Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:17:11.277011 lava-dispatcher, installed at version: 2024.05
2 13:17:11.277218 start: 0 validate
3 13:17:11.277386 Start time: 2024-07-18 13:17:11.277380+00:00 (UTC)
4 13:17:11.277517 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:17:11.277662 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:17:11.540969 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:17:11.541740 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:17:11.802831 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:17:11.803014 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:17:12.067481 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:17:12.067616 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:17:12.581948 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:17:12.582093 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:17:12.842542 validate duration: 1.57
16 13:17:12.842787 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:17:12.842882 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:17:12.842960 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:17:12.843107 Not decompressing ramdisk as can be used compressed.
20 13:17:12.843192 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 13:17:12.843249 saving as /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/ramdisk/initrd.cpio.gz
22 13:17:12.843308 total size: 5628151 (5 MB)
23 13:17:12.844420 progress 0 % (0 MB)
24 13:17:12.846106 progress 5 % (0 MB)
25 13:17:12.847600 progress 10 % (0 MB)
26 13:17:12.848924 progress 15 % (0 MB)
27 13:17:12.850440 progress 20 % (1 MB)
28 13:17:12.851790 progress 25 % (1 MB)
29 13:17:12.853328 progress 30 % (1 MB)
30 13:17:12.854843 progress 35 % (1 MB)
31 13:17:12.856497 progress 40 % (2 MB)
32 13:17:12.858023 progress 45 % (2 MB)
33 13:17:12.859331 progress 50 % (2 MB)
34 13:17:12.860804 progress 55 % (2 MB)
35 13:17:12.862319 progress 60 % (3 MB)
36 13:17:12.863613 progress 65 % (3 MB)
37 13:17:12.865196 progress 70 % (3 MB)
38 13:17:12.866716 progress 75 % (4 MB)
39 13:17:12.868309 progress 80 % (4 MB)
40 13:17:12.869691 progress 85 % (4 MB)
41 13:17:12.871265 progress 90 % (4 MB)
42 13:17:12.872721 progress 95 % (5 MB)
43 13:17:12.874129 progress 100 % (5 MB)
44 13:17:12.874329 5 MB downloaded in 0.03 s (173.06 MB/s)
45 13:17:12.874479 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:17:12.874694 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:17:12.874772 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:17:12.874846 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:17:12.874964 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:17:12.875024 saving as /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/kernel/Image
52 13:17:12.875076 total size: 54813184 (52 MB)
53 13:17:12.875128 No compression specified
54 13:17:12.876108 progress 0 % (0 MB)
55 13:17:12.889780 progress 5 % (2 MB)
56 13:17:12.903510 progress 10 % (5 MB)
57 13:17:12.917437 progress 15 % (7 MB)
58 13:17:12.931462 progress 20 % (10 MB)
59 13:17:12.944857 progress 25 % (13 MB)
60 13:17:12.958040 progress 30 % (15 MB)
61 13:17:12.971351 progress 35 % (18 MB)
62 13:17:12.984548 progress 40 % (20 MB)
63 13:17:12.997576 progress 45 % (23 MB)
64 13:17:13.010878 progress 50 % (26 MB)
65 13:17:13.024142 progress 55 % (28 MB)
66 13:17:13.037703 progress 60 % (31 MB)
67 13:17:13.051238 progress 65 % (34 MB)
68 13:17:13.064304 progress 70 % (36 MB)
69 13:17:13.077628 progress 75 % (39 MB)
70 13:17:13.090887 progress 80 % (41 MB)
71 13:17:13.103953 progress 85 % (44 MB)
72 13:17:13.117326 progress 90 % (47 MB)
73 13:17:13.130790 progress 95 % (49 MB)
74 13:17:13.143806 progress 100 % (52 MB)
75 13:17:13.144027 52 MB downloaded in 0.27 s (194.36 MB/s)
76 13:17:13.144171 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:17:13.144376 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:17:13.144455 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:17:13.144529 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:17:13.144642 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:17:13.144702 saving as /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/dtb/mt8192-asurada-spherion-r0.dtb
83 13:17:13.144753 total size: 47258 (0 MB)
84 13:17:13.144805 No compression specified
85 13:17:13.145916 progress 69 % (0 MB)
86 13:17:13.146166 progress 100 % (0 MB)
87 13:17:13.146359 0 MB downloaded in 0.00 s (28.10 MB/s)
88 13:17:13.146470 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:17:13.146666 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:17:13.146740 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:17:13.146814 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:17:13.146917 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 13:17:13.146975 saving as /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/nfsrootfs/full.rootfs.tar
95 13:17:13.147026 total size: 69067788 (65 MB)
96 13:17:13.147079 Using unxz to decompress xz
97 13:17:13.148306 progress 0 % (0 MB)
98 13:17:13.333328 progress 5 % (3 MB)
99 13:17:13.523813 progress 10 % (6 MB)
100 13:17:13.714433 progress 15 % (9 MB)
101 13:17:13.875321 progress 20 % (13 MB)
102 13:17:14.056541 progress 25 % (16 MB)
103 13:17:14.243903 progress 30 % (19 MB)
104 13:17:14.362200 progress 35 % (23 MB)
105 13:17:14.459042 progress 40 % (26 MB)
106 13:17:14.650994 progress 45 % (29 MB)
107 13:17:14.843038 progress 50 % (32 MB)
108 13:17:15.033028 progress 55 % (36 MB)
109 13:17:15.236632 progress 60 % (39 MB)
110 13:17:15.418811 progress 65 % (42 MB)
111 13:17:15.607069 progress 70 % (46 MB)
112 13:17:15.790578 progress 75 % (49 MB)
113 13:17:15.985068 progress 80 % (52 MB)
114 13:17:16.150066 progress 85 % (56 MB)
115 13:17:16.337155 progress 90 % (59 MB)
116 13:17:16.537381 progress 95 % (62 MB)
117 13:17:16.735696 progress 100 % (65 MB)
118 13:17:16.741773 65 MB downloaded in 3.59 s (18.32 MB/s)
119 13:17:16.741961 end: 1.4.1 http-download (duration 00:00:04) [common]
121 13:17:16.742198 end: 1.4 download-retry (duration 00:00:04) [common]
122 13:17:16.742288 start: 1.5 download-retry (timeout 00:09:56) [common]
123 13:17:16.742375 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 13:17:16.742521 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:17:16.742653 saving as /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/modules/modules.tar
126 13:17:16.742740 total size: 8611320 (8 MB)
127 13:17:16.742829 Using unxz to decompress xz
128 13:17:16.744510 progress 0 % (0 MB)
129 13:17:16.765084 progress 5 % (0 MB)
130 13:17:16.790160 progress 10 % (0 MB)
131 13:17:16.814288 progress 15 % (1 MB)
132 13:17:16.838420 progress 20 % (1 MB)
133 13:17:16.862013 progress 25 % (2 MB)
134 13:17:16.885514 progress 30 % (2 MB)
135 13:17:16.908353 progress 35 % (2 MB)
136 13:17:16.934661 progress 40 % (3 MB)
137 13:17:16.958828 progress 45 % (3 MB)
138 13:17:16.982889 progress 50 % (4 MB)
139 13:17:17.007447 progress 55 % (4 MB)
140 13:17:17.031667 progress 60 % (4 MB)
141 13:17:17.054840 progress 65 % (5 MB)
142 13:17:17.079682 progress 70 % (5 MB)
143 13:17:17.106494 progress 75 % (6 MB)
144 13:17:17.134163 progress 80 % (6 MB)
145 13:17:17.157892 progress 85 % (7 MB)
146 13:17:17.180804 progress 90 % (7 MB)
147 13:17:17.204235 progress 95 % (7 MB)
148 13:17:17.227150 progress 100 % (8 MB)
149 13:17:17.232822 8 MB downloaded in 0.49 s (16.76 MB/s)
150 13:17:17.233003 end: 1.5.1 http-download (duration 00:00:00) [common]
152 13:17:17.233214 end: 1.5 download-retry (duration 00:00:00) [common]
153 13:17:17.233363 start: 1.6 prepare-tftp-overlay (timeout 00:09:56) [common]
154 13:17:17.233493 start: 1.6.1 extract-nfsrootfs (timeout 00:09:56) [common]
155 13:17:18.792702 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14879033/extract-nfsrootfs-yhmhiiif
156 13:17:18.792888 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:17:18.792979 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 13:17:18.793144 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl
159 13:17:18.793306 makedir: /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin
160 13:17:18.793400 makedir: /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/tests
161 13:17:18.793487 makedir: /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/results
162 13:17:18.793570 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-add-keys
163 13:17:18.793696 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-add-sources
164 13:17:18.793811 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-background-process-start
165 13:17:18.793924 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-background-process-stop
166 13:17:18.794043 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-common-functions
167 13:17:18.794155 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-echo-ipv4
168 13:17:18.794266 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-install-packages
169 13:17:18.794375 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-installed-packages
170 13:17:18.794484 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-os-build
171 13:17:18.794594 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-probe-channel
172 13:17:18.794705 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-probe-ip
173 13:17:18.794816 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-target-ip
174 13:17:18.794926 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-target-mac
175 13:17:18.795037 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-target-storage
176 13:17:18.795151 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-test-case
177 13:17:18.795261 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-test-event
178 13:17:18.795370 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-test-feedback
179 13:17:18.795478 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-test-raise
180 13:17:18.795692 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-test-reference
181 13:17:18.795885 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-test-runner
182 13:17:18.795997 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-test-set
183 13:17:18.796108 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-test-shell
184 13:17:18.796220 Updating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-install-packages (oe)
185 13:17:18.796355 Updating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/bin/lava-installed-packages (oe)
186 13:17:18.796466 Creating /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/environment
187 13:17:18.796550 LAVA metadata
188 13:17:18.796614 - LAVA_JOB_ID=14879033
189 13:17:18.796670 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:17:18.796763 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 13:17:18.796820 skipped lava-vland-overlay
192 13:17:18.796912 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:17:18.797019 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 13:17:18.797117 skipped lava-multinode-overlay
195 13:17:18.797219 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:17:18.797366 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 13:17:18.797440 Loading test definitions
198 13:17:18.797518 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 13:17:18.797577 Using /lava-14879033 at stage 0
200 13:17:18.797868 uuid=14879033_1.6.2.3.1 testdef=None
201 13:17:18.797948 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:17:18.798023 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 13:17:18.798442 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:17:18.798641 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 13:17:18.799175 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:17:18.799379 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 13:17:18.800442 runner path: /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/0/tests/0_lc-compliance test_uuid 14879033_1.6.2.3.1
210 13:17:18.800618 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:17:18.800796 Creating lava-test-runner.conf files
213 13:17:18.800852 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879033/lava-overlay-6izh2odl/lava-14879033/0 for stage 0
214 13:17:18.800931 - 0_lc-compliance
215 13:17:18.801019 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 13:17:18.801095 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 13:17:18.806758 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 13:17:18.806866 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 13:17:18.806946 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 13:17:18.807028 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 13:17:18.807104 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 13:17:18.949558 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 13:17:18.949703 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 13:17:18.949783 extracting modules file /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879033/extract-nfsrootfs-yhmhiiif
225 13:17:19.174583 extracting modules file /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879033/extract-overlay-ramdisk-n5mjy140/ramdisk
226 13:17:19.401555 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 13:17:19.401703 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 13:17:19.401788 [common] Applying overlay to NFS
229 13:17:19.401846 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879033/compress-overlay-cypkkggt/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879033/extract-nfsrootfs-yhmhiiif
230 13:17:19.408059 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 13:17:19.408167 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 13:17:19.408247 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 13:17:19.408323 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 13:17:19.408388 Building ramdisk /var/lib/lava/dispatcher/tmp/14879033/extract-overlay-ramdisk-n5mjy140/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879033/extract-overlay-ramdisk-n5mjy140/ramdisk
235 13:17:19.689314 >> 129966 blocks
236 13:17:21.768217 rename /var/lib/lava/dispatcher/tmp/14879033/extract-overlay-ramdisk-n5mjy140/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/ramdisk/ramdisk.cpio.gz
237 13:17:21.768380 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 13:17:21.768512 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 13:17:21.768591 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 13:17:21.768667 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/kernel/Image']
241 13:17:35.880109 Returned 0 in 14 seconds
242 13:17:35.880331 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/kernel/image.itb
243 13:17:36.234977 output: FIT description: Kernel Image image with one or more FDT blobs
244 13:17:36.235103 output: Created: Thu Jul 18 14:17:36 2024
245 13:17:36.235162 output: Image 0 (kernel-1)
246 13:17:36.235216 output: Description:
247 13:17:36.235266 output: Created: Thu Jul 18 14:17:36 2024
248 13:17:36.235316 output: Type: Kernel Image
249 13:17:36.235378 output: Compression: lzma compressed
250 13:17:36.235435 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
251 13:17:36.235484 output: Architecture: AArch64
252 13:17:36.235531 output: OS: Linux
253 13:17:36.235579 output: Load Address: 0x00000000
254 13:17:36.235627 output: Entry Point: 0x00000000
255 13:17:36.235675 output: Hash algo: crc32
256 13:17:36.235725 output: Hash value: a47b020b
257 13:17:36.235773 output: Image 1 (fdt-1)
258 13:17:36.235820 output: Description: mt8192-asurada-spherion-r0
259 13:17:36.235867 output: Created: Thu Jul 18 14:17:36 2024
260 13:17:36.235914 output: Type: Flat Device Tree
261 13:17:36.235962 output: Compression: uncompressed
262 13:17:36.236009 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 13:17:36.236076 output: Architecture: AArch64
264 13:17:36.236139 output: Hash algo: crc32
265 13:17:36.236201 output: Hash value: 0f8e4d2e
266 13:17:36.236279 output: Image 2 (ramdisk-1)
267 13:17:36.236368 output: Description: unavailable
268 13:17:36.236415 output: Created: Thu Jul 18 14:17:36 2024
269 13:17:36.236477 output: Type: RAMDisk Image
270 13:17:36.236556 output: Compression: uncompressed
271 13:17:36.236634 output: Data Size: 18719904 Bytes = 18281.16 KiB = 17.85 MiB
272 13:17:36.236711 output: Architecture: AArch64
273 13:17:36.236828 output: OS: Linux
274 13:17:36.236904 output: Load Address: unavailable
275 13:17:36.236981 output: Entry Point: unavailable
276 13:17:36.237057 output: Hash algo: crc32
277 13:17:36.237134 output: Hash value: fae5d39e
278 13:17:36.237210 output: Default Configuration: 'conf-1'
279 13:17:36.237330 output: Configuration 0 (conf-1)
280 13:17:36.237406 output: Description: mt8192-asurada-spherion-r0
281 13:17:36.237484 output: Kernel: kernel-1
282 13:17:36.237560 output: Init Ramdisk: ramdisk-1
283 13:17:36.237636 output: FDT: fdt-1
284 13:17:36.237714 output: Loadables: kernel-1
285 13:17:36.237788 output:
286 13:17:36.237917 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 13:17:36.238021 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 13:17:36.238123 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 13:17:36.238227 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 13:17:36.238310 No LXC device requested
291 13:17:36.238408 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 13:17:36.238510 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 13:17:36.238605 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 13:17:36.238689 Checking files for TFTP limit of 4294967296 bytes.
295 13:17:36.239239 end: 1 tftp-deploy (duration 00:00:23) [common]
296 13:17:36.239351 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 13:17:36.239455 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 13:17:36.239581 substitutions:
299 13:17:36.239662 - {DTB}: 14879033/tftp-deploy-q9ao1fcs/dtb/mt8192-asurada-spherion-r0.dtb
300 13:17:36.239742 - {INITRD}: 14879033/tftp-deploy-q9ao1fcs/ramdisk/ramdisk.cpio.gz
301 13:17:36.239820 - {KERNEL}: 14879033/tftp-deploy-q9ao1fcs/kernel/Image
302 13:17:36.239896 - {LAVA_MAC}: None
303 13:17:36.239972 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14879033/extract-nfsrootfs-yhmhiiif
304 13:17:36.240048 - {NFS_SERVER_IP}: 192.168.201.1
305 13:17:36.240123 - {PRESEED_CONFIG}: None
306 13:17:36.240210 - {PRESEED_LOCAL}: None
307 13:17:36.240286 - {RAMDISK}: 14879033/tftp-deploy-q9ao1fcs/ramdisk/ramdisk.cpio.gz
308 13:17:36.240362 - {ROOT_PART}: None
309 13:17:36.240436 - {ROOT}: None
310 13:17:36.240511 - {SERVER_IP}: 192.168.201.1
311 13:17:36.240585 - {TEE}: None
312 13:17:36.240660 Parsed boot commands:
313 13:17:36.240756 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 13:17:36.240945 Parsed boot commands: tftpboot 192.168.201.1 14879033/tftp-deploy-q9ao1fcs/kernel/image.itb 14879033/tftp-deploy-q9ao1fcs/kernel/cmdline
315 13:17:36.241047 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 13:17:36.241146 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 13:17:36.241248 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 13:17:36.241379 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 13:17:36.241447 Not connected, no need to disconnect.
320 13:17:36.241513 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 13:17:36.241597 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 13:17:36.241678 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
323 13:17:36.244618 Setting prompt string to ['lava-test: # ']
324 13:17:36.244982 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 13:17:36.245103 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 13:17:36.245222 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 13:17:36.245374 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 13:17:36.245582 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
329 13:17:45.376035 >> Command sent successfully.
330 13:17:45.390215 Returned 0 in 9 seconds
331 13:17:45.390840 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 13:17:45.391980 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 13:17:45.392474 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 13:17:45.392874 Setting prompt string to 'Starting depthcharge on Spherion...'
336 13:17:45.393206 Changing prompt to 'Starting depthcharge on Spherion...'
337 13:17:45.393661 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 13:17:45.395371 [Enter `^Ec?' for help]
339 13:17:46.647702
340 13:17:46.648173
341 13:17:46.648715 F0: 102B 0000
342 13:17:46.649330
343 13:17:46.649826 F3: 1001 0000 [0200]
344 13:17:46.650347
345 13:17:46.651187 F3: 1001 0000
346 13:17:46.651717
347 13:17:46.652215 F7: 102D 0000
348 13:17:46.652771
349 13:17:46.653320 F1: 0000 0000
350 13:17:46.655246
351 13:17:46.655657 V0: 0000 0000 [0001]
352 13:17:46.655973
353 13:17:46.656267 00: 0007 8000
354 13:17:46.656593
355 13:17:46.658430 01: 0000 0000
356 13:17:46.658948
357 13:17:46.659294 BP: 0C00 0209 [0000]
358 13:17:46.659619
359 13:17:46.661912 G0: 1182 0000
360 13:17:46.662324
361 13:17:46.662642 EC: 0000 0021 [4000]
362 13:17:46.662971
363 13:17:46.665735 S7: 0000 0000 [0000]
364 13:17:46.666106
365 13:17:46.666433 CC: 0000 0000 [0001]
366 13:17:46.666712
367 13:17:46.668923 T0: 0000 0040 [010F]
368 13:17:46.669328
369 13:17:46.669646 Jump to BL
370 13:17:46.669940
371 13:17:46.694420
372 13:17:46.694937
373 13:17:46.701542 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 13:17:46.705211 ARM64: Exception handlers installed.
375 13:17:46.708648 ARM64: Testing exception
376 13:17:46.713119 ARM64: Done test exception
377 13:17:46.720197 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 13:17:46.727093 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 13:17:46.734090 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 13:17:46.745754 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 13:17:46.752760 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 13:17:46.759283 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 13:17:46.770955 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 13:17:46.777556 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 13:17:46.797494 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 13:17:46.802011 WDT: Last reset was cold boot
387 13:17:46.805125 SPI1(PAD0) initialized at 2873684 Hz
388 13:17:46.808053 SPI5(PAD0) initialized at 992727 Hz
389 13:17:46.808127 VBOOT: Loading verstage.
390 13:17:46.815609 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 13:17:46.819651 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 13:17:46.822738 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 13:17:46.826575 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 13:17:46.834710 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 13:17:46.842005 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 13:17:46.852288 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 13:17:46.852368
398 13:17:46.852423
399 13:17:46.863076 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 13:17:46.866263 ARM64: Exception handlers installed.
401 13:17:46.866340 ARM64: Testing exception
402 13:17:46.870164 ARM64: Done test exception
403 13:17:46.874228 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 13:17:46.880717 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 13:17:46.893189 Probing TPM: . done!
406 13:17:46.893307 TPM ready after 0 ms
407 13:17:46.900526 Connected to device vid:did:rid of 1ae0:0028:00
408 13:17:46.907494 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
409 13:17:46.966540 Initialized TPM device CR50 revision 0
410 13:17:46.980022 tlcl_send_startup: Startup return code is 0
411 13:17:46.980121 TPM: setup succeeded
412 13:17:46.992948 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 13:17:47.002594 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 13:17:47.013737 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 13:17:47.024408 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 13:17:47.027434 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 13:17:47.031363 in-header: 03 07 00 00 08 00 00 00
418 13:17:47.036082 in-data: aa e4 47 04 13 02 00 00
419 13:17:47.038924 Chrome EC: UHEPI supported
420 13:17:47.046816 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 13:17:47.049351 in-header: 03 a9 00 00 08 00 00 00
422 13:17:47.053072 in-data: 84 60 60 08 00 00 00 00
423 13:17:47.053147 Phase 1
424 13:17:47.056308 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 13:17:47.062637 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 13:17:47.067274 VB2:vb2_check_recovery() Recovery was requested manually
427 13:17:47.074830 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 13:17:47.076082 Recovery requested (1009000e)
429 13:17:47.080454 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 13:17:47.089143 tlcl_extend: response is 0
431 13:17:47.097269 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 13:17:47.102055 tlcl_extend: response is 0
433 13:17:47.108732 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 13:17:47.129746 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 13:17:47.136131 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 13:17:47.136217
437 13:17:47.136274
438 13:17:47.146084 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 13:17:47.149236 ARM64: Exception handlers installed.
440 13:17:47.153457 ARM64: Testing exception
441 13:17:47.153558 ARM64: Done test exception
442 13:17:47.175183 pmic_efuse_setting: Set efuses in 11 msecs
443 13:17:47.178494 pmwrap_interface_init: Select PMIF_VLD_RDY
444 13:17:47.185300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 13:17:47.188304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 13:17:47.195164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 13:17:47.198083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 13:17:47.204762 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 13:17:47.208150 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 13:17:47.211724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 13:17:47.218343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 13:17:47.221862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 13:17:47.228177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 13:17:47.231469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 13:17:47.235111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 13:17:47.241896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 13:17:47.248595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 13:17:47.251341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 13:17:47.258461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 13:17:47.265080 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 13:17:47.271811 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 13:17:47.276042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 13:17:47.282485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 13:17:47.288712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 13:17:47.292374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 13:17:47.298923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 13:17:47.305266 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 13:17:47.308663 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 13:17:47.315714 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 13:17:47.318630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 13:17:47.325076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 13:17:47.328600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 13:17:47.335025 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 13:17:47.338460 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 13:17:47.344762 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 13:17:47.349664 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 13:17:47.356383 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 13:17:47.359805 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 13:17:47.366138 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 13:17:47.369149 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 13:17:47.376458 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 13:17:47.379486 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 13:17:47.382817 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 13:17:47.389290 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 13:17:47.393369 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 13:17:47.396259 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 13:17:47.398985 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 13:17:47.406202 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 13:17:47.408967 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 13:17:47.412756 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 13:17:47.419473 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 13:17:47.423244 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 13:17:47.425932 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 13:17:47.428669 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 13:17:47.438875 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 13:17:47.446053 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 13:17:47.452512 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 13:17:47.459616 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 13:17:47.469690 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 13:17:47.473055 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 13:17:47.475968 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 13:17:47.483186 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 13:17:47.489798 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1d
504 13:17:47.493117 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 13:17:47.501102 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 13:17:47.503548 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 13:17:47.512645 [RTC]rtc_get_frequency_meter,154: input=15, output=764
508 13:17:47.522601 [RTC]rtc_get_frequency_meter,154: input=23, output=949
509 13:17:47.531693 [RTC]rtc_get_frequency_meter,154: input=19, output=856
510 13:17:47.541448 [RTC]rtc_get_frequency_meter,154: input=17, output=811
511 13:17:47.550837 [RTC]rtc_get_frequency_meter,154: input=16, output=787
512 13:17:47.560133 [RTC]rtc_get_frequency_meter,154: input=16, output=787
513 13:17:47.569590 [RTC]rtc_get_frequency_meter,154: input=17, output=810
514 13:17:47.573435 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 13:17:47.579954 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 13:17:47.583566 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 13:17:47.586749 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 13:17:47.593369 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 13:17:47.597354 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 13:17:47.600500 ADC[4]: Raw value=669695 ID=5
521 13:17:47.600969 ADC[3]: Raw value=212549 ID=1
522 13:17:47.603457 RAM Code: 0x51
523 13:17:47.607175 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 13:17:47.614431 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 13:17:47.621421 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
526 13:17:47.626666 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
527 13:17:47.630129 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 13:17:47.633337 in-header: 03 07 00 00 08 00 00 00
529 13:17:47.636765 in-data: aa e4 47 04 13 02 00 00
530 13:17:47.640210 Chrome EC: UHEPI supported
531 13:17:47.647195 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 13:17:47.649727 in-header: 03 a9 00 00 08 00 00 00
533 13:17:47.653690 in-data: 84 60 60 08 00 00 00 00
534 13:17:47.657321 MRC: failed to locate region type 0.
535 13:17:47.663461 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 13:17:47.663890 DRAM-K: Running full calibration
537 13:17:47.669790 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
538 13:17:47.673451 header.status = 0x0
539 13:17:47.677199 header.version = 0x6 (expected: 0x6)
540 13:17:47.680356 header.size = 0xd00 (expected: 0xd00)
541 13:17:47.680742 header.flags = 0x0
542 13:17:47.686687 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 13:17:47.705048 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 13:17:47.711995 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 13:17:47.715862 dram_init: ddr_geometry: 0
546 13:17:47.717939 [EMI] MDL number = 0
547 13:17:47.718495 [EMI] Get MDL freq = 0
548 13:17:47.721322 dram_init: ddr_type: 0
549 13:17:47.721750 is_discrete_lpddr4: 1
550 13:17:47.724577 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 13:17:47.725108
552 13:17:47.725499
553 13:17:47.728127 [Bian_co] ETT version 0.0.0.1
554 13:17:47.734446 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
555 13:17:47.734882
556 13:17:47.738498 dramc_set_vcore_voltage set vcore to 650000
557 13:17:47.738924 Read voltage for 800, 4
558 13:17:47.741521 Vio18 = 0
559 13:17:47.742025 Vcore = 650000
560 13:17:47.742361 Vdram = 0
561 13:17:47.744706 Vddq = 0
562 13:17:47.745127 Vmddr = 0
563 13:17:47.748883 dram_init: config_dvfs: 1
564 13:17:47.751900 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 13:17:47.758136 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 13:17:47.761587 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 13:17:47.764676 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 13:17:47.768161 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 13:17:47.771271 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 13:17:47.774794 MEM_TYPE=3, freq_sel=18
571 13:17:47.778136 sv_algorithm_assistance_LP4_1600
572 13:17:47.782490 ============ PULL DRAM RESETB DOWN ============
573 13:17:47.785175 ========== PULL DRAM RESETB DOWN end =========
574 13:17:47.791487 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 13:17:47.795503 ===================================
576 13:17:47.797892 LPDDR4 DRAM CONFIGURATION
577 13:17:47.801536 ===================================
578 13:17:47.801967 EX_ROW_EN[0] = 0x0
579 13:17:47.804846 EX_ROW_EN[1] = 0x0
580 13:17:47.805306 LP4Y_EN = 0x0
581 13:17:47.807819 WORK_FSP = 0x0
582 13:17:47.808242 WL = 0x2
583 13:17:47.811557 RL = 0x2
584 13:17:47.811979 BL = 0x2
585 13:17:47.814802 RPST = 0x0
586 13:17:47.815229 RD_PRE = 0x0
587 13:17:47.818209 WR_PRE = 0x1
588 13:17:47.818634 WR_PST = 0x0
589 13:17:47.820955 DBI_WR = 0x0
590 13:17:47.821437 DBI_RD = 0x0
591 13:17:47.825737 OTF = 0x1
592 13:17:47.827818 ===================================
593 13:17:47.831005 ===================================
594 13:17:47.831431 ANA top config
595 13:17:47.835684 ===================================
596 13:17:47.838351 DLL_ASYNC_EN = 0
597 13:17:47.841797 ALL_SLAVE_EN = 1
598 13:17:47.845660 NEW_RANK_MODE = 1
599 13:17:47.846089 DLL_IDLE_MODE = 1
600 13:17:47.847770 LP45_APHY_COMB_EN = 1
601 13:17:47.851182 TX_ODT_DIS = 1
602 13:17:47.854643 NEW_8X_MODE = 1
603 13:17:47.857904 ===================================
604 13:17:47.861406 ===================================
605 13:17:47.864818 data_rate = 1600
606 13:17:47.865291 CKR = 1
607 13:17:47.867924 DQ_P2S_RATIO = 8
608 13:17:47.871284 ===================================
609 13:17:47.875081 CA_P2S_RATIO = 8
610 13:17:47.878284 DQ_CA_OPEN = 0
611 13:17:47.881185 DQ_SEMI_OPEN = 0
612 13:17:47.884632 CA_SEMI_OPEN = 0
613 13:17:47.885148 CA_FULL_RATE = 0
614 13:17:47.888507 DQ_CKDIV4_EN = 1
615 13:17:47.891743 CA_CKDIV4_EN = 1
616 13:17:47.894757 CA_PREDIV_EN = 0
617 13:17:47.897744 PH8_DLY = 0
618 13:17:47.898181 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 13:17:47.901338 DQ_AAMCK_DIV = 4
620 13:17:47.905173 CA_AAMCK_DIV = 4
621 13:17:47.908475 CA_ADMCK_DIV = 4
622 13:17:47.911250 DQ_TRACK_CA_EN = 0
623 13:17:47.914992 CA_PICK = 800
624 13:17:47.918012 CA_MCKIO = 800
625 13:17:47.918469 MCKIO_SEMI = 0
626 13:17:47.921680 PLL_FREQ = 3068
627 13:17:47.924778 DQ_UI_PI_RATIO = 32
628 13:17:47.928396 CA_UI_PI_RATIO = 0
629 13:17:47.931346 ===================================
630 13:17:47.934982 ===================================
631 13:17:47.937627 memory_type:LPDDR4
632 13:17:47.938050 GP_NUM : 10
633 13:17:47.941194 SRAM_EN : 1
634 13:17:47.941658 MD32_EN : 0
635 13:17:47.944700 ===================================
636 13:17:47.947833 [ANA_INIT] >>>>>>>>>>>>>>
637 13:17:47.951628 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 13:17:47.955056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 13:17:47.958162 ===================================
640 13:17:47.961675 data_rate = 1600,PCW = 0X7600
641 13:17:47.964714 ===================================
642 13:17:47.968313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 13:17:47.974143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 13:17:47.978162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 13:17:47.984747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 13:17:47.987903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 13:17:47.991652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 13:17:47.992051 [ANA_INIT] flow start
649 13:17:47.995025 [ANA_INIT] PLL >>>>>>>>
650 13:17:47.997868 [ANA_INIT] PLL <<<<<<<<
651 13:17:47.998249 [ANA_INIT] MIDPI >>>>>>>>
652 13:17:48.001213 [ANA_INIT] MIDPI <<<<<<<<
653 13:17:48.004666 [ANA_INIT] DLL >>>>>>>>
654 13:17:48.005058 [ANA_INIT] flow end
655 13:17:48.011555 ============ LP4 DIFF to SE enter ============
656 13:17:48.015033 ============ LP4 DIFF to SE exit ============
657 13:17:48.018114 [ANA_INIT] <<<<<<<<<<<<<
658 13:17:48.018514 [Flow] Enable top DCM control >>>>>
659 13:17:48.021894 [Flow] Enable top DCM control <<<<<
660 13:17:48.024265 Enable DLL master slave shuffle
661 13:17:48.031473 ==============================================================
662 13:17:48.034413 Gating Mode config
663 13:17:48.038046 ==============================================================
664 13:17:48.041136 Config description:
665 13:17:48.051638 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 13:17:48.058085 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 13:17:48.062271 SELPH_MODE 0: By rank 1: By Phase
668 13:17:48.067727 ==============================================================
669 13:17:48.071881 GAT_TRACK_EN = 1
670 13:17:48.074776 RX_GATING_MODE = 2
671 13:17:48.075158 RX_GATING_TRACK_MODE = 2
672 13:17:48.078071 SELPH_MODE = 1
673 13:17:48.080924 PICG_EARLY_EN = 1
674 13:17:48.084337 VALID_LAT_VALUE = 1
675 13:17:48.091450 ==============================================================
676 13:17:48.094424 Enter into Gating configuration >>>>
677 13:17:48.098304 Exit from Gating configuration <<<<
678 13:17:48.101641 Enter into DVFS_PRE_config >>>>>
679 13:17:48.111802 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 13:17:48.114908 Exit from DVFS_PRE_config <<<<<
681 13:17:48.118187 Enter into PICG configuration >>>>
682 13:17:48.121620 Exit from PICG configuration <<<<
683 13:17:48.125923 [RX_INPUT] configuration >>>>>
684 13:17:48.126349 [RX_INPUT] configuration <<<<<
685 13:17:48.131583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 13:17:48.138110 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 13:17:48.141488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 13:17:48.148363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 13:17:48.156964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 13:17:48.163650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 13:17:48.166811 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 13:17:48.170244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 13:17:48.174861 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 13:17:48.178853 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 13:17:48.180962 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 13:17:48.188293 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 13:17:48.191355 ===================================
698 13:17:48.191798 LPDDR4 DRAM CONFIGURATION
699 13:17:48.195136 ===================================
700 13:17:48.198340 EX_ROW_EN[0] = 0x0
701 13:17:48.198836 EX_ROW_EN[1] = 0x0
702 13:17:48.201470 LP4Y_EN = 0x0
703 13:17:48.201987 WORK_FSP = 0x0
704 13:17:48.204622 WL = 0x2
705 13:17:48.208111 RL = 0x2
706 13:17:48.208570 BL = 0x2
707 13:17:48.211315 RPST = 0x0
708 13:17:48.211873 RD_PRE = 0x0
709 13:17:48.214554 WR_PRE = 0x1
710 13:17:48.214942 WR_PST = 0x0
711 13:17:48.218856 DBI_WR = 0x0
712 13:17:48.219287 DBI_RD = 0x0
713 13:17:48.221647 OTF = 0x1
714 13:17:48.224950 ===================================
715 13:17:48.228592 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 13:17:48.231675 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 13:17:48.235164 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 13:17:48.237988 ===================================
719 13:17:48.241020 LPDDR4 DRAM CONFIGURATION
720 13:17:48.244605 ===================================
721 13:17:48.248466 EX_ROW_EN[0] = 0x10
722 13:17:48.248848 EX_ROW_EN[1] = 0x0
723 13:17:48.251349 LP4Y_EN = 0x0
724 13:17:48.251733 WORK_FSP = 0x0
725 13:17:48.254580 WL = 0x2
726 13:17:48.255042 RL = 0x2
727 13:17:48.257545 BL = 0x2
728 13:17:48.257999 RPST = 0x0
729 13:17:48.261176 RD_PRE = 0x0
730 13:17:48.261596 WR_PRE = 0x1
731 13:17:48.264842 WR_PST = 0x0
732 13:17:48.265296 DBI_WR = 0x0
733 13:17:48.267965 DBI_RD = 0x0
734 13:17:48.271664 OTF = 0x1
735 13:17:48.274832 ===================================
736 13:17:48.277765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 13:17:48.283287 nWR fixed to 40
738 13:17:48.287197 [ModeRegInit_LP4] CH0 RK0
739 13:17:48.287652 [ModeRegInit_LP4] CH0 RK1
740 13:17:48.290285 [ModeRegInit_LP4] CH1 RK0
741 13:17:48.292965 [ModeRegInit_LP4] CH1 RK1
742 13:17:48.293495 match AC timing 12
743 13:17:48.299743 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
744 13:17:48.303119 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 13:17:48.306351 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 13:17:48.312932 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 13:17:48.316977 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 13:17:48.317479 [EMI DOE] emi_dcm 0
749 13:17:48.322852 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 13:17:48.323255 ==
751 13:17:48.326077 Dram Type= 6, Freq= 0, CH_0, rank 0
752 13:17:48.329675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
753 13:17:48.330059 ==
754 13:17:48.336379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 13:17:48.342870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 13:17:48.350170 [CA 0] Center 37 (7~68) winsize 62
757 13:17:48.353441 [CA 1] Center 37 (7~68) winsize 62
758 13:17:48.356677 [CA 2] Center 35 (5~66) winsize 62
759 13:17:48.360372 [CA 3] Center 35 (5~66) winsize 62
760 13:17:48.363959 [CA 4] Center 34 (3~65) winsize 63
761 13:17:48.367219 [CA 5] Center 34 (4~65) winsize 62
762 13:17:48.367618
763 13:17:48.370374 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 13:17:48.370757
765 13:17:48.373809 [CATrainingPosCal] consider 1 rank data
766 13:17:48.377047 u2DelayCellTimex100 = 270/100 ps
767 13:17:48.380250 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
768 13:17:48.383301 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
769 13:17:48.390274 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
770 13:17:48.393584 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
771 13:17:48.397212 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
772 13:17:48.400337 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
773 13:17:48.400831
774 13:17:48.404206 CA PerBit enable=1, Macro0, CA PI delay=34
775 13:17:48.404676
776 13:17:48.406996 [CBTSetCACLKResult] CA Dly = 34
777 13:17:48.407422 CS Dly: 6 (0~37)
778 13:17:48.407751 ==
779 13:17:48.410494 Dram Type= 6, Freq= 0, CH_0, rank 1
780 13:17:48.418282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 13:17:48.418757 ==
782 13:17:48.421332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 13:17:48.427351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 13:17:48.436063 [CA 0] Center 37 (7~68) winsize 62
785 13:17:48.439989 [CA 1] Center 37 (6~68) winsize 63
786 13:17:48.442563 [CA 2] Center 35 (4~66) winsize 63
787 13:17:48.446083 [CA 3] Center 34 (4~65) winsize 62
788 13:17:48.449800 [CA 4] Center 33 (3~64) winsize 62
789 13:17:48.452749 [CA 5] Center 33 (3~64) winsize 62
790 13:17:48.453170
791 13:17:48.457315 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 13:17:48.457751
793 13:17:48.459565 [CATrainingPosCal] consider 2 rank data
794 13:17:48.462882 u2DelayCellTimex100 = 270/100 ps
795 13:17:48.465950 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 13:17:48.470246 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 13:17:48.476239 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
798 13:17:48.479726 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
799 13:17:48.483239 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 13:17:48.486385 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
801 13:17:48.486770
802 13:17:48.489599 CA PerBit enable=1, Macro0, CA PI delay=33
803 13:17:48.490026
804 13:17:48.492675 [CBTSetCACLKResult] CA Dly = 33
805 13:17:48.493158 CS Dly: 6 (0~38)
806 13:17:48.493538
807 13:17:48.496527 ----->DramcWriteLeveling(PI) begin...
808 13:17:48.499899 ==
809 13:17:48.502513 Dram Type= 6, Freq= 0, CH_0, rank 0
810 13:17:48.506099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 13:17:48.506489 ==
812 13:17:48.509356 Write leveling (Byte 0): 29 => 29
813 13:17:48.513077 Write leveling (Byte 1): 28 => 28
814 13:17:48.516335 DramcWriteLeveling(PI) end<-----
815 13:17:48.516759
816 13:17:48.517086 ==
817 13:17:48.519962 Dram Type= 6, Freq= 0, CH_0, rank 0
818 13:17:48.522774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
819 13:17:48.523167 ==
820 13:17:48.526009 [Gating] SW mode calibration
821 13:17:48.532996 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 13:17:48.536381 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 13:17:48.543698 0 6 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
824 13:17:48.546906 0 6 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
825 13:17:48.550109 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:17:48.556187 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:17:48.559565 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:17:48.562625 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:17:48.570127 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:17:48.572723 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 13:17:48.576190 0 7 0 | B1->B0 | 2929 3030 | 0 0 | (1 1) (0 0)
832 13:17:48.583190 0 7 4 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
833 13:17:48.586298 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:17:48.590253 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:17:48.595874 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:17:48.599991 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 13:17:48.602704 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 13:17:48.609391 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 13:17:48.612816 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 13:17:48.616306 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:17:48.619743 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:17:48.626233 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:17:48.629877 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:17:48.633139 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:17:48.640004 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:17:48.642604 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:17:48.646933 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:17:48.653170 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:17:48.655984 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:17:48.659773 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:17:48.665877 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:17:48.669347 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 13:17:48.672561 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 13:17:48.679638 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 13:17:48.682596 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
856 13:17:48.686176 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
857 13:17:48.692790 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
858 13:17:48.693338 Total UI for P1: 0, mck2ui 16
859 13:17:48.699659 best dqsien dly found for B0: ( 0, 10, 2)
860 13:17:48.700084 Total UI for P1: 0, mck2ui 16
861 13:17:48.706208 best dqsien dly found for B1: ( 0, 10, 2)
862 13:17:48.710149 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
863 13:17:48.712937 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
864 13:17:48.713499
865 13:17:48.716249 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
866 13:17:48.719570 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
867 13:17:48.722776 [Gating] SW calibration Done
868 13:17:48.723204 ==
869 13:17:48.726736 Dram Type= 6, Freq= 0, CH_0, rank 0
870 13:17:48.731061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
871 13:17:48.731554 ==
872 13:17:48.731887 RX Vref Scan: 0
873 13:17:48.732259
874 13:17:48.733920 RX Vref 0 -> 0, step: 1
875 13:17:48.734393
876 13:17:48.737369 RX Delay -130 -> 252, step: 16
877 13:17:48.740120 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
878 13:17:48.744100 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
879 13:17:48.750525 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
880 13:17:48.753682 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
881 13:17:48.757332 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
882 13:17:48.760353 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
883 13:17:48.763724 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
884 13:17:48.766924 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
885 13:17:48.774149 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
886 13:17:48.777885 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
887 13:17:48.780931 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
888 13:17:48.783609 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
889 13:17:48.787051 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
890 13:17:48.793855 iDelay=222, Bit 13, Center 69 (-50 ~ 189) 240
891 13:17:48.797392 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
892 13:17:48.800882 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
893 13:17:48.801305 ==
894 13:17:48.803542 Dram Type= 6, Freq= 0, CH_0, rank 0
895 13:17:48.807355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
896 13:17:48.810694 ==
897 13:17:48.811078 DQS Delay:
898 13:17:48.811373 DQS0 = 0, DQS1 = 0
899 13:17:48.813646 DQM Delay:
900 13:17:48.814225 DQM0 = 83, DQM1 = 70
901 13:17:48.817136 DQ Delay:
902 13:17:48.817670 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
903 13:17:48.820344 DQ4 =77, DQ5 =69, DQ6 =101, DQ7 =101
904 13:17:48.823914 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
905 13:17:48.827279 DQ12 =77, DQ13 =69, DQ14 =85, DQ15 =77
906 13:17:48.830433
907 13:17:48.830933
908 13:17:48.831246 ==
909 13:17:48.833406 Dram Type= 6, Freq= 0, CH_0, rank 0
910 13:17:48.836693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
911 13:17:48.837080 ==
912 13:17:48.837552
913 13:17:48.837839
914 13:17:48.840074 TX Vref Scan disable
915 13:17:48.840455 == TX Byte 0 ==
916 13:17:48.847616 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 13:17:48.850161 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 13:17:48.850553 == TX Byte 1 ==
919 13:17:48.857009 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
920 13:17:48.860805 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
921 13:17:48.861278 ==
922 13:17:48.863484 Dram Type= 6, Freq= 0, CH_0, rank 0
923 13:17:48.867593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 13:17:48.868065 ==
925 13:17:48.880761 TX Vref=22, minBit 2, minWin=27, winSum=447
926 13:17:48.883675 TX Vref=24, minBit 0, minWin=27, winSum=448
927 13:17:48.887221 TX Vref=26, minBit 4, minWin=27, winSum=450
928 13:17:48.891207 TX Vref=28, minBit 2, minWin=28, winSum=459
929 13:17:48.893719 TX Vref=30, minBit 0, minWin=28, winSum=455
930 13:17:48.897748 TX Vref=32, minBit 0, minWin=28, winSum=453
931 13:17:48.903919 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 28
932 13:17:48.904407
933 13:17:48.907188 Final TX Range 1 Vref 28
934 13:17:48.907650
935 13:17:48.908059 ==
936 13:17:48.910176 Dram Type= 6, Freq= 0, CH_0, rank 0
937 13:17:48.913900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
938 13:17:48.914370 ==
939 13:17:48.914776
940 13:17:48.916759
941 13:17:48.917180 TX Vref Scan disable
942 13:17:48.920564 == TX Byte 0 ==
943 13:17:48.923454 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 13:17:48.930215 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 13:17:48.930689 == TX Byte 1 ==
946 13:17:48.933459 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
947 13:17:48.940087 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
948 13:17:48.940559
949 13:17:48.940887 [DATLAT]
950 13:17:48.941279 Freq=800, CH0 RK0
951 13:17:48.941666
952 13:17:48.944640 DATLAT Default: 0xa
953 13:17:48.945156 0, 0xFFFF, sum = 0
954 13:17:48.947027 1, 0xFFFF, sum = 0
955 13:17:48.947453 2, 0xFFFF, sum = 0
956 13:17:48.950021 3, 0xFFFF, sum = 0
957 13:17:48.953209 4, 0xFFFF, sum = 0
958 13:17:48.953748 5, 0xFFFF, sum = 0
959 13:17:48.956414 6, 0xFFFF, sum = 0
960 13:17:48.956845 7, 0xFFFF, sum = 0
961 13:17:48.960402 8, 0x0, sum = 1
962 13:17:48.960850 9, 0x0, sum = 2
963 13:17:48.961186 10, 0x0, sum = 3
964 13:17:48.963174 11, 0x0, sum = 4
965 13:17:48.963600 best_step = 9
966 13:17:48.963923
967 13:17:48.964239 ==
968 13:17:48.966848 Dram Type= 6, Freq= 0, CH_0, rank 0
969 13:17:48.974577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
970 13:17:48.975084 ==
971 13:17:48.975417 RX Vref Scan: 1
972 13:17:48.975717
973 13:17:48.977333 Set Vref Range= 32 -> 127
974 13:17:48.977755
975 13:17:48.980801 RX Vref 32 -> 127, step: 1
976 13:17:48.981341
977 13:17:48.983435 RX Delay -111 -> 252, step: 8
978 13:17:48.983856
979 13:17:48.987499 Set Vref, RX VrefLevel [Byte0]: 32
980 13:17:48.988007 [Byte1]: 32
981 13:17:48.991630
982 13:17:48.992137 Set Vref, RX VrefLevel [Byte0]: 33
983 13:17:48.994595 [Byte1]: 33
984 13:17:48.999196
985 13:17:48.999685 Set Vref, RX VrefLevel [Byte0]: 34
986 13:17:49.002179 [Byte1]: 34
987 13:17:49.006950
988 13:17:49.007452 Set Vref, RX VrefLevel [Byte0]: 35
989 13:17:49.010219 [Byte1]: 35
990 13:17:49.014254
991 13:17:49.014759 Set Vref, RX VrefLevel [Byte0]: 36
992 13:17:49.017076 [Byte1]: 36
993 13:17:49.022187
994 13:17:49.022670 Set Vref, RX VrefLevel [Byte0]: 37
995 13:17:49.024850 [Byte1]: 37
996 13:17:49.029647
997 13:17:49.030148 Set Vref, RX VrefLevel [Byte0]: 38
998 13:17:49.032582 [Byte1]: 38
999 13:17:49.036984
1000 13:17:49.037544 Set Vref, RX VrefLevel [Byte0]: 39
1001 13:17:49.041008 [Byte1]: 39
1002 13:17:49.044782
1003 13:17:49.045207 Set Vref, RX VrefLevel [Byte0]: 40
1004 13:17:49.048503 [Byte1]: 40
1005 13:17:49.052315
1006 13:17:49.052808 Set Vref, RX VrefLevel [Byte0]: 41
1007 13:17:49.055471 [Byte1]: 41
1008 13:17:49.060443
1009 13:17:49.061097 Set Vref, RX VrefLevel [Byte0]: 42
1010 13:17:49.064612 [Byte1]: 42
1011 13:17:49.067921
1012 13:17:49.068403 Set Vref, RX VrefLevel [Byte0]: 43
1013 13:17:49.070834 [Byte1]: 43
1014 13:17:49.075622
1015 13:17:49.076085 Set Vref, RX VrefLevel [Byte0]: 44
1016 13:17:49.079793 [Byte1]: 44
1017 13:17:49.083390
1018 13:17:49.083815 Set Vref, RX VrefLevel [Byte0]: 45
1019 13:17:49.086217 [Byte1]: 45
1020 13:17:49.090688
1021 13:17:49.091165 Set Vref, RX VrefLevel [Byte0]: 46
1022 13:17:49.094223 [Byte1]: 46
1023 13:17:49.098374
1024 13:17:49.098795 Set Vref, RX VrefLevel [Byte0]: 47
1025 13:17:49.101466 [Byte1]: 47
1026 13:17:49.106577
1027 13:17:49.107061 Set Vref, RX VrefLevel [Byte0]: 48
1028 13:17:49.109576 [Byte1]: 48
1029 13:17:49.114041
1030 13:17:49.114511 Set Vref, RX VrefLevel [Byte0]: 49
1031 13:17:49.116607 [Byte1]: 49
1032 13:17:49.121670
1033 13:17:49.122092 Set Vref, RX VrefLevel [Byte0]: 50
1034 13:17:49.124179 [Byte1]: 50
1035 13:17:49.129147
1036 13:17:49.129683 Set Vref, RX VrefLevel [Byte0]: 51
1037 13:17:49.132007 [Byte1]: 51
1038 13:17:49.136676
1039 13:17:49.137097 Set Vref, RX VrefLevel [Byte0]: 52
1040 13:17:49.139611 [Byte1]: 52
1041 13:17:49.144460
1042 13:17:49.144973 Set Vref, RX VrefLevel [Byte0]: 53
1043 13:17:49.147578 [Byte1]: 53
1044 13:17:49.151777
1045 13:17:49.152320 Set Vref, RX VrefLevel [Byte0]: 54
1046 13:17:49.155932 [Byte1]: 54
1047 13:17:49.160189
1048 13:17:49.160762 Set Vref, RX VrefLevel [Byte0]: 55
1049 13:17:49.162655 [Byte1]: 55
1050 13:17:49.167194
1051 13:17:49.167621 Set Vref, RX VrefLevel [Byte0]: 56
1052 13:17:49.170457 [Byte1]: 56
1053 13:17:49.174556
1054 13:17:49.174978 Set Vref, RX VrefLevel [Byte0]: 57
1055 13:17:49.179019 [Byte1]: 57
1056 13:17:49.182774
1057 13:17:49.183201 Set Vref, RX VrefLevel [Byte0]: 58
1058 13:17:49.185491 [Byte1]: 58
1059 13:17:49.190208
1060 13:17:49.190640 Set Vref, RX VrefLevel [Byte0]: 59
1061 13:17:49.193356 [Byte1]: 59
1062 13:17:49.197890
1063 13:17:49.198313 Set Vref, RX VrefLevel [Byte0]: 60
1064 13:17:49.200953 [Byte1]: 60
1065 13:17:49.205268
1066 13:17:49.205742 Set Vref, RX VrefLevel [Byte0]: 61
1067 13:17:49.208673 [Byte1]: 61
1068 13:17:49.213767
1069 13:17:49.214275 Set Vref, RX VrefLevel [Byte0]: 62
1070 13:17:49.216997 [Byte1]: 62
1071 13:17:49.221187
1072 13:17:49.221716 Set Vref, RX VrefLevel [Byte0]: 63
1073 13:17:49.224010 [Byte1]: 63
1074 13:17:49.228290
1075 13:17:49.228793 Set Vref, RX VrefLevel [Byte0]: 64
1076 13:17:49.231863 [Byte1]: 64
1077 13:17:49.235632
1078 13:17:49.236058 Set Vref, RX VrefLevel [Byte0]: 65
1079 13:17:49.239334 [Byte1]: 65
1080 13:17:49.243879
1081 13:17:49.244388 Set Vref, RX VrefLevel [Byte0]: 66
1082 13:17:49.246663 [Byte1]: 66
1083 13:17:49.251258
1084 13:17:49.251759 Set Vref, RX VrefLevel [Byte0]: 67
1085 13:17:49.254455 [Byte1]: 67
1086 13:17:49.258924
1087 13:17:49.259347 Set Vref, RX VrefLevel [Byte0]: 68
1088 13:17:49.261720 [Byte1]: 68
1089 13:17:49.267738
1090 13:17:49.268252 Set Vref, RX VrefLevel [Byte0]: 69
1091 13:17:49.269745 [Byte1]: 69
1092 13:17:49.273940
1093 13:17:49.274367 Set Vref, RX VrefLevel [Byte0]: 70
1094 13:17:49.279391 [Byte1]: 70
1095 13:17:49.282280
1096 13:17:49.282704 Set Vref, RX VrefLevel [Byte0]: 71
1097 13:17:49.285036 [Byte1]: 71
1098 13:17:49.289463
1099 13:17:49.289965 Set Vref, RX VrefLevel [Byte0]: 72
1100 13:17:49.292326 [Byte1]: 72
1101 13:17:49.297540
1102 13:17:49.298042 Set Vref, RX VrefLevel [Byte0]: 73
1103 13:17:49.300466 [Byte1]: 73
1104 13:17:49.305044
1105 13:17:49.305767 Final RX Vref Byte 0 = 51 to rank0
1106 13:17:49.308010 Final RX Vref Byte 1 = 55 to rank0
1107 13:17:49.311297 Final RX Vref Byte 0 = 51 to rank1
1108 13:17:49.314911 Final RX Vref Byte 1 = 55 to rank1==
1109 13:17:49.318492 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 13:17:49.324506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1111 13:17:49.324999 ==
1112 13:17:49.325542 DQS Delay:
1113 13:17:49.325875 DQS0 = 0, DQS1 = 0
1114 13:17:49.328727 DQM Delay:
1115 13:17:49.329269 DQM0 = 83, DQM1 = 73
1116 13:17:49.331626 DQ Delay:
1117 13:17:49.334572 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1118 13:17:49.335000 DQ4 =88, DQ5 =72, DQ6 =88, DQ7 =92
1119 13:17:49.338345 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1120 13:17:49.341221 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1121 13:17:49.344635
1122 13:17:49.345050
1123 13:17:49.351535 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1124 13:17:49.354832 CH0 RK0: MR19=606, MR18=3B3B
1125 13:17:49.361862 CH0_RK0: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1126 13:17:49.362288
1127 13:17:49.364628 ----->DramcWriteLeveling(PI) begin...
1128 13:17:49.365057 ==
1129 13:17:49.367963 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 13:17:49.371418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1131 13:17:49.371859 ==
1132 13:17:49.374367 Write leveling (Byte 0): 27 => 27
1133 13:17:49.378064 Write leveling (Byte 1): 30 => 30
1134 13:17:49.382047 DramcWriteLeveling(PI) end<-----
1135 13:17:49.382543
1136 13:17:49.382875 ==
1137 13:17:49.385166 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 13:17:49.388095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1139 13:17:49.388536 ==
1140 13:17:49.391388 [Gating] SW mode calibration
1141 13:17:49.398505 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 13:17:49.404996 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 13:17:49.408492 0 6 0 | B1->B0 | 3131 3030 | 0 1 | (0 1) (0 1)
1144 13:17:49.411677 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
1145 13:17:49.417834 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 13:17:49.422712 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 13:17:49.424506 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 13:17:49.431559 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 13:17:49.434796 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:17:49.438296 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:17:49.441324 0 7 0 | B1->B0 | 2525 2e2e | 0 0 | (1 1) (1 1)
1152 13:17:49.448432 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1153 13:17:49.451557 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1154 13:17:49.455796 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1155 13:17:49.461651 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1156 13:17:49.464974 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1157 13:17:49.468415 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1158 13:17:49.474635 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1159 13:17:49.478070 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1160 13:17:49.481101 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1161 13:17:49.487705 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1162 13:17:49.491293 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1163 13:17:49.495008 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1164 13:17:49.501382 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1165 13:17:49.504639 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1166 13:17:49.507824 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1167 13:17:49.515392 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1168 13:17:49.518581 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1169 13:17:49.521438 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1170 13:17:49.529311 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1171 13:17:49.531537 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1172 13:17:49.534715 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1173 13:17:49.538302 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1174 13:17:49.545672 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1175 13:17:49.548171 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1176 13:17:49.551466 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1177 13:17:49.554694 Total UI for P1: 0, mck2ui 16
1178 13:17:49.557990 best dqsien dly found for B0: ( 0, 10, 0)
1179 13:17:49.561469 Total UI for P1: 0, mck2ui 16
1180 13:17:49.564668 best dqsien dly found for B1: ( 0, 10, 0)
1181 13:17:49.568530 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1182 13:17:49.571703 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1183 13:17:49.615732
1184 13:17:49.616201 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1185 13:17:49.616851 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1186 13:17:49.617189 [Gating] SW calibration Done
1187 13:17:49.617546 ==
1188 13:17:49.617835 Dram Type= 6, Freq= 0, CH_0, rank 1
1189 13:17:49.618285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1190 13:17:49.618595 ==
1191 13:17:49.618877 RX Vref Scan: 0
1192 13:17:49.619153
1193 13:17:49.619426 RX Vref 0 -> 0, step: 1
1194 13:17:49.619696
1195 13:17:49.619967 RX Delay -130 -> 252, step: 16
1196 13:17:49.620246 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1197 13:17:49.620523 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1198 13:17:49.620796 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1199 13:17:49.621070 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1200 13:17:49.660121 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1201 13:17:49.660599 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1202 13:17:49.661302 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1203 13:17:49.661656 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1204 13:17:49.661961 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1205 13:17:49.662252 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1206 13:17:49.662538 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1207 13:17:49.662872 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1208 13:17:49.663256 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1209 13:17:49.663627 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1210 13:17:49.663969 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1211 13:17:49.683690 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1212 13:17:49.684180 ==
1213 13:17:49.684513 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 13:17:49.685134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1215 13:17:49.685499 ==
1216 13:17:49.685795 DQS Delay:
1217 13:17:49.686076 DQS0 = 0, DQS1 = 0
1218 13:17:49.686354 DQM Delay:
1219 13:17:49.686627 DQM0 = 83, DQM1 = 74
1220 13:17:49.686988 DQ Delay:
1221 13:17:49.687336 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1222 13:17:49.687626 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1223 13:17:49.688943 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1224 13:17:49.692039 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1225 13:17:49.692541
1226 13:17:49.692868
1227 13:17:49.693169 ==
1228 13:17:49.694961 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 13:17:49.698534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1230 13:17:49.698962 ==
1231 13:17:49.699348
1232 13:17:49.699651
1233 13:17:49.701111 TX Vref Scan disable
1234 13:17:49.701583 == TX Byte 0 ==
1235 13:17:49.707882 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1236 13:17:49.711373 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1237 13:17:49.711885 == TX Byte 1 ==
1238 13:17:49.718546 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1239 13:17:49.722399 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1240 13:17:49.722819 ==
1241 13:17:49.725424 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 13:17:49.728592 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1243 13:17:49.728976 ==
1244 13:17:49.741806 TX Vref=22, minBit 0, minWin=27, winSum=440
1245 13:17:49.745399 TX Vref=24, minBit 0, minWin=27, winSum=450
1246 13:17:49.748006 TX Vref=26, minBit 1, minWin=28, winSum=453
1247 13:17:49.751686 TX Vref=28, minBit 2, minWin=28, winSum=458
1248 13:17:49.755174 TX Vref=30, minBit 2, minWin=28, winSum=460
1249 13:17:49.758104 TX Vref=32, minBit 0, minWin=28, winSum=458
1250 13:17:49.764652 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 30
1251 13:17:49.765038
1252 13:17:49.768254 Final TX Range 1 Vref 30
1253 13:17:49.768634
1254 13:17:49.768922 ==
1255 13:17:49.771609 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 13:17:49.775452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1257 13:17:49.775723 ==
1258 13:17:49.775930
1259 13:17:49.777846
1260 13:17:49.778113 TX Vref Scan disable
1261 13:17:49.781599 == TX Byte 0 ==
1262 13:17:49.784533 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1263 13:17:49.789140 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1264 13:17:49.792037 == TX Byte 1 ==
1265 13:17:49.794734 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1266 13:17:49.798115 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1267 13:17:49.801653
1268 13:17:49.801921 [DATLAT]
1269 13:17:49.802134 Freq=800, CH0 RK1
1270 13:17:49.802331
1271 13:17:49.804721 DATLAT Default: 0x9
1272 13:17:49.804996 0, 0xFFFF, sum = 0
1273 13:17:49.808358 1, 0xFFFF, sum = 0
1274 13:17:49.808633 2, 0xFFFF, sum = 0
1275 13:17:49.811434 3, 0xFFFF, sum = 0
1276 13:17:49.811709 4, 0xFFFF, sum = 0
1277 13:17:49.814810 5, 0xFFFF, sum = 0
1278 13:17:49.815162 6, 0xFFFF, sum = 0
1279 13:17:49.818142 7, 0xFFFF, sum = 0
1280 13:17:49.818436 8, 0x0, sum = 1
1281 13:17:49.821218 9, 0x0, sum = 2
1282 13:17:49.821584 10, 0x0, sum = 3
1283 13:17:49.824771 11, 0x0, sum = 4
1284 13:17:49.825137 best_step = 9
1285 13:17:49.825466
1286 13:17:49.825721 ==
1287 13:17:49.828234 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 13:17:49.834971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1289 13:17:49.835369 ==
1290 13:17:49.835673 RX Vref Scan: 0
1291 13:17:49.835987
1292 13:17:49.838335 RX Vref 0 -> 0, step: 1
1293 13:17:49.838740
1294 13:17:49.841640 RX Delay -111 -> 252, step: 8
1295 13:17:49.845329 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1296 13:17:49.848499 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1297 13:17:49.851562 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1298 13:17:49.858618 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1299 13:17:49.861595 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1300 13:17:49.864848 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1301 13:17:49.868338 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1302 13:17:49.871737 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1303 13:17:49.878523 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1304 13:17:49.881419 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1305 13:17:49.884806 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1306 13:17:49.888284 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1307 13:17:49.892513 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1308 13:17:49.898253 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1309 13:17:49.902349 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1310 13:17:49.905217 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1311 13:17:49.905634 ==
1312 13:17:49.908683 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 13:17:49.911923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1314 13:17:49.912338 ==
1315 13:17:49.915972 DQS Delay:
1316 13:17:49.916356 DQS0 = 0, DQS1 = 0
1317 13:17:49.918432 DQM Delay:
1318 13:17:49.918813 DQM0 = 86, DQM1 = 74
1319 13:17:49.921633 DQ Delay:
1320 13:17:49.922127 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =84
1321 13:17:49.924718 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1322 13:17:49.928315 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1323 13:17:49.931762 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1324 13:17:49.932190
1325 13:17:49.934456
1326 13:17:49.942020 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f4f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1327 13:17:49.944700 CH0 RK1: MR19=606, MR18=4F4F
1328 13:17:49.951309 CH0_RK1: MR19=0x606, MR18=0x4F4F, DQSOSC=390, MR23=63, INC=97, DEC=64
1329 13:17:49.951876 [RxdqsGatingPostProcess] freq 800
1330 13:17:49.958727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1331 13:17:49.961408 Pre-setting of DQS Precalculation
1332 13:17:49.964913 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1333 13:17:49.968022 ==
1334 13:17:49.968433 Dram Type= 6, Freq= 0, CH_1, rank 0
1335 13:17:49.975196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1336 13:17:49.975828 ==
1337 13:17:49.978130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1338 13:17:49.984708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1339 13:17:49.994018 [CA 0] Center 36 (6~67) winsize 62
1340 13:17:49.998331 [CA 1] Center 36 (6~67) winsize 62
1341 13:17:50.000719 [CA 2] Center 34 (4~65) winsize 62
1342 13:17:50.004523 [CA 3] Center 34 (4~65) winsize 62
1343 13:17:50.007722 [CA 4] Center 33 (3~64) winsize 62
1344 13:17:50.010703 [CA 5] Center 33 (3~64) winsize 62
1345 13:17:50.011088
1346 13:17:50.014284 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1347 13:17:50.014677
1348 13:17:50.017378 [CATrainingPosCal] consider 1 rank data
1349 13:17:50.021027 u2DelayCellTimex100 = 270/100 ps
1350 13:17:50.024364 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1351 13:17:50.027780 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1352 13:17:50.034435 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1353 13:17:50.037553 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1354 13:17:50.041697 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1355 13:17:50.044411 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1356 13:17:50.045013
1357 13:17:50.047736 CA PerBit enable=1, Macro0, CA PI delay=33
1358 13:17:50.048121
1359 13:17:50.051146 [CBTSetCACLKResult] CA Dly = 33
1360 13:17:50.051527 CS Dly: 4 (0~35)
1361 13:17:50.054120 ==
1362 13:17:50.054533 Dram Type= 6, Freq= 0, CH_1, rank 1
1363 13:17:50.061320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1364 13:17:50.061739 ==
1365 13:17:50.063921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1366 13:17:50.070561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1367 13:17:50.080354 [CA 0] Center 36 (6~67) winsize 62
1368 13:17:50.084131 [CA 1] Center 36 (5~67) winsize 63
1369 13:17:50.087348 [CA 2] Center 34 (4~65) winsize 62
1370 13:17:50.090762 [CA 3] Center 34 (4~64) winsize 61
1371 13:17:50.093933 [CA 4] Center 33 (3~64) winsize 62
1372 13:17:50.096911 [CA 5] Center 33 (2~64) winsize 63
1373 13:17:50.097378
1374 13:17:50.100733 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1375 13:17:50.101255
1376 13:17:50.103709 [CATrainingPosCal] consider 2 rank data
1377 13:17:50.106767 u2DelayCellTimex100 = 270/100 ps
1378 13:17:50.110132 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1379 13:17:50.113162 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1380 13:17:50.120183 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1381 13:17:50.124086 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1382 13:17:50.126784 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1383 13:17:50.129813 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1384 13:17:50.130378
1385 13:17:50.133353 CA PerBit enable=1, Macro0, CA PI delay=33
1386 13:17:50.133738
1387 13:17:50.136915 [CBTSetCACLKResult] CA Dly = 33
1388 13:17:50.137331 CS Dly: 4 (0~36)
1389 13:17:50.137634
1390 13:17:50.140602 ----->DramcWriteLeveling(PI) begin...
1391 13:17:50.143281 ==
1392 13:17:50.143666 Dram Type= 6, Freq= 0, CH_1, rank 0
1393 13:17:50.149842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1394 13:17:50.150224 ==
1395 13:17:50.153409 Write leveling (Byte 0): 27 => 27
1396 13:17:50.156682 Write leveling (Byte 1): 26 => 26
1397 13:17:50.160213 DramcWriteLeveling(PI) end<-----
1398 13:17:50.160662
1399 13:17:50.160983 ==
1400 13:17:50.163174 Dram Type= 6, Freq= 0, CH_1, rank 0
1401 13:17:50.166688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1402 13:17:50.167174 ==
1403 13:17:50.170235 [Gating] SW mode calibration
1404 13:17:50.176734 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1405 13:17:50.180265 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1406 13:17:50.186859 0 6 0 | B1->B0 | 2f2f 2626 | 1 1 | (1 0) (1 0)
1407 13:17:50.190347 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1408 13:17:50.194082 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1409 13:17:50.199946 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1410 13:17:50.203794 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1411 13:17:50.206971 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1412 13:17:50.213639 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1413 13:17:50.217708 0 6 28 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
1414 13:17:50.220221 0 7 0 | B1->B0 | 2727 4141 | 1 0 | (0 0) (0 0)
1415 13:17:50.226962 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1416 13:17:50.230368 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1417 13:17:50.233869 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1418 13:17:50.239803 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1419 13:17:50.243713 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1420 13:17:50.246880 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1421 13:17:50.254158 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1422 13:17:50.256851 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1423 13:17:50.260065 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1424 13:17:50.263518 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1425 13:17:50.270084 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1426 13:17:50.273314 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1427 13:17:50.276987 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1428 13:17:50.283103 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1429 13:17:50.286257 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1430 13:17:50.290201 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1431 13:17:50.297078 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1432 13:17:50.300432 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1433 13:17:50.303949 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1434 13:17:50.309823 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1435 13:17:50.313153 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1436 13:17:50.317112 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1437 13:17:50.323153 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1438 13:17:50.327236 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1439 13:17:50.330221 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1440 13:17:50.333459 Total UI for P1: 0, mck2ui 16
1441 13:17:50.337297 best dqsien dly found for B0: ( 0, 9, 30)
1442 13:17:50.340433 Total UI for P1: 0, mck2ui 16
1443 13:17:50.344136 best dqsien dly found for B1: ( 0, 10, 0)
1444 13:17:50.347565 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1445 13:17:50.350070 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1446 13:17:50.350506
1447 13:17:50.353527 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1448 13:17:50.360338 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1449 13:17:50.360876 [Gating] SW calibration Done
1450 13:17:50.361279 ==
1451 13:17:50.363269 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 13:17:50.369878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1453 13:17:50.370300 ==
1454 13:17:50.370622 RX Vref Scan: 0
1455 13:17:50.370920
1456 13:17:50.373126 RX Vref 0 -> 0, step: 1
1457 13:17:50.373680
1458 13:17:50.376683 RX Delay -130 -> 252, step: 16
1459 13:17:50.380223 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1460 13:17:50.384559 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1461 13:17:50.387211 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1462 13:17:50.393493 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1463 13:17:50.396666 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1464 13:17:50.400586 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1465 13:17:50.403660 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1466 13:17:50.407416 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1467 13:17:50.414231 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1468 13:17:50.416730 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1469 13:17:50.419943 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1470 13:17:50.423396 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1471 13:17:50.426661 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1472 13:17:50.433324 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1473 13:17:50.437084 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1474 13:17:50.439892 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1475 13:17:50.440311 ==
1476 13:17:50.443738 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 13:17:50.446642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1478 13:17:50.447063 ==
1479 13:17:50.450099 DQS Delay:
1480 13:17:50.450518 DQS0 = 0, DQS1 = 0
1481 13:17:50.453314 DQM Delay:
1482 13:17:50.453809 DQM0 = 81, DQM1 = 70
1483 13:17:50.454140 DQ Delay:
1484 13:17:50.457518 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1485 13:17:50.459791 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1486 13:17:50.463482 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1487 13:17:50.466865 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1488 13:17:50.467286
1489 13:17:50.467608
1490 13:17:50.467905 ==
1491 13:17:50.470273 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 13:17:50.476630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1493 13:17:50.477037 ==
1494 13:17:50.477407
1495 13:17:50.477686
1496 13:17:50.477955 TX Vref Scan disable
1497 13:17:50.480562 == TX Byte 0 ==
1498 13:17:50.484073 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1499 13:17:50.487089 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1500 13:17:50.490793 == TX Byte 1 ==
1501 13:17:50.493830 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1502 13:17:50.497565 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1503 13:17:50.500656 ==
1504 13:17:50.503869 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 13:17:50.507376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1506 13:17:50.507874 ==
1507 13:17:50.519371 TX Vref=22, minBit 3, minWin=27, winSum=443
1508 13:17:50.522419 TX Vref=24, minBit 3, minWin=27, winSum=449
1509 13:17:50.525932 TX Vref=26, minBit 3, minWin=27, winSum=447
1510 13:17:50.528954 TX Vref=28, minBit 0, minWin=28, winSum=451
1511 13:17:50.532560 TX Vref=30, minBit 0, minWin=28, winSum=453
1512 13:17:50.536619 TX Vref=32, minBit 0, minWin=28, winSum=452
1513 13:17:50.542547 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1514 13:17:50.542937
1515 13:17:50.546168 Final TX Range 1 Vref 30
1516 13:17:50.546552
1517 13:17:50.546915 ==
1518 13:17:50.549358 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 13:17:50.553206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 13:17:50.553635 ==
1521 13:17:50.553934
1522 13:17:50.556240
1523 13:17:50.556623 TX Vref Scan disable
1524 13:17:50.559150 == TX Byte 0 ==
1525 13:17:50.562875 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1526 13:17:50.566392 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1527 13:17:50.569135 == TX Byte 1 ==
1528 13:17:50.572747 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1529 13:17:50.575817 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1530 13:17:50.579432
1531 13:17:50.579814 [DATLAT]
1532 13:17:50.580110 Freq=800, CH1 RK0
1533 13:17:50.580388
1534 13:17:50.582789 DATLAT Default: 0xa
1535 13:17:50.583222 0, 0xFFFF, sum = 0
1536 13:17:50.585966 1, 0xFFFF, sum = 0
1537 13:17:50.586392 2, 0xFFFF, sum = 0
1538 13:17:50.589760 3, 0xFFFF, sum = 0
1539 13:17:50.590185 4, 0xFFFF, sum = 0
1540 13:17:50.592435 5, 0xFFFF, sum = 0
1541 13:17:50.593001 6, 0xFFFF, sum = 0
1542 13:17:50.595554 7, 0xFFFF, sum = 0
1543 13:17:50.595967 8, 0x0, sum = 1
1544 13:17:50.598974 9, 0x0, sum = 2
1545 13:17:50.599375 10, 0x0, sum = 3
1546 13:17:50.603092 11, 0x0, sum = 4
1547 13:17:50.603495 best_step = 9
1548 13:17:50.603788
1549 13:17:50.604075 ==
1550 13:17:50.606020 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 13:17:50.612240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1552 13:17:50.612904 ==
1553 13:17:50.613456 RX Vref Scan: 1
1554 13:17:50.613756
1555 13:17:50.616099 Set Vref Range= 32 -> 127
1556 13:17:50.616482
1557 13:17:50.619176 RX Vref 32 -> 127, step: 1
1558 13:17:50.619712
1559 13:17:50.620076 RX Delay -111 -> 252, step: 8
1560 13:17:50.623039
1561 13:17:50.623438 Set Vref, RX VrefLevel [Byte0]: 32
1562 13:17:50.625686 [Byte1]: 32
1563 13:17:50.630983
1564 13:17:50.631436 Set Vref, RX VrefLevel [Byte0]: 33
1565 13:17:50.633441 [Byte1]: 33
1566 13:17:50.638568
1567 13:17:50.639012 Set Vref, RX VrefLevel [Byte0]: 34
1568 13:17:50.640809 [Byte1]: 34
1569 13:17:50.645789
1570 13:17:50.646190 Set Vref, RX VrefLevel [Byte0]: 35
1571 13:17:50.648756 [Byte1]: 35
1572 13:17:50.653671
1573 13:17:50.654120 Set Vref, RX VrefLevel [Byte0]: 36
1574 13:17:50.656377 [Byte1]: 36
1575 13:17:50.660612
1576 13:17:50.661037 Set Vref, RX VrefLevel [Byte0]: 37
1577 13:17:50.664557 [Byte1]: 37
1578 13:17:50.668592
1579 13:17:50.668970 Set Vref, RX VrefLevel [Byte0]: 38
1580 13:17:50.671867 [Byte1]: 38
1581 13:17:50.676036
1582 13:17:50.676473 Set Vref, RX VrefLevel [Byte0]: 39
1583 13:17:50.679632 [Byte1]: 39
1584 13:17:50.683599
1585 13:17:50.684042 Set Vref, RX VrefLevel [Byte0]: 40
1586 13:17:50.686721 [Byte1]: 40
1587 13:17:50.691394
1588 13:17:50.691818 Set Vref, RX VrefLevel [Byte0]: 41
1589 13:17:50.694275 [Byte1]: 41
1590 13:17:50.699969
1591 13:17:50.700457 Set Vref, RX VrefLevel [Byte0]: 42
1592 13:17:50.702453 [Byte1]: 42
1593 13:17:50.706990
1594 13:17:50.707410 Set Vref, RX VrefLevel [Byte0]: 43
1595 13:17:50.709567 [Byte1]: 43
1596 13:17:50.714035
1597 13:17:50.714474 Set Vref, RX VrefLevel [Byte0]: 44
1598 13:17:50.718038 [Byte1]: 44
1599 13:17:50.722044
1600 13:17:50.722464 Set Vref, RX VrefLevel [Byte0]: 45
1601 13:17:50.725331 [Byte1]: 45
1602 13:17:50.729497
1603 13:17:50.729878 Set Vref, RX VrefLevel [Byte0]: 46
1604 13:17:50.732746 [Byte1]: 46
1605 13:17:50.737646
1606 13:17:50.738023 Set Vref, RX VrefLevel [Byte0]: 47
1607 13:17:50.740515 [Byte1]: 47
1608 13:17:50.745095
1609 13:17:50.745550 Set Vref, RX VrefLevel [Byte0]: 48
1610 13:17:50.748021 [Byte1]: 48
1611 13:17:50.752686
1612 13:17:50.753187 Set Vref, RX VrefLevel [Byte0]: 49
1613 13:17:50.755916 [Byte1]: 49
1614 13:17:50.760111
1615 13:17:50.760565 Set Vref, RX VrefLevel [Byte0]: 50
1616 13:17:50.763296 [Byte1]: 50
1617 13:17:50.767429
1618 13:17:50.767807 Set Vref, RX VrefLevel [Byte0]: 51
1619 13:17:50.771078 [Byte1]: 51
1620 13:17:50.775330
1621 13:17:50.775752 Set Vref, RX VrefLevel [Byte0]: 52
1622 13:17:50.778780 [Byte1]: 52
1623 13:17:50.783612
1624 13:17:50.784066 Set Vref, RX VrefLevel [Byte0]: 53
1625 13:17:50.786346 [Byte1]: 53
1626 13:17:50.790857
1627 13:17:50.791284 Set Vref, RX VrefLevel [Byte0]: 54
1628 13:17:50.794284 [Byte1]: 54
1629 13:17:50.798692
1630 13:17:50.799068 Set Vref, RX VrefLevel [Byte0]: 55
1631 13:17:50.801577 [Byte1]: 55
1632 13:17:50.806287
1633 13:17:50.806712 Set Vref, RX VrefLevel [Byte0]: 56
1634 13:17:50.809862 [Byte1]: 56
1635 13:17:50.813612
1636 13:17:50.814042 Set Vref, RX VrefLevel [Byte0]: 57
1637 13:17:50.817045 [Byte1]: 57
1638 13:17:50.821162
1639 13:17:50.821591 Set Vref, RX VrefLevel [Byte0]: 58
1640 13:17:50.824632 [Byte1]: 58
1641 13:17:50.829403
1642 13:17:50.829836 Set Vref, RX VrefLevel [Byte0]: 59
1643 13:17:50.832290 [Byte1]: 59
1644 13:17:50.836551
1645 13:17:50.837119 Set Vref, RX VrefLevel [Byte0]: 60
1646 13:17:50.840091 [Byte1]: 60
1647 13:17:50.844454
1648 13:17:50.844868 Set Vref, RX VrefLevel [Byte0]: 61
1649 13:17:50.847980 [Byte1]: 61
1650 13:17:50.851671
1651 13:17:50.852046 Set Vref, RX VrefLevel [Byte0]: 62
1652 13:17:50.855226 [Byte1]: 62
1653 13:17:50.859385
1654 13:17:50.859762 Set Vref, RX VrefLevel [Byte0]: 63
1655 13:17:50.863006 [Byte1]: 63
1656 13:17:50.867040
1657 13:17:50.867444 Set Vref, RX VrefLevel [Byte0]: 64
1658 13:17:50.870780 [Byte1]: 64
1659 13:17:50.875784
1660 13:17:50.876166 Set Vref, RX VrefLevel [Byte0]: 65
1661 13:17:50.878827 [Byte1]: 65
1662 13:17:50.882796
1663 13:17:50.883190 Set Vref, RX VrefLevel [Byte0]: 66
1664 13:17:50.885679 [Byte1]: 66
1665 13:17:50.890729
1666 13:17:50.891128 Set Vref, RX VrefLevel [Byte0]: 67
1667 13:17:50.893473 [Byte1]: 67
1668 13:17:50.897884
1669 13:17:50.898270 Set Vref, RX VrefLevel [Byte0]: 68
1670 13:17:50.901331 [Byte1]: 68
1671 13:17:50.905769
1672 13:17:50.906199 Set Vref, RX VrefLevel [Byte0]: 69
1673 13:17:50.909283 [Byte1]: 69
1674 13:17:50.913848
1675 13:17:50.914311 Set Vref, RX VrefLevel [Byte0]: 70
1676 13:17:50.917120 [Byte1]: 70
1677 13:17:50.921163
1678 13:17:50.921683 Set Vref, RX VrefLevel [Byte0]: 71
1679 13:17:50.924607 [Byte1]: 71
1680 13:17:50.928813
1681 13:17:50.929290 Set Vref, RX VrefLevel [Byte0]: 72
1682 13:17:50.931621 [Byte1]: 72
1683 13:17:50.935981
1684 13:17:50.936408 Set Vref, RX VrefLevel [Byte0]: 73
1685 13:17:50.942712 [Byte1]: 73
1686 13:17:50.943187
1687 13:17:50.946361 Set Vref, RX VrefLevel [Byte0]: 74
1688 13:17:50.949175 [Byte1]: 74
1689 13:17:50.949679
1690 13:17:50.952673 Set Vref, RX VrefLevel [Byte0]: 75
1691 13:17:50.956316 [Byte1]: 75
1692 13:17:50.956812
1693 13:17:50.959573 Final RX Vref Byte 0 = 60 to rank0
1694 13:17:50.962804 Final RX Vref Byte 1 = 55 to rank0
1695 13:17:50.966213 Final RX Vref Byte 0 = 60 to rank1
1696 13:17:50.969166 Final RX Vref Byte 1 = 55 to rank1==
1697 13:17:50.973312 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 13:17:50.976217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1699 13:17:50.979426 ==
1700 13:17:50.979798 DQS Delay:
1701 13:17:50.980103 DQS0 = 0, DQS1 = 0
1702 13:17:50.982494 DQM Delay:
1703 13:17:50.982913 DQM0 = 79, DQM1 = 72
1704 13:17:50.983236 DQ Delay:
1705 13:17:50.986123 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1706 13:17:50.989303 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1707 13:17:50.992872 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1708 13:17:50.996484 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1709 13:17:50.996859
1710 13:17:50.997185
1711 13:17:51.006248 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x606, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
1712 13:17:51.009787 CH1 RK0: MR19=606, MR18=5959
1713 13:17:51.015772 CH1_RK0: MR19=0x606, MR18=0x5959, DQSOSC=387, MR23=63, INC=98, DEC=65
1714 13:17:51.016200
1715 13:17:51.019838 ----->DramcWriteLeveling(PI) begin...
1716 13:17:51.020269 ==
1717 13:17:51.023062 Dram Type= 6, Freq= 0, CH_1, rank 1
1718 13:17:51.025861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1719 13:17:51.026249 ==
1720 13:17:51.029273 Write leveling (Byte 0): 26 => 26
1721 13:17:51.033258 Write leveling (Byte 1): 28 => 28
1722 13:17:51.036030 DramcWriteLeveling(PI) end<-----
1723 13:17:51.036417
1724 13:17:51.036714 ==
1725 13:17:51.039133 Dram Type= 6, Freq= 0, CH_1, rank 1
1726 13:17:51.042820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1727 13:17:51.043210 ==
1728 13:17:51.046098 [Gating] SW mode calibration
1729 13:17:51.052741 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1730 13:17:51.059030 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1731 13:17:51.062506 0 6 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
1732 13:17:51.065594 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1733 13:17:51.072506 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1734 13:17:51.075730 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1735 13:17:51.079603 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1736 13:17:51.085617 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1737 13:17:51.089880 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1738 13:17:51.093201 0 6 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
1739 13:17:51.096191 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
1740 13:17:51.102686 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1741 13:17:51.105723 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1742 13:17:51.109320 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1743 13:17:51.115842 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1744 13:17:51.119376 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1745 13:17:51.122773 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1746 13:17:51.129646 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1747 13:17:51.132602 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1748 13:17:51.136270 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1749 13:17:51.142730 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1750 13:17:51.146377 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1751 13:17:51.149444 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1752 13:17:51.155852 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1753 13:17:51.159479 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1754 13:17:51.162260 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1755 13:17:51.169325 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1756 13:17:51.172903 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1757 13:17:51.175588 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1758 13:17:51.182623 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1759 13:17:51.186144 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1760 13:17:51.189299 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1761 13:17:51.192688 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1762 13:17:51.199057 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1763 13:17:51.202603 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1764 13:17:51.206155 Total UI for P1: 0, mck2ui 16
1765 13:17:51.209867 best dqsien dly found for B0: ( 0, 9, 28)
1766 13:17:51.212642 Total UI for P1: 0, mck2ui 16
1767 13:17:51.215934 best dqsien dly found for B1: ( 0, 9, 30)
1768 13:17:51.219671 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1769 13:17:51.222784 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1770 13:17:51.223254
1771 13:17:51.225709 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1772 13:17:51.232579 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1773 13:17:51.233013 [Gating] SW calibration Done
1774 13:17:51.233380 ==
1775 13:17:51.237103 Dram Type= 6, Freq= 0, CH_1, rank 1
1776 13:17:51.242268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1777 13:17:51.242656 ==
1778 13:17:51.242955 RX Vref Scan: 0
1779 13:17:51.243228
1780 13:17:51.245921 RX Vref 0 -> 0, step: 1
1781 13:17:51.246302
1782 13:17:51.249004 RX Delay -130 -> 252, step: 16
1783 13:17:51.253711 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1784 13:17:51.255979 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1785 13:17:51.259187 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1786 13:17:51.265858 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1787 13:17:51.269262 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1788 13:17:51.272616 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1789 13:17:51.276348 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1790 13:17:51.278762 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1791 13:17:51.282466 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1792 13:17:51.288853 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1793 13:17:51.293049 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1794 13:17:51.296280 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1795 13:17:51.299320 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1796 13:17:51.305590 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1797 13:17:51.309870 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1798 13:17:51.312879 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1799 13:17:51.313343 ==
1800 13:17:51.315923 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 13:17:51.318826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1802 13:17:51.319307 ==
1803 13:17:51.322113 DQS Delay:
1804 13:17:51.322583 DQS0 = 0, DQS1 = 0
1805 13:17:51.325567 DQM Delay:
1806 13:17:51.325987 DQM0 = 81, DQM1 = 70
1807 13:17:51.326318 DQ Delay:
1808 13:17:51.329130 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1809 13:17:51.332641 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1810 13:17:51.335788 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1811 13:17:51.338516 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1812 13:17:51.338941
1813 13:17:51.339265
1814 13:17:51.341897 ==
1815 13:17:51.342316 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 13:17:51.349435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1817 13:17:51.349861 ==
1818 13:17:51.350188
1819 13:17:51.350488
1820 13:17:51.351933 TX Vref Scan disable
1821 13:17:51.352368 == TX Byte 0 ==
1822 13:17:51.356018 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1823 13:17:51.362010 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1824 13:17:51.362436 == TX Byte 1 ==
1825 13:17:51.365799 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1826 13:17:51.371827 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1827 13:17:51.372261 ==
1828 13:17:51.374960 Dram Type= 6, Freq= 0, CH_1, rank 1
1829 13:17:51.378129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1830 13:17:51.378759 ==
1831 13:17:51.391557 TX Vref=22, minBit 8, minWin=27, winSum=450
1832 13:17:51.395198 TX Vref=24, minBit 8, minWin=27, winSum=451
1833 13:17:51.398364 TX Vref=26, minBit 8, minWin=27, winSum=456
1834 13:17:51.401922 TX Vref=28, minBit 0, minWin=28, winSum=457
1835 13:17:51.405155 TX Vref=30, minBit 0, minWin=28, winSum=456
1836 13:17:51.408623 TX Vref=32, minBit 9, minWin=27, winSum=454
1837 13:17:51.415397 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1838 13:17:51.415693
1839 13:17:51.418250 Final TX Range 1 Vref 28
1840 13:17:51.418488
1841 13:17:51.418672 ==
1842 13:17:51.421857 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 13:17:51.425155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1844 13:17:51.425460 ==
1845 13:17:51.425671
1846 13:17:51.428082
1847 13:17:51.428375 TX Vref Scan disable
1848 13:17:51.431911 == TX Byte 0 ==
1849 13:17:51.435388 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1850 13:17:51.438209 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1851 13:17:51.441811 == TX Byte 1 ==
1852 13:17:51.445311 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1853 13:17:51.448296 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1854 13:17:51.448718
1855 13:17:51.451846 [DATLAT]
1856 13:17:51.452322 Freq=800, CH1 RK1
1857 13:17:51.452651
1858 13:17:51.455438 DATLAT Default: 0x9
1859 13:17:51.455860 0, 0xFFFF, sum = 0
1860 13:17:51.458210 1, 0xFFFF, sum = 0
1861 13:17:51.458641 2, 0xFFFF, sum = 0
1862 13:17:51.461612 3, 0xFFFF, sum = 0
1863 13:17:51.462044 4, 0xFFFF, sum = 0
1864 13:17:51.465875 5, 0xFFFF, sum = 0
1865 13:17:51.466354 6, 0xFFFF, sum = 0
1866 13:17:51.468221 7, 0xFFFF, sum = 0
1867 13:17:51.468674 8, 0x0, sum = 1
1868 13:17:51.471442 9, 0x0, sum = 2
1869 13:17:51.471876 10, 0x0, sum = 3
1870 13:17:51.475654 11, 0x0, sum = 4
1871 13:17:51.476088 best_step = 9
1872 13:17:51.476412
1873 13:17:51.476750 ==
1874 13:17:51.478203 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 13:17:51.484894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1876 13:17:51.485365 ==
1877 13:17:51.485702 RX Vref Scan: 0
1878 13:17:51.486006
1879 13:17:51.488846 RX Vref 0 -> 0, step: 1
1880 13:17:51.489313
1881 13:17:51.491632 RX Delay -111 -> 252, step: 8
1882 13:17:51.495150 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1883 13:17:51.498075 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1884 13:17:51.505194 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1885 13:17:51.509335 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1886 13:17:51.512404 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1887 13:17:51.515094 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1888 13:17:51.518022 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1889 13:17:51.521741 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1890 13:17:51.528689 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1891 13:17:51.531932 iDelay=217, Bit 9, Center 60 (-63 ~ 184) 248
1892 13:17:51.535067 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1893 13:17:51.538133 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1894 13:17:51.542656 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1895 13:17:51.548912 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1896 13:17:51.551685 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1897 13:17:51.554990 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1898 13:17:51.555374 ==
1899 13:17:51.558366 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 13:17:51.561978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1901 13:17:51.562476 ==
1902 13:17:51.565602 DQS Delay:
1903 13:17:51.565987 DQS0 = 0, DQS1 = 0
1904 13:17:51.568283 DQM Delay:
1905 13:17:51.568667 DQM0 = 82, DQM1 = 72
1906 13:17:51.568964 DQ Delay:
1907 13:17:51.571482 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1908 13:17:51.575395 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1909 13:17:51.579708 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1910 13:17:51.581990 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
1911 13:17:51.582461
1912 13:17:51.582766
1913 13:17:51.591441 [DQSOSCAuto] RK1, (LSB)MR18= 0x4444, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1914 13:17:51.595113 CH1 RK1: MR19=606, MR18=4444
1915 13:17:51.601505 CH1_RK1: MR19=0x606, MR18=0x4444, DQSOSC=392, MR23=63, INC=96, DEC=64
1916 13:17:51.601897 [RxdqsGatingPostProcess] freq 800
1917 13:17:51.608237 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1918 13:17:51.612070 Pre-setting of DQS Precalculation
1919 13:17:51.615166 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1920 13:17:51.625203 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1921 13:17:51.631943 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1922 13:17:51.632391
1923 13:17:51.632693
1924 13:17:51.634840 [Calibration Summary] 1600 Mbps
1925 13:17:51.635282 CH 0, Rank 0
1926 13:17:51.638397 SW Impedance : PASS
1927 13:17:51.638780 DUTY Scan : NO K
1928 13:17:51.641549 ZQ Calibration : PASS
1929 13:17:51.645157 Jitter Meter : NO K
1930 13:17:51.645570 CBT Training : PASS
1931 13:17:51.648755 Write leveling : PASS
1932 13:17:51.652083 RX DQS gating : PASS
1933 13:17:51.652473 RX DQ/DQS(RDDQC) : PASS
1934 13:17:51.655221 TX DQ/DQS : PASS
1935 13:17:51.658849 RX DATLAT : PASS
1936 13:17:51.659235 RX DQ/DQS(Engine): PASS
1937 13:17:51.661865 TX OE : NO K
1938 13:17:51.662254 All Pass.
1939 13:17:51.662555
1940 13:17:51.664828 CH 0, Rank 1
1941 13:17:51.665211 SW Impedance : PASS
1942 13:17:51.668287 DUTY Scan : NO K
1943 13:17:51.668671 ZQ Calibration : PASS
1944 13:17:51.672168 Jitter Meter : NO K
1945 13:17:51.674976 CBT Training : PASS
1946 13:17:51.675360 Write leveling : PASS
1947 13:17:51.678100 RX DQS gating : PASS
1948 13:17:51.681620 RX DQ/DQS(RDDQC) : PASS
1949 13:17:51.682005 TX DQ/DQS : PASS
1950 13:17:51.684832 RX DATLAT : PASS
1951 13:17:51.688468 RX DQ/DQS(Engine): PASS
1952 13:17:51.688853 TX OE : NO K
1953 13:17:51.691509 All Pass.
1954 13:17:51.691893
1955 13:17:51.692188 CH 1, Rank 0
1956 13:17:51.695400 SW Impedance : PASS
1957 13:17:51.695785 DUTY Scan : NO K
1958 13:17:51.698315 ZQ Calibration : PASS
1959 13:17:51.701615 Jitter Meter : NO K
1960 13:17:51.702005 CBT Training : PASS
1961 13:17:51.705435 Write leveling : PASS
1962 13:17:51.705827 RX DQS gating : PASS
1963 13:17:51.708591 RX DQ/DQS(RDDQC) : PASS
1964 13:17:51.711364 TX DQ/DQS : PASS
1965 13:17:51.711765 RX DATLAT : PASS
1966 13:17:51.714875 RX DQ/DQS(Engine): PASS
1967 13:17:51.718659 TX OE : NO K
1968 13:17:51.719183 All Pass.
1969 13:17:51.719719
1970 13:17:51.720099 CH 1, Rank 1
1971 13:17:51.721379 SW Impedance : PASS
1972 13:17:51.724685 DUTY Scan : NO K
1973 13:17:51.725079 ZQ Calibration : PASS
1974 13:17:51.728380 Jitter Meter : NO K
1975 13:17:51.732093 CBT Training : PASS
1976 13:17:51.732592 Write leveling : PASS
1977 13:17:51.735063 RX DQS gating : PASS
1978 13:17:51.738308 RX DQ/DQS(RDDQC) : PASS
1979 13:17:51.738690 TX DQ/DQS : PASS
1980 13:17:51.741451 RX DATLAT : PASS
1981 13:17:51.744467 RX DQ/DQS(Engine): PASS
1982 13:17:51.744856 TX OE : NO K
1983 13:17:51.745155 All Pass.
1984 13:17:51.748286
1985 13:17:51.748665 DramC Write-DBI off
1986 13:17:51.751505 PER_BANK_REFRESH: Hybrid Mode
1987 13:17:51.751890 TX_TRACKING: ON
1988 13:17:51.755209 [GetDramInforAfterCalByMRR] Vendor 6.
1989 13:17:51.757913 [GetDramInforAfterCalByMRR] Revision 606.
1990 13:17:51.764756 [GetDramInforAfterCalByMRR] Revision 2 0.
1991 13:17:51.765141 MR0 0x3939
1992 13:17:51.765521 MR8 0x1111
1993 13:17:51.768042 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1994 13:17:51.768434
1995 13:17:51.771247 MR0 0x3939
1996 13:17:51.771633 MR8 0x1111
1997 13:17:51.775370 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1998 13:17:51.775833
1999 13:17:51.785194 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2000 13:17:51.788722 [FAST_K] Save calibration result to emmc
2001 13:17:51.791564 [FAST_K] Save calibration result to emmc
2002 13:17:51.795277 dram_init: config_dvfs: 1
2003 13:17:51.798492 dramc_set_vcore_voltage set vcore to 662500
2004 13:17:51.798884 Read voltage for 1200, 2
2005 13:17:51.801632 Vio18 = 0
2006 13:17:51.802014 Vcore = 662500
2007 13:17:51.802315 Vdram = 0
2008 13:17:51.804690 Vddq = 0
2009 13:17:51.805074 Vmddr = 0
2010 13:17:51.808558 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2011 13:17:51.814830 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2012 13:17:51.818346 MEM_TYPE=3, freq_sel=15
2013 13:17:51.821367 sv_algorithm_assistance_LP4_1600
2014 13:17:51.825141 ============ PULL DRAM RESETB DOWN ============
2015 13:17:51.828131 ========== PULL DRAM RESETB DOWN end =========
2016 13:17:51.834887 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2017 13:17:51.838184 ===================================
2018 13:17:51.838706 LPDDR4 DRAM CONFIGURATION
2019 13:17:51.841551 ===================================
2020 13:17:51.845192 EX_ROW_EN[0] = 0x0
2021 13:17:51.845658 EX_ROW_EN[1] = 0x0
2022 13:17:51.848160 LP4Y_EN = 0x0
2023 13:17:51.848653 WORK_FSP = 0x0
2024 13:17:51.851659 WL = 0x4
2025 13:17:51.852161 RL = 0x4
2026 13:17:51.855235 BL = 0x2
2027 13:17:51.855724 RPST = 0x0
2028 13:17:51.858278 RD_PRE = 0x0
2029 13:17:51.861451 WR_PRE = 0x1
2030 13:17:51.861929 WR_PST = 0x0
2031 13:17:51.864999 DBI_WR = 0x0
2032 13:17:51.865612 DBI_RD = 0x0
2033 13:17:51.868332 OTF = 0x1
2034 13:17:51.871475 ===================================
2035 13:17:51.876123 ===================================
2036 13:17:51.876596 ANA top config
2037 13:17:51.878360 ===================================
2038 13:17:51.882024 DLL_ASYNC_EN = 0
2039 13:17:51.882477 ALL_SLAVE_EN = 0
2040 13:17:51.885616 NEW_RANK_MODE = 1
2041 13:17:51.888239 DLL_IDLE_MODE = 1
2042 13:17:51.891444 LP45_APHY_COMB_EN = 1
2043 13:17:51.895679 TX_ODT_DIS = 1
2044 13:17:51.896163 NEW_8X_MODE = 1
2045 13:17:51.898317 ===================================
2046 13:17:51.902227 ===================================
2047 13:17:51.905089 data_rate = 2400
2048 13:17:51.908748 CKR = 1
2049 13:17:51.912104 DQ_P2S_RATIO = 8
2050 13:17:51.915167 ===================================
2051 13:17:51.918913 CA_P2S_RATIO = 8
2052 13:17:51.922152 DQ_CA_OPEN = 0
2053 13:17:51.922663 DQ_SEMI_OPEN = 0
2054 13:17:51.925482 CA_SEMI_OPEN = 0
2055 13:17:51.928276 CA_FULL_RATE = 0
2056 13:17:51.932040 DQ_CKDIV4_EN = 0
2057 13:17:51.935062 CA_CKDIV4_EN = 0
2058 13:17:51.938875 CA_PREDIV_EN = 0
2059 13:17:51.939295 PH8_DLY = 17
2060 13:17:51.941869 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2061 13:17:51.945386 DQ_AAMCK_DIV = 4
2062 13:17:51.948894 CA_AAMCK_DIV = 4
2063 13:17:51.951549 CA_ADMCK_DIV = 4
2064 13:17:51.951986 DQ_TRACK_CA_EN = 0
2065 13:17:51.955002 CA_PICK = 1200
2066 13:17:51.958775 CA_MCKIO = 1200
2067 13:17:51.961514 MCKIO_SEMI = 0
2068 13:17:51.965628 PLL_FREQ = 2366
2069 13:17:51.968103 DQ_UI_PI_RATIO = 32
2070 13:17:51.972115 CA_UI_PI_RATIO = 0
2071 13:17:51.976288 ===================================
2072 13:17:51.978410 ===================================
2073 13:17:51.978833 memory_type:LPDDR4
2074 13:17:51.981725 GP_NUM : 10
2075 13:17:51.985463 SRAM_EN : 1
2076 13:17:51.985922 MD32_EN : 0
2077 13:17:51.988824 ===================================
2078 13:17:51.992103 [ANA_INIT] >>>>>>>>>>>>>>
2079 13:17:51.995989 <<<<<< [CONFIGURE PHASE]: ANA_TX
2080 13:17:51.998751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2081 13:17:52.001955 ===================================
2082 13:17:52.006218 data_rate = 2400,PCW = 0X5b00
2083 13:17:52.008595 ===================================
2084 13:17:52.012719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2085 13:17:52.015207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2086 13:17:52.021909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2087 13:17:52.024980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2088 13:17:52.029057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2089 13:17:52.031798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2090 13:17:52.035317 [ANA_INIT] flow start
2091 13:17:52.038234 [ANA_INIT] PLL >>>>>>>>
2092 13:17:52.038704 [ANA_INIT] PLL <<<<<<<<
2093 13:17:52.042151 [ANA_INIT] MIDPI >>>>>>>>
2094 13:17:52.044941 [ANA_INIT] MIDPI <<<<<<<<
2095 13:17:52.045430 [ANA_INIT] DLL >>>>>>>>
2096 13:17:52.048119 [ANA_INIT] DLL <<<<<<<<
2097 13:17:52.051641 [ANA_INIT] flow end
2098 13:17:52.055108 ============ LP4 DIFF to SE enter ============
2099 13:17:52.058447 ============ LP4 DIFF to SE exit ============
2100 13:17:52.062258 [ANA_INIT] <<<<<<<<<<<<<
2101 13:17:52.065355 [Flow] Enable top DCM control >>>>>
2102 13:17:52.068763 [Flow] Enable top DCM control <<<<<
2103 13:17:52.071858 Enable DLL master slave shuffle
2104 13:17:52.075769 ==============================================================
2105 13:17:52.078830 Gating Mode config
2106 13:17:52.085591 ==============================================================
2107 13:17:52.086013 Config description:
2108 13:17:52.095640 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2109 13:17:52.101921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2110 13:17:52.105848 SELPH_MODE 0: By rank 1: By Phase
2111 13:17:52.111899 ==============================================================
2112 13:17:52.115043 GAT_TRACK_EN = 1
2113 13:17:52.119099 RX_GATING_MODE = 2
2114 13:17:52.121885 RX_GATING_TRACK_MODE = 2
2115 13:17:52.125275 SELPH_MODE = 1
2116 13:17:52.128764 PICG_EARLY_EN = 1
2117 13:17:52.131414 VALID_LAT_VALUE = 1
2118 13:17:52.135173 ==============================================================
2119 13:17:52.138535 Enter into Gating configuration >>>>
2120 13:17:52.141924 Exit from Gating configuration <<<<
2121 13:17:52.145110 Enter into DVFS_PRE_config >>>>>
2122 13:17:52.158174 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2123 13:17:52.158636 Exit from DVFS_PRE_config <<<<<
2124 13:17:52.161574 Enter into PICG configuration >>>>
2125 13:17:52.165489 Exit from PICG configuration <<<<
2126 13:17:52.168127 [RX_INPUT] configuration >>>>>
2127 13:17:52.171994 [RX_INPUT] configuration <<<<<
2128 13:17:52.178561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2129 13:17:52.181931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2130 13:17:52.188447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2131 13:17:52.195482 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2132 13:17:52.202149 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2133 13:17:52.208165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2134 13:17:52.212236 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2135 13:17:52.215724 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2136 13:17:52.219174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2137 13:17:52.224579 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2138 13:17:52.228389 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2139 13:17:52.231392 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2140 13:17:52.234867 ===================================
2141 13:17:52.238938 LPDDR4 DRAM CONFIGURATION
2142 13:17:52.241690 ===================================
2143 13:17:52.242073 EX_ROW_EN[0] = 0x0
2144 13:17:52.245543 EX_ROW_EN[1] = 0x0
2145 13:17:52.246010 LP4Y_EN = 0x0
2146 13:17:52.248397 WORK_FSP = 0x0
2147 13:17:52.248801 WL = 0x4
2148 13:17:52.251471 RL = 0x4
2149 13:17:52.254979 BL = 0x2
2150 13:17:52.255381 RPST = 0x0
2151 13:17:52.258771 RD_PRE = 0x0
2152 13:17:52.259151 WR_PRE = 0x1
2153 13:17:52.262689 WR_PST = 0x0
2154 13:17:52.263177 DBI_WR = 0x0
2155 13:17:52.265023 DBI_RD = 0x0
2156 13:17:52.265494 OTF = 0x1
2157 13:17:52.268433 ===================================
2158 13:17:52.271581 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2159 13:17:52.275541 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2160 13:17:52.281722 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2161 13:17:52.284904 ===================================
2162 13:17:52.288327 LPDDR4 DRAM CONFIGURATION
2163 13:17:52.291790 ===================================
2164 13:17:52.292178 EX_ROW_EN[0] = 0x10
2165 13:17:52.295218 EX_ROW_EN[1] = 0x0
2166 13:17:52.295606 LP4Y_EN = 0x0
2167 13:17:52.298558 WORK_FSP = 0x0
2168 13:17:52.298950 WL = 0x4
2169 13:17:52.301827 RL = 0x4
2170 13:17:52.302331 BL = 0x2
2171 13:17:52.305629 RPST = 0x0
2172 13:17:52.306093 RD_PRE = 0x0
2173 13:17:52.308727 WR_PRE = 0x1
2174 13:17:52.309110 WR_PST = 0x0
2175 13:17:52.312192 DBI_WR = 0x0
2176 13:17:52.312574 DBI_RD = 0x0
2177 13:17:52.315749 OTF = 0x1
2178 13:17:52.318311 ===================================
2179 13:17:52.325814 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2180 13:17:52.326247 ==
2181 13:17:52.329066 Dram Type= 6, Freq= 0, CH_0, rank 0
2182 13:17:52.331905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2183 13:17:52.332291 ==
2184 13:17:52.335560 [Duty_Offset_Calibration]
2185 13:17:52.335951 B0:0 B1:2 CA:1
2186 13:17:52.336252
2187 13:17:52.338311 [DutyScan_Calibration_Flow] k_type=0
2188 13:17:52.348582
2189 13:17:52.348979 ==CLK 0==
2190 13:17:52.352546 Final CLK duty delay cell = 0
2191 13:17:52.355921 [0] MAX Duty = 5093%(X100), DQS PI = 12
2192 13:17:52.358979 [0] MIN Duty = 4938%(X100), DQS PI = 52
2193 13:17:52.359360 [0] AVG Duty = 5015%(X100)
2194 13:17:52.362512
2195 13:17:52.366098 CH0 CLK Duty spec in!! Max-Min= 155%
2196 13:17:52.368547 [DutyScan_Calibration_Flow] ====Done====
2197 13:17:52.368926
2198 13:17:52.372024 [DutyScan_Calibration_Flow] k_type=1
2199 13:17:52.387960
2200 13:17:52.388408 ==DQS 0 ==
2201 13:17:52.391520 Final DQS duty delay cell = 0
2202 13:17:52.394587 [0] MAX Duty = 5125%(X100), DQS PI = 32
2203 13:17:52.398646 [0] MIN Duty = 5031%(X100), DQS PI = 6
2204 13:17:52.399156 [0] AVG Duty = 5078%(X100)
2205 13:17:52.401685
2206 13:17:52.402067 ==DQS 1 ==
2207 13:17:52.405094 Final DQS duty delay cell = 0
2208 13:17:52.407684 [0] MAX Duty = 5062%(X100), DQS PI = 56
2209 13:17:52.411169 [0] MIN Duty = 4906%(X100), DQS PI = 16
2210 13:17:52.411489 [0] AVG Duty = 4984%(X100)
2211 13:17:52.414320
2212 13:17:52.417877 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2213 13:17:52.418050
2214 13:17:52.421301 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2215 13:17:52.424749 [DutyScan_Calibration_Flow] ====Done====
2216 13:17:52.424912
2217 13:17:52.427531 [DutyScan_Calibration_Flow] k_type=3
2218 13:17:52.444851
2219 13:17:52.444989 ==DQM 0 ==
2220 13:17:52.448061 Final DQM duty delay cell = 0
2221 13:17:52.451866 [0] MAX Duty = 5124%(X100), DQS PI = 20
2222 13:17:52.455026 [0] MIN Duty = 4969%(X100), DQS PI = 40
2223 13:17:52.458326 [0] AVG Duty = 5046%(X100)
2224 13:17:52.458475
2225 13:17:52.458548 ==DQM 1 ==
2226 13:17:52.461722 Final DQM duty delay cell = 4
2227 13:17:52.464862 [4] MAX Duty = 5187%(X100), DQS PI = 54
2228 13:17:52.468820 [4] MIN Duty = 5000%(X100), DQS PI = 18
2229 13:17:52.468898 [4] AVG Duty = 5093%(X100)
2230 13:17:52.472432
2231 13:17:52.474879 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2232 13:17:52.474955
2233 13:17:52.478322 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2234 13:17:52.482342 [DutyScan_Calibration_Flow] ====Done====
2235 13:17:52.482422
2236 13:17:52.484947 [DutyScan_Calibration_Flow] k_type=2
2237 13:17:52.500054
2238 13:17:52.500140 ==DQ 0 ==
2239 13:17:52.503184 Final DQ duty delay cell = -4
2240 13:17:52.506245 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2241 13:17:52.510326 [-4] MIN Duty = 4813%(X100), DQS PI = 6
2242 13:17:52.513064 [-4] AVG Duty = 4937%(X100)
2243 13:17:52.513166
2244 13:17:52.513233 ==DQ 1 ==
2245 13:17:52.517499 Final DQ duty delay cell = -4
2246 13:17:52.520028 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2247 13:17:52.523682 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2248 13:17:52.526357 [-4] AVG Duty = 4969%(X100)
2249 13:17:52.526439
2250 13:17:52.530406 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2251 13:17:52.530490
2252 13:17:52.533038 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2253 13:17:52.536447 [DutyScan_Calibration_Flow] ====Done====
2254 13:17:52.536530 ==
2255 13:17:52.540041 Dram Type= 6, Freq= 0, CH_1, rank 0
2256 13:17:52.542993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2257 13:17:52.543073 ==
2258 13:17:52.546814 [Duty_Offset_Calibration]
2259 13:17:52.546899 B0:0 B1:5 CA:-5
2260 13:17:52.546966
2261 13:17:52.549751 [DutyScan_Calibration_Flow] k_type=0
2262 13:17:52.560705
2263 13:17:52.560796 ==CLK 0==
2264 13:17:52.563689 Final CLK duty delay cell = 0
2265 13:17:52.566771 [0] MAX Duty = 5094%(X100), DQS PI = 24
2266 13:17:52.570822 [0] MIN Duty = 4876%(X100), DQS PI = 52
2267 13:17:52.570915 [0] AVG Duty = 4985%(X100)
2268 13:17:52.574291
2269 13:17:52.577630 CH1 CLK Duty spec in!! Max-Min= 218%
2270 13:17:52.580497 [DutyScan_Calibration_Flow] ====Done====
2271 13:17:52.580600
2272 13:17:52.583773 [DutyScan_Calibration_Flow] k_type=1
2273 13:17:52.599010
2274 13:17:52.599125 ==DQS 0 ==
2275 13:17:52.602350 Final DQS duty delay cell = 0
2276 13:17:52.605499 [0] MAX Duty = 5125%(X100), DQS PI = 14
2277 13:17:52.608812 [0] MIN Duty = 4875%(X100), DQS PI = 40
2278 13:17:52.608914 [0] AVG Duty = 5000%(X100)
2279 13:17:52.612148
2280 13:17:52.612250 ==DQS 1 ==
2281 13:17:52.615429 Final DQS duty delay cell = -4
2282 13:17:52.618859 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2283 13:17:52.622591 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2284 13:17:52.625852 [-4] AVG Duty = 4953%(X100)
2285 13:17:52.625954
2286 13:17:52.628732 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2287 13:17:52.628843
2288 13:17:52.632183 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2289 13:17:52.635727 [DutyScan_Calibration_Flow] ====Done====
2290 13:17:52.635883
2291 13:17:52.639269 [DutyScan_Calibration_Flow] k_type=3
2292 13:17:52.654039
2293 13:17:52.654225 ==DQM 0 ==
2294 13:17:52.657725 Final DQM duty delay cell = -4
2295 13:17:52.661278 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2296 13:17:52.664412 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2297 13:17:52.668190 [-4] AVG Duty = 4984%(X100)
2298 13:17:52.668373
2299 13:17:52.668518 ==DQM 1 ==
2300 13:17:52.671239 Final DQM duty delay cell = -4
2301 13:17:52.674179 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2302 13:17:52.678079 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2303 13:17:52.681129 [-4] AVG Duty = 4984%(X100)
2304 13:17:52.681293
2305 13:17:52.684379 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2306 13:17:52.684530
2307 13:17:52.687797 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2308 13:17:52.691076 [DutyScan_Calibration_Flow] ====Done====
2309 13:17:52.691227
2310 13:17:52.694490 [DutyScan_Calibration_Flow] k_type=2
2311 13:17:52.711382
2312 13:17:52.711654 ==DQ 0 ==
2313 13:17:52.714470 Final DQ duty delay cell = 0
2314 13:17:52.717839 [0] MAX Duty = 5062%(X100), DQS PI = 0
2315 13:17:52.720971 [0] MIN Duty = 4938%(X100), DQS PI = 44
2316 13:17:52.721130 [0] AVG Duty = 5000%(X100)
2317 13:17:52.721269
2318 13:17:52.724736 ==DQ 1 ==
2319 13:17:52.728392 Final DQ duty delay cell = 0
2320 13:17:52.730989 [0] MAX Duty = 5000%(X100), DQS PI = 6
2321 13:17:52.734607 [0] MIN Duty = 4907%(X100), DQS PI = 0
2322 13:17:52.734728 [0] AVG Duty = 4953%(X100)
2323 13:17:52.734823
2324 13:17:52.737445 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2325 13:17:52.737573
2326 13:17:52.741611 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2327 13:17:52.747685 [DutyScan_Calibration_Flow] ====Done====
2328 13:17:52.750643 nWR fixed to 30
2329 13:17:52.750753 [ModeRegInit_LP4] CH0 RK0
2330 13:17:52.754303 [ModeRegInit_LP4] CH0 RK1
2331 13:17:52.757673 [ModeRegInit_LP4] CH1 RK0
2332 13:17:52.757790 [ModeRegInit_LP4] CH1 RK1
2333 13:17:52.761135 match AC timing 6
2334 13:17:52.765136 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2335 13:17:52.767543 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2336 13:17:52.775493 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2337 13:17:52.778398 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2338 13:17:52.784971 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2339 13:17:52.785386 ==
2340 13:17:52.788693 Dram Type= 6, Freq= 0, CH_0, rank 0
2341 13:17:52.791568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2342 13:17:52.791961 ==
2343 13:17:52.798164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2344 13:17:52.801435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2345 13:17:52.811310 [CA 0] Center 39 (9~70) winsize 62
2346 13:17:52.814416 [CA 1] Center 39 (8~70) winsize 63
2347 13:17:52.817429 [CA 2] Center 36 (5~67) winsize 63
2348 13:17:52.821297 [CA 3] Center 35 (4~66) winsize 63
2349 13:17:52.824108 [CA 4] Center 34 (3~65) winsize 63
2350 13:17:52.827762 [CA 5] Center 33 (3~64) winsize 62
2351 13:17:52.827966
2352 13:17:52.831511 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2353 13:17:52.831717
2354 13:17:52.834637 [CATrainingPosCal] consider 1 rank data
2355 13:17:52.837689 u2DelayCellTimex100 = 270/100 ps
2356 13:17:52.840950 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2357 13:17:52.844311 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2358 13:17:52.850581 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2359 13:17:52.854813 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2360 13:17:52.857424 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2361 13:17:52.860996 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2362 13:17:52.861404
2363 13:17:52.864953 CA PerBit enable=1, Macro0, CA PI delay=33
2364 13:17:52.865357
2365 13:17:52.868028 [CBTSetCACLKResult] CA Dly = 33
2366 13:17:52.868348 CS Dly: 7 (0~38)
2367 13:17:52.868593 ==
2368 13:17:52.871362 Dram Type= 6, Freq= 0, CH_0, rank 1
2369 13:17:52.877570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2370 13:17:52.877892 ==
2371 13:17:52.881322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2372 13:17:52.888190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2373 13:17:52.896360 [CA 0] Center 39 (8~70) winsize 63
2374 13:17:52.899595 [CA 1] Center 39 (8~70) winsize 63
2375 13:17:52.903360 [CA 2] Center 36 (5~67) winsize 63
2376 13:17:52.906365 [CA 3] Center 35 (4~66) winsize 63
2377 13:17:52.909858 [CA 4] Center 33 (3~64) winsize 62
2378 13:17:52.913856 [CA 5] Center 33 (3~64) winsize 62
2379 13:17:52.914232
2380 13:17:52.917216 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2381 13:17:52.917613
2382 13:17:52.919827 [CATrainingPosCal] consider 2 rank data
2383 13:17:52.923610 u2DelayCellTimex100 = 270/100 ps
2384 13:17:52.926727 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2385 13:17:52.929716 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2386 13:17:52.936285 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2387 13:17:52.940052 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2388 13:17:52.943577 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2389 13:17:52.946852 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2390 13:17:52.947286
2391 13:17:52.949961 CA PerBit enable=1, Macro0, CA PI delay=33
2392 13:17:52.950422
2393 13:17:52.953149 [CBTSetCACLKResult] CA Dly = 33
2394 13:17:52.953682 CS Dly: 7 (0~39)
2395 13:17:52.954013
2396 13:17:52.956651 ----->DramcWriteLeveling(PI) begin...
2397 13:17:52.960004 ==
2398 13:17:52.963271 Dram Type= 6, Freq= 0, CH_0, rank 0
2399 13:17:52.966382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2400 13:17:52.966908 ==
2401 13:17:52.969956 Write leveling (Byte 0): 27 => 27
2402 13:17:52.973121 Write leveling (Byte 1): 27 => 27
2403 13:17:52.976118 DramcWriteLeveling(PI) end<-----
2404 13:17:52.976498
2405 13:17:52.976789 ==
2406 13:17:52.979993 Dram Type= 6, Freq= 0, CH_0, rank 0
2407 13:17:52.983359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2408 13:17:52.983740 ==
2409 13:17:52.986173 [Gating] SW mode calibration
2410 13:17:52.992841 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2411 13:17:52.996517 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2412 13:17:53.002901 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2413 13:17:53.006229 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2414 13:17:53.009758 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2415 13:17:53.016531 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2416 13:17:53.019925 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2417 13:17:53.023079 0 11 20 | B1->B0 | 2f2f 2c2c | 0 0 | (1 0) (1 0)
2418 13:17:53.030193 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2419 13:17:53.032992 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2420 13:17:53.036316 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2421 13:17:53.043074 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2422 13:17:53.046773 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2423 13:17:53.050192 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2424 13:17:53.056928 0 12 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2425 13:17:53.060367 0 12 20 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
2426 13:17:53.063392 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2427 13:17:53.069808 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2428 13:17:53.072967 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2429 13:17:53.076708 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2430 13:17:53.083507 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2431 13:17:53.086336 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2432 13:17:53.089904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2433 13:17:53.096950 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2434 13:17:53.099824 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2435 13:17:53.103162 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2436 13:17:53.107136 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2437 13:17:53.112881 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2438 13:17:53.116853 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2439 13:17:53.120185 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2440 13:17:53.126200 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2441 13:17:53.130168 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2442 13:17:53.133304 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2443 13:17:53.140226 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2444 13:17:53.143675 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2445 13:17:53.146117 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2446 13:17:53.152977 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2447 13:17:53.156811 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2448 13:17:53.160029 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2449 13:17:53.166333 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2450 13:17:53.169543 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2451 13:17:53.173196 Total UI for P1: 0, mck2ui 16
2452 13:17:53.176641 best dqsien dly found for B0: ( 0, 15, 18)
2453 13:17:53.180285 Total UI for P1: 0, mck2ui 16
2454 13:17:53.183273 best dqsien dly found for B1: ( 0, 15, 18)
2455 13:17:53.186410 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2456 13:17:53.190223 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2457 13:17:53.190611
2458 13:17:53.193195 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2459 13:17:53.196250 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2460 13:17:53.199756 [Gating] SW calibration Done
2461 13:17:53.200262 ==
2462 13:17:53.202800 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 13:17:53.206841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2464 13:17:53.209888 ==
2465 13:17:53.210272 RX Vref Scan: 0
2466 13:17:53.210589
2467 13:17:53.212956 RX Vref 0 -> 0, step: 1
2468 13:17:53.213362
2469 13:17:53.216032 RX Delay -40 -> 252, step: 8
2470 13:17:53.219747 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2471 13:17:53.222994 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2472 13:17:53.226803 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2473 13:17:53.229780 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2474 13:17:53.236457 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2475 13:17:53.239544 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2476 13:17:53.243247 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2477 13:17:53.245910 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2478 13:17:53.249549 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2479 13:17:53.252419 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2480 13:17:53.259624 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2481 13:17:53.262401 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2482 13:17:53.265861 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2483 13:17:53.270215 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2484 13:17:53.272752 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2485 13:17:53.279466 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2486 13:17:53.279893 ==
2487 13:17:53.282540 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 13:17:53.286229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2489 13:17:53.286620 ==
2490 13:17:53.286921 DQS Delay:
2491 13:17:53.290424 DQS0 = 0, DQS1 = 0
2492 13:17:53.290809 DQM Delay:
2493 13:17:53.292735 DQM0 = 115, DQM1 = 105
2494 13:17:53.293119 DQ Delay:
2495 13:17:53.296021 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2496 13:17:53.299774 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2497 13:17:53.302644 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2498 13:17:53.305832 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2499 13:17:53.306214
2500 13:17:53.309351
2501 13:17:53.309777 ==
2502 13:17:53.312610 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 13:17:53.316160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2504 13:17:53.316541 ==
2505 13:17:53.316829
2506 13:17:53.317093
2507 13:17:53.319307 TX Vref Scan disable
2508 13:17:53.319662 == TX Byte 0 ==
2509 13:17:53.322829 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2510 13:17:53.329770 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2511 13:17:53.330199 == TX Byte 1 ==
2512 13:17:53.332723 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2513 13:17:53.339840 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2514 13:17:53.340269 ==
2515 13:17:53.342432 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 13:17:53.345923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2517 13:17:53.346304 ==
2518 13:17:53.358066 TX Vref=22, minBit 9, minWin=25, winSum=416
2519 13:17:53.361094 TX Vref=24, minBit 10, minWin=25, winSum=423
2520 13:17:53.364254 TX Vref=26, minBit 8, minWin=25, winSum=432
2521 13:17:53.368144 TX Vref=28, minBit 8, minWin=26, winSum=431
2522 13:17:53.370891 TX Vref=30, minBit 10, minWin=26, winSum=435
2523 13:17:53.378124 TX Vref=32, minBit 12, minWin=26, winSum=438
2524 13:17:53.381883 [TxChooseVref] Worse bit 12, Min win 26, Win sum 438, Final Vref 32
2525 13:17:53.382331
2526 13:17:53.384850 Final TX Range 1 Vref 32
2527 13:17:53.385263
2528 13:17:53.385580 ==
2529 13:17:53.388270 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 13:17:53.391526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2531 13:17:53.394163 ==
2532 13:17:53.394682
2533 13:17:53.394990
2534 13:17:53.395355 TX Vref Scan disable
2535 13:17:53.397841 == TX Byte 0 ==
2536 13:17:53.401465 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2537 13:17:53.407839 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2538 13:17:53.408326 == TX Byte 1 ==
2539 13:17:53.411649 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2540 13:17:53.418732 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2541 13:17:53.419165
2542 13:17:53.419468 [DATLAT]
2543 13:17:53.419746 Freq=1200, CH0 RK0
2544 13:17:53.420026
2545 13:17:53.420581 DATLAT Default: 0xd
2546 13:17:53.420863 0, 0xFFFF, sum = 0
2547 13:17:53.424800 1, 0xFFFF, sum = 0
2548 13:17:53.427874 2, 0xFFFF, sum = 0
2549 13:17:53.428264 3, 0xFFFF, sum = 0
2550 13:17:53.431461 4, 0xFFFF, sum = 0
2551 13:17:53.431852 5, 0xFFFF, sum = 0
2552 13:17:53.434637 6, 0xFFFF, sum = 0
2553 13:17:53.435026 7, 0xFFFF, sum = 0
2554 13:17:53.437573 8, 0xFFFF, sum = 0
2555 13:17:53.437967 9, 0xFFFF, sum = 0
2556 13:17:53.441187 10, 0xFFFF, sum = 0
2557 13:17:53.441610 11, 0x0, sum = 1
2558 13:17:53.444631 12, 0x0, sum = 2
2559 13:17:53.445023 13, 0x0, sum = 3
2560 13:17:53.445358 14, 0x0, sum = 4
2561 13:17:53.448362 best_step = 12
2562 13:17:53.448806
2563 13:17:53.449111 ==
2564 13:17:53.450979 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 13:17:53.454513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2566 13:17:53.454902 ==
2567 13:17:53.457910 RX Vref Scan: 1
2568 13:17:53.458394
2569 13:17:53.461158 Set Vref Range= 32 -> 127
2570 13:17:53.461574
2571 13:17:53.461871 RX Vref 32 -> 127, step: 1
2572 13:17:53.462146
2573 13:17:53.464371 RX Delay -21 -> 252, step: 4
2574 13:17:53.464755
2575 13:17:53.467919 Set Vref, RX VrefLevel [Byte0]: 32
2576 13:17:53.471111 [Byte1]: 32
2577 13:17:53.474397
2578 13:17:53.474782 Set Vref, RX VrefLevel [Byte0]: 33
2579 13:17:53.478046 [Byte1]: 33
2580 13:17:53.482051
2581 13:17:53.482428 Set Vref, RX VrefLevel [Byte0]: 34
2582 13:17:53.485915 [Byte1]: 34
2583 13:17:53.491240
2584 13:17:53.491749 Set Vref, RX VrefLevel [Byte0]: 35
2585 13:17:53.493599 [Byte1]: 35
2586 13:17:53.498168
2587 13:17:53.498643 Set Vref, RX VrefLevel [Byte0]: 36
2588 13:17:53.501914 [Byte1]: 36
2589 13:17:53.506733
2590 13:17:53.507118 Set Vref, RX VrefLevel [Byte0]: 37
2591 13:17:53.509659 [Byte1]: 37
2592 13:17:53.513795
2593 13:17:53.514182 Set Vref, RX VrefLevel [Byte0]: 38
2594 13:17:53.517507 [Byte1]: 38
2595 13:17:53.521914
2596 13:17:53.522296 Set Vref, RX VrefLevel [Byte0]: 39
2597 13:17:53.526377 [Byte1]: 39
2598 13:17:53.530616
2599 13:17:53.531049 Set Vref, RX VrefLevel [Byte0]: 40
2600 13:17:53.533159 [Byte1]: 40
2601 13:17:53.537975
2602 13:17:53.538369 Set Vref, RX VrefLevel [Byte0]: 41
2603 13:17:53.541180 [Byte1]: 41
2604 13:17:53.545870
2605 13:17:53.546251 Set Vref, RX VrefLevel [Byte0]: 42
2606 13:17:53.550155 [Byte1]: 42
2607 13:17:53.553468
2608 13:17:53.553845 Set Vref, RX VrefLevel [Byte0]: 43
2609 13:17:53.557191 [Byte1]: 43
2610 13:17:53.561624
2611 13:17:53.562001 Set Vref, RX VrefLevel [Byte0]: 44
2612 13:17:53.564900 [Byte1]: 44
2613 13:17:53.570232
2614 13:17:53.570609 Set Vref, RX VrefLevel [Byte0]: 45
2615 13:17:53.573313 [Byte1]: 45
2616 13:17:53.577599
2617 13:17:53.578015 Set Vref, RX VrefLevel [Byte0]: 46
2618 13:17:53.580966 [Byte1]: 46
2619 13:17:53.586430
2620 13:17:53.586809 Set Vref, RX VrefLevel [Byte0]: 47
2621 13:17:53.588722 [Byte1]: 47
2622 13:17:53.593270
2623 13:17:53.593659 Set Vref, RX VrefLevel [Byte0]: 48
2624 13:17:53.596693 [Byte1]: 48
2625 13:17:53.601005
2626 13:17:53.601541 Set Vref, RX VrefLevel [Byte0]: 49
2627 13:17:53.605156 [Byte1]: 49
2628 13:17:53.609385
2629 13:17:53.609763 Set Vref, RX VrefLevel [Byte0]: 50
2630 13:17:53.613547 [Byte1]: 50
2631 13:17:53.617442
2632 13:17:53.617953 Set Vref, RX VrefLevel [Byte0]: 51
2633 13:17:53.620613 [Byte1]: 51
2634 13:17:53.624935
2635 13:17:53.625365 Set Vref, RX VrefLevel [Byte0]: 52
2636 13:17:53.628675 [Byte1]: 52
2637 13:17:53.633021
2638 13:17:53.633443 Set Vref, RX VrefLevel [Byte0]: 53
2639 13:17:53.636262 [Byte1]: 53
2640 13:17:53.640676
2641 13:17:53.641057 Set Vref, RX VrefLevel [Byte0]: 54
2642 13:17:53.644177 [Byte1]: 54
2643 13:17:53.649368
2644 13:17:53.649792 Set Vref, RX VrefLevel [Byte0]: 55
2645 13:17:53.652006 [Byte1]: 55
2646 13:17:53.656919
2647 13:17:53.657377 Set Vref, RX VrefLevel [Byte0]: 56
2648 13:17:53.660445 [Byte1]: 56
2649 13:17:53.665021
2650 13:17:53.665480 Set Vref, RX VrefLevel [Byte0]: 57
2651 13:17:53.668283 [Byte1]: 57
2652 13:17:53.672860
2653 13:17:53.673317 Set Vref, RX VrefLevel [Byte0]: 58
2654 13:17:53.675568 [Byte1]: 58
2655 13:17:53.680498
2656 13:17:53.680966 Set Vref, RX VrefLevel [Byte0]: 59
2657 13:17:53.683971 [Byte1]: 59
2658 13:17:53.688926
2659 13:17:53.689453 Set Vref, RX VrefLevel [Byte0]: 60
2660 13:17:53.692141 [Byte1]: 60
2661 13:17:53.696281
2662 13:17:53.696769 Set Vref, RX VrefLevel [Byte0]: 61
2663 13:17:53.700406 [Byte1]: 61
2664 13:17:53.705020
2665 13:17:53.705496 Set Vref, RX VrefLevel [Byte0]: 62
2666 13:17:53.707807 [Byte1]: 62
2667 13:17:53.712049
2668 13:17:53.712520 Set Vref, RX VrefLevel [Byte0]: 63
2669 13:17:53.715784 [Byte1]: 63
2670 13:17:53.720126
2671 13:17:53.720544 Set Vref, RX VrefLevel [Byte0]: 64
2672 13:17:53.723914 [Byte1]: 64
2673 13:17:53.728433
2674 13:17:53.728892 Set Vref, RX VrefLevel [Byte0]: 65
2675 13:17:53.731246 [Byte1]: 65
2676 13:17:53.736436
2677 13:17:53.736942 Set Vref, RX VrefLevel [Byte0]: 66
2678 13:17:53.739138 [Byte1]: 66
2679 13:17:53.744213
2680 13:17:53.744763 Set Vref, RX VrefLevel [Byte0]: 67
2681 13:17:53.747793 [Byte1]: 67
2682 13:17:53.751473
2683 13:17:53.752052 Set Vref, RX VrefLevel [Byte0]: 68
2684 13:17:53.755651 [Byte1]: 68
2685 13:17:53.759451
2686 13:17:53.760070 Final RX Vref Byte 0 = 48 to rank0
2687 13:17:53.763205 Final RX Vref Byte 1 = 50 to rank0
2688 13:17:53.766133 Final RX Vref Byte 0 = 48 to rank1
2689 13:17:53.769777 Final RX Vref Byte 1 = 50 to rank1==
2690 13:17:53.773137 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 13:17:53.779518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2692 13:17:53.779997 ==
2693 13:17:53.780327 DQS Delay:
2694 13:17:53.780632 DQS0 = 0, DQS1 = 0
2695 13:17:53.783572 DQM Delay:
2696 13:17:53.783995 DQM0 = 114, DQM1 = 105
2697 13:17:53.786329 DQ Delay:
2698 13:17:53.790060 DQ0 =110, DQ1 =116, DQ2 =110, DQ3 =110
2699 13:17:53.792915 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2700 13:17:53.797143 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2701 13:17:53.799705 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2702 13:17:53.800195
2703 13:17:53.800518
2704 13:17:53.806788 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2705 13:17:53.810036 CH0 RK0: MR19=404, MR18=E0E
2706 13:17:53.816503 CH0_RK0: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2707 13:17:53.816886
2708 13:17:53.819439 ----->DramcWriteLeveling(PI) begin...
2709 13:17:53.819925 ==
2710 13:17:53.823026 Dram Type= 6, Freq= 0, CH_0, rank 1
2711 13:17:53.826193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2712 13:17:53.826575 ==
2713 13:17:53.829897 Write leveling (Byte 0): 27 => 27
2714 13:17:53.832782 Write leveling (Byte 1): 25 => 25
2715 13:17:53.836165 DramcWriteLeveling(PI) end<-----
2716 13:17:53.836540
2717 13:17:53.836833 ==
2718 13:17:53.839476 Dram Type= 6, Freq= 0, CH_0, rank 1
2719 13:17:53.844069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2720 13:17:53.846276 ==
2721 13:17:53.846658 [Gating] SW mode calibration
2722 13:17:53.856005 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2723 13:17:53.859543 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2724 13:17:53.862769 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2725 13:17:53.869799 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2726 13:17:53.873158 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2727 13:17:53.876299 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2728 13:17:53.883703 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2729 13:17:53.885994 0 11 20 | B1->B0 | 3030 2525 | 0 1 | (1 0) (1 0)
2730 13:17:53.889667 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2731 13:17:53.896159 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2732 13:17:53.899845 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2733 13:17:53.903624 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2734 13:17:53.909508 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2735 13:17:53.912770 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2736 13:17:53.916036 0 12 16 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
2737 13:17:53.923404 0 12 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2738 13:17:53.926450 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2739 13:17:53.929349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2740 13:17:53.932711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2741 13:17:53.939392 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2742 13:17:53.942668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2743 13:17:53.945852 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2744 13:17:53.952509 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2745 13:17:53.956055 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2746 13:17:53.959411 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2747 13:17:53.966362 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2748 13:17:53.969476 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2749 13:17:53.972782 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2750 13:17:53.979551 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2751 13:17:53.983198 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2752 13:17:53.986476 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2753 13:17:53.993150 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2754 13:17:53.996210 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2755 13:17:54.000342 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2756 13:17:54.006526 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2757 13:17:54.009593 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2758 13:17:54.013314 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2759 13:17:54.019360 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2760 13:17:54.022736 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2761 13:17:54.026604 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2762 13:17:54.032969 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 13:17:54.033521 Total UI for P1: 0, mck2ui 16
2764 13:17:54.036378 best dqsien dly found for B0: ( 0, 15, 18)
2765 13:17:54.039408 Total UI for P1: 0, mck2ui 16
2766 13:17:54.043158 best dqsien dly found for B1: ( 0, 15, 18)
2767 13:17:54.046131 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2768 13:17:54.053145 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2769 13:17:54.053723
2770 13:17:54.056413 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2771 13:17:54.059498 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2772 13:17:54.063174 [Gating] SW calibration Done
2773 13:17:54.063597 ==
2774 13:17:54.066071 Dram Type= 6, Freq= 0, CH_0, rank 1
2775 13:17:54.069831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2776 13:17:54.070330 ==
2777 13:17:54.070657 RX Vref Scan: 0
2778 13:17:54.072664
2779 13:17:54.073155 RX Vref 0 -> 0, step: 1
2780 13:17:54.073684
2781 13:17:54.075830 RX Delay -40 -> 252, step: 8
2782 13:17:54.079780 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2783 13:17:54.082699 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2784 13:17:54.089561 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2785 13:17:54.093094 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2786 13:17:54.096172 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2787 13:17:54.099172 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2788 13:17:54.102942 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2789 13:17:54.109460 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2790 13:17:54.112772 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2791 13:17:54.116401 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2792 13:17:54.119147 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2793 13:17:54.123070 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2794 13:17:54.129199 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2795 13:17:54.133418 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2796 13:17:54.136017 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2797 13:17:54.139153 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2798 13:17:54.139577 ==
2799 13:17:54.142792 Dram Type= 6, Freq= 0, CH_0, rank 1
2800 13:17:54.149411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2801 13:17:54.149838 ==
2802 13:17:54.150164 DQS Delay:
2803 13:17:54.150468 DQS0 = 0, DQS1 = 0
2804 13:17:54.152755 DQM Delay:
2805 13:17:54.153176 DQM0 = 114, DQM1 = 107
2806 13:17:54.156452 DQ Delay:
2807 13:17:54.159465 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2808 13:17:54.162478 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2809 13:17:54.165759 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2810 13:17:54.169709 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =115
2811 13:17:54.170110
2812 13:17:54.170468
2813 13:17:54.170744 ==
2814 13:17:54.172854 Dram Type= 6, Freq= 0, CH_0, rank 1
2815 13:17:54.175719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2816 13:17:54.176108 ==
2817 13:17:54.176403
2818 13:17:54.176717
2819 13:17:54.179373 TX Vref Scan disable
2820 13:17:54.182571 == TX Byte 0 ==
2821 13:17:54.185721 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2822 13:17:54.189466 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2823 13:17:54.192997 == TX Byte 1 ==
2824 13:17:54.195884 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2825 13:17:54.199911 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2826 13:17:54.200350 ==
2827 13:17:54.202586 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 13:17:54.209184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2829 13:17:54.209639 ==
2830 13:17:54.219931 TX Vref=22, minBit 8, minWin=25, winSum=419
2831 13:17:54.222891 TX Vref=24, minBit 9, minWin=25, winSum=420
2832 13:17:54.226649 TX Vref=26, minBit 1, minWin=26, winSum=431
2833 13:17:54.230065 TX Vref=28, minBit 1, minWin=26, winSum=425
2834 13:17:54.233026 TX Vref=30, minBit 10, minWin=26, winSum=430
2835 13:17:54.239993 TX Vref=32, minBit 5, minWin=26, winSum=431
2836 13:17:54.243323 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 26
2837 13:17:54.243756
2838 13:17:54.246088 Final TX Range 1 Vref 26
2839 13:17:54.246514
2840 13:17:54.246840 ==
2841 13:17:54.249418 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 13:17:54.254193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2843 13:17:54.254578 ==
2844 13:17:54.254873
2845 13:17:54.255981
2846 13:17:54.256362 TX Vref Scan disable
2847 13:17:54.260016 == TX Byte 0 ==
2848 13:17:54.262896 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2849 13:17:54.266492 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2850 13:17:54.269819 == TX Byte 1 ==
2851 13:17:54.272818 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2852 13:17:54.276699 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2853 13:17:54.277079
2854 13:17:54.280506 [DATLAT]
2855 13:17:54.280995 Freq=1200, CH0 RK1
2856 13:17:54.281540
2857 13:17:54.282873 DATLAT Default: 0xc
2858 13:17:54.283253 0, 0xFFFF, sum = 0
2859 13:17:54.286129 1, 0xFFFF, sum = 0
2860 13:17:54.286520 2, 0xFFFF, sum = 0
2861 13:17:54.289850 3, 0xFFFF, sum = 0
2862 13:17:54.290318 4, 0xFFFF, sum = 0
2863 13:17:54.293026 5, 0xFFFF, sum = 0
2864 13:17:54.293438 6, 0xFFFF, sum = 0
2865 13:17:54.296674 7, 0xFFFF, sum = 0
2866 13:17:54.300336 8, 0xFFFF, sum = 0
2867 13:17:54.300812 9, 0xFFFF, sum = 0
2868 13:17:54.302728 10, 0xFFFF, sum = 0
2869 13:17:54.303116 11, 0x0, sum = 1
2870 13:17:54.306518 12, 0x0, sum = 2
2871 13:17:54.306905 13, 0x0, sum = 3
2872 13:17:54.307207 14, 0x0, sum = 4
2873 13:17:54.309735 best_step = 12
2874 13:17:54.310115
2875 13:17:54.310509 ==
2876 13:17:54.312853 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 13:17:54.316373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2878 13:17:54.316853 ==
2879 13:17:54.319594 RX Vref Scan: 0
2880 13:17:54.319990
2881 13:17:54.320285 RX Vref 0 -> 0, step: 1
2882 13:17:54.320562
2883 13:17:54.322833 RX Delay -21 -> 252, step: 4
2884 13:17:54.330164 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2885 13:17:54.333219 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2886 13:17:54.337138 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2887 13:17:54.339854 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2888 13:17:54.343562 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2889 13:17:54.349948 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2890 13:17:54.354465 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2891 13:17:54.356348 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2892 13:17:54.360058 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2893 13:17:54.363157 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2894 13:17:54.370468 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2895 13:17:54.373403 iDelay=199, Bit 11, Center 98 (39 ~ 158) 120
2896 13:17:54.376416 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2897 13:17:54.379868 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2898 13:17:54.383376 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2899 13:17:54.390101 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2900 13:17:54.390607 ==
2901 13:17:54.393856 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 13:17:54.397067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2903 13:17:54.397700 ==
2904 13:17:54.398032 DQS Delay:
2905 13:17:54.399736 DQS0 = 0, DQS1 = 0
2906 13:17:54.400115 DQM Delay:
2907 13:17:54.404000 DQM0 = 115, DQM1 = 106
2908 13:17:54.404428 DQ Delay:
2909 13:17:54.406710 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2910 13:17:54.410246 DQ4 =116, DQ5 =108, DQ6 =124, DQ7 =124
2911 13:17:54.413476 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =98
2912 13:17:54.416866 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2913 13:17:54.417420
2914 13:17:54.417756
2915 13:17:54.427181 [DQSOSCAuto] RK1, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
2916 13:17:54.430561 CH0 RK1: MR19=404, MR18=1515
2917 13:17:54.433434 CH0_RK1: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
2918 13:17:54.436745 [RxdqsGatingPostProcess] freq 1200
2919 13:17:54.443940 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2920 13:17:54.446991 Pre-setting of DQS Precalculation
2921 13:17:54.450382 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2922 13:17:54.450830 ==
2923 13:17:54.454223 Dram Type= 6, Freq= 0, CH_1, rank 0
2924 13:17:54.460449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2925 13:17:54.460879 ==
2926 13:17:54.465288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2927 13:17:54.470242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2928 13:17:54.479130 [CA 0] Center 37 (7~68) winsize 62
2929 13:17:54.482238 [CA 1] Center 37 (7~68) winsize 62
2930 13:17:54.485269 [CA 2] Center 34 (4~65) winsize 62
2931 13:17:54.489342 [CA 3] Center 34 (4~64) winsize 61
2932 13:17:54.492008 [CA 4] Center 32 (2~63) winsize 62
2933 13:17:54.495379 [CA 5] Center 32 (2~63) winsize 62
2934 13:17:54.495891
2935 13:17:54.499176 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2936 13:17:54.499667
2937 13:17:54.502174 [CATrainingPosCal] consider 1 rank data
2938 13:17:54.505120 u2DelayCellTimex100 = 270/100 ps
2939 13:17:54.508765 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2940 13:17:54.512230 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2941 13:17:54.518402 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2942 13:17:54.522052 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2943 13:17:54.525112 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2944 13:17:54.528876 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2945 13:17:54.529350
2946 13:17:54.532380 CA PerBit enable=1, Macro0, CA PI delay=32
2947 13:17:54.532873
2948 13:17:54.535147 [CBTSetCACLKResult] CA Dly = 32
2949 13:17:54.535708 CS Dly: 6 (0~37)
2950 13:17:54.536049 ==
2951 13:17:54.539321 Dram Type= 6, Freq= 0, CH_1, rank 1
2952 13:17:54.545317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2953 13:17:54.545777 ==
2954 13:17:54.548384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2955 13:17:54.555527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2956 13:17:54.563812 [CA 0] Center 37 (7~68) winsize 62
2957 13:17:54.567150 [CA 1] Center 37 (7~68) winsize 62
2958 13:17:54.571817 [CA 2] Center 34 (3~65) winsize 63
2959 13:17:54.574282 [CA 3] Center 33 (3~64) winsize 62
2960 13:17:54.577174 [CA 4] Center 32 (2~63) winsize 62
2961 13:17:54.581196 [CA 5] Center 32 (1~63) winsize 63
2962 13:17:54.581671
2963 13:17:54.583677 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2964 13:17:54.584102
2965 13:17:54.587450 [CATrainingPosCal] consider 2 rank data
2966 13:17:54.590895 u2DelayCellTimex100 = 270/100 ps
2967 13:17:54.593871 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2968 13:17:54.597939 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2969 13:17:54.603866 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2970 13:17:54.606969 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2971 13:17:54.610638 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2972 13:17:54.613917 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2973 13:17:54.614343
2974 13:17:54.617378 CA PerBit enable=1, Macro0, CA PI delay=32
2975 13:17:54.617808
2976 13:17:54.621197 [CBTSetCACLKResult] CA Dly = 32
2977 13:17:54.621675 CS Dly: 6 (0~38)
2978 13:17:54.622081
2979 13:17:54.624361 ----->DramcWriteLeveling(PI) begin...
2980 13:17:54.627637 ==
2981 13:17:54.628070 Dram Type= 6, Freq= 0, CH_1, rank 0
2982 13:17:54.634065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2983 13:17:54.634537 ==
2984 13:17:54.637045 Write leveling (Byte 0): 23 => 23
2985 13:17:54.640850 Write leveling (Byte 1): 22 => 22
2986 13:17:54.644148 DramcWriteLeveling(PI) end<-----
2987 13:17:54.644578
2988 13:17:54.644955 ==
2989 13:17:54.646816 Dram Type= 6, Freq= 0, CH_1, rank 0
2990 13:17:54.650530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2991 13:17:54.651002 ==
2992 13:17:54.653802 [Gating] SW mode calibration
2993 13:17:54.660351 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2994 13:17:54.663956 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2995 13:17:54.670673 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2996 13:17:54.674161 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2997 13:17:54.677383 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2998 13:17:54.684000 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2999 13:17:54.687936 0 11 16 | B1->B0 | 3333 2626 | 0 0 | (0 0) (1 0)
3000 13:17:54.690296 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3001 13:17:54.697506 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3002 13:17:54.700370 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3003 13:17:54.704080 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3004 13:17:54.710760 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3005 13:17:54.714021 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3006 13:17:54.717401 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3007 13:17:54.724192 0 12 16 | B1->B0 | 2e2e 3e3e | 0 0 | (0 0) (0 0)
3008 13:17:54.727164 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3009 13:17:54.730743 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3010 13:17:54.734684 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3011 13:17:54.740799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3012 13:17:54.743990 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3013 13:17:54.747951 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3014 13:17:54.753611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3015 13:17:54.757350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3016 13:17:54.760927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3017 13:17:54.767071 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3018 13:17:54.770735 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3019 13:17:54.773598 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3020 13:17:54.780482 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3021 13:17:54.784192 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3022 13:17:54.787259 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3023 13:17:54.793803 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3024 13:17:54.797380 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3025 13:17:54.800476 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3026 13:17:54.806988 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3027 13:17:54.810458 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3028 13:17:54.813713 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3029 13:17:54.820462 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3030 13:17:54.823866 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3031 13:17:54.828017 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3032 13:17:54.830335 Total UI for P1: 0, mck2ui 16
3033 13:17:54.833561 best dqsien dly found for B0: ( 0, 15, 14)
3034 13:17:54.837204 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3035 13:17:54.844009 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 13:17:54.847001 Total UI for P1: 0, mck2ui 16
3037 13:17:54.850346 best dqsien dly found for B1: ( 0, 15, 18)
3038 13:17:54.854661 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3039 13:17:54.857461 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3040 13:17:54.857963
3041 13:17:54.860832 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3042 13:17:54.863777 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3043 13:17:54.867973 [Gating] SW calibration Done
3044 13:17:54.868394 ==
3045 13:17:54.871232 Dram Type= 6, Freq= 0, CH_1, rank 0
3046 13:17:54.873975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3047 13:17:54.874404 ==
3048 13:17:54.877554 RX Vref Scan: 0
3049 13:17:54.878051
3050 13:17:54.881026 RX Vref 0 -> 0, step: 1
3051 13:17:54.881605
3052 13:17:54.881990 RX Delay -40 -> 252, step: 8
3053 13:17:54.887326 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3054 13:17:54.891121 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3055 13:17:54.893817 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3056 13:17:54.897774 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3057 13:17:54.900187 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3058 13:17:54.907626 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3059 13:17:54.910569 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3060 13:17:54.914226 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3061 13:17:54.916953 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3062 13:17:54.920276 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3063 13:17:54.927631 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3064 13:17:54.930417 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3065 13:17:54.934052 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3066 13:17:54.937035 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3067 13:17:54.940799 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3068 13:17:54.947280 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3069 13:17:54.947702 ==
3070 13:17:54.950285 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 13:17:54.953886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3072 13:17:54.954308 ==
3073 13:17:54.954633 DQS Delay:
3074 13:17:54.956814 DQS0 = 0, DQS1 = 0
3075 13:17:54.957441 DQM Delay:
3076 13:17:54.960367 DQM0 = 116, DQM1 = 108
3077 13:17:54.960789 DQ Delay:
3078 13:17:54.963647 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3079 13:17:54.966969 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3080 13:17:54.970121 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3081 13:17:54.974189 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3082 13:17:54.974744
3083 13:17:54.975227
3084 13:17:54.975725 ==
3085 13:17:54.976469 Dram Type= 6, Freq= 0, CH_1, rank 0
3086 13:17:54.983436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3087 13:17:54.983880 ==
3088 13:17:54.984211
3089 13:17:54.984511
3090 13:17:54.984793 TX Vref Scan disable
3091 13:17:54.987766 == TX Byte 0 ==
3092 13:17:54.990881 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3093 13:17:54.997966 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3094 13:17:54.998389 == TX Byte 1 ==
3095 13:17:55.000580 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3096 13:17:55.007408 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3097 13:17:55.007788 ==
3098 13:17:55.010321 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 13:17:55.014150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3100 13:17:55.014542 ==
3101 13:17:55.025219 TX Vref=22, minBit 8, minWin=25, winSum=418
3102 13:17:55.028256 TX Vref=24, minBit 11, minWin=25, winSum=426
3103 13:17:55.031792 TX Vref=26, minBit 8, minWin=26, winSum=432
3104 13:17:55.035692 TX Vref=28, minBit 8, minWin=26, winSum=437
3105 13:17:55.038388 TX Vref=30, minBit 11, minWin=26, winSum=434
3106 13:17:55.044592 TX Vref=32, minBit 9, minWin=26, winSum=433
3107 13:17:55.048626 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 28
3108 13:17:55.049015
3109 13:17:55.051586 Final TX Range 1 Vref 28
3110 13:17:55.051976
3111 13:17:55.052273 ==
3112 13:17:55.054641 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 13:17:55.057905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3114 13:17:55.058295 ==
3115 13:17:55.061695
3116 13:17:55.062083
3117 13:17:55.062381 TX Vref Scan disable
3118 13:17:55.065048 == TX Byte 0 ==
3119 13:17:55.067984 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3120 13:17:55.074354 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3121 13:17:55.074955 == TX Byte 1 ==
3122 13:17:55.077947 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3123 13:17:55.084533 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3124 13:17:55.084921
3125 13:17:55.085220 [DATLAT]
3126 13:17:55.085564 Freq=1200, CH1 RK0
3127 13:17:55.085834
3128 13:17:55.087900 DATLAT Default: 0xd
3129 13:17:55.088323 0, 0xFFFF, sum = 0
3130 13:17:55.091775 1, 0xFFFF, sum = 0
3131 13:17:55.092198 2, 0xFFFF, sum = 0
3132 13:17:55.094304 3, 0xFFFF, sum = 0
3133 13:17:55.097751 4, 0xFFFF, sum = 0
3134 13:17:55.098154 5, 0xFFFF, sum = 0
3135 13:17:55.101527 6, 0xFFFF, sum = 0
3136 13:17:55.101928 7, 0xFFFF, sum = 0
3137 13:17:55.104304 8, 0xFFFF, sum = 0
3138 13:17:55.104691 9, 0xFFFF, sum = 0
3139 13:17:55.108308 10, 0xFFFF, sum = 0
3140 13:17:55.109012 11, 0x0, sum = 1
3141 13:17:55.111199 12, 0x0, sum = 2
3142 13:17:55.111583 13, 0x0, sum = 3
3143 13:17:55.114246 14, 0x0, sum = 4
3144 13:17:55.114634 best_step = 12
3145 13:17:55.115206
3146 13:17:55.115731 ==
3147 13:17:55.118291 Dram Type= 6, Freq= 0, CH_1, rank 0
3148 13:17:55.122002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3149 13:17:55.122386 ==
3150 13:17:55.124719 RX Vref Scan: 1
3151 13:17:55.125099
3152 13:17:55.127868 Set Vref Range= 32 -> 127
3153 13:17:55.128292
3154 13:17:55.128588 RX Vref 32 -> 127, step: 1
3155 13:17:55.128864
3156 13:17:55.131064 RX Delay -29 -> 252, step: 4
3157 13:17:55.131449
3158 13:17:55.134168 Set Vref, RX VrefLevel [Byte0]: 32
3159 13:17:55.137729 [Byte1]: 32
3160 13:17:55.141600
3161 13:17:55.142001 Set Vref, RX VrefLevel [Byte0]: 33
3162 13:17:55.144702 [Byte1]: 33
3163 13:17:55.149399
3164 13:17:55.149821 Set Vref, RX VrefLevel [Byte0]: 34
3165 13:17:55.152468 [Byte1]: 34
3166 13:17:55.157497
3167 13:17:55.157873 Set Vref, RX VrefLevel [Byte0]: 35
3168 13:17:55.160682 [Byte1]: 35
3169 13:17:55.165740
3170 13:17:55.166134 Set Vref, RX VrefLevel [Byte0]: 36
3171 13:17:55.168362 [Byte1]: 36
3172 13:17:55.173845
3173 13:17:55.174222 Set Vref, RX VrefLevel [Byte0]: 37
3174 13:17:55.176735 [Byte1]: 37
3175 13:17:55.181204
3176 13:17:55.181735 Set Vref, RX VrefLevel [Byte0]: 38
3177 13:17:55.184368 [Byte1]: 38
3178 13:17:55.188989
3179 13:17:55.189539 Set Vref, RX VrefLevel [Byte0]: 39
3180 13:17:55.192794 [Byte1]: 39
3181 13:17:55.197507
3182 13:17:55.197893 Set Vref, RX VrefLevel [Byte0]: 40
3183 13:17:55.200940 [Byte1]: 40
3184 13:17:55.205100
3185 13:17:55.205532 Set Vref, RX VrefLevel [Byte0]: 41
3186 13:17:55.208224 [Byte1]: 41
3187 13:17:55.212741
3188 13:17:55.213257 Set Vref, RX VrefLevel [Byte0]: 42
3189 13:17:55.216536 [Byte1]: 42
3190 13:17:55.221410
3191 13:17:55.221786 Set Vref, RX VrefLevel [Byte0]: 43
3192 13:17:55.223983 [Byte1]: 43
3193 13:17:55.229421
3194 13:17:55.229888 Set Vref, RX VrefLevel [Byte0]: 44
3195 13:17:55.232354 [Byte1]: 44
3196 13:17:55.236856
3197 13:17:55.240153 Set Vref, RX VrefLevel [Byte0]: 45
3198 13:17:55.243510 [Byte1]: 45
3199 13:17:55.243893
3200 13:17:55.246948 Set Vref, RX VrefLevel [Byte0]: 46
3201 13:17:55.250381 [Byte1]: 46
3202 13:17:55.250768
3203 13:17:55.254313 Set Vref, RX VrefLevel [Byte0]: 47
3204 13:17:55.256697 [Byte1]: 47
3205 13:17:55.261674
3206 13:17:55.262057 Set Vref, RX VrefLevel [Byte0]: 48
3207 13:17:55.264286 [Byte1]: 48
3208 13:17:55.268837
3209 13:17:55.269221 Set Vref, RX VrefLevel [Byte0]: 49
3210 13:17:55.271890 [Byte1]: 49
3211 13:17:55.276672
3212 13:17:55.277053 Set Vref, RX VrefLevel [Byte0]: 50
3213 13:17:55.279719 [Byte1]: 50
3214 13:17:55.285527
3215 13:17:55.285909 Set Vref, RX VrefLevel [Byte0]: 51
3216 13:17:55.287963 [Byte1]: 51
3217 13:17:55.293320
3218 13:17:55.293744 Set Vref, RX VrefLevel [Byte0]: 52
3219 13:17:55.296471 [Byte1]: 52
3220 13:17:55.301052
3221 13:17:55.301487 Set Vref, RX VrefLevel [Byte0]: 53
3222 13:17:55.303894 [Byte1]: 53
3223 13:17:55.308274
3224 13:17:55.308694 Set Vref, RX VrefLevel [Byte0]: 54
3225 13:17:55.311617 [Byte1]: 54
3226 13:17:55.316280
3227 13:17:55.316700 Set Vref, RX VrefLevel [Byte0]: 55
3228 13:17:55.320046 [Byte1]: 55
3229 13:17:55.324684
3230 13:17:55.325103 Set Vref, RX VrefLevel [Byte0]: 56
3231 13:17:55.327845 [Byte1]: 56
3232 13:17:55.333293
3233 13:17:55.335601 Set Vref, RX VrefLevel [Byte0]: 57
3234 13:17:55.336124 [Byte1]: 57
3235 13:17:55.341108
3236 13:17:55.341527 Set Vref, RX VrefLevel [Byte0]: 58
3237 13:17:55.344042 [Byte1]: 58
3238 13:17:55.348176
3239 13:17:55.348560 Set Vref, RX VrefLevel [Byte0]: 59
3240 13:17:55.351277 [Byte1]: 59
3241 13:17:55.356523
3242 13:17:55.356950 Set Vref, RX VrefLevel [Byte0]: 60
3243 13:17:55.359406 [Byte1]: 60
3244 13:17:55.364154
3245 13:17:55.364578 Set Vref, RX VrefLevel [Byte0]: 61
3246 13:17:55.367762 [Byte1]: 61
3247 13:17:55.372191
3248 13:17:55.372612 Set Vref, RX VrefLevel [Byte0]: 62
3249 13:17:55.375569 [Byte1]: 62
3250 13:17:55.380509
3251 13:17:55.380960 Set Vref, RX VrefLevel [Byte0]: 63
3252 13:17:55.383338 [Byte1]: 63
3253 13:17:55.389047
3254 13:17:55.389654 Set Vref, RX VrefLevel [Byte0]: 64
3255 13:17:55.392205 [Byte1]: 64
3256 13:17:55.396073
3257 13:17:55.396547 Set Vref, RX VrefLevel [Byte0]: 65
3258 13:17:55.399296 [Byte1]: 65
3259 13:17:55.404225
3260 13:17:55.404643 Final RX Vref Byte 0 = 55 to rank0
3261 13:17:55.407330 Final RX Vref Byte 1 = 49 to rank0
3262 13:17:55.410490 Final RX Vref Byte 0 = 55 to rank1
3263 13:17:55.414008 Final RX Vref Byte 1 = 49 to rank1==
3264 13:17:55.417320 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 13:17:55.423759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3266 13:17:55.424191 ==
3267 13:17:55.424519 DQS Delay:
3268 13:17:55.427854 DQS0 = 0, DQS1 = 0
3269 13:17:55.428321 DQM Delay:
3270 13:17:55.428650 DQM0 = 115, DQM1 = 106
3271 13:17:55.431807 DQ Delay:
3272 13:17:55.434064 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3273 13:17:55.437067 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3274 13:17:55.440745 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =98
3275 13:17:55.444058 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3276 13:17:55.444476
3277 13:17:55.444804
3278 13:17:55.450642 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3279 13:17:55.453354 CH1 RK0: MR19=404, MR18=1B1B
3280 13:17:55.460429 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3281 13:17:55.460899
3282 13:17:55.464095 ----->DramcWriteLeveling(PI) begin...
3283 13:17:55.464575 ==
3284 13:17:55.466885 Dram Type= 6, Freq= 0, CH_1, rank 1
3285 13:17:55.473918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3286 13:17:55.474425 ==
3287 13:17:55.476830 Write leveling (Byte 0): 20 => 20
3288 13:17:55.477287 Write leveling (Byte 1): 23 => 23
3289 13:17:55.480704 DramcWriteLeveling(PI) end<-----
3290 13:17:55.481173
3291 13:17:55.481563 ==
3292 13:17:55.483433 Dram Type= 6, Freq= 0, CH_1, rank 1
3293 13:17:55.490321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3294 13:17:55.490900 ==
3295 13:17:55.493938 [Gating] SW mode calibration
3296 13:17:55.500459 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3297 13:17:55.504193 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3298 13:17:55.510124 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3299 13:17:55.513816 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3300 13:17:55.517045 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3301 13:17:55.523538 0 11 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
3302 13:17:55.527059 0 11 16 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
3303 13:17:55.530038 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3304 13:17:55.536637 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3305 13:17:55.540380 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3306 13:17:55.543627 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3307 13:17:55.549827 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3308 13:17:55.553031 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3309 13:17:55.556488 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3310 13:17:55.562903 0 12 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3311 13:17:55.566732 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3312 13:17:55.569725 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3313 13:17:55.573671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3314 13:17:55.580355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3315 13:17:55.583825 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3316 13:17:55.586037 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3317 13:17:55.592867 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3318 13:17:55.596068 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3319 13:17:55.599725 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3320 13:17:55.605824 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3321 13:17:55.609167 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3322 13:17:55.612919 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3323 13:17:55.619880 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3324 13:17:55.622829 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3325 13:17:55.626163 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3326 13:17:55.632713 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3327 13:17:55.636205 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3328 13:17:55.639345 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3329 13:17:55.645808 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3330 13:17:55.648980 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3331 13:17:55.653333 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3332 13:17:55.659269 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3333 13:17:55.662049 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3334 13:17:55.665478 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3335 13:17:55.669354 Total UI for P1: 0, mck2ui 16
3336 13:17:55.672304 best dqsien dly found for B0: ( 0, 15, 12)
3337 13:17:55.678671 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3338 13:17:55.681878 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 13:17:55.685656 Total UI for P1: 0, mck2ui 16
3340 13:17:55.688781 best dqsien dly found for B1: ( 0, 15, 16)
3341 13:17:55.691957 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3342 13:17:55.695712 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3343 13:17:55.696092
3344 13:17:55.698407 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3345 13:17:55.704845 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3346 13:17:55.705209 [Gating] SW calibration Done
3347 13:17:55.705572 ==
3348 13:17:55.708861 Dram Type= 6, Freq= 0, CH_1, rank 1
3349 13:17:55.715022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3350 13:17:55.715375 ==
3351 13:17:55.715600 RX Vref Scan: 0
3352 13:17:55.715798
3353 13:17:55.718148 RX Vref 0 -> 0, step: 1
3354 13:17:55.718417
3355 13:17:55.721299 RX Delay -40 -> 252, step: 8
3356 13:17:55.724965 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3357 13:17:55.728470 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3358 13:17:55.731742 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3359 13:17:55.738687 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3360 13:17:55.741602 iDelay=208, Bit 4, Center 119 (48 ~ 191) 144
3361 13:17:55.745605 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3362 13:17:55.748091 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3363 13:17:55.751683 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3364 13:17:55.754746 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3365 13:17:55.761892 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3366 13:17:55.764676 iDelay=208, Bit 10, Center 103 (32 ~ 175) 144
3367 13:17:55.768326 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3368 13:17:55.771344 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3369 13:17:55.778154 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3370 13:17:55.781072 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3371 13:17:55.784574 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
3372 13:17:55.785008 ==
3373 13:17:55.787849 Dram Type= 6, Freq= 0, CH_1, rank 1
3374 13:17:55.791751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3375 13:17:55.792186 ==
3376 13:17:55.794211 DQS Delay:
3377 13:17:55.794593 DQS0 = 0, DQS1 = 0
3378 13:17:55.797651 DQM Delay:
3379 13:17:55.798075 DQM0 = 117, DQM1 = 106
3380 13:17:55.800851 DQ Delay:
3381 13:17:55.804545 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3382 13:17:55.808335 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =115
3383 13:17:55.811659 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3384 13:17:55.814138 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3385 13:17:55.814554
3386 13:17:55.814874
3387 13:17:55.815168 ==
3388 13:17:55.817730 Dram Type= 6, Freq= 0, CH_1, rank 1
3389 13:17:55.822098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3390 13:17:55.822519 ==
3391 13:17:55.822841
3392 13:17:55.823137
3393 13:17:55.824954 TX Vref Scan disable
3394 13:17:55.828416 == TX Byte 0 ==
3395 13:17:55.830847 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3396 13:17:55.834335 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3397 13:17:55.838187 == TX Byte 1 ==
3398 13:17:55.840915 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3399 13:17:55.845644 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3400 13:17:55.846059 ==
3401 13:17:55.847791 Dram Type= 6, Freq= 0, CH_1, rank 1
3402 13:17:55.850932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3403 13:17:55.853993 ==
3404 13:17:55.864328 TX Vref=22, minBit 8, minWin=25, winSum=424
3405 13:17:55.867840 TX Vref=24, minBit 9, minWin=25, winSum=428
3406 13:17:55.870937 TX Vref=26, minBit 9, minWin=25, winSum=428
3407 13:17:55.874234 TX Vref=28, minBit 4, minWin=26, winSum=431
3408 13:17:55.877957 TX Vref=30, minBit 9, minWin=26, winSum=433
3409 13:17:55.884136 TX Vref=32, minBit 9, minWin=26, winSum=432
3410 13:17:55.887179 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3411 13:17:55.887606
3412 13:17:55.890894 Final TX Range 1 Vref 30
3413 13:17:55.891392
3414 13:17:55.891717 ==
3415 13:17:55.894196 Dram Type= 6, Freq= 0, CH_1, rank 1
3416 13:17:55.897293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3417 13:17:55.901025 ==
3418 13:17:55.901578
3419 13:17:55.901906
3420 13:17:55.902203 TX Vref Scan disable
3421 13:17:55.903908 == TX Byte 0 ==
3422 13:17:55.907692 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3423 13:17:55.914051 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3424 13:17:55.914573 == TX Byte 1 ==
3425 13:17:55.918048 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3426 13:17:55.923622 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3427 13:17:55.924049
3428 13:17:55.924556 [DATLAT]
3429 13:17:55.924923 Freq=1200, CH1 RK1
3430 13:17:55.925264
3431 13:17:55.926766 DATLAT Default: 0xc
3432 13:17:55.930507 0, 0xFFFF, sum = 0
3433 13:17:55.931065 1, 0xFFFF, sum = 0
3434 13:17:55.933589 2, 0xFFFF, sum = 0
3435 13:17:55.934126 3, 0xFFFF, sum = 0
3436 13:17:55.936683 4, 0xFFFF, sum = 0
3437 13:17:55.937268 5, 0xFFFF, sum = 0
3438 13:17:55.940026 6, 0xFFFF, sum = 0
3439 13:17:55.940550 7, 0xFFFF, sum = 0
3440 13:17:55.943741 8, 0xFFFF, sum = 0
3441 13:17:55.944279 9, 0xFFFF, sum = 0
3442 13:17:55.947033 10, 0xFFFF, sum = 0
3443 13:17:55.947529 11, 0x0, sum = 1
3444 13:17:55.950301 12, 0x0, sum = 2
3445 13:17:55.950776 13, 0x0, sum = 3
3446 13:17:55.953345 14, 0x0, sum = 4
3447 13:17:55.953777 best_step = 12
3448 13:17:55.954154
3449 13:17:55.954460 ==
3450 13:17:55.957635 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 13:17:55.959880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3452 13:17:55.960302 ==
3453 13:17:55.963163 RX Vref Scan: 0
3454 13:17:55.963582
3455 13:17:55.967109 RX Vref 0 -> 0, step: 1
3456 13:17:55.967616
3457 13:17:55.967955 RX Delay -29 -> 252, step: 4
3458 13:17:55.974607 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3459 13:17:55.977853 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3460 13:17:55.980734 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3461 13:17:55.984172 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3462 13:17:55.987865 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3463 13:17:55.994816 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3464 13:17:55.997595 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3465 13:17:56.001514 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3466 13:17:56.004337 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3467 13:17:56.007705 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3468 13:17:56.014692 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3469 13:17:56.017560 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3470 13:17:56.020916 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3471 13:17:56.024548 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3472 13:17:56.031025 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3473 13:17:56.034229 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3474 13:17:56.034653 ==
3475 13:17:56.037339 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 13:17:56.040424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3477 13:17:56.040870 ==
3478 13:17:56.043791 DQS Delay:
3479 13:17:56.044302 DQS0 = 0, DQS1 = 0
3480 13:17:56.044625 DQM Delay:
3481 13:17:56.047054 DQM0 = 114, DQM1 = 104
3482 13:17:56.047515 DQ Delay:
3483 13:17:56.050318 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3484 13:17:56.053563 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3485 13:17:56.056674 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3486 13:17:56.060073 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
3487 13:17:56.063570
3488 13:17:56.064035
3489 13:17:56.070847 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3490 13:17:56.073805 CH1 RK1: MR19=404, MR18=D0D
3491 13:17:56.079849 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3492 13:17:56.083721 [RxdqsGatingPostProcess] freq 1200
3493 13:17:56.086497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3494 13:17:56.090172 Pre-setting of DQS Precalculation
3495 13:17:56.096950 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3496 13:17:56.103950 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3497 13:17:56.110401 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3498 13:17:56.110896
3499 13:17:56.111381
3500 13:17:56.113350 [Calibration Summary] 2400 Mbps
3501 13:17:56.113809 CH 0, Rank 0
3502 13:17:56.116455 SW Impedance : PASS
3503 13:17:56.119700 DUTY Scan : NO K
3504 13:17:56.120122 ZQ Calibration : PASS
3505 13:17:56.123382 Jitter Meter : NO K
3506 13:17:56.126422 CBT Training : PASS
3507 13:17:56.126841 Write leveling : PASS
3508 13:17:56.130063 RX DQS gating : PASS
3509 13:17:56.132710 RX DQ/DQS(RDDQC) : PASS
3510 13:17:56.133130 TX DQ/DQS : PASS
3511 13:17:56.136351 RX DATLAT : PASS
3512 13:17:56.136819 RX DQ/DQS(Engine): PASS
3513 13:17:56.139971 TX OE : NO K
3514 13:17:56.140479 All Pass.
3515 13:17:56.140810
3516 13:17:56.142664 CH 0, Rank 1
3517 13:17:56.143026 SW Impedance : PASS
3518 13:17:56.147155 DUTY Scan : NO K
3519 13:17:56.150070 ZQ Calibration : PASS
3520 13:17:56.150503 Jitter Meter : NO K
3521 13:17:56.153984 CBT Training : PASS
3522 13:17:56.156372 Write leveling : PASS
3523 13:17:56.156790 RX DQS gating : PASS
3524 13:17:56.160109 RX DQ/DQS(RDDQC) : PASS
3525 13:17:56.162981 TX DQ/DQS : PASS
3526 13:17:56.163405 RX DATLAT : PASS
3527 13:17:56.166124 RX DQ/DQS(Engine): PASS
3528 13:17:56.169333 TX OE : NO K
3529 13:17:56.169775 All Pass.
3530 13:17:56.170105
3531 13:17:56.170403 CH 1, Rank 0
3532 13:17:56.172625 SW Impedance : PASS
3533 13:17:56.175906 DUTY Scan : NO K
3534 13:17:56.176327 ZQ Calibration : PASS
3535 13:17:56.179349 Jitter Meter : NO K
3536 13:17:56.182375 CBT Training : PASS
3537 13:17:56.182799 Write leveling : PASS
3538 13:17:56.186044 RX DQS gating : PASS
3539 13:17:56.189336 RX DQ/DQS(RDDQC) : PASS
3540 13:17:56.189843 TX DQ/DQS : PASS
3541 13:17:56.192217 RX DATLAT : PASS
3542 13:17:56.195898 RX DQ/DQS(Engine): PASS
3543 13:17:56.196405 TX OE : NO K
3544 13:17:56.196740 All Pass.
3545 13:17:56.199266
3546 13:17:56.199685 CH 1, Rank 1
3547 13:17:56.202440 SW Impedance : PASS
3548 13:17:56.202866 DUTY Scan : NO K
3549 13:17:56.205692 ZQ Calibration : PASS
3550 13:17:56.206119 Jitter Meter : NO K
3551 13:17:56.209027 CBT Training : PASS
3552 13:17:56.212413 Write leveling : PASS
3553 13:17:56.212836 RX DQS gating : PASS
3554 13:17:56.215988 RX DQ/DQS(RDDQC) : PASS
3555 13:17:56.219145 TX DQ/DQS : PASS
3556 13:17:56.219631 RX DATLAT : PASS
3557 13:17:56.223036 RX DQ/DQS(Engine): PASS
3558 13:17:56.226265 TX OE : NO K
3559 13:17:56.226691 All Pass.
3560 13:17:56.227014
3561 13:17:56.229756 DramC Write-DBI off
3562 13:17:56.230366 PER_BANK_REFRESH: Hybrid Mode
3563 13:17:56.232699 TX_TRACKING: ON
3564 13:17:56.239499 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3565 13:17:56.245855 [FAST_K] Save calibration result to emmc
3566 13:17:56.249122 dramc_set_vcore_voltage set vcore to 650000
3567 13:17:56.249692 Read voltage for 600, 5
3568 13:17:56.252464 Vio18 = 0
3569 13:17:56.253037 Vcore = 650000
3570 13:17:56.253632 Vdram = 0
3571 13:17:56.255591 Vddq = 0
3572 13:17:56.256192 Vmddr = 0
3573 13:17:56.259400 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3574 13:17:56.265753 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3575 13:17:56.269113 MEM_TYPE=3, freq_sel=19
3576 13:17:56.272532 sv_algorithm_assistance_LP4_1600
3577 13:17:56.276075 ============ PULL DRAM RESETB DOWN ============
3578 13:17:56.278338 ========== PULL DRAM RESETB DOWN end =========
3579 13:17:56.285215 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3580 13:17:56.288292 ===================================
3581 13:17:56.288603 LPDDR4 DRAM CONFIGURATION
3582 13:17:56.291276 ===================================
3583 13:17:56.294703 EX_ROW_EN[0] = 0x0
3584 13:17:56.294921 EX_ROW_EN[1] = 0x0
3585 13:17:56.298210 LP4Y_EN = 0x0
3586 13:17:56.301368 WORK_FSP = 0x0
3587 13:17:56.301584 WL = 0x2
3588 13:17:56.304902 RL = 0x2
3589 13:17:56.305301 BL = 0x2
3590 13:17:56.307988 RPST = 0x0
3591 13:17:56.308203 RD_PRE = 0x0
3592 13:17:56.311660 WR_PRE = 0x1
3593 13:17:56.311876 WR_PST = 0x0
3594 13:17:56.315199 DBI_WR = 0x0
3595 13:17:56.315494 DBI_RD = 0x0
3596 13:17:56.318519 OTF = 0x1
3597 13:17:56.321514 ===================================
3598 13:17:56.324933 ===================================
3599 13:17:56.325454 ANA top config
3600 13:17:56.328708 ===================================
3601 13:17:56.332330 DLL_ASYNC_EN = 0
3602 13:17:56.336137 ALL_SLAVE_EN = 1
3603 13:17:56.336561 NEW_RANK_MODE = 1
3604 13:17:56.338661 DLL_IDLE_MODE = 1
3605 13:17:56.341280 LP45_APHY_COMB_EN = 1
3606 13:17:56.345116 TX_ODT_DIS = 1
3607 13:17:56.348636 NEW_8X_MODE = 1
3608 13:17:56.351315 ===================================
3609 13:17:56.355046 ===================================
3610 13:17:56.355429 data_rate = 1200
3611 13:17:56.358266 CKR = 1
3612 13:17:56.361529 DQ_P2S_RATIO = 8
3613 13:17:56.365463 ===================================
3614 13:17:56.368087 CA_P2S_RATIO = 8
3615 13:17:56.371625 DQ_CA_OPEN = 0
3616 13:17:56.374662 DQ_SEMI_OPEN = 0
3617 13:17:56.375122 CA_SEMI_OPEN = 0
3618 13:17:56.378415 CA_FULL_RATE = 0
3619 13:17:56.381666 DQ_CKDIV4_EN = 1
3620 13:17:56.384725 CA_CKDIV4_EN = 1
3621 13:17:56.388854 CA_PREDIV_EN = 0
3622 13:17:56.391449 PH8_DLY = 0
3623 13:17:56.391826 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3624 13:17:56.394470 DQ_AAMCK_DIV = 4
3625 13:17:56.397763 CA_AAMCK_DIV = 4
3626 13:17:56.401623 CA_ADMCK_DIV = 4
3627 13:17:56.405336 DQ_TRACK_CA_EN = 0
3628 13:17:56.408208 CA_PICK = 600
3629 13:17:56.408595 CA_MCKIO = 600
3630 13:17:56.410793 MCKIO_SEMI = 0
3631 13:17:56.414460 PLL_FREQ = 2288
3632 13:17:56.417528 DQ_UI_PI_RATIO = 32
3633 13:17:56.421074 CA_UI_PI_RATIO = 0
3634 13:17:56.424753 ===================================
3635 13:17:56.427968 ===================================
3636 13:17:56.431500 memory_type:LPDDR4
3637 13:17:56.431923 GP_NUM : 10
3638 13:17:56.434751 SRAM_EN : 1
3639 13:17:56.435051 MD32_EN : 0
3640 13:17:56.438497 ===================================
3641 13:17:56.441324 [ANA_INIT] >>>>>>>>>>>>>>
3642 13:17:56.444843 <<<<<< [CONFIGURE PHASE]: ANA_TX
3643 13:17:56.447703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3644 13:17:56.451830 ===================================
3645 13:17:56.454596 data_rate = 1200,PCW = 0X5800
3646 13:17:56.457834 ===================================
3647 13:17:56.461256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3648 13:17:56.467987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3649 13:17:56.471436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3650 13:17:56.477367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3651 13:17:56.481324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3652 13:17:56.484316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3653 13:17:56.484746 [ANA_INIT] flow start
3654 13:17:56.487116 [ANA_INIT] PLL >>>>>>>>
3655 13:17:56.491724 [ANA_INIT] PLL <<<<<<<<
3656 13:17:56.492152 [ANA_INIT] MIDPI >>>>>>>>
3657 13:17:56.494383 [ANA_INIT] MIDPI <<<<<<<<
3658 13:17:56.497959 [ANA_INIT] DLL >>>>>>>>
3659 13:17:56.498390 [ANA_INIT] flow end
3660 13:17:56.504325 ============ LP4 DIFF to SE enter ============
3661 13:17:56.507699 ============ LP4 DIFF to SE exit ============
3662 13:17:56.510379 [ANA_INIT] <<<<<<<<<<<<<
3663 13:17:56.514245 [Flow] Enable top DCM control >>>>>
3664 13:17:56.517294 [Flow] Enable top DCM control <<<<<
3665 13:17:56.517942 Enable DLL master slave shuffle
3666 13:17:56.523482 ==============================================================
3667 13:17:56.527133 Gating Mode config
3668 13:17:56.530483 ==============================================================
3669 13:17:56.533843 Config description:
3670 13:17:56.543828 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3671 13:17:56.550559 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3672 13:17:56.554403 SELPH_MODE 0: By rank 1: By Phase
3673 13:17:56.560784 ==============================================================
3674 13:17:56.563542 GAT_TRACK_EN = 1
3675 13:17:56.567425 RX_GATING_MODE = 2
3676 13:17:56.571004 RX_GATING_TRACK_MODE = 2
3677 13:17:56.571430 SELPH_MODE = 1
3678 13:17:56.574410 PICG_EARLY_EN = 1
3679 13:17:56.578116 VALID_LAT_VALUE = 1
3680 13:17:56.583840 ==============================================================
3681 13:17:56.587771 Enter into Gating configuration >>>>
3682 13:17:56.590633 Exit from Gating configuration <<<<
3683 13:17:56.593665 Enter into DVFS_PRE_config >>>>>
3684 13:17:56.603401 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3685 13:17:56.607090 Exit from DVFS_PRE_config <<<<<
3686 13:17:56.609904 Enter into PICG configuration >>>>
3687 13:17:56.613517 Exit from PICG configuration <<<<
3688 13:17:56.617124 [RX_INPUT] configuration >>>>>
3689 13:17:56.619873 [RX_INPUT] configuration <<<<<
3690 13:17:56.623122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3691 13:17:56.630331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3692 13:17:56.636454 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3693 13:17:56.643543 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3694 13:17:56.650224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3695 13:17:56.653111 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3696 13:17:56.660341 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3697 13:17:56.663609 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3698 13:17:56.666904 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3699 13:17:56.670270 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3700 13:17:56.676538 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3701 13:17:56.679766 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3702 13:17:56.683332 ===================================
3703 13:17:56.686718 LPDDR4 DRAM CONFIGURATION
3704 13:17:56.690195 ===================================
3705 13:17:56.690597 EX_ROW_EN[0] = 0x0
3706 13:17:56.693069 EX_ROW_EN[1] = 0x0
3707 13:17:56.693543 LP4Y_EN = 0x0
3708 13:17:56.696548 WORK_FSP = 0x0
3709 13:17:56.697043 WL = 0x2
3710 13:17:56.699519 RL = 0x2
3711 13:17:56.699950 BL = 0x2
3712 13:17:56.703373 RPST = 0x0
3713 13:17:56.706374 RD_PRE = 0x0
3714 13:17:56.706840 WR_PRE = 0x1
3715 13:17:56.709658 WR_PST = 0x0
3716 13:17:56.710043 DBI_WR = 0x0
3717 13:17:56.712974 DBI_RD = 0x0
3718 13:17:56.713502 OTF = 0x1
3719 13:17:56.716419 ===================================
3720 13:17:56.719525 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3721 13:17:56.726001 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3722 13:17:56.729540 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3723 13:17:56.732975 ===================================
3724 13:17:56.736098 LPDDR4 DRAM CONFIGURATION
3725 13:17:56.740145 ===================================
3726 13:17:56.740535 EX_ROW_EN[0] = 0x10
3727 13:17:56.742810 EX_ROW_EN[1] = 0x0
3728 13:17:56.743196 LP4Y_EN = 0x0
3729 13:17:56.746758 WORK_FSP = 0x0
3730 13:17:56.747144 WL = 0x2
3731 13:17:56.749466 RL = 0x2
3732 13:17:56.749902 BL = 0x2
3733 13:17:56.752795 RPST = 0x0
3734 13:17:56.753177 RD_PRE = 0x0
3735 13:17:56.756549 WR_PRE = 0x1
3736 13:17:56.757008 WR_PST = 0x0
3737 13:17:56.759582 DBI_WR = 0x0
3738 13:17:56.762957 DBI_RD = 0x0
3739 13:17:56.763424 OTF = 0x1
3740 13:17:56.765812 ===================================
3741 13:17:56.772528 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3742 13:17:56.776235 nWR fixed to 30
3743 13:17:56.780467 [ModeRegInit_LP4] CH0 RK0
3744 13:17:56.780854 [ModeRegInit_LP4] CH0 RK1
3745 13:17:56.782735 [ModeRegInit_LP4] CH1 RK0
3746 13:17:56.785749 [ModeRegInit_LP4] CH1 RK1
3747 13:17:56.786139 match AC timing 16
3748 13:17:56.793124 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3749 13:17:56.795873 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3750 13:17:56.799699 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3751 13:17:56.805519 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3752 13:17:56.809212 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3753 13:17:56.809854 ==
3754 13:17:56.812125 Dram Type= 6, Freq= 0, CH_0, rank 0
3755 13:17:56.815879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3756 13:17:56.816306 ==
3757 13:17:56.821997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3758 13:17:56.828939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3759 13:17:56.832220 [CA 0] Center 35 (5~66) winsize 62
3760 13:17:56.835302 [CA 1] Center 35 (5~66) winsize 62
3761 13:17:56.838879 [CA 2] Center 34 (4~65) winsize 62
3762 13:17:56.842199 [CA 3] Center 34 (4~65) winsize 62
3763 13:17:56.845097 [CA 4] Center 33 (3~64) winsize 62
3764 13:17:56.848455 [CA 5] Center 33 (3~64) winsize 62
3765 13:17:56.848896
3766 13:17:56.852174 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3767 13:17:56.852790
3768 13:17:56.855018 [CATrainingPosCal] consider 1 rank data
3769 13:17:56.858559 u2DelayCellTimex100 = 270/100 ps
3770 13:17:56.861835 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3771 13:17:56.864870 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3772 13:17:56.868571 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3773 13:17:56.874848 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3774 13:17:56.878261 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3775 13:17:56.881819 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3776 13:17:56.882245
3777 13:17:56.885835 CA PerBit enable=1, Macro0, CA PI delay=33
3778 13:17:56.886310
3779 13:17:56.888046 [CBTSetCACLKResult] CA Dly = 33
3780 13:17:56.888475 CS Dly: 6 (0~37)
3781 13:17:56.888810 ==
3782 13:17:56.891420 Dram Type= 6, Freq= 0, CH_0, rank 1
3783 13:17:56.898465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3784 13:17:56.898953 ==
3785 13:17:56.901538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3786 13:17:56.908042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3787 13:17:56.912987 [CA 0] Center 35 (5~66) winsize 62
3788 13:17:56.915137 [CA 1] Center 35 (5~66) winsize 62
3789 13:17:56.918113 [CA 2] Center 34 (4~65) winsize 62
3790 13:17:56.921392 [CA 3] Center 34 (4~65) winsize 62
3791 13:17:56.925011 [CA 4] Center 33 (3~64) winsize 62
3792 13:17:56.928169 [CA 5] Center 33 (3~64) winsize 62
3793 13:17:56.928695
3794 13:17:56.930801 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3795 13:17:56.931231
3796 13:17:56.934838 [CATrainingPosCal] consider 2 rank data
3797 13:17:56.937777 u2DelayCellTimex100 = 270/100 ps
3798 13:17:56.941145 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3799 13:17:56.947547 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3800 13:17:56.951031 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3801 13:17:56.954077 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3802 13:17:56.957428 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3803 13:17:56.960763 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3804 13:17:56.961193
3805 13:17:56.964059 CA PerBit enable=1, Macro0, CA PI delay=33
3806 13:17:56.964487
3807 13:17:56.967632 [CBTSetCACLKResult] CA Dly = 33
3808 13:17:56.971035 CS Dly: 6 (0~37)
3809 13:17:56.971466
3810 13:17:56.974715 ----->DramcWriteLeveling(PI) begin...
3811 13:17:56.975153 ==
3812 13:17:56.977296 Dram Type= 6, Freq= 0, CH_0, rank 0
3813 13:17:56.980656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3814 13:17:56.981104 ==
3815 13:17:56.983938 Write leveling (Byte 0): 29 => 29
3816 13:17:56.987181 Write leveling (Byte 1): 29 => 29
3817 13:17:56.990801 DramcWriteLeveling(PI) end<-----
3818 13:17:56.991279
3819 13:17:56.991581 ==
3820 13:17:56.994579 Dram Type= 6, Freq= 0, CH_0, rank 0
3821 13:17:56.997665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3822 13:17:56.998170 ==
3823 13:17:57.000862 [Gating] SW mode calibration
3824 13:17:57.007566 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3825 13:17:57.014125 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3826 13:17:57.017338 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3827 13:17:57.020243 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3828 13:17:57.027311 0 5 8 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 0)
3829 13:17:57.030722 0 5 12 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0)
3830 13:17:57.035069 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3831 13:17:57.040073 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3832 13:17:57.044359 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3833 13:17:57.046892 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3834 13:17:57.053195 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3835 13:17:57.057358 0 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3836 13:17:57.060571 0 6 8 | B1->B0 | 2f2e 3434 | 1 0 | (0 0) (0 0)
3837 13:17:57.066534 0 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
3838 13:17:57.071411 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3839 13:17:57.072979 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3840 13:17:57.079846 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3841 13:17:57.083372 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3842 13:17:57.086652 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3843 13:17:57.093219 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3844 13:17:57.096824 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3845 13:17:57.099701 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3846 13:17:57.106101 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3847 13:17:57.109823 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3848 13:17:57.113388 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3849 13:17:57.119402 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3850 13:17:57.122960 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3851 13:17:57.126639 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3852 13:17:57.132437 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3853 13:17:57.136159 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3854 13:17:57.139564 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3855 13:17:57.145687 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3856 13:17:57.149440 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3857 13:17:57.152301 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3858 13:17:57.160297 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3859 13:17:57.163232 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3860 13:17:57.165965 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3861 13:17:57.169801 Total UI for P1: 0, mck2ui 16
3862 13:17:57.172658 best dqsien dly found for B0: ( 0, 9, 6)
3863 13:17:57.179189 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 13:17:57.179591 Total UI for P1: 0, mck2ui 16
3865 13:17:57.182267 best dqsien dly found for B1: ( 0, 9, 8)
3866 13:17:57.188737 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3867 13:17:57.192518 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3868 13:17:57.192905
3869 13:17:57.195324 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3870 13:17:57.199219 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3871 13:17:57.202326 [Gating] SW calibration Done
3872 13:17:57.202713 ==
3873 13:17:57.205752 Dram Type= 6, Freq= 0, CH_0, rank 0
3874 13:17:57.208875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3875 13:17:57.209308 ==
3876 13:17:57.212879 RX Vref Scan: 0
3877 13:17:57.213299
3878 13:17:57.213608 RX Vref 0 -> 0, step: 1
3879 13:17:57.213890
3880 13:17:57.215563 RX Delay -230 -> 252, step: 16
3881 13:17:57.219306 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3882 13:17:57.225012 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3883 13:17:57.228710 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3884 13:17:57.232285 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3885 13:17:57.236191 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3886 13:17:57.241594 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3887 13:17:57.245133 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3888 13:17:57.249283 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3889 13:17:57.251410 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3890 13:17:57.254608 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3891 13:17:57.261789 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3892 13:17:57.264819 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3893 13:17:57.267958 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3894 13:17:57.271631 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3895 13:17:57.277901 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3896 13:17:57.281683 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3897 13:17:57.282178 ==
3898 13:17:57.284639 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 13:17:57.288502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3900 13:17:57.288891 ==
3901 13:17:57.291627 DQS Delay:
3902 13:17:57.292094 DQS0 = 0, DQS1 = 0
3903 13:17:57.294727 DQM Delay:
3904 13:17:57.295110 DQM0 = 38, DQM1 = 33
3905 13:17:57.295404 DQ Delay:
3906 13:17:57.298186 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3907 13:17:57.301093 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3908 13:17:57.304552 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3909 13:17:57.307964 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3910 13:17:57.308351
3911 13:17:57.308646
3912 13:17:57.308934 ==
3913 13:17:57.311255 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 13:17:57.318205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3915 13:17:57.318596 ==
3916 13:17:57.318895
3917 13:17:57.319166
3918 13:17:57.321179 TX Vref Scan disable
3919 13:17:57.321605 == TX Byte 0 ==
3920 13:17:57.324523 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3921 13:17:57.331212 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3922 13:17:57.331603 == TX Byte 1 ==
3923 13:17:57.334590 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3924 13:17:57.341270 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3925 13:17:57.341662 ==
3926 13:17:57.344572 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 13:17:57.348016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3928 13:17:57.348612 ==
3929 13:17:57.349006
3930 13:17:57.349345
3931 13:17:57.350663 TX Vref Scan disable
3932 13:17:57.354306 == TX Byte 0 ==
3933 13:17:57.357294 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3934 13:17:57.361082 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3935 13:17:57.364332 == TX Byte 1 ==
3936 13:17:57.367489 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3937 13:17:57.370829 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3938 13:17:57.371271
3939 13:17:57.373800 [DATLAT]
3940 13:17:57.374185 Freq=600, CH0 RK0
3941 13:17:57.374486
3942 13:17:57.377791 DATLAT Default: 0x9
3943 13:17:57.378178 0, 0xFFFF, sum = 0
3944 13:17:57.380324 1, 0xFFFF, sum = 0
3945 13:17:57.380729 2, 0xFFFF, sum = 0
3946 13:17:57.384686 3, 0xFFFF, sum = 0
3947 13:17:57.385082 4, 0xFFFF, sum = 0
3948 13:17:57.387220 5, 0xFFFF, sum = 0
3949 13:17:57.387670 6, 0xFFFF, sum = 0
3950 13:17:57.390504 7, 0x0, sum = 1
3951 13:17:57.390897 8, 0x0, sum = 2
3952 13:17:57.393684 9, 0x0, sum = 3
3953 13:17:57.394079 10, 0x0, sum = 4
3954 13:17:57.396959 best_step = 8
3955 13:17:57.397384
3956 13:17:57.397690 ==
3957 13:17:57.400069 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 13:17:57.403669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3959 13:17:57.404080 ==
3960 13:17:57.407144 RX Vref Scan: 1
3961 13:17:57.407530
3962 13:17:57.407952 RX Vref 0 -> 0, step: 1
3963 13:17:57.408309
3964 13:17:57.410373 RX Delay -195 -> 252, step: 8
3965 13:17:57.410855
3966 13:17:57.414053 Set Vref, RX VrefLevel [Byte0]: 48
3967 13:17:57.416512 [Byte1]: 50
3968 13:17:57.420909
3969 13:17:57.421335 Final RX Vref Byte 0 = 48 to rank0
3970 13:17:57.424145 Final RX Vref Byte 1 = 50 to rank0
3971 13:17:57.427091 Final RX Vref Byte 0 = 48 to rank1
3972 13:17:57.430439 Final RX Vref Byte 1 = 50 to rank1==
3973 13:17:57.433621 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 13:17:57.440285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3975 13:17:57.440747 ==
3976 13:17:57.441061 DQS Delay:
3977 13:17:57.441541 DQS0 = 0, DQS1 = 0
3978 13:17:57.444247 DQM Delay:
3979 13:17:57.444630 DQM0 = 40, DQM1 = 29
3980 13:17:57.447070 DQ Delay:
3981 13:17:57.450517 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =36
3982 13:17:57.454069 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3983 13:17:57.454488 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3984 13:17:57.460407 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
3985 13:17:57.460794
3986 13:17:57.461090
3987 13:17:57.467123 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3988 13:17:57.470187 CH0 RK0: MR19=808, MR18=5959
3989 13:17:57.477117 CH0_RK0: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
3990 13:17:57.477590
3991 13:17:57.480070 ----->DramcWriteLeveling(PI) begin...
3992 13:17:57.480462 ==
3993 13:17:57.484213 Dram Type= 6, Freq= 0, CH_0, rank 1
3994 13:17:57.486688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3995 13:17:57.487324 ==
3996 13:17:57.490786 Write leveling (Byte 0): 32 => 32
3997 13:17:57.493627 Write leveling (Byte 1): 30 => 30
3998 13:17:57.497104 DramcWriteLeveling(PI) end<-----
3999 13:17:57.497553
4000 13:17:57.497853 ==
4001 13:17:57.500090 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 13:17:57.503462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4003 13:17:57.503970 ==
4004 13:17:57.506810 [Gating] SW mode calibration
4005 13:17:57.513516 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4006 13:17:57.520626 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4007 13:17:57.523524 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 13:17:57.529884 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4009 13:17:57.533421 0 5 8 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
4010 13:17:57.536486 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
4011 13:17:57.542980 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 13:17:57.546439 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 13:17:57.549715 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 13:17:57.556213 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 13:17:57.559490 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 13:17:57.562530 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 13:17:57.570435 0 6 8 | B1->B0 | 2d2d 3535 | 0 0 | (1 1) (0 0)
4018 13:17:57.572842 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4019 13:17:57.576362 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 13:17:57.579898 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 13:17:57.586476 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 13:17:57.589939 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 13:17:57.593219 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 13:17:57.600106 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 13:17:57.602858 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4026 13:17:57.606409 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:17:57.612638 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:17:57.615848 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 13:17:57.619341 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 13:17:57.626285 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 13:17:57.629436 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 13:17:57.633438 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 13:17:57.639654 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 13:17:57.643020 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 13:17:57.645991 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 13:17:57.652759 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 13:17:57.656497 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 13:17:57.659193 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 13:17:57.665870 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 13:17:57.668972 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 13:17:57.673106 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4042 13:17:57.678790 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 13:17:57.679218 Total UI for P1: 0, mck2ui 16
4044 13:17:57.686190 best dqsien dly found for B0: ( 0, 9, 8)
4045 13:17:57.686661 Total UI for P1: 0, mck2ui 16
4046 13:17:57.692561 best dqsien dly found for B1: ( 0, 9, 8)
4047 13:17:57.695962 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4048 13:17:57.699612 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4049 13:17:57.700037
4050 13:17:57.702755 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4051 13:17:57.706124 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4052 13:17:57.708634 [Gating] SW calibration Done
4053 13:17:57.709057 ==
4054 13:17:57.711993 Dram Type= 6, Freq= 0, CH_0, rank 1
4055 13:17:57.716355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4056 13:17:57.716781 ==
4057 13:17:57.719144 RX Vref Scan: 0
4058 13:17:57.719526
4059 13:17:57.719820 RX Vref 0 -> 0, step: 1
4060 13:17:57.720096
4061 13:17:57.722786 RX Delay -230 -> 252, step: 16
4062 13:17:57.725584 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4063 13:17:57.732768 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4064 13:17:57.735427 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4065 13:17:57.738898 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4066 13:17:57.742349 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4067 13:17:57.750258 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4068 13:17:57.752079 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4069 13:17:57.755796 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4070 13:17:57.759281 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4071 13:17:57.762063 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4072 13:17:57.768696 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4073 13:17:57.772197 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4074 13:17:57.775326 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4075 13:17:57.778978 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4076 13:17:57.785193 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4077 13:17:57.788439 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4078 13:17:57.788829 ==
4079 13:17:57.791743 Dram Type= 6, Freq= 0, CH_0, rank 1
4080 13:17:57.795375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4081 13:17:57.795809 ==
4082 13:17:57.798300 DQS Delay:
4083 13:17:57.798682 DQS0 = 0, DQS1 = 0
4084 13:17:57.798982 DQM Delay:
4085 13:17:57.802194 DQM0 = 41, DQM1 = 34
4086 13:17:57.802575 DQ Delay:
4087 13:17:57.804994 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4088 13:17:57.808932 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4089 13:17:57.812301 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4090 13:17:57.815260 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4091 13:17:57.815644
4092 13:17:57.815947
4093 13:17:57.816223 ==
4094 13:17:57.818877 Dram Type= 6, Freq= 0, CH_0, rank 1
4095 13:17:57.825304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4096 13:17:57.825759 ==
4097 13:17:57.826058
4098 13:17:57.826372
4099 13:17:57.826841 TX Vref Scan disable
4100 13:17:57.828636 == TX Byte 0 ==
4101 13:17:57.832225 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4102 13:17:57.839015 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4103 13:17:57.839442 == TX Byte 1 ==
4104 13:17:57.842197 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4105 13:17:57.848807 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4106 13:17:57.849279 ==
4107 13:17:57.852064 Dram Type= 6, Freq= 0, CH_0, rank 1
4108 13:17:57.855361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4109 13:17:57.855834 ==
4110 13:17:57.856162
4111 13:17:57.856464
4112 13:17:57.858722 TX Vref Scan disable
4113 13:17:57.862714 == TX Byte 0 ==
4114 13:17:57.864897 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4115 13:17:57.868420 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4116 13:17:57.871668 == TX Byte 1 ==
4117 13:17:57.875340 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4118 13:17:57.878487 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4119 13:17:57.878877
4120 13:17:57.879226 [DATLAT]
4121 13:17:57.881719 Freq=600, CH0 RK1
4122 13:17:57.882183
4123 13:17:57.884932 DATLAT Default: 0x8
4124 13:17:57.885463 0, 0xFFFF, sum = 0
4125 13:17:57.888407 1, 0xFFFF, sum = 0
4126 13:17:57.888800 2, 0xFFFF, sum = 0
4127 13:17:57.891816 3, 0xFFFF, sum = 0
4128 13:17:57.892260 4, 0xFFFF, sum = 0
4129 13:17:57.895266 5, 0xFFFF, sum = 0
4130 13:17:57.895720 6, 0xFFFF, sum = 0
4131 13:17:57.898406 7, 0x0, sum = 1
4132 13:17:57.898847 8, 0x0, sum = 2
4133 13:17:57.899158 9, 0x0, sum = 3
4134 13:17:57.901570 10, 0x0, sum = 4
4135 13:17:57.901964 best_step = 8
4136 13:17:57.902264
4137 13:17:57.902538 ==
4138 13:17:57.904767 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 13:17:57.911517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4140 13:17:57.911947 ==
4141 13:17:57.912250 RX Vref Scan: 0
4142 13:17:57.912529
4143 13:17:57.914648 RX Vref 0 -> 0, step: 1
4144 13:17:57.915226
4145 13:17:57.918415 RX Delay -179 -> 252, step: 8
4146 13:17:57.921627 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4147 13:17:57.928314 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4148 13:17:57.931669 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4149 13:17:57.935033 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4150 13:17:57.938521 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4151 13:17:57.944554 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4152 13:17:57.948071 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4153 13:17:57.951139 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4154 13:17:57.954335 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4155 13:17:57.958610 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4156 13:17:57.964308 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4157 13:17:57.968643 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4158 13:17:57.971270 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4159 13:17:57.974535 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4160 13:17:57.981210 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4161 13:17:57.984616 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4162 13:17:57.985003 ==
4163 13:17:57.988341 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 13:17:57.990992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4165 13:17:57.991387 ==
4166 13:17:57.994393 DQS Delay:
4167 13:17:57.994853 DQS0 = 0, DQS1 = 0
4168 13:17:57.997676 DQM Delay:
4169 13:17:57.998140 DQM0 = 40, DQM1 = 32
4170 13:17:57.998444 DQ Delay:
4171 13:17:58.000787 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4172 13:17:58.004152 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4173 13:17:58.008141 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4174 13:17:58.010591 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4175 13:17:58.010978
4176 13:17:58.011274
4177 13:17:58.020429 [DQSOSCAuto] RK1, (LSB)MR18= 0x7171, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4178 13:17:58.024123 CH0 RK1: MR19=808, MR18=7171
4179 13:17:58.031000 CH0_RK1: MR19=0x808, MR18=0x7171, DQSOSC=388, MR23=63, INC=174, DEC=116
4180 13:17:58.031491 [RxdqsGatingPostProcess] freq 600
4181 13:17:58.037413 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4182 13:17:58.040584 Pre-setting of DQS Precalculation
4183 13:17:58.044592 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4184 13:17:58.047971 ==
4185 13:17:58.050565 Dram Type= 6, Freq= 0, CH_1, rank 0
4186 13:17:58.053884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4187 13:17:58.054490 ==
4188 13:17:58.057890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4189 13:17:58.064527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4190 13:17:58.067719 [CA 0] Center 35 (5~66) winsize 62
4191 13:17:58.070934 [CA 1] Center 35 (5~66) winsize 62
4192 13:17:58.074424 [CA 2] Center 33 (3~64) winsize 62
4193 13:17:58.077789 [CA 3] Center 33 (3~64) winsize 62
4194 13:17:58.080796 [CA 4] Center 33 (2~64) winsize 63
4195 13:17:58.083973 [CA 5] Center 33 (2~64) winsize 63
4196 13:17:58.084399
4197 13:17:58.087664 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4198 13:17:58.088168
4199 13:17:58.090938 [CATrainingPosCal] consider 1 rank data
4200 13:17:58.093918 u2DelayCellTimex100 = 270/100 ps
4201 13:17:58.097543 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4202 13:17:58.103738 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4203 13:17:58.107474 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4204 13:17:58.110571 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4205 13:17:58.113698 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4206 13:17:58.117614 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4207 13:17:58.118129
4208 13:17:58.120782 CA PerBit enable=1, Macro0, CA PI delay=33
4209 13:17:58.121317
4210 13:17:58.124387 [CBTSetCACLKResult] CA Dly = 33
4211 13:17:58.124883 CS Dly: 3 (0~34)
4212 13:17:58.127575 ==
4213 13:17:58.130253 Dram Type= 6, Freq= 0, CH_1, rank 1
4214 13:17:58.133886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4215 13:17:58.134393 ==
4216 13:17:58.137288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4217 13:17:58.143934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4218 13:17:58.147949 [CA 0] Center 35 (5~66) winsize 62
4219 13:17:58.151261 [CA 1] Center 34 (4~65) winsize 62
4220 13:17:58.154566 [CA 2] Center 33 (3~64) winsize 62
4221 13:17:58.157760 [CA 3] Center 33 (3~64) winsize 62
4222 13:17:58.160725 [CA 4] Center 32 (2~63) winsize 62
4223 13:17:58.164191 [CA 5] Center 32 (2~63) winsize 62
4224 13:17:58.164615
4225 13:17:58.167691 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4226 13:17:58.168114
4227 13:17:58.170859 [CATrainingPosCal] consider 2 rank data
4228 13:17:58.173858 u2DelayCellTimex100 = 270/100 ps
4229 13:17:58.177470 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4230 13:17:58.183905 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4231 13:17:58.188982 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4232 13:17:58.190494 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4233 13:17:58.194533 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4234 13:17:58.197677 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4235 13:17:58.198103
4236 13:17:58.200973 CA PerBit enable=1, Macro0, CA PI delay=32
4237 13:17:58.201477
4238 13:17:58.204278 [CBTSetCACLKResult] CA Dly = 32
4239 13:17:58.204757 CS Dly: 4 (0~36)
4240 13:17:58.207241
4241 13:17:58.211392 ----->DramcWriteLeveling(PI) begin...
4242 13:17:58.211825 ==
4243 13:17:58.213656 Dram Type= 6, Freq= 0, CH_1, rank 0
4244 13:17:58.217630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4245 13:17:58.218128 ==
4246 13:17:58.220528 Write leveling (Byte 0): 28 => 28
4247 13:17:58.223668 Write leveling (Byte 1): 26 => 26
4248 13:17:58.227754 DramcWriteLeveling(PI) end<-----
4249 13:17:58.228223
4250 13:17:58.228791 ==
4251 13:17:58.230206 Dram Type= 6, Freq= 0, CH_1, rank 0
4252 13:17:58.233976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4253 13:17:58.234466 ==
4254 13:17:58.237059 [Gating] SW mode calibration
4255 13:17:58.243897 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4256 13:17:58.250239 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4257 13:17:58.253312 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4258 13:17:58.256704 0 5 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4259 13:17:58.263118 0 5 8 | B1->B0 | 2f2f 2727 | 1 1 | (1 1) (1 0)
4260 13:17:58.267019 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 13:17:58.270085 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 13:17:58.277041 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 13:17:58.279837 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 13:17:58.283189 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 13:17:58.289734 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 13:17:58.293074 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4267 13:17:58.296880 0 6 8 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4268 13:17:58.303962 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 13:17:58.306585 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 13:17:58.310275 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 13:17:58.317044 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 13:17:58.319990 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 13:17:58.323139 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 13:17:58.329672 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 13:17:58.333169 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4276 13:17:58.336667 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 13:17:58.343032 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 13:17:58.346207 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 13:17:58.349212 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 13:17:58.356495 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 13:17:58.359949 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 13:17:58.362925 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 13:17:58.369257 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 13:17:58.373071 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 13:17:58.376265 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 13:17:58.379520 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 13:17:58.386231 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 13:17:58.389392 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 13:17:58.392603 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 13:17:58.399241 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4291 13:17:58.402658 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4292 13:17:58.406414 Total UI for P1: 0, mck2ui 16
4293 13:17:58.409096 best dqsien dly found for B0: ( 0, 9, 4)
4294 13:17:58.412503 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 13:17:58.416338 Total UI for P1: 0, mck2ui 16
4296 13:17:58.419336 best dqsien dly found for B1: ( 0, 9, 8)
4297 13:17:58.422198 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4298 13:17:58.425606 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4299 13:17:58.426033
4300 13:17:58.432233 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4301 13:17:58.436102 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4302 13:17:58.438874 [Gating] SW calibration Done
4303 13:17:58.439297 ==
4304 13:17:58.442381 Dram Type= 6, Freq= 0, CH_1, rank 0
4305 13:17:58.445933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4306 13:17:58.446380 ==
4307 13:17:58.446838 RX Vref Scan: 0
4308 13:17:58.447157
4309 13:17:58.449409 RX Vref 0 -> 0, step: 1
4310 13:17:58.449830
4311 13:17:58.452070 RX Delay -230 -> 252, step: 16
4312 13:17:58.455820 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4313 13:17:58.458922 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4314 13:17:58.465825 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4315 13:17:58.468909 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4316 13:17:58.471912 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4317 13:17:58.475758 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4318 13:17:58.481826 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4319 13:17:58.485160 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4320 13:17:58.488258 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4321 13:17:58.491964 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4322 13:17:58.495803 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4323 13:17:58.502903 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4324 13:17:58.505307 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4325 13:17:58.509309 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4326 13:17:58.511931 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4327 13:17:58.518928 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4328 13:17:58.519314 ==
4329 13:17:58.522080 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 13:17:58.525312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4331 13:17:58.525697 ==
4332 13:17:58.525991 DQS Delay:
4333 13:17:58.528260 DQS0 = 0, DQS1 = 0
4334 13:17:58.528639 DQM Delay:
4335 13:17:58.531738 DQM0 = 39, DQM1 = 31
4336 13:17:58.532117 DQ Delay:
4337 13:17:58.535422 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4338 13:17:58.538034 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4339 13:17:58.541373 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4340 13:17:58.545373 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4341 13:17:58.545751
4342 13:17:58.546044
4343 13:17:58.546313 ==
4344 13:17:58.548924 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 13:17:58.555166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4346 13:17:58.555550 ==
4347 13:17:58.555841
4348 13:17:58.556110
4349 13:17:58.556366 TX Vref Scan disable
4350 13:17:58.558853 == TX Byte 0 ==
4351 13:17:58.562097 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4352 13:17:58.568282 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4353 13:17:58.568685 == TX Byte 1 ==
4354 13:17:58.571307 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4355 13:17:58.574835 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4356 13:17:58.578330 ==
4357 13:17:58.581274 Dram Type= 6, Freq= 0, CH_1, rank 0
4358 13:17:58.584500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4359 13:17:58.584883 ==
4360 13:17:58.585371
4361 13:17:58.585659
4362 13:17:58.587737 TX Vref Scan disable
4363 13:17:58.591184 == TX Byte 0 ==
4364 13:17:58.594430 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4365 13:17:58.597662 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4366 13:17:58.601723 == TX Byte 1 ==
4367 13:17:58.604903 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4368 13:17:58.608072 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4369 13:17:58.608455
4370 13:17:58.608745 [DATLAT]
4371 13:17:58.611723 Freq=600, CH1 RK0
4372 13:17:58.612145
4373 13:17:58.612439 DATLAT Default: 0x9
4374 13:17:58.614855 0, 0xFFFF, sum = 0
4375 13:17:58.615239 1, 0xFFFF, sum = 0
4376 13:17:58.617659 2, 0xFFFF, sum = 0
4377 13:17:58.621008 3, 0xFFFF, sum = 0
4378 13:17:58.621453 4, 0xFFFF, sum = 0
4379 13:17:58.624640 5, 0xFFFF, sum = 0
4380 13:17:58.625020 6, 0xFFFF, sum = 0
4381 13:17:58.628167 7, 0x0, sum = 1
4382 13:17:58.628547 8, 0x0, sum = 2
4383 13:17:58.628844 9, 0x0, sum = 3
4384 13:17:58.630994 10, 0x0, sum = 4
4385 13:17:58.631531 best_step = 8
4386 13:17:58.632021
4387 13:17:58.632443 ==
4388 13:17:58.634024 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 13:17:58.640965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4390 13:17:58.641457 ==
4391 13:17:58.641759 RX Vref Scan: 1
4392 13:17:58.642031
4393 13:17:58.644738 RX Vref 0 -> 0, step: 1
4394 13:17:58.645278
4395 13:17:58.647985 RX Delay -195 -> 252, step: 8
4396 13:17:58.648521
4397 13:17:58.651191 Set Vref, RX VrefLevel [Byte0]: 55
4398 13:17:58.654384 [Byte1]: 49
4399 13:17:58.654768
4400 13:17:58.657338 Final RX Vref Byte 0 = 55 to rank0
4401 13:17:58.661074 Final RX Vref Byte 1 = 49 to rank0
4402 13:17:58.663924 Final RX Vref Byte 0 = 55 to rank1
4403 13:17:58.667816 Final RX Vref Byte 1 = 49 to rank1==
4404 13:17:58.670770 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 13:17:58.673832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4406 13:17:58.674228 ==
4407 13:17:58.677517 DQS Delay:
4408 13:17:58.677901 DQS0 = 0, DQS1 = 0
4409 13:17:58.680800 DQM Delay:
4410 13:17:58.681181 DQM0 = 38, DQM1 = 30
4411 13:17:58.681537 DQ Delay:
4412 13:17:58.684588 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4413 13:17:58.687806 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4414 13:17:58.691466 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4415 13:17:58.693910 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4416 13:17:58.694294
4417 13:17:58.694587
4418 13:17:58.704277 [DQSOSCAuto] RK0, (LSB)MR18= 0x7d7d, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4419 13:17:58.707228 CH1 RK0: MR19=808, MR18=7D7D
4420 13:17:58.714174 CH1_RK0: MR19=0x808, MR18=0x7D7D, DQSOSC=386, MR23=63, INC=176, DEC=117
4421 13:17:58.714588
4422 13:17:58.717316 ----->DramcWriteLeveling(PI) begin...
4423 13:17:58.717733 ==
4424 13:17:58.721151 Dram Type= 6, Freq= 0, CH_1, rank 1
4425 13:17:58.724006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4426 13:17:58.724393 ==
4427 13:17:58.727778 Write leveling (Byte 0): 26 => 26
4428 13:17:58.730373 Write leveling (Byte 1): 27 => 27
4429 13:17:58.733565 DramcWriteLeveling(PI) end<-----
4430 13:17:58.733954
4431 13:17:58.734250 ==
4432 13:17:58.737455 Dram Type= 6, Freq= 0, CH_1, rank 1
4433 13:17:58.740925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4434 13:17:58.741440 ==
4435 13:17:58.743609 [Gating] SW mode calibration
4436 13:17:58.750198 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4437 13:17:58.757777 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4438 13:17:58.760274 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 13:17:58.763856 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
4440 13:17:58.770248 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4441 13:17:58.773219 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 13:17:58.776719 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 13:17:58.784452 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 13:17:58.786451 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 13:17:58.790260 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 13:17:58.797283 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 13:17:58.799692 0 6 4 | B1->B0 | 2424 2b2b | 0 1 | (0 0) (0 0)
4448 13:17:58.803253 0 6 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4449 13:17:58.810022 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 13:17:58.812833 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 13:17:58.816483 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 13:17:58.823209 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 13:17:58.826170 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 13:17:58.829938 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 13:17:58.836165 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 13:17:58.839547 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:17:58.843237 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:17:58.849749 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:17:58.852899 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:17:58.856138 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:17:58.863606 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:17:58.866566 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:17:58.869323 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:17:58.876397 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:17:58.879968 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 13:17:58.882553 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 13:17:58.889296 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 13:17:58.893440 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 13:17:58.896040 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 13:17:58.902844 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 13:17:58.905725 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4472 13:17:58.909270 Total UI for P1: 0, mck2ui 16
4473 13:17:58.912418 best dqsien dly found for B1: ( 0, 9, 2)
4474 13:17:58.915671 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 13:17:58.919216 Total UI for P1: 0, mck2ui 16
4476 13:17:58.922289 best dqsien dly found for B0: ( 0, 9, 4)
4477 13:17:58.925612 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4478 13:17:58.929163 best DQS1 dly(MCK, UI, PI) = (0, 9, 2)
4479 13:17:58.929618
4480 13:17:58.932133 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4481 13:17:58.938880 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 2)
4482 13:17:58.939361 [Gating] SW calibration Done
4483 13:17:58.939661 ==
4484 13:17:58.942273 Dram Type= 6, Freq= 0, CH_1, rank 1
4485 13:17:58.949610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4486 13:17:58.950165 ==
4487 13:17:58.950472 RX Vref Scan: 0
4488 13:17:58.950746
4489 13:17:58.952584 RX Vref 0 -> 0, step: 1
4490 13:17:58.952964
4491 13:17:58.955579 RX Delay -230 -> 252, step: 16
4492 13:17:58.958859 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4493 13:17:58.962250 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4494 13:17:58.965523 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4495 13:17:58.973667 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4496 13:17:58.975650 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4497 13:17:58.978768 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4498 13:17:58.981644 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4499 13:17:58.988628 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4500 13:17:58.991706 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4501 13:17:58.995507 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4502 13:17:58.998889 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4503 13:17:59.002262 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4504 13:17:59.008713 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4505 13:17:59.012506 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4506 13:17:59.015509 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4507 13:17:59.018909 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4508 13:17:59.021962 ==
4509 13:17:59.025289 Dram Type= 6, Freq= 0, CH_1, rank 1
4510 13:17:59.028542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4511 13:17:59.029013 ==
4512 13:17:59.029380 DQS Delay:
4513 13:17:59.031640 DQS0 = 0, DQS1 = 0
4514 13:17:59.032059 DQM Delay:
4515 13:17:59.034869 DQM0 = 40, DQM1 = 34
4516 13:17:59.035296 DQ Delay:
4517 13:17:59.038837 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4518 13:17:59.041798 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4519 13:17:59.045292 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4520 13:17:59.048277 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4521 13:17:59.048715
4522 13:17:59.049050
4523 13:17:59.049414 ==
4524 13:17:59.052456 Dram Type= 6, Freq= 0, CH_1, rank 1
4525 13:17:59.054992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4526 13:17:59.055425 ==
4527 13:17:59.055754
4528 13:17:59.056057
4529 13:17:59.058226 TX Vref Scan disable
4530 13:17:59.061183 == TX Byte 0 ==
4531 13:17:59.064626 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4532 13:17:59.067988 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4533 13:17:59.071630 == TX Byte 1 ==
4534 13:17:59.075068 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4535 13:17:59.078410 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4536 13:17:59.078549 ==
4537 13:17:59.081549 Dram Type= 6, Freq= 0, CH_1, rank 1
4538 13:17:59.084501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4539 13:17:59.088445 ==
4540 13:17:59.088605
4541 13:17:59.088706
4542 13:17:59.088793 TX Vref Scan disable
4543 13:17:59.091968 == TX Byte 0 ==
4544 13:17:59.095171 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4545 13:17:59.102533 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4546 13:17:59.102728 == TX Byte 1 ==
4547 13:17:59.105157 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4548 13:17:59.111636 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4549 13:17:59.111858
4550 13:17:59.112028 [DATLAT]
4551 13:17:59.112187 Freq=600, CH1 RK1
4552 13:17:59.112340
4553 13:17:59.114946 DATLAT Default: 0x8
4554 13:17:59.115167 0, 0xFFFF, sum = 0
4555 13:17:59.118788 1, 0xFFFF, sum = 0
4556 13:17:59.121824 2, 0xFFFF, sum = 0
4557 13:17:59.122211 3, 0xFFFF, sum = 0
4558 13:17:59.125310 4, 0xFFFF, sum = 0
4559 13:17:59.125707 5, 0xFFFF, sum = 0
4560 13:17:59.128765 6, 0xFFFF, sum = 0
4561 13:17:59.129361 7, 0x0, sum = 1
4562 13:17:59.132164 8, 0x0, sum = 2
4563 13:17:59.132599 9, 0x0, sum = 3
4564 13:17:59.132934 10, 0x0, sum = 4
4565 13:17:59.135563 best_step = 8
4566 13:17:59.135986
4567 13:17:59.136315 ==
4568 13:17:59.138330 Dram Type= 6, Freq= 0, CH_1, rank 1
4569 13:17:59.141989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4570 13:17:59.142422 ==
4571 13:17:59.145601 RX Vref Scan: 0
4572 13:17:59.146090
4573 13:17:59.146422 RX Vref 0 -> 0, step: 1
4574 13:17:59.146726
4575 13:17:59.148088 RX Delay -195 -> 252, step: 8
4576 13:17:59.156603 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4577 13:17:59.159311 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4578 13:17:59.162451 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4579 13:17:59.165990 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4580 13:17:59.172933 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4581 13:17:59.176199 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4582 13:17:59.179071 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4583 13:17:59.182588 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4584 13:17:59.185744 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4585 13:17:59.192474 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4586 13:17:59.195591 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4587 13:17:59.199178 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4588 13:17:59.202458 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4589 13:17:59.208920 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4590 13:17:59.212332 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4591 13:17:59.215621 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4592 13:17:59.216049 ==
4593 13:17:59.218568 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 13:17:59.225814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4595 13:17:59.226248 ==
4596 13:17:59.226575 DQS Delay:
4597 13:17:59.226880 DQS0 = 0, DQS1 = 0
4598 13:17:59.228995 DQM Delay:
4599 13:17:59.229476 DQM0 = 36, DQM1 = 30
4600 13:17:59.232176 DQ Delay:
4601 13:17:59.235932 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4602 13:17:59.239144 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4603 13:17:59.241921 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4604 13:17:59.245487 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4605 13:17:59.246011
4606 13:17:59.246347
4607 13:17:59.251791 [DQSOSCAuto] RK1, (LSB)MR18= 0x6262, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4608 13:17:59.256012 CH1 RK1: MR19=808, MR18=6262
4609 13:17:59.262161 CH1_RK1: MR19=0x808, MR18=0x6262, DQSOSC=391, MR23=63, INC=171, DEC=114
4610 13:17:59.264988 [RxdqsGatingPostProcess] freq 600
4611 13:17:59.268136 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4612 13:17:59.272079 Pre-setting of DQS Precalculation
4613 13:17:59.278323 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4614 13:17:59.284956 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4615 13:17:59.291387 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4616 13:17:59.291836
4617 13:17:59.292193
4618 13:17:59.294815 [Calibration Summary] 1200 Mbps
4619 13:17:59.295251 CH 0, Rank 0
4620 13:17:59.299335 SW Impedance : PASS
4621 13:17:59.301489 DUTY Scan : NO K
4622 13:17:59.301884 ZQ Calibration : PASS
4623 13:17:59.304893 Jitter Meter : NO K
4624 13:17:59.308622 CBT Training : PASS
4625 13:17:59.309095 Write leveling : PASS
4626 13:17:59.311791 RX DQS gating : PASS
4627 13:17:59.315163 RX DQ/DQS(RDDQC) : PASS
4628 13:17:59.315566 TX DQ/DQS : PASS
4629 13:17:59.318418 RX DATLAT : PASS
4630 13:17:59.318890 RX DQ/DQS(Engine): PASS
4631 13:17:59.321609 TX OE : NO K
4632 13:17:59.322121 All Pass.
4633 13:17:59.322431
4634 13:17:59.324612 CH 0, Rank 1
4635 13:17:59.324990 SW Impedance : PASS
4636 13:17:59.328243 DUTY Scan : NO K
4637 13:17:59.331295 ZQ Calibration : PASS
4638 13:17:59.331689 Jitter Meter : NO K
4639 13:17:59.335174 CBT Training : PASS
4640 13:17:59.338304 Write leveling : PASS
4641 13:17:59.338687 RX DQS gating : PASS
4642 13:17:59.341113 RX DQ/DQS(RDDQC) : PASS
4643 13:17:59.345001 TX DQ/DQS : PASS
4644 13:17:59.345414 RX DATLAT : PASS
4645 13:17:59.347662 RX DQ/DQS(Engine): PASS
4646 13:17:59.351293 TX OE : NO K
4647 13:17:59.351674 All Pass.
4648 13:17:59.351966
4649 13:17:59.352237 CH 1, Rank 0
4650 13:17:59.355327 SW Impedance : PASS
4651 13:17:59.358036 DUTY Scan : NO K
4652 13:17:59.358417 ZQ Calibration : PASS
4653 13:17:59.361543 Jitter Meter : NO K
4654 13:17:59.364616 CBT Training : PASS
4655 13:17:59.364998 Write leveling : PASS
4656 13:17:59.368456 RX DQS gating : PASS
4657 13:17:59.371159 RX DQ/DQS(RDDQC) : PASS
4658 13:17:59.371537 TX DQ/DQS : PASS
4659 13:17:59.374340 RX DATLAT : PASS
4660 13:17:59.377407 RX DQ/DQS(Engine): PASS
4661 13:17:59.377786 TX OE : NO K
4662 13:17:59.378085 All Pass.
4663 13:17:59.381160
4664 13:17:59.381573 CH 1, Rank 1
4665 13:17:59.384228 SW Impedance : PASS
4666 13:17:59.384650 DUTY Scan : NO K
4667 13:17:59.387833 ZQ Calibration : PASS
4668 13:17:59.390911 Jitter Meter : NO K
4669 13:17:59.391312 CBT Training : PASS
4670 13:17:59.394108 Write leveling : PASS
4671 13:17:59.394507 RX DQS gating : PASS
4672 13:17:59.397439 RX DQ/DQS(RDDQC) : PASS
4673 13:17:59.401326 TX DQ/DQS : PASS
4674 13:17:59.401727 RX DATLAT : PASS
4675 13:17:59.404294 RX DQ/DQS(Engine): PASS
4676 13:17:59.407357 TX OE : NO K
4677 13:17:59.407757 All Pass.
4678 13:17:59.408151
4679 13:17:59.411360 DramC Write-DBI off
4680 13:17:59.411738 PER_BANK_REFRESH: Hybrid Mode
4681 13:17:59.414094 TX_TRACKING: ON
4682 13:17:59.424441 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4683 13:17:59.428609 [FAST_K] Save calibration result to emmc
4684 13:17:59.430633 dramc_set_vcore_voltage set vcore to 662500
4685 13:17:59.431017 Read voltage for 933, 3
4686 13:17:59.434244 Vio18 = 0
4687 13:17:59.434621 Vcore = 662500
4688 13:17:59.434916 Vdram = 0
4689 13:17:59.437846 Vddq = 0
4690 13:17:59.438226 Vmddr = 0
4691 13:17:59.440607 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4692 13:17:59.447601 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4693 13:17:59.450474 MEM_TYPE=3, freq_sel=17
4694 13:17:59.453770 sv_algorithm_assistance_LP4_1600
4695 13:17:59.457646 ============ PULL DRAM RESETB DOWN ============
4696 13:17:59.460127 ========== PULL DRAM RESETB DOWN end =========
4697 13:17:59.466889 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4698 13:17:59.470325 ===================================
4699 13:17:59.470711 LPDDR4 DRAM CONFIGURATION
4700 13:17:59.473807 ===================================
4701 13:17:59.477108 EX_ROW_EN[0] = 0x0
4702 13:17:59.477558 EX_ROW_EN[1] = 0x0
4703 13:17:59.480921 LP4Y_EN = 0x0
4704 13:17:59.483620 WORK_FSP = 0x0
4705 13:17:59.484002 WL = 0x3
4706 13:17:59.486963 RL = 0x3
4707 13:17:59.487340 BL = 0x2
4708 13:17:59.490571 RPST = 0x0
4709 13:17:59.490955 RD_PRE = 0x0
4710 13:17:59.493570 WR_PRE = 0x1
4711 13:17:59.494008 WR_PST = 0x0
4712 13:17:59.496737 DBI_WR = 0x0
4713 13:17:59.497147 DBI_RD = 0x0
4714 13:17:59.499849 OTF = 0x1
4715 13:17:59.503651 ===================================
4716 13:17:59.506732 ===================================
4717 13:17:59.507130 ANA top config
4718 13:17:59.510033 ===================================
4719 13:17:59.513298 DLL_ASYNC_EN = 0
4720 13:17:59.516541 ALL_SLAVE_EN = 1
4721 13:17:59.516937 NEW_RANK_MODE = 1
4722 13:17:59.520406 DLL_IDLE_MODE = 1
4723 13:17:59.523784 LP45_APHY_COMB_EN = 1
4724 13:17:59.527434 TX_ODT_DIS = 1
4725 13:17:59.530189 NEW_8X_MODE = 1
4726 13:17:59.534231 ===================================
4727 13:17:59.534635 ===================================
4728 13:17:59.537400 data_rate = 1866
4729 13:17:59.540143 CKR = 1
4730 13:17:59.543220 DQ_P2S_RATIO = 8
4731 13:17:59.546848 ===================================
4732 13:17:59.549831 CA_P2S_RATIO = 8
4733 13:17:59.553139 DQ_CA_OPEN = 0
4734 13:17:59.556403 DQ_SEMI_OPEN = 0
4735 13:17:59.556901 CA_SEMI_OPEN = 0
4736 13:17:59.559985 CA_FULL_RATE = 0
4737 13:17:59.563038 DQ_CKDIV4_EN = 1
4738 13:17:59.566414 CA_CKDIV4_EN = 1
4739 13:17:59.569321 CA_PREDIV_EN = 0
4740 13:17:59.573192 PH8_DLY = 0
4741 13:17:59.573671 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4742 13:17:59.576602 DQ_AAMCK_DIV = 4
4743 13:17:59.579592 CA_AAMCK_DIV = 4
4744 13:17:59.583092 CA_ADMCK_DIV = 4
4745 13:17:59.586127 DQ_TRACK_CA_EN = 0
4746 13:17:59.590266 CA_PICK = 933
4747 13:17:59.593675 CA_MCKIO = 933
4748 13:17:59.594100 MCKIO_SEMI = 0
4749 13:17:59.596222 PLL_FREQ = 3732
4750 13:17:59.599436 DQ_UI_PI_RATIO = 32
4751 13:17:59.602854 CA_UI_PI_RATIO = 0
4752 13:17:59.606257 ===================================
4753 13:17:59.609842 ===================================
4754 13:17:59.612657 memory_type:LPDDR4
4755 13:17:59.613202 GP_NUM : 10
4756 13:17:59.616293 SRAM_EN : 1
4757 13:17:59.616732 MD32_EN : 0
4758 13:17:59.619921 ===================================
4759 13:17:59.623040 [ANA_INIT] >>>>>>>>>>>>>>
4760 13:17:59.626729 <<<<<< [CONFIGURE PHASE]: ANA_TX
4761 13:17:59.629317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4762 13:17:59.632680 ===================================
4763 13:17:59.635957 data_rate = 1866,PCW = 0X8f00
4764 13:17:59.639636 ===================================
4765 13:17:59.642636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4766 13:17:59.649654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4767 13:17:59.653146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4768 13:17:59.660516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4769 13:17:59.662793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4770 13:17:59.665699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4771 13:17:59.666122 [ANA_INIT] flow start
4772 13:17:59.669146 [ANA_INIT] PLL >>>>>>>>
4773 13:17:59.673163 [ANA_INIT] PLL <<<<<<<<
4774 13:17:59.673632 [ANA_INIT] MIDPI >>>>>>>>
4775 13:17:59.676152 [ANA_INIT] MIDPI <<<<<<<<
4776 13:17:59.678959 [ANA_INIT] DLL >>>>>>>>
4777 13:17:59.679396 [ANA_INIT] flow end
4778 13:17:59.685584 ============ LP4 DIFF to SE enter ============
4779 13:17:59.689561 ============ LP4 DIFF to SE exit ============
4780 13:17:59.692728 [ANA_INIT] <<<<<<<<<<<<<
4781 13:17:59.695541 [Flow] Enable top DCM control >>>>>
4782 13:17:59.699340 [Flow] Enable top DCM control <<<<<
4783 13:17:59.699480 Enable DLL master slave shuffle
4784 13:17:59.705081 ==============================================================
4785 13:17:59.708877 Gating Mode config
4786 13:17:59.714280 ==============================================================
4787 13:17:59.715664 Config description:
4788 13:17:59.725935 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4789 13:17:59.732648 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4790 13:17:59.736294 SELPH_MODE 0: By rank 1: By Phase
4791 13:17:59.742454 ==============================================================
4792 13:17:59.745445 GAT_TRACK_EN = 1
4793 13:17:59.749204 RX_GATING_MODE = 2
4794 13:17:59.752774 RX_GATING_TRACK_MODE = 2
4795 13:17:59.755687 SELPH_MODE = 1
4796 13:17:59.756114 PICG_EARLY_EN = 1
4797 13:17:59.758871 VALID_LAT_VALUE = 1
4798 13:17:59.765488 ==============================================================
4799 13:17:59.769028 Enter into Gating configuration >>>>
4800 13:17:59.772380 Exit from Gating configuration <<<<
4801 13:17:59.776195 Enter into DVFS_PRE_config >>>>>
4802 13:17:59.786268 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4803 13:17:59.788684 Exit from DVFS_PRE_config <<<<<
4804 13:17:59.792523 Enter into PICG configuration >>>>
4805 13:17:59.795419 Exit from PICG configuration <<<<
4806 13:17:59.798329 [RX_INPUT] configuration >>>>>
4807 13:17:59.801721 [RX_INPUT] configuration <<<<<
4808 13:17:59.804892 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4809 13:17:59.812260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4810 13:17:59.818896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4811 13:17:59.825220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4812 13:17:59.831467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4813 13:17:59.837987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4814 13:17:59.841456 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4815 13:17:59.844631 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4816 13:17:59.847814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4817 13:17:59.854337 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4818 13:17:59.857983 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4819 13:17:59.861530 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4820 13:17:59.864740 ===================================
4821 13:17:59.867743 LPDDR4 DRAM CONFIGURATION
4822 13:17:59.871484 ===================================
4823 13:17:59.871873 EX_ROW_EN[0] = 0x0
4824 13:17:59.874915 EX_ROW_EN[1] = 0x0
4825 13:17:59.875356 LP4Y_EN = 0x0
4826 13:17:59.877696 WORK_FSP = 0x0
4827 13:17:59.878084 WL = 0x3
4828 13:17:59.880988 RL = 0x3
4829 13:17:59.884889 BL = 0x2
4830 13:17:59.885323 RPST = 0x0
4831 13:17:59.888434 RD_PRE = 0x0
4832 13:17:59.888896 WR_PRE = 0x1
4833 13:17:59.891148 WR_PST = 0x0
4834 13:17:59.891533 DBI_WR = 0x0
4835 13:17:59.894863 DBI_RD = 0x0
4836 13:17:59.895292 OTF = 0x1
4837 13:17:59.897601 ===================================
4838 13:17:59.901002 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4839 13:17:59.907773 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4840 13:17:59.911019 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4841 13:17:59.914588 ===================================
4842 13:17:59.917567 LPDDR4 DRAM CONFIGURATION
4843 13:17:59.921143 ===================================
4844 13:17:59.921627 EX_ROW_EN[0] = 0x10
4845 13:17:59.924704 EX_ROW_EN[1] = 0x0
4846 13:17:59.925113 LP4Y_EN = 0x0
4847 13:17:59.928408 WORK_FSP = 0x0
4848 13:17:59.928872 WL = 0x3
4849 13:17:59.930768 RL = 0x3
4850 13:17:59.931157 BL = 0x2
4851 13:17:59.934616 RPST = 0x0
4852 13:17:59.937656 RD_PRE = 0x0
4853 13:17:59.938045 WR_PRE = 0x1
4854 13:17:59.940944 WR_PST = 0x0
4855 13:17:59.941413 DBI_WR = 0x0
4856 13:17:59.944294 DBI_RD = 0x0
4857 13:17:59.944689 OTF = 0x1
4858 13:17:59.949012 ===================================
4859 13:17:59.953669 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4860 13:17:59.958415 nWR fixed to 30
4861 13:17:59.961730 [ModeRegInit_LP4] CH0 RK0
4862 13:17:59.962116 [ModeRegInit_LP4] CH0 RK1
4863 13:17:59.965532 [ModeRegInit_LP4] CH1 RK0
4864 13:17:59.967865 [ModeRegInit_LP4] CH1 RK1
4865 13:17:59.968255 match AC timing 8
4866 13:17:59.974161 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4867 13:17:59.977892 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4868 13:17:59.980986 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4869 13:17:59.987747 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4870 13:17:59.991398 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4871 13:17:59.991834 ==
4872 13:17:59.994675 Dram Type= 6, Freq= 0, CH_0, rank 0
4873 13:17:59.997924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4874 13:17:59.998363 ==
4875 13:18:00.004280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4876 13:18:00.010955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4877 13:18:00.014196 [CA 0] Center 38 (8~69) winsize 62
4878 13:18:00.017324 [CA 1] Center 38 (8~69) winsize 62
4879 13:18:00.020639 [CA 2] Center 36 (6~67) winsize 62
4880 13:18:00.025194 [CA 3] Center 36 (6~67) winsize 62
4881 13:18:00.027574 [CA 4] Center 34 (4~65) winsize 62
4882 13:18:00.030941 [CA 5] Center 34 (4~65) winsize 62
4883 13:18:00.031502
4884 13:18:00.034158 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4885 13:18:00.034620
4886 13:18:00.037459 [CATrainingPosCal] consider 1 rank data
4887 13:18:00.041379 u2DelayCellTimex100 = 270/100 ps
4888 13:18:00.044809 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4889 13:18:00.047708 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4890 13:18:00.050877 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4891 13:18:00.054120 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4892 13:18:00.057723 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4893 13:18:00.064148 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4894 13:18:00.064762
4895 13:18:00.067167 CA PerBit enable=1, Macro0, CA PI delay=34
4896 13:18:00.067601
4897 13:18:00.070435 [CBTSetCACLKResult] CA Dly = 34
4898 13:18:00.070902 CS Dly: 7 (0~38)
4899 13:18:00.071343 ==
4900 13:18:00.073992 Dram Type= 6, Freq= 0, CH_0, rank 1
4901 13:18:00.077510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 13:18:00.080984 ==
4903 13:18:00.084129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4904 13:18:00.090278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4905 13:18:00.093891 [CA 0] Center 38 (8~69) winsize 62
4906 13:18:00.098270 [CA 1] Center 38 (7~69) winsize 63
4907 13:18:00.101118 [CA 2] Center 36 (5~67) winsize 63
4908 13:18:00.104342 [CA 3] Center 35 (5~66) winsize 62
4909 13:18:00.107224 [CA 4] Center 34 (4~65) winsize 62
4910 13:18:00.110352 [CA 5] Center 34 (4~65) winsize 62
4911 13:18:00.110731
4912 13:18:00.113633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4913 13:18:00.114015
4914 13:18:00.117394 [CATrainingPosCal] consider 2 rank data
4915 13:18:00.120606 u2DelayCellTimex100 = 270/100 ps
4916 13:18:00.124092 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4917 13:18:00.127421 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4918 13:18:00.130484 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4919 13:18:00.134208 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4920 13:18:00.140259 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4921 13:18:00.143858 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4922 13:18:00.144353
4923 13:18:00.147312 CA PerBit enable=1, Macro0, CA PI delay=34
4924 13:18:00.147832
4925 13:18:00.150820 [CBTSetCACLKResult] CA Dly = 34
4926 13:18:00.151253 CS Dly: 7 (0~39)
4927 13:18:00.151582
4928 13:18:00.154085 ----->DramcWriteLeveling(PI) begin...
4929 13:18:00.154520 ==
4930 13:18:00.157647 Dram Type= 6, Freq= 0, CH_0, rank 0
4931 13:18:00.163718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4932 13:18:00.164156 ==
4933 13:18:00.167589 Write leveling (Byte 0): 28 => 28
4934 13:18:00.168087 Write leveling (Byte 1): 28 => 28
4935 13:18:00.170997 DramcWriteLeveling(PI) end<-----
4936 13:18:00.171647
4937 13:18:00.173808 ==
4938 13:18:00.174325 Dram Type= 6, Freq= 0, CH_0, rank 0
4939 13:18:00.181107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4940 13:18:00.181631 ==
4941 13:18:00.183814 [Gating] SW mode calibration
4942 13:18:00.190122 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4943 13:18:00.193503 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4944 13:18:00.200338 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4945 13:18:00.203913 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4946 13:18:00.207068 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4947 13:18:00.213331 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4948 13:18:00.216634 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4949 13:18:00.220918 0 10 20 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
4950 13:18:00.226883 0 10 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
4951 13:18:00.231592 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4952 13:18:00.233356 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4953 13:18:00.239778 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4954 13:18:00.243719 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4955 13:18:00.247044 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4956 13:18:00.253904 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4957 13:18:00.257272 0 11 20 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
4958 13:18:00.260012 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4959 13:18:00.264086 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4960 13:18:00.269990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4961 13:18:00.273141 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4962 13:18:00.276327 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4963 13:18:00.283778 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4964 13:18:00.286475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4965 13:18:00.289702 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4966 13:18:00.296831 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4967 13:18:00.299669 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4968 13:18:00.303048 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4969 13:18:00.309783 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4970 13:18:00.313367 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4971 13:18:00.316161 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4972 13:18:00.322915 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4973 13:18:00.326067 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4974 13:18:00.329518 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4975 13:18:00.336561 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4976 13:18:00.339361 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4977 13:18:00.343024 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4978 13:18:00.349057 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4979 13:18:00.352948 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4980 13:18:00.356489 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4981 13:18:00.362852 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4982 13:18:00.366738 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 13:18:00.369158 Total UI for P1: 0, mck2ui 16
4984 13:18:00.373101 best dqsien dly found for B0: ( 0, 14, 20)
4985 13:18:00.375839 Total UI for P1: 0, mck2ui 16
4986 13:18:00.379581 best dqsien dly found for B1: ( 0, 14, 20)
4987 13:18:00.382570 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4988 13:18:00.385979 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4989 13:18:00.386415
4990 13:18:00.389610 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4991 13:18:00.393267 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4992 13:18:00.396305 [Gating] SW calibration Done
4993 13:18:00.396817 ==
4994 13:18:00.399380 Dram Type= 6, Freq= 0, CH_0, rank 0
4995 13:18:00.403780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4996 13:18:00.405899 ==
4997 13:18:00.406341 RX Vref Scan: 0
4998 13:18:00.406784
4999 13:18:00.409401 RX Vref 0 -> 0, step: 1
5000 13:18:00.409838
5001 13:18:00.412510 RX Delay -80 -> 252, step: 8
5002 13:18:00.415612 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5003 13:18:00.420469 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5004 13:18:00.422599 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5005 13:18:00.425572 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5006 13:18:00.429384 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5007 13:18:00.435683 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5008 13:18:00.438510 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5009 13:18:00.441750 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5010 13:18:00.445345 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5011 13:18:00.449340 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5012 13:18:00.455510 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5013 13:18:00.458699 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5014 13:18:00.462961 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5015 13:18:00.465266 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5016 13:18:00.469012 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5017 13:18:00.475540 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5018 13:18:00.475770 ==
5019 13:18:00.479739 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 13:18:00.482055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5021 13:18:00.482380 ==
5022 13:18:00.482591 DQS Delay:
5023 13:18:00.485381 DQS0 = 0, DQS1 = 0
5024 13:18:00.485697 DQM Delay:
5025 13:18:00.488878 DQM0 = 95, DQM1 = 84
5026 13:18:00.489254 DQ Delay:
5027 13:18:00.492070 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5028 13:18:00.495556 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5029 13:18:00.498727 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5030 13:18:00.502353 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5031 13:18:00.502777
5032 13:18:00.503101
5033 13:18:00.503401 ==
5034 13:18:00.506043 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 13:18:00.508501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5036 13:18:00.508940 ==
5037 13:18:00.509323
5038 13:18:00.512345
5039 13:18:00.512765 TX Vref Scan disable
5040 13:18:00.516038 == TX Byte 0 ==
5041 13:18:00.519014 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5042 13:18:00.521928 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5043 13:18:00.525072 == TX Byte 1 ==
5044 13:18:00.529118 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5045 13:18:00.532062 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5046 13:18:00.532490 ==
5047 13:18:00.535101 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 13:18:00.542186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5049 13:18:00.542680 ==
5050 13:18:00.543084
5051 13:18:00.543391
5052 13:18:00.543683 TX Vref Scan disable
5053 13:18:00.545833 == TX Byte 0 ==
5054 13:18:00.549622 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5055 13:18:00.555935 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5056 13:18:00.556367 == TX Byte 1 ==
5057 13:18:00.559490 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5058 13:18:00.566376 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5059 13:18:00.566820
5060 13:18:00.567253 [DATLAT]
5061 13:18:00.567657 Freq=933, CH0 RK0
5062 13:18:00.568084
5063 13:18:00.569603 DATLAT Default: 0xd
5064 13:18:00.570028 0, 0xFFFF, sum = 0
5065 13:18:00.572886 1, 0xFFFF, sum = 0
5066 13:18:00.573396 2, 0xFFFF, sum = 0
5067 13:18:00.575980 3, 0xFFFF, sum = 0
5068 13:18:00.580701 4, 0xFFFF, sum = 0
5069 13:18:00.581315 5, 0xFFFF, sum = 0
5070 13:18:00.582726 6, 0xFFFF, sum = 0
5071 13:18:00.583184 7, 0xFFFF, sum = 0
5072 13:18:00.586118 8, 0xFFFF, sum = 0
5073 13:18:00.586550 9, 0xFFFF, sum = 0
5074 13:18:00.589104 10, 0x0, sum = 1
5075 13:18:00.589589 11, 0x0, sum = 2
5076 13:18:00.592743 12, 0x0, sum = 3
5077 13:18:00.593318 13, 0x0, sum = 4
5078 13:18:00.593679 best_step = 11
5079 13:18:00.593984
5080 13:18:00.595826 ==
5081 13:18:00.599844 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 13:18:00.602448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5083 13:18:00.602882 ==
5084 13:18:00.603209 RX Vref Scan: 1
5085 13:18:00.603509
5086 13:18:00.605965 RX Vref 0 -> 0, step: 1
5087 13:18:00.606391
5088 13:18:00.609343 RX Delay -69 -> 252, step: 4
5089 13:18:00.609771
5090 13:18:00.612664 Set Vref, RX VrefLevel [Byte0]: 48
5091 13:18:00.615975 [Byte1]: 50
5092 13:18:00.616412
5093 13:18:00.619332 Final RX Vref Byte 0 = 48 to rank0
5094 13:18:00.622413 Final RX Vref Byte 1 = 50 to rank0
5095 13:18:00.625709 Final RX Vref Byte 0 = 48 to rank1
5096 13:18:00.629023 Final RX Vref Byte 1 = 50 to rank1==
5097 13:18:00.632445 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 13:18:00.635649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5099 13:18:00.639455 ==
5100 13:18:00.639875 DQS Delay:
5101 13:18:00.640198 DQS0 = 0, DQS1 = 0
5102 13:18:00.641917 DQM Delay:
5103 13:18:00.642418 DQM0 = 96, DQM1 = 87
5104 13:18:00.645925 DQ Delay:
5105 13:18:00.646389 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5106 13:18:00.649463 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5107 13:18:00.651897 DQ8 =78, DQ9 =70, DQ10 =88, DQ11 =80
5108 13:18:00.659070 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =98
5109 13:18:00.659534
5110 13:18:00.659860
5111 13:18:00.665852 [DQSOSCAuto] RK0, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5112 13:18:00.670024 CH0 RK0: MR19=505, MR18=2020
5113 13:18:00.675697 CH0_RK0: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5114 13:18:00.676131
5115 13:18:00.678919 ----->DramcWriteLeveling(PI) begin...
5116 13:18:00.679350 ==
5117 13:18:00.681999 Dram Type= 6, Freq= 0, CH_0, rank 1
5118 13:18:00.685347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5119 13:18:00.685776 ==
5120 13:18:00.689326 Write leveling (Byte 0): 29 => 29
5121 13:18:00.691765 Write leveling (Byte 1): 27 => 27
5122 13:18:00.696017 DramcWriteLeveling(PI) end<-----
5123 13:18:00.696490
5124 13:18:00.696823 ==
5125 13:18:00.699101 Dram Type= 6, Freq= 0, CH_0, rank 1
5126 13:18:00.701856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5127 13:18:00.702392 ==
5128 13:18:00.705513 [Gating] SW mode calibration
5129 13:18:00.711658 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5130 13:18:00.718473 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5131 13:18:00.722117 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 13:18:00.728137 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 13:18:00.732038 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 13:18:00.734835 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 13:18:00.738443 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 13:18:00.745954 0 10 20 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
5137 13:18:00.748605 0 10 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5138 13:18:00.751461 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 13:18:00.758470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 13:18:00.761531 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 13:18:00.765348 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 13:18:00.772027 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 13:18:00.774637 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5144 13:18:00.777846 0 11 20 | B1->B0 | 2a2a 3535 | 1 0 | (0 0) (1 1)
5145 13:18:00.784409 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5146 13:18:00.788402 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 13:18:00.791781 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 13:18:00.797907 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 13:18:00.800998 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 13:18:00.805032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 13:18:00.811135 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 13:18:00.814656 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5153 13:18:00.817942 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5154 13:18:00.824767 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:18:00.827818 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:18:00.831582 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:18:00.837400 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:18:00.842001 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:18:00.844174 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:18:00.852090 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:18:00.854170 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 13:18:00.857750 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 13:18:00.863991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 13:18:00.867545 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 13:18:00.870854 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 13:18:00.877807 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 13:18:00.880694 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 13:18:00.883956 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5169 13:18:00.890471 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 13:18:00.890860 Total UI for P1: 0, mck2ui 16
5171 13:18:00.897134 best dqsien dly found for B0: ( 0, 14, 20)
5172 13:18:00.897571 Total UI for P1: 0, mck2ui 16
5173 13:18:00.900578 best dqsien dly found for B1: ( 0, 14, 20)
5174 13:18:00.907405 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5175 13:18:00.910701 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5176 13:18:00.911082
5177 13:18:00.913904 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5178 13:18:00.917285 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5179 13:18:00.921145 [Gating] SW calibration Done
5180 13:18:00.921721 ==
5181 13:18:00.923817 Dram Type= 6, Freq= 0, CH_0, rank 1
5182 13:18:00.927253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5183 13:18:00.927819 ==
5184 13:18:00.931915 RX Vref Scan: 0
5185 13:18:00.932341
5186 13:18:00.932654 RX Vref 0 -> 0, step: 1
5187 13:18:00.932928
5188 13:18:00.934300 RX Delay -80 -> 252, step: 8
5189 13:18:00.937313 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5190 13:18:00.943709 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5191 13:18:00.947184 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5192 13:18:00.950845 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5193 13:18:00.953875 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5194 13:18:00.957340 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5195 13:18:00.960539 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5196 13:18:00.966939 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5197 13:18:00.970107 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5198 13:18:00.973303 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5199 13:18:00.976824 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5200 13:18:00.980227 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5201 13:18:00.983348 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5202 13:18:00.990207 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5203 13:18:00.993446 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5204 13:18:00.997060 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5205 13:18:00.997530 ==
5206 13:18:01.000344 Dram Type= 6, Freq= 0, CH_0, rank 1
5207 13:18:01.003278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5208 13:18:01.003687 ==
5209 13:18:01.006600 DQS Delay:
5210 13:18:01.007104 DQS0 = 0, DQS1 = 0
5211 13:18:01.009969 DQM Delay:
5212 13:18:01.010434 DQM0 = 96, DQM1 = 85
5213 13:18:01.010733 DQ Delay:
5214 13:18:01.013209 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5215 13:18:01.016625 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5216 13:18:01.020116 DQ8 =71, DQ9 =67, DQ10 =87, DQ11 =75
5217 13:18:01.023804 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5218 13:18:01.024234
5219 13:18:01.024529
5220 13:18:01.026505 ==
5221 13:18:01.029728 Dram Type= 6, Freq= 0, CH_0, rank 1
5222 13:18:01.033659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5223 13:18:01.034227 ==
5224 13:18:01.034612
5225 13:18:01.034893
5226 13:18:01.036399 TX Vref Scan disable
5227 13:18:01.036779 == TX Byte 0 ==
5228 13:18:01.039820 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5229 13:18:01.046482 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5230 13:18:01.046917 == TX Byte 1 ==
5231 13:18:01.053104 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5232 13:18:01.056033 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5233 13:18:01.056110 ==
5234 13:18:01.059342 Dram Type= 6, Freq= 0, CH_0, rank 1
5235 13:18:01.062711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5236 13:18:01.062846 ==
5237 13:18:01.062912
5238 13:18:01.062971
5239 13:18:01.066062 TX Vref Scan disable
5240 13:18:01.069347 == TX Byte 0 ==
5241 13:18:01.072814 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5242 13:18:01.076250 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5243 13:18:01.079218 == TX Byte 1 ==
5244 13:18:01.083174 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5245 13:18:01.086089 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5246 13:18:01.086190
5247 13:18:01.090087 [DATLAT]
5248 13:18:01.090249 Freq=933, CH0 RK1
5249 13:18:01.090334
5250 13:18:01.092683 DATLAT Default: 0xb
5251 13:18:01.092855 0, 0xFFFF, sum = 0
5252 13:18:01.096157 1, 0xFFFF, sum = 0
5253 13:18:01.096350 2, 0xFFFF, sum = 0
5254 13:18:01.099561 3, 0xFFFF, sum = 0
5255 13:18:01.099750 4, 0xFFFF, sum = 0
5256 13:18:01.102856 5, 0xFFFF, sum = 0
5257 13:18:01.103061 6, 0xFFFF, sum = 0
5258 13:18:01.105633 7, 0xFFFF, sum = 0
5259 13:18:01.105858 8, 0xFFFF, sum = 0
5260 13:18:01.109831 9, 0xFFFF, sum = 0
5261 13:18:01.109991 10, 0x0, sum = 1
5262 13:18:01.112443 11, 0x0, sum = 2
5263 13:18:01.112695 12, 0x0, sum = 3
5264 13:18:01.115698 13, 0x0, sum = 4
5265 13:18:01.115924 best_step = 11
5266 13:18:01.116092
5267 13:18:01.116248 ==
5268 13:18:01.119929 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 13:18:01.126244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5270 13:18:01.126680 ==
5271 13:18:01.126954 RX Vref Scan: 0
5272 13:18:01.127205
5273 13:18:01.129566 RX Vref 0 -> 0, step: 1
5274 13:18:01.130135
5275 13:18:01.133114 RX Delay -77 -> 252, step: 4
5276 13:18:01.136060 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5277 13:18:01.139392 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5278 13:18:01.146447 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5279 13:18:01.149361 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5280 13:18:01.152571 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5281 13:18:01.155531 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5282 13:18:01.159157 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5283 13:18:01.162463 iDelay=203, Bit 7, Center 110 (19 ~ 202) 184
5284 13:18:01.169178 iDelay=203, Bit 8, Center 78 (-9 ~ 166) 176
5285 13:18:01.172463 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5286 13:18:01.175907 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5287 13:18:01.179440 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5288 13:18:01.182038 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5289 13:18:01.189076 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5290 13:18:01.192742 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5291 13:18:01.196392 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5292 13:18:01.196884 ==
5293 13:18:01.199011 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 13:18:01.202201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5295 13:18:01.202716 ==
5296 13:18:01.206037 DQS Delay:
5297 13:18:01.206678 DQS0 = 0, DQS1 = 0
5298 13:18:01.207168 DQM Delay:
5299 13:18:01.209535 DQM0 = 97, DQM1 = 86
5300 13:18:01.209957 DQ Delay:
5301 13:18:01.212770 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5302 13:18:01.215878 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =110
5303 13:18:01.218632 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5304 13:18:01.222625 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5305 13:18:01.223135
5306 13:18:01.223460
5307 13:18:01.232075 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5308 13:18:01.236465 CH0 RK1: MR19=505, MR18=2A2A
5309 13:18:01.239221 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5310 13:18:01.242093 [RxdqsGatingPostProcess] freq 933
5311 13:18:01.248673 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5312 13:18:01.252111 Pre-setting of DQS Precalculation
5313 13:18:01.255919 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5314 13:18:01.256423 ==
5315 13:18:01.259041 Dram Type= 6, Freq= 0, CH_1, rank 0
5316 13:18:01.265790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5317 13:18:01.266293 ==
5318 13:18:01.269595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5319 13:18:01.275358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5320 13:18:01.279282 [CA 0] Center 37 (6~68) winsize 63
5321 13:18:01.281695 [CA 1] Center 37 (6~68) winsize 63
5322 13:18:01.285184 [CA 2] Center 34 (4~65) winsize 62
5323 13:18:01.288257 [CA 3] Center 34 (4~65) winsize 62
5324 13:18:01.292088 [CA 4] Center 33 (2~64) winsize 63
5325 13:18:01.295045 [CA 5] Center 33 (3~64) winsize 62
5326 13:18:01.295467
5327 13:18:01.298775 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5328 13:18:01.299251
5329 13:18:01.301900 [CATrainingPosCal] consider 1 rank data
5330 13:18:01.305541 u2DelayCellTimex100 = 270/100 ps
5331 13:18:01.308310 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5332 13:18:01.314710 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5333 13:18:01.318848 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5334 13:18:01.321392 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5335 13:18:01.325416 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5336 13:18:01.328493 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5337 13:18:01.329006
5338 13:18:01.331936 CA PerBit enable=1, Macro0, CA PI delay=33
5339 13:18:01.332384
5340 13:18:01.335634 [CBTSetCACLKResult] CA Dly = 33
5341 13:18:01.338020 CS Dly: 5 (0~36)
5342 13:18:01.338436 ==
5343 13:18:01.341685 Dram Type= 6, Freq= 0, CH_1, rank 1
5344 13:18:01.345428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5345 13:18:01.345855 ==
5346 13:18:01.351542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5347 13:18:01.354679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5348 13:18:01.358466 [CA 0] Center 37 (6~68) winsize 63
5349 13:18:01.361611 [CA 1] Center 37 (6~68) winsize 63
5350 13:18:01.364887 [CA 2] Center 34 (4~65) winsize 62
5351 13:18:01.368188 [CA 3] Center 34 (4~64) winsize 61
5352 13:18:01.371674 [CA 4] Center 33 (2~64) winsize 63
5353 13:18:01.374637 [CA 5] Center 32 (2~63) winsize 62
5354 13:18:01.374933
5355 13:18:01.378431 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5356 13:18:01.378723
5357 13:18:01.381405 [CATrainingPosCal] consider 2 rank data
5358 13:18:01.384463 u2DelayCellTimex100 = 270/100 ps
5359 13:18:01.388203 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5360 13:18:01.394699 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5361 13:18:01.398580 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5362 13:18:01.401462 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5363 13:18:01.406560 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5364 13:18:01.408073 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5365 13:18:01.408237
5366 13:18:01.410726 CA PerBit enable=1, Macro0, CA PI delay=33
5367 13:18:01.410890
5368 13:18:01.414207 [CBTSetCACLKResult] CA Dly = 33
5369 13:18:01.417623 CS Dly: 5 (0~37)
5370 13:18:01.417917
5371 13:18:01.421434 ----->DramcWriteLeveling(PI) begin...
5372 13:18:01.421730 ==
5373 13:18:01.424297 Dram Type= 6, Freq= 0, CH_1, rank 0
5374 13:18:01.427824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5375 13:18:01.428206 ==
5376 13:18:01.432346 Write leveling (Byte 0): 25 => 25
5377 13:18:01.434332 Write leveling (Byte 1): 25 => 25
5378 13:18:01.437698 DramcWriteLeveling(PI) end<-----
5379 13:18:01.438251
5380 13:18:01.438727 ==
5381 13:18:01.440720 Dram Type= 6, Freq= 0, CH_1, rank 0
5382 13:18:01.444442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5383 13:18:01.445124 ==
5384 13:18:01.448115 [Gating] SW mode calibration
5385 13:18:01.454348 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5386 13:18:01.461454 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5387 13:18:01.464933 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 13:18:01.467730 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 13:18:01.474452 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 13:18:01.477710 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 13:18:01.480786 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (0 1)
5392 13:18:01.487492 0 10 20 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
5393 13:18:01.490941 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5394 13:18:01.493862 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 13:18:01.501272 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 13:18:01.505743 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 13:18:01.507699 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 13:18:01.514070 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 13:18:01.517491 0 11 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
5400 13:18:01.521012 0 11 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
5401 13:18:01.527323 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5402 13:18:01.530527 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 13:18:01.533649 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 13:18:01.540743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 13:18:01.544176 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 13:18:01.546822 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 13:18:01.553539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5408 13:18:01.557169 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5409 13:18:01.560507 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 13:18:01.567269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 13:18:01.571046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 13:18:01.573559 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 13:18:01.580537 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 13:18:01.583270 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 13:18:01.586896 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 13:18:01.593736 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 13:18:01.596511 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 13:18:01.600344 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 13:18:01.607725 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 13:18:01.610292 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 13:18:01.613606 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 13:18:01.617010 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 13:18:01.623969 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 13:18:01.627035 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 13:18:01.630321 Total UI for P1: 0, mck2ui 16
5426 13:18:01.633353 best dqsien dly found for B0: ( 0, 14, 18)
5427 13:18:01.636667 Total UI for P1: 0, mck2ui 16
5428 13:18:01.640645 best dqsien dly found for B1: ( 0, 14, 18)
5429 13:18:01.643443 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5430 13:18:01.646734 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5431 13:18:01.647226
5432 13:18:01.650119 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5433 13:18:01.657004 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5434 13:18:01.657700 [Gating] SW calibration Done
5435 13:18:01.658216 ==
5436 13:18:01.660224 Dram Type= 6, Freq= 0, CH_1, rank 0
5437 13:18:01.666142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5438 13:18:01.666652 ==
5439 13:18:01.666984 RX Vref Scan: 0
5440 13:18:01.667290
5441 13:18:01.670025 RX Vref 0 -> 0, step: 1
5442 13:18:01.670450
5443 13:18:01.673807 RX Delay -80 -> 252, step: 8
5444 13:18:01.677584 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5445 13:18:01.679975 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5446 13:18:01.683248 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5447 13:18:01.686585 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5448 13:18:01.693257 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5449 13:18:01.697340 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5450 13:18:01.700065 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5451 13:18:01.703372 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5452 13:18:01.706303 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5453 13:18:01.709651 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5454 13:18:01.716565 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5455 13:18:01.719565 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5456 13:18:01.723057 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5457 13:18:01.726239 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5458 13:18:01.729858 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5459 13:18:01.736494 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5460 13:18:01.737000 ==
5461 13:18:01.739295 Dram Type= 6, Freq= 0, CH_1, rank 0
5462 13:18:01.743058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5463 13:18:01.743563 ==
5464 13:18:01.743894 DQS Delay:
5465 13:18:01.746211 DQS0 = 0, DQS1 = 0
5466 13:18:01.746636 DQM Delay:
5467 13:18:01.750229 DQM0 = 95, DQM1 = 87
5468 13:18:01.750729 DQ Delay:
5469 13:18:01.752436 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5470 13:18:01.756221 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5471 13:18:01.759965 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5472 13:18:01.762734 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5473 13:18:01.763164
5474 13:18:01.763493
5475 13:18:01.763798 ==
5476 13:18:01.765728 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 13:18:01.769308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5478 13:18:01.769742 ==
5479 13:18:01.772608
5480 13:18:01.773034
5481 13:18:01.773412 TX Vref Scan disable
5482 13:18:01.776556 == TX Byte 0 ==
5483 13:18:01.779319 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5484 13:18:01.782978 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5485 13:18:01.786231 == TX Byte 1 ==
5486 13:18:01.789100 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5487 13:18:01.793285 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5488 13:18:01.793757 ==
5489 13:18:01.796536 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 13:18:01.803055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5491 13:18:01.803526 ==
5492 13:18:01.803856
5493 13:18:01.804225
5494 13:18:01.804744 TX Vref Scan disable
5495 13:18:01.806495 == TX Byte 0 ==
5496 13:18:01.811447 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5497 13:18:01.813603 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5498 13:18:01.816838 == TX Byte 1 ==
5499 13:18:01.820235 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5500 13:18:01.826608 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5501 13:18:01.827107
5502 13:18:01.827538 [DATLAT]
5503 13:18:01.827979 Freq=933, CH1 RK0
5504 13:18:01.828436
5505 13:18:01.830137 DATLAT Default: 0xd
5506 13:18:01.830712 0, 0xFFFF, sum = 0
5507 13:18:01.833352 1, 0xFFFF, sum = 0
5508 13:18:01.833787 2, 0xFFFF, sum = 0
5509 13:18:01.836852 3, 0xFFFF, sum = 0
5510 13:18:01.840668 4, 0xFFFF, sum = 0
5511 13:18:01.841349 5, 0xFFFF, sum = 0
5512 13:18:01.843531 6, 0xFFFF, sum = 0
5513 13:18:01.844185 7, 0xFFFF, sum = 0
5514 13:18:01.846489 8, 0xFFFF, sum = 0
5515 13:18:01.846927 9, 0xFFFF, sum = 0
5516 13:18:01.850663 10, 0x0, sum = 1
5517 13:18:01.851267 11, 0x0, sum = 2
5518 13:18:01.853099 12, 0x0, sum = 3
5519 13:18:01.853573 13, 0x0, sum = 4
5520 13:18:01.853909 best_step = 11
5521 13:18:01.854215
5522 13:18:01.857611 ==
5523 13:18:01.859583 Dram Type= 6, Freq= 0, CH_1, rank 0
5524 13:18:01.863490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5525 13:18:01.864004 ==
5526 13:18:01.864451 RX Vref Scan: 1
5527 13:18:01.864941
5528 13:18:01.866926 RX Vref 0 -> 0, step: 1
5529 13:18:01.867351
5530 13:18:01.869583 RX Delay -69 -> 252, step: 4
5531 13:18:01.870007
5532 13:18:01.873726 Set Vref, RX VrefLevel [Byte0]: 55
5533 13:18:01.876522 [Byte1]: 49
5534 13:18:01.876952
5535 13:18:01.879801 Final RX Vref Byte 0 = 55 to rank0
5536 13:18:01.883372 Final RX Vref Byte 1 = 49 to rank0
5537 13:18:01.886596 Final RX Vref Byte 0 = 55 to rank1
5538 13:18:01.889732 Final RX Vref Byte 1 = 49 to rank1==
5539 13:18:01.893447 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 13:18:01.896363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5541 13:18:01.896797 ==
5542 13:18:01.900117 DQS Delay:
5543 13:18:01.900691 DQS0 = 0, DQS1 = 0
5544 13:18:01.902857 DQM Delay:
5545 13:18:01.903288 DQM0 = 94, DQM1 = 87
5546 13:18:01.903616 DQ Delay:
5547 13:18:01.906235 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5548 13:18:01.909465 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5549 13:18:01.913044 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5550 13:18:01.916004 DQ12 =94, DQ13 =98, DQ14 =94, DQ15 =98
5551 13:18:01.920623
5552 13:18:01.921284
5553 13:18:01.925877 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x505, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
5554 13:18:01.929372 CH1 RK0: MR19=505, MR18=3A3A
5555 13:18:01.935723 CH1_RK0: MR19=0x505, MR18=0x3A3A, DQSOSC=403, MR23=63, INC=66, DEC=44
5556 13:18:01.936198
5557 13:18:01.939868 ----->DramcWriteLeveling(PI) begin...
5558 13:18:01.940304 ==
5559 13:18:01.942563 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 13:18:01.946009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5561 13:18:01.946444 ==
5562 13:18:01.949429 Write leveling (Byte 0): 23 => 23
5563 13:18:01.952834 Write leveling (Byte 1): 23 => 23
5564 13:18:01.956114 DramcWriteLeveling(PI) end<-----
5565 13:18:01.956619
5566 13:18:01.957051 ==
5567 13:18:01.959119 Dram Type= 6, Freq= 0, CH_1, rank 1
5568 13:18:01.962910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5569 13:18:01.963546 ==
5570 13:18:01.965913 [Gating] SW mode calibration
5571 13:18:01.971921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5572 13:18:01.979361 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5573 13:18:01.982447 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 13:18:01.988862 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 13:18:01.992022 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 13:18:01.995582 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5577 13:18:02.001816 0 10 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
5578 13:18:02.005922 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5579 13:18:02.008643 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 13:18:02.015091 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 13:18:02.018355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 13:18:02.022207 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 13:18:02.025024 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 13:18:02.031693 0 11 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
5585 13:18:02.034791 0 11 16 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
5586 13:18:02.038826 0 11 20 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
5587 13:18:02.044565 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 13:18:02.048198 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 13:18:02.051809 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 13:18:02.058502 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 13:18:02.061801 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 13:18:02.064736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5593 13:18:02.071229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5594 13:18:02.074536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5595 13:18:02.077902 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 13:18:02.084394 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 13:18:02.088258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 13:18:02.091326 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 13:18:02.097884 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 13:18:02.101059 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 13:18:02.104438 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 13:18:02.111108 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 13:18:02.114468 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 13:18:02.117697 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 13:18:02.124750 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 13:18:02.127839 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:18:02.131390 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:18:02.138243 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:18:02.141396 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5610 13:18:02.144446 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5611 13:18:02.148119 Total UI for P1: 0, mck2ui 16
5612 13:18:02.151485 best dqsien dly found for B0: ( 0, 14, 16)
5613 13:18:02.157397 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 13:18:02.157832 Total UI for P1: 0, mck2ui 16
5615 13:18:02.163895 best dqsien dly found for B1: ( 0, 14, 20)
5616 13:18:02.167737 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5617 13:18:02.170914 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5618 13:18:02.171386
5619 13:18:02.173872 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5620 13:18:02.177447 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5621 13:18:02.180819 [Gating] SW calibration Done
5622 13:18:02.181280 ==
5623 13:18:02.184112 Dram Type= 6, Freq= 0, CH_1, rank 1
5624 13:18:02.187685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5625 13:18:02.188138 ==
5626 13:18:02.190550 RX Vref Scan: 0
5627 13:18:02.190990
5628 13:18:02.191320 RX Vref 0 -> 0, step: 1
5629 13:18:02.193983
5630 13:18:02.194406 RX Delay -80 -> 252, step: 8
5631 13:18:02.200275 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5632 13:18:02.203703 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5633 13:18:02.206939 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5634 13:18:02.210169 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5635 13:18:02.213528 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5636 13:18:02.216836 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5637 13:18:02.223902 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5638 13:18:02.227645 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5639 13:18:02.230346 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5640 13:18:02.234391 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5641 13:18:02.237662 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5642 13:18:02.243628 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5643 13:18:02.246718 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5644 13:18:02.250657 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5645 13:18:02.253580 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5646 13:18:02.257222 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5647 13:18:02.257695 ==
5648 13:18:02.260226 Dram Type= 6, Freq= 0, CH_1, rank 1
5649 13:18:02.267306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5650 13:18:02.267747 ==
5651 13:18:02.268138 DQS Delay:
5652 13:18:02.269729 DQS0 = 0, DQS1 = 0
5653 13:18:02.270164 DQM Delay:
5654 13:18:02.272863 DQM0 = 94, DQM1 = 86
5655 13:18:02.273302 DQ Delay:
5656 13:18:02.277048 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5657 13:18:02.279833 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5658 13:18:02.283195 DQ8 =75, DQ9 =79, DQ10 =83, DQ11 =79
5659 13:18:02.286647 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =95
5660 13:18:02.287041
5661 13:18:02.287427
5662 13:18:02.287791 ==
5663 13:18:02.290399 Dram Type= 6, Freq= 0, CH_1, rank 1
5664 13:18:02.293712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5665 13:18:02.294108 ==
5666 13:18:02.294541
5667 13:18:02.294896
5668 13:18:02.296758 TX Vref Scan disable
5669 13:18:02.299634 == TX Byte 0 ==
5670 13:18:02.303227 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5671 13:18:02.306188 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5672 13:18:02.309660 == TX Byte 1 ==
5673 13:18:02.313359 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5674 13:18:02.316014 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5675 13:18:02.316396 ==
5676 13:18:02.319795 Dram Type= 6, Freq= 0, CH_1, rank 1
5677 13:18:02.322789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5678 13:18:02.325987 ==
5679 13:18:02.326407
5680 13:18:02.326727
5681 13:18:02.327025 TX Vref Scan disable
5682 13:18:02.330485 == TX Byte 0 ==
5683 13:18:02.332986 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5684 13:18:02.339694 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5685 13:18:02.340191 == TX Byte 1 ==
5686 13:18:02.343653 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5687 13:18:02.349488 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5688 13:18:02.350027
5689 13:18:02.350502 [DATLAT]
5690 13:18:02.350832 Freq=933, CH1 RK1
5691 13:18:02.351134
5692 13:18:02.352945 DATLAT Default: 0xb
5693 13:18:02.353430 0, 0xFFFF, sum = 0
5694 13:18:02.356224 1, 0xFFFF, sum = 0
5695 13:18:02.359847 2, 0xFFFF, sum = 0
5696 13:18:02.360299 3, 0xFFFF, sum = 0
5697 13:18:02.363047 4, 0xFFFF, sum = 0
5698 13:18:02.363474 5, 0xFFFF, sum = 0
5699 13:18:02.366294 6, 0xFFFF, sum = 0
5700 13:18:02.366728 7, 0xFFFF, sum = 0
5701 13:18:02.369111 8, 0xFFFF, sum = 0
5702 13:18:02.369574 9, 0xFFFF, sum = 0
5703 13:18:02.372840 10, 0x0, sum = 1
5704 13:18:02.373309 11, 0x0, sum = 2
5705 13:18:02.376310 12, 0x0, sum = 3
5706 13:18:02.376824 13, 0x0, sum = 4
5707 13:18:02.377156 best_step = 11
5708 13:18:02.379479
5709 13:18:02.379899 ==
5710 13:18:02.382997 Dram Type= 6, Freq= 0, CH_1, rank 1
5711 13:18:02.386199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5712 13:18:02.386706 ==
5713 13:18:02.387040 RX Vref Scan: 0
5714 13:18:02.387347
5715 13:18:02.389556 RX Vref 0 -> 0, step: 1
5716 13:18:02.389974
5717 13:18:02.392684 RX Delay -69 -> 252, step: 4
5718 13:18:02.399394 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5719 13:18:02.402438 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5720 13:18:02.406481 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5721 13:18:02.409733 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5722 13:18:02.412646 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5723 13:18:02.415839 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5724 13:18:02.423004 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5725 13:18:02.426099 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5726 13:18:02.429863 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5727 13:18:02.432490 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5728 13:18:02.435722 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5729 13:18:02.442033 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5730 13:18:02.445364 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5731 13:18:02.449209 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5732 13:18:02.452175 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5733 13:18:02.455677 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5734 13:18:02.455798 ==
5735 13:18:02.458714 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 13:18:02.466112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5737 13:18:02.466278 ==
5738 13:18:02.466363 DQS Delay:
5739 13:18:02.468475 DQS0 = 0, DQS1 = 0
5740 13:18:02.468638 DQM Delay:
5741 13:18:02.468721 DQM0 = 96, DQM1 = 87
5742 13:18:02.472659 DQ Delay:
5743 13:18:02.475630 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5744 13:18:02.479054 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5745 13:18:02.481618 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5746 13:18:02.485551 DQ12 =96, DQ13 =98, DQ14 =94, DQ15 =96
5747 13:18:02.485789
5748 13:18:02.485924
5749 13:18:02.491923 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5750 13:18:02.495239 CH1 RK1: MR19=505, MR18=2222
5751 13:18:02.502310 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5752 13:18:02.504967 [RxdqsGatingPostProcess] freq 933
5753 13:18:02.508342 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5754 13:18:02.511939 Pre-setting of DQS Precalculation
5755 13:18:02.518716 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5756 13:18:02.525862 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5757 13:18:02.532027 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5758 13:18:02.532518
5759 13:18:02.532851
5760 13:18:02.535142 [Calibration Summary] 1866 Mbps
5761 13:18:02.538240 CH 0, Rank 0
5762 13:18:02.538772 SW Impedance : PASS
5763 13:18:02.541516 DUTY Scan : NO K
5764 13:18:02.545793 ZQ Calibration : PASS
5765 13:18:02.546322 Jitter Meter : NO K
5766 13:18:02.548056 CBT Training : PASS
5767 13:18:02.548500 Write leveling : PASS
5768 13:18:02.551547 RX DQS gating : PASS
5769 13:18:02.554549 RX DQ/DQS(RDDQC) : PASS
5770 13:18:02.555009 TX DQ/DQS : PASS
5771 13:18:02.557669 RX DATLAT : PASS
5772 13:18:02.561143 RX DQ/DQS(Engine): PASS
5773 13:18:02.561613 TX OE : NO K
5774 13:18:02.564855 All Pass.
5775 13:18:02.565418
5776 13:18:02.565771 CH 0, Rank 1
5777 13:18:02.567752 SW Impedance : PASS
5778 13:18:02.568176 DUTY Scan : NO K
5779 13:18:02.571413 ZQ Calibration : PASS
5780 13:18:02.575164 Jitter Meter : NO K
5781 13:18:02.575589 CBT Training : PASS
5782 13:18:02.578079 Write leveling : PASS
5783 13:18:02.580992 RX DQS gating : PASS
5784 13:18:02.581480 RX DQ/DQS(RDDQC) : PASS
5785 13:18:02.584285 TX DQ/DQS : PASS
5786 13:18:02.587969 RX DATLAT : PASS
5787 13:18:02.588394 RX DQ/DQS(Engine): PASS
5788 13:18:02.591178 TX OE : NO K
5789 13:18:02.591603 All Pass.
5790 13:18:02.591926
5791 13:18:02.595001 CH 1, Rank 0
5792 13:18:02.595423 SW Impedance : PASS
5793 13:18:02.598334 DUTY Scan : NO K
5794 13:18:02.601389 ZQ Calibration : PASS
5795 13:18:02.601816 Jitter Meter : NO K
5796 13:18:02.605307 CBT Training : PASS
5797 13:18:02.605808 Write leveling : PASS
5798 13:18:02.608109 RX DQS gating : PASS
5799 13:18:02.611361 RX DQ/DQS(RDDQC) : PASS
5800 13:18:02.611785 TX DQ/DQS : PASS
5801 13:18:02.614377 RX DATLAT : PASS
5802 13:18:02.617428 RX DQ/DQS(Engine): PASS
5803 13:18:02.617978 TX OE : NO K
5804 13:18:02.621089 All Pass.
5805 13:18:02.621651
5806 13:18:02.621984 CH 1, Rank 1
5807 13:18:02.624472 SW Impedance : PASS
5808 13:18:02.624893 DUTY Scan : NO K
5809 13:18:02.627864 ZQ Calibration : PASS
5810 13:18:02.631768 Jitter Meter : NO K
5811 13:18:02.632194 CBT Training : PASS
5812 13:18:02.634156 Write leveling : PASS
5813 13:18:02.637545 RX DQS gating : PASS
5814 13:18:02.637971 RX DQ/DQS(RDDQC) : PASS
5815 13:18:02.640983 TX DQ/DQS : PASS
5816 13:18:02.644357 RX DATLAT : PASS
5817 13:18:02.644783 RX DQ/DQS(Engine): PASS
5818 13:18:02.647230 TX OE : NO K
5819 13:18:02.647657 All Pass.
5820 13:18:02.647982
5821 13:18:02.650719 DramC Write-DBI off
5822 13:18:02.654440 PER_BANK_REFRESH: Hybrid Mode
5823 13:18:02.654869 TX_TRACKING: ON
5824 13:18:02.663914 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5825 13:18:02.667024 [FAST_K] Save calibration result to emmc
5826 13:18:02.670270 dramc_set_vcore_voltage set vcore to 650000
5827 13:18:02.673676 Read voltage for 400, 6
5828 13:18:02.673971 Vio18 = 0
5829 13:18:02.674196 Vcore = 650000
5830 13:18:02.677114 Vdram = 0
5831 13:18:02.677438 Vddq = 0
5832 13:18:02.677664 Vmddr = 0
5833 13:18:02.683737 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5834 13:18:02.687187 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5835 13:18:02.690203 MEM_TYPE=3, freq_sel=20
5836 13:18:02.693667 sv_algorithm_assistance_LP4_800
5837 13:18:02.697735 ============ PULL DRAM RESETB DOWN ============
5838 13:18:02.700545 ========== PULL DRAM RESETB DOWN end =========
5839 13:18:02.707325 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5840 13:18:02.710692 ===================================
5841 13:18:02.711171 LPDDR4 DRAM CONFIGURATION
5842 13:18:02.713810 ===================================
5843 13:18:02.716771 EX_ROW_EN[0] = 0x0
5844 13:18:02.720286 EX_ROW_EN[1] = 0x0
5845 13:18:02.720713 LP4Y_EN = 0x0
5846 13:18:02.723752 WORK_FSP = 0x0
5847 13:18:02.724243 WL = 0x2
5848 13:18:02.726776 RL = 0x2
5849 13:18:02.727196 BL = 0x2
5850 13:18:02.730502 RPST = 0x0
5851 13:18:02.730991 RD_PRE = 0x0
5852 13:18:02.734485 WR_PRE = 0x1
5853 13:18:02.734990 WR_PST = 0x0
5854 13:18:02.737073 DBI_WR = 0x0
5855 13:18:02.737543 DBI_RD = 0x0
5856 13:18:02.740678 OTF = 0x1
5857 13:18:02.743394 ===================================
5858 13:18:02.746664 ===================================
5859 13:18:02.747092 ANA top config
5860 13:18:02.750257 ===================================
5861 13:18:02.754549 DLL_ASYNC_EN = 0
5862 13:18:02.756581 ALL_SLAVE_EN = 1
5863 13:18:02.760036 NEW_RANK_MODE = 1
5864 13:18:02.760512 DLL_IDLE_MODE = 1
5865 13:18:02.763886 LP45_APHY_COMB_EN = 1
5866 13:18:02.766996 TX_ODT_DIS = 1
5867 13:18:02.769813 NEW_8X_MODE = 1
5868 13:18:02.773436 ===================================
5869 13:18:02.776659 ===================================
5870 13:18:02.780457 data_rate = 800
5871 13:18:02.780883 CKR = 1
5872 13:18:02.783388 DQ_P2S_RATIO = 4
5873 13:18:02.786955 ===================================
5874 13:18:02.790990 CA_P2S_RATIO = 4
5875 13:18:02.793519 DQ_CA_OPEN = 0
5876 13:18:02.796438 DQ_SEMI_OPEN = 1
5877 13:18:02.800757 CA_SEMI_OPEN = 1
5878 13:18:02.801333 CA_FULL_RATE = 0
5879 13:18:02.803233 DQ_CKDIV4_EN = 0
5880 13:18:02.806777 CA_CKDIV4_EN = 1
5881 13:18:02.810291 CA_PREDIV_EN = 0
5882 13:18:02.813063 PH8_DLY = 0
5883 13:18:02.816810 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5884 13:18:02.817363 DQ_AAMCK_DIV = 0
5885 13:18:02.819629 CA_AAMCK_DIV = 0
5886 13:18:02.822990 CA_ADMCK_DIV = 4
5887 13:18:02.826737 DQ_TRACK_CA_EN = 0
5888 13:18:02.830148 CA_PICK = 800
5889 13:18:02.832987 CA_MCKIO = 400
5890 13:18:02.833441 MCKIO_SEMI = 400
5891 13:18:02.836484 PLL_FREQ = 3016
5892 13:18:02.840536 DQ_UI_PI_RATIO = 32
5893 13:18:02.842994 CA_UI_PI_RATIO = 32
5894 13:18:02.846513 ===================================
5895 13:18:02.849797 ===================================
5896 13:18:02.853640 memory_type:LPDDR4
5897 13:18:02.854107 GP_NUM : 10
5898 13:18:02.856741 SRAM_EN : 1
5899 13:18:02.859828 MD32_EN : 0
5900 13:18:02.863683 ===================================
5901 13:18:02.864146 [ANA_INIT] >>>>>>>>>>>>>>
5902 13:18:02.866608 <<<<<< [CONFIGURE PHASE]: ANA_TX
5903 13:18:02.869709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5904 13:18:02.873100 ===================================
5905 13:18:02.876312 data_rate = 800,PCW = 0X7400
5906 13:18:02.879542 ===================================
5907 13:18:02.882882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5908 13:18:02.889823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5909 13:18:02.899548 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5910 13:18:02.906298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5911 13:18:02.909669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5912 13:18:02.912808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5913 13:18:02.913287 [ANA_INIT] flow start
5914 13:18:02.916255 [ANA_INIT] PLL >>>>>>>>
5915 13:18:02.919749 [ANA_INIT] PLL <<<<<<<<
5916 13:18:02.920187 [ANA_INIT] MIDPI >>>>>>>>
5917 13:18:02.922706 [ANA_INIT] MIDPI <<<<<<<<
5918 13:18:02.926390 [ANA_INIT] DLL >>>>>>>>
5919 13:18:02.927026 [ANA_INIT] flow end
5920 13:18:02.932984 ============ LP4 DIFF to SE enter ============
5921 13:18:02.936340 ============ LP4 DIFF to SE exit ============
5922 13:18:02.939330 [ANA_INIT] <<<<<<<<<<<<<
5923 13:18:02.942580 [Flow] Enable top DCM control >>>>>
5924 13:18:02.946306 [Flow] Enable top DCM control <<<<<
5925 13:18:02.946819 Enable DLL master slave shuffle
5926 13:18:02.953083 ==============================================================
5927 13:18:02.956515 Gating Mode config
5928 13:18:02.959379 ==============================================================
5929 13:18:02.962788 Config description:
5930 13:18:02.972206 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5931 13:18:02.979235 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5932 13:18:02.983131 SELPH_MODE 0: By rank 1: By Phase
5933 13:18:02.988834 ==============================================================
5934 13:18:02.992146 GAT_TRACK_EN = 0
5935 13:18:02.996059 RX_GATING_MODE = 2
5936 13:18:02.999026 RX_GATING_TRACK_MODE = 2
5937 13:18:03.002664 SELPH_MODE = 1
5938 13:18:03.003137 PICG_EARLY_EN = 1
5939 13:18:03.005836 VALID_LAT_VALUE = 1
5940 13:18:03.012782 ==============================================================
5941 13:18:03.015363 Enter into Gating configuration >>>>
5942 13:18:03.019234 Exit from Gating configuration <<<<
5943 13:18:03.022027 Enter into DVFS_PRE_config >>>>>
5944 13:18:03.032399 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5945 13:18:03.036383 Exit from DVFS_PRE_config <<<<<
5946 13:18:03.038947 Enter into PICG configuration >>>>
5947 13:18:03.042241 Exit from PICG configuration <<<<
5948 13:18:03.045199 [RX_INPUT] configuration >>>>>
5949 13:18:03.048950 [RX_INPUT] configuration <<<<<
5950 13:18:03.052444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5951 13:18:03.058997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5952 13:18:03.065441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5953 13:18:03.072546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5954 13:18:03.078440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5955 13:18:03.082251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5956 13:18:03.089397 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5957 13:18:03.093497 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5958 13:18:03.095614 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5959 13:18:03.098952 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5960 13:18:03.105576 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5961 13:18:03.108743 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5962 13:18:03.111952 ===================================
5963 13:18:03.114690 LPDDR4 DRAM CONFIGURATION
5964 13:18:03.118509 ===================================
5965 13:18:03.119040 EX_ROW_EN[0] = 0x0
5966 13:18:03.121898 EX_ROW_EN[1] = 0x0
5967 13:18:03.122324 LP4Y_EN = 0x0
5968 13:18:03.124942 WORK_FSP = 0x0
5969 13:18:03.125400 WL = 0x2
5970 13:18:03.128184 RL = 0x2
5971 13:18:03.128689 BL = 0x2
5972 13:18:03.131135 RPST = 0x0
5973 13:18:03.134764 RD_PRE = 0x0
5974 13:18:03.135224 WR_PRE = 0x1
5975 13:18:03.137764 WR_PST = 0x0
5976 13:18:03.138190 DBI_WR = 0x0
5977 13:18:03.141434 DBI_RD = 0x0
5978 13:18:03.142097 OTF = 0x1
5979 13:18:03.144514 ===================================
5980 13:18:03.147859 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5981 13:18:03.154798 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5982 13:18:03.157921 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5983 13:18:03.161130 ===================================
5984 13:18:03.164566 LPDDR4 DRAM CONFIGURATION
5985 13:18:03.167827 ===================================
5986 13:18:03.168127 EX_ROW_EN[0] = 0x10
5987 13:18:03.171482 EX_ROW_EN[1] = 0x0
5988 13:18:03.171774 LP4Y_EN = 0x0
5989 13:18:03.174496 WORK_FSP = 0x0
5990 13:18:03.174867 WL = 0x2
5991 13:18:03.177804 RL = 0x2
5992 13:18:03.178180 BL = 0x2
5993 13:18:03.181909 RPST = 0x0
5994 13:18:03.185613 RD_PRE = 0x0
5995 13:18:03.186002 WR_PRE = 0x1
5996 13:18:03.188589 WR_PST = 0x0
5997 13:18:03.188963 DBI_WR = 0x0
5998 13:18:03.191169 DBI_RD = 0x0
5999 13:18:03.191547 OTF = 0x1
6000 13:18:03.194096 ===================================
6001 13:18:03.201061 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6002 13:18:03.204792 nWR fixed to 30
6003 13:18:03.208162 [ModeRegInit_LP4] CH0 RK0
6004 13:18:03.208666 [ModeRegInit_LP4] CH0 RK1
6005 13:18:03.211444 [ModeRegInit_LP4] CH1 RK0
6006 13:18:03.214452 [ModeRegInit_LP4] CH1 RK1
6007 13:18:03.214881 match AC timing 18
6008 13:18:03.221122 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6009 13:18:03.224659 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6010 13:18:03.227783 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6011 13:18:03.234766 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6012 13:18:03.238116 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6013 13:18:03.238627 ==
6014 13:18:03.241543 Dram Type= 6, Freq= 0, CH_0, rank 0
6015 13:18:03.245048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6016 13:18:03.245537 ==
6017 13:18:03.250818 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6018 13:18:03.258237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6019 13:18:03.260855 [CA 0] Center 36 (8~64) winsize 57
6020 13:18:03.265147 [CA 1] Center 36 (8~64) winsize 57
6021 13:18:03.268234 [CA 2] Center 36 (8~64) winsize 57
6022 13:18:03.271078 [CA 3] Center 36 (8~64) winsize 57
6023 13:18:03.271505 [CA 4] Center 36 (8~64) winsize 57
6024 13:18:03.274711 [CA 5] Center 36 (8~64) winsize 57
6025 13:18:03.275220
6026 13:18:03.280779 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6027 13:18:03.281220
6028 13:18:03.284411 [CATrainingPosCal] consider 1 rank data
6029 13:18:03.287107 u2DelayCellTimex100 = 270/100 ps
6030 13:18:03.290782 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 13:18:03.294364 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 13:18:03.297746 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 13:18:03.301643 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 13:18:03.304042 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 13:18:03.307298 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 13:18:03.307804
6037 13:18:03.310418 CA PerBit enable=1, Macro0, CA PI delay=36
6038 13:18:03.310845
6039 13:18:03.314313 [CBTSetCACLKResult] CA Dly = 36
6040 13:18:03.317285 CS Dly: 1 (0~32)
6041 13:18:03.317714 ==
6042 13:18:03.321219 Dram Type= 6, Freq= 0, CH_0, rank 1
6043 13:18:03.323571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6044 13:18:03.324001 ==
6045 13:18:03.330723 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6046 13:18:03.337032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6047 13:18:03.337601 [CA 0] Center 36 (8~64) winsize 57
6048 13:18:03.340612 [CA 1] Center 36 (8~64) winsize 57
6049 13:18:03.343413 [CA 2] Center 36 (8~64) winsize 57
6050 13:18:03.347165 [CA 3] Center 36 (8~64) winsize 57
6051 13:18:03.350319 [CA 4] Center 36 (8~64) winsize 57
6052 13:18:03.353583 [CA 5] Center 36 (8~64) winsize 57
6053 13:18:03.354214
6054 13:18:03.357020 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6055 13:18:03.357646
6056 13:18:03.360887 [CATrainingPosCal] consider 2 rank data
6057 13:18:03.363480 u2DelayCellTimex100 = 270/100 ps
6058 13:18:03.367059 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6059 13:18:03.373743 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6060 13:18:03.377016 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 13:18:03.381328 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 13:18:03.383662 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 13:18:03.387241 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 13:18:03.387674
6065 13:18:03.391215 CA PerBit enable=1, Macro0, CA PI delay=36
6066 13:18:03.391740
6067 13:18:03.393618 [CBTSetCACLKResult] CA Dly = 36
6068 13:18:03.394047 CS Dly: 1 (0~32)
6069 13:18:03.394377
6070 13:18:03.397013 ----->DramcWriteLeveling(PI) begin...
6071 13:18:03.400210 ==
6072 13:18:03.403495 Dram Type= 6, Freq= 0, CH_0, rank 0
6073 13:18:03.406610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6074 13:18:03.407116 ==
6075 13:18:03.409987 Write leveling (Byte 0): 32 => 0
6076 13:18:03.413748 Write leveling (Byte 1): 32 => 0
6077 13:18:03.417011 DramcWriteLeveling(PI) end<-----
6078 13:18:03.417557
6079 13:18:03.417890 ==
6080 13:18:03.420360 Dram Type= 6, Freq= 0, CH_0, rank 0
6081 13:18:03.423158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6082 13:18:03.423644 ==
6083 13:18:03.426691 [Gating] SW mode calibration
6084 13:18:03.433283 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6085 13:18:03.440263 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6086 13:18:03.443403 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6087 13:18:03.446848 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6088 13:18:03.453925 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6089 13:18:03.456589 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6090 13:18:03.460266 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6091 13:18:03.463628 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6092 13:18:03.470156 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6093 13:18:03.472780 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6094 13:18:03.476653 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6095 13:18:03.480246 Total UI for P1: 0, mck2ui 16
6096 13:18:03.483030 best dqsien dly found for B0: ( 0, 10, 16)
6097 13:18:03.486441 Total UI for P1: 0, mck2ui 16
6098 13:18:03.489348 best dqsien dly found for B1: ( 0, 10, 16)
6099 13:18:03.492921 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6100 13:18:03.500339 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6101 13:18:03.500848
6102 13:18:03.502805 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6103 13:18:03.506875 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6104 13:18:03.509994 [Gating] SW calibration Done
6105 13:18:03.510493 ==
6106 13:18:03.512859 Dram Type= 6, Freq= 0, CH_0, rank 0
6107 13:18:03.516179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6108 13:18:03.516607 ==
6109 13:18:03.519684 RX Vref Scan: 0
6110 13:18:03.520114
6111 13:18:03.520441 RX Vref 0 -> 0, step: 1
6112 13:18:03.520747
6113 13:18:03.522534 RX Delay -410 -> 252, step: 16
6114 13:18:03.526395 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6115 13:18:03.532862 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6116 13:18:03.536224 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6117 13:18:03.539675 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6118 13:18:03.542693 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6119 13:18:03.549121 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6120 13:18:03.552800 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6121 13:18:03.556709 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6122 13:18:03.560165 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6123 13:18:03.566162 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6124 13:18:03.568997 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6125 13:18:03.572748 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6126 13:18:03.579479 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6127 13:18:03.582007 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6128 13:18:03.585792 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6129 13:18:03.588903 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6130 13:18:03.589375 ==
6131 13:18:03.592192 Dram Type= 6, Freq= 0, CH_0, rank 0
6132 13:18:03.599667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6133 13:18:03.600185 ==
6134 13:18:03.600524 DQS Delay:
6135 13:18:03.602568 DQS0 = 51, DQS1 = 59
6136 13:18:03.602994 DQM Delay:
6137 13:18:03.605438 DQM0 = 11, DQM1 = 13
6138 13:18:03.605863 DQ Delay:
6139 13:18:03.609440 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6140 13:18:03.612277 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6141 13:18:03.615341 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6142 13:18:03.618783 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6143 13:18:03.619216
6144 13:18:03.619546
6145 13:18:03.619851 ==
6146 13:18:03.622045 Dram Type= 6, Freq= 0, CH_0, rank 0
6147 13:18:03.625312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6148 13:18:03.625817 ==
6149 13:18:03.626151
6150 13:18:03.626453
6151 13:18:03.629045 TX Vref Scan disable
6152 13:18:03.629598 == TX Byte 0 ==
6153 13:18:03.635249 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6154 13:18:03.638242 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6155 13:18:03.638676 == TX Byte 1 ==
6156 13:18:03.645372 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6157 13:18:03.649114 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6158 13:18:03.649661 ==
6159 13:18:03.652834 Dram Type= 6, Freq= 0, CH_0, rank 0
6160 13:18:03.655414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6161 13:18:03.655937 ==
6162 13:18:03.656272
6163 13:18:03.656576
6164 13:18:03.658730 TX Vref Scan disable
6165 13:18:03.661542 == TX Byte 0 ==
6166 13:18:03.665019 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6167 13:18:03.668586 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6168 13:18:03.671607 == TX Byte 1 ==
6169 13:18:03.675206 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6170 13:18:03.677985 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6171 13:18:03.678623
6172 13:18:03.679163 [DATLAT]
6173 13:18:03.681444 Freq=400, CH0 RK0
6174 13:18:03.682030
6175 13:18:03.682545 DATLAT Default: 0xf
6176 13:18:03.684966 0, 0xFFFF, sum = 0
6177 13:18:03.688037 1, 0xFFFF, sum = 0
6178 13:18:03.688676 2, 0xFFFF, sum = 0
6179 13:18:03.692019 3, 0xFFFF, sum = 0
6180 13:18:03.692453 4, 0xFFFF, sum = 0
6181 13:18:03.695056 5, 0xFFFF, sum = 0
6182 13:18:03.695491 6, 0xFFFF, sum = 0
6183 13:18:03.698388 7, 0xFFFF, sum = 0
6184 13:18:03.698833 8, 0xFFFF, sum = 0
6185 13:18:03.703602 9, 0xFFFF, sum = 0
6186 13:18:03.704110 10, 0xFFFF, sum = 0
6187 13:18:03.704775 11, 0xFFFF, sum = 0
6188 13:18:03.705116 12, 0x0, sum = 1
6189 13:18:03.708484 13, 0x0, sum = 2
6190 13:18:03.709050 14, 0x0, sum = 3
6191 13:18:03.711573 15, 0x0, sum = 4
6192 13:18:03.712083 best_step = 13
6193 13:18:03.712415
6194 13:18:03.712738 ==
6195 13:18:03.714740 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 13:18:03.717777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6197 13:18:03.721774 ==
6198 13:18:03.722202 RX Vref Scan: 1
6199 13:18:03.722536
6200 13:18:03.724350 RX Vref 0 -> 0, step: 1
6201 13:18:03.724774
6202 13:18:03.727982 RX Delay -359 -> 252, step: 8
6203 13:18:03.728411
6204 13:18:03.731438 Set Vref, RX VrefLevel [Byte0]: 48
6205 13:18:03.734960 [Byte1]: 50
6206 13:18:03.735457
6207 13:18:03.738151 Final RX Vref Byte 0 = 48 to rank0
6208 13:18:03.740796 Final RX Vref Byte 1 = 50 to rank0
6209 13:18:03.744252 Final RX Vref Byte 0 = 48 to rank1
6210 13:18:03.748152 Final RX Vref Byte 1 = 50 to rank1==
6211 13:18:03.751076 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 13:18:03.755070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6213 13:18:03.755573 ==
6214 13:18:03.757492 DQS Delay:
6215 13:18:03.757917 DQS0 = 52, DQS1 = 68
6216 13:18:03.761087 DQM Delay:
6217 13:18:03.761650 DQM0 = 9, DQM1 = 16
6218 13:18:03.761989 DQ Delay:
6219 13:18:03.764356 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6220 13:18:03.767777 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6221 13:18:03.771033 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6222 13:18:03.774911 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6223 13:18:03.775409
6224 13:18:03.775739
6225 13:18:03.784375 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaaa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6226 13:18:03.784887 CH0 RK0: MR19=C0C, MR18=AAAA
6227 13:18:03.790886 CH0_RK0: MR19=0xC0C, MR18=0xAAAA, DQSOSC=388, MR23=63, INC=392, DEC=261
6228 13:18:03.791387 ==
6229 13:18:03.794204 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 13:18:03.800662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6231 13:18:03.801201 ==
6232 13:18:03.803902 [Gating] SW mode calibration
6233 13:18:03.811318 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6234 13:18:03.814245 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6235 13:18:03.821016 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6236 13:18:03.824441 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6237 13:18:03.827499 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6238 13:18:03.834128 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6239 13:18:03.837360 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6240 13:18:03.840615 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6241 13:18:03.844002 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6242 13:18:03.850427 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6243 13:18:03.853695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6244 13:18:03.857432 Total UI for P1: 0, mck2ui 16
6245 13:18:03.860731 best dqsien dly found for B0: ( 0, 10, 16)
6246 13:18:03.864223 Total UI for P1: 0, mck2ui 16
6247 13:18:03.867628 best dqsien dly found for B1: ( 0, 10, 24)
6248 13:18:03.870771 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6249 13:18:03.873739 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6250 13:18:03.874247
6251 13:18:03.877817 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6252 13:18:03.883871 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6253 13:18:03.884382 [Gating] SW calibration Done
6254 13:18:03.884712 ==
6255 13:18:03.887664 Dram Type= 6, Freq= 0, CH_0, rank 1
6256 13:18:03.893877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6257 13:18:03.894308 ==
6258 13:18:03.894656 RX Vref Scan: 0
6259 13:18:03.894963
6260 13:18:03.896946 RX Vref 0 -> 0, step: 1
6261 13:18:03.897406
6262 13:18:03.900114 RX Delay -410 -> 252, step: 16
6263 13:18:03.903338 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6264 13:18:03.907518 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6265 13:18:03.914164 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6266 13:18:03.917141 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6267 13:18:03.920102 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6268 13:18:03.924125 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6269 13:18:03.930790 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6270 13:18:03.933579 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6271 13:18:03.936703 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6272 13:18:03.940404 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6273 13:18:03.946760 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6274 13:18:03.950200 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6275 13:18:03.953635 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6276 13:18:03.960301 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6277 13:18:03.963181 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6278 13:18:03.966853 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6279 13:18:03.967399 ==
6280 13:18:03.969900 Dram Type= 6, Freq= 0, CH_0, rank 1
6281 13:18:03.973034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6282 13:18:03.976559 ==
6283 13:18:03.976988 DQS Delay:
6284 13:18:03.977358 DQS0 = 43, DQS1 = 59
6285 13:18:03.979548 DQM Delay:
6286 13:18:03.979974 DQM0 = 7, DQM1 = 14
6287 13:18:03.982986 DQ Delay:
6288 13:18:03.983412 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6289 13:18:03.986375 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6290 13:18:03.989663 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6291 13:18:03.993467 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6292 13:18:03.994007
6293 13:18:03.994343
6294 13:18:03.994659 ==
6295 13:18:03.996393 Dram Type= 6, Freq= 0, CH_0, rank 1
6296 13:18:04.003055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6297 13:18:04.003558 ==
6298 13:18:04.003886
6299 13:18:04.004201
6300 13:18:04.004494 TX Vref Scan disable
6301 13:18:04.006235 == TX Byte 0 ==
6302 13:18:04.009807 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6303 13:18:04.013211 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6304 13:18:04.015963 == TX Byte 1 ==
6305 13:18:04.020692 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6306 13:18:04.023675 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6307 13:18:04.024181 ==
6308 13:18:04.025920 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 13:18:04.033201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6310 13:18:04.033750 ==
6311 13:18:04.034085
6312 13:18:04.034386
6313 13:18:04.036092 TX Vref Scan disable
6314 13:18:04.036573 == TX Byte 0 ==
6315 13:18:04.039584 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6316 13:18:04.042364 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6317 13:18:04.046210 == TX Byte 1 ==
6318 13:18:04.049589 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6319 13:18:04.053096 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6320 13:18:04.056490
6321 13:18:04.056991 [DATLAT]
6322 13:18:04.057361 Freq=400, CH0 RK1
6323 13:18:04.057679
6324 13:18:04.059227 DATLAT Default: 0xd
6325 13:18:04.059651 0, 0xFFFF, sum = 0
6326 13:18:04.062248 1, 0xFFFF, sum = 0
6327 13:18:04.062685 2, 0xFFFF, sum = 0
6328 13:18:04.066256 3, 0xFFFF, sum = 0
6329 13:18:04.066759 4, 0xFFFF, sum = 0
6330 13:18:04.070602 5, 0xFFFF, sum = 0
6331 13:18:04.073432 6, 0xFFFF, sum = 0
6332 13:18:04.073870 7, 0xFFFF, sum = 0
6333 13:18:04.076186 8, 0xFFFF, sum = 0
6334 13:18:04.076622 9, 0xFFFF, sum = 0
6335 13:18:04.079225 10, 0xFFFF, sum = 0
6336 13:18:04.079742 11, 0xFFFF, sum = 0
6337 13:18:04.082753 12, 0x0, sum = 1
6338 13:18:04.083186 13, 0x0, sum = 2
6339 13:18:04.086150 14, 0x0, sum = 3
6340 13:18:04.086657 15, 0x0, sum = 4
6341 13:18:04.086994 best_step = 13
6342 13:18:04.087295
6343 13:18:04.088773 ==
6344 13:18:04.092392 Dram Type= 6, Freq= 0, CH_0, rank 1
6345 13:18:04.096075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6346 13:18:04.096503 ==
6347 13:18:04.096830 RX Vref Scan: 0
6348 13:18:04.097134
6349 13:18:04.099303 RX Vref 0 -> 0, step: 1
6350 13:18:04.099725
6351 13:18:04.102072 RX Delay -359 -> 252, step: 8
6352 13:18:04.109327 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6353 13:18:04.112745 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6354 13:18:04.116392 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6355 13:18:04.122578 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6356 13:18:04.126092 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6357 13:18:04.129398 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6358 13:18:04.132436 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6359 13:18:04.139400 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6360 13:18:04.143707 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6361 13:18:04.145808 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6362 13:18:04.148890 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6363 13:18:04.156066 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6364 13:18:04.159100 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6365 13:18:04.162303 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6366 13:18:04.165992 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6367 13:18:04.172455 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6368 13:18:04.172951 ==
6369 13:18:04.175495 Dram Type= 6, Freq= 0, CH_0, rank 1
6370 13:18:04.179152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6371 13:18:04.179666 ==
6372 13:18:04.180000 DQS Delay:
6373 13:18:04.182304 DQS0 = 52, DQS1 = 64
6374 13:18:04.182745 DQM Delay:
6375 13:18:04.185295 DQM0 = 10, DQM1 = 14
6376 13:18:04.185718 DQ Delay:
6377 13:18:04.188890 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6378 13:18:04.192055 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6379 13:18:04.195218 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6380 13:18:04.198810 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6381 13:18:04.199315
6382 13:18:04.199642
6383 13:18:04.205988 [DQSOSCAuto] RK1, (LSB)MR18= 0xc4c4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6384 13:18:04.208972 CH0 RK1: MR19=C0C, MR18=C4C4
6385 13:18:04.215636 CH0_RK1: MR19=0xC0C, MR18=0xC4C4, DQSOSC=385, MR23=63, INC=398, DEC=265
6386 13:18:04.218681 [RxdqsGatingPostProcess] freq 400
6387 13:18:04.226002 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6388 13:18:04.229933 Pre-setting of DQS Precalculation
6389 13:18:04.231659 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6390 13:18:04.232205 ==
6391 13:18:04.235123 Dram Type= 6, Freq= 0, CH_1, rank 0
6392 13:18:04.238352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6393 13:18:04.238897 ==
6394 13:18:04.245474 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6395 13:18:04.252177 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6396 13:18:04.255548 [CA 0] Center 36 (8~64) winsize 57
6397 13:18:04.258357 [CA 1] Center 36 (8~64) winsize 57
6398 13:18:04.261591 [CA 2] Center 36 (8~64) winsize 57
6399 13:18:04.265310 [CA 3] Center 36 (8~64) winsize 57
6400 13:18:04.268607 [CA 4] Center 36 (8~64) winsize 57
6401 13:18:04.269104 [CA 5] Center 36 (8~64) winsize 57
6402 13:18:04.272264
6403 13:18:04.275273 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6404 13:18:04.275702
6405 13:18:04.278057 [CATrainingPosCal] consider 1 rank data
6406 13:18:04.281728 u2DelayCellTimex100 = 270/100 ps
6407 13:18:04.285450 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 13:18:04.288337 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 13:18:04.291363 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 13:18:04.294663 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 13:18:04.298221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 13:18:04.302162 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 13:18:04.302664
6414 13:18:04.305792 CA PerBit enable=1, Macro0, CA PI delay=36
6415 13:18:04.306221
6416 13:18:04.308769 [CBTSetCACLKResult] CA Dly = 36
6417 13:18:04.311827 CS Dly: 1 (0~32)
6418 13:18:04.312327 ==
6419 13:18:04.314408 Dram Type= 6, Freq= 0, CH_1, rank 1
6420 13:18:04.318178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6421 13:18:04.318684 ==
6422 13:18:04.325109 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6423 13:18:04.331843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6424 13:18:04.335975 [CA 0] Center 36 (8~64) winsize 57
6425 13:18:04.337498 [CA 1] Center 36 (8~64) winsize 57
6426 13:18:04.338034 [CA 2] Center 36 (8~64) winsize 57
6427 13:18:04.341220 [CA 3] Center 36 (8~64) winsize 57
6428 13:18:04.344795 [CA 4] Center 36 (8~64) winsize 57
6429 13:18:04.347813 [CA 5] Center 36 (8~64) winsize 57
6430 13:18:04.348476
6431 13:18:04.351153 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6432 13:18:04.354592
6433 13:18:04.357584 [CATrainingPosCal] consider 2 rank data
6434 13:18:04.358030 u2DelayCellTimex100 = 270/100 ps
6435 13:18:04.364012 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6436 13:18:04.368020 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6437 13:18:04.371049 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 13:18:04.375270 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 13:18:04.377564 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 13:18:04.381119 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 13:18:04.381836
6442 13:18:04.383849 CA PerBit enable=1, Macro0, CA PI delay=36
6443 13:18:04.384362
6444 13:18:04.387346 [CBTSetCACLKResult] CA Dly = 36
6445 13:18:04.390743 CS Dly: 1 (0~32)
6446 13:18:04.391371
6447 13:18:04.394017 ----->DramcWriteLeveling(PI) begin...
6448 13:18:04.394466 ==
6449 13:18:04.397097 Dram Type= 6, Freq= 0, CH_1, rank 0
6450 13:18:04.401436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6451 13:18:04.401936 ==
6452 13:18:04.404027 Write leveling (Byte 0): 32 => 0
6453 13:18:04.407389 Write leveling (Byte 1): 32 => 0
6454 13:18:04.410725 DramcWriteLeveling(PI) end<-----
6455 13:18:04.411223
6456 13:18:04.411550 ==
6457 13:18:04.414230 Dram Type= 6, Freq= 0, CH_1, rank 0
6458 13:18:04.417524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6459 13:18:04.417957 ==
6460 13:18:04.420813 [Gating] SW mode calibration
6461 13:18:04.427154 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6462 13:18:04.434217 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6463 13:18:04.437060 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6464 13:18:04.440594 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 13:18:04.447673 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 13:18:04.450772 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6467 13:18:04.453663 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 13:18:04.460421 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 13:18:04.463723 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 13:18:04.467840 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6471 13:18:04.473820 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 13:18:04.474206 Total UI for P1: 0, mck2ui 16
6473 13:18:04.481269 best dqsien dly found for B0: ( 0, 10, 16)
6474 13:18:04.481745 Total UI for P1: 0, mck2ui 16
6475 13:18:04.487483 best dqsien dly found for B1: ( 0, 10, 16)
6476 13:18:04.489996 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6477 13:18:04.493196 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6478 13:18:04.493617
6479 13:18:04.496781 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6480 13:18:04.500618 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6481 13:18:04.503980 [Gating] SW calibration Done
6482 13:18:04.504480 ==
6483 13:18:04.507382 Dram Type= 6, Freq= 0, CH_1, rank 0
6484 13:18:04.510383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6485 13:18:04.510822 ==
6486 13:18:04.513439 RX Vref Scan: 0
6487 13:18:04.513819
6488 13:18:04.514113 RX Vref 0 -> 0, step: 1
6489 13:18:04.514384
6490 13:18:04.516573 RX Delay -410 -> 252, step: 16
6491 13:18:04.523753 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6492 13:18:04.526913 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6493 13:18:04.530033 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6494 13:18:04.533162 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6495 13:18:04.542513 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6496 13:18:04.543292 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6497 13:18:04.546544 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6498 13:18:04.549639 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6499 13:18:04.556580 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6500 13:18:04.559668 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6501 13:18:04.563058 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6502 13:18:04.566223 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6503 13:18:04.573201 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6504 13:18:04.576391 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6505 13:18:04.579666 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6506 13:18:04.586074 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6507 13:18:04.586501 ==
6508 13:18:04.589371 Dram Type= 6, Freq= 0, CH_1, rank 0
6509 13:18:04.592934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6510 13:18:04.593388 ==
6511 13:18:04.593720 DQS Delay:
6512 13:18:04.595861 DQS0 = 43, DQS1 = 59
6513 13:18:04.596306 DQM Delay:
6514 13:18:04.599553 DQM0 = 6, DQM1 = 13
6515 13:18:04.599980 DQ Delay:
6516 13:18:04.603282 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6517 13:18:04.606751 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6518 13:18:04.610158 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6519 13:18:04.613145 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6520 13:18:04.613673
6521 13:18:04.614002
6522 13:18:04.614302 ==
6523 13:18:04.616862 Dram Type= 6, Freq= 0, CH_1, rank 0
6524 13:18:04.619524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6525 13:18:04.620024 ==
6526 13:18:04.620349
6527 13:18:04.620646
6528 13:18:04.623027 TX Vref Scan disable
6529 13:18:04.623446 == TX Byte 0 ==
6530 13:18:04.629556 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6531 13:18:04.632463 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6532 13:18:04.632887 == TX Byte 1 ==
6533 13:18:04.639992 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6534 13:18:04.642566 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6535 13:18:04.643006 ==
6536 13:18:04.646231 Dram Type= 6, Freq= 0, CH_1, rank 0
6537 13:18:04.648956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6538 13:18:04.649417 ==
6539 13:18:04.649754
6540 13:18:04.650053
6541 13:18:04.652613 TX Vref Scan disable
6542 13:18:04.656367 == TX Byte 0 ==
6543 13:18:04.659165 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6544 13:18:04.663332 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6545 13:18:04.665851 == TX Byte 1 ==
6546 13:18:04.669404 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6547 13:18:04.672759 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6548 13:18:04.673295
6549 13:18:04.673628 [DATLAT]
6550 13:18:04.675977 Freq=400, CH1 RK0
6551 13:18:04.676479
6552 13:18:04.679484 DATLAT Default: 0xf
6553 13:18:04.679986 0, 0xFFFF, sum = 0
6554 13:18:04.682422 1, 0xFFFF, sum = 0
6555 13:18:04.682852 2, 0xFFFF, sum = 0
6556 13:18:04.686234 3, 0xFFFF, sum = 0
6557 13:18:04.686739 4, 0xFFFF, sum = 0
6558 13:18:04.689046 5, 0xFFFF, sum = 0
6559 13:18:04.689583 6, 0xFFFF, sum = 0
6560 13:18:04.692479 7, 0xFFFF, sum = 0
6561 13:18:04.693075 8, 0xFFFF, sum = 0
6562 13:18:04.695884 9, 0xFFFF, sum = 0
6563 13:18:04.696324 10, 0xFFFF, sum = 0
6564 13:18:04.699325 11, 0xFFFF, sum = 0
6565 13:18:04.699764 12, 0x0, sum = 1
6566 13:18:04.702077 13, 0x0, sum = 2
6567 13:18:04.702580 14, 0x0, sum = 3
6568 13:18:04.705463 15, 0x0, sum = 4
6569 13:18:04.705984 best_step = 13
6570 13:18:04.706309
6571 13:18:04.706605 ==
6572 13:18:04.709200 Dram Type= 6, Freq= 0, CH_1, rank 0
6573 13:18:04.712111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6574 13:18:04.716058 ==
6575 13:18:04.716482 RX Vref Scan: 1
6576 13:18:04.716808
6577 13:18:04.718606 RX Vref 0 -> 0, step: 1
6578 13:18:04.719040
6579 13:18:04.722353 RX Delay -359 -> 252, step: 8
6580 13:18:04.722806
6581 13:18:04.725442 Set Vref, RX VrefLevel [Byte0]: 55
6582 13:18:04.729194 [Byte1]: 49
6583 13:18:04.729739
6584 13:18:04.732135 Final RX Vref Byte 0 = 55 to rank0
6585 13:18:04.735272 Final RX Vref Byte 1 = 49 to rank0
6586 13:18:04.738792 Final RX Vref Byte 0 = 55 to rank1
6587 13:18:04.741828 Final RX Vref Byte 1 = 49 to rank1==
6588 13:18:04.745539 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 13:18:04.748747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6590 13:18:04.751556 ==
6591 13:18:04.751976 DQS Delay:
6592 13:18:04.752298 DQS0 = 52, DQS1 = 64
6593 13:18:04.755533 DQM Delay:
6594 13:18:04.756036 DQM0 = 11, DQM1 = 15
6595 13:18:04.758751 DQ Delay:
6596 13:18:04.759256 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6597 13:18:04.761545 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6598 13:18:04.764956 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6599 13:18:04.768484 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6600 13:18:04.768982
6601 13:18:04.769345
6602 13:18:04.779242 [DQSOSCAuto] RK0, (LSB)MR18= 0xdcdc, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6603 13:18:04.781922 CH1 RK0: MR19=C0C, MR18=DCDC
6604 13:18:04.788024 CH1_RK0: MR19=0xC0C, MR18=0xDCDC, DQSOSC=382, MR23=63, INC=404, DEC=269
6605 13:18:04.788528 ==
6606 13:18:04.791624 Dram Type= 6, Freq= 0, CH_1, rank 1
6607 13:18:04.795588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6608 13:18:04.796094 ==
6609 13:18:04.798865 [Gating] SW mode calibration
6610 13:18:04.804976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6611 13:18:04.808118 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6612 13:18:04.814695 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6613 13:18:04.817683 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6614 13:18:04.821346 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6615 13:18:04.827346 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6616 13:18:04.831279 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6617 13:18:04.834182 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6618 13:18:04.840926 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6619 13:18:04.844593 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6620 13:18:04.847745 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6621 13:18:04.850960 Total UI for P1: 0, mck2ui 16
6622 13:18:04.854467 best dqsien dly found for B0: ( 0, 10, 16)
6623 13:18:04.857537 Total UI for P1: 0, mck2ui 16
6624 13:18:04.861431 best dqsien dly found for B1: ( 0, 10, 16)
6625 13:18:04.864672 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6626 13:18:04.867717 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6627 13:18:04.870890
6628 13:18:04.874440 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6629 13:18:04.877818 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6630 13:18:04.881521 [Gating] SW calibration Done
6631 13:18:04.882156 ==
6632 13:18:04.883909 Dram Type= 6, Freq= 0, CH_1, rank 1
6633 13:18:04.887551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6634 13:18:04.887977 ==
6635 13:18:04.890737 RX Vref Scan: 0
6636 13:18:04.890811
6637 13:18:04.890869 RX Vref 0 -> 0, step: 1
6638 13:18:04.890922
6639 13:18:04.893660 RX Delay -410 -> 252, step: 16
6640 13:18:04.896948 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6641 13:18:04.903401 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6642 13:18:04.906839 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6643 13:18:04.910367 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6644 13:18:04.913863 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6645 13:18:04.920439 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6646 13:18:04.923781 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6647 13:18:04.927012 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6648 13:18:04.929760 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6649 13:18:04.936741 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6650 13:18:04.940524 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6651 13:18:04.943282 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6652 13:18:04.946421 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6653 13:18:04.953808 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6654 13:18:04.956588 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6655 13:18:04.961146 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6656 13:18:04.961265 ==
6657 13:18:04.963570 Dram Type= 6, Freq= 0, CH_1, rank 1
6658 13:18:04.969710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6659 13:18:04.969808 ==
6660 13:18:04.969889 DQS Delay:
6661 13:18:04.973651 DQS0 = 43, DQS1 = 59
6662 13:18:04.973717 DQM Delay:
6663 13:18:04.973770 DQM0 = 9, DQM1 = 17
6664 13:18:04.977035 DQ Delay:
6665 13:18:04.979551 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6666 13:18:04.979625 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6667 13:18:04.983305 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6668 13:18:04.986378 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6669 13:18:04.986454
6670 13:18:04.990272
6671 13:18:04.990352 ==
6672 13:18:04.992878 Dram Type= 6, Freq= 0, CH_1, rank 1
6673 13:18:04.995977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6674 13:18:04.996072 ==
6675 13:18:04.996154
6676 13:18:04.996230
6677 13:18:04.999843 TX Vref Scan disable
6678 13:18:04.999907 == TX Byte 0 ==
6679 13:18:05.002586 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6680 13:18:05.009491 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6681 13:18:05.009581 == TX Byte 1 ==
6682 13:18:05.013028 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6683 13:18:05.019772 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6684 13:18:05.019868 ==
6685 13:18:05.022819 Dram Type= 6, Freq= 0, CH_1, rank 1
6686 13:18:05.026066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6687 13:18:05.026129 ==
6688 13:18:05.026182
6689 13:18:05.026232
6690 13:18:05.029290 TX Vref Scan disable
6691 13:18:05.029360 == TX Byte 0 ==
6692 13:18:05.032891 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6693 13:18:05.039603 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6694 13:18:05.039694 == TX Byte 1 ==
6695 13:18:05.042906 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6696 13:18:05.049009 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6697 13:18:05.049097
6698 13:18:05.049182 [DATLAT]
6699 13:18:05.049309 Freq=400, CH1 RK1
6700 13:18:05.052868
6701 13:18:05.052952 DATLAT Default: 0xd
6702 13:18:05.056191 0, 0xFFFF, sum = 0
6703 13:18:05.056278 1, 0xFFFF, sum = 0
6704 13:18:05.059048 2, 0xFFFF, sum = 0
6705 13:18:05.059134 3, 0xFFFF, sum = 0
6706 13:18:05.063017 4, 0xFFFF, sum = 0
6707 13:18:05.063095 5, 0xFFFF, sum = 0
6708 13:18:05.066056 6, 0xFFFF, sum = 0
6709 13:18:05.066123 7, 0xFFFF, sum = 0
6710 13:18:05.069156 8, 0xFFFF, sum = 0
6711 13:18:05.069293 9, 0xFFFF, sum = 0
6712 13:18:05.072782 10, 0xFFFF, sum = 0
6713 13:18:05.072872 11, 0xFFFF, sum = 0
6714 13:18:05.075846 12, 0x0, sum = 1
6715 13:18:05.075934 13, 0x0, sum = 2
6716 13:18:05.079007 14, 0x0, sum = 3
6717 13:18:05.079083 15, 0x0, sum = 4
6718 13:18:05.082904 best_step = 13
6719 13:18:05.082988
6720 13:18:05.083073 ==
6721 13:18:05.085986 Dram Type= 6, Freq= 0, CH_1, rank 1
6722 13:18:05.088850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6723 13:18:05.088938 ==
6724 13:18:05.092403 RX Vref Scan: 0
6725 13:18:05.092488
6726 13:18:05.092576 RX Vref 0 -> 0, step: 1
6727 13:18:05.092655
6728 13:18:05.096033 RX Delay -359 -> 252, step: 8
6729 13:18:05.104207 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6730 13:18:05.106999 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6731 13:18:05.110353 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6732 13:18:05.113319 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6733 13:18:05.119867 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6734 13:18:05.123382 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6735 13:18:05.126449 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6736 13:18:05.130288 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6737 13:18:05.136871 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6738 13:18:05.139694 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6739 13:18:05.143602 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6740 13:18:05.149692 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6741 13:18:05.152752 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6742 13:18:05.156494 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6743 13:18:05.160104 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6744 13:18:05.166362 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6745 13:18:05.166429 ==
6746 13:18:05.170173 Dram Type= 6, Freq= 0, CH_1, rank 1
6747 13:18:05.172634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6748 13:18:05.172720 ==
6749 13:18:05.172800 DQS Delay:
6750 13:18:05.175911 DQS0 = 48, DQS1 = 64
6751 13:18:05.176002 DQM Delay:
6752 13:18:05.179388 DQM0 = 9, DQM1 = 15
6753 13:18:05.179474 DQ Delay:
6754 13:18:05.183566 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6755 13:18:05.185853 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6756 13:18:05.189208 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6757 13:18:05.193388 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6758 13:18:05.193484
6759 13:18:05.193564
6760 13:18:05.199296 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6761 13:18:05.202621 CH1 RK1: MR19=C0C, MR18=B7B7
6762 13:18:05.209528 CH1_RK1: MR19=0xC0C, MR18=0xB7B7, DQSOSC=387, MR23=63, INC=394, DEC=262
6763 13:18:05.212393 [RxdqsGatingPostProcess] freq 400
6764 13:18:05.219578 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6765 13:18:05.222401 Pre-setting of DQS Precalculation
6766 13:18:05.226280 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6767 13:18:05.232138 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6768 13:18:05.239177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6769 13:18:05.239252
6770 13:18:05.239309
6771 13:18:05.241980 [Calibration Summary] 800 Mbps
6772 13:18:05.245674 CH 0, Rank 0
6773 13:18:05.245748 SW Impedance : PASS
6774 13:18:05.248908 DUTY Scan : NO K
6775 13:18:05.251881 ZQ Calibration : PASS
6776 13:18:05.251955 Jitter Meter : NO K
6777 13:18:05.255583 CBT Training : PASS
6778 13:18:05.259022 Write leveling : PASS
6779 13:18:05.259096 RX DQS gating : PASS
6780 13:18:05.262523 RX DQ/DQS(RDDQC) : PASS
6781 13:18:05.266266 TX DQ/DQS : PASS
6782 13:18:05.266340 RX DATLAT : PASS
6783 13:18:05.268845 RX DQ/DQS(Engine): PASS
6784 13:18:05.272096 TX OE : NO K
6785 13:18:05.272170 All Pass.
6786 13:18:05.272228
6787 13:18:05.272281 CH 0, Rank 1
6788 13:18:05.275451 SW Impedance : PASS
6789 13:18:05.279040 DUTY Scan : NO K
6790 13:18:05.279114 ZQ Calibration : PASS
6791 13:18:05.282350 Jitter Meter : NO K
6792 13:18:05.282425 CBT Training : PASS
6793 13:18:05.285783 Write leveling : NO K
6794 13:18:05.288700 RX DQS gating : PASS
6795 13:18:05.288774 RX DQ/DQS(RDDQC) : PASS
6796 13:18:05.291799 TX DQ/DQS : PASS
6797 13:18:05.296237 RX DATLAT : PASS
6798 13:18:05.296311 RX DQ/DQS(Engine): PASS
6799 13:18:05.298886 TX OE : NO K
6800 13:18:05.298961 All Pass.
6801 13:18:05.299018
6802 13:18:05.301667 CH 1, Rank 0
6803 13:18:05.301741 SW Impedance : PASS
6804 13:18:05.305341 DUTY Scan : NO K
6805 13:18:05.308650 ZQ Calibration : PASS
6806 13:18:05.308724 Jitter Meter : NO K
6807 13:18:05.311872 CBT Training : PASS
6808 13:18:05.314880 Write leveling : PASS
6809 13:18:05.314955 RX DQS gating : PASS
6810 13:18:05.318584 RX DQ/DQS(RDDQC) : PASS
6811 13:18:05.321943 TX DQ/DQS : PASS
6812 13:18:05.322017 RX DATLAT : PASS
6813 13:18:05.325333 RX DQ/DQS(Engine): PASS
6814 13:18:05.328464 TX OE : NO K
6815 13:18:05.328538 All Pass.
6816 13:18:05.328596
6817 13:18:05.328648 CH 1, Rank 1
6818 13:18:05.331535 SW Impedance : PASS
6819 13:18:05.335541 DUTY Scan : NO K
6820 13:18:05.335616 ZQ Calibration : PASS
6821 13:18:05.338689 Jitter Meter : NO K
6822 13:18:05.341527 CBT Training : PASS
6823 13:18:05.341601 Write leveling : NO K
6824 13:18:05.345203 RX DQS gating : PASS
6825 13:18:05.345288 RX DQ/DQS(RDDQC) : PASS
6826 13:18:05.347890 TX DQ/DQS : PASS
6827 13:18:05.351570 RX DATLAT : PASS
6828 13:18:05.351666 RX DQ/DQS(Engine): PASS
6829 13:18:05.355343 TX OE : NO K
6830 13:18:05.355431 All Pass.
6831 13:18:05.355511
6832 13:18:05.358068 DramC Write-DBI off
6833 13:18:05.361083 PER_BANK_REFRESH: Hybrid Mode
6834 13:18:05.361170 TX_TRACKING: ON
6835 13:18:05.371244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6836 13:18:05.374619 [FAST_K] Save calibration result to emmc
6837 13:18:05.378445 dramc_set_vcore_voltage set vcore to 725000
6838 13:18:05.381432 Read voltage for 1600, 0
6839 13:18:05.381525 Vio18 = 0
6840 13:18:05.384645 Vcore = 725000
6841 13:18:05.384709 Vdram = 0
6842 13:18:05.384781 Vddq = 0
6843 13:18:05.384833 Vmddr = 0
6844 13:18:05.391256 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6845 13:18:05.397920 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6846 13:18:05.398020 MEM_TYPE=3, freq_sel=13
6847 13:18:05.401234 sv_algorithm_assistance_LP4_3733
6848 13:18:05.404661 ============ PULL DRAM RESETB DOWN ============
6849 13:18:05.411066 ========== PULL DRAM RESETB DOWN end =========
6850 13:18:05.414492 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6851 13:18:05.417671 ===================================
6852 13:18:05.421039 LPDDR4 DRAM CONFIGURATION
6853 13:18:05.424759 ===================================
6854 13:18:05.424826 EX_ROW_EN[0] = 0x0
6855 13:18:05.427571 EX_ROW_EN[1] = 0x0
6856 13:18:05.427637 LP4Y_EN = 0x0
6857 13:18:05.430880 WORK_FSP = 0x1
6858 13:18:05.430967 WL = 0x5
6859 13:18:05.434301 RL = 0x5
6860 13:18:05.434362 BL = 0x2
6861 13:18:05.437646 RPST = 0x0
6862 13:18:05.441353 RD_PRE = 0x0
6863 13:18:05.441444 WR_PRE = 0x1
6864 13:18:05.444364 WR_PST = 0x1
6865 13:18:05.444456 DBI_WR = 0x0
6866 13:18:05.447504 DBI_RD = 0x0
6867 13:18:05.447588 OTF = 0x1
6868 13:18:05.450906 ===================================
6869 13:18:05.453933 ===================================
6870 13:18:05.457331 ANA top config
6871 13:18:05.460485 ===================================
6872 13:18:05.460577 DLL_ASYNC_EN = 0
6873 13:18:05.464320 ALL_SLAVE_EN = 0
6874 13:18:05.467337 NEW_RANK_MODE = 1
6875 13:18:05.470380 DLL_IDLE_MODE = 1
6876 13:18:05.470445 LP45_APHY_COMB_EN = 1
6877 13:18:05.474146 TX_ODT_DIS = 0
6878 13:18:05.477725 NEW_8X_MODE = 1
6879 13:18:05.481382 ===================================
6880 13:18:05.483714 ===================================
6881 13:18:05.487406 data_rate = 3200
6882 13:18:05.490400 CKR = 1
6883 13:18:05.494323 DQ_P2S_RATIO = 8
6884 13:18:05.498029 ===================================
6885 13:18:05.498104 CA_P2S_RATIO = 8
6886 13:18:05.500735 DQ_CA_OPEN = 0
6887 13:18:05.503836 DQ_SEMI_OPEN = 0
6888 13:18:05.507036 CA_SEMI_OPEN = 0
6889 13:18:05.509985 CA_FULL_RATE = 0
6890 13:18:05.513470 DQ_CKDIV4_EN = 0
6891 13:18:05.513543 CA_CKDIV4_EN = 0
6892 13:18:05.517118 CA_PREDIV_EN = 0
6893 13:18:05.520079 PH8_DLY = 12
6894 13:18:05.523382 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6895 13:18:05.527371 DQ_AAMCK_DIV = 4
6896 13:18:05.530105 CA_AAMCK_DIV = 4
6897 13:18:05.530170 CA_ADMCK_DIV = 4
6898 13:18:05.534016 DQ_TRACK_CA_EN = 0
6899 13:18:05.536839 CA_PICK = 1600
6900 13:18:05.540290 CA_MCKIO = 1600
6901 13:18:05.543444 MCKIO_SEMI = 0
6902 13:18:05.546963 PLL_FREQ = 3068
6903 13:18:05.549876 DQ_UI_PI_RATIO = 32
6904 13:18:05.549955 CA_UI_PI_RATIO = 0
6905 13:18:05.553283 ===================================
6906 13:18:05.557122 ===================================
6907 13:18:05.560745 memory_type:LPDDR4
6908 13:18:05.563710 GP_NUM : 10
6909 13:18:05.563798 SRAM_EN : 1
6910 13:18:05.566593 MD32_EN : 0
6911 13:18:05.569680 ===================================
6912 13:18:05.573379 [ANA_INIT] >>>>>>>>>>>>>>
6913 13:18:05.576765 <<<<<< [CONFIGURE PHASE]: ANA_TX
6914 13:18:05.580004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6915 13:18:05.583752 ===================================
6916 13:18:05.583844 data_rate = 3200,PCW = 0X7600
6917 13:18:05.587227 ===================================
6918 13:18:05.590007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6919 13:18:05.596435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6920 13:18:05.603492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6921 13:18:05.607170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6922 13:18:05.610723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6923 13:18:05.613189 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6924 13:18:05.616516 [ANA_INIT] flow start
6925 13:18:05.616593 [ANA_INIT] PLL >>>>>>>>
6926 13:18:05.620070 [ANA_INIT] PLL <<<<<<<<
6927 13:18:05.623341 [ANA_INIT] MIDPI >>>>>>>>
6928 13:18:05.626362 [ANA_INIT] MIDPI <<<<<<<<
6929 13:18:05.626436 [ANA_INIT] DLL >>>>>>>>
6930 13:18:05.629531 [ANA_INIT] DLL <<<<<<<<
6931 13:18:05.632928 [ANA_INIT] flow end
6932 13:18:05.636285 ============ LP4 DIFF to SE enter ============
6933 13:18:05.639860 ============ LP4 DIFF to SE exit ============
6934 13:18:05.643065 [ANA_INIT] <<<<<<<<<<<<<
6935 13:18:05.646782 [Flow] Enable top DCM control >>>>>
6936 13:18:05.650101 [Flow] Enable top DCM control <<<<<
6937 13:18:05.653319 Enable DLL master slave shuffle
6938 13:18:05.656406 ==============================================================
6939 13:18:05.659896 Gating Mode config
6940 13:18:05.665939 ==============================================================
6941 13:18:05.666014 Config description:
6942 13:18:05.676234 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6943 13:18:05.683252 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6944 13:18:05.686326 SELPH_MODE 0: By rank 1: By Phase
6945 13:18:05.692969 ==============================================================
6946 13:18:05.696708 GAT_TRACK_EN = 1
6947 13:18:05.699186 RX_GATING_MODE = 2
6948 13:18:05.703024 RX_GATING_TRACK_MODE = 2
6949 13:18:05.706497 SELPH_MODE = 1
6950 13:18:05.709503 PICG_EARLY_EN = 1
6951 13:18:05.712931 VALID_LAT_VALUE = 1
6952 13:18:05.715983 ==============================================================
6953 13:18:05.719096 Enter into Gating configuration >>>>
6954 13:18:05.722477 Exit from Gating configuration <<<<
6955 13:18:05.725687 Enter into DVFS_PRE_config >>>>>
6956 13:18:05.735934 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6957 13:18:05.739636 Exit from DVFS_PRE_config <<<<<
6958 13:18:05.742511 Enter into PICG configuration >>>>
6959 13:18:05.745889 Exit from PICG configuration <<<<
6960 13:18:05.749030 [RX_INPUT] configuration >>>>>
6961 13:18:05.752274 [RX_INPUT] configuration <<<<<
6962 13:18:05.759898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6963 13:18:05.762145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6964 13:18:05.768978 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6965 13:18:05.775744 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6966 13:18:05.782015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6967 13:18:05.788861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6968 13:18:05.792110 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6969 13:18:05.795920 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6970 13:18:05.800051 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6971 13:18:05.806012 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6972 13:18:05.808883 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6973 13:18:05.812660 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6974 13:18:05.815724 ===================================
6975 13:18:05.818364 LPDDR4 DRAM CONFIGURATION
6976 13:18:05.822123 ===================================
6977 13:18:05.825030 EX_ROW_EN[0] = 0x0
6978 13:18:05.825106 EX_ROW_EN[1] = 0x0
6979 13:18:05.828478 LP4Y_EN = 0x0
6980 13:18:05.828555 WORK_FSP = 0x1
6981 13:18:05.831876 WL = 0x5
6982 13:18:05.831952 RL = 0x5
6983 13:18:05.835671 BL = 0x2
6984 13:18:05.835747 RPST = 0x0
6985 13:18:05.838184 RD_PRE = 0x0
6986 13:18:05.838261 WR_PRE = 0x1
6987 13:18:05.841636 WR_PST = 0x1
6988 13:18:05.841713 DBI_WR = 0x0
6989 13:18:05.845166 DBI_RD = 0x0
6990 13:18:05.845267 OTF = 0x1
6991 13:18:05.848703 ===================================
6992 13:18:05.851904 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6993 13:18:05.858309 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6994 13:18:05.862390 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6995 13:18:05.865033 ===================================
6996 13:18:05.868748 LPDDR4 DRAM CONFIGURATION
6997 13:18:05.871729 ===================================
6998 13:18:05.871806 EX_ROW_EN[0] = 0x10
6999 13:18:05.874810 EX_ROW_EN[1] = 0x0
7000 13:18:05.878258 LP4Y_EN = 0x0
7001 13:18:05.878335 WORK_FSP = 0x1
7002 13:18:05.881456 WL = 0x5
7003 13:18:05.881533 RL = 0x5
7004 13:18:05.884579 BL = 0x2
7005 13:18:05.884669 RPST = 0x0
7006 13:18:05.888329 RD_PRE = 0x0
7007 13:18:05.888405 WR_PRE = 0x1
7008 13:18:05.891537 WR_PST = 0x1
7009 13:18:05.891615 DBI_WR = 0x0
7010 13:18:05.894614 DBI_RD = 0x0
7011 13:18:05.894690 OTF = 0x1
7012 13:18:05.898304 ===================================
7013 13:18:05.904848 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7014 13:18:05.904925 ==
7015 13:18:05.908108 Dram Type= 6, Freq= 0, CH_0, rank 0
7016 13:18:05.913071 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7017 13:18:05.914603 ==
7018 13:18:05.914680 [Duty_Offset_Calibration]
7019 13:18:05.918544 B0:0 B1:2 CA:1
7020 13:18:05.918620
7021 13:18:05.921567 [DutyScan_Calibration_Flow] k_type=0
7022 13:18:05.930476
7023 13:18:05.930552 ==CLK 0==
7024 13:18:05.933603 Final CLK duty delay cell = 0
7025 13:18:05.936530 [0] MAX Duty = 5156%(X100), DQS PI = 22
7026 13:18:05.940332 [0] MIN Duty = 4938%(X100), DQS PI = 52
7027 13:18:05.943516 [0] AVG Duty = 5047%(X100)
7028 13:18:05.943592
7029 13:18:05.946819 CH0 CLK Duty spec in!! Max-Min= 218%
7030 13:18:05.949784 [DutyScan_Calibration_Flow] ====Done====
7031 13:18:05.949860
7032 13:18:05.953512 [DutyScan_Calibration_Flow] k_type=1
7033 13:18:05.969991
7034 13:18:05.970068 ==DQS 0 ==
7035 13:18:05.973497 Final DQS duty delay cell = 0
7036 13:18:05.976926 [0] MAX Duty = 5125%(X100), DQS PI = 32
7037 13:18:05.980147 [0] MIN Duty = 5031%(X100), DQS PI = 8
7038 13:18:05.983372 [0] AVG Duty = 5078%(X100)
7039 13:18:05.983449
7040 13:18:05.983525 ==DQS 1 ==
7041 13:18:05.986514 Final DQS duty delay cell = 0
7042 13:18:05.989902 [0] MAX Duty = 5031%(X100), DQS PI = 2
7043 13:18:05.994161 [0] MIN Duty = 4844%(X100), DQS PI = 18
7044 13:18:05.994238 [0] AVG Duty = 4937%(X100)
7045 13:18:05.996912
7046 13:18:06.000368 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7047 13:18:06.000445
7048 13:18:06.003033 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7049 13:18:06.006530 [DutyScan_Calibration_Flow] ====Done====
7050 13:18:06.006606
7051 13:18:06.009669 [DutyScan_Calibration_Flow] k_type=3
7052 13:18:06.027558
7053 13:18:06.027633 ==DQM 0 ==
7054 13:18:06.030598 Final DQM duty delay cell = 0
7055 13:18:06.033912 [0] MAX Duty = 5187%(X100), DQS PI = 22
7056 13:18:06.036757 [0] MIN Duty = 4907%(X100), DQS PI = 42
7057 13:18:06.040843 [0] AVG Duty = 5047%(X100)
7058 13:18:06.040920
7059 13:18:06.040995 ==DQM 1 ==
7060 13:18:06.044189 Final DQM duty delay cell = 0
7061 13:18:06.046948 [0] MAX Duty = 5031%(X100), DQS PI = 52
7062 13:18:06.050004 [0] MIN Duty = 4782%(X100), DQS PI = 16
7063 13:18:06.053740 [0] AVG Duty = 4906%(X100)
7064 13:18:06.053816
7065 13:18:06.056728 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7066 13:18:06.056803
7067 13:18:06.060010 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7068 13:18:06.063387 [DutyScan_Calibration_Flow] ====Done====
7069 13:18:06.063466
7070 13:18:06.067208 [DutyScan_Calibration_Flow] k_type=2
7071 13:18:06.083277
7072 13:18:06.083352 ==DQ 0 ==
7073 13:18:06.087067 Final DQ duty delay cell = 0
7074 13:18:06.090268 [0] MAX Duty = 5218%(X100), DQS PI = 18
7075 13:18:06.093278 [0] MIN Duty = 4938%(X100), DQS PI = 56
7076 13:18:06.093368 [0] AVG Duty = 5078%(X100)
7077 13:18:06.097086
7078 13:18:06.097161 ==DQ 1 ==
7079 13:18:06.100280 Final DQ duty delay cell = -4
7080 13:18:06.103515 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7081 13:18:06.106332 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7082 13:18:06.110089 [-4] AVG Duty = 4953%(X100)
7083 13:18:06.110164
7084 13:18:06.113299 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7085 13:18:06.113388
7086 13:18:06.116501 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7087 13:18:06.120539 [DutyScan_Calibration_Flow] ====Done====
7088 13:18:06.120616 ==
7089 13:18:06.122937 Dram Type= 6, Freq= 0, CH_1, rank 0
7090 13:18:06.126784 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7091 13:18:06.126860 ==
7092 13:18:06.129550 [Duty_Offset_Calibration]
7093 13:18:06.129627 B0:0 B1:5 CA:-5
7094 13:18:06.129702
7095 13:18:06.132771 [DutyScan_Calibration_Flow] k_type=0
7096 13:18:06.144937
7097 13:18:06.145012 ==CLK 0==
7098 13:18:06.147613 Final CLK duty delay cell = 0
7099 13:18:06.150560 [0] MAX Duty = 5156%(X100), DQS PI = 22
7100 13:18:06.154229 [0] MIN Duty = 4875%(X100), DQS PI = 50
7101 13:18:06.157253 [0] AVG Duty = 5015%(X100)
7102 13:18:06.157329
7103 13:18:06.160667 CH1 CLK Duty spec in!! Max-Min= 281%
7104 13:18:06.164125 [DutyScan_Calibration_Flow] ====Done====
7105 13:18:06.164201
7106 13:18:06.167383 [DutyScan_Calibration_Flow] k_type=1
7107 13:18:06.183356
7108 13:18:06.183432 ==DQS 0 ==
7109 13:18:06.186307 Final DQS duty delay cell = 0
7110 13:18:06.189401 [0] MAX Duty = 5187%(X100), DQS PI = 20
7111 13:18:06.193097 [0] MIN Duty = 4876%(X100), DQS PI = 42
7112 13:18:06.196311 [0] AVG Duty = 5031%(X100)
7113 13:18:06.196390
7114 13:18:06.196467 ==DQS 1 ==
7115 13:18:06.199819 Final DQS duty delay cell = -4
7116 13:18:06.202794 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7117 13:18:06.206802 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7118 13:18:06.209412 [-4] AVG Duty = 4922%(X100)
7119 13:18:06.209490
7120 13:18:06.212777 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7121 13:18:06.212877
7122 13:18:06.215882 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7123 13:18:06.219126 [DutyScan_Calibration_Flow] ====Done====
7124 13:18:06.219200
7125 13:18:06.222176 [DutyScan_Calibration_Flow] k_type=3
7126 13:18:06.239169
7127 13:18:06.239258 ==DQM 0 ==
7128 13:18:06.242775 Final DQM duty delay cell = -4
7129 13:18:06.245382 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7130 13:18:06.249010 [-4] MIN Duty = 4782%(X100), DQS PI = 42
7131 13:18:06.252170 [-4] AVG Duty = 4922%(X100)
7132 13:18:06.252235
7133 13:18:06.252294 ==DQM 1 ==
7134 13:18:06.255187 Final DQM duty delay cell = -4
7135 13:18:06.258547 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7136 13:18:06.262105 [-4] MIN Duty = 4876%(X100), DQS PI = 40
7137 13:18:06.266485 [-4] AVG Duty = 4969%(X100)
7138 13:18:06.266557
7139 13:18:06.268326 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7140 13:18:06.268388
7141 13:18:06.273090 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7142 13:18:06.275128 [DutyScan_Calibration_Flow] ====Done====
7143 13:18:06.275194
7144 13:18:06.278486 [DutyScan_Calibration_Flow] k_type=2
7145 13:18:06.296739
7146 13:18:06.296810 ==DQ 0 ==
7147 13:18:06.299726 Final DQ duty delay cell = 0
7148 13:18:06.302981 [0] MAX Duty = 5093%(X100), DQS PI = 34
7149 13:18:06.306980 [0] MIN Duty = 4938%(X100), DQS PI = 48
7150 13:18:06.307056 [0] AVG Duty = 5015%(X100)
7151 13:18:06.309520
7152 13:18:06.309594 ==DQ 1 ==
7153 13:18:06.313092 Final DQ duty delay cell = 0
7154 13:18:06.316805 [0] MAX Duty = 5031%(X100), DQS PI = 4
7155 13:18:06.320196 [0] MIN Duty = 4875%(X100), DQS PI = 30
7156 13:18:06.320271 [0] AVG Duty = 4953%(X100)
7157 13:18:06.320329
7158 13:18:06.323198 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7159 13:18:06.326689
7160 13:18:06.329671 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7161 13:18:06.333280 [DutyScan_Calibration_Flow] ====Done====
7162 13:18:06.336214 nWR fixed to 30
7163 13:18:06.336290 [ModeRegInit_LP4] CH0 RK0
7164 13:18:06.339523 [ModeRegInit_LP4] CH0 RK1
7165 13:18:06.342649 [ModeRegInit_LP4] CH1 RK0
7166 13:18:06.346058 [ModeRegInit_LP4] CH1 RK1
7167 13:18:06.346132 match AC timing 4
7168 13:18:06.349756 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7169 13:18:06.356734 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7170 13:18:06.359970 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7171 13:18:06.366203 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7172 13:18:06.368915 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7173 13:18:06.368990 [MiockJmeterHQA]
7174 13:18:06.369046
7175 13:18:06.372546 [DramcMiockJmeter] u1RxGatingPI = 0
7176 13:18:06.376643 0 : 4252, 4027
7177 13:18:06.376719 4 : 4363, 4137
7178 13:18:06.378901 8 : 4252, 4027
7179 13:18:06.378976 12 : 4252, 4027
7180 13:18:06.379033 16 : 4365, 4140
7181 13:18:06.383081 20 : 4252, 4027
7182 13:18:06.383157 24 : 4252, 4027
7183 13:18:06.385673 28 : 4253, 4026
7184 13:18:06.385748 32 : 4363, 4138
7185 13:18:06.390073 36 : 4363, 4137
7186 13:18:06.390148 40 : 4252, 4027
7187 13:18:06.392474 44 : 4253, 4027
7188 13:18:06.392551 48 : 4252, 4026
7189 13:18:06.392609 52 : 4252, 4027
7190 13:18:06.395979 56 : 4252, 4027
7191 13:18:06.396079 60 : 4361, 4137
7192 13:18:06.398976 64 : 4250, 4027
7193 13:18:06.399051 68 : 4250, 4026
7194 13:18:06.402882 72 : 4250, 4027
7195 13:18:06.403010 76 : 4255, 4031
7196 13:18:06.403067 80 : 4250, 4026
7197 13:18:06.405847 84 : 4360, 4138
7198 13:18:06.405936 88 : 4360, 4137
7199 13:18:06.409713 92 : 4250, 4027
7200 13:18:06.409801 96 : 4250, 4026
7201 13:18:06.412391 100 : 4250, 1985
7202 13:18:06.412457 104 : 4250, 0
7203 13:18:06.415876 108 : 4361, 0
7204 13:18:06.415948 112 : 4250, 0
7205 13:18:06.416020 116 : 4250, 0
7206 13:18:06.418970 120 : 4250, 0
7207 13:18:06.419063 124 : 4249, 0
7208 13:18:06.419135 128 : 4250, 0
7209 13:18:06.422531 132 : 4250, 0
7210 13:18:06.422597 136 : 4249, 0
7211 13:18:06.425315 140 : 4360, 0
7212 13:18:06.425392 144 : 4250, 0
7213 13:18:06.425469 148 : 4250, 0
7214 13:18:06.429264 152 : 4250, 0
7215 13:18:06.429357 156 : 4250, 0
7216 13:18:06.432233 160 : 4250, 0
7217 13:18:06.432310 164 : 4250, 0
7218 13:18:06.432387 168 : 4250, 0
7219 13:18:06.435859 172 : 4250, 0
7220 13:18:06.435937 176 : 4253, 0
7221 13:18:06.438828 180 : 4250, 0
7222 13:18:06.438905 184 : 4250, 0
7223 13:18:06.438982 188 : 4249, 0
7224 13:18:06.442072 192 : 4360, 0
7225 13:18:06.442151 196 : 4361, 0
7226 13:18:06.442228 200 : 4360, 0
7227 13:18:06.445555 204 : 4250, 0
7228 13:18:06.445631 208 : 4250, 0
7229 13:18:06.449305 212 : 4250, 0
7230 13:18:06.449386 216 : 4250, 0
7231 13:18:06.449464 220 : 4250, 568
7232 13:18:06.451981 224 : 4249, 3992
7233 13:18:06.452059 228 : 4361, 4138
7234 13:18:06.455886 232 : 4360, 4137
7235 13:18:06.455963 236 : 4250, 4027
7236 13:18:06.458444 240 : 4250, 4027
7237 13:18:06.458522 244 : 4360, 4137
7238 13:18:06.462259 248 : 4250, 4026
7239 13:18:06.462337 252 : 4250, 4027
7240 13:18:06.465433 256 : 4250, 4027
7241 13:18:06.465511 260 : 4249, 4027
7242 13:18:06.468886 264 : 4250, 4026
7243 13:18:06.468964 268 : 4250, 4027
7244 13:18:06.471757 272 : 4360, 4138
7245 13:18:06.471835 276 : 4249, 4027
7246 13:18:06.475587 280 : 4250, 4026
7247 13:18:06.475664 284 : 4361, 4137
7248 13:18:06.475741 288 : 4250, 4027
7249 13:18:06.478583 292 : 4250, 4026
7250 13:18:06.478660 296 : 4250, 4027
7251 13:18:06.482033 300 : 4250, 4026
7252 13:18:06.482110 304 : 4250, 4027
7253 13:18:06.485879 308 : 4250, 4027
7254 13:18:06.485957 312 : 4249, 4027
7255 13:18:06.488451 316 : 4250, 4026
7256 13:18:06.488529 320 : 4250, 4027
7257 13:18:06.491798 324 : 4360, 4138
7258 13:18:06.491876 328 : 4249, 4027
7259 13:18:06.495293 332 : 4250, 4026
7260 13:18:06.495370 336 : 4361, 4021
7261 13:18:06.495448 340 : 4250, 1849
7262 13:18:06.499133
7263 13:18:06.499239 MIOCK jitter meter ch=0
7264 13:18:06.499314
7265 13:18:06.501971 1T = (340-100) = 240 dly cells
7266 13:18:06.508523 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7267 13:18:06.508621 ==
7268 13:18:06.511636 Dram Type= 6, Freq= 0, CH_0, rank 0
7269 13:18:06.515460 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7270 13:18:06.515551 ==
7271 13:18:06.521654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7272 13:18:06.525188 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7273 13:18:06.528408 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7274 13:18:06.534990 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7275 13:18:06.543645 [CA 0] Center 42 (12~72) winsize 61
7276 13:18:06.547062 [CA 1] Center 41 (11~72) winsize 62
7277 13:18:06.550592 [CA 2] Center 37 (7~68) winsize 62
7278 13:18:06.553641 [CA 3] Center 37 (7~67) winsize 61
7279 13:18:06.557216 [CA 4] Center 35 (5~66) winsize 62
7280 13:18:06.559858 [CA 5] Center 35 (5~65) winsize 61
7281 13:18:06.559934
7282 13:18:06.563675 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7283 13:18:06.563750
7284 13:18:06.566495 [CATrainingPosCal] consider 1 rank data
7285 13:18:06.570221 u2DelayCellTimex100 = 271/100 ps
7286 13:18:06.573686 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7287 13:18:06.580874 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7288 13:18:06.583445 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7289 13:18:06.586525 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7290 13:18:06.590231 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7291 13:18:06.593454 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7292 13:18:06.593531
7293 13:18:06.596365 CA PerBit enable=1, Macro0, CA PI delay=35
7294 13:18:06.596441
7295 13:18:06.600302 [CBTSetCACLKResult] CA Dly = 35
7296 13:18:06.603515 CS Dly: 11 (0~42)
7297 13:18:06.606417 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7298 13:18:06.609710 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7299 13:18:06.609776 ==
7300 13:18:06.613203 Dram Type= 6, Freq= 0, CH_0, rank 1
7301 13:18:06.616880 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7302 13:18:06.620286 ==
7303 13:18:06.622786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7304 13:18:06.626390 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7305 13:18:06.632974 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7306 13:18:06.636108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7307 13:18:06.646159 [CA 0] Center 42 (12~73) winsize 62
7308 13:18:06.649525 [CA 1] Center 42 (12~73) winsize 62
7309 13:18:06.652702 [CA 2] Center 38 (9~68) winsize 60
7310 13:18:06.656349 [CA 3] Center 37 (8~67) winsize 60
7311 13:18:06.659480 [CA 4] Center 36 (6~66) winsize 61
7312 13:18:06.663071 [CA 5] Center 36 (6~66) winsize 61
7313 13:18:06.663146
7314 13:18:06.666301 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7315 13:18:06.666375
7316 13:18:06.669824 [CATrainingPosCal] consider 2 rank data
7317 13:18:06.672586 u2DelayCellTimex100 = 271/100 ps
7318 13:18:06.675736 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7319 13:18:06.683109 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7320 13:18:06.686414 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7321 13:18:06.689447 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7322 13:18:06.692665 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7323 13:18:06.696111 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7324 13:18:06.696186
7325 13:18:06.699435 CA PerBit enable=1, Macro0, CA PI delay=35
7326 13:18:06.699510
7327 13:18:06.702565 [CBTSetCACLKResult] CA Dly = 35
7328 13:18:06.705792 CS Dly: 11 (0~42)
7329 13:18:06.708920 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7330 13:18:06.712982 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7331 13:18:06.713056
7332 13:18:06.715622 ----->DramcWriteLeveling(PI) begin...
7333 13:18:06.715721 ==
7334 13:18:06.719507 Dram Type= 6, Freq= 0, CH_0, rank 0
7335 13:18:06.726463 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7336 13:18:06.726538 ==
7337 13:18:06.729170 Write leveling (Byte 0): 29 => 29
7338 13:18:06.729300 Write leveling (Byte 1): 26 => 26
7339 13:18:06.733379 DramcWriteLeveling(PI) end<-----
7340 13:18:06.733452
7341 13:18:06.733509 ==
7342 13:18:06.735509 Dram Type= 6, Freq= 0, CH_0, rank 0
7343 13:18:06.742347 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7344 13:18:06.742419 ==
7345 13:18:06.745746 [Gating] SW mode calibration
7346 13:18:06.752317 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7347 13:18:06.756140 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7348 13:18:06.762702 0 12 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7349 13:18:06.765780 0 12 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7350 13:18:06.768906 0 12 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7351 13:18:06.775921 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7352 13:18:06.778999 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7353 13:18:06.782155 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7354 13:18:06.788887 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7355 13:18:06.792484 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7356 13:18:06.795553 0 13 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7357 13:18:06.801723 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (1 0) (1 0)
7358 13:18:06.805475 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7359 13:18:06.809016 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7360 13:18:06.815292 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7361 13:18:06.818456 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7362 13:18:06.822458 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7363 13:18:06.828660 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7364 13:18:06.832483 0 14 0 | B1->B0 | 2323 3838 | 1 0 | (0 0) (1 1)
7365 13:18:06.835269 0 14 4 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7366 13:18:06.842060 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7367 13:18:06.845448 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7368 13:18:06.848902 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7369 13:18:06.851843 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7370 13:18:06.858468 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7371 13:18:06.861662 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7372 13:18:06.865401 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7373 13:18:06.871629 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7374 13:18:06.875698 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7375 13:18:06.878675 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7376 13:18:06.885426 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7377 13:18:06.888498 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7378 13:18:06.891339 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7379 13:18:06.898589 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7380 13:18:06.901919 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7381 13:18:06.904655 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7382 13:18:06.912115 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7383 13:18:06.915184 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7384 13:18:06.918600 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7385 13:18:06.925274 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7386 13:18:06.928154 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7387 13:18:06.932479 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7388 13:18:06.938145 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7389 13:18:06.941871 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7390 13:18:06.944655 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7391 13:18:06.947917 Total UI for P1: 0, mck2ui 16
7392 13:18:06.951694 best dqsien dly found for B0: ( 1, 1, 2)
7393 13:18:06.958529 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7394 13:18:06.958604 Total UI for P1: 0, mck2ui 16
7395 13:18:06.961521 best dqsien dly found for B1: ( 1, 1, 6)
7396 13:18:06.967848 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7397 13:18:06.971306 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7398 13:18:06.971380
7399 13:18:06.974445 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7400 13:18:06.978398 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7401 13:18:06.980848 [Gating] SW calibration Done
7402 13:18:06.980922 ==
7403 13:18:06.984413 Dram Type= 6, Freq= 0, CH_0, rank 0
7404 13:18:06.988314 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7405 13:18:06.988389 ==
7406 13:18:06.988446 RX Vref Scan: 0
7407 13:18:06.991109
7408 13:18:06.991182 RX Vref 0 -> 0, step: 1
7409 13:18:06.991239
7410 13:18:06.994504 RX Delay 0 -> 252, step: 8
7411 13:18:06.998142 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7412 13:18:07.001153 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7413 13:18:07.008069 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7414 13:18:07.010986 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7415 13:18:07.014418 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7416 13:18:07.017812 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7417 13:18:07.020857 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7418 13:18:07.027888 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7419 13:18:07.030787 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7420 13:18:07.033982 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7421 13:18:07.038676 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7422 13:18:07.040956 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7423 13:18:07.047395 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7424 13:18:07.050431 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7425 13:18:07.053714 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7426 13:18:07.057277 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7427 13:18:07.057353 ==
7428 13:18:07.060785 Dram Type= 6, Freq= 0, CH_0, rank 0
7429 13:18:07.067295 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7430 13:18:07.067371 ==
7431 13:18:07.067429 DQS Delay:
7432 13:18:07.070836 DQS0 = 0, DQS1 = 0
7433 13:18:07.070911 DQM Delay:
7434 13:18:07.073946 DQM0 = 130, DQM1 = 124
7435 13:18:07.074021 DQ Delay:
7436 13:18:07.077284 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7437 13:18:07.080283 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7438 13:18:07.083947 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7439 13:18:07.087073 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7440 13:18:07.087148
7441 13:18:07.087205
7442 13:18:07.087258 ==
7443 13:18:07.090131 Dram Type= 6, Freq= 0, CH_0, rank 0
7444 13:18:07.097062 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7445 13:18:07.097160 ==
7446 13:18:07.097250
7447 13:18:07.097306
7448 13:18:07.097357 TX Vref Scan disable
7449 13:18:07.100632 == TX Byte 0 ==
7450 13:18:07.103770 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7451 13:18:07.110778 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7452 13:18:07.110853 == TX Byte 1 ==
7453 13:18:07.113378 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7454 13:18:07.120350 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7455 13:18:07.120425 ==
7456 13:18:07.123757 Dram Type= 6, Freq= 0, CH_0, rank 0
7457 13:18:07.126612 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7458 13:18:07.126686 ==
7459 13:18:07.139053
7460 13:18:07.142786 TX Vref early break, caculate TX vref
7461 13:18:07.145598 TX Vref=16, minBit 8, minWin=22, winSum=368
7462 13:18:07.149191 TX Vref=18, minBit 8, minWin=22, winSum=377
7463 13:18:07.152605 TX Vref=20, minBit 9, minWin=22, winSum=384
7464 13:18:07.155487 TX Vref=22, minBit 8, minWin=24, winSum=397
7465 13:18:07.159255 TX Vref=24, minBit 8, minWin=24, winSum=405
7466 13:18:07.165385 TX Vref=26, minBit 7, minWin=25, winSum=412
7467 13:18:07.168560 TX Vref=28, minBit 8, minWin=24, winSum=413
7468 13:18:07.172224 TX Vref=30, minBit 0, minWin=25, winSum=411
7469 13:18:07.175467 TX Vref=32, minBit 6, minWin=24, winSum=402
7470 13:18:07.178913 TX Vref=34, minBit 8, minWin=23, winSum=390
7471 13:18:07.185743 [TxChooseVref] Worse bit 7, Min win 25, Win sum 412, Final Vref 26
7472 13:18:07.185819
7473 13:18:07.188635 Final TX Range 0 Vref 26
7474 13:18:07.188710
7475 13:18:07.188767 ==
7476 13:18:07.192491 Dram Type= 6, Freq= 0, CH_0, rank 0
7477 13:18:07.195175 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7478 13:18:07.195251 ==
7479 13:18:07.195309
7480 13:18:07.195361
7481 13:18:07.198484 TX Vref Scan disable
7482 13:18:07.205703 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7483 13:18:07.205779 == TX Byte 0 ==
7484 13:18:07.208763 u2DelayCellOfst[0]=10 cells (3 PI)
7485 13:18:07.212143 u2DelayCellOfst[1]=18 cells (5 PI)
7486 13:18:07.214844 u2DelayCellOfst[2]=14 cells (4 PI)
7487 13:18:07.218835 u2DelayCellOfst[3]=10 cells (3 PI)
7488 13:18:07.222429 u2DelayCellOfst[4]=7 cells (2 PI)
7489 13:18:07.225102 u2DelayCellOfst[5]=0 cells (0 PI)
7490 13:18:07.228229 u2DelayCellOfst[6]=18 cells (5 PI)
7491 13:18:07.231789 u2DelayCellOfst[7]=18 cells (5 PI)
7492 13:18:07.235399 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7493 13:18:07.238407 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7494 13:18:07.241733 == TX Byte 1 ==
7495 13:18:07.244964 u2DelayCellOfst[8]=3 cells (1 PI)
7496 13:18:07.245038 u2DelayCellOfst[9]=0 cells (0 PI)
7497 13:18:07.248508 u2DelayCellOfst[10]=10 cells (3 PI)
7498 13:18:07.251404 u2DelayCellOfst[11]=3 cells (1 PI)
7499 13:18:07.255374 u2DelayCellOfst[12]=14 cells (4 PI)
7500 13:18:07.258354 u2DelayCellOfst[13]=14 cells (4 PI)
7501 13:18:07.261667 u2DelayCellOfst[14]=18 cells (5 PI)
7502 13:18:07.265001 u2DelayCellOfst[15]=18 cells (5 PI)
7503 13:18:07.267972 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7504 13:18:07.274806 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7505 13:18:07.274882 DramC Write-DBI on
7506 13:18:07.274940 ==
7507 13:18:07.278215 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 13:18:07.284969 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7509 13:18:07.285044 ==
7510 13:18:07.285101
7511 13:18:07.285154
7512 13:18:07.285204 TX Vref Scan disable
7513 13:18:07.288553 == TX Byte 0 ==
7514 13:18:07.292018 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7515 13:18:07.296316 == TX Byte 1 ==
7516 13:18:07.298882 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7517 13:18:07.302096 DramC Write-DBI off
7518 13:18:07.302170
7519 13:18:07.302228 [DATLAT]
7520 13:18:07.302281 Freq=1600, CH0 RK0
7521 13:18:07.302333
7522 13:18:07.305548 DATLAT Default: 0xf
7523 13:18:07.305622 0, 0xFFFF, sum = 0
7524 13:18:07.308307 1, 0xFFFF, sum = 0
7525 13:18:07.311864 2, 0xFFFF, sum = 0
7526 13:18:07.311940 3, 0xFFFF, sum = 0
7527 13:18:07.315231 4, 0xFFFF, sum = 0
7528 13:18:07.315306 5, 0xFFFF, sum = 0
7529 13:18:07.318955 6, 0xFFFF, sum = 0
7530 13:18:07.319031 7, 0xFFFF, sum = 0
7531 13:18:07.322709 8, 0xFFFF, sum = 0
7532 13:18:07.322785 9, 0xFFFF, sum = 0
7533 13:18:07.325269 10, 0xFFFF, sum = 0
7534 13:18:07.325346 11, 0xFFFF, sum = 0
7535 13:18:07.328635 12, 0xBFF, sum = 0
7536 13:18:07.328711 13, 0x0, sum = 1
7537 13:18:07.332063 14, 0x0, sum = 2
7538 13:18:07.332138 15, 0x0, sum = 3
7539 13:18:07.334858 16, 0x0, sum = 4
7540 13:18:07.334935 best_step = 14
7541 13:18:07.334992
7542 13:18:07.335045 ==
7543 13:18:07.338208 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 13:18:07.342135 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7545 13:18:07.344970 ==
7546 13:18:07.345044 RX Vref Scan: 1
7547 13:18:07.345101
7548 13:18:07.348134 Set Vref Range= 24 -> 127
7549 13:18:07.348207
7550 13:18:07.348265 RX Vref 24 -> 127, step: 1
7551 13:18:07.351888
7552 13:18:07.351962 RX Delay 11 -> 252, step: 4
7553 13:18:07.352020
7554 13:18:07.355059 Set Vref, RX VrefLevel [Byte0]: 24
7555 13:18:07.360807 [Byte1]: 24
7556 13:18:07.362759
7557 13:18:07.362833 Set Vref, RX VrefLevel [Byte0]: 25
7558 13:18:07.365702 [Byte1]: 25
7559 13:18:07.369844
7560 13:18:07.369919 Set Vref, RX VrefLevel [Byte0]: 26
7561 13:18:07.373144 [Byte1]: 26
7562 13:18:07.378124
7563 13:18:07.378198 Set Vref, RX VrefLevel [Byte0]: 27
7564 13:18:07.380455 [Byte1]: 27
7565 13:18:07.384727
7566 13:18:07.384803 Set Vref, RX VrefLevel [Byte0]: 28
7567 13:18:07.387866 [Byte1]: 28
7568 13:18:07.392424
7569 13:18:07.392501 Set Vref, RX VrefLevel [Byte0]: 29
7570 13:18:07.395412 [Byte1]: 29
7571 13:18:07.400392
7572 13:18:07.400469 Set Vref, RX VrefLevel [Byte0]: 30
7573 13:18:07.403307 [Byte1]: 30
7574 13:18:07.407423
7575 13:18:07.407499 Set Vref, RX VrefLevel [Byte0]: 31
7576 13:18:07.411360 [Byte1]: 31
7577 13:18:07.415203
7578 13:18:07.415279 Set Vref, RX VrefLevel [Byte0]: 32
7579 13:18:07.419029 [Byte1]: 32
7580 13:18:07.422875
7581 13:18:07.422952 Set Vref, RX VrefLevel [Byte0]: 33
7582 13:18:07.426675 [Byte1]: 33
7583 13:18:07.430897
7584 13:18:07.430973 Set Vref, RX VrefLevel [Byte0]: 34
7585 13:18:07.434273 [Byte1]: 34
7586 13:18:07.438370
7587 13:18:07.438447 Set Vref, RX VrefLevel [Byte0]: 35
7588 13:18:07.441840 [Byte1]: 35
7589 13:18:07.446085
7590 13:18:07.446161 Set Vref, RX VrefLevel [Byte0]: 36
7591 13:18:07.448923 [Byte1]: 36
7592 13:18:07.453168
7593 13:18:07.453277 Set Vref, RX VrefLevel [Byte0]: 37
7594 13:18:07.457026 [Byte1]: 37
7595 13:18:07.460983
7596 13:18:07.461059 Set Vref, RX VrefLevel [Byte0]: 38
7597 13:18:07.465074 [Byte1]: 38
7598 13:18:07.468631
7599 13:18:07.468707 Set Vref, RX VrefLevel [Byte0]: 39
7600 13:18:07.472026 [Byte1]: 39
7601 13:18:07.475974
7602 13:18:07.476050 Set Vref, RX VrefLevel [Byte0]: 40
7603 13:18:07.480065 [Byte1]: 40
7604 13:18:07.483990
7605 13:18:07.484067 Set Vref, RX VrefLevel [Byte0]: 41
7606 13:18:07.487137 [Byte1]: 41
7607 13:18:07.491187
7608 13:18:07.491264 Set Vref, RX VrefLevel [Byte0]: 42
7609 13:18:07.495088 [Byte1]: 42
7610 13:18:07.499101
7611 13:18:07.499176 Set Vref, RX VrefLevel [Byte0]: 43
7612 13:18:07.502125 [Byte1]: 43
7613 13:18:07.506286
7614 13:18:07.506374 Set Vref, RX VrefLevel [Byte0]: 44
7615 13:18:07.509739 [Byte1]: 44
7616 13:18:07.514048
7617 13:18:07.514116 Set Vref, RX VrefLevel [Byte0]: 45
7618 13:18:07.517695 [Byte1]: 45
7619 13:18:07.521659
7620 13:18:07.521751 Set Vref, RX VrefLevel [Byte0]: 46
7621 13:18:07.525149 [Byte1]: 46
7622 13:18:07.530001
7623 13:18:07.530065 Set Vref, RX VrefLevel [Byte0]: 47
7624 13:18:07.532574 [Byte1]: 47
7625 13:18:07.537101
7626 13:18:07.537206 Set Vref, RX VrefLevel [Byte0]: 48
7627 13:18:07.540523 [Byte1]: 48
7628 13:18:07.544770
7629 13:18:07.544867 Set Vref, RX VrefLevel [Byte0]: 49
7630 13:18:07.548629 [Byte1]: 49
7631 13:18:07.552423
7632 13:18:07.552492 Set Vref, RX VrefLevel [Byte0]: 50
7633 13:18:07.555342 [Byte1]: 50
7634 13:18:07.560031
7635 13:18:07.560102 Set Vref, RX VrefLevel [Byte0]: 51
7636 13:18:07.563623 [Byte1]: 51
7637 13:18:07.568297
7638 13:18:07.568363 Set Vref, RX VrefLevel [Byte0]: 52
7639 13:18:07.570899 [Byte1]: 52
7640 13:18:07.575378
7641 13:18:07.575466 Set Vref, RX VrefLevel [Byte0]: 53
7642 13:18:07.578312 [Byte1]: 53
7643 13:18:07.582570
7644 13:18:07.582664 Set Vref, RX VrefLevel [Byte0]: 54
7645 13:18:07.585871 [Byte1]: 54
7646 13:18:07.590283
7647 13:18:07.590364 Set Vref, RX VrefLevel [Byte0]: 55
7648 13:18:07.594664 [Byte1]: 55
7649 13:18:07.598043
7650 13:18:07.598117 Set Vref, RX VrefLevel [Byte0]: 56
7651 13:18:07.601195 [Byte1]: 56
7652 13:18:07.605631
7653 13:18:07.605706 Set Vref, RX VrefLevel [Byte0]: 57
7654 13:18:07.609250 [Byte1]: 57
7655 13:18:07.613173
7656 13:18:07.613286 Set Vref, RX VrefLevel [Byte0]: 58
7657 13:18:07.616641 [Byte1]: 58
7658 13:18:07.620519
7659 13:18:07.620594 Set Vref, RX VrefLevel [Byte0]: 59
7660 13:18:07.624036 [Byte1]: 59
7661 13:18:07.628215
7662 13:18:07.628319 Set Vref, RX VrefLevel [Byte0]: 60
7663 13:18:07.631753 [Byte1]: 60
7664 13:18:07.636127
7665 13:18:07.636200 Set Vref, RX VrefLevel [Byte0]: 61
7666 13:18:07.639245 [Byte1]: 61
7667 13:18:07.643746
7668 13:18:07.643820 Set Vref, RX VrefLevel [Byte0]: 62
7669 13:18:07.646874 [Byte1]: 62
7670 13:18:07.651255
7671 13:18:07.651330 Set Vref, RX VrefLevel [Byte0]: 63
7672 13:18:07.654639 [Byte1]: 63
7673 13:18:07.658968
7674 13:18:07.659042 Set Vref, RX VrefLevel [Byte0]: 64
7675 13:18:07.662058 [Byte1]: 64
7676 13:18:07.666826
7677 13:18:07.666901 Set Vref, RX VrefLevel [Byte0]: 65
7678 13:18:07.670229 [Byte1]: 65
7679 13:18:07.674373
7680 13:18:07.674447 Set Vref, RX VrefLevel [Byte0]: 66
7681 13:18:07.677676 [Byte1]: 66
7682 13:18:07.681785
7683 13:18:07.681859 Set Vref, RX VrefLevel [Byte0]: 67
7684 13:18:07.684675 [Byte1]: 67
7685 13:18:07.689929
7686 13:18:07.690003 Set Vref, RX VrefLevel [Byte0]: 68
7687 13:18:07.692689 [Byte1]: 68
7688 13:18:07.697833
7689 13:18:07.697907 Set Vref, RX VrefLevel [Byte0]: 69
7690 13:18:07.700373 [Byte1]: 69
7691 13:18:07.704832
7692 13:18:07.704906 Set Vref, RX VrefLevel [Byte0]: 70
7693 13:18:07.707790 [Byte1]: 70
7694 13:18:07.712046
7695 13:18:07.712121 Final RX Vref Byte 0 = 52 to rank0
7696 13:18:07.715854 Final RX Vref Byte 1 = 56 to rank0
7697 13:18:07.719095 Final RX Vref Byte 0 = 52 to rank1
7698 13:18:07.721742 Final RX Vref Byte 1 = 56 to rank1==
7699 13:18:07.725158 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 13:18:07.731767 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7701 13:18:07.731843 ==
7702 13:18:07.731902 DQS Delay:
7703 13:18:07.735798 DQS0 = 0, DQS1 = 0
7704 13:18:07.735874 DQM Delay:
7705 13:18:07.735932 DQM0 = 126, DQM1 = 121
7706 13:18:07.738669 DQ Delay:
7707 13:18:07.741634 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7708 13:18:07.744939 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7709 13:18:07.748179 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7710 13:18:07.751486 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7711 13:18:07.751562
7712 13:18:07.751619
7713 13:18:07.751672
7714 13:18:07.755109 [DramC_TX_OE_Calibration] TA2
7715 13:18:07.758519 Original DQ_B0 (3 6) =30, OEN = 27
7716 13:18:07.761798 Original DQ_B1 (3 6) =30, OEN = 27
7717 13:18:07.764817 24, 0x0, End_B0=24 End_B1=24
7718 13:18:07.768717 25, 0x0, End_B0=25 End_B1=25
7719 13:18:07.768793 26, 0x0, End_B0=26 End_B1=26
7720 13:18:07.771548 27, 0x0, End_B0=27 End_B1=27
7721 13:18:07.774595 28, 0x0, End_B0=28 End_B1=28
7722 13:18:07.779022 29, 0x0, End_B0=29 End_B1=29
7723 13:18:07.779099 30, 0x0, End_B0=30 End_B1=30
7724 13:18:07.781289 31, 0x4141, End_B0=30 End_B1=30
7725 13:18:07.784853 Byte0 end_step=30 best_step=27
7726 13:18:07.787605 Byte1 end_step=30 best_step=27
7727 13:18:07.791768 Byte0 TX OE(2T, 0.5T) = (3, 3)
7728 13:18:07.795032 Byte1 TX OE(2T, 0.5T) = (3, 3)
7729 13:18:07.795110
7730 13:18:07.795170
7731 13:18:07.801549 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7732 13:18:07.804993 CH0 RK0: MR19=303, MR18=1D1D
7733 13:18:07.811383 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7734 13:18:07.811481
7735 13:18:07.814431 ----->DramcWriteLeveling(PI) begin...
7736 13:18:07.814529 ==
7737 13:18:07.817523 Dram Type= 6, Freq= 0, CH_0, rank 1
7738 13:18:07.820725 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7739 13:18:07.820838 ==
7740 13:18:07.824793 Write leveling (Byte 0): 30 => 30
7741 13:18:07.827481 Write leveling (Byte 1): 27 => 27
7742 13:18:07.830904 DramcWriteLeveling(PI) end<-----
7743 13:18:07.831043
7744 13:18:07.831151 ==
7745 13:18:07.834285 Dram Type= 6, Freq= 0, CH_0, rank 1
7746 13:18:07.838217 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7747 13:18:07.841090 ==
7748 13:18:07.841328 [Gating] SW mode calibration
7749 13:18:07.850882 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7750 13:18:07.854292 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7751 13:18:07.857519 0 12 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7752 13:18:07.863876 0 12 4 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7753 13:18:07.867092 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7754 13:18:07.870553 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7755 13:18:07.877301 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7756 13:18:07.881846 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7757 13:18:07.883800 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7758 13:18:07.890800 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7759 13:18:07.893668 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
7760 13:18:07.897095 0 13 4 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7761 13:18:07.903763 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7762 13:18:07.907582 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7763 13:18:07.910548 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7764 13:18:07.916779 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7765 13:18:07.920363 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7766 13:18:07.923605 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7767 13:18:07.930202 0 14 0 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
7768 13:18:07.933049 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7769 13:18:07.936560 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7770 13:18:07.943636 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7771 13:18:07.946431 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7772 13:18:07.950540 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7773 13:18:07.956867 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7774 13:18:07.959990 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7775 13:18:07.963172 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7776 13:18:07.969886 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7777 13:18:07.973245 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7778 13:18:07.976478 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7779 13:18:07.983162 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7780 13:18:07.986076 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7781 13:18:07.989288 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7782 13:18:07.996276 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7783 13:18:07.999196 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7784 13:18:08.002527 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7785 13:18:08.009126 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7786 13:18:08.012634 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7787 13:18:08.015586 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7788 13:18:08.022562 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7789 13:18:08.026048 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7790 13:18:08.029608 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7791 13:18:08.035649 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7792 13:18:08.039003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7793 13:18:08.042123 Total UI for P1: 0, mck2ui 16
7794 13:18:08.045816 best dqsien dly found for B0: ( 1, 0, 28)
7795 13:18:08.049082 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7796 13:18:08.052239 Total UI for P1: 0, mck2ui 16
7797 13:18:08.055839 best dqsien dly found for B1: ( 1, 1, 2)
7798 13:18:08.059068 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7799 13:18:08.062130 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7800 13:18:08.062207
7801 13:18:08.065860 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7802 13:18:08.072125 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7803 13:18:08.072204 [Gating] SW calibration Done
7804 13:18:08.072282 ==
7805 13:18:08.075572 Dram Type= 6, Freq= 0, CH_0, rank 1
7806 13:18:08.081850 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7807 13:18:08.081928 ==
7808 13:18:08.082005 RX Vref Scan: 0
7809 13:18:08.082077
7810 13:18:08.085338 RX Vref 0 -> 0, step: 1
7811 13:18:08.085426
7812 13:18:08.088553 RX Delay 0 -> 252, step: 8
7813 13:18:08.092388 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7814 13:18:08.095208 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7815 13:18:08.098534 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7816 13:18:08.101961 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7817 13:18:08.108691 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7818 13:18:08.112267 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7819 13:18:08.115505 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7820 13:18:08.118340 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7821 13:18:08.124875 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7822 13:18:08.128173 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7823 13:18:08.131549 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7824 13:18:08.134983 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7825 13:18:08.138068 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7826 13:18:08.145013 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7827 13:18:08.148365 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7828 13:18:08.151339 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7829 13:18:08.151416 ==
7830 13:18:08.155380 Dram Type= 6, Freq= 0, CH_0, rank 1
7831 13:18:08.158544 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7832 13:18:08.158622 ==
7833 13:18:08.161175 DQS Delay:
7834 13:18:08.161261 DQS0 = 0, DQS1 = 0
7835 13:18:08.165005 DQM Delay:
7836 13:18:08.165095 DQM0 = 130, DQM1 = 124
7837 13:18:08.168037 DQ Delay:
7838 13:18:08.171191 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7839 13:18:08.174561 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7840 13:18:08.178312 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7841 13:18:08.181179 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7842 13:18:08.181315
7843 13:18:08.181392
7844 13:18:08.181464 ==
7845 13:18:08.184450 Dram Type= 6, Freq= 0, CH_0, rank 1
7846 13:18:08.187868 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7847 13:18:08.187935 ==
7848 13:18:08.188005
7849 13:18:08.188072
7850 13:18:08.191735 TX Vref Scan disable
7851 13:18:08.194360 == TX Byte 0 ==
7852 13:18:08.198057 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7853 13:18:08.201151 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7854 13:18:08.204812 == TX Byte 1 ==
7855 13:18:08.208060 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7856 13:18:08.211945 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7857 13:18:08.212022 ==
7858 13:18:08.214102 Dram Type= 6, Freq= 0, CH_0, rank 1
7859 13:18:08.220650 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7860 13:18:08.220728 ==
7861 13:18:08.233584
7862 13:18:08.237338 TX Vref early break, caculate TX vref
7863 13:18:08.241155 TX Vref=16, minBit 1, minWin=22, winSum=376
7864 13:18:08.243607 TX Vref=18, minBit 9, minWin=22, winSum=388
7865 13:18:08.247099 TX Vref=20, minBit 1, minWin=23, winSum=392
7866 13:18:08.250166 TX Vref=22, minBit 11, minWin=23, winSum=399
7867 13:18:08.253579 TX Vref=24, minBit 9, minWin=24, winSum=411
7868 13:18:08.259920 TX Vref=26, minBit 8, minWin=24, winSum=412
7869 13:18:08.264378 TX Vref=28, minBit 0, minWin=25, winSum=414
7870 13:18:08.266593 TX Vref=30, minBit 1, minWin=24, winSum=413
7871 13:18:08.270488 TX Vref=32, minBit 8, minWin=23, winSum=400
7872 13:18:08.273238 TX Vref=34, minBit 8, minWin=22, winSum=393
7873 13:18:08.276560 TX Vref=36, minBit 8, minWin=23, winSum=390
7874 13:18:08.284168 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
7875 13:18:08.284244
7876 13:18:08.286841 Final TX Range 0 Vref 28
7877 13:18:08.286915
7878 13:18:08.286971 ==
7879 13:18:08.290081 Dram Type= 6, Freq= 0, CH_0, rank 1
7880 13:18:08.292979 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7881 13:18:08.293053 ==
7882 13:18:08.297404
7883 13:18:08.297478
7884 13:18:08.297535 TX Vref Scan disable
7885 13:18:08.303391 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7886 13:18:08.303467 == TX Byte 0 ==
7887 13:18:08.307258 u2DelayCellOfst[0]=10 cells (3 PI)
7888 13:18:08.309700 u2DelayCellOfst[1]=14 cells (4 PI)
7889 13:18:08.313080 u2DelayCellOfst[2]=10 cells (3 PI)
7890 13:18:08.316478 u2DelayCellOfst[3]=10 cells (3 PI)
7891 13:18:08.320287 u2DelayCellOfst[4]=7 cells (2 PI)
7892 13:18:08.323413 u2DelayCellOfst[5]=0 cells (0 PI)
7893 13:18:08.326734 u2DelayCellOfst[6]=14 cells (4 PI)
7894 13:18:08.329531 u2DelayCellOfst[7]=14 cells (4 PI)
7895 13:18:08.332906 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7896 13:18:08.336833 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7897 13:18:08.339467 == TX Byte 1 ==
7898 13:18:08.343551 u2DelayCellOfst[8]=3 cells (1 PI)
7899 13:18:08.346275 u2DelayCellOfst[9]=0 cells (0 PI)
7900 13:18:08.349280 u2DelayCellOfst[10]=7 cells (2 PI)
7901 13:18:08.353334 u2DelayCellOfst[11]=3 cells (1 PI)
7902 13:18:08.353408 u2DelayCellOfst[12]=14 cells (4 PI)
7903 13:18:08.356026 u2DelayCellOfst[13]=14 cells (4 PI)
7904 13:18:08.359410 u2DelayCellOfst[14]=18 cells (5 PI)
7905 13:18:08.362893 u2DelayCellOfst[15]=14 cells (4 PI)
7906 13:18:08.369261 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7907 13:18:08.372737 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7908 13:18:08.372802 DramC Write-DBI on
7909 13:18:08.376757 ==
7910 13:18:08.376819 Dram Type= 6, Freq= 0, CH_0, rank 1
7911 13:18:08.382298 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7912 13:18:08.382385 ==
7913 13:18:08.382465
7914 13:18:08.382545
7915 13:18:08.386581 TX Vref Scan disable
7916 13:18:08.386639 == TX Byte 0 ==
7917 13:18:08.392439 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7918 13:18:08.392500 == TX Byte 1 ==
7919 13:18:08.396140 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7920 13:18:08.398878 DramC Write-DBI off
7921 13:18:08.398936
7922 13:18:08.398986 [DATLAT]
7923 13:18:08.402394 Freq=1600, CH0 RK1
7924 13:18:08.402457
7925 13:18:08.402506 DATLAT Default: 0xe
7926 13:18:08.405622 0, 0xFFFF, sum = 0
7927 13:18:08.405702 1, 0xFFFF, sum = 0
7928 13:18:08.408930 2, 0xFFFF, sum = 0
7929 13:18:08.408996 3, 0xFFFF, sum = 0
7930 13:18:08.412309 4, 0xFFFF, sum = 0
7931 13:18:08.412409 5, 0xFFFF, sum = 0
7932 13:18:08.415712 6, 0xFFFF, sum = 0
7933 13:18:08.418855 7, 0xFFFF, sum = 0
7934 13:18:08.418930 8, 0xFFFF, sum = 0
7935 13:18:08.422661 9, 0xFFFF, sum = 0
7936 13:18:08.422736 10, 0xFFFF, sum = 0
7937 13:18:08.425656 11, 0xFFFF, sum = 0
7938 13:18:08.425731 12, 0x8FFF, sum = 0
7939 13:18:08.428936 13, 0x0, sum = 1
7940 13:18:08.429011 14, 0x0, sum = 2
7941 13:18:08.431885 15, 0x0, sum = 3
7942 13:18:08.431951 16, 0x0, sum = 4
7943 13:18:08.432007 best_step = 14
7944 13:18:08.435749
7945 13:18:08.435822 ==
7946 13:18:08.439253 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 13:18:08.443322 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7948 13:18:08.443436 ==
7949 13:18:08.443520 RX Vref Scan: 0
7950 13:18:08.443617
7951 13:18:08.445468 RX Vref 0 -> 0, step: 1
7952 13:18:08.445542
7953 13:18:08.448366 RX Delay 11 -> 252, step: 4
7954 13:18:08.451971 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7955 13:18:08.458615 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7956 13:18:08.462133 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7957 13:18:08.465059 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7958 13:18:08.469035 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7959 13:18:08.471669 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7960 13:18:08.478445 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7961 13:18:08.481711 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7962 13:18:08.485156 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7963 13:18:08.488309 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7964 13:18:08.492370 iDelay=195, Bit 10, Center 120 (67 ~ 174) 108
7965 13:18:08.498476 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7966 13:18:08.501766 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7967 13:18:08.504946 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7968 13:18:08.508338 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7969 13:18:08.514587 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7970 13:18:08.514661 ==
7971 13:18:08.517959 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 13:18:08.521648 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7973 13:18:08.521723 ==
7974 13:18:08.521780 DQS Delay:
7975 13:18:08.524365 DQS0 = 0, DQS1 = 0
7976 13:18:08.524438 DQM Delay:
7977 13:18:08.527793 DQM0 = 129, DQM1 = 120
7978 13:18:08.527867 DQ Delay:
7979 13:18:08.531194 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7980 13:18:08.534347 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7981 13:18:08.537906 DQ8 =108, DQ9 =106, DQ10 =120, DQ11 =112
7982 13:18:08.541405 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7983 13:18:08.541481
7984 13:18:08.541562
7985 13:18:08.541636
7986 13:18:08.544392 [DramC_TX_OE_Calibration] TA2
7987 13:18:08.548423 Original DQ_B0 (3 6) =30, OEN = 27
7988 13:18:08.551729 Original DQ_B1 (3 6) =30, OEN = 27
7989 13:18:08.554286 24, 0x0, End_B0=24 End_B1=24
7990 13:18:08.557827 25, 0x0, End_B0=25 End_B1=25
7991 13:18:08.557930 26, 0x0, End_B0=26 End_B1=26
7992 13:18:08.561327 27, 0x0, End_B0=27 End_B1=27
7993 13:18:08.565506 28, 0x0, End_B0=28 End_B1=28
7994 13:18:08.568255 29, 0x0, End_B0=29 End_B1=29
7995 13:18:08.571030 30, 0x0, End_B0=30 End_B1=30
7996 13:18:08.571105 31, 0x4141, End_B0=30 End_B1=30
7997 13:18:08.574160 Byte0 end_step=30 best_step=27
7998 13:18:08.577563 Byte1 end_step=30 best_step=27
7999 13:18:08.580953 Byte0 TX OE(2T, 0.5T) = (3, 3)
8000 13:18:08.583874 Byte1 TX OE(2T, 0.5T) = (3, 3)
8001 13:18:08.583974
8002 13:18:08.584057
8003 13:18:08.591106 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8004 13:18:08.594667 CH0 RK1: MR19=303, MR18=2323
8005 13:18:08.600539 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8006 13:18:08.603725 [RxdqsGatingPostProcess] freq 1600
8007 13:18:08.610780 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8008 13:18:08.613963 Pre-setting of DQS Precalculation
8009 13:18:08.616867 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8010 13:18:08.616942 ==
8011 13:18:08.621061 Dram Type= 6, Freq= 0, CH_1, rank 0
8012 13:18:08.623620 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8013 13:18:08.627100 ==
8014 13:18:08.630281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8015 13:18:08.633578 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8016 13:18:08.639933 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8017 13:18:08.643538 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8018 13:18:08.652776 [CA 0] Center 41 (11~71) winsize 61
8019 13:18:08.656550 [CA 1] Center 41 (11~72) winsize 62
8020 13:18:08.659912 [CA 2] Center 37 (7~67) winsize 61
8021 13:18:08.662851 [CA 3] Center 36 (6~66) winsize 61
8022 13:18:08.666179 [CA 4] Center 34 (5~64) winsize 60
8023 13:18:08.670273 [CA 5] Center 34 (5~64) winsize 60
8024 13:18:08.670349
8025 13:18:08.673639 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8026 13:18:08.673713
8027 13:18:08.676377 [CATrainingPosCal] consider 1 rank data
8028 13:18:08.679789 u2DelayCellTimex100 = 271/100 ps
8029 13:18:08.682950 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8030 13:18:08.689639 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8031 13:18:08.693174 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8032 13:18:08.696698 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
8033 13:18:08.699669 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8034 13:18:08.703147 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8035 13:18:08.703222
8036 13:18:08.706552 CA PerBit enable=1, Macro0, CA PI delay=34
8037 13:18:08.706628
8038 13:18:08.709458 [CBTSetCACLKResult] CA Dly = 34
8039 13:18:08.712687 CS Dly: 8 (0~39)
8040 13:18:08.716031 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8041 13:18:08.720057 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8042 13:18:08.720155 ==
8043 13:18:08.723256 Dram Type= 6, Freq= 0, CH_1, rank 1
8044 13:18:08.726695 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8045 13:18:08.729484 ==
8046 13:18:08.733069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8047 13:18:08.736088 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8048 13:18:08.742636 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8049 13:18:08.745780 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8050 13:18:08.755553 [CA 0] Center 40 (10~70) winsize 61
8051 13:18:08.759078 [CA 1] Center 39 (9~70) winsize 62
8052 13:18:08.761981 [CA 2] Center 35 (6~65) winsize 60
8053 13:18:08.765505 [CA 3] Center 35 (6~65) winsize 60
8054 13:18:08.768721 [CA 4] Center 33 (4~62) winsize 59
8055 13:18:08.772999 [CA 5] Center 32 (3~62) winsize 60
8056 13:18:08.773067
8057 13:18:08.775539 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8058 13:18:08.775599
8059 13:18:08.778608 [CATrainingPosCal] consider 2 rank data
8060 13:18:08.781847 u2DelayCellTimex100 = 271/100 ps
8061 13:18:08.785219 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8062 13:18:08.791759 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8063 13:18:08.795398 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8064 13:18:08.798643 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8065 13:18:08.802363 CA4 delay=33 (5~62),Diff = 0 PI (0 cell)
8066 13:18:08.805199 CA5 delay=33 (5~62),Diff = 0 PI (0 cell)
8067 13:18:08.805309
8068 13:18:08.809092 CA PerBit enable=1, Macro0, CA PI delay=33
8069 13:18:08.809162
8070 13:18:08.811755 [CBTSetCACLKResult] CA Dly = 33
8071 13:18:08.815227 CS Dly: 9 (0~41)
8072 13:18:08.818308 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8073 13:18:08.821646 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8074 13:18:08.821710
8075 13:18:08.824633 ----->DramcWriteLeveling(PI) begin...
8076 13:18:08.824696 ==
8077 13:18:08.828029 Dram Type= 6, Freq= 0, CH_1, rank 0
8078 13:18:08.835127 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8079 13:18:08.835202 ==
8080 13:18:08.838196 Write leveling (Byte 0): 21 => 21
8081 13:18:08.838269 Write leveling (Byte 1): 23 => 23
8082 13:18:08.841951 DramcWriteLeveling(PI) end<-----
8083 13:18:08.842020
8084 13:18:08.844677 ==
8085 13:18:08.844738 Dram Type= 6, Freq= 0, CH_1, rank 0
8086 13:18:08.851503 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8087 13:18:08.851570 ==
8088 13:18:08.854487 [Gating] SW mode calibration
8089 13:18:08.861243 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8090 13:18:08.864665 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8091 13:18:08.871716 0 12 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8092 13:18:08.875410 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8093 13:18:08.878664 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8094 13:18:08.884348 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8095 13:18:08.888871 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8096 13:18:08.891441 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8097 13:18:08.898446 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8098 13:18:08.901521 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8099 13:18:08.904881 0 13 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8100 13:18:08.911029 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 13:18:08.914199 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 13:18:08.918370 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 13:18:08.924248 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 13:18:08.927563 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8105 13:18:08.931347 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8106 13:18:08.937473 0 13 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8107 13:18:08.941336 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8108 13:18:08.944705 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 13:18:08.951194 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 13:18:08.954089 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 13:18:08.957238 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 13:18:08.960864 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 13:18:08.967353 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8114 13:18:08.970940 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8115 13:18:08.977177 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8116 13:18:08.980965 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8117 13:18:08.983486 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 13:18:08.991367 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 13:18:08.993687 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 13:18:08.996856 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 13:18:09.001079 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 13:18:09.006888 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 13:18:09.010854 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 13:18:09.013701 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 13:18:09.020267 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 13:18:09.024237 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 13:18:09.026530 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 13:18:09.033491 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 13:18:09.036705 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8130 13:18:09.040149 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8131 13:18:09.043791 Total UI for P1: 0, mck2ui 16
8132 13:18:09.047187 best dqsien dly found for B0: ( 1, 0, 24)
8133 13:18:09.052850 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8134 13:18:09.056633 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8135 13:18:09.060092 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 13:18:09.063492 Total UI for P1: 0, mck2ui 16
8137 13:18:09.066332 best dqsien dly found for B1: ( 1, 1, 0)
8138 13:18:09.069644 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8139 13:18:09.072965 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8140 13:18:09.076199
8141 13:18:09.079285 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8142 13:18:09.082889 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8143 13:18:09.086253 [Gating] SW calibration Done
8144 13:18:09.086350 ==
8145 13:18:09.089382 Dram Type= 6, Freq= 0, CH_1, rank 0
8146 13:18:09.093261 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8147 13:18:09.093336 ==
8148 13:18:09.093394 RX Vref Scan: 0
8149 13:18:09.093448
8150 13:18:09.095976 RX Vref 0 -> 0, step: 1
8151 13:18:09.096050
8152 13:18:09.100699 RX Delay 0 -> 252, step: 8
8153 13:18:09.102849 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8154 13:18:09.106567 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8155 13:18:09.112717 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8156 13:18:09.116525 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8157 13:18:09.119022 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8158 13:18:09.123171 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8159 13:18:09.125691 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8160 13:18:09.132646 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8161 13:18:09.135827 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8162 13:18:09.139166 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8163 13:18:09.142415 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8164 13:18:09.145793 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8165 13:18:09.152054 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8166 13:18:09.155492 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8167 13:18:09.159408 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8168 13:18:09.162080 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8169 13:18:09.162158 ==
8170 13:18:09.165269 Dram Type= 6, Freq= 0, CH_1, rank 0
8171 13:18:09.172884 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8172 13:18:09.172968 ==
8173 13:18:09.173049 DQS Delay:
8174 13:18:09.175472 DQS0 = 0, DQS1 = 0
8175 13:18:09.175549 DQM Delay:
8176 13:18:09.178537 DQM0 = 129, DQM1 = 126
8177 13:18:09.178654 DQ Delay:
8178 13:18:09.182260 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8179 13:18:09.185148 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8180 13:18:09.188679 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8181 13:18:09.192137 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8182 13:18:09.192214
8183 13:18:09.192290
8184 13:18:09.192361 ==
8185 13:18:09.195165 Dram Type= 6, Freq= 0, CH_1, rank 0
8186 13:18:09.202156 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8187 13:18:09.202262 ==
8188 13:18:09.202353
8189 13:18:09.202443
8190 13:18:09.202535 TX Vref Scan disable
8191 13:18:09.205399 == TX Byte 0 ==
8192 13:18:09.208589 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8193 13:18:09.216257 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8194 13:18:09.216339 == TX Byte 1 ==
8195 13:18:09.219101 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8196 13:18:09.224977 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8197 13:18:09.225057 ==
8198 13:18:09.229137 Dram Type= 6, Freq= 0, CH_1, rank 0
8199 13:18:09.231417 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8200 13:18:09.231494 ==
8201 13:18:09.244376
8202 13:18:09.247905 TX Vref early break, caculate TX vref
8203 13:18:09.250597 TX Vref=16, minBit 3, minWin=21, winSum=363
8204 13:18:09.253992 TX Vref=18, minBit 1, minWin=22, winSum=374
8205 13:18:09.256766 TX Vref=20, minBit 0, minWin=23, winSum=385
8206 13:18:09.260363 TX Vref=22, minBit 1, minWin=23, winSum=392
8207 13:18:09.263844 TX Vref=24, minBit 3, minWin=23, winSum=397
8208 13:18:09.270637 TX Vref=26, minBit 3, minWin=24, winSum=413
8209 13:18:09.273617 TX Vref=28, minBit 3, minWin=24, winSum=410
8210 13:18:09.277125 TX Vref=30, minBit 3, minWin=24, winSum=406
8211 13:18:09.279879 TX Vref=32, minBit 3, minWin=23, winSum=393
8212 13:18:09.283236 TX Vref=34, minBit 1, minWin=23, winSum=388
8213 13:18:09.291215 [TxChooseVref] Worse bit 3, Min win 24, Win sum 413, Final Vref 26
8214 13:18:09.291336
8215 13:18:09.293506 Final TX Range 0 Vref 26
8216 13:18:09.293581
8217 13:18:09.293638 ==
8218 13:18:09.296692 Dram Type= 6, Freq= 0, CH_1, rank 0
8219 13:18:09.300395 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8220 13:18:09.300474 ==
8221 13:18:09.300532
8222 13:18:09.300585
8223 13:18:09.303522 TX Vref Scan disable
8224 13:18:09.310139 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8225 13:18:09.310231 == TX Byte 0 ==
8226 13:18:09.313425 u2DelayCellOfst[0]=18 cells (5 PI)
8227 13:18:09.317078 u2DelayCellOfst[1]=10 cells (3 PI)
8228 13:18:09.321142 u2DelayCellOfst[2]=0 cells (0 PI)
8229 13:18:09.323186 u2DelayCellOfst[3]=7 cells (2 PI)
8230 13:18:09.326775 u2DelayCellOfst[4]=10 cells (3 PI)
8231 13:18:09.330519 u2DelayCellOfst[5]=18 cells (5 PI)
8232 13:18:09.333554 u2DelayCellOfst[6]=18 cells (5 PI)
8233 13:18:09.333633 u2DelayCellOfst[7]=7 cells (2 PI)
8234 13:18:09.340099 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8235 13:18:09.343295 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8236 13:18:09.343365 == TX Byte 1 ==
8237 13:18:09.346862 u2DelayCellOfst[8]=0 cells (0 PI)
8238 13:18:09.350026 u2DelayCellOfst[9]=3 cells (1 PI)
8239 13:18:09.353585 u2DelayCellOfst[10]=10 cells (3 PI)
8240 13:18:09.356701 u2DelayCellOfst[11]=3 cells (1 PI)
8241 13:18:09.360079 u2DelayCellOfst[12]=18 cells (5 PI)
8242 13:18:09.363368 u2DelayCellOfst[13]=21 cells (6 PI)
8243 13:18:09.366726 u2DelayCellOfst[14]=21 cells (6 PI)
8244 13:18:09.370428 u2DelayCellOfst[15]=18 cells (5 PI)
8245 13:18:09.373878 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8246 13:18:09.379475 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8247 13:18:09.379554 DramC Write-DBI on
8248 13:18:09.379612 ==
8249 13:18:09.383433 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 13:18:09.386273 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8251 13:18:09.389994 ==
8252 13:18:09.390098
8253 13:18:09.390180
8254 13:18:09.390257 TX Vref Scan disable
8255 13:18:09.392854 == TX Byte 0 ==
8256 13:18:09.396498 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8257 13:18:09.399456 == TX Byte 1 ==
8258 13:18:09.402614 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8259 13:18:09.406359 DramC Write-DBI off
8260 13:18:09.406437
8261 13:18:09.406495 [DATLAT]
8262 13:18:09.406550 Freq=1600, CH1 RK0
8263 13:18:09.406601
8264 13:18:09.409994 DATLAT Default: 0xf
8265 13:18:09.410070 0, 0xFFFF, sum = 0
8266 13:18:09.412828 1, 0xFFFF, sum = 0
8267 13:18:09.416486 2, 0xFFFF, sum = 0
8268 13:18:09.416588 3, 0xFFFF, sum = 0
8269 13:18:09.419794 4, 0xFFFF, sum = 0
8270 13:18:09.419871 5, 0xFFFF, sum = 0
8271 13:18:09.423181 6, 0xFFFF, sum = 0
8272 13:18:09.423257 7, 0xFFFF, sum = 0
8273 13:18:09.426169 8, 0xFFFF, sum = 0
8274 13:18:09.426245 9, 0xFFFF, sum = 0
8275 13:18:09.429486 10, 0xFFFF, sum = 0
8276 13:18:09.429563 11, 0xFFFF, sum = 0
8277 13:18:09.433239 12, 0x8FFF, sum = 0
8278 13:18:09.433345 13, 0x0, sum = 1
8279 13:18:09.436292 14, 0x0, sum = 2
8280 13:18:09.436369 15, 0x0, sum = 3
8281 13:18:09.439389 16, 0x0, sum = 4
8282 13:18:09.439465 best_step = 14
8283 13:18:09.439551
8284 13:18:09.439605 ==
8285 13:18:09.442631 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 13:18:09.446563 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8287 13:18:09.449747 ==
8288 13:18:09.449847 RX Vref Scan: 1
8289 13:18:09.449928
8290 13:18:09.452846 Set Vref Range= 24 -> 127
8291 13:18:09.452922
8292 13:18:09.456451 RX Vref 24 -> 127, step: 1
8293 13:18:09.456549
8294 13:18:09.456634 RX Delay 3 -> 252, step: 4
8295 13:18:09.456699
8296 13:18:09.459125 Set Vref, RX VrefLevel [Byte0]: 24
8297 13:18:09.462213 [Byte1]: 24
8298 13:18:09.466352
8299 13:18:09.466426 Set Vref, RX VrefLevel [Byte0]: 25
8300 13:18:09.469518 [Byte1]: 25
8301 13:18:09.474149
8302 13:18:09.474227 Set Vref, RX VrefLevel [Byte0]: 26
8303 13:18:09.477340 [Byte1]: 26
8304 13:18:09.482114
8305 13:18:09.482218 Set Vref, RX VrefLevel [Byte0]: 27
8306 13:18:09.485031 [Byte1]: 27
8307 13:18:09.489417
8308 13:18:09.489492 Set Vref, RX VrefLevel [Byte0]: 28
8309 13:18:09.493322 [Byte1]: 28
8310 13:18:09.497016
8311 13:18:09.497118 Set Vref, RX VrefLevel [Byte0]: 29
8312 13:18:09.500061 [Byte1]: 29
8313 13:18:09.504535
8314 13:18:09.504615 Set Vref, RX VrefLevel [Byte0]: 30
8315 13:18:09.507947 [Byte1]: 30
8316 13:18:09.512040
8317 13:18:09.512111 Set Vref, RX VrefLevel [Byte0]: 31
8318 13:18:09.515521 [Byte1]: 31
8319 13:18:09.520056
8320 13:18:09.520124 Set Vref, RX VrefLevel [Byte0]: 32
8321 13:18:09.523554 [Byte1]: 32
8322 13:18:09.528139
8323 13:18:09.528212 Set Vref, RX VrefLevel [Byte0]: 33
8324 13:18:09.530762 [Byte1]: 33
8325 13:18:09.536361
8326 13:18:09.538925 Set Vref, RX VrefLevel [Byte0]: 34
8327 13:18:09.539017 [Byte1]: 34
8328 13:18:09.543146
8329 13:18:09.543219 Set Vref, RX VrefLevel [Byte0]: 35
8330 13:18:09.546142 [Byte1]: 35
8331 13:18:09.550781
8332 13:18:09.550853 Set Vref, RX VrefLevel [Byte0]: 36
8333 13:18:09.554364 [Byte1]: 36
8334 13:18:09.558308
8335 13:18:09.558388 Set Vref, RX VrefLevel [Byte0]: 37
8336 13:18:09.561490 [Byte1]: 37
8337 13:18:09.565779
8338 13:18:09.565855 Set Vref, RX VrefLevel [Byte0]: 38
8339 13:18:09.569324 [Byte1]: 38
8340 13:18:09.573571
8341 13:18:09.573662 Set Vref, RX VrefLevel [Byte0]: 39
8342 13:18:09.576900 [Byte1]: 39
8343 13:18:09.581108
8344 13:18:09.581183 Set Vref, RX VrefLevel [Byte0]: 40
8345 13:18:09.584489 [Byte1]: 40
8346 13:18:09.588615
8347 13:18:09.588691 Set Vref, RX VrefLevel [Byte0]: 41
8348 13:18:09.592339 [Byte1]: 41
8349 13:18:09.596352
8350 13:18:09.596427 Set Vref, RX VrefLevel [Byte0]: 42
8351 13:18:09.599724 [Byte1]: 42
8352 13:18:09.604264
8353 13:18:09.604371 Set Vref, RX VrefLevel [Byte0]: 43
8354 13:18:09.607363 [Byte1]: 43
8355 13:18:09.612079
8356 13:18:09.612162 Set Vref, RX VrefLevel [Byte0]: 44
8357 13:18:09.614972 [Byte1]: 44
8358 13:18:09.619742
8359 13:18:09.619817 Set Vref, RX VrefLevel [Byte0]: 45
8360 13:18:09.622366 [Byte1]: 45
8361 13:18:09.627206
8362 13:18:09.627281 Set Vref, RX VrefLevel [Byte0]: 46
8363 13:18:09.630554 [Byte1]: 46
8364 13:18:09.634676
8365 13:18:09.634752 Set Vref, RX VrefLevel [Byte0]: 47
8366 13:18:09.637894 [Byte1]: 47
8367 13:18:09.642784
8368 13:18:09.642871 Set Vref, RX VrefLevel [Byte0]: 48
8369 13:18:09.645291 [Byte1]: 48
8370 13:18:09.650143
8371 13:18:09.650211 Set Vref, RX VrefLevel [Byte0]: 49
8372 13:18:09.653505 [Byte1]: 49
8373 13:18:09.657727
8374 13:18:09.657836 Set Vref, RX VrefLevel [Byte0]: 50
8375 13:18:09.660862 [Byte1]: 50
8376 13:18:09.665309
8377 13:18:09.665385 Set Vref, RX VrefLevel [Byte0]: 51
8378 13:18:09.668696 [Byte1]: 51
8379 13:18:09.673531
8380 13:18:09.673627 Set Vref, RX VrefLevel [Byte0]: 52
8381 13:18:09.676682 [Byte1]: 52
8382 13:18:09.680672
8383 13:18:09.680747 Set Vref, RX VrefLevel [Byte0]: 53
8384 13:18:09.684034 [Byte1]: 53
8385 13:18:09.688211
8386 13:18:09.688286 Set Vref, RX VrefLevel [Byte0]: 54
8387 13:18:09.691964 [Byte1]: 54
8388 13:18:09.695774
8389 13:18:09.695860 Set Vref, RX VrefLevel [Byte0]: 55
8390 13:18:09.699684 [Byte1]: 55
8391 13:18:09.703576
8392 13:18:09.703653 Set Vref, RX VrefLevel [Byte0]: 56
8393 13:18:09.707224 [Byte1]: 56
8394 13:18:09.711289
8395 13:18:09.711368 Set Vref, RX VrefLevel [Byte0]: 57
8396 13:18:09.715135 [Byte1]: 57
8397 13:18:09.718804
8398 13:18:09.718884 Set Vref, RX VrefLevel [Byte0]: 58
8399 13:18:09.722489 [Byte1]: 58
8400 13:18:09.726500
8401 13:18:09.726611 Set Vref, RX VrefLevel [Byte0]: 59
8402 13:18:09.729480 [Byte1]: 59
8403 13:18:09.733919
8404 13:18:09.733996 Set Vref, RX VrefLevel [Byte0]: 60
8405 13:18:09.737262 [Byte1]: 60
8406 13:18:09.742044
8407 13:18:09.742114 Set Vref, RX VrefLevel [Byte0]: 61
8408 13:18:09.745145 [Byte1]: 61
8409 13:18:09.750919
8410 13:18:09.751013 Set Vref, RX VrefLevel [Byte0]: 62
8411 13:18:09.752638 [Byte1]: 62
8412 13:18:09.757432
8413 13:18:09.757504 Set Vref, RX VrefLevel [Byte0]: 63
8414 13:18:09.760132 [Byte1]: 63
8415 13:18:09.764837
8416 13:18:09.764904 Set Vref, RX VrefLevel [Byte0]: 64
8417 13:18:09.768950 [Byte1]: 64
8418 13:18:09.772494
8419 13:18:09.772594 Set Vref, RX VrefLevel [Byte0]: 65
8420 13:18:09.777221 [Byte1]: 65
8421 13:18:09.780097
8422 13:18:09.780195 Set Vref, RX VrefLevel [Byte0]: 66
8423 13:18:09.783558 [Byte1]: 66
8424 13:18:09.787464
8425 13:18:09.787556 Set Vref, RX VrefLevel [Byte0]: 67
8426 13:18:09.791157 [Byte1]: 67
8427 13:18:09.795394
8428 13:18:09.795489 Set Vref, RX VrefLevel [Byte0]: 68
8429 13:18:09.798888 [Byte1]: 68
8430 13:18:09.803243
8431 13:18:09.803320 Set Vref, RX VrefLevel [Byte0]: 69
8432 13:18:09.807024 [Byte1]: 69
8433 13:18:09.810394
8434 13:18:09.810493 Set Vref, RX VrefLevel [Byte0]: 70
8435 13:18:09.813997 [Byte1]: 70
8436 13:18:09.818917
8437 13:18:09.819019 Set Vref, RX VrefLevel [Byte0]: 71
8438 13:18:09.822717 [Byte1]: 71
8439 13:18:09.825876
8440 13:18:09.825945 Set Vref, RX VrefLevel [Byte0]: 72
8441 13:18:09.828999 [Byte1]: 72
8442 13:18:09.833760
8443 13:18:09.833860 Set Vref, RX VrefLevel [Byte0]: 73
8444 13:18:09.837471 [Byte1]: 73
8445 13:18:09.840973
8446 13:18:09.841040 Set Vref, RX VrefLevel [Byte0]: 74
8447 13:18:09.844427 [Byte1]: 74
8448 13:18:09.849011
8449 13:18:09.849113 Set Vref, RX VrefLevel [Byte0]: 75
8450 13:18:09.852705 [Byte1]: 75
8451 13:18:09.856567
8452 13:18:09.856644 Final RX Vref Byte 0 = 59 to rank0
8453 13:18:09.859756 Final RX Vref Byte 1 = 53 to rank0
8454 13:18:09.863924 Final RX Vref Byte 0 = 59 to rank1
8455 13:18:09.866219 Final RX Vref Byte 1 = 53 to rank1==
8456 13:18:09.869775 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 13:18:09.876058 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8458 13:18:09.876142 ==
8459 13:18:09.876244 DQS Delay:
8460 13:18:09.879846 DQS0 = 0, DQS1 = 0
8461 13:18:09.879923 DQM Delay:
8462 13:18:09.879982 DQM0 = 128, DQM1 = 124
8463 13:18:09.882998 DQ Delay:
8464 13:18:09.887127 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8465 13:18:09.889405 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =124
8466 13:18:09.893326 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8467 13:18:09.896629 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8468 13:18:09.896704
8469 13:18:09.896762
8470 13:18:09.896815
8471 13:18:09.899580 [DramC_TX_OE_Calibration] TA2
8472 13:18:09.902772 Original DQ_B0 (3 6) =30, OEN = 27
8473 13:18:09.906265 Original DQ_B1 (3 6) =30, OEN = 27
8474 13:18:09.909463 24, 0x0, End_B0=24 End_B1=24
8475 13:18:09.909541 25, 0x0, End_B0=25 End_B1=25
8476 13:18:09.912672 26, 0x0, End_B0=26 End_B1=26
8477 13:18:09.915873 27, 0x0, End_B0=27 End_B1=27
8478 13:18:09.920130 28, 0x0, End_B0=28 End_B1=28
8479 13:18:09.922811 29, 0x0, End_B0=29 End_B1=29
8480 13:18:09.922905 30, 0x0, End_B0=30 End_B1=30
8481 13:18:09.926340 31, 0x5151, End_B0=30 End_B1=30
8482 13:18:09.929650 Byte0 end_step=30 best_step=27
8483 13:18:09.932865 Byte1 end_step=30 best_step=27
8484 13:18:09.936590 Byte0 TX OE(2T, 0.5T) = (3, 3)
8485 13:18:09.939298 Byte1 TX OE(2T, 0.5T) = (3, 3)
8486 13:18:09.939402
8487 13:18:09.939493
8488 13:18:09.946323 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8489 13:18:09.949496 CH1 RK0: MR19=303, MR18=2626
8490 13:18:09.956135 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8491 13:18:09.956247
8492 13:18:09.958967 ----->DramcWriteLeveling(PI) begin...
8493 13:18:09.959077 ==
8494 13:18:09.962448 Dram Type= 6, Freq= 0, CH_1, rank 1
8495 13:18:09.966129 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8496 13:18:09.966240 ==
8497 13:18:09.969105 Write leveling (Byte 0): 22 => 22
8498 13:18:09.972899 Write leveling (Byte 1): 22 => 22
8499 13:18:09.975703 DramcWriteLeveling(PI) end<-----
8500 13:18:09.975809
8501 13:18:09.975905 ==
8502 13:18:09.979512 Dram Type= 6, Freq= 0, CH_1, rank 1
8503 13:18:09.982851 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8504 13:18:09.982964 ==
8505 13:18:09.985782 [Gating] SW mode calibration
8506 13:18:09.992723 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8507 13:18:09.999233 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8508 13:18:10.002397 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8509 13:18:10.009628 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8510 13:18:10.012177 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8511 13:18:10.015500 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8512 13:18:10.022019 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8513 13:18:10.025175 0 12 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8514 13:18:10.029136 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8515 13:18:10.035232 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8516 13:18:10.038926 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
8517 13:18:10.041928 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8518 13:18:10.049126 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8519 13:18:10.051754 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8520 13:18:10.055732 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8521 13:18:10.058917 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8522 13:18:10.065722 0 13 24 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8523 13:18:10.068435 0 13 28 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
8524 13:18:10.071610 0 14 0 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
8525 13:18:10.078157 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8526 13:18:10.081944 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8527 13:18:10.085111 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8528 13:18:10.091932 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8529 13:18:10.094846 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8530 13:18:10.098690 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8531 13:18:10.105589 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8532 13:18:10.108332 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8533 13:18:10.112048 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8534 13:18:10.117942 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8535 13:18:10.121437 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8536 13:18:10.125013 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8537 13:18:10.131200 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8538 13:18:10.134594 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8539 13:18:10.138251 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8540 13:18:10.144562 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8541 13:18:10.147801 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8542 13:18:10.151528 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8543 13:18:10.157969 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8544 13:18:10.161527 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8545 13:18:10.164429 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8546 13:18:10.170927 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8547 13:18:10.171077 Total UI for P1: 0, mck2ui 16
8548 13:18:10.177631 best dqsien dly found for B0: ( 1, 0, 20)
8549 13:18:10.181687 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8550 13:18:10.184749 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8551 13:18:10.191115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8552 13:18:10.191267 Total UI for P1: 0, mck2ui 16
8553 13:18:10.198156 best dqsien dly found for B1: ( 1, 0, 30)
8554 13:18:10.201947 best DQS0 dly(MCK, UI, PI) = (1, 0, 20)
8555 13:18:10.204253 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8556 13:18:10.204335
8557 13:18:10.208211 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 20)
8558 13:18:10.210820 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8559 13:18:10.214460 [Gating] SW calibration Done
8560 13:18:10.214541 ==
8561 13:18:10.218176 Dram Type= 6, Freq= 0, CH_1, rank 1
8562 13:18:10.220925 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8563 13:18:10.221028 ==
8564 13:18:10.224725 RX Vref Scan: 0
8565 13:18:10.224803
8566 13:18:10.224862 RX Vref 0 -> 0, step: 1
8567 13:18:10.224917
8568 13:18:10.228131 RX Delay 0 -> 252, step: 8
8569 13:18:10.231069 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8570 13:18:10.234208 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8571 13:18:10.241176 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8572 13:18:10.244278 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8573 13:18:10.247807 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8574 13:18:10.250596 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8575 13:18:10.254053 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8576 13:18:10.260964 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8577 13:18:10.264411 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8578 13:18:10.267230 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8579 13:18:10.270573 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8580 13:18:10.277214 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8581 13:18:10.280715 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8582 13:18:10.283732 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8583 13:18:10.287445 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8584 13:18:10.291211 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8585 13:18:10.294516 ==
8586 13:18:10.294621 Dram Type= 6, Freq= 0, CH_1, rank 1
8587 13:18:10.300544 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8588 13:18:10.300645 ==
8589 13:18:10.300731 DQS Delay:
8590 13:18:10.304317 DQS0 = 0, DQS1 = 0
8591 13:18:10.304415 DQM Delay:
8592 13:18:10.307688 DQM0 = 131, DQM1 = 123
8593 13:18:10.307780 DQ Delay:
8594 13:18:10.310927 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =131
8595 13:18:10.313766 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8596 13:18:10.317433 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8597 13:18:10.320102 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =131
8598 13:18:10.320204
8599 13:18:10.320303
8600 13:18:10.320395 ==
8601 13:18:10.323445 Dram Type= 6, Freq= 0, CH_1, rank 1
8602 13:18:10.330326 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8603 13:18:10.330450 ==
8604 13:18:10.330543
8605 13:18:10.330643
8606 13:18:10.330732 TX Vref Scan disable
8607 13:18:10.334353 == TX Byte 0 ==
8608 13:18:10.337856 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8609 13:18:10.343951 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8610 13:18:10.344063 == TX Byte 1 ==
8611 13:18:10.347149 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8612 13:18:10.353653 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8613 13:18:10.353767 ==
8614 13:18:10.356747 Dram Type= 6, Freq= 0, CH_1, rank 1
8615 13:18:10.360223 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8616 13:18:10.360330 ==
8617 13:18:10.372225
8618 13:18:10.375735 TX Vref early break, caculate TX vref
8619 13:18:10.378905 TX Vref=16, minBit 3, minWin=22, winSum=382
8620 13:18:10.382450 TX Vref=18, minBit 5, minWin=22, winSum=388
8621 13:18:10.385526 TX Vref=20, minBit 0, minWin=24, winSum=400
8622 13:18:10.388865 TX Vref=22, minBit 4, minWin=24, winSum=404
8623 13:18:10.392230 TX Vref=24, minBit 0, minWin=25, winSum=413
8624 13:18:10.398624 TX Vref=26, minBit 0, minWin=24, winSum=420
8625 13:18:10.402182 TX Vref=28, minBit 0, minWin=25, winSum=420
8626 13:18:10.405802 TX Vref=30, minBit 0, minWin=25, winSum=416
8627 13:18:10.408929 TX Vref=32, minBit 0, minWin=25, winSum=408
8628 13:18:10.411893 TX Vref=34, minBit 0, minWin=23, winSum=397
8629 13:18:10.418913 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8630 13:18:10.419001
8631 13:18:10.421638 Final TX Range 0 Vref 28
8632 13:18:10.421717
8633 13:18:10.421798 ==
8634 13:18:10.425206 Dram Type= 6, Freq= 0, CH_1, rank 1
8635 13:18:10.428812 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8636 13:18:10.428892 ==
8637 13:18:10.428970
8638 13:18:10.429063
8639 13:18:10.432995 TX Vref Scan disable
8640 13:18:10.439012 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8641 13:18:10.439093 == TX Byte 0 ==
8642 13:18:10.441512 u2DelayCellOfst[0]=18 cells (5 PI)
8643 13:18:10.445135 u2DelayCellOfst[1]=10 cells (3 PI)
8644 13:18:10.448465 u2DelayCellOfst[2]=0 cells (0 PI)
8645 13:18:10.451898 u2DelayCellOfst[3]=7 cells (2 PI)
8646 13:18:10.454923 u2DelayCellOfst[4]=10 cells (3 PI)
8647 13:18:10.458705 u2DelayCellOfst[5]=14 cells (4 PI)
8648 13:18:10.461631 u2DelayCellOfst[6]=14 cells (4 PI)
8649 13:18:10.461713 u2DelayCellOfst[7]=7 cells (2 PI)
8650 13:18:10.468487 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8651 13:18:10.471536 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8652 13:18:10.471616 == TX Byte 1 ==
8653 13:18:10.475015 u2DelayCellOfst[8]=0 cells (0 PI)
8654 13:18:10.478697 u2DelayCellOfst[9]=7 cells (2 PI)
8655 13:18:10.481841 u2DelayCellOfst[10]=10 cells (3 PI)
8656 13:18:10.485346 u2DelayCellOfst[11]=3 cells (1 PI)
8657 13:18:10.488182 u2DelayCellOfst[12]=18 cells (5 PI)
8658 13:18:10.491823 u2DelayCellOfst[13]=21 cells (6 PI)
8659 13:18:10.495061 u2DelayCellOfst[14]=21 cells (6 PI)
8660 13:18:10.498432 u2DelayCellOfst[15]=21 cells (6 PI)
8661 13:18:10.501755 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8662 13:18:10.508350 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8663 13:18:10.508436 DramC Write-DBI on
8664 13:18:10.508511 ==
8665 13:18:10.511660 Dram Type= 6, Freq= 0, CH_1, rank 1
8666 13:18:10.514812 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8667 13:18:10.518042 ==
8668 13:18:10.518147
8669 13:18:10.518236
8670 13:18:10.518358 TX Vref Scan disable
8671 13:18:10.521719 == TX Byte 0 ==
8672 13:18:10.525825 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8673 13:18:10.528200 == TX Byte 1 ==
8674 13:18:10.531724 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8675 13:18:10.531801 DramC Write-DBI off
8676 13:18:10.536068
8677 13:18:10.536143 [DATLAT]
8678 13:18:10.536200 Freq=1600, CH1 RK1
8679 13:18:10.536255
8680 13:18:10.538306 DATLAT Default: 0xe
8681 13:18:10.538395 0, 0xFFFF, sum = 0
8682 13:18:10.541500 1, 0xFFFF, sum = 0
8683 13:18:10.541601 2, 0xFFFF, sum = 0
8684 13:18:10.544607 3, 0xFFFF, sum = 0
8685 13:18:10.544683 4, 0xFFFF, sum = 0
8686 13:18:10.548607 5, 0xFFFF, sum = 0
8687 13:18:10.551995 6, 0xFFFF, sum = 0
8688 13:18:10.552091 7, 0xFFFF, sum = 0
8689 13:18:10.554887 8, 0xFFFF, sum = 0
8690 13:18:10.554980 9, 0xFFFF, sum = 0
8691 13:18:10.557911 10, 0xFFFF, sum = 0
8692 13:18:10.557987 11, 0xFFFF, sum = 0
8693 13:18:10.561126 12, 0xF7F, sum = 0
8694 13:18:10.561253 13, 0x0, sum = 1
8695 13:18:10.565410 14, 0x0, sum = 2
8696 13:18:10.565487 15, 0x0, sum = 3
8697 13:18:10.567740 16, 0x0, sum = 4
8698 13:18:10.567816 best_step = 14
8699 13:18:10.567874
8700 13:18:10.567927 ==
8701 13:18:10.571099 Dram Type= 6, Freq= 0, CH_1, rank 1
8702 13:18:10.574855 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8703 13:18:10.577829 ==
8704 13:18:10.577904 RX Vref Scan: 0
8705 13:18:10.577962
8706 13:18:10.581520 RX Vref 0 -> 0, step: 1
8707 13:18:10.581595
8708 13:18:10.581653 RX Delay 3 -> 252, step: 4
8709 13:18:10.588183 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8710 13:18:10.591517 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8711 13:18:10.595283 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8712 13:18:10.598405 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8713 13:18:10.601698 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8714 13:18:10.608299 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8715 13:18:10.611802 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8716 13:18:10.615317 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8717 13:18:10.617975 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8718 13:18:10.621511 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8719 13:18:10.628654 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8720 13:18:10.632275 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8721 13:18:10.634721 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8722 13:18:10.637980 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8723 13:18:10.645379 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8724 13:18:10.647807 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8725 13:18:10.647885 ==
8726 13:18:10.651841 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 13:18:10.654573 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8728 13:18:10.654649 ==
8729 13:18:10.658131 DQS Delay:
8730 13:18:10.658235 DQS0 = 0, DQS1 = 0
8731 13:18:10.658323 DQM Delay:
8732 13:18:10.661395 DQM0 = 126, DQM1 = 122
8733 13:18:10.661470 DQ Delay:
8734 13:18:10.664828 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =122
8735 13:18:10.668333 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8736 13:18:10.671226 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8737 13:18:10.678114 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8738 13:18:10.678191
8739 13:18:10.678249
8740 13:18:10.678301
8741 13:18:10.681796 [DramC_TX_OE_Calibration] TA2
8742 13:18:10.681915 Original DQ_B0 (3 6) =30, OEN = 27
8743 13:18:10.684461 Original DQ_B1 (3 6) =30, OEN = 27
8744 13:18:10.688114 24, 0x0, End_B0=24 End_B1=24
8745 13:18:10.691040 25, 0x0, End_B0=25 End_B1=25
8746 13:18:10.694394 26, 0x0, End_B0=26 End_B1=26
8747 13:18:10.694486 27, 0x0, End_B0=27 End_B1=27
8748 13:18:10.698396 28, 0x0, End_B0=28 End_B1=28
8749 13:18:10.701122 29, 0x0, End_B0=29 End_B1=29
8750 13:18:10.705209 30, 0x0, End_B0=30 End_B1=30
8751 13:18:10.707728 31, 0x4141, End_B0=30 End_B1=30
8752 13:18:10.711205 Byte0 end_step=30 best_step=27
8753 13:18:10.711276 Byte1 end_step=30 best_step=27
8754 13:18:10.714697 Byte0 TX OE(2T, 0.5T) = (3, 3)
8755 13:18:10.717721 Byte1 TX OE(2T, 0.5T) = (3, 3)
8756 13:18:10.717803
8757 13:18:10.717858
8758 13:18:10.728219 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8759 13:18:10.728305 CH1 RK1: MR19=303, MR18=2121
8760 13:18:10.734234 CH1_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8761 13:18:10.738190 [RxdqsGatingPostProcess] freq 1600
8762 13:18:10.744974 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8763 13:18:10.747827 Pre-setting of DQS Precalculation
8764 13:18:10.751292 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8765 13:18:10.757776 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8766 13:18:10.767842 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8767 13:18:10.767924
8768 13:18:10.767983
8769 13:18:10.770848 [Calibration Summary] 3200 Mbps
8770 13:18:10.770924 CH 0, Rank 0
8771 13:18:10.774013 SW Impedance : PASS
8772 13:18:10.774089 DUTY Scan : NO K
8773 13:18:10.777377 ZQ Calibration : PASS
8774 13:18:10.780892 Jitter Meter : NO K
8775 13:18:10.780968 CBT Training : PASS
8776 13:18:10.784173 Write leveling : PASS
8777 13:18:10.784248 RX DQS gating : PASS
8778 13:18:10.787750 RX DQ/DQS(RDDQC) : PASS
8779 13:18:10.791123 TX DQ/DQS : PASS
8780 13:18:10.791199 RX DATLAT : PASS
8781 13:18:10.793952 RX DQ/DQS(Engine): PASS
8782 13:18:10.797542 TX OE : PASS
8783 13:18:10.797618 All Pass.
8784 13:18:10.797691
8785 13:18:10.797744 CH 0, Rank 1
8786 13:18:10.800545 SW Impedance : PASS
8787 13:18:10.804296 DUTY Scan : NO K
8788 13:18:10.804445 ZQ Calibration : PASS
8789 13:18:10.807609 Jitter Meter : NO K
8790 13:18:10.810511 CBT Training : PASS
8791 13:18:10.810609 Write leveling : PASS
8792 13:18:10.813866 RX DQS gating : PASS
8793 13:18:10.817735 RX DQ/DQS(RDDQC) : PASS
8794 13:18:10.817833 TX DQ/DQS : PASS
8795 13:18:10.820407 RX DATLAT : PASS
8796 13:18:10.824118 RX DQ/DQS(Engine): PASS
8797 13:18:10.824214 TX OE : PASS
8798 13:18:10.826896 All Pass.
8799 13:18:10.826995
8800 13:18:10.827082 CH 1, Rank 0
8801 13:18:10.830145 SW Impedance : PASS
8802 13:18:10.830244 DUTY Scan : NO K
8803 13:18:10.833542 ZQ Calibration : PASS
8804 13:18:10.837504 Jitter Meter : NO K
8805 13:18:10.837601 CBT Training : PASS
8806 13:18:10.840052 Write leveling : PASS
8807 13:18:10.843718 RX DQS gating : PASS
8808 13:18:10.843816 RX DQ/DQS(RDDQC) : PASS
8809 13:18:10.848031 TX DQ/DQS : PASS
8810 13:18:10.848129 RX DATLAT : PASS
8811 13:18:10.850258 RX DQ/DQS(Engine): PASS
8812 13:18:10.853532 TX OE : PASS
8813 13:18:10.853631 All Pass.
8814 13:18:10.853719
8815 13:18:10.853803 CH 1, Rank 1
8816 13:18:10.856859 SW Impedance : PASS
8817 13:18:10.860154 DUTY Scan : NO K
8818 13:18:10.860252 ZQ Calibration : PASS
8819 13:18:10.864363 Jitter Meter : NO K
8820 13:18:10.867428 CBT Training : PASS
8821 13:18:10.867529 Write leveling : PASS
8822 13:18:10.869935 RX DQS gating : PASS
8823 13:18:10.873271 RX DQ/DQS(RDDQC) : PASS
8824 13:18:10.873371 TX DQ/DQS : PASS
8825 13:18:10.877125 RX DATLAT : PASS
8826 13:18:10.880487 RX DQ/DQS(Engine): PASS
8827 13:18:10.880595 TX OE : PASS
8828 13:18:10.883821 All Pass.
8829 13:18:10.883916
8830 13:18:10.884000 DramC Write-DBI on
8831 13:18:10.887033 PER_BANK_REFRESH: Hybrid Mode
8832 13:18:10.887128 TX_TRACKING: ON
8833 13:18:10.896980 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8834 13:18:10.904027 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8835 13:18:10.913767 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8836 13:18:10.917332 [FAST_K] Save calibration result to emmc
8837 13:18:10.920100 sync common calibartion params.
8838 13:18:10.920197 sync cbt_mode0:0, 1:0
8839 13:18:10.923599 dram_init: ddr_geometry: 0
8840 13:18:10.926854 dram_init: ddr_geometry: 0
8841 13:18:10.926949 dram_init: ddr_geometry: 0
8842 13:18:10.930412 0:dram_rank_size:80000000
8843 13:18:10.933247 1:dram_rank_size:80000000
8844 13:18:10.936658 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8845 13:18:10.940434 DFS_SHUFFLE_HW_MODE: ON
8846 13:18:10.943110 dramc_set_vcore_voltage set vcore to 725000
8847 13:18:10.946806 Read voltage for 1600, 0
8848 13:18:10.946902 Vio18 = 0
8849 13:18:10.950877 Vcore = 725000
8850 13:18:10.950973 Vdram = 0
8851 13:18:10.951056 Vddq = 0
8852 13:18:10.951138 Vmddr = 0
8853 13:18:10.953441 switch to 3200 Mbps bootup
8854 13:18:10.956791 [DramcRunTimeConfig]
8855 13:18:10.956891 PHYPLL
8856 13:18:10.960175 DPM_CONTROL_AFTERK: ON
8857 13:18:10.960275 PER_BANK_REFRESH: ON
8858 13:18:10.963398 REFRESH_OVERHEAD_REDUCTION: ON
8859 13:18:10.966509 CMD_PICG_NEW_MODE: OFF
8860 13:18:10.966606 XRTWTW_NEW_MODE: ON
8861 13:18:10.970214 XRTRTR_NEW_MODE: ON
8862 13:18:10.970309 TX_TRACKING: ON
8863 13:18:10.972891 RDSEL_TRACKING: OFF
8864 13:18:10.976059 DQS Precalculation for DVFS: ON
8865 13:18:10.976155 RX_TRACKING: OFF
8866 13:18:10.980008 HW_GATING DBG: ON
8867 13:18:10.980103 ZQCS_ENABLE_LP4: ON
8868 13:18:10.983162 RX_PICG_NEW_MODE: ON
8869 13:18:10.983257 TX_PICG_NEW_MODE: ON
8870 13:18:10.987228 ENABLE_RX_DCM_DPHY: ON
8871 13:18:10.989423 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8872 13:18:10.992875 DUMMY_READ_FOR_TRACKING: OFF
8873 13:18:10.992971 !!! SPM_CONTROL_AFTERK: OFF
8874 13:18:10.996425 !!! SPM could not control APHY
8875 13:18:11.000129 IMPEDANCE_TRACKING: ON
8876 13:18:11.000225 TEMP_SENSOR: ON
8877 13:18:11.002390 HW_SAVE_FOR_SR: OFF
8878 13:18:11.006063 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8879 13:18:11.009966 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8880 13:18:11.010077 Read ODT Tracking: ON
8881 13:18:11.012617 Refresh Rate DeBounce: ON
8882 13:18:11.015689 DFS_NO_QUEUE_FLUSH: ON
8883 13:18:11.019310 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8884 13:18:11.019405 ENABLE_DFS_RUNTIME_MRW: OFF
8885 13:18:11.022516 DDR_RESERVE_NEW_MODE: ON
8886 13:18:11.025996 MR_CBT_SWITCH_FREQ: ON
8887 13:18:11.026091 =========================
8888 13:18:11.046144 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8889 13:18:11.049084 dram_init: ddr_geometry: 0
8890 13:18:11.067424 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8891 13:18:11.070867 dram_init: dram init end (result: 0)
8892 13:18:11.077813 DRAM-K: Full calibration passed in 23401 msecs
8893 13:18:11.080460 MRC: failed to locate region type 0.
8894 13:18:11.080556 DRAM rank0 size:0x80000000,
8895 13:18:11.083965 DRAM rank1 size=0x80000000
8896 13:18:11.093575 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8897 13:18:11.100659 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8898 13:18:11.107351 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8899 13:18:11.113818 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8900 13:18:11.117023 DRAM rank0 size:0x80000000,
8901 13:18:11.120128 DRAM rank1 size=0x80000000
8902 13:18:11.120223 CBMEM:
8903 13:18:11.123889 IMD: root @ 0xfffff000 254 entries.
8904 13:18:11.126864 IMD: root @ 0xffffec00 62 entries.
8905 13:18:11.131002 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8906 13:18:11.134386 WARNING: RO_VPD is uninitialized or empty.
8907 13:18:11.140167 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8908 13:18:11.147180 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8909 13:18:11.160090 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8910 13:18:11.171842 BS: romstage times (exec / console): total (unknown) / 22942 ms
8911 13:18:11.171959
8912 13:18:11.172077
8913 13:18:11.180798 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8914 13:18:11.184738 ARM64: Exception handlers installed.
8915 13:18:11.188039 ARM64: Testing exception
8916 13:18:11.191271 ARM64: Done test exception
8917 13:18:11.191369 Enumerating buses...
8918 13:18:11.194223 Show all devs... Before device enumeration.
8919 13:18:11.197570 Root Device: enabled 1
8920 13:18:11.201114 CPU_CLUSTER: 0: enabled 1
8921 13:18:11.201212 CPU: 00: enabled 1
8922 13:18:11.204871 Compare with tree...
8923 13:18:11.204970 Root Device: enabled 1
8924 13:18:11.207737 CPU_CLUSTER: 0: enabled 1
8925 13:18:11.211128 CPU: 00: enabled 1
8926 13:18:11.211226 Root Device scanning...
8927 13:18:11.213925 scan_static_bus for Root Device
8928 13:18:11.217178 CPU_CLUSTER: 0 enabled
8929 13:18:11.220910 scan_static_bus for Root Device done
8930 13:18:11.224337 scan_bus: bus Root Device finished in 8 msecs
8931 13:18:11.224436 done
8932 13:18:11.231138 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8933 13:18:11.233856 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8934 13:18:11.240622 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8935 13:18:11.244146 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8936 13:18:11.247902 Allocating resources...
8937 13:18:11.250970 Reading resources...
8938 13:18:11.253871 Root Device read_resources bus 0 link: 0
8939 13:18:11.253968 DRAM rank0 size:0x80000000,
8940 13:18:11.256985 DRAM rank1 size=0x80000000
8941 13:18:11.260569 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8942 13:18:11.264771 CPU: 00 missing read_resources
8943 13:18:11.266740 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8944 13:18:11.273703 Root Device read_resources bus 0 link: 0 done
8945 13:18:11.273857 Done reading resources.
8946 13:18:11.280427 Show resources in subtree (Root Device)...After reading.
8947 13:18:11.283665 Root Device child on link 0 CPU_CLUSTER: 0
8948 13:18:11.287743 CPU_CLUSTER: 0 child on link 0 CPU: 00
8949 13:18:11.297028 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8950 13:18:11.297137 CPU: 00
8951 13:18:11.300344 Root Device assign_resources, bus 0 link: 0
8952 13:18:11.303766 CPU_CLUSTER: 0 missing set_resources
8953 13:18:11.310196 Root Device assign_resources, bus 0 link: 0 done
8954 13:18:11.310304 Done setting resources.
8955 13:18:11.317222 Show resources in subtree (Root Device)...After assigning values.
8956 13:18:11.320194 Root Device child on link 0 CPU_CLUSTER: 0
8957 13:18:11.323158 CPU_CLUSTER: 0 child on link 0 CPU: 00
8958 13:18:11.333366 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8959 13:18:11.333481 CPU: 00
8960 13:18:11.337165 Done allocating resources.
8961 13:18:11.340812 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8962 13:18:11.343006 Enabling resources...
8963 13:18:11.343107 done.
8964 13:18:11.350046 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8965 13:18:11.350150 Initializing devices...
8966 13:18:11.352865 Root Device init
8967 13:18:11.352959 init hardware done!
8968 13:18:11.356655 0x00000018: ctrlr->caps
8969 13:18:11.360580 52.000 MHz: ctrlr->f_max
8970 13:18:11.360685 0.400 MHz: ctrlr->f_min
8971 13:18:11.363027 0x40ff8080: ctrlr->voltages
8972 13:18:11.366283 sclk: 390625
8973 13:18:11.366382 Bus Width = 1
8974 13:18:11.366469 sclk: 390625
8975 13:18:11.369326 Bus Width = 1
8976 13:18:11.369424 Early init status = 3
8977 13:18:11.376027 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8978 13:18:11.379711 in-header: 03 fc 00 00 01 00 00 00
8979 13:18:11.379809 in-data: 00
8980 13:18:11.386363 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8981 13:18:11.389928 in-header: 03 fd 00 00 00 00 00 00
8982 13:18:11.393503 in-data:
8983 13:18:11.396281 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8984 13:18:11.400732 in-header: 03 fc 00 00 01 00 00 00
8985 13:18:11.403126 in-data: 00
8986 13:18:11.406072 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8987 13:18:11.411010 in-header: 03 fd 00 00 00 00 00 00
8988 13:18:11.414521 in-data:
8989 13:18:11.417936 [SSUSB] Setting up USB HOST controller...
8990 13:18:11.420961 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8991 13:18:11.424516 [SSUSB] phy power-on done.
8992 13:18:11.427742 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8993 13:18:11.434856 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8994 13:18:11.438226 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8995 13:18:11.444361 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8996 13:18:11.450893 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8997 13:18:11.457559 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8998 13:18:11.464240 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8999 13:18:11.471158 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9000 13:18:11.474159 SPM: binary array size = 0x9dc
9001 13:18:11.477797 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9002 13:18:11.484042 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9003 13:18:11.490986 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9004 13:18:11.497565 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9005 13:18:11.500527 configure_display: Starting display init
9006 13:18:11.534443 anx7625_power_on_init: Init interface.
9007 13:18:11.538683 anx7625_disable_pd_protocol: Disabled PD feature.
9008 13:18:11.541346 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9009 13:18:11.568928 anx7625_start_dp_work: Secure OCM version=00
9010 13:18:11.571961 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9011 13:18:11.586943 sp_tx_get_edid_block: EDID Block = 1
9012 13:18:11.690171 Extracted contents:
9013 13:18:11.692879 header: 00 ff ff ff ff ff ff 00
9014 13:18:11.696291 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9015 13:18:11.699480 version: 01 04
9016 13:18:11.702452 basic params: 95 1f 11 78 0a
9017 13:18:11.706059 chroma info: 76 90 94 55 54 90 27 21 50 54
9018 13:18:11.709873 established: 00 00 00
9019 13:18:11.716177 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9020 13:18:11.719363 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9021 13:18:11.726473 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9022 13:18:11.733175 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9023 13:18:11.739084 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9024 13:18:11.742729 extensions: 00
9025 13:18:11.742822 checksum: fb
9026 13:18:11.742911
9027 13:18:11.746074 Manufacturer: IVO Model 57d Serial Number 0
9028 13:18:11.749547 Made week 0 of 2020
9029 13:18:11.749623 EDID version: 1.4
9030 13:18:11.753073 Digital display
9031 13:18:11.756314 6 bits per primary color channel
9032 13:18:11.756392 DisplayPort interface
9033 13:18:11.758917 Maximum image size: 31 cm x 17 cm
9034 13:18:11.762355 Gamma: 220%
9035 13:18:11.762432 Check DPMS levels
9036 13:18:11.765834 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9037 13:18:11.772274 First detailed timing is preferred timing
9038 13:18:11.772351 Established timings supported:
9039 13:18:11.775442 Standard timings supported:
9040 13:18:11.779714 Detailed timings
9041 13:18:11.782629 Hex of detail: 383680a07038204018303c0035ae10000019
9042 13:18:11.785548 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9043 13:18:11.793090 0780 0798 07c8 0820 hborder 0
9044 13:18:11.795505 0438 043b 0447 0458 vborder 0
9045 13:18:11.798855 -hsync -vsync
9046 13:18:11.798949 Did detailed timing
9047 13:18:11.805806 Hex of detail: 000000000000000000000000000000000000
9048 13:18:11.805916 Manufacturer-specified data, tag 0
9049 13:18:11.812250 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9050 13:18:11.816349 ASCII string: InfoVision
9051 13:18:11.819167 Hex of detail: 000000fe00523134304e574635205248200a
9052 13:18:11.822493 ASCII string: R140NWF5 RH
9053 13:18:11.822622 Checksum
9054 13:18:11.825273 Checksum: 0xfb (valid)
9055 13:18:11.829613 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9056 13:18:11.831997 DSI data_rate: 832800000 bps
9057 13:18:11.838744 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9058 13:18:11.842222 anx7625_parse_edid: pixelclock(138800).
9059 13:18:11.845121 hactive(1920), hsync(48), hfp(24), hbp(88)
9060 13:18:11.848711 vactive(1080), vsync(12), vfp(3), vbp(17)
9061 13:18:11.853028 anx7625_dsi_config: config dsi.
9062 13:18:11.858659 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9063 13:18:11.871550 anx7625_dsi_config: success to config DSI
9064 13:18:11.875001 anx7625_dp_start: MIPI phy setup OK.
9065 13:18:11.878534 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9066 13:18:11.882009 mtk_ddp_mode_set invalid vrefresh 60
9067 13:18:11.884909 main_disp_path_setup
9068 13:18:11.885013 ovl_layer_smi_id_en
9069 13:18:11.888630 ovl_layer_smi_id_en
9070 13:18:11.888721 ccorr_config
9071 13:18:11.888793 aal_config
9072 13:18:11.891596 gamma_config
9073 13:18:11.891688 postmask_config
9074 13:18:11.895082 dither_config
9075 13:18:11.898965 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9076 13:18:11.904926 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9077 13:18:11.909078 Root Device init finished in 551 msecs
9078 13:18:11.912048 CPU_CLUSTER: 0 init
9079 13:18:11.918541 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9080 13:18:11.921601 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9081 13:18:11.925124 APU_MBOX 0x190000b0 = 0x10001
9082 13:18:11.928183 APU_MBOX 0x190001b0 = 0x10001
9083 13:18:11.930967 APU_MBOX 0x190005b0 = 0x10001
9084 13:18:11.934616 APU_MBOX 0x190006b0 = 0x10001
9085 13:18:11.937938 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9086 13:18:11.950732 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9087 13:18:11.962982 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9088 13:18:11.969337 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9089 13:18:11.981644 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9090 13:18:11.990502 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9091 13:18:11.993401 CPU_CLUSTER: 0 init finished in 81 msecs
9092 13:18:11.997365 Devices initialized
9093 13:18:12.000700 Show all devs... After init.
9094 13:18:12.000798 Root Device: enabled 1
9095 13:18:12.003435 CPU_CLUSTER: 0: enabled 1
9096 13:18:12.007234 CPU: 00: enabled 1
9097 13:18:12.010432 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9098 13:18:12.013595 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9099 13:18:12.016952 ELOG: NV offset 0x57f000 size 0x1000
9100 13:18:12.023976 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9101 13:18:12.030384 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9102 13:18:12.034129 ELOG: Event(17) added with size 13 at 2024-07-18 13:18:11 UTC
9103 13:18:12.036875 out: cmd=0x121: 03 db 21 01 00 00 00 00
9104 13:18:12.041380 in-header: 03 00 00 00 2c 00 00 00
9105 13:18:12.054722 in-data: 42 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9106 13:18:12.061339 ELOG: Event(A1) added with size 10 at 2024-07-18 13:18:11 UTC
9107 13:18:12.068516 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9108 13:18:12.071617 ELOG: Event(A0) added with size 9 at 2024-07-18 13:18:11 UTC
9109 13:18:12.078096 elog_add_boot_reason: Logged dev mode boot
9110 13:18:12.081579 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9111 13:18:12.085092 Finalize devices...
9112 13:18:12.085193 Devices finalized
9113 13:18:12.091548 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9114 13:18:12.094679 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9115 13:18:12.098604 in-header: 03 07 00 00 08 00 00 00
9116 13:18:12.101415 in-data: aa e4 47 04 13 02 00 00
9117 13:18:12.101489 Chrome EC: UHEPI supported
9118 13:18:12.108026 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9119 13:18:12.111784 in-header: 03 a9 00 00 08 00 00 00
9120 13:18:12.115545 in-data: 84 60 60 08 00 00 00 00
9121 13:18:12.121763 ELOG: Event(91) added with size 10 at 2024-07-18 13:18:11 UTC
9122 13:18:12.125487 Chrome EC: clear events_b mask to 0x0000000020004000
9123 13:18:12.131994 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9124 13:18:12.136531 in-header: 03 fd 00 00 00 00 00 00
9125 13:18:12.139577 in-data:
9126 13:18:12.142553 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9127 13:18:12.145834 Writing coreboot table at 0xffe64000
9128 13:18:12.152542 0. 000000000010a000-0000000000113fff: RAMSTAGE
9129 13:18:12.156354 1. 0000000040000000-00000000400fffff: RAM
9130 13:18:12.159791 2. 0000000040100000-000000004032afff: RAMSTAGE
9131 13:18:12.162463 3. 000000004032b000-00000000545fffff: RAM
9132 13:18:12.165938 4. 0000000054600000-000000005465ffff: BL31
9133 13:18:12.169221 5. 0000000054660000-00000000ffe63fff: RAM
9134 13:18:12.175861 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9135 13:18:12.179069 7. 0000000100000000-000000013fffffff: RAM
9136 13:18:12.182104 Passing 5 GPIOs to payload:
9137 13:18:12.185700 NAME | PORT | POLARITY | VALUE
9138 13:18:12.192485 EC in RW | 0x000000aa | low | undefined
9139 13:18:12.196192 EC interrupt | 0x00000005 | low | undefined
9140 13:18:12.198951 TPM interrupt | 0x000000ab | high | undefined
9141 13:18:12.205797 SD card detect | 0x00000011 | high | undefined
9142 13:18:12.209349 speaker enable | 0x00000093 | high | undefined
9143 13:18:12.212125 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9144 13:18:12.216294 in-header: 03 f8 00 00 02 00 00 00
9145 13:18:12.219325 in-data: 03 00
9146 13:18:12.222664 ADC[4]: Raw value=668958 ID=5
9147 13:18:12.226319 ADC[3]: Raw value=212549 ID=1
9148 13:18:12.226422 RAM Code: 0x51
9149 13:18:12.229440 ADC[6]: Raw value=74778 ID=0
9150 13:18:12.232434 ADC[5]: Raw value=211812 ID=1
9151 13:18:12.232546 SKU Code: 0x1
9152 13:18:12.239786 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum db59
9153 13:18:12.239904 coreboot table: 964 bytes.
9154 13:18:12.242553 IMD ROOT 0. 0xfffff000 0x00001000
9155 13:18:12.246668 IMD SMALL 1. 0xffffe000 0x00001000
9156 13:18:12.249457 RO MCACHE 2. 0xffffc000 0x00001104
9157 13:18:12.252821 CONSOLE 3. 0xfff7c000 0x00080000
9158 13:18:12.256453 FMAP 4. 0xfff7b000 0x00000452
9159 13:18:12.259146 TIME STAMP 5. 0xfff7a000 0x00000910
9160 13:18:12.262571 VBOOT WORK 6. 0xfff66000 0x00014000
9161 13:18:12.265473 RAMOOPS 7. 0xffe66000 0x00100000
9162 13:18:12.269260 COREBOOT 8. 0xffe64000 0x00002000
9163 13:18:12.273214 IMD small region:
9164 13:18:12.275921 IMD ROOT 0. 0xffffec00 0x00000400
9165 13:18:12.279127 VPD 1. 0xffffeb80 0x0000006c
9166 13:18:12.282420 MMC STATUS 2. 0xffffeb60 0x00000004
9167 13:18:12.285965 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9168 13:18:12.292201 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9169 13:18:12.333454 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9170 13:18:12.337349 Checking segment from ROM address 0x40100000
9171 13:18:12.340265 Checking segment from ROM address 0x4010001c
9172 13:18:12.347583 Loading segment from ROM address 0x40100000
9173 13:18:12.347657 code (compression=0)
9174 13:18:12.356832 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9175 13:18:12.363472 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9176 13:18:12.363554 it's not compressed!
9177 13:18:12.370669 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9178 13:18:12.374862 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9179 13:18:12.393741 Loading segment from ROM address 0x4010001c
9180 13:18:12.393843 Entry Point 0x80000000
9181 13:18:12.397566 Loaded segments
9182 13:18:12.400995 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9183 13:18:12.407279 Jumping to boot code at 0x80000000(0xffe64000)
9184 13:18:12.414390 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9185 13:18:12.420736 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9186 13:18:12.428576 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9187 13:18:12.431930 Checking segment from ROM address 0x40100000
9188 13:18:12.435906 Checking segment from ROM address 0x4010001c
9189 13:18:12.441692 Loading segment from ROM address 0x40100000
9190 13:18:12.441766 code (compression=1)
9191 13:18:12.448902 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9192 13:18:12.458575 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9193 13:18:12.458657 using LZMA
9194 13:18:12.467110 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9195 13:18:12.473920 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9196 13:18:12.477032 Loading segment from ROM address 0x4010001c
9197 13:18:12.477128 Entry Point 0x54601000
9198 13:18:12.480582 Loaded segments
9199 13:18:12.483164 NOTICE: MT8192 bl31_setup
9200 13:18:12.491095 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9201 13:18:12.494075 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9202 13:18:12.497894 WARNING: region 0:
9203 13:18:12.500487 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9204 13:18:12.500548 WARNING: region 1:
9205 13:18:12.507199 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9206 13:18:12.510293 WARNING: region 2:
9207 13:18:12.513871 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9208 13:18:12.517122 WARNING: region 3:
9209 13:18:12.520358 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9210 13:18:12.523700 WARNING: region 4:
9211 13:18:12.530855 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9212 13:18:12.530925 WARNING: region 5:
9213 13:18:12.535074 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9214 13:18:12.537278 WARNING: region 6:
9215 13:18:12.540249 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9216 13:18:12.543927 WARNING: region 7:
9217 13:18:12.546886 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9218 13:18:12.553818 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9219 13:18:12.556934 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9220 13:18:12.560584 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9221 13:18:12.566902 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9222 13:18:12.570822 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9223 13:18:12.573679 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9224 13:18:12.580081 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9225 13:18:12.584166 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9226 13:18:12.590198 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9227 13:18:12.593816 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9228 13:18:12.597354 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9229 13:18:12.603232 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9230 13:18:12.606522 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9231 13:18:12.610041 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9232 13:18:12.616857 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9233 13:18:12.620095 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9234 13:18:12.626964 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9235 13:18:12.630294 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9236 13:18:12.633106 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9237 13:18:12.640223 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9238 13:18:12.643761 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9239 13:18:12.649968 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9240 13:18:12.653095 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9241 13:18:12.656421 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9242 13:18:12.663026 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9243 13:18:12.666733 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9244 13:18:12.672888 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9245 13:18:12.676090 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9246 13:18:12.679891 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9247 13:18:12.686380 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9248 13:18:12.690211 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9249 13:18:12.696434 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9250 13:18:12.699803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9251 13:18:12.702634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9252 13:18:12.706066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9253 13:18:12.713038 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9254 13:18:12.716306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9255 13:18:12.719407 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9256 13:18:12.722452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9257 13:18:12.729204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9258 13:18:12.733063 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9259 13:18:12.736621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9260 13:18:12.739089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9261 13:18:12.746602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9262 13:18:12.749868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9263 13:18:12.752563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9264 13:18:12.756221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9265 13:18:12.762844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9266 13:18:12.766087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9267 13:18:12.773082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9268 13:18:12.775792 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9269 13:18:12.779248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9270 13:18:12.785818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9271 13:18:12.789329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9272 13:18:12.795694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9273 13:18:12.800102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9274 13:18:12.805447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9275 13:18:12.809181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9276 13:18:12.812389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9277 13:18:12.819326 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9278 13:18:12.822449 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9279 13:18:12.828827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9280 13:18:12.832501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9281 13:18:12.839255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9282 13:18:12.842342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9283 13:18:12.849004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9284 13:18:12.852617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9285 13:18:12.855366 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9286 13:18:12.862570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9287 13:18:12.865611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9288 13:18:12.872269 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9289 13:18:12.876047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9290 13:18:12.878730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9291 13:18:12.885145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9292 13:18:12.888835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9293 13:18:12.895429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9294 13:18:12.898783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9295 13:18:12.905600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9296 13:18:12.908827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9297 13:18:12.915460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9298 13:18:12.919377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9299 13:18:12.922046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9300 13:18:12.928602 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9301 13:18:12.932022 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9302 13:18:12.938864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9303 13:18:12.941888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9304 13:18:12.948513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9305 13:18:12.952311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9306 13:18:12.955206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9307 13:18:12.961980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9308 13:18:12.965579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9309 13:18:12.972055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9310 13:18:12.975351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9311 13:18:12.981708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9312 13:18:12.985060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9313 13:18:12.992389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9314 13:18:12.995122 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9315 13:18:12.999044 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9316 13:18:13.002187 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9317 13:18:13.008367 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9318 13:18:13.011516 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9319 13:18:13.014983 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9320 13:18:13.021662 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9321 13:18:13.025528 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9322 13:18:13.031271 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9323 13:18:13.035246 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9324 13:18:13.038158 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9325 13:18:13.045185 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9326 13:18:13.048091 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9327 13:18:13.054607 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9328 13:18:13.057926 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9329 13:18:13.061240 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9330 13:18:13.068031 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9331 13:18:13.071462 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9332 13:18:13.077935 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9333 13:18:13.081428 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9334 13:18:13.084805 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9335 13:18:13.088093 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9336 13:18:13.094972 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9337 13:18:13.098598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9338 13:18:13.101433 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9339 13:18:13.107851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9340 13:18:13.111102 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9341 13:18:13.114265 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9342 13:18:13.121063 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9343 13:18:13.124689 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9344 13:18:13.127717 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9345 13:18:13.133886 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9346 13:18:13.137357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9347 13:18:13.143885 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9348 13:18:13.147212 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9349 13:18:13.150687 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9350 13:18:13.157197 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9351 13:18:13.160794 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9352 13:18:13.167609 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9353 13:18:13.170307 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9354 13:18:13.174079 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9355 13:18:13.180496 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9356 13:18:13.183904 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9357 13:18:13.187224 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9358 13:18:13.193570 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9359 13:18:13.197113 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9360 13:18:13.203502 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9361 13:18:13.206903 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9362 13:18:13.210058 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9363 13:18:13.216639 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9364 13:18:13.219794 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9365 13:18:13.226380 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9366 13:18:13.229863 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9367 13:18:13.236695 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9368 13:18:13.239708 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9369 13:18:13.243574 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9370 13:18:13.249903 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9371 13:18:13.253387 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9372 13:18:13.256564 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9373 13:18:13.263232 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9374 13:18:13.266309 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9375 13:18:13.273385 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9376 13:18:13.276092 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9377 13:18:13.279677 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9378 13:18:13.286049 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9379 13:18:13.289955 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9380 13:18:13.296318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9381 13:18:13.300140 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9382 13:18:13.303137 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9383 13:18:13.309587 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9384 13:18:13.313100 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9385 13:18:13.319576 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9386 13:18:13.322860 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9387 13:18:13.325804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9388 13:18:13.333040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9389 13:18:13.335853 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9390 13:18:13.339295 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9391 13:18:13.345833 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9392 13:18:13.349008 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9393 13:18:13.356013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9394 13:18:13.359541 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9395 13:18:13.362906 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9396 13:18:13.369772 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9397 13:18:13.372541 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9398 13:18:13.378895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9399 13:18:13.382678 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9400 13:18:13.385696 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9401 13:18:13.392493 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9402 13:18:13.395734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9403 13:18:13.402347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9404 13:18:13.405283 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9405 13:18:13.408845 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9406 13:18:13.415220 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9407 13:18:13.418864 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9408 13:18:13.425920 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9409 13:18:13.428675 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9410 13:18:13.435371 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9411 13:18:13.438563 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9412 13:18:13.442805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9413 13:18:13.448976 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9414 13:18:13.452054 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9415 13:18:13.458962 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9416 13:18:13.462546 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9417 13:18:13.465406 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9418 13:18:13.472110 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9419 13:18:13.475615 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9420 13:18:13.482409 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9421 13:18:13.485342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9422 13:18:13.492085 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9423 13:18:13.495392 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9424 13:18:13.498606 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9425 13:18:13.505473 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9426 13:18:13.508955 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9427 13:18:13.515191 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9428 13:18:13.518201 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9429 13:18:13.521718 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9430 13:18:13.528120 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9431 13:18:13.532091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9432 13:18:13.538205 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9433 13:18:13.541762 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9434 13:18:13.547933 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9435 13:18:13.551994 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9436 13:18:13.555045 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9437 13:18:13.561188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9438 13:18:13.564577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9439 13:18:13.571180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9440 13:18:13.574539 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9441 13:18:13.578016 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9442 13:18:13.584512 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9443 13:18:13.588370 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9444 13:18:13.595174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9445 13:18:13.597778 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9446 13:18:13.604660 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9447 13:18:13.607841 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9448 13:18:13.611978 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9449 13:18:13.614337 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9450 13:18:13.617858 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9451 13:18:13.624588 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9452 13:18:13.627496 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9453 13:18:13.630788 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9454 13:18:13.638040 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9455 13:18:13.641336 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9456 13:18:13.644301 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9457 13:18:13.651330 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9458 13:18:13.654595 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9459 13:18:13.660611 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9460 13:18:13.664877 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9461 13:18:13.667411 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9462 13:18:13.674108 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9463 13:18:13.677353 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9464 13:18:13.684466 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9465 13:18:13.687344 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9466 13:18:13.690461 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9467 13:18:13.697998 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9468 13:18:13.700756 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9469 13:18:13.704104 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9470 13:18:13.710219 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9471 13:18:13.713808 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9472 13:18:13.717016 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9473 13:18:13.723535 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9474 13:18:13.727140 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9475 13:18:13.733842 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9476 13:18:13.737490 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9477 13:18:13.740909 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9478 13:18:13.747410 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9479 13:18:13.750635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9480 13:18:13.753427 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9481 13:18:13.760429 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9482 13:18:13.763672 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9483 13:18:13.766460 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9484 13:18:13.773615 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9485 13:18:13.776909 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9486 13:18:13.783517 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9487 13:18:13.787319 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9488 13:18:13.790215 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9489 13:18:13.793452 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9490 13:18:13.796498 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9491 13:18:13.803108 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9492 13:18:13.806398 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9493 13:18:13.809713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9494 13:18:13.813418 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9495 13:18:13.820861 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9496 13:18:13.823038 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9497 13:18:13.826969 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9498 13:18:13.833309 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9499 13:18:13.836443 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9500 13:18:13.839860 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9501 13:18:13.846368 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9502 13:18:13.849616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9503 13:18:13.852675 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9504 13:18:13.859580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9505 13:18:13.863031 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9506 13:18:13.869651 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9507 13:18:13.872633 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9508 13:18:13.875827 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9509 13:18:13.883030 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9510 13:18:13.886091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9511 13:18:13.892757 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9512 13:18:13.895916 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9513 13:18:13.902530 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9514 13:18:13.906270 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9515 13:18:13.909125 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9516 13:18:13.915881 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9517 13:18:13.919727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9518 13:18:13.925823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9519 13:18:13.929589 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9520 13:18:13.932857 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9521 13:18:13.939298 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9522 13:18:13.942801 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9523 13:18:13.949717 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9524 13:18:13.952681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9525 13:18:13.955619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9526 13:18:13.962340 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9527 13:18:13.965841 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9528 13:18:13.972148 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9529 13:18:13.975700 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9530 13:18:13.982782 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9531 13:18:13.985754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9532 13:18:13.989113 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9533 13:18:13.995448 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9534 13:18:13.999188 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9535 13:18:14.006094 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9536 13:18:14.009484 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9537 13:18:14.012119 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9538 13:18:14.019475 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9539 13:18:14.022029 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9540 13:18:14.028745 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9541 13:18:14.032124 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9542 13:18:14.036162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9543 13:18:14.042154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9544 13:18:14.045336 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9545 13:18:14.052043 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9546 13:18:14.055318 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9547 13:18:14.058558 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9548 13:18:14.065380 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9549 13:18:14.068595 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9550 13:18:14.075410 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9551 13:18:14.079241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9552 13:18:14.085591 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9553 13:18:14.088471 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9554 13:18:14.091964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9555 13:18:14.098754 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9556 13:18:14.101651 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9557 13:18:14.108233 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9558 13:18:14.112182 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9559 13:18:14.114922 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9560 13:18:14.121678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9561 13:18:14.125478 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9562 13:18:14.131593 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9563 13:18:14.135429 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9564 13:18:14.138129 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9565 13:18:14.144934 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9566 13:18:14.148194 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9567 13:18:14.154669 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9568 13:18:14.158213 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9569 13:18:14.164967 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9570 13:18:14.168171 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9571 13:18:14.171758 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9572 13:18:14.177955 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9573 13:18:14.181104 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9574 13:18:14.187945 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9575 13:18:14.191223 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9576 13:18:14.197635 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9577 13:18:14.201340 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9578 13:18:14.205070 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9579 13:18:14.211244 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9580 13:18:14.214787 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9581 13:18:14.220997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9582 13:18:14.224546 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9583 13:18:14.231164 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9584 13:18:14.234202 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9585 13:18:14.237477 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9586 13:18:14.244014 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9587 13:18:14.247760 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9588 13:18:14.254100 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9589 13:18:14.257989 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9590 13:18:14.264894 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9591 13:18:14.267581 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9592 13:18:14.270738 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9593 13:18:14.277409 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9594 13:18:14.281134 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9595 13:18:14.287401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9596 13:18:14.291137 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9597 13:18:14.297954 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9598 13:18:14.300911 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9599 13:18:14.304374 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9600 13:18:14.310744 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9601 13:18:14.314327 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9602 13:18:14.320953 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9603 13:18:14.324173 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9604 13:18:14.330657 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9605 13:18:14.334241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9606 13:18:14.337078 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9607 13:18:14.344133 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9608 13:18:14.348118 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9609 13:18:14.354128 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9610 13:18:14.357258 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9611 13:18:14.364004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9612 13:18:14.366864 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9613 13:18:14.373570 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9614 13:18:14.377132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9615 13:18:14.380744 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9616 13:18:14.387007 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9617 13:18:14.390414 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9618 13:18:14.396812 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9619 13:18:14.400211 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9620 13:18:14.403907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9621 13:18:14.409930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9622 13:18:14.413212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9623 13:18:14.419755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9624 13:18:14.424049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9625 13:18:14.430263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9626 13:18:14.434111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9627 13:18:14.440401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9628 13:18:14.443331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9629 13:18:14.450089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9630 13:18:14.453874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9631 13:18:14.460108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9632 13:18:14.463740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9633 13:18:14.469814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9634 13:18:14.473176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9635 13:18:14.479970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9636 13:18:14.483765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9637 13:18:14.489606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9638 13:18:14.492960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9639 13:18:14.499666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9640 13:18:14.502860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9641 13:18:14.509766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9642 13:18:14.513440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9643 13:18:14.519979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9644 13:18:14.522676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9645 13:18:14.529428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9646 13:18:14.532905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9647 13:18:14.539403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9648 13:18:14.543118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9649 13:18:14.549036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9650 13:18:14.552511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9651 13:18:14.559581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9652 13:18:14.562971 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9653 13:18:14.565609 INFO: [APUAPC] vio 0
9654 13:18:14.569316 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9655 13:18:14.572171 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9656 13:18:14.575868 INFO: [APUAPC] D0_APC_0: 0x400510
9657 13:18:14.579358 INFO: [APUAPC] D0_APC_1: 0x0
9658 13:18:14.582441 INFO: [APUAPC] D0_APC_2: 0x1540
9659 13:18:14.586873 INFO: [APUAPC] D0_APC_3: 0x0
9660 13:18:14.589054 INFO: [APUAPC] D1_APC_0: 0xffffffff
9661 13:18:14.592085 INFO: [APUAPC] D1_APC_1: 0xffffffff
9662 13:18:14.595314 INFO: [APUAPC] D1_APC_2: 0x3fffff
9663 13:18:14.598799 INFO: [APUAPC] D1_APC_3: 0x0
9664 13:18:14.601939 INFO: [APUAPC] D2_APC_0: 0xffffffff
9665 13:18:14.605390 INFO: [APUAPC] D2_APC_1: 0xffffffff
9666 13:18:14.609128 INFO: [APUAPC] D2_APC_2: 0x3fffff
9667 13:18:14.612101 INFO: [APUAPC] D2_APC_3: 0x0
9668 13:18:14.615712 INFO: [APUAPC] D3_APC_0: 0xffffffff
9669 13:18:14.618806 INFO: [APUAPC] D3_APC_1: 0xffffffff
9670 13:18:14.621891 INFO: [APUAPC] D3_APC_2: 0x3fffff
9671 13:18:14.625420 INFO: [APUAPC] D3_APC_3: 0x0
9672 13:18:14.629467 INFO: [APUAPC] D4_APC_0: 0xffffffff
9673 13:18:14.632367 INFO: [APUAPC] D4_APC_1: 0xffffffff
9674 13:18:14.636345 INFO: [APUAPC] D4_APC_2: 0x3fffff
9675 13:18:14.638538 INFO: [APUAPC] D4_APC_3: 0x0
9676 13:18:14.642221 INFO: [APUAPC] D5_APC_0: 0xffffffff
9677 13:18:14.645258 INFO: [APUAPC] D5_APC_1: 0xffffffff
9678 13:18:14.648471 INFO: [APUAPC] D5_APC_2: 0x3fffff
9679 13:18:14.652045 INFO: [APUAPC] D5_APC_3: 0x0
9680 13:18:14.655069 INFO: [APUAPC] D6_APC_0: 0xffffffff
9681 13:18:14.658690 INFO: [APUAPC] D6_APC_1: 0xffffffff
9682 13:18:14.661628 INFO: [APUAPC] D6_APC_2: 0x3fffff
9683 13:18:14.665201 INFO: [APUAPC] D6_APC_3: 0x0
9684 13:18:14.668650 INFO: [APUAPC] D7_APC_0: 0xffffffff
9685 13:18:14.671667 INFO: [APUAPC] D7_APC_1: 0xffffffff
9686 13:18:14.675125 INFO: [APUAPC] D7_APC_2: 0x3fffff
9687 13:18:14.678619 INFO: [APUAPC] D7_APC_3: 0x0
9688 13:18:14.682074 INFO: [APUAPC] D8_APC_0: 0xffffffff
9689 13:18:14.684950 INFO: [APUAPC] D8_APC_1: 0xffffffff
9690 13:18:14.688212 INFO: [APUAPC] D8_APC_2: 0x3fffff
9691 13:18:14.691823 INFO: [APUAPC] D8_APC_3: 0x0
9692 13:18:14.694960 INFO: [APUAPC] D9_APC_0: 0xffffffff
9693 13:18:14.698572 INFO: [APUAPC] D9_APC_1: 0xffffffff
9694 13:18:14.701409 INFO: [APUAPC] D9_APC_2: 0x3fffff
9695 13:18:14.704712 INFO: [APUAPC] D9_APC_3: 0x0
9696 13:18:14.707887 INFO: [APUAPC] D10_APC_0: 0xffffffff
9697 13:18:14.711605 INFO: [APUAPC] D10_APC_1: 0xffffffff
9698 13:18:14.714891 INFO: [APUAPC] D10_APC_2: 0x3fffff
9699 13:18:14.718072 INFO: [APUAPC] D10_APC_3: 0x0
9700 13:18:14.721456 INFO: [APUAPC] D11_APC_0: 0xffffffff
9701 13:18:14.724677 INFO: [APUAPC] D11_APC_1: 0xffffffff
9702 13:18:14.728385 INFO: [APUAPC] D11_APC_2: 0x3fffff
9703 13:18:14.731184 INFO: [APUAPC] D11_APC_3: 0x0
9704 13:18:14.734346 INFO: [APUAPC] D12_APC_0: 0xffffffff
9705 13:18:14.737570 INFO: [APUAPC] D12_APC_1: 0xffffffff
9706 13:18:14.741263 INFO: [APUAPC] D12_APC_2: 0x3fffff
9707 13:18:14.745008 INFO: [APUAPC] D12_APC_3: 0x0
9708 13:18:14.747838 INFO: [APUAPC] D13_APC_0: 0xffffffff
9709 13:18:14.750806 INFO: [APUAPC] D13_APC_1: 0xffffffff
9710 13:18:14.754106 INFO: [APUAPC] D13_APC_2: 0x3fffff
9711 13:18:14.758165 INFO: [APUAPC] D13_APC_3: 0x0
9712 13:18:14.761096 INFO: [APUAPC] D14_APC_0: 0xffffffff
9713 13:18:14.764507 INFO: [APUAPC] D14_APC_1: 0xffffffff
9714 13:18:14.767927 INFO: [APUAPC] D14_APC_2: 0x3fffff
9715 13:18:14.770714 INFO: [APUAPC] D14_APC_3: 0x0
9716 13:18:14.774074 INFO: [APUAPC] D15_APC_0: 0xffffffff
9717 13:18:14.777643 INFO: [APUAPC] D15_APC_1: 0xffffffff
9718 13:18:14.781138 INFO: [APUAPC] D15_APC_2: 0x3fffff
9719 13:18:14.784205 INFO: [APUAPC] D15_APC_3: 0x0
9720 13:18:14.787504 INFO: [APUAPC] APC_CON: 0x4
9721 13:18:14.787575 INFO: [NOCDAPC] D0_APC_0: 0x0
9722 13:18:14.791428 INFO: [NOCDAPC] D0_APC_1: 0x0
9723 13:18:14.794030 INFO: [NOCDAPC] D1_APC_0: 0x0
9724 13:18:14.797945 INFO: [NOCDAPC] D1_APC_1: 0xfff
9725 13:18:14.801162 INFO: [NOCDAPC] D2_APC_0: 0x0
9726 13:18:14.804179 INFO: [NOCDAPC] D2_APC_1: 0xfff
9727 13:18:14.808034 INFO: [NOCDAPC] D3_APC_0: 0x0
9728 13:18:14.810624 INFO: [NOCDAPC] D3_APC_1: 0xfff
9729 13:18:14.813933 INFO: [NOCDAPC] D4_APC_0: 0x0
9730 13:18:14.817001 INFO: [NOCDAPC] D4_APC_1: 0xfff
9731 13:18:14.820822 INFO: [NOCDAPC] D5_APC_0: 0x0
9732 13:18:14.820900 INFO: [NOCDAPC] D5_APC_1: 0xfff
9733 13:18:14.823598 INFO: [NOCDAPC] D6_APC_0: 0x0
9734 13:18:14.827194 INFO: [NOCDAPC] D6_APC_1: 0xfff
9735 13:18:14.830316 INFO: [NOCDAPC] D7_APC_0: 0x0
9736 13:18:14.833502 INFO: [NOCDAPC] D7_APC_1: 0xfff
9737 13:18:14.837153 INFO: [NOCDAPC] D8_APC_0: 0x0
9738 13:18:14.840817 INFO: [NOCDAPC] D8_APC_1: 0xfff
9739 13:18:14.843630 INFO: [NOCDAPC] D9_APC_0: 0x0
9740 13:18:14.847722 INFO: [NOCDAPC] D9_APC_1: 0xfff
9741 13:18:14.850240 INFO: [NOCDAPC] D10_APC_0: 0x0
9742 13:18:14.853738 INFO: [NOCDAPC] D10_APC_1: 0xfff
9743 13:18:14.856973 INFO: [NOCDAPC] D11_APC_0: 0x0
9744 13:18:14.860179 INFO: [NOCDAPC] D11_APC_1: 0xfff
9745 13:18:14.860272 INFO: [NOCDAPC] D12_APC_0: 0x0
9746 13:18:14.863773 INFO: [NOCDAPC] D12_APC_1: 0xfff
9747 13:18:14.866832 INFO: [NOCDAPC] D13_APC_0: 0x0
9748 13:18:14.870070 INFO: [NOCDAPC] D13_APC_1: 0xfff
9749 13:18:14.873870 INFO: [NOCDAPC] D14_APC_0: 0x0
9750 13:18:14.876752 INFO: [NOCDAPC] D14_APC_1: 0xfff
9751 13:18:14.879866 INFO: [NOCDAPC] D15_APC_0: 0x0
9752 13:18:14.883471 INFO: [NOCDAPC] D15_APC_1: 0xfff
9753 13:18:14.886839 INFO: [NOCDAPC] APC_CON: 0x4
9754 13:18:14.889731 INFO: [APUAPC] set_apusys_apc done
9755 13:18:14.893417 INFO: [DEVAPC] devapc_init done
9756 13:18:14.896548 INFO: GICv3 without legacy support detected.
9757 13:18:14.899871 INFO: ARM GICv3 driver initialized in EL3
9758 13:18:14.902946 INFO: Maximum SPI INTID supported: 639
9759 13:18:14.909881 INFO: BL31: Initializing runtime services
9760 13:18:14.912939 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9761 13:18:14.916498 INFO: SPM: enable CPC mode
9762 13:18:14.922961 INFO: mcdi ready for mcusys-off-idle and system suspend
9763 13:18:14.927033 INFO: BL31: Preparing for EL3 exit to normal world
9764 13:18:14.929825 INFO: Entry point address = 0x80000000
9765 13:18:14.932913 INFO: SPSR = 0x8
9766 13:18:14.938130
9767 13:18:14.938210
9768 13:18:14.938267
9769 13:18:14.941658 Starting depthcharge on Spherion...
9770 13:18:14.941733
9771 13:18:14.941789 Wipe memory regions:
9772 13:18:14.941844
9773 13:18:14.942475 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
9774 13:18:14.942590 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9775 13:18:14.942681 Setting prompt string to ['asurada:']
9776 13:18:14.942745 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9777 13:18:14.945495 [0x00000040000000, 0x00000054600000)
9778 13:18:15.067026
9779 13:18:15.067196 [0x00000054660000, 0x00000080000000)
9780 13:18:15.328139
9781 13:18:15.328279 [0x000000821a7280, 0x000000ffe64000)
9782 13:18:16.072928
9783 13:18:16.073052 [0x00000100000000, 0x00000140000000)
9784 13:18:16.453903
9785 13:18:16.456924 Initializing XHCI USB controller at 0x11200000.
9786 13:18:17.495241
9787 13:18:17.498159 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9788 13:18:17.498251
9789 13:18:17.498309
9790 13:18:17.498571 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9791 13:18:17.498670 Sending line: 'tftpboot 192.168.201.1 14879033/tftp-deploy-q9ao1fcs/kernel/image.itb 14879033/tftp-deploy-q9ao1fcs/kernel/cmdline '
9793 13:18:17.599176 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9794 13:18:17.599256 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:19)
9795 13:18:17.604071 asurada: tftpboot 192.168.201.1 14879033/tftp-deploy-q9ao1fcs/kernel/image.ittp-deploy-q9ao1fcs/kernel/cmdline
9796 13:18:17.604149
9797 13:18:17.604207 Waiting for link
9798 13:18:17.761460
9799 13:18:17.761573 R8152: Initializing
9800 13:18:17.761634
9801 13:18:17.764704 Version 9 (ocp_data = 6010)
9802 13:18:17.764778
9803 13:18:17.767721 R8152: Done initializing
9804 13:18:17.767790
9805 13:18:17.767844 Adding net device
9806 13:18:19.657801
9807 13:18:19.657930 done.
9808 13:18:19.658021
9809 13:18:19.658138 MAC: 00:e0:4c:68:03:bd
9810 13:18:19.658251
9811 13:18:19.660359 Sending DHCP discover... done.
9812 13:18:19.660450
9813 13:18:19.663500 Waiting for reply... done.
9814 13:18:19.663594
9815 13:18:19.666587 Sending DHCP request... done.
9816 13:18:19.666683
9817 13:18:19.678693 Waiting for reply... done.
9818 13:18:19.678795
9819 13:18:19.678880 My ip is 192.168.201.16
9820 13:18:19.678960
9821 13:18:19.682222 The DHCP server ip is 192.168.201.1
9822 13:18:19.682311
9823 13:18:19.689105 TFTP server IP predefined by user: 192.168.201.1
9824 13:18:19.689203
9825 13:18:19.695537 Bootfile predefined by user: 14879033/tftp-deploy-q9ao1fcs/kernel/image.itb
9826 13:18:19.695633
9827 13:18:19.698206 Sending tftp read request... done.
9828 13:18:19.698299
9829 13:18:19.702431 Waiting for the transfer...
9830 13:18:19.702523
9831 13:18:19.962840 00000000 ################################################################
9832 13:18:19.963002
9833 13:18:20.219196 00080000 ################################################################
9834 13:18:20.219324
9835 13:18:20.481832 00100000 ################################################################
9836 13:18:20.481962
9837 13:18:20.738702 00180000 ################################################################
9838 13:18:20.738834
9839 13:18:21.000140 00200000 ################################################################
9840 13:18:21.000269
9841 13:18:21.269061 00280000 ################################################################
9842 13:18:21.269211
9843 13:18:21.536089 00300000 ################################################################
9844 13:18:21.536215
9845 13:18:21.800233 00380000 ################################################################
9846 13:18:21.800393
9847 13:18:22.059251 00400000 ################################################################
9848 13:18:22.059374
9849 13:18:22.323005 00480000 ################################################################
9850 13:18:22.323170
9851 13:18:22.588077 00500000 ################################################################
9852 13:18:22.588219
9853 13:18:22.857517 00580000 ################################################################
9854 13:18:22.857630
9855 13:18:23.127097 00600000 ################################################################
9856 13:18:23.127210
9857 13:18:23.382603 00680000 ################################################################
9858 13:18:23.382744
9859 13:18:23.643763 00700000 ################################################################
9860 13:18:23.643899
9861 13:18:23.907738 00780000 ################################################################
9862 13:18:23.907851
9863 13:18:24.177798 00800000 ################################################################
9864 13:18:24.177911
9865 13:18:24.447329 00880000 ################################################################
9866 13:18:24.447443
9867 13:18:24.733129 00900000 ################################################################
9868 13:18:24.733265
9869 13:18:25.015360 00980000 ################################################################
9870 13:18:25.015501
9871 13:18:25.288998 00a00000 ################################################################
9872 13:18:25.289128
9873 13:18:25.579455 00a80000 ################################################################
9874 13:18:25.579568
9875 13:18:25.833538 00b00000 ################################################################
9876 13:18:25.833661
9877 13:18:26.097849 00b80000 ################################################################
9878 13:18:26.097962
9879 13:18:26.358109 00c00000 ################################################################
9880 13:18:26.358222
9881 13:18:26.646260 00c80000 ################################################################
9882 13:18:26.646375
9883 13:18:26.926000 00d00000 ################################################################
9884 13:18:26.926115
9885 13:18:27.183476 00d80000 ################################################################
9886 13:18:27.183592
9887 13:18:27.448942 00e00000 ################################################################
9888 13:18:27.449058
9889 13:18:27.728811 00e80000 ################################################################
9890 13:18:27.728952
9891 13:18:28.005674 00f00000 ################################################################
9892 13:18:28.005790
9893 13:18:28.278186 00f80000 ################################################################
9894 13:18:28.278302
9895 13:18:28.562052 01000000 ################################################################
9896 13:18:28.562258
9897 13:18:28.816762 01080000 ################################################################
9898 13:18:28.816870
9899 13:18:29.067767 01100000 ################################################################
9900 13:18:29.067888
9901 13:18:29.319750 01180000 ################################################################
9902 13:18:29.319865
9903 13:18:29.592990 01200000 ################################################################
9904 13:18:29.593102
9905 13:18:29.869085 01280000 ################################################################
9906 13:18:29.869223
9907 13:18:30.154726 01300000 ################################################################
9908 13:18:30.154836
9909 13:18:30.417909 01380000 ################################################################
9910 13:18:30.418024
9911 13:18:30.685167 01400000 ################################################################
9912 13:18:30.685298
9913 13:18:30.950589 01480000 ################################################################
9914 13:18:30.950703
9915 13:18:31.216784 01500000 ################################################################
9916 13:18:31.216896
9917 13:18:31.482034 01580000 ################################################################
9918 13:18:31.482148
9919 13:18:31.745878 01600000 ################################################################
9920 13:18:31.745990
9921 13:18:32.042723 01680000 ################################################################
9922 13:18:32.042839
9923 13:18:32.334819 01700000 ################################################################
9924 13:18:32.334931
9925 13:18:32.633493 01780000 ################################################################
9926 13:18:32.633609
9927 13:18:32.919750 01800000 ################################################################
9928 13:18:32.919868
9929 13:18:33.183374 01880000 ################################################################
9930 13:18:33.183488
9931 13:18:33.441018 01900000 ################################################################
9932 13:18:33.441132
9933 13:18:33.706009 01980000 ################################################################
9934 13:18:33.706123
9935 13:18:33.966655 01a00000 ################################################################
9936 13:18:33.966769
9937 13:18:34.250805 01a80000 ################################################################
9938 13:18:34.250919
9939 13:18:34.529043 01b00000 ################################################################
9940 13:18:34.529157
9941 13:18:34.779347 01b80000 ################################################################
9942 13:18:34.779461
9943 13:18:35.038045 01c00000 ################################################################
9944 13:18:35.038156
9945 13:18:35.317606 01c80000 ################################################################
9946 13:18:35.317746
9947 13:18:35.603621 01d00000 ################################################################
9948 13:18:35.603731
9949 13:18:35.890789 01d80000 ################################################################
9950 13:18:35.890901
9951 13:18:36.123236 01e00000 ##################################################### done.
9952 13:18:36.123347
9953 13:18:36.126985 The bootfile was 31883658 bytes long.
9954 13:18:36.127067
9955 13:18:36.130400 Sending tftp read request... done.
9956 13:18:36.130489
9957 13:18:36.130555 Waiting for the transfer...
9958 13:18:36.133562
9959 13:18:36.133648 00000000 # done.
9960 13:18:36.133717
9961 13:18:36.139870 Command line loaded dynamically from TFTP file: 14879033/tftp-deploy-q9ao1fcs/kernel/cmdline
9962 13:18:36.139973
9963 13:18:36.163082 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879033/extract-nfsrootfs-yhmhiiif,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
9964 13:18:36.163270
9965 13:18:36.163406 Loading FIT.
9966 13:18:36.166699
9967 13:18:36.166878 Image ramdisk-1 has 18719904 bytes.
9968 13:18:36.167036
9969 13:18:36.170244 Image fdt-1 has 47258 bytes.
9970 13:18:36.170562
9971 13:18:36.174024 Image kernel-1 has 13114469 bytes.
9972 13:18:36.174253
9973 13:18:36.183680 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9974 13:18:36.184038
9975 13:18:36.200270 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9976 13:18:36.200749
9977 13:18:36.206796 Choosing best match conf-1 for compat google,spherion-rev3.
9978 13:18:36.207184
9979 13:18:36.214656 Connected to device vid:did:rid of 1ae0:0028:00
9980 13:18:36.222273
9981 13:18:36.226047 tpm_get_response: command 0x17b, return code 0x0
9982 13:18:36.226461
9983 13:18:36.229221 ec_init: CrosEC protocol v3 supported (256, 248)
9984 13:18:36.233287
9985 13:18:36.236755 tpm_cleanup: add release locality here.
9986 13:18:36.237353
9987 13:18:36.237670 Shutting down all USB controllers.
9988 13:18:36.237986
9989 13:18:36.239843 Removing current net device
9990 13:18:36.240220
9991 13:18:36.246322 Exiting depthcharge with code 4 at timestamp: 49548927
9992 13:18:36.246721
9993 13:18:36.249848 LZMA decompressing kernel-1 to 0x821a6718
9994 13:18:36.250282
9995 13:18:36.253077 LZMA decompressing kernel-1 to 0x40000000
9996 13:18:37.868114
9997 13:18:37.868561 jumping to kernel
9998 13:18:37.870201 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
9999 13:18:37.870679 start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10000 13:18:37.871053 Setting prompt string to ['Linux version [0-9]']
10001 13:18:37.871361 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10002 13:18:37.871708 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10003 13:18:37.917616
10004 13:18:37.920916 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10005 13:18:37.924630 start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10006 13:18:37.925135 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10007 13:18:37.925544 Setting prompt string to []
10008 13:18:37.925909 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10009 13:18:37.926264 Using line separator: #'\n'#
10010 13:18:37.926546 No login prompt set.
10011 13:18:37.926888 Parsing kernel messages
10012 13:18:37.927166 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10013 13:18:37.927716 [login-action] Waiting for messages, (timeout 00:03:58)
10014 13:18:37.928046 Waiting using forced prompt support (timeout 00:01:59)
10015 13:18:37.944556 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10016 13:18:37.947366 [ 0.000000] random: crng init done
10017 13:18:37.950572 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10018 13:18:37.954144 [ 0.000000] efi: UEFI not found.
10019 13:18:37.963861 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10020 13:18:37.970349 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10021 13:18:37.980343 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10022 13:18:37.990379 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10023 13:18:37.996897 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10024 13:18:38.000422 [ 0.000000] printk: bootconsole [mtk8250] enabled
10025 13:18:38.008298 [ 0.000000] NUMA: No NUMA configuration found
10026 13:18:38.015022 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10027 13:18:38.022141 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10028 13:18:38.022579 [ 0.000000] Zone ranges:
10029 13:18:38.028625 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10030 13:18:38.031814 [ 0.000000] DMA32 empty
10031 13:18:38.038296 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10032 13:18:38.041599 [ 0.000000] Movable zone start for each node
10033 13:18:38.044785 [ 0.000000] Early memory node ranges
10034 13:18:38.051630 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10035 13:18:38.058159 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10036 13:18:38.065006 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10037 13:18:38.071725 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10038 13:18:38.077893 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10039 13:18:38.084676 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10040 13:18:38.115939 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10041 13:18:38.122097 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10042 13:18:38.128305 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10043 13:18:38.132569 [ 0.000000] psci: probing for conduit method from DT.
10044 13:18:38.138718 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10045 13:18:38.141756 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10046 13:18:38.148353 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10047 13:18:38.151789 [ 0.000000] psci: SMC Calling Convention v1.2
10048 13:18:38.158353 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10049 13:18:38.162339 [ 0.000000] Detected VIPT I-cache on CPU0
10050 13:18:38.168853 [ 0.000000] CPU features: detected: GIC system register CPU interface
10051 13:18:38.174928 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10052 13:18:38.181377 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10053 13:18:38.188271 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10054 13:18:38.197997 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10055 13:18:38.205165 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10056 13:18:38.207910 [ 0.000000] alternatives: applying boot alternatives
10057 13:18:38.214405 [ 0.000000] Fallback order for Node 0: 0
10058 13:18:38.221334 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10059 13:18:38.224781 [ 0.000000] Policy zone: Normal
10060 13:18:38.247498 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879033/extract-nfsrootfs-yhmhiiif,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10061 13:18:38.257283 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10062 13:18:38.267694 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10063 13:18:38.274024 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10064 13:18:38.280999 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10065 13:18:38.286990 <6>[ 0.000000] software IO TLB: area num 8.
10066 13:18:38.342282 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10067 13:18:38.424111 <6>[ 0.000000] Memory: 3831368K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 327096K reserved, 32768K cma-reserved)
10068 13:18:38.430189 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10069 13:18:38.436457 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10070 13:18:38.440049 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10071 13:18:38.446504 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10072 13:18:38.453174 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10073 13:18:38.456564 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10074 13:18:38.466351 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10075 13:18:38.473328 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10076 13:18:38.479574 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10077 13:18:38.485989 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10078 13:18:38.489552 <6>[ 0.000000] GICv3: 608 SPIs implemented
10079 13:18:38.493056 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10080 13:18:38.499721 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10081 13:18:38.503265 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10082 13:18:38.509394 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10083 13:18:38.522473 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10084 13:18:38.535698 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10085 13:18:38.542292 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10086 13:18:38.550084 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10087 13:18:38.563633 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10088 13:18:38.569748 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10089 13:18:38.576858 <6>[ 0.009176] Console: colour dummy device 80x25
10090 13:18:38.586986 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10091 13:18:38.593133 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10092 13:18:38.596377 <6>[ 0.029217] LSM: Security Framework initializing
10093 13:18:38.603411 <6>[ 0.034130] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10094 13:18:38.612968 <6>[ 0.041783] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10095 13:18:38.619531 <6>[ 0.051063] cblist_init_generic: Setting adjustable number of callback queues.
10096 13:18:38.626323 <6>[ 0.058503] cblist_init_generic: Setting shift to 3 and lim to 1.
10097 13:18:38.636420 <6>[ 0.064842] cblist_init_generic: Setting adjustable number of callback queues.
10098 13:18:38.642594 <6>[ 0.072268] cblist_init_generic: Setting shift to 3 and lim to 1.
10099 13:18:38.645841 <6>[ 0.078666] rcu: Hierarchical SRCU implementation.
10100 13:18:38.652537 <6>[ 0.083682] rcu: Max phase no-delay instances is 1000.
10101 13:18:38.659289 <6>[ 0.090709] EFI services will not be available.
10102 13:18:38.662358 <6>[ 0.095689] smp: Bringing up secondary CPUs ...
10103 13:18:38.670532 <6>[ 0.100741] Detected VIPT I-cache on CPU1
10104 13:18:38.677273 <6>[ 0.100812] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10105 13:18:38.683921 <6>[ 0.100842] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10106 13:18:38.686657 <6>[ 0.101179] Detected VIPT I-cache on CPU2
10107 13:18:38.696949 <6>[ 0.101234] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10108 13:18:38.703471 <6>[ 0.101250] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10109 13:18:38.707274 <6>[ 0.101513] Detected VIPT I-cache on CPU3
10110 13:18:38.713412 <6>[ 0.101561] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10111 13:18:38.720734 <6>[ 0.101576] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10112 13:18:38.723252 <6>[ 0.101882] CPU features: detected: Spectre-v4
10113 13:18:38.729776 <6>[ 0.101889] CPU features: detected: Spectre-BHB
10114 13:18:38.733367 <6>[ 0.101895] Detected PIPT I-cache on CPU4
10115 13:18:38.739822 <6>[ 0.101954] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10116 13:18:38.746745 <6>[ 0.101971] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10117 13:18:38.753402 <6>[ 0.102266] Detected PIPT I-cache on CPU5
10118 13:18:38.759592 <6>[ 0.102328] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10119 13:18:38.766321 <6>[ 0.102344] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10120 13:18:38.769532 <6>[ 0.102624] Detected PIPT I-cache on CPU6
10121 13:18:38.779430 <6>[ 0.102686] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10122 13:18:38.785825 <6>[ 0.102702] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10123 13:18:38.788972 <6>[ 0.103005] Detected PIPT I-cache on CPU7
10124 13:18:38.795771 <6>[ 0.103070] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10125 13:18:38.802695 <6>[ 0.103085] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10126 13:18:38.806162 <6>[ 0.103133] smp: Brought up 1 node, 8 CPUs
10127 13:18:38.812493 <6>[ 0.244478] SMP: Total of 8 processors activated.
10128 13:18:38.815703 <6>[ 0.249399] CPU features: detected: 32-bit EL0 Support
10129 13:18:38.825827 <6>[ 0.254762] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10130 13:18:38.831981 <6>[ 0.263562] CPU features: detected: Common not Private translations
10131 13:18:38.839083 <6>[ 0.270038] CPU features: detected: CRC32 instructions
10132 13:18:38.842292 <6>[ 0.275390] CPU features: detected: RCpc load-acquire (LDAPR)
10133 13:18:38.849124 <6>[ 0.281387] CPU features: detected: LSE atomic instructions
10134 13:18:38.855454 <6>[ 0.287168] CPU features: detected: Privileged Access Never
10135 13:18:38.862144 <6>[ 0.292947] CPU features: detected: RAS Extension Support
10136 13:18:38.868756 <6>[ 0.298555] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10137 13:18:38.872002 <6>[ 0.305818] CPU: All CPU(s) started at EL2
10138 13:18:38.878953 <6>[ 0.310161] alternatives: applying system-wide alternatives
10139 13:18:38.887435 <6>[ 0.320204] devtmpfs: initialized
10140 13:18:38.902313 <6>[ 0.328457] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10141 13:18:38.909071 <6>[ 0.338417] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10142 13:18:38.915618 <6>[ 0.346655] pinctrl core: initialized pinctrl subsystem
10143 13:18:38.919168 <6>[ 0.353335] DMI not present or invalid.
10144 13:18:38.925593 <6>[ 0.357738] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10145 13:18:38.935528 <6>[ 0.364614] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10146 13:18:38.942058 <6>[ 0.372062] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10147 13:18:38.952229 <6>[ 0.380153] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10148 13:18:38.956425 <6>[ 0.388310] audit: initializing netlink subsys (disabled)
10149 13:18:38.965941 <5>[ 0.394007] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10150 13:18:38.971665 <6>[ 0.394707] thermal_sys: Registered thermal governor 'step_wise'
10151 13:18:38.978493 <6>[ 0.401972] thermal_sys: Registered thermal governor 'power_allocator'
10152 13:18:38.981869 <6>[ 0.408224] cpuidle: using governor menu
10153 13:18:38.988635 <6>[ 0.419176] NET: Registered PF_QIPCRTR protocol family
10154 13:18:38.994572 <6>[ 0.424675] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10155 13:18:39.000808 <6>[ 0.431775] ASID allocator initialised with 32768 entries
10156 13:18:39.004865 <6>[ 0.438337] Serial: AMBA PL011 UART driver
10157 13:18:39.014333 <4>[ 0.447682] Trying to register duplicate clock ID: 134
10158 13:18:39.074882 <6>[ 0.510836] KASLR enabled
10159 13:18:39.088892 <6>[ 0.518549] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10160 13:18:39.095344 <6>[ 0.525561] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10161 13:18:39.102452 <6>[ 0.532051] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10162 13:18:39.108557 <6>[ 0.539057] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10163 13:18:39.115048 <6>[ 0.545545] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10164 13:18:39.121594 <6>[ 0.552551] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10165 13:18:39.128602 <6>[ 0.559037] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10166 13:18:39.134943 <6>[ 0.566043] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10167 13:18:39.138344 <6>[ 0.573542] ACPI: Interpreter disabled.
10168 13:18:39.146989 <6>[ 0.579971] iommu: Default domain type: Translated
10169 13:18:39.153515 <6>[ 0.585082] iommu: DMA domain TLB invalidation policy: strict mode
10170 13:18:39.156923 <5>[ 0.591737] SCSI subsystem initialized
10171 13:18:39.163633 <6>[ 0.595912] usbcore: registered new interface driver usbfs
10172 13:18:39.169978 <6>[ 0.601647] usbcore: registered new interface driver hub
10173 13:18:39.173618 <6>[ 0.607199] usbcore: registered new device driver usb
10174 13:18:39.180327 <6>[ 0.613312] pps_core: LinuxPPS API ver. 1 registered
10175 13:18:39.190666 <6>[ 0.618505] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10176 13:18:39.194028 <6>[ 0.627854] PTP clock support registered
10177 13:18:39.197106 <6>[ 0.632100] EDAC MC: Ver: 3.0.0
10178 13:18:39.204391 <6>[ 0.637246] FPGA manager framework
10179 13:18:39.211248 <6>[ 0.640932] Advanced Linux Sound Architecture Driver Initialized.
10180 13:18:39.214697 <6>[ 0.647730] vgaarb: loaded
10181 13:18:39.221128 <6>[ 0.650853] clocksource: Switched to clocksource arch_sys_counter
10182 13:18:39.224722 <5>[ 0.657295] VFS: Disk quotas dquot_6.6.0
10183 13:18:39.230862 <6>[ 0.661478] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10184 13:18:39.234522 <6>[ 0.668666] pnp: PnP ACPI: disabled
10185 13:18:39.243087 <6>[ 0.675383] NET: Registered PF_INET protocol family
10186 13:18:39.249184 <6>[ 0.680768] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10187 13:18:39.260864 <6>[ 0.690787] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10188 13:18:39.270931 <6>[ 0.699573] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10189 13:18:39.277491 <6>[ 0.707539] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10190 13:18:39.284341 <6>[ 0.715940] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10191 13:18:39.295604 <6>[ 0.724594] TCP: Hash tables configured (established 32768 bind 32768)
10192 13:18:39.301317 <6>[ 0.731457] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10193 13:18:39.308388 <6>[ 0.738478] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10194 13:18:39.314838 <6>[ 0.745997] NET: Registered PF_UNIX/PF_LOCAL protocol family
10195 13:18:39.321044 <6>[ 0.752149] RPC: Registered named UNIX socket transport module.
10196 13:18:39.324818 <6>[ 0.758302] RPC: Registered udp transport module.
10197 13:18:39.331394 <6>[ 0.763235] RPC: Registered tcp transport module.
10198 13:18:39.337352 <6>[ 0.768167] RPC: Registered tcp NFSv4.1 backchannel transport module.
10199 13:18:39.341192 <6>[ 0.774832] PCI: CLS 0 bytes, default 64
10200 13:18:39.344327 <6>[ 0.779176] Unpacking initramfs...
10201 13:18:39.354069 <6>[ 0.783032] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10202 13:18:39.360874 <6>[ 0.791662] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10203 13:18:39.367477 <6>[ 0.800465] kvm [1]: IPA Size Limit: 40 bits
10204 13:18:39.370969 <6>[ 0.804991] kvm [1]: GICv3: no GICV resource entry
10205 13:18:39.377729 <6>[ 0.810011] kvm [1]: disabling GICv2 emulation
10206 13:18:39.383825 <6>[ 0.814698] kvm [1]: GIC system register CPU interface enabled
10207 13:18:39.387315 <6>[ 0.820857] kvm [1]: vgic interrupt IRQ18
10208 13:18:39.393952 <6>[ 0.826949] kvm [1]: VHE mode initialized successfully
10209 13:18:39.400872 <5>[ 0.833494] Initialise system trusted keyrings
10210 13:18:39.407199 <6>[ 0.838313] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10211 13:18:39.415576 <6>[ 0.848266] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10212 13:18:39.421877 <5>[ 0.854655] NFS: Registering the id_resolver key type
10213 13:18:39.425732 <5>[ 0.859951] Key type id_resolver registered
10214 13:18:39.432053 <5>[ 0.864365] Key type id_legacy registered
10215 13:18:39.439176 <6>[ 0.868644] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10216 13:18:39.445540 <6>[ 0.875568] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10217 13:18:39.451723 <6>[ 0.883306] 9p: Installing v9fs 9p2000 file system support
10218 13:18:39.487668 <5>[ 0.920257] Key type asymmetric registered
10219 13:18:39.491428 <5>[ 0.924587] Asymmetric key parser 'x509' registered
10220 13:18:39.501118 <6>[ 0.929733] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10221 13:18:39.504338 <6>[ 0.937349] io scheduler mq-deadline registered
10222 13:18:39.507313 <6>[ 0.942105] io scheduler kyber registered
10223 13:18:39.526654 <6>[ 0.959423] EINJ: ACPI disabled.
10224 13:18:39.559635 <4>[ 0.985798] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10225 13:18:39.569132 <4>[ 0.996425] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10226 13:18:39.584187 <6>[ 1.017359] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10227 13:18:39.592956 <6>[ 1.025321] printk: console [ttyS0] disabled
10228 13:18:39.620045 <6>[ 1.049949] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10229 13:18:39.627062 <6>[ 1.059420] printk: console [ttyS0] enabled
10230 13:18:39.630975 <6>[ 1.059420] printk: console [ttyS0] enabled
10231 13:18:39.637058 <6>[ 1.068314] printk: bootconsole [mtk8250] disabled
10232 13:18:39.640348 <6>[ 1.068314] printk: bootconsole [mtk8250] disabled
10233 13:18:39.646896 <6>[ 1.079417] SuperH (H)SCI(F) driver initialized
10234 13:18:39.650671 <6>[ 1.084683] msm_serial: driver initialized
10235 13:18:39.664080 <6>[ 1.093639] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10236 13:18:39.673885 <6>[ 1.102193] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10237 13:18:39.681158 <6>[ 1.110736] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10238 13:18:39.690472 <6>[ 1.119363] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10239 13:18:39.701070 <6>[ 1.128069] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10240 13:18:39.707613 <6>[ 1.136788] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10241 13:18:39.717270 <6>[ 1.145328] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10242 13:18:39.724281 <6>[ 1.154124] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10243 13:18:39.733715 <6>[ 1.162666] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10244 13:18:39.745881 <6>[ 1.178207] loop: module loaded
10245 13:18:39.752402 <6>[ 1.184131] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10246 13:18:39.775182 <4>[ 1.207551] mtk-pmic-keys: Failed to locate of_node [id: -1]
10247 13:18:39.782099 <6>[ 1.214356] megasas: 07.719.03.00-rc1
10248 13:18:39.791620 <6>[ 1.224021] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10249 13:18:39.798174 <6>[ 1.230250] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10250 13:18:39.814277 <6>[ 1.247076] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10251 13:18:39.871468 <6>[ 1.297163] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10252 13:18:40.141655 <6>[ 1.574012] Freeing initrd memory: 18276K
10253 13:18:40.153295 <6>[ 1.585768] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10254 13:18:40.164257 <6>[ 1.596871] tun: Universal TUN/TAP device driver, 1.6
10255 13:18:40.167626 <6>[ 1.602960] thunder_xcv, ver 1.0
10256 13:18:40.171268 <6>[ 1.606455] thunder_bgx, ver 1.0
10257 13:18:40.174483 <6>[ 1.609956] nicpf, ver 1.0
10258 13:18:40.184804 <6>[ 1.613981] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10259 13:18:40.188021 <6>[ 1.621457] hns3: Copyright (c) 2017 Huawei Corporation.
10260 13:18:40.194728 <6>[ 1.627049] hclge is initializing
10261 13:18:40.198512 <6>[ 1.630626] e1000: Intel(R) PRO/1000 Network Driver
10262 13:18:40.204669 <6>[ 1.635755] e1000: Copyright (c) 1999-2006 Intel Corporation.
10263 13:18:40.208018 <6>[ 1.641770] e1000e: Intel(R) PRO/1000 Network Driver
10264 13:18:40.214360 <6>[ 1.646985] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10265 13:18:40.221494 <6>[ 1.653172] igb: Intel(R) Gigabit Ethernet Network Driver
10266 13:18:40.227785 <6>[ 1.658822] igb: Copyright (c) 2007-2014 Intel Corporation.
10267 13:18:40.234622 <6>[ 1.664659] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10268 13:18:40.241039 <6>[ 1.671177] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10269 13:18:40.243898 <6>[ 1.677639] sky2: driver version 1.30
10270 13:18:40.250880 <6>[ 1.682574] usbcore: registered new device driver r8152-cfgselector
10271 13:18:40.257576 <6>[ 1.689113] usbcore: registered new interface driver r8152
10272 13:18:40.264141 <6>[ 1.694934] VFIO - User Level meta-driver version: 0.3
10273 13:18:40.270607 <6>[ 1.703205] usbcore: registered new interface driver usb-storage
10274 13:18:40.278124 <6>[ 1.709652] usbcore: registered new device driver onboard-usb-hub
10275 13:18:40.286001 <6>[ 1.718814] mt6397-rtc mt6359-rtc: registered as rtc0
10276 13:18:40.296173 <6>[ 1.724281] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:18:39 UTC (1721308719)
10277 13:18:40.299597 <6>[ 1.733855] i2c_dev: i2c /dev entries driver
10278 13:18:40.313324 <4>[ 1.745945] cpu cpu0: supply cpu not found, using dummy regulator
10279 13:18:40.320063 <4>[ 1.752376] cpu cpu1: supply cpu not found, using dummy regulator
10280 13:18:40.326925 <4>[ 1.758779] cpu cpu2: supply cpu not found, using dummy regulator
10281 13:18:40.333017 <4>[ 1.765181] cpu cpu3: supply cpu not found, using dummy regulator
10282 13:18:40.340203 <4>[ 1.771596] cpu cpu4: supply cpu not found, using dummy regulator
10283 13:18:40.346576 <4>[ 1.777994] cpu cpu5: supply cpu not found, using dummy regulator
10284 13:18:40.354137 <4>[ 1.784391] cpu cpu6: supply cpu not found, using dummy regulator
10285 13:18:40.359952 <4>[ 1.790784] cpu cpu7: supply cpu not found, using dummy regulator
10286 13:18:40.378569 <6>[ 1.811408] cpu cpu0: EM: created perf domain
10287 13:18:40.382591 <6>[ 1.816315] cpu cpu4: EM: created perf domain
10288 13:18:40.389216 <6>[ 1.821864] sdhci: Secure Digital Host Controller Interface driver
10289 13:18:40.395998 <6>[ 1.828297] sdhci: Copyright(c) Pierre Ossman
10290 13:18:40.402253 <6>[ 1.833213] Synopsys Designware Multimedia Card Interface Driver
10291 13:18:40.409066 <6>[ 1.839818] sdhci-pltfm: SDHCI platform and OF driver helper
10292 13:18:40.412505 <6>[ 1.839926] mmc0: CQHCI version 5.10
10293 13:18:40.418816 <6>[ 1.850057] ledtrig-cpu: registered to indicate activity on CPUs
10294 13:18:40.425788 <6>[ 1.857147] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10295 13:18:40.432195 <6>[ 1.864170] usbcore: registered new interface driver usbhid
10296 13:18:40.435615 <6>[ 1.869991] usbhid: USB HID core driver
10297 13:18:40.442475 <6>[ 1.874156] spi_master spi0: will run message pump with realtime priority
10298 13:18:40.489132 <6>[ 1.914285] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10299 13:18:40.507277 <6>[ 1.930464] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10300 13:18:40.511144 <6>[ 1.940187] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15c14
10301 13:18:40.519891 <6>[ 1.951858] cros-ec-spi spi0.0: Chrome EC device registered
10302 13:18:40.526122 <6>[ 1.957877] mmc0: Command Queue Engine enabled
10303 13:18:40.532897 <6>[ 1.962636] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10304 13:18:40.535985 <6>[ 1.970338] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10305 13:18:40.549322 <6>[ 1.981629] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10306 13:18:40.558833 <6>[ 1.985600] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10307 13:18:40.565772 <6>[ 1.989014] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10308 13:18:40.568956 <6>[ 1.998047] NET: Registered PF_PACKET protocol family
10309 13:18:40.575482 <6>[ 2.002869] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10310 13:18:40.579067 <6>[ 2.007464] 9pnet: Installing 9P2000 support
10311 13:18:40.585391 <6>[ 2.013294] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10312 13:18:40.592526 <5>[ 2.017151] Key type dns_resolver registered
10313 13:18:40.595417 <6>[ 2.028608] registered taskstats version 1
10314 13:18:40.601818 <5>[ 2.032984] Loading compiled-in X.509 certificates
10315 13:18:40.627877 <4>[ 2.054091] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10316 13:18:40.638400 <4>[ 2.065079] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10317 13:18:40.654168 <6>[ 2.087152] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10318 13:18:40.661271 <6>[ 2.094037] xhci-mtk 11200000.usb: xHCI Host Controller
10319 13:18:40.668022 <6>[ 2.099614] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10320 13:18:40.678267 <6>[ 2.107493] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10321 13:18:40.684774 <6>[ 2.116926] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10322 13:18:40.691691 <6>[ 2.123080] xhci-mtk 11200000.usb: xHCI Host Controller
10323 13:18:40.697992 <6>[ 2.128574] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10324 13:18:40.704591 <6>[ 2.136234] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10325 13:18:40.711294 <6>[ 2.144032] hub 1-0:1.0: USB hub found
10326 13:18:40.714684 <6>[ 2.148053] hub 1-0:1.0: 1 port detected
10327 13:18:40.724744 <6>[ 2.152323] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10328 13:18:40.727906 <6>[ 2.161028] hub 2-0:1.0: USB hub found
10329 13:18:40.731133 <6>[ 2.165046] hub 2-0:1.0: 1 port detected
10330 13:18:40.739072 <6>[ 2.171901] mtk-msdc 11f70000.mmc: Got CD GPIO
10331 13:18:40.757361 <6>[ 2.186601] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10332 13:18:40.767258 <6>[ 2.194990] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10333 13:18:40.773761 <6>[ 2.203330] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10334 13:18:40.783688 <6>[ 2.211668] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10335 13:18:40.789976 <6>[ 2.220006] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10336 13:18:40.800150 <6>[ 2.228345] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10337 13:18:40.806720 <6>[ 2.236685] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10338 13:18:40.816760 <6>[ 2.245024] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10339 13:18:40.824167 <6>[ 2.253363] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10340 13:18:40.834023 <6>[ 2.261702] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10341 13:18:40.840251 <6>[ 2.270039] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10342 13:18:40.850247 <6>[ 2.278387] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10343 13:18:40.856951 <6>[ 2.286727] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10344 13:18:40.866744 <6>[ 2.295065] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10345 13:18:40.873878 <6>[ 2.303403] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10346 13:18:40.880467 <6>[ 2.312106] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10347 13:18:40.887174 <6>[ 2.319232] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10348 13:18:40.893451 <6>[ 2.326015] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10349 13:18:40.903315 <6>[ 2.332764] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10350 13:18:40.909979 <6>[ 2.339706] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10351 13:18:40.916577 <6>[ 2.346552] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10352 13:18:40.926206 <6>[ 2.355683] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10353 13:18:40.936093 <6>[ 2.364803] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10354 13:18:40.946528 <6>[ 2.374099] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10355 13:18:40.956203 <6>[ 2.383566] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10356 13:18:40.966289 <6>[ 2.393036] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10357 13:18:40.973135 <6>[ 2.402155] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10358 13:18:40.982702 <6>[ 2.411621] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10359 13:18:40.992357 <6>[ 2.420742] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10360 13:18:41.002407 <6>[ 2.430040] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10361 13:18:41.012229 <6>[ 2.440201] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10362 13:18:41.023209 <6>[ 2.452230] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10363 13:18:41.029629 <6>[ 2.462717] Trying to probe devices needed for running init ...
10364 13:18:41.040124 <3>[ 2.469804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10365 13:18:41.146091 <6>[ 2.575153] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10366 13:18:41.300195 <6>[ 2.733200] hub 1-1:1.0: USB hub found
10367 13:18:41.303811 <6>[ 2.737729] hub 1-1:1.0: 4 ports detected
10368 13:18:41.313187 <6>[ 2.746190] hub 1-1:1.0: USB hub found
10369 13:18:41.316824 <6>[ 2.750451] hub 1-1:1.0: 4 ports detected
10370 13:18:41.426106 <6>[ 2.855524] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10371 13:18:41.452204 <6>[ 2.885078] hub 2-1:1.0: USB hub found
10372 13:18:41.455475 <6>[ 2.889593] hub 2-1:1.0: 3 ports detected
10373 13:18:41.467057 <6>[ 2.900042] hub 2-1:1.0: USB hub found
10374 13:18:41.470434 <6>[ 2.904485] hub 2-1:1.0: 3 ports detected
10375 13:18:41.637674 <6>[ 3.067180] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10376 13:18:41.770451 <6>[ 3.203155] hub 1-1.4:1.0: USB hub found
10377 13:18:41.773723 <6>[ 3.207841] hub 1-1.4:1.0: 2 ports detected
10378 13:18:41.788790 <6>[ 3.221323] hub 1-1.4:1.0: USB hub found
10379 13:18:41.791678 <6>[ 3.225945] hub 1-1.4:1.0: 2 ports detected
10380 13:18:41.849865 <6>[ 3.279402] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10381 13:18:41.957945 <6>[ 3.387844] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10382 13:18:41.993753 <4>[ 3.423638] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10383 13:18:42.004211 <4>[ 3.432735] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10384 13:18:42.052504 <6>[ 3.485164] r8152 2-1.3:1.0 eth0: v1.12.13
10385 13:18:42.089407 <6>[ 3.518942] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10386 13:18:42.281302 <6>[ 3.711175] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10387 13:18:43.643625 <6>[ 5.076702] r8152 2-1.3:1.0 eth0: carrier on
10388 13:18:43.682223 <5>[ 5.098910] Sending DHCP requests ., OK
10389 13:18:43.688298 <6>[ 5.119148] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10390 13:18:43.691865 <6>[ 5.127412] IP-Config: Complete:
10391 13:18:43.705458 <6>[ 5.130893] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10392 13:18:43.711470 <6>[ 5.141581] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10393 13:18:43.718588 <6>[ 5.150183] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10394 13:18:43.724785 <6>[ 5.150187] nameserver0=192.168.201.1
10395 13:18:43.728187 <6>[ 5.162191] clk: Disabling unused clocks
10396 13:18:43.731660 <6>[ 5.167075] ALSA device list:
10397 13:18:43.734461 <6>[ 5.170334] No soundcards found.
10398 13:18:43.749187 <6>[ 5.182358] Freeing unused kernel memory: 8512K
10399 13:18:43.752320 <6>[ 5.187206] Run /init as init process
10400 13:18:43.763390 Loading, please wait...
10401 13:18:43.787933 Starting systemd-udevd version 252.22-1~deb12u1
10402 13:18:44.082595 <4>[ 5.512242] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10403 13:18:44.089327 <6>[ 5.512271] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10404 13:18:44.095565 <6>[ 5.518046] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10405 13:18:44.106265 <4>[ 5.527361] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10406 13:18:44.112031 <3>[ 5.541407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10407 13:18:44.119011 <6>[ 5.543448] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10408 13:18:44.125672 <6>[ 5.544604] remoteproc remoteproc0: scp is available
10409 13:18:44.132259 <6>[ 5.544702] remoteproc remoteproc0: powering up scp
10410 13:18:44.138706 <6>[ 5.544708] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10411 13:18:44.145266 <6>[ 5.544730] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10412 13:18:44.152333 <3>[ 5.550636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10413 13:18:44.161760 <6>[ 5.558875] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10414 13:18:44.168635 <6>[ 5.561900] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10415 13:18:44.178357 <6>[ 5.561930] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10416 13:18:44.184803 <6>[ 5.561941] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10417 13:18:44.194706 <3>[ 5.563831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10418 13:18:44.201445 <4>[ 5.569111] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10419 13:18:44.211588 <3>[ 5.583761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10420 13:18:44.217854 <6>[ 5.591618] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10421 13:18:44.228443 <3>[ 5.598976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10422 13:18:44.231396 <6>[ 5.604405] mc: Linux media interface: v0.10
10423 13:18:44.238493 <6>[ 5.606516] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10424 13:18:44.248194 <3>[ 5.615225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 13:18:44.254940 <6>[ 5.625121] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10426 13:18:44.262222 <3>[ 5.632011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 13:18:44.271731 <3>[ 5.632021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10428 13:18:44.278365 <6>[ 5.633736] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10429 13:18:44.285356 <6>[ 5.639659] videodev: Linux video capture interface: v2.00
10430 13:18:44.291523 <6>[ 5.641076] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10431 13:18:44.301680 <3>[ 5.649232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10432 13:18:44.311331 <6>[ 5.654889] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10433 13:18:44.318440 <6>[ 5.657220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10434 13:18:44.328747 <4>[ 5.660963] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10435 13:18:44.332021 <4>[ 5.660963] Fallback method does not support PEC.
10436 13:18:44.341576 <3>[ 5.665331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10437 13:18:44.348181 <6>[ 5.669817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10438 13:18:44.358060 <6>[ 5.669987] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10439 13:18:44.364656 <6>[ 5.670116] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10440 13:18:44.370799 <6>[ 5.670123] remoteproc remoteproc0: remote processor scp is now up
10441 13:18:44.381114 <3>[ 5.675786] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10442 13:18:44.387350 <3>[ 5.677720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10443 13:18:44.394150 <6>[ 5.684272] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10444 13:18:44.400983 <6>[ 5.684279] pci_bus 0000:00: root bus resource [bus 00-ff]
10445 13:18:44.407689 <6>[ 5.684286] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10446 13:18:44.417551 <6>[ 5.684293] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10447 13:18:44.423929 <6>[ 5.684332] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10448 13:18:44.430385 <6>[ 5.684357] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10449 13:18:44.436978 <6>[ 5.684448] pci 0000:00:00.0: supports D1 D2
10450 13:18:44.444350 <6>[ 5.684451] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10451 13:18:44.450646 <6>[ 5.686147] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10452 13:18:44.460276 <3>[ 5.693696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10453 13:18:44.467341 <3>[ 5.693731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10454 13:18:44.477163 <3>[ 5.697935] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10455 13:18:44.483403 <6>[ 5.701911] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10456 13:18:44.490159 <3>[ 5.709869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10457 13:18:44.500191 <3>[ 5.709872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10458 13:18:44.506840 <3>[ 5.709874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10459 13:18:44.513156 <6>[ 5.717548] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10460 13:18:44.522884 <6>[ 5.719790] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10461 13:18:44.533131 <6>[ 5.720163] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10462 13:18:44.540266 <3>[ 5.723250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10463 13:18:44.550070 <3>[ 5.723284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10464 13:18:44.556127 <6>[ 5.731107] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10465 13:18:44.566647 <6>[ 5.740795] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10466 13:18:44.573134 <6>[ 5.748789] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10467 13:18:44.579811 <6>[ 5.760320] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10468 13:18:44.586717 <6>[ 5.770580] pci 0000:01:00.0: supports D1 D2
10469 13:18:44.589559 <6>[ 5.771016] Bluetooth: Core ver 2.22
10470 13:18:44.595833 <6>[ 5.771105] NET: Registered PF_BLUETOOTH protocol family
10471 13:18:44.602376 <6>[ 5.771113] Bluetooth: HCI device and connection manager initialized
10472 13:18:44.606057 <6>[ 5.771168] Bluetooth: HCI socket layer initialized
10473 13:18:44.612425 <6>[ 5.771186] Bluetooth: L2CAP socket layer initialized
10474 13:18:44.615445 <6>[ 5.771203] Bluetooth: SCO socket layer initialized
10475 13:18:44.622544 <6>[ 5.789002] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10476 13:18:44.629276 <6>[ 5.795460] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10477 13:18:44.641848 <6>[ 5.804410] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10478 13:18:44.648550 <6>[ 5.810392] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10479 13:18:44.655020 <6>[ 5.818443] usbcore: registered new interface driver uvcvideo
10480 13:18:44.661594 <6>[ 5.826387] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10481 13:18:44.668219 <6>[ 5.834003] usbcore: registered new interface driver btusb
10482 13:18:44.678509 <4>[ 5.834494] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10483 13:18:44.685375 <3>[ 5.834499] Bluetooth: hci0: Failed to load firmware file (-2)
10484 13:18:44.691502 <3>[ 5.834501] Bluetooth: hci0: Failed to set up firmware (-2)
10485 13:18:44.702047 <4>[ 5.834503] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10486 13:18:44.708112 <6>[ 5.838983] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10487 13:18:44.717886 <6>[ 6.147337] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10488 13:18:44.725028 <6>[ 6.155374] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10489 13:18:44.735065 <6>[ 6.163378] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10490 13:18:44.741560 <6>[ 6.171380] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10491 13:18:44.748507 <6>[ 6.179380] pci 0000:00:00.0: PCI bridge to [bus 01]
10492 13:18:44.754533 <6>[ 6.184596] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10493 13:18:44.761207 <6>[ 6.192714] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10494 13:18:44.767667 <6>[ 6.199475] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10495 13:18:44.774055 <6>[ 6.206129] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10496 13:18:44.795376 <5>[ 6.225560] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10497 13:18:44.820596 <5>[ 6.250545] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10498 13:18:44.827500 <5>[ 6.257955] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10499 13:18:44.837166 <4>[ 6.266453] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10500 13:18:44.843569 <6>[ 6.275367] cfg80211: failed to load regulatory.db
10501 13:18:44.903572 <6>[ 6.333447] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10502 13:18:44.910130 <6>[ 6.341008] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10503 13:18:44.934631 <6>[ 6.368045] mt7921e 0000:01:00.0: ASIC revision: 79610010
10504 13:18:45.040156 <6>[ 6.469086] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10505 13:18:45.042318 <6>[ 6.469086]
10506 13:18:45.052846 Begin: Loading essential drivers ... done.
10507 13:18:45.055912 Begin: Running /scripts/init-premount ... done.
10508 13:18:45.062593 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10509 13:18:45.072362 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10510 13:18:45.075643 Device /sys/class/net/eth0 found
10511 13:18:45.076081 done.
10512 13:18:45.082177 Begin: Waiting up to 180 secs for any network device to become available ... done.
10513 13:18:45.138104 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10514 13:18:45.145659 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10515 13:18:45.151148 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10516 13:18:45.157754 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10517 13:18:45.164562 host : mt8192-asurada-spherion-r0-cbg-4
10518 13:18:45.171125 domain : lava-rack
10519 13:18:45.174269 rootserver: 192.168.201.1 rootpath:
10520 13:18:45.177452 filename :
10521 13:18:45.220959 done.
10522 13:18:45.228863 Begin: Running /scripts/nfs-bottom ... done.
10523 13:18:45.247216 Begin: Running /scripts/init-bottom ... done.
10524 13:18:45.310181 <6>[ 6.740187] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10525 13:18:46.614535 <6>[ 8.047862] NET: Registered PF_INET6 protocol family
10526 13:18:46.621618 <6>[ 8.055286] Segment Routing with IPv6
10527 13:18:46.625133 <6>[ 8.059276] In-situ OAM (IOAM) with IPv6
10528 13:18:46.789316 <30>[ 8.196152] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10529 13:18:46.796198 <30>[ 8.229302] systemd[1]: Detected architecture arm64.
10530 13:18:46.804494
10531 13:18:46.808117 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10532 13:18:46.808633
10533 13:18:46.831169 <30>[ 8.264741] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10534 13:18:47.935085 <30>[ 9.365284] systemd[1]: Queued start job for default target graphical.target.
10535 13:18:47.971258 <30>[ 9.401244] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10536 13:18:47.977710 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10537 13:18:47.999346 <30>[ 9.429263] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10538 13:18:48.008839 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10539 13:18:48.026754 <30>[ 9.457202] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10540 13:18:48.036903 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10541 13:18:48.055281 <30>[ 9.485577] systemd[1]: Created slice user.slice - User and Session Slice.
10542 13:18:48.062028 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10543 13:18:48.085203 <30>[ 9.512142] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10544 13:18:48.094882 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10545 13:18:48.117598 <30>[ 9.544052] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10546 13:18:48.123863 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10547 13:18:48.150754 <30>[ 9.571392] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10548 13:18:48.160897 <30>[ 9.591216] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10549 13:18:48.167536 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10550 13:18:48.184661 <30>[ 9.615204] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10551 13:18:48.191881 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10552 13:18:48.209379 <30>[ 9.639251] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10553 13:18:48.219151 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10554 13:18:48.234439 <30>[ 9.667731] systemd[1]: Reached target paths.target - Path Units.
10555 13:18:48.244237 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10556 13:18:48.261333 <30>[ 9.691618] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10557 13:18:48.267977 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10558 13:18:48.281556 <30>[ 9.715168] systemd[1]: Reached target slices.target - Slice Units.
10559 13:18:48.292192 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10560 13:18:48.306034 <30>[ 9.739684] systemd[1]: Reached target swap.target - Swaps.
10561 13:18:48.313165 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10562 13:18:48.333299 <30>[ 9.763693] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10563 13:18:48.343288 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10564 13:18:48.362228 <30>[ 9.792189] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10565 13:18:48.371616 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10566 13:18:48.391688 <30>[ 9.822048] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10567 13:18:48.401733 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10568 13:18:48.418572 <30>[ 9.848742] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10569 13:18:48.428256 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10570 13:18:48.446080 <30>[ 9.876544] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10571 13:18:48.452515 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10572 13:18:48.474562 <30>[ 9.905092] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10573 13:18:48.484636 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10574 13:18:48.505516 <30>[ 9.935424] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10575 13:18:48.515415 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10576 13:18:48.534057 <30>[ 9.963781] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10577 13:18:48.543190 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10578 13:18:48.597059 <30>[ 10.027379] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10579 13:18:48.603346 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10580 13:18:48.625634 <30>[ 10.056363] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10581 13:18:48.632202 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10582 13:18:48.658055 <30>[ 10.088533] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10583 13:18:48.664248 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10584 13:18:48.691953 <30>[ 10.115815] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10585 13:18:48.707433 <30>[ 10.137933] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10586 13:18:48.717492 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10587 13:18:48.736783 <30>[ 10.166899] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10588 13:18:48.742700 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10589 13:18:48.770911 <30>[ 10.201181] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10590 13:18:48.777396 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10591 13:18:48.800809 <30>[ 10.231252] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10592 13:18:48.806840 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10593 13:18:48.817515 <6>[ 10.247913] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10594 13:18:48.830472 <30>[ 10.261035] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10595 13:18:48.840225 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10596 13:18:48.861319 <30>[ 10.291768] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10597 13:18:48.868203 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10598 13:18:48.895743 <30>[ 10.325636] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10599 13:18:48.901977 Startin<6>[ 10.334586] fuse: init (API version 7.37)
10600 13:18:48.908411 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10601 13:18:48.969406 <30>[ 10.399841] systemd[1]: Starting systemd-journald.service - Journal Service...
10602 13:18:48.976094 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10603 13:18:49.007459 <30>[ 10.437409] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10604 13:18:49.013390 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10605 13:18:49.040536 <30>[ 10.467695] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10606 13:18:49.047058 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10607 13:18:49.069782 <30>[ 10.499690] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10608 13:18:49.079337 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10609 13:18:49.145578 <30>[ 10.576092] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10610 13:18:49.152435 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10611 13:18:49.163667 <3>[ 10.594264] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10612 13:18:49.185422 <30>[ 10.616278] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10613 13:18:49.192797 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10614 13:18:49.202563 <3>[ 10.631915] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10615 13:18:49.213290 <30>[ 10.644004] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10616 13:18:49.223450 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10617 13:18:49.241440 <30>[ 10.671527] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10618 13:18:49.251092 <3>[ 10.672296] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10619 13:18:49.257588 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10620 13:18:49.277760 <3>[ 10.708049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10621 13:18:49.287759 <30>[ 10.718256] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10622 13:18:49.297848 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10623 13:18:49.309545 <3>[ 10.740123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 13:18:49.320173 <30>[ 10.750271] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10625 13:18:49.326437 <30>[ 10.758449] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10626 13:18:49.343676 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 10.771551] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 13:18:49.346962 Load Kernel Module configfs.
10628 13:18:49.366506 <30>[ 10.796188] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10629 13:18:49.373055 <30>[ 10.804299] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10630 13:18:49.382648 <3>[ 10.804861] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 13:18:49.392356 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10632 13:18:49.410940 <30>[ 10.841339] systemd[1]: modprobe@drm.service: Deactivated successfully.
10633 13:18:49.418203 <3>[ 10.846039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 13:18:49.424435 <30>[ 10.848864] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10635 13:18:49.434732 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10636 13:18:49.450734 <3>[ 10.881054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10637 13:18:49.461943 <30>[ 10.892144] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10638 13:18:49.472472 <30>[ 10.900715] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10639 13:18:49.482471 [[0;32m OK [0m] Finished [0<3>[ 10.912372] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 13:18:49.489071 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10641 13:18:49.506406 <30>[ 10.936328] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10642 13:18:49.512990 <30>[ 10.944498] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10643 13:18:49.523319 <3>[ 10.945766] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10644 13:18:49.530121 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10645 13:18:49.547928 <30>[ 10.981093] systemd[1]: modprobe@loop.service: Deactivated successfully.
10646 13:18:49.558498 <30>[ 10.988654] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10647 13:18:49.565600 <3>[ 10.994732] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10648 13:18:49.583367 <4>[ 11.005277] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10649 13:18:49.589384 <3>[ 11.005281] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10650 13:18:49.599659 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10651 13:18:49.619081 <30>[ 11.049643] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10652 13:18:49.626757 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10653 13:18:49.648964 <30>[ 11.079611] systemd[1]: Started systemd-journald.service - Journal Service.
10654 13:18:49.655623 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10655 13:18:49.677611 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10656 13:18:49.698283 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10657 13:18:49.718648 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10658 13:18:49.740008 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10659 13:18:49.793265 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10660 13:18:49.817321 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10661 13:18:49.846773 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10662 13:18:49.901807 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed..<46>[ 11.332669] systemd-journald[307]: Received client request to flush runtime journal.
10663 13:18:49.901922 .
10664 13:18:49.929624 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10665 13:18:49.956921 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10666 13:18:50.251967 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10667 13:18:50.272744 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10668 13:18:50.294012 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10669 13:18:50.314085 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10670 13:18:51.062078 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10671 13:18:51.117562 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10672 13:18:51.375071 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10673 13:18:51.481414 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10674 13:18:51.501203 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10675 13:18:51.520703 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10676 13:18:51.572907 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10677 13:18:51.600909 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10678 13:18:51.766268 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10679 13:18:51.831558 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10680 13:18:51.894266 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10681 13:18:52.130452 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10682 13:18:52.151543 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10683 13:18:52.161377 <6>[ 13.595385] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10684 13:18:52.229916 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10685 13:18:52.361375 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10686 13:18:52.391021 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10687 13:18:52.410322 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10688 13:18:52.453618 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10689 13:18:52.518357 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10690 13:18:52.533593 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10691 13:18:52.552860 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10692 13:18:52.573019 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10693 13:18:52.594504 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10694 13:18:52.617865 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10695 13:18:52.636405 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10696 13:18:52.652210 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10697 13:18:52.677023 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10698 13:18:52.716477 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10699 13:18:52.732738 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10700 13:18:52.750945 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10701 13:18:52.771342 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10702 13:18:52.788056 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10703 13:18:52.806684 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10704 13:18:52.824631 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10705 13:18:52.841104 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10706 13:18:52.886129 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10707 13:18:52.928024 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10708 13:18:52.969756 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10709 13:18:52.997044 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10710 13:18:53.023463 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10711 13:18:53.099261 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10712 13:18:53.117637 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10713 13:18:53.180776 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10714 13:18:53.233420 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10715 13:18:53.256625 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10716 13:18:53.273482 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10717 13:18:53.300701 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10718 13:18:53.404310 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10719 13:18:53.426967 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10720 13:18:53.446413 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10721 13:18:53.491364 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10722 13:18:53.541093 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10723 13:18:53.616358
10724 13:18:53.620111 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10725 13:18:53.620186
10726 13:18:53.622878 debian-bookworm-arm64 login: root (automatic login)
10727 13:18:53.622952
10728 13:18:53.833135 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
10729 13:18:53.833316
10730 13:18:53.839935 The programs included with the Debian GNU/Linux system are free software;
10731 13:18:53.846497 the exact distribution terms for each program are described in the
10732 13:18:53.849989 individual files in /usr/share/doc/*/copyright.
10733 13:18:53.850063
10734 13:18:53.856268 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10735 13:18:53.859474 permitted by applicable law.
10736 13:18:53.944196 Matched prompt #10: / #
10738 13:18:53.944416 Setting prompt string to ['/ #']
10739 13:18:53.944502 end: 2.2.5.1 login-action (duration 00:00:16) [common]
10741 13:18:53.944673 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10742 13:18:53.944754 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
10743 13:18:53.944812 Setting prompt string to ['/ #']
10744 13:18:53.944865 Forcing a shell prompt, looking for ['/ #']
10745 13:18:53.944918 Sending line: ''
10747 13:18:53.995219 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10748 13:18:53.995285 Waiting using forced prompt support (timeout 00:02:30)
10749 13:18:53.999797 / #
10750 13:18:54.000057 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10751 13:18:54.000140 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
10752 13:18:54.000211 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879033/extract-nfsrootfs-yhmhiiif'"
10754 13:18:54.105797 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879033/extract-nfsrootfs-yhmhiiif'
10755 13:18:54.106044 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
10757 13:18:54.211900 / # export NFS_SERVER_IP='192.168.201.1'
10758 13:18:54.212179 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10759 13:18:54.212266 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
10760 13:18:54.212354 end: 2 depthcharge-action (duration 00:01:18) [common]
10761 13:18:54.212441 start: 3 lava-test-retry (timeout 00:30:00) [common]
10762 13:18:54.212529 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10763 13:18:54.212623 Using namespace: common
10764 13:18:54.212715 Sending line: '#'
10766 13:18:54.313325 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10767 13:18:54.318408 / # #
10768 13:18:54.318658 Using /lava-14879033
10769 13:18:54.318719 Sending line: 'export SHELL=/bin/sh'
10771 13:18:54.424309 / # export SHELL=/bin/sh
10772 13:18:54.424556 Sending line: '. /lava-14879033/environment'
10774 13:18:54.529894 / # . /lava-14879033/environment
10775 13:18:54.535726 Sending line: '/lava-14879033/bin/lava-test-runner /lava-14879033/0'
10777 13:18:54.636180 Test shell timeout: 10s (minimum of the action and connection timeout)
10778 13:18:54.641048 / # /lava-14879033/bin/lava-test-runner /lava-14879033/0
10779 13:18:54.837733 + export TESTRUN_ID=0_lc-compliance
10780 13:18:54.844345 + cd /lava-14879033/0/tests/0_lc-compliance
10781 13:18:54.844427 + cat uuid
10782 13:18:54.849220 + UUID=14879033_1.6.2.3.1
10783 13:18:54.849336 + set +x
10784 13:18:54.856194 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14879033_1.6.2.3.1>
10785 13:18:54.856477 Received signal: <STARTRUN> 0_lc-compliance 14879033_1.6.2.3.1
10786 13:18:54.856545 Starting test lava.0_lc-compliance (14879033_1.6.2.3.1)
10787 13:18:54.856618 Skipping test definition patterns.
10788 13:18:54.859536 + /usr/bin/lc-compliance-parser.sh
10789 13:18:56.466177 [0:00:17.779547000] [410] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
10790 13:18:56.469357 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10791 13:18:56.483458 [0:00:17.796655616] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10792 13:18:56.544763 [0:00:17.858165923] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10793 13:18:56.548178 [==========] Running 120 tests from 1 test suite.
10794 13:18:56.605585 [0:00:17.919111846] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10795 13:18:56.609455 [----------] Global test environment set-up.
10796 13:18:56.651085 [----------] 120 tests from CaptureTests/SingleStream
10797 13:18:56.660260 [0:00:17.974330000] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10798 13:18:56.703686 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
10799 13:18:56.751748 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
10800 13:18:56.752012 Received signal: <TESTSET> START CaptureTests/SingleStream
10801 13:18:56.752079 Starting test_set CaptureTests/SingleStream
10802 13:18:56.754863 Camera needs 4 requests, can't test only 1
10803 13:18:56.812630 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10804 13:18:56.865021
10805 13:18:56.916733 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
10806 13:18:56.985368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
10807 13:18:56.985671 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
10809 13:18:56.999304 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
10810 13:18:57.043064 Camera needs 4 requests, can't test only 2
10811 13:18:57.088531 [0:00:18.402401616] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10812 13:18:57.103566 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10813 13:18:57.157066
10814 13:18:57.219962 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (60 ms)
10815 13:18:57.280752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
10816 13:18:57.281050 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
10818 13:18:57.289196 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
10819 13:18:57.325609 Camera needs 4 requests, can't test only 3
10820 13:18:57.383685 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10821 13:18:57.429915
10822 13:18:57.481402 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
10823 13:18:57.544686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
10824 13:18:57.544946 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
10826 13:18:57.558089 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
10827 13:18:57.601365 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (429 ms)
10828 13:18:57.671383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
10829 13:18:57.671648 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
10831 13:18:57.682146 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
10832 13:18:57.773751 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (692 ms)
10833 13:18:57.783600 [0:00:19.096701693] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10834 13:18:57.864172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
10835 13:18:57.864828 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
10837 13:18:57.879531 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
10838 13:18:59.061953 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1289 ms)
10839 13:18:59.071870 [0:00:20.385568847] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10840 13:18:59.126291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
10841 13:18:59.126559 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
10843 13:18:59.138410 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
10844 13:19:00.910813 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1848 ms)
10845 13:19:00.920360 [0:00:22.234366539] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10846 13:19:00.995000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
10847 13:19:00.995267 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
10849 13:19:01.008595 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
10850 13:19:03.667587 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2757 ms)
10851 13:19:03.677424 [0:00:24.991438078] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10852 13:19:03.748705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
10853 13:19:03.749057 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
10855 13:19:03.760276 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
10856 13:19:07.895592 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4229 ms)
10857 13:19:07.905574 [0:00:29.220741309] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10858 13:19:07.965665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
10859 13:19:07.965990 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
10861 13:19:07.978444 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
10862 13:19:14.479581 <6>[ 35.919239] vpu: disabling
10863 13:19:14.481887 <6>[ 35.922302] vproc2: disabling
10864 13:19:14.485814 <6>[ 35.925586] vproc1: disabling
10865 13:19:14.489347 <6>[ 35.928849] vaud18: disabling
10866 13:19:14.495194 <6>[ 35.932255] vsram_others: disabling
10867 13:19:14.499347 <6>[ 35.936126] va09: disabling
10868 13:19:14.501838 <6>[ 35.939232] vsram_md: disabling
10869 13:19:14.504966 [ OK ] Cap<6>[ 35.942719] Vgpu: disabling
10870 13:19:14.508478 tureTests/SingleStream.Capture/Raw_89 (6609 ms)
10871 13:19:14.518431 [0:00:35.829535924] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10872 13:19:14.569672 [0:00:35.885024694] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10873 13:19:14.576102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
10874 13:19:14.576355 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
10876 13:19:14.586831 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
10877 13:19:14.625790 [0:00:35.940982155] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10878 13:19:14.628432 Camera needs 4 requests, can't test only 1
10879 13:19:14.672513 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10880 13:19:14.682451 [0:00:35.995897309] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10881 13:19:14.723833
10882 13:19:14.776888 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
10883 13:19:14.824544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
10884 13:19:14.824817 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
10886 13:19:14.833485 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
10887 13:19:14.873209 Camera needs 4 requests, can't test only 2
10888 13:19:14.918062 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10889 13:19:14.970461
10890 13:19:15.044704 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
10891 13:19:15.106933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
10892 13:19:15.107200 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
10894 13:19:15.120271 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
10895 13:19:15.157527 Camera needs 4 requests, can't test only 3
10896 13:19:15.204210 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10897 13:19:15.253192
10898 13:19:15.314895 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
10899 13:19:15.381945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
10900 13:19:15.382205 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
10902 13:19:15.395440 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
10903 13:19:15.408771 [0:00:36.724662924] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10904 13:19:15.440459 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (727 ms)
10905 13:19:15.500396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
10906 13:19:15.500654 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
10908 13:19:15.511875 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
10909 13:19:16.338508 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (939 ms)
10910 13:19:16.351373 [0:00:37.662852771] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10911 13:19:16.406032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
10912 13:19:16.406311 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
10914 13:19:16.416866 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
10915 13:19:17.623329 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1284 ms)
10916 13:19:17.636890 [0:00:38.947785848] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10917 13:19:17.688273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
10918 13:19:17.688540 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
10920 13:19:17.700198 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
10921 13:19:19.469901 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1846 ms)
10922 13:19:19.482001 [0:00:40.794020232] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10923 13:19:19.532178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
10924 13:19:19.532477 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
10926 13:19:19.541843 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
10927 13:19:22.226271 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2757 ms)
10928 13:19:22.239577 [0:00:43.551411002] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10929 13:19:22.290046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
10930 13:19:22.290316 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
10932 13:19:22.298957 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
10933 13:19:26.451359 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4225 ms)
10934 13:19:26.464427 [0:00:47.776983387] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10935 13:19:26.521254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
10936 13:19:26.521545 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
10938 13:19:26.532982 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
10939 13:19:33.056528 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6605 ms)
10940 13:19:33.069782 [0:00:54.382876387] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10941 13:19:33.117778 [0:00:54.435748156] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10942 13:19:33.124524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
10943 13:19:33.124821 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
10945 13:19:33.132211 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
10946 13:19:33.170212 [0:00:54.488161618] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10947 13:19:33.173534 Camera needs 4 requests, can't test only 1
10948 13:19:33.215029 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10949 13:19:33.225532 [0:00:54.541296926] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10950 13:19:33.263590
10951 13:19:33.317759 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (53 ms)
10952 13:19:33.375413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
10953 13:19:33.375707 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
10955 13:19:33.384009 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
10956 13:19:33.416657 Camera needs 4 requests, can't test only 2
10957 13:19:33.468693 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10958 13:19:33.521927
10959 13:19:33.572578 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (52 ms)
10960 13:19:33.631253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
10961 13:19:33.631552 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
10963 13:19:33.644247 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
10964 13:19:33.688811 Camera needs 4 requests, can't test only 3
10965 13:19:33.747062 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10966 13:19:33.802458
10967 13:19:33.864414 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (52 ms)
10968 13:19:33.923573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
10969 13:19:33.923863 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
10971 13:19:33.932372 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
10972 13:19:33.947738 [0:00:55.265803464] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10973 13:19:33.968983 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (724 ms)
10974 13:19:34.031071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
10975 13:19:34.031390 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
10977 13:19:34.040537 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
10978 13:19:34.878729 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (938 ms)
10979 13:19:34.890947 [0:00:56.204559464] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10980 13:19:34.944771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
10981 13:19:34.945064 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
10983 13:19:34.954684 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
10984 13:19:36.162845 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1284 ms)
10985 13:19:36.176587 [0:00:57.489641618] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10986 13:19:36.227389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
10987 13:19:36.227799 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
10989 13:19:36.237854 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
10990 13:19:38.007970 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1844 ms)
10991 13:19:38.020758 [0:00:59.334321618] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10992 13:19:38.082442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
10993 13:19:38.082745 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
10995 13:19:38.095203 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
10996 13:19:40.763844 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2756 ms)
10997 13:19:40.777458 [0:01:02.091418849] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10998 13:19:40.830988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
10999 13:19:40.831260 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11001 13:19:40.841497 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11002 13:19:44.989502 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4225 ms)
11003 13:19:45.002697 [0:01:06.316885157] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11004 13:19:45.049413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11005 13:19:45.049714 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11007 13:19:45.060912 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11008 13:19:51.593841 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6605 ms)
11009 13:19:51.607403 [0:01:12.922755850] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11010 13:19:51.655851 [0:01:12.976020927] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11011 13:19:51.662609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11012 13:19:51.662944 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11014 13:19:51.669875 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11015 13:19:51.710224 [0:01:13.029979157] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11016 13:19:51.713237 Camera needs 4 requests, can't test only 1
11017 13:19:51.755886 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11018 13:19:51.765160 [0:01:13.084052619] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11019 13:19:51.804965
11020 13:19:51.853723 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
11021 13:19:51.909539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11022 13:19:51.909869 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11024 13:19:51.920307 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11025 13:19:51.954485 Camera needs 4 requests, can't test only 2
11026 13:19:52.000777 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11027 13:19:52.047971
11028 13:19:52.106240 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (53 ms)
11029 13:19:52.168522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11030 13:19:52.168815 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11032 13:19:52.178884 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11033 13:19:52.216398 Camera needs 4 requests, can't test only 3
11034 13:19:52.274747 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11035 13:19:52.328991
11036 13:19:52.381776 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (53 ms)
11037 13:19:52.445133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11038 13:19:52.445473 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11040 13:19:52.456672 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11041 13:19:52.490525 [0:01:13.809902234] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11042 13:19:52.496139 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (725 ms)
11043 13:19:52.556964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11044 13:19:52.557282 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11046 13:19:52.566971 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11047 13:19:53.416926 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (935 ms)
11048 13:19:53.429692 [0:01:14.745424234] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11049 13:19:53.479149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11050 13:19:53.479474 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11052 13:19:53.488183 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11053 13:19:54.701692 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1284 ms)
11054 13:19:54.714363 [0:01:16.030475773] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11055 13:19:54.768947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11056 13:19:54.769298 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11058 13:19:54.779273 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11059 13:19:56.546769 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1845 ms)
11060 13:19:56.559913 [0:01:17.875979773] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11061 13:19:56.609487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11062 13:19:56.609767 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11064 13:19:56.619947 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11065 13:19:59.302443 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2755 ms)
11066 13:19:59.315095 [0:01:20.631641312] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11067 13:19:59.370046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11068 13:19:59.370360 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11070 13:19:59.381032 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11071 13:20:03.527726 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4225 ms)
11072 13:20:03.540669 [0:01:24.857350466] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11073 13:20:03.591927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11074 13:20:03.592238 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11076 13:20:03.601341 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11077 13:20:10.133102 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6605 ms)
11078 13:20:10.146027 [0:01:31.463593543] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11079 13:20:10.194515 [0:01:31.516956466] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11080 13:20:10.198030 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11082 13:20:10.201377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11083 13:20:10.208152 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11084 13:20:10.248314 [0:01:31.570466697] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 13:20:10.251509 Camera needs 4 requests, can't test only 1
11086 13:20:10.293624 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11087 13:20:10.303078 [0:01:31.623171312] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11088 13:20:10.344280
11089 13:20:10.398647 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (53 ms)
11090 13:20:10.454795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11091 13:20:10.455140 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11093 13:20:10.468383 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11094 13:20:10.499840 Camera needs 4 requests, can't test only 2
11095 13:20:10.547089 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11096 13:20:10.589731
11097 13:20:10.644777 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (53 ms)
11098 13:20:10.701836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11099 13:20:10.702208 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11101 13:20:10.710825 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11102 13:20:10.748507 Camera needs 4 requests, can't test only 3
11103 13:20:10.796784 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11104 13:20:10.840189
11105 13:20:10.891703 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (52 ms)
11106 13:20:10.945388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11107 13:20:10.945682 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11109 13:20:10.953680 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11110 13:20:12.460221 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2167 ms)
11111 13:20:12.473470 [0:01:33.791258543] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11112 13:20:12.515725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11113 13:20:12.516074 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11115 13:20:12.527354 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11116 13:20:15.263525 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2802 ms)
11117 13:20:15.275657 [0:01:36.594261851] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11118 13:20:15.325557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11119 13:20:15.325841 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11121 13:20:15.336537 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11122 13:20:19.110781 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3848 ms)
11123 13:20:19.123781 [0:01:40.442316774] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11124 13:20:19.169194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11125 13:20:19.169482 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11127 13:20:19.178253 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11128 13:20:24.637423 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5527 ms)
11129 13:20:24.650999 [0:01:45.970245621] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11130 13:20:24.714874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11131 13:20:24.715154 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11133 13:20:24.729521 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11134 13:20:32.897184 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8260 ms)
11135 13:20:32.911119 [0:01:54.230872775] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11136 13:20:32.981043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11137 13:20:32.981330 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11139 13:20:32.993458 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11140 13:20:45.564400 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12667 ms)
11141 13:20:45.576934 [0:02:06.898843545] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11142 13:20:45.635045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11143 13:20:45.635792 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11145 13:20:45.649434 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11146 13:21:05.371842 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19810 ms)
11147 13:21:05.384707 [0:02:26.708682931] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11148 13:21:05.432521 [0:02:26.761351469] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 13:21:05.439195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11150 13:21:05.439445 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11152 13:21:05.448029 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11153 13:21:05.484723 [0:02:26.813531008] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11154 13:21:05.488935 Camera needs 4 requests, can't test only 1
11155 13:21:05.537341 [0:02:26.865937931] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11156 13:21:05.540670 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11157 13:21:05.585478
11158 13:21:05.639573 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (52 ms)
11159 13:21:05.696859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11160 13:21:05.697127 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11162 13:21:05.703229 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11163 13:21:05.740105 Camera needs 4 requests, can't test only 2
11164 13:21:05.797821 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11165 13:21:05.846202
11166 13:21:05.897369 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (52 ms)
11167 13:21:05.959719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11168 13:21:05.959984 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11170 13:21:05.967517 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11171 13:21:06.003330 Camera needs 4 requests, can't test only 3
11172 13:21:06.055360 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11173 13:21:06.100647
11174 13:21:06.160052 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (51 ms)
11175 13:21:06.221599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11176 13:21:06.221877 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11178 13:21:06.229478 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11179 13:21:07.699995 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2167 ms)
11180 13:21:07.709982 [0:02:29.033874700] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11181 13:21:07.762309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11182 13:21:07.762569 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11184 13:21:07.768853 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11185 13:21:10.496223 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2796 ms)
11186 13:21:10.506332 [0:02:31.830818393] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11187 13:21:10.580314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11188 13:21:10.580599 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11190 13:21:10.588494 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11191 13:21:14.343839 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3847 ms)
11192 13:21:14.353624 [0:02:35.678396624] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11193 13:21:14.426692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11194 13:21:14.427375 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11196 13:21:14.435440 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11197 13:21:19.870528 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5527 ms)
11198 13:21:19.880106 [0:02:41.205645855] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11199 13:21:19.944961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11200 13:21:19.945972 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11202 13:21:19.954216 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11203 13:21:28.128983 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8259 ms)
11204 13:21:28.138599 [0:02:49.464789625] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11205 13:21:28.218517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11206 13:21:28.219203 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11208 13:21:28.228944 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11209 13:21:40.796229 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12669 ms)
11210 13:21:40.806101 [0:03:02.134310087] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11211 13:21:40.874566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11212 13:21:40.874851 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11214 13:21:40.883167 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11215 13:22:00.604521 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19810 ms)
11216 13:22:00.614295 [0:03:21.944391780] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 13:22:00.661027 [0:03:21.996106627] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 13:22:00.679214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11219 13:22:00.679468 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11221 13:22:00.688174 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11222 13:22:00.714117 [0:03:22.049153550] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 13:22:00.732857 Camera needs 4 requests, can't test only 1
11224 13:22:00.767786 [0:03:22.102936550] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11225 13:22:00.794949 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11226 13:22:00.849990
11227 13:22:00.917499 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (52 ms)
11228 13:22:00.981573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11229 13:22:00.981865 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11231 13:22:00.992484 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11232 13:22:01.031559 Camera needs 4 requests, can't test only 2
11233 13:22:01.086947 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11234 13:22:01.141691
11235 13:22:01.199947 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (53 ms)
11236 13:22:01.267509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11237 13:22:01.267789 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11239 13:22:01.276407 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11240 13:22:01.321027 Camera needs 4 requests, can't test only 3
11241 13:22:01.382677 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11242 13:22:01.436702
11243 13:22:01.512693 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11244 13:22:01.582515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11245 13:22:01.582809 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11247 13:22:01.591359 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11248 13:22:02.933503 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2170 ms)
11249 13:22:02.943840 [0:03:24.274369473] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11250 13:22:03.003651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11251 13:22:03.003932 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11253 13:22:03.011504 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11254 13:22:05.733020 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2798 ms)
11255 13:22:05.743011 [0:03:27.072984704] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11256 13:22:05.813064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11257 13:22:05.814026 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11259 13:22:05.822810 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11260 13:22:09.581517 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3848 ms)
11261 13:22:09.591160 [0:03:30.922578089] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11262 13:22:09.659982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11263 13:22:09.660621 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11265 13:22:09.669922 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11266 13:22:15.109312 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5528 ms)
11267 13:22:15.119760 [0:03:36.451090166] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11268 13:22:15.190229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11269 13:22:15.190974 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11271 13:22:15.201152 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11272 13:22:23.370635 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8262 ms)
11273 13:22:23.380406 [0:03:44.712997551] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 13:22:23.445885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11275 13:22:23.446579 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11277 13:22:23.456087 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11278 13:22:36.039767 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12670 ms)
11279 13:22:36.049628 [0:03:57.383631552] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11280 13:22:36.116786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11281 13:22:36.117057 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11283 13:22:36.127278 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11284 13:22:55.848623 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19811 ms)
11285 13:22:55.858729 [0:04:17.195207784] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 13:22:55.906571 [0:04:17.248039707] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11287 13:22:55.940708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11288 13:22:55.940968 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11290 13:22:55.948820 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11291 13:22:55.962756 [0:04:17.304141015] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 13:22:56.000202 Camera needs 4 requests, can't test only 1
11293 13:22:56.017952 [0:04:17.358945245] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11294 13:22:56.078698 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11295 13:22:56.145156
11296 13:22:56.220259 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (52 ms)
11297 13:22:56.297402 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11299 13:22:56.300288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11300 13:22:56.307251 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11301 13:22:56.349530 Camera needs 4 requests, can't test only 2
11302 13:22:56.418292 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11303 13:22:56.483542
11304 13:22:56.546616 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (55 ms)
11305 13:22:56.615282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11306 13:22:56.615565 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11308 13:22:56.627226 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11309 13:22:56.674911 Camera needs 4 requests, can't test only 3
11310 13:22:56.742829 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11311 13:22:56.806036
11312 13:22:56.887296 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (54 ms)
11313 13:22:56.969804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11314 13:22:56.970532 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11316 13:22:56.980312 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11317 13:22:58.180235 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2167 ms)
11318 13:22:58.189438 [0:04:19.526571861] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11319 13:22:58.255117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11320 13:22:58.255471 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11322 13:22:58.264791 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11323 13:23:00.977570 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2798 ms)
11324 13:23:00.987872 [0:04:22.324962476] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11325 13:23:01.051309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11326 13:23:01.051612 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11328 13:23:01.059072 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11329 13:23:04.827334 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3849 ms)
11330 13:23:04.837511 [0:04:26.174822861] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11331 13:23:04.912091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11332 13:23:04.912751 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11334 13:23:04.924699 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11335 13:23:10.626485 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5799 ms)
11336 13:23:10.636603 [0:04:31.974583400] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11337 13:23:10.710803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11338 13:23:10.711579 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11340 13:23:10.720263 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11341 13:23:18.887096 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8262 ms)
11342 13:23:18.897116 [0:04:40.236575554] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 13:23:18.952629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11344 13:23:18.952972 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11346 13:23:18.959391 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11347 13:23:31.556331 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12670 ms)
11348 13:23:31.566034 [0:04:52.907056709] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11349 13:23:31.619313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11350 13:23:31.619926 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11352 13:23:31.627931 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11353 13:23:51.365845 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19811 ms)
11354 13:23:51.375369 [0:05:12.718796787] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 13:23:51.426301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11356 13:23:51.426567 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11358 13:23:51.433555 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11359 13:23:51.806519 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (444 ms)
11360 13:23:51.820157 [0:05:13.163271633] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 13:23:51.863215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11362 13:23:51.863512 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11364 13:23:51.873214 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11365 13:23:52.323013 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (516 ms)
11366 13:23:52.336376 [0:05:13.679652326] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11367 13:23:52.380405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11368 13:23:52.380661 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11370 13:23:52.390359 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11371 13:23:52.907535 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (584 ms)
11372 13:23:52.920895 [0:05:14.264507710] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 13:23:52.968879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11374 13:23:52.969137 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11376 13:23:52.976708 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11377 13:23:53.632444 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (724 ms)
11378 13:23:53.645839 [0:05:14.989259479] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11379 13:23:53.694635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11380 13:23:53.694906 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11382 13:23:53.705699 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11383 13:23:54.567530 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (935 ms)
11384 13:23:54.580533 [0:05:15.924524172] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11385 13:23:54.639996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11386 13:23:54.640302 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11388 13:23:54.653574 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11389 13:23:55.851685 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1284 ms)
11390 13:23:55.864850 [0:05:17.207833249] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11391 13:23:55.934708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11392 13:23:55.935355 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11394 13:23:55.946160 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11395 13:23:57.694566 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1843 ms)
11396 13:23:57.707490 [0:05:19.051989172] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11397 13:23:57.762193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11398 13:23:57.762503 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11400 13:23:57.773383 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11401 13:24:00.450026 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2755 ms)
11402 13:24:00.462786 [0:05:21.807459711] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11403 13:24:00.528158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11404 13:24:00.528884 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11406 13:24:00.541848 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11407 13:24:04.675020 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4225 ms)
11408 13:24:04.688154 [0:05:26.032713019] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11409 13:24:04.757967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11410 13:24:04.758649 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11412 13:24:04.770100 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11413 13:24:11.280483 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6605 ms)
11414 13:24:11.293556 [0:05:32.638784865] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11415 13:24:11.365394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11416 13:24:11.366076 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11418 13:24:11.376911 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11419 13:24:11.727839 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (444 ms)
11420 13:24:11.737805 [0:05:33.083563173] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11421 13:24:11.813505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11422 13:24:11.814355 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11424 13:24:11.822901 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11425 13:24:12.243005 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (515 ms)
11426 13:24:12.253097 [0:05:33.598751942] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 13:24:12.319542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11428 13:24:12.320384 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11430 13:24:12.330232 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11431 13:24:12.828309 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (585 ms)
11432 13:24:12.838220 [0:05:34.183656942] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 13:24:12.908377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11434 13:24:12.908658 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11436 13:24:12.916122 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11437 13:24:13.552896 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (724 ms)
11438 13:24:13.562773 [0:05:34.908580788] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11439 13:24:13.632634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11440 13:24:13.633070 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11442 13:24:13.640916 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11443 13:24:14.489774 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (936 ms)
11444 13:24:14.499452 [0:05:35.845100096] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11445 13:24:14.578630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11446 13:24:14.579493 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11448 13:24:14.589310 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11449 13:24:15.774557 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1284 ms)
11450 13:24:15.783779 [0:05:37.130051942] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 13:24:15.859204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11452 13:24:15.859508 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11454 13:24:15.866764 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11455 13:24:17.618790 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1844 ms)
11456 13:24:17.628610 [0:05:38.975234635] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11457 13:24:17.699108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11458 13:24:17.699373 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11460 13:24:17.707296 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11461 13:24:20.376113 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2757 ms)
11462 13:24:20.385712 [0:05:41.732514096] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11463 13:24:20.458567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11464 13:24:20.458834 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11466 13:24:20.466740 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11467 13:24:24.600600 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4225 ms)
11468 13:24:24.610897 [0:05:45.958054251] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11469 13:24:24.674640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11470 13:24:24.674917 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11472 13:24:24.684046 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11473 13:24:31.206095 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6605 ms)
11474 13:24:31.215643 [0:05:52.563819636] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11475 13:24:31.282966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11476 13:24:31.283250 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11478 13:24:31.292371 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11479 13:24:31.650527 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (444 ms)
11480 13:24:31.660341 [0:05:53.008139020] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 13:24:31.727936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11482 13:24:31.728204 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11484 13:24:31.737457 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11485 13:24:32.165180 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (515 ms)
11486 13:24:32.176353 [0:05:53.523449251] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11487 13:24:32.247369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11488 13:24:32.247668 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11490 13:24:32.257644 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11491 13:24:32.750124 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (584 ms)
11492 13:24:32.759656 [0:05:54.108059713] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11493 13:24:32.824241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11494 13:24:32.824512 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11496 13:24:32.833806 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11497 13:24:33.474678 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (724 ms)
11498 13:24:33.484450 [0:05:54.832547713] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 13:24:33.553139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11500 13:24:33.553457 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11502 13:24:33.562034 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11503 13:24:34.410963 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (936 ms)
11504 13:24:34.420802 [0:05:55.769225867] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 13:24:34.489859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11506 13:24:34.490138 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11508 13:24:34.498353 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11509 13:24:35.695497 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1284 ms)
11510 13:24:35.705353 [0:05:57.054361559] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11511 13:24:35.768894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11512 13:24:35.769169 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11514 13:24:35.777160 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11515 13:24:37.540692 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1845 ms)
11516 13:24:37.550281 [0:05:58.899487251] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11517 13:24:37.615651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11518 13:24:37.615929 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11520 13:24:37.623330 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11521 13:24:40.296258 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2755 ms)
11522 13:24:40.305614 [0:06:01.655142098] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11523 13:24:40.369889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11524 13:24:40.370192 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11526 13:24:40.379439 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11527 13:24:44.521238 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4225 ms)
11528 13:24:44.530541 [0:06:05.880531021] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11529 13:24:44.594079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11530 13:24:44.594380 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11532 13:24:44.603562 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11533 13:24:51.126555 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6605 ms)
11534 13:24:51.136315 [0:06:12.486584714] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11535 13:24:51.202526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11536 13:24:51.202801 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11538 13:24:51.212332 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11539 13:24:51.571016 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (444 ms)
11540 13:24:51.581001 [0:06:12.931487637] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11541 13:24:51.643116 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11543 13:24:51.645907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11544 13:24:51.653981 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11545 13:24:52.085712 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (514 ms)
11546 13:24:52.096151 [0:06:13.446509329] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11547 13:24:52.152656 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11549 13:24:52.155446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11550 13:24:52.167158 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11551 13:24:52.670918 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (584 ms)
11552 13:24:52.680766 [0:06:14.031363714] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11553 13:24:52.746507 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11555 13:24:52.750595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11556 13:24:52.758663 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11557 13:24:53.395028 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (724 ms)
11558 13:24:53.405112 [0:06:14.755686791] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11559 13:24:53.462361 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11561 13:24:53.465089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11562 13:24:53.474568 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11563 13:24:54.330360 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (934 ms)
11564 13:24:54.339895 [0:06:15.690797406] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 13:24:54.385718 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11567 13:24:54.388738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11568 13:24:54.400485 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11569 13:24:55.614849 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1284 ms)
11570 13:24:55.624245 [0:06:16.975563022] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 13:24:55.687548 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11573 13:24:55.690685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11574 13:24:55.701379 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11575 13:24:57.459184 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1844 ms)
11576 13:24:57.468882 [0:06:18.820140406] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 13:24:57.539076 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11579 13:24:57.541677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11580 13:24:57.551686 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11581 13:25:00.214645 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2755 ms)
11582 13:25:00.224506 [0:06:21.576045407] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11583 13:25:00.279811 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11585 13:25:00.283063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11586 13:25:00.291861 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11587 13:25:04.439529 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4225 ms)
11588 13:25:04.449248 [0:06:25.801382561] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11589 13:25:04.515020 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11591 13:25:04.518409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11592 13:25:04.526880 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11593 13:25:11.045371 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6606 ms)
11594 13:25:11.114300 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11596 13:25:11.117505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11597 13:25:11.125953 [----------] 120 tests from CaptureTests/SingleStream (374611 ms total)
11598 13:25:11.174158
11599 13:25:11.241414 [----------] Global test environment tear-down
11600 13:25:11.303546 [==========] 120 tests from 1 test suite ran. (374612 ms total)
11601 13:25:11.368378 <LAVA_SIGNAL_TESTSET STOP>
11602 13:25:11.368486 + set +x
11603 13:25:11.368715 Received signal: <TESTSET> STOP
11604 13:25:11.368784 Closing test_set CaptureTests/SingleStream
11605 13:25:11.374213 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14879033_1.6.2.3.1>
11606 13:25:11.374441 Received signal: <ENDRUN> 0_lc-compliance 14879033_1.6.2.3.1
11607 13:25:11.374513 Ending use of test pattern.
11608 13:25:11.374568 Ending test lava.0_lc-compliance (14879033_1.6.2.3.1), duration 376.52
11610 13:25:11.377687 <LAVA_TEST_RUNNER EXIT>
11611 13:25:11.377919 ok: lava_test_shell seems to have completed
11612 13:25:11.379587 Capture/Raw_1:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_2:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_3:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_5:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_8:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_13:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_21:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_34:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_55:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_89:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
11613 13:25:11.379788 end: 3.1 lava-test-shell (duration 00:06:17) [common]
11614 13:25:11.379871 end: 3 lava-test-retry (duration 00:06:17) [common]
11615 13:25:11.379953 start: 4 finalize (timeout 00:10:00) [common]
11616 13:25:11.380035 start: 4.1 power-off (timeout 00:00:30) [common]
11617 13:25:11.380157 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11618 13:25:13.447251 >> Command sent successfully.
11619 13:25:13.450857 Returned 0 in 2 seconds
11620 13:25:13.451014 end: 4.1 power-off (duration 00:00:02) [common]
11622 13:25:13.451231 start: 4.2 read-feedback (timeout 00:09:58) [common]
11623 13:25:13.451416 Listened to connection for namespace 'common' for up to 1s
11624 13:25:14.452458 Finalising connection for namespace 'common'
11625 13:25:14.452614 Disconnecting from shell: Finalise
11626 13:25:14.452696 / #
11627 13:25:14.552986 end: 4.2 read-feedback (duration 00:00:01) [common]
11628 13:25:14.553130 end: 4 finalize (duration 00:00:03) [common]
11629 13:25:14.553286 Cleaning after the job
11630 13:25:14.553393 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/ramdisk
11631 13:25:14.553966 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/kernel
11632 13:25:14.556053 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/dtb
11633 13:25:14.556206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/nfsrootfs
11634 13:25:14.565095 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879033/tftp-deploy-q9ao1fcs/modules
11635 13:25:14.566342 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879033
11636 13:25:14.774537 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879033
11637 13:25:14.774713 Job finished correctly