Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 13:18:09.822032 lava-dispatcher, installed at version: 2024.05
2 13:18:09.822228 start: 0 validate
3 13:18:09.822340 Start time: 2024-07-18 13:18:09.822335+00:00 (UTC)
4 13:18:09.822472 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:18:09.822607 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:18:10.086206 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:18:10.086831 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:18:10.346572 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:18:10.346875 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:18:10.606272 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:18:10.606851 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 13:18:10.868137 validate duration: 1.05
14 13:18:10.868463 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:18:10.868592 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:18:10.868700 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:18:10.868893 Not decompressing ramdisk as can be used compressed.
18 13:18:10.868999 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 13:18:10.869089 saving as /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/ramdisk/rootfs.cpio.gz
20 13:18:10.869230 total size: 28105535 (26 MB)
21 13:18:10.870664 progress 0 % (0 MB)
22 13:18:10.879452 progress 5 % (1 MB)
23 13:18:10.887370 progress 10 % (2 MB)
24 13:18:10.895178 progress 15 % (4 MB)
25 13:18:10.902269 progress 20 % (5 MB)
26 13:18:10.909548 progress 25 % (6 MB)
27 13:18:10.916937 progress 30 % (8 MB)
28 13:18:10.924553 progress 35 % (9 MB)
29 13:18:10.932132 progress 40 % (10 MB)
30 13:18:10.938992 progress 45 % (12 MB)
31 13:18:10.945860 progress 50 % (13 MB)
32 13:18:10.955662 progress 55 % (14 MB)
33 13:18:10.965669 progress 60 % (16 MB)
34 13:18:10.972940 progress 65 % (17 MB)
35 13:18:10.980207 progress 70 % (18 MB)
36 13:18:10.987537 progress 75 % (20 MB)
37 13:18:10.994837 progress 80 % (21 MB)
38 13:18:11.002040 progress 85 % (22 MB)
39 13:18:11.011743 progress 90 % (24 MB)
40 13:18:11.019069 progress 95 % (25 MB)
41 13:18:11.026258 progress 100 % (26 MB)
42 13:18:11.026489 26 MB downloaded in 0.16 s (170.45 MB/s)
43 13:18:11.026687 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:18:11.027034 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:18:11.027143 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:18:11.027248 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:18:11.027404 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 13:18:11.027495 saving as /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/kernel/Image
50 13:18:11.027577 total size: 54813184 (52 MB)
51 13:18:11.027659 No compression specified
52 13:18:11.029110 progress 0 % (0 MB)
53 13:18:11.043150 progress 5 % (2 MB)
54 13:18:11.059449 progress 10 % (5 MB)
55 13:18:11.074797 progress 15 % (7 MB)
56 13:18:11.088241 progress 20 % (10 MB)
57 13:18:11.103879 progress 25 % (13 MB)
58 13:18:11.119053 progress 30 % (15 MB)
59 13:18:11.132052 progress 35 % (18 MB)
60 13:18:11.145855 progress 40 % (20 MB)
61 13:18:11.159414 progress 45 % (23 MB)
62 13:18:11.191997 progress 50 % (26 MB)
63 13:18:11.216919 progress 55 % (28 MB)
64 13:18:11.230332 progress 60 % (31 MB)
65 13:18:11.243484 progress 65 % (34 MB)
66 13:18:11.256496 progress 70 % (36 MB)
67 13:18:11.269874 progress 75 % (39 MB)
68 13:18:11.283416 progress 80 % (41 MB)
69 13:18:11.297310 progress 85 % (44 MB)
70 13:18:11.310801 progress 90 % (47 MB)
71 13:18:11.324522 progress 95 % (49 MB)
72 13:18:11.337740 progress 100 % (52 MB)
73 13:18:11.337954 52 MB downloaded in 0.31 s (168.42 MB/s)
74 13:18:11.338099 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:18:11.338305 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:18:11.338383 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:18:11.338456 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:18:11.338582 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:18:11.338649 saving as /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/dtb/mt8192-asurada-spherion-r0.dtb
81 13:18:11.338708 total size: 47258 (0 MB)
82 13:18:11.338804 No compression specified
83 13:18:11.339756 progress 69 % (0 MB)
84 13:18:11.339999 progress 100 % (0 MB)
85 13:18:11.340139 0 MB downloaded in 0.00 s (31.54 MB/s)
86 13:18:11.340246 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:18:11.340439 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:18:11.340539 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:18:11.340645 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:18:11.340824 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 13:18:11.340912 saving as /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/modules/modules.tar
93 13:18:11.340995 total size: 8611320 (8 MB)
94 13:18:11.341077 Using unxz to decompress xz
95 13:18:11.342597 progress 0 % (0 MB)
96 13:18:11.362694 progress 5 % (0 MB)
97 13:18:11.386626 progress 10 % (0 MB)
98 13:18:11.409896 progress 15 % (1 MB)
99 13:18:11.433228 progress 20 % (1 MB)
100 13:18:11.456268 progress 25 % (2 MB)
101 13:18:11.479161 progress 30 % (2 MB)
102 13:18:11.501395 progress 35 % (2 MB)
103 13:18:11.526923 progress 40 % (3 MB)
104 13:18:11.550259 progress 45 % (3 MB)
105 13:18:11.573376 progress 50 % (4 MB)
106 13:18:11.597352 progress 55 % (4 MB)
107 13:18:11.620447 progress 60 % (4 MB)
108 13:18:11.643211 progress 65 % (5 MB)
109 13:18:11.668145 progress 70 % (5 MB)
110 13:18:11.694343 progress 75 % (6 MB)
111 13:18:11.720518 progress 80 % (6 MB)
112 13:18:11.743939 progress 85 % (7 MB)
113 13:18:11.766250 progress 90 % (7 MB)
114 13:18:11.788740 progress 95 % (7 MB)
115 13:18:11.811253 progress 100 % (8 MB)
116 13:18:11.816549 8 MB downloaded in 0.48 s (17.27 MB/s)
117 13:18:11.816692 end: 1.4.1 http-download (duration 00:00:00) [common]
119 13:18:11.816899 end: 1.4 download-retry (duration 00:00:00) [common]
120 13:18:11.816979 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:18:11.817056 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:18:11.817158 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:18:11.817244 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:18:11.817411 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24
125 13:18:11.817529 makedir: /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin
126 13:18:11.817618 makedir: /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/tests
127 13:18:11.817706 makedir: /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/results
128 13:18:11.817791 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-add-keys
129 13:18:11.817918 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-add-sources
130 13:18:11.818034 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-background-process-start
131 13:18:11.818149 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-background-process-stop
132 13:18:11.818274 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-common-functions
133 13:18:11.818387 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-echo-ipv4
134 13:18:11.818502 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-install-packages
135 13:18:11.818613 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-installed-packages
136 13:18:11.818723 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-os-build
137 13:18:11.818833 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-probe-channel
138 13:18:11.818948 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-probe-ip
139 13:18:11.819058 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-target-ip
140 13:18:11.819167 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-target-mac
141 13:18:11.819276 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-target-storage
142 13:18:11.819390 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-test-case
143 13:18:11.819501 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-test-event
144 13:18:11.819610 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-test-feedback
145 13:18:11.819720 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-test-raise
146 13:18:11.819839 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-test-reference
147 13:18:11.819951 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-test-runner
148 13:18:11.820062 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-test-set
149 13:18:11.820171 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-test-shell
150 13:18:11.820283 Updating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-install-packages (oe)
151 13:18:11.820420 Updating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/bin/lava-installed-packages (oe)
152 13:18:11.820528 Creating /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/environment
153 13:18:11.820626 LAVA metadata
154 13:18:11.820688 - LAVA_JOB_ID=14879043
155 13:18:11.820743 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:18:11.820829 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:18:11.820884 skipped lava-vland-overlay
158 13:18:11.820949 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:18:11.821017 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:18:11.821071 skipped lava-multinode-overlay
161 13:18:11.821149 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:18:11.821220 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:18:11.821284 Loading test definitions
164 13:18:11.821358 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:18:11.821415 Using /lava-14879043 at stage 0
166 13:18:11.821702 uuid=14879043_1.5.2.3.1 testdef=None
167 13:18:11.821781 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:18:11.821855 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:18:11.822284 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:18:11.822478 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:18:11.823030 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:18:11.823234 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:18:11.823768 runner path: /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14879043_1.5.2.3.1
176 13:18:11.823907 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:18:11.824090 Creating lava-test-runner.conf files
179 13:18:11.824145 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879043/lava-overlay-qb6lt_24/lava-14879043/0 for stage 0
180 13:18:11.824225 - 0_v4l2-compliance-mtk-vcodec-enc
181 13:18:11.824314 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:18:11.824387 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:18:11.830488 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:18:11.830580 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:18:11.830657 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:18:11.830732 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:18:11.830806 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:18:12.611268 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:18:12.611414 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:18:12.611493 extracting modules file /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879043/extract-overlay-ramdisk-dsdbng2_/ramdisk
191 13:18:12.840151 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:18:12.840290 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:18:12.840413 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879043/compress-overlay-lr_rpoyv/overlay-1.5.2.4.tar.gz to ramdisk
194 13:18:12.840488 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879043/compress-overlay-lr_rpoyv/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879043/extract-overlay-ramdisk-dsdbng2_/ramdisk
195 13:18:12.846920 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:18:12.847013 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:18:12.847096 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:18:12.847172 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:18:12.847236 Building ramdisk /var/lib/lava/dispatcher/tmp/14879043/extract-overlay-ramdisk-dsdbng2_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879043/extract-overlay-ramdisk-dsdbng2_/ramdisk
200 13:18:13.429774 >> 275513 blocks
201 13:18:17.625281 rename /var/lib/lava/dispatcher/tmp/14879043/extract-overlay-ramdisk-dsdbng2_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/ramdisk/ramdisk.cpio.gz
202 13:18:17.625430 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:18:17.625515 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 13:18:17.625592 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 13:18:17.625671 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/kernel/Image']
206 13:18:31.269914 Returned 0 in 13 seconds
207 13:18:31.270077 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/kernel/image.itb
208 13:18:31.880726 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:18:31.880842 output: Created: Thu Jul 18 14:18:31 2024
210 13:18:31.880935 output: Image 0 (kernel-1)
211 13:18:31.880989 output: Description:
212 13:18:31.881041 output: Created: Thu Jul 18 14:18:31 2024
213 13:18:31.881093 output: Type: Kernel Image
214 13:18:31.881181 output: Compression: lzma compressed
215 13:18:31.881233 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
216 13:18:31.881282 output: Architecture: AArch64
217 13:18:31.881330 output: OS: Linux
218 13:18:31.881379 output: Load Address: 0x00000000
219 13:18:31.881427 output: Entry Point: 0x00000000
220 13:18:31.881474 output: Hash algo: crc32
221 13:18:31.881523 output: Hash value: a47b020b
222 13:18:31.881571 output: Image 1 (fdt-1)
223 13:18:31.881619 output: Description: mt8192-asurada-spherion-r0
224 13:18:31.881667 output: Created: Thu Jul 18 14:18:31 2024
225 13:18:31.881714 output: Type: Flat Device Tree
226 13:18:31.881762 output: Compression: uncompressed
227 13:18:31.881809 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:18:31.881889 output: Architecture: AArch64
229 13:18:31.881937 output: Hash algo: crc32
230 13:18:31.881984 output: Hash value: 0f8e4d2e
231 13:18:31.882031 output: Image 2 (ramdisk-1)
232 13:18:31.882078 output: Description: unavailable
233 13:18:31.882126 output: Created: Thu Jul 18 14:18:31 2024
234 13:18:31.882205 output: Type: RAMDisk Image
235 13:18:31.882252 output: Compression: uncompressed
236 13:18:31.882300 output: Data Size: 41203095 Bytes = 40237.40 KiB = 39.29 MiB
237 13:18:31.882347 output: Architecture: AArch64
238 13:18:31.882395 output: OS: Linux
239 13:18:31.882442 output: Load Address: unavailable
240 13:18:31.882521 output: Entry Point: unavailable
241 13:18:31.882568 output: Hash algo: crc32
242 13:18:31.882615 output: Hash value: d8d234d8
243 13:18:31.882662 output: Default Configuration: 'conf-1'
244 13:18:31.882709 output: Configuration 0 (conf-1)
245 13:18:31.882756 output: Description: mt8192-asurada-spherion-r0
246 13:18:31.882833 output: Kernel: kernel-1
247 13:18:31.882880 output: Init Ramdisk: ramdisk-1
248 13:18:31.882927 output: FDT: fdt-1
249 13:18:31.882974 output: Loadables: kernel-1
250 13:18:31.883022 output:
251 13:18:31.883175 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:18:31.883251 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:18:31.883325 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 13:18:31.883428 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 13:18:31.883485 No LXC device requested
256 13:18:31.883553 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:18:31.883629 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 13:18:31.883727 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:18:31.883782 Checking files for TFTP limit of 4294967296 bytes.
260 13:18:31.884171 end: 1 tftp-deploy (duration 00:00:21) [common]
261 13:18:31.884258 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:18:31.884365 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:18:31.884453 substitutions:
264 13:18:31.884512 - {DTB}: 14879043/tftp-deploy-ccdzcpl7/dtb/mt8192-asurada-spherion-r0.dtb
265 13:18:31.884567 - {INITRD}: 14879043/tftp-deploy-ccdzcpl7/ramdisk/ramdisk.cpio.gz
266 13:18:31.884648 - {KERNEL}: 14879043/tftp-deploy-ccdzcpl7/kernel/Image
267 13:18:31.884699 - {LAVA_MAC}: None
268 13:18:31.884749 - {PRESEED_CONFIG}: None
269 13:18:31.884798 - {PRESEED_LOCAL}: None
270 13:18:31.884847 - {RAMDISK}: 14879043/tftp-deploy-ccdzcpl7/ramdisk/ramdisk.cpio.gz
271 13:18:31.884901 - {ROOT_PART}: None
272 13:18:31.884965 - {ROOT}: None
273 13:18:31.885014 - {SERVER_IP}: 192.168.201.1
274 13:18:31.885064 - {TEE}: None
275 13:18:31.885118 Parsed boot commands:
276 13:18:31.885181 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:18:31.885362 Parsed boot commands: tftpboot 192.168.201.1 14879043/tftp-deploy-ccdzcpl7/kernel/image.itb 14879043/tftp-deploy-ccdzcpl7/kernel/cmdline
278 13:18:31.885441 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:18:31.885545 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:18:31.885615 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:18:31.885684 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:18:31.885737 Not connected, no need to disconnect.
283 13:18:31.885819 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:18:31.885900 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:18:31.885954 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 13:18:31.888889 Setting prompt string to ['lava-test: # ']
287 13:18:31.889240 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:18:31.889334 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:18:31.889420 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:18:31.889542 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:18:31.889768 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 13:18:41.027721 >> Command sent successfully.
293 13:18:41.031768 Returned 0 in 9 seconds
294 13:18:41.031920 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 13:18:41.032128 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 13:18:41.032211 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 13:18:41.032279 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:18:41.032334 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:18:41.032391 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:18:41.032932 [Enter `^Ec?' for help]
302 13:18:42.631900
303 13:18:42.632074
304 13:18:42.632169 F0: 102B 0000
305 13:18:42.632270
306 13:18:42.632362 F3: 1001 0000 [0200]
307 13:18:42.632451
308 13:18:42.635811 F3: 1001 0000
309 13:18:42.635909
310 13:18:42.635994 F7: 102D 0000
311 13:18:42.636083
312 13:18:42.636164 F1: 0000 0000
313 13:18:42.636241
314 13:18:42.639419 V0: 0000 0000 [0001]
315 13:18:42.639482
316 13:18:42.639535 00: 0007 8000
317 13:18:42.639587
318 13:18:42.643394 01: 0000 0000
319 13:18:42.643486
320 13:18:42.643542 BP: 0C00 0209 [0000]
321 13:18:42.643592
322 13:18:42.643647 G0: 1182 0000
323 13:18:42.643697
324 13:18:42.647043 EC: 0000 0021 [4000]
325 13:18:42.647128
326 13:18:42.647205 S7: 0000 0000 [0000]
327 13:18:42.650483
328 13:18:42.650545 CC: 0000 0000 [0001]
329 13:18:42.650599
330 13:18:42.653858 T0: 0000 0040 [010F]
331 13:18:42.653950
332 13:18:42.654049 Jump to BL
333 13:18:42.654104
334 13:18:42.678482
335 13:18:42.678580
336 13:18:42.685641 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:18:42.689240 ARM64: Exception handlers installed.
338 13:18:42.693237 ARM64: Testing exception
339 13:18:42.696655 ARM64: Done test exception
340 13:18:42.704198 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:18:42.711264 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:18:42.718480 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:18:42.730560 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:18:42.737774 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:18:42.744740 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:18:42.755839 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:18:42.762871 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:18:42.782792 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:18:42.786155 WDT: Last reset was cold boot
350 13:18:42.790169 SPI1(PAD0) initialized at 2873684 Hz
351 13:18:42.793278 SPI5(PAD0) initialized at 992727 Hz
352 13:18:42.793402 VBOOT: Loading verstage.
353 13:18:42.800853 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:18:42.805183 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:18:42.808379 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:18:42.811632 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:18:42.819265 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:18:42.826352 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:18:42.836952 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
360 13:18:42.837055
361 13:18:42.837184
362 13:18:42.848564 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:18:42.848649 ARM64: Exception handlers installed.
364 13:18:42.852192 ARM64: Testing exception
365 13:18:42.855698 ARM64: Done test exception
366 13:18:42.859859 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:18:42.863439 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:18:42.877965 Probing TPM: . done!
369 13:18:42.878042 TPM ready after 0 ms
370 13:18:42.881938 Connected to device vid:did:rid of 1ae0:0028:00
371 13:18:42.953361 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:18:42.953476 Initialized TPM device CR50 revision 0
373 13:18:42.958554 tlcl_send_startup: Startup return code is 0
374 13:18:42.966799 TPM: setup succeeded
375 13:18:42.983228 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:18:42.990413 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:18:43.000877 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:18:43.010777 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:18:43.014525 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:18:43.018808 in-header: 03 07 00 00 08 00 00 00
381 13:18:43.022747 in-data: aa e4 47 04 13 02 00 00
382 13:18:43.022824 Chrome EC: UHEPI supported
383 13:18:43.030049 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:18:43.033853 in-header: 03 a9 00 00 08 00 00 00
385 13:18:43.037416 in-data: 84 60 60 08 00 00 00 00
386 13:18:43.037505 Phase 1
387 13:18:43.041185 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:18:43.048997 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:18:43.052461 VB2:vb2_check_recovery() Recovery was requested manually
390 13:18:43.060058 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 13:18:43.060159 Recovery requested (1009000e)
392 13:18:43.068623 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:18:43.074295 tlcl_extend: response is 0
394 13:18:43.084271 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:18:43.087807 tlcl_extend: response is 0
396 13:18:43.094357 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:18:43.114643 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 13:18:43.122608 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:18:43.122682
400 13:18:43.122747
401 13:18:43.130028 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:18:43.133615 ARM64: Exception handlers installed.
403 13:18:43.137017 ARM64: Testing exception
404 13:18:43.140399 ARM64: Done test exception
405 13:18:43.160231 pmic_efuse_setting: Set efuses in 11 msecs
406 13:18:43.163711 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:18:43.170129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:18:43.173967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:18:43.180392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:18:43.183823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:18:43.191025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:18:43.193725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:18:43.197380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:18:43.203722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:18:43.207331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:18:43.213850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:18:43.217354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:18:43.220813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:18:43.227155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:18:43.234198 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:18:43.237610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:18:43.244171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:18:43.250957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:18:43.254202 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:18:43.260658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:18:43.267277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:18:43.270969 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:18:43.277367 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:18:43.284274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:18:43.287364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:18:43.294426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:18:43.301499 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:18:43.304636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:18:43.311334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:18:43.314363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:18:43.318070 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:18:43.324722 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:18:43.327650 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:18:43.335011 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:18:43.337909 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:18:43.345141 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:18:43.348630 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:18:43.355500 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:18:43.359121 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:18:43.362284 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:18:43.368901 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:18:43.371917 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:18:43.375463 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:18:43.381940 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:18:43.385440 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:18:43.389188 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:18:43.395527 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:18:43.399147 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:18:43.402458 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:18:43.405546 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:18:43.412195 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:18:43.415893 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:18:43.422704 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 13:18:43.432250 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:18:43.436008 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:18:43.445837 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:18:43.452790 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:18:43.455769 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:18:43.462495 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:18:43.465969 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:18:43.473226 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 13:18:43.479794 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:18:43.483429 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 13:18:43.486580 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:18:43.497268 [RTC]rtc_get_frequency_meter,154: input=15, output=791
471 13:18:43.507359 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 13:18:43.516291 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 13:18:43.525779 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 13:18:43.535538 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 13:18:43.545100 [RTC]rtc_get_frequency_meter,154: input=15, output=789
476 13:18:43.554759 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 13:18:43.558287 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 13:18:43.564884 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 13:18:43.568658 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:18:43.571863 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:18:43.578566 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:18:43.581643 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:18:43.585193 ADC[4]: Raw value=901328 ID=7
484 13:18:43.585269 ADC[3]: Raw value=213336 ID=1
485 13:18:43.588729 RAM Code: 0x71
486 13:18:43.591879 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:18:43.598528 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:18:43.605398 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:18:43.611828 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:18:43.615351 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:18:43.619031 in-header: 03 07 00 00 08 00 00 00
492 13:18:43.622171 in-data: aa e4 47 04 13 02 00 00
493 13:18:43.625222 Chrome EC: UHEPI supported
494 13:18:43.631788 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:18:43.635332 in-header: 03 a9 00 00 08 00 00 00
496 13:18:43.638891 in-data: 84 60 60 08 00 00 00 00
497 13:18:43.641950 MRC: failed to locate region type 0.
498 13:18:43.648707 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:18:43.652402 DRAM-K: Running full calibration
500 13:18:43.658876 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:18:43.658954 header.status = 0x0
502 13:18:43.662357 header.version = 0x6 (expected: 0x6)
503 13:18:43.665385 header.size = 0xd00 (expected: 0xd00)
504 13:18:43.669040 header.flags = 0x0
505 13:18:43.672290 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:18:43.691481 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
507 13:18:43.697946 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:18:43.701652 dram_init: ddr_geometry: 2
509 13:18:43.701729 [EMI] MDL number = 2
510 13:18:43.704529 [EMI] Get MDL freq = 0
511 13:18:43.708261 dram_init: ddr_type: 0
512 13:18:43.708331 is_discrete_lpddr4: 1
513 13:18:43.711999 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:18:43.712091
515 13:18:43.712176
516 13:18:43.714673 [Bian_co] ETT version 0.0.0.1
517 13:18:43.721698 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:18:43.721777
519 13:18:43.724867 dramc_set_vcore_voltage set vcore to 650000
520 13:18:43.724943 Read voltage for 800, 4
521 13:18:43.728451 Vio18 = 0
522 13:18:43.728525 Vcore = 650000
523 13:18:43.728582 Vdram = 0
524 13:18:43.731540 Vddq = 0
525 13:18:43.731614 Vmddr = 0
526 13:18:43.734910 dram_init: config_dvfs: 1
527 13:18:43.738669 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:18:43.745428 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:18:43.748203 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 13:18:43.751823 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 13:18:43.755252 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 13:18:43.758487 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 13:18:43.762180 MEM_TYPE=3, freq_sel=18
534 13:18:43.765100 sv_algorithm_assistance_LP4_1600
535 13:18:43.768900 ============ PULL DRAM RESETB DOWN ============
536 13:18:43.771947 ========== PULL DRAM RESETB DOWN end =========
537 13:18:43.779031 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:18:43.782037 ===================================
539 13:18:43.782129 LPDDR4 DRAM CONFIGURATION
540 13:18:43.785603 ===================================
541 13:18:43.789921 EX_ROW_EN[0] = 0x0
542 13:18:43.789997 EX_ROW_EN[1] = 0x0
543 13:18:43.792939 LP4Y_EN = 0x0
544 13:18:43.793036 WORK_FSP = 0x0
545 13:18:43.797039 WL = 0x2
546 13:18:43.797123 RL = 0x2
547 13:18:43.800702 BL = 0x2
548 13:18:43.800783 RPST = 0x0
549 13:18:43.804428 RD_PRE = 0x0
550 13:18:43.804503 WR_PRE = 0x1
551 13:18:43.804561 WR_PST = 0x0
552 13:18:43.807447 DBI_WR = 0x0
553 13:18:43.810972 DBI_RD = 0x0
554 13:18:43.811085 OTF = 0x1
555 13:18:43.815093 ===================================
556 13:18:43.818851 ===================================
557 13:18:43.818927 ANA top config
558 13:18:43.822637 ===================================
559 13:18:43.826143 DLL_ASYNC_EN = 0
560 13:18:43.826218 ALL_SLAVE_EN = 1
561 13:18:43.829261 NEW_RANK_MODE = 1
562 13:18:43.832808 DLL_IDLE_MODE = 1
563 13:18:43.835887 LP45_APHY_COMB_EN = 1
564 13:18:43.839563 TX_ODT_DIS = 1
565 13:18:43.839638 NEW_8X_MODE = 1
566 13:18:43.843045 ===================================
567 13:18:43.846326 ===================================
568 13:18:43.849739 data_rate = 1600
569 13:18:43.853236 CKR = 1
570 13:18:43.856547 DQ_P2S_RATIO = 8
571 13:18:43.859504 ===================================
572 13:18:43.863204 CA_P2S_RATIO = 8
573 13:18:43.863278 DQ_CA_OPEN = 0
574 13:18:43.866139 DQ_SEMI_OPEN = 0
575 13:18:43.869634 CA_SEMI_OPEN = 0
576 13:18:43.873307 CA_FULL_RATE = 0
577 13:18:43.876241 DQ_CKDIV4_EN = 1
578 13:18:43.876331 CA_CKDIV4_EN = 1
579 13:18:43.879948 CA_PREDIV_EN = 0
580 13:18:43.883150 PH8_DLY = 0
581 13:18:43.886417 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:18:43.890024 DQ_AAMCK_DIV = 4
583 13:18:43.893740 CA_AAMCK_DIV = 4
584 13:18:43.893816 CA_ADMCK_DIV = 4
585 13:18:43.896898 DQ_TRACK_CA_EN = 0
586 13:18:43.899918 CA_PICK = 800
587 13:18:43.903336 CA_MCKIO = 800
588 13:18:43.906853 MCKIO_SEMI = 0
589 13:18:43.910323 PLL_FREQ = 3068
590 13:18:43.910399 DQ_UI_PI_RATIO = 32
591 13:18:43.913367 CA_UI_PI_RATIO = 0
592 13:18:43.916984 ===================================
593 13:18:43.920105 ===================================
594 13:18:43.923767 memory_type:LPDDR4
595 13:18:43.927200 GP_NUM : 10
596 13:18:43.927275 SRAM_EN : 1
597 13:18:43.930570 MD32_EN : 0
598 13:18:43.933966 ===================================
599 13:18:43.936882 [ANA_INIT] >>>>>>>>>>>>>>
600 13:18:43.937019 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:18:43.940652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:18:43.943759 ===================================
603 13:18:43.947388 data_rate = 1600,PCW = 0X7600
604 13:18:43.950291 ===================================
605 13:18:43.953775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:18:43.960643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:18:43.963649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:18:43.970640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:18:43.973998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:18:43.977681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:18:43.977757 [ANA_INIT] flow start
612 13:18:43.980616 [ANA_INIT] PLL >>>>>>>>
613 13:18:43.983739 [ANA_INIT] PLL <<<<<<<<
614 13:18:43.987464 [ANA_INIT] MIDPI >>>>>>>>
615 13:18:43.987540 [ANA_INIT] MIDPI <<<<<<<<
616 13:18:43.991022 [ANA_INIT] DLL >>>>>>>>
617 13:18:43.994470 [ANA_INIT] flow end
618 13:18:43.997449 ============ LP4 DIFF to SE enter ============
619 13:18:44.001078 ============ LP4 DIFF to SE exit ============
620 13:18:44.004196 [ANA_INIT] <<<<<<<<<<<<<
621 13:18:44.007239 [Flow] Enable top DCM control >>>>>
622 13:18:44.010735 [Flow] Enable top DCM control <<<<<
623 13:18:44.010810 Enable DLL master slave shuffle
624 13:18:44.017673 ==============================================================
625 13:18:44.021044 Gating Mode config
626 13:18:44.024766 ==============================================================
627 13:18:44.027810 Config description:
628 13:18:44.038028 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:18:44.044535 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:18:44.048184 SELPH_MODE 0: By rank 1: By Phase
631 13:18:44.054858 ==============================================================
632 13:18:44.058012 GAT_TRACK_EN = 1
633 13:18:44.058087 RX_GATING_MODE = 2
634 13:18:44.061358 RX_GATING_TRACK_MODE = 2
635 13:18:44.065043 SELPH_MODE = 1
636 13:18:44.068417 PICG_EARLY_EN = 1
637 13:18:44.071929 VALID_LAT_VALUE = 1
638 13:18:44.078150 ==============================================================
639 13:18:44.081834 Enter into Gating configuration >>>>
640 13:18:44.085404 Exit from Gating configuration <<<<
641 13:18:44.088460 Enter into DVFS_PRE_config >>>>>
642 13:18:44.098719 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:18:44.102026 Exit from DVFS_PRE_config <<<<<
644 13:18:44.105146 Enter into PICG configuration >>>>
645 13:18:44.108744 Exit from PICG configuration <<<<
646 13:18:44.111916 [RX_INPUT] configuration >>>>>
647 13:18:44.111991 [RX_INPUT] configuration <<<<<
648 13:18:44.118877 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:18:44.125522 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:18:44.129100 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:18:44.135316 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:18:44.141998 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:18:44.148802 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:18:44.152092 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:18:44.155775 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:18:44.162401 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:18:44.165462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:18:44.168829 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:18:44.172718 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:18:44.175883 ===================================
661 13:18:44.179366 LPDDR4 DRAM CONFIGURATION
662 13:18:44.182800 ===================================
663 13:18:44.186001 EX_ROW_EN[0] = 0x0
664 13:18:44.186076 EX_ROW_EN[1] = 0x0
665 13:18:44.189102 LP4Y_EN = 0x0
666 13:18:44.189186 WORK_FSP = 0x0
667 13:18:44.192874 WL = 0x2
668 13:18:44.192948 RL = 0x2
669 13:18:44.195870 BL = 0x2
670 13:18:44.195945 RPST = 0x0
671 13:18:44.199546 RD_PRE = 0x0
672 13:18:44.199620 WR_PRE = 0x1
673 13:18:44.202476 WR_PST = 0x0
674 13:18:44.202565 DBI_WR = 0x0
675 13:18:44.205939 DBI_RD = 0x0
676 13:18:44.206032 OTF = 0x1
677 13:18:44.209617 ===================================
678 13:18:44.212519 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:18:44.219152 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:18:44.222870 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:18:44.225852 ===================================
682 13:18:44.229412 LPDDR4 DRAM CONFIGURATION
683 13:18:44.232669 ===================================
684 13:18:44.232745 EX_ROW_EN[0] = 0x10
685 13:18:44.236227 EX_ROW_EN[1] = 0x0
686 13:18:44.236304 LP4Y_EN = 0x0
687 13:18:44.239283 WORK_FSP = 0x0
688 13:18:44.239360 WL = 0x2
689 13:18:44.242939 RL = 0x2
690 13:18:44.243014 BL = 0x2
691 13:18:44.246089 RPST = 0x0
692 13:18:44.249723 RD_PRE = 0x0
693 13:18:44.249798 WR_PRE = 0x1
694 13:18:44.252740 WR_PST = 0x0
695 13:18:44.252815 DBI_WR = 0x0
696 13:18:44.256139 DBI_RD = 0x0
697 13:18:44.256213 OTF = 0x1
698 13:18:44.259483 ===================================
699 13:18:44.266071 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:18:44.269848 nWR fixed to 40
701 13:18:44.273347 [ModeRegInit_LP4] CH0 RK0
702 13:18:44.273422 [ModeRegInit_LP4] CH0 RK1
703 13:18:44.276870 [ModeRegInit_LP4] CH1 RK0
704 13:18:44.279646 [ModeRegInit_LP4] CH1 RK1
705 13:18:44.279721 match AC timing 13
706 13:18:44.286718 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:18:44.289968 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:18:44.293252 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:18:44.300201 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:18:44.303581 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:18:44.303660 [EMI DOE] emi_dcm 0
712 13:18:44.310300 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:18:44.310376 ==
714 13:18:44.313716 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:18:44.317003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:18:44.317092 ==
717 13:18:44.323548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:18:44.326630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:18:44.337342 [CA 0] Center 37 (7~68) winsize 62
720 13:18:44.340897 [CA 1] Center 37 (6~68) winsize 63
721 13:18:44.344534 [CA 2] Center 35 (5~66) winsize 62
722 13:18:44.348249 [CA 3] Center 34 (4~65) winsize 62
723 13:18:44.351213 [CA 4] Center 34 (3~65) winsize 63
724 13:18:44.354745 [CA 5] Center 33 (3~64) winsize 62
725 13:18:44.354821
726 13:18:44.357839 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:18:44.357931
728 13:18:44.361492 [CATrainingPosCal] consider 1 rank data
729 13:18:44.364882 u2DelayCellTimex100 = 270/100 ps
730 13:18:44.368313 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 13:18:44.372539 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 13:18:44.375793 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 13:18:44.379394 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:18:44.382350 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 13:18:44.385989 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:18:44.386083
737 13:18:44.389529 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:18:44.392748
739 13:18:44.392848 [CBTSetCACLKResult] CA Dly = 33
740 13:18:44.395690 CS Dly: 5 (0~36)
741 13:18:44.395765 ==
742 13:18:44.398905 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:18:44.402462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:18:44.402544 ==
745 13:18:44.409280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:18:44.415929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:18:44.423542 [CA 0] Center 37 (6~68) winsize 63
748 13:18:44.426760 [CA 1] Center 37 (7~68) winsize 62
749 13:18:44.430354 [CA 2] Center 35 (4~66) winsize 63
750 13:18:44.433439 [CA 3] Center 35 (4~66) winsize 63
751 13:18:44.436926 [CA 4] Center 34 (3~65) winsize 63
752 13:18:44.440021 [CA 5] Center 33 (3~64) winsize 62
753 13:18:44.440113
754 13:18:44.443560 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:18:44.443635
756 13:18:44.446948 [CATrainingPosCal] consider 2 rank data
757 13:18:44.450564 u2DelayCellTimex100 = 270/100 ps
758 13:18:44.453537 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:18:44.457222 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 13:18:44.463856 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 13:18:44.466938 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:18:44.470535 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 13:18:44.473912 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:18:44.473988
765 13:18:44.477228 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:18:44.477303
767 13:18:44.480296 [CBTSetCACLKResult] CA Dly = 33
768 13:18:44.480380 CS Dly: 5 (0~37)
769 13:18:44.480439
770 13:18:44.483847 ----->DramcWriteLeveling(PI) begin...
771 13:18:44.487002 ==
772 13:18:44.487088 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:18:44.493679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:18:44.493768 ==
775 13:18:44.497288 Write leveling (Byte 0): 31 => 31
776 13:18:44.500629 Write leveling (Byte 1): 30 => 30
777 13:18:44.500704 DramcWriteLeveling(PI) end<-----
778 13:18:44.503795
779 13:18:44.503926 ==
780 13:18:44.507086 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:18:44.510778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:18:44.510855 ==
783 13:18:44.513815 [Gating] SW mode calibration
784 13:18:44.520531 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:18:44.523754 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:18:44.530578 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:18:44.533847 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 13:18:44.537647 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 13:18:44.544350 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:18:44.547285 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:18:44.550666 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:18:44.554187 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:18:44.560884 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:18:44.564610 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:18:44.567712 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:18:44.574559 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:18:44.577585 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:18:44.580896 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:18:44.587733 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:18:44.590844 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:18:44.594577 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:18:44.601324 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:18:44.604454 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 13:18:44.607936 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 13:18:44.614649 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 13:18:44.617509 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:18:44.621160 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:18:44.624539 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:18:44.631049 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:18:44.634585 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:18:44.638119 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:18:44.644675 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
813 13:18:44.647934 0 9 12 | B1->B0 | 2727 2f2f | 1 1 | (1 1) (1 1)
814 13:18:44.651392 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:18:44.658299 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:18:44.661274 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:18:44.664883 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:18:44.671581 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:18:44.675157 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 13:18:44.678119 0 10 8 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
821 13:18:44.682040 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
822 13:18:44.688238 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:18:44.691590 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:18:44.695142 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:18:44.701732 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:18:44.705525 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:18:44.708425 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:18:44.715095 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
829 13:18:44.718235 0 11 12 | B1->B0 | 3838 4343 | 0 0 | (0 0) (0 0)
830 13:18:44.722035 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:18:44.728570 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:18:44.731922 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:18:44.735425 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:18:44.738412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:18:44.745403 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:18:44.748986 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 13:18:44.751855 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:18:44.759149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:18:44.762332 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:18:44.765640 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:18:44.772099 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:18:44.775783 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:18:44.778865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:18:44.785637 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:18:44.789374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:18:44.792256 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:18:44.799263 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:18:44.802237 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:18:44.806043 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:18:44.808939 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:18:44.815725 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:18:44.819293 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 13:18:44.822400 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 13:18:44.825918 Total UI for P1: 0, mck2ui 16
855 13:18:44.829428 best dqsien dly found for B0: ( 0, 14, 8)
856 13:18:44.832945 Total UI for P1: 0, mck2ui 16
857 13:18:44.836301 best dqsien dly found for B1: ( 0, 14, 8)
858 13:18:44.839387 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 13:18:44.842630 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 13:18:44.842754
861 13:18:44.845903 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 13:18:44.852961 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 13:18:44.853039 [Gating] SW calibration Done
864 13:18:44.853100 ==
865 13:18:44.855966 Dram Type= 6, Freq= 0, CH_0, rank 0
866 13:18:44.862886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 13:18:44.862965 ==
868 13:18:44.863040 RX Vref Scan: 0
869 13:18:44.863094
870 13:18:44.866204 RX Vref 0 -> 0, step: 1
871 13:18:44.866279
872 13:18:44.869582 RX Delay -130 -> 252, step: 16
873 13:18:44.872837 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 13:18:44.876435 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 13:18:44.879846 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 13:18:44.886296 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 13:18:44.889422 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 13:18:44.893041 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 13:18:44.896199 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 13:18:44.899707 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 13:18:44.903056 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 13:18:44.909787 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 13:18:44.913400 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 13:18:44.916526 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 13:18:44.920178 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 13:18:44.923218 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 13:18:44.929811 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 13:18:44.933434 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 13:18:44.933510 ==
890 13:18:44.936988 Dram Type= 6, Freq= 0, CH_0, rank 0
891 13:18:44.940118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 13:18:44.940194 ==
893 13:18:44.940253 DQS Delay:
894 13:18:44.943906 DQS0 = 0, DQS1 = 0
895 13:18:44.943982 DQM Delay:
896 13:18:44.946569 DQM0 = 84, DQM1 = 78
897 13:18:44.946646 DQ Delay:
898 13:18:44.950113 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 13:18:44.953778 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
900 13:18:44.956874 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 13:18:44.960263 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 13:18:44.960352
903 13:18:44.960426
904 13:18:44.960481 ==
905 13:18:44.964032 Dram Type= 6, Freq= 0, CH_0, rank 0
906 13:18:44.967097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 13:18:44.967174 ==
908 13:18:44.970450
909 13:18:44.970527
910 13:18:44.970587 TX Vref Scan disable
911 13:18:44.973962 == TX Byte 0 ==
912 13:18:44.976932 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 13:18:44.980467 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 13:18:44.983897 == TX Byte 1 ==
915 13:18:44.987054 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 13:18:44.990259 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 13:18:44.990351 ==
918 13:18:44.993956 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:18:45.000591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:18:45.000698 ==
921 13:18:45.012275 TX Vref=22, minBit 2, minWin=27, winSum=438
922 13:18:45.015812 TX Vref=24, minBit 7, minWin=27, winSum=444
923 13:18:45.018982 TX Vref=26, minBit 5, minWin=27, winSum=448
924 13:18:45.022469 TX Vref=28, minBit 13, minWin=27, winSum=452
925 13:18:45.025491 TX Vref=30, minBit 3, minWin=28, winSum=457
926 13:18:45.029106 TX Vref=32, minBit 2, minWin=28, winSum=456
927 13:18:45.036039 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30
928 13:18:45.036116
929 13:18:45.038972 Final TX Range 1 Vref 30
930 13:18:45.039047
931 13:18:45.039106 ==
932 13:18:45.042644 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:18:45.046270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:18:45.046346 ==
935 13:18:45.046405
936 13:18:45.046459
937 13:18:45.049262 TX Vref Scan disable
938 13:18:45.052760 == TX Byte 0 ==
939 13:18:45.056217 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 13:18:45.059427 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 13:18:45.062922 == TX Byte 1 ==
942 13:18:45.065956 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 13:18:45.069722 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 13:18:45.069801
945 13:18:45.072534 [DATLAT]
946 13:18:45.072609 Freq=800, CH0 RK0
947 13:18:45.072668
948 13:18:45.076105 DATLAT Default: 0xa
949 13:18:45.076182 0, 0xFFFF, sum = 0
950 13:18:45.079496 1, 0xFFFF, sum = 0
951 13:18:45.079573 2, 0xFFFF, sum = 0
952 13:18:45.083157 3, 0xFFFF, sum = 0
953 13:18:45.083233 4, 0xFFFF, sum = 0
954 13:18:45.086353 5, 0xFFFF, sum = 0
955 13:18:45.086429 6, 0xFFFF, sum = 0
956 13:18:45.089409 7, 0xFFFF, sum = 0
957 13:18:45.089485 8, 0xFFFF, sum = 0
958 13:18:45.092985 9, 0x0, sum = 1
959 13:18:45.093061 10, 0x0, sum = 2
960 13:18:45.096312 11, 0x0, sum = 3
961 13:18:45.096388 12, 0x0, sum = 4
962 13:18:45.099489 best_step = 10
963 13:18:45.099564
964 13:18:45.099622 ==
965 13:18:45.102808 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:18:45.106164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:18:45.106241 ==
968 13:18:45.106300 RX Vref Scan: 1
969 13:18:45.109797
970 13:18:45.109873 Set Vref Range= 32 -> 127
971 13:18:45.109931
972 13:18:45.113256 RX Vref 32 -> 127, step: 1
973 13:18:45.113331
974 13:18:45.116626 RX Delay -95 -> 252, step: 8
975 13:18:45.116700
976 13:18:45.119721 Set Vref, RX VrefLevel [Byte0]: 32
977 13:18:45.123375 [Byte1]: 32
978 13:18:45.123449
979 13:18:45.126404 Set Vref, RX VrefLevel [Byte0]: 33
980 13:18:45.130074 [Byte1]: 33
981 13:18:45.130149
982 13:18:45.133083 Set Vref, RX VrefLevel [Byte0]: 34
983 13:18:45.136786 [Byte1]: 34
984 13:18:45.140331
985 13:18:45.140406 Set Vref, RX VrefLevel [Byte0]: 35
986 13:18:45.143419 [Byte1]: 35
987 13:18:45.148261
988 13:18:45.148336 Set Vref, RX VrefLevel [Byte0]: 36
989 13:18:45.151075 [Byte1]: 36
990 13:18:45.155302
991 13:18:45.155377 Set Vref, RX VrefLevel [Byte0]: 37
992 13:18:45.159033 [Byte1]: 37
993 13:18:45.163045
994 13:18:45.163120 Set Vref, RX VrefLevel [Byte0]: 38
995 13:18:45.166391 [Byte1]: 38
996 13:18:45.170637
997 13:18:45.170712 Set Vref, RX VrefLevel [Byte0]: 39
998 13:18:45.173589 [Byte1]: 39
999 13:18:45.178035
1000 13:18:45.178124 Set Vref, RX VrefLevel [Byte0]: 40
1001 13:18:45.181261 [Byte1]: 40
1002 13:18:45.185799
1003 13:18:45.185873 Set Vref, RX VrefLevel [Byte0]: 41
1004 13:18:45.188886 [Byte1]: 41
1005 13:18:45.193737
1006 13:18:45.193811 Set Vref, RX VrefLevel [Byte0]: 42
1007 13:18:45.196854 [Byte1]: 42
1008 13:18:45.201135
1009 13:18:45.201250 Set Vref, RX VrefLevel [Byte0]: 43
1010 13:18:45.204065 [Byte1]: 43
1011 13:18:45.208573
1012 13:18:45.208649 Set Vref, RX VrefLevel [Byte0]: 44
1013 13:18:45.211841 [Byte1]: 44
1014 13:18:45.216452
1015 13:18:45.216527 Set Vref, RX VrefLevel [Byte0]: 45
1016 13:18:45.219624 [Byte1]: 45
1017 13:18:45.224102
1018 13:18:45.224191 Set Vref, RX VrefLevel [Byte0]: 46
1019 13:18:45.227291 [Byte1]: 46
1020 13:18:45.231549
1021 13:18:45.231627 Set Vref, RX VrefLevel [Byte0]: 47
1022 13:18:45.234466 [Byte1]: 47
1023 13:18:45.238772
1024 13:18:45.238863 Set Vref, RX VrefLevel [Byte0]: 48
1025 13:18:45.242198 [Byte1]: 48
1026 13:18:45.246393
1027 13:18:45.246468 Set Vref, RX VrefLevel [Byte0]: 49
1028 13:18:45.250054 [Byte1]: 49
1029 13:18:45.254279
1030 13:18:45.254358 Set Vref, RX VrefLevel [Byte0]: 50
1031 13:18:45.257786 [Byte1]: 50
1032 13:18:45.261783
1033 13:18:45.261859 Set Vref, RX VrefLevel [Byte0]: 51
1034 13:18:45.265707 [Byte1]: 51
1035 13:18:45.269274
1036 13:18:45.269370 Set Vref, RX VrefLevel [Byte0]: 52
1037 13:18:45.272528 [Byte1]: 52
1038 13:18:45.276972
1039 13:18:45.277048 Set Vref, RX VrefLevel [Byte0]: 53
1040 13:18:45.280432 [Byte1]: 53
1041 13:18:45.284302
1042 13:18:45.284379 Set Vref, RX VrefLevel [Byte0]: 54
1043 13:18:45.287806 [Byte1]: 54
1044 13:18:45.292359
1045 13:18:45.292435 Set Vref, RX VrefLevel [Byte0]: 55
1046 13:18:45.295532 [Byte1]: 55
1047 13:18:45.299656
1048 13:18:45.299732 Set Vref, RX VrefLevel [Byte0]: 56
1049 13:18:45.303294 [Byte1]: 56
1050 13:18:45.307476
1051 13:18:45.307551 Set Vref, RX VrefLevel [Byte0]: 57
1052 13:18:45.310535 [Byte1]: 57
1053 13:18:45.315061
1054 13:18:45.315164 Set Vref, RX VrefLevel [Byte0]: 58
1055 13:18:45.318383 [Byte1]: 58
1056 13:18:45.322503
1057 13:18:45.322578 Set Vref, RX VrefLevel [Byte0]: 59
1058 13:18:45.326105 [Byte1]: 59
1059 13:18:45.330332
1060 13:18:45.330407 Set Vref, RX VrefLevel [Byte0]: 60
1061 13:18:45.333725 [Byte1]: 60
1062 13:18:45.337820
1063 13:18:45.337898 Set Vref, RX VrefLevel [Byte0]: 61
1064 13:18:45.340870 [Byte1]: 61
1065 13:18:45.345222
1066 13:18:45.345298 Set Vref, RX VrefLevel [Byte0]: 62
1067 13:18:45.348620 [Byte1]: 62
1068 13:18:45.352906
1069 13:18:45.353004 Set Vref, RX VrefLevel [Byte0]: 63
1070 13:18:45.355962 [Byte1]: 63
1071 13:18:45.360277
1072 13:18:45.360352 Set Vref, RX VrefLevel [Byte0]: 64
1073 13:18:45.363899 [Byte1]: 64
1074 13:18:45.368071
1075 13:18:45.368163 Set Vref, RX VrefLevel [Byte0]: 65
1076 13:18:45.371108 [Byte1]: 65
1077 13:18:45.375788
1078 13:18:45.375879 Set Vref, RX VrefLevel [Byte0]: 66
1079 13:18:45.378767 [Byte1]: 66
1080 13:18:45.383050
1081 13:18:45.383149 Set Vref, RX VrefLevel [Byte0]: 67
1082 13:18:45.386653 [Byte1]: 67
1083 13:18:45.391139
1084 13:18:45.391214 Set Vref, RX VrefLevel [Byte0]: 68
1085 13:18:45.394162 [Byte1]: 68
1086 13:18:45.398623
1087 13:18:45.398730 Set Vref, RX VrefLevel [Byte0]: 69
1088 13:18:45.401823 [Byte1]: 69
1089 13:18:45.406001
1090 13:18:45.406076 Set Vref, RX VrefLevel [Byte0]: 70
1091 13:18:45.409699 [Byte1]: 70
1092 13:18:45.413867
1093 13:18:45.413942 Set Vref, RX VrefLevel [Byte0]: 71
1094 13:18:45.416813 [Byte1]: 71
1095 13:18:45.421067
1096 13:18:45.421180 Set Vref, RX VrefLevel [Byte0]: 72
1097 13:18:45.424433 [Byte1]: 72
1098 13:18:45.428937
1099 13:18:45.429053 Set Vref, RX VrefLevel [Byte0]: 73
1100 13:18:45.432456 [Byte1]: 73
1101 13:18:45.436579
1102 13:18:45.436653 Set Vref, RX VrefLevel [Byte0]: 74
1103 13:18:45.440112 [Byte1]: 74
1104 13:18:45.443944
1105 13:18:45.444018 Set Vref, RX VrefLevel [Byte0]: 75
1106 13:18:45.447275 [Byte1]: 75
1107 13:18:45.451654
1108 13:18:45.451744 Set Vref, RX VrefLevel [Byte0]: 76
1109 13:18:45.455215 [Byte1]: 76
1110 13:18:45.459565
1111 13:18:45.459640 Set Vref, RX VrefLevel [Byte0]: 77
1112 13:18:45.462832 [Byte1]: 77
1113 13:18:45.466769
1114 13:18:45.466845 Final RX Vref Byte 0 = 61 to rank0
1115 13:18:45.470320 Final RX Vref Byte 1 = 58 to rank0
1116 13:18:45.473822 Final RX Vref Byte 0 = 61 to rank1
1117 13:18:45.476877 Final RX Vref Byte 1 = 58 to rank1==
1118 13:18:45.480465 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 13:18:45.483893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 13:18:45.486790 ==
1121 13:18:45.486859 DQS Delay:
1122 13:18:45.486916 DQS0 = 0, DQS1 = 0
1123 13:18:45.490597 DQM Delay:
1124 13:18:45.490672 DQM0 = 88, DQM1 = 79
1125 13:18:45.494047 DQ Delay:
1126 13:18:45.494123 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1127 13:18:45.497300 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =92
1128 13:18:45.500292 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1129 13:18:45.503812 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1130 13:18:45.503888
1131 13:18:45.503946
1132 13:18:45.514157 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1133 13:18:45.517124 CH0 RK0: MR19=606, MR18=2E15
1134 13:18:45.520686 CH0_RK0: MR19=0x606, MR18=0x2E15, DQSOSC=398, MR23=63, INC=93, DEC=62
1135 13:18:45.524351
1136 13:18:45.527314 ----->DramcWriteLeveling(PI) begin...
1137 13:18:45.527395 ==
1138 13:18:45.530812 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 13:18:45.534183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 13:18:45.534261 ==
1141 13:18:45.537726 Write leveling (Byte 0): 32 => 32
1142 13:18:45.540797 Write leveling (Byte 1): 30 => 30
1143 13:18:45.544444 DramcWriteLeveling(PI) end<-----
1144 13:18:45.544521
1145 13:18:45.544581 ==
1146 13:18:45.547895 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 13:18:45.550768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 13:18:45.550849 ==
1149 13:18:45.554251 [Gating] SW mode calibration
1150 13:18:45.561326 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 13:18:45.564381 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 13:18:45.608284 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 13:18:45.608844 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 13:18:45.609104 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 13:18:45.609188 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:18:45.609252 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:18:45.609318 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:18:45.609383 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:18:45.610140 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:18:45.610396 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:18:45.610461 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:18:45.652306 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:18:45.652878 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:18:45.653156 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:18:45.653221 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:18:45.653277 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:18:45.653371 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:18:45.653434 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:18:45.653497 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1170 13:18:45.654059 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:18:45.654138 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:18:45.696862 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:18:45.697132 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:18:45.697221 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:18:45.697460 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:18:45.697519 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:18:45.698084 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:18:45.698340 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (1 1) (0 0)
1179 13:18:45.698461 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1180 13:18:45.698558 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:18:45.698629 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:18:45.704255 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:18:45.707696 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 13:18:45.711576 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1185 13:18:45.714473 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1186 13:18:45.720912 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (0 0)
1187 13:18:45.724433 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:18:45.727432 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:18:45.734282 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:18:45.737872 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:18:45.740962 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:18:45.744525 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:18:45.751327 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1194 13:18:45.754692 0 11 8 | B1->B0 | 3131 4141 | 0 1 | (1 1) (0 0)
1195 13:18:45.757530 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1196 13:18:45.764670 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:18:45.767761 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:18:45.771227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:18:45.777876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:18:45.781453 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 13:18:45.784415 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 13:18:45.791133 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 13:18:45.794641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1204 13:18:45.797654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:18:45.804452 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:18:45.807931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:18:45.811268 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:18:45.814767 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:18:45.821519 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:18:45.825027 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:18:45.828010 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:18:45.834974 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:18:45.838114 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:18:45.841726 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:18:45.848388 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:18:45.851975 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:18:45.854785 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:18:45.861560 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 13:18:45.861670 Total UI for P1: 0, mck2ui 16
1220 13:18:45.865282 best dqsien dly found for B0: ( 0, 14, 6)
1221 13:18:45.871636 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 13:18:45.875288 Total UI for P1: 0, mck2ui 16
1223 13:18:45.878313 best dqsien dly found for B1: ( 0, 14, 8)
1224 13:18:45.881663 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1225 13:18:45.884913 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 13:18:45.884988
1227 13:18:45.888274 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 13:18:45.891747 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 13:18:45.895395 [Gating] SW calibration Done
1230 13:18:45.895470 ==
1231 13:18:45.898551 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 13:18:45.902187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 13:18:45.902263 ==
1234 13:18:45.905295 RX Vref Scan: 0
1235 13:18:45.905371
1236 13:18:45.905429 RX Vref 0 -> 0, step: 1
1237 13:18:45.905484
1238 13:18:45.908992 RX Delay -130 -> 252, step: 16
1239 13:18:45.911972 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1240 13:18:45.918948 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1241 13:18:45.921856 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1242 13:18:45.925511 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1243 13:18:45.928589 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1244 13:18:45.932087 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1245 13:18:45.938775 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1246 13:18:45.942248 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1247 13:18:45.945238 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1248 13:18:45.948826 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1249 13:18:45.952615 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 13:18:45.958803 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1251 13:18:45.962273 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1252 13:18:45.965460 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1253 13:18:45.968924 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1254 13:18:45.972316 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1255 13:18:45.972391 ==
1256 13:18:45.975532 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 13:18:45.982468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 13:18:45.982544 ==
1259 13:18:45.982603 DQS Delay:
1260 13:18:45.986025 DQS0 = 0, DQS1 = 0
1261 13:18:45.986100 DQM Delay:
1262 13:18:45.986158 DQM0 = 85, DQM1 = 75
1263 13:18:45.989525 DQ Delay:
1264 13:18:45.992445 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1265 13:18:45.995854 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1266 13:18:45.999247 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1267 13:18:46.002285 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1268 13:18:46.002361
1269 13:18:46.002420
1270 13:18:46.002473 ==
1271 13:18:46.005996 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 13:18:46.009035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 13:18:46.009111 ==
1274 13:18:46.009210
1275 13:18:46.009264
1276 13:18:46.012736 TX Vref Scan disable
1277 13:18:46.012838 == TX Byte 0 ==
1278 13:18:46.019337 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1279 13:18:46.023017 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1280 13:18:46.023094 == TX Byte 1 ==
1281 13:18:46.029341 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1282 13:18:46.032427 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1283 13:18:46.032502 ==
1284 13:18:46.035918 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 13:18:46.039244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 13:18:46.039320 ==
1287 13:18:46.053151 TX Vref=22, minBit 5, minWin=27, winSum=446
1288 13:18:46.056257 TX Vref=24, minBit 9, minWin=27, winSum=448
1289 13:18:46.059921 TX Vref=26, minBit 9, minWin=27, winSum=451
1290 13:18:46.063540 TX Vref=28, minBit 9, minWin=27, winSum=451
1291 13:18:46.066476 TX Vref=30, minBit 3, minWin=28, winSum=454
1292 13:18:46.070097 TX Vref=32, minBit 4, minWin=28, winSum=458
1293 13:18:46.076783 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 32
1294 13:18:46.076860
1295 13:18:46.080262 Final TX Range 1 Vref 32
1296 13:18:46.080329
1297 13:18:46.080385 ==
1298 13:18:46.083584 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 13:18:46.086733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 13:18:46.086814 ==
1301 13:18:46.086871
1302 13:18:46.086924
1303 13:18:46.090087 TX Vref Scan disable
1304 13:18:46.093545 == TX Byte 0 ==
1305 13:18:46.096620 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1306 13:18:46.100234 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1307 13:18:46.103627 == TX Byte 1 ==
1308 13:18:46.107096 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 13:18:46.110081 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 13:18:46.110146
1311 13:18:46.113704 [DATLAT]
1312 13:18:46.113779 Freq=800, CH0 RK1
1313 13:18:46.113844
1314 13:18:46.116715 DATLAT Default: 0xa
1315 13:18:46.116818 0, 0xFFFF, sum = 0
1316 13:18:46.120260 1, 0xFFFF, sum = 0
1317 13:18:46.120352 2, 0xFFFF, sum = 0
1318 13:18:46.123768 3, 0xFFFF, sum = 0
1319 13:18:46.123866 4, 0xFFFF, sum = 0
1320 13:18:46.126770 5, 0xFFFF, sum = 0
1321 13:18:46.126846 6, 0xFFFF, sum = 0
1322 13:18:46.130498 7, 0xFFFF, sum = 0
1323 13:18:46.130582 8, 0xFFFF, sum = 0
1324 13:18:46.133567 9, 0x0, sum = 1
1325 13:18:46.133643 10, 0x0, sum = 2
1326 13:18:46.137573 11, 0x0, sum = 3
1327 13:18:46.137639 12, 0x0, sum = 4
1328 13:18:46.140119 best_step = 10
1329 13:18:46.140180
1330 13:18:46.140281 ==
1331 13:18:46.143704 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 13:18:46.146952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 13:18:46.147052 ==
1334 13:18:46.150514 RX Vref Scan: 0
1335 13:18:46.150589
1336 13:18:46.150646 RX Vref 0 -> 0, step: 1
1337 13:18:46.150700
1338 13:18:46.153774 RX Delay -95 -> 252, step: 8
1339 13:18:46.160295 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1340 13:18:46.164009 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1341 13:18:46.166913 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1342 13:18:46.170433 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1343 13:18:46.173996 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1344 13:18:46.177272 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1345 13:18:46.183887 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1346 13:18:46.187444 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1347 13:18:46.190438 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1348 13:18:46.194259 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1349 13:18:46.197607 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1350 13:18:46.200589 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1351 13:18:46.207666 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1352 13:18:46.211220 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1353 13:18:46.214146 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1354 13:18:46.217711 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 13:18:46.217784 ==
1356 13:18:46.221272 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 13:18:46.227782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 13:18:46.227857 ==
1359 13:18:46.227914 DQS Delay:
1360 13:18:46.231383 DQS0 = 0, DQS1 = 0
1361 13:18:46.231457 DQM Delay:
1362 13:18:46.231514 DQM0 = 87, DQM1 = 77
1363 13:18:46.234440 DQ Delay:
1364 13:18:46.238147 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1365 13:18:46.241010 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1366 13:18:46.244643 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1367 13:18:46.247546 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1368 13:18:46.247620
1369 13:18:46.247678
1370 13:18:46.254810 [DQSOSCAuto] RK1, (LSB)MR18= 0x341d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1371 13:18:46.257663 CH0 RK1: MR19=606, MR18=341D
1372 13:18:46.264670 CH0_RK1: MR19=0x606, MR18=0x341D, DQSOSC=396, MR23=63, INC=94, DEC=62
1373 13:18:46.267752 [RxdqsGatingPostProcess] freq 800
1374 13:18:46.271679 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 13:18:46.274954 Pre-setting of DQS Precalculation
1376 13:18:46.281681 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 13:18:46.281756 ==
1378 13:18:46.284623 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 13:18:46.288207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 13:18:46.288307 ==
1381 13:18:46.292001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 13:18:46.298122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 13:18:46.307899 [CA 0] Center 36 (6~67) winsize 62
1384 13:18:46.311464 [CA 1] Center 36 (5~67) winsize 63
1385 13:18:46.314699 [CA 2] Center 34 (4~64) winsize 61
1386 13:18:46.318290 [CA 3] Center 33 (3~64) winsize 62
1387 13:18:46.321502 [CA 4] Center 34 (3~65) winsize 63
1388 13:18:46.324844 [CA 5] Center 33 (3~64) winsize 62
1389 13:18:46.324918
1390 13:18:46.328352 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 13:18:46.328427
1392 13:18:46.331850 [CATrainingPosCal] consider 1 rank data
1393 13:18:46.334835 u2DelayCellTimex100 = 270/100 ps
1394 13:18:46.338439 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 13:18:46.342127 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1396 13:18:46.345165 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1397 13:18:46.351894 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 13:18:46.355272 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1399 13:18:46.358319 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1400 13:18:46.358395
1401 13:18:46.361724 CA PerBit enable=1, Macro0, CA PI delay=33
1402 13:18:46.361822
1403 13:18:46.365515 [CBTSetCACLKResult] CA Dly = 33
1404 13:18:46.365591 CS Dly: 5 (0~36)
1405 13:18:46.365648 ==
1406 13:18:46.368306 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 13:18:46.375436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 13:18:46.375510 ==
1409 13:18:46.378406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 13:18:46.385085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 13:18:46.394285 [CA 0] Center 36 (5~67) winsize 63
1412 13:18:46.397222 [CA 1] Center 36 (6~67) winsize 62
1413 13:18:46.400932 [CA 2] Center 33 (3~64) winsize 62
1414 13:18:46.404341 [CA 3] Center 33 (3~64) winsize 62
1415 13:18:46.408023 [CA 4] Center 34 (3~65) winsize 63
1416 13:18:46.411095 [CA 5] Center 33 (2~64) winsize 63
1417 13:18:46.411170
1418 13:18:46.414195 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 13:18:46.414269
1420 13:18:46.417640 [CATrainingPosCal] consider 2 rank data
1421 13:18:46.421067 u2DelayCellTimex100 = 270/100 ps
1422 13:18:46.424352 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1423 13:18:46.428007 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1424 13:18:46.431171 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1425 13:18:46.434660 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 13:18:46.441494 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1427 13:18:46.444681 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1428 13:18:46.444757
1429 13:18:46.448265 CA PerBit enable=1, Macro0, CA PI delay=33
1430 13:18:46.448340
1431 13:18:46.451260 [CBTSetCACLKResult] CA Dly = 33
1432 13:18:46.451351 CS Dly: 5 (0~37)
1433 13:18:46.451408
1434 13:18:46.454858 ----->DramcWriteLeveling(PI) begin...
1435 13:18:46.454934 ==
1436 13:18:46.458034 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 13:18:46.464792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 13:18:46.464868 ==
1439 13:18:46.468197 Write leveling (Byte 0): 27 => 27
1440 13:18:46.468272 Write leveling (Byte 1): 29 => 29
1441 13:18:46.471409 DramcWriteLeveling(PI) end<-----
1442 13:18:46.471484
1443 13:18:46.471542 ==
1444 13:18:46.474794 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 13:18:46.481708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 13:18:46.481783 ==
1447 13:18:46.484905 [Gating] SW mode calibration
1448 13:18:46.491664 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 13:18:46.494683 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 13:18:46.498322 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 13:18:46.504883 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 13:18:46.508376 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 13:18:46.511413 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:18:46.518263 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:18:46.521749 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:18:46.525303 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:18:46.531988 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:18:46.535474 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:18:46.538643 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:18:46.545218 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:18:46.548746 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:18:46.552241 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:18:46.555689 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:18:46.562244 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:18:46.565753 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:18:46.568748 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:18:46.575305 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 13:18:46.578771 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:18:46.582255 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:18:46.589034 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:18:46.592289 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:18:46.595617 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:18:46.602400 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:18:46.605532 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:18:46.609052 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:18:46.615853 0 9 8 | B1->B0 | 2a2a 2525 | 0 1 | (0 0) (1 1)
1477 13:18:46.618826 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 13:18:46.622239 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:18:46.625864 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:18:46.632626 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:18:46.635666 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 13:18:46.639271 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1483 13:18:46.645782 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 13:18:46.649181 0 10 8 | B1->B0 | 2929 2e2e | 0 0 | (1 0) (0 1)
1485 13:18:46.652788 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:18:46.659433 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:18:46.662778 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:18:46.666084 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:18:46.672702 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:18:46.676381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:18:46.679127 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1492 13:18:46.686170 0 11 8 | B1->B0 | 3737 3636 | 0 0 | (0 0) (0 0)
1493 13:18:46.689576 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:18:46.692981 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:18:46.696203 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:18:46.702921 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:18:46.706561 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 13:18:46.709621 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 13:18:46.716218 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 13:18:46.719935 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 13:18:46.722906 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:18:46.729886 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:18:46.733012 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:18:46.736637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:18:46.743394 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:18:46.746832 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:18:46.749667 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:18:46.753079 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:18:46.759705 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:18:46.763273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:18:46.766624 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:18:46.773282 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:18:46.776694 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:18:46.780348 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:18:46.786454 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1516 13:18:46.790160 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 13:18:46.793699 Total UI for P1: 0, mck2ui 16
1518 13:18:46.797197 best dqsien dly found for B0: ( 0, 14, 6)
1519 13:18:46.800487 Total UI for P1: 0, mck2ui 16
1520 13:18:46.803753 best dqsien dly found for B1: ( 0, 14, 4)
1521 13:18:46.807213 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 13:18:46.810603 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 13:18:46.810679
1524 13:18:46.813462 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 13:18:46.817028 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 13:18:46.820538 [Gating] SW calibration Done
1527 13:18:46.820614 ==
1528 13:18:46.823605 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 13:18:46.827229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 13:18:46.827318 ==
1531 13:18:46.830328 RX Vref Scan: 0
1532 13:18:46.830403
1533 13:18:46.830460 RX Vref 0 -> 0, step: 1
1534 13:18:46.830531
1535 13:18:46.833915 RX Delay -130 -> 252, step: 16
1536 13:18:46.837459 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1537 13:18:46.844234 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1538 13:18:46.847230 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1539 13:18:46.850848 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1540 13:18:46.854262 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1541 13:18:46.857702 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1542 13:18:46.864278 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1543 13:18:46.867432 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1544 13:18:46.871042 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1545 13:18:46.874309 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1546 13:18:46.877843 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1547 13:18:46.881254 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1548 13:18:46.887915 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1549 13:18:46.890864 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1550 13:18:46.894536 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1551 13:18:46.898044 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1552 13:18:46.898119 ==
1553 13:18:46.901466 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 13:18:46.907931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 13:18:46.908006 ==
1556 13:18:46.908065 DQS Delay:
1557 13:18:46.911515 DQS0 = 0, DQS1 = 0
1558 13:18:46.911621 DQM Delay:
1559 13:18:46.911713 DQM0 = 80, DQM1 = 75
1560 13:18:46.914577 DQ Delay:
1561 13:18:46.918078 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1562 13:18:46.921397 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1563 13:18:46.921472 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1564 13:18:46.924864 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1565 13:18:46.928365
1566 13:18:46.928438
1567 13:18:46.928513 ==
1568 13:18:46.931432 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 13:18:46.934978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 13:18:46.935076 ==
1571 13:18:46.935162
1572 13:18:46.935245
1573 13:18:46.938394 TX Vref Scan disable
1574 13:18:46.938462 == TX Byte 0 ==
1575 13:18:46.944972 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 13:18:46.947929 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 13:18:46.948028 == TX Byte 1 ==
1578 13:18:46.955238 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1579 13:18:46.958047 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1580 13:18:46.958119 ==
1581 13:18:46.961491 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 13:18:46.964900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 13:18:46.964990 ==
1584 13:18:46.978480 TX Vref=22, minBit 8, minWin=26, winSum=434
1585 13:18:46.981738 TX Vref=24, minBit 11, minWin=26, winSum=439
1586 13:18:46.985327 TX Vref=26, minBit 10, minWin=27, winSum=449
1587 13:18:46.988240 TX Vref=28, minBit 10, minWin=27, winSum=448
1588 13:18:46.992010 TX Vref=30, minBit 10, minWin=27, winSum=452
1589 13:18:46.998625 TX Vref=32, minBit 1, minWin=28, winSum=454
1590 13:18:47.001670 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 32
1591 13:18:47.001776
1592 13:18:47.005189 Final TX Range 1 Vref 32
1593 13:18:47.005264
1594 13:18:47.005322 ==
1595 13:18:47.008756 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 13:18:47.011849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 13:18:47.011925 ==
1598 13:18:47.015254
1599 13:18:47.015341
1600 13:18:47.015415 TX Vref Scan disable
1601 13:18:47.018540 == TX Byte 0 ==
1602 13:18:47.022109 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 13:18:47.025614 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 13:18:47.029049 == TX Byte 1 ==
1605 13:18:47.032615 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 13:18:47.035430 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 13:18:47.035505
1608 13:18:47.038990 [DATLAT]
1609 13:18:47.039081 Freq=800, CH1 RK0
1610 13:18:47.039171
1611 13:18:47.042536 DATLAT Default: 0xa
1612 13:18:47.042611 0, 0xFFFF, sum = 0
1613 13:18:47.045616 1, 0xFFFF, sum = 0
1614 13:18:47.045693 2, 0xFFFF, sum = 0
1615 13:18:47.049361 3, 0xFFFF, sum = 0
1616 13:18:47.049437 4, 0xFFFF, sum = 0
1617 13:18:47.052283 5, 0xFFFF, sum = 0
1618 13:18:47.052359 6, 0xFFFF, sum = 0
1619 13:18:47.055891 7, 0xFFFF, sum = 0
1620 13:18:47.055970 8, 0xFFFF, sum = 0
1621 13:18:47.058902 9, 0x0, sum = 1
1622 13:18:47.059010 10, 0x0, sum = 2
1623 13:18:47.062397 11, 0x0, sum = 3
1624 13:18:47.062475 12, 0x0, sum = 4
1625 13:18:47.065678 best_step = 10
1626 13:18:47.065753
1627 13:18:47.065811 ==
1628 13:18:47.069188 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 13:18:47.072903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 13:18:47.073011 ==
1631 13:18:47.075983 RX Vref Scan: 1
1632 13:18:47.076057
1633 13:18:47.076115 Set Vref Range= 32 -> 127
1634 13:18:47.076212
1635 13:18:47.079182 RX Vref 32 -> 127, step: 1
1636 13:18:47.079256
1637 13:18:47.082682 RX Delay -111 -> 252, step: 8
1638 13:18:47.082773
1639 13:18:47.086175 Set Vref, RX VrefLevel [Byte0]: 32
1640 13:18:47.089573 [Byte1]: 32
1641 13:18:47.089650
1642 13:18:47.092957 Set Vref, RX VrefLevel [Byte0]: 33
1643 13:18:47.095897 [Byte1]: 33
1644 13:18:47.096003
1645 13:18:47.099423 Set Vref, RX VrefLevel [Byte0]: 34
1646 13:18:47.102484 [Byte1]: 34
1647 13:18:47.106612
1648 13:18:47.106744 Set Vref, RX VrefLevel [Byte0]: 35
1649 13:18:47.110165 [Byte1]: 35
1650 13:18:47.114410
1651 13:18:47.114487 Set Vref, RX VrefLevel [Byte0]: 36
1652 13:18:47.118238 [Byte1]: 36
1653 13:18:47.122213
1654 13:18:47.122356 Set Vref, RX VrefLevel [Byte0]: 37
1655 13:18:47.125649 [Byte1]: 37
1656 13:18:47.129839
1657 13:18:47.129950 Set Vref, RX VrefLevel [Byte0]: 38
1658 13:18:47.132829 [Byte1]: 38
1659 13:18:47.137659
1660 13:18:47.137760 Set Vref, RX VrefLevel [Byte0]: 39
1661 13:18:47.140485 [Byte1]: 39
1662 13:18:47.144795
1663 13:18:47.144891 Set Vref, RX VrefLevel [Byte0]: 40
1664 13:18:47.148103 [Byte1]: 40
1665 13:18:47.152782
1666 13:18:47.152887 Set Vref, RX VrefLevel [Byte0]: 41
1667 13:18:47.155823 [Byte1]: 41
1668 13:18:47.160119
1669 13:18:47.160215 Set Vref, RX VrefLevel [Byte0]: 42
1670 13:18:47.163805 [Byte1]: 42
1671 13:18:47.168062
1672 13:18:47.168163 Set Vref, RX VrefLevel [Byte0]: 43
1673 13:18:47.171279 [Byte1]: 43
1674 13:18:47.175773
1675 13:18:47.175869 Set Vref, RX VrefLevel [Byte0]: 44
1676 13:18:47.178790 [Byte1]: 44
1677 13:18:47.183093
1678 13:18:47.183185 Set Vref, RX VrefLevel [Byte0]: 45
1679 13:18:47.186776 [Byte1]: 45
1680 13:18:47.191006
1681 13:18:47.191101 Set Vref, RX VrefLevel [Byte0]: 46
1682 13:18:47.194437 [Byte1]: 46
1683 13:18:47.198739
1684 13:18:47.198845 Set Vref, RX VrefLevel [Byte0]: 47
1685 13:18:47.201931 [Byte1]: 47
1686 13:18:47.206167
1687 13:18:47.206243 Set Vref, RX VrefLevel [Byte0]: 48
1688 13:18:47.209792 [Byte1]: 48
1689 13:18:47.213983
1690 13:18:47.214085 Set Vref, RX VrefLevel [Byte0]: 49
1691 13:18:47.217017 [Byte1]: 49
1692 13:18:47.221284
1693 13:18:47.221357 Set Vref, RX VrefLevel [Byte0]: 50
1694 13:18:47.225009 [Byte1]: 50
1695 13:18:47.229267
1696 13:18:47.229337 Set Vref, RX VrefLevel [Byte0]: 51
1697 13:18:47.232273 [Byte1]: 51
1698 13:18:47.236602
1699 13:18:47.236672 Set Vref, RX VrefLevel [Byte0]: 52
1700 13:18:47.240361 [Byte1]: 52
1701 13:18:47.244573
1702 13:18:47.244666 Set Vref, RX VrefLevel [Byte0]: 53
1703 13:18:47.247631 [Byte1]: 53
1704 13:18:47.252246
1705 13:18:47.252323 Set Vref, RX VrefLevel [Byte0]: 54
1706 13:18:47.255644 [Byte1]: 54
1707 13:18:47.259993
1708 13:18:47.260069 Set Vref, RX VrefLevel [Byte0]: 55
1709 13:18:47.263352 [Byte1]: 55
1710 13:18:47.267683
1711 13:18:47.267760 Set Vref, RX VrefLevel [Byte0]: 56
1712 13:18:47.270796 [Byte1]: 56
1713 13:18:47.274967
1714 13:18:47.275044 Set Vref, RX VrefLevel [Byte0]: 57
1715 13:18:47.278324 [Byte1]: 57
1716 13:18:47.282786
1717 13:18:47.282862 Set Vref, RX VrefLevel [Byte0]: 58
1718 13:18:47.286377 [Byte1]: 58
1719 13:18:47.290731
1720 13:18:47.290813 Set Vref, RX VrefLevel [Byte0]: 59
1721 13:18:47.293816 [Byte1]: 59
1722 13:18:47.297828
1723 13:18:47.297915 Set Vref, RX VrefLevel [Byte0]: 60
1724 13:18:47.301303 [Byte1]: 60
1725 13:18:47.305726
1726 13:18:47.305804 Set Vref, RX VrefLevel [Byte0]: 61
1727 13:18:47.309251 [Byte1]: 61
1728 13:18:47.313043
1729 13:18:47.313146 Set Vref, RX VrefLevel [Byte0]: 62
1730 13:18:47.316597 [Byte1]: 62
1731 13:18:47.320834
1732 13:18:47.320925 Set Vref, RX VrefLevel [Byte0]: 63
1733 13:18:47.324453 [Byte1]: 63
1734 13:18:47.328705
1735 13:18:47.328774 Set Vref, RX VrefLevel [Byte0]: 64
1736 13:18:47.331747 [Byte1]: 64
1737 13:18:47.335985
1738 13:18:47.336051 Set Vref, RX VrefLevel [Byte0]: 65
1739 13:18:47.339581 [Byte1]: 65
1740 13:18:47.344114
1741 13:18:47.344182 Set Vref, RX VrefLevel [Byte0]: 66
1742 13:18:47.347543 [Byte1]: 66
1743 13:18:47.351876
1744 13:18:47.351967 Set Vref, RX VrefLevel [Byte0]: 67
1745 13:18:47.354816 [Byte1]: 67
1746 13:18:47.358949
1747 13:18:47.359014 Set Vref, RX VrefLevel [Byte0]: 68
1748 13:18:47.362494 [Byte1]: 68
1749 13:18:47.366645
1750 13:18:47.366741 Set Vref, RX VrefLevel [Byte0]: 69
1751 13:18:47.369993 [Byte1]: 69
1752 13:18:47.374757
1753 13:18:47.374848 Set Vref, RX VrefLevel [Byte0]: 70
1754 13:18:47.377747 [Byte1]: 70
1755 13:18:47.381999
1756 13:18:47.382091 Set Vref, RX VrefLevel [Byte0]: 71
1757 13:18:47.385303 [Byte1]: 71
1758 13:18:47.389697
1759 13:18:47.389765 Set Vref, RX VrefLevel [Byte0]: 72
1760 13:18:47.392730 [Byte1]: 72
1761 13:18:47.397679
1762 13:18:47.397771 Set Vref, RX VrefLevel [Byte0]: 73
1763 13:18:47.400693 [Byte1]: 73
1764 13:18:47.404905
1765 13:18:47.404996 Set Vref, RX VrefLevel [Byte0]: 74
1766 13:18:47.408542 [Byte1]: 74
1767 13:18:47.412482
1768 13:18:47.412581 Set Vref, RX VrefLevel [Byte0]: 75
1769 13:18:47.415783 [Byte1]: 75
1770 13:18:47.420297
1771 13:18:47.420395 Set Vref, RX VrefLevel [Byte0]: 76
1772 13:18:47.423512 [Byte1]: 76
1773 13:18:47.427774
1774 13:18:47.427871 Set Vref, RX VrefLevel [Byte0]: 77
1775 13:18:47.431598 [Byte1]: 77
1776 13:18:47.435795
1777 13:18:47.435891 Set Vref, RX VrefLevel [Byte0]: 78
1778 13:18:47.438857 [Byte1]: 78
1779 13:18:47.443128
1780 13:18:47.443203 Final RX Vref Byte 0 = 66 to rank0
1781 13:18:47.446738 Final RX Vref Byte 1 = 60 to rank0
1782 13:18:47.449753 Final RX Vref Byte 0 = 66 to rank1
1783 13:18:47.453667 Final RX Vref Byte 1 = 60 to rank1==
1784 13:18:47.456475 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 13:18:47.460105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 13:18:47.463149 ==
1787 13:18:47.463244 DQS Delay:
1788 13:18:47.463328 DQS0 = 0, DQS1 = 0
1789 13:18:47.467049 DQM Delay:
1790 13:18:47.467138 DQM0 = 82, DQM1 = 74
1791 13:18:47.470099 DQ Delay:
1792 13:18:47.470165 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1793 13:18:47.473395 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1794 13:18:47.476831 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1795 13:18:47.480358 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1796 13:18:47.480441
1797 13:18:47.483418
1798 13:18:47.490526 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1799 13:18:47.493818 CH1 RK0: MR19=606, MR18=2E02
1800 13:18:47.500219 CH1_RK0: MR19=0x606, MR18=0x2E02, DQSOSC=398, MR23=63, INC=93, DEC=62
1801 13:18:47.500308
1802 13:18:47.503920 ----->DramcWriteLeveling(PI) begin...
1803 13:18:47.504006 ==
1804 13:18:47.506853 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 13:18:47.510547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 13:18:47.510620 ==
1807 13:18:47.514115 Write leveling (Byte 0): 29 => 29
1808 13:18:47.517068 Write leveling (Byte 1): 29 => 29
1809 13:18:47.520632 DramcWriteLeveling(PI) end<-----
1810 13:18:47.520716
1811 13:18:47.520795 ==
1812 13:18:47.524060 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 13:18:47.527116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 13:18:47.527182 ==
1815 13:18:47.530393 [Gating] SW mode calibration
1816 13:18:47.537499 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 13:18:47.540520 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 13:18:47.547180 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1819 13:18:47.550840 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1820 13:18:47.553803 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:18:47.560531 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:18:47.564508 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:18:47.567568 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:18:47.573992 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:18:47.577653 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:18:47.580943 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:18:47.587650 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:18:47.591241 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:18:47.594204 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:18:47.597810 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:18:47.604228 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:18:47.607933 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:18:47.611531 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:18:47.618157 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1835 13:18:47.621085 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:18:47.624806 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1837 13:18:47.631444 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:18:47.634534 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:18:47.638273 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:18:47.644629 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:18:47.648214 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:18:47.651282 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:18:47.658078 0 9 4 | B1->B0 | 2322 2828 | 1 0 | (0 0) (0 0)
1844 13:18:47.661637 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1845 13:18:47.664695 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1846 13:18:47.668381 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 13:18:47.674760 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 13:18:47.678551 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 13:18:47.681604 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 13:18:47.688151 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 13:18:47.691491 0 10 4 | B1->B0 | 2f2f 2e2e | 0 0 | (0 1) (0 1)
1852 13:18:47.694875 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:18:47.701407 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:18:47.704973 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:18:47.708352 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:18:47.715337 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:18:47.718173 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:18:47.721726 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:18:47.728268 0 11 4 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
1860 13:18:47.731863 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1861 13:18:47.734955 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:18:47.738642 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 13:18:47.745064 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 13:18:47.748483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 13:18:47.751942 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 13:18:47.758511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 13:18:47.761670 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1868 13:18:47.765181 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1869 13:18:47.771851 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:18:47.774813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:18:47.778358 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:18:47.785173 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:18:47.788812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:18:47.791635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:18:47.798294 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:18:47.801673 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:18:47.805028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:18:47.811930 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:18:47.815381 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:18:47.818670 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:18:47.821924 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 13:18:47.828705 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 13:18:47.832219 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1884 13:18:47.835627 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 13:18:47.838706 Total UI for P1: 0, mck2ui 16
1886 13:18:47.842315 best dqsien dly found for B0: ( 0, 14, 4)
1887 13:18:47.845425 Total UI for P1: 0, mck2ui 16
1888 13:18:47.848767 best dqsien dly found for B1: ( 0, 14, 6)
1889 13:18:47.852182 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1890 13:18:47.855704 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1891 13:18:47.855772
1892 13:18:47.859413 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 13:18:47.865585 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1894 13:18:47.865653 [Gating] SW calibration Done
1895 13:18:47.865711 ==
1896 13:18:47.869110 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 13:18:47.875821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 13:18:47.875917 ==
1899 13:18:47.875999 RX Vref Scan: 0
1900 13:18:47.876086
1901 13:18:47.878926 RX Vref 0 -> 0, step: 1
1902 13:18:47.878989
1903 13:18:47.882510 RX Delay -130 -> 252, step: 16
1904 13:18:47.886126 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1905 13:18:47.889784 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1906 13:18:47.892793 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1907 13:18:47.895841 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1908 13:18:47.903171 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1909 13:18:47.906512 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1910 13:18:47.909543 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1911 13:18:47.912992 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1912 13:18:47.916160 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1913 13:18:47.919497 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1914 13:18:47.926743 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1915 13:18:47.929809 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1916 13:18:47.932914 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1917 13:18:47.936326 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1918 13:18:47.942899 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1919 13:18:47.946669 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1920 13:18:47.946765 ==
1921 13:18:47.949706 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 13:18:47.953276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 13:18:47.953343 ==
1924 13:18:47.953399 DQS Delay:
1925 13:18:47.956165 DQS0 = 0, DQS1 = 0
1926 13:18:47.956248 DQM Delay:
1927 13:18:47.959981 DQM0 = 80, DQM1 = 78
1928 13:18:47.960067 DQ Delay:
1929 13:18:47.963370 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1930 13:18:47.966208 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1931 13:18:47.969581 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1932 13:18:47.973496 DQ12 =85, DQ13 =93, DQ14 =85, DQ15 =85
1933 13:18:47.973560
1934 13:18:47.973615
1935 13:18:47.973670 ==
1936 13:18:47.976518 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 13:18:47.980179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 13:18:47.980268 ==
1939 13:18:47.983376
1940 13:18:47.983455
1941 13:18:47.983515 TX Vref Scan disable
1942 13:18:47.986806 == TX Byte 0 ==
1943 13:18:47.990240 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1944 13:18:47.993450 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1945 13:18:47.996509 == TX Byte 1 ==
1946 13:18:47.999999 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1947 13:18:48.003636 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1948 13:18:48.003714 ==
1949 13:18:48.006691 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 13:18:48.013483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 13:18:48.013559 ==
1952 13:18:48.025011 TX Vref=22, minBit 10, minWin=26, winSum=441
1953 13:18:48.028343 TX Vref=24, minBit 0, minWin=27, winSum=448
1954 13:18:48.031734 TX Vref=26, minBit 13, minWin=27, winSum=451
1955 13:18:48.034990 TX Vref=28, minBit 2, minWin=28, winSum=452
1956 13:18:48.038446 TX Vref=30, minBit 1, minWin=28, winSum=453
1957 13:18:48.041693 TX Vref=32, minBit 8, minWin=28, winSum=456
1958 13:18:48.048192 [TxChooseVref] Worse bit 8, Min win 28, Win sum 456, Final Vref 32
1959 13:18:48.048268
1960 13:18:48.051826 Final TX Range 1 Vref 32
1961 13:18:48.051901
1962 13:18:48.051960 ==
1963 13:18:48.054932 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 13:18:48.058475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 13:18:48.058550 ==
1966 13:18:48.058609
1967 13:18:48.058661
1968 13:18:48.061595 TX Vref Scan disable
1969 13:18:48.065041 == TX Byte 0 ==
1970 13:18:48.068496 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1971 13:18:48.072110 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1972 13:18:48.075778 == TX Byte 1 ==
1973 13:18:48.078676 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 13:18:48.082371 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 13:18:48.082447
1976 13:18:48.085451 [DATLAT]
1977 13:18:48.085525 Freq=800, CH1 RK1
1978 13:18:48.085583
1979 13:18:48.088539 DATLAT Default: 0xa
1980 13:18:48.088613 0, 0xFFFF, sum = 0
1981 13:18:48.092082 1, 0xFFFF, sum = 0
1982 13:18:48.092158 2, 0xFFFF, sum = 0
1983 13:18:48.095120 3, 0xFFFF, sum = 0
1984 13:18:48.095198 4, 0xFFFF, sum = 0
1985 13:18:48.098758 5, 0xFFFF, sum = 0
1986 13:18:48.098834 6, 0xFFFF, sum = 0
1987 13:18:48.101801 7, 0xFFFF, sum = 0
1988 13:18:48.101876 8, 0xFFFF, sum = 0
1989 13:18:48.105619 9, 0x0, sum = 1
1990 13:18:48.105694 10, 0x0, sum = 2
1991 13:18:48.108994 11, 0x0, sum = 3
1992 13:18:48.109071 12, 0x0, sum = 4
1993 13:18:48.112096 best_step = 10
1994 13:18:48.112187
1995 13:18:48.112246 ==
1996 13:18:48.115737 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 13:18:48.118653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 13:18:48.118745 ==
1999 13:18:48.122382 RX Vref Scan: 0
2000 13:18:48.122456
2001 13:18:48.122513 RX Vref 0 -> 0, step: 1
2002 13:18:48.122568
2003 13:18:48.125399 RX Delay -95 -> 252, step: 8
2004 13:18:48.129007 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2005 13:18:48.135242 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2006 13:18:48.138754 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2007 13:18:48.142332 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2008 13:18:48.145429 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2009 13:18:48.149057 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2010 13:18:48.156175 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2011 13:18:48.158866 iDelay=201, Bit 7, Center 76 (-31 ~ 184) 216
2012 13:18:48.162223 iDelay=201, Bit 8, Center 68 (-47 ~ 184) 232
2013 13:18:48.165473 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2014 13:18:48.169201 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2015 13:18:48.176044 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2016 13:18:48.179053 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2017 13:18:48.182840 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2018 13:18:48.185921 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2019 13:18:48.188955 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2020 13:18:48.189031 ==
2021 13:18:48.192674 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 13:18:48.199780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 13:18:48.199886 ==
2024 13:18:48.199943 DQS Delay:
2025 13:18:48.202686 DQS0 = 0, DQS1 = 0
2026 13:18:48.202763 DQM Delay:
2027 13:18:48.202822 DQM0 = 79, DQM1 = 76
2028 13:18:48.206359 DQ Delay:
2029 13:18:48.209441 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =80
2030 13:18:48.212983 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
2031 13:18:48.216006 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2032 13:18:48.219793 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2033 13:18:48.219868
2034 13:18:48.219926
2035 13:18:48.226332 [DQSOSCAuto] RK1, (LSB)MR18= 0x2530, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2036 13:18:48.229560 CH1 RK1: MR19=606, MR18=2530
2037 13:18:48.236388 CH1_RK1: MR19=0x606, MR18=0x2530, DQSOSC=397, MR23=63, INC=93, DEC=62
2038 13:18:48.239877 [RxdqsGatingPostProcess] freq 800
2039 13:18:48.242740 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 13:18:48.246184 Pre-setting of DQS Precalculation
2041 13:18:48.252775 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 13:18:48.259864 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 13:18:48.266120 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 13:18:48.266198
2045 13:18:48.266290
2046 13:18:48.269538 [Calibration Summary] 1600 Mbps
2047 13:18:48.269629 CH 0, Rank 0
2048 13:18:48.272713 SW Impedance : PASS
2049 13:18:48.276243 DUTY Scan : NO K
2050 13:18:48.276313 ZQ Calibration : PASS
2051 13:18:48.279735 Jitter Meter : NO K
2052 13:18:48.279824 CBT Training : PASS
2053 13:18:48.283179 Write leveling : PASS
2054 13:18:48.286194 RX DQS gating : PASS
2055 13:18:48.286259 RX DQ/DQS(RDDQC) : PASS
2056 13:18:48.289912 TX DQ/DQS : PASS
2057 13:18:48.292909 RX DATLAT : PASS
2058 13:18:48.292984 RX DQ/DQS(Engine): PASS
2059 13:18:48.296530 TX OE : NO K
2060 13:18:48.296607 All Pass.
2061 13:18:48.296660
2062 13:18:48.299507 CH 0, Rank 1
2063 13:18:48.299564 SW Impedance : PASS
2064 13:18:48.302986 DUTY Scan : NO K
2065 13:18:48.306407 ZQ Calibration : PASS
2066 13:18:48.306495 Jitter Meter : NO K
2067 13:18:48.310149 CBT Training : PASS
2068 13:18:48.313150 Write leveling : PASS
2069 13:18:48.313239 RX DQS gating : PASS
2070 13:18:48.316263 RX DQ/DQS(RDDQC) : PASS
2071 13:18:48.316337 TX DQ/DQS : PASS
2072 13:18:48.319920 RX DATLAT : PASS
2073 13:18:48.323478 RX DQ/DQS(Engine): PASS
2074 13:18:48.323552 TX OE : NO K
2075 13:18:48.326449 All Pass.
2076 13:18:48.326523
2077 13:18:48.326580 CH 1, Rank 0
2078 13:18:48.329947 SW Impedance : PASS
2079 13:18:48.330046 DUTY Scan : NO K
2080 13:18:48.333688 ZQ Calibration : PASS
2081 13:18:48.336597 Jitter Meter : NO K
2082 13:18:48.336685 CBT Training : PASS
2083 13:18:48.339724 Write leveling : PASS
2084 13:18:48.343303 RX DQS gating : PASS
2085 13:18:48.343391 RX DQ/DQS(RDDQC) : PASS
2086 13:18:48.346807 TX DQ/DQS : PASS
2087 13:18:48.346882 RX DATLAT : PASS
2088 13:18:48.350019 RX DQ/DQS(Engine): PASS
2089 13:18:48.353565 TX OE : NO K
2090 13:18:48.353646 All Pass.
2091 13:18:48.353741
2092 13:18:48.353798 CH 1, Rank 1
2093 13:18:48.356499 SW Impedance : PASS
2094 13:18:48.360107 DUTY Scan : NO K
2095 13:18:48.360184 ZQ Calibration : PASS
2096 13:18:48.363499 Jitter Meter : NO K
2097 13:18:48.367016 CBT Training : PASS
2098 13:18:48.367090 Write leveling : PASS
2099 13:18:48.370029 RX DQS gating : PASS
2100 13:18:48.373651 RX DQ/DQS(RDDQC) : PASS
2101 13:18:48.373726 TX DQ/DQS : PASS
2102 13:18:48.376587 RX DATLAT : PASS
2103 13:18:48.380092 RX DQ/DQS(Engine): PASS
2104 13:18:48.380167 TX OE : NO K
2105 13:18:48.380225 All Pass.
2106 13:18:48.383317
2107 13:18:48.383416 DramC Write-DBI off
2108 13:18:48.387101 PER_BANK_REFRESH: Hybrid Mode
2109 13:18:48.387203 TX_TRACKING: ON
2110 13:18:48.390031 [GetDramInforAfterCalByMRR] Vendor 6.
2111 13:18:48.393550 [GetDramInforAfterCalByMRR] Revision 606.
2112 13:18:48.400233 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 13:18:48.400308 MR0 0x3b3b
2114 13:18:48.400366 MR8 0x5151
2115 13:18:48.403879 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 13:18:48.403953
2117 13:18:48.406912 MR0 0x3b3b
2118 13:18:48.406986 MR8 0x5151
2119 13:18:48.410524 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 13:18:48.410599
2121 13:18:48.420838 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 13:18:48.423823 [FAST_K] Save calibration result to emmc
2123 13:18:48.427479 [FAST_K] Save calibration result to emmc
2124 13:18:48.430412 dram_init: config_dvfs: 1
2125 13:18:48.434089 dramc_set_vcore_voltage set vcore to 662500
2126 13:18:48.434164 Read voltage for 1200, 2
2127 13:18:48.437766 Vio18 = 0
2128 13:18:48.437841 Vcore = 662500
2129 13:18:48.437900 Vdram = 0
2130 13:18:48.440826 Vddq = 0
2131 13:18:48.440928 Vmddr = 0
2132 13:18:48.444297 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 13:18:48.450961 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 13:18:48.454026 MEM_TYPE=3, freq_sel=15
2135 13:18:48.457485 sv_algorithm_assistance_LP4_1600
2136 13:18:48.460771 ============ PULL DRAM RESETB DOWN ============
2137 13:18:48.464287 ========== PULL DRAM RESETB DOWN end =========
2138 13:18:48.467667 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 13:18:48.470930 ===================================
2140 13:18:48.473923 LPDDR4 DRAM CONFIGURATION
2141 13:18:48.477581 ===================================
2142 13:18:48.480690 EX_ROW_EN[0] = 0x0
2143 13:18:48.480752 EX_ROW_EN[1] = 0x0
2144 13:18:48.484267 LP4Y_EN = 0x0
2145 13:18:48.484343 WORK_FSP = 0x0
2146 13:18:48.487737 WL = 0x4
2147 13:18:48.487823 RL = 0x4
2148 13:18:48.490736 BL = 0x2
2149 13:18:48.490829 RPST = 0x0
2150 13:18:48.494108 RD_PRE = 0x0
2151 13:18:48.494170 WR_PRE = 0x1
2152 13:18:48.497856 WR_PST = 0x0
2153 13:18:48.497949 DBI_WR = 0x0
2154 13:18:48.500699 DBI_RD = 0x0
2155 13:18:48.500760 OTF = 0x1
2156 13:18:48.504010 ===================================
2157 13:18:48.507746 ===================================
2158 13:18:48.511130 ANA top config
2159 13:18:48.514097 ===================================
2160 13:18:48.517594 DLL_ASYNC_EN = 0
2161 13:18:48.517658 ALL_SLAVE_EN = 0
2162 13:18:48.521107 NEW_RANK_MODE = 1
2163 13:18:48.524234 DLL_IDLE_MODE = 1
2164 13:18:48.527973 LP45_APHY_COMB_EN = 1
2165 13:18:48.528034 TX_ODT_DIS = 1
2166 13:18:48.530988 NEW_8X_MODE = 1
2167 13:18:48.534828 ===================================
2168 13:18:48.537849 ===================================
2169 13:18:48.541516 data_rate = 2400
2170 13:18:48.544562 CKR = 1
2171 13:18:48.547737 DQ_P2S_RATIO = 8
2172 13:18:48.551247 ===================================
2173 13:18:48.551349 CA_P2S_RATIO = 8
2174 13:18:48.554518 DQ_CA_OPEN = 0
2175 13:18:48.557949 DQ_SEMI_OPEN = 0
2176 13:18:48.561511 CA_SEMI_OPEN = 0
2177 13:18:48.564896 CA_FULL_RATE = 0
2178 13:18:48.568150 DQ_CKDIV4_EN = 0
2179 13:18:48.568245 CA_CKDIV4_EN = 0
2180 13:18:48.571465 CA_PREDIV_EN = 0
2181 13:18:48.575074 PH8_DLY = 17
2182 13:18:48.578062 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 13:18:48.581743 DQ_AAMCK_DIV = 4
2184 13:18:48.581817 CA_AAMCK_DIV = 4
2185 13:18:48.585370 CA_ADMCK_DIV = 4
2186 13:18:48.588207 DQ_TRACK_CA_EN = 0
2187 13:18:48.591751 CA_PICK = 1200
2188 13:18:48.595445 CA_MCKIO = 1200
2189 13:18:48.598485 MCKIO_SEMI = 0
2190 13:18:48.602085 PLL_FREQ = 2366
2191 13:18:48.602160 DQ_UI_PI_RATIO = 32
2192 13:18:48.605555 CA_UI_PI_RATIO = 0
2193 13:18:48.608752 ===================================
2194 13:18:48.612185 ===================================
2195 13:18:48.615706 memory_type:LPDDR4
2196 13:18:48.618757 GP_NUM : 10
2197 13:18:48.618834 SRAM_EN : 1
2198 13:18:48.621821 MD32_EN : 0
2199 13:18:48.625267 ===================================
2200 13:18:48.625342 [ANA_INIT] >>>>>>>>>>>>>>
2201 13:18:48.628922 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 13:18:48.632036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 13:18:48.635670 ===================================
2204 13:18:48.638711 data_rate = 2400,PCW = 0X5b00
2205 13:18:48.641752 ===================================
2206 13:18:48.645329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 13:18:48.651911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 13:18:48.655781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 13:18:48.662032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 13:18:48.665319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 13:18:48.668723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 13:18:48.668798 [ANA_INIT] flow start
2213 13:18:48.672093 [ANA_INIT] PLL >>>>>>>>
2214 13:18:48.675793 [ANA_INIT] PLL <<<<<<<<
2215 13:18:48.678904 [ANA_INIT] MIDPI >>>>>>>>
2216 13:18:48.678979 [ANA_INIT] MIDPI <<<<<<<<
2217 13:18:48.682422 [ANA_INIT] DLL >>>>>>>>
2218 13:18:48.685748 [ANA_INIT] DLL <<<<<<<<
2219 13:18:48.685823 [ANA_INIT] flow end
2220 13:18:48.688875 ============ LP4 DIFF to SE enter ============
2221 13:18:48.696019 ============ LP4 DIFF to SE exit ============
2222 13:18:48.696095 [ANA_INIT] <<<<<<<<<<<<<
2223 13:18:48.699032 [Flow] Enable top DCM control >>>>>
2224 13:18:48.702205 [Flow] Enable top DCM control <<<<<
2225 13:18:48.705737 Enable DLL master slave shuffle
2226 13:18:48.712278 ==============================================================
2227 13:18:48.712386 Gating Mode config
2228 13:18:48.719043 ==============================================================
2229 13:18:48.722709 Config description:
2230 13:18:48.729524 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 13:18:48.735973 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 13:18:48.742613 SELPH_MODE 0: By rank 1: By Phase
2233 13:18:48.746177 ==============================================================
2234 13:18:48.749300 GAT_TRACK_EN = 1
2235 13:18:48.752891 RX_GATING_MODE = 2
2236 13:18:48.755927 RX_GATING_TRACK_MODE = 2
2237 13:18:48.759726 SELPH_MODE = 1
2238 13:18:48.763171 PICG_EARLY_EN = 1
2239 13:18:48.766139 VALID_LAT_VALUE = 1
2240 13:18:48.769428 ==============================================================
2241 13:18:48.773224 Enter into Gating configuration >>>>
2242 13:18:48.776079 Exit from Gating configuration <<<<
2243 13:18:48.779687 Enter into DVFS_PRE_config >>>>>
2244 13:18:48.793491 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 13:18:48.796914 Exit from DVFS_PRE_config <<<<<
2246 13:18:48.797010 Enter into PICG configuration >>>>
2247 13:18:48.800035 Exit from PICG configuration <<<<
2248 13:18:48.803158 [RX_INPUT] configuration >>>>>
2249 13:18:48.806437 [RX_INPUT] configuration <<<<<
2250 13:18:48.813682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 13:18:48.816477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 13:18:48.823332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 13:18:48.830193 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 13:18:48.836659 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 13:18:48.843252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 13:18:48.846942 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 13:18:48.849884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 13:18:48.853542 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 13:18:48.860110 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 13:18:48.863293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 13:18:48.866926 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 13:18:48.870030 ===================================
2263 13:18:48.873545 LPDDR4 DRAM CONFIGURATION
2264 13:18:48.877007 ===================================
2265 13:18:48.877122 EX_ROW_EN[0] = 0x0
2266 13:18:48.880415 EX_ROW_EN[1] = 0x0
2267 13:18:48.880486 LP4Y_EN = 0x0
2268 13:18:48.883244 WORK_FSP = 0x0
2269 13:18:48.886716 WL = 0x4
2270 13:18:48.886805 RL = 0x4
2271 13:18:48.890182 BL = 0x2
2272 13:18:48.890260 RPST = 0x0
2273 13:18:48.893715 RD_PRE = 0x0
2274 13:18:48.893843 WR_PRE = 0x1
2275 13:18:48.896814 WR_PST = 0x0
2276 13:18:48.896949 DBI_WR = 0x0
2277 13:18:48.900449 DBI_RD = 0x0
2278 13:18:48.900540 OTF = 0x1
2279 13:18:48.903320 ===================================
2280 13:18:48.906787 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 13:18:48.910264 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 13:18:48.916908 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 13:18:48.920201 ===================================
2284 13:18:48.923908 LPDDR4 DRAM CONFIGURATION
2285 13:18:48.927101 ===================================
2286 13:18:48.927170 EX_ROW_EN[0] = 0x10
2287 13:18:48.930547 EX_ROW_EN[1] = 0x0
2288 13:18:48.930612 LP4Y_EN = 0x0
2289 13:18:48.933857 WORK_FSP = 0x0
2290 13:18:48.933922 WL = 0x4
2291 13:18:48.937213 RL = 0x4
2292 13:18:48.937277 BL = 0x2
2293 13:18:48.940741 RPST = 0x0
2294 13:18:48.940841 RD_PRE = 0x0
2295 13:18:48.944117 WR_PRE = 0x1
2296 13:18:48.944218 WR_PST = 0x0
2297 13:18:48.947161 DBI_WR = 0x0
2298 13:18:48.947263 DBI_RD = 0x0
2299 13:18:48.950783 OTF = 0x1
2300 13:18:48.953778 ===================================
2301 13:18:48.960550 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 13:18:48.960659 ==
2303 13:18:48.964140 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 13:18:48.967201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 13:18:48.967297 ==
2306 13:18:48.970884 [Duty_Offset_Calibration]
2307 13:18:48.970954 B0:2 B1:-1 CA:1
2308 13:18:48.971011
2309 13:18:48.973849 [DutyScan_Calibration_Flow] k_type=0
2310 13:18:48.983403
2311 13:18:48.983495 ==CLK 0==
2312 13:18:48.986809 Final CLK duty delay cell = -4
2313 13:18:48.990464 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2314 13:18:48.993992 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2315 13:18:48.996698 [-4] AVG Duty = 4953%(X100)
2316 13:18:48.996794
2317 13:18:49.000407 CH0 CLK Duty spec in!! Max-Min= 156%
2318 13:18:49.003942 [DutyScan_Calibration_Flow] ====Done====
2319 13:18:49.004041
2320 13:18:49.007188 [DutyScan_Calibration_Flow] k_type=1
2321 13:18:49.022267
2322 13:18:49.022338 ==DQS 0 ==
2323 13:18:49.025915 Final DQS duty delay cell = 0
2324 13:18:49.029222 [0] MAX Duty = 5125%(X100), DQS PI = 48
2325 13:18:49.032510 [0] MIN Duty = 5000%(X100), DQS PI = 12
2326 13:18:49.032605 [0] AVG Duty = 5062%(X100)
2327 13:18:49.032688
2328 13:18:49.036272 ==DQS 1 ==
2329 13:18:49.039450 Final DQS duty delay cell = -4
2330 13:18:49.042497 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2331 13:18:49.046060 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2332 13:18:49.046156 [-4] AVG Duty = 5062%(X100)
2333 13:18:49.048936
2334 13:18:49.052685 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2335 13:18:49.052789
2336 13:18:49.055835 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2337 13:18:49.059424 [DutyScan_Calibration_Flow] ====Done====
2338 13:18:49.059492
2339 13:18:49.062438 [DutyScan_Calibration_Flow] k_type=3
2340 13:18:49.079077
2341 13:18:49.079150 ==DQM 0 ==
2342 13:18:49.082793 Final DQM duty delay cell = 0
2343 13:18:49.085723 [0] MAX Duty = 5000%(X100), DQS PI = 46
2344 13:18:49.089127 [0] MIN Duty = 4907%(X100), DQS PI = 2
2345 13:18:49.089213 [0] AVG Duty = 4953%(X100)
2346 13:18:49.092431
2347 13:18:49.092524 ==DQM 1 ==
2348 13:18:49.096045 Final DQM duty delay cell = 0
2349 13:18:49.099642 [0] MAX Duty = 5156%(X100), DQS PI = 62
2350 13:18:49.103030 [0] MIN Duty = 4969%(X100), DQS PI = 10
2351 13:18:49.103131 [0] AVG Duty = 5062%(X100)
2352 13:18:49.103218
2353 13:18:49.105889 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2354 13:18:49.109533
2355 13:18:49.112573 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2356 13:18:49.116225 [DutyScan_Calibration_Flow] ====Done====
2357 13:18:49.116300
2358 13:18:49.119246 [DutyScan_Calibration_Flow] k_type=2
2359 13:18:49.134651
2360 13:18:49.134749 ==DQ 0 ==
2361 13:18:49.138013 Final DQ duty delay cell = -4
2362 13:18:49.141452 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2363 13:18:49.144980 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2364 13:18:49.148601 [-4] AVG Duty = 4937%(X100)
2365 13:18:49.148693
2366 13:18:49.148776 ==DQ 1 ==
2367 13:18:49.151380 Final DQ duty delay cell = 0
2368 13:18:49.155050 [0] MAX Duty = 5031%(X100), DQS PI = 18
2369 13:18:49.158084 [0] MIN Duty = 4907%(X100), DQS PI = 14
2370 13:18:49.158178 [0] AVG Duty = 4969%(X100)
2371 13:18:49.161681
2372 13:18:49.164990 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2373 13:18:49.165079
2374 13:18:49.168151 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2375 13:18:49.171401 [DutyScan_Calibration_Flow] ====Done====
2376 13:18:49.171496 ==
2377 13:18:49.175112 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 13:18:49.178167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 13:18:49.178266 ==
2380 13:18:49.181870 [Duty_Offset_Calibration]
2381 13:18:49.181944 B0:1 B1:1 CA:2
2382 13:18:49.182002
2383 13:18:49.184914 [DutyScan_Calibration_Flow] k_type=0
2384 13:18:49.195284
2385 13:18:49.195415 ==CLK 0==
2386 13:18:49.198643 Final CLK duty delay cell = 0
2387 13:18:49.201628 [0] MAX Duty = 5156%(X100), DQS PI = 24
2388 13:18:49.205269 [0] MIN Duty = 4938%(X100), DQS PI = 42
2389 13:18:49.205349 [0] AVG Duty = 5047%(X100)
2390 13:18:49.205407
2391 13:18:49.208412 CH1 CLK Duty spec in!! Max-Min= 218%
2392 13:18:49.215206 [DutyScan_Calibration_Flow] ====Done====
2393 13:18:49.215317
2394 13:18:49.218839 [DutyScan_Calibration_Flow] k_type=1
2395 13:18:49.234440
2396 13:18:49.234511 ==DQS 0 ==
2397 13:18:49.237818 Final DQS duty delay cell = 0
2398 13:18:49.241245 [0] MAX Duty = 5031%(X100), DQS PI = 18
2399 13:18:49.244596 [0] MIN Duty = 4875%(X100), DQS PI = 44
2400 13:18:49.244689 [0] AVG Duty = 4953%(X100)
2401 13:18:49.247955
2402 13:18:49.248047 ==DQS 1 ==
2403 13:18:49.250989 Final DQS duty delay cell = 0
2404 13:18:49.254743 [0] MAX Duty = 5031%(X100), DQS PI = 36
2405 13:18:49.257761 [0] MIN Duty = 4907%(X100), DQS PI = 16
2406 13:18:49.257833 [0] AVG Duty = 4969%(X100)
2407 13:18:49.261298
2408 13:18:49.264817 CH1 DQS 0 Duty spec in!! Max-Min= 156%
2409 13:18:49.264889
2410 13:18:49.268169 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2411 13:18:49.271375 [DutyScan_Calibration_Flow] ====Done====
2412 13:18:49.271440
2413 13:18:49.274320 [DutyScan_Calibration_Flow] k_type=3
2414 13:18:49.291367
2415 13:18:49.291434 ==DQM 0 ==
2416 13:18:49.294398 Final DQM duty delay cell = 0
2417 13:18:49.297958 [0] MAX Duty = 5093%(X100), DQS PI = 16
2418 13:18:49.301044 [0] MIN Duty = 4876%(X100), DQS PI = 48
2419 13:18:49.301156 [0] AVG Duty = 4984%(X100)
2420 13:18:49.304345
2421 13:18:49.304435 ==DQM 1 ==
2422 13:18:49.307806 Final DQM duty delay cell = 0
2423 13:18:49.310915 [0] MAX Duty = 5125%(X100), DQS PI = 0
2424 13:18:49.314638 [0] MIN Duty = 4969%(X100), DQS PI = 20
2425 13:18:49.314729 [0] AVG Duty = 5047%(X100)
2426 13:18:49.314813
2427 13:18:49.320926 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2428 13:18:49.321000
2429 13:18:49.324646 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2430 13:18:49.327773 [DutyScan_Calibration_Flow] ====Done====
2431 13:18:49.327848
2432 13:18:49.331315 [DutyScan_Calibration_Flow] k_type=2
2433 13:18:49.347680
2434 13:18:49.347751 ==DQ 0 ==
2435 13:18:49.350722 Final DQ duty delay cell = 0
2436 13:18:49.354040 [0] MAX Duty = 5093%(X100), DQS PI = 18
2437 13:18:49.357513 [0] MIN Duty = 4907%(X100), DQS PI = 50
2438 13:18:49.357582 [0] AVG Duty = 5000%(X100)
2439 13:18:49.357638
2440 13:18:49.361075 ==DQ 1 ==
2441 13:18:49.364122 Final DQ duty delay cell = 0
2442 13:18:49.367843 [0] MAX Duty = 5093%(X100), DQS PI = 10
2443 13:18:49.370855 [0] MIN Duty = 5000%(X100), DQS PI = 52
2444 13:18:49.370922 [0] AVG Duty = 5046%(X100)
2445 13:18:49.370981
2446 13:18:49.374388 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2447 13:18:49.374471
2448 13:18:49.377732 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2449 13:18:49.384324 [DutyScan_Calibration_Flow] ====Done====
2450 13:18:49.387449 nWR fixed to 30
2451 13:18:49.387554 [ModeRegInit_LP4] CH0 RK0
2452 13:18:49.391403 [ModeRegInit_LP4] CH0 RK1
2453 13:18:49.394557 [ModeRegInit_LP4] CH1 RK0
2454 13:18:49.394632 [ModeRegInit_LP4] CH1 RK1
2455 13:18:49.397669 match AC timing 7
2456 13:18:49.401280 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 13:18:49.404442 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 13:18:49.411060 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 13:18:49.414752 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 13:18:49.421376 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 13:18:49.421452 ==
2462 13:18:49.424939 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 13:18:49.427682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 13:18:49.427747 ==
2465 13:18:49.431300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 13:18:49.438139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2467 13:18:49.447467 [CA 0] Center 40 (10~71) winsize 62
2468 13:18:49.450932 [CA 1] Center 39 (9~70) winsize 62
2469 13:18:49.454044 [CA 2] Center 36 (6~67) winsize 62
2470 13:18:49.457558 [CA 3] Center 35 (5~66) winsize 62
2471 13:18:49.460991 [CA 4] Center 34 (4~65) winsize 62
2472 13:18:49.464288 [CA 5] Center 34 (4~64) winsize 61
2473 13:18:49.464356
2474 13:18:49.467918 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2475 13:18:49.467983
2476 13:18:49.470949 [CATrainingPosCal] consider 1 rank data
2477 13:18:49.474442 u2DelayCellTimex100 = 270/100 ps
2478 13:18:49.477531 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2479 13:18:49.481154 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2480 13:18:49.487886 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2481 13:18:49.491281 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2482 13:18:49.494754 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2483 13:18:49.497874 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2484 13:18:49.497940
2485 13:18:49.501014 CA PerBit enable=1, Macro0, CA PI delay=34
2486 13:18:49.501105
2487 13:18:49.504709 [CBTSetCACLKResult] CA Dly = 34
2488 13:18:49.504806 CS Dly: 7 (0~38)
2489 13:18:49.504894 ==
2490 13:18:49.507648 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 13:18:49.514475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 13:18:49.514545 ==
2493 13:18:49.518006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 13:18:49.524863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 13:18:49.533238 [CA 0] Center 39 (9~70) winsize 62
2496 13:18:49.536835 [CA 1] Center 39 (9~70) winsize 62
2497 13:18:49.539894 [CA 2] Center 36 (6~67) winsize 62
2498 13:18:49.543567 [CA 3] Center 35 (5~66) winsize 62
2499 13:18:49.546944 [CA 4] Center 34 (4~65) winsize 62
2500 13:18:49.549928 [CA 5] Center 34 (4~64) winsize 61
2501 13:18:49.549993
2502 13:18:49.553466 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 13:18:49.553533
2504 13:18:49.557114 [CATrainingPosCal] consider 2 rank data
2505 13:18:49.560063 u2DelayCellTimex100 = 270/100 ps
2506 13:18:49.563694 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2507 13:18:49.567254 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2508 13:18:49.570472 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2509 13:18:49.577126 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2510 13:18:49.580231 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2511 13:18:49.583730 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2512 13:18:49.583797
2513 13:18:49.587238 CA PerBit enable=1, Macro0, CA PI delay=34
2514 13:18:49.587302
2515 13:18:49.590299 [CBTSetCACLKResult] CA Dly = 34
2516 13:18:49.590366 CS Dly: 8 (0~41)
2517 13:18:49.590420
2518 13:18:49.593911 ----->DramcWriteLeveling(PI) begin...
2519 13:18:49.593974 ==
2520 13:18:49.596887 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 13:18:49.603928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 13:18:49.604000 ==
2523 13:18:49.607208 Write leveling (Byte 0): 30 => 30
2524 13:18:49.610546 Write leveling (Byte 1): 30 => 30
2525 13:18:49.610615 DramcWriteLeveling(PI) end<-----
2526 13:18:49.610672
2527 13:18:49.613955 ==
2528 13:18:49.614019 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 13:18:49.620708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 13:18:49.620778 ==
2531 13:18:49.624258 [Gating] SW mode calibration
2532 13:18:49.631056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 13:18:49.634443 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 13:18:49.641066 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 13:18:49.644476 0 15 4 | B1->B0 | 2424 3131 | 1 1 | (1 1) (1 1)
2536 13:18:49.647356 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2537 13:18:49.650736 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 13:18:49.657425 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 13:18:49.661224 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 13:18:49.664614 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 13:18:49.671365 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 13:18:49.674456 1 0 0 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 0)
2543 13:18:49.677989 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2544 13:18:49.684547 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 13:18:49.687948 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 13:18:49.691530 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 13:18:49.698266 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 13:18:49.701289 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 13:18:49.704917 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 13:18:49.707969 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2551 13:18:49.714531 1 1 4 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2552 13:18:49.717997 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 13:18:49.721684 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 13:18:49.728025 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 13:18:49.731454 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 13:18:49.735056 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 13:18:49.741868 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 13:18:49.744879 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2559 13:18:49.748509 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2560 13:18:49.755082 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2561 13:18:49.757983 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:18:49.761437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:18:49.768261 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:18:49.771888 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:18:49.775000 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:18:49.781765 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:18:49.784816 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 13:18:49.788350 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:18:49.791853 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:18:49.798610 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:18:49.802058 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 13:18:49.805076 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 13:18:49.811855 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 13:18:49.815551 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2575 13:18:49.818410 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 13:18:49.821797 Total UI for P1: 0, mck2ui 16
2577 13:18:49.825456 best dqsien dly found for B0: ( 1, 4, 0)
2578 13:18:49.828490 Total UI for P1: 0, mck2ui 16
2579 13:18:49.832077 best dqsien dly found for B1: ( 1, 4, 0)
2580 13:18:49.835556 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2581 13:18:49.838716 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2582 13:18:49.838782
2583 13:18:49.841901 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2584 13:18:49.845732 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2585 13:18:49.849026 [Gating] SW calibration Done
2586 13:18:49.849094 ==
2587 13:18:49.852209 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 13:18:49.859102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 13:18:49.859174 ==
2590 13:18:49.859232 RX Vref Scan: 0
2591 13:18:49.859286
2592 13:18:49.862512 RX Vref 0 -> 0, step: 1
2593 13:18:49.862605
2594 13:18:49.865929 RX Delay -40 -> 252, step: 8
2595 13:18:49.869018 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2596 13:18:49.872587 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2597 13:18:49.875726 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2598 13:18:49.879235 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2599 13:18:49.886019 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2600 13:18:49.889073 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2601 13:18:49.892773 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2602 13:18:49.895933 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2603 13:18:49.899450 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2604 13:18:49.902498 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2605 13:18:49.909041 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2606 13:18:49.912752 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2607 13:18:49.916158 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2608 13:18:49.919200 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2609 13:18:49.922816 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2610 13:18:49.929178 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2611 13:18:49.929252 ==
2612 13:18:49.932807 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 13:18:49.935853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 13:18:49.935920 ==
2615 13:18:49.935977 DQS Delay:
2616 13:18:49.939518 DQS0 = 0, DQS1 = 0
2617 13:18:49.939591 DQM Delay:
2618 13:18:49.943002 DQM0 = 115, DQM1 = 108
2619 13:18:49.943080 DQ Delay:
2620 13:18:49.945938 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2621 13:18:49.949302 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2622 13:18:49.953088 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2623 13:18:49.956200 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2624 13:18:49.956277
2625 13:18:49.956352
2626 13:18:49.956423 ==
2627 13:18:49.959722 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 13:18:49.966289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 13:18:49.966368 ==
2630 13:18:49.966430
2631 13:18:49.966484
2632 13:18:49.966559 TX Vref Scan disable
2633 13:18:49.969758 == TX Byte 0 ==
2634 13:18:49.973062 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2635 13:18:49.976331 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2636 13:18:49.979774 == TX Byte 1 ==
2637 13:18:49.983472 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2638 13:18:49.986488 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2639 13:18:49.990076 ==
2640 13:18:49.993037 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 13:18:49.996684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 13:18:49.996760 ==
2643 13:18:50.007513 TX Vref=22, minBit 7, minWin=24, winSum=416
2644 13:18:50.010998 TX Vref=24, minBit 5, minWin=25, winSum=422
2645 13:18:50.014163 TX Vref=26, minBit 1, minWin=25, winSum=428
2646 13:18:50.017563 TX Vref=28, minBit 1, minWin=26, winSum=434
2647 13:18:50.020955 TX Vref=30, minBit 1, minWin=26, winSum=436
2648 13:18:50.024540 TX Vref=32, minBit 0, minWin=26, winSum=434
2649 13:18:50.031072 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 30
2650 13:18:50.031156
2651 13:18:50.034348 Final TX Range 1 Vref 30
2652 13:18:50.034421
2653 13:18:50.034478 ==
2654 13:18:50.037909 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 13:18:50.040994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 13:18:50.041088 ==
2657 13:18:50.041178
2658 13:18:50.041231
2659 13:18:50.044816 TX Vref Scan disable
2660 13:18:50.047832 == TX Byte 0 ==
2661 13:18:50.051459 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2662 13:18:50.054403 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2663 13:18:50.057865 == TX Byte 1 ==
2664 13:18:50.060897 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2665 13:18:50.064424 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2666 13:18:50.064516
2667 13:18:50.067814 [DATLAT]
2668 13:18:50.067904 Freq=1200, CH0 RK0
2669 13:18:50.067983
2670 13:18:50.071159 DATLAT Default: 0xd
2671 13:18:50.071224 0, 0xFFFF, sum = 0
2672 13:18:50.074689 1, 0xFFFF, sum = 0
2673 13:18:50.074759 2, 0xFFFF, sum = 0
2674 13:18:50.077871 3, 0xFFFF, sum = 0
2675 13:18:50.077941 4, 0xFFFF, sum = 0
2676 13:18:50.081047 5, 0xFFFF, sum = 0
2677 13:18:50.081172 6, 0xFFFF, sum = 0
2678 13:18:50.084463 7, 0xFFFF, sum = 0
2679 13:18:50.084535 8, 0xFFFF, sum = 0
2680 13:18:50.088105 9, 0xFFFF, sum = 0
2681 13:18:50.088199 10, 0xFFFF, sum = 0
2682 13:18:50.091293 11, 0xFFFF, sum = 0
2683 13:18:50.091444 12, 0x0, sum = 1
2684 13:18:50.094772 13, 0x0, sum = 2
2685 13:18:50.094847 14, 0x0, sum = 3
2686 13:18:50.097892 15, 0x0, sum = 4
2687 13:18:50.097968 best_step = 13
2688 13:18:50.098030
2689 13:18:50.098085 ==
2690 13:18:50.101588 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 13:18:50.108098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 13:18:50.108174 ==
2693 13:18:50.108237 RX Vref Scan: 1
2694 13:18:50.108291
2695 13:18:50.111181 Set Vref Range= 32 -> 127
2696 13:18:50.111273
2697 13:18:50.114670 RX Vref 32 -> 127, step: 1
2698 13:18:50.114769
2699 13:18:50.114851 RX Delay -21 -> 252, step: 4
2700 13:18:50.114954
2701 13:18:50.118420 Set Vref, RX VrefLevel [Byte0]: 32
2702 13:18:50.121480 [Byte1]: 32
2703 13:18:50.125838
2704 13:18:50.125914 Set Vref, RX VrefLevel [Byte0]: 33
2705 13:18:50.129280 [Byte1]: 33
2706 13:18:50.133700
2707 13:18:50.133776 Set Vref, RX VrefLevel [Byte0]: 34
2708 13:18:50.136807 [Byte1]: 34
2709 13:18:50.141431
2710 13:18:50.141507 Set Vref, RX VrefLevel [Byte0]: 35
2711 13:18:50.144987 [Byte1]: 35
2712 13:18:50.149754
2713 13:18:50.149830 Set Vref, RX VrefLevel [Byte0]: 36
2714 13:18:50.152793 [Byte1]: 36
2715 13:18:50.157683
2716 13:18:50.157760 Set Vref, RX VrefLevel [Byte0]: 37
2717 13:18:50.160663 [Byte1]: 37
2718 13:18:50.165275
2719 13:18:50.165351 Set Vref, RX VrefLevel [Byte0]: 38
2720 13:18:50.168822 [Byte1]: 38
2721 13:18:50.173069
2722 13:18:50.173155 Set Vref, RX VrefLevel [Byte0]: 39
2723 13:18:50.176735 [Byte1]: 39
2724 13:18:50.181389
2725 13:18:50.181466 Set Vref, RX VrefLevel [Byte0]: 40
2726 13:18:50.184749 [Byte1]: 40
2727 13:18:50.188921
2728 13:18:50.188997 Set Vref, RX VrefLevel [Byte0]: 41
2729 13:18:50.192295 [Byte1]: 41
2730 13:18:50.196942
2731 13:18:50.197038 Set Vref, RX VrefLevel [Byte0]: 42
2732 13:18:50.200523 [Byte1]: 42
2733 13:18:50.205354
2734 13:18:50.205428 Set Vref, RX VrefLevel [Byte0]: 43
2735 13:18:50.208408 [Byte1]: 43
2736 13:18:50.213220
2737 13:18:50.213294 Set Vref, RX VrefLevel [Byte0]: 44
2738 13:18:50.216349 [Byte1]: 44
2739 13:18:50.221341
2740 13:18:50.221435 Set Vref, RX VrefLevel [Byte0]: 45
2741 13:18:50.224228 [Byte1]: 45
2742 13:18:50.228549
2743 13:18:50.228628 Set Vref, RX VrefLevel [Byte0]: 46
2744 13:18:50.232051 [Byte1]: 46
2745 13:18:50.236796
2746 13:18:50.236867 Set Vref, RX VrefLevel [Byte0]: 47
2747 13:18:50.239779 [Byte1]: 47
2748 13:18:50.244684
2749 13:18:50.244766 Set Vref, RX VrefLevel [Byte0]: 48
2750 13:18:50.248062 [Byte1]: 48
2751 13:18:50.252633
2752 13:18:50.252706 Set Vref, RX VrefLevel [Byte0]: 49
2753 13:18:50.255931 [Byte1]: 49
2754 13:18:50.261089
2755 13:18:50.261192 Set Vref, RX VrefLevel [Byte0]: 50
2756 13:18:50.264028 [Byte1]: 50
2757 13:18:50.268223
2758 13:18:50.268294 Set Vref, RX VrefLevel [Byte0]: 51
2759 13:18:50.271921 [Byte1]: 51
2760 13:18:50.276340
2761 13:18:50.276416 Set Vref, RX VrefLevel [Byte0]: 52
2762 13:18:50.279858 [Byte1]: 52
2763 13:18:50.284157
2764 13:18:50.284233 Set Vref, RX VrefLevel [Byte0]: 53
2765 13:18:50.287603 [Byte1]: 53
2766 13:18:50.291998
2767 13:18:50.292073 Set Vref, RX VrefLevel [Byte0]: 54
2768 13:18:50.295653 [Byte1]: 54
2769 13:18:50.300372
2770 13:18:50.300459 Set Vref, RX VrefLevel [Byte0]: 55
2771 13:18:50.303526 [Byte1]: 55
2772 13:18:50.308082
2773 13:18:50.308183 Set Vref, RX VrefLevel [Byte0]: 56
2774 13:18:50.311458 [Byte1]: 56
2775 13:18:50.316065
2776 13:18:50.316142 Set Vref, RX VrefLevel [Byte0]: 57
2777 13:18:50.319493 [Byte1]: 57
2778 13:18:50.323727
2779 13:18:50.323828 Set Vref, RX VrefLevel [Byte0]: 58
2780 13:18:50.327243 [Byte1]: 58
2781 13:18:50.331732
2782 13:18:50.331807 Set Vref, RX VrefLevel [Byte0]: 59
2783 13:18:50.335180 [Byte1]: 59
2784 13:18:50.340038
2785 13:18:50.340178 Set Vref, RX VrefLevel [Byte0]: 60
2786 13:18:50.343103 [Byte1]: 60
2787 13:18:50.347972
2788 13:18:50.348111 Set Vref, RX VrefLevel [Byte0]: 61
2789 13:18:50.350891 [Byte1]: 61
2790 13:18:50.355743
2791 13:18:50.355876 Set Vref, RX VrefLevel [Byte0]: 62
2792 13:18:50.358746 [Byte1]: 62
2793 13:18:50.363493
2794 13:18:50.363591 Set Vref, RX VrefLevel [Byte0]: 63
2795 13:18:50.366883 [Byte1]: 63
2796 13:18:50.371276
2797 13:18:50.371372 Set Vref, RX VrefLevel [Byte0]: 64
2798 13:18:50.374520 [Byte1]: 64
2799 13:18:50.379669
2800 13:18:50.379765 Set Vref, RX VrefLevel [Byte0]: 65
2801 13:18:50.382729 [Byte1]: 65
2802 13:18:50.387111
2803 13:18:50.387272 Set Vref, RX VrefLevel [Byte0]: 66
2804 13:18:50.390733 [Byte1]: 66
2805 13:18:50.395346
2806 13:18:50.395442 Set Vref, RX VrefLevel [Byte0]: 67
2807 13:18:50.398712 [Byte1]: 67
2808 13:18:50.403060
2809 13:18:50.403162 Set Vref, RX VrefLevel [Byte0]: 68
2810 13:18:50.406695 [Byte1]: 68
2811 13:18:50.410936
2812 13:18:50.411062 Final RX Vref Byte 0 = 53 to rank0
2813 13:18:50.414431 Final RX Vref Byte 1 = 54 to rank0
2814 13:18:50.417636 Final RX Vref Byte 0 = 53 to rank1
2815 13:18:50.421207 Final RX Vref Byte 1 = 54 to rank1==
2816 13:18:50.424716 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 13:18:50.427733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 13:18:50.431280 ==
2819 13:18:50.431378 DQS Delay:
2820 13:18:50.431461 DQS0 = 0, DQS1 = 0
2821 13:18:50.434422 DQM Delay:
2822 13:18:50.434515 DQM0 = 115, DQM1 = 105
2823 13:18:50.437986 DQ Delay:
2824 13:18:50.441273 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2825 13:18:50.444712 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2826 13:18:50.447990 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2827 13:18:50.451497 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2828 13:18:50.451582
2829 13:18:50.451641
2830 13:18:50.458185 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
2831 13:18:50.461704 CH0 RK0: MR19=403, MR18=3F2
2832 13:18:50.468337 CH0_RK0: MR19=0x403, MR18=0x3F2, DQSOSC=408, MR23=63, INC=39, DEC=26
2833 13:18:50.468419
2834 13:18:50.471821 ----->DramcWriteLeveling(PI) begin...
2835 13:18:50.471894 ==
2836 13:18:50.474718 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 13:18:50.478282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 13:18:50.478388 ==
2839 13:18:50.481618 Write leveling (Byte 0): 32 => 32
2840 13:18:50.485001 Write leveling (Byte 1): 28 => 28
2841 13:18:50.488436 DramcWriteLeveling(PI) end<-----
2842 13:18:50.488521
2843 13:18:50.488582 ==
2844 13:18:50.492045 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 13:18:50.495208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 13:18:50.495299 ==
2847 13:18:50.498339 [Gating] SW mode calibration
2848 13:18:50.505436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 13:18:50.512023 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 13:18:50.514995 0 15 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
2851 13:18:50.518556 0 15 4 | B1->B0 | 2d2d 3434 | 1 0 | (0 0) (0 0)
2852 13:18:50.525124 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 13:18:50.528709 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 13:18:50.532327 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 13:18:50.539083 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 13:18:50.542671 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2857 13:18:50.545579 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
2858 13:18:50.548969 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2859 13:18:50.555668 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 13:18:50.559029 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 13:18:50.562919 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 13:18:50.568977 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 13:18:50.572536 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 13:18:50.575554 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2865 13:18:50.582767 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2866 13:18:50.586204 1 1 0 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (1 1)
2867 13:18:50.589134 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
2868 13:18:50.595940 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 13:18:50.599504 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 13:18:50.602564 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 13:18:50.609443 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 13:18:50.613005 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 13:18:50.615978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2874 13:18:50.619543 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2875 13:18:50.626155 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2876 13:18:50.629655 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 13:18:50.633271 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 13:18:50.639408 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 13:18:50.643016 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 13:18:50.646132 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 13:18:50.652888 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 13:18:50.656671 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 13:18:50.659709 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 13:18:50.666634 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 13:18:50.669893 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:18:50.672982 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:18:50.676475 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:18:50.683552 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:18:50.686788 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2890 13:18:50.690036 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2891 13:18:50.693134 Total UI for P1: 0, mck2ui 16
2892 13:18:50.696648 best dqsien dly found for B0: ( 1, 3, 28)
2893 13:18:50.703274 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 13:18:50.703371 Total UI for P1: 0, mck2ui 16
2895 13:18:50.709887 best dqsien dly found for B1: ( 1, 4, 2)
2896 13:18:50.713530 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2897 13:18:50.716554 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2898 13:18:50.716655
2899 13:18:50.720266 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2900 13:18:50.723782 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2901 13:18:50.726913 [Gating] SW calibration Done
2902 13:18:50.726980 ==
2903 13:18:50.729981 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 13:18:50.733782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 13:18:50.733851 ==
2906 13:18:50.736595 RX Vref Scan: 0
2907 13:18:50.736662
2908 13:18:50.736715 RX Vref 0 -> 0, step: 1
2909 13:18:50.736768
2910 13:18:50.740240 RX Delay -40 -> 252, step: 8
2911 13:18:50.743274 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2912 13:18:50.746974 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2913 13:18:50.753660 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2914 13:18:50.756812 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2915 13:18:50.760552 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2916 13:18:50.763453 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2917 13:18:50.767183 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2918 13:18:50.773834 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2919 13:18:50.776864 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2920 13:18:50.780295 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2921 13:18:50.783705 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2922 13:18:50.786949 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2923 13:18:50.793666 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2924 13:18:50.797275 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2925 13:18:50.800186 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2926 13:18:50.803861 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2927 13:18:50.803931 ==
2928 13:18:50.806894 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 13:18:50.810593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 13:18:50.813932 ==
2931 13:18:50.814023 DQS Delay:
2932 13:18:50.814105 DQS0 = 0, DQS1 = 0
2933 13:18:50.817291 DQM Delay:
2934 13:18:50.817360 DQM0 = 115, DQM1 = 106
2935 13:18:50.820436 DQ Delay:
2936 13:18:50.823821 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2937 13:18:50.827372 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2938 13:18:50.830278 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2939 13:18:50.834087 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2940 13:18:50.834162
2941 13:18:50.834221
2942 13:18:50.834274 ==
2943 13:18:50.837038 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 13:18:50.840516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 13:18:50.840595 ==
2946 13:18:50.840654
2947 13:18:50.840707
2948 13:18:50.843650 TX Vref Scan disable
2949 13:18:50.847438 == TX Byte 0 ==
2950 13:18:50.850542 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2951 13:18:50.854139 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2952 13:18:50.857302 == TX Byte 1 ==
2953 13:18:50.860303 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2954 13:18:50.863964 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2955 13:18:50.864039 ==
2956 13:18:50.867141 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 13:18:50.870756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 13:18:50.873735 ==
2959 13:18:50.884082 TX Vref=22, minBit 1, minWin=25, winSum=422
2960 13:18:50.887549 TX Vref=24, minBit 0, minWin=26, winSum=430
2961 13:18:50.890835 TX Vref=26, minBit 0, minWin=26, winSum=431
2962 13:18:50.894271 TX Vref=28, minBit 0, minWin=27, winSum=437
2963 13:18:50.897783 TX Vref=30, minBit 0, minWin=27, winSum=437
2964 13:18:50.900869 TX Vref=32, minBit 0, minWin=27, winSum=437
2965 13:18:50.907332 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 28
2966 13:18:50.907408
2967 13:18:50.910658 Final TX Range 1 Vref 28
2968 13:18:50.910757
2969 13:18:50.910841 ==
2970 13:18:50.914233 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 13:18:50.917682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 13:18:50.917776 ==
2973 13:18:50.917859
2974 13:18:50.917938
2975 13:18:50.920933 TX Vref Scan disable
2976 13:18:50.924399 == TX Byte 0 ==
2977 13:18:50.927558 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2978 13:18:50.930811 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2979 13:18:50.934071 == TX Byte 1 ==
2980 13:18:50.937290 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2981 13:18:50.940615 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2982 13:18:50.940706
2983 13:18:50.944071 [DATLAT]
2984 13:18:50.944161 Freq=1200, CH0 RK1
2985 13:18:50.944221
2986 13:18:50.947657 DATLAT Default: 0xd
2987 13:18:50.947725 0, 0xFFFF, sum = 0
2988 13:18:50.950701 1, 0xFFFF, sum = 0
2989 13:18:50.950769 2, 0xFFFF, sum = 0
2990 13:18:50.954268 3, 0xFFFF, sum = 0
2991 13:18:50.954339 4, 0xFFFF, sum = 0
2992 13:18:50.957298 5, 0xFFFF, sum = 0
2993 13:18:50.957381 6, 0xFFFF, sum = 0
2994 13:18:50.960962 7, 0xFFFF, sum = 0
2995 13:18:50.964126 8, 0xFFFF, sum = 0
2996 13:18:50.964192 9, 0xFFFF, sum = 0
2997 13:18:50.967107 10, 0xFFFF, sum = 0
2998 13:18:50.967171 11, 0xFFFF, sum = 0
2999 13:18:50.970694 12, 0x0, sum = 1
3000 13:18:50.970758 13, 0x0, sum = 2
3001 13:18:50.973736 14, 0x0, sum = 3
3002 13:18:50.973816 15, 0x0, sum = 4
3003 13:18:50.973884 best_step = 13
3004 13:18:50.973956
3005 13:18:50.977412 ==
3006 13:18:50.980294 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 13:18:50.983953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 13:18:50.984020 ==
3009 13:18:50.984073 RX Vref Scan: 0
3010 13:18:50.984125
3011 13:18:50.987022 RX Vref 0 -> 0, step: 1
3012 13:18:50.987084
3013 13:18:50.990501 RX Delay -21 -> 252, step: 4
3014 13:18:50.994162 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3015 13:18:51.000839 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3016 13:18:51.003710 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3017 13:18:51.007299 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3018 13:18:51.010437 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3019 13:18:51.013677 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3020 13:18:51.020443 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3021 13:18:51.023997 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3022 13:18:51.027073 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3023 13:18:51.030726 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3024 13:18:51.033786 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3025 13:18:51.037390 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3026 13:18:51.043954 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3027 13:18:51.047385 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3028 13:18:51.050584 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3029 13:18:51.053774 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3030 13:18:51.053846 ==
3031 13:18:51.057442 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 13:18:51.063727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 13:18:51.063796 ==
3034 13:18:51.063894 DQS Delay:
3035 13:18:51.063972 DQS0 = 0, DQS1 = 0
3036 13:18:51.067534 DQM Delay:
3037 13:18:51.067596 DQM0 = 114, DQM1 = 105
3038 13:18:51.070515 DQ Delay:
3039 13:18:51.074281 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3040 13:18:51.077309 DQ4 =112, DQ5 =106, DQ6 =122, DQ7 =122
3041 13:18:51.080819 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3042 13:18:51.083827 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
3043 13:18:51.083892
3044 13:18:51.083944
3045 13:18:51.090523 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3046 13:18:51.093982 CH0 RK1: MR19=403, MR18=3F4
3047 13:18:51.100693 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3048 13:18:51.104163 [RxdqsGatingPostProcess] freq 1200
3049 13:18:51.110879 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3050 13:18:51.110974 best DQS0 dly(2T, 0.5T) = (0, 12)
3051 13:18:51.113884 best DQS1 dly(2T, 0.5T) = (0, 12)
3052 13:18:51.117484 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3053 13:18:51.120988 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3054 13:18:51.124433 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 13:18:51.127231 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 13:18:51.131148 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 13:18:51.134079 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 13:18:51.137556 Pre-setting of DQS Precalculation
3059 13:18:51.140509 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3060 13:18:51.144122 ==
3061 13:18:51.144188 Dram Type= 6, Freq= 0, CH_1, rank 0
3062 13:18:51.150876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 13:18:51.150972 ==
3064 13:18:51.153841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3065 13:18:51.160824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3066 13:18:51.169707 [CA 0] Center 38 (9~68) winsize 60
3067 13:18:51.172973 [CA 1] Center 38 (8~68) winsize 61
3068 13:18:51.176253 [CA 2] Center 35 (5~65) winsize 61
3069 13:18:51.179536 [CA 3] Center 34 (4~65) winsize 62
3070 13:18:51.182821 [CA 4] Center 34 (4~65) winsize 62
3071 13:18:51.186216 [CA 5] Center 33 (3~64) winsize 62
3072 13:18:51.186306
3073 13:18:51.189833 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3074 13:18:51.189932
3075 13:18:51.192982 [CATrainingPosCal] consider 1 rank data
3076 13:18:51.196500 u2DelayCellTimex100 = 270/100 ps
3077 13:18:51.199519 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3078 13:18:51.202981 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3079 13:18:51.209532 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3080 13:18:51.213098 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3081 13:18:51.216095 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3082 13:18:51.219870 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3083 13:18:51.220022
3084 13:18:51.222784 CA PerBit enable=1, Macro0, CA PI delay=33
3085 13:18:51.222881
3086 13:18:51.226550 [CBTSetCACLKResult] CA Dly = 33
3087 13:18:51.226651 CS Dly: 5 (0~36)
3088 13:18:51.226737 ==
3089 13:18:51.229546 Dram Type= 6, Freq= 0, CH_1, rank 1
3090 13:18:51.236176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 13:18:51.236256 ==
3092 13:18:51.239479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 13:18:51.246457 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3094 13:18:51.254987 [CA 0] Center 38 (8~68) winsize 61
3095 13:18:51.258498 [CA 1] Center 38 (8~68) winsize 61
3096 13:18:51.262081 [CA 2] Center 34 (4~65) winsize 62
3097 13:18:51.264954 [CA 3] Center 34 (3~65) winsize 63
3098 13:18:51.268564 [CA 4] Center 34 (4~65) winsize 62
3099 13:18:51.271633 [CA 5] Center 33 (3~64) winsize 62
3100 13:18:51.271725
3101 13:18:51.275390 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 13:18:51.275481
3103 13:18:51.278461 [CATrainingPosCal] consider 2 rank data
3104 13:18:51.281938 u2DelayCellTimex100 = 270/100 ps
3105 13:18:51.285468 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3106 13:18:51.288777 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3107 13:18:51.291863 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3108 13:18:51.299061 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3109 13:18:51.302262 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3110 13:18:51.305516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3111 13:18:51.305588
3112 13:18:51.309080 CA PerBit enable=1, Macro0, CA PI delay=33
3113 13:18:51.309182
3114 13:18:51.312003 [CBTSetCACLKResult] CA Dly = 33
3115 13:18:51.312071 CS Dly: 7 (0~40)
3116 13:18:51.312153
3117 13:18:51.315678 ----->DramcWriteLeveling(PI) begin...
3118 13:18:51.315745 ==
3119 13:18:51.318626 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 13:18:51.325185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 13:18:51.325254 ==
3122 13:18:51.328697 Write leveling (Byte 0): 25 => 25
3123 13:18:51.332162 Write leveling (Byte 1): 31 => 31
3124 13:18:51.332228 DramcWriteLeveling(PI) end<-----
3125 13:18:51.332285
3126 13:18:51.335661 ==
3127 13:18:51.338729 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 13:18:51.342346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 13:18:51.342412 ==
3130 13:18:51.345301 [Gating] SW mode calibration
3131 13:18:51.352204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3132 13:18:51.355735 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3133 13:18:51.362447 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3134 13:18:51.365496 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3135 13:18:51.368953 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 13:18:51.375548 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 13:18:51.379260 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3138 13:18:51.382371 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 13:18:51.389036 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 13:18:51.392665 0 15 28 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
3141 13:18:51.395711 1 0 0 | B1->B0 | 2323 2828 | 0 0 | (1 0) (0 0)
3142 13:18:51.399200 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 13:18:51.405745 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 13:18:51.409080 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 13:18:51.412436 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 13:18:51.419014 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 13:18:51.422366 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 13:18:51.425682 1 0 28 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
3149 13:18:51.432209 1 1 0 | B1->B0 | 4141 3333 | 0 1 | (0 0) (0 0)
3150 13:18:51.435794 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 13:18:51.438904 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 13:18:51.445488 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 13:18:51.449065 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 13:18:51.452163 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 13:18:51.459230 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 13:18:51.462658 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 13:18:51.465871 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3158 13:18:51.472544 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 13:18:51.475932 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 13:18:51.479409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 13:18:51.486061 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 13:18:51.489035 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 13:18:51.492051 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 13:18:51.495823 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 13:18:51.502596 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 13:18:51.506187 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 13:18:51.509218 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 13:18:51.515907 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 13:18:51.518916 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:18:51.522489 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:18:51.529391 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3172 13:18:51.532503 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 13:18:51.535682 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 13:18:51.539033 Total UI for P1: 0, mck2ui 16
3175 13:18:51.542346 best dqsien dly found for B0: ( 1, 3, 26)
3176 13:18:51.545769 Total UI for P1: 0, mck2ui 16
3177 13:18:51.548828 best dqsien dly found for B1: ( 1, 3, 28)
3178 13:18:51.552416 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3179 13:18:51.555467 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3180 13:18:51.555535
3181 13:18:51.562637 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3182 13:18:51.565772 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3183 13:18:51.565838 [Gating] SW calibration Done
3184 13:18:51.568905 ==
3185 13:18:51.572386 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 13:18:51.575739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 13:18:51.575823 ==
3188 13:18:51.575893 RX Vref Scan: 0
3189 13:18:51.575962
3190 13:18:51.579118 RX Vref 0 -> 0, step: 1
3191 13:18:51.579196
3192 13:18:51.582152 RX Delay -40 -> 252, step: 8
3193 13:18:51.585800 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3194 13:18:51.588887 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3195 13:18:51.592322 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3196 13:18:51.598906 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3197 13:18:51.602483 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3198 13:18:51.605458 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3199 13:18:51.609032 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3200 13:18:51.612764 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3201 13:18:51.619193 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3202 13:18:51.622551 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3203 13:18:51.626168 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3204 13:18:51.629214 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3205 13:18:51.632336 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3206 13:18:51.638879 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3207 13:18:51.642192 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3208 13:18:51.645628 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3209 13:18:51.645694 ==
3210 13:18:51.648978 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 13:18:51.652676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 13:18:51.652743 ==
3213 13:18:51.655752 DQS Delay:
3214 13:18:51.655817 DQS0 = 0, DQS1 = 0
3215 13:18:51.659161 DQM Delay:
3216 13:18:51.659223 DQM0 = 115, DQM1 = 108
3217 13:18:51.659328 DQ Delay:
3218 13:18:51.662774 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3219 13:18:51.665732 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3220 13:18:51.672235 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3221 13:18:51.676060 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3222 13:18:51.676122
3223 13:18:51.676174
3224 13:18:51.676224 ==
3225 13:18:51.678965 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 13:18:51.682717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 13:18:51.682793 ==
3228 13:18:51.682851
3229 13:18:51.682921
3230 13:18:51.685599 TX Vref Scan disable
3231 13:18:51.685677 == TX Byte 0 ==
3232 13:18:51.692514 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3233 13:18:51.695979 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3234 13:18:51.696055 == TX Byte 1 ==
3235 13:18:51.702334 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3236 13:18:51.705977 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3237 13:18:51.706057 ==
3238 13:18:51.708853 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 13:18:51.712416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 13:18:51.712520 ==
3241 13:18:51.725785 TX Vref=22, minBit 0, minWin=25, winSum=405
3242 13:18:51.729201 TX Vref=24, minBit 1, minWin=25, winSum=415
3243 13:18:51.732536 TX Vref=26, minBit 1, minWin=25, winSum=417
3244 13:18:51.735734 TX Vref=28, minBit 0, minWin=26, winSum=421
3245 13:18:51.738780 TX Vref=30, minBit 13, minWin=25, winSum=424
3246 13:18:51.745644 TX Vref=32, minBit 11, minWin=25, winSum=418
3247 13:18:51.749083 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 28
3248 13:18:51.749179
3249 13:18:51.752203 Final TX Range 1 Vref 28
3250 13:18:51.752278
3251 13:18:51.752351 ==
3252 13:18:51.755818 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 13:18:51.758697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 13:18:51.758773 ==
3255 13:18:51.761989
3256 13:18:51.762064
3257 13:18:51.762122 TX Vref Scan disable
3258 13:18:51.765747 == TX Byte 0 ==
3259 13:18:51.769028 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3260 13:18:51.772170 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3261 13:18:51.775597 == TX Byte 1 ==
3262 13:18:51.778731 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3263 13:18:51.782283 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3264 13:18:51.785465
3265 13:18:51.785541 [DATLAT]
3266 13:18:51.785599 Freq=1200, CH1 RK0
3267 13:18:51.785655
3268 13:18:51.789241 DATLAT Default: 0xd
3269 13:18:51.789315 0, 0xFFFF, sum = 0
3270 13:18:51.792215 1, 0xFFFF, sum = 0
3271 13:18:51.792294 2, 0xFFFF, sum = 0
3272 13:18:51.795783 3, 0xFFFF, sum = 0
3273 13:18:51.795859 4, 0xFFFF, sum = 0
3274 13:18:51.798652 5, 0xFFFF, sum = 0
3275 13:18:51.802213 6, 0xFFFF, sum = 0
3276 13:18:51.802289 7, 0xFFFF, sum = 0
3277 13:18:51.805366 8, 0xFFFF, sum = 0
3278 13:18:51.805485 9, 0xFFFF, sum = 0
3279 13:18:51.808684 10, 0xFFFF, sum = 0
3280 13:18:51.808760 11, 0xFFFF, sum = 0
3281 13:18:51.812014 12, 0x0, sum = 1
3282 13:18:51.812090 13, 0x0, sum = 2
3283 13:18:51.815732 14, 0x0, sum = 3
3284 13:18:51.815824 15, 0x0, sum = 4
3285 13:18:51.815944 best_step = 13
3286 13:18:51.816017
3287 13:18:51.818684 ==
3288 13:18:51.822529 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 13:18:51.825663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 13:18:51.825738 ==
3291 13:18:51.825838 RX Vref Scan: 1
3292 13:18:51.825920
3293 13:18:51.829200 Set Vref Range= 32 -> 127
3294 13:18:51.829281
3295 13:18:51.832222 RX Vref 32 -> 127, step: 1
3296 13:18:51.832299
3297 13:18:51.835778 RX Delay -21 -> 252, step: 4
3298 13:18:51.835852
3299 13:18:51.839158 Set Vref, RX VrefLevel [Byte0]: 32
3300 13:18:51.842084 [Byte1]: 32
3301 13:18:51.842173
3302 13:18:51.845590 Set Vref, RX VrefLevel [Byte0]: 33
3303 13:18:51.849255 [Byte1]: 33
3304 13:18:51.849329
3305 13:18:51.852326 Set Vref, RX VrefLevel [Byte0]: 34
3306 13:18:51.855836 [Byte1]: 34
3307 13:18:51.860182
3308 13:18:51.860256 Set Vref, RX VrefLevel [Byte0]: 35
3309 13:18:51.863139 [Byte1]: 35
3310 13:18:51.867635
3311 13:18:51.867699 Set Vref, RX VrefLevel [Byte0]: 36
3312 13:18:51.871267 [Byte1]: 36
3313 13:18:51.875970
3314 13:18:51.876035 Set Vref, RX VrefLevel [Byte0]: 37
3315 13:18:51.878909 [Byte1]: 37
3316 13:18:51.883767
3317 13:18:51.883832 Set Vref, RX VrefLevel [Byte0]: 38
3318 13:18:51.887219 [Byte1]: 38
3319 13:18:51.891394
3320 13:18:51.891460 Set Vref, RX VrefLevel [Byte0]: 39
3321 13:18:51.894968 [Byte1]: 39
3322 13:18:51.899662
3323 13:18:51.899727 Set Vref, RX VrefLevel [Byte0]: 40
3324 13:18:51.902679 [Byte1]: 40
3325 13:18:51.907560
3326 13:18:51.907623 Set Vref, RX VrefLevel [Byte0]: 41
3327 13:18:51.910532 [Byte1]: 41
3328 13:18:51.915483
3329 13:18:51.915547 Set Vref, RX VrefLevel [Byte0]: 42
3330 13:18:51.918449 [Byte1]: 42
3331 13:18:51.923180
3332 13:18:51.923282 Set Vref, RX VrefLevel [Byte0]: 43
3333 13:18:51.926485 [Byte1]: 43
3334 13:18:51.931060
3335 13:18:51.931144 Set Vref, RX VrefLevel [Byte0]: 44
3336 13:18:51.934819 [Byte1]: 44
3337 13:18:51.939397
3338 13:18:51.939486 Set Vref, RX VrefLevel [Byte0]: 45
3339 13:18:51.942351 [Byte1]: 45
3340 13:18:51.947302
3341 13:18:51.947369 Set Vref, RX VrefLevel [Byte0]: 46
3342 13:18:51.950576 [Byte1]: 46
3343 13:18:51.954778
3344 13:18:51.954852 Set Vref, RX VrefLevel [Byte0]: 47
3345 13:18:51.958402 [Byte1]: 47
3346 13:18:51.963206
3347 13:18:51.963272 Set Vref, RX VrefLevel [Byte0]: 48
3348 13:18:51.966282 [Byte1]: 48
3349 13:18:51.970551
3350 13:18:51.970643 Set Vref, RX VrefLevel [Byte0]: 49
3351 13:18:51.974028 [Byte1]: 49
3352 13:18:51.978903
3353 13:18:51.978964 Set Vref, RX VrefLevel [Byte0]: 50
3354 13:18:51.981899 [Byte1]: 50
3355 13:18:51.986660
3356 13:18:51.986725 Set Vref, RX VrefLevel [Byte0]: 51
3357 13:18:51.990120 [Byte1]: 51
3358 13:18:51.994671
3359 13:18:51.994735 Set Vref, RX VrefLevel [Byte0]: 52
3360 13:18:51.997873 [Byte1]: 52
3361 13:18:52.002668
3362 13:18:52.002734 Set Vref, RX VrefLevel [Byte0]: 53
3363 13:18:52.005631 [Byte1]: 53
3364 13:18:52.010544
3365 13:18:52.010624 Set Vref, RX VrefLevel [Byte0]: 54
3366 13:18:52.013612 [Byte1]: 54
3367 13:18:52.018524
3368 13:18:52.018587 Set Vref, RX VrefLevel [Byte0]: 55
3369 13:18:52.021672 [Byte1]: 55
3370 13:18:52.026489
3371 13:18:52.026553 Set Vref, RX VrefLevel [Byte0]: 56
3372 13:18:52.029380 [Byte1]: 56
3373 13:18:52.034263
3374 13:18:52.034325 Set Vref, RX VrefLevel [Byte0]: 57
3375 13:18:52.037640 [Byte1]: 57
3376 13:18:52.041881
3377 13:18:52.041944 Set Vref, RX VrefLevel [Byte0]: 58
3378 13:18:52.045111 [Byte1]: 58
3379 13:18:52.050127
3380 13:18:52.050218 Set Vref, RX VrefLevel [Byte0]: 59
3381 13:18:52.053655 [Byte1]: 59
3382 13:18:52.057691
3383 13:18:52.057760 Set Vref, RX VrefLevel [Byte0]: 60
3384 13:18:52.061319 [Byte1]: 60
3385 13:18:52.065579
3386 13:18:52.065649 Set Vref, RX VrefLevel [Byte0]: 61
3387 13:18:52.069112 [Byte1]: 61
3388 13:18:52.073966
3389 13:18:52.074034 Set Vref, RX VrefLevel [Byte0]: 62
3390 13:18:52.077271 [Byte1]: 62
3391 13:18:52.081761
3392 13:18:52.081840 Set Vref, RX VrefLevel [Byte0]: 63
3393 13:18:52.085439 [Byte1]: 63
3394 13:18:52.089719
3395 13:18:52.089805 Set Vref, RX VrefLevel [Byte0]: 64
3396 13:18:52.092693 [Byte1]: 64
3397 13:18:52.097525
3398 13:18:52.097589 Set Vref, RX VrefLevel [Byte0]: 65
3399 13:18:52.101086 [Byte1]: 65
3400 13:18:52.105739
3401 13:18:52.105808 Set Vref, RX VrefLevel [Byte0]: 66
3402 13:18:52.108740 [Byte1]: 66
3403 13:18:52.113292
3404 13:18:52.113438 Set Vref, RX VrefLevel [Byte0]: 67
3405 13:18:52.116753 [Byte1]: 67
3406 13:18:52.121104
3407 13:18:52.121189 Set Vref, RX VrefLevel [Byte0]: 68
3408 13:18:52.124704 [Byte1]: 68
3409 13:18:52.129016
3410 13:18:52.129102 Set Vref, RX VrefLevel [Byte0]: 69
3411 13:18:52.132680 [Byte1]: 69
3412 13:18:52.136939
3413 13:18:52.137030 Set Vref, RX VrefLevel [Byte0]: 70
3414 13:18:52.140648 [Byte1]: 70
3415 13:18:52.145251
3416 13:18:52.145316 Set Vref, RX VrefLevel [Byte0]: 71
3417 13:18:52.148140 [Byte1]: 71
3418 13:18:52.153618
3419 13:18:52.153693 Final RX Vref Byte 0 = 61 to rank0
3420 13:18:52.156012 Final RX Vref Byte 1 = 53 to rank0
3421 13:18:52.159877 Final RX Vref Byte 0 = 61 to rank1
3422 13:18:52.162921 Final RX Vref Byte 1 = 53 to rank1==
3423 13:18:52.166492 Dram Type= 6, Freq= 0, CH_1, rank 0
3424 13:18:52.173241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 13:18:52.173310 ==
3426 13:18:52.173366 DQS Delay:
3427 13:18:52.173463 DQS0 = 0, DQS1 = 0
3428 13:18:52.176323 DQM Delay:
3429 13:18:52.176387 DQM0 = 116, DQM1 = 109
3430 13:18:52.179767 DQ Delay:
3431 13:18:52.182701 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3432 13:18:52.186119 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3433 13:18:52.189370 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3434 13:18:52.193109 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3435 13:18:52.193216
3436 13:18:52.193275
3437 13:18:52.199647 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3438 13:18:52.202674 CH1 RK0: MR19=403, MR18=2E6
3439 13:18:52.209415 CH1_RK0: MR19=0x403, MR18=0x2E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3440 13:18:52.209533
3441 13:18:52.212986 ----->DramcWriteLeveling(PI) begin...
3442 13:18:52.213079 ==
3443 13:18:52.216043 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 13:18:52.219401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 13:18:52.219539 ==
3446 13:18:52.222714 Write leveling (Byte 0): 26 => 26
3447 13:18:52.226384 Write leveling (Byte 1): 28 => 28
3448 13:18:52.229447 DramcWriteLeveling(PI) end<-----
3449 13:18:52.229527
3450 13:18:52.229585 ==
3451 13:18:52.233081 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 13:18:52.236643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 13:18:52.239731 ==
3454 13:18:52.239821 [Gating] SW mode calibration
3455 13:18:52.249404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3456 13:18:52.252942 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3457 13:18:52.256095 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3458 13:18:52.262930 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 13:18:52.266387 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 13:18:52.269377 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 13:18:52.276032 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 13:18:52.279649 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3463 13:18:52.282628 0 15 24 | B1->B0 | 3535 2f2f | 0 0 | (0 0) (0 1)
3464 13:18:52.289445 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
3465 13:18:52.292722 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 13:18:52.296003 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 13:18:52.302811 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 13:18:52.306159 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 13:18:52.309282 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 13:18:52.316048 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3471 13:18:52.319822 1 0 24 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (1 1)
3472 13:18:52.322847 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3473 13:18:52.329502 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3474 13:18:52.332751 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 13:18:52.336041 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 13:18:52.339162 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 13:18:52.345952 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 13:18:52.349588 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3479 13:18:52.352710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3480 13:18:52.359560 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3481 13:18:52.363339 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 13:18:52.366236 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 13:18:52.373088 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:18:52.376672 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:18:52.379413 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:18:52.386683 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:18:52.389683 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:18:52.392703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:18:52.399295 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 13:18:52.402941 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 13:18:52.406161 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 13:18:52.412949 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 13:18:52.416126 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 13:18:52.419466 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3495 13:18:52.423190 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3496 13:18:52.429798 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3497 13:18:52.433063 Total UI for P1: 0, mck2ui 16
3498 13:18:52.436101 best dqsien dly found for B0: ( 1, 3, 22)
3499 13:18:52.439702 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 13:18:52.443019 Total UI for P1: 0, mck2ui 16
3501 13:18:52.446293 best dqsien dly found for B1: ( 1, 3, 28)
3502 13:18:52.449727 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3503 13:18:52.452708 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3504 13:18:52.452788
3505 13:18:52.456514 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3506 13:18:52.459571 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3507 13:18:52.462585 [Gating] SW calibration Done
3508 13:18:52.462650 ==
3509 13:18:52.466369 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 13:18:52.472925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 13:18:52.472992 ==
3512 13:18:52.473047 RX Vref Scan: 0
3513 13:18:52.473099
3514 13:18:52.476361 RX Vref 0 -> 0, step: 1
3515 13:18:52.476421
3516 13:18:52.479256 RX Delay -40 -> 252, step: 8
3517 13:18:52.482804 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3518 13:18:52.486262 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3519 13:18:52.489370 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3520 13:18:52.493016 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3521 13:18:52.499748 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3522 13:18:52.502825 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3523 13:18:52.506429 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3524 13:18:52.509515 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3525 13:18:52.513301 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3526 13:18:52.516132 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3527 13:18:52.523119 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3528 13:18:52.526179 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3529 13:18:52.529393 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3530 13:18:52.533019 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3531 13:18:52.539459 iDelay=192, Bit 14, Center 115 (40 ~ 191) 152
3532 13:18:52.543134 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3533 13:18:52.543205 ==
3534 13:18:52.546140 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 13:18:52.549391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 13:18:52.549458 ==
3537 13:18:52.549516 DQS Delay:
3538 13:18:52.552855 DQS0 = 0, DQS1 = 0
3539 13:18:52.552919 DQM Delay:
3540 13:18:52.556229 DQM0 = 113, DQM1 = 110
3541 13:18:52.556302 DQ Delay:
3542 13:18:52.559804 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3543 13:18:52.562883 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3544 13:18:52.566478 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3545 13:18:52.569546 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3546 13:18:52.569651
3547 13:18:52.573105
3548 13:18:52.573247 ==
3549 13:18:52.576703 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 13:18:52.579748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 13:18:52.579850 ==
3552 13:18:52.579904
3553 13:18:52.579958
3554 13:18:52.583243 TX Vref Scan disable
3555 13:18:52.583329 == TX Byte 0 ==
3556 13:18:52.589865 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3557 13:18:52.592751 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3558 13:18:52.592849 == TX Byte 1 ==
3559 13:18:52.600060 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3560 13:18:52.603135 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3561 13:18:52.603204 ==
3562 13:18:52.606853 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 13:18:52.609941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 13:18:52.610009 ==
3565 13:18:52.621994 TX Vref=22, minBit 2, minWin=25, winSum=421
3566 13:18:52.624940 TX Vref=24, minBit 2, minWin=25, winSum=426
3567 13:18:52.628526 TX Vref=26, minBit 1, minWin=26, winSum=429
3568 13:18:52.631493 TX Vref=28, minBit 3, minWin=26, winSum=434
3569 13:18:52.635122 TX Vref=30, minBit 0, minWin=27, winSum=434
3570 13:18:52.641711 TX Vref=32, minBit 0, minWin=26, winSum=431
3571 13:18:52.644969 [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 30
3572 13:18:52.645058
3573 13:18:52.648155 Final TX Range 1 Vref 30
3574 13:18:52.648219
3575 13:18:52.648272 ==
3576 13:18:52.651598 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 13:18:52.655161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 13:18:52.655235 ==
3579 13:18:52.658011
3580 13:18:52.658082
3581 13:18:52.658138 TX Vref Scan disable
3582 13:18:52.661362 == TX Byte 0 ==
3583 13:18:52.664840 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3584 13:18:52.668099 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3585 13:18:52.671435 == TX Byte 1 ==
3586 13:18:52.675013 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3587 13:18:52.678060 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3588 13:18:52.681859
3589 13:18:52.681927 [DATLAT]
3590 13:18:52.681984 Freq=1200, CH1 RK1
3591 13:18:52.682037
3592 13:18:52.685033 DATLAT Default: 0xd
3593 13:18:52.685100 0, 0xFFFF, sum = 0
3594 13:18:52.688057 1, 0xFFFF, sum = 0
3595 13:18:52.688123 2, 0xFFFF, sum = 0
3596 13:18:52.691553 3, 0xFFFF, sum = 0
3597 13:18:52.691622 4, 0xFFFF, sum = 0
3598 13:18:52.694932 5, 0xFFFF, sum = 0
3599 13:18:52.695000 6, 0xFFFF, sum = 0
3600 13:18:52.698522 7, 0xFFFF, sum = 0
3601 13:18:52.701384 8, 0xFFFF, sum = 0
3602 13:18:52.701455 9, 0xFFFF, sum = 0
3603 13:18:52.704972 10, 0xFFFF, sum = 0
3604 13:18:52.705068 11, 0xFFFF, sum = 0
3605 13:18:52.707929 12, 0x0, sum = 1
3606 13:18:52.707994 13, 0x0, sum = 2
3607 13:18:52.711578 14, 0x0, sum = 3
3608 13:18:52.711643 15, 0x0, sum = 4
3609 13:18:52.711699 best_step = 13
3610 13:18:52.711750
3611 13:18:52.715154 ==
3612 13:18:52.718174 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 13:18:52.721757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 13:18:52.721826 ==
3615 13:18:52.721881 RX Vref Scan: 0
3616 13:18:52.721934
3617 13:18:52.725265 RX Vref 0 -> 0, step: 1
3618 13:18:52.725330
3619 13:18:52.728246 RX Delay -21 -> 252, step: 4
3620 13:18:52.731342 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3621 13:18:52.738639 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3622 13:18:52.741641 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3623 13:18:52.744743 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3624 13:18:52.748378 iDelay=191, Bit 4, Center 112 (47 ~ 178) 132
3625 13:18:52.751490 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3626 13:18:52.755125 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3627 13:18:52.761768 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3628 13:18:52.764971 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3629 13:18:52.768340 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3630 13:18:52.771481 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3631 13:18:52.775158 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3632 13:18:52.781514 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3633 13:18:52.785029 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3634 13:18:52.788176 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3635 13:18:52.791861 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3636 13:18:52.791926 ==
3637 13:18:52.794883 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 13:18:52.798372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 13:18:52.801589 ==
3640 13:18:52.801653 DQS Delay:
3641 13:18:52.801709 DQS0 = 0, DQS1 = 0
3642 13:18:52.804986 DQM Delay:
3643 13:18:52.805074 DQM0 = 113, DQM1 = 109
3644 13:18:52.808782 DQ Delay:
3645 13:18:52.812219 DQ0 =112, DQ1 =108, DQ2 =106, DQ3 =112
3646 13:18:52.815136 DQ4 =112, DQ5 =124, DQ6 =120, DQ7 =110
3647 13:18:52.818326 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3648 13:18:52.821944 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118
3649 13:18:52.822015
3650 13:18:52.822072
3651 13:18:52.828459 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3652 13:18:52.831967 CH1 RK1: MR19=304, MR18=FA01
3653 13:18:52.838807 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3654 13:18:52.841832 [RxdqsGatingPostProcess] freq 1200
3655 13:18:52.848635 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3656 13:18:52.851682 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 13:18:52.851751 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 13:18:52.855447 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 13:18:52.858532 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 13:18:52.861601 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 13:18:52.865268 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 13:18:52.868449 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 13:18:52.872044 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 13:18:52.875547 Pre-setting of DQS Precalculation
3665 13:18:52.881928 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3666 13:18:52.888644 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3667 13:18:52.895409 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3668 13:18:52.895478
3669 13:18:52.895534
3670 13:18:52.898625 [Calibration Summary] 2400 Mbps
3671 13:18:52.898689 CH 0, Rank 0
3672 13:18:52.901774 SW Impedance : PASS
3673 13:18:52.905477 DUTY Scan : NO K
3674 13:18:52.905542 ZQ Calibration : PASS
3675 13:18:52.908585 Jitter Meter : NO K
3676 13:18:52.908652 CBT Training : PASS
3677 13:18:52.912042 Write leveling : PASS
3678 13:18:52.915042 RX DQS gating : PASS
3679 13:18:52.915111 RX DQ/DQS(RDDQC) : PASS
3680 13:18:52.918495 TX DQ/DQS : PASS
3681 13:18:52.922120 RX DATLAT : PASS
3682 13:18:52.922192 RX DQ/DQS(Engine): PASS
3683 13:18:52.925091 TX OE : NO K
3684 13:18:52.925176 All Pass.
3685 13:18:52.925232
3686 13:18:52.928815 CH 0, Rank 1
3687 13:18:52.928878 SW Impedance : PASS
3688 13:18:52.931758 DUTY Scan : NO K
3689 13:18:52.935243 ZQ Calibration : PASS
3690 13:18:52.935311 Jitter Meter : NO K
3691 13:18:52.938889 CBT Training : PASS
3692 13:18:52.941916 Write leveling : PASS
3693 13:18:52.941982 RX DQS gating : PASS
3694 13:18:52.945010 RX DQ/DQS(RDDQC) : PASS
3695 13:18:52.945074 TX DQ/DQS : PASS
3696 13:18:52.948723 RX DATLAT : PASS
3697 13:18:52.951783 RX DQ/DQS(Engine): PASS
3698 13:18:52.951848 TX OE : NO K
3699 13:18:52.955453 All Pass.
3700 13:18:52.955521
3701 13:18:52.955576 CH 1, Rank 0
3702 13:18:52.958525 SW Impedance : PASS
3703 13:18:52.958589 DUTY Scan : NO K
3704 13:18:52.962191 ZQ Calibration : PASS
3705 13:18:52.965206 Jitter Meter : NO K
3706 13:18:52.965299 CBT Training : PASS
3707 13:18:52.968848 Write leveling : PASS
3708 13:18:52.971924 RX DQS gating : PASS
3709 13:18:52.971990 RX DQ/DQS(RDDQC) : PASS
3710 13:18:52.975522 TX DQ/DQS : PASS
3711 13:18:52.978459 RX DATLAT : PASS
3712 13:18:52.978528 RX DQ/DQS(Engine): PASS
3713 13:18:52.982078 TX OE : NO K
3714 13:18:52.982146 All Pass.
3715 13:18:52.982201
3716 13:18:52.985316 CH 1, Rank 1
3717 13:18:52.985381 SW Impedance : PASS
3718 13:18:52.988599 DUTY Scan : NO K
3719 13:18:52.991906 ZQ Calibration : PASS
3720 13:18:52.991973 Jitter Meter : NO K
3721 13:18:52.995206 CBT Training : PASS
3722 13:18:52.995270 Write leveling : PASS
3723 13:18:52.998855 RX DQS gating : PASS
3724 13:18:53.002004 RX DQ/DQS(RDDQC) : PASS
3725 13:18:53.002073 TX DQ/DQS : PASS
3726 13:18:53.005473 RX DATLAT : PASS
3727 13:18:53.008853 RX DQ/DQS(Engine): PASS
3728 13:18:53.008949 TX OE : NO K
3729 13:18:53.012182 All Pass.
3730 13:18:53.012249
3731 13:18:53.012305 DramC Write-DBI off
3732 13:18:53.015674 PER_BANK_REFRESH: Hybrid Mode
3733 13:18:53.015745 TX_TRACKING: ON
3734 13:18:53.025049 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3735 13:18:53.028524 [FAST_K] Save calibration result to emmc
3736 13:18:53.031941 dramc_set_vcore_voltage set vcore to 650000
3737 13:18:53.035586 Read voltage for 600, 5
3738 13:18:53.035656 Vio18 = 0
3739 13:18:53.038337 Vcore = 650000
3740 13:18:53.038407 Vdram = 0
3741 13:18:53.038464 Vddq = 0
3742 13:18:53.042011 Vmddr = 0
3743 13:18:53.044976 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3744 13:18:53.051631 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3745 13:18:53.051705 MEM_TYPE=3, freq_sel=19
3746 13:18:53.055396 sv_algorithm_assistance_LP4_1600
3747 13:18:53.061561 ============ PULL DRAM RESETB DOWN ============
3748 13:18:53.065463 ========== PULL DRAM RESETB DOWN end =========
3749 13:18:53.068435 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3750 13:18:53.072019 ===================================
3751 13:18:53.075127 LPDDR4 DRAM CONFIGURATION
3752 13:18:53.078096 ===================================
3753 13:18:53.078163 EX_ROW_EN[0] = 0x0
3754 13:18:53.081565 EX_ROW_EN[1] = 0x0
3755 13:18:53.085023 LP4Y_EN = 0x0
3756 13:18:53.085106 WORK_FSP = 0x0
3757 13:18:53.088141 WL = 0x2
3758 13:18:53.088212 RL = 0x2
3759 13:18:53.091738 BL = 0x2
3760 13:18:53.091807 RPST = 0x0
3761 13:18:53.095124 RD_PRE = 0x0
3762 13:18:53.095208 WR_PRE = 0x1
3763 13:18:53.098492 WR_PST = 0x0
3764 13:18:53.098569 DBI_WR = 0x0
3765 13:18:53.101702 DBI_RD = 0x0
3766 13:18:53.101779 OTF = 0x1
3767 13:18:53.104988 ===================================
3768 13:18:53.108520 ===================================
3769 13:18:53.111639 ANA top config
3770 13:18:53.114762 ===================================
3771 13:18:53.114840 DLL_ASYNC_EN = 0
3772 13:18:53.118404 ALL_SLAVE_EN = 1
3773 13:18:53.121929 NEW_RANK_MODE = 1
3774 13:18:53.125325 DLL_IDLE_MODE = 1
3775 13:18:53.125396 LP45_APHY_COMB_EN = 1
3776 13:18:53.128837 TX_ODT_DIS = 1
3777 13:18:53.132054 NEW_8X_MODE = 1
3778 13:18:53.135873 ===================================
3779 13:18:53.138553 ===================================
3780 13:18:53.141668 data_rate = 1200
3781 13:18:53.145072 CKR = 1
3782 13:18:53.145204 DQ_P2S_RATIO = 8
3783 13:18:53.148607 ===================================
3784 13:18:53.151658 CA_P2S_RATIO = 8
3785 13:18:53.155351 DQ_CA_OPEN = 0
3786 13:18:53.158499 DQ_SEMI_OPEN = 0
3787 13:18:53.162044 CA_SEMI_OPEN = 0
3788 13:18:53.165249 CA_FULL_RATE = 0
3789 13:18:53.165322 DQ_CKDIV4_EN = 1
3790 13:18:53.168432 CA_CKDIV4_EN = 1
3791 13:18:53.171983 CA_PREDIV_EN = 0
3792 13:18:53.175662 PH8_DLY = 0
3793 13:18:53.178709 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3794 13:18:53.182377 DQ_AAMCK_DIV = 4
3795 13:18:53.182448 CA_AAMCK_DIV = 4
3796 13:18:53.185197 CA_ADMCK_DIV = 4
3797 13:18:53.188455 DQ_TRACK_CA_EN = 0
3798 13:18:53.192071 CA_PICK = 600
3799 13:18:53.195230 CA_MCKIO = 600
3800 13:18:53.198821 MCKIO_SEMI = 0
3801 13:18:53.198920 PLL_FREQ = 2288
3802 13:18:53.201865 DQ_UI_PI_RATIO = 32
3803 13:18:53.205433 CA_UI_PI_RATIO = 0
3804 13:18:53.208802 ===================================
3805 13:18:53.212066 ===================================
3806 13:18:53.215512 memory_type:LPDDR4
3807 13:18:53.215581 GP_NUM : 10
3808 13:18:53.218994 SRAM_EN : 1
3809 13:18:53.222187 MD32_EN : 0
3810 13:18:53.225301 ===================================
3811 13:18:53.225371 [ANA_INIT] >>>>>>>>>>>>>>
3812 13:18:53.228956 <<<<<< [CONFIGURE PHASE]: ANA_TX
3813 13:18:53.232076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3814 13:18:53.235652 ===================================
3815 13:18:53.238701 data_rate = 1200,PCW = 0X5800
3816 13:18:53.242256 ===================================
3817 13:18:53.245914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3818 13:18:53.252122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 13:18:53.255623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 13:18:53.262432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3821 13:18:53.265493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3822 13:18:53.269230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3823 13:18:53.269301 [ANA_INIT] flow start
3824 13:18:53.272506 [ANA_INIT] PLL >>>>>>>>
3825 13:18:53.275911 [ANA_INIT] PLL <<<<<<<<
3826 13:18:53.275996 [ANA_INIT] MIDPI >>>>>>>>
3827 13:18:53.278926 [ANA_INIT] MIDPI <<<<<<<<
3828 13:18:53.282608 [ANA_INIT] DLL >>>>>>>>
3829 13:18:53.282677 [ANA_INIT] flow end
3830 13:18:53.289365 ============ LP4 DIFF to SE enter ============
3831 13:18:53.292109 ============ LP4 DIFF to SE exit ============
3832 13:18:53.295794 [ANA_INIT] <<<<<<<<<<<<<
3833 13:18:53.298849 [Flow] Enable top DCM control >>>>>
3834 13:18:53.302482 [Flow] Enable top DCM control <<<<<
3835 13:18:53.302551 Enable DLL master slave shuffle
3836 13:18:53.309095 ==============================================================
3837 13:18:53.312643 Gating Mode config
3838 13:18:53.315983 ==============================================================
3839 13:18:53.319211 Config description:
3840 13:18:53.328903 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3841 13:18:53.335530 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3842 13:18:53.339082 SELPH_MODE 0: By rank 1: By Phase
3843 13:18:53.345711 ==============================================================
3844 13:18:53.349293 GAT_TRACK_EN = 1
3845 13:18:53.352600 RX_GATING_MODE = 2
3846 13:18:53.355945 RX_GATING_TRACK_MODE = 2
3847 13:18:53.356023 SELPH_MODE = 1
3848 13:18:53.358987 PICG_EARLY_EN = 1
3849 13:18:53.362380 VALID_LAT_VALUE = 1
3850 13:18:53.369042 ==============================================================
3851 13:18:53.372614 Enter into Gating configuration >>>>
3852 13:18:53.375632 Exit from Gating configuration <<<<
3853 13:18:53.379262 Enter into DVFS_PRE_config >>>>>
3854 13:18:53.389045 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3855 13:18:53.392138 Exit from DVFS_PRE_config <<<<<
3856 13:18:53.395686 Enter into PICG configuration >>>>
3857 13:18:53.399407 Exit from PICG configuration <<<<
3858 13:18:53.402308 [RX_INPUT] configuration >>>>>
3859 13:18:53.405392 [RX_INPUT] configuration <<<<<
3860 13:18:53.408696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3861 13:18:53.415829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3862 13:18:53.422423 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 13:18:53.428978 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 13:18:53.432350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 13:18:53.438885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 13:18:53.442024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3867 13:18:53.448723 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3868 13:18:53.452376 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3869 13:18:53.455552 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3870 13:18:53.458582 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3871 13:18:53.465386 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 13:18:53.469035 ===================================
3873 13:18:53.469155 LPDDR4 DRAM CONFIGURATION
3874 13:18:53.472088 ===================================
3875 13:18:53.475716 EX_ROW_EN[0] = 0x0
3876 13:18:53.478983 EX_ROW_EN[1] = 0x0
3877 13:18:53.479054 LP4Y_EN = 0x0
3878 13:18:53.482261 WORK_FSP = 0x0
3879 13:18:53.482329 WL = 0x2
3880 13:18:53.485506 RL = 0x2
3881 13:18:53.485571 BL = 0x2
3882 13:18:53.489005 RPST = 0x0
3883 13:18:53.489094 RD_PRE = 0x0
3884 13:18:53.492599 WR_PRE = 0x1
3885 13:18:53.492687 WR_PST = 0x0
3886 13:18:53.495605 DBI_WR = 0x0
3887 13:18:53.495673 DBI_RD = 0x0
3888 13:18:53.498724 OTF = 0x1
3889 13:18:53.502116 ===================================
3890 13:18:53.505735 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3891 13:18:53.508797 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3892 13:18:53.515791 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3893 13:18:53.518982 ===================================
3894 13:18:53.519055 LPDDR4 DRAM CONFIGURATION
3895 13:18:53.521999 ===================================
3896 13:18:53.525687 EX_ROW_EN[0] = 0x10
3897 13:18:53.525759 EX_ROW_EN[1] = 0x0
3898 13:18:53.528790 LP4Y_EN = 0x0
3899 13:18:53.532409 WORK_FSP = 0x0
3900 13:18:53.532477 WL = 0x2
3901 13:18:53.535370 RL = 0x2
3902 13:18:53.535445 BL = 0x2
3903 13:18:53.538745 RPST = 0x0
3904 13:18:53.538835 RD_PRE = 0x0
3905 13:18:53.542153 WR_PRE = 0x1
3906 13:18:53.542245 WR_PST = 0x0
3907 13:18:53.545842 DBI_WR = 0x0
3908 13:18:53.545915 DBI_RD = 0x0
3909 13:18:53.549079 OTF = 0x1
3910 13:18:53.552459 ===================================
3911 13:18:53.555608 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3912 13:18:53.561304 nWR fixed to 30
3913 13:18:53.564259 [ModeRegInit_LP4] CH0 RK0
3914 13:18:53.564328 [ModeRegInit_LP4] CH0 RK1
3915 13:18:53.567962 [ModeRegInit_LP4] CH1 RK0
3916 13:18:53.571442 [ModeRegInit_LP4] CH1 RK1
3917 13:18:53.571513 match AC timing 17
3918 13:18:53.578214 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3919 13:18:53.581384 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3920 13:18:53.584452 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3921 13:18:53.591605 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3922 13:18:53.594701 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3923 13:18:53.594771 ==
3924 13:18:53.598208 Dram Type= 6, Freq= 0, CH_0, rank 0
3925 13:18:53.601026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3926 13:18:53.601149 ==
3927 13:18:53.608092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3928 13:18:53.614313 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3929 13:18:53.617761 [CA 0] Center 36 (6~66) winsize 61
3930 13:18:53.621173 [CA 1] Center 36 (6~66) winsize 61
3931 13:18:53.624249 [CA 2] Center 34 (4~65) winsize 62
3932 13:18:53.627872 [CA 3] Center 34 (4~65) winsize 62
3933 13:18:53.630987 [CA 4] Center 33 (3~64) winsize 62
3934 13:18:53.634649 [CA 5] Center 33 (3~64) winsize 62
3935 13:18:53.634739
3936 13:18:53.637935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3937 13:18:53.638009
3938 13:18:53.641030 [CATrainingPosCal] consider 1 rank data
3939 13:18:53.644673 u2DelayCellTimex100 = 270/100 ps
3940 13:18:53.648072 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3941 13:18:53.650939 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3942 13:18:53.654533 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3943 13:18:53.657585 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3944 13:18:53.661218 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3945 13:18:53.664767 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3946 13:18:53.664857
3947 13:18:53.671296 CA PerBit enable=1, Macro0, CA PI delay=33
3948 13:18:53.671365
3949 13:18:53.671436 [CBTSetCACLKResult] CA Dly = 33
3950 13:18:53.674699 CS Dly: 5 (0~36)
3951 13:18:53.674769 ==
3952 13:18:53.677766 Dram Type= 6, Freq= 0, CH_0, rank 1
3953 13:18:53.681050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 13:18:53.681137 ==
3955 13:18:53.687645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 13:18:53.694205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 13:18:53.697851 [CA 0] Center 36 (6~66) winsize 61
3958 13:18:53.700782 [CA 1] Center 36 (6~66) winsize 61
3959 13:18:53.704587 [CA 2] Center 34 (4~65) winsize 62
3960 13:18:53.707618 [CA 3] Center 34 (4~65) winsize 62
3961 13:18:53.710729 [CA 4] Center 33 (3~64) winsize 62
3962 13:18:53.714399 [CA 5] Center 33 (3~64) winsize 62
3963 13:18:53.714483
3964 13:18:53.717555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 13:18:53.717632
3966 13:18:53.720629 [CATrainingPosCal] consider 2 rank data
3967 13:18:53.724146 u2DelayCellTimex100 = 270/100 ps
3968 13:18:53.727150 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 13:18:53.730812 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 13:18:53.733907 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 13:18:53.737661 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 13:18:53.740581 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 13:18:53.747269 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 13:18:53.747345
3975 13:18:53.750781 CA PerBit enable=1, Macro0, CA PI delay=33
3976 13:18:53.750857
3977 13:18:53.753801 [CBTSetCACLKResult] CA Dly = 33
3978 13:18:53.753877 CS Dly: 5 (0~37)
3979 13:18:53.753937
3980 13:18:53.757100 ----->DramcWriteLeveling(PI) begin...
3981 13:18:53.757215 ==
3982 13:18:53.760600 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 13:18:53.767453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 13:18:53.767530 ==
3985 13:18:53.770549 Write leveling (Byte 0): 31 => 31
3986 13:18:53.770625 Write leveling (Byte 1): 31 => 31
3987 13:18:53.774168 DramcWriteLeveling(PI) end<-----
3988 13:18:53.774259
3989 13:18:53.774346 ==
3990 13:18:53.777189 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 13:18:53.783790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 13:18:53.783892 ==
3993 13:18:53.787101 [Gating] SW mode calibration
3994 13:18:53.793924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3995 13:18:53.797861 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3996 13:18:53.800781 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 13:18:53.807437 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 13:18:53.810489 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 13:18:53.814163 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 13:18:53.820494 0 9 16 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 0)
4001 13:18:53.824314 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 13:18:53.827354 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 13:18:53.833944 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 13:18:53.837411 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 13:18:53.841001 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 13:18:53.847600 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 13:18:53.850670 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4008 13:18:53.854605 0 10 16 | B1->B0 | 2e2e 3b3b | 1 0 | (0 0) (0 0)
4009 13:18:53.860832 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4010 13:18:53.864239 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 13:18:53.867578 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 13:18:53.874249 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 13:18:53.877926 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 13:18:53.881010 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 13:18:53.884097 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 13:18:53.890585 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4017 13:18:53.894216 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:18:53.897654 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:18:53.904380 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:18:53.907545 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:18:53.910985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:18:53.917382 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:18:53.921031 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:18:53.924132 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:18:53.931253 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:18:53.934339 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:18:53.937706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:18:53.944074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 13:18:53.947754 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 13:18:53.950990 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 13:18:53.957961 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 13:18:53.960946 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4033 13:18:53.964059 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 13:18:53.967862 Total UI for P1: 0, mck2ui 16
4035 13:18:53.971299 best dqsien dly found for B0: ( 0, 13, 16)
4036 13:18:53.974093 Total UI for P1: 0, mck2ui 16
4037 13:18:53.977675 best dqsien dly found for B1: ( 0, 13, 16)
4038 13:18:53.981374 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4039 13:18:53.984442 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4040 13:18:53.984511
4041 13:18:53.988033 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4042 13:18:53.994491 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4043 13:18:53.994564 [Gating] SW calibration Done
4044 13:18:53.994621 ==
4045 13:18:53.997542 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 13:18:54.004183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 13:18:54.004255 ==
4048 13:18:54.004314 RX Vref Scan: 0
4049 13:18:54.004373
4050 13:18:54.007855 RX Vref 0 -> 0, step: 1
4051 13:18:54.007946
4052 13:18:54.011398 RX Delay -230 -> 252, step: 16
4053 13:18:54.014460 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4054 13:18:54.017878 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4055 13:18:54.021098 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4056 13:18:54.027836 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4057 13:18:54.030904 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4058 13:18:54.034406 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4059 13:18:54.037932 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4060 13:18:54.041028 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4061 13:18:54.048095 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4062 13:18:54.051084 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4063 13:18:54.054675 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4064 13:18:54.058076 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4065 13:18:54.064636 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4066 13:18:54.067808 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4067 13:18:54.070963 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4068 13:18:54.074453 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4069 13:18:54.074524 ==
4070 13:18:54.078119 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 13:18:54.084216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 13:18:54.084293 ==
4073 13:18:54.084367 DQS Delay:
4074 13:18:54.087551 DQS0 = 0, DQS1 = 0
4075 13:18:54.087617 DQM Delay:
4076 13:18:54.087672 DQM0 = 42, DQM1 = 32
4077 13:18:54.090925 DQ Delay:
4078 13:18:54.094503 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4079 13:18:54.097963 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4080 13:18:54.101060 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4081 13:18:54.104777 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4082 13:18:54.104866
4083 13:18:54.104945
4084 13:18:54.105033 ==
4085 13:18:54.107651 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 13:18:54.111316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 13:18:54.111382 ==
4088 13:18:54.111438
4089 13:18:54.111489
4090 13:18:54.114349 TX Vref Scan disable
4091 13:18:54.114413 == TX Byte 0 ==
4092 13:18:54.121653 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4093 13:18:54.124629 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4094 13:18:54.124699 == TX Byte 1 ==
4095 13:18:54.131380 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4096 13:18:54.134836 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4097 13:18:54.134903 ==
4098 13:18:54.138161 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 13:18:54.141393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 13:18:54.141484 ==
4101 13:18:54.141567
4102 13:18:54.144467
4103 13:18:54.144531 TX Vref Scan disable
4104 13:18:54.148057 == TX Byte 0 ==
4105 13:18:54.151244 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4106 13:18:54.154632 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4107 13:18:54.157641 == TX Byte 1 ==
4108 13:18:54.161390 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4109 13:18:54.164249 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4110 13:18:54.168007
4111 13:18:54.168077 [DATLAT]
4112 13:18:54.168134 Freq=600, CH0 RK0
4113 13:18:54.168189
4114 13:18:54.170931 DATLAT Default: 0x9
4115 13:18:54.171023 0, 0xFFFF, sum = 0
4116 13:18:54.174467 1, 0xFFFF, sum = 0
4117 13:18:54.174541 2, 0xFFFF, sum = 0
4118 13:18:54.177708 3, 0xFFFF, sum = 0
4119 13:18:54.177786 4, 0xFFFF, sum = 0
4120 13:18:54.181006 5, 0xFFFF, sum = 0
4121 13:18:54.184279 6, 0xFFFF, sum = 0
4122 13:18:54.184357 7, 0xFFFF, sum = 0
4123 13:18:54.184416 8, 0x0, sum = 1
4124 13:18:54.188034 9, 0x0, sum = 2
4125 13:18:54.188104 10, 0x0, sum = 3
4126 13:18:54.191522 11, 0x0, sum = 4
4127 13:18:54.191594 best_step = 9
4128 13:18:54.191655
4129 13:18:54.191708 ==
4130 13:18:54.194755 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 13:18:54.201284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 13:18:54.201381 ==
4133 13:18:54.201462 RX Vref Scan: 1
4134 13:18:54.201545
4135 13:18:54.204766 RX Vref 0 -> 0, step: 1
4136 13:18:54.204861
4137 13:18:54.207827 RX Delay -195 -> 252, step: 8
4138 13:18:54.207892
4139 13:18:54.211385 Set Vref, RX VrefLevel [Byte0]: 53
4140 13:18:54.214535 [Byte1]: 54
4141 13:18:54.214608
4142 13:18:54.217592 Final RX Vref Byte 0 = 53 to rank0
4143 13:18:54.221227 Final RX Vref Byte 1 = 54 to rank0
4144 13:18:54.224198 Final RX Vref Byte 0 = 53 to rank1
4145 13:18:54.227798 Final RX Vref Byte 1 = 54 to rank1==
4146 13:18:54.230933 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 13:18:54.234720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 13:18:54.234818 ==
4149 13:18:54.237799 DQS Delay:
4150 13:18:54.237864 DQS0 = 0, DQS1 = 0
4151 13:18:54.237919 DQM Delay:
4152 13:18:54.240859 DQM0 = 43, DQM1 = 33
4153 13:18:54.240927 DQ Delay:
4154 13:18:54.244493 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4155 13:18:54.247465 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4156 13:18:54.251033 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4157 13:18:54.254226 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4158 13:18:54.254295
4159 13:18:54.254351
4160 13:18:54.264445 [DQSOSCAuto] RK0, (LSB)MR18= 0x4423, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4161 13:18:54.268012 CH0 RK0: MR19=808, MR18=4423
4162 13:18:54.271267 CH0_RK0: MR19=0x808, MR18=0x4423, DQSOSC=396, MR23=63, INC=167, DEC=111
4163 13:18:54.271338
4164 13:18:54.274144 ----->DramcWriteLeveling(PI) begin...
4165 13:18:54.277777 ==
4166 13:18:54.277850 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 13:18:54.284384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 13:18:54.284456 ==
4169 13:18:54.287479 Write leveling (Byte 0): 32 => 32
4170 13:18:54.290930 Write leveling (Byte 1): 28 => 28
4171 13:18:54.294444 DramcWriteLeveling(PI) end<-----
4172 13:18:54.294519
4173 13:18:54.294577 ==
4174 13:18:54.297809 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 13:18:54.301246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 13:18:54.301323 ==
4177 13:18:54.304415 [Gating] SW mode calibration
4178 13:18:54.311150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4179 13:18:54.314659 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4180 13:18:54.320957 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 13:18:54.324641 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 13:18:54.327770 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 13:18:54.334353 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4184 13:18:54.337983 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4185 13:18:54.341022 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 13:18:54.347993 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 13:18:54.351054 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 13:18:54.354600 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 13:18:54.361307 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 13:18:54.364322 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4191 13:18:54.367916 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4192 13:18:54.374314 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4193 13:18:54.377726 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 13:18:54.380864 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 13:18:54.387882 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 13:18:54.390938 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 13:18:54.394473 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 13:18:54.397503 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 13:18:54.404205 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 13:18:54.407814 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4201 13:18:54.410881 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 13:18:54.417905 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:18:54.421158 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:18:54.424254 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:18:54.430760 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:18:54.434695 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:18:54.437765 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:18:54.444353 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:18:54.447451 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:18:54.451027 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 13:18:54.457858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 13:18:54.460833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 13:18:54.464608 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 13:18:54.471235 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4215 13:18:54.474202 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4216 13:18:54.477978 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4217 13:18:54.480972 Total UI for P1: 0, mck2ui 16
4218 13:18:54.484776 best dqsien dly found for B0: ( 0, 13, 10)
4219 13:18:54.487518 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 13:18:54.490994 Total UI for P1: 0, mck2ui 16
4221 13:18:54.494580 best dqsien dly found for B1: ( 0, 13, 16)
4222 13:18:54.500889 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4223 13:18:54.504226 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4224 13:18:54.504303
4225 13:18:54.507773 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4226 13:18:54.510869 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4227 13:18:54.514490 [Gating] SW calibration Done
4228 13:18:54.514564 ==
4229 13:18:54.517489 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 13:18:54.521121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 13:18:54.521189 ==
4232 13:18:54.524188 RX Vref Scan: 0
4233 13:18:54.524257
4234 13:18:54.524311 RX Vref 0 -> 0, step: 1
4235 13:18:54.524363
4236 13:18:54.527780 RX Delay -230 -> 252, step: 16
4237 13:18:54.530770 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4238 13:18:54.537310 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4239 13:18:54.541048 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4240 13:18:54.544422 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4241 13:18:54.547650 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4242 13:18:54.551191 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4243 13:18:54.557460 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4244 13:18:54.560819 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4245 13:18:54.564529 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4246 13:18:54.567505 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4247 13:18:54.574168 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4248 13:18:54.577804 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4249 13:18:54.580836 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4250 13:18:54.584385 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4251 13:18:54.588051 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4252 13:18:54.594418 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4253 13:18:54.594489 ==
4254 13:18:54.598086 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 13:18:54.601046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 13:18:54.601114 ==
4257 13:18:54.601213 DQS Delay:
4258 13:18:54.604775 DQS0 = 0, DQS1 = 0
4259 13:18:54.604837 DQM Delay:
4260 13:18:54.607647 DQM0 = 43, DQM1 = 31
4261 13:18:54.607711 DQ Delay:
4262 13:18:54.611424 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4263 13:18:54.614690 DQ4 =49, DQ5 =25, DQ6 =57, DQ7 =57
4264 13:18:54.617744 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4265 13:18:54.621289 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4266 13:18:54.621378
4267 13:18:54.621438
4268 13:18:54.621491 ==
4269 13:18:54.624481 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 13:18:54.628144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 13:18:54.628220 ==
4272 13:18:54.628279
4273 13:18:54.631611
4274 13:18:54.631674 TX Vref Scan disable
4275 13:18:54.634543 == TX Byte 0 ==
4276 13:18:54.638146 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4277 13:18:54.641002 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4278 13:18:54.644636 == TX Byte 1 ==
4279 13:18:54.648084 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4280 13:18:54.651233 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4281 13:18:54.651300 ==
4282 13:18:54.654287 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 13:18:54.661472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 13:18:54.661551 ==
4285 13:18:54.661617
4286 13:18:54.661678
4287 13:18:54.661732 TX Vref Scan disable
4288 13:18:54.665856 == TX Byte 0 ==
4289 13:18:54.669496 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4290 13:18:54.672462 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4291 13:18:54.676025 == TX Byte 1 ==
4292 13:18:54.679690 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4293 13:18:54.682537 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4294 13:18:54.686248
4295 13:18:54.686315 [DATLAT]
4296 13:18:54.686371 Freq=600, CH0 RK1
4297 13:18:54.686424
4298 13:18:54.689250 DATLAT Default: 0x9
4299 13:18:54.689313 0, 0xFFFF, sum = 0
4300 13:18:54.692905 1, 0xFFFF, sum = 0
4301 13:18:54.692969 2, 0xFFFF, sum = 0
4302 13:18:54.695814 3, 0xFFFF, sum = 0
4303 13:18:54.695881 4, 0xFFFF, sum = 0
4304 13:18:54.699342 5, 0xFFFF, sum = 0
4305 13:18:54.699407 6, 0xFFFF, sum = 0
4306 13:18:54.702400 7, 0xFFFF, sum = 0
4307 13:18:54.702464 8, 0x0, sum = 1
4308 13:18:54.706161 9, 0x0, sum = 2
4309 13:18:54.706225 10, 0x0, sum = 3
4310 13:18:54.709074 11, 0x0, sum = 4
4311 13:18:54.709189 best_step = 9
4312 13:18:54.709242
4313 13:18:54.709292 ==
4314 13:18:54.712832 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 13:18:54.719552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 13:18:54.719619 ==
4317 13:18:54.719672 RX Vref Scan: 0
4318 13:18:54.719724
4319 13:18:54.722936 RX Vref 0 -> 0, step: 1
4320 13:18:54.723002
4321 13:18:54.726109 RX Delay -195 -> 252, step: 8
4322 13:18:54.729262 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4323 13:18:54.735916 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4324 13:18:54.739532 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4325 13:18:54.743026 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4326 13:18:54.746091 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4327 13:18:54.749030 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4328 13:18:54.756091 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4329 13:18:54.759050 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4330 13:18:54.762592 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4331 13:18:54.765835 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4332 13:18:54.769462 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4333 13:18:54.776103 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4334 13:18:54.779411 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4335 13:18:54.782802 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4336 13:18:54.786277 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4337 13:18:54.792608 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4338 13:18:54.792676 ==
4339 13:18:54.795865 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 13:18:54.799081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 13:18:54.799152 ==
4342 13:18:54.799210 DQS Delay:
4343 13:18:54.802468 DQS0 = 0, DQS1 = 0
4344 13:18:54.802533 DQM Delay:
4345 13:18:54.805781 DQM0 = 39, DQM1 = 32
4346 13:18:54.805845 DQ Delay:
4347 13:18:54.809343 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4348 13:18:54.812718 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4349 13:18:54.815770 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4350 13:18:54.819442 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4351 13:18:54.819507
4352 13:18:54.819564
4353 13:18:54.828969 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b2e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4354 13:18:54.829043 CH0 RK1: MR19=808, MR18=4B2E
4355 13:18:54.835980 CH0_RK1: MR19=0x808, MR18=0x4B2E, DQSOSC=395, MR23=63, INC=168, DEC=112
4356 13:18:54.839245 [RxdqsGatingPostProcess] freq 600
4357 13:18:54.846224 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4358 13:18:54.849212 Pre-setting of DQS Precalculation
4359 13:18:54.852843 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4360 13:18:54.852907 ==
4361 13:18:54.855737 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 13:18:54.859407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 13:18:54.859471 ==
4364 13:18:54.865630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 13:18:54.872294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4366 13:18:54.875947 [CA 0] Center 35 (5~66) winsize 62
4367 13:18:54.879042 [CA 1] Center 35 (5~66) winsize 62
4368 13:18:54.882706 [CA 2] Center 33 (3~64) winsize 62
4369 13:18:54.885724 [CA 3] Center 33 (3~64) winsize 62
4370 13:18:54.889484 [CA 4] Center 34 (3~65) winsize 63
4371 13:18:54.892568 [CA 5] Center 33 (3~64) winsize 62
4372 13:18:54.892630
4373 13:18:54.895627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4374 13:18:54.895686
4375 13:18:54.899356 [CATrainingPosCal] consider 1 rank data
4376 13:18:54.902835 u2DelayCellTimex100 = 270/100 ps
4377 13:18:54.905803 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4378 13:18:54.909027 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 13:18:54.912922 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 13:18:54.915842 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4381 13:18:54.919310 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4382 13:18:54.925729 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 13:18:54.925791
4384 13:18:54.928926 CA PerBit enable=1, Macro0, CA PI delay=33
4385 13:18:54.928987
4386 13:18:54.932389 [CBTSetCACLKResult] CA Dly = 33
4387 13:18:54.932457 CS Dly: 4 (0~35)
4388 13:18:54.932512 ==
4389 13:18:54.935784 Dram Type= 6, Freq= 0, CH_1, rank 1
4390 13:18:54.939107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 13:18:54.942278 ==
4392 13:18:54.945934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 13:18:54.952613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4394 13:18:54.955639 [CA 0] Center 35 (5~66) winsize 62
4395 13:18:54.959232 [CA 1] Center 36 (6~66) winsize 61
4396 13:18:54.962452 [CA 2] Center 34 (3~65) winsize 63
4397 13:18:54.966007 [CA 3] Center 34 (3~65) winsize 63
4398 13:18:54.969008 [CA 4] Center 34 (4~65) winsize 62
4399 13:18:54.972633 [CA 5] Center 33 (3~64) winsize 62
4400 13:18:54.972718
4401 13:18:54.975775 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4402 13:18:54.975842
4403 13:18:54.978817 [CATrainingPosCal] consider 2 rank data
4404 13:18:54.982417 u2DelayCellTimex100 = 270/100 ps
4405 13:18:54.985367 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 13:18:54.988966 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 13:18:54.992700 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 13:18:54.995839 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 13:18:54.998884 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 13:18:55.005675 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 13:18:55.005745
4412 13:18:55.009089 CA PerBit enable=1, Macro0, CA PI delay=33
4413 13:18:55.009187
4414 13:18:55.012189 [CBTSetCACLKResult] CA Dly = 33
4415 13:18:55.012256 CS Dly: 4 (0~36)
4416 13:18:55.012310
4417 13:18:55.015717 ----->DramcWriteLeveling(PI) begin...
4418 13:18:55.015785 ==
4419 13:18:55.018788 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 13:18:55.025641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 13:18:55.025716 ==
4422 13:18:55.029229 Write leveling (Byte 0): 29 => 29
4423 13:18:55.029299 Write leveling (Byte 1): 29 => 29
4424 13:18:55.032202 DramcWriteLeveling(PI) end<-----
4425 13:18:55.032263
4426 13:18:55.032317 ==
4427 13:18:55.035651 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 13:18:55.042204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 13:18:55.042269 ==
4430 13:18:55.045489 [Gating] SW mode calibration
4431 13:18:55.052563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4432 13:18:55.055457 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4433 13:18:55.062317 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 13:18:55.065935 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4435 13:18:55.069104 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 13:18:55.072568 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4437 13:18:55.079163 0 9 16 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
4438 13:18:55.082290 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 13:18:55.085910 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 13:18:55.092754 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4441 13:18:55.095728 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 13:18:55.099398 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 13:18:55.106008 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 13:18:55.108997 0 10 12 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
4445 13:18:55.112647 0 10 16 | B1->B0 | 3c3c 3e3e | 0 0 | (0 0) (1 1)
4446 13:18:55.119133 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 13:18:55.122248 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 13:18:55.125858 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 13:18:55.132513 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 13:18:55.135529 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 13:18:55.138955 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 13:18:55.146141 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4453 13:18:55.149213 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 13:18:55.152305 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:18:55.156269 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:18:55.162411 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:18:55.165702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:18:55.168994 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:18:55.175966 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:18:55.179209 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:18:55.182489 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:18:55.189204 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:18:55.192590 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:18:55.195659 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:18:55.202659 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 13:18:55.205754 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 13:18:55.208988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 13:18:55.215724 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4469 13:18:55.215794 Total UI for P1: 0, mck2ui 16
4470 13:18:55.222875 best dqsien dly found for B1: ( 0, 13, 10)
4471 13:18:55.225944 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 13:18:55.228985 Total UI for P1: 0, mck2ui 16
4473 13:18:55.232510 best dqsien dly found for B0: ( 0, 13, 12)
4474 13:18:55.235624 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4475 13:18:55.239282 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4476 13:18:55.239351
4477 13:18:55.242821 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4478 13:18:55.245716 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4479 13:18:55.249366 [Gating] SW calibration Done
4480 13:18:55.249447 ==
4481 13:18:55.252425 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 13:18:55.256128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 13:18:55.256200 ==
4484 13:18:55.259416 RX Vref Scan: 0
4485 13:18:55.259489
4486 13:18:55.262762 RX Vref 0 -> 0, step: 1
4487 13:18:55.262839
4488 13:18:55.265785 RX Delay -230 -> 252, step: 16
4489 13:18:55.269361 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4490 13:18:55.272436 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4491 13:18:55.275974 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4492 13:18:55.278957 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4493 13:18:55.285867 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4494 13:18:55.288868 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4495 13:18:55.292417 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4496 13:18:55.295946 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4497 13:18:55.302734 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4498 13:18:55.305846 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4499 13:18:55.308838 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4500 13:18:55.312407 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4501 13:18:55.315883 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4502 13:18:55.322808 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4503 13:18:55.325757 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4504 13:18:55.329448 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4505 13:18:55.329519 ==
4506 13:18:55.332297 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 13:18:55.335912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 13:18:55.339048 ==
4509 13:18:55.339119 DQS Delay:
4510 13:18:55.339175 DQS0 = 0, DQS1 = 0
4511 13:18:55.342679 DQM Delay:
4512 13:18:55.342746 DQM0 = 43, DQM1 = 35
4513 13:18:55.346057 DQ Delay:
4514 13:18:55.346123 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4515 13:18:55.349635 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4516 13:18:55.352767 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4517 13:18:55.355786 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4518 13:18:55.355857
4519 13:18:55.355913
4520 13:18:55.359561 ==
4521 13:18:55.362551 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 13:18:55.366069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 13:18:55.366139 ==
4524 13:18:55.366229
4525 13:18:55.366330
4526 13:18:55.369697 TX Vref Scan disable
4527 13:18:55.369768 == TX Byte 0 ==
4528 13:18:55.375885 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 13:18:55.379545 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 13:18:55.379614 == TX Byte 1 ==
4531 13:18:55.386125 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4532 13:18:55.389069 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4533 13:18:55.389201 ==
4534 13:18:55.392626 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 13:18:55.395630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 13:18:55.395707 ==
4537 13:18:55.395767
4538 13:18:55.395821
4539 13:18:55.399260 TX Vref Scan disable
4540 13:18:55.402202 == TX Byte 0 ==
4541 13:18:55.405753 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 13:18:55.409310 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 13:18:55.412316 == TX Byte 1 ==
4544 13:18:55.415812 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4545 13:18:55.419274 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4546 13:18:55.419344
4547 13:18:55.422737 [DATLAT]
4548 13:18:55.422806 Freq=600, CH1 RK0
4549 13:18:55.422861
4550 13:18:55.425999 DATLAT Default: 0x9
4551 13:18:55.426073 0, 0xFFFF, sum = 0
4552 13:18:55.429131 1, 0xFFFF, sum = 0
4553 13:18:55.429213 2, 0xFFFF, sum = 0
4554 13:18:55.432537 3, 0xFFFF, sum = 0
4555 13:18:55.432603 4, 0xFFFF, sum = 0
4556 13:18:55.435863 5, 0xFFFF, sum = 0
4557 13:18:55.435933 6, 0xFFFF, sum = 0
4558 13:18:55.439013 7, 0xFFFF, sum = 0
4559 13:18:55.439138 8, 0x0, sum = 1
4560 13:18:55.442571 9, 0x0, sum = 2
4561 13:18:55.442647 10, 0x0, sum = 3
4562 13:18:55.445709 11, 0x0, sum = 4
4563 13:18:55.445786 best_step = 9
4564 13:18:55.445845
4565 13:18:55.445899 ==
4566 13:18:55.449024 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 13:18:55.452574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 13:18:55.455568 ==
4569 13:18:55.455643 RX Vref Scan: 1
4570 13:18:55.455701
4571 13:18:55.459188 RX Vref 0 -> 0, step: 1
4572 13:18:55.459302
4573 13:18:55.462562 RX Delay -195 -> 252, step: 8
4574 13:18:55.462657
4575 13:18:55.465462 Set Vref, RX VrefLevel [Byte0]: 61
4576 13:18:55.465530 [Byte1]: 53
4577 13:18:55.470656
4578 13:18:55.470726 Final RX Vref Byte 0 = 61 to rank0
4579 13:18:55.474211 Final RX Vref Byte 1 = 53 to rank0
4580 13:18:55.477347 Final RX Vref Byte 0 = 61 to rank1
4581 13:18:55.480630 Final RX Vref Byte 1 = 53 to rank1==
4582 13:18:55.484211 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 13:18:55.490692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 13:18:55.490770 ==
4585 13:18:55.490829 DQS Delay:
4586 13:18:55.490883 DQS0 = 0, DQS1 = 0
4587 13:18:55.494305 DQM Delay:
4588 13:18:55.494381 DQM0 = 40, DQM1 = 32
4589 13:18:55.497426 DQ Delay:
4590 13:18:55.500809 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4591 13:18:55.500893 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4592 13:18:55.503870 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4593 13:18:55.507412 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4594 13:18:55.510824
4595 13:18:55.510912
4596 13:18:55.517393 [DQSOSCAuto] RK0, (LSB)MR18= 0x460b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4597 13:18:55.521077 CH1 RK0: MR19=808, MR18=460B
4598 13:18:55.527344 CH1_RK0: MR19=0x808, MR18=0x460B, DQSOSC=396, MR23=63, INC=167, DEC=111
4599 13:18:55.527458
4600 13:18:55.530998 ----->DramcWriteLeveling(PI) begin...
4601 13:18:55.531085 ==
4602 13:18:55.534065 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 13:18:55.537645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 13:18:55.537732 ==
4605 13:18:55.540547 Write leveling (Byte 0): 28 => 28
4606 13:18:55.543806 Write leveling (Byte 1): 31 => 31
4607 13:18:55.547518 DramcWriteLeveling(PI) end<-----
4608 13:18:55.547597
4609 13:18:55.547656 ==
4610 13:18:55.550385 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 13:18:55.553931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 13:18:55.554011 ==
4613 13:18:55.557080 [Gating] SW mode calibration
4614 13:18:55.564259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4615 13:18:55.570957 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4616 13:18:55.574016 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 13:18:55.577729 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 13:18:55.584142 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 13:18:55.587209 0 9 12 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
4620 13:18:55.590812 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4621 13:18:55.597296 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 13:18:55.600828 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 13:18:55.604276 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 13:18:55.610761 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4625 13:18:55.614132 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 13:18:55.617242 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4627 13:18:55.623689 0 10 12 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)
4628 13:18:55.627315 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4629 13:18:55.630815 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 13:18:55.637540 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 13:18:55.640580 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 13:18:55.643582 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 13:18:55.647226 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 13:18:55.654001 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 13:18:55.657290 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4636 13:18:55.660655 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4637 13:18:55.667403 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 13:18:55.670562 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:18:55.673984 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:18:55.680802 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:18:55.683785 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:18:55.687533 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:18:55.694149 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:18:55.697142 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 13:18:55.700489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 13:18:55.707324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 13:18:55.710723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 13:18:55.713754 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 13:18:55.720345 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 13:18:55.723783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4651 13:18:55.726931 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4652 13:18:55.730546 Total UI for P1: 0, mck2ui 16
4653 13:18:55.733928 best dqsien dly found for B0: ( 0, 13, 8)
4654 13:18:55.737027 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 13:18:55.740664 Total UI for P1: 0, mck2ui 16
4656 13:18:55.743712 best dqsien dly found for B1: ( 0, 13, 14)
4657 13:18:55.747328 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4658 13:18:55.754114 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4659 13:18:55.754222
4660 13:18:55.757207 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4661 13:18:55.760835 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4662 13:18:55.763829 [Gating] SW calibration Done
4663 13:18:55.763915 ==
4664 13:18:55.767307 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 13:18:55.770634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 13:18:55.770716 ==
4667 13:18:55.770777 RX Vref Scan: 0
4668 13:18:55.774090
4669 13:18:55.774169 RX Vref 0 -> 0, step: 1
4670 13:18:55.774230
4671 13:18:55.777158 RX Delay -230 -> 252, step: 16
4672 13:18:55.780788 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4673 13:18:55.787406 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4674 13:18:55.790679 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4675 13:18:55.793868 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4676 13:18:55.797095 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4677 13:18:55.800725 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4678 13:18:55.807481 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4679 13:18:55.810713 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4680 13:18:55.813671 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4681 13:18:55.817136 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4682 13:18:55.824025 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4683 13:18:55.826961 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4684 13:18:55.830596 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4685 13:18:55.833655 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4686 13:18:55.837287 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4687 13:18:55.843886 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4688 13:18:55.843970 ==
4689 13:18:55.847547 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 13:18:55.850466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 13:18:55.850545 ==
4692 13:18:55.850606 DQS Delay:
4693 13:18:55.853547 DQS0 = 0, DQS1 = 0
4694 13:18:55.853625 DQM Delay:
4695 13:18:55.857074 DQM0 = 40, DQM1 = 36
4696 13:18:55.857173 DQ Delay:
4697 13:18:55.860186 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4698 13:18:55.863883 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4699 13:18:55.866947 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4700 13:18:55.870641 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4701 13:18:55.870720
4702 13:18:55.870781
4703 13:18:55.870836 ==
4704 13:18:55.873523 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 13:18:55.876897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 13:18:55.880534 ==
4707 13:18:55.880613
4708 13:18:55.880673
4709 13:18:55.880729 TX Vref Scan disable
4710 13:18:55.883556 == TX Byte 0 ==
4711 13:18:55.887306 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4712 13:18:55.890414 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4713 13:18:55.893477 == TX Byte 1 ==
4714 13:18:55.897112 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4715 13:18:55.900733 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4716 13:18:55.903654 ==
4717 13:18:55.903757 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 13:18:55.910414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 13:18:55.910495 ==
4720 13:18:55.910555
4721 13:18:55.910611
4722 13:18:55.913706 TX Vref Scan disable
4723 13:18:55.913784 == TX Byte 0 ==
4724 13:18:55.920259 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4725 13:18:55.923624 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4726 13:18:55.923706 == TX Byte 1 ==
4727 13:18:55.930456 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4728 13:18:55.933536 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4729 13:18:55.933620
4730 13:18:55.933681 [DATLAT]
4731 13:18:55.936813 Freq=600, CH1 RK1
4732 13:18:55.936892
4733 13:18:55.936952 DATLAT Default: 0x9
4734 13:18:55.940505 0, 0xFFFF, sum = 0
4735 13:18:55.940585 1, 0xFFFF, sum = 0
4736 13:18:55.943488 2, 0xFFFF, sum = 0
4737 13:18:55.943568 3, 0xFFFF, sum = 0
4738 13:18:55.946918 4, 0xFFFF, sum = 0
4739 13:18:55.946998 5, 0xFFFF, sum = 0
4740 13:18:55.950555 6, 0xFFFF, sum = 0
4741 13:18:55.953637 7, 0xFFFF, sum = 0
4742 13:18:55.953718 8, 0x0, sum = 1
4743 13:18:55.953779 9, 0x0, sum = 2
4744 13:18:55.956704 10, 0x0, sum = 3
4745 13:18:55.956783 11, 0x0, sum = 4
4746 13:18:55.960259 best_step = 9
4747 13:18:55.960338
4748 13:18:55.960398 ==
4749 13:18:55.963540 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 13:18:55.966831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 13:18:55.966911 ==
4752 13:18:55.970645 RX Vref Scan: 0
4753 13:18:55.970724
4754 13:18:55.970784 RX Vref 0 -> 0, step: 1
4755 13:18:55.970841
4756 13:18:55.973759 RX Delay -179 -> 252, step: 8
4757 13:18:55.980545 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4758 13:18:55.984001 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4759 13:18:55.987263 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4760 13:18:55.990378 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4761 13:18:55.997437 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4762 13:18:56.000460 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4763 13:18:56.004030 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4764 13:18:56.007048 iDelay=205, Bit 7, Center 32 (-115 ~ 180) 296
4765 13:18:56.010750 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4766 13:18:56.017212 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4767 13:18:56.020604 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4768 13:18:56.024235 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4769 13:18:56.027512 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4770 13:18:56.034292 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4771 13:18:56.037281 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4772 13:18:56.040598 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4773 13:18:56.040692 ==
4774 13:18:56.043967 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 13:18:56.047554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 13:18:56.047649 ==
4777 13:18:56.050572 DQS Delay:
4778 13:18:56.050665 DQS0 = 0, DQS1 = 0
4779 13:18:56.054029 DQM Delay:
4780 13:18:56.054138 DQM0 = 37, DQM1 = 32
4781 13:18:56.054230 DQ Delay:
4782 13:18:56.057457 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4783 13:18:56.061008 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4784 13:18:56.064025 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4785 13:18:56.067437 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4786 13:18:56.067533
4787 13:18:56.067611
4788 13:18:56.077217 [DQSOSCAuto] RK1, (LSB)MR18= 0x3643, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
4789 13:18:56.080968 CH1 RK1: MR19=808, MR18=3643
4790 13:18:56.087126 CH1_RK1: MR19=0x808, MR18=0x3643, DQSOSC=397, MR23=63, INC=166, DEC=110
4791 13:18:56.087209 [RxdqsGatingPostProcess] freq 600
4792 13:18:56.094041 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4793 13:18:56.097288 Pre-setting of DQS Precalculation
4794 13:18:56.100582 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4795 13:18:56.110502 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4796 13:18:56.117170 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4797 13:18:56.117283
4798 13:18:56.117370
4799 13:18:56.120854 [Calibration Summary] 1200 Mbps
4800 13:18:56.120932 CH 0, Rank 0
4801 13:18:56.123838 SW Impedance : PASS
4802 13:18:56.123930 DUTY Scan : NO K
4803 13:18:56.126911 ZQ Calibration : PASS
4804 13:18:56.130503 Jitter Meter : NO K
4805 13:18:56.130604 CBT Training : PASS
4806 13:18:56.133864 Write leveling : PASS
4807 13:18:56.137072 RX DQS gating : PASS
4808 13:18:56.137185 RX DQ/DQS(RDDQC) : PASS
4809 13:18:56.140440 TX DQ/DQS : PASS
4810 13:18:56.143994 RX DATLAT : PASS
4811 13:18:56.144073 RX DQ/DQS(Engine): PASS
4812 13:18:56.147168 TX OE : NO K
4813 13:18:56.147281 All Pass.
4814 13:18:56.147340
4815 13:18:56.150446 CH 0, Rank 1
4816 13:18:56.150538 SW Impedance : PASS
4817 13:18:56.153892 DUTY Scan : NO K
4818 13:18:56.153969 ZQ Calibration : PASS
4819 13:18:56.157282 Jitter Meter : NO K
4820 13:18:56.160397 CBT Training : PASS
4821 13:18:56.160475 Write leveling : PASS
4822 13:18:56.163983 RX DQS gating : PASS
4823 13:18:56.166925 RX DQ/DQS(RDDQC) : PASS
4824 13:18:56.167055 TX DQ/DQS : PASS
4825 13:18:56.170655 RX DATLAT : PASS
4826 13:18:56.174182 RX DQ/DQS(Engine): PASS
4827 13:18:56.174285 TX OE : NO K
4828 13:18:56.177249 All Pass.
4829 13:18:56.177381
4830 13:18:56.177482 CH 1, Rank 0
4831 13:18:56.180982 SW Impedance : PASS
4832 13:18:56.181070 DUTY Scan : NO K
4833 13:18:56.183931 ZQ Calibration : PASS
4834 13:18:56.187540 Jitter Meter : NO K
4835 13:18:56.187616 CBT Training : PASS
4836 13:18:56.190544 Write leveling : PASS
4837 13:18:56.190619 RX DQS gating : PASS
4838 13:18:56.194141 RX DQ/DQS(RDDQC) : PASS
4839 13:18:56.197097 TX DQ/DQS : PASS
4840 13:18:56.197194 RX DATLAT : PASS
4841 13:18:56.200743 RX DQ/DQS(Engine): PASS
4842 13:18:56.204282 TX OE : NO K
4843 13:18:56.204360 All Pass.
4844 13:18:56.204418
4845 13:18:56.204472 CH 1, Rank 1
4846 13:18:56.207587 SW Impedance : PASS
4847 13:18:56.210839 DUTY Scan : NO K
4848 13:18:56.210916 ZQ Calibration : PASS
4849 13:18:56.214460 Jitter Meter : NO K
4850 13:18:56.217351 CBT Training : PASS
4851 13:18:56.217458 Write leveling : PASS
4852 13:18:56.221078 RX DQS gating : PASS
4853 13:18:56.224083 RX DQ/DQS(RDDQC) : PASS
4854 13:18:56.224159 TX DQ/DQS : PASS
4855 13:18:56.227468 RX DATLAT : PASS
4856 13:18:56.227548 RX DQ/DQS(Engine): PASS
4857 13:18:56.231052 TX OE : NO K
4858 13:18:56.231131 All Pass.
4859 13:18:56.231192
4860 13:18:56.234146 DramC Write-DBI off
4861 13:18:56.237299 PER_BANK_REFRESH: Hybrid Mode
4862 13:18:56.237401 TX_TRACKING: ON
4863 13:18:56.247550 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4864 13:18:56.251150 [FAST_K] Save calibration result to emmc
4865 13:18:56.254183 dramc_set_vcore_voltage set vcore to 662500
4866 13:18:56.257606 Read voltage for 933, 3
4867 13:18:56.257685 Vio18 = 0
4868 13:18:56.257746 Vcore = 662500
4869 13:18:56.261186 Vdram = 0
4870 13:18:56.261266 Vddq = 0
4871 13:18:56.261326 Vmddr = 0
4872 13:18:56.267801 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4873 13:18:56.270737 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4874 13:18:56.274352 MEM_TYPE=3, freq_sel=17
4875 13:18:56.277855 sv_algorithm_assistance_LP4_1600
4876 13:18:56.280699 ============ PULL DRAM RESETB DOWN ============
4877 13:18:56.284131 ========== PULL DRAM RESETB DOWN end =========
4878 13:18:56.291158 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4879 13:18:56.294154 ===================================
4880 13:18:56.297815 LPDDR4 DRAM CONFIGURATION
4881 13:18:56.300805 ===================================
4882 13:18:56.300886 EX_ROW_EN[0] = 0x0
4883 13:18:56.304394 EX_ROW_EN[1] = 0x0
4884 13:18:56.304474 LP4Y_EN = 0x0
4885 13:18:56.307240 WORK_FSP = 0x0
4886 13:18:56.307321 WL = 0x3
4887 13:18:56.310999 RL = 0x3
4888 13:18:56.311080 BL = 0x2
4889 13:18:56.313951 RPST = 0x0
4890 13:18:56.314031 RD_PRE = 0x0
4891 13:18:56.317284 WR_PRE = 0x1
4892 13:18:56.317366 WR_PST = 0x0
4893 13:18:56.321207 DBI_WR = 0x0
4894 13:18:56.321290 DBI_RD = 0x0
4895 13:18:56.324273 OTF = 0x1
4896 13:18:56.327789 ===================================
4897 13:18:56.330792 ===================================
4898 13:18:56.330874 ANA top config
4899 13:18:56.334441 ===================================
4900 13:18:56.337495 DLL_ASYNC_EN = 0
4901 13:18:56.340518 ALL_SLAVE_EN = 1
4902 13:18:56.344129 NEW_RANK_MODE = 1
4903 13:18:56.344211 DLL_IDLE_MODE = 1
4904 13:18:56.347773 LP45_APHY_COMB_EN = 1
4905 13:18:56.350821 TX_ODT_DIS = 1
4906 13:18:56.354251 NEW_8X_MODE = 1
4907 13:18:56.357524 ===================================
4908 13:18:56.360684 ===================================
4909 13:18:56.364014 data_rate = 1866
4910 13:18:56.364126 CKR = 1
4911 13:18:56.367680 DQ_P2S_RATIO = 8
4912 13:18:56.370666 ===================================
4913 13:18:56.374265 CA_P2S_RATIO = 8
4914 13:18:56.377629 DQ_CA_OPEN = 0
4915 13:18:56.380948 DQ_SEMI_OPEN = 0
4916 13:18:56.381051 CA_SEMI_OPEN = 0
4917 13:18:56.384050 CA_FULL_RATE = 0
4918 13:18:56.387699 DQ_CKDIV4_EN = 1
4919 13:18:56.391029 CA_CKDIV4_EN = 1
4920 13:18:56.394255 CA_PREDIV_EN = 0
4921 13:18:56.397466 PH8_DLY = 0
4922 13:18:56.397545 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4923 13:18:56.400976 DQ_AAMCK_DIV = 4
4924 13:18:56.404226 CA_AAMCK_DIV = 4
4925 13:18:56.407363 CA_ADMCK_DIV = 4
4926 13:18:56.410706 DQ_TRACK_CA_EN = 0
4927 13:18:56.414296 CA_PICK = 933
4928 13:18:56.414374 CA_MCKIO = 933
4929 13:18:56.417919 MCKIO_SEMI = 0
4930 13:18:56.420991 PLL_FREQ = 3732
4931 13:18:56.424378 DQ_UI_PI_RATIO = 32
4932 13:18:56.427675 CA_UI_PI_RATIO = 0
4933 13:18:56.431082 ===================================
4934 13:18:56.434495 ===================================
4935 13:18:56.438002 memory_type:LPDDR4
4936 13:18:56.438078 GP_NUM : 10
4937 13:18:56.441038 SRAM_EN : 1
4938 13:18:56.441160 MD32_EN : 0
4939 13:18:56.444768 ===================================
4940 13:18:56.447759 [ANA_INIT] >>>>>>>>>>>>>>
4941 13:18:56.451441 <<<<<< [CONFIGURE PHASE]: ANA_TX
4942 13:18:56.454487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4943 13:18:56.457601 ===================================
4944 13:18:56.461191 data_rate = 1866,PCW = 0X8f00
4945 13:18:56.464582 ===================================
4946 13:18:56.467971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4947 13:18:56.471037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 13:18:56.477933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 13:18:56.484538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4950 13:18:56.487566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4951 13:18:56.491281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4952 13:18:56.491359 [ANA_INIT] flow start
4953 13:18:56.494301 [ANA_INIT] PLL >>>>>>>>
4954 13:18:56.497906 [ANA_INIT] PLL <<<<<<<<
4955 13:18:56.497983 [ANA_INIT] MIDPI >>>>>>>>
4956 13:18:56.501193 [ANA_INIT] MIDPI <<<<<<<<
4957 13:18:56.504504 [ANA_INIT] DLL >>>>>>>>
4958 13:18:56.504582 [ANA_INIT] flow end
4959 13:18:56.507454 ============ LP4 DIFF to SE enter ============
4960 13:18:56.514263 ============ LP4 DIFF to SE exit ============
4961 13:18:56.514375 [ANA_INIT] <<<<<<<<<<<<<
4962 13:18:56.517539 [Flow] Enable top DCM control >>>>>
4963 13:18:56.520906 [Flow] Enable top DCM control <<<<<
4964 13:18:56.524628 Enable DLL master slave shuffle
4965 13:18:56.531179 ==============================================================
4966 13:18:56.531266 Gating Mode config
4967 13:18:56.537478 ==============================================================
4968 13:18:56.541148 Config description:
4969 13:18:56.551428 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4970 13:18:56.557566 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4971 13:18:56.561099 SELPH_MODE 0: By rank 1: By Phase
4972 13:18:56.567797 ==============================================================
4973 13:18:56.571362 GAT_TRACK_EN = 1
4974 13:18:56.571482 RX_GATING_MODE = 2
4975 13:18:56.574686 RX_GATING_TRACK_MODE = 2
4976 13:18:56.577716 SELPH_MODE = 1
4977 13:18:56.581092 PICG_EARLY_EN = 1
4978 13:18:56.584379 VALID_LAT_VALUE = 1
4979 13:18:56.591409 ==============================================================
4980 13:18:56.594922 Enter into Gating configuration >>>>
4981 13:18:56.597843 Exit from Gating configuration <<<<
4982 13:18:56.601398 Enter into DVFS_PRE_config >>>>>
4983 13:18:56.611185 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4984 13:18:56.614944 Exit from DVFS_PRE_config <<<<<
4985 13:18:56.618041 Enter into PICG configuration >>>>
4986 13:18:56.621615 Exit from PICG configuration <<<<
4987 13:18:56.624389 [RX_INPUT] configuration >>>>>
4988 13:18:56.624466 [RX_INPUT] configuration <<<<<
4989 13:18:56.631187 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4990 13:18:56.637810 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4991 13:18:56.641484 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 13:18:56.647857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 13:18:56.654748 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 13:18:56.661405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 13:18:56.664984 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4996 13:18:56.667972 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4997 13:18:56.674659 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4998 13:18:56.678242 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4999 13:18:56.681194 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5000 13:18:56.684793 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 13:18:56.688170 ===================================
5002 13:18:56.691339 LPDDR4 DRAM CONFIGURATION
5003 13:18:56.694575 ===================================
5004 13:18:56.698540 EX_ROW_EN[0] = 0x0
5005 13:18:56.698619 EX_ROW_EN[1] = 0x0
5006 13:18:56.701605 LP4Y_EN = 0x0
5007 13:18:56.701699 WORK_FSP = 0x0
5008 13:18:56.704663 WL = 0x3
5009 13:18:56.704741 RL = 0x3
5010 13:18:56.708198 BL = 0x2
5011 13:18:56.708274 RPST = 0x0
5012 13:18:56.711279 RD_PRE = 0x0
5013 13:18:56.711356 WR_PRE = 0x1
5014 13:18:56.715027 WR_PST = 0x0
5015 13:18:56.715105 DBI_WR = 0x0
5016 13:18:56.718092 DBI_RD = 0x0
5017 13:18:56.718170 OTF = 0x1
5018 13:18:56.721750 ===================================
5019 13:18:56.728440 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5020 13:18:56.731530 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5021 13:18:56.735455 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 13:18:56.738263 ===================================
5023 13:18:56.741864 LPDDR4 DRAM CONFIGURATION
5024 13:18:56.744643 ===================================
5025 13:18:56.748421 EX_ROW_EN[0] = 0x10
5026 13:18:56.748500 EX_ROW_EN[1] = 0x0
5027 13:18:56.751832 LP4Y_EN = 0x0
5028 13:18:56.751911 WORK_FSP = 0x0
5029 13:18:56.754716 WL = 0x3
5030 13:18:56.754795 RL = 0x3
5031 13:18:56.758040 BL = 0x2
5032 13:18:56.758119 RPST = 0x0
5033 13:18:56.761400 RD_PRE = 0x0
5034 13:18:56.761481 WR_PRE = 0x1
5035 13:18:56.764693 WR_PST = 0x0
5036 13:18:56.764772 DBI_WR = 0x0
5037 13:18:56.768050 DBI_RD = 0x0
5038 13:18:56.768120 OTF = 0x1
5039 13:18:56.771657 ===================================
5040 13:18:56.777887 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5041 13:18:56.782916 nWR fixed to 30
5042 13:18:56.785939 [ModeRegInit_LP4] CH0 RK0
5043 13:18:56.786024 [ModeRegInit_LP4] CH0 RK1
5044 13:18:56.789373 [ModeRegInit_LP4] CH1 RK0
5045 13:18:56.792527 [ModeRegInit_LP4] CH1 RK1
5046 13:18:56.792606 match AC timing 9
5047 13:18:56.799276 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5048 13:18:56.802599 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5049 13:18:56.805850 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5050 13:18:56.812583 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5051 13:18:56.815594 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5052 13:18:56.815684 ==
5053 13:18:56.819100 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 13:18:56.822277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 13:18:56.822360 ==
5056 13:18:56.828938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 13:18:56.835723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5058 13:18:56.839213 [CA 0] Center 38 (8~69) winsize 62
5059 13:18:56.842143 [CA 1] Center 38 (7~69) winsize 63
5060 13:18:56.845787 [CA 2] Center 35 (5~66) winsize 62
5061 13:18:56.849445 [CA 3] Center 35 (5~65) winsize 61
5062 13:18:56.852377 [CA 4] Center 34 (4~65) winsize 62
5063 13:18:56.855719 [CA 5] Center 34 (4~64) winsize 61
5064 13:18:56.855798
5065 13:18:56.859214 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5066 13:18:56.859295
5067 13:18:56.862827 [CATrainingPosCal] consider 1 rank data
5068 13:18:56.865940 u2DelayCellTimex100 = 270/100 ps
5069 13:18:56.869586 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5070 13:18:56.872720 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5071 13:18:56.876040 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5072 13:18:56.879321 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5073 13:18:56.882682 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5074 13:18:56.885860 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5075 13:18:56.885939
5076 13:18:56.892722 CA PerBit enable=1, Macro0, CA PI delay=34
5077 13:18:56.892808
5078 13:18:56.892870 [CBTSetCACLKResult] CA Dly = 34
5079 13:18:56.896709 CS Dly: 6 (0~37)
5080 13:18:56.896788 ==
5081 13:18:56.899294 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 13:18:56.902434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 13:18:56.902514 ==
5084 13:18:56.909427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 13:18:56.915620 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 13:18:56.918936 [CA 0] Center 38 (7~69) winsize 63
5087 13:18:56.922602 [CA 1] Center 38 (7~69) winsize 63
5088 13:18:56.925660 [CA 2] Center 35 (5~66) winsize 62
5089 13:18:56.929201 [CA 3] Center 34 (4~65) winsize 62
5090 13:18:56.932798 [CA 4] Center 33 (3~64) winsize 62
5091 13:18:56.935900 [CA 5] Center 33 (3~64) winsize 62
5092 13:18:56.935979
5093 13:18:56.938985 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 13:18:56.939064
5095 13:18:56.942635 [CATrainingPosCal] consider 2 rank data
5096 13:18:56.945698 u2DelayCellTimex100 = 270/100 ps
5097 13:18:56.949296 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5098 13:18:56.952483 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5099 13:18:56.955977 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5100 13:18:56.959500 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5101 13:18:56.962909 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5102 13:18:56.965949 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5103 13:18:56.966029
5104 13:18:56.969399 CA PerBit enable=1, Macro0, CA PI delay=34
5105 13:18:56.973058
5106 13:18:56.973163 [CBTSetCACLKResult] CA Dly = 34
5107 13:18:56.976056 CS Dly: 7 (0~39)
5108 13:18:56.976149
5109 13:18:56.979613 ----->DramcWriteLeveling(PI) begin...
5110 13:18:56.979684 ==
5111 13:18:56.982470 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 13:18:56.986191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 13:18:56.986292 ==
5114 13:18:56.989360 Write leveling (Byte 0): 30 => 30
5115 13:18:56.992529 Write leveling (Byte 1): 28 => 28
5116 13:18:56.996166 DramcWriteLeveling(PI) end<-----
5117 13:18:56.996247
5118 13:18:56.996307 ==
5119 13:18:56.999237 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 13:18:57.003002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 13:18:57.003081 ==
5122 13:18:57.005961 [Gating] SW mode calibration
5123 13:18:57.012523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5124 13:18:57.019088 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5125 13:18:57.022880 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (1 1) (0 0)
5126 13:18:57.029294 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5127 13:18:57.032600 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 13:18:57.036179 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 13:18:57.042612 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 13:18:57.046147 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 13:18:57.049228 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 13:18:57.052894 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5133 13:18:57.059590 0 15 0 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (0 0)
5134 13:18:57.062575 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 13:18:57.066130 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 13:18:57.072527 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 13:18:57.076143 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 13:18:57.079229 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 13:18:57.086178 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 13:18:57.089239 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5141 13:18:57.092825 1 0 0 | B1->B0 | 2c2c 3939 | 0 1 | (0 0) (0 0)
5142 13:18:57.099225 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 13:18:57.102883 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 13:18:57.106444 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 13:18:57.112657 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 13:18:57.116238 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 13:18:57.119819 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 13:18:57.126313 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5149 13:18:57.129831 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 13:18:57.132954 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5151 13:18:57.136616 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 13:18:57.143057 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:18:57.146302 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:18:57.149735 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:18:57.156539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:18:57.159512 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:18:57.162794 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:18:57.169735 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:18:57.172671 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:18:57.176329 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:18:57.182894 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 13:18:57.186620 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 13:18:57.189569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 13:18:57.196229 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5165 13:18:57.199401 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5166 13:18:57.203028 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 13:18:57.206349 Total UI for P1: 0, mck2ui 16
5168 13:18:57.209498 best dqsien dly found for B0: ( 1, 2, 30)
5169 13:18:57.213088 Total UI for P1: 0, mck2ui 16
5170 13:18:57.216236 best dqsien dly found for B1: ( 1, 2, 30)
5171 13:18:57.219781 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5172 13:18:57.222826 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5173 13:18:57.222905
5174 13:18:57.226620 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5175 13:18:57.229712 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5176 13:18:57.233080 [Gating] SW calibration Done
5177 13:18:57.233166 ==
5178 13:18:57.236214 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 13:18:57.242879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 13:18:57.242966 ==
5181 13:18:57.243029 RX Vref Scan: 0
5182 13:18:57.243086
5183 13:18:57.246549 RX Vref 0 -> 0, step: 1
5184 13:18:57.246616
5185 13:18:57.249620 RX Delay -80 -> 252, step: 8
5186 13:18:57.253314 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5187 13:18:57.256258 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5188 13:18:57.259628 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5189 13:18:57.263084 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5190 13:18:57.266519 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5191 13:18:57.273066 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5192 13:18:57.276478 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5193 13:18:57.279620 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5194 13:18:57.283043 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5195 13:18:57.286633 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5196 13:18:57.289849 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5197 13:18:57.296292 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5198 13:18:57.299537 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5199 13:18:57.303203 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5200 13:18:57.306308 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5201 13:18:57.309834 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5202 13:18:57.309910 ==
5203 13:18:57.312809 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 13:18:57.319449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 13:18:57.319535 ==
5206 13:18:57.319597 DQS Delay:
5207 13:18:57.323070 DQS0 = 0, DQS1 = 0
5208 13:18:57.323149 DQM Delay:
5209 13:18:57.323211 DQM0 = 97, DQM1 = 86
5210 13:18:57.326729 DQ Delay:
5211 13:18:57.329704 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5212 13:18:57.332784 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5213 13:18:57.336404 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5214 13:18:57.339516 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5215 13:18:57.339593
5216 13:18:57.339652
5217 13:18:57.339730 ==
5218 13:18:57.343155 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 13:18:57.346770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 13:18:57.346848 ==
5221 13:18:57.346908
5222 13:18:57.346962
5223 13:18:57.349773 TX Vref Scan disable
5224 13:18:57.349850 == TX Byte 0 ==
5225 13:18:57.356480 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5226 13:18:57.359987 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5227 13:18:57.363386 == TX Byte 1 ==
5228 13:18:57.366607 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5229 13:18:57.369619 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5230 13:18:57.369697 ==
5231 13:18:57.373176 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 13:18:57.376218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 13:18:57.376296 ==
5234 13:18:57.376355
5235 13:18:57.380006
5236 13:18:57.380082 TX Vref Scan disable
5237 13:18:57.382953 == TX Byte 0 ==
5238 13:18:57.386484 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5239 13:18:57.389766 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5240 13:18:57.392988 == TX Byte 1 ==
5241 13:18:57.396177 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5242 13:18:57.399740 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5243 13:18:57.403140
5244 13:18:57.403265 [DATLAT]
5245 13:18:57.403325 Freq=933, CH0 RK0
5246 13:18:57.403380
5247 13:18:57.406630 DATLAT Default: 0xd
5248 13:18:57.406707 0, 0xFFFF, sum = 0
5249 13:18:57.409767 1, 0xFFFF, sum = 0
5250 13:18:57.409888 2, 0xFFFF, sum = 0
5251 13:18:57.412900 3, 0xFFFF, sum = 0
5252 13:18:57.412993 4, 0xFFFF, sum = 0
5253 13:18:57.416326 5, 0xFFFF, sum = 0
5254 13:18:57.416418 6, 0xFFFF, sum = 0
5255 13:18:57.419789 7, 0xFFFF, sum = 0
5256 13:18:57.422883 8, 0xFFFF, sum = 0
5257 13:18:57.422968 9, 0xFFFF, sum = 0
5258 13:18:57.426552 10, 0x0, sum = 1
5259 13:18:57.426626 11, 0x0, sum = 2
5260 13:18:57.426684 12, 0x0, sum = 3
5261 13:18:57.429924 13, 0x0, sum = 4
5262 13:18:57.430000 best_step = 11
5263 13:18:57.430058
5264 13:18:57.430112 ==
5265 13:18:57.433039 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 13:18:57.439749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 13:18:57.439828 ==
5268 13:18:57.439896 RX Vref Scan: 1
5269 13:18:57.439962
5270 13:18:57.443330 RX Vref 0 -> 0, step: 1
5271 13:18:57.443408
5272 13:18:57.446222 RX Delay -61 -> 252, step: 4
5273 13:18:57.446300
5274 13:18:57.449822 Set Vref, RX VrefLevel [Byte0]: 53
5275 13:18:57.452847 [Byte1]: 54
5276 13:18:57.452952
5277 13:18:57.456560 Final RX Vref Byte 0 = 53 to rank0
5278 13:18:57.459665 Final RX Vref Byte 1 = 54 to rank0
5279 13:18:57.463389 Final RX Vref Byte 0 = 53 to rank1
5280 13:18:57.466381 Final RX Vref Byte 1 = 54 to rank1==
5281 13:18:57.469842 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 13:18:57.473049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 13:18:57.473136 ==
5284 13:18:57.476189 DQS Delay:
5285 13:18:57.476268 DQS0 = 0, DQS1 = 0
5286 13:18:57.479901 DQM Delay:
5287 13:18:57.479979 DQM0 = 96, DQM1 = 89
5288 13:18:57.480039 DQ Delay:
5289 13:18:57.482977 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5290 13:18:57.486041 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5291 13:18:57.489696 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =82
5292 13:18:57.492758 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =98
5293 13:18:57.492837
5294 13:18:57.492897
5295 13:18:57.502982 [DQSOSCAuto] RK0, (LSB)MR18= 0x1904, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5296 13:18:57.506305 CH0 RK0: MR19=505, MR18=1904
5297 13:18:57.509431 CH0_RK0: MR19=0x505, MR18=0x1904, DQSOSC=413, MR23=63, INC=63, DEC=42
5298 13:18:57.512671
5299 13:18:57.516436 ----->DramcWriteLeveling(PI) begin...
5300 13:18:57.516515 ==
5301 13:18:57.519493 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 13:18:57.523150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 13:18:57.523231 ==
5304 13:18:57.526153 Write leveling (Byte 0): 33 => 33
5305 13:18:57.530012 Write leveling (Byte 1): 32 => 32
5306 13:18:57.533208 DramcWriteLeveling(PI) end<-----
5307 13:18:57.533289
5308 13:18:57.533349 ==
5309 13:18:57.536204 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 13:18:57.539745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 13:18:57.539825 ==
5312 13:18:57.542695 [Gating] SW mode calibration
5313 13:18:57.549522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5314 13:18:57.556217 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5315 13:18:57.559355 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
5316 13:18:57.562994 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5317 13:18:57.569733 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 13:18:57.572738 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 13:18:57.576488 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 13:18:57.579293 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 13:18:57.586087 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5322 13:18:57.589897 0 14 28 | B1->B0 | 3333 2929 | 1 0 | (1 1) (0 0)
5323 13:18:57.592778 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5324 13:18:57.599567 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 13:18:57.603127 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 13:18:57.606328 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 13:18:57.612765 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 13:18:57.616652 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 13:18:57.619623 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 13:18:57.626060 0 15 28 | B1->B0 | 2b2b 3d3d | 0 0 | (0 0) (1 1)
5331 13:18:57.629594 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5332 13:18:57.633155 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 13:18:57.639615 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 13:18:57.642512 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 13:18:57.646306 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 13:18:57.652443 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 13:18:57.655748 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 13:18:57.659148 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5339 13:18:57.666038 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5340 13:18:57.669037 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5341 13:18:57.672790 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 13:18:57.679481 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:18:57.682431 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:18:57.686046 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:18:57.692562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:18:57.695681 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 13:18:57.699111 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 13:18:57.702871 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 13:18:57.709399 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 13:18:57.712526 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 13:18:57.716181 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 13:18:57.722507 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 13:18:57.725822 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5354 13:18:57.729093 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5355 13:18:57.736060 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 13:18:57.739083 Total UI for P1: 0, mck2ui 16
5357 13:18:57.742777 best dqsien dly found for B0: ( 1, 2, 26)
5358 13:18:57.742876 Total UI for P1: 0, mck2ui 16
5359 13:18:57.749004 best dqsien dly found for B1: ( 1, 2, 30)
5360 13:18:57.752663 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5361 13:18:57.755834 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5362 13:18:57.755929
5363 13:18:57.759424 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5364 13:18:57.762776 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5365 13:18:57.765699 [Gating] SW calibration Done
5366 13:18:57.765799 ==
5367 13:18:57.769416 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 13:18:57.772429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 13:18:57.772523 ==
5370 13:18:57.776208 RX Vref Scan: 0
5371 13:18:57.776306
5372 13:18:57.776371 RX Vref 0 -> 0, step: 1
5373 13:18:57.776428
5374 13:18:57.779805 RX Delay -80 -> 252, step: 8
5375 13:18:57.782840 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5376 13:18:57.786375 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5377 13:18:57.792596 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5378 13:18:57.796120 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5379 13:18:57.799693 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5380 13:18:57.802535 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5381 13:18:57.806026 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5382 13:18:57.809273 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5383 13:18:57.816034 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5384 13:18:57.819652 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5385 13:18:57.822691 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5386 13:18:57.826211 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5387 13:18:57.829323 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5388 13:18:57.832705 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5389 13:18:57.839340 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5390 13:18:57.842753 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5391 13:18:57.842836 ==
5392 13:18:57.846365 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 13:18:57.849429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 13:18:57.849509 ==
5395 13:18:57.849569 DQS Delay:
5396 13:18:57.852615 DQS0 = 0, DQS1 = 0
5397 13:18:57.852694 DQM Delay:
5398 13:18:57.856220 DQM0 = 96, DQM1 = 88
5399 13:18:57.856299 DQ Delay:
5400 13:18:57.859959 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5401 13:18:57.862928 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5402 13:18:57.865961 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5403 13:18:57.869613 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5404 13:18:57.869708
5405 13:18:57.869770
5406 13:18:57.869825 ==
5407 13:18:57.872764 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 13:18:57.876515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 13:18:57.879478 ==
5410 13:18:57.879556
5411 13:18:57.879615
5412 13:18:57.879672 TX Vref Scan disable
5413 13:18:57.882892 == TX Byte 0 ==
5414 13:18:57.886264 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5415 13:18:57.889726 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5416 13:18:57.892962 == TX Byte 1 ==
5417 13:18:57.896091 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5418 13:18:57.899714 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5419 13:18:57.899795 ==
5420 13:18:57.902845 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 13:18:57.909533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 13:18:57.909618 ==
5423 13:18:57.909680
5424 13:18:57.909741
5425 13:18:57.909798 TX Vref Scan disable
5426 13:18:57.913895 == TX Byte 0 ==
5427 13:18:57.917490 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5428 13:18:57.921161 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5429 13:18:57.924200 == TX Byte 1 ==
5430 13:18:57.927350 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5431 13:18:57.930899 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5432 13:18:57.930980
5433 13:18:57.934408 [DATLAT]
5434 13:18:57.934487 Freq=933, CH0 RK1
5435 13:18:57.934548
5436 13:18:57.937360 DATLAT Default: 0xb
5437 13:18:57.937438 0, 0xFFFF, sum = 0
5438 13:18:57.940835 1, 0xFFFF, sum = 0
5439 13:18:57.940914 2, 0xFFFF, sum = 0
5440 13:18:57.944102 3, 0xFFFF, sum = 0
5441 13:18:57.944182 4, 0xFFFF, sum = 0
5442 13:18:57.947378 5, 0xFFFF, sum = 0
5443 13:18:57.947457 6, 0xFFFF, sum = 0
5444 13:18:57.951038 7, 0xFFFF, sum = 0
5445 13:18:57.951118 8, 0xFFFF, sum = 0
5446 13:18:57.954104 9, 0xFFFF, sum = 0
5447 13:18:57.954174 10, 0x0, sum = 1
5448 13:18:57.957769 11, 0x0, sum = 2
5449 13:18:57.957849 12, 0x0, sum = 3
5450 13:18:57.960729 13, 0x0, sum = 4
5451 13:18:57.960809 best_step = 11
5452 13:18:57.960869
5453 13:18:57.960924 ==
5454 13:18:57.964408 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 13:18:57.971114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 13:18:57.971201 ==
5457 13:18:57.971263 RX Vref Scan: 0
5458 13:18:57.971318
5459 13:18:57.974205 RX Vref 0 -> 0, step: 1
5460 13:18:57.974284
5461 13:18:57.977317 RX Delay -53 -> 252, step: 4
5462 13:18:57.980918 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5463 13:18:57.983963 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5464 13:18:57.990861 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5465 13:18:57.993883 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5466 13:18:57.997517 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5467 13:18:58.000974 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5468 13:18:58.004273 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5469 13:18:58.007484 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5470 13:18:58.014105 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5471 13:18:58.017461 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5472 13:18:58.020495 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5473 13:18:58.024396 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5474 13:18:58.027224 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5475 13:18:58.030698 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5476 13:18:58.037111 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5477 13:18:58.040803 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5478 13:18:58.040890 ==
5479 13:18:58.044321 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 13:18:58.047729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 13:18:58.047833 ==
5482 13:18:58.047920 DQS Delay:
5483 13:18:58.050529 DQS0 = 0, DQS1 = 0
5484 13:18:58.050608 DQM Delay:
5485 13:18:58.053880 DQM0 = 95, DQM1 = 89
5486 13:18:58.053958 DQ Delay:
5487 13:18:58.057543 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5488 13:18:58.060802 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5489 13:18:58.064320 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =80
5490 13:18:58.067215 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5491 13:18:58.067295
5492 13:18:58.067355
5493 13:18:58.077575 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
5494 13:18:58.077666 CH0 RK1: MR19=505, MR18=1C09
5495 13:18:58.083805 CH0_RK1: MR19=0x505, MR18=0x1C09, DQSOSC=412, MR23=63, INC=63, DEC=42
5496 13:18:58.087470 [RxdqsGatingPostProcess] freq 933
5497 13:18:58.094336 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5498 13:18:58.097065 best DQS0 dly(2T, 0.5T) = (0, 10)
5499 13:18:58.100663 best DQS1 dly(2T, 0.5T) = (0, 10)
5500 13:18:58.104334 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5501 13:18:58.107449 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5502 13:18:58.107546 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 13:18:58.111046 best DQS1 dly(2T, 0.5T) = (0, 10)
5504 13:18:58.114128 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 13:18:58.117534 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5506 13:18:58.120940 Pre-setting of DQS Precalculation
5507 13:18:58.127536 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5508 13:18:58.127641 ==
5509 13:18:58.130917 Dram Type= 6, Freq= 0, CH_1, rank 0
5510 13:18:58.134485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 13:18:58.134560 ==
5512 13:18:58.140894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5513 13:18:58.144323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5514 13:18:58.148480 [CA 0] Center 36 (6~67) winsize 62
5515 13:18:58.151698 [CA 1] Center 36 (6~67) winsize 62
5516 13:18:58.155270 [CA 2] Center 34 (4~64) winsize 61
5517 13:18:58.158330 [CA 3] Center 33 (3~64) winsize 62
5518 13:18:58.161600 [CA 4] Center 33 (3~64) winsize 62
5519 13:18:58.165318 [CA 5] Center 33 (3~63) winsize 61
5520 13:18:58.165399
5521 13:18:58.168550 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5522 13:18:58.168632
5523 13:18:58.172048 [CATrainingPosCal] consider 1 rank data
5524 13:18:58.175092 u2DelayCellTimex100 = 270/100 ps
5525 13:18:58.178692 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5526 13:18:58.181843 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5527 13:18:58.188457 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5528 13:18:58.191427 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5529 13:18:58.195182 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5530 13:18:58.198664 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5531 13:18:58.198731
5532 13:18:58.201584 CA PerBit enable=1, Macro0, CA PI delay=33
5533 13:18:58.201649
5534 13:18:58.205183 [CBTSetCACLKResult] CA Dly = 33
5535 13:18:58.205251 CS Dly: 4 (0~35)
5536 13:18:58.208138 ==
5537 13:18:58.208204 Dram Type= 6, Freq= 0, CH_1, rank 1
5538 13:18:58.214940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 13:18:58.215020 ==
5540 13:18:58.218579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 13:18:58.225152 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5542 13:18:58.228182 [CA 0] Center 36 (6~67) winsize 62
5543 13:18:58.231779 [CA 1] Center 37 (7~67) winsize 61
5544 13:18:58.234856 [CA 2] Center 33 (3~64) winsize 62
5545 13:18:58.238484 [CA 3] Center 33 (3~64) winsize 62
5546 13:18:58.242014 [CA 4] Center 34 (4~65) winsize 62
5547 13:18:58.245248 [CA 5] Center 32 (2~63) winsize 62
5548 13:18:58.245328
5549 13:18:58.248186 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5550 13:18:58.248282
5551 13:18:58.251581 [CATrainingPosCal] consider 2 rank data
5552 13:18:58.254804 u2DelayCellTimex100 = 270/100 ps
5553 13:18:58.258661 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 13:18:58.261693 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5555 13:18:58.268361 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5556 13:18:58.271596 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 13:18:58.274938 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5558 13:18:58.278197 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5559 13:18:58.278287
5560 13:18:58.281530 CA PerBit enable=1, Macro0, CA PI delay=33
5561 13:18:58.281599
5562 13:18:58.285026 [CBTSetCACLKResult] CA Dly = 33
5563 13:18:58.285098 CS Dly: 5 (0~38)
5564 13:18:58.285185
5565 13:18:58.288617 ----->DramcWriteLeveling(PI) begin...
5566 13:18:58.291673 ==
5567 13:18:58.294712 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 13:18:58.298484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 13:18:58.298563 ==
5570 13:18:58.301363 Write leveling (Byte 0): 26 => 26
5571 13:18:58.305043 Write leveling (Byte 1): 30 => 30
5572 13:18:58.308480 DramcWriteLeveling(PI) end<-----
5573 13:18:58.308558
5574 13:18:58.308618 ==
5575 13:18:58.311515 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 13:18:58.315187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 13:18:58.315265 ==
5578 13:18:58.318212 [Gating] SW mode calibration
5579 13:18:58.324838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5580 13:18:58.327921 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5581 13:18:58.334657 0 14 0 | B1->B0 | 3030 3131 | 1 0 | (1 1) (0 0)
5582 13:18:58.338250 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 13:18:58.341298 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5584 13:18:58.348490 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 13:18:58.351349 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 13:18:58.354973 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 13:18:58.361775 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 13:18:58.364682 0 14 28 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
5589 13:18:58.368060 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5590 13:18:58.374779 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 13:18:58.378037 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 13:18:58.381198 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 13:18:58.388325 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 13:18:58.391511 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 13:18:58.394845 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 13:18:58.401522 0 15 28 | B1->B0 | 2d2d 2d2d | 0 0 | (0 0) (0 0)
5597 13:18:58.404794 1 0 0 | B1->B0 | 4444 4444 | 0 0 | (0 0) (0 0)
5598 13:18:58.408385 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 13:18:58.415021 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 13:18:58.418069 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 13:18:58.421747 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 13:18:58.424837 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 13:18:58.431656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5604 13:18:58.434700 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5605 13:18:58.438361 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5606 13:18:58.445038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:18:58.448141 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:18:58.451848 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:18:58.458473 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:18:58.461558 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:18:58.465249 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:18:58.471638 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 13:18:58.474726 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 13:18:58.478137 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 13:18:58.485421 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 13:18:58.488048 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 13:18:58.491563 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 13:18:58.498251 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 13:18:58.501677 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5620 13:18:58.505151 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5621 13:18:58.508083 Total UI for P1: 0, mck2ui 16
5622 13:18:58.511679 best dqsien dly found for B1: ( 1, 2, 26)
5623 13:18:58.514761 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:18:58.518157 Total UI for P1: 0, mck2ui 16
5625 13:18:58.521700 best dqsien dly found for B0: ( 1, 2, 26)
5626 13:18:58.524862 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5627 13:18:58.531816 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5628 13:18:58.531940
5629 13:18:58.534761 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5630 13:18:58.538543 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5631 13:18:58.541513 [Gating] SW calibration Done
5632 13:18:58.541596 ==
5633 13:18:58.545146 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 13:18:58.548091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 13:18:58.548173 ==
5636 13:18:58.548234 RX Vref Scan: 0
5637 13:18:58.548291
5638 13:18:58.551695 RX Vref 0 -> 0, step: 1
5639 13:18:58.551778
5640 13:18:58.554932 RX Delay -80 -> 252, step: 8
5641 13:18:58.558549 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5642 13:18:58.561456 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5643 13:18:58.568042 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5644 13:18:58.571695 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5645 13:18:58.575129 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5646 13:18:58.578313 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5647 13:18:58.581445 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5648 13:18:58.584854 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5649 13:18:58.588456 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5650 13:18:58.594930 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5651 13:18:58.598352 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5652 13:18:58.602065 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5653 13:18:58.605044 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5654 13:18:58.608562 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5655 13:18:58.615077 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5656 13:18:58.618698 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5657 13:18:58.618780 ==
5658 13:18:58.621850 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 13:18:58.625445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 13:18:58.625526 ==
5661 13:18:58.625605 DQS Delay:
5662 13:18:58.628723 DQS0 = 0, DQS1 = 0
5663 13:18:58.628804 DQM Delay:
5664 13:18:58.632093 DQM0 = 95, DQM1 = 88
5665 13:18:58.632174 DQ Delay:
5666 13:18:58.635150 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5667 13:18:58.638780 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5668 13:18:58.641794 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5669 13:18:58.645012 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5670 13:18:58.645092
5671 13:18:58.645178
5672 13:18:58.645253 ==
5673 13:18:58.648525 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 13:18:58.652098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 13:18:58.652179 ==
5676 13:18:58.655218
5677 13:18:58.655296
5678 13:18:58.655374 TX Vref Scan disable
5679 13:18:58.658944 == TX Byte 0 ==
5680 13:18:58.661817 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5681 13:18:58.665632 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5682 13:18:58.668366 == TX Byte 1 ==
5683 13:18:58.672080 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5684 13:18:58.675084 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5685 13:18:58.675163 ==
5686 13:18:58.678640 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 13:18:58.685390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 13:18:58.685473 ==
5689 13:18:58.685535
5690 13:18:58.685596
5691 13:18:58.685651 TX Vref Scan disable
5692 13:18:58.689774 == TX Byte 0 ==
5693 13:18:58.692532 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5694 13:18:58.699321 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5695 13:18:58.699393 == TX Byte 1 ==
5696 13:18:58.702722 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5697 13:18:58.709575 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5698 13:18:58.709651
5699 13:18:58.709712 [DATLAT]
5700 13:18:58.709768 Freq=933, CH1 RK0
5701 13:18:58.709822
5702 13:18:58.712562 DATLAT Default: 0xd
5703 13:18:58.712651 0, 0xFFFF, sum = 0
5704 13:18:58.715868 1, 0xFFFF, sum = 0
5705 13:18:58.715943 2, 0xFFFF, sum = 0
5706 13:18:58.719474 3, 0xFFFF, sum = 0
5707 13:18:58.719545 4, 0xFFFF, sum = 0
5708 13:18:58.722501 5, 0xFFFF, sum = 0
5709 13:18:58.726163 6, 0xFFFF, sum = 0
5710 13:18:58.726231 7, 0xFFFF, sum = 0
5711 13:18:58.729198 8, 0xFFFF, sum = 0
5712 13:18:58.729282 9, 0xFFFF, sum = 0
5713 13:18:58.732938 10, 0x0, sum = 1
5714 13:18:58.733037 11, 0x0, sum = 2
5715 13:18:58.733099 12, 0x0, sum = 3
5716 13:18:58.735919 13, 0x0, sum = 4
5717 13:18:58.735980 best_step = 11
5718 13:18:58.736031
5719 13:18:58.739538 ==
5720 13:18:58.739605 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 13:18:58.746309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 13:18:58.746384 ==
5723 13:18:58.746442 RX Vref Scan: 1
5724 13:18:58.746499
5725 13:18:58.749497 RX Vref 0 -> 0, step: 1
5726 13:18:58.749566
5727 13:18:58.753012 RX Delay -61 -> 252, step: 4
5728 13:18:58.753083
5729 13:18:58.755861 Set Vref, RX VrefLevel [Byte0]: 61
5730 13:18:58.759213 [Byte1]: 53
5731 13:18:58.759307
5732 13:18:58.762803 Final RX Vref Byte 0 = 61 to rank0
5733 13:18:58.765867 Final RX Vref Byte 1 = 53 to rank0
5734 13:18:58.769542 Final RX Vref Byte 0 = 61 to rank1
5735 13:18:58.772544 Final RX Vref Byte 1 = 53 to rank1==
5736 13:18:58.776026 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 13:18:58.779737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 13:18:58.779812 ==
5739 13:18:58.782631 DQS Delay:
5740 13:18:58.782702 DQS0 = 0, DQS1 = 0
5741 13:18:58.786302 DQM Delay:
5742 13:18:58.786374 DQM0 = 98, DQM1 = 91
5743 13:18:58.786432 DQ Delay:
5744 13:18:58.789419 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =96
5745 13:18:58.792499 DQ4 =96, DQ5 =106, DQ6 =110, DQ7 =96
5746 13:18:58.795915 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5747 13:18:58.799378 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =98
5748 13:18:58.799452
5749 13:18:58.802505
5750 13:18:58.809755 [DQSOSCAuto] RK0, (LSB)MR18= 0x1bf7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5751 13:18:58.812706 CH1 RK0: MR19=504, MR18=1BF7
5752 13:18:58.819402 CH1_RK0: MR19=0x504, MR18=0x1BF7, DQSOSC=413, MR23=63, INC=63, DEC=42
5753 13:18:58.819477
5754 13:18:58.822679 ----->DramcWriteLeveling(PI) begin...
5755 13:18:58.822753 ==
5756 13:18:58.826454 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 13:18:58.829559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 13:18:58.829631 ==
5759 13:18:58.833206 Write leveling (Byte 0): 27 => 27
5760 13:18:58.836208 Write leveling (Byte 1): 28 => 28
5761 13:18:58.839856 DramcWriteLeveling(PI) end<-----
5762 13:18:58.839931
5763 13:18:58.839990 ==
5764 13:18:58.842883 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 13:18:58.846516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 13:18:58.846591 ==
5767 13:18:58.849575 [Gating] SW mode calibration
5768 13:18:58.855926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5769 13:18:58.862711 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5770 13:18:58.865845 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5771 13:18:58.869897 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 13:18:58.876081 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 13:18:58.879419 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 13:18:58.882621 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5775 13:18:58.889381 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 13:18:58.892707 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
5777 13:18:58.896237 0 14 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
5778 13:18:58.899371 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5779 13:18:58.906355 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 13:18:58.909429 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 13:18:58.912621 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 13:18:58.919242 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 13:18:58.923043 0 15 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5784 13:18:58.926392 0 15 24 | B1->B0 | 2a2a 3232 | 0 0 | (0 0) (0 0)
5785 13:18:58.932920 0 15 28 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
5786 13:18:58.936031 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 13:18:58.939732 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 13:18:58.946362 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 13:18:58.949431 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 13:18:58.953020 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 13:18:58.959678 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5792 13:18:58.962861 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5793 13:18:58.966350 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5794 13:18:58.973020 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5795 13:18:58.976045 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:18:58.979705 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 13:18:58.986443 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:18:58.989483 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:18:58.993099 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:18:58.996469 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 13:18:59.002693 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 13:18:59.006072 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 13:18:59.009563 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 13:18:59.016425 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 13:18:59.019545 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 13:18:59.023209 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 13:18:59.029699 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 13:18:59.033071 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5809 13:18:59.036402 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 13:18:59.039610 Total UI for P1: 0, mck2ui 16
5811 13:18:59.042913 best dqsien dly found for B0: ( 1, 2, 24)
5812 13:18:59.046566 Total UI for P1: 0, mck2ui 16
5813 13:18:59.049558 best dqsien dly found for B1: ( 1, 2, 26)
5814 13:18:59.053211 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5815 13:18:59.056126 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5816 13:18:59.056203
5817 13:18:59.059716 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5818 13:18:59.066537 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5819 13:18:59.066618 [Gating] SW calibration Done
5820 13:18:59.066679 ==
5821 13:18:59.069471 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 13:18:59.076362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 13:18:59.076444 ==
5824 13:18:59.076505 RX Vref Scan: 0
5825 13:18:59.076560
5826 13:18:59.079551 RX Vref 0 -> 0, step: 1
5827 13:18:59.079628
5828 13:18:59.083376 RX Delay -80 -> 252, step: 8
5829 13:18:59.086642 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5830 13:18:59.089669 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5831 13:18:59.092828 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5832 13:18:59.096352 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5833 13:18:59.103022 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5834 13:18:59.106103 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5835 13:18:59.109675 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5836 13:18:59.112910 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5837 13:18:59.116513 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5838 13:18:59.119672 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5839 13:18:59.125967 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5840 13:18:59.129500 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5841 13:18:59.133218 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5842 13:18:59.136306 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5843 13:18:59.139809 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5844 13:18:59.143180 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5845 13:18:59.145948 ==
5846 13:18:59.149271 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 13:18:59.152961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 13:18:59.153065 ==
5849 13:18:59.153157 DQS Delay:
5850 13:18:59.155975 DQS0 = 0, DQS1 = 0
5851 13:18:59.156053 DQM Delay:
5852 13:18:59.159553 DQM0 = 94, DQM1 = 90
5853 13:18:59.159631 DQ Delay:
5854 13:18:59.163141 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5855 13:18:59.166210 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5856 13:18:59.169439 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5857 13:18:59.172612 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5858 13:18:59.172690
5859 13:18:59.172750
5860 13:18:59.172806 ==
5861 13:18:59.176353 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 13:18:59.179442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 13:18:59.179546 ==
5864 13:18:59.179633
5865 13:18:59.179719
5866 13:18:59.182988 TX Vref Scan disable
5867 13:18:59.186007 == TX Byte 0 ==
5868 13:18:59.189528 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5869 13:18:59.192739 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5870 13:18:59.195860 == TX Byte 1 ==
5871 13:18:59.199487 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5872 13:18:59.203010 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5873 13:18:59.203113 ==
5874 13:18:59.206015 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 13:18:59.209719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 13:18:59.212808 ==
5877 13:18:59.212909
5878 13:18:59.213002
5879 13:18:59.213089 TX Vref Scan disable
5880 13:18:59.216441 == TX Byte 0 ==
5881 13:18:59.219483 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5882 13:18:59.226158 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5883 13:18:59.226235 == TX Byte 1 ==
5884 13:18:59.229550 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5885 13:18:59.236642 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5886 13:18:59.236742
5887 13:18:59.236835 [DATLAT]
5888 13:18:59.236918 Freq=933, CH1 RK1
5889 13:18:59.236999
5890 13:18:59.239678 DATLAT Default: 0xb
5891 13:18:59.239755 0, 0xFFFF, sum = 0
5892 13:18:59.243125 1, 0xFFFF, sum = 0
5893 13:18:59.243204 2, 0xFFFF, sum = 0
5894 13:18:59.246569 3, 0xFFFF, sum = 0
5895 13:18:59.246649 4, 0xFFFF, sum = 0
5896 13:18:59.249498 5, 0xFFFF, sum = 0
5897 13:18:59.252835 6, 0xFFFF, sum = 0
5898 13:18:59.252914 7, 0xFFFF, sum = 0
5899 13:18:59.256407 8, 0xFFFF, sum = 0
5900 13:18:59.256486 9, 0xFFFF, sum = 0
5901 13:18:59.259747 10, 0x0, sum = 1
5902 13:18:59.259826 11, 0x0, sum = 2
5903 13:18:59.259888 12, 0x0, sum = 3
5904 13:18:59.263148 13, 0x0, sum = 4
5905 13:18:59.263227 best_step = 11
5906 13:18:59.263286
5907 13:18:59.263341 ==
5908 13:18:59.266546 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 13:18:59.273220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 13:18:59.273306 ==
5911 13:18:59.273367 RX Vref Scan: 0
5912 13:18:59.273424
5913 13:18:59.276224 RX Vref 0 -> 0, step: 1
5914 13:18:59.276301
5915 13:18:59.279384 RX Delay -61 -> 252, step: 4
5916 13:18:59.283012 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5917 13:18:59.286686 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5918 13:18:59.293144 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5919 13:18:59.296167 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5920 13:18:59.300002 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5921 13:18:59.302979 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5922 13:18:59.306484 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5923 13:18:59.309533 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5924 13:18:59.316217 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5925 13:18:59.319854 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5926 13:18:59.322903 iDelay=195, Bit 10, Center 88 (-5 ~ 182) 188
5927 13:18:59.326699 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5928 13:18:59.330180 iDelay=195, Bit 12, Center 98 (11 ~ 186) 176
5929 13:18:59.336257 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5930 13:18:59.339813 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5931 13:18:59.343261 iDelay=195, Bit 15, Center 100 (11 ~ 190) 180
5932 13:18:59.343364 ==
5933 13:18:59.346571 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 13:18:59.349952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 13:18:59.350031 ==
5936 13:18:59.353248 DQS Delay:
5937 13:18:59.353327 DQS0 = 0, DQS1 = 0
5938 13:18:59.353397 DQM Delay:
5939 13:18:59.356397 DQM0 = 95, DQM1 = 90
5940 13:18:59.356474 DQ Delay:
5941 13:18:59.359711 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5942 13:18:59.363112 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5943 13:18:59.366826 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =82
5944 13:18:59.369708 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =100
5945 13:18:59.369787
5946 13:18:59.369848
5947 13:18:59.380162 [DQSOSCAuto] RK1, (LSB)MR18= 0x131d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
5948 13:18:59.383228 CH1 RK1: MR19=505, MR18=131D
5949 13:18:59.386866 CH1_RK1: MR19=0x505, MR18=0x131D, DQSOSC=412, MR23=63, INC=63, DEC=42
5950 13:18:59.389791 [RxdqsGatingPostProcess] freq 933
5951 13:18:59.396307 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 13:18:59.399801 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 13:18:59.403338 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 13:18:59.406500 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 13:18:59.409995 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 13:18:59.413011 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 13:18:59.416612 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 13:18:59.419742 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 13:18:59.423441 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 13:18:59.423520 Pre-setting of DQS Precalculation
5961 13:18:59.429516 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 13:18:59.436679 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 13:18:59.443323 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 13:18:59.443406
5965 13:18:59.443466
5966 13:18:59.446374 [Calibration Summary] 1866 Mbps
5967 13:18:59.449834 CH 0, Rank 0
5968 13:18:59.449911 SW Impedance : PASS
5969 13:18:59.453474 DUTY Scan : NO K
5970 13:18:59.456484 ZQ Calibration : PASS
5971 13:18:59.456563 Jitter Meter : NO K
5972 13:18:59.460093 CBT Training : PASS
5973 13:18:59.460171 Write leveling : PASS
5974 13:18:59.463190 RX DQS gating : PASS
5975 13:18:59.466834 RX DQ/DQS(RDDQC) : PASS
5976 13:18:59.466914 TX DQ/DQS : PASS
5977 13:18:59.470226 RX DATLAT : PASS
5978 13:18:59.473434 RX DQ/DQS(Engine): PASS
5979 13:18:59.473512 TX OE : NO K
5980 13:18:59.476643 All Pass.
5981 13:18:59.476721
5982 13:18:59.476780 CH 0, Rank 1
5983 13:18:59.480218 SW Impedance : PASS
5984 13:18:59.480302 DUTY Scan : NO K
5985 13:18:59.483427 ZQ Calibration : PASS
5986 13:18:59.486694 Jitter Meter : NO K
5987 13:18:59.486772 CBT Training : PASS
5988 13:18:59.490047 Write leveling : PASS
5989 13:18:59.493087 RX DQS gating : PASS
5990 13:18:59.493180 RX DQ/DQS(RDDQC) : PASS
5991 13:18:59.496770 TX DQ/DQS : PASS
5992 13:18:59.496849 RX DATLAT : PASS
5993 13:18:59.500141 RX DQ/DQS(Engine): PASS
5994 13:18:59.503645 TX OE : NO K
5995 13:18:59.503723 All Pass.
5996 13:18:59.503782
5997 13:18:59.503837 CH 1, Rank 0
5998 13:18:59.506557 SW Impedance : PASS
5999 13:18:59.510199 DUTY Scan : NO K
6000 13:18:59.510276 ZQ Calibration : PASS
6001 13:18:59.513227 Jitter Meter : NO K
6002 13:18:59.516739 CBT Training : PASS
6003 13:18:59.516816 Write leveling : PASS
6004 13:18:59.519933 RX DQS gating : PASS
6005 13:18:59.523675 RX DQ/DQS(RDDQC) : PASS
6006 13:18:59.523752 TX DQ/DQS : PASS
6007 13:18:59.526664 RX DATLAT : PASS
6008 13:18:59.530378 RX DQ/DQS(Engine): PASS
6009 13:18:59.530456 TX OE : NO K
6010 13:18:59.533447 All Pass.
6011 13:18:59.533524
6012 13:18:59.533584 CH 1, Rank 1
6013 13:18:59.536412 SW Impedance : PASS
6014 13:18:59.536489 DUTY Scan : NO K
6015 13:18:59.540099 ZQ Calibration : PASS
6016 13:18:59.543127 Jitter Meter : NO K
6017 13:18:59.543204 CBT Training : PASS
6018 13:18:59.546586 Write leveling : PASS
6019 13:18:59.546664 RX DQS gating : PASS
6020 13:18:59.549948 RX DQ/DQS(RDDQC) : PASS
6021 13:18:59.553366 TX DQ/DQS : PASS
6022 13:18:59.553443 RX DATLAT : PASS
6023 13:18:59.556439 RX DQ/DQS(Engine): PASS
6024 13:18:59.559954 TX OE : NO K
6025 13:18:59.560033 All Pass.
6026 13:18:59.560092
6027 13:18:59.563600 DramC Write-DBI off
6028 13:18:59.563677 PER_BANK_REFRESH: Hybrid Mode
6029 13:18:59.566839 TX_TRACKING: ON
6030 13:18:59.573452 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 13:18:59.580029 [FAST_K] Save calibration result to emmc
6032 13:18:59.583521 dramc_set_vcore_voltage set vcore to 650000
6033 13:18:59.583600 Read voltage for 400, 6
6034 13:18:59.586337 Vio18 = 0
6035 13:18:59.586415 Vcore = 650000
6036 13:18:59.586474 Vdram = 0
6037 13:18:59.589990 Vddq = 0
6038 13:18:59.590090 Vmddr = 0
6039 13:18:59.593011 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 13:18:59.599695 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 13:18:59.602919 MEM_TYPE=3, freq_sel=20
6042 13:18:59.606439 sv_algorithm_assistance_LP4_800
6043 13:18:59.609878 ============ PULL DRAM RESETB DOWN ============
6044 13:18:59.613056 ========== PULL DRAM RESETB DOWN end =========
6045 13:18:59.616686 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 13:18:59.619658 ===================================
6047 13:18:59.623117 LPDDR4 DRAM CONFIGURATION
6048 13:18:59.626263 ===================================
6049 13:18:59.630081 EX_ROW_EN[0] = 0x0
6050 13:18:59.630158 EX_ROW_EN[1] = 0x0
6051 13:18:59.632964 LP4Y_EN = 0x0
6052 13:18:59.633066 WORK_FSP = 0x0
6053 13:18:59.636666 WL = 0x2
6054 13:18:59.636779 RL = 0x2
6055 13:18:59.639851 BL = 0x2
6056 13:18:59.639927 RPST = 0x0
6057 13:18:59.642925 RD_PRE = 0x0
6058 13:18:59.643001 WR_PRE = 0x1
6059 13:18:59.646676 WR_PST = 0x0
6060 13:18:59.649673 DBI_WR = 0x0
6061 13:18:59.649789 DBI_RD = 0x0
6062 13:18:59.653295 OTF = 0x1
6063 13:18:59.656718 ===================================
6064 13:18:59.656794 ===================================
6065 13:18:59.660327 ANA top config
6066 13:18:59.663389 ===================================
6067 13:18:59.666753 DLL_ASYNC_EN = 0
6068 13:18:59.666831 ALL_SLAVE_EN = 1
6069 13:18:59.669845 NEW_RANK_MODE = 1
6070 13:18:59.673412 DLL_IDLE_MODE = 1
6071 13:18:59.676504 LP45_APHY_COMB_EN = 1
6072 13:18:59.676572 TX_ODT_DIS = 1
6073 13:18:59.680168 NEW_8X_MODE = 1
6074 13:18:59.683147 ===================================
6075 13:18:59.686810 ===================================
6076 13:18:59.690485 data_rate = 800
6077 13:18:59.693264 CKR = 1
6078 13:18:59.696726 DQ_P2S_RATIO = 4
6079 13:18:59.700159 ===================================
6080 13:18:59.703776 CA_P2S_RATIO = 4
6081 13:18:59.703886 DQ_CA_OPEN = 0
6082 13:18:59.706784 DQ_SEMI_OPEN = 1
6083 13:18:59.710395 CA_SEMI_OPEN = 1
6084 13:18:59.713287 CA_FULL_RATE = 0
6085 13:18:59.716915 DQ_CKDIV4_EN = 0
6086 13:18:59.720407 CA_CKDIV4_EN = 1
6087 13:18:59.720519 CA_PREDIV_EN = 0
6088 13:18:59.723198 PH8_DLY = 0
6089 13:18:59.726873 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 13:18:59.729912 DQ_AAMCK_DIV = 0
6091 13:18:59.733067 CA_AAMCK_DIV = 0
6092 13:18:59.736804 CA_ADMCK_DIV = 4
6093 13:18:59.736912 DQ_TRACK_CA_EN = 0
6094 13:18:59.740141 CA_PICK = 800
6095 13:18:59.743791 CA_MCKIO = 400
6096 13:18:59.746733 MCKIO_SEMI = 400
6097 13:18:59.749852 PLL_FREQ = 3016
6098 13:18:59.753393 DQ_UI_PI_RATIO = 32
6099 13:18:59.756529 CA_UI_PI_RATIO = 32
6100 13:18:59.760326 ===================================
6101 13:18:59.763472 ===================================
6102 13:18:59.763549 memory_type:LPDDR4
6103 13:18:59.766789 GP_NUM : 10
6104 13:18:59.769939 SRAM_EN : 1
6105 13:18:59.770016 MD32_EN : 0
6106 13:18:59.773791 ===================================
6107 13:18:59.776752 [ANA_INIT] >>>>>>>>>>>>>>
6108 13:18:59.779763 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 13:18:59.783476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 13:18:59.787116 ===================================
6111 13:18:59.787193 data_rate = 800,PCW = 0X7400
6112 13:18:59.790130 ===================================
6113 13:18:59.793687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 13:18:59.800021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 13:18:59.813504 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 13:18:59.816705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 13:18:59.820333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 13:18:59.823491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 13:18:59.827181 [ANA_INIT] flow start
6120 13:18:59.827259 [ANA_INIT] PLL >>>>>>>>
6121 13:18:59.830158 [ANA_INIT] PLL <<<<<<<<
6122 13:18:59.833332 [ANA_INIT] MIDPI >>>>>>>>
6123 13:18:59.833409 [ANA_INIT] MIDPI <<<<<<<<
6124 13:18:59.836856 [ANA_INIT] DLL >>>>>>>>
6125 13:18:59.840175 [ANA_INIT] flow end
6126 13:18:59.843544 ============ LP4 DIFF to SE enter ============
6127 13:18:59.846877 ============ LP4 DIFF to SE exit ============
6128 13:18:59.850489 [ANA_INIT] <<<<<<<<<<<<<
6129 13:18:59.853543 [Flow] Enable top DCM control >>>>>
6130 13:18:59.856849 [Flow] Enable top DCM control <<<<<
6131 13:18:59.860051 Enable DLL master slave shuffle
6132 13:18:59.863788 ==============================================================
6133 13:18:59.866800 Gating Mode config
6134 13:18:59.870410 ==============================================================
6135 13:18:59.873947 Config description:
6136 13:18:59.883933 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 13:18:59.890402 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 13:18:59.894147 SELPH_MODE 0: By rank 1: By Phase
6139 13:18:59.900785 ==============================================================
6140 13:18:59.903657 GAT_TRACK_EN = 0
6141 13:18:59.907341 RX_GATING_MODE = 2
6142 13:18:59.910155 RX_GATING_TRACK_MODE = 2
6143 13:18:59.913611 SELPH_MODE = 1
6144 13:18:59.917052 PICG_EARLY_EN = 1
6145 13:18:59.917140 VALID_LAT_VALUE = 1
6146 13:18:59.923872 ==============================================================
6147 13:18:59.926785 Enter into Gating configuration >>>>
6148 13:18:59.930469 Exit from Gating configuration <<<<
6149 13:18:59.933511 Enter into DVFS_PRE_config >>>>>
6150 13:18:59.943724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 13:18:59.946842 Exit from DVFS_PRE_config <<<<<
6152 13:18:59.950445 Enter into PICG configuration >>>>
6153 13:18:59.953872 Exit from PICG configuration <<<<
6154 13:18:59.956969 [RX_INPUT] configuration >>>>>
6155 13:18:59.960535 [RX_INPUT] configuration <<<<<
6156 13:18:59.963335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 13:18:59.970342 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 13:18:59.977215 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 13:18:59.983806 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 13:18:59.990539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 13:18:59.996673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 13:19:00.000378 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 13:19:00.003465 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 13:19:00.007001 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 13:19:00.010182 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 13:19:00.016713 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 13:19:00.020312 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 13:19:00.023242 ===================================
6169 13:19:00.026801 LPDDR4 DRAM CONFIGURATION
6170 13:19:00.030415 ===================================
6171 13:19:00.030488 EX_ROW_EN[0] = 0x0
6172 13:19:00.033415 EX_ROW_EN[1] = 0x0
6173 13:19:00.033508 LP4Y_EN = 0x0
6174 13:19:00.037017 WORK_FSP = 0x0
6175 13:19:00.037124 WL = 0x2
6176 13:19:00.040200 RL = 0x2
6177 13:19:00.040293 BL = 0x2
6178 13:19:00.043856 RPST = 0x0
6179 13:19:00.043927 RD_PRE = 0x0
6180 13:19:00.046780 WR_PRE = 0x1
6181 13:19:00.046848 WR_PST = 0x0
6182 13:19:00.050406 DBI_WR = 0x0
6183 13:19:00.050505 DBI_RD = 0x0
6184 13:19:00.053505 OTF = 0x1
6185 13:19:00.056993 ===================================
6186 13:19:00.060521 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 13:19:00.063817 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 13:19:00.070453 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 13:19:00.074050 ===================================
6190 13:19:00.074131 LPDDR4 DRAM CONFIGURATION
6191 13:19:00.077344 ===================================
6192 13:19:00.080562 EX_ROW_EN[0] = 0x10
6193 13:19:00.083882 EX_ROW_EN[1] = 0x0
6194 13:19:00.083957 LP4Y_EN = 0x0
6195 13:19:00.087227 WORK_FSP = 0x0
6196 13:19:00.087299 WL = 0x2
6197 13:19:00.090571 RL = 0x2
6198 13:19:00.090649 BL = 0x2
6199 13:19:00.093572 RPST = 0x0
6200 13:19:00.093647 RD_PRE = 0x0
6201 13:19:00.097413 WR_PRE = 0x1
6202 13:19:00.097486 WR_PST = 0x0
6203 13:19:00.100341 DBI_WR = 0x0
6204 13:19:00.100410 DBI_RD = 0x0
6205 13:19:00.103992 OTF = 0x1
6206 13:19:00.107058 ===================================
6207 13:19:00.114068 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 13:19:00.117520 nWR fixed to 30
6209 13:19:00.117600 [ModeRegInit_LP4] CH0 RK0
6210 13:19:00.120461 [ModeRegInit_LP4] CH0 RK1
6211 13:19:00.124063 [ModeRegInit_LP4] CH1 RK0
6212 13:19:00.124142 [ModeRegInit_LP4] CH1 RK1
6213 13:19:00.127136 match AC timing 19
6214 13:19:00.130782 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 13:19:00.133720 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 13:19:00.140544 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 13:19:00.144337 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 13:19:00.150369 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 13:19:00.150447 ==
6220 13:19:00.153962 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 13:19:00.156994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 13:19:00.157096 ==
6223 13:19:00.163533 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 13:19:00.167364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6225 13:19:00.170268 [CA 0] Center 36 (8~64) winsize 57
6226 13:19:00.173893 [CA 1] Center 36 (8~64) winsize 57
6227 13:19:00.177000 [CA 2] Center 36 (8~64) winsize 57
6228 13:19:00.180774 [CA 3] Center 36 (8~64) winsize 57
6229 13:19:00.183802 [CA 4] Center 36 (8~64) winsize 57
6230 13:19:00.187381 [CA 5] Center 36 (8~64) winsize 57
6231 13:19:00.187458
6232 13:19:00.190861 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6233 13:19:00.190937
6234 13:19:00.193793 [CATrainingPosCal] consider 1 rank data
6235 13:19:00.197240 u2DelayCellTimex100 = 270/100 ps
6236 13:19:00.200562 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 13:19:00.204023 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 13:19:00.207349 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 13:19:00.213874 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 13:19:00.217504 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:19:00.220486 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:19:00.220563
6243 13:19:00.224043 CA PerBit enable=1, Macro0, CA PI delay=36
6244 13:19:00.224145
6245 13:19:00.227215 [CBTSetCACLKResult] CA Dly = 36
6246 13:19:00.227293 CS Dly: 1 (0~32)
6247 13:19:00.227352 ==
6248 13:19:00.230797 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 13:19:00.237332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 13:19:00.237417 ==
6251 13:19:00.240425 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 13:19:00.247176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 13:19:00.250337 [CA 0] Center 36 (8~64) winsize 57
6254 13:19:00.253912 [CA 1] Center 36 (8~64) winsize 57
6255 13:19:00.257410 [CA 2] Center 36 (8~64) winsize 57
6256 13:19:00.260523 [CA 3] Center 36 (8~64) winsize 57
6257 13:19:00.264141 [CA 4] Center 36 (8~64) winsize 57
6258 13:19:00.267119 [CA 5] Center 36 (8~64) winsize 57
6259 13:19:00.267199
6260 13:19:00.270539 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 13:19:00.270616
6262 13:19:00.274208 [CATrainingPosCal] consider 2 rank data
6263 13:19:00.277358 u2DelayCellTimex100 = 270/100 ps
6264 13:19:00.280462 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 13:19:00.284170 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 13:19:00.287518 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 13:19:00.290541 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 13:19:00.294116 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 13:19:00.297178 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 13:19:00.297254
6271 13:19:00.300807 CA PerBit enable=1, Macro0, CA PI delay=36
6272 13:19:00.303832
6273 13:19:00.303911 [CBTSetCACLKResult] CA Dly = 36
6274 13:19:00.307407 CS Dly: 1 (0~32)
6275 13:19:00.307484
6276 13:19:00.310646 ----->DramcWriteLeveling(PI) begin...
6277 13:19:00.310736 ==
6278 13:19:00.313782 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 13:19:00.317305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 13:19:00.317385 ==
6281 13:19:00.320651 Write leveling (Byte 0): 40 => 8
6282 13:19:00.324128 Write leveling (Byte 1): 32 => 0
6283 13:19:00.327288 DramcWriteLeveling(PI) end<-----
6284 13:19:00.327366
6285 13:19:00.327462 ==
6286 13:19:00.330692 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 13:19:00.334045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 13:19:00.334138 ==
6289 13:19:00.337688 [Gating] SW mode calibration
6290 13:19:00.344405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 13:19:00.350854 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 13:19:00.353809 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 13:19:00.360491 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 13:19:00.364023 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 13:19:00.367122 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 13:19:00.373610 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 13:19:00.377111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 13:19:00.380845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 13:19:00.383807 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 13:19:00.390472 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 13:19:00.393581 Total UI for P1: 0, mck2ui 16
6302 13:19:00.397103 best dqsien dly found for B0: ( 0, 14, 24)
6303 13:19:00.400757 Total UI for P1: 0, mck2ui 16
6304 13:19:00.403902 best dqsien dly found for B1: ( 0, 14, 24)
6305 13:19:00.406851 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 13:19:00.410589 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 13:19:00.410666
6308 13:19:00.413549 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 13:19:00.416882 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 13:19:00.420208 [Gating] SW calibration Done
6311 13:19:00.420284 ==
6312 13:19:00.423717 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 13:19:00.426940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 13:19:00.427022 ==
6315 13:19:00.430562 RX Vref Scan: 0
6316 13:19:00.430638
6317 13:19:00.433507 RX Vref 0 -> 0, step: 1
6318 13:19:00.433605
6319 13:19:00.433695 RX Delay -410 -> 252, step: 16
6320 13:19:00.440753 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6321 13:19:00.444037 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6322 13:19:00.446936 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6323 13:19:00.450555 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6324 13:19:00.456964 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6325 13:19:00.460317 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6326 13:19:00.464168 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6327 13:19:00.467202 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6328 13:19:00.473775 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6329 13:19:00.477499 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6330 13:19:00.480366 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6331 13:19:00.483930 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6332 13:19:00.490570 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6333 13:19:00.493781 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6334 13:19:00.496756 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6335 13:19:00.500280 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6336 13:19:00.503723 ==
6337 13:19:00.506855 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 13:19:00.510549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 13:19:00.510625 ==
6340 13:19:00.510698 DQS Delay:
6341 13:19:00.513652 DQS0 = 43, DQS1 = 51
6342 13:19:00.513730 DQM Delay:
6343 13:19:00.517270 DQM0 = 14, DQM1 = 10
6344 13:19:00.517359 DQ Delay:
6345 13:19:00.520375 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =8
6346 13:19:00.523466 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6347 13:19:00.527053 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6348 13:19:00.530308 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6349 13:19:00.530385
6350 13:19:00.530445
6351 13:19:00.530500 ==
6352 13:19:00.533730 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 13:19:00.537151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 13:19:00.537235 ==
6355 13:19:00.537294
6356 13:19:00.537348
6357 13:19:00.540671 TX Vref Scan disable
6358 13:19:00.540747 == TX Byte 0 ==
6359 13:19:00.547235 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 13:19:00.550501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 13:19:00.550580 == TX Byte 1 ==
6362 13:19:00.557165 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6363 13:19:00.560194 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6364 13:19:00.560274 ==
6365 13:19:00.563913 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 13:19:00.566975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 13:19:00.567057 ==
6368 13:19:00.567118
6369 13:19:00.567173
6370 13:19:00.570482 TX Vref Scan disable
6371 13:19:00.570560 == TX Byte 0 ==
6372 13:19:00.576974 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 13:19:00.580321 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 13:19:00.580401 == TX Byte 1 ==
6375 13:19:00.586909 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6376 13:19:00.590322 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6377 13:19:00.590402
6378 13:19:00.590463 [DATLAT]
6379 13:19:00.593980 Freq=400, CH0 RK0
6380 13:19:00.594060
6381 13:19:00.594120 DATLAT Default: 0xf
6382 13:19:00.596819 0, 0xFFFF, sum = 0
6383 13:19:00.596899 1, 0xFFFF, sum = 0
6384 13:19:00.600480 2, 0xFFFF, sum = 0
6385 13:19:00.600560 3, 0xFFFF, sum = 0
6386 13:19:00.603569 4, 0xFFFF, sum = 0
6387 13:19:00.603648 5, 0xFFFF, sum = 0
6388 13:19:00.606950 6, 0xFFFF, sum = 0
6389 13:19:00.607030 7, 0xFFFF, sum = 0
6390 13:19:00.610623 8, 0xFFFF, sum = 0
6391 13:19:00.610702 9, 0xFFFF, sum = 0
6392 13:19:00.613765 10, 0xFFFF, sum = 0
6393 13:19:00.617330 11, 0xFFFF, sum = 0
6394 13:19:00.617412 12, 0xFFFF, sum = 0
6395 13:19:00.620390 13, 0x0, sum = 1
6396 13:19:00.620470 14, 0x0, sum = 2
6397 13:19:00.620532 15, 0x0, sum = 3
6398 13:19:00.624250 16, 0x0, sum = 4
6399 13:19:00.624330 best_step = 14
6400 13:19:00.624391
6401 13:19:00.624447 ==
6402 13:19:00.627197 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 13:19:00.634025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 13:19:00.634124 ==
6405 13:19:00.634185 RX Vref Scan: 1
6406 13:19:00.634240
6407 13:19:00.637403 RX Vref 0 -> 0, step: 1
6408 13:19:00.637481
6409 13:19:00.640189 RX Delay -343 -> 252, step: 8
6410 13:19:00.640266
6411 13:19:00.644087 Set Vref, RX VrefLevel [Byte0]: 53
6412 13:19:00.646851 [Byte1]: 54
6413 13:19:00.650493
6414 13:19:00.650601 Final RX Vref Byte 0 = 53 to rank0
6415 13:19:00.653970 Final RX Vref Byte 1 = 54 to rank0
6416 13:19:00.657333 Final RX Vref Byte 0 = 53 to rank1
6417 13:19:00.660634 Final RX Vref Byte 1 = 54 to rank1==
6418 13:19:00.663786 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 13:19:00.670678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 13:19:00.670764 ==
6421 13:19:00.670826 DQS Delay:
6422 13:19:00.673531 DQS0 = 44, DQS1 = 60
6423 13:19:00.673635 DQM Delay:
6424 13:19:00.673729 DQM0 = 10, DQM1 = 13
6425 13:19:00.677142 DQ Delay:
6426 13:19:00.680171 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6427 13:19:00.680321 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6428 13:19:00.683871 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6429 13:19:00.686947 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6430 13:19:00.687051
6431 13:19:00.690539
6432 13:19:00.697288 [DQSOSCAuto] RK0, (LSB)MR18= 0x8654, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6433 13:19:00.700429 CH0 RK0: MR19=C0C, MR18=8654
6434 13:19:00.707318 CH0_RK0: MR19=0xC0C, MR18=0x8654, DQSOSC=393, MR23=63, INC=382, DEC=254
6435 13:19:00.707397 ==
6436 13:19:00.710277 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 13:19:00.714159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 13:19:00.714263 ==
6439 13:19:00.717101 [Gating] SW mode calibration
6440 13:19:00.723766 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 13:19:00.727393 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 13:19:00.734165 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 13:19:00.737283 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 13:19:00.740790 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 13:19:00.747094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 13:19:00.750501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 13:19:00.753979 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 13:19:00.760699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 13:19:00.764118 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 13:19:00.767412 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 13:19:00.770953 Total UI for P1: 0, mck2ui 16
6452 13:19:00.774080 best dqsien dly found for B0: ( 0, 14, 24)
6453 13:19:00.777330 Total UI for P1: 0, mck2ui 16
6454 13:19:00.780951 best dqsien dly found for B1: ( 0, 14, 24)
6455 13:19:00.783937 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 13:19:00.787574 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 13:19:00.787653
6458 13:19:00.791148 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 13:19:00.797748 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 13:19:00.797818 [Gating] SW calibration Done
6461 13:19:00.797876 ==
6462 13:19:00.800951 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 13:19:00.807670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 13:19:00.807749 ==
6465 13:19:00.807818 RX Vref Scan: 0
6466 13:19:00.807877
6467 13:19:00.810944 RX Vref 0 -> 0, step: 1
6468 13:19:00.811020
6469 13:19:00.814436 RX Delay -410 -> 252, step: 16
6470 13:19:00.817432 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6471 13:19:00.820518 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6472 13:19:00.827382 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6473 13:19:00.830989 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6474 13:19:00.834037 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6475 13:19:00.837365 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6476 13:19:00.844029 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6477 13:19:00.847157 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6478 13:19:00.850646 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6479 13:19:00.854202 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6480 13:19:00.860589 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6481 13:19:00.864147 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6482 13:19:00.867188 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6483 13:19:00.870850 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6484 13:19:00.877559 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6485 13:19:00.880571 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6486 13:19:00.880647 ==
6487 13:19:00.884286 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 13:19:00.887523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 13:19:00.887600 ==
6490 13:19:00.890917 DQS Delay:
6491 13:19:00.891049 DQS0 = 43, DQS1 = 51
6492 13:19:00.893996 DQM Delay:
6493 13:19:00.894071 DQM0 = 13, DQM1 = 10
6494 13:19:00.894130 DQ Delay:
6495 13:19:00.897175 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6496 13:19:00.900770 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6497 13:19:00.903847 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 13:19:00.907573 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6499 13:19:00.907679
6500 13:19:00.907738
6501 13:19:00.907791 ==
6502 13:19:00.910671 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 13:19:00.914217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 13:19:00.917427 ==
6505 13:19:00.917544
6506 13:19:00.917604
6507 13:19:00.917658 TX Vref Scan disable
6508 13:19:00.920917 == TX Byte 0 ==
6509 13:19:00.923964 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6510 13:19:00.927513 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6511 13:19:00.930555 == TX Byte 1 ==
6512 13:19:00.933958 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6513 13:19:00.937633 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6514 13:19:00.937755 ==
6515 13:19:00.940804 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 13:19:00.944077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 13:19:00.947475 ==
6518 13:19:00.947566
6519 13:19:00.947650
6520 13:19:00.947706 TX Vref Scan disable
6521 13:19:00.950975 == TX Byte 0 ==
6522 13:19:00.954466 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6523 13:19:00.957245 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6524 13:19:00.960578 == TX Byte 1 ==
6525 13:19:00.963989 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6526 13:19:00.967492 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6527 13:19:00.967585
6528 13:19:00.967685 [DATLAT]
6529 13:19:00.970576 Freq=400, CH0 RK1
6530 13:19:00.970643
6531 13:19:00.974318 DATLAT Default: 0xe
6532 13:19:00.974408 0, 0xFFFF, sum = 0
6533 13:19:00.977340 1, 0xFFFF, sum = 0
6534 13:19:00.977407 2, 0xFFFF, sum = 0
6535 13:19:00.980646 3, 0xFFFF, sum = 0
6536 13:19:00.980711 4, 0xFFFF, sum = 0
6537 13:19:00.984433 5, 0xFFFF, sum = 0
6538 13:19:00.984549 6, 0xFFFF, sum = 0
6539 13:19:00.987492 7, 0xFFFF, sum = 0
6540 13:19:00.987624 8, 0xFFFF, sum = 0
6541 13:19:00.991150 9, 0xFFFF, sum = 0
6542 13:19:00.991259 10, 0xFFFF, sum = 0
6543 13:19:00.993968 11, 0xFFFF, sum = 0
6544 13:19:00.994037 12, 0xFFFF, sum = 0
6545 13:19:00.997828 13, 0x0, sum = 1
6546 13:19:00.997959 14, 0x0, sum = 2
6547 13:19:01.001011 15, 0x0, sum = 3
6548 13:19:01.001102 16, 0x0, sum = 4
6549 13:19:01.004576 best_step = 14
6550 13:19:01.004657
6551 13:19:01.004725 ==
6552 13:19:01.007652 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 13:19:01.011233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 13:19:01.011327 ==
6555 13:19:01.011417 RX Vref Scan: 0
6556 13:19:01.014244
6557 13:19:01.014315 RX Vref 0 -> 0, step: 1
6558 13:19:01.014404
6559 13:19:01.017800 RX Delay -343 -> 252, step: 8
6560 13:19:01.025009 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6561 13:19:01.028116 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6562 13:19:01.031753 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6563 13:19:01.035221 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6564 13:19:01.041672 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6565 13:19:01.044716 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6566 13:19:01.048493 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6567 13:19:01.051854 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6568 13:19:01.058304 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6569 13:19:01.061456 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6570 13:19:01.064981 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6571 13:19:01.068075 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6572 13:19:01.075039 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6573 13:19:01.078111 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6574 13:19:01.081914 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6575 13:19:01.085287 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6576 13:19:01.088192 ==
6577 13:19:01.092012 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 13:19:01.094889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 13:19:01.094967 ==
6580 13:19:01.095028 DQS Delay:
6581 13:19:01.098532 DQS0 = 48, DQS1 = 60
6582 13:19:01.098621 DQM Delay:
6583 13:19:01.101509 DQM0 = 12, DQM1 = 13
6584 13:19:01.101588 DQ Delay:
6585 13:19:01.105290 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6586 13:19:01.108221 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6587 13:19:01.111947 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6588 13:19:01.115134 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6589 13:19:01.115212
6590 13:19:01.115271
6591 13:19:01.121757 [DQSOSCAuto] RK1, (LSB)MR18= 0x976b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6592 13:19:01.125481 CH0 RK1: MR19=C0C, MR18=976B
6593 13:19:01.131986 CH0_RK1: MR19=0xC0C, MR18=0x976B, DQSOSC=390, MR23=63, INC=388, DEC=258
6594 13:19:01.134881 [RxdqsGatingPostProcess] freq 400
6595 13:19:01.138503 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 13:19:01.141444 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 13:19:01.145067 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 13:19:01.148528 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 13:19:01.151549 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 13:19:01.155170 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 13:19:01.158314 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 13:19:01.161698 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 13:19:01.164800 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 13:19:01.168401 Pre-setting of DQS Precalculation
6605 13:19:01.171697 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 13:19:01.174959 ==
6607 13:19:01.175035 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 13:19:01.181661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 13:19:01.181741 ==
6610 13:19:01.184707 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 13:19:01.191589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 13:19:01.194845 [CA 0] Center 36 (8~64) winsize 57
6613 13:19:01.198155 [CA 1] Center 36 (8~64) winsize 57
6614 13:19:01.201457 [CA 2] Center 36 (8~64) winsize 57
6615 13:19:01.204768 [CA 3] Center 36 (8~64) winsize 57
6616 13:19:01.208055 [CA 4] Center 36 (8~64) winsize 57
6617 13:19:01.211130 [CA 5] Center 36 (8~64) winsize 57
6618 13:19:01.211207
6619 13:19:01.214811 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 13:19:01.214887
6621 13:19:01.218522 [CATrainingPosCal] consider 1 rank data
6622 13:19:01.221411 u2DelayCellTimex100 = 270/100 ps
6623 13:19:01.225344 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 13:19:01.228235 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 13:19:01.231243 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 13:19:01.234867 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 13:19:01.238078 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:19:01.244601 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:19:01.244678
6630 13:19:01.248223 CA PerBit enable=1, Macro0, CA PI delay=36
6631 13:19:01.248301
6632 13:19:01.251786 [CBTSetCACLKResult] CA Dly = 36
6633 13:19:01.251862 CS Dly: 1 (0~32)
6634 13:19:01.251922 ==
6635 13:19:01.254825 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 13:19:01.257932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 13:19:01.258010 ==
6638 13:19:01.264805 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 13:19:01.271470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 13:19:01.275197 [CA 0] Center 36 (8~64) winsize 57
6641 13:19:01.278019 [CA 1] Center 36 (8~64) winsize 57
6642 13:19:01.281562 [CA 2] Center 36 (8~64) winsize 57
6643 13:19:01.285043 [CA 3] Center 36 (8~64) winsize 57
6644 13:19:01.285158 [CA 4] Center 36 (8~64) winsize 57
6645 13:19:01.288163 [CA 5] Center 36 (8~64) winsize 57
6646 13:19:01.288239
6647 13:19:01.295209 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 13:19:01.295289
6649 13:19:01.298573 [CATrainingPosCal] consider 2 rank data
6650 13:19:01.301594 u2DelayCellTimex100 = 270/100 ps
6651 13:19:01.305375 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 13:19:01.308365 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 13:19:01.311765 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 13:19:01.314909 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 13:19:01.318633 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 13:19:01.321627 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 13:19:01.321736
6658 13:19:01.324664 CA PerBit enable=1, Macro0, CA PI delay=36
6659 13:19:01.324758
6660 13:19:01.328224 [CBTSetCACLKResult] CA Dly = 36
6661 13:19:01.331946 CS Dly: 1 (0~32)
6662 13:19:01.332055
6663 13:19:01.335099 ----->DramcWriteLeveling(PI) begin...
6664 13:19:01.335177 ==
6665 13:19:01.338228 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 13:19:01.341771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 13:19:01.341849 ==
6668 13:19:01.345164 Write leveling (Byte 0): 40 => 8
6669 13:19:01.348231 Write leveling (Byte 1): 40 => 8
6670 13:19:01.351943 DramcWriteLeveling(PI) end<-----
6671 13:19:01.352019
6672 13:19:01.352078 ==
6673 13:19:01.354742 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 13:19:01.358320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 13:19:01.358399 ==
6676 13:19:01.361914 [Gating] SW mode calibration
6677 13:19:01.368622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 13:19:01.374777 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 13:19:01.378403 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 13:19:01.381789 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6681 13:19:01.388489 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 13:19:01.391906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 13:19:01.395133 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 13:19:01.401453 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 13:19:01.404868 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 13:19:01.408350 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 13:19:01.411448 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 13:19:01.414979 Total UI for P1: 0, mck2ui 16
6689 13:19:01.418153 best dqsien dly found for B0: ( 0, 14, 24)
6690 13:19:01.421933 Total UI for P1: 0, mck2ui 16
6691 13:19:01.424838 best dqsien dly found for B1: ( 0, 14, 24)
6692 13:19:01.428189 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 13:19:01.434649 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 13:19:01.434727
6695 13:19:01.438603 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 13:19:01.441506 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 13:19:01.445106 [Gating] SW calibration Done
6698 13:19:01.445217 ==
6699 13:19:01.448126 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 13:19:01.451713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 13:19:01.451848 ==
6702 13:19:01.451940 RX Vref Scan: 0
6703 13:19:01.454858
6704 13:19:01.454929 RX Vref 0 -> 0, step: 1
6705 13:19:01.454986
6706 13:19:01.458367 RX Delay -410 -> 252, step: 16
6707 13:19:01.461871 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6708 13:19:01.467986 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6709 13:19:01.471678 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6710 13:19:01.474679 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6711 13:19:01.478409 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6712 13:19:01.485181 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6713 13:19:01.488128 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6714 13:19:01.491593 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6715 13:19:01.495178 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6716 13:19:01.501736 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6717 13:19:01.505043 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6718 13:19:01.507990 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6719 13:19:01.511431 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6720 13:19:01.518590 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6721 13:19:01.521577 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6722 13:19:01.525066 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6723 13:19:01.525170 ==
6724 13:19:01.528145 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 13:19:01.531910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 13:19:01.534821 ==
6727 13:19:01.534887 DQS Delay:
6728 13:19:01.534948 DQS0 = 51, DQS1 = 59
6729 13:19:01.538409 DQM Delay:
6730 13:19:01.538497 DQM0 = 19, DQM1 = 16
6731 13:19:01.541835 DQ Delay:
6732 13:19:01.541925 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6733 13:19:01.545077 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6734 13:19:01.548465 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6735 13:19:01.551894 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6736 13:19:01.551973
6737 13:19:01.552048
6738 13:19:01.555382 ==
6739 13:19:01.558409 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 13:19:01.561870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 13:19:01.561950 ==
6742 13:19:01.562026
6743 13:19:01.562098
6744 13:19:01.565350 TX Vref Scan disable
6745 13:19:01.565427 == TX Byte 0 ==
6746 13:19:01.568469 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 13:19:01.572142 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 13:19:01.575137 == TX Byte 1 ==
6749 13:19:01.578774 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 13:19:01.582318 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 13:19:01.585524 ==
6752 13:19:01.585591 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 13:19:01.592150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 13:19:01.592245 ==
6755 13:19:01.592327
6756 13:19:01.592408
6757 13:19:01.594906 TX Vref Scan disable
6758 13:19:01.594996 == TX Byte 0 ==
6759 13:19:01.598217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 13:19:01.605433 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 13:19:01.605528 == TX Byte 1 ==
6762 13:19:01.608336 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 13:19:01.611570 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 13:19:01.615100
6765 13:19:01.615177 [DATLAT]
6766 13:19:01.615254 Freq=400, CH1 RK0
6767 13:19:01.615325
6768 13:19:01.618634 DATLAT Default: 0xf
6769 13:19:01.618711 0, 0xFFFF, sum = 0
6770 13:19:01.622095 1, 0xFFFF, sum = 0
6771 13:19:01.622175 2, 0xFFFF, sum = 0
6772 13:19:01.624952 3, 0xFFFF, sum = 0
6773 13:19:01.625026 4, 0xFFFF, sum = 0
6774 13:19:01.628685 5, 0xFFFF, sum = 0
6775 13:19:01.631975 6, 0xFFFF, sum = 0
6776 13:19:01.632047 7, 0xFFFF, sum = 0
6777 13:19:01.634724 8, 0xFFFF, sum = 0
6778 13:19:01.634795 9, 0xFFFF, sum = 0
6779 13:19:01.638417 10, 0xFFFF, sum = 0
6780 13:19:01.638488 11, 0xFFFF, sum = 0
6781 13:19:01.641501 12, 0xFFFF, sum = 0
6782 13:19:01.641567 13, 0x0, sum = 1
6783 13:19:01.645266 14, 0x0, sum = 2
6784 13:19:01.645332 15, 0x0, sum = 3
6785 13:19:01.648214 16, 0x0, sum = 4
6786 13:19:01.648280 best_step = 14
6787 13:19:01.648334
6788 13:19:01.648405 ==
6789 13:19:01.651661 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 13:19:01.654994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 13:19:01.655071 ==
6792 13:19:01.658508 RX Vref Scan: 1
6793 13:19:01.658594
6794 13:19:01.661634 RX Vref 0 -> 0, step: 1
6795 13:19:01.661699
6796 13:19:01.665044 RX Delay -359 -> 252, step: 8
6797 13:19:01.665113
6798 13:19:01.665213 Set Vref, RX VrefLevel [Byte0]: 61
6799 13:19:01.667872 [Byte1]: 53
6800 13:19:01.673871
6801 13:19:01.673943 Final RX Vref Byte 0 = 61 to rank0
6802 13:19:01.677019 Final RX Vref Byte 1 = 53 to rank0
6803 13:19:01.680536 Final RX Vref Byte 0 = 61 to rank1
6804 13:19:01.683554 Final RX Vref Byte 1 = 53 to rank1==
6805 13:19:01.687110 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 13:19:01.693952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 13:19:01.694031 ==
6808 13:19:01.694092 DQS Delay:
6809 13:19:01.694146 DQS0 = 48, DQS1 = 60
6810 13:19:01.697016 DQM Delay:
6811 13:19:01.697081 DQM0 = 11, DQM1 = 13
6812 13:19:01.700606 DQ Delay:
6813 13:19:01.703887 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6814 13:19:01.703959 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6815 13:19:01.707414 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6816 13:19:01.710561 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6817 13:19:01.710627
6818 13:19:01.710686
6819 13:19:01.720662 [DQSOSCAuto] RK0, (LSB)MR18= 0x9238, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6820 13:19:01.724330 CH1 RK0: MR19=C0C, MR18=9238
6821 13:19:01.727310 CH1_RK0: MR19=0xC0C, MR18=0x9238, DQSOSC=391, MR23=63, INC=386, DEC=257
6822 13:19:01.730663 ==
6823 13:19:01.734336 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 13:19:01.737888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 13:19:01.737960 ==
6826 13:19:01.740763 [Gating] SW mode calibration
6827 13:19:01.747479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 13:19:01.751193 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 13:19:01.757688 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6830 13:19:01.761157 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 13:19:01.763927 0 12 0 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
6832 13:19:01.770520 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 13:19:01.773851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 13:19:01.777570 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 13:19:01.784306 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 13:19:01.787329 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 13:19:01.791002 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 13:19:01.794051 Total UI for P1: 0, mck2ui 16
6839 13:19:01.797140 best dqsien dly found for B0: ( 0, 14, 24)
6840 13:19:01.800828 Total UI for P1: 0, mck2ui 16
6841 13:19:01.804061 best dqsien dly found for B1: ( 0, 14, 24)
6842 13:19:01.807536 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 13:19:01.810984 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 13:19:01.811053
6845 13:19:01.814312 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 13:19:01.820890 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 13:19:01.820972 [Gating] SW calibration Done
6848 13:19:01.823873 ==
6849 13:19:01.823940 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 13:19:01.830725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 13:19:01.830811 ==
6852 13:19:01.830902 RX Vref Scan: 0
6853 13:19:01.830961
6854 13:19:01.833747 RX Vref 0 -> 0, step: 1
6855 13:19:01.833811
6856 13:19:01.837063 RX Delay -410 -> 252, step: 16
6857 13:19:01.840483 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6858 13:19:01.843909 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6859 13:19:01.850579 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6860 13:19:01.854323 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6861 13:19:01.857426 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6862 13:19:01.860470 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6863 13:19:01.867508 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6864 13:19:01.870834 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6865 13:19:01.874215 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6866 13:19:01.877525 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6867 13:19:01.883809 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6868 13:19:01.887198 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6869 13:19:01.890512 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6870 13:19:01.893964 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6871 13:19:01.900595 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6872 13:19:01.904387 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6873 13:19:01.904459 ==
6874 13:19:01.907426 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 13:19:01.911126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 13:19:01.911194 ==
6877 13:19:01.914156 DQS Delay:
6878 13:19:01.914222 DQS0 = 51, DQS1 = 59
6879 13:19:01.914275 DQM Delay:
6880 13:19:01.917598 DQM0 = 17, DQM1 = 20
6881 13:19:01.917664 DQ Delay:
6882 13:19:01.921037 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6883 13:19:01.924402 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6884 13:19:01.928068 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6885 13:19:01.930933 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6886 13:19:01.931010
6887 13:19:01.931086
6888 13:19:01.931157 ==
6889 13:19:01.934174 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 13:19:01.937545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 13:19:01.941114 ==
6892 13:19:01.941216
6893 13:19:01.941292
6894 13:19:01.941363 TX Vref Scan disable
6895 13:19:01.944643 == TX Byte 0 ==
6896 13:19:01.947984 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6897 13:19:01.950721 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6898 13:19:01.954268 == TX Byte 1 ==
6899 13:19:01.957750 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6900 13:19:01.960834 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6901 13:19:01.960911 ==
6902 13:19:01.964633 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 13:19:01.967639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 13:19:01.971406 ==
6905 13:19:01.971481
6906 13:19:01.971540
6907 13:19:01.971593 TX Vref Scan disable
6908 13:19:01.974146 == TX Byte 0 ==
6909 13:19:01.977737 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6910 13:19:01.980902 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6911 13:19:01.984492 == TX Byte 1 ==
6912 13:19:01.987449 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6913 13:19:01.991243 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6914 13:19:01.991318
6915 13:19:01.991410 [DATLAT]
6916 13:19:01.994540 Freq=400, CH1 RK1
6917 13:19:01.994614
6918 13:19:01.997357 DATLAT Default: 0xe
6919 13:19:01.997431 0, 0xFFFF, sum = 0
6920 13:19:02.000910 1, 0xFFFF, sum = 0
6921 13:19:02.000985 2, 0xFFFF, sum = 0
6922 13:19:02.004667 3, 0xFFFF, sum = 0
6923 13:19:02.004797 4, 0xFFFF, sum = 0
6924 13:19:02.007774 5, 0xFFFF, sum = 0
6925 13:19:02.007850 6, 0xFFFF, sum = 0
6926 13:19:02.010878 7, 0xFFFF, sum = 0
6927 13:19:02.010954 8, 0xFFFF, sum = 0
6928 13:19:02.013993 9, 0xFFFF, sum = 0
6929 13:19:02.014086 10, 0xFFFF, sum = 0
6930 13:19:02.017684 11, 0xFFFF, sum = 0
6931 13:19:02.017760 12, 0xFFFF, sum = 0
6932 13:19:02.020656 13, 0x0, sum = 1
6933 13:19:02.020731 14, 0x0, sum = 2
6934 13:19:02.024067 15, 0x0, sum = 3
6935 13:19:02.024143 16, 0x0, sum = 4
6936 13:19:02.027619 best_step = 14
6937 13:19:02.027692
6938 13:19:02.027749 ==
6939 13:19:02.031294 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 13:19:02.034231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 13:19:02.034325 ==
6942 13:19:02.037835 RX Vref Scan: 0
6943 13:19:02.037928
6944 13:19:02.038001 RX Vref 0 -> 0, step: 1
6945 13:19:02.038054
6946 13:19:02.040700 RX Delay -359 -> 252, step: 8
6947 13:19:02.048465 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6948 13:19:02.051887 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6949 13:19:02.055343 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6950 13:19:02.058592 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6951 13:19:02.065150 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6952 13:19:02.068302 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6953 13:19:02.071999 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6954 13:19:02.074972 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6955 13:19:02.081629 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6956 13:19:02.085393 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6957 13:19:02.088570 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6958 13:19:02.095297 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6959 13:19:02.098571 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6960 13:19:02.101689 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6961 13:19:02.105086 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6962 13:19:02.112153 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6963 13:19:02.112229 ==
6964 13:19:02.115312 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 13:19:02.118310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 13:19:02.118388 ==
6967 13:19:02.118465 DQS Delay:
6968 13:19:02.122036 DQS0 = 52, DQS1 = 56
6969 13:19:02.122110 DQM Delay:
6970 13:19:02.125024 DQM0 = 13, DQM1 = 8
6971 13:19:02.125128 DQ Delay:
6972 13:19:02.128668 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6973 13:19:02.131586 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6974 13:19:02.134968 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6975 13:19:02.138650 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6976 13:19:02.138725
6977 13:19:02.138800
6978 13:19:02.145361 [DQSOSCAuto] RK1, (LSB)MR18= 0x7e93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
6979 13:19:02.148348 CH1 RK1: MR19=C0C, MR18=7E93
6980 13:19:02.154938 CH1_RK1: MR19=0xC0C, MR18=0x7E93, DQSOSC=391, MR23=63, INC=386, DEC=257
6981 13:19:02.158530 [RxdqsGatingPostProcess] freq 400
6982 13:19:02.161991 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 13:19:02.165139 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 13:19:02.168568 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 13:19:02.172196 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 13:19:02.175241 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 13:19:02.178908 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 13:19:02.181916 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 13:19:02.185011 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 13:19:02.188605 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 13:19:02.191701 Pre-setting of DQS Precalculation
6992 13:19:02.195358 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 13:19:02.205485 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 13:19:02.212028 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 13:19:02.212104
6996 13:19:02.212167
6997 13:19:02.215765 [Calibration Summary] 800 Mbps
6998 13:19:02.215843 CH 0, Rank 0
6999 13:19:02.218516 SW Impedance : PASS
7000 13:19:02.218580 DUTY Scan : NO K
7001 13:19:02.222107 ZQ Calibration : PASS
7002 13:19:02.225220 Jitter Meter : NO K
7003 13:19:02.225284 CBT Training : PASS
7004 13:19:02.228956 Write leveling : PASS
7005 13:19:02.229058 RX DQS gating : PASS
7006 13:19:02.232328 RX DQ/DQS(RDDQC) : PASS
7007 13:19:02.235429 TX DQ/DQS : PASS
7008 13:19:02.235511 RX DATLAT : PASS
7009 13:19:02.238997 RX DQ/DQS(Engine): PASS
7010 13:19:02.241889 TX OE : NO K
7011 13:19:02.241955 All Pass.
7012 13:19:02.242010
7013 13:19:02.242061 CH 0, Rank 1
7014 13:19:02.245551 SW Impedance : PASS
7015 13:19:02.248682 DUTY Scan : NO K
7016 13:19:02.248743 ZQ Calibration : PASS
7017 13:19:02.252317 Jitter Meter : NO K
7018 13:19:02.255312 CBT Training : PASS
7019 13:19:02.255374 Write leveling : NO K
7020 13:19:02.258716 RX DQS gating : PASS
7021 13:19:02.261922 RX DQ/DQS(RDDQC) : PASS
7022 13:19:02.261991 TX DQ/DQS : PASS
7023 13:19:02.265742 RX DATLAT : PASS
7024 13:19:02.265812 RX DQ/DQS(Engine): PASS
7025 13:19:02.269026 TX OE : NO K
7026 13:19:02.269093 All Pass.
7027 13:19:02.269189
7028 13:19:02.272031 CH 1, Rank 0
7029 13:19:02.272110 SW Impedance : PASS
7030 13:19:02.275413 DUTY Scan : NO K
7031 13:19:02.278813 ZQ Calibration : PASS
7032 13:19:02.278888 Jitter Meter : NO K
7033 13:19:02.281967 CBT Training : PASS
7034 13:19:02.285853 Write leveling : PASS
7035 13:19:02.285927 RX DQS gating : PASS
7036 13:19:02.288810 RX DQ/DQS(RDDQC) : PASS
7037 13:19:02.292433 TX DQ/DQS : PASS
7038 13:19:02.292503 RX DATLAT : PASS
7039 13:19:02.295473 RX DQ/DQS(Engine): PASS
7040 13:19:02.298554 TX OE : NO K
7041 13:19:02.298635 All Pass.
7042 13:19:02.298694
7043 13:19:02.298783 CH 1, Rank 1
7044 13:19:02.302091 SW Impedance : PASS
7045 13:19:02.305783 DUTY Scan : NO K
7046 13:19:02.305846 ZQ Calibration : PASS
7047 13:19:02.308783 Jitter Meter : NO K
7048 13:19:02.308853 CBT Training : PASS
7049 13:19:02.311908 Write leveling : NO K
7050 13:19:02.315373 RX DQS gating : PASS
7051 13:19:02.315450 RX DQ/DQS(RDDQC) : PASS
7052 13:19:02.319050 TX DQ/DQS : PASS
7053 13:19:02.321996 RX DATLAT : PASS
7054 13:19:02.322071 RX DQ/DQS(Engine): PASS
7055 13:19:02.325301 TX OE : NO K
7056 13:19:02.325366 All Pass.
7057 13:19:02.325437
7058 13:19:02.328956 DramC Write-DBI off
7059 13:19:02.332275 PER_BANK_REFRESH: Hybrid Mode
7060 13:19:02.332343 TX_TRACKING: ON
7061 13:19:02.342423 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 13:19:02.345402 [FAST_K] Save calibration result to emmc
7063 13:19:02.348965 dramc_set_vcore_voltage set vcore to 725000
7064 13:19:02.352079 Read voltage for 1600, 0
7065 13:19:02.352161 Vio18 = 0
7066 13:19:02.352219 Vcore = 725000
7067 13:19:02.355656 Vdram = 0
7068 13:19:02.355722 Vddq = 0
7069 13:19:02.355791 Vmddr = 0
7070 13:19:02.362383 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 13:19:02.365795 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 13:19:02.369265 MEM_TYPE=3, freq_sel=13
7073 13:19:02.372559 sv_algorithm_assistance_LP4_3733
7074 13:19:02.375807 ============ PULL DRAM RESETB DOWN ============
7075 13:19:02.379231 ========== PULL DRAM RESETB DOWN end =========
7076 13:19:02.385366 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 13:19:02.389065 ===================================
7078 13:19:02.389175 LPDDR4 DRAM CONFIGURATION
7079 13:19:02.392190 ===================================
7080 13:19:02.395876 EX_ROW_EN[0] = 0x0
7081 13:19:02.398887 EX_ROW_EN[1] = 0x0
7082 13:19:02.398959 LP4Y_EN = 0x0
7083 13:19:02.402528 WORK_FSP = 0x1
7084 13:19:02.402595 WL = 0x5
7085 13:19:02.406064 RL = 0x5
7086 13:19:02.406127 BL = 0x2
7087 13:19:02.408969 RPST = 0x0
7088 13:19:02.409035 RD_PRE = 0x0
7089 13:19:02.412507 WR_PRE = 0x1
7090 13:19:02.412566 WR_PST = 0x1
7091 13:19:02.415638 DBI_WR = 0x0
7092 13:19:02.415719 DBI_RD = 0x0
7093 13:19:02.419327 OTF = 0x1
7094 13:19:02.422187 ===================================
7095 13:19:02.425844 ===================================
7096 13:19:02.425944 ANA top config
7097 13:19:02.428804 ===================================
7098 13:19:02.432371 DLL_ASYNC_EN = 0
7099 13:19:02.435682 ALL_SLAVE_EN = 0
7100 13:19:02.438901 NEW_RANK_MODE = 1
7101 13:19:02.438983 DLL_IDLE_MODE = 1
7102 13:19:02.442369 LP45_APHY_COMB_EN = 1
7103 13:19:02.445679 TX_ODT_DIS = 0
7104 13:19:02.449179 NEW_8X_MODE = 1
7105 13:19:02.452546 ===================================
7106 13:19:02.455590 ===================================
7107 13:19:02.455659 data_rate = 3200
7108 13:19:02.459287 CKR = 1
7109 13:19:02.462462 DQ_P2S_RATIO = 8
7110 13:19:02.466023 ===================================
7111 13:19:02.469089 CA_P2S_RATIO = 8
7112 13:19:02.472680 DQ_CA_OPEN = 0
7113 13:19:02.475993 DQ_SEMI_OPEN = 0
7114 13:19:02.476069 CA_SEMI_OPEN = 0
7115 13:19:02.479423 CA_FULL_RATE = 0
7116 13:19:02.482478 DQ_CKDIV4_EN = 0
7117 13:19:02.486093 CA_CKDIV4_EN = 0
7118 13:19:02.489400 CA_PREDIV_EN = 0
7119 13:19:02.489471 PH8_DLY = 12
7120 13:19:02.492969 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 13:19:02.495971 DQ_AAMCK_DIV = 4
7122 13:19:02.499652 CA_AAMCK_DIV = 4
7123 13:19:02.502802 CA_ADMCK_DIV = 4
7124 13:19:02.506210 DQ_TRACK_CA_EN = 0
7125 13:19:02.509085 CA_PICK = 1600
7126 13:19:02.509238 CA_MCKIO = 1600
7127 13:19:02.512813 MCKIO_SEMI = 0
7128 13:19:02.516344 PLL_FREQ = 3068
7129 13:19:02.519483 DQ_UI_PI_RATIO = 32
7130 13:19:02.522493 CA_UI_PI_RATIO = 0
7131 13:19:02.526054 ===================================
7132 13:19:02.529648 ===================================
7133 13:19:02.529752 memory_type:LPDDR4
7134 13:19:02.532803 GP_NUM : 10
7135 13:19:02.536295 SRAM_EN : 1
7136 13:19:02.536389 MD32_EN : 0
7137 13:19:02.539324 ===================================
7138 13:19:02.542873 [ANA_INIT] >>>>>>>>>>>>>>
7139 13:19:02.546246 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 13:19:02.549471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 13:19:02.552712 ===================================
7142 13:19:02.555863 data_rate = 3200,PCW = 0X7600
7143 13:19:02.559242 ===================================
7144 13:19:02.562991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 13:19:02.565969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 13:19:02.573102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 13:19:02.575918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 13:19:02.579422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 13:19:02.582831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 13:19:02.586322 [ANA_INIT] flow start
7151 13:19:02.589410 [ANA_INIT] PLL >>>>>>>>
7152 13:19:02.589490 [ANA_INIT] PLL <<<<<<<<
7153 13:19:02.592921 [ANA_INIT] MIDPI >>>>>>>>
7154 13:19:02.595937 [ANA_INIT] MIDPI <<<<<<<<
7155 13:19:02.599495 [ANA_INIT] DLL >>>>>>>>
7156 13:19:02.599594 [ANA_INIT] DLL <<<<<<<<
7157 13:19:02.603033 [ANA_INIT] flow end
7158 13:19:02.606111 ============ LP4 DIFF to SE enter ============
7159 13:19:02.609723 ============ LP4 DIFF to SE exit ============
7160 13:19:02.612602 [ANA_INIT] <<<<<<<<<<<<<
7161 13:19:02.616143 [Flow] Enable top DCM control >>>>>
7162 13:19:02.619365 [Flow] Enable top DCM control <<<<<
7163 13:19:02.622937 Enable DLL master slave shuffle
7164 13:19:02.629440 ==============================================================
7165 13:19:02.629507 Gating Mode config
7166 13:19:02.636148 ==============================================================
7167 13:19:02.636245 Config description:
7168 13:19:02.645894 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 13:19:02.653110 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 13:19:02.659365 SELPH_MODE 0: By rank 1: By Phase
7171 13:19:02.662707 ==============================================================
7172 13:19:02.666144 GAT_TRACK_EN = 1
7173 13:19:02.669456 RX_GATING_MODE = 2
7174 13:19:02.672747 RX_GATING_TRACK_MODE = 2
7175 13:19:02.676350 SELPH_MODE = 1
7176 13:19:02.679426 PICG_EARLY_EN = 1
7177 13:19:02.682795 VALID_LAT_VALUE = 1
7178 13:19:02.686197 ==============================================================
7179 13:19:02.689572 Enter into Gating configuration >>>>
7180 13:19:02.693104 Exit from Gating configuration <<<<
7181 13:19:02.696194 Enter into DVFS_PRE_config >>>>>
7182 13:19:02.709571 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 13:19:02.709653 Exit from DVFS_PRE_config <<<<<
7184 13:19:02.712878 Enter into PICG configuration >>>>
7185 13:19:02.716287 Exit from PICG configuration <<<<
7186 13:19:02.719713 [RX_INPUT] configuration >>>>>
7187 13:19:02.722747 [RX_INPUT] configuration <<<<<
7188 13:19:02.729667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 13:19:02.732934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 13:19:02.739527 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 13:19:02.746362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 13:19:02.752906 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 13:19:02.759696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 13:19:02.762675 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 13:19:02.766101 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 13:19:02.769366 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 13:19:02.776550 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 13:19:02.779739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 13:19:02.782981 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 13:19:02.786367 ===================================
7201 13:19:02.789807 LPDDR4 DRAM CONFIGURATION
7202 13:19:02.793330 ===================================
7203 13:19:02.793436 EX_ROW_EN[0] = 0x0
7204 13:19:02.796038 EX_ROW_EN[1] = 0x0
7205 13:19:02.796139 LP4Y_EN = 0x0
7206 13:19:02.799526 WORK_FSP = 0x1
7207 13:19:02.799621 WL = 0x5
7208 13:19:02.803070 RL = 0x5
7209 13:19:02.806097 BL = 0x2
7210 13:19:02.806164 RPST = 0x0
7211 13:19:02.809645 RD_PRE = 0x0
7212 13:19:02.809712 WR_PRE = 0x1
7213 13:19:02.813105 WR_PST = 0x1
7214 13:19:02.813219 DBI_WR = 0x0
7215 13:19:02.816136 DBI_RD = 0x0
7216 13:19:02.816231 OTF = 0x1
7217 13:19:02.819770 ===================================
7218 13:19:02.823170 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 13:19:02.829499 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 13:19:02.833088 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 13:19:02.836442 ===================================
7222 13:19:02.839564 LPDDR4 DRAM CONFIGURATION
7223 13:19:02.843197 ===================================
7224 13:19:02.843305 EX_ROW_EN[0] = 0x10
7225 13:19:02.846116 EX_ROW_EN[1] = 0x0
7226 13:19:02.846185 LP4Y_EN = 0x0
7227 13:19:02.849801 WORK_FSP = 0x1
7228 13:19:02.849879 WL = 0x5
7229 13:19:02.852884 RL = 0x5
7230 13:19:02.852977 BL = 0x2
7231 13:19:02.856644 RPST = 0x0
7232 13:19:02.856747 RD_PRE = 0x0
7233 13:19:02.859695 WR_PRE = 0x1
7234 13:19:02.859768 WR_PST = 0x1
7235 13:19:02.863273 DBI_WR = 0x0
7236 13:19:02.863399 DBI_RD = 0x0
7237 13:19:02.866355 OTF = 0x1
7238 13:19:02.869918 ===================================
7239 13:19:02.876668 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 13:19:02.876803 ==
7241 13:19:02.880132 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 13:19:02.883032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 13:19:02.883137 ==
7244 13:19:02.886524 [Duty_Offset_Calibration]
7245 13:19:02.886608 B0:2 B1:-1 CA:1
7246 13:19:02.886665
7247 13:19:02.889523 [DutyScan_Calibration_Flow] k_type=0
7248 13:19:02.899907
7249 13:19:02.900042 ==CLK 0==
7250 13:19:02.902950 Final CLK duty delay cell = -4
7251 13:19:02.906465 [-4] MAX Duty = 5000%(X100), DQS PI = 10
7252 13:19:02.909540 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7253 13:19:02.912985 [-4] AVG Duty = 4922%(X100)
7254 13:19:02.913069
7255 13:19:02.916520 CH0 CLK Duty spec in!! Max-Min= 156%
7256 13:19:02.919937 [DutyScan_Calibration_Flow] ====Done====
7257 13:19:02.920038
7258 13:19:02.922996 [DutyScan_Calibration_Flow] k_type=1
7259 13:19:02.939137
7260 13:19:02.939281 ==DQS 0 ==
7261 13:19:02.942693 Final DQS duty delay cell = 0
7262 13:19:02.945793 [0] MAX Duty = 5125%(X100), DQS PI = 20
7263 13:19:02.949576 [0] MIN Duty = 5000%(X100), DQS PI = 14
7264 13:19:02.952714 [0] AVG Duty = 5062%(X100)
7265 13:19:02.952814
7266 13:19:02.952896 ==DQS 1 ==
7267 13:19:02.956305 Final DQS duty delay cell = -4
7268 13:19:02.959348 [-4] MAX Duty = 5093%(X100), DQS PI = 2
7269 13:19:02.962326 [-4] MIN Duty = 5000%(X100), DQS PI = 24
7270 13:19:02.966033 [-4] AVG Duty = 5046%(X100)
7271 13:19:02.966165
7272 13:19:02.969615 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7273 13:19:02.969695
7274 13:19:02.972758 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7275 13:19:02.975726 [DutyScan_Calibration_Flow] ====Done====
7276 13:19:02.975810
7277 13:19:02.979211 [DutyScan_Calibration_Flow] k_type=3
7278 13:19:02.996630
7279 13:19:02.996758 ==DQM 0 ==
7280 13:19:03.000120 Final DQM duty delay cell = 0
7281 13:19:03.003662 [0] MAX Duty = 5000%(X100), DQS PI = 20
7282 13:19:03.006688 [0] MIN Duty = 4875%(X100), DQS PI = 4
7283 13:19:03.006773 [0] AVG Duty = 4937%(X100)
7284 13:19:03.009712
7285 13:19:03.009810 ==DQM 1 ==
7286 13:19:03.013671 Final DQM duty delay cell = 0
7287 13:19:03.016508 [0] MAX Duty = 5187%(X100), DQS PI = 58
7288 13:19:03.019716 [0] MIN Duty = 4969%(X100), DQS PI = 18
7289 13:19:03.023487 [0] AVG Duty = 5078%(X100)
7290 13:19:03.023572
7291 13:19:03.026537 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7292 13:19:03.026619
7293 13:19:03.029952 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7294 13:19:03.033670 [DutyScan_Calibration_Flow] ====Done====
7295 13:19:03.033768
7296 13:19:03.036623 [DutyScan_Calibration_Flow] k_type=2
7297 13:19:03.054132
7298 13:19:03.054228 ==DQ 0 ==
7299 13:19:03.057052 Final DQ duty delay cell = 0
7300 13:19:03.060229 [0] MAX Duty = 5156%(X100), DQS PI = 0
7301 13:19:03.063964 [0] MIN Duty = 5031%(X100), DQS PI = 12
7302 13:19:03.064040 [0] AVG Duty = 5093%(X100)
7303 13:19:03.064099
7304 13:19:03.066904 ==DQ 1 ==
7305 13:19:03.070593 Final DQ duty delay cell = 0
7306 13:19:03.073679 [0] MAX Duty = 5031%(X100), DQS PI = 30
7307 13:19:03.077276 [0] MIN Duty = 4907%(X100), DQS PI = 18
7308 13:19:03.077415 [0] AVG Duty = 4969%(X100)
7309 13:19:03.077522
7310 13:19:03.080418 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7311 13:19:03.080499
7312 13:19:03.083794 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7313 13:19:03.090332 [DutyScan_Calibration_Flow] ====Done====
7314 13:19:03.090452 ==
7315 13:19:03.094455 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 13:19:03.097236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 13:19:03.097335 ==
7318 13:19:03.100687 [Duty_Offset_Calibration]
7319 13:19:03.100767 B0:1 B1:1 CA:2
7320 13:19:03.100825
7321 13:19:03.104183 [DutyScan_Calibration_Flow] k_type=0
7322 13:19:03.113719
7323 13:19:03.113830 ==CLK 0==
7324 13:19:03.117071 Final CLK duty delay cell = 0
7325 13:19:03.120753 [0] MAX Duty = 5156%(X100), DQS PI = 24
7326 13:19:03.124231 [0] MIN Duty = 4938%(X100), DQS PI = 50
7327 13:19:03.124319 [0] AVG Duty = 5047%(X100)
7328 13:19:03.124378
7329 13:19:03.127178 CH1 CLK Duty spec in!! Max-Min= 218%
7330 13:19:03.133998 [DutyScan_Calibration_Flow] ====Done====
7331 13:19:03.134104
7332 13:19:03.137132 [DutyScan_Calibration_Flow] k_type=1
7333 13:19:03.153722
7334 13:19:03.153847 ==DQS 0 ==
7335 13:19:03.156628 Final DQS duty delay cell = 0
7336 13:19:03.160302 [0] MAX Duty = 5062%(X100), DQS PI = 20
7337 13:19:03.163867 [0] MIN Duty = 4813%(X100), DQS PI = 52
7338 13:19:03.163945 [0] AVG Duty = 4937%(X100)
7339 13:19:03.166987
7340 13:19:03.167052 ==DQS 1 ==
7341 13:19:03.170522 Final DQS duty delay cell = 0
7342 13:19:03.173524 [0] MAX Duty = 5031%(X100), DQS PI = 34
7343 13:19:03.177028 [0] MIN Duty = 4938%(X100), DQS PI = 14
7344 13:19:03.177155 [0] AVG Duty = 4984%(X100)
7345 13:19:03.180662
7346 13:19:03.183712 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7347 13:19:03.183793
7348 13:19:03.187450 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7349 13:19:03.190458 [DutyScan_Calibration_Flow] ====Done====
7350 13:19:03.190535
7351 13:19:03.193473 [DutyScan_Calibration_Flow] k_type=3
7352 13:19:03.210580
7353 13:19:03.210700 ==DQM 0 ==
7354 13:19:03.214063 Final DQM duty delay cell = 0
7355 13:19:03.217023 [0] MAX Duty = 5124%(X100), DQS PI = 18
7356 13:19:03.220624 [0] MIN Duty = 4813%(X100), DQS PI = 52
7357 13:19:03.220722 [0] AVG Duty = 4968%(X100)
7358 13:19:03.220783
7359 13:19:03.224130 ==DQM 1 ==
7360 13:19:03.227545 Final DQM duty delay cell = 0
7361 13:19:03.230752 [0] MAX Duty = 5156%(X100), DQS PI = 60
7362 13:19:03.234343 [0] MIN Duty = 4907%(X100), DQS PI = 18
7363 13:19:03.234426 [0] AVG Duty = 5031%(X100)
7364 13:19:03.234488
7365 13:19:03.240566 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7366 13:19:03.240654
7367 13:19:03.244106 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7368 13:19:03.247526 [DutyScan_Calibration_Flow] ====Done====
7369 13:19:03.247604
7370 13:19:03.250391 [DutyScan_Calibration_Flow] k_type=2
7371 13:19:03.267606
7372 13:19:03.267731 ==DQ 0 ==
7373 13:19:03.270500 Final DQ duty delay cell = 0
7374 13:19:03.273664 [0] MAX Duty = 5125%(X100), DQS PI = 20
7375 13:19:03.277427 [0] MIN Duty = 4907%(X100), DQS PI = 52
7376 13:19:03.277515 [0] AVG Duty = 5016%(X100)
7377 13:19:03.277595
7378 13:19:03.280977 ==DQ 1 ==
7379 13:19:03.284183 Final DQ duty delay cell = 0
7380 13:19:03.287053 [0] MAX Duty = 5093%(X100), DQS PI = 6
7381 13:19:03.290627 [0] MIN Duty = 5031%(X100), DQS PI = 0
7382 13:19:03.290713 [0] AVG Duty = 5062%(X100)
7383 13:19:03.290771
7384 13:19:03.293803 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7385 13:19:03.293882
7386 13:19:03.297610 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7387 13:19:03.303716 [DutyScan_Calibration_Flow] ====Done====
7388 13:19:03.307131 nWR fixed to 30
7389 13:19:03.307228 [ModeRegInit_LP4] CH0 RK0
7390 13:19:03.310521 [ModeRegInit_LP4] CH0 RK1
7391 13:19:03.313857 [ModeRegInit_LP4] CH1 RK0
7392 13:19:03.313953 [ModeRegInit_LP4] CH1 RK1
7393 13:19:03.317042 match AC timing 5
7394 13:19:03.320359 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 13:19:03.324087 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 13:19:03.330736 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 13:19:03.333756 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 13:19:03.340516 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 13:19:03.340625 [MiockJmeterHQA]
7400 13:19:03.340685
7401 13:19:03.344094 [DramcMiockJmeter] u1RxGatingPI = 0
7402 13:19:03.344171 0 : 4257, 4029
7403 13:19:03.347030 4 : 4258, 4029
7404 13:19:03.347102 8 : 4257, 4032
7405 13:19:03.350724 12 : 4258, 4029
7406 13:19:03.350795 16 : 4365, 4140
7407 13:19:03.354134 20 : 4368, 4140
7408 13:19:03.354202 24 : 4257, 4029
7409 13:19:03.357270 28 : 4252, 4027
7410 13:19:03.357337 32 : 4255, 4029
7411 13:19:03.357390 36 : 4258, 4029
7412 13:19:03.360558 40 : 4253, 4026
7413 13:19:03.360623 44 : 4363, 4138
7414 13:19:03.364114 48 : 4258, 4029
7415 13:19:03.364187 52 : 4252, 4027
7416 13:19:03.367032 56 : 4253, 4026
7417 13:19:03.367100 60 : 4370, 4145
7418 13:19:03.367156 64 : 4361, 4137
7419 13:19:03.370399 68 : 4366, 4140
7420 13:19:03.370465 72 : 4253, 4029
7421 13:19:03.373758 76 : 4255, 4029
7422 13:19:03.373842 80 : 4250, 4027
7423 13:19:03.376987 84 : 4249, 4027
7424 13:19:03.377070 88 : 4257, 4034
7425 13:19:03.380583 92 : 4250, 4027
7426 13:19:03.380656 96 : 4250, 3364
7427 13:19:03.380733 100 : 4250, 0
7428 13:19:03.383712 104 : 4363, 0
7429 13:19:03.383785 108 : 4252, 0
7430 13:19:03.387356 112 : 4361, 0
7431 13:19:03.387429 116 : 4252, 0
7432 13:19:03.387506 120 : 4250, 0
7433 13:19:03.390271 124 : 4250, 0
7434 13:19:03.390357 128 : 4250, 0
7435 13:19:03.390429 132 : 4255, 0
7436 13:19:03.394012 136 : 4250, 0
7437 13:19:03.394085 140 : 4255, 0
7438 13:19:03.397066 144 : 4255, 0
7439 13:19:03.397175 148 : 4363, 0
7440 13:19:03.397251 152 : 4249, 0
7441 13:19:03.400790 156 : 4252, 0
7442 13:19:03.400859 160 : 4250, 0
7443 13:19:03.403806 164 : 4252, 0
7444 13:19:03.403876 168 : 4252, 0
7445 13:19:03.403949 172 : 4250, 0
7446 13:19:03.407818 176 : 4363, 0
7447 13:19:03.407918 180 : 4255, 0
7448 13:19:03.410566 184 : 4250, 0
7449 13:19:03.410647 188 : 4250, 0
7450 13:19:03.410707 192 : 4363, 0
7451 13:19:03.414048 196 : 4253, 0
7452 13:19:03.414137 200 : 4250, 0
7453 13:19:03.414198 204 : 4255, 0
7454 13:19:03.416999 208 : 4250, 0
7455 13:19:03.417077 212 : 4253, 103
7456 13:19:03.420297 216 : 4250, 3817
7457 13:19:03.420414 220 : 4255, 4029
7458 13:19:03.423624 224 : 4250, 4027
7459 13:19:03.423703 228 : 4253, 4026
7460 13:19:03.427002 232 : 4250, 4027
7461 13:19:03.427083 236 : 4253, 4029
7462 13:19:03.430503 240 : 4250, 4027
7463 13:19:03.430586 244 : 4253, 4029
7464 13:19:03.430647 248 : 4250, 4027
7465 13:19:03.434181 252 : 4257, 4034
7466 13:19:03.434263 256 : 4250, 4027
7467 13:19:03.437043 260 : 4250, 4027
7468 13:19:03.437152 264 : 4252, 4029
7469 13:19:03.440547 268 : 4252, 4029
7470 13:19:03.440627 272 : 4368, 4145
7471 13:19:03.444062 276 : 4250, 4027
7472 13:19:03.444149 280 : 4250, 4026
7473 13:19:03.447414 284 : 4360, 4138
7474 13:19:03.447496 288 : 4255, 4029
7475 13:19:03.450779 292 : 4255, 4029
7476 13:19:03.450864 296 : 4250, 4026
7477 13:19:03.453720 300 : 4255, 4029
7478 13:19:03.453802 304 : 4255, 4032
7479 13:19:03.453862 308 : 4255, 4029
7480 13:19:03.457409 312 : 4250, 4027
7481 13:19:03.457491 316 : 4252, 4029
7482 13:19:03.460360 320 : 4250, 4027
7483 13:19:03.460440 324 : 4250, 4027
7484 13:19:03.463704 328 : 4363, 4140
7485 13:19:03.463787 332 : 4250, 3130
7486 13:19:03.467429 336 : 4252, 63
7487 13:19:03.467514
7488 13:19:03.467573 MIOCK jitter meter ch=0
7489 13:19:03.467626
7490 13:19:03.470417 1T = (336-100) = 236 dly cells
7491 13:19:03.476934 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7492 13:19:03.477047 ==
7493 13:19:03.480369 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 13:19:03.483780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 13:19:03.483874 ==
7496 13:19:03.490510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 13:19:03.493664 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 13:19:03.497341 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 13:19:03.504096 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 13:19:03.513814 [CA 0] Center 44 (14~75) winsize 62
7501 13:19:03.517377 [CA 1] Center 44 (13~75) winsize 63
7502 13:19:03.520234 [CA 2] Center 40 (11~69) winsize 59
7503 13:19:03.523823 [CA 3] Center 39 (10~69) winsize 60
7504 13:19:03.527029 [CA 4] Center 38 (8~68) winsize 61
7505 13:19:03.530487 [CA 5] Center 37 (7~67) winsize 61
7506 13:19:03.530558
7507 13:19:03.533784 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 13:19:03.533852
7509 13:19:03.536793 [CATrainingPosCal] consider 1 rank data
7510 13:19:03.540458 u2DelayCellTimex100 = 275/100 ps
7511 13:19:03.543864 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7512 13:19:03.550939 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7513 13:19:03.553491 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7514 13:19:03.556702 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7515 13:19:03.560111 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7516 13:19:03.563683 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7517 13:19:03.563758
7518 13:19:03.567130 CA PerBit enable=1, Macro0, CA PI delay=37
7519 13:19:03.567313
7520 13:19:03.570491 [CBTSetCACLKResult] CA Dly = 37
7521 13:19:03.573717 CS Dly: 11 (0~42)
7522 13:19:03.577133 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 13:19:03.580125 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 13:19:03.580202 ==
7525 13:19:03.583704 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 13:19:03.587080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 13:19:03.590064 ==
7528 13:19:03.593548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 13:19:03.596836 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 13:19:03.603444 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 13:19:03.609970 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 13:19:03.617457 [CA 0] Center 44 (14~75) winsize 62
7533 13:19:03.621058 [CA 1] Center 44 (14~75) winsize 62
7534 13:19:03.624197 [CA 2] Center 40 (11~69) winsize 59
7535 13:19:03.627769 [CA 3] Center 39 (10~69) winsize 60
7536 13:19:03.630800 [CA 4] Center 37 (8~67) winsize 60
7537 13:19:03.634057 [CA 5] Center 37 (7~67) winsize 61
7538 13:19:03.634136
7539 13:19:03.637401 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 13:19:03.637485
7541 13:19:03.640859 [CATrainingPosCal] consider 2 rank data
7542 13:19:03.644457 u2DelayCellTimex100 = 275/100 ps
7543 13:19:03.647360 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7544 13:19:03.654059 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7545 13:19:03.657822 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7546 13:19:03.660755 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7547 13:19:03.664129 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7548 13:19:03.667556 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7549 13:19:03.667668
7550 13:19:03.670723 CA PerBit enable=1, Macro0, CA PI delay=37
7551 13:19:03.670887
7552 13:19:03.673882 [CBTSetCACLKResult] CA Dly = 37
7553 13:19:03.677423 CS Dly: 12 (0~44)
7554 13:19:03.680716 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 13:19:03.684389 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 13:19:03.684474
7557 13:19:03.687480 ----->DramcWriteLeveling(PI) begin...
7558 13:19:03.687584 ==
7559 13:19:03.690969 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 13:19:03.697858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 13:19:03.697954 ==
7562 13:19:03.700733 Write leveling (Byte 0): 33 => 33
7563 13:19:03.700811 Write leveling (Byte 1): 28 => 28
7564 13:19:03.704167 DramcWriteLeveling(PI) end<-----
7565 13:19:03.704245
7566 13:19:03.704305 ==
7567 13:19:03.707610 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 13:19:03.714549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 13:19:03.714629 ==
7570 13:19:03.717430 [Gating] SW mode calibration
7571 13:19:03.724066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 13:19:03.727629 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 13:19:03.734378 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 13:19:03.737267 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 13:19:03.740521 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 13:19:03.747308 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 13:19:03.750791 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7578 13:19:03.753729 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7579 13:19:03.760351 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7580 13:19:03.763937 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 13:19:03.766997 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 13:19:03.773637 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 13:19:03.777335 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 13:19:03.780839 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7585 13:19:03.784107 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7586 13:19:03.790488 1 5 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 1)
7587 13:19:03.794199 1 5 24 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7588 13:19:03.797144 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 13:19:03.804167 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 13:19:03.807171 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 13:19:03.810193 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 13:19:03.816969 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 13:19:03.820579 1 6 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7594 13:19:03.823619 1 6 20 | B1->B0 | 2e2d 4646 | 1 0 | (1 1) (0 0)
7595 13:19:03.830305 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7596 13:19:03.834128 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 13:19:03.837072 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 13:19:03.843689 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 13:19:03.847132 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 13:19:03.850593 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 13:19:03.857134 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 13:19:03.860793 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7603 13:19:03.863945 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 13:19:03.870596 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 13:19:03.874211 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 13:19:03.877391 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 13:19:03.880426 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 13:19:03.887451 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 13:19:03.890422 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 13:19:03.894329 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 13:19:03.900970 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 13:19:03.903949 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 13:19:03.907499 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 13:19:03.914363 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 13:19:03.917295 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 13:19:03.920723 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 13:19:03.927514 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7618 13:19:03.930636 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7619 13:19:03.934068 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 13:19:03.937235 Total UI for P1: 0, mck2ui 16
7621 13:19:03.940817 best dqsien dly found for B0: ( 1, 9, 18)
7622 13:19:03.943954 Total UI for P1: 0, mck2ui 16
7623 13:19:03.947577 best dqsien dly found for B1: ( 1, 9, 18)
7624 13:19:03.950486 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7625 13:19:03.953999 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7626 13:19:03.954071
7627 13:19:03.957471 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7628 13:19:03.964104 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7629 13:19:03.964174 [Gating] SW calibration Done
7630 13:19:03.967557 ==
7631 13:19:03.967629 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 13:19:03.973705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 13:19:03.973787 ==
7634 13:19:03.973847 RX Vref Scan: 0
7635 13:19:03.973902
7636 13:19:03.977564 RX Vref 0 -> 0, step: 1
7637 13:19:03.977629
7638 13:19:03.980700 RX Delay 0 -> 252, step: 8
7639 13:19:03.983799 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7640 13:19:03.987508 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7641 13:19:03.990510 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7642 13:19:03.997235 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7643 13:19:04.000508 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7644 13:19:04.003993 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7645 13:19:04.007170 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7646 13:19:04.010664 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7647 13:19:04.013672 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7648 13:19:04.020500 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7649 13:19:04.024050 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7650 13:19:04.027117 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7651 13:19:04.030443 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7652 13:19:04.036982 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7653 13:19:04.040657 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7654 13:19:04.044291 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7655 13:19:04.044368 ==
7656 13:19:04.047347 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 13:19:04.050480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 13:19:04.050573 ==
7659 13:19:04.054039 DQS Delay:
7660 13:19:04.054107 DQS0 = 0, DQS1 = 0
7661 13:19:04.054184 DQM Delay:
7662 13:19:04.057501 DQM0 = 132, DQM1 = 125
7663 13:19:04.057568 DQ Delay:
7664 13:19:04.060659 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7665 13:19:04.063737 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7666 13:19:04.067472 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7667 13:19:04.074144 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7668 13:19:04.074237
7669 13:19:04.074297
7670 13:19:04.074353 ==
7671 13:19:04.077597 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 13:19:04.080614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 13:19:04.080704 ==
7674 13:19:04.080785
7675 13:19:04.080876
7676 13:19:04.083977 TX Vref Scan disable
7677 13:19:04.084066 == TX Byte 0 ==
7678 13:19:04.090695 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7679 13:19:04.094400 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7680 13:19:04.094478 == TX Byte 1 ==
7681 13:19:04.100904 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7682 13:19:04.103969 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7683 13:19:04.104058 ==
7684 13:19:04.107614 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 13:19:04.110751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 13:19:04.110846 ==
7687 13:19:04.126689
7688 13:19:04.129934 TX Vref early break, caculate TX vref
7689 13:19:04.133283 TX Vref=16, minBit 1, minWin=21, winSum=367
7690 13:19:04.136290 TX Vref=18, minBit 1, minWin=22, winSum=374
7691 13:19:04.139776 TX Vref=20, minBit 1, minWin=23, winSum=385
7692 13:19:04.143270 TX Vref=22, minBit 0, minWin=24, winSum=395
7693 13:19:04.146294 TX Vref=24, minBit 0, minWin=25, winSum=407
7694 13:19:04.152912 TX Vref=26, minBit 0, minWin=24, winSum=418
7695 13:19:04.156550 TX Vref=28, minBit 3, minWin=25, winSum=422
7696 13:19:04.159682 TX Vref=30, minBit 0, minWin=25, winSum=420
7697 13:19:04.163203 TX Vref=32, minBit 0, minWin=25, winSum=414
7698 13:19:04.166875 TX Vref=34, minBit 0, minWin=24, winSum=403
7699 13:19:04.169463 TX Vref=36, minBit 4, minWin=23, winSum=393
7700 13:19:04.176129 [TxChooseVref] Worse bit 3, Min win 25, Win sum 422, Final Vref 28
7701 13:19:04.176234
7702 13:19:04.179945 Final TX Range 0 Vref 28
7703 13:19:04.180024
7704 13:19:04.180082 ==
7705 13:19:04.182841 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 13:19:04.186195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 13:19:04.186263 ==
7708 13:19:04.186318
7709 13:19:04.186375
7710 13:19:04.189710 TX Vref Scan disable
7711 13:19:04.196276 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7712 13:19:04.196356 == TX Byte 0 ==
7713 13:19:04.200021 u2DelayCellOfst[0]=17 cells (5 PI)
7714 13:19:04.203048 u2DelayCellOfst[1]=21 cells (6 PI)
7715 13:19:04.206245 u2DelayCellOfst[2]=14 cells (4 PI)
7716 13:19:04.209919 u2DelayCellOfst[3]=14 cells (4 PI)
7717 13:19:04.213045 u2DelayCellOfst[4]=10 cells (3 PI)
7718 13:19:04.216221 u2DelayCellOfst[5]=0 cells (0 PI)
7719 13:19:04.219829 u2DelayCellOfst[6]=21 cells (6 PI)
7720 13:19:04.223363 u2DelayCellOfst[7]=21 cells (6 PI)
7721 13:19:04.226733 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7722 13:19:04.229976 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7723 13:19:04.233394 == TX Byte 1 ==
7724 13:19:04.233471 u2DelayCellOfst[8]=0 cells (0 PI)
7725 13:19:04.236586 u2DelayCellOfst[9]=0 cells (0 PI)
7726 13:19:04.240088 u2DelayCellOfst[10]=7 cells (2 PI)
7727 13:19:04.243067 u2DelayCellOfst[11]=3 cells (1 PI)
7728 13:19:04.246674 u2DelayCellOfst[12]=14 cells (4 PI)
7729 13:19:04.249755 u2DelayCellOfst[13]=14 cells (4 PI)
7730 13:19:04.253049 u2DelayCellOfst[14]=14 cells (4 PI)
7731 13:19:04.256661 u2DelayCellOfst[15]=10 cells (3 PI)
7732 13:19:04.259658 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7733 13:19:04.266483 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7734 13:19:04.266550 DramC Write-DBI on
7735 13:19:04.266606 ==
7736 13:19:04.270074 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 13:19:04.273058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 13:19:04.273168 ==
7739 13:19:04.276727
7740 13:19:04.276796
7741 13:19:04.276858 TX Vref Scan disable
7742 13:19:04.279787 == TX Byte 0 ==
7743 13:19:04.283416 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7744 13:19:04.286183 == TX Byte 1 ==
7745 13:19:04.289575 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7746 13:19:04.292875 DramC Write-DBI off
7747 13:19:04.292941
7748 13:19:04.292995 [DATLAT]
7749 13:19:04.293047 Freq=1600, CH0 RK0
7750 13:19:04.293098
7751 13:19:04.296575 DATLAT Default: 0xf
7752 13:19:04.296634 0, 0xFFFF, sum = 0
7753 13:19:04.300041 1, 0xFFFF, sum = 0
7754 13:19:04.300120 2, 0xFFFF, sum = 0
7755 13:19:04.303026 3, 0xFFFF, sum = 0
7756 13:19:04.306736 4, 0xFFFF, sum = 0
7757 13:19:04.306812 5, 0xFFFF, sum = 0
7758 13:19:04.309803 6, 0xFFFF, sum = 0
7759 13:19:04.309875 7, 0xFFFF, sum = 0
7760 13:19:04.313413 8, 0xFFFF, sum = 0
7761 13:19:04.313477 9, 0xFFFF, sum = 0
7762 13:19:04.316483 10, 0xFFFF, sum = 0
7763 13:19:04.316547 11, 0xFFFF, sum = 0
7764 13:19:04.320138 12, 0xFFFF, sum = 0
7765 13:19:04.320206 13, 0xFFFF, sum = 0
7766 13:19:04.323148 14, 0x0, sum = 1
7767 13:19:04.323215 15, 0x0, sum = 2
7768 13:19:04.326372 16, 0x0, sum = 3
7769 13:19:04.326432 17, 0x0, sum = 4
7770 13:19:04.330068 best_step = 15
7771 13:19:04.330131
7772 13:19:04.330182 ==
7773 13:19:04.333165 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 13:19:04.336575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 13:19:04.336639 ==
7776 13:19:04.336691 RX Vref Scan: 1
7777 13:19:04.336740
7778 13:19:04.339937 Set Vref Range= 24 -> 127
7779 13:19:04.339995
7780 13:19:04.343227 RX Vref 24 -> 127, step: 1
7781 13:19:04.343285
7782 13:19:04.346484 RX Delay 11 -> 252, step: 4
7783 13:19:04.346552
7784 13:19:04.350151 Set Vref, RX VrefLevel [Byte0]: 24
7785 13:19:04.353189 [Byte1]: 24
7786 13:19:04.353325
7787 13:19:04.356470 Set Vref, RX VrefLevel [Byte0]: 25
7788 13:19:04.359677 [Byte1]: 25
7789 13:19:04.359737
7790 13:19:04.363582 Set Vref, RX VrefLevel [Byte0]: 26
7791 13:19:04.366983 [Byte1]: 26
7792 13:19:04.370590
7793 13:19:04.370652 Set Vref, RX VrefLevel [Byte0]: 27
7794 13:19:04.373682 [Byte1]: 27
7795 13:19:04.377845
7796 13:19:04.377933 Set Vref, RX VrefLevel [Byte0]: 28
7797 13:19:04.381171 [Byte1]: 28
7798 13:19:04.385381
7799 13:19:04.385472 Set Vref, RX VrefLevel [Byte0]: 29
7800 13:19:04.388688 [Byte1]: 29
7801 13:19:04.392872
7802 13:19:04.392958 Set Vref, RX VrefLevel [Byte0]: 30
7803 13:19:04.396519 [Byte1]: 30
7804 13:19:04.400865
7805 13:19:04.400967 Set Vref, RX VrefLevel [Byte0]: 31
7806 13:19:04.404246 [Byte1]: 31
7807 13:19:04.408635
7808 13:19:04.408738 Set Vref, RX VrefLevel [Byte0]: 32
7809 13:19:04.411724 [Byte1]: 32
7810 13:19:04.415863
7811 13:19:04.415945 Set Vref, RX VrefLevel [Byte0]: 33
7812 13:19:04.419562 [Byte1]: 33
7813 13:19:04.423780
7814 13:19:04.423851 Set Vref, RX VrefLevel [Byte0]: 34
7815 13:19:04.426818 [Byte1]: 34
7816 13:19:04.431170
7817 13:19:04.431233 Set Vref, RX VrefLevel [Byte0]: 35
7818 13:19:04.434334 [Byte1]: 35
7819 13:19:04.438550
7820 13:19:04.438613 Set Vref, RX VrefLevel [Byte0]: 36
7821 13:19:04.442108 [Byte1]: 36
7822 13:19:04.446376
7823 13:19:04.446438 Set Vref, RX VrefLevel [Byte0]: 37
7824 13:19:04.449441 [Byte1]: 37
7825 13:19:04.454159
7826 13:19:04.454220 Set Vref, RX VrefLevel [Byte0]: 38
7827 13:19:04.457336 [Byte1]: 38
7828 13:19:04.461587
7829 13:19:04.461659 Set Vref, RX VrefLevel [Byte0]: 39
7830 13:19:04.465092 [Byte1]: 39
7831 13:19:04.469374
7832 13:19:04.469460 Set Vref, RX VrefLevel [Byte0]: 40
7833 13:19:04.472424 [Byte1]: 40
7834 13:19:04.476990
7835 13:19:04.477079 Set Vref, RX VrefLevel [Byte0]: 41
7836 13:19:04.479920 [Byte1]: 41
7837 13:19:04.484288
7838 13:19:04.484371 Set Vref, RX VrefLevel [Byte0]: 42
7839 13:19:04.487710 [Byte1]: 42
7840 13:19:04.492025
7841 13:19:04.492096 Set Vref, RX VrefLevel [Byte0]: 43
7842 13:19:04.495252 [Byte1]: 43
7843 13:19:04.499749
7844 13:19:04.499822 Set Vref, RX VrefLevel [Byte0]: 44
7845 13:19:04.502730 [Byte1]: 44
7846 13:19:04.507415
7847 13:19:04.507484 Set Vref, RX VrefLevel [Byte0]: 45
7848 13:19:04.510846 [Byte1]: 45
7849 13:19:04.514941
7850 13:19:04.515016 Set Vref, RX VrefLevel [Byte0]: 46
7851 13:19:04.518547 [Byte1]: 46
7852 13:19:04.522784
7853 13:19:04.522859 Set Vref, RX VrefLevel [Byte0]: 47
7854 13:19:04.525811 [Byte1]: 47
7855 13:19:04.530116
7856 13:19:04.530191 Set Vref, RX VrefLevel [Byte0]: 48
7857 13:19:04.533443 [Byte1]: 48
7858 13:19:04.537498
7859 13:19:04.537572 Set Vref, RX VrefLevel [Byte0]: 49
7860 13:19:04.541152 [Byte1]: 49
7861 13:19:04.545494
7862 13:19:04.545568 Set Vref, RX VrefLevel [Byte0]: 50
7863 13:19:04.548355 [Byte1]: 50
7864 13:19:04.552696
7865 13:19:04.552771 Set Vref, RX VrefLevel [Byte0]: 51
7866 13:19:04.556749 [Byte1]: 51
7867 13:19:04.560560
7868 13:19:04.560634 Set Vref, RX VrefLevel [Byte0]: 52
7869 13:19:04.564131 [Byte1]: 52
7870 13:19:04.567918
7871 13:19:04.568022 Set Vref, RX VrefLevel [Byte0]: 53
7872 13:19:04.571617 [Byte1]: 53
7873 13:19:04.576084
7874 13:19:04.576159 Set Vref, RX VrefLevel [Byte0]: 54
7875 13:19:04.579346 [Byte1]: 54
7876 13:19:04.583583
7877 13:19:04.583658 Set Vref, RX VrefLevel [Byte0]: 55
7878 13:19:04.586688 [Byte1]: 55
7879 13:19:04.591029
7880 13:19:04.591103 Set Vref, RX VrefLevel [Byte0]: 56
7881 13:19:04.594062 [Byte1]: 56
7882 13:19:04.598707
7883 13:19:04.598781 Set Vref, RX VrefLevel [Byte0]: 57
7884 13:19:04.602162 [Byte1]: 57
7885 13:19:04.606153
7886 13:19:04.606227 Set Vref, RX VrefLevel [Byte0]: 58
7887 13:19:04.609616 [Byte1]: 58
7888 13:19:04.613724
7889 13:19:04.613798 Set Vref, RX VrefLevel [Byte0]: 59
7890 13:19:04.617419 [Byte1]: 59
7891 13:19:04.621268
7892 13:19:04.621342 Set Vref, RX VrefLevel [Byte0]: 60
7893 13:19:04.624728 [Byte1]: 60
7894 13:19:04.628835
7895 13:19:04.628909 Set Vref, RX VrefLevel [Byte0]: 61
7896 13:19:04.632610 [Byte1]: 61
7897 13:19:04.636871
7898 13:19:04.636945 Set Vref, RX VrefLevel [Byte0]: 62
7899 13:19:04.639989 [Byte1]: 62
7900 13:19:04.644319
7901 13:19:04.644393 Set Vref, RX VrefLevel [Byte0]: 63
7902 13:19:04.647358 [Byte1]: 63
7903 13:19:04.651731
7904 13:19:04.651805 Set Vref, RX VrefLevel [Byte0]: 64
7905 13:19:04.655249 [Byte1]: 64
7906 13:19:04.659451
7907 13:19:04.659525 Set Vref, RX VrefLevel [Byte0]: 65
7908 13:19:04.663161 [Byte1]: 65
7909 13:19:04.666871
7910 13:19:04.666946 Set Vref, RX VrefLevel [Byte0]: 66
7911 13:19:04.670617 [Byte1]: 66
7912 13:19:04.674728
7913 13:19:04.674803 Set Vref, RX VrefLevel [Byte0]: 67
7914 13:19:04.678173 [Byte1]: 67
7915 13:19:04.682539
7916 13:19:04.682659 Set Vref, RX VrefLevel [Byte0]: 68
7917 13:19:04.685475 [Byte1]: 68
7918 13:19:04.689975
7919 13:19:04.690050 Set Vref, RX VrefLevel [Byte0]: 69
7920 13:19:04.693355 [Byte1]: 69
7921 13:19:04.697666
7922 13:19:04.697759 Set Vref, RX VrefLevel [Byte0]: 70
7923 13:19:04.700898 [Byte1]: 70
7924 13:19:04.704943
7925 13:19:04.705017 Set Vref, RX VrefLevel [Byte0]: 71
7926 13:19:04.708568 [Byte1]: 71
7927 13:19:04.712509
7928 13:19:04.712597 Set Vref, RX VrefLevel [Byte0]: 72
7929 13:19:04.716183 [Byte1]: 72
7930 13:19:04.720259
7931 13:19:04.720366 Set Vref, RX VrefLevel [Byte0]: 73
7932 13:19:04.723377 [Byte1]: 73
7933 13:19:04.727919
7934 13:19:04.727994 Set Vref, RX VrefLevel [Byte0]: 74
7935 13:19:04.731539 [Byte1]: 74
7936 13:19:04.735781
7937 13:19:04.735859 Set Vref, RX VrefLevel [Byte0]: 75
7938 13:19:04.738734 [Byte1]: 75
7939 13:19:04.743055
7940 13:19:04.743149 Set Vref, RX VrefLevel [Byte0]: 76
7941 13:19:04.746555 [Byte1]: 76
7942 13:19:04.750693
7943 13:19:04.750767 Final RX Vref Byte 0 = 58 to rank0
7944 13:19:04.754489 Final RX Vref Byte 1 = 63 to rank0
7945 13:19:04.757604 Final RX Vref Byte 0 = 58 to rank1
7946 13:19:04.761288 Final RX Vref Byte 1 = 63 to rank1==
7947 13:19:04.764334 Dram Type= 6, Freq= 0, CH_0, rank 0
7948 13:19:04.767855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 13:19:04.770890 ==
7950 13:19:04.770964 DQS Delay:
7951 13:19:04.771023 DQS0 = 0, DQS1 = 0
7952 13:19:04.774616 DQM Delay:
7953 13:19:04.774690 DQM0 = 128, DQM1 = 122
7954 13:19:04.777649 DQ Delay:
7955 13:19:04.781244 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =124
7956 13:19:04.784309 DQ4 =132, DQ5 =116, DQ6 =136, DQ7 =136
7957 13:19:04.787850 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7958 13:19:04.791177 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =134
7959 13:19:04.791251
7960 13:19:04.791310
7961 13:19:04.791363
7962 13:19:04.794583 [DramC_TX_OE_Calibration] TA2
7963 13:19:04.798049 Original DQ_B0 (3 6) =30, OEN = 27
7964 13:19:04.801003 Original DQ_B1 (3 6) =30, OEN = 27
7965 13:19:04.801103 24, 0x0, End_B0=24 End_B1=24
7966 13:19:04.804382 25, 0x0, End_B0=25 End_B1=25
7967 13:19:04.807689 26, 0x0, End_B0=26 End_B1=26
7968 13:19:04.811527 27, 0x0, End_B0=27 End_B1=27
7969 13:19:04.814757 28, 0x0, End_B0=28 End_B1=28
7970 13:19:04.814837 29, 0x0, End_B0=29 End_B1=29
7971 13:19:04.818076 30, 0x0, End_B0=30 End_B1=30
7972 13:19:04.820895 31, 0x4141, End_B0=30 End_B1=30
7973 13:19:04.824249 Byte0 end_step=30 best_step=27
7974 13:19:04.827801 Byte1 end_step=30 best_step=27
7975 13:19:04.831201 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 13:19:04.831276 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 13:19:04.831335
7978 13:19:04.831388
7979 13:19:04.840865 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7980 13:19:04.844554 CH0 RK0: MR19=303, MR18=1307
7981 13:19:04.851258 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
7982 13:19:04.851334
7983 13:19:04.854322 ----->DramcWriteLeveling(PI) begin...
7984 13:19:04.854398 ==
7985 13:19:04.857902 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 13:19:04.860925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 13:19:04.861002 ==
7988 13:19:04.864508 Write leveling (Byte 0): 35 => 35
7989 13:19:04.867539 Write leveling (Byte 1): 26 => 26
7990 13:19:04.871250 DramcWriteLeveling(PI) end<-----
7991 13:19:04.871325
7992 13:19:04.871383 ==
7993 13:19:04.874176 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 13:19:04.877829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 13:19:04.877908 ==
7996 13:19:04.880944 [Gating] SW mode calibration
7997 13:19:04.887757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7998 13:19:04.894363 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7999 13:19:04.897911 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 13:19:04.901124 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 13:19:04.907484 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8002 13:19:04.911055 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8003 13:19:04.914604 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8004 13:19:04.917980 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8005 13:19:04.924171 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 13:19:04.928050 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 13:19:04.931048 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 13:19:04.938094 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 13:19:04.941231 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8010 13:19:04.944857 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8011 13:19:04.951408 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8012 13:19:04.954628 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8013 13:19:04.958181 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 13:19:04.964402 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 13:19:04.967854 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 13:19:04.971503 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 13:19:04.978113 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8018 13:19:04.981113 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8019 13:19:04.984908 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8020 13:19:04.987934 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8021 13:19:04.994779 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 13:19:04.997776 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 13:19:05.001462 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 13:19:05.007814 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8025 13:19:05.011538 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 13:19:05.015028 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 13:19:05.021607 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8028 13:19:05.024455 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 13:19:05.028418 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 13:19:05.034399 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 13:19:05.038039 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 13:19:05.041050 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 13:19:05.048130 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 13:19:05.051104 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 13:19:05.054805 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 13:19:05.061350 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 13:19:05.064628 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 13:19:05.067884 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 13:19:05.074941 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 13:19:05.078055 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 13:19:05.081143 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 13:19:05.084918 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8043 13:19:05.087839 Total UI for P1: 0, mck2ui 16
8044 13:19:05.091510 best dqsien dly found for B0: ( 1, 9, 10)
8045 13:19:05.097688 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8046 13:19:05.101434 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8047 13:19:05.104425 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 13:19:05.108055 Total UI for P1: 0, mck2ui 16
8049 13:19:05.111071 best dqsien dly found for B1: ( 1, 9, 18)
8050 13:19:05.114684 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8051 13:19:05.118115 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8052 13:19:05.118215
8053 13:19:05.124718 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8054 13:19:05.128158 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8055 13:19:05.131184 [Gating] SW calibration Done
8056 13:19:05.131261 ==
8057 13:19:05.134556 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 13:19:05.137850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 13:19:05.137928 ==
8060 13:19:05.137988 RX Vref Scan: 0
8061 13:19:05.141090
8062 13:19:05.141175 RX Vref 0 -> 0, step: 1
8063 13:19:05.141236
8064 13:19:05.144647 RX Delay 0 -> 252, step: 8
8065 13:19:05.148055 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8066 13:19:05.151151 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8067 13:19:05.157990 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8068 13:19:05.161515 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8069 13:19:05.164732 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8070 13:19:05.168157 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8071 13:19:05.171029 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8072 13:19:05.174675 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8073 13:19:05.181237 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8074 13:19:05.184567 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8075 13:19:05.188171 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8076 13:19:05.191265 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8077 13:19:05.198099 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8078 13:19:05.201134 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8079 13:19:05.204920 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8080 13:19:05.207798 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8081 13:19:05.207876 ==
8082 13:19:05.211518 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 13:19:05.214573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 13:19:05.218175 ==
8085 13:19:05.218276 DQS Delay:
8086 13:19:05.218363 DQS0 = 0, DQS1 = 0
8087 13:19:05.221267 DQM Delay:
8088 13:19:05.221343 DQM0 = 131, DQM1 = 126
8089 13:19:05.224914 DQ Delay:
8090 13:19:05.228196 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8091 13:19:05.231196 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8092 13:19:05.234893 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8093 13:19:05.237951 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8094 13:19:05.238071
8095 13:19:05.238137
8096 13:19:05.238194 ==
8097 13:19:05.241201 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 13:19:05.244490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 13:19:05.244565 ==
8100 13:19:05.244624
8101 13:19:05.244677
8102 13:19:05.247824 TX Vref Scan disable
8103 13:19:05.251148 == TX Byte 0 ==
8104 13:19:05.255028 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8105 13:19:05.257895 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8106 13:19:05.261459 == TX Byte 1 ==
8107 13:19:05.265001 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8108 13:19:05.267903 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8109 13:19:05.267978 ==
8110 13:19:05.271609 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 13:19:05.274783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 13:19:05.277843 ==
8113 13:19:05.291764
8114 13:19:05.294774 TX Vref early break, caculate TX vref
8115 13:19:05.298329 TX Vref=16, minBit 9, minWin=22, winSum=377
8116 13:19:05.301412 TX Vref=18, minBit 12, minWin=22, winSum=386
8117 13:19:05.304991 TX Vref=20, minBit 9, minWin=23, winSum=393
8118 13:19:05.308096 TX Vref=22, minBit 9, minWin=24, winSum=403
8119 13:19:05.311699 TX Vref=24, minBit 8, minWin=24, winSum=409
8120 13:19:05.318311 TX Vref=26, minBit 4, minWin=25, winSum=414
8121 13:19:05.321990 TX Vref=28, minBit 9, minWin=25, winSum=421
8122 13:19:05.325058 TX Vref=30, minBit 8, minWin=25, winSum=421
8123 13:19:05.328575 TX Vref=32, minBit 5, minWin=25, winSum=414
8124 13:19:05.331633 TX Vref=34, minBit 5, minWin=25, winSum=411
8125 13:19:05.335011 TX Vref=36, minBit 13, minWin=23, winSum=394
8126 13:19:05.341768 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
8127 13:19:05.341854
8128 13:19:05.344690 Final TX Range 0 Vref 28
8129 13:19:05.344753
8130 13:19:05.344805 ==
8131 13:19:05.348203 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 13:19:05.351760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 13:19:05.351875 ==
8134 13:19:05.351933
8135 13:19:05.351986
8136 13:19:05.355137 TX Vref Scan disable
8137 13:19:05.361688 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8138 13:19:05.361767 == TX Byte 0 ==
8139 13:19:05.364880 u2DelayCellOfst[0]=14 cells (4 PI)
8140 13:19:05.368532 u2DelayCellOfst[1]=21 cells (6 PI)
8141 13:19:05.371485 u2DelayCellOfst[2]=10 cells (3 PI)
8142 13:19:05.374975 u2DelayCellOfst[3]=14 cells (4 PI)
8143 13:19:05.378326 u2DelayCellOfst[4]=10 cells (3 PI)
8144 13:19:05.381997 u2DelayCellOfst[5]=0 cells (0 PI)
8145 13:19:05.385413 u2DelayCellOfst[6]=21 cells (6 PI)
8146 13:19:05.388523 u2DelayCellOfst[7]=21 cells (6 PI)
8147 13:19:05.391961 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8148 13:19:05.394949 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8149 13:19:05.398328 == TX Byte 1 ==
8150 13:19:05.401654 u2DelayCellOfst[8]=0 cells (0 PI)
8151 13:19:05.405360 u2DelayCellOfst[9]=0 cells (0 PI)
8152 13:19:05.405436 u2DelayCellOfst[10]=7 cells (2 PI)
8153 13:19:05.408524 u2DelayCellOfst[11]=0 cells (0 PI)
8154 13:19:05.411381 u2DelayCellOfst[12]=10 cells (3 PI)
8155 13:19:05.414984 u2DelayCellOfst[13]=10 cells (3 PI)
8156 13:19:05.418224 u2DelayCellOfst[14]=14 cells (4 PI)
8157 13:19:05.421785 u2DelayCellOfst[15]=10 cells (3 PI)
8158 13:19:05.424877 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8159 13:19:05.431531 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8160 13:19:05.431607 DramC Write-DBI on
8161 13:19:05.431666 ==
8162 13:19:05.434590 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 13:19:05.441725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 13:19:05.441801 ==
8165 13:19:05.441860
8166 13:19:05.441914
8167 13:19:05.441965 TX Vref Scan disable
8168 13:19:05.445594 == TX Byte 0 ==
8169 13:19:05.448915 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8170 13:19:05.451884 == TX Byte 1 ==
8171 13:19:05.455422 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8172 13:19:05.459075 DramC Write-DBI off
8173 13:19:05.459174
8174 13:19:05.459257 [DATLAT]
8175 13:19:05.459338 Freq=1600, CH0 RK1
8176 13:19:05.459418
8177 13:19:05.462060 DATLAT Default: 0xf
8178 13:19:05.462135 0, 0xFFFF, sum = 0
8179 13:19:05.465605 1, 0xFFFF, sum = 0
8180 13:19:05.468541 2, 0xFFFF, sum = 0
8181 13:19:05.468644 3, 0xFFFF, sum = 0
8182 13:19:05.472031 4, 0xFFFF, sum = 0
8183 13:19:05.472168 5, 0xFFFF, sum = 0
8184 13:19:05.475344 6, 0xFFFF, sum = 0
8185 13:19:05.475428 7, 0xFFFF, sum = 0
8186 13:19:05.478450 8, 0xFFFF, sum = 0
8187 13:19:05.478528 9, 0xFFFF, sum = 0
8188 13:19:05.482031 10, 0xFFFF, sum = 0
8189 13:19:05.482133 11, 0xFFFF, sum = 0
8190 13:19:05.485128 12, 0xFFFF, sum = 0
8191 13:19:05.485227 13, 0xFFFF, sum = 0
8192 13:19:05.488865 14, 0x0, sum = 1
8193 13:19:05.488989 15, 0x0, sum = 2
8194 13:19:05.491749 16, 0x0, sum = 3
8195 13:19:05.491839 17, 0x0, sum = 4
8196 13:19:05.495265 best_step = 15
8197 13:19:05.495340
8198 13:19:05.495399 ==
8199 13:19:05.498849 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 13:19:05.501868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 13:19:05.501943 ==
8202 13:19:05.502002 RX Vref Scan: 0
8203 13:19:05.505320
8204 13:19:05.505381 RX Vref 0 -> 0, step: 1
8205 13:19:05.505436
8206 13:19:05.508601 RX Delay 11 -> 252, step: 4
8207 13:19:05.511748 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8208 13:19:05.518365 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8209 13:19:05.521983 iDelay=191, Bit 2, Center 124 (67 ~ 182) 116
8210 13:19:05.525025 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8211 13:19:05.528755 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8212 13:19:05.531890 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8213 13:19:05.538498 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8214 13:19:05.542210 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8215 13:19:05.545272 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8216 13:19:05.548840 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8217 13:19:05.551820 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8218 13:19:05.558851 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8219 13:19:05.562262 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8220 13:19:05.565073 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8221 13:19:05.568488 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8222 13:19:05.571954 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8223 13:19:05.572130 ==
8224 13:19:05.575723 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 13:19:05.581796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 13:19:05.581891 ==
8227 13:19:05.581950 DQS Delay:
8228 13:19:05.585749 DQS0 = 0, DQS1 = 0
8229 13:19:05.585824 DQM Delay:
8230 13:19:05.588772 DQM0 = 126, DQM1 = 122
8231 13:19:05.588847 DQ Delay:
8232 13:19:05.592158 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8233 13:19:05.595457 DQ4 =124, DQ5 =114, DQ6 =136, DQ7 =134
8234 13:19:05.598690 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =116
8235 13:19:05.601845 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8236 13:19:05.601913
8237 13:19:05.601969
8238 13:19:05.602022
8239 13:19:05.605656 [DramC_TX_OE_Calibration] TA2
8240 13:19:05.608526 Original DQ_B0 (3 6) =30, OEN = 27
8241 13:19:05.611934 Original DQ_B1 (3 6) =30, OEN = 27
8242 13:19:05.615316 24, 0x0, End_B0=24 End_B1=24
8243 13:19:05.615429 25, 0x0, End_B0=25 End_B1=25
8244 13:19:05.619038 26, 0x0, End_B0=26 End_B1=26
8245 13:19:05.622067 27, 0x0, End_B0=27 End_B1=27
8246 13:19:05.625568 28, 0x0, End_B0=28 End_B1=28
8247 13:19:05.628560 29, 0x0, End_B0=29 End_B1=29
8248 13:19:05.628656 30, 0x0, End_B0=30 End_B1=30
8249 13:19:05.632212 31, 0x5151, End_B0=30 End_B1=30
8250 13:19:05.635344 Byte0 end_step=30 best_step=27
8251 13:19:05.638342 Byte1 end_step=30 best_step=27
8252 13:19:05.642084 Byte0 TX OE(2T, 0.5T) = (3, 3)
8253 13:19:05.645058 Byte1 TX OE(2T, 0.5T) = (3, 3)
8254 13:19:05.645154
8255 13:19:05.645235
8256 13:19:05.651706 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8257 13:19:05.655524 CH0 RK1: MR19=303, MR18=1B10
8258 13:19:05.662141 CH0_RK1: MR19=0x303, MR18=0x1B10, DQSOSC=396, MR23=63, INC=23, DEC=15
8259 13:19:05.665019 [RxdqsGatingPostProcess] freq 1600
8260 13:19:05.668346 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8261 13:19:05.671731 best DQS0 dly(2T, 0.5T) = (1, 1)
8262 13:19:05.675105 best DQS1 dly(2T, 0.5T) = (1, 1)
8263 13:19:05.678812 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8264 13:19:05.681720 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8265 13:19:05.685214 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 13:19:05.688755 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 13:19:05.692279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 13:19:05.695350 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 13:19:05.698528 Pre-setting of DQS Precalculation
8270 13:19:05.701921 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8271 13:19:05.701999 ==
8272 13:19:05.705468 Dram Type= 6, Freq= 0, CH_1, rank 0
8273 13:19:05.708621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 13:19:05.708713 ==
8275 13:19:05.715695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 13:19:05.718544 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 13:19:05.725572 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 13:19:05.728640 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 13:19:05.738325 [CA 0] Center 43 (14~72) winsize 59
8280 13:19:05.742145 [CA 1] Center 43 (14~72) winsize 59
8281 13:19:05.745090 [CA 2] Center 38 (10~67) winsize 58
8282 13:19:05.748724 [CA 3] Center 37 (8~66) winsize 59
8283 13:19:05.751657 [CA 4] Center 38 (9~68) winsize 60
8284 13:19:05.754898 [CA 5] Center 37 (8~66) winsize 59
8285 13:19:05.754976
8286 13:19:05.758383 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8287 13:19:05.758457
8288 13:19:05.761894 [CATrainingPosCal] consider 1 rank data
8289 13:19:05.764894 u2DelayCellTimex100 = 275/100 ps
8290 13:19:05.768546 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8291 13:19:05.775225 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8292 13:19:05.778251 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8293 13:19:05.781587 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8294 13:19:05.784936 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8295 13:19:05.788638 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8296 13:19:05.788736
8297 13:19:05.791952 CA PerBit enable=1, Macro0, CA PI delay=37
8298 13:19:05.792045
8299 13:19:05.795144 [CBTSetCACLKResult] CA Dly = 37
8300 13:19:05.798399 CS Dly: 9 (0~40)
8301 13:19:05.801745 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 13:19:05.805142 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 13:19:05.805223 ==
8304 13:19:05.808582 Dram Type= 6, Freq= 0, CH_1, rank 1
8305 13:19:05.811938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 13:19:05.812016 ==
8307 13:19:05.818540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 13:19:05.821888 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 13:19:05.828294 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 13:19:05.831686 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 13:19:05.841867 [CA 0] Center 42 (13~72) winsize 60
8312 13:19:05.845495 [CA 1] Center 43 (14~72) winsize 59
8313 13:19:05.848383 [CA 2] Center 38 (9~67) winsize 59
8314 13:19:05.851904 [CA 3] Center 36 (7~66) winsize 60
8315 13:19:05.854987 [CA 4] Center 38 (9~68) winsize 60
8316 13:19:05.858560 [CA 5] Center 36 (7~66) winsize 60
8317 13:19:05.858657
8318 13:19:05.861621 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 13:19:05.861712
8320 13:19:05.865340 [CATrainingPosCal] consider 2 rank data
8321 13:19:05.868376 u2DelayCellTimex100 = 275/100 ps
8322 13:19:05.871936 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8323 13:19:05.878683 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8324 13:19:05.881705 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8325 13:19:05.885101 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8326 13:19:05.888244 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8327 13:19:05.891748 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8328 13:19:05.891839
8329 13:19:05.895321 CA PerBit enable=1, Macro0, CA PI delay=37
8330 13:19:05.895413
8331 13:19:05.898110 [CBTSetCACLKResult] CA Dly = 37
8332 13:19:05.901705 CS Dly: 11 (0~44)
8333 13:19:05.905275 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 13:19:05.908445 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 13:19:05.908513
8336 13:19:05.911444 ----->DramcWriteLeveling(PI) begin...
8337 13:19:05.911513 ==
8338 13:19:05.915129 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 13:19:05.918544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 13:19:05.921759 ==
8341 13:19:05.921831 Write leveling (Byte 0): 25 => 25
8342 13:19:05.925026 Write leveling (Byte 1): 29 => 29
8343 13:19:05.928724 DramcWriteLeveling(PI) end<-----
8344 13:19:05.928817
8345 13:19:05.928909 ==
8346 13:19:05.931501 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 13:19:05.938276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 13:19:05.938371 ==
8349 13:19:05.938431 [Gating] SW mode calibration
8350 13:19:05.948149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8351 13:19:05.951830 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8352 13:19:05.954763 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 13:19:05.961620 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 13:19:05.965352 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 13:19:05.968093 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 13:19:05.974863 1 4 16 | B1->B0 | 2f2f 2928 | 0 1 | (0 0) (0 0)
8357 13:19:05.978678 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 13:19:05.981831 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 13:19:05.988342 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 13:19:05.991954 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 13:19:05.995041 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 13:19:06.001983 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 13:19:06.004771 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8364 13:19:06.008363 1 5 16 | B1->B0 | 2929 3131 | 1 1 | (1 0) (1 0)
8365 13:19:06.015402 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 13:19:06.018320 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 13:19:06.021894 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 13:19:06.028701 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 13:19:06.031758 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 13:19:06.034951 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 13:19:06.038461 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8372 13:19:06.045307 1 6 16 | B1->B0 | 3939 2e2e | 0 0 | (0 0) (0 0)
8373 13:19:06.048420 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 13:19:06.051933 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 13:19:06.058489 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 13:19:06.062067 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 13:19:06.065001 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 13:19:06.071689 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 13:19:06.075406 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8380 13:19:06.078417 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8381 13:19:06.085024 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8382 13:19:06.088752 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 13:19:06.091827 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 13:19:06.098366 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 13:19:06.102160 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 13:19:06.105259 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 13:19:06.111900 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 13:19:06.115047 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 13:19:06.118643 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 13:19:06.125107 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 13:19:06.128819 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 13:19:06.131896 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 13:19:06.135548 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 13:19:06.142419 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 13:19:06.145476 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 13:19:06.148882 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8397 13:19:06.155278 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 13:19:06.158510 Total UI for P1: 0, mck2ui 16
8399 13:19:06.162115 best dqsien dly found for B0: ( 1, 9, 16)
8400 13:19:06.162220 Total UI for P1: 0, mck2ui 16
8401 13:19:06.168969 best dqsien dly found for B1: ( 1, 9, 16)
8402 13:19:06.171987 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8403 13:19:06.175098 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8404 13:19:06.175201
8405 13:19:06.178289 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8406 13:19:06.181722 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8407 13:19:06.185457 [Gating] SW calibration Done
8408 13:19:06.185562 ==
8409 13:19:06.188634 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 13:19:06.192166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 13:19:06.192243 ==
8412 13:19:06.195108 RX Vref Scan: 0
8413 13:19:06.195215
8414 13:19:06.195303 RX Vref 0 -> 0, step: 1
8415 13:19:06.195392
8416 13:19:06.198811 RX Delay 0 -> 252, step: 8
8417 13:19:06.201744 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8418 13:19:06.208362 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8419 13:19:06.211998 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8420 13:19:06.215086 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8421 13:19:06.218289 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8422 13:19:06.221671 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8423 13:19:06.228528 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8424 13:19:06.231651 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8425 13:19:06.235331 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8426 13:19:06.238426 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8427 13:19:06.241932 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8428 13:19:06.248606 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8429 13:19:06.252022 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8430 13:19:06.255402 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8431 13:19:06.258474 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8432 13:19:06.261651 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8433 13:19:06.265069 ==
8434 13:19:06.265166 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 13:19:06.271822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 13:19:06.271930 ==
8437 13:19:06.272022 DQS Delay:
8438 13:19:06.274938 DQS0 = 0, DQS1 = 0
8439 13:19:06.275014 DQM Delay:
8440 13:19:06.278714 DQM0 = 135, DQM1 = 126
8441 13:19:06.278791 DQ Delay:
8442 13:19:06.281960 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8443 13:19:06.285120 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8444 13:19:06.288765 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8445 13:19:06.291766 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8446 13:19:06.291866
8447 13:19:06.291952
8448 13:19:06.292034 ==
8449 13:19:06.295443 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 13:19:06.298560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 13:19:06.302064 ==
8452 13:19:06.302170
8453 13:19:06.302262
8454 13:19:06.302354 TX Vref Scan disable
8455 13:19:06.305707 == TX Byte 0 ==
8456 13:19:06.308734 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8457 13:19:06.312458 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8458 13:19:06.315485 == TX Byte 1 ==
8459 13:19:06.318494 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8460 13:19:06.322162 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8461 13:19:06.325297 ==
8462 13:19:06.325374 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 13:19:06.331610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 13:19:06.331726 ==
8465 13:19:06.344083
8466 13:19:06.347665 TX Vref early break, caculate TX vref
8467 13:19:06.350577 TX Vref=16, minBit 8, minWin=20, winSum=361
8468 13:19:06.354220 TX Vref=18, minBit 8, minWin=20, winSum=367
8469 13:19:06.357751 TX Vref=20, minBit 5, minWin=22, winSum=378
8470 13:19:06.360679 TX Vref=22, minBit 8, minWin=23, winSum=393
8471 13:19:06.364147 TX Vref=24, minBit 8, minWin=23, winSum=397
8472 13:19:06.370701 TX Vref=26, minBit 5, minWin=24, winSum=412
8473 13:19:06.374304 TX Vref=28, minBit 8, minWin=25, winSum=416
8474 13:19:06.377764 TX Vref=30, minBit 8, minWin=25, winSum=419
8475 13:19:06.380656 TX Vref=32, minBit 13, minWin=24, winSum=409
8476 13:19:06.384018 TX Vref=34, minBit 8, minWin=23, winSum=395
8477 13:19:06.390659 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 30
8478 13:19:06.390737
8479 13:19:06.393926 Final TX Range 0 Vref 30
8480 13:19:06.394031
8481 13:19:06.394120 ==
8482 13:19:06.397372 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 13:19:06.401100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 13:19:06.401187 ==
8485 13:19:06.401248
8486 13:19:06.401303
8487 13:19:06.404099 TX Vref Scan disable
8488 13:19:06.411177 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8489 13:19:06.411255 == TX Byte 0 ==
8490 13:19:06.414193 u2DelayCellOfst[0]=17 cells (5 PI)
8491 13:19:06.417355 u2DelayCellOfst[1]=10 cells (3 PI)
8492 13:19:06.420921 u2DelayCellOfst[2]=0 cells (0 PI)
8493 13:19:06.424574 u2DelayCellOfst[3]=7 cells (2 PI)
8494 13:19:06.427539 u2DelayCellOfst[4]=10 cells (3 PI)
8495 13:19:06.427616 u2DelayCellOfst[5]=17 cells (5 PI)
8496 13:19:06.431110 u2DelayCellOfst[6]=17 cells (5 PI)
8497 13:19:06.434721 u2DelayCellOfst[7]=7 cells (2 PI)
8498 13:19:06.440854 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8499 13:19:06.444644 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8500 13:19:06.444722 == TX Byte 1 ==
8501 13:19:06.447485 u2DelayCellOfst[8]=0 cells (0 PI)
8502 13:19:06.450897 u2DelayCellOfst[9]=7 cells (2 PI)
8503 13:19:06.454690 u2DelayCellOfst[10]=10 cells (3 PI)
8504 13:19:06.457759 u2DelayCellOfst[11]=7 cells (2 PI)
8505 13:19:06.460827 u2DelayCellOfst[12]=14 cells (4 PI)
8506 13:19:06.464390 u2DelayCellOfst[13]=17 cells (5 PI)
8507 13:19:06.468031 u2DelayCellOfst[14]=17 cells (5 PI)
8508 13:19:06.470924 u2DelayCellOfst[15]=17 cells (5 PI)
8509 13:19:06.474341 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8510 13:19:06.477566 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8511 13:19:06.480924 DramC Write-DBI on
8512 13:19:06.481022 ==
8513 13:19:06.484500 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 13:19:06.488036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 13:19:06.488148 ==
8516 13:19:06.488226
8517 13:19:06.488311
8518 13:19:06.490968 TX Vref Scan disable
8519 13:19:06.494486 == TX Byte 0 ==
8520 13:19:06.497850 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8521 13:19:06.497951 == TX Byte 1 ==
8522 13:19:06.504562 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8523 13:19:06.504632 DramC Write-DBI off
8524 13:19:06.504690
8525 13:19:06.504746 [DATLAT]
8526 13:19:06.508172 Freq=1600, CH1 RK0
8527 13:19:06.508241
8528 13:19:06.511060 DATLAT Default: 0xf
8529 13:19:06.511159 0, 0xFFFF, sum = 0
8530 13:19:06.514983 1, 0xFFFF, sum = 0
8531 13:19:06.515049 2, 0xFFFF, sum = 0
8532 13:19:06.517936 3, 0xFFFF, sum = 0
8533 13:19:06.518027 4, 0xFFFF, sum = 0
8534 13:19:06.521567 5, 0xFFFF, sum = 0
8535 13:19:06.521658 6, 0xFFFF, sum = 0
8536 13:19:06.524711 7, 0xFFFF, sum = 0
8537 13:19:06.524776 8, 0xFFFF, sum = 0
8538 13:19:06.528198 9, 0xFFFF, sum = 0
8539 13:19:06.528263 10, 0xFFFF, sum = 0
8540 13:19:06.531509 11, 0xFFFF, sum = 0
8541 13:19:06.531598 12, 0xFFFF, sum = 0
8542 13:19:06.534982 13, 0xFFFF, sum = 0
8543 13:19:06.535049 14, 0x0, sum = 1
8544 13:19:06.538048 15, 0x0, sum = 2
8545 13:19:06.538124 16, 0x0, sum = 3
8546 13:19:06.541081 17, 0x0, sum = 4
8547 13:19:06.541179 best_step = 15
8548 13:19:06.541259
8549 13:19:06.541347 ==
8550 13:19:06.544853 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 13:19:06.551405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 13:19:06.551487 ==
8553 13:19:06.551544 RX Vref Scan: 1
8554 13:19:06.551618
8555 13:19:06.554623 Set Vref Range= 24 -> 127
8556 13:19:06.554703
8557 13:19:06.558094 RX Vref 24 -> 127, step: 1
8558 13:19:06.558161
8559 13:19:06.558215 RX Delay 11 -> 252, step: 4
8560 13:19:06.558281
8561 13:19:06.561616 Set Vref, RX VrefLevel [Byte0]: 24
8562 13:19:06.564701 [Byte1]: 24
8563 13:19:06.568967
8564 13:19:06.569067 Set Vref, RX VrefLevel [Byte0]: 25
8565 13:19:06.572075 [Byte1]: 25
8566 13:19:06.576250
8567 13:19:06.576323 Set Vref, RX VrefLevel [Byte0]: 26
8568 13:19:06.579879 [Byte1]: 26
8569 13:19:06.584319
8570 13:19:06.584392 Set Vref, RX VrefLevel [Byte0]: 27
8571 13:19:06.587342 [Byte1]: 27
8572 13:19:06.591699
8573 13:19:06.591797 Set Vref, RX VrefLevel [Byte0]: 28
8574 13:19:06.594620 [Byte1]: 28
8575 13:19:06.599297
8576 13:19:06.599396 Set Vref, RX VrefLevel [Byte0]: 29
8577 13:19:06.602820 [Byte1]: 29
8578 13:19:06.607046
8579 13:19:06.607144 Set Vref, RX VrefLevel [Byte0]: 30
8580 13:19:06.609911 [Byte1]: 30
8581 13:19:06.614188
8582 13:19:06.614261 Set Vref, RX VrefLevel [Byte0]: 31
8583 13:19:06.617903 [Byte1]: 31
8584 13:19:06.622014
8585 13:19:06.622115 Set Vref, RX VrefLevel [Byte0]: 32
8586 13:19:06.625062 [Byte1]: 32
8587 13:19:06.629747
8588 13:19:06.629849 Set Vref, RX VrefLevel [Byte0]: 33
8589 13:19:06.632769 [Byte1]: 33
8590 13:19:06.637020
8591 13:19:06.637123 Set Vref, RX VrefLevel [Byte0]: 34
8592 13:19:06.640683 [Byte1]: 34
8593 13:19:06.645011
8594 13:19:06.645111 Set Vref, RX VrefLevel [Byte0]: 35
8595 13:19:06.648039 [Byte1]: 35
8596 13:19:06.652349
8597 13:19:06.652441 Set Vref, RX VrefLevel [Byte0]: 36
8598 13:19:06.655873 [Byte1]: 36
8599 13:19:06.660390
8600 13:19:06.660493 Set Vref, RX VrefLevel [Byte0]: 37
8601 13:19:06.663133 [Byte1]: 37
8602 13:19:06.667453
8603 13:19:06.667553 Set Vref, RX VrefLevel [Byte0]: 38
8604 13:19:06.671306 [Byte1]: 38
8605 13:19:06.675375
8606 13:19:06.675472 Set Vref, RX VrefLevel [Byte0]: 39
8607 13:19:06.678389 [Byte1]: 39
8608 13:19:06.683141
8609 13:19:06.683245 Set Vref, RX VrefLevel [Byte0]: 40
8610 13:19:06.686267 [Byte1]: 40
8611 13:19:06.690443
8612 13:19:06.690541 Set Vref, RX VrefLevel [Byte0]: 41
8613 13:19:06.693833 [Byte1]: 41
8614 13:19:06.698321
8615 13:19:06.698413 Set Vref, RX VrefLevel [Byte0]: 42
8616 13:19:06.701465 [Byte1]: 42
8617 13:19:06.705565
8618 13:19:06.705665 Set Vref, RX VrefLevel [Byte0]: 43
8619 13:19:06.709039 [Byte1]: 43
8620 13:19:06.713305
8621 13:19:06.713417 Set Vref, RX VrefLevel [Byte0]: 44
8622 13:19:06.716929 [Byte1]: 44
8623 13:19:06.720946
8624 13:19:06.721019 Set Vref, RX VrefLevel [Byte0]: 45
8625 13:19:06.724298 [Byte1]: 45
8626 13:19:06.728551
8627 13:19:06.728661 Set Vref, RX VrefLevel [Byte0]: 46
8628 13:19:06.731650 [Byte1]: 46
8629 13:19:06.736521
8630 13:19:06.736592 Set Vref, RX VrefLevel [Byte0]: 47
8631 13:19:06.739382 [Byte1]: 47
8632 13:19:06.743682
8633 13:19:06.743778 Set Vref, RX VrefLevel [Byte0]: 48
8634 13:19:06.747340 [Byte1]: 48
8635 13:19:06.751552
8636 13:19:06.751645 Set Vref, RX VrefLevel [Byte0]: 49
8637 13:19:06.754504 [Byte1]: 49
8638 13:19:06.758690
8639 13:19:06.758780 Set Vref, RX VrefLevel [Byte0]: 50
8640 13:19:06.762333 [Byte1]: 50
8641 13:19:06.766525
8642 13:19:06.766625 Set Vref, RX VrefLevel [Byte0]: 51
8643 13:19:06.770067 [Byte1]: 51
8644 13:19:06.774075
8645 13:19:06.774170 Set Vref, RX VrefLevel [Byte0]: 52
8646 13:19:06.777342 [Byte1]: 52
8647 13:19:06.781977
8648 13:19:06.782049 Set Vref, RX VrefLevel [Byte0]: 53
8649 13:19:06.785599 [Byte1]: 53
8650 13:19:06.789676
8651 13:19:06.789745 Set Vref, RX VrefLevel [Byte0]: 54
8652 13:19:06.792864 [Byte1]: 54
8653 13:19:06.796915
8654 13:19:06.796983 Set Vref, RX VrefLevel [Byte0]: 55
8655 13:19:06.800587 [Byte1]: 55
8656 13:19:06.804606
8657 13:19:06.804676 Set Vref, RX VrefLevel [Byte0]: 56
8658 13:19:06.807898 [Byte1]: 56
8659 13:19:06.812177
8660 13:19:06.812258 Set Vref, RX VrefLevel [Byte0]: 57
8661 13:19:06.815714 [Byte1]: 57
8662 13:19:06.819846
8663 13:19:06.819923 Set Vref, RX VrefLevel [Byte0]: 58
8664 13:19:06.823448 [Byte1]: 58
8665 13:19:06.827764
8666 13:19:06.827848 Set Vref, RX VrefLevel [Byte0]: 59
8667 13:19:06.830969 [Byte1]: 59
8668 13:19:06.835049
8669 13:19:06.835121 Set Vref, RX VrefLevel [Byte0]: 60
8670 13:19:06.838233 [Byte1]: 60
8671 13:19:06.842616
8672 13:19:06.842715 Set Vref, RX VrefLevel [Byte0]: 61
8673 13:19:06.846057 [Byte1]: 61
8674 13:19:06.850170
8675 13:19:06.850276 Set Vref, RX VrefLevel [Byte0]: 62
8676 13:19:06.853866 [Byte1]: 62
8677 13:19:06.858084
8678 13:19:06.858158 Set Vref, RX VrefLevel [Byte0]: 63
8679 13:19:06.860991 [Byte1]: 63
8680 13:19:06.865795
8681 13:19:06.865894 Set Vref, RX VrefLevel [Byte0]: 64
8682 13:19:06.868936 [Byte1]: 64
8683 13:19:06.873136
8684 13:19:06.873215 Set Vref, RX VrefLevel [Byte0]: 65
8685 13:19:06.876607 [Byte1]: 65
8686 13:19:06.880666
8687 13:19:06.880767 Set Vref, RX VrefLevel [Byte0]: 66
8688 13:19:06.883910 [Byte1]: 66
8689 13:19:06.888311
8690 13:19:06.888412 Set Vref, RX VrefLevel [Byte0]: 67
8691 13:19:06.891804 [Byte1]: 67
8692 13:19:06.896067
8693 13:19:06.896169 Set Vref, RX VrefLevel [Byte0]: 68
8694 13:19:06.899133 [Byte1]: 68
8695 13:19:06.903508
8696 13:19:06.903586 Set Vref, RX VrefLevel [Byte0]: 69
8697 13:19:06.907063 [Byte1]: 69
8698 13:19:06.911402
8699 13:19:06.911479 Set Vref, RX VrefLevel [Byte0]: 70
8700 13:19:06.914426 [Byte1]: 70
8701 13:19:06.919180
8702 13:19:06.919258 Set Vref, RX VrefLevel [Byte0]: 71
8703 13:19:06.922062 [Byte1]: 71
8704 13:19:06.926704
8705 13:19:06.926800 Set Vref, RX VrefLevel [Byte0]: 72
8706 13:19:06.929579 [Byte1]: 72
8707 13:19:06.933811
8708 13:19:06.933915 Set Vref, RX VrefLevel [Byte0]: 73
8709 13:19:06.937582 [Byte1]: 73
8710 13:19:06.941756
8711 13:19:06.941853 Set Vref, RX VrefLevel [Byte0]: 74
8712 13:19:06.944801 [Byte1]: 74
8713 13:19:06.949307
8714 13:19:06.949411 Set Vref, RX VrefLevel [Byte0]: 75
8715 13:19:06.952618 [Byte1]: 75
8716 13:19:06.957020
8717 13:19:06.957125 Set Vref, RX VrefLevel [Byte0]: 76
8718 13:19:06.960311 [Byte1]: 76
8719 13:19:06.964667
8720 13:19:06.964763 Final RX Vref Byte 0 = 58 to rank0
8721 13:19:06.968320 Final RX Vref Byte 1 = 55 to rank0
8722 13:19:06.971368 Final RX Vref Byte 0 = 58 to rank1
8723 13:19:06.974908 Final RX Vref Byte 1 = 55 to rank1==
8724 13:19:06.978032 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 13:19:06.984423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 13:19:06.984530 ==
8727 13:19:06.984615 DQS Delay:
8728 13:19:06.984709 DQS0 = 0, DQS1 = 0
8729 13:19:06.987906 DQM Delay:
8730 13:19:06.987993 DQM0 = 130, DQM1 = 124
8731 13:19:06.991427 DQ Delay:
8732 13:19:06.994636 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8733 13:19:06.997970 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8734 13:19:07.001225 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8735 13:19:07.004875 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8736 13:19:07.004965
8737 13:19:07.005053
8738 13:19:07.005147
8739 13:19:07.007992 [DramC_TX_OE_Calibration] TA2
8740 13:19:07.011112 Original DQ_B0 (3 6) =30, OEN = 27
8741 13:19:07.014928 Original DQ_B1 (3 6) =30, OEN = 27
8742 13:19:07.017887 24, 0x0, End_B0=24 End_B1=24
8743 13:19:07.017980 25, 0x0, End_B0=25 End_B1=25
8744 13:19:07.021469 26, 0x0, End_B0=26 End_B1=26
8745 13:19:07.024457 27, 0x0, End_B0=27 End_B1=27
8746 13:19:07.028269 28, 0x0, End_B0=28 End_B1=28
8747 13:19:07.028361 29, 0x0, End_B0=29 End_B1=29
8748 13:19:07.031290 30, 0x0, End_B0=30 End_B1=30
8749 13:19:07.034606 31, 0x4141, End_B0=30 End_B1=30
8750 13:19:07.037831 Byte0 end_step=30 best_step=27
8751 13:19:07.041328 Byte1 end_step=30 best_step=27
8752 13:19:07.044930 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 13:19:07.045029 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 13:19:07.045112
8755 13:19:07.045202
8756 13:19:07.055102 [DQSOSCAuto] RK0, (LSB)MR18= 0x15ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8757 13:19:07.058091 CH1 RK0: MR19=302, MR18=15FF
8758 13:19:07.061646 CH1_RK0: MR19=0x302, MR18=0x15FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8759 13:19:07.065310
8760 13:19:07.068310 ----->DramcWriteLeveling(PI) begin...
8761 13:19:07.068403 ==
8762 13:19:07.071452 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 13:19:07.075158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 13:19:07.075250 ==
8765 13:19:07.078214 Write leveling (Byte 0): 24 => 24
8766 13:19:07.081502 Write leveling (Byte 1): 25 => 25
8767 13:19:07.084938 DramcWriteLeveling(PI) end<-----
8768 13:19:07.085037
8769 13:19:07.085132 ==
8770 13:19:07.088128 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 13:19:07.091758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 13:19:07.091828 ==
8773 13:19:07.094870 [Gating] SW mode calibration
8774 13:19:07.102087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 13:19:07.108325 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 13:19:07.111553 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 13:19:07.115218 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 13:19:07.118313 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8779 13:19:07.125129 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8780 13:19:07.128086 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8781 13:19:07.131681 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 13:19:07.138507 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 13:19:07.141574 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 13:19:07.144987 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8785 13:19:07.151379 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8786 13:19:07.155086 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8787 13:19:07.158359 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8788 13:19:07.164916 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8789 13:19:07.168033 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 13:19:07.171718 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 13:19:07.178482 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 13:19:07.181958 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 13:19:07.184985 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 13:19:07.191817 1 6 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
8795 13:19:07.194886 1 6 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8796 13:19:07.198054 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 13:19:07.201645 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 13:19:07.208330 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 13:19:07.211720 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 13:19:07.215154 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 13:19:07.222048 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8802 13:19:07.225538 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 13:19:07.228575 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8804 13:19:07.235350 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8805 13:19:07.238293 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 13:19:07.241953 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 13:19:07.248832 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 13:19:07.251980 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 13:19:07.254932 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 13:19:07.261685 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 13:19:07.265085 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 13:19:07.268279 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 13:19:07.275402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 13:19:07.278471 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 13:19:07.282144 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 13:19:07.285132 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 13:19:07.292014 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 13:19:07.295105 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8819 13:19:07.298441 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8820 13:19:07.301833 Total UI for P1: 0, mck2ui 16
8821 13:19:07.305098 best dqsien dly found for B0: ( 1, 9, 6)
8822 13:19:07.311946 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 13:19:07.315018 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 13:19:07.318699 Total UI for P1: 0, mck2ui 16
8825 13:19:07.322109 best dqsien dly found for B1: ( 1, 9, 14)
8826 13:19:07.325468 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8827 13:19:07.328753 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8828 13:19:07.328828
8829 13:19:07.331664 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8830 13:19:07.335305 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8831 13:19:07.338850 [Gating] SW calibration Done
8832 13:19:07.338925 ==
8833 13:19:07.342022 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 13:19:07.345140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 13:19:07.348687 ==
8836 13:19:07.348763 RX Vref Scan: 0
8837 13:19:07.348822
8838 13:19:07.352341 RX Vref 0 -> 0, step: 1
8839 13:19:07.352417
8840 13:19:07.352475 RX Delay 0 -> 252, step: 8
8841 13:19:07.358973 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8842 13:19:07.361968 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8843 13:19:07.365386 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8844 13:19:07.369022 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8845 13:19:07.372088 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8846 13:19:07.378887 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8847 13:19:07.382076 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8848 13:19:07.385562 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8849 13:19:07.388965 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8850 13:19:07.392437 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8851 13:19:07.399252 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8852 13:19:07.402247 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8853 13:19:07.405842 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8854 13:19:07.408720 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8855 13:19:07.412167 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8856 13:19:07.419032 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8857 13:19:07.419109 ==
8858 13:19:07.422283 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 13:19:07.425483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 13:19:07.425560 ==
8861 13:19:07.425635 DQS Delay:
8862 13:19:07.428849 DQS0 = 0, DQS1 = 0
8863 13:19:07.428927 DQM Delay:
8864 13:19:07.432092 DQM0 = 132, DQM1 = 127
8865 13:19:07.432170 DQ Delay:
8866 13:19:07.435589 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8867 13:19:07.439235 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8868 13:19:07.442410 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8869 13:19:07.445911 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8870 13:19:07.445988
8871 13:19:07.446048
8872 13:19:07.448950 ==
8873 13:19:07.449027 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 13:19:07.455659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 13:19:07.455737 ==
8876 13:19:07.455797
8877 13:19:07.455852
8878 13:19:07.458830 TX Vref Scan disable
8879 13:19:07.458907 == TX Byte 0 ==
8880 13:19:07.462423 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8881 13:19:07.468760 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8882 13:19:07.468838 == TX Byte 1 ==
8883 13:19:07.472330 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8884 13:19:07.479169 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8885 13:19:07.479249 ==
8886 13:19:07.482258 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 13:19:07.485352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 13:19:07.485453 ==
8889 13:19:07.499533
8890 13:19:07.502592 TX Vref early break, caculate TX vref
8891 13:19:07.506128 TX Vref=16, minBit 8, minWin=22, winSum=383
8892 13:19:07.509245 TX Vref=18, minBit 0, minWin=24, winSum=396
8893 13:19:07.512862 TX Vref=20, minBit 6, minWin=24, winSum=403
8894 13:19:07.515874 TX Vref=22, minBit 8, minWin=24, winSum=410
8895 13:19:07.519555 TX Vref=24, minBit 5, minWin=25, winSum=420
8896 13:19:07.525941 TX Vref=26, minBit 0, minWin=26, winSum=428
8897 13:19:07.529264 TX Vref=28, minBit 0, minWin=26, winSum=432
8898 13:19:07.532695 TX Vref=30, minBit 0, minWin=26, winSum=430
8899 13:19:07.536094 TX Vref=32, minBit 0, minWin=25, winSum=426
8900 13:19:07.539429 TX Vref=34, minBit 0, minWin=24, winSum=414
8901 13:19:07.542855 TX Vref=36, minBit 0, minWin=24, winSum=408
8902 13:19:07.549762 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8903 13:19:07.549851
8904 13:19:07.552749 Final TX Range 0 Vref 28
8905 13:19:07.552861
8906 13:19:07.552950 ==
8907 13:19:07.556479 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 13:19:07.559509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 13:19:07.559622 ==
8910 13:19:07.559709
8911 13:19:07.559790
8912 13:19:07.563138 TX Vref Scan disable
8913 13:19:07.569759 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8914 13:19:07.569886 == TX Byte 0 ==
8915 13:19:07.572869 u2DelayCellOfst[0]=17 cells (5 PI)
8916 13:19:07.576346 u2DelayCellOfst[1]=10 cells (3 PI)
8917 13:19:07.579416 u2DelayCellOfst[2]=0 cells (0 PI)
8918 13:19:07.583067 u2DelayCellOfst[3]=7 cells (2 PI)
8919 13:19:07.586254 u2DelayCellOfst[4]=10 cells (3 PI)
8920 13:19:07.589356 u2DelayCellOfst[5]=17 cells (5 PI)
8921 13:19:07.592945 u2DelayCellOfst[6]=17 cells (5 PI)
8922 13:19:07.593062 u2DelayCellOfst[7]=3 cells (1 PI)
8923 13:19:07.599707 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8924 13:19:07.602645 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8925 13:19:07.602756 == TX Byte 1 ==
8926 13:19:07.606032 u2DelayCellOfst[8]=0 cells (0 PI)
8927 13:19:07.609769 u2DelayCellOfst[9]=3 cells (1 PI)
8928 13:19:07.612928 u2DelayCellOfst[10]=10 cells (3 PI)
8929 13:19:07.616470 u2DelayCellOfst[11]=3 cells (1 PI)
8930 13:19:07.619735 u2DelayCellOfst[12]=10 cells (3 PI)
8931 13:19:07.622782 u2DelayCellOfst[13]=14 cells (4 PI)
8932 13:19:07.626440 u2DelayCellOfst[14]=14 cells (4 PI)
8933 13:19:07.629487 u2DelayCellOfst[15]=14 cells (4 PI)
8934 13:19:07.633058 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8935 13:19:07.636365 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8936 13:19:07.639849 DramC Write-DBI on
8937 13:19:07.639962 ==
8938 13:19:07.643284 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 13:19:07.646126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 13:19:07.646233 ==
8941 13:19:07.646335
8942 13:19:07.649395
8943 13:19:07.649495 TX Vref Scan disable
8944 13:19:07.652848 == TX Byte 0 ==
8945 13:19:07.656106 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8946 13:19:07.659528 == TX Byte 1 ==
8947 13:19:07.663170 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8948 13:19:07.663253 DramC Write-DBI off
8949 13:19:07.663312
8950 13:19:07.666051 [DATLAT]
8951 13:19:07.666128 Freq=1600, CH1 RK1
8952 13:19:07.666188
8953 13:19:07.669702 DATLAT Default: 0xf
8954 13:19:07.669784 0, 0xFFFF, sum = 0
8955 13:19:07.672690 1, 0xFFFF, sum = 0
8956 13:19:07.672767 2, 0xFFFF, sum = 0
8957 13:19:07.676157 3, 0xFFFF, sum = 0
8958 13:19:07.676260 4, 0xFFFF, sum = 0
8959 13:19:07.679752 5, 0xFFFF, sum = 0
8960 13:19:07.679830 6, 0xFFFF, sum = 0
8961 13:19:07.682744 7, 0xFFFF, sum = 0
8962 13:19:07.682826 8, 0xFFFF, sum = 0
8963 13:19:07.685906 9, 0xFFFF, sum = 0
8964 13:19:07.689593 10, 0xFFFF, sum = 0
8965 13:19:07.689671 11, 0xFFFF, sum = 0
8966 13:19:07.692638 12, 0xFFFF, sum = 0
8967 13:19:07.692720 13, 0xFFFF, sum = 0
8968 13:19:07.696395 14, 0x0, sum = 1
8969 13:19:07.696464 15, 0x0, sum = 2
8970 13:19:07.699340 16, 0x0, sum = 3
8971 13:19:07.699408 17, 0x0, sum = 4
8972 13:19:07.699471 best_step = 15
8973 13:19:07.703046
8974 13:19:07.703113 ==
8975 13:19:07.706108 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 13:19:07.709683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 13:19:07.709755 ==
8978 13:19:07.709812 RX Vref Scan: 0
8979 13:19:07.709866
8980 13:19:07.712743 RX Vref 0 -> 0, step: 1
8981 13:19:07.712803
8982 13:19:07.716652 RX Delay 11 -> 252, step: 4
8983 13:19:07.719158 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8984 13:19:07.722524 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8985 13:19:07.729267 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8986 13:19:07.733061 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8987 13:19:07.736218 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8988 13:19:07.739682 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8989 13:19:07.742416 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8990 13:19:07.749366 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8991 13:19:07.752956 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8992 13:19:07.755832 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8993 13:19:07.759125 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8994 13:19:07.762562 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8995 13:19:07.769435 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8996 13:19:07.772493 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8997 13:19:07.776306 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8998 13:19:07.779168 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8999 13:19:07.779244 ==
9000 13:19:07.782702 Dram Type= 6, Freq= 0, CH_1, rank 1
9001 13:19:07.789381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9002 13:19:07.789457 ==
9003 13:19:07.789516 DQS Delay:
9004 13:19:07.792347 DQS0 = 0, DQS1 = 0
9005 13:19:07.792414 DQM Delay:
9006 13:19:07.792469 DQM0 = 129, DQM1 = 125
9007 13:19:07.796033 DQ Delay:
9008 13:19:07.798988 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9009 13:19:07.802722 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9010 13:19:07.805836 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =116
9011 13:19:07.809411 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9012 13:19:07.809478
9013 13:19:07.809533
9014 13:19:07.809608
9015 13:19:07.812906 [DramC_TX_OE_Calibration] TA2
9016 13:19:07.815828 Original DQ_B0 (3 6) =30, OEN = 27
9017 13:19:07.819616 Original DQ_B1 (3 6) =30, OEN = 27
9018 13:19:07.822500 24, 0x0, End_B0=24 End_B1=24
9019 13:19:07.822579 25, 0x0, End_B0=25 End_B1=25
9020 13:19:07.826043 26, 0x0, End_B0=26 End_B1=26
9021 13:19:07.829043 27, 0x0, End_B0=27 End_B1=27
9022 13:19:07.832610 28, 0x0, End_B0=28 End_B1=28
9023 13:19:07.835850 29, 0x0, End_B0=29 End_B1=29
9024 13:19:07.835930 30, 0x0, End_B0=30 End_B1=30
9025 13:19:07.839489 31, 0x4141, End_B0=30 End_B1=30
9026 13:19:07.842501 Byte0 end_step=30 best_step=27
9027 13:19:07.845784 Byte1 end_step=30 best_step=27
9028 13:19:07.849054 Byte0 TX OE(2T, 0.5T) = (3, 3)
9029 13:19:07.852460 Byte1 TX OE(2T, 0.5T) = (3, 3)
9030 13:19:07.852544
9031 13:19:07.852604
9032 13:19:07.859175 [DQSOSCAuto] RK1, (LSB)MR18= 0x1015, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
9033 13:19:07.862650 CH1 RK1: MR19=303, MR18=1015
9034 13:19:07.868949 CH1_RK1: MR19=0x303, MR18=0x1015, DQSOSC=399, MR23=63, INC=23, DEC=15
9035 13:19:07.872627 [RxdqsGatingPostProcess] freq 1600
9036 13:19:07.876003 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9037 13:19:07.879534 best DQS0 dly(2T, 0.5T) = (1, 1)
9038 13:19:07.882555 best DQS1 dly(2T, 0.5T) = (1, 1)
9039 13:19:07.886174 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9040 13:19:07.889279 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9041 13:19:07.893049 best DQS0 dly(2T, 0.5T) = (1, 1)
9042 13:19:07.895975 best DQS1 dly(2T, 0.5T) = (1, 1)
9043 13:19:07.899038 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9044 13:19:07.902747 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9045 13:19:07.905680 Pre-setting of DQS Precalculation
9046 13:19:07.909380 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9047 13:19:07.915980 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9048 13:19:07.922520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9049 13:19:07.922612
9050 13:19:07.922672
9051 13:19:07.926345 [Calibration Summary] 3200 Mbps
9052 13:19:07.929172 CH 0, Rank 0
9053 13:19:07.929252 SW Impedance : PASS
9054 13:19:07.932732 DUTY Scan : NO K
9055 13:19:07.935796 ZQ Calibration : PASS
9056 13:19:07.935867 Jitter Meter : NO K
9057 13:19:07.939365 CBT Training : PASS
9058 13:19:07.942814 Write leveling : PASS
9059 13:19:07.942906 RX DQS gating : PASS
9060 13:19:07.946003 RX DQ/DQS(RDDQC) : PASS
9061 13:19:07.946104 TX DQ/DQS : PASS
9062 13:19:07.949556 RX DATLAT : PASS
9063 13:19:07.952965 RX DQ/DQS(Engine): PASS
9064 13:19:07.953042 TX OE : PASS
9065 13:19:07.956376 All Pass.
9066 13:19:07.956451
9067 13:19:07.956511 CH 0, Rank 1
9068 13:19:07.959568 SW Impedance : PASS
9069 13:19:07.959669 DUTY Scan : NO K
9070 13:19:07.962965 ZQ Calibration : PASS
9071 13:19:07.966124 Jitter Meter : NO K
9072 13:19:07.966195 CBT Training : PASS
9073 13:19:07.969112 Write leveling : PASS
9074 13:19:07.972434 RX DQS gating : PASS
9075 13:19:07.972505 RX DQ/DQS(RDDQC) : PASS
9076 13:19:07.975920 TX DQ/DQS : PASS
9077 13:19:07.979604 RX DATLAT : PASS
9078 13:19:07.979702 RX DQ/DQS(Engine): PASS
9079 13:19:07.982395 TX OE : PASS
9080 13:19:07.982472 All Pass.
9081 13:19:07.982535
9082 13:19:07.986368 CH 1, Rank 0
9083 13:19:07.986447 SW Impedance : PASS
9084 13:19:07.989215 DUTY Scan : NO K
9085 13:19:07.989285 ZQ Calibration : PASS
9086 13:19:07.992767 Jitter Meter : NO K
9087 13:19:07.995917 CBT Training : PASS
9088 13:19:07.995986 Write leveling : PASS
9089 13:19:07.999451 RX DQS gating : PASS
9090 13:19:08.002545 RX DQ/DQS(RDDQC) : PASS
9091 13:19:08.002615 TX DQ/DQS : PASS
9092 13:19:08.006162 RX DATLAT : PASS
9093 13:19:08.009206 RX DQ/DQS(Engine): PASS
9094 13:19:08.009283 TX OE : PASS
9095 13:19:08.012946 All Pass.
9096 13:19:08.013041
9097 13:19:08.013131 CH 1, Rank 1
9098 13:19:08.016097 SW Impedance : PASS
9099 13:19:08.016191 DUTY Scan : NO K
9100 13:19:08.019687 ZQ Calibration : PASS
9101 13:19:08.022691 Jitter Meter : NO K
9102 13:19:08.022762 CBT Training : PASS
9103 13:19:08.026080 Write leveling : PASS
9104 13:19:08.026150 RX DQS gating : PASS
9105 13:19:08.029732 RX DQ/DQS(RDDQC) : PASS
9106 13:19:08.032674 TX DQ/DQS : PASS
9107 13:19:08.032741 RX DATLAT : PASS
9108 13:19:08.036349 RX DQ/DQS(Engine): PASS
9109 13:19:08.039323 TX OE : PASS
9110 13:19:08.039400 All Pass.
9111 13:19:08.039459
9112 13:19:08.042893 DramC Write-DBI on
9113 13:19:08.042969 PER_BANK_REFRESH: Hybrid Mode
9114 13:19:08.046370 TX_TRACKING: ON
9115 13:19:08.056299 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9116 13:19:08.062714 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9117 13:19:08.069417 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9118 13:19:08.072793 [FAST_K] Save calibration result to emmc
9119 13:19:08.076373 sync common calibartion params.
9120 13:19:08.079463 sync cbt_mode0:1, 1:1
9121 13:19:08.079547 dram_init: ddr_geometry: 2
9122 13:19:08.082956 dram_init: ddr_geometry: 2
9123 13:19:08.086295 dram_init: ddr_geometry: 2
9124 13:19:08.089708 0:dram_rank_size:100000000
9125 13:19:08.089784 1:dram_rank_size:100000000
9126 13:19:08.096055 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9127 13:19:08.099305 DFS_SHUFFLE_HW_MODE: ON
9128 13:19:08.102832 dramc_set_vcore_voltage set vcore to 725000
9129 13:19:08.102912 Read voltage for 1600, 0
9130 13:19:08.106518 Vio18 = 0
9131 13:19:08.106584 Vcore = 725000
9132 13:19:08.106639 Vdram = 0
9133 13:19:08.109618 Vddq = 0
9134 13:19:08.109692 Vmddr = 0
9135 13:19:08.112695 switch to 3200 Mbps bootup
9136 13:19:08.112774 [DramcRunTimeConfig]
9137 13:19:08.112829 PHYPLL
9138 13:19:08.116238 DPM_CONTROL_AFTERK: ON
9139 13:19:08.119829 PER_BANK_REFRESH: ON
9140 13:19:08.119897 REFRESH_OVERHEAD_REDUCTION: ON
9141 13:19:08.122749 CMD_PICG_NEW_MODE: OFF
9142 13:19:08.126551 XRTWTW_NEW_MODE: ON
9143 13:19:08.126661 XRTRTR_NEW_MODE: ON
9144 13:19:08.129348 TX_TRACKING: ON
9145 13:19:08.129423 RDSEL_TRACKING: OFF
9146 13:19:08.132860 DQS Precalculation for DVFS: ON
9147 13:19:08.132985 RX_TRACKING: OFF
9148 13:19:08.136041 HW_GATING DBG: ON
9149 13:19:08.136110 ZQCS_ENABLE_LP4: ON
9150 13:19:08.139385 RX_PICG_NEW_MODE: ON
9151 13:19:08.143156 TX_PICG_NEW_MODE: ON
9152 13:19:08.143229 ENABLE_RX_DCM_DPHY: ON
9153 13:19:08.146112 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9154 13:19:08.149630 DUMMY_READ_FOR_TRACKING: OFF
9155 13:19:08.153255 !!! SPM_CONTROL_AFTERK: OFF
9156 13:19:08.153330 !!! SPM could not control APHY
9157 13:19:08.156332 IMPEDANCE_TRACKING: ON
9158 13:19:08.159851 TEMP_SENSOR: ON
9159 13:19:08.159967 HW_SAVE_FOR_SR: OFF
9160 13:19:08.162788 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9161 13:19:08.166398 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9162 13:19:08.169348 Read ODT Tracking: ON
9163 13:19:08.169413 Refresh Rate DeBounce: ON
9164 13:19:08.173221 DFS_NO_QUEUE_FLUSH: ON
9165 13:19:08.176091 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9166 13:19:08.179413 ENABLE_DFS_RUNTIME_MRW: OFF
9167 13:19:08.179522 DDR_RESERVE_NEW_MODE: ON
9168 13:19:08.183110 MR_CBT_SWITCH_FREQ: ON
9169 13:19:08.186124 =========================
9170 13:19:08.203977 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9171 13:19:08.207498 dram_init: ddr_geometry: 2
9172 13:19:08.225817 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9173 13:19:08.228958 dram_init: dram init end (result: 0)
9174 13:19:08.235850 DRAM-K: Full calibration passed in 24572 msecs
9175 13:19:08.238912 MRC: failed to locate region type 0.
9176 13:19:08.238987 DRAM rank0 size:0x100000000,
9177 13:19:08.242384 DRAM rank1 size=0x100000000
9178 13:19:08.252617 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9179 13:19:08.259110 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9180 13:19:08.265540 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9181 13:19:08.272280 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9182 13:19:08.275694 DRAM rank0 size:0x100000000,
9183 13:19:08.278749 DRAM rank1 size=0x100000000
9184 13:19:08.278817 CBMEM:
9185 13:19:08.282359 IMD: root @ 0xfffff000 254 entries.
9186 13:19:08.285652 IMD: root @ 0xffffec00 62 entries.
9187 13:19:08.289382 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9188 13:19:08.292496 WARNING: RO_VPD is uninitialized or empty.
9189 13:19:08.298938 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9190 13:19:08.305588 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9191 13:19:08.318219 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9192 13:19:08.329619 BS: romstage times (exec / console): total (unknown) / 24071 ms
9193 13:19:08.329696
9194 13:19:08.329763
9195 13:19:08.339749 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9196 13:19:08.343335 ARM64: Exception handlers installed.
9197 13:19:08.346764 ARM64: Testing exception
9198 13:19:08.349653 ARM64: Done test exception
9199 13:19:08.349731 Enumerating buses...
9200 13:19:08.353309 Show all devs... Before device enumeration.
9201 13:19:08.356213 Root Device: enabled 1
9202 13:19:08.359814 CPU_CLUSTER: 0: enabled 1
9203 13:19:08.359893 CPU: 00: enabled 1
9204 13:19:08.363292 Compare with tree...
9205 13:19:08.363357 Root Device: enabled 1
9206 13:19:08.366541 CPU_CLUSTER: 0: enabled 1
9207 13:19:08.369904 CPU: 00: enabled 1
9208 13:19:08.370032 Root Device scanning...
9209 13:19:08.372879 scan_static_bus for Root Device
9210 13:19:08.376667 CPU_CLUSTER: 0 enabled
9211 13:19:08.379687 scan_static_bus for Root Device done
9212 13:19:08.383291 scan_bus: bus Root Device finished in 8 msecs
9213 13:19:08.383358 done
9214 13:19:08.389789 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9215 13:19:08.393182 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9216 13:19:08.399548 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9217 13:19:08.403001 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9218 13:19:08.406717 Allocating resources...
9219 13:19:08.406783 Reading resources...
9220 13:19:08.413463 Root Device read_resources bus 0 link: 0
9221 13:19:08.413555 DRAM rank0 size:0x100000000,
9222 13:19:08.416565 DRAM rank1 size=0x100000000
9223 13:19:08.419628 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9224 13:19:08.423064 CPU: 00 missing read_resources
9225 13:19:08.426740 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9226 13:19:08.433075 Root Device read_resources bus 0 link: 0 done
9227 13:19:08.433185 Done reading resources.
9228 13:19:08.439795 Show resources in subtree (Root Device)...After reading.
9229 13:19:08.443162 Root Device child on link 0 CPU_CLUSTER: 0
9230 13:19:08.446220 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 13:19:08.456178 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 13:19:08.456286 CPU: 00
9233 13:19:08.459733 Root Device assign_resources, bus 0 link: 0
9234 13:19:08.463229 CPU_CLUSTER: 0 missing set_resources
9235 13:19:08.466406 Root Device assign_resources, bus 0 link: 0 done
9236 13:19:08.469345 Done setting resources.
9237 13:19:08.476084 Show resources in subtree (Root Device)...After assigning values.
9238 13:19:08.479711 Root Device child on link 0 CPU_CLUSTER: 0
9239 13:19:08.482717 CPU_CLUSTER: 0 child on link 0 CPU: 00
9240 13:19:08.492743 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9241 13:19:08.492822 CPU: 00
9242 13:19:08.496293 Done allocating resources.
9243 13:19:08.499684 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9244 13:19:08.503095 Enabling resources...
9245 13:19:08.503170 done.
9246 13:19:08.509601 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9247 13:19:08.509678 Initializing devices...
9248 13:19:08.512697 Root Device init
9249 13:19:08.512799 init hardware done!
9250 13:19:08.516389 0x00000018: ctrlr->caps
9251 13:19:08.519509 52.000 MHz: ctrlr->f_max
9252 13:19:08.519588 0.400 MHz: ctrlr->f_min
9253 13:19:08.522650 0x40ff8080: ctrlr->voltages
9254 13:19:08.522728 sclk: 390625
9255 13:19:08.526073 Bus Width = 1
9256 13:19:08.526153 sclk: 390625
9257 13:19:08.526212 Bus Width = 1
9258 13:19:08.529569 Early init status = 3
9259 13:19:08.532574 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9260 13:19:08.537367 in-header: 03 fc 00 00 01 00 00 00
9261 13:19:08.540894 in-data: 00
9262 13:19:08.543927 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9263 13:19:08.548673 in-header: 03 fd 00 00 00 00 00 00
9264 13:19:08.551873 in-data:
9265 13:19:08.554831 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9266 13:19:08.558369 in-header: 03 fc 00 00 01 00 00 00
9267 13:19:08.562243 in-data: 00
9268 13:19:08.565586 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9269 13:19:08.569759 in-header: 03 fd 00 00 00 00 00 00
9270 13:19:08.573480 in-data:
9271 13:19:08.576416 [SSUSB] Setting up USB HOST controller...
9272 13:19:08.579839 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9273 13:19:08.583134 [SSUSB] phy power-on done.
9274 13:19:08.586837 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9275 13:19:08.593389 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9276 13:19:08.596512 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9277 13:19:08.603029 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9278 13:19:08.609910 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9279 13:19:08.616370 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9280 13:19:08.623138 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9281 13:19:08.629956 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9282 13:19:08.630027 SPM: binary array size = 0x9dc
9283 13:19:08.636646 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9284 13:19:08.643136 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9285 13:19:08.649881 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9286 13:19:08.653357 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9287 13:19:08.656330 configure_display: Starting display init
9288 13:19:08.693092 anx7625_power_on_init: Init interface.
9289 13:19:08.696679 anx7625_disable_pd_protocol: Disabled PD feature.
9290 13:19:08.699724 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9291 13:19:08.727759 anx7625_start_dp_work: Secure OCM version=00
9292 13:19:08.730723 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9293 13:19:08.745682 sp_tx_get_edid_block: EDID Block = 1
9294 13:19:08.848053 Extracted contents:
9295 13:19:08.851527 header: 00 ff ff ff ff ff ff 00
9296 13:19:08.855145 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9297 13:19:08.858220 version: 01 04
9298 13:19:08.861811 basic params: 95 1f 11 78 0a
9299 13:19:08.864809 chroma info: 76 90 94 55 54 90 27 21 50 54
9300 13:19:08.867916 established: 00 00 00
9301 13:19:08.874516 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9302 13:19:08.878144 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9303 13:19:08.884802 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9304 13:19:08.891120 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9305 13:19:08.898193 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9306 13:19:08.900943 extensions: 00
9307 13:19:08.901012 checksum: fb
9308 13:19:08.901082
9309 13:19:08.904468 Manufacturer: IVO Model 57d Serial Number 0
9310 13:19:08.907754 Made week 0 of 2020
9311 13:19:08.907822 EDID version: 1.4
9312 13:19:08.911579 Digital display
9313 13:19:08.914358 6 bits per primary color channel
9314 13:19:08.914430 DisplayPort interface
9315 13:19:08.917914 Maximum image size: 31 cm x 17 cm
9316 13:19:08.920974 Gamma: 220%
9317 13:19:08.921042 Check DPMS levels
9318 13:19:08.924643 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9319 13:19:08.927585 First detailed timing is preferred timing
9320 13:19:08.931238 Established timings supported:
9321 13:19:08.934354 Standard timings supported:
9322 13:19:08.934429 Detailed timings
9323 13:19:08.941241 Hex of detail: 383680a07038204018303c0035ae10000019
9324 13:19:08.944469 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9325 13:19:08.951408 0780 0798 07c8 0820 hborder 0
9326 13:19:08.954324 0438 043b 0447 0458 vborder 0
9327 13:19:08.958107 -hsync -vsync
9328 13:19:08.958174 Did detailed timing
9329 13:19:08.961062 Hex of detail: 000000000000000000000000000000000000
9330 13:19:08.964599 Manufacturer-specified data, tag 0
9331 13:19:08.970860 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9332 13:19:08.970928 ASCII string: InfoVision
9333 13:19:08.977961 Hex of detail: 000000fe00523134304e574635205248200a
9334 13:19:08.981011 ASCII string: R140NWF5 RH
9335 13:19:08.981080 Checksum
9336 13:19:08.981179 Checksum: 0xfb (valid)
9337 13:19:08.987599 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9338 13:19:08.990803 DSI data_rate: 832800000 bps
9339 13:19:08.994453 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9340 13:19:09.001004 anx7625_parse_edid: pixelclock(138800).
9341 13:19:09.004286 hactive(1920), hsync(48), hfp(24), hbp(88)
9342 13:19:09.007790 vactive(1080), vsync(12), vfp(3), vbp(17)
9343 13:19:09.010668 anx7625_dsi_config: config dsi.
9344 13:19:09.017477 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9345 13:19:09.030208 anx7625_dsi_config: success to config DSI
9346 13:19:09.033860 anx7625_dp_start: MIPI phy setup OK.
9347 13:19:09.036807 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9348 13:19:09.040453 mtk_ddp_mode_set invalid vrefresh 60
9349 13:19:09.043425 main_disp_path_setup
9350 13:19:09.043495 ovl_layer_smi_id_en
9351 13:19:09.047016 ovl_layer_smi_id_en
9352 13:19:09.047082 ccorr_config
9353 13:19:09.047137 aal_config
9354 13:19:09.050122 gamma_config
9355 13:19:09.050210 postmask_config
9356 13:19:09.053688 dither_config
9357 13:19:09.057018 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9358 13:19:09.063262 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9359 13:19:09.066770 Root Device init finished in 551 msecs
9360 13:19:09.066847 CPU_CLUSTER: 0 init
9361 13:19:09.076704 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9362 13:19:09.080381 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9363 13:19:09.083373 APU_MBOX 0x190000b0 = 0x10001
9364 13:19:09.086436 APU_MBOX 0x190001b0 = 0x10001
9365 13:19:09.090000 APU_MBOX 0x190005b0 = 0x10001
9366 13:19:09.093663 APU_MBOX 0x190006b0 = 0x10001
9367 13:19:09.096483 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9368 13:19:09.109401 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9369 13:19:09.121749 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9370 13:19:09.128405 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9371 13:19:09.140086 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9372 13:19:09.149289 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9373 13:19:09.152295 CPU_CLUSTER: 0 init finished in 81 msecs
9374 13:19:09.155948 Devices initialized
9375 13:19:09.158986 Show all devs... After init.
9376 13:19:09.159080 Root Device: enabled 1
9377 13:19:09.162738 CPU_CLUSTER: 0: enabled 1
9378 13:19:09.165596 CPU: 00: enabled 1
9379 13:19:09.169126 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9380 13:19:09.172631 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9381 13:19:09.175427 ELOG: NV offset 0x57f000 size 0x1000
9382 13:19:09.182072 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9383 13:19:09.189173 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9384 13:19:09.192241 ELOG: Event(17) added with size 13 at 2024-07-18 13:19:09 UTC
9385 13:19:09.195420 out: cmd=0x121: 03 db 21 01 00 00 00 00
9386 13:19:09.200163 in-header: 03 85 00 00 2c 00 00 00
9387 13:19:09.213085 in-data: b8 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9388 13:19:09.220014 ELOG: Event(A1) added with size 10 at 2024-07-18 13:19:09 UTC
9389 13:19:09.226524 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9390 13:19:09.233051 ELOG: Event(A0) added with size 9 at 2024-07-18 13:19:09 UTC
9391 13:19:09.236684 elog_add_boot_reason: Logged dev mode boot
9392 13:19:09.239621 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9393 13:19:09.243213 Finalize devices...
9394 13:19:09.243290 Devices finalized
9395 13:19:09.249794 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9396 13:19:09.253093 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9397 13:19:09.256442 in-header: 03 07 00 00 08 00 00 00
9398 13:19:09.259618 in-data: aa e4 47 04 13 02 00 00
9399 13:19:09.263255 Chrome EC: UHEPI supported
9400 13:19:09.269885 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9401 13:19:09.272921 in-header: 03 a9 00 00 08 00 00 00
9402 13:19:09.276080 in-data: 84 60 60 08 00 00 00 00
9403 13:19:09.279727 ELOG: Event(91) added with size 10 at 2024-07-18 13:19:09 UTC
9404 13:19:09.286100 Chrome EC: clear events_b mask to 0x0000000020004000
9405 13:19:09.292965 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9406 13:19:09.296636 in-header: 03 fd 00 00 00 00 00 00
9407 13:19:09.299937 in-data:
9408 13:19:09.303040 BS: BS_WRITE_TABLES entry times (exec / console): 4 / 46 ms
9409 13:19:09.306728 Writing coreboot table at 0xffe64000
9410 13:19:09.313123 0. 000000000010a000-0000000000113fff: RAMSTAGE
9411 13:19:09.316534 1. 0000000040000000-00000000400fffff: RAM
9412 13:19:09.320136 2. 0000000040100000-000000004032afff: RAMSTAGE
9413 13:19:09.323198 3. 000000004032b000-00000000545fffff: RAM
9414 13:19:09.326831 4. 0000000054600000-000000005465ffff: BL31
9415 13:19:09.330102 5. 0000000054660000-00000000ffe63fff: RAM
9416 13:19:09.336453 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9417 13:19:09.339489 7. 0000000100000000-000000023fffffff: RAM
9418 13:19:09.343217 Passing 5 GPIOs to payload:
9419 13:19:09.346199 NAME | PORT | POLARITY | VALUE
9420 13:19:09.353374 EC in RW | 0x000000aa | low | undefined
9421 13:19:09.356732 EC interrupt | 0x00000005 | low | undefined
9422 13:19:09.359575 TPM interrupt | 0x000000ab | high | undefined
9423 13:19:09.366543 SD card detect | 0x00000011 | high | undefined
9424 13:19:09.370060 speaker enable | 0x00000093 | high | undefined
9425 13:19:09.373094 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9426 13:19:09.376190 in-header: 03 f9 00 00 02 00 00 00
9427 13:19:09.379904 in-data: 02 00
9428 13:19:09.382880 ADC[4]: Raw value=900590 ID=7
9429 13:19:09.382957 ADC[3]: Raw value=213336 ID=1
9430 13:19:09.386163 RAM Code: 0x71
9431 13:19:09.389705 ADC[6]: Raw value=74557 ID=0
9432 13:19:09.389780 ADC[5]: Raw value=211860 ID=1
9433 13:19:09.393342 SKU Code: 0x1
9434 13:19:09.399843 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 91f5
9435 13:19:09.399919 coreboot table: 964 bytes.
9436 13:19:09.403392 IMD ROOT 0. 0xfffff000 0x00001000
9437 13:19:09.406510 IMD SMALL 1. 0xffffe000 0x00001000
9438 13:19:09.409761 RO MCACHE 2. 0xffffc000 0x00001104
9439 13:19:09.412810 CONSOLE 3. 0xfff7c000 0x00080000
9440 13:19:09.416473 FMAP 4. 0xfff7b000 0x00000452
9441 13:19:09.419946 TIME STAMP 5. 0xfff7a000 0x00000910
9442 13:19:09.423255 VBOOT WORK 6. 0xfff66000 0x00014000
9443 13:19:09.426738 RAMOOPS 7. 0xffe66000 0x00100000
9444 13:19:09.429778 COREBOOT 8. 0xffe64000 0x00002000
9445 13:19:09.433280 IMD small region:
9446 13:19:09.436602 IMD ROOT 0. 0xffffec00 0x00000400
9447 13:19:09.439869 VPD 1. 0xffffeb80 0x0000006c
9448 13:19:09.443425 MMC STATUS 2. 0xffffeb60 0x00000004
9449 13:19:09.446473 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9450 13:19:09.453103 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9451 13:19:09.493527 read SPI 0x3990ec 0x4f1b0: 34857 us, 9295 KB/s, 74.360 Mbps
9452 13:19:09.497266 Checking segment from ROM address 0x40100000
9453 13:19:09.500256 Checking segment from ROM address 0x4010001c
9454 13:19:09.506895 Loading segment from ROM address 0x40100000
9455 13:19:09.506973 code (compression=0)
9456 13:19:09.513499 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9457 13:19:09.523763 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9458 13:19:09.523844 it's not compressed!
9459 13:19:09.530518 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9460 13:19:09.534007 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9461 13:19:09.554405 Loading segment from ROM address 0x4010001c
9462 13:19:09.554484 Entry Point 0x80000000
9463 13:19:09.557298 Loaded segments
9464 13:19:09.560846 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9465 13:19:09.567295 Jumping to boot code at 0x80000000(0xffe64000)
9466 13:19:09.574127 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9467 13:19:09.580689 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9468 13:19:09.588466 read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps
9469 13:19:09.592124 Checking segment from ROM address 0x40100000
9470 13:19:09.595065 Checking segment from ROM address 0x4010001c
9471 13:19:09.601683 Loading segment from ROM address 0x40100000
9472 13:19:09.601760 code (compression=1)
9473 13:19:09.608795 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9474 13:19:09.618436 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9475 13:19:09.618513 using LZMA
9476 13:19:09.626788 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9477 13:19:09.633509 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9478 13:19:09.636785 Loading segment from ROM address 0x4010001c
9479 13:19:09.636888 Entry Point 0x54601000
9480 13:19:09.640087 Loaded segments
9481 13:19:09.643364 NOTICE: MT8192 bl31_setup
9482 13:19:09.650446 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9483 13:19:09.653876 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9484 13:19:09.657030 WARNING: region 0:
9485 13:19:09.660307 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 13:19:09.660413 WARNING: region 1:
9487 13:19:09.667267 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9488 13:19:09.670237 WARNING: region 2:
9489 13:19:09.673857 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9490 13:19:09.676950 WARNING: region 3:
9491 13:19:09.680665 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 13:19:09.683832 WARNING: region 4:
9493 13:19:09.690498 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 13:19:09.690593 WARNING: region 5:
9495 13:19:09.694073 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 13:19:09.696797 WARNING: region 6:
9497 13:19:09.700472 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 13:19:09.703922 WARNING: region 7:
9499 13:19:09.706873 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 13:19:09.713399 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9501 13:19:09.717103 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9502 13:19:09.720284 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9503 13:19:09.726903 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9504 13:19:09.730631 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9505 13:19:09.733660 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9506 13:19:09.740138 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9507 13:19:09.743893 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9508 13:19:09.750338 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9509 13:19:09.753708 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9510 13:19:09.757278 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9511 13:19:09.764137 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9512 13:19:09.766701 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9513 13:19:09.770051 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9514 13:19:09.776784 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9515 13:19:09.780297 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9516 13:19:09.786950 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9517 13:19:09.790083 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9518 13:19:09.793687 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9519 13:19:09.800438 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9520 13:19:09.803906 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9521 13:19:09.806706 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9522 13:19:09.813899 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9523 13:19:09.816846 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9524 13:19:09.823447 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9525 13:19:09.826997 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9526 13:19:09.829958 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9527 13:19:09.836700 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9528 13:19:09.840491 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9529 13:19:09.847019 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9530 13:19:09.850309 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9531 13:19:09.853165 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9532 13:19:09.859931 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9533 13:19:09.863255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9534 13:19:09.866852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9535 13:19:09.869919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9536 13:19:09.876554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9537 13:19:09.880031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9538 13:19:09.883381 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9539 13:19:09.886639 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9540 13:19:09.893347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9541 13:19:09.896365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9542 13:19:09.900023 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9543 13:19:09.903106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9544 13:19:09.909796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9545 13:19:09.913301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9546 13:19:09.916151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9547 13:19:09.920033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9548 13:19:09.926441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9549 13:19:09.929569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9550 13:19:09.936381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9551 13:19:09.940172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9552 13:19:09.946390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9553 13:19:09.950067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9554 13:19:09.953565 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9555 13:19:09.959888 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9556 13:19:09.962838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9557 13:19:09.969807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9558 13:19:09.973073 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9559 13:19:09.979771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9560 13:19:09.983330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9561 13:19:09.989544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9562 13:19:09.993042 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9563 13:19:09.996026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9564 13:19:10.002573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9565 13:19:10.005966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9566 13:19:10.012636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9567 13:19:10.016569 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9568 13:19:10.022557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9569 13:19:10.026165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9570 13:19:10.029570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9571 13:19:10.036033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9572 13:19:10.039587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9573 13:19:10.046450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9574 13:19:10.049471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9575 13:19:10.056140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9576 13:19:10.059114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9577 13:19:10.066243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9578 13:19:10.069070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9579 13:19:10.072645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9580 13:19:10.079068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9581 13:19:10.082430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9582 13:19:10.088949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9583 13:19:10.092730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9584 13:19:10.098938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9585 13:19:10.101985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9586 13:19:10.109321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9587 13:19:10.111982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9588 13:19:10.115294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9589 13:19:10.122335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9590 13:19:10.125480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9591 13:19:10.132316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9592 13:19:10.135289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9593 13:19:10.142114 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9594 13:19:10.145313 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9595 13:19:10.149124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9596 13:19:10.155588 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9597 13:19:10.158664 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9598 13:19:10.162267 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9599 13:19:10.165643 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9600 13:19:10.172110 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9601 13:19:10.175622 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9602 13:19:10.182669 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9603 13:19:10.185413 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9604 13:19:10.188726 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9605 13:19:10.195651 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9606 13:19:10.198870 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9607 13:19:10.205445 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9608 13:19:10.208519 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9609 13:19:10.212058 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9610 13:19:10.218567 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9611 13:19:10.222065 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9612 13:19:10.228665 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9613 13:19:10.231996 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9614 13:19:10.235294 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9615 13:19:10.242109 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9616 13:19:10.245097 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9617 13:19:10.248701 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9618 13:19:10.255530 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9619 13:19:10.258340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9620 13:19:10.261664 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9621 13:19:10.265425 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9622 13:19:10.271850 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9623 13:19:10.275546 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9624 13:19:10.278305 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9625 13:19:10.284900 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9626 13:19:10.288543 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9627 13:19:10.291481 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9628 13:19:10.298544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9629 13:19:10.302016 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9630 13:19:10.308669 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9631 13:19:10.311711 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9632 13:19:10.315528 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9633 13:19:10.321862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9634 13:19:10.325059 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9635 13:19:10.331661 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9636 13:19:10.335419 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9637 13:19:10.338333 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9638 13:19:10.345238 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9639 13:19:10.348219 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9640 13:19:10.351690 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9641 13:19:10.358392 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9642 13:19:10.361958 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9643 13:19:10.368094 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9644 13:19:10.371491 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9645 13:19:10.375107 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9646 13:19:10.381939 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9647 13:19:10.384773 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9648 13:19:10.391941 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9649 13:19:10.394998 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9650 13:19:10.398503 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9651 13:19:10.405083 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9652 13:19:10.408281 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9653 13:19:10.411955 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9654 13:19:10.418072 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9655 13:19:10.421850 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9656 13:19:10.428438 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9657 13:19:10.431948 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9658 13:19:10.435026 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9659 13:19:10.441802 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9660 13:19:10.444926 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9661 13:19:10.451670 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9662 13:19:10.455138 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9663 13:19:10.458399 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9664 13:19:10.464789 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9665 13:19:10.468314 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9666 13:19:10.471467 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9667 13:19:10.478156 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9668 13:19:10.481727 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9669 13:19:10.488237 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9670 13:19:10.491438 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9671 13:19:10.495243 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9672 13:19:10.501896 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9673 13:19:10.504950 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9674 13:19:10.511703 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9675 13:19:10.514925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9676 13:19:10.518248 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9677 13:19:10.524959 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9678 13:19:10.528050 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9679 13:19:10.534550 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9680 13:19:10.538128 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9681 13:19:10.541272 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9682 13:19:10.547890 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9683 13:19:10.551509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9684 13:19:10.558291 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9685 13:19:10.561228 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9686 13:19:10.564899 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9687 13:19:10.571136 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9688 13:19:10.574919 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9689 13:19:10.581350 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9690 13:19:10.584972 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9691 13:19:10.587743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9692 13:19:10.594262 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9693 13:19:10.597841 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9694 13:19:10.604393 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9695 13:19:10.607692 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9696 13:19:10.611360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9697 13:19:10.618121 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9698 13:19:10.620997 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9699 13:19:10.627633 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9700 13:19:10.631284 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9701 13:19:10.634418 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9702 13:19:10.640940 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9703 13:19:10.644049 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9704 13:19:10.650775 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9705 13:19:10.654337 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9706 13:19:10.661126 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9707 13:19:10.664130 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9708 13:19:10.667829 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9709 13:19:10.674612 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9710 13:19:10.677708 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9711 13:19:10.684228 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9712 13:19:10.687381 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9713 13:19:10.693999 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9714 13:19:10.697336 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9715 13:19:10.700664 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9716 13:19:10.707478 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9717 13:19:10.710790 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9718 13:19:10.717501 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9719 13:19:10.720783 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9720 13:19:10.724476 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9721 13:19:10.730898 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9722 13:19:10.734311 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9723 13:19:10.740888 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9724 13:19:10.744407 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9725 13:19:10.747516 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9726 13:19:10.754274 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9727 13:19:10.757306 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9728 13:19:10.763960 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9729 13:19:10.767633 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9730 13:19:10.770635 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9731 13:19:10.774226 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9732 13:19:10.777309 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9733 13:19:10.784103 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9734 13:19:10.787684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9735 13:19:10.793762 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9736 13:19:10.797247 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9737 13:19:10.800559 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9738 13:19:10.807276 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9739 13:19:10.810714 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9740 13:19:10.814139 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9741 13:19:10.821005 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9742 13:19:10.823763 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9743 13:19:10.827359 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9744 13:19:10.833670 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9745 13:19:10.837332 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9746 13:19:10.843964 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9747 13:19:10.847262 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9748 13:19:10.850661 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9749 13:19:10.857408 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9750 13:19:10.860455 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9751 13:19:10.864084 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9752 13:19:10.870692 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9753 13:19:10.873901 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9754 13:19:10.876877 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9755 13:19:10.883710 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9756 13:19:10.887364 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9757 13:19:10.893931 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9758 13:19:10.896928 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9759 13:19:10.900618 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9760 13:19:10.907370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9761 13:19:10.910248 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9762 13:19:10.913922 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9763 13:19:10.920721 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9764 13:19:10.923542 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9765 13:19:10.926817 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9766 13:19:10.933975 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9767 13:19:10.936884 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9768 13:19:10.940644 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9769 13:19:10.946837 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9770 13:19:10.950273 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9771 13:19:10.953744 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9772 13:19:10.956948 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9773 13:19:10.960217 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9774 13:19:10.967157 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9775 13:19:10.970239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9776 13:19:10.973862 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9777 13:19:10.980573 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9778 13:19:10.983502 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9779 13:19:10.987118 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9780 13:19:10.990274 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9781 13:19:10.996820 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9782 13:19:11.000484 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9783 13:19:11.003454 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9784 13:19:11.010102 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9785 13:19:11.013751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9786 13:19:11.020343 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9787 13:19:11.023801 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9788 13:19:11.030401 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9789 13:19:11.033707 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9790 13:19:11.036960 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9791 13:19:11.043323 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9792 13:19:11.046813 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9793 13:19:11.053837 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9794 13:19:11.056796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9795 13:19:11.060106 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9796 13:19:11.066740 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9797 13:19:11.070137 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9798 13:19:11.076636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9799 13:19:11.080040 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9800 13:19:11.083641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9801 13:19:11.089646 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9802 13:19:11.093454 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9803 13:19:11.100074 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9804 13:19:11.103141 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9805 13:19:11.106734 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9806 13:19:11.113383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9807 13:19:11.116466 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9808 13:19:11.123006 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9809 13:19:11.126618 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9810 13:19:11.133045 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9811 13:19:11.136166 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9812 13:19:11.139891 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9813 13:19:11.146645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9814 13:19:11.149509 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9815 13:19:11.156123 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9816 13:19:11.159850 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9817 13:19:11.162944 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9818 13:19:11.169514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9819 13:19:11.172648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9820 13:19:11.179362 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9821 13:19:11.182911 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9822 13:19:11.186533 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9823 13:19:11.192659 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9824 13:19:11.196234 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9825 13:19:11.202927 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9826 13:19:11.206005 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9827 13:19:11.212605 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9828 13:19:11.216383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9829 13:19:11.219491 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9830 13:19:11.226041 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9831 13:19:11.229540 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9832 13:19:11.232604 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9833 13:19:11.239160 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9834 13:19:11.242807 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9835 13:19:11.249292 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9836 13:19:11.252911 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9837 13:19:11.256330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9838 13:19:11.262673 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9839 13:19:11.266274 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9840 13:19:11.272741 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9841 13:19:11.275775 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9842 13:19:11.282457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9843 13:19:11.286042 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9844 13:19:11.289770 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9845 13:19:11.296079 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9846 13:19:11.299116 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9847 13:19:11.305459 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9848 13:19:11.308981 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9849 13:19:11.312261 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9850 13:19:11.318896 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9851 13:19:11.322578 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9852 13:19:11.329343 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9853 13:19:11.332105 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9854 13:19:11.335567 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9855 13:19:11.342474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9856 13:19:11.345494 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9857 13:19:11.352233 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9858 13:19:11.355310 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9859 13:19:11.362449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9860 13:19:11.365950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9861 13:19:11.368696 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9862 13:19:11.375537 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9863 13:19:11.378871 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9864 13:19:11.385847 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9865 13:19:11.388847 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9866 13:19:11.395300 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9867 13:19:11.399050 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9868 13:19:11.405376 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9869 13:19:11.408512 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9870 13:19:11.412041 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9871 13:19:11.418787 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9872 13:19:11.421923 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9873 13:19:11.428738 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9874 13:19:11.431791 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9875 13:19:11.438487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9876 13:19:11.442006 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9877 13:19:11.445511 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9878 13:19:11.452089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9879 13:19:11.455306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9880 13:19:11.461874 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9881 13:19:11.464930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9882 13:19:11.472189 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9883 13:19:11.475055 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9884 13:19:11.481977 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9885 13:19:11.485105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9886 13:19:11.488400 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9887 13:19:11.494907 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9888 13:19:11.498391 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9889 13:19:11.505190 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9890 13:19:11.508245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9891 13:19:11.515328 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9892 13:19:11.518619 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9893 13:19:11.521842 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9894 13:19:11.528520 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9895 13:19:11.531518 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9896 13:19:11.538193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9897 13:19:11.541919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9898 13:19:11.548452 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9899 13:19:11.551709 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9900 13:19:11.555345 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9901 13:19:11.561459 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9902 13:19:11.565093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9903 13:19:11.568222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9904 13:19:11.574824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9905 13:19:11.578437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9906 13:19:11.585064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9907 13:19:11.588533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9908 13:19:11.594941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9909 13:19:11.598302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9910 13:19:11.604935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9911 13:19:11.608211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9912 13:19:11.614870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9913 13:19:11.618477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9914 13:19:11.625192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9915 13:19:11.628583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9916 13:19:11.634991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9917 13:19:11.638282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9918 13:19:11.644920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9919 13:19:11.648552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9920 13:19:11.655137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9921 13:19:11.658520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9922 13:19:11.661553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9923 13:19:11.668293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9924 13:19:11.671805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9925 13:19:11.678292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9926 13:19:11.681797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9927 13:19:11.688569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9928 13:19:11.695305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9929 13:19:11.698105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9930 13:19:11.704940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9931 13:19:11.708817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9932 13:19:11.714743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9933 13:19:11.718113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9934 13:19:11.721582 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9935 13:19:11.724982 INFO: [APUAPC] vio 0
9936 13:19:11.728011 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9937 13:19:11.734650 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9938 13:19:11.738098 INFO: [APUAPC] D0_APC_0: 0x400510
9939 13:19:11.741327 INFO: [APUAPC] D0_APC_1: 0x0
9940 13:19:11.745082 INFO: [APUAPC] D0_APC_2: 0x1540
9941 13:19:11.745181 INFO: [APUAPC] D0_APC_3: 0x0
9942 13:19:11.747853 INFO: [APUAPC] D1_APC_0: 0xffffffff
9943 13:19:11.751902 INFO: [APUAPC] D1_APC_1: 0xffffffff
9944 13:19:11.754914 INFO: [APUAPC] D1_APC_2: 0x3fffff
9945 13:19:11.757951 INFO: [APUAPC] D1_APC_3: 0x0
9946 13:19:11.761435 INFO: [APUAPC] D2_APC_0: 0xffffffff
9947 13:19:11.764886 INFO: [APUAPC] D2_APC_1: 0xffffffff
9948 13:19:11.767942 INFO: [APUAPC] D2_APC_2: 0x3fffff
9949 13:19:11.771601 INFO: [APUAPC] D2_APC_3: 0x0
9950 13:19:11.774657 INFO: [APUAPC] D3_APC_0: 0xffffffff
9951 13:19:11.778151 INFO: [APUAPC] D3_APC_1: 0xffffffff
9952 13:19:11.781261 INFO: [APUAPC] D3_APC_2: 0x3fffff
9953 13:19:11.784856 INFO: [APUAPC] D3_APC_3: 0x0
9954 13:19:11.788122 INFO: [APUAPC] D4_APC_0: 0xffffffff
9955 13:19:11.791688 INFO: [APUAPC] D4_APC_1: 0xffffffff
9956 13:19:11.794709 INFO: [APUAPC] D4_APC_2: 0x3fffff
9957 13:19:11.798500 INFO: [APUAPC] D4_APC_3: 0x0
9958 13:19:11.801192 INFO: [APUAPC] D5_APC_0: 0xffffffff
9959 13:19:11.804858 INFO: [APUAPC] D5_APC_1: 0xffffffff
9960 13:19:11.807814 INFO: [APUAPC] D5_APC_2: 0x3fffff
9961 13:19:11.811164 INFO: [APUAPC] D5_APC_3: 0x0
9962 13:19:11.814614 INFO: [APUAPC] D6_APC_0: 0xffffffff
9963 13:19:11.818372 INFO: [APUAPC] D6_APC_1: 0xffffffff
9964 13:19:11.821175 INFO: [APUAPC] D6_APC_2: 0x3fffff
9965 13:19:11.824475 INFO: [APUAPC] D6_APC_3: 0x0
9966 13:19:11.828351 INFO: [APUAPC] D7_APC_0: 0xffffffff
9967 13:19:11.831713 INFO: [APUAPC] D7_APC_1: 0xffffffff
9968 13:19:11.834724 INFO: [APUAPC] D7_APC_2: 0x3fffff
9969 13:19:11.838362 INFO: [APUAPC] D7_APC_3: 0x0
9970 13:19:11.841365 INFO: [APUAPC] D8_APC_0: 0xffffffff
9971 13:19:11.844413 INFO: [APUAPC] D8_APC_1: 0xffffffff
9972 13:19:11.847873 INFO: [APUAPC] D8_APC_2: 0x3fffff
9973 13:19:11.851252 INFO: [APUAPC] D8_APC_3: 0x0
9974 13:19:11.854898 INFO: [APUAPC] D9_APC_0: 0xffffffff
9975 13:19:11.858214 INFO: [APUAPC] D9_APC_1: 0xffffffff
9976 13:19:11.861561 INFO: [APUAPC] D9_APC_2: 0x3fffff
9977 13:19:11.864466 INFO: [APUAPC] D9_APC_3: 0x0
9978 13:19:11.867961 INFO: [APUAPC] D10_APC_0: 0xffffffff
9979 13:19:11.871430 INFO: [APUAPC] D10_APC_1: 0xffffffff
9980 13:19:11.874505 INFO: [APUAPC] D10_APC_2: 0x3fffff
9981 13:19:11.878395 INFO: [APUAPC] D10_APC_3: 0x0
9982 13:19:11.881970 INFO: [APUAPC] D11_APC_0: 0xffffffff
9983 13:19:11.884801 INFO: [APUAPC] D11_APC_1: 0xffffffff
9984 13:19:11.888000 INFO: [APUAPC] D11_APC_2: 0x3fffff
9985 13:19:11.891565 INFO: [APUAPC] D11_APC_3: 0x0
9986 13:19:11.894631 INFO: [APUAPC] D12_APC_0: 0xffffffff
9987 13:19:11.898303 INFO: [APUAPC] D12_APC_1: 0xffffffff
9988 13:19:11.901379 INFO: [APUAPC] D12_APC_2: 0x3fffff
9989 13:19:11.904869 INFO: [APUAPC] D12_APC_3: 0x0
9990 13:19:11.907898 INFO: [APUAPC] D13_APC_0: 0xffffffff
9991 13:19:11.911461 INFO: [APUAPC] D13_APC_1: 0xffffffff
9992 13:19:11.914577 INFO: [APUAPC] D13_APC_2: 0x3fffff
9993 13:19:11.918070 INFO: [APUAPC] D13_APC_3: 0x0
9994 13:19:11.921398 INFO: [APUAPC] D14_APC_0: 0xffffffff
9995 13:19:11.925063 INFO: [APUAPC] D14_APC_1: 0xffffffff
9996 13:19:11.928021 INFO: [APUAPC] D14_APC_2: 0x3fffff
9997 13:19:11.931453 INFO: [APUAPC] D14_APC_3: 0x0
9998 13:19:11.934691 INFO: [APUAPC] D15_APC_0: 0xffffffff
9999 13:19:11.937860 INFO: [APUAPC] D15_APC_1: 0xffffffff
10000 13:19:11.941458 INFO: [APUAPC] D15_APC_2: 0x3fffff
10001 13:19:11.945135 INFO: [APUAPC] D15_APC_3: 0x0
10002 13:19:11.945213 INFO: [APUAPC] APC_CON: 0x4
10003 13:19:11.948245 INFO: [NOCDAPC] D0_APC_0: 0x0
10004 13:19:11.951298 INFO: [NOCDAPC] D0_APC_1: 0x0
10005 13:19:11.954969 INFO: [NOCDAPC] D1_APC_0: 0x0
10006 13:19:11.957842 INFO: [NOCDAPC] D1_APC_1: 0xfff
10007 13:19:11.961254 INFO: [NOCDAPC] D2_APC_0: 0x0
10008 13:19:11.964689 INFO: [NOCDAPC] D2_APC_1: 0xfff
10009 13:19:11.968026 INFO: [NOCDAPC] D3_APC_0: 0x0
10010 13:19:11.971330 INFO: [NOCDAPC] D3_APC_1: 0xfff
10011 13:19:11.974682 INFO: [NOCDAPC] D4_APC_0: 0x0
10012 13:19:11.974760 INFO: [NOCDAPC] D4_APC_1: 0xfff
10013 13:19:11.978091 INFO: [NOCDAPC] D5_APC_0: 0x0
10014 13:19:11.981233 INFO: [NOCDAPC] D5_APC_1: 0xfff
10015 13:19:11.984883 INFO: [NOCDAPC] D6_APC_0: 0x0
10016 13:19:11.987791 INFO: [NOCDAPC] D6_APC_1: 0xfff
10017 13:19:11.991406 INFO: [NOCDAPC] D7_APC_0: 0x0
10018 13:19:11.994384 INFO: [NOCDAPC] D7_APC_1: 0xfff
10019 13:19:11.998113 INFO: [NOCDAPC] D8_APC_0: 0x0
10020 13:19:12.001085 INFO: [NOCDAPC] D8_APC_1: 0xfff
10021 13:19:12.004755 INFO: [NOCDAPC] D9_APC_0: 0x0
10022 13:19:12.007866 INFO: [NOCDAPC] D9_APC_1: 0xfff
10023 13:19:12.007944 INFO: [NOCDAPC] D10_APC_0: 0x0
10024 13:19:12.011470 INFO: [NOCDAPC] D10_APC_1: 0xfff
10025 13:19:12.014521 INFO: [NOCDAPC] D11_APC_0: 0x0
10026 13:19:12.018162 INFO: [NOCDAPC] D11_APC_1: 0xfff
10027 13:19:12.021154 INFO: [NOCDAPC] D12_APC_0: 0x0
10028 13:19:12.024784 INFO: [NOCDAPC] D12_APC_1: 0xfff
10029 13:19:12.028133 INFO: [NOCDAPC] D13_APC_0: 0x0
10030 13:19:12.031447 INFO: [NOCDAPC] D13_APC_1: 0xfff
10031 13:19:12.034443 INFO: [NOCDAPC] D14_APC_0: 0x0
10032 13:19:12.038093 INFO: [NOCDAPC] D14_APC_1: 0xfff
10033 13:19:12.041092 INFO: [NOCDAPC] D15_APC_0: 0x0
10034 13:19:12.044472 INFO: [NOCDAPC] D15_APC_1: 0xfff
10035 13:19:12.047771 INFO: [NOCDAPC] APC_CON: 0x4
10036 13:19:12.051228 INFO: [APUAPC] set_apusys_apc done
10037 13:19:12.051305 INFO: [DEVAPC] devapc_init done
10038 13:19:12.057918 INFO: GICv3 without legacy support detected.
10039 13:19:12.061397 INFO: ARM GICv3 driver initialized in EL3
10040 13:19:12.064784 INFO: Maximum SPI INTID supported: 639
10041 13:19:12.067899 INFO: BL31: Initializing runtime services
10042 13:19:12.074880 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10043 13:19:12.077774 INFO: SPM: enable CPC mode
10044 13:19:12.081251 INFO: mcdi ready for mcusys-off-idle and system suspend
10045 13:19:12.087997 INFO: BL31: Preparing for EL3 exit to normal world
10046 13:19:12.090979 INFO: Entry point address = 0x80000000
10047 13:19:12.091055 INFO: SPSR = 0x8
10048 13:19:12.098672
10049 13:19:12.098764
10050 13:19:12.098836
10051 13:19:12.101712 Starting depthcharge on Spherion...
10052 13:19:12.101819
10053 13:19:12.101876 Wipe memory regions:
10054 13:19:12.101947
10055 13:19:12.102613 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10056 13:19:12.102702 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10057 13:19:12.102774 Setting prompt string to ['asurada:']
10058 13:19:12.102838 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10059 13:19:12.105401 [0x00000040000000, 0x00000054600000)
10060 13:19:12.226877
10061 13:19:12.226996 [0x00000054660000, 0x00000080000000)
10062 13:19:12.487431
10063 13:19:12.487582 [0x000000821a7280, 0x000000ffe64000)
10064 13:19:13.232176
10065 13:19:13.232318 [0x00000100000000, 0x00000240000000)
10066 13:19:15.121886
10067 13:19:15.125615 Initializing XHCI USB controller at 0x11200000.
10068 13:19:16.163390
10069 13:19:16.167119 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10070 13:19:16.167197
10071 13:19:16.167267
10072 13:19:16.167575 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 13:19:16.167682 Sending line: 'tftpboot 192.168.201.1 14879043/tftp-deploy-ccdzcpl7/kernel/image.itb 14879043/tftp-deploy-ccdzcpl7/kernel/cmdline '
10075 13:19:16.268160 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 13:19:16.268246 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10077 13:19:16.272891 asurada: tftpboot 192.168.201.1 14879043/tftp-deploy-ccdzcpl7/kernel/image.itp-deploy-ccdzcpl7/kernel/cmdline
10078 13:19:16.272971
10079 13:19:16.273064 Waiting for link
10080 13:19:16.430707
10081 13:19:16.430822 R8152: Initializing
10082 13:19:16.430905
10083 13:19:16.434030 Version 6 (ocp_data = 5c30)
10084 13:19:16.434108
10085 13:19:16.437045 R8152: Done initializing
10086 13:19:16.437161
10087 13:19:16.437249 Adding net device
10088 13:19:18.310429
10089 13:19:18.310560 done.
10090 13:19:18.310740
10091 13:19:18.310812 MAC: 00:24:32:30:78:52
10092 13:19:18.310865
10093 13:19:18.314147 Sending DHCP discover... done.
10094 13:19:18.314222
10095 13:19:18.317153 Waiting for reply... done.
10096 13:19:18.317242
10097 13:19:18.320772 Sending DHCP request... done.
10098 13:19:18.320847
10099 13:19:18.337269 Waiting for reply... done.
10100 13:19:18.337346
10101 13:19:18.337405 My ip is 192.168.201.14
10102 13:19:18.337459
10103 13:19:18.340226 The DHCP server ip is 192.168.201.1
10104 13:19:18.340301
10105 13:19:18.346760 TFTP server IP predefined by user: 192.168.201.1
10106 13:19:18.346862
10107 13:19:18.354017 Bootfile predefined by user: 14879043/tftp-deploy-ccdzcpl7/kernel/image.itb
10108 13:19:18.354093
10109 13:19:18.354152 Sending tftp read request... done.
10110 13:19:18.356778
10111 13:19:18.360535 Waiting for the transfer...
10112 13:19:18.360611
10113 13:19:18.892031 00000000 ################################################################
10114 13:19:18.892150
10115 13:19:19.422842 00080000 ################################################################
10116 13:19:19.422974
10117 13:19:19.951529 00100000 ################################################################
10118 13:19:19.951684
10119 13:19:20.486224 00180000 ################################################################
10120 13:19:20.486359
10121 13:19:21.052519 00200000 ################################################################
10122 13:19:21.052666
10123 13:19:21.601391 00280000 ################################################################
10124 13:19:21.601578
10125 13:19:22.133976 00300000 ################################################################
10126 13:19:22.134128
10127 13:19:22.673128 00380000 ################################################################
10128 13:19:22.673270
10129 13:19:23.210365 00400000 ################################################################
10130 13:19:23.210501
10131 13:19:23.747562 00480000 ################################################################
10132 13:19:23.747713
10133 13:19:24.295385 00500000 ################################################################
10134 13:19:24.295527
10135 13:19:24.836386 00580000 ################################################################
10136 13:19:24.836523
10137 13:19:25.381780 00600000 ################################################################
10138 13:19:25.381910
10139 13:19:25.927480 00680000 ################################################################
10140 13:19:25.927620
10141 13:19:26.459799 00700000 ################################################################
10142 13:19:26.459921
10143 13:19:26.991807 00780000 ################################################################
10144 13:19:26.991939
10145 13:19:27.537340 00800000 ################################################################
10146 13:19:27.537472
10147 13:19:28.091026 00880000 ################################################################
10148 13:19:28.091153
10149 13:19:28.646193 00900000 ################################################################
10150 13:19:28.646323
10151 13:19:29.196160 00980000 ################################################################
10152 13:19:29.196313
10153 13:19:29.740157 00a00000 ################################################################
10154 13:19:29.740275
10155 13:19:30.276294 00a80000 ################################################################
10156 13:19:30.276452
10157 13:19:30.798228 00b00000 ################################################################
10158 13:19:30.798361
10159 13:19:31.332258 00b80000 ################################################################
10160 13:19:31.332383
10161 13:19:31.875564 00c00000 ################################################################
10162 13:19:31.875699
10163 13:19:32.534681 00c80000 ################################################################
10164 13:19:32.535102
10165 13:19:33.112384 00d00000 ################################################################
10166 13:19:33.112624
10167 13:19:33.665835 00d80000 ################################################################
10168 13:19:33.665982
10169 13:19:34.196341 00e00000 ################################################################
10170 13:19:34.196462
10171 13:19:34.723619 00e80000 ################################################################
10172 13:19:34.723761
10173 13:19:35.269454 00f00000 ################################################################
10174 13:19:35.269568
10175 13:19:35.805114 00f80000 ################################################################
10176 13:19:35.805251
10177 13:19:36.504364 01000000 ################################################################
10178 13:19:36.504486
10179 13:19:37.189809 01080000 ################################################################
10180 13:19:37.189996
10181 13:19:37.745978 01100000 ################################################################
10182 13:19:37.746110
10183 13:19:38.298673 01180000 ################################################################
10184 13:19:38.298821
10185 13:19:38.845533 01200000 ################################################################
10186 13:19:38.845648
10187 13:19:39.383304 01280000 ################################################################
10188 13:19:39.383600
10189 13:19:40.043595 01300000 ################################################################
10190 13:19:40.043720
10191 13:19:40.610859 01380000 ################################################################
10192 13:19:40.611328
10193 13:19:41.179532 01400000 ################################################################
10194 13:19:41.179680
10195 13:19:41.741202 01480000 ################################################################
10196 13:19:41.741332
10197 13:19:42.295905 01500000 ################################################################
10198 13:19:42.296021
10199 13:19:42.864689 01580000 ################################################################
10200 13:19:42.864946
10201 13:19:43.531099 01600000 ################################################################
10202 13:19:43.531563
10203 13:19:44.174866 01680000 ################################################################
10204 13:19:44.175469
10205 13:19:44.855933 01700000 ################################################################
10206 13:19:44.856416
10207 13:19:45.526814 01780000 ################################################################
10208 13:19:45.527302
10209 13:19:46.138427 01800000 ################################################################
10210 13:19:46.138555
10211 13:19:46.754044 01880000 ################################################################
10212 13:19:46.754515
10213 13:19:47.345226 01900000 ################################################################
10214 13:19:47.345355
10215 13:19:47.910265 01980000 ################################################################
10216 13:19:47.910433
10217 13:19:48.488926 01a00000 ################################################################
10218 13:19:48.489104
10219 13:19:49.039843 01a80000 ################################################################
10220 13:19:49.039968
10221 13:19:49.574416 01b00000 ################################################################
10222 13:19:49.574587
10223 13:19:50.129294 01b80000 ################################################################
10224 13:19:50.129437
10225 13:19:50.703412 01c00000 ################################################################
10226 13:19:50.703543
10227 13:19:51.258875 01c80000 ################################################################
10228 13:19:51.259033
10229 13:19:51.831637 01d00000 ################################################################
10230 13:19:51.832048
10231 13:19:52.478885 01d80000 ################################################################
10232 13:19:52.479298
10233 13:19:53.047175 01e00000 ################################################################
10234 13:19:53.047322
10235 13:19:53.608119 01e80000 ################################################################
10236 13:19:53.608234
10237 13:19:54.167640 01f00000 ################################################################
10238 13:19:54.167757
10239 13:19:54.712412 01f80000 ################################################################
10240 13:19:54.712548
10241 13:19:55.311835 02000000 ################################################################
10242 13:19:55.312918
10243 13:19:55.974333 02080000 ################################################################
10244 13:19:55.974904
10245 13:19:56.635415 02100000 ################################################################
10246 13:19:56.635886
10247 13:19:57.272415 02180000 ################################################################
10248 13:19:57.272528
10249 13:19:57.903105 02200000 ################################################################
10250 13:19:57.903483
10251 13:19:58.454694 02280000 ################################################################
10252 13:19:58.454869
10253 13:19:59.073637 02300000 ################################################################
10254 13:19:59.074101
10255 13:19:59.760855 02380000 ################################################################
10256 13:19:59.761443
10257 13:20:00.427163 02400000 ################################################################
10258 13:20:00.427287
10259 13:20:00.985102 02480000 ################################################################
10260 13:20:00.985259
10261 13:20:01.546184 02500000 ################################################################
10262 13:20:01.546314
10263 13:20:02.080859 02580000 ################################################################
10264 13:20:02.080977
10265 13:20:02.599493 02600000 ################################################################
10266 13:20:02.599604
10267 13:20:03.131310 02680000 ################################################################
10268 13:20:03.131422
10269 13:20:03.663349 02700000 ################################################################
10270 13:20:03.663488
10271 13:20:04.308369 02780000 ################################################################
10272 13:20:04.308516
10273 13:20:04.939385 02800000 ################################################################
10274 13:20:04.939542
10275 13:20:05.498072 02880000 ################################################################
10276 13:20:05.498190
10277 13:20:06.050083 02900000 ################################################################
10278 13:20:06.050225
10279 13:20:06.614131 02980000 ################################################################
10280 13:20:06.614291
10281 13:20:07.142752 02a00000 ################################################################
10282 13:20:07.142869
10283 13:20:07.685396 02a80000 ################################################################
10284 13:20:07.685515
10285 13:20:08.209725 02b00000 ################################################################
10286 13:20:08.209845
10287 13:20:08.728955 02b80000 ################################################################
10288 13:20:08.729107
10289 13:20:09.248226 02c00000 ################################################################
10290 13:20:09.248345
10291 13:20:09.767836 02c80000 ################################################################
10292 13:20:09.767960
10293 13:20:10.297416 02d00000 ################################################################
10294 13:20:10.297570
10295 13:20:10.822741 02d80000 ################################################################
10296 13:20:10.822877
10297 13:20:11.360871 02e00000 ################################################################
10298 13:20:11.361001
10299 13:20:11.909482 02e80000 ################################################################
10300 13:20:11.909637
10301 13:20:12.447559 02f00000 ################################################################
10302 13:20:12.447719
10303 13:20:12.966083 02f80000 ################################################################
10304 13:20:12.966240
10305 13:20:13.489429 03000000 ################################################################
10306 13:20:13.489556
10307 13:20:14.033726 03080000 ################################################################
10308 13:20:14.033844
10309 13:20:14.567319 03100000 ################################################################
10310 13:20:14.567449
10311 13:20:15.100933 03180000 ################################################################
10312 13:20:15.101047
10313 13:20:15.649589 03200000 ################################################################
10314 13:20:15.649712
10315 13:20:16.223550 03280000 ################################################################
10316 13:20:16.223672
10317 13:20:16.761401 03300000 ################################################################
10318 13:20:16.761526
10319 13:20:17.130455 03380000 ############################################# done.
10320 13:20:17.130570
10321 13:20:17.133997 The bootfile was 54366850 bytes long.
10322 13:20:17.134124
10323 13:20:17.137537 Sending tftp read request... done.
10324 13:20:17.137614
10325 13:20:17.137673 Waiting for the transfer...
10326 13:20:17.137727
10327 13:20:17.140626 00000000 # done.
10328 13:20:17.140705
10329 13:20:17.147221 Command line loaded dynamically from TFTP file: 14879043/tftp-deploy-ccdzcpl7/kernel/cmdline
10330 13:20:17.147318
10331 13:20:17.160866 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10332 13:20:17.160946
10333 13:20:17.164320 Loading FIT.
10334 13:20:17.164398
10335 13:20:17.167438 Image ramdisk-1 has 41203095 bytes.
10336 13:20:17.167517
10337 13:20:17.167593 Image fdt-1 has 47258 bytes.
10338 13:20:17.167683
10339 13:20:17.170637 Image kernel-1 has 13114469 bytes.
10340 13:20:17.170714
10341 13:20:17.181028 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10342 13:20:17.181108
10343 13:20:17.197360 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10344 13:20:17.197441
10345 13:20:17.204288 Choosing best match conf-1 for compat google,spherion-rev2.
10346 13:20:17.207717
10347 13:20:17.212992 Connected to device vid:did:rid of 1ae0:0028:00
10348 13:20:17.220811
10349 13:20:17.223733 tpm_get_response: command 0x17b, return code 0x0
10350 13:20:17.223836
10351 13:20:17.230789 ec_init: CrosEC protocol v3 supported (256, 248)
10352 13:20:17.230882
10353 13:20:17.234350 tpm_cleanup: add release locality here.
10354 13:20:17.234427
10355 13:20:17.237437 Shutting down all USB controllers.
10356 13:20:17.237514
10357 13:20:17.241126 Removing current net device
10358 13:20:17.241231
10359 13:20:17.244069 Exiting depthcharge with code 4 at timestamp: 94564817
10360 13:20:17.244146
10361 13:20:17.250859 LZMA decompressing kernel-1 to 0x821a6718
10362 13:20:17.250937
10363 13:20:17.254228 LZMA decompressing kernel-1 to 0x40000000
10364 13:20:18.868403
10365 13:20:18.868524 jumping to kernel
10366 13:20:18.869352 end: 2.2.4 bootloader-commands (duration 00:01:07) [common]
10367 13:20:18.869482 start: 2.2.5 auto-login-action (timeout 00:03:13) [common]
10368 13:20:18.869585 Setting prompt string to ['Linux version [0-9]']
10369 13:20:18.869684 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10370 13:20:18.869784 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10371 13:20:18.949381
10372 13:20:18.952503 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10373 13:20:18.956312 start: 2.2.5.1 login-action (timeout 00:03:13) [common]
10374 13:20:18.956430 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10375 13:20:18.956533 Setting prompt string to []
10376 13:20:18.956640 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10377 13:20:18.956743 Using line separator: #'\n'#
10378 13:20:18.956827 No login prompt set.
10379 13:20:18.956911 Parsing kernel messages
10380 13:20:18.956998 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10381 13:20:18.957163 [login-action] Waiting for messages, (timeout 00:03:13)
10382 13:20:18.957241 Waiting using forced prompt support (timeout 00:01:36)
10383 13:20:18.975894 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10384 13:20:18.979382 [ 0.000000] random: crng init done
10385 13:20:18.982412 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10386 13:20:18.986225 [ 0.000000] efi: UEFI not found.
10387 13:20:18.995898 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10388 13:20:19.002642 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10389 13:20:19.012909 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10390 13:20:19.022442 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10391 13:20:19.029343 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10392 13:20:19.032426 [ 0.000000] printk: bootconsole [mtk8250] enabled
10393 13:20:19.040627 [ 0.000000] NUMA: No NUMA configuration found
10394 13:20:19.047092 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10395 13:20:19.053967 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10396 13:20:19.054040 [ 0.000000] Zone ranges:
10397 13:20:19.060499 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10398 13:20:19.064062 [ 0.000000] DMA32 empty
10399 13:20:19.070588 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10400 13:20:19.074027 [ 0.000000] Movable zone start for each node
10401 13:20:19.077350 [ 0.000000] Early memory node ranges
10402 13:20:19.083927 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10403 13:20:19.090455 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10404 13:20:19.097238 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10405 13:20:19.103526 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10406 13:20:19.110487 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10407 13:20:19.116743 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10408 13:20:19.174228 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10409 13:20:19.180676 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10410 13:20:19.187418 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10411 13:20:19.190963 [ 0.000000] psci: probing for conduit method from DT.
10412 13:20:19.196896 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10413 13:20:19.200798 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10414 13:20:19.206936 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10415 13:20:19.210228 [ 0.000000] psci: SMC Calling Convention v1.2
10416 13:20:19.216932 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10417 13:20:19.220671 [ 0.000000] Detected VIPT I-cache on CPU0
10418 13:20:19.227391 [ 0.000000] CPU features: detected: GIC system register CPU interface
10419 13:20:19.233725 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10420 13:20:19.240205 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10421 13:20:19.247218 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10422 13:20:19.253954 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10423 13:20:19.260352 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10424 13:20:19.267427 [ 0.000000] alternatives: applying boot alternatives
10425 13:20:19.270414 [ 0.000000] Fallback order for Node 0: 0
10426 13:20:19.277360 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10427 13:20:19.280553 [ 0.000000] Policy zone: Normal
10428 13:20:19.297045 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10429 13:20:19.307336 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10430 13:20:19.318345 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10431 13:20:19.328715 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10432 13:20:19.334992 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10433 13:20:19.338190 <6>[ 0.000000] software IO TLB: area num 8.
10434 13:20:19.394256 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10435 13:20:19.543907 <6>[ 0.000000] Memory: 7923824K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 428944K reserved, 32768K cma-reserved)
10436 13:20:19.550529 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10437 13:20:19.557153 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10438 13:20:19.560698 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10439 13:20:19.567159 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10440 13:20:19.574014 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10441 13:20:19.577404 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10442 13:20:19.587681 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10443 13:20:19.593950 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10444 13:20:19.597684 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10445 13:20:19.604710 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10446 13:20:19.608505 <6>[ 0.000000] GICv3: 608 SPIs implemented
10447 13:20:19.615036 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10448 13:20:19.618167 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10449 13:20:19.621835 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10450 13:20:19.631242 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10451 13:20:19.641271 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10452 13:20:19.654828 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10453 13:20:19.661290 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10454 13:20:19.670137 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10455 13:20:19.684114 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10456 13:20:19.690494 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10457 13:20:19.697469 <6>[ 0.009178] Console: colour dummy device 80x25
10458 13:20:19.707176 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10459 13:20:19.710442 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10460 13:20:19.716850 <6>[ 0.029317] LSM: Security Framework initializing
10461 13:20:19.723633 <6>[ 0.034257] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 13:20:19.733863 <6>[ 0.042069] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10463 13:20:19.740077 <6>[ 0.051492] cblist_init_generic: Setting adjustable number of callback queues.
10464 13:20:19.746960 <6>[ 0.058932] cblist_init_generic: Setting shift to 3 and lim to 1.
10465 13:20:19.753645 <6>[ 0.065271] cblist_init_generic: Setting adjustable number of callback queues.
10466 13:20:19.760168 <6>[ 0.072697] cblist_init_generic: Setting shift to 3 and lim to 1.
10467 13:20:19.766952 <6>[ 0.079138] rcu: Hierarchical SRCU implementation.
10468 13:20:19.773982 <6>[ 0.084152] rcu: Max phase no-delay instances is 1000.
10469 13:20:19.776971 <6>[ 0.091173] EFI services will not be available.
10470 13:20:19.784022 <6>[ 0.096133] smp: Bringing up secondary CPUs ...
10471 13:20:19.791648 <6>[ 0.101185] Detected VIPT I-cache on CPU1
10472 13:20:19.797609 <6>[ 0.101255] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10473 13:20:19.804630 <6>[ 0.101286] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10474 13:20:19.808189 <6>[ 0.101626] Detected VIPT I-cache on CPU2
10475 13:20:19.814458 <6>[ 0.101676] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10476 13:20:19.821234 <6>[ 0.101692] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10477 13:20:19.827816 <6>[ 0.101951] Detected VIPT I-cache on CPU3
10478 13:20:19.834450 <6>[ 0.102000] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10479 13:20:19.841551 <6>[ 0.102014] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10480 13:20:19.844721 <6>[ 0.102321] CPU features: detected: Spectre-v4
10481 13:20:19.851544 <6>[ 0.102327] CPU features: detected: Spectre-BHB
10482 13:20:19.854472 <6>[ 0.102332] Detected PIPT I-cache on CPU4
10483 13:20:19.861375 <6>[ 0.102392] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10484 13:20:19.868064 <6>[ 0.102409] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10485 13:20:19.871549 <6>[ 0.102700] Detected PIPT I-cache on CPU5
10486 13:20:19.881215 <6>[ 0.102762] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10487 13:20:19.888330 <6>[ 0.102779] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10488 13:20:19.891441 <6>[ 0.103060] Detected PIPT I-cache on CPU6
10489 13:20:19.898116 <6>[ 0.103127] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10490 13:20:19.904978 <6>[ 0.103143] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10491 13:20:19.908464 <6>[ 0.103442] Detected PIPT I-cache on CPU7
10492 13:20:19.914789 <6>[ 0.103507] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10493 13:20:19.924500 <6>[ 0.103523] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10494 13:20:19.927754 <6>[ 0.103571] smp: Brought up 1 node, 8 CPUs
10495 13:20:19.931132 <6>[ 0.244881] SMP: Total of 8 processors activated.
10496 13:20:19.938293 <6>[ 0.249802] CPU features: detected: 32-bit EL0 Support
10497 13:20:19.947538 <6>[ 0.255198] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10498 13:20:19.954602 <6>[ 0.264053] CPU features: detected: Common not Private translations
10499 13:20:19.957989 <6>[ 0.270530] CPU features: detected: CRC32 instructions
10500 13:20:19.964307 <6>[ 0.275881] CPU features: detected: RCpc load-acquire (LDAPR)
10501 13:20:19.971429 <6>[ 0.281841] CPU features: detected: LSE atomic instructions
10502 13:20:19.974260 <6>[ 0.287623] CPU features: detected: Privileged Access Never
10503 13:20:19.980762 <6>[ 0.293402] CPU features: detected: RAS Extension Support
10504 13:20:19.987788 <6>[ 0.299045] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10505 13:20:19.994127 <6>[ 0.306265] CPU: All CPU(s) started at EL2
10506 13:20:19.997886 <6>[ 0.310582] alternatives: applying system-wide alternatives
10507 13:20:20.009147 <6>[ 0.321504] devtmpfs: initialized
10508 13:20:20.024638 <6>[ 0.330349] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10509 13:20:20.030963 <6>[ 0.340305] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10510 13:20:20.037881 <6>[ 0.348555] pinctrl core: initialized pinctrl subsystem
10511 13:20:20.041391 <6>[ 0.355230] DMI not present or invalid.
10512 13:20:20.047681 <6>[ 0.359638] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10513 13:20:20.057485 <6>[ 0.366532] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10514 13:20:20.064540 <6>[ 0.374115] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10515 13:20:20.074477 <6>[ 0.382344] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10516 13:20:20.077355 <6>[ 0.390586] audit: initializing netlink subsys (disabled)
10517 13:20:20.087701 <5>[ 0.396275] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10518 13:20:20.094248 <6>[ 0.396986] thermal_sys: Registered thermal governor 'step_wise'
10519 13:20:20.100717 <6>[ 0.404240] thermal_sys: Registered thermal governor 'power_allocator'
10520 13:20:20.104394 <6>[ 0.410496] cpuidle: using governor menu
10521 13:20:20.110788 <6>[ 0.421456] NET: Registered PF_QIPCRTR protocol family
10522 13:20:20.117261 <6>[ 0.426945] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10523 13:20:20.120538 <6>[ 0.434048] ASID allocator initialised with 32768 entries
10524 13:20:20.127904 <6>[ 0.440615] Serial: AMBA PL011 UART driver
10525 13:20:20.137734 <4>[ 0.449966] Trying to register duplicate clock ID: 134
10526 13:20:20.195577 <6>[ 0.511258] KASLR enabled
10527 13:20:20.209721 <6>[ 0.518884] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10528 13:20:20.216211 <6>[ 0.525899] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10529 13:20:20.222842 <6>[ 0.532389] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10530 13:20:20.230003 <6>[ 0.539396] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10531 13:20:20.236332 <6>[ 0.545882] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10532 13:20:20.242790 <6>[ 0.552886] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10533 13:20:20.249752 <6>[ 0.559370] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10534 13:20:20.256223 <6>[ 0.566375] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10535 13:20:20.259845 <6>[ 0.573843] ACPI: Interpreter disabled.
10536 13:20:20.267947 <6>[ 0.580275] iommu: Default domain type: Translated
10537 13:20:20.274417 <6>[ 0.585426] iommu: DMA domain TLB invalidation policy: strict mode
10538 13:20:20.277952 <5>[ 0.592078] SCSI subsystem initialized
10539 13:20:20.284620 <6>[ 0.596325] usbcore: registered new interface driver usbfs
10540 13:20:20.290936 <6>[ 0.602059] usbcore: registered new interface driver hub
10541 13:20:20.294203 <6>[ 0.607609] usbcore: registered new device driver usb
10542 13:20:20.301526 <6>[ 0.613741] pps_core: LinuxPPS API ver. 1 registered
10543 13:20:20.310994 <6>[ 0.618933] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10544 13:20:20.314675 <6>[ 0.628274] PTP clock support registered
10545 13:20:20.317578 <6>[ 0.632519] EDAC MC: Ver: 3.0.0
10546 13:20:20.325283 <6>[ 0.637723] FPGA manager framework
10547 13:20:20.331935 <6>[ 0.641403] Advanced Linux Sound Architecture Driver Initialized.
10548 13:20:20.335259 <6>[ 0.648200] vgaarb: loaded
10549 13:20:20.341571 <6>[ 0.651348] clocksource: Switched to clocksource arch_sys_counter
10550 13:20:20.344946 <5>[ 0.657796] VFS: Disk quotas dquot_6.6.0
10551 13:20:20.351401 <6>[ 0.661980] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10552 13:20:20.354775 <6>[ 0.669171] pnp: PnP ACPI: disabled
10553 13:20:20.363560 <6>[ 0.675861] NET: Registered PF_INET protocol family
10554 13:20:20.373357 <6>[ 0.681453] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10555 13:20:20.384327 <6>[ 0.693724] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10556 13:20:20.394500 <6>[ 0.702536] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10557 13:20:20.401456 <6>[ 0.710505] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10558 13:20:20.407503 <6>[ 0.719207] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10559 13:20:20.419761 <6>[ 0.728964] TCP: Hash tables configured (established 65536 bind 65536)
10560 13:20:20.426844 <6>[ 0.735836] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10561 13:20:20.433265 <6>[ 0.743036] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10562 13:20:20.439789 <6>[ 0.750736] NET: Registered PF_UNIX/PF_LOCAL protocol family
10563 13:20:20.446733 <6>[ 0.756883] RPC: Registered named UNIX socket transport module.
10564 13:20:20.449898 <6>[ 0.763035] RPC: Registered udp transport module.
10565 13:20:20.456577 <6>[ 0.767965] RPC: Registered tcp transport module.
10566 13:20:20.463423 <6>[ 0.772898] RPC: Registered tcp NFSv4.1 backchannel transport module.
10567 13:20:20.466898 <6>[ 0.779559] PCI: CLS 0 bytes, default 64
10568 13:20:20.469694 <6>[ 0.783911] Unpacking initramfs...
10569 13:20:20.479705 <6>[ 0.787629] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10570 13:20:20.486784 <6>[ 0.796266] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10571 13:20:20.493177 <6>[ 0.805067] kvm [1]: IPA Size Limit: 40 bits
10572 13:20:20.496520 <6>[ 0.809584] kvm [1]: GICv3: no GICV resource entry
10573 13:20:20.503116 <6>[ 0.814602] kvm [1]: disabling GICv2 emulation
10574 13:20:20.506524 <6>[ 0.819288] kvm [1]: GIC system register CPU interface enabled
10575 13:20:20.513473 <6>[ 0.825450] kvm [1]: vgic interrupt IRQ18
10576 13:20:20.519597 <6>[ 0.831533] kvm [1]: VHE mode initialized successfully
10577 13:20:20.526584 <5>[ 0.837959] Initialise system trusted keyrings
10578 13:20:20.533046 <6>[ 0.842743] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10579 13:20:20.540202 <6>[ 0.852759] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10580 13:20:20.547198 <5>[ 0.859117] NFS: Registering the id_resolver key type
10581 13:20:20.550233 <5>[ 0.864419] Key type id_resolver registered
10582 13:20:20.557127 <5>[ 0.868836] Key type id_legacy registered
10583 13:20:20.563944 <6>[ 0.873117] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10584 13:20:20.570092 <6>[ 0.880036] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10585 13:20:20.576989 <6>[ 0.887750] 9p: Installing v9fs 9p2000 file system support
10586 13:20:20.613390 <5>[ 0.925931] Key type asymmetric registered
10587 13:20:20.617041 <5>[ 0.930260] Asymmetric key parser 'x509' registered
10588 13:20:20.626932 <6>[ 0.935398] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10589 13:20:20.630274 <6>[ 0.943012] io scheduler mq-deadline registered
10590 13:20:20.633582 <6>[ 0.947771] io scheduler kyber registered
10591 13:20:20.652559 <6>[ 0.964885] EINJ: ACPI disabled.
10592 13:20:20.684895 <4>[ 0.990931] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 13:20:20.695450 <4>[ 1.001708] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 13:20:20.710032 <6>[ 1.022605] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10595 13:20:20.718303 <6>[ 1.030569] printk: console [ttyS0] disabled
10596 13:20:20.746099 <6>[ 1.055199] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10597 13:20:20.752517 <6>[ 1.064671] printk: console [ttyS0] enabled
10598 13:20:20.755842 <6>[ 1.064671] printk: console [ttyS0] enabled
10599 13:20:20.762931 <6>[ 1.073564] printk: bootconsole [mtk8250] disabled
10600 13:20:20.766483 <6>[ 1.073564] printk: bootconsole [mtk8250] disabled
10601 13:20:20.772486 <6>[ 1.084597] SuperH (H)SCI(F) driver initialized
10602 13:20:20.775897 <6>[ 1.089869] msm_serial: driver initialized
10603 13:20:20.789623 <6>[ 1.098793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10604 13:20:20.799910 <6>[ 1.107341] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10605 13:20:20.806364 <6>[ 1.115882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10606 13:20:20.816354 <6>[ 1.124515] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10607 13:20:20.822723 <6>[ 1.133222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10608 13:20:20.832665 <6>[ 1.141936] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10609 13:20:20.842575 <6>[ 1.150476] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10610 13:20:20.849657 <6>[ 1.159271] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10611 13:20:20.859432 <6>[ 1.167812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10612 13:20:20.870917 <6>[ 1.183395] loop: module loaded
10613 13:20:20.877576 <6>[ 1.189259] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10614 13:20:20.899789 <4>[ 1.212078] mtk-pmic-keys: Failed to locate of_node [id: -1]
10615 13:20:20.907002 <6>[ 1.218903] megasas: 07.719.03.00-rc1
10616 13:20:20.915823 <6>[ 1.228550] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10617 13:20:20.926168 <6>[ 1.238752] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10618 13:20:20.943429 <6>[ 1.255617] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10619 13:20:21.000248 <6>[ 1.305846] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10620 13:20:22.217419 <6>[ 2.529992] Freeing initrd memory: 40232K
10621 13:20:22.229158 <6>[ 2.541819] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10622 13:20:22.240092 <6>[ 2.552745] tun: Universal TUN/TAP device driver, 1.6
10623 13:20:22.243584 <6>[ 2.558828] thunder_xcv, ver 1.0
10624 13:20:22.246603 <6>[ 2.562334] thunder_bgx, ver 1.0
10625 13:20:22.249885 <6>[ 2.565830] nicpf, ver 1.0
10626 13:20:22.260252 <6>[ 2.569851] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10627 13:20:22.263776 <6>[ 2.577327] hns3: Copyright (c) 2017 Huawei Corporation.
10628 13:20:22.267210 <6>[ 2.582915] hclge is initializing
10629 13:20:22.274172 <6>[ 2.586492] e1000: Intel(R) PRO/1000 Network Driver
10630 13:20:22.280486 <6>[ 2.591621] e1000: Copyright (c) 1999-2006 Intel Corporation.
10631 13:20:22.284016 <6>[ 2.597634] e1000e: Intel(R) PRO/1000 Network Driver
10632 13:20:22.290368 <6>[ 2.602849] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10633 13:20:22.296969 <6>[ 2.609037] igb: Intel(R) Gigabit Ethernet Network Driver
10634 13:20:22.303479 <6>[ 2.614687] igb: Copyright (c) 2007-2014 Intel Corporation.
10635 13:20:22.310249 <6>[ 2.620524] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10636 13:20:22.317015 <6>[ 2.627043] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10637 13:20:22.320007 <6>[ 2.633502] sky2: driver version 1.30
10638 13:20:22.327160 <6>[ 2.638443] usbcore: registered new device driver r8152-cfgselector
10639 13:20:22.333905 <6>[ 2.644978] usbcore: registered new interface driver r8152
10640 13:20:22.340420 <6>[ 2.650803] VFIO - User Level meta-driver version: 0.3
10641 13:20:22.346623 <6>[ 2.659029] usbcore: registered new interface driver usb-storage
10642 13:20:22.352961 <6>[ 2.665479] usbcore: registered new device driver onboard-usb-hub
10643 13:20:22.362399 <6>[ 2.674671] mt6397-rtc mt6359-rtc: registered as rtc0
10644 13:20:22.371868 <6>[ 2.680138] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:20:22 UTC (1721308822)
10645 13:20:22.375334 <6>[ 2.689700] i2c_dev: i2c /dev entries driver
10646 13:20:22.389148 <4>[ 2.701855] cpu cpu0: supply cpu not found, using dummy regulator
10647 13:20:22.395653 <4>[ 2.708315] cpu cpu1: supply cpu not found, using dummy regulator
10648 13:20:22.402732 <4>[ 2.714716] cpu cpu2: supply cpu not found, using dummy regulator
10649 13:20:22.409232 <4>[ 2.721123] cpu cpu3: supply cpu not found, using dummy regulator
10650 13:20:22.416199 <4>[ 2.727523] cpu cpu4: supply cpu not found, using dummy regulator
10651 13:20:22.422660 <4>[ 2.733918] cpu cpu5: supply cpu not found, using dummy regulator
10652 13:20:22.428958 <4>[ 2.740332] cpu cpu6: supply cpu not found, using dummy regulator
10653 13:20:22.436064 <4>[ 2.746726] cpu cpu7: supply cpu not found, using dummy regulator
10654 13:20:22.454743 <6>[ 2.767364] cpu cpu0: EM: created perf domain
10655 13:20:22.458040 <6>[ 2.772307] cpu cpu4: EM: created perf domain
10656 13:20:22.465380 <6>[ 2.777944] sdhci: Secure Digital Host Controller Interface driver
10657 13:20:22.471906 <6>[ 2.784377] sdhci: Copyright(c) Pierre Ossman
10658 13:20:22.478506 <6>[ 2.789327] Synopsys Designware Multimedia Card Interface Driver
10659 13:20:22.484969 <6>[ 2.795968] sdhci-pltfm: SDHCI platform and OF driver helper
10660 13:20:22.488337 <6>[ 2.796042] mmc0: CQHCI version 5.10
10661 13:20:22.495248 <6>[ 2.806000] ledtrig-cpu: registered to indicate activity on CPUs
10662 13:20:22.501757 <6>[ 2.812994] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10663 13:20:22.508374 <6>[ 2.820042] usbcore: registered new interface driver usbhid
10664 13:20:22.511402 <6>[ 2.825863] usbhid: USB HID core driver
10665 13:20:22.518443 <6>[ 2.830058] spi_master spi0: will run message pump with realtime priority
10666 13:20:22.566137 <6>[ 2.872403] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10667 13:20:22.584802 <6>[ 2.887825] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10668 13:20:22.588190 <6>[ 2.897032] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10669 13:20:22.596146 <6>[ 2.908996] cros-ec-spi spi0.0: Chrome EC device registered
10670 13:20:22.603293 <6>[ 2.915066] mmc0: Command Queue Engine enabled
10671 13:20:22.609626 <6>[ 2.919831] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10672 13:20:22.612800 <6>[ 2.927471] mmcblk0: mmc0:0001 DA4128 116 GiB
10673 13:20:22.623701 <6>[ 2.936575] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10674 13:20:22.631331 <6>[ 2.944027] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10675 13:20:22.637927 <6>[ 2.950155] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10676 13:20:22.647844 <6>[ 2.954047] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10677 13:20:22.654838 <6>[ 2.956253] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10678 13:20:22.657695 <6>[ 2.965896] NET: Registered PF_PACKET protocol family
10679 13:20:22.664731 <6>[ 2.976681] 9pnet: Installing 9P2000 support
10680 13:20:22.667655 <5>[ 2.981250] Key type dns_resolver registered
10681 13:20:22.674452 <6>[ 2.986363] registered taskstats version 1
10682 13:20:22.677894 <5>[ 2.990768] Loading compiled-in X.509 certificates
10683 13:20:22.706396 <4>[ 3.012331] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 13:20:22.715906 <4>[ 3.023108] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 13:20:22.731655 <6>[ 3.044062] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10686 13:20:22.738101 <6>[ 3.050750] xhci-mtk 11200000.usb: xHCI Host Controller
10687 13:20:22.744603 <6>[ 3.056264] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10688 13:20:22.754934 <6>[ 3.064116] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10689 13:20:22.761940 <6>[ 3.073544] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10690 13:20:22.768432 <6>[ 3.079630] xhci-mtk 11200000.usb: xHCI Host Controller
10691 13:20:22.774673 <6>[ 3.085109] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10692 13:20:22.781685 <6>[ 3.092756] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10693 13:20:22.788047 <6>[ 3.100396] hub 1-0:1.0: USB hub found
10694 13:20:22.791602 <6>[ 3.104423] hub 1-0:1.0: 1 port detected
10695 13:20:22.797963 <6>[ 3.108703] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10696 13:20:22.804606 <6>[ 3.117230] hub 2-0:1.0: USB hub found
10697 13:20:22.808022 <6>[ 3.121240] hub 2-0:1.0: 1 port detected
10698 13:20:22.815722 <6>[ 3.128302] mtk-msdc 11f70000.mmc: Got CD GPIO
10699 13:20:22.828044 <6>[ 3.137683] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10700 13:20:22.838317 <6>[ 3.146062] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10701 13:20:22.844797 <6>[ 3.154403] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10702 13:20:22.854975 <6>[ 3.162749] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10703 13:20:22.861590 <6>[ 3.171090] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10704 13:20:22.871435 <6>[ 3.179429] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10705 13:20:22.877953 <6>[ 3.187771] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10706 13:20:22.888188 <6>[ 3.196112] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10707 13:20:22.894480 <6>[ 3.204451] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10708 13:20:22.904319 <6>[ 3.212790] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10709 13:20:22.910959 <6>[ 3.221128] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10710 13:20:22.920918 <6>[ 3.229467] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10711 13:20:22.927508 <6>[ 3.237806] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10712 13:20:22.938075 <6>[ 3.246148] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10713 13:20:22.944263 <6>[ 3.254488] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10714 13:20:22.951227 <6>[ 3.263204] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10715 13:20:22.957772 <6>[ 3.270390] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10716 13:20:22.964584 <6>[ 3.277199] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10717 13:20:22.974657 <6>[ 3.283963] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10718 13:20:22.981179 <6>[ 3.290902] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10719 13:20:22.987876 <6>[ 3.297777] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10720 13:20:22.997709 <6>[ 3.306910] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10721 13:20:23.007541 <6>[ 3.316033] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10722 13:20:23.017592 <6>[ 3.325328] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10723 13:20:23.027928 <6>[ 3.334797] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10724 13:20:23.034284 <6>[ 3.344264] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10725 13:20:23.044306 <6>[ 3.353385] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10726 13:20:23.054556 <6>[ 3.362852] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10727 13:20:23.064173 <6>[ 3.371971] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10728 13:20:23.073988 <6>[ 3.381271] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10729 13:20:23.084360 <6>[ 3.391432] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10730 13:20:23.094289 <6>[ 3.403622] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10731 13:20:23.198710 <6>[ 3.507934] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10732 13:20:23.227659 <6>[ 3.539963] hub 2-1:1.0: USB hub found
10733 13:20:23.230526 <6>[ 3.544488] hub 2-1:1.0: 3 ports detected
10734 13:20:23.241291 <6>[ 3.554196] hub 2-1:1.0: USB hub found
10735 13:20:23.244765 <6>[ 3.558597] hub 2-1:1.0: 3 ports detected
10736 13:20:23.350292 <6>[ 3.659646] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10737 13:20:23.505314 <6>[ 3.817773] hub 1-1:1.0: USB hub found
10738 13:20:23.508138 <6>[ 3.822254] hub 1-1:1.0: 4 ports detected
10739 13:20:23.521434 <6>[ 3.834256] hub 1-1:1.0: USB hub found
10740 13:20:23.524773 <6>[ 3.838839] hub 1-1:1.0: 4 ports detected
10741 13:20:23.594123 <6>[ 3.903892] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10742 13:20:23.703207 <6>[ 4.012342] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10743 13:20:23.740123 <4>[ 4.049335] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10744 13:20:23.749856 <4>[ 4.058526] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10745 13:20:23.788338 <6>[ 4.100871] r8152 2-1.3:1.0 eth0: v1.12.13
10746 13:20:23.854273 <6>[ 4.163617] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10747 13:20:23.986752 <6>[ 4.299669] hub 1-1.4:1.0: USB hub found
10748 13:20:23.989830 <6>[ 4.304357] hub 1-1.4:1.0: 2 ports detected
10749 13:20:24.005419 <6>[ 4.318472] hub 1-1.4:1.0: USB hub found
10750 13:20:24.009163 <6>[ 4.323086] hub 1-1.4:1.0: 2 ports detected
10751 13:20:24.305744 <6>[ 4.615529] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10752 13:20:24.497718 <6>[ 4.807523] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10753 13:20:25.398130 <6>[ 5.711012] r8152 2-1.3:1.0 eth0: carrier on
10754 13:20:27.710322 <5>[ 5.735611] Sending DHCP requests .., OK
10755 13:20:27.716908 <6>[ 8.027712] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10756 13:20:27.720445 <6>[ 8.036002] IP-Config: Complete:
10757 13:20:27.733431 <6>[ 8.039496] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10758 13:20:27.739954 <6>[ 8.050222] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10759 13:20:27.746669 <6>[ 8.058848] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10760 13:20:27.753263 <6>[ 8.058858] nameserver0=192.168.201.1
10761 13:20:27.756782 <6>[ 8.071012] clk: Disabling unused clocks
10762 13:20:27.759815 <6>[ 8.076573] ALSA device list:
10763 13:20:27.766407 <6>[ 8.079853] No soundcards found.
10764 13:20:27.774010 <6>[ 8.087172] Freeing unused kernel memory: 8512K
10765 13:20:27.777530 <6>[ 8.092134] Run /init as init process
10766 13:20:27.807860 <6>[ 8.121136] NET: Registered PF_INET6 protocol family
10767 13:20:27.814386 <6>[ 8.127587] Segment Routing with IPv6
10768 13:20:27.817788 <6>[ 8.131529] In-situ OAM (IOAM) with IPv6
10769 13:20:27.858944 <30>[ 8.145547] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10770 13:20:27.865542 <30>[ 8.178613] systemd[1]: Detected architecture arm64.
10771 13:20:27.865619
10772 13:20:27.871672 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10773 13:20:27.871749
10774 13:20:27.886244 <30>[ 8.199751] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10775 13:20:28.030875 <30>[ 8.341025] systemd[1]: Queued start job for default target graphical.target.
10776 13:20:28.091464 <30>[ 8.401473] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10777 13:20:28.097932 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10778 13:20:28.118533 <30>[ 8.428257] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10779 13:20:28.128274 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10780 13:20:28.146574 <30>[ 8.456575] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10781 13:20:28.156629 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10782 13:20:28.174876 <30>[ 8.485169] systemd[1]: Created slice user.slice - User and Session Slice.
10783 13:20:28.182080 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10784 13:20:28.205838 <30>[ 8.512481] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10785 13:20:28.215354 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10786 13:20:28.237473 <30>[ 8.544010] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10787 13:20:28.243919 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10788 13:20:28.272372 <30>[ 8.572242] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10789 13:20:28.282024 <30>[ 8.592177] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10790 13:20:28.288852 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10791 13:20:28.306384 <30>[ 8.616059] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10792 13:20:28.312956 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10793 13:20:28.334100 <30>[ 8.644187] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10794 13:20:28.344098 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10795 13:20:28.358529 <30>[ 8.671814] systemd[1]: Reached target paths.target - Path Units.
10796 13:20:28.365438 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10797 13:20:28.386320 <30>[ 8.696149] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10798 13:20:28.392620 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10799 13:20:28.406450 <30>[ 8.719754] systemd[1]: Reached target slices.target - Slice Units.
10800 13:20:28.416289 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10801 13:20:28.430782 <30>[ 8.744163] systemd[1]: Reached target swap.target - Swaps.
10802 13:20:28.437693 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10803 13:20:28.457684 <30>[ 8.767822] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10804 13:20:28.467624 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10805 13:20:28.486287 <30>[ 8.796225] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10806 13:20:28.495880 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10807 13:20:28.516198 <30>[ 8.826047] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10808 13:20:28.525728 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10809 13:20:28.542141 <30>[ 8.852402] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10810 13:20:28.552458 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10811 13:20:28.570277 <30>[ 8.880401] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10812 13:20:28.576600 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10813 13:20:28.594551 <30>[ 8.904477] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10814 13:20:28.604236 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10815 13:20:28.622499 <30>[ 8.932487] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10816 13:20:28.632172 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10817 13:20:28.649890 <30>[ 8.960247] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10818 13:20:28.659930 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10819 13:20:28.709620 <30>[ 9.019854] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10820 13:20:28.716059 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10821 13:20:28.727046 <30>[ 9.037213] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10822 13:20:28.733552 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10823 13:20:28.757078 <30>[ 9.067042] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10824 13:20:28.763733 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10825 13:20:28.792575 <30>[ 9.096030] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10826 13:20:28.805407 <30>[ 9.115527] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10827 13:20:28.815095 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10828 13:20:28.869922 <30>[ 9.180264] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10829 13:20:28.876708 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10830 13:20:28.903494 <30>[ 9.213657] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10831 13:20:28.913447 Startin<6>[ 9.222900] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10832 13:20:28.920188 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10833 13:20:28.966506 <30>[ 9.276546] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10834 13:20:28.972973 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10835 13:20:28.999223 <30>[ 9.309594] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10836 13:20:29.005878 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10837 13:20:29.031863 <30>[ 9.341777] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10838 13:20:29.038322 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10839 13:20:29.067206 <30>[ 9.377549] systemd[1]: Starting systemd-journald.service - Journal Service...
10840 13:20:29.073883 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10841 13:20:29.092065 <30>[ 9.402289] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10842 13:20:29.098775 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10843 13:20:29.124711 <30>[ 9.431737] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10844 13:20:29.131643 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10845 13:20:29.152187 <30>[ 9.462600] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10846 13:20:29.162695 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10847 13:20:29.190126 <30>[ 9.500072] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10848 13:20:29.196396 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10849 13:20:29.223538 <30>[ 9.533416] systemd[1]: Started systemd-journald.service - Journal Service.
10850 13:20:29.229868 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10851 13:20:29.252068 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10852 13:20:29.270130 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10853 13:20:29.290180 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10854 13:20:29.306770 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10855 13:20:29.327133 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10856 13:20:29.347295 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10857 13:20:29.370415 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10858 13:20:29.389041 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10859 13:20:29.410021 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10860 13:20:29.428255 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10861 13:20:29.448323 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10862 13:20:29.469829 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10863 13:20:29.476095 See 'systemctl status systemd-remount-fs.service' for details.
10864 13:20:29.486013 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10865 13:20:29.508646 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10866 13:20:29.558697 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10867 13:20:29.579936 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10868 13:20:29.591381 <46>[ 9.901865] systemd-journald[196]: Received client request to flush runtime journal.
10869 13:20:29.603806 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10870 13:20:29.628534 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10871 13:20:29.650719 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10872 13:20:29.679552 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10873 13:20:29.703828 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10874 13:20:29.727113 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10875 13:20:29.751771 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10876 13:20:29.771003 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10877 13:20:29.814425 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10878 13:20:29.836912 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10879 13:20:29.854225 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10880 13:20:29.869626 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10881 13:20:29.898522 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10882 13:20:29.925583 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10883 13:20:29.951072 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10884 13:20:29.980753 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10885 13:20:30.007849 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10886 13:20:30.030446 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10887 13:20:30.060909 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10888 13:20:30.096863 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10889 13:20:30.126007 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10890 13:20:30.215232 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10891 13:20:30.235270 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10892 13:20:30.254783 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10893 13:20:30.277065 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10894 13:20:30.294831 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10895 13:20:30.311330 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10896 13:20:30.331017 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10897 13:20:30.360635 <6>[ 10.670314] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10898 13:20:30.366745 <6>[ 10.670673] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10899 13:20:30.379960 <6>[ 10.689562] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10900 13:20:30.383031 <6>[ 10.693142] remoteproc remoteproc0: scp is available
10901 13:20:30.393244 <6>[ 10.696557] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10902 13:20:30.399649 <6>[ 10.696588] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10903 13:20:30.409268 <6>[ 10.696598] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10904 13:20:30.416382 <6>[ 10.697848] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10905 13:20:30.422584 <6>[ 10.702951] remoteproc remoteproc0: powering up scp
10906 13:20:30.432628 <4>[ 10.712575] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10907 13:20:30.439144 <4>[ 10.718492] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10908 13:20:30.445982 <6>[ 10.719119] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10909 13:20:30.452688 <6>[ 10.719146] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10910 13:20:30.462770 <6>[ 10.728339] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10911 13:20:30.469093 <4>[ 10.730405] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10912 13:20:30.476174 <3>[ 10.736973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 13:20:30.485788 <6>[ 10.740778] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10914 13:20:30.492658 <6>[ 10.747120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10915 13:20:30.499168 <3>[ 10.750001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 13:20:30.509096 <6>[ 10.757226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10917 13:20:30.515864 <3>[ 10.765663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 13:20:30.525602 <6>[ 10.771444] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10919 13:20:30.529331 <6>[ 10.796007] mc: Linux media interface: v0.10
10920 13:20:30.535726 <3>[ 10.796034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 13:20:30.545916 <3>[ 10.796048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 13:20:30.552650 <3>[ 10.796052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 13:20:30.562233 <3>[ 10.796058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10924 13:20:30.569177 <3>[ 10.796061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10925 13:20:30.579260 <6>[ 10.802759] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10926 13:20:30.585714 <3>[ 10.803937] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 13:20:30.595899 <3>[ 10.803997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 13:20:30.602323 <3>[ 10.804001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 13:20:30.609217 <3>[ 10.804005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 13:20:30.619161 <3>[ 10.804834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 13:20:30.626251 <3>[ 10.804860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 13:20:30.635757 <3>[ 10.804864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 13:20:30.642696 <3>[ 10.804869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10934 13:20:30.653162 <3>[ 10.804871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10935 13:20:30.659600 <3>[ 10.811684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10936 13:20:30.666341 <6>[ 10.831951] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10937 13:20:30.672618 <6>[ 10.833679] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10938 13:20:30.679620 <6>[ 10.833693] pci_bus 0000:00: root bus resource [bus 00-ff]
10939 13:20:30.685992 <6>[ 10.833702] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10940 13:20:30.695734 <6>[ 10.833712] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10941 13:20:30.702495 <6>[ 10.833774] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10942 13:20:30.708977 <6>[ 10.833797] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10943 13:20:30.715862 <6>[ 10.833886] pci 0000:00:00.0: supports D1 D2
10944 13:20:30.722392 <6>[ 10.833888] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10945 13:20:30.732164 <6>[ 10.848211] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10946 13:20:30.738769 <6>[ 10.857080] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10947 13:20:30.745368 <6>[ 10.857096] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10948 13:20:30.756924 <6>[ 10.863746] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10949 13:20:30.763185 <6>[ 10.871638] remoteproc remoteproc0: remote processor scp is now up
10950 13:20:30.772663 <6>[ 10.881733] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10951 13:20:30.779806 <4>[ 10.896811] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10952 13:20:30.786356 <4>[ 10.896811] Fallback method does not support PEC.
10953 13:20:30.793265 <6>[ 10.905626] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10954 13:20:30.803022 <3>[ 10.929624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 13:20:30.809870 <6>[ 11.040327] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10956 13:20:30.816154 <3>[ 11.074002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 13:20:30.826185 <6>[ 11.074974] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10958 13:20:30.836266 Startin<6>[ 11.144569] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10959 13:20:30.842499 g [0;1;39msyste<6>[ 11.146974] videodev: Linux video capture interface: v2.00
10960 13:20:30.849601 <6>[ 11.153260] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10961 13:20:30.855882 md-networkd.…i<6>[ 11.167999] pci 0000:01:00.0: supports D1 D2
10962 13:20:30.862664 <6>[ 11.173875] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10963 13:20:30.872399 ce[0m - Network<6>[ 11.175465] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10964 13:20:30.875916 <6>[ 11.181505] Bluetooth: Core ver 2.22
10965 13:20:30.882422 <6>[ 11.191621] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10966 13:20:30.892636 Configuration..<6>[ 11.193642] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10967 13:20:30.893032 .
10968 13:20:30.899784 <6>[ 11.194312] NET: Registered PF_BLUETOOTH protocol family
10969 13:20:30.906231 <6>[ 11.201224] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10970 13:20:30.913076 <6>[ 11.210725] Bluetooth: HCI device and connection manager initialized
10971 13:20:30.919583 <6>[ 11.210758] Bluetooth: HCI socket layer initialized
10972 13:20:30.927270 <6>[ 11.216661] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10973 13:20:30.933667 <6>[ 11.217902] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10974 13:20:30.946988 <6>[ 11.219332] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10975 13:20:30.950480 <6>[ 11.219448] usbcore: registered new interface driver uvcvideo
10976 13:20:30.957181 <6>[ 11.224731] Bluetooth: L2CAP socket layer initialized
10977 13:20:30.967402 <3>[ 11.224919] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 13:20:30.973594 <6>[ 11.231405] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10979 13:20:30.980626 <6>[ 11.236477] Bluetooth: SCO socket layer initialized
10980 13:20:30.987060 <6>[ 11.244482] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10981 13:20:30.996970 <3>[ 11.244854] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 13:20:31.003422 <6>[ 11.245131] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10983 13:20:31.010676 <5>[ 11.254465] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10984 13:20:31.016752 <6>[ 11.263935] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10985 13:20:31.023455 <6>[ 11.263950] pci 0000:00:00.0: PCI bridge to [bus 01]
10986 13:20:31.030462 <6>[ 11.263958] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10987 13:20:31.037256 <6>[ 11.264221] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10988 13:20:31.044256 <5>[ 11.286925] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10989 13:20:31.051373 <6>[ 11.293549] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10990 13:20:31.061080 <5>[ 11.298061] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10991 13:20:31.064425 <6>[ 11.298342] usbcore: registered new interface driver btusb
10992 13:20:31.074972 <4>[ 11.299551] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10993 13:20:31.081915 <3>[ 11.299562] Bluetooth: hci0: Failed to load firmware file (-2)
10994 13:20:31.088381 <3>[ 11.299565] Bluetooth: hci0: Failed to set up firmware (-2)
10995 13:20:31.098332 <4>[ 11.299567] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10996 13:20:31.104514 <6>[ 11.305749] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10997 13:20:31.111670 <4>[ 11.314309] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10998 13:20:31.121570 <3>[ 11.361106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 13:20:31.127936 <6>[ 11.363211] cfg80211: failed to load regulatory.db
11000 13:20:31.134625 <3>[ 11.390911] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 13:20:31.144417 <6>[ 11.405290] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11002 13:20:31.147985 <6>[ 11.461316] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11003 13:20:31.158411 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11004 13:20:31.168959 <6>[ 11.482079] mt7921e 0000:01:00.0: ASIC revision: 79610010
11005 13:20:31.212362 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11006 13:20:31.240730 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11007 13:20:31.273980 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Conf<6>[ 11.583732] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11008 13:20:31.276888 <6>[ 11.583732]
11009 13:20:31.277387 iguration.
11010 13:20:31.301492 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus<3>[ 11.610404] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 13:20:31.301896 .
11012 13:20:31.335011 <3>[ 11.644463] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 13:20:31.368720 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11014 13:20:31.380116 <3>[ 11.689978] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 13:20:31.394213 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11016 13:20:31.419605 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m<3>[ 11.727540] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 13:20:31.420000 - Bluetooth Support.
11018 13:20:31.437218 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11019 13:20:31.457556 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11020 13:20:31.519611 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11021 13:20:31.548051 Startin<6>[ 11.854944] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11022 13:20:31.550879 g [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11023 13:20:31.577584 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11024 13:20:31.597261 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11025 13:20:31.640661 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11026 13:20:31.668092 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11027 13:20:31.690118 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11028 13:20:31.709513 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11029 13:20:31.734208 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11030 13:20:31.787374 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11031 13:20:31.811783 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11032 13:20:31.837811 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11033 13:20:31.882332 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11034 13:20:31.933080
11035 13:20:31.936554 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11036 13:20:31.936938
11037 13:20:31.939861 debian-bookworm-arm64 login: root (automatic login)
11038 13:20:31.940244
11039 13:20:31.952588 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11040 13:20:31.952977
11041 13:20:31.959266 The programs included with the Debian GNU/Linux system are free software;
11042 13:20:31.965896 the exact distribution terms for each program are described in the
11043 13:20:31.969058 individual files in /usr/share/doc/*/copyright.
11044 13:20:31.969493
11045 13:20:31.975713 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11046 13:20:31.978793 permitted by applicable law.
11047 13:20:31.980034 Matched prompt #10: / #
11049 13:20:31.980941 Setting prompt string to ['/ #']
11050 13:20:31.981482 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11052 13:20:31.982389 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
11053 13:20:31.982792 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11054 13:20:31.983099 Setting prompt string to ['/ #']
11055 13:20:31.983450 Forcing a shell prompt, looking for ['/ #']
11056 13:20:31.983736 Sending line: ''
11058 13:20:32.034291 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11059 13:20:32.034362 Waiting using forced prompt support (timeout 00:02:30)
11060 13:20:32.038790 / #
11061 13:20:32.039057 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11062 13:20:32.039151 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11063 13:20:32.039237 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11064 13:20:32.039315 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11065 13:20:32.039395 end: 2 depthcharge-action (duration 00:02:00) [common]
11066 13:20:32.039474 start: 3 lava-test-retry (timeout 00:07:39) [common]
11067 13:20:32.039553 start: 3.1 lava-test-shell (timeout 00:07:39) [common]
11068 13:20:32.039617 Using namespace: common
11069 13:20:32.039680 Sending line: '#'
11071 13:20:32.140102 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11072 13:20:32.144790 / # #
11073 13:20:32.145063 Using /lava-14879043
11074 13:20:32.145176 Sending line: 'export SHELL=/bin/sh'
11076 13:20:32.250473 / # export SHELL=/bin/sh
11077 13:20:32.250766 Sending line: '. /lava-14879043/environment'
11079 13:20:32.356220 / # . /lava-14879043/environment
11080 13:20:32.356502 Sending line: '/lava-14879043/bin/lava-test-runner /lava-14879043/0'
11082 13:20:32.456945 Test shell timeout: 10s (minimum of the action and connection timeout)
11083 13:20:32.457227 / # <6>[ 12.725692] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11084 13:20:32.462325 /lava-14879043/bin/lava-test-runner /lava-14879043/0
11085 13:20:32.490713 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11086 13:20:32.497739 + cd /lava-14879043/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11087 13:20:32.497837 + cat uuid
11088 13:20:32.500654 + UUID=14879043_1.5.2.3.1
11089 13:20:32.500730 + set +x
11090 13:20:32.507122 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14879043_1.5.2.3.1>
11091 13:20:32.507377 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14879043_1.5.2.3.1
11092 13:20:32.507443 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14879043_1.5.2.3.1)
11093 13:20:32.507518 Skipping test definition patterns.
11094 13:20:32.510606 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11095 13:20:32.516958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11096 13:20:32.517059 device: /dev/video2
11097 13:20:32.517343 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11099 13:20:32.541782 <4>[ 12.852171] use of bytesused == 0 is deprecated and will be removed in the future,
11100 13:20:32.544735 <4>[ 12.860013] use the actual size instead.
11101 13:20:32.561175 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11102 13:20:32.572026 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11103 13:20:32.576256
11104 13:20:32.589325 Compliance test for mtk-vcodec-enc device /dev/video2:
11105 13:20:32.595339
11106 13:20:32.604465 Driver Info:
11107 13:20:32.613221 Driver name : mtk-vcodec-enc
11108 13:20:32.626995 Card type : MT8192 video encoder
11109 13:20:32.637742 Bus info : platform:17020000.vcodec
11110 13:20:32.646153 Driver version : 6.1.96
11111 13:20:32.655755 Capabilities : 0x84204000
11112 13:20:32.667293 Video Memory-to-Memory Multiplanar
11113 13:20:32.684154 Streaming
11114 13:20:32.695394 Extended Pix Format
11115 13:20:32.710877 Device Capabilities
11116 13:20:32.722530 Device Caps : 0x04204000
11117 13:20:32.734179 Video Memory-to-Memory Multiplanar
11118 13:20:32.743405 Streaming
11119 13:20:32.754659 Extended Pix Format
11120 13:20:32.765954 Detected Stateful Encoder
11121 13:20:32.782680
11122 13:20:32.792680 Required ioctls:
11123 13:20:32.810440 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11124 13:20:32.810553 test VIDIOC_QUERYCAP: OK
11125 13:20:32.810815 Received signal: <TESTSET> START Required-ioctls
11126 13:20:32.810888 Starting test_set Required-ioctls
11127 13:20:32.833557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11128 13:20:32.833814 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11130 13:20:32.836543 test invalid ioctls: OK
11131 13:20:32.858263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11132 13:20:32.858356
11133 13:20:32.858604 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11135 13:20:32.875104 Allow for multiple opens:
11136 13:20:32.882940 <LAVA_SIGNAL_TESTSET STOP>
11137 13:20:32.883193 Received signal: <TESTSET> STOP
11138 13:20:32.883268 Closing test_set Required-ioctls
11139 13:20:32.892452 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11140 13:20:32.892702 Received signal: <TESTSET> START Allow-for-multiple-opens
11141 13:20:32.892772 Starting test_set Allow-for-multiple-opens
11142 13:20:32.895817 test second /dev/video2 open: OK
11143 13:20:32.918320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11144 13:20:32.918576 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11146 13:20:32.921088 test VIDIOC_QUERYCAP: OK
11147 13:20:32.943685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11148 13:20:32.943967 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11150 13:20:32.946431 test VIDIOC_G/S_PRIORITY: OK
11151 13:20:32.967899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11152 13:20:32.968170 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11154 13:20:32.971176 test for unlimited opens: OK
11155 13:20:32.992505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11156 13:20:32.992604
11157 13:20:32.992852 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11159 13:20:33.007129 Debug ioctls:
11160 13:20:33.015787 <LAVA_SIGNAL_TESTSET STOP>
11161 13:20:33.016071 Received signal: <TESTSET> STOP
11162 13:20:33.016167 Closing test_set Allow-for-multiple-opens
11163 13:20:33.025527 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11164 13:20:33.025780 Received signal: <TESTSET> START Debug-ioctls
11165 13:20:33.025865 Starting test_set Debug-ioctls
11166 13:20:33.028426 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11167 13:20:33.055663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11168 13:20:33.055951 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11170 13:20:33.062045 test VIDIOC_LOG_STATUS: OK (Not Supported)
11171 13:20:33.080331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11172 13:20:33.080418
11173 13:20:33.080663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11175 13:20:33.090797 Input ioctls:
11176 13:20:33.096633 <LAVA_SIGNAL_TESTSET STOP>
11177 13:20:33.096884 Received signal: <TESTSET> STOP
11178 13:20:33.096953 Closing test_set Debug-ioctls
11179 13:20:33.106893 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11180 13:20:33.107141 Received signal: <TESTSET> START Input-ioctls
11181 13:20:33.107210 Starting test_set Input-ioctls
11182 13:20:33.109601 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11183 13:20:33.135159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11184 13:20:33.135424 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11186 13:20:33.138288 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11187 13:20:33.155859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11188 13:20:33.156124 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11190 13:20:33.162688 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11191 13:20:33.183942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11192 13:20:33.184213 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11194 13:20:33.190430 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11195 13:20:33.206340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11196 13:20:33.206603 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11198 13:20:33.209893 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11199 13:20:33.233310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11200 13:20:33.233567 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11202 13:20:33.236533 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11203 13:20:33.257492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11204 13:20:33.257755 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11206 13:20:33.260807 Inputs: 0 Audio Inputs: 0 Tuners: 0
11207 13:20:33.268891
11208 13:20:33.290166 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11209 13:20:33.311726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11210 13:20:33.312030 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11212 13:20:33.318248 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11213 13:20:33.336042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11214 13:20:33.336308 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11216 13:20:33.339586 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11217 13:20:33.367685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11218 13:20:33.367973 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11220 13:20:33.374039 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11221 13:20:33.392602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11222 13:20:33.392880 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11224 13:20:33.398750 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11225 13:20:33.422546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11226 13:20:33.422672
11227 13:20:33.422937 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11229 13:20:33.441861 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11230 13:20:33.463130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11231 13:20:33.463410 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11233 13:20:33.470046 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11234 13:20:33.495992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11235 13:20:33.496274 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11237 13:20:33.499452 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11238 13:20:33.517015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11239 13:20:33.517276 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11241 13:20:33.520412 test VIDIOC_G/S_EDID: OK (Not Supported)
11242 13:20:33.540963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11243 13:20:33.541055
11244 13:20:33.541280 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11246 13:20:33.553390 Control ioctls:
11247 13:20:33.559996 <LAVA_SIGNAL_TESTSET STOP>
11248 13:20:33.560236 Received signal: <TESTSET> STOP
11249 13:20:33.560299 Closing test_set Input-ioctls
11250 13:20:33.569268 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11251 13:20:33.569509 Received signal: <TESTSET> START Control-ioctls
11252 13:20:33.569573 Starting test_set Control-ioctls
11253 13:20:33.572277 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11254 13:20:33.596892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11255 13:20:33.596970 test VIDIOC_QUERYCTRL: OK
11256 13:20:33.597193 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11258 13:20:33.618968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11259 13:20:33.619215 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11261 13:20:33.622045 test VIDIOC_G/S_CTRL: OK
11262 13:20:33.643553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11263 13:20:33.643801 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11265 13:20:33.646945 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11266 13:20:33.668894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11267 13:20:33.669150 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11269 13:20:33.675430 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11270 13:20:33.683331 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11271 13:20:33.712151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11272 13:20:33.712401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11274 13:20:33.715069 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11275 13:20:33.734129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11276 13:20:33.734400 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11278 13:20:33.737563 Standard Controls: 16 Private Controls: 0
11279 13:20:33.745938
11280 13:20:33.756952 Format ioctls:
11281 13:20:33.764081 <LAVA_SIGNAL_TESTSET STOP>
11282 13:20:33.764324 Received signal: <TESTSET> STOP
11283 13:20:33.764385 Closing test_set Control-ioctls
11284 13:20:33.773386 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11285 13:20:33.773629 Received signal: <TESTSET> START Format-ioctls
11286 13:20:33.773715 Starting test_set Format-ioctls
11287 13:20:33.776238 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11288 13:20:33.802010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11289 13:20:33.802255 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11291 13:20:33.805096 test VIDIOC_G/S_PARM: OK
11292 13:20:33.822488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11293 13:20:33.822730 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11295 13:20:33.825219 test VIDIOC_G_FBUF: OK (Not Supported)
11296 13:20:33.846718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11297 13:20:33.846990 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11299 13:20:33.850066 test VIDIOC_G_FMT: OK
11300 13:20:33.871526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11301 13:20:33.871773 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11303 13:20:33.874991 test VIDIOC_TRY_FMT: OK
11304 13:20:33.895844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11305 13:20:33.896087 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11307 13:20:33.902207 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11308 13:20:33.907591 test VIDIOC_S_FMT: FAIL
11309 13:20:33.935840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11310 13:20:33.936102 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11312 13:20:33.939310 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11313 13:20:33.962348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11314 13:20:33.962617 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11316 13:20:33.965593 test Cropping: OK
11317 13:20:33.988248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11318 13:20:33.988541 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11320 13:20:33.991849 test Composing: OK (Not Supported)
11321 13:20:34.016609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11322 13:20:34.016896 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11324 13:20:34.020011 test Scaling: OK (Not Supported)
11325 13:20:34.043416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11326 13:20:34.043525
11327 13:20:34.043753 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11329 13:20:34.054097 Codec ioctls:
11330 13:20:34.060927 <LAVA_SIGNAL_TESTSET STOP>
11331 13:20:34.061154 Received signal: <TESTSET> STOP
11332 13:20:34.061229 Closing test_set Format-ioctls
11333 13:20:34.070832 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11334 13:20:34.071082 Received signal: <TESTSET> START Codec-ioctls
11335 13:20:34.071144 Starting test_set Codec-ioctls
11336 13:20:34.073925 test VIDIOC_(TRY_)ENCODER_CMD: OK
11337 13:20:34.101855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11338 13:20:34.102128 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11340 13:20:34.108268 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11341 13:20:34.125864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11342 13:20:34.126144 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11344 13:20:34.132929 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11345 13:20:34.151953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11346 13:20:34.152047
11347 13:20:34.152274 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11349 13:20:34.163522 Buffer ioctls:
11350 13:20:34.171411 <LAVA_SIGNAL_TESTSET STOP>
11351 13:20:34.171671 Received signal: <TESTSET> STOP
11352 13:20:34.171761 Closing test_set Codec-ioctls
11353 13:20:34.180906 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11354 13:20:34.181135 Received signal: <TESTSET> START Buffer-ioctls
11355 13:20:34.181236 Starting test_set Buffer-ioctls
11356 13:20:34.184281 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11357 13:20:34.210044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11358 13:20:34.210351 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11360 13:20:34.212127 test CREATE_BUFS maximum buffers: OK
11361 13:20:34.230586 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11363 13:20:34.233326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11364 13:20:34.233403 test VIDIOC_EXPBUF: OK
11365 13:20:34.255044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11366 13:20:34.255305 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11368 13:20:34.258266 test Requests: OK (Not Supported)
11369 13:20:34.279901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11370 13:20:34.279995
11371 13:20:34.280220 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11373 13:20:34.292365 Test input 0:
11374 13:20:34.301591
11375 13:20:34.312380 Streaming ioctls:
11376 13:20:34.320195 <LAVA_SIGNAL_TESTSET STOP>
11377 13:20:34.320466 Received signal: <TESTSET> STOP
11378 13:20:34.320539 Closing test_set Buffer-ioctls
11379 13:20:34.330152 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11380 13:20:34.330393 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11381 13:20:34.330456 Starting test_set Streaming-ioctls_Test-input-0
11382 13:20:34.332735 test read/write: OK (Not Supported)
11383 13:20:34.354970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11384 13:20:34.355245 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11386 13:20:34.361915 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11387 13:20:34.374385 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11388 13:20:34.381887 test blocking wait: FAIL
11389 13:20:34.408654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11390 13:20:34.408930 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11392 13:20:34.415249 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11393 13:20:34.420566 test MMAP (select): FAIL
11394 13:20:34.450809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11395 13:20:34.451072 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11397 13:20:34.457191 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11398 13:20:34.461809 test MMAP (epoll): FAIL
11399 13:20:34.486053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11400 13:20:34.486312 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11402 13:20:34.492227 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11403 13:20:34.504874 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11404 13:20:34.512494 test USERPTR (select): FAIL
11405 13:20:34.537604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11406 13:20:34.537861 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11408 13:20:34.544146 test DMABUF: Cannot test, specify --expbuf-device
11409 13:20:34.544221
11410 13:20:34.567986 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11411 13:20:34.574787 <LAVA_TEST_RUNNER EXIT>
11412 13:20:34.575032 ok: lava_test_shell seems to have completed
11413 13:20:34.575104 Marking unfinished test run as failed
11415 13:20:34.575870 device-presence: pass
VIDIOC_QUERYCAP:
set: Allow-for-multiple-opens
result: pass
invalid-ioctls:
set: Required-ioctls
result: pass
second-/dev/video2-open:
set: Allow-for-multiple-opens
result: pass
VIDIOC_G/S_PRIORITY:
set: Allow-for-multiple-opens
result: pass
for-unlimited-opens:
set: Allow-for-multiple-opens
result: pass
VIDIOC_DBG_G/S_REGISTER:
set: Debug-ioctls
result: pass
VIDIOC_LOG_STATUS:
set: Debug-ioctls
result: pass
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
set: Input-ioctls
result: pass
VIDIOC_G/S_FREQUENCY:
set: Input-ioctls
result: pass
VIDIOC_S_HW_FREQ_SEEK:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMINPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S_MODULATOR:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDOUT:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMOUTPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDOUT:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_STD:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
set: Input-ioctls
result: pass
VIDIOC_DV_TIMINGS_CAP:
set: Input-ioctls
result: pass
VIDIOC_G/S_EDID:
set: Input-ioctls
result: pass
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
set: Control-ioctls
result: pass
VIDIOC_QUERYCTRL:
set: Control-ioctls
result: pass
VIDIOC_G/S_CTRL:
set: Control-ioctls
result: pass
VIDIOC_G/S/TRY_EXT_CTRLS:
set: Control-ioctls
result: pass
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
set: Control-ioctls
result: fail
VIDIOC_G/S_JPEGCOMP:
set: Control-ioctls
result: pass
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
set: Format-ioctls
result: pass
VIDIOC_G/S_PARM:
set: Format-ioctls
result: pass
VIDIOC_G_FBUF:
set: Format-ioctls
result: pass
VIDIOC_G_FMT:
set: Format-ioctls
result: pass
VIDIOC_TRY_FMT:
set: Format-ioctls
result: pass
VIDIOC_S_FMT:
set: Format-ioctls
result: fail
VIDIOC_G_SLICED_VBI_CAP:
set: Format-ioctls
result: pass
Cropping:
set: Format-ioctls
result: pass
Composing:
set: Format-ioctls
result: pass
Scaling:
set: Format-ioctls
result: pass
VIDIOC_TRY_ENCODER_CMD:
set: Codec-ioctls
result: pass
VIDIOC_G_ENC_INDEX:
set: Codec-ioctls
result: pass
VIDIOC_TRY_DECODER_CMD:
set: Codec-ioctls
result: pass
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
set: Buffer-ioctls
result: pass
CREATE_BUFS-maximum-buffers:
set: Buffer-ioctls
result: pass
VIDIOC_EXPBUF:
set: Buffer-ioctls
result: pass
Requests:
set: Buffer-ioctls
result: pass
read/write:
set: Streaming-ioctls_Test-input-0
result: pass
blocking-wait:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-select:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-epoll:
set: Streaming-ioctls_Test-input-0
result: fail
USERPTR-select:
set: Streaming-ioctls_Test-input-0
result: fail
11416 13:20:34.575990 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11417 13:20:34.576069 end: 3 lava-test-retry (duration 00:00:03) [common]
11418 13:20:34.576149 start: 4 finalize (timeout 00:07:36) [common]
11419 13:20:34.576230 start: 4.1 power-off (timeout 00:00:30) [common]
11420 13:20:34.576354 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11421 13:20:36.650140 >> Command sent successfully.
11422 13:20:36.653645 Returned 0 in 2 seconds
11423 13:20:36.653811 end: 4.1 power-off (duration 00:00:02) [common]
11425 13:20:36.654026 start: 4.2 read-feedback (timeout 00:07:34) [common]
11426 13:20:36.654158 Listened to connection for namespace 'common' for up to 1s
11427 13:20:37.655202 Finalising connection for namespace 'common'
11428 13:20:37.655350 Disconnecting from shell: Finalise
11429 13:20:37.655418 / #
11430 13:20:37.755666 end: 4.2 read-feedback (duration 00:00:01) [common]
11431 13:20:37.755808 end: 4 finalize (duration 00:00:03) [common]
11432 13:20:37.755911 Cleaning after the job
11433 13:20:37.756003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/ramdisk
11434 13:20:37.760691 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/kernel
11435 13:20:37.774138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/dtb
11436 13:20:37.774349 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879043/tftp-deploy-ccdzcpl7/modules
11437 13:20:37.779705 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879043
11438 13:20:37.844479 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879043
11439 13:20:37.844635 Job finished correctly