Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:02:14.006433 lava-dispatcher, installed at version: 2024.05
2 11:02:14.006623 start: 0 validate
3 11:02:14.006744 Start time: 2024-07-10 11:02:14.006735+00:00 (UTC)
4 11:02:14.006877 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:14.007014 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 11:02:14.277880 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:14.278590 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:02:33.930035 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:02:33.931050 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:02:34.203031 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:02:34.203929 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:02:37.977568 validate duration: 23.97
14 11:02:37.978685 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:02:37.979189 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:02:37.979600 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:02:37.980221 Not decompressing ramdisk as can be used compressed.
18 11:02:37.980642 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 11:02:37.980948 saving as /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/ramdisk/rootfs.cpio.gz
20 11:02:37.981273 total size: 8181887 (7 MB)
21 11:02:38.249540 progress 0 % (0 MB)
22 11:02:38.251795 progress 5 % (0 MB)
23 11:02:38.253904 progress 10 % (0 MB)
24 11:02:38.256089 progress 15 % (1 MB)
25 11:02:38.258123 progress 20 % (1 MB)
26 11:02:38.260282 progress 25 % (1 MB)
27 11:02:38.262317 progress 30 % (2 MB)
28 11:02:38.264487 progress 35 % (2 MB)
29 11:02:38.266520 progress 40 % (3 MB)
30 11:02:38.268725 progress 45 % (3 MB)
31 11:02:38.270787 progress 50 % (3 MB)
32 11:02:38.272925 progress 55 % (4 MB)
33 11:02:38.274897 progress 60 % (4 MB)
34 11:02:38.277026 progress 65 % (5 MB)
35 11:02:38.279027 progress 70 % (5 MB)
36 11:02:38.281138 progress 75 % (5 MB)
37 11:02:38.283158 progress 80 % (6 MB)
38 11:02:38.285319 progress 85 % (6 MB)
39 11:02:38.287274 progress 90 % (7 MB)
40 11:02:38.289438 progress 95 % (7 MB)
41 11:02:38.291407 progress 100 % (7 MB)
42 11:02:38.291598 7 MB downloaded in 0.31 s (25.14 MB/s)
43 11:02:38.291746 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:02:38.291961 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:02:38.292040 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:02:38.292115 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:02:38.292246 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:02:38.292306 saving as /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/kernel/Image
50 11:02:38.292359 total size: 54813184 (52 MB)
51 11:02:38.292413 No compression specified
52 11:02:38.293514 progress 0 % (0 MB)
53 11:02:38.307165 progress 5 % (2 MB)
54 11:02:38.320999 progress 10 % (5 MB)
55 11:02:38.334712 progress 15 % (7 MB)
56 11:02:38.348320 progress 20 % (10 MB)
57 11:02:38.361886 progress 25 % (13 MB)
58 11:02:38.375328 progress 30 % (15 MB)
59 11:02:38.388915 progress 35 % (18 MB)
60 11:02:38.402476 progress 40 % (20 MB)
61 11:02:38.416093 progress 45 % (23 MB)
62 11:02:38.429911 progress 50 % (26 MB)
63 11:02:38.443933 progress 55 % (28 MB)
64 11:02:38.457824 progress 60 % (31 MB)
65 11:02:38.471535 progress 65 % (34 MB)
66 11:02:38.485074 progress 70 % (36 MB)
67 11:02:38.498722 progress 75 % (39 MB)
68 11:02:38.512450 progress 80 % (41 MB)
69 11:02:38.525942 progress 85 % (44 MB)
70 11:02:38.539617 progress 90 % (47 MB)
71 11:02:38.553595 progress 95 % (49 MB)
72 11:02:38.567208 progress 100 % (52 MB)
73 11:02:38.567470 52 MB downloaded in 0.28 s (190.01 MB/s)
74 11:02:38.567637 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:02:38.567846 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:02:38.567963 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:02:38.568038 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:02:38.568166 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:02:38.568230 saving as /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/dtb/mt8192-asurada-spherion-r0.dtb
81 11:02:38.568284 total size: 47258 (0 MB)
82 11:02:38.568338 No compression specified
83 11:02:38.569458 progress 69 % (0 MB)
84 11:02:38.569715 progress 100 % (0 MB)
85 11:02:38.569885 0 MB downloaded in 0.00 s (28.19 MB/s)
86 11:02:38.569998 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:02:38.570196 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:02:38.570271 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:02:38.570345 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:02:38.570451 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:02:38.570512 saving as /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/modules/modules.tar
93 11:02:38.570564 total size: 8607984 (8 MB)
94 11:02:38.570619 Using unxz to decompress xz
95 11:02:38.572073 progress 0 % (0 MB)
96 11:02:38.592921 progress 5 % (0 MB)
97 11:02:38.617174 progress 10 % (0 MB)
98 11:02:38.640956 progress 15 % (1 MB)
99 11:02:38.665804 progress 20 % (1 MB)
100 11:02:38.689886 progress 25 % (2 MB)
101 11:02:38.714108 progress 30 % (2 MB)
102 11:02:38.736883 progress 35 % (2 MB)
103 11:02:38.764015 progress 40 % (3 MB)
104 11:02:38.788561 progress 45 % (3 MB)
105 11:02:38.812936 progress 50 % (4 MB)
106 11:02:38.838505 progress 55 % (4 MB)
107 11:02:38.863042 progress 60 % (4 MB)
108 11:02:38.886558 progress 65 % (5 MB)
109 11:02:38.912211 progress 70 % (5 MB)
110 11:02:38.939230 progress 75 % (6 MB)
111 11:02:38.967066 progress 80 % (6 MB)
112 11:02:38.990810 progress 85 % (7 MB)
113 11:02:39.014303 progress 90 % (7 MB)
114 11:02:39.038075 progress 95 % (7 MB)
115 11:02:39.060973 progress 100 % (8 MB)
116 11:02:39.066434 8 MB downloaded in 0.50 s (16.56 MB/s)
117 11:02:39.066598 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:02:39.066814 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:02:39.066893 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:02:39.067002 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:02:39.067073 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:02:39.067144 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:02:39.067321 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76
125 11:02:39.067435 makedir: /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin
126 11:02:39.067522 makedir: /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/tests
127 11:02:39.067606 makedir: /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/results
128 11:02:39.067693 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-add-keys
129 11:02:39.067830 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-add-sources
130 11:02:39.067973 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-background-process-start
131 11:02:39.068114 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-background-process-stop
132 11:02:39.068251 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-common-functions
133 11:02:39.068412 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-echo-ipv4
134 11:02:39.068550 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-install-packages
135 11:02:39.068661 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-installed-packages
136 11:02:39.068774 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-os-build
137 11:02:39.068914 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-probe-channel
138 11:02:39.069052 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-probe-ip
139 11:02:39.069227 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-target-ip
140 11:02:39.069342 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-target-mac
141 11:02:39.069456 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-target-storage
142 11:02:39.069569 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-test-case
143 11:02:39.069681 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-test-event
144 11:02:39.069792 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-test-feedback
145 11:02:39.069900 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-test-raise
146 11:02:39.070012 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-test-reference
147 11:02:39.070120 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-test-runner
148 11:02:39.070273 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-test-set
149 11:02:39.070435 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-test-shell
150 11:02:39.070601 Updating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-install-packages (oe)
151 11:02:39.070771 Updating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/bin/lava-installed-packages (oe)
152 11:02:39.070915 Creating /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/environment
153 11:02:39.071037 LAVA metadata
154 11:02:39.071128 - LAVA_JOB_ID=14786858
155 11:02:39.071211 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:02:39.071335 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:02:39.071418 skipped lava-vland-overlay
158 11:02:39.071513 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:02:39.071609 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:02:39.071686 skipped lava-multinode-overlay
161 11:02:39.071781 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:02:39.071876 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:02:39.071966 Loading test definitions
164 11:02:39.072069 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:02:39.072154 Using /lava-14786858 at stage 0
166 11:02:39.072547 uuid=14786858_1.5.2.3.1 testdef=None
167 11:02:39.072629 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:02:39.072709 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:02:39.073175 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:02:39.073391 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:02:39.073975 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:02:39.074239 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:02:39.074846 runner path: /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/0/tests/0_dmesg test_uuid 14786858_1.5.2.3.1
176 11:02:39.074989 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:02:39.075244 Creating lava-test-runner.conf files
179 11:02:39.075326 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786858/lava-overlay-zbjqcj76/lava-14786858/0 for stage 0
180 11:02:39.075433 - 0_dmesg
181 11:02:39.075550 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:02:39.075656 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:02:39.082405 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:02:39.082533 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:02:39.082643 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:02:39.082739 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:02:39.082814 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:02:39.319813 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 11:02:39.319959 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 11:02:39.320035 extracting modules file /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786858/extract-overlay-ramdisk-w49dqcfd/ramdisk
191 11:02:39.543270 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:02:39.543413 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:02:39.543490 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786858/compress-overlay-1oh7_p9p/overlay-1.5.2.4.tar.gz to ramdisk
194 11:02:39.543550 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786858/compress-overlay-1oh7_p9p/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786858/extract-overlay-ramdisk-w49dqcfd/ramdisk
195 11:02:39.550133 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:02:39.550231 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:02:39.550311 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:02:39.550386 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:02:39.550450 Building ramdisk /var/lib/lava/dispatcher/tmp/14786858/extract-overlay-ramdisk-w49dqcfd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786858/extract-overlay-ramdisk-w49dqcfd/ramdisk
200 11:02:39.947490 >> 144626 blocks
201 11:02:42.266699 rename /var/lib/lava/dispatcher/tmp/14786858/extract-overlay-ramdisk-w49dqcfd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/ramdisk/ramdisk.cpio.gz
202 11:02:42.266872 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 11:02:42.266960 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 11:02:42.267040 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 11:02:42.267113 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/kernel/Image']
206 11:02:56.662526 Returned 0 in 14 seconds
207 11:02:56.662734 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/kernel/image.itb
208 11:02:57.286538 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:02:57.286671 output: Created: Wed Jul 10 12:02:57 2024
210 11:02:57.286735 output: Image 0 (kernel-1)
211 11:02:57.286790 output: Description:
212 11:02:57.286843 output: Created: Wed Jul 10 12:02:57 2024
213 11:02:57.286895 output: Type: Kernel Image
214 11:02:57.286945 output: Compression: lzma compressed
215 11:02:57.286998 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
216 11:02:57.287048 output: Architecture: AArch64
217 11:02:57.287097 output: OS: Linux
218 11:02:57.287145 output: Load Address: 0x00000000
219 11:02:57.287194 output: Entry Point: 0x00000000
220 11:02:57.287243 output: Hash algo: crc32
221 11:02:57.287292 output: Hash value: 9bb85fb9
222 11:02:57.287341 output: Image 1 (fdt-1)
223 11:02:57.287389 output: Description: mt8192-asurada-spherion-r0
224 11:02:57.287437 output: Created: Wed Jul 10 12:02:57 2024
225 11:02:57.287486 output: Type: Flat Device Tree
226 11:02:57.287534 output: Compression: uncompressed
227 11:02:57.287582 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:02:57.287631 output: Architecture: AArch64
229 11:02:57.287679 output: Hash algo: crc32
230 11:02:57.287727 output: Hash value: 0f8e4d2e
231 11:02:57.287775 output: Image 2 (ramdisk-1)
232 11:02:57.287823 output: Description: unavailable
233 11:02:57.287871 output: Created: Wed Jul 10 12:02:57 2024
234 11:02:57.287920 output: Type: RAMDisk Image
235 11:02:57.287969 output: Compression: uncompressed
236 11:02:57.288016 output: Data Size: 21342431 Bytes = 20842.22 KiB = 20.35 MiB
237 11:02:57.288065 output: Architecture: AArch64
238 11:02:57.288112 output: OS: Linux
239 11:02:57.288160 output: Load Address: unavailable
240 11:02:57.288208 output: Entry Point: unavailable
241 11:02:57.288255 output: Hash algo: crc32
242 11:02:57.288303 output: Hash value: 998f67d2
243 11:02:57.288349 output: Default Configuration: 'conf-1'
244 11:02:57.288397 output: Configuration 0 (conf-1)
245 11:02:57.288445 output: Description: mt8192-asurada-spherion-r0
246 11:02:57.288492 output: Kernel: kernel-1
247 11:02:57.288540 output: Init Ramdisk: ramdisk-1
248 11:02:57.288589 output: FDT: fdt-1
249 11:02:57.288638 output: Loadables: kernel-1
250 11:02:57.288685 output:
251 11:02:57.288790 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 11:02:57.288865 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 11:02:57.288940 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 11:02:57.289014 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 11:02:57.289071 No LXC device requested
256 11:02:57.289167 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:02:57.289258 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 11:02:57.289328 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:02:57.289392 Checking files for TFTP limit of 4294967296 bytes.
260 11:02:57.289921 end: 1 tftp-deploy (duration 00:00:19) [common]
261 11:02:57.290013 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:02:57.290093 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:02:57.290182 substitutions:
264 11:02:57.290241 - {DTB}: 14786858/tftp-deploy-wtiz35rr/dtb/mt8192-asurada-spherion-r0.dtb
265 11:02:57.290298 - {INITRD}: 14786858/tftp-deploy-wtiz35rr/ramdisk/ramdisk.cpio.gz
266 11:02:57.290350 - {KERNEL}: 14786858/tftp-deploy-wtiz35rr/kernel/Image
267 11:02:57.290402 - {LAVA_MAC}: None
268 11:02:57.290453 - {PRESEED_CONFIG}: None
269 11:02:57.290503 - {PRESEED_LOCAL}: None
270 11:02:57.290552 - {RAMDISK}: 14786858/tftp-deploy-wtiz35rr/ramdisk/ramdisk.cpio.gz
271 11:02:57.290611 - {ROOT_PART}: None
272 11:02:57.290663 - {ROOT}: None
273 11:02:57.290712 - {SERVER_IP}: 192.168.201.1
274 11:02:57.290762 - {TEE}: None
275 11:02:57.290811 Parsed boot commands:
276 11:02:57.290859 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:02:57.291000 Parsed boot commands: tftpboot 192.168.201.1 14786858/tftp-deploy-wtiz35rr/kernel/image.itb 14786858/tftp-deploy-wtiz35rr/kernel/cmdline
278 11:02:57.291080 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:02:57.291154 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:02:57.291227 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:02:57.291298 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:02:57.291354 Not connected, no need to disconnect.
283 11:02:57.291421 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:02:57.291489 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:02:57.291544 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 11:02:57.294603 Setting prompt string to ['lava-test: # ']
287 11:02:57.294999 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:02:57.295107 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:02:57.295230 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:02:57.295314 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:02:57.295621 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=reboot']
292 11:03:06.439279 >> Command sent successfully.
293 11:03:06.442568 Returned 0 in 9 seconds
294 11:03:06.442737 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:03:06.443051 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:03:06.443181 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:03:06.443285 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:03:06.443371 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:03:06.443466 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:03:06.443957 [Enter `^Ec?' for help]
302 11:03:07.639723
303 11:03:07.639848
304 11:03:07.639916 F0: 102B 0000
305 11:03:07.639977
306 11:03:07.643643 F3: 1001 0000 [0200]
307 11:03:07.643729
308 11:03:07.643789 F3: 1001 0000
309 11:03:07.643844
310 11:03:07.643896 F7: 102D 0000
311 11:03:07.643947
312 11:03:07.646899 F1: 0000 0000
313 11:03:07.646978
314 11:03:07.647035 V0: 0000 0000 [0001]
315 11:03:07.647088
316 11:03:07.647140 00: 0007 8000
317 11:03:07.650635
318 11:03:07.650714 01: 0000 0000
319 11:03:07.650775
320 11:03:07.650828 BP: 0C00 0209 [0000]
321 11:03:07.650879
322 11:03:07.654373 G0: 1182 0000
323 11:03:07.654451
324 11:03:07.654509 EC: 0000 0021 [4000]
325 11:03:07.654564
326 11:03:07.657817 S7: 0000 0000 [0000]
327 11:03:07.657895
328 11:03:07.657953 CC: 0000 0000 [0001]
329 11:03:07.658007
330 11:03:07.661462 T0: 0000 0040 [010F]
331 11:03:07.661542
332 11:03:07.661600 Jump to BL
333 11:03:07.661653
334 11:03:07.686941
335 11:03:07.687093
336 11:03:07.694225 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:03:07.698134 ARM64: Exception handlers installed.
338 11:03:07.701738 ARM64: Testing exception
339 11:03:07.705955 ARM64: Done test exception
340 11:03:07.712877 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:03:07.719909 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:03:07.726996 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:03:07.738214 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:03:07.745954 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:03:07.752492 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:03:07.764174 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:03:07.770525 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:03:07.790538 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:03:07.793941 WDT: Last reset was cold boot
350 11:03:07.797849 SPI1(PAD0) initialized at 2873684 Hz
351 11:03:07.801510 SPI5(PAD0) initialized at 992727 Hz
352 11:03:07.801599 VBOOT: Loading verstage.
353 11:03:07.808222 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:03:07.811538 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:03:07.814566 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:03:07.821378 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:03:07.828501 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:03:07.834868 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:03:07.844414 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 11:03:07.844534
361 11:03:07.844596
362 11:03:07.854364 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:03:07.857785 ARM64: Exception handlers installed.
364 11:03:07.861295 ARM64: Testing exception
365 11:03:07.861378 ARM64: Done test exception
366 11:03:07.867785 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:03:07.871183 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:03:07.885591 Probing TPM: . done!
369 11:03:07.885735 TPM ready after 0 ms
370 11:03:07.892387 Connected to device vid:did:rid of 1ae0:0028:00
371 11:03:07.899090 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
372 11:03:07.953937 Initialized TPM device CR50 revision 0
373 11:03:07.963720 tlcl_send_startup: Startup return code is 0
374 11:03:07.963843 TPM: setup succeeded
375 11:03:07.974992 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:03:07.984195 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:03:07.994083 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:03:08.002820 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:03:08.006115 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:03:08.009635 in-header: 03 07 00 00 08 00 00 00
381 11:03:08.012784 in-data: aa e4 47 04 13 02 00 00
382 11:03:08.016068 Chrome EC: UHEPI supported
383 11:03:08.023349 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:03:08.026409 in-header: 03 a9 00 00 08 00 00 00
385 11:03:08.029627 in-data: 84 60 60 08 00 00 00 00
386 11:03:08.029710 Phase 1
387 11:03:08.032485 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:03:08.039503 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:03:08.045938 VB2:vb2_check_recovery() Recovery was requested manually
390 11:03:08.049378 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:03:08.052769 Recovery requested (1009000e)
392 11:03:08.061060 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:03:08.066464 tlcl_extend: response is 0
394 11:03:08.077202 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:03:08.080594 tlcl_extend: response is 0
396 11:03:08.086775 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:03:08.107309 read SPI 0x210d4 0x2173b: 15141 us, 9049 KB/s, 72.392 Mbps
398 11:03:08.113748 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:03:08.113856
400 11:03:08.113916
401 11:03:08.124053 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:03:08.127002 ARM64: Exception handlers installed.
403 11:03:08.130920 ARM64: Testing exception
404 11:03:08.131008 ARM64: Done test exception
405 11:03:08.152376 pmic_efuse_setting: Set efuses in 11 msecs
406 11:03:08.155964 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:03:08.162726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:03:08.165731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:03:08.172730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:03:08.175774 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:03:08.182671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:03:08.186031 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:03:08.189509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:03:08.196056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:03:08.199439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:03:08.206241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:03:08.209645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:03:08.212500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:03:08.219191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:03:08.225633 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:03:08.228872 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:03:08.235462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:03:08.242275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:03:08.249263 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:03:08.252734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:03:08.259094 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:03:08.265850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:03:08.268916 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:03:08.275591 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:03:08.282727 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:03:08.286262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:03:08.292795 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:03:08.295427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:03:08.302622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:03:08.305702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:03:08.312328 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:03:08.315868 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:03:08.323302 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:03:08.325628 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:03:08.332689 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:03:08.335925 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:03:08.342674 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:03:08.345843 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:03:08.353129 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:03:08.355853 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:03:08.359288 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:03:08.365680 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:03:08.368924 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:03:08.372409 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:03:08.379061 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:03:08.382818 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:03:08.385877 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:03:08.389526 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:03:08.395476 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:03:08.399290 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:03:08.402353 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:03:08.405815 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:03:08.415994 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:03:08.425722 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:03:08.429023 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:03:08.435312 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:03:08.445606 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:03:08.448963 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:03:08.455835 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:03:08.458704 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:03:08.465588 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
467 11:03:08.471895 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:03:08.475366 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 11:03:08.478665 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:03:08.490122 [RTC]rtc_get_frequency_meter,154: input=15, output=853
471 11:03:08.499834 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 11:03:08.509492 [RTC]rtc_get_frequency_meter,154: input=11, output=790
473 11:03:08.518609 [RTC]rtc_get_frequency_meter,154: input=13, output=822
474 11:03:08.528309 [RTC]rtc_get_frequency_meter,154: input=12, output=807
475 11:03:08.537368 [RTC]rtc_get_frequency_meter,154: input=11, output=790
476 11:03:08.547003 [RTC]rtc_get_frequency_meter,154: input=12, output=806
477 11:03:08.550094 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 11:03:08.557407 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 11:03:08.560673 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:03:08.564584 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 11:03:08.570918 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:03:08.574359 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 11:03:08.577574 ADC[4]: Raw value=904064 ID=7
484 11:03:08.577658 ADC[3]: Raw value=213177 ID=1
485 11:03:08.580553 RAM Code: 0x71
486 11:03:08.583914 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:03:08.590590 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:03:08.597007 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:03:08.603753 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:03:08.607393 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:03:08.610195 in-header: 03 07 00 00 08 00 00 00
492 11:03:08.613657 in-data: aa e4 47 04 13 02 00 00
493 11:03:08.617003 Chrome EC: UHEPI supported
494 11:03:08.623611 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:03:08.626843 in-header: 03 a9 00 00 08 00 00 00
496 11:03:08.630200 in-data: 84 60 60 08 00 00 00 00
497 11:03:08.633616 MRC: failed to locate region type 0.
498 11:03:08.640186 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:03:08.643782 DRAM-K: Running full calibration
500 11:03:08.650516 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:03:08.653665 header.status = 0x0
502 11:03:08.657303 header.version = 0x6 (expected: 0x6)
503 11:03:08.660126 header.size = 0xd00 (expected: 0xd00)
504 11:03:08.660234 header.flags = 0x0
505 11:03:08.667007 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:03:08.684573 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 11:03:08.690921 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:03:08.694378 dram_init: ddr_geometry: 2
509 11:03:08.697921 [EMI] MDL number = 2
510 11:03:08.698030 [EMI] Get MDL freq = 0
511 11:03:08.701376 dram_init: ddr_type: 0
512 11:03:08.701475 is_discrete_lpddr4: 1
513 11:03:08.704755 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:03:08.704853
515 11:03:08.704943
516 11:03:08.708008 [Bian_co] ETT version 0.0.0.1
517 11:03:08.714649 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:03:08.714749
519 11:03:08.717623 dramc_set_vcore_voltage set vcore to 650000
520 11:03:08.717727 Read voltage for 800, 4
521 11:03:08.720931 Vio18 = 0
522 11:03:08.721029 Vcore = 650000
523 11:03:08.721119 Vdram = 0
524 11:03:08.724261 Vddq = 0
525 11:03:08.724354 Vmddr = 0
526 11:03:08.727669 dram_init: config_dvfs: 1
527 11:03:08.731165 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:03:08.737873 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:03:08.741421 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:03:08.744334 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:03:08.747582 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:03:08.752061 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:03:08.754310 MEM_TYPE=3, freq_sel=18
534 11:03:08.757959 sv_algorithm_assistance_LP4_1600
535 11:03:08.761030 ============ PULL DRAM RESETB DOWN ============
536 11:03:08.764540 ========== PULL DRAM RESETB DOWN end =========
537 11:03:08.770973 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:03:08.774273 ===================================
539 11:03:08.777747 LPDDR4 DRAM CONFIGURATION
540 11:03:08.780999 ===================================
541 11:03:08.781106 EX_ROW_EN[0] = 0x0
542 11:03:08.784206 EX_ROW_EN[1] = 0x0
543 11:03:08.784287 LP4Y_EN = 0x0
544 11:03:08.787964 WORK_FSP = 0x0
545 11:03:08.788046 WL = 0x2
546 11:03:08.791086 RL = 0x2
547 11:03:08.791166 BL = 0x2
548 11:03:08.794441 RPST = 0x0
549 11:03:08.794521 RD_PRE = 0x0
550 11:03:08.797607 WR_PRE = 0x1
551 11:03:08.797686 WR_PST = 0x0
552 11:03:08.800941 DBI_WR = 0x0
553 11:03:08.801021 DBI_RD = 0x0
554 11:03:08.804340 OTF = 0x1
555 11:03:08.807671 ===================================
556 11:03:08.811205 ===================================
557 11:03:08.811292 ANA top config
558 11:03:08.814435 ===================================
559 11:03:08.817818 DLL_ASYNC_EN = 0
560 11:03:08.820931 ALL_SLAVE_EN = 1
561 11:03:08.824325 NEW_RANK_MODE = 1
562 11:03:08.824438 DLL_IDLE_MODE = 1
563 11:03:08.828337 LP45_APHY_COMB_EN = 1
564 11:03:08.831107 TX_ODT_DIS = 1
565 11:03:08.834250 NEW_8X_MODE = 1
566 11:03:08.837623 ===================================
567 11:03:08.841021 ===================================
568 11:03:08.844032 data_rate = 1600
569 11:03:08.844139 CKR = 1
570 11:03:08.847427 DQ_P2S_RATIO = 8
571 11:03:08.851182 ===================================
572 11:03:08.853927 CA_P2S_RATIO = 8
573 11:03:08.858093 DQ_CA_OPEN = 0
574 11:03:08.861066 DQ_SEMI_OPEN = 0
575 11:03:08.863983 CA_SEMI_OPEN = 0
576 11:03:08.864082 CA_FULL_RATE = 0
577 11:03:08.867430 DQ_CKDIV4_EN = 1
578 11:03:08.870816 CA_CKDIV4_EN = 1
579 11:03:08.873998 CA_PREDIV_EN = 0
580 11:03:08.877551 PH8_DLY = 0
581 11:03:08.880702 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:03:08.880802 DQ_AAMCK_DIV = 4
583 11:03:08.883868 CA_AAMCK_DIV = 4
584 11:03:08.887506 CA_ADMCK_DIV = 4
585 11:03:08.891164 DQ_TRACK_CA_EN = 0
586 11:03:08.894363 CA_PICK = 800
587 11:03:08.897343 CA_MCKIO = 800
588 11:03:08.897441 MCKIO_SEMI = 0
589 11:03:08.900804 PLL_FREQ = 3068
590 11:03:08.904663 DQ_UI_PI_RATIO = 32
591 11:03:08.907130 CA_UI_PI_RATIO = 0
592 11:03:08.910571 ===================================
593 11:03:08.913927 ===================================
594 11:03:08.917016 memory_type:LPDDR4
595 11:03:08.917097 GP_NUM : 10
596 11:03:08.920872 SRAM_EN : 1
597 11:03:08.923899 MD32_EN : 0
598 11:03:08.927732 ===================================
599 11:03:08.927819 [ANA_INIT] >>>>>>>>>>>>>>
600 11:03:08.930566 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:03:08.934083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:03:08.937537 ===================================
603 11:03:08.940543 data_rate = 1600,PCW = 0X7600
604 11:03:08.943787 ===================================
605 11:03:08.947019 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:03:08.953960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:03:08.957428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:03:08.963624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:03:08.967386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:03:08.970369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:03:08.970453 [ANA_INIT] flow start
612 11:03:08.973875 [ANA_INIT] PLL >>>>>>>>
613 11:03:08.976923 [ANA_INIT] PLL <<<<<<<<
614 11:03:08.980705 [ANA_INIT] MIDPI >>>>>>>>
615 11:03:08.980791 [ANA_INIT] MIDPI <<<<<<<<
616 11:03:08.983616 [ANA_INIT] DLL >>>>>>>>
617 11:03:08.983695 [ANA_INIT] flow end
618 11:03:08.990389 ============ LP4 DIFF to SE enter ============
619 11:03:08.993693 ============ LP4 DIFF to SE exit ============
620 11:03:08.997078 [ANA_INIT] <<<<<<<<<<<<<
621 11:03:09.000521 [Flow] Enable top DCM control >>>>>
622 11:03:09.004015 [Flow] Enable top DCM control <<<<<
623 11:03:09.007070 Enable DLL master slave shuffle
624 11:03:09.010841 ==============================================================
625 11:03:09.013885 Gating Mode config
626 11:03:09.017100 ==============================================================
627 11:03:09.020419 Config description:
628 11:03:09.030086 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:03:09.036882 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:03:09.040262 SELPH_MODE 0: By rank 1: By Phase
631 11:03:09.047364 ==============================================================
632 11:03:09.050140 GAT_TRACK_EN = 1
633 11:03:09.053925 RX_GATING_MODE = 2
634 11:03:09.056992 RX_GATING_TRACK_MODE = 2
635 11:03:09.060286 SELPH_MODE = 1
636 11:03:09.060369 PICG_EARLY_EN = 1
637 11:03:09.063449 VALID_LAT_VALUE = 1
638 11:03:09.070347 ==============================================================
639 11:03:09.073722 Enter into Gating configuration >>>>
640 11:03:09.077024 Exit from Gating configuration <<<<
641 11:03:09.080254 Enter into DVFS_PRE_config >>>>>
642 11:03:09.090303 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:03:09.093681 Exit from DVFS_PRE_config <<<<<
644 11:03:09.096591 Enter into PICG configuration >>>>
645 11:03:09.100284 Exit from PICG configuration <<<<
646 11:03:09.103504 [RX_INPUT] configuration >>>>>
647 11:03:09.107153 [RX_INPUT] configuration <<<<<
648 11:03:09.110261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:03:09.116602 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:03:09.123893 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:03:09.129987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:03:09.136581 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:03:09.139949 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:03:09.146533 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:03:09.150570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:03:09.153079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:03:09.157066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:03:09.160296 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:03:09.167705 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:03:09.171456 ===================================
661 11:03:09.171575 LPDDR4 DRAM CONFIGURATION
662 11:03:09.175267 ===================================
663 11:03:09.179104 EX_ROW_EN[0] = 0x0
664 11:03:09.179206 EX_ROW_EN[1] = 0x0
665 11:03:09.182722 LP4Y_EN = 0x0
666 11:03:09.182823 WORK_FSP = 0x0
667 11:03:09.186756 WL = 0x2
668 11:03:09.186859 RL = 0x2
669 11:03:09.186943 BL = 0x2
670 11:03:09.189924 RPST = 0x0
671 11:03:09.190019 RD_PRE = 0x0
672 11:03:09.193788 WR_PRE = 0x1
673 11:03:09.193886 WR_PST = 0x0
674 11:03:09.196872 DBI_WR = 0x0
675 11:03:09.196968 DBI_RD = 0x0
676 11:03:09.200710 OTF = 0x1
677 11:03:09.204115 ===================================
678 11:03:09.206878 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:03:09.210242 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:03:09.217048 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:03:09.220129 ===================================
682 11:03:09.220241 LPDDR4 DRAM CONFIGURATION
683 11:03:09.223829 ===================================
684 11:03:09.227112 EX_ROW_EN[0] = 0x10
685 11:03:09.230175 EX_ROW_EN[1] = 0x0
686 11:03:09.230260 LP4Y_EN = 0x0
687 11:03:09.233739 WORK_FSP = 0x0
688 11:03:09.233818 WL = 0x2
689 11:03:09.236738 RL = 0x2
690 11:03:09.236817 BL = 0x2
691 11:03:09.240401 RPST = 0x0
692 11:03:09.240481 RD_PRE = 0x0
693 11:03:09.243453 WR_PRE = 0x1
694 11:03:09.243551 WR_PST = 0x0
695 11:03:09.246941 DBI_WR = 0x0
696 11:03:09.247040 DBI_RD = 0x0
697 11:03:09.249944 OTF = 0x1
698 11:03:09.253538 ===================================
699 11:03:09.260488 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:03:09.263231 nWR fixed to 40
701 11:03:09.263317 [ModeRegInit_LP4] CH0 RK0
702 11:03:09.267245 [ModeRegInit_LP4] CH0 RK1
703 11:03:09.270327 [ModeRegInit_LP4] CH1 RK0
704 11:03:09.273438 [ModeRegInit_LP4] CH1 RK1
705 11:03:09.273545 match AC timing 13
706 11:03:09.280078 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:03:09.283136 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:03:09.286630 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:03:09.293337 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:03:09.296633 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:03:09.296741 [EMI DOE] emi_dcm 0
712 11:03:09.303422 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:03:09.303529 ==
714 11:03:09.306345 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:03:09.309688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:03:09.309797 ==
717 11:03:09.316576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:03:09.319707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:03:09.330340 [CA 0] Center 37 (7~68) winsize 62
720 11:03:09.335008 [CA 1] Center 37 (6~68) winsize 63
721 11:03:09.337127 [CA 2] Center 34 (4~65) winsize 62
722 11:03:09.340566 [CA 3] Center 34 (4~65) winsize 62
723 11:03:09.343548 [CA 4] Center 33 (3~64) winsize 62
724 11:03:09.347135 [CA 5] Center 33 (3~64) winsize 62
725 11:03:09.347217
726 11:03:09.350325 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:03:09.350404
728 11:03:09.353608 [CATrainingPosCal] consider 1 rank data
729 11:03:09.357190 u2DelayCellTimex100 = 270/100 ps
730 11:03:09.360199 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:03:09.363892 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:03:09.370490 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 11:03:09.373881 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:03:09.376739 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 11:03:09.380352 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:03:09.380461
737 11:03:09.383501 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:03:09.383594
739 11:03:09.386810 [CBTSetCACLKResult] CA Dly = 33
740 11:03:09.386891 CS Dly: 5 (0~36)
741 11:03:09.386952 ==
742 11:03:09.390331 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:03:09.397416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:03:09.397512 ==
745 11:03:09.400505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:03:09.407060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:03:09.416687 [CA 0] Center 38 (7~69) winsize 63
748 11:03:09.420240 [CA 1] Center 37 (7~68) winsize 62
749 11:03:09.423332 [CA 2] Center 35 (5~66) winsize 62
750 11:03:09.426622 [CA 3] Center 35 (4~66) winsize 63
751 11:03:09.429707 [CA 4] Center 34 (3~65) winsize 63
752 11:03:09.433039 [CA 5] Center 33 (3~64) winsize 62
753 11:03:09.433122
754 11:03:09.436900 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:03:09.436982
756 11:03:09.439864 [CATrainingPosCal] consider 2 rank data
757 11:03:09.443481 u2DelayCellTimex100 = 270/100 ps
758 11:03:09.446291 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:03:09.453630 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:03:09.457248 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
761 11:03:09.459500 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:03:09.463085 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 11:03:09.466472 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:03:09.466574
765 11:03:09.469679 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:03:09.469779
767 11:03:09.472996 [CBTSetCACLKResult] CA Dly = 33
768 11:03:09.473097 CS Dly: 6 (0~38)
769 11:03:09.476314
770 11:03:09.479934 ----->DramcWriteLeveling(PI) begin...
771 11:03:09.480016 ==
772 11:03:09.483224 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:03:09.486430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:03:09.486511 ==
775 11:03:09.489825 Write leveling (Byte 0): 29 => 29
776 11:03:09.493116 Write leveling (Byte 1): 27 => 27
777 11:03:09.496777 DramcWriteLeveling(PI) end<-----
778 11:03:09.496860
779 11:03:09.496920 ==
780 11:03:09.499383 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:03:09.502992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:03:09.503074 ==
783 11:03:09.506190 [Gating] SW mode calibration
784 11:03:09.513113 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:03:09.519797 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:03:09.522697 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:03:09.526592 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:03:09.533271 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 11:03:09.536467 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:03:09.539528 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:03:09.542769 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:03:09.549633 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:03:09.553128 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:03:09.556435 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:03:09.563083 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:03:09.566360 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:03:09.569486 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:03:09.576397 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:03:09.579576 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:03:09.582907 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:03:09.589792 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:03:09.592713 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:03:09.596510 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:03:09.602953 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 11:03:09.606126 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:03:09.609631 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:03:09.616122 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:03:09.619411 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:03:09.622755 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:03:09.629301 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:03:09.632774 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:03:09.636239 0 9 8 | B1->B0 | 2323 3333 | 1 0 | (1 1) (1 1)
813 11:03:09.642598 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
814 11:03:09.646003 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:03:09.648975 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:03:09.655769 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:03:09.659201 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:03:09.662951 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:03:09.666172 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
820 11:03:09.672524 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
821 11:03:09.675587 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
822 11:03:09.679327 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:03:09.685893 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:03:09.689345 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:03:09.692175 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:03:09.699120 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:03:09.702296 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 11:03:09.705834 0 11 8 | B1->B0 | 2e2e 4545 | 0 0 | (0 0) (0 0)
829 11:03:09.712385 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
830 11:03:09.715879 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:03:09.718967 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:03:09.725693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:03:09.729357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:03:09.731985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:03:09.739085 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 11:03:09.742677 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 11:03:09.746096 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:03:09.749681 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:03:09.756098 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:03:09.759960 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:03:09.762876 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:03:09.769350 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:03:09.772692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:03:09.775939 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:03:09.783053 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:03:09.786167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:03:09.789732 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:03:09.795950 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:03:09.799529 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:03:09.802759 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:03:09.809737 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:03:09.812640 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 11:03:09.815948 Total UI for P1: 0, mck2ui 16
854 11:03:09.819457 best dqsien dly found for B0: ( 0, 14, 4)
855 11:03:09.822954 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:03:09.826039 Total UI for P1: 0, mck2ui 16
857 11:03:09.829289 best dqsien dly found for B1: ( 0, 14, 8)
858 11:03:09.832724 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 11:03:09.835778 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:03:09.835859
861 11:03:09.839244 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 11:03:09.845852 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:03:09.845956 [Gating] SW calibration Done
864 11:03:09.846053 ==
865 11:03:09.849062 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:03:09.855700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:03:09.855796 ==
868 11:03:09.855857 RX Vref Scan: 0
869 11:03:09.855914
870 11:03:09.859548 RX Vref 0 -> 0, step: 1
871 11:03:09.859630
872 11:03:09.862614 RX Delay -130 -> 252, step: 16
873 11:03:09.866058 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:03:09.869180 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 11:03:09.872460 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:03:09.879686 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:03:09.882837 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 11:03:09.885810 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 11:03:09.889289 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:03:09.892578 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 11:03:09.895927 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 11:03:09.902759 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 11:03:09.906111 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 11:03:09.909073 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:03:09.912332 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:03:09.919430 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 11:03:09.923076 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 11:03:09.925783 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 11:03:09.925874 ==
890 11:03:09.929756 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:03:09.933016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:03:09.933116 ==
893 11:03:09.936269 DQS Delay:
894 11:03:09.936371 DQS0 = 0, DQS1 = 0
895 11:03:09.936457 DQM Delay:
896 11:03:09.939384 DQM0 = 88, DQM1 = 75
897 11:03:09.939467 DQ Delay:
898 11:03:09.942573 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 11:03:09.946379 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 11:03:09.949562 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
901 11:03:09.953016 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 11:03:09.953179
903 11:03:09.953247
904 11:03:09.953309 ==
905 11:03:09.955997 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:03:09.962973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:03:09.963213 ==
908 11:03:09.963318
909 11:03:09.963410
910 11:03:09.963498 TX Vref Scan disable
911 11:03:09.966107 == TX Byte 0 ==
912 11:03:09.969878 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
913 11:03:09.976062 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
914 11:03:09.976209 == TX Byte 1 ==
915 11:03:09.979531 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 11:03:09.986940 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 11:03:09.987064 ==
918 11:03:09.989370 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:03:09.992543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:03:09.992714 ==
921 11:03:10.005677 TX Vref=22, minBit 0, minWin=27, winSum=439
922 11:03:10.008717 TX Vref=24, minBit 0, minWin=27, winSum=444
923 11:03:10.011888 TX Vref=26, minBit 0, minWin=27, winSum=445
924 11:03:10.015684 TX Vref=28, minBit 3, minWin=27, winSum=447
925 11:03:10.018819 TX Vref=30, minBit 2, minWin=27, winSum=451
926 11:03:10.022512 TX Vref=32, minBit 1, minWin=27, winSum=445
927 11:03:10.028559 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
928 11:03:10.028705
929 11:03:10.032059 Final TX Range 1 Vref 30
930 11:03:10.032177
931 11:03:10.032268 ==
932 11:03:10.035419 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:03:10.039178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:03:10.039301 ==
935 11:03:10.039388
936 11:03:10.041844
937 11:03:10.041982 TX Vref Scan disable
938 11:03:10.045532 == TX Byte 0 ==
939 11:03:10.048887 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 11:03:10.055166 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 11:03:10.055292 == TX Byte 1 ==
942 11:03:10.058451 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 11:03:10.064888 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 11:03:10.065008
945 11:03:10.065070 [DATLAT]
946 11:03:10.065126 Freq=800, CH0 RK0
947 11:03:10.065242
948 11:03:10.068250 DATLAT Default: 0xa
949 11:03:10.068336 0, 0xFFFF, sum = 0
950 11:03:10.071931 1, 0xFFFF, sum = 0
951 11:03:10.072025 2, 0xFFFF, sum = 0
952 11:03:10.075020 3, 0xFFFF, sum = 0
953 11:03:10.078364 4, 0xFFFF, sum = 0
954 11:03:10.078473 5, 0xFFFF, sum = 0
955 11:03:10.081750 6, 0xFFFF, sum = 0
956 11:03:10.081855 7, 0xFFFF, sum = 0
957 11:03:10.084884 8, 0xFFFF, sum = 0
958 11:03:10.084977 9, 0x0, sum = 1
959 11:03:10.088079 10, 0x0, sum = 2
960 11:03:10.088180 11, 0x0, sum = 3
961 11:03:10.088241 12, 0x0, sum = 4
962 11:03:10.091454 best_step = 10
963 11:03:10.091547
964 11:03:10.091607 ==
965 11:03:10.094893 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:03:10.098179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:03:10.098281 ==
968 11:03:10.101480 RX Vref Scan: 1
969 11:03:10.101583
970 11:03:10.104975 Set Vref Range= 32 -> 127
971 11:03:10.105093
972 11:03:10.105215 RX Vref 32 -> 127, step: 1
973 11:03:10.105280
974 11:03:10.107934 RX Delay -111 -> 252, step: 8
975 11:03:10.108049
976 11:03:10.111923 Set Vref, RX VrefLevel [Byte0]: 32
977 11:03:10.114581 [Byte1]: 32
978 11:03:10.118096
979 11:03:10.118238 Set Vref, RX VrefLevel [Byte0]: 33
980 11:03:10.121458 [Byte1]: 33
981 11:03:10.125485
982 11:03:10.125616 Set Vref, RX VrefLevel [Byte0]: 34
983 11:03:10.129050 [Byte1]: 34
984 11:03:10.133453
985 11:03:10.133545 Set Vref, RX VrefLevel [Byte0]: 35
986 11:03:10.136595 [Byte1]: 35
987 11:03:10.141805
988 11:03:10.141903 Set Vref, RX VrefLevel [Byte0]: 36
989 11:03:10.144478 [Byte1]: 36
990 11:03:10.148846
991 11:03:10.148933 Set Vref, RX VrefLevel [Byte0]: 37
992 11:03:10.151921 [Byte1]: 37
993 11:03:10.156699
994 11:03:10.156794 Set Vref, RX VrefLevel [Byte0]: 38
995 11:03:10.159376 [Byte1]: 38
996 11:03:10.163879
997 11:03:10.163965 Set Vref, RX VrefLevel [Byte0]: 39
998 11:03:10.167521 [Byte1]: 39
999 11:03:10.171859
1000 11:03:10.171949 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:03:10.174958 [Byte1]: 40
1002 11:03:10.179287
1003 11:03:10.179379 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:03:10.182909 [Byte1]: 41
1005 11:03:10.186844
1006 11:03:10.186932 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:03:10.190202 [Byte1]: 42
1008 11:03:10.194562
1009 11:03:10.194653 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:03:10.197777 [Byte1]: 43
1011 11:03:10.202597
1012 11:03:10.202687 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:03:10.205310 [Byte1]: 44
1014 11:03:10.209944
1015 11:03:10.210041 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:03:10.212939 [Byte1]: 45
1017 11:03:10.217986
1018 11:03:10.218077 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:03:10.220827 [Byte1]: 46
1020 11:03:10.224944
1021 11:03:10.228522 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:03:10.231664 [Byte1]: 47
1023 11:03:10.231775
1024 11:03:10.234622 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:03:10.238399 [Byte1]: 48
1026 11:03:10.238488
1027 11:03:10.241845 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:03:10.244785 [Byte1]: 49
1029 11:03:10.244865
1030 11:03:10.248217 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:03:10.251806 [Byte1]: 50
1032 11:03:10.255530
1033 11:03:10.255632 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:03:10.259078 [Byte1]: 51
1035 11:03:10.263912
1036 11:03:10.264004 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:03:10.266915 [Byte1]: 52
1038 11:03:10.271019
1039 11:03:10.271106 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:03:10.274474 [Byte1]: 53
1041 11:03:10.278700
1042 11:03:10.278784 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:03:10.282005 [Byte1]: 54
1044 11:03:10.286615
1045 11:03:10.286710 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:03:10.289296 [Byte1]: 55
1047 11:03:10.293758
1048 11:03:10.293847 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:03:10.297247 [Byte1]: 56
1050 11:03:10.301353
1051 11:03:10.301439 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:03:10.304713 [Byte1]: 57
1053 11:03:10.309160
1054 11:03:10.309293 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:03:10.312478 [Byte1]: 58
1056 11:03:10.317076
1057 11:03:10.317204 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:03:10.320900 [Byte1]: 59
1059 11:03:10.324665
1060 11:03:10.324756 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:03:10.327592 [Byte1]: 60
1062 11:03:10.332077
1063 11:03:10.332171 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:03:10.335478 [Byte1]: 61
1065 11:03:10.340074
1066 11:03:10.340163 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:03:10.342901 [Byte1]: 62
1068 11:03:10.347549
1069 11:03:10.347635 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:03:10.350784 [Byte1]: 63
1071 11:03:10.355358
1072 11:03:10.355450 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:03:10.358565 [Byte1]: 64
1074 11:03:10.362971
1075 11:03:10.363060 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:03:10.366183 [Byte1]: 65
1077 11:03:10.370479
1078 11:03:10.370564 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:03:10.373604 [Byte1]: 66
1080 11:03:10.378234
1081 11:03:10.378326 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:03:10.381167 [Byte1]: 67
1083 11:03:10.385517
1084 11:03:10.385601 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:03:10.389471 [Byte1]: 68
1086 11:03:10.393123
1087 11:03:10.393216 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:03:10.396647 [Byte1]: 69
1089 11:03:10.400929
1090 11:03:10.401014 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:03:10.404251 [Byte1]: 70
1092 11:03:10.408637
1093 11:03:10.408725 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:03:10.411892 [Byte1]: 71
1095 11:03:10.416243
1096 11:03:10.416335 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:03:10.419641 [Byte1]: 72
1098 11:03:10.424172
1099 11:03:10.424260 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:03:10.427725 [Byte1]: 73
1101 11:03:10.431532
1102 11:03:10.431614 Final RX Vref Byte 0 = 56 to rank0
1103 11:03:10.434930 Final RX Vref Byte 1 = 61 to rank0
1104 11:03:10.438122 Final RX Vref Byte 0 = 56 to rank1
1105 11:03:10.441696 Final RX Vref Byte 1 = 61 to rank1==
1106 11:03:10.444693 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 11:03:10.451433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 11:03:10.451530 ==
1109 11:03:10.451590 DQS Delay:
1110 11:03:10.451645 DQS0 = 0, DQS1 = 0
1111 11:03:10.454882 DQM Delay:
1112 11:03:10.454959 DQM0 = 88, DQM1 = 76
1113 11:03:10.458090 DQ Delay:
1114 11:03:10.461269 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1115 11:03:10.464537 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1116 11:03:10.467971 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1117 11:03:10.471404 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1118 11:03:10.471488
1119 11:03:10.471547
1120 11:03:10.477742 [DQSOSCAuto] RK0, (LSB)MR18= 0x362f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
1121 11:03:10.481400 CH0 RK0: MR19=606, MR18=362F
1122 11:03:10.487670 CH0_RK0: MR19=0x606, MR18=0x362F, DQSOSC=396, MR23=63, INC=94, DEC=62
1123 11:03:10.487773
1124 11:03:10.491130 ----->DramcWriteLeveling(PI) begin...
1125 11:03:10.491213 ==
1126 11:03:10.494405 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 11:03:10.498449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 11:03:10.498563 ==
1129 11:03:10.501181 Write leveling (Byte 0): 30 => 30
1130 11:03:10.504191 Write leveling (Byte 1): 24 => 24
1131 11:03:10.507471 DramcWriteLeveling(PI) end<-----
1132 11:03:10.507576
1133 11:03:10.507664 ==
1134 11:03:10.511200 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 11:03:10.514536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 11:03:10.514622 ==
1137 11:03:10.517727 [Gating] SW mode calibration
1138 11:03:10.524483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 11:03:10.530926 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 11:03:10.534539 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1141 11:03:10.537866 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1142 11:03:10.544231 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1143 11:03:10.547725 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 11:03:10.551078 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 11:03:10.598058 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 11:03:10.598286 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 11:03:10.598799 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 11:03:10.599156 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:03:10.600278 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:03:10.600561 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:03:10.600657 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:03:10.600747 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:03:10.600908 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:03:10.601664 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:03:10.642348 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:03:10.642502 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1157 11:03:10.642853 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1158 11:03:10.643251 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1159 11:03:10.643753 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:03:10.644071 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:03:10.644166 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:03:10.644335 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:03:10.644890 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:03:10.645185 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:03:10.647712 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1166 11:03:10.647807 0 9 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
1167 11:03:10.654320 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1168 11:03:10.657919 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 11:03:10.661652 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 11:03:10.668025 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 11:03:10.671317 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 11:03:10.674814 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 11:03:10.681089 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1174 11:03:10.685283 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1175 11:03:10.687475 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:03:10.694662 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:03:10.697400 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:03:10.701194 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:03:10.707936 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:03:10.711357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:03:10.714486 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
1182 11:03:10.717875 0 11 8 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
1183 11:03:10.724167 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1184 11:03:10.727772 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 11:03:10.731351 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 11:03:10.737781 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 11:03:10.741381 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 11:03:10.744201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 11:03:10.751133 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1190 11:03:10.754289 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1191 11:03:10.757345 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 11:03:10.764404 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 11:03:10.767847 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 11:03:10.770680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 11:03:10.777431 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:03:10.780599 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:03:10.784136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:03:10.790748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:03:10.794391 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:03:10.797461 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:03:10.804055 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:03:10.807292 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:03:10.810374 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:03:10.816831 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:03:10.820317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1206 11:03:10.823779 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1207 11:03:10.827116 Total UI for P1: 0, mck2ui 16
1208 11:03:10.830524 best dqsien dly found for B0: ( 0, 14, 4)
1209 11:03:10.837036 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 11:03:10.837205 Total UI for P1: 0, mck2ui 16
1211 11:03:10.840337 best dqsien dly found for B1: ( 0, 14, 8)
1212 11:03:10.847245 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1213 11:03:10.850422 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1214 11:03:10.850514
1215 11:03:10.853707 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1216 11:03:10.857344 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1217 11:03:10.860640 [Gating] SW calibration Done
1218 11:03:10.860751 ==
1219 11:03:10.864057 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 11:03:10.867376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 11:03:10.867455 ==
1222 11:03:10.870354 RX Vref Scan: 0
1223 11:03:10.870443
1224 11:03:10.870511 RX Vref 0 -> 0, step: 1
1225 11:03:10.870618
1226 11:03:10.873640 RX Delay -130 -> 252, step: 16
1227 11:03:10.876896 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1228 11:03:10.883445 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1229 11:03:10.886696 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1230 11:03:10.890936 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1231 11:03:10.894106 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1232 11:03:10.896658 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1233 11:03:10.903561 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1234 11:03:10.906903 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1235 11:03:10.910432 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1236 11:03:10.913387 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1237 11:03:10.916828 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1238 11:03:10.923207 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1239 11:03:10.926415 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1240 11:03:10.930299 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1241 11:03:10.933116 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1242 11:03:10.936859 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1243 11:03:10.939835 ==
1244 11:03:10.943242 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 11:03:10.946462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 11:03:10.946546 ==
1247 11:03:10.946605 DQS Delay:
1248 11:03:10.950343 DQS0 = 0, DQS1 = 0
1249 11:03:10.950426 DQM Delay:
1250 11:03:10.953495 DQM0 = 86, DQM1 = 76
1251 11:03:10.953580 DQ Delay:
1252 11:03:10.956877 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1253 11:03:10.959766 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1254 11:03:10.963608 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1255 11:03:10.966741 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1256 11:03:10.966831
1257 11:03:10.966890
1258 11:03:10.966944 ==
1259 11:03:10.969817 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:03:10.972855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:03:10.972945 ==
1262 11:03:10.973041
1263 11:03:10.973132
1264 11:03:10.976304 TX Vref Scan disable
1265 11:03:10.979906 == TX Byte 0 ==
1266 11:03:10.983202 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1267 11:03:10.986719 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1268 11:03:10.990010 == TX Byte 1 ==
1269 11:03:10.993142 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1270 11:03:10.996516 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1271 11:03:10.996614 ==
1272 11:03:10.999567 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 11:03:11.005963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 11:03:11.006088 ==
1275 11:03:11.018254 TX Vref=22, minBit 0, minWin=27, winSum=441
1276 11:03:11.021511 TX Vref=24, minBit 0, minWin=27, winSum=445
1277 11:03:11.024704 TX Vref=26, minBit 0, minWin=27, winSum=446
1278 11:03:11.028673 TX Vref=28, minBit 1, minWin=27, winSum=452
1279 11:03:11.031508 TX Vref=30, minBit 3, minWin=27, winSum=451
1280 11:03:11.038378 TX Vref=32, minBit 3, minWin=27, winSum=450
1281 11:03:11.042093 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 28
1282 11:03:11.042200
1283 11:03:11.044892 Final TX Range 1 Vref 28
1284 11:03:11.044986
1285 11:03:11.045089 ==
1286 11:03:11.048144 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 11:03:11.051265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 11:03:11.051391 ==
1289 11:03:11.054490
1290 11:03:11.054590
1291 11:03:11.054675 TX Vref Scan disable
1292 11:03:11.058225 == TX Byte 0 ==
1293 11:03:11.061184 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1294 11:03:11.064634 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1295 11:03:11.068238 == TX Byte 1 ==
1296 11:03:11.071603 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1297 11:03:11.078512 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1298 11:03:11.078621
1299 11:03:11.078680 [DATLAT]
1300 11:03:11.078734 Freq=800, CH0 RK1
1301 11:03:11.078787
1302 11:03:11.081605 DATLAT Default: 0xa
1303 11:03:11.081682 0, 0xFFFF, sum = 0
1304 11:03:11.085054 1, 0xFFFF, sum = 0
1305 11:03:11.085175 2, 0xFFFF, sum = 0
1306 11:03:11.088344 3, 0xFFFF, sum = 0
1307 11:03:11.088429 4, 0xFFFF, sum = 0
1308 11:03:11.091611 5, 0xFFFF, sum = 0
1309 11:03:11.094911 6, 0xFFFF, sum = 0
1310 11:03:11.094994 7, 0xFFFF, sum = 0
1311 11:03:11.098195 8, 0xFFFF, sum = 0
1312 11:03:11.098306 9, 0x0, sum = 1
1313 11:03:11.098367 10, 0x0, sum = 2
1314 11:03:11.101612 11, 0x0, sum = 3
1315 11:03:11.101693 12, 0x0, sum = 4
1316 11:03:11.104692 best_step = 10
1317 11:03:11.104771
1318 11:03:11.104830 ==
1319 11:03:11.108143 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 11:03:11.111641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 11:03:11.111730 ==
1322 11:03:11.114827 RX Vref Scan: 0
1323 11:03:11.114905
1324 11:03:11.114964 RX Vref 0 -> 0, step: 1
1325 11:03:11.115018
1326 11:03:11.118013 RX Delay -95 -> 252, step: 8
1327 11:03:11.124827 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1328 11:03:11.128071 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1329 11:03:11.131194 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1330 11:03:11.134533 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1331 11:03:11.137954 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1332 11:03:11.144968 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1333 11:03:11.148231 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1334 11:03:11.151394 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1335 11:03:11.154886 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1336 11:03:11.158401 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1337 11:03:11.164495 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1338 11:03:11.168127 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1339 11:03:11.171093 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1340 11:03:11.174655 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1341 11:03:11.181214 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1342 11:03:11.184996 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1343 11:03:11.185106 ==
1344 11:03:11.188090 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 11:03:11.191341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 11:03:11.191423 ==
1347 11:03:11.191513 DQS Delay:
1348 11:03:11.194587 DQS0 = 0, DQS1 = 0
1349 11:03:11.194687 DQM Delay:
1350 11:03:11.198353 DQM0 = 86, DQM1 = 77
1351 11:03:11.198449 DQ Delay:
1352 11:03:11.201348 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1353 11:03:11.204848 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1354 11:03:11.208205 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1355 11:03:11.211674 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1356 11:03:11.211759
1357 11:03:11.211819
1358 11:03:11.221232 [DQSOSCAuto] RK1, (LSB)MR18= 0x312d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1359 11:03:11.221351 CH0 RK1: MR19=606, MR18=312D
1360 11:03:11.227756 CH0_RK1: MR19=0x606, MR18=0x312D, DQSOSC=397, MR23=63, INC=93, DEC=62
1361 11:03:11.231368 [RxdqsGatingPostProcess] freq 800
1362 11:03:11.238141 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 11:03:11.241363 Pre-setting of DQS Precalculation
1364 11:03:11.244902 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1365 11:03:11.245000 ==
1366 11:03:11.247895 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 11:03:11.251438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:03:11.251545 ==
1369 11:03:11.258318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 11:03:11.264491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 11:03:11.273258 [CA 0] Center 36 (6~67) winsize 62
1372 11:03:11.276987 [CA 1] Center 37 (6~68) winsize 63
1373 11:03:11.279962 [CA 2] Center 34 (4~65) winsize 62
1374 11:03:11.282985 [CA 3] Center 34 (4~65) winsize 62
1375 11:03:11.286404 [CA 4] Center 34 (4~65) winsize 62
1376 11:03:11.289983 [CA 5] Center 33 (3~64) winsize 62
1377 11:03:11.290101
1378 11:03:11.292991 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 11:03:11.293098
1380 11:03:11.296402 [CATrainingPosCal] consider 1 rank data
1381 11:03:11.299851 u2DelayCellTimex100 = 270/100 ps
1382 11:03:11.302708 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1383 11:03:11.309419 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1384 11:03:11.312700 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 11:03:11.316190 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 11:03:11.319422 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 11:03:11.323000 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 11:03:11.323088
1389 11:03:11.326130 CA PerBit enable=1, Macro0, CA PI delay=33
1390 11:03:11.326213
1391 11:03:11.329445 [CBTSetCACLKResult] CA Dly = 33
1392 11:03:11.329528 CS Dly: 4 (0~35)
1393 11:03:11.333100 ==
1394 11:03:11.336629 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 11:03:11.339293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 11:03:11.339395 ==
1397 11:03:11.342747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 11:03:11.349462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 11:03:11.359258 [CA 0] Center 36 (6~67) winsize 62
1400 11:03:11.362738 [CA 1] Center 37 (7~67) winsize 61
1401 11:03:11.365790 [CA 2] Center 34 (4~65) winsize 62
1402 11:03:11.369655 [CA 3] Center 33 (3~64) winsize 62
1403 11:03:11.372655 [CA 4] Center 34 (3~65) winsize 63
1404 11:03:11.375863 [CA 5] Center 34 (3~65) winsize 63
1405 11:03:11.375948
1406 11:03:11.379386 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1407 11:03:11.379465
1408 11:03:11.382803 [CATrainingPosCal] consider 2 rank data
1409 11:03:11.386299 u2DelayCellTimex100 = 270/100 ps
1410 11:03:11.389090 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 11:03:11.392658 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
1412 11:03:11.399288 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 11:03:11.402365 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1414 11:03:11.406022 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 11:03:11.409091 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 11:03:11.409230
1417 11:03:11.412618 CA PerBit enable=1, Macro0, CA PI delay=33
1418 11:03:11.412701
1419 11:03:11.415538 [CBTSetCACLKResult] CA Dly = 33
1420 11:03:11.415618 CS Dly: 5 (0~37)
1421 11:03:11.415676
1422 11:03:11.422725 ----->DramcWriteLeveling(PI) begin...
1423 11:03:11.422824 ==
1424 11:03:11.425977 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 11:03:11.428789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 11:03:11.428872 ==
1427 11:03:11.432571 Write leveling (Byte 0): 25 => 25
1428 11:03:11.435557 Write leveling (Byte 1): 30 => 30
1429 11:03:11.438882 DramcWriteLeveling(PI) end<-----
1430 11:03:11.438983
1431 11:03:11.439072 ==
1432 11:03:11.442667 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 11:03:11.445648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 11:03:11.445747 ==
1435 11:03:11.449064 [Gating] SW mode calibration
1436 11:03:11.455540 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 11:03:11.462570 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 11:03:11.465693 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1439 11:03:11.469255 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1440 11:03:11.472474 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 11:03:11.478951 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 11:03:11.482164 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 11:03:11.485893 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 11:03:11.492266 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 11:03:11.495636 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:03:11.498934 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 11:03:11.505593 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:03:11.509018 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:03:11.512039 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:03:11.518875 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:03:11.522340 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:03:11.525727 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:03:11.532527 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:03:11.535658 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:03:11.538886 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1456 11:03:11.545307 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:03:11.548998 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:03:11.551996 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:03:11.558936 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:03:11.562240 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:03:11.565541 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:03:11.572467 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:03:11.575597 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1464 11:03:11.579026 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1465 11:03:11.585643 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 11:03:11.588532 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 11:03:11.592333 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 11:03:11.595352 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 11:03:11.601878 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 11:03:11.605499 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 11:03:11.609058 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (1 1)
1472 11:03:11.615204 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1473 11:03:11.618596 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:03:11.622003 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:03:11.628264 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:03:11.631729 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:03:11.634741 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:03:11.642038 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:03:11.644972 0 11 4 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
1480 11:03:11.648072 0 11 8 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
1481 11:03:11.655508 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 11:03:11.658920 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 11:03:11.661979 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 11:03:11.668286 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 11:03:11.671388 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 11:03:11.674428 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 11:03:11.681066 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1488 11:03:11.684478 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 11:03:11.687939 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 11:03:11.694643 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 11:03:11.697651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 11:03:11.701348 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 11:03:11.707686 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:03:11.711101 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:03:11.714318 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:03:11.721416 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:03:11.724548 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:03:11.727886 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:03:11.734710 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:03:11.737937 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:03:11.741116 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:03:11.747429 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:03:11.751159 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1504 11:03:11.754129 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:03:11.757752 Total UI for P1: 0, mck2ui 16
1506 11:03:11.760525 best dqsien dly found for B0: ( 0, 14, 4)
1507 11:03:11.763949 Total UI for P1: 0, mck2ui 16
1508 11:03:11.767322 best dqsien dly found for B1: ( 0, 14, 4)
1509 11:03:11.771386 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1510 11:03:11.774055 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1511 11:03:11.774136
1512 11:03:11.777778 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1513 11:03:11.784288 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1514 11:03:11.784384 [Gating] SW calibration Done
1515 11:03:11.784444 ==
1516 11:03:11.787663 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 11:03:11.794378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1518 11:03:11.794475 ==
1519 11:03:11.794535 RX Vref Scan: 0
1520 11:03:11.794591
1521 11:03:11.797463 RX Vref 0 -> 0, step: 1
1522 11:03:11.797541
1523 11:03:11.800500 RX Delay -130 -> 252, step: 16
1524 11:03:11.803647 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1525 11:03:11.807173 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1526 11:03:11.810422 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1527 11:03:11.817120 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1528 11:03:11.820217 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1529 11:03:11.823683 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1530 11:03:11.826921 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1531 11:03:11.830572 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1532 11:03:11.836939 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1533 11:03:11.841069 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1534 11:03:11.843396 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1535 11:03:11.847143 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1536 11:03:11.850422 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1537 11:03:11.856921 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1538 11:03:11.860807 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1539 11:03:11.863465 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1540 11:03:11.863564 ==
1541 11:03:11.867069 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 11:03:11.870152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 11:03:11.873662 ==
1544 11:03:11.873758 DQS Delay:
1545 11:03:11.873845 DQS0 = 0, DQS1 = 0
1546 11:03:11.876542 DQM Delay:
1547 11:03:11.876632 DQM0 = 85, DQM1 = 79
1548 11:03:11.879972 DQ Delay:
1549 11:03:11.883484 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1550 11:03:11.883576 DQ4 =77, DQ5 =101, DQ6 =93, DQ7 =85
1551 11:03:11.887030 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1552 11:03:11.893529 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1553 11:03:11.893633
1554 11:03:11.893714
1555 11:03:11.893788 ==
1556 11:03:11.896899 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 11:03:11.900043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 11:03:11.900128 ==
1559 11:03:11.900206
1560 11:03:11.900278
1561 11:03:11.903260 TX Vref Scan disable
1562 11:03:11.903345 == TX Byte 0 ==
1563 11:03:11.910127 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1564 11:03:11.913926 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1565 11:03:11.914022 == TX Byte 1 ==
1566 11:03:11.920007 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1567 11:03:11.923118 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1568 11:03:11.923209 ==
1569 11:03:11.926629 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 11:03:11.929710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 11:03:11.929814 ==
1572 11:03:11.944104 TX Vref=22, minBit 0, minWin=27, winSum=442
1573 11:03:11.947347 TX Vref=24, minBit 0, minWin=27, winSum=444
1574 11:03:11.950699 TX Vref=26, minBit 2, minWin=27, winSum=447
1575 11:03:11.954199 TX Vref=28, minBit 5, minWin=27, winSum=456
1576 11:03:11.957798 TX Vref=30, minBit 0, minWin=28, winSum=457
1577 11:03:11.960687 TX Vref=32, minBit 0, minWin=28, winSum=452
1578 11:03:11.967377 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1579 11:03:11.967483
1580 11:03:11.971157 Final TX Range 1 Vref 30
1581 11:03:11.971262
1582 11:03:11.971350 ==
1583 11:03:11.974059 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 11:03:11.977333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 11:03:11.977417 ==
1586 11:03:11.977477
1587 11:03:11.980895
1588 11:03:11.980997 TX Vref Scan disable
1589 11:03:11.983898 == TX Byte 0 ==
1590 11:03:11.987496 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1591 11:03:11.990629 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1592 11:03:11.994070 == TX Byte 1 ==
1593 11:03:11.997676 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1594 11:03:12.001126 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1595 11:03:12.004433
1596 11:03:12.004541 [DATLAT]
1597 11:03:12.004603 Freq=800, CH1 RK0
1598 11:03:12.004660
1599 11:03:12.007530 DATLAT Default: 0xa
1600 11:03:12.007609 0, 0xFFFF, sum = 0
1601 11:03:12.010824 1, 0xFFFF, sum = 0
1602 11:03:12.010906 2, 0xFFFF, sum = 0
1603 11:03:12.014322 3, 0xFFFF, sum = 0
1604 11:03:12.014436 4, 0xFFFF, sum = 0
1605 11:03:12.017940 5, 0xFFFF, sum = 0
1606 11:03:12.020771 6, 0xFFFF, sum = 0
1607 11:03:12.020884 7, 0xFFFF, sum = 0
1608 11:03:12.024216 8, 0xFFFF, sum = 0
1609 11:03:12.024303 9, 0x0, sum = 1
1610 11:03:12.024365 10, 0x0, sum = 2
1611 11:03:12.027347 11, 0x0, sum = 3
1612 11:03:12.027457 12, 0x0, sum = 4
1613 11:03:12.030697 best_step = 10
1614 11:03:12.030797
1615 11:03:12.030884 ==
1616 11:03:12.034429 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 11:03:12.037774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 11:03:12.037879 ==
1619 11:03:12.040595 RX Vref Scan: 1
1620 11:03:12.040692
1621 11:03:12.040781 Set Vref Range= 32 -> 127
1622 11:03:12.043839
1623 11:03:12.043920 RX Vref 32 -> 127, step: 1
1624 11:03:12.044001
1625 11:03:12.047201 RX Delay -95 -> 252, step: 8
1626 11:03:12.047290
1627 11:03:12.050763 Set Vref, RX VrefLevel [Byte0]: 32
1628 11:03:12.054123 [Byte1]: 32
1629 11:03:12.054210
1630 11:03:12.057269 Set Vref, RX VrefLevel [Byte0]: 33
1631 11:03:12.060612 [Byte1]: 33
1632 11:03:12.064632
1633 11:03:12.064721 Set Vref, RX VrefLevel [Byte0]: 34
1634 11:03:12.067647 [Byte1]: 34
1635 11:03:12.071980
1636 11:03:12.072072 Set Vref, RX VrefLevel [Byte0]: 35
1637 11:03:12.075586 [Byte1]: 35
1638 11:03:12.080305
1639 11:03:12.080434 Set Vref, RX VrefLevel [Byte0]: 36
1640 11:03:12.083247 [Byte1]: 36
1641 11:03:12.087507
1642 11:03:12.087592 Set Vref, RX VrefLevel [Byte0]: 37
1643 11:03:12.091023 [Byte1]: 37
1644 11:03:12.094831
1645 11:03:12.094914 Set Vref, RX VrefLevel [Byte0]: 38
1646 11:03:12.098615 [Byte1]: 38
1647 11:03:12.102735
1648 11:03:12.102823 Set Vref, RX VrefLevel [Byte0]: 39
1649 11:03:12.105772 [Byte1]: 39
1650 11:03:12.109958
1651 11:03:12.110042 Set Vref, RX VrefLevel [Byte0]: 40
1652 11:03:12.113607 [Byte1]: 40
1653 11:03:12.117628
1654 11:03:12.117718 Set Vref, RX VrefLevel [Byte0]: 41
1655 11:03:12.121131 [Byte1]: 41
1656 11:03:12.125235
1657 11:03:12.125347 Set Vref, RX VrefLevel [Byte0]: 42
1658 11:03:12.128726 [Byte1]: 42
1659 11:03:12.132952
1660 11:03:12.133064 Set Vref, RX VrefLevel [Byte0]: 43
1661 11:03:12.136419 [Byte1]: 43
1662 11:03:12.140337
1663 11:03:12.140441 Set Vref, RX VrefLevel [Byte0]: 44
1664 11:03:12.143677 [Byte1]: 44
1665 11:03:12.148064
1666 11:03:12.148159 Set Vref, RX VrefLevel [Byte0]: 45
1667 11:03:12.151270 [Byte1]: 45
1668 11:03:12.155977
1669 11:03:12.156102 Set Vref, RX VrefLevel [Byte0]: 46
1670 11:03:12.158969 [Byte1]: 46
1671 11:03:12.163582
1672 11:03:12.163670 Set Vref, RX VrefLevel [Byte0]: 47
1673 11:03:12.166741 [Byte1]: 47
1674 11:03:12.170875
1675 11:03:12.170962 Set Vref, RX VrefLevel [Byte0]: 48
1676 11:03:12.173875 [Byte1]: 48
1677 11:03:12.178548
1678 11:03:12.178672 Set Vref, RX VrefLevel [Byte0]: 49
1679 11:03:12.181935 [Byte1]: 49
1680 11:03:12.186273
1681 11:03:12.186384 Set Vref, RX VrefLevel [Byte0]: 50
1682 11:03:12.189329 [Byte1]: 50
1683 11:03:12.193513
1684 11:03:12.193589 Set Vref, RX VrefLevel [Byte0]: 51
1685 11:03:12.196916 [Byte1]: 51
1686 11:03:12.201500
1687 11:03:12.201579 Set Vref, RX VrefLevel [Byte0]: 52
1688 11:03:12.204457 [Byte1]: 52
1689 11:03:12.208826
1690 11:03:12.208904 Set Vref, RX VrefLevel [Byte0]: 53
1691 11:03:12.212000 [Byte1]: 53
1692 11:03:12.216505
1693 11:03:12.216584 Set Vref, RX VrefLevel [Byte0]: 54
1694 11:03:12.220028 [Byte1]: 54
1695 11:03:12.224141
1696 11:03:12.224218 Set Vref, RX VrefLevel [Byte0]: 55
1697 11:03:12.227391 [Byte1]: 55
1698 11:03:12.231915
1699 11:03:12.231991 Set Vref, RX VrefLevel [Byte0]: 56
1700 11:03:12.235219 [Byte1]: 56
1701 11:03:12.238981
1702 11:03:12.239058 Set Vref, RX VrefLevel [Byte0]: 57
1703 11:03:12.242612 [Byte1]: 57
1704 11:03:12.246564
1705 11:03:12.246642 Set Vref, RX VrefLevel [Byte0]: 58
1706 11:03:12.250531 [Byte1]: 58
1707 11:03:12.254599
1708 11:03:12.254676 Set Vref, RX VrefLevel [Byte0]: 59
1709 11:03:12.257541 [Byte1]: 59
1710 11:03:12.262293
1711 11:03:12.262370 Set Vref, RX VrefLevel [Byte0]: 60
1712 11:03:12.265371 [Byte1]: 60
1713 11:03:12.269355
1714 11:03:12.269432 Set Vref, RX VrefLevel [Byte0]: 61
1715 11:03:12.272674 [Byte1]: 61
1716 11:03:12.277085
1717 11:03:12.277184 Set Vref, RX VrefLevel [Byte0]: 62
1718 11:03:12.280214 [Byte1]: 62
1719 11:03:12.284616
1720 11:03:12.284692 Set Vref, RX VrefLevel [Byte0]: 63
1721 11:03:12.288251 [Byte1]: 63
1722 11:03:12.292342
1723 11:03:12.292418 Set Vref, RX VrefLevel [Byte0]: 64
1724 11:03:12.296291 [Byte1]: 64
1725 11:03:12.299915
1726 11:03:12.299992 Set Vref, RX VrefLevel [Byte0]: 65
1727 11:03:12.303650 [Byte1]: 65
1728 11:03:12.307321
1729 11:03:12.307400 Set Vref, RX VrefLevel [Byte0]: 66
1730 11:03:12.310658 [Byte1]: 66
1731 11:03:12.315888
1732 11:03:12.315970 Set Vref, RX VrefLevel [Byte0]: 67
1733 11:03:12.318494 [Byte1]: 67
1734 11:03:12.322775
1735 11:03:12.322853 Set Vref, RX VrefLevel [Byte0]: 68
1736 11:03:12.326211 [Byte1]: 68
1737 11:03:12.330451
1738 11:03:12.330530 Set Vref, RX VrefLevel [Byte0]: 69
1739 11:03:12.333461 [Byte1]: 69
1740 11:03:12.338227
1741 11:03:12.338304 Set Vref, RX VrefLevel [Byte0]: 70
1742 11:03:12.341453 [Byte1]: 70
1743 11:03:12.345662
1744 11:03:12.345739 Set Vref, RX VrefLevel [Byte0]: 71
1745 11:03:12.349319 [Byte1]: 71
1746 11:03:12.354064
1747 11:03:12.354141 Set Vref, RX VrefLevel [Byte0]: 72
1748 11:03:12.356145 [Byte1]: 72
1749 11:03:12.360593
1750 11:03:12.360669 Set Vref, RX VrefLevel [Byte0]: 73
1751 11:03:12.363929 [Byte1]: 73
1752 11:03:12.368301
1753 11:03:12.368378 Set Vref, RX VrefLevel [Byte0]: 74
1754 11:03:12.371551 [Byte1]: 74
1755 11:03:12.375894
1756 11:03:12.375971 Set Vref, RX VrefLevel [Byte0]: 75
1757 11:03:12.379307 [Byte1]: 75
1758 11:03:12.383555
1759 11:03:12.383632 Final RX Vref Byte 0 = 60 to rank0
1760 11:03:12.386903 Final RX Vref Byte 1 = 54 to rank0
1761 11:03:12.390000 Final RX Vref Byte 0 = 60 to rank1
1762 11:03:12.393459 Final RX Vref Byte 1 = 54 to rank1==
1763 11:03:12.396643 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 11:03:12.403479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 11:03:12.403557 ==
1766 11:03:12.403618 DQS Delay:
1767 11:03:12.403674 DQS0 = 0, DQS1 = 0
1768 11:03:12.406753 DQM Delay:
1769 11:03:12.406829 DQM0 = 86, DQM1 = 80
1770 11:03:12.410149 DQ Delay:
1771 11:03:12.413195 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
1772 11:03:12.417035 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1773 11:03:12.420033 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1774 11:03:12.423370 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1775 11:03:12.423447
1776 11:03:12.423507
1777 11:03:12.429886 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f33, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
1778 11:03:12.433772 CH1 RK0: MR19=606, MR18=1F33
1779 11:03:12.439957 CH1_RK0: MR19=0x606, MR18=0x1F33, DQSOSC=396, MR23=63, INC=94, DEC=62
1780 11:03:12.440040
1781 11:03:12.443405 ----->DramcWriteLeveling(PI) begin...
1782 11:03:12.443484 ==
1783 11:03:12.446688 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 11:03:12.449873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 11:03:12.449954 ==
1786 11:03:12.453739 Write leveling (Byte 0): 25 => 25
1787 11:03:12.456761 Write leveling (Byte 1): 30 => 30
1788 11:03:12.459631 DramcWriteLeveling(PI) end<-----
1789 11:03:12.459708
1790 11:03:12.459771 ==
1791 11:03:12.463097 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 11:03:12.466342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 11:03:12.466420 ==
1794 11:03:12.469696 [Gating] SW mode calibration
1795 11:03:12.476396 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 11:03:12.483284 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 11:03:12.486412 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1798 11:03:12.489593 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1799 11:03:12.496603 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1800 11:03:12.500152 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 11:03:12.502992 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 11:03:12.509683 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 11:03:12.512988 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 11:03:12.516557 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 11:03:12.523136 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:03:12.526781 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:03:12.530144 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:03:12.536496 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:03:12.539670 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:03:12.543031 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:03:12.549559 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:03:12.553003 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:03:12.556432 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1814 11:03:12.563122 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1815 11:03:12.566187 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1816 11:03:12.569726 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:03:12.576278 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:03:12.579985 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:03:12.582872 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:03:12.586500 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:03:12.592797 0 9 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1822 11:03:12.596252 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1823 11:03:12.600204 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1824 11:03:12.606870 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 11:03:12.609748 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 11:03:12.613111 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 11:03:12.619723 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 11:03:12.623032 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 11:03:12.626496 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1830 11:03:12.632821 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
1831 11:03:12.636255 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1832 11:03:12.639275 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:03:12.646919 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:03:12.649509 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:03:12.652635 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:03:12.659336 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:03:12.662907 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:03:12.666376 0 11 4 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
1839 11:03:12.672602 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 11:03:12.676160 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 11:03:12.679336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 11:03:12.685887 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 11:03:12.689430 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 11:03:12.693104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 11:03:12.699765 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1846 11:03:12.702593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1847 11:03:12.706382 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 11:03:12.709279 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 11:03:12.716247 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 11:03:12.719545 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 11:03:12.722985 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 11:03:12.729175 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 11:03:12.732616 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:03:12.735955 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:03:12.742415 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:03:12.745674 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:03:12.749078 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:03:12.755499 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:03:12.758842 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:03:12.762534 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:03:12.769129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1862 11:03:12.772187 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1863 11:03:12.775669 Total UI for P1: 0, mck2ui 16
1864 11:03:12.779434 best dqsien dly found for B0: ( 0, 14, 0)
1865 11:03:12.782357 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 11:03:12.785602 Total UI for P1: 0, mck2ui 16
1867 11:03:12.789045 best dqsien dly found for B1: ( 0, 14, 4)
1868 11:03:12.792529 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1869 11:03:12.795803 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1870 11:03:12.795882
1871 11:03:12.802376 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1872 11:03:12.805695 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 11:03:12.805777 [Gating] SW calibration Done
1874 11:03:12.809000 ==
1875 11:03:12.811869 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 11:03:12.815442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 11:03:12.815521 ==
1878 11:03:12.815582 RX Vref Scan: 0
1879 11:03:12.815638
1880 11:03:12.818927 RX Vref 0 -> 0, step: 1
1881 11:03:12.819004
1882 11:03:12.822385 RX Delay -130 -> 252, step: 16
1883 11:03:12.825145 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1884 11:03:12.828611 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1885 11:03:12.835265 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1886 11:03:12.838846 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1887 11:03:12.841879 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1888 11:03:12.845017 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1889 11:03:12.848528 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1890 11:03:12.855318 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1891 11:03:12.858645 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1892 11:03:12.862207 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1893 11:03:12.865390 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1894 11:03:12.868993 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1895 11:03:12.875178 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1896 11:03:12.878495 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1897 11:03:12.881888 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1898 11:03:12.885038 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1899 11:03:12.885119 ==
1900 11:03:12.888535 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 11:03:12.895129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 11:03:12.895216 ==
1903 11:03:12.895295 DQS Delay:
1904 11:03:12.895368 DQS0 = 0, DQS1 = 0
1905 11:03:12.898976 DQM Delay:
1906 11:03:12.899056 DQM0 = 82, DQM1 = 82
1907 11:03:12.901825 DQ Delay:
1908 11:03:12.905415 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1909 11:03:12.905496 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1910 11:03:12.908348 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1911 11:03:12.911708 DQ12 =93, DQ13 =85, DQ14 =93, DQ15 =93
1912 11:03:12.914954
1913 11:03:12.915060
1914 11:03:12.915152 ==
1915 11:03:12.918312 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 11:03:12.921462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 11:03:12.921562 ==
1918 11:03:12.921647
1919 11:03:12.921731
1920 11:03:12.925256 TX Vref Scan disable
1921 11:03:12.925352 == TX Byte 0 ==
1922 11:03:12.931916 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1923 11:03:12.935074 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1924 11:03:12.935155 == TX Byte 1 ==
1925 11:03:12.941718 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1926 11:03:12.945309 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1927 11:03:12.945391 ==
1928 11:03:12.948828 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 11:03:12.952110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 11:03:12.952211 ==
1931 11:03:12.965946 TX Vref=22, minBit 7, minWin=27, winSum=451
1932 11:03:12.969377 TX Vref=24, minBit 1, minWin=27, winSum=451
1933 11:03:12.973009 TX Vref=26, minBit 0, minWin=28, winSum=453
1934 11:03:12.975805 TX Vref=28, minBit 1, minWin=27, winSum=453
1935 11:03:12.978970 TX Vref=30, minBit 0, minWin=28, winSum=456
1936 11:03:12.982757 TX Vref=32, minBit 5, minWin=27, winSum=455
1937 11:03:12.989064 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1938 11:03:12.989159
1939 11:03:12.992577 Final TX Range 1 Vref 30
1940 11:03:12.992658
1941 11:03:12.992717 ==
1942 11:03:12.995833 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 11:03:12.999126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 11:03:12.999204 ==
1945 11:03:12.999264
1946 11:03:13.002147
1947 11:03:13.002224 TX Vref Scan disable
1948 11:03:13.005789 == TX Byte 0 ==
1949 11:03:13.009446 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1950 11:03:13.012345 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1951 11:03:13.015795 == TX Byte 1 ==
1952 11:03:13.019354 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1953 11:03:13.025769 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1954 11:03:13.025858
1955 11:03:13.025919 [DATLAT]
1956 11:03:13.025974 Freq=800, CH1 RK1
1957 11:03:13.026030
1958 11:03:13.029003 DATLAT Default: 0xa
1959 11:03:13.029081 0, 0xFFFF, sum = 0
1960 11:03:13.032773 1, 0xFFFF, sum = 0
1961 11:03:13.032855 2, 0xFFFF, sum = 0
1962 11:03:13.036080 3, 0xFFFF, sum = 0
1963 11:03:13.036161 4, 0xFFFF, sum = 0
1964 11:03:13.039243 5, 0xFFFF, sum = 0
1965 11:03:13.042412 6, 0xFFFF, sum = 0
1966 11:03:13.042496 7, 0xFFFF, sum = 0
1967 11:03:13.045872 8, 0xFFFF, sum = 0
1968 11:03:13.045988 9, 0x0, sum = 1
1969 11:03:13.046107 10, 0x0, sum = 2
1970 11:03:13.048895 11, 0x0, sum = 3
1971 11:03:13.048974 12, 0x0, sum = 4
1972 11:03:13.052670 best_step = 10
1973 11:03:13.052751
1974 11:03:13.052811 ==
1975 11:03:13.056021 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 11:03:13.059114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 11:03:13.059194 ==
1978 11:03:13.062453 RX Vref Scan: 0
1979 11:03:13.062529
1980 11:03:13.062588 RX Vref 0 -> 0, step: 1
1981 11:03:13.062644
1982 11:03:13.065716 RX Delay -95 -> 252, step: 8
1983 11:03:13.072854 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1984 11:03:13.076204 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1985 11:03:13.079069 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1986 11:03:13.082645 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1987 11:03:13.085885 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1988 11:03:13.092392 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1989 11:03:13.095483 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1990 11:03:13.099801 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1991 11:03:13.102146 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1992 11:03:13.105662 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1993 11:03:13.112050 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1994 11:03:13.115387 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1995 11:03:13.118649 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1996 11:03:13.122095 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1997 11:03:13.128948 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1998 11:03:13.132324 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1999 11:03:13.132420 ==
2000 11:03:13.135580 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 11:03:13.138697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 11:03:13.138783 ==
2003 11:03:13.142242 DQS Delay:
2004 11:03:13.142322 DQS0 = 0, DQS1 = 0
2005 11:03:13.142382 DQM Delay:
2006 11:03:13.145225 DQM0 = 86, DQM1 = 81
2007 11:03:13.145341 DQ Delay:
2008 11:03:13.148573 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2009 11:03:13.151863 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2010 11:03:13.155756 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2011 11:03:13.158404 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2012 11:03:13.158489
2013 11:03:13.158549
2014 11:03:13.168479 [DQSOSCAuto] RK1, (LSB)MR18= 0x2642, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2015 11:03:13.168594 CH1 RK1: MR19=606, MR18=2642
2016 11:03:13.175499 CH1_RK1: MR19=0x606, MR18=0x2642, DQSOSC=393, MR23=63, INC=95, DEC=63
2017 11:03:13.178493 [RxdqsGatingPostProcess] freq 800
2018 11:03:13.185251 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2019 11:03:13.188468 Pre-setting of DQS Precalculation
2020 11:03:13.192093 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2021 11:03:13.198604 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2022 11:03:13.208689 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2023 11:03:13.208775
2024 11:03:13.208837
2025 11:03:13.208893 [Calibration Summary] 1600 Mbps
2026 11:03:13.211891 CH 0, Rank 0
2027 11:03:13.215545 SW Impedance : PASS
2028 11:03:13.215642 DUTY Scan : NO K
2029 11:03:13.218461 ZQ Calibration : PASS
2030 11:03:13.218539 Jitter Meter : NO K
2031 11:03:13.222106 CBT Training : PASS
2032 11:03:13.225201 Write leveling : PASS
2033 11:03:13.225279 RX DQS gating : PASS
2034 11:03:13.228714 RX DQ/DQS(RDDQC) : PASS
2035 11:03:13.231709 TX DQ/DQS : PASS
2036 11:03:13.231787 RX DATLAT : PASS
2037 11:03:13.235224 RX DQ/DQS(Engine): PASS
2038 11:03:13.238468 TX OE : NO K
2039 11:03:13.238548 All Pass.
2040 11:03:13.238607
2041 11:03:13.238663 CH 0, Rank 1
2042 11:03:13.241675 SW Impedance : PASS
2043 11:03:13.244866 DUTY Scan : NO K
2044 11:03:13.244944 ZQ Calibration : PASS
2045 11:03:13.248199 Jitter Meter : NO K
2046 11:03:13.251496 CBT Training : PASS
2047 11:03:13.251575 Write leveling : PASS
2048 11:03:13.254874 RX DQS gating : PASS
2049 11:03:13.258145 RX DQ/DQS(RDDQC) : PASS
2050 11:03:13.258224 TX DQ/DQS : PASS
2051 11:03:13.261393 RX DATLAT : PASS
2052 11:03:13.264854 RX DQ/DQS(Engine): PASS
2053 11:03:13.264932 TX OE : NO K
2054 11:03:13.264992 All Pass.
2055 11:03:13.268303
2056 11:03:13.268382 CH 1, Rank 0
2057 11:03:13.271448 SW Impedance : PASS
2058 11:03:13.271543 DUTY Scan : NO K
2059 11:03:13.274640 ZQ Calibration : PASS
2060 11:03:13.274720 Jitter Meter : NO K
2061 11:03:13.277982 CBT Training : PASS
2062 11:03:13.282006 Write leveling : PASS
2063 11:03:13.282084 RX DQS gating : PASS
2064 11:03:13.284713 RX DQ/DQS(RDDQC) : PASS
2065 11:03:13.288084 TX DQ/DQS : PASS
2066 11:03:13.288162 RX DATLAT : PASS
2067 11:03:13.291366 RX DQ/DQS(Engine): PASS
2068 11:03:13.294671 TX OE : NO K
2069 11:03:13.294750 All Pass.
2070 11:03:13.294810
2071 11:03:13.294865 CH 1, Rank 1
2072 11:03:13.298232 SW Impedance : PASS
2073 11:03:13.301181 DUTY Scan : NO K
2074 11:03:13.301259 ZQ Calibration : PASS
2075 11:03:13.304752 Jitter Meter : NO K
2076 11:03:13.307753 CBT Training : PASS
2077 11:03:13.307830 Write leveling : PASS
2078 11:03:13.311333 RX DQS gating : PASS
2079 11:03:13.314423 RX DQ/DQS(RDDQC) : PASS
2080 11:03:13.314501 TX DQ/DQS : PASS
2081 11:03:13.317893 RX DATLAT : PASS
2082 11:03:13.321098 RX DQ/DQS(Engine): PASS
2083 11:03:13.321218 TX OE : NO K
2084 11:03:13.321280 All Pass.
2085 11:03:13.324738
2086 11:03:13.324820 DramC Write-DBI off
2087 11:03:13.327747 PER_BANK_REFRESH: Hybrid Mode
2088 11:03:13.327860 TX_TRACKING: ON
2089 11:03:13.331354 [GetDramInforAfterCalByMRR] Vendor 6.
2090 11:03:13.334424 [GetDramInforAfterCalByMRR] Revision 606.
2091 11:03:13.341504 [GetDramInforAfterCalByMRR] Revision 2 0.
2092 11:03:13.341588 MR0 0x3b3b
2093 11:03:13.341651 MR8 0x5151
2094 11:03:13.344470 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 11:03:13.344548
2096 11:03:13.347850 MR0 0x3b3b
2097 11:03:13.347928 MR8 0x5151
2098 11:03:13.351101 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 11:03:13.351179
2100 11:03:13.361049 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2101 11:03:13.364287 [FAST_K] Save calibration result to emmc
2102 11:03:13.367815 [FAST_K] Save calibration result to emmc
2103 11:03:13.371319 dram_init: config_dvfs: 1
2104 11:03:13.374529 dramc_set_vcore_voltage set vcore to 662500
2105 11:03:13.377923 Read voltage for 1200, 2
2106 11:03:13.378042 Vio18 = 0
2107 11:03:13.378101 Vcore = 662500
2108 11:03:13.381531 Vdram = 0
2109 11:03:13.381607 Vddq = 0
2110 11:03:13.381666 Vmddr = 0
2111 11:03:13.387990 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2112 11:03:13.391020 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2113 11:03:13.394310 MEM_TYPE=3, freq_sel=15
2114 11:03:13.397920 sv_algorithm_assistance_LP4_1600
2115 11:03:13.401301 ============ PULL DRAM RESETB DOWN ============
2116 11:03:13.404362 ========== PULL DRAM RESETB DOWN end =========
2117 11:03:13.410720 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2118 11:03:13.414440 ===================================
2119 11:03:13.414518 LPDDR4 DRAM CONFIGURATION
2120 11:03:13.418122 ===================================
2121 11:03:13.421295 EX_ROW_EN[0] = 0x0
2122 11:03:13.424503 EX_ROW_EN[1] = 0x0
2123 11:03:13.424581 LP4Y_EN = 0x0
2124 11:03:13.427572 WORK_FSP = 0x0
2125 11:03:13.427648 WL = 0x4
2126 11:03:13.431205 RL = 0x4
2127 11:03:13.431283 BL = 0x2
2128 11:03:13.434357 RPST = 0x0
2129 11:03:13.434435 RD_PRE = 0x0
2130 11:03:13.437413 WR_PRE = 0x1
2131 11:03:13.437491 WR_PST = 0x0
2132 11:03:13.440893 DBI_WR = 0x0
2133 11:03:13.440969 DBI_RD = 0x0
2134 11:03:13.444408 OTF = 0x1
2135 11:03:13.447591 ===================================
2136 11:03:13.450806 ===================================
2137 11:03:13.450886 ANA top config
2138 11:03:13.454341 ===================================
2139 11:03:13.457377 DLL_ASYNC_EN = 0
2140 11:03:13.461026 ALL_SLAVE_EN = 0
2141 11:03:13.461104 NEW_RANK_MODE = 1
2142 11:03:13.463942 DLL_IDLE_MODE = 1
2143 11:03:13.467351 LP45_APHY_COMB_EN = 1
2144 11:03:13.471130 TX_ODT_DIS = 1
2145 11:03:13.473877 NEW_8X_MODE = 1
2146 11:03:13.477923 ===================================
2147 11:03:13.480722 ===================================
2148 11:03:13.480825 data_rate = 2400
2149 11:03:13.484093 CKR = 1
2150 11:03:13.487067 DQ_P2S_RATIO = 8
2151 11:03:13.490494 ===================================
2152 11:03:13.493832 CA_P2S_RATIO = 8
2153 11:03:13.497277 DQ_CA_OPEN = 0
2154 11:03:13.501005 DQ_SEMI_OPEN = 0
2155 11:03:13.501083 CA_SEMI_OPEN = 0
2156 11:03:13.504095 CA_FULL_RATE = 0
2157 11:03:13.507427 DQ_CKDIV4_EN = 0
2158 11:03:13.510428 CA_CKDIV4_EN = 0
2159 11:03:13.513544 CA_PREDIV_EN = 0
2160 11:03:13.517025 PH8_DLY = 17
2161 11:03:13.517127 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2162 11:03:13.520623 DQ_AAMCK_DIV = 4
2163 11:03:13.523738 CA_AAMCK_DIV = 4
2164 11:03:13.527208 CA_ADMCK_DIV = 4
2165 11:03:13.530130 DQ_TRACK_CA_EN = 0
2166 11:03:13.533513 CA_PICK = 1200
2167 11:03:13.537867 CA_MCKIO = 1200
2168 11:03:13.537945 MCKIO_SEMI = 0
2169 11:03:13.540469 PLL_FREQ = 2366
2170 11:03:13.543780 DQ_UI_PI_RATIO = 32
2171 11:03:13.546747 CA_UI_PI_RATIO = 0
2172 11:03:13.550145 ===================================
2173 11:03:13.553557 ===================================
2174 11:03:13.557282 memory_type:LPDDR4
2175 11:03:13.557359 GP_NUM : 10
2176 11:03:13.560043 SRAM_EN : 1
2177 11:03:13.563835 MD32_EN : 0
2178 11:03:13.567258 ===================================
2179 11:03:13.567336 [ANA_INIT] >>>>>>>>>>>>>>
2180 11:03:13.570193 <<<<<< [CONFIGURE PHASE]: ANA_TX
2181 11:03:13.573228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2182 11:03:13.576497 ===================================
2183 11:03:13.579869 data_rate = 2400,PCW = 0X5b00
2184 11:03:13.583459 ===================================
2185 11:03:13.586858 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2186 11:03:13.593270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 11:03:13.597292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 11:03:13.603556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2189 11:03:13.606656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2190 11:03:13.609957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2191 11:03:13.610035 [ANA_INIT] flow start
2192 11:03:13.613110 [ANA_INIT] PLL >>>>>>>>
2193 11:03:13.616655 [ANA_INIT] PLL <<<<<<<<
2194 11:03:13.616734 [ANA_INIT] MIDPI >>>>>>>>
2195 11:03:13.620515 [ANA_INIT] MIDPI <<<<<<<<
2196 11:03:13.623464 [ANA_INIT] DLL >>>>>>>>
2197 11:03:13.626738 [ANA_INIT] DLL <<<<<<<<
2198 11:03:13.626816 [ANA_INIT] flow end
2199 11:03:13.630326 ============ LP4 DIFF to SE enter ============
2200 11:03:13.636413 ============ LP4 DIFF to SE exit ============
2201 11:03:13.636495 [ANA_INIT] <<<<<<<<<<<<<
2202 11:03:13.639716 [Flow] Enable top DCM control >>>>>
2203 11:03:13.642823 [Flow] Enable top DCM control <<<<<
2204 11:03:13.646580 Enable DLL master slave shuffle
2205 11:03:13.653105 ==============================================================
2206 11:03:13.653234 Gating Mode config
2207 11:03:13.659541 ==============================================================
2208 11:03:13.663576 Config description:
2209 11:03:13.673088 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2210 11:03:13.680040 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2211 11:03:13.682915 SELPH_MODE 0: By rank 1: By Phase
2212 11:03:13.689464 ==============================================================
2213 11:03:13.692714 GAT_TRACK_EN = 1
2214 11:03:13.692795 RX_GATING_MODE = 2
2215 11:03:13.696402 RX_GATING_TRACK_MODE = 2
2216 11:03:13.699594 SELPH_MODE = 1
2217 11:03:13.703351 PICG_EARLY_EN = 1
2218 11:03:13.706156 VALID_LAT_VALUE = 1
2219 11:03:13.712773 ==============================================================
2220 11:03:13.716240 Enter into Gating configuration >>>>
2221 11:03:13.719938 Exit from Gating configuration <<<<
2222 11:03:13.723281 Enter into DVFS_PRE_config >>>>>
2223 11:03:13.732796 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2224 11:03:13.736364 Exit from DVFS_PRE_config <<<<<
2225 11:03:13.739501 Enter into PICG configuration >>>>
2226 11:03:13.742411 Exit from PICG configuration <<<<
2227 11:03:13.746030 [RX_INPUT] configuration >>>>>
2228 11:03:13.749108 [RX_INPUT] configuration <<<<<
2229 11:03:13.752559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2230 11:03:13.759098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2231 11:03:13.765960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 11:03:13.772555 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 11:03:13.775935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 11:03:13.782234 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 11:03:13.785935 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2236 11:03:13.792359 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2237 11:03:13.795592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2238 11:03:13.799245 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2239 11:03:13.802393 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2240 11:03:13.809146 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2241 11:03:13.812623 ===================================
2242 11:03:13.812701 LPDDR4 DRAM CONFIGURATION
2243 11:03:13.815523 ===================================
2244 11:03:13.818994 EX_ROW_EN[0] = 0x0
2245 11:03:13.822806 EX_ROW_EN[1] = 0x0
2246 11:03:13.822885 LP4Y_EN = 0x0
2247 11:03:13.825851 WORK_FSP = 0x0
2248 11:03:13.825951 WL = 0x4
2249 11:03:13.829080 RL = 0x4
2250 11:03:13.829196 BL = 0x2
2251 11:03:13.832376 RPST = 0x0
2252 11:03:13.832477 RD_PRE = 0x0
2253 11:03:13.836082 WR_PRE = 0x1
2254 11:03:13.836183 WR_PST = 0x0
2255 11:03:13.838998 DBI_WR = 0x0
2256 11:03:13.839074 DBI_RD = 0x0
2257 11:03:13.842176 OTF = 0x1
2258 11:03:13.845919 ===================================
2259 11:03:13.849263 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2260 11:03:13.852176 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2261 11:03:13.859357 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 11:03:13.862431 ===================================
2263 11:03:13.862535 LPDDR4 DRAM CONFIGURATION
2264 11:03:13.865688 ===================================
2265 11:03:13.869525 EX_ROW_EN[0] = 0x10
2266 11:03:13.869626 EX_ROW_EN[1] = 0x0
2267 11:03:13.872204 LP4Y_EN = 0x0
2268 11:03:13.872303 WORK_FSP = 0x0
2269 11:03:13.875626 WL = 0x4
2270 11:03:13.879402 RL = 0x4
2271 11:03:13.879501 BL = 0x2
2272 11:03:13.882409 RPST = 0x0
2273 11:03:13.882506 RD_PRE = 0x0
2274 11:03:13.885520 WR_PRE = 0x1
2275 11:03:13.885616 WR_PST = 0x0
2276 11:03:13.888770 DBI_WR = 0x0
2277 11:03:13.888868 DBI_RD = 0x0
2278 11:03:13.892379 OTF = 0x1
2279 11:03:13.895677 ===================================
2280 11:03:13.902417 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2281 11:03:13.902526 ==
2282 11:03:13.905555 Dram Type= 6, Freq= 0, CH_0, rank 0
2283 11:03:13.908953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2284 11:03:13.909054 ==
2285 11:03:13.912661 [Duty_Offset_Calibration]
2286 11:03:13.912761 B0:2 B1:0 CA:4
2287 11:03:13.912847
2288 11:03:13.915775 [DutyScan_Calibration_Flow] k_type=0
2289 11:03:13.924298
2290 11:03:13.924409 ==CLK 0==
2291 11:03:13.927593 Final CLK duty delay cell = -4
2292 11:03:13.931235 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2293 11:03:13.934452 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2294 11:03:13.937623 [-4] AVG Duty = 4937%(X100)
2295 11:03:13.937725
2296 11:03:13.940721 CH0 CLK Duty spec in!! Max-Min= 187%
2297 11:03:13.944458 [DutyScan_Calibration_Flow] ====Done====
2298 11:03:13.944557
2299 11:03:13.947393 [DutyScan_Calibration_Flow] k_type=1
2300 11:03:13.964094
2301 11:03:13.964221 ==DQS 0 ==
2302 11:03:13.967256 Final DQS duty delay cell = 0
2303 11:03:13.970902 [0] MAX Duty = 5156%(X100), DQS PI = 18
2304 11:03:13.974105 [0] MIN Duty = 5093%(X100), DQS PI = 0
2305 11:03:13.974214 [0] AVG Duty = 5124%(X100)
2306 11:03:13.977085
2307 11:03:13.977206 ==DQS 1 ==
2308 11:03:13.980686 Final DQS duty delay cell = 0
2309 11:03:13.984298 [0] MAX Duty = 5093%(X100), DQS PI = 4
2310 11:03:13.987190 [0] MIN Duty = 4969%(X100), DQS PI = 62
2311 11:03:13.987290 [0] AVG Duty = 5031%(X100)
2312 11:03:13.990678
2313 11:03:13.993955 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2314 11:03:13.994053
2315 11:03:13.997473 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2316 11:03:14.000714 [DutyScan_Calibration_Flow] ====Done====
2317 11:03:14.000811
2318 11:03:14.003820 [DutyScan_Calibration_Flow] k_type=3
2319 11:03:14.020613
2320 11:03:14.020747 ==DQM 0 ==
2321 11:03:14.023782 Final DQM duty delay cell = 0
2322 11:03:14.027082 [0] MAX Duty = 5125%(X100), DQS PI = 20
2323 11:03:14.030362 [0] MIN Duty = 4844%(X100), DQS PI = 50
2324 11:03:14.033583 [0] AVG Duty = 4984%(X100)
2325 11:03:14.033684
2326 11:03:14.033771 ==DQM 1 ==
2327 11:03:14.037331 Final DQM duty delay cell = 0
2328 11:03:14.040429 [0] MAX Duty = 4969%(X100), DQS PI = 2
2329 11:03:14.043701 [0] MIN Duty = 4875%(X100), DQS PI = 20
2330 11:03:14.043803 [0] AVG Duty = 4922%(X100)
2331 11:03:14.046666
2332 11:03:14.050245 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2333 11:03:14.050341
2334 11:03:14.053493 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2335 11:03:14.056755 [DutyScan_Calibration_Flow] ====Done====
2336 11:03:14.056853
2337 11:03:14.060027 [DutyScan_Calibration_Flow] k_type=2
2338 11:03:14.077010
2339 11:03:14.077160 ==DQ 0 ==
2340 11:03:14.080716 Final DQ duty delay cell = 0
2341 11:03:14.083654 [0] MAX Duty = 5156%(X100), DQS PI = 20
2342 11:03:14.086673 [0] MIN Duty = 4938%(X100), DQS PI = 58
2343 11:03:14.086773 [0] AVG Duty = 5047%(X100)
2344 11:03:14.086858
2345 11:03:14.090004 ==DQ 1 ==
2346 11:03:14.093720 Final DQ duty delay cell = 0
2347 11:03:14.096517 [0] MAX Duty = 5125%(X100), DQS PI = 4
2348 11:03:14.099907 [0] MIN Duty = 4938%(X100), DQS PI = 16
2349 11:03:14.100007 [0] AVG Duty = 5031%(X100)
2350 11:03:14.100092
2351 11:03:14.103596 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2352 11:03:14.103692
2353 11:03:14.107274 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2354 11:03:14.113304 [DutyScan_Calibration_Flow] ====Done====
2355 11:03:14.113408 ==
2356 11:03:14.116515 Dram Type= 6, Freq= 0, CH_1, rank 0
2357 11:03:14.120120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 11:03:14.120225 ==
2359 11:03:14.123524 [Duty_Offset_Calibration]
2360 11:03:14.123621 B0:0 B1:-1 CA:3
2361 11:03:14.123705
2362 11:03:14.127063 [DutyScan_Calibration_Flow] k_type=0
2363 11:03:14.136675
2364 11:03:14.136791 ==CLK 0==
2365 11:03:14.140096 Final CLK duty delay cell = 0
2366 11:03:14.143708 [0] MAX Duty = 5156%(X100), DQS PI = 0
2367 11:03:14.146607 [0] MIN Duty = 5000%(X100), DQS PI = 36
2368 11:03:14.146709 [0] AVG Duty = 5078%(X100)
2369 11:03:14.150296
2370 11:03:14.153434 CH1 CLK Duty spec in!! Max-Min= 156%
2371 11:03:14.156497 [DutyScan_Calibration_Flow] ====Done====
2372 11:03:14.156593
2373 11:03:14.160018 [DutyScan_Calibration_Flow] k_type=1
2374 11:03:14.175944
2375 11:03:14.176078 ==DQS 0 ==
2376 11:03:14.179263 Final DQS duty delay cell = 0
2377 11:03:14.182533 [0] MAX Duty = 5156%(X100), DQS PI = 18
2378 11:03:14.185963 [0] MIN Duty = 4907%(X100), DQS PI = 38
2379 11:03:14.186061 [0] AVG Duty = 5031%(X100)
2380 11:03:14.189526
2381 11:03:14.189621 ==DQS 1 ==
2382 11:03:14.192833 Final DQS duty delay cell = 0
2383 11:03:14.196692 [0] MAX Duty = 5156%(X100), DQS PI = 8
2384 11:03:14.199432 [0] MIN Duty = 5000%(X100), DQS PI = 26
2385 11:03:14.199528 [0] AVG Duty = 5078%(X100)
2386 11:03:14.202533
2387 11:03:14.205965 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2388 11:03:14.206063
2389 11:03:14.209068 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2390 11:03:14.212627 [DutyScan_Calibration_Flow] ====Done====
2391 11:03:14.212724
2392 11:03:14.216331 [DutyScan_Calibration_Flow] k_type=3
2393 11:03:14.232353
2394 11:03:14.232472 ==DQM 0 ==
2395 11:03:14.235691 Final DQM duty delay cell = 0
2396 11:03:14.239209 [0] MAX Duty = 5031%(X100), DQS PI = 26
2397 11:03:14.242549 [0] MIN Duty = 4813%(X100), DQS PI = 38
2398 11:03:14.245592 [0] AVG Duty = 4922%(X100)
2399 11:03:14.245690
2400 11:03:14.245774 ==DQM 1 ==
2401 11:03:14.249121 Final DQM duty delay cell = 0
2402 11:03:14.252531 [0] MAX Duty = 4969%(X100), DQS PI = 34
2403 11:03:14.255387 [0] MIN Duty = 4813%(X100), DQS PI = 0
2404 11:03:14.259139 [0] AVG Duty = 4891%(X100)
2405 11:03:14.259236
2406 11:03:14.262170 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2407 11:03:14.262267
2408 11:03:14.266113 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2409 11:03:14.268968 [DutyScan_Calibration_Flow] ====Done====
2410 11:03:14.269065
2411 11:03:14.272126 [DutyScan_Calibration_Flow] k_type=2
2412 11:03:14.289054
2413 11:03:14.289199 ==DQ 0 ==
2414 11:03:14.292254 Final DQ duty delay cell = -4
2415 11:03:14.295644 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2416 11:03:14.298662 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2417 11:03:14.301976 [-4] AVG Duty = 4922%(X100)
2418 11:03:14.302076
2419 11:03:14.302162 ==DQ 1 ==
2420 11:03:14.305209 Final DQ duty delay cell = 4
2421 11:03:14.308697 [4] MAX Duty = 5156%(X100), DQS PI = 26
2422 11:03:14.312018 [4] MIN Duty = 5031%(X100), DQS PI = 62
2423 11:03:14.315118 [4] AVG Duty = 5093%(X100)
2424 11:03:14.315217
2425 11:03:14.319003 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2426 11:03:14.319124
2427 11:03:14.321899 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2428 11:03:14.325307 [DutyScan_Calibration_Flow] ====Done====
2429 11:03:14.328517 nWR fixed to 30
2430 11:03:14.331711 [ModeRegInit_LP4] CH0 RK0
2431 11:03:14.331810 [ModeRegInit_LP4] CH0 RK1
2432 11:03:14.335038 [ModeRegInit_LP4] CH1 RK0
2433 11:03:14.338156 [ModeRegInit_LP4] CH1 RK1
2434 11:03:14.338268 match AC timing 7
2435 11:03:14.345120 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2436 11:03:14.348629 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2437 11:03:14.351634 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2438 11:03:14.358295 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2439 11:03:14.361663 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2440 11:03:14.361740 ==
2441 11:03:14.364922 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 11:03:14.368454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 11:03:14.368562 ==
2444 11:03:14.375260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2445 11:03:14.381422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2446 11:03:14.389115 [CA 0] Center 39 (9~70) winsize 62
2447 11:03:14.392625 [CA 1] Center 39 (9~69) winsize 61
2448 11:03:14.395743 [CA 2] Center 35 (5~66) winsize 62
2449 11:03:14.399153 [CA 3] Center 35 (5~66) winsize 62
2450 11:03:14.402260 [CA 4] Center 33 (3~64) winsize 62
2451 11:03:14.405706 [CA 5] Center 33 (3~63) winsize 61
2452 11:03:14.405782
2453 11:03:14.409237 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2454 11:03:14.409313
2455 11:03:14.412369 [CATrainingPosCal] consider 1 rank data
2456 11:03:14.415861 u2DelayCellTimex100 = 270/100 ps
2457 11:03:14.419051 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2458 11:03:14.425864 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2459 11:03:14.428760 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2460 11:03:14.432305 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2461 11:03:14.435815 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2462 11:03:14.439413 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2463 11:03:14.439495
2464 11:03:14.442620 CA PerBit enable=1, Macro0, CA PI delay=33
2465 11:03:14.442697
2466 11:03:14.445766 [CBTSetCACLKResult] CA Dly = 33
2467 11:03:14.445843 CS Dly: 7 (0~38)
2468 11:03:14.449016 ==
2469 11:03:14.449118 Dram Type= 6, Freq= 0, CH_0, rank 1
2470 11:03:14.455476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 11:03:14.455556 ==
2472 11:03:14.459103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 11:03:14.465489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2474 11:03:14.475048 [CA 0] Center 39 (9~70) winsize 62
2475 11:03:14.478253 [CA 1] Center 39 (9~70) winsize 62
2476 11:03:14.481700 [CA 2] Center 35 (5~66) winsize 62
2477 11:03:14.485143 [CA 3] Center 35 (5~66) winsize 62
2478 11:03:14.488261 [CA 4] Center 34 (4~65) winsize 62
2479 11:03:14.491674 [CA 5] Center 33 (3~64) winsize 62
2480 11:03:14.491751
2481 11:03:14.495169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 11:03:14.495246
2483 11:03:14.498251 [CATrainingPosCal] consider 2 rank data
2484 11:03:14.501400 u2DelayCellTimex100 = 270/100 ps
2485 11:03:14.504676 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2486 11:03:14.508351 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2487 11:03:14.515160 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 11:03:14.518354 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2489 11:03:14.521771 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2490 11:03:14.525170 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2491 11:03:14.525263
2492 11:03:14.528275 CA PerBit enable=1, Macro0, CA PI delay=33
2493 11:03:14.528353
2494 11:03:14.531585 [CBTSetCACLKResult] CA Dly = 33
2495 11:03:14.531691 CS Dly: 8 (0~41)
2496 11:03:14.531778
2497 11:03:14.535052 ----->DramcWriteLeveling(PI) begin...
2498 11:03:14.538081 ==
2499 11:03:14.541687 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 11:03:14.544922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 11:03:14.545002 ==
2502 11:03:14.548161 Write leveling (Byte 0): 32 => 32
2503 11:03:14.551684 Write leveling (Byte 1): 27 => 27
2504 11:03:14.554977 DramcWriteLeveling(PI) end<-----
2505 11:03:14.555057
2506 11:03:14.555117 ==
2507 11:03:14.558251 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 11:03:14.561433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 11:03:14.561516 ==
2510 11:03:14.564815 [Gating] SW mode calibration
2511 11:03:14.571521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2512 11:03:14.577998 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2513 11:03:14.581538 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2514 11:03:14.584539 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2515 11:03:14.588507 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 11:03:14.594751 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 11:03:14.597950 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 11:03:14.601523 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 11:03:14.607825 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2520 11:03:14.611273 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2521 11:03:14.614464 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
2522 11:03:14.621342 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 11:03:14.625362 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 11:03:14.628124 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 11:03:14.634672 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 11:03:14.638211 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 11:03:14.641008 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
2528 11:03:14.647647 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2529 11:03:14.651119 1 1 0 | B1->B0 | 2d2c 4646 | 1 0 | (0 0) (0 0)
2530 11:03:14.654471 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 11:03:14.661960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 11:03:14.664242 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 11:03:14.667448 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 11:03:14.674320 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 11:03:14.677240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 11:03:14.680749 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2537 11:03:14.687950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2538 11:03:14.690532 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2539 11:03:14.694276 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 11:03:14.700444 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 11:03:14.704057 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 11:03:14.707219 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 11:03:14.713897 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 11:03:14.717034 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:03:14.720757 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:03:14.727054 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:03:14.730752 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:03:14.733898 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:03:14.740706 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:03:14.743975 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:03:14.747354 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:03:14.753604 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2553 11:03:14.753691 Total UI for P1: 0, mck2ui 16
2554 11:03:14.760106 best dqsien dly found for B0: ( 1, 3, 26)
2555 11:03:14.763731 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2556 11:03:14.767104 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 11:03:14.770483 Total UI for P1: 0, mck2ui 16
2558 11:03:14.774017 best dqsien dly found for B1: ( 1, 4, 0)
2559 11:03:14.777540 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2560 11:03:14.780619 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2561 11:03:14.780698
2562 11:03:14.783836 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2563 11:03:14.787425 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 11:03:14.790572 [Gating] SW calibration Done
2565 11:03:14.790655 ==
2566 11:03:14.794153 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 11:03:14.800210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 11:03:14.800295 ==
2569 11:03:14.800356 RX Vref Scan: 0
2570 11:03:14.800413
2571 11:03:14.803480 RX Vref 0 -> 0, step: 1
2572 11:03:14.803558
2573 11:03:14.807050 RX Delay -40 -> 252, step: 8
2574 11:03:14.810243 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2575 11:03:14.813856 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2576 11:03:14.816731 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2577 11:03:14.820003 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2578 11:03:14.826816 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2579 11:03:14.830125 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2580 11:03:14.833460 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2581 11:03:14.837132 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2582 11:03:14.840025 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2583 11:03:14.846751 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2584 11:03:14.850115 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2585 11:03:14.853318 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2586 11:03:14.857311 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2587 11:03:14.859831 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2588 11:03:14.866618 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2589 11:03:14.870070 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2590 11:03:14.870148 ==
2591 11:03:14.873372 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 11:03:14.876610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 11:03:14.876689 ==
2594 11:03:14.879837 DQS Delay:
2595 11:03:14.879914 DQS0 = 0, DQS1 = 0
2596 11:03:14.879974 DQM Delay:
2597 11:03:14.883391 DQM0 = 117, DQM1 = 107
2598 11:03:14.883469 DQ Delay:
2599 11:03:14.886619 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2600 11:03:14.890050 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2601 11:03:14.893725 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2602 11:03:14.900031 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2603 11:03:14.900115
2604 11:03:14.900175
2605 11:03:14.900232 ==
2606 11:03:14.903150 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 11:03:14.906221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 11:03:14.906303 ==
2609 11:03:14.906363
2610 11:03:14.906419
2611 11:03:14.909906 TX Vref Scan disable
2612 11:03:14.909984 == TX Byte 0 ==
2613 11:03:14.916772 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2614 11:03:14.919511 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2615 11:03:14.919591 == TX Byte 1 ==
2616 11:03:14.926244 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2617 11:03:14.929909 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2618 11:03:14.929992 ==
2619 11:03:14.933224 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 11:03:14.936406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 11:03:14.936487 ==
2622 11:03:14.949371 TX Vref=22, minBit 1, minWin=25, winSum=413
2623 11:03:14.952993 TX Vref=24, minBit 8, minWin=25, winSum=422
2624 11:03:14.956444 TX Vref=26, minBit 13, minWin=25, winSum=424
2625 11:03:14.959649 TX Vref=28, minBit 4, minWin=26, winSum=430
2626 11:03:14.963198 TX Vref=30, minBit 4, minWin=26, winSum=431
2627 11:03:14.969597 TX Vref=32, minBit 13, minWin=25, winSum=428
2628 11:03:14.973431 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 30
2629 11:03:14.973516
2630 11:03:14.976179 Final TX Range 1 Vref 30
2631 11:03:14.976257
2632 11:03:14.976317 ==
2633 11:03:14.979425 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 11:03:14.983054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 11:03:14.985909 ==
2636 11:03:14.985985
2637 11:03:14.986044
2638 11:03:14.986098 TX Vref Scan disable
2639 11:03:14.989537 == TX Byte 0 ==
2640 11:03:14.992697 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2641 11:03:14.999537 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2642 11:03:14.999618 == TX Byte 1 ==
2643 11:03:15.003067 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2644 11:03:15.009197 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2645 11:03:15.009285
2646 11:03:15.009345 [DATLAT]
2647 11:03:15.009400 Freq=1200, CH0 RK0
2648 11:03:15.009455
2649 11:03:15.012745 DATLAT Default: 0xd
2650 11:03:15.012821 0, 0xFFFF, sum = 0
2651 11:03:15.015996 1, 0xFFFF, sum = 0
2652 11:03:15.019158 2, 0xFFFF, sum = 0
2653 11:03:15.019238 3, 0xFFFF, sum = 0
2654 11:03:15.023281 4, 0xFFFF, sum = 0
2655 11:03:15.023359 5, 0xFFFF, sum = 0
2656 11:03:15.025810 6, 0xFFFF, sum = 0
2657 11:03:15.025887 7, 0xFFFF, sum = 0
2658 11:03:15.029548 8, 0xFFFF, sum = 0
2659 11:03:15.029625 9, 0xFFFF, sum = 0
2660 11:03:15.032717 10, 0xFFFF, sum = 0
2661 11:03:15.032796 11, 0xFFFF, sum = 0
2662 11:03:15.036518 12, 0x0, sum = 1
2663 11:03:15.036597 13, 0x0, sum = 2
2664 11:03:15.039337 14, 0x0, sum = 3
2665 11:03:15.039416 15, 0x0, sum = 4
2666 11:03:15.039477 best_step = 13
2667 11:03:15.042538
2668 11:03:15.042614 ==
2669 11:03:15.045939 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 11:03:15.049071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 11:03:15.049208 ==
2672 11:03:15.049269 RX Vref Scan: 1
2673 11:03:15.049326
2674 11:03:15.052869 Set Vref Range= 32 -> 127
2675 11:03:15.052947
2676 11:03:15.055831 RX Vref 32 -> 127, step: 1
2677 11:03:15.055909
2678 11:03:15.059120 RX Delay -21 -> 252, step: 4
2679 11:03:15.059197
2680 11:03:15.062797 Set Vref, RX VrefLevel [Byte0]: 32
2681 11:03:15.065963 [Byte1]: 32
2682 11:03:15.066042
2683 11:03:15.069588 Set Vref, RX VrefLevel [Byte0]: 33
2684 11:03:15.072661 [Byte1]: 33
2685 11:03:15.076026
2686 11:03:15.076103 Set Vref, RX VrefLevel [Byte0]: 34
2687 11:03:15.079176 [Byte1]: 34
2688 11:03:15.083923
2689 11:03:15.084005 Set Vref, RX VrefLevel [Byte0]: 35
2690 11:03:15.087482 [Byte1]: 35
2691 11:03:15.091787
2692 11:03:15.091866 Set Vref, RX VrefLevel [Byte0]: 36
2693 11:03:15.094970 [Byte1]: 36
2694 11:03:15.099677
2695 11:03:15.099756 Set Vref, RX VrefLevel [Byte0]: 37
2696 11:03:15.103126 [Byte1]: 37
2697 11:03:15.108099
2698 11:03:15.108179 Set Vref, RX VrefLevel [Byte0]: 38
2699 11:03:15.111361 [Byte1]: 38
2700 11:03:15.115611
2701 11:03:15.115725 Set Vref, RX VrefLevel [Byte0]: 39
2702 11:03:15.119440 [Byte1]: 39
2703 11:03:15.123825
2704 11:03:15.123908 Set Vref, RX VrefLevel [Byte0]: 40
2705 11:03:15.127375 [Byte1]: 40
2706 11:03:15.131591
2707 11:03:15.131673 Set Vref, RX VrefLevel [Byte0]: 41
2708 11:03:15.134852 [Byte1]: 41
2709 11:03:15.139791
2710 11:03:15.139875 Set Vref, RX VrefLevel [Byte0]: 42
2711 11:03:15.142843 [Byte1]: 42
2712 11:03:15.147137
2713 11:03:15.147219 Set Vref, RX VrefLevel [Byte0]: 43
2714 11:03:15.150416 [Byte1]: 43
2715 11:03:15.155209
2716 11:03:15.155290 Set Vref, RX VrefLevel [Byte0]: 44
2717 11:03:15.158788 [Byte1]: 44
2718 11:03:15.162914
2719 11:03:15.162995 Set Vref, RX VrefLevel [Byte0]: 45
2720 11:03:15.166551 [Byte1]: 45
2721 11:03:15.171193
2722 11:03:15.171280 Set Vref, RX VrefLevel [Byte0]: 46
2723 11:03:15.174665 [Byte1]: 46
2724 11:03:15.179476
2725 11:03:15.179578 Set Vref, RX VrefLevel [Byte0]: 47
2726 11:03:15.182416 [Byte1]: 47
2727 11:03:15.187136
2728 11:03:15.187215 Set Vref, RX VrefLevel [Byte0]: 48
2729 11:03:15.190339 [Byte1]: 48
2730 11:03:15.195180
2731 11:03:15.195261 Set Vref, RX VrefLevel [Byte0]: 49
2732 11:03:15.198106 [Byte1]: 49
2733 11:03:15.202651
2734 11:03:15.202730 Set Vref, RX VrefLevel [Byte0]: 50
2735 11:03:15.205839 [Byte1]: 50
2736 11:03:15.210575
2737 11:03:15.210654 Set Vref, RX VrefLevel [Byte0]: 51
2738 11:03:15.214125 [Byte1]: 51
2739 11:03:15.218890
2740 11:03:15.218970 Set Vref, RX VrefLevel [Byte0]: 52
2741 11:03:15.221865 [Byte1]: 52
2742 11:03:15.226387
2743 11:03:15.226467 Set Vref, RX VrefLevel [Byte0]: 53
2744 11:03:15.229663 [Byte1]: 53
2745 11:03:15.234746
2746 11:03:15.234825 Set Vref, RX VrefLevel [Byte0]: 54
2747 11:03:15.237744 [Byte1]: 54
2748 11:03:15.242310
2749 11:03:15.242389 Set Vref, RX VrefLevel [Byte0]: 55
2750 11:03:15.245853 [Byte1]: 55
2751 11:03:15.250323
2752 11:03:15.250404 Set Vref, RX VrefLevel [Byte0]: 56
2753 11:03:15.253990 [Byte1]: 56
2754 11:03:15.258380
2755 11:03:15.258504 Set Vref, RX VrefLevel [Byte0]: 57
2756 11:03:15.261345 [Byte1]: 57
2757 11:03:15.266523
2758 11:03:15.266600 Set Vref, RX VrefLevel [Byte0]: 58
2759 11:03:15.269441 [Byte1]: 58
2760 11:03:15.273804
2761 11:03:15.273884 Set Vref, RX VrefLevel [Byte0]: 59
2762 11:03:15.277507 [Byte1]: 59
2763 11:03:15.281893
2764 11:03:15.281970 Set Vref, RX VrefLevel [Byte0]: 60
2765 11:03:15.286019 [Byte1]: 60
2766 11:03:15.290050
2767 11:03:15.290127 Set Vref, RX VrefLevel [Byte0]: 61
2768 11:03:15.293042 [Byte1]: 61
2769 11:03:15.298207
2770 11:03:15.298300 Set Vref, RX VrefLevel [Byte0]: 62
2771 11:03:15.301346 [Byte1]: 62
2772 11:03:15.305977
2773 11:03:15.306058 Set Vref, RX VrefLevel [Byte0]: 63
2774 11:03:15.309002 [Byte1]: 63
2775 11:03:15.313655
2776 11:03:15.313738 Set Vref, RX VrefLevel [Byte0]: 64
2777 11:03:15.317068 [Byte1]: 64
2778 11:03:15.321830
2779 11:03:15.321913 Set Vref, RX VrefLevel [Byte0]: 65
2780 11:03:15.325033 [Byte1]: 65
2781 11:03:15.329695
2782 11:03:15.329777 Set Vref, RX VrefLevel [Byte0]: 66
2783 11:03:15.332828 [Byte1]: 66
2784 11:03:15.337327
2785 11:03:15.337409 Set Vref, RX VrefLevel [Byte0]: 67
2786 11:03:15.340730 [Byte1]: 67
2787 11:03:15.345603
2788 11:03:15.345684 Set Vref, RX VrefLevel [Byte0]: 68
2789 11:03:15.348869 [Byte1]: 68
2790 11:03:15.353520
2791 11:03:15.353615 Set Vref, RX VrefLevel [Byte0]: 69
2792 11:03:15.356689 [Byte1]: 69
2793 11:03:15.361233
2794 11:03:15.361313 Set Vref, RX VrefLevel [Byte0]: 70
2795 11:03:15.364544 [Byte1]: 70
2796 11:03:15.369367
2797 11:03:15.369448 Final RX Vref Byte 0 = 53 to rank0
2798 11:03:15.372374 Final RX Vref Byte 1 = 59 to rank0
2799 11:03:15.375806 Final RX Vref Byte 0 = 53 to rank1
2800 11:03:15.379181 Final RX Vref Byte 1 = 59 to rank1==
2801 11:03:15.383071 Dram Type= 6, Freq= 0, CH_0, rank 0
2802 11:03:15.389589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2803 11:03:15.389669 ==
2804 11:03:15.389729 DQS Delay:
2805 11:03:15.389784 DQS0 = 0, DQS1 = 0
2806 11:03:15.392637 DQM Delay:
2807 11:03:15.392714 DQM0 = 117, DQM1 = 105
2808 11:03:15.395950 DQ Delay:
2809 11:03:15.399758 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2810 11:03:15.402372 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2811 11:03:15.405976 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2812 11:03:15.409441 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2813 11:03:15.409584
2814 11:03:15.409663
2815 11:03:15.415676 [DQSOSCAuto] RK0, (LSB)MR18= 0x501, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 408 ps
2816 11:03:15.419690 CH0 RK0: MR19=404, MR18=501
2817 11:03:15.425992 CH0_RK0: MR19=0x404, MR18=0x501, DQSOSC=408, MR23=63, INC=39, DEC=26
2818 11:03:15.426084
2819 11:03:15.429551 ----->DramcWriteLeveling(PI) begin...
2820 11:03:15.429633 ==
2821 11:03:15.433347 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 11:03:15.436314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 11:03:15.436394 ==
2824 11:03:15.439559 Write leveling (Byte 0): 32 => 32
2825 11:03:15.442602 Write leveling (Byte 1): 26 => 26
2826 11:03:15.446066 DramcWriteLeveling(PI) end<-----
2827 11:03:15.446147
2828 11:03:15.446223 ==
2829 11:03:15.449195 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 11:03:15.452333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 11:03:15.456099 ==
2832 11:03:15.456178 [Gating] SW mode calibration
2833 11:03:15.465917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2834 11:03:15.469696 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2835 11:03:15.472349 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2836 11:03:15.479067 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 11:03:15.482313 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 11:03:15.486129 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 11:03:15.492484 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 11:03:15.495682 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2841 11:03:15.499204 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2842 11:03:15.505532 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
2843 11:03:15.509065 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2844 11:03:15.512418 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 11:03:15.519598 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 11:03:15.522254 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 11:03:15.525430 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 11:03:15.532049 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 11:03:15.535792 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2850 11:03:15.538734 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2851 11:03:15.545349 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2852 11:03:15.548944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 11:03:15.552578 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 11:03:15.558851 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 11:03:15.562199 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 11:03:15.565484 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 11:03:15.571674 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2858 11:03:15.575676 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2859 11:03:15.578653 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2860 11:03:15.581752 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 11:03:15.589043 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 11:03:15.592035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 11:03:15.595129 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:03:15.601754 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:03:15.605487 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:03:15.609077 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:03:15.615185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:03:15.618617 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:03:15.621959 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:03:15.628337 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:03:15.632461 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:03:15.635148 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:03:15.641534 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2874 11:03:15.645421 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2875 11:03:15.648306 Total UI for P1: 0, mck2ui 16
2876 11:03:15.651584 best dqsien dly found for B0: ( 1, 3, 24)
2877 11:03:15.655065 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2878 11:03:15.661540 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 11:03:15.661631 Total UI for P1: 0, mck2ui 16
2880 11:03:15.668266 best dqsien dly found for B1: ( 1, 4, 0)
2881 11:03:15.671324 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2882 11:03:15.675112 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2883 11:03:15.675195
2884 11:03:15.678238 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2885 11:03:15.681395 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2886 11:03:15.684964 [Gating] SW calibration Done
2887 11:03:15.685040 ==
2888 11:03:15.688244 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 11:03:15.691453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 11:03:15.691536 ==
2891 11:03:15.694976 RX Vref Scan: 0
2892 11:03:15.695059
2893 11:03:15.695119 RX Vref 0 -> 0, step: 1
2894 11:03:15.695174
2895 11:03:15.698293 RX Delay -40 -> 252, step: 8
2896 11:03:15.701384 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2897 11:03:15.707925 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2898 11:03:15.711633 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2899 11:03:15.715117 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2900 11:03:15.718145 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2901 11:03:15.721561 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2902 11:03:15.725071 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2903 11:03:15.731592 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2904 11:03:15.735047 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2905 11:03:15.738583 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2906 11:03:15.741436 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2907 11:03:15.744658 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2908 11:03:15.751232 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2909 11:03:15.754674 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2910 11:03:15.757819 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2911 11:03:15.761907 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2912 11:03:15.761992 ==
2913 11:03:15.764882 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 11:03:15.772377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 11:03:15.772465 ==
2916 11:03:15.772526 DQS Delay:
2917 11:03:15.774610 DQS0 = 0, DQS1 = 0
2918 11:03:15.774688 DQM Delay:
2919 11:03:15.777906 DQM0 = 116, DQM1 = 108
2920 11:03:15.777984 DQ Delay:
2921 11:03:15.781225 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2922 11:03:15.784676 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2923 11:03:15.788086 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2924 11:03:15.791060 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2925 11:03:15.791139
2926 11:03:15.791216
2927 11:03:15.791287 ==
2928 11:03:15.794292 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 11:03:15.801083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 11:03:15.801219 ==
2931 11:03:15.801296
2932 11:03:15.801368
2933 11:03:15.801438 TX Vref Scan disable
2934 11:03:15.804995 == TX Byte 0 ==
2935 11:03:15.807941 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2936 11:03:15.814255 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2937 11:03:15.814339 == TX Byte 1 ==
2938 11:03:15.817818 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2939 11:03:15.824515 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2940 11:03:15.824605 ==
2941 11:03:15.827746 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 11:03:15.830926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 11:03:15.831006 ==
2944 11:03:15.842985 TX Vref=22, minBit 10, minWin=25, winSum=418
2945 11:03:15.845802 TX Vref=24, minBit 13, minWin=25, winSum=423
2946 11:03:15.849726 TX Vref=26, minBit 13, minWin=25, winSum=428
2947 11:03:15.852400 TX Vref=28, minBit 5, minWin=26, winSum=433
2948 11:03:15.855856 TX Vref=30, minBit 10, minWin=26, winSum=432
2949 11:03:15.862688 TX Vref=32, minBit 5, minWin=26, winSum=430
2950 11:03:15.865850 [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 28
2951 11:03:15.865935
2952 11:03:15.869605 Final TX Range 1 Vref 28
2953 11:03:15.869684
2954 11:03:15.869762 ==
2955 11:03:15.872758 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 11:03:15.875748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 11:03:15.879031 ==
2958 11:03:15.879158
2959 11:03:15.879266
2960 11:03:15.879388 TX Vref Scan disable
2961 11:03:15.882921 == TX Byte 0 ==
2962 11:03:15.886448 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2963 11:03:15.889692 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2964 11:03:15.892655 == TX Byte 1 ==
2965 11:03:15.895949 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2966 11:03:15.902906 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2967 11:03:15.902990
2968 11:03:15.903049 [DATLAT]
2969 11:03:15.903104 Freq=1200, CH0 RK1
2970 11:03:15.903198
2971 11:03:15.905861 DATLAT Default: 0xd
2972 11:03:15.905938 0, 0xFFFF, sum = 0
2973 11:03:15.909460 1, 0xFFFF, sum = 0
2974 11:03:15.909540 2, 0xFFFF, sum = 0
2975 11:03:15.912708 3, 0xFFFF, sum = 0
2976 11:03:15.915503 4, 0xFFFF, sum = 0
2977 11:03:15.915584 5, 0xFFFF, sum = 0
2978 11:03:15.919208 6, 0xFFFF, sum = 0
2979 11:03:15.919338 7, 0xFFFF, sum = 0
2980 11:03:15.922786 8, 0xFFFF, sum = 0
2981 11:03:15.922865 9, 0xFFFF, sum = 0
2982 11:03:15.925855 10, 0xFFFF, sum = 0
2983 11:03:15.925935 11, 0xFFFF, sum = 0
2984 11:03:15.929281 12, 0x0, sum = 1
2985 11:03:15.929360 13, 0x0, sum = 2
2986 11:03:15.932288 14, 0x0, sum = 3
2987 11:03:15.932367 15, 0x0, sum = 4
2988 11:03:15.935986 best_step = 13
2989 11:03:15.936063
2990 11:03:15.936157 ==
2991 11:03:15.938785 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 11:03:15.942328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 11:03:15.942407 ==
2994 11:03:15.942468 RX Vref Scan: 0
2995 11:03:15.945848
2996 11:03:15.945926 RX Vref 0 -> 0, step: 1
2997 11:03:15.945986
2998 11:03:15.949466 RX Delay -21 -> 252, step: 4
2999 11:03:15.952363 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3000 11:03:15.959308 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3001 11:03:15.962202 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3002 11:03:15.966041 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3003 11:03:15.969338 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3004 11:03:15.972249 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3005 11:03:15.978915 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3006 11:03:15.981938 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3007 11:03:15.985729 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3008 11:03:15.988666 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3009 11:03:15.992202 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3010 11:03:15.999078 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3011 11:03:16.001793 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3012 11:03:16.005253 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3013 11:03:16.008832 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3014 11:03:16.015184 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3015 11:03:16.015266 ==
3016 11:03:16.018567 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 11:03:16.022300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 11:03:16.022381 ==
3019 11:03:16.022476 DQS Delay:
3020 11:03:16.025551 DQS0 = 0, DQS1 = 0
3021 11:03:16.025629 DQM Delay:
3022 11:03:16.028944 DQM0 = 116, DQM1 = 106
3023 11:03:16.029044 DQ Delay:
3024 11:03:16.031867 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3025 11:03:16.035078 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3026 11:03:16.038789 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3027 11:03:16.041782 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3028 11:03:16.041860
3029 11:03:16.041921
3030 11:03:16.051821 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3031 11:03:16.054731 CH0 RK1: MR19=403, MR18=1FE
3032 11:03:16.058015 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3033 11:03:16.061517 [RxdqsGatingPostProcess] freq 1200
3034 11:03:16.068094 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3035 11:03:16.071376 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 11:03:16.074735 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 11:03:16.078293 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 11:03:16.081272 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 11:03:16.085288 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 11:03:16.088284 best DQS1 dly(2T, 0.5T) = (0, 12)
3041 11:03:16.091044 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 11:03:16.094403 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3043 11:03:16.097690 Pre-setting of DQS Precalculation
3044 11:03:16.101035 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3045 11:03:16.101142 ==
3046 11:03:16.104330 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 11:03:16.107586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 11:03:16.107666 ==
3049 11:03:16.114036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3050 11:03:16.120588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3051 11:03:16.128714 [CA 0] Center 38 (8~68) winsize 61
3052 11:03:16.132098 [CA 1] Center 37 (7~68) winsize 62
3053 11:03:16.135281 [CA 2] Center 35 (5~65) winsize 61
3054 11:03:16.138582 [CA 3] Center 34 (4~64) winsize 61
3055 11:03:16.142261 [CA 4] Center 34 (4~65) winsize 62
3056 11:03:16.145418 [CA 5] Center 33 (3~63) winsize 61
3057 11:03:16.145496
3058 11:03:16.148647 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3059 11:03:16.148725
3060 11:03:16.151672 [CATrainingPosCal] consider 1 rank data
3061 11:03:16.155223 u2DelayCellTimex100 = 270/100 ps
3062 11:03:16.158409 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3063 11:03:16.165076 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 11:03:16.168240 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3065 11:03:16.171644 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3066 11:03:16.174847 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3067 11:03:16.178104 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3068 11:03:16.178197
3069 11:03:16.181395 CA PerBit enable=1, Macro0, CA PI delay=33
3070 11:03:16.181491
3071 11:03:16.184758 [CBTSetCACLKResult] CA Dly = 33
3072 11:03:16.188365 CS Dly: 4 (0~35)
3073 11:03:16.188458 ==
3074 11:03:16.191244 Dram Type= 6, Freq= 0, CH_1, rank 1
3075 11:03:16.194528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 11:03:16.194621 ==
3077 11:03:16.201666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 11:03:16.204648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3079 11:03:16.214473 [CA 0] Center 37 (7~68) winsize 62
3080 11:03:16.217829 [CA 1] Center 38 (8~68) winsize 61
3081 11:03:16.220809 [CA 2] Center 35 (5~65) winsize 61
3082 11:03:16.224303 [CA 3] Center 34 (4~64) winsize 61
3083 11:03:16.227561 [CA 4] Center 34 (4~64) winsize 61
3084 11:03:16.230974 [CA 5] Center 33 (3~63) winsize 61
3085 11:03:16.231051
3086 11:03:16.234496 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3087 11:03:16.234573
3088 11:03:16.237647 [CATrainingPosCal] consider 2 rank data
3089 11:03:16.241169 u2DelayCellTimex100 = 270/100 ps
3090 11:03:16.244161 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3091 11:03:16.251239 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3092 11:03:16.253850 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 11:03:16.257264 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 11:03:16.260934 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 11:03:16.263899 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3096 11:03:16.263977
3097 11:03:16.267389 CA PerBit enable=1, Macro0, CA PI delay=33
3098 11:03:16.267467
3099 11:03:16.270950 [CBTSetCACLKResult] CA Dly = 33
3100 11:03:16.271028 CS Dly: 6 (0~39)
3101 11:03:16.273930
3102 11:03:16.277410 ----->DramcWriteLeveling(PI) begin...
3103 11:03:16.277489 ==
3104 11:03:16.280494 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 11:03:16.284019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 11:03:16.284097 ==
3107 11:03:16.287443 Write leveling (Byte 0): 23 => 23
3108 11:03:16.290701 Write leveling (Byte 1): 27 => 27
3109 11:03:16.293789 DramcWriteLeveling(PI) end<-----
3110 11:03:16.293867
3111 11:03:16.293927 ==
3112 11:03:16.297329 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 11:03:16.300848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 11:03:16.300926 ==
3115 11:03:16.304276 [Gating] SW mode calibration
3116 11:03:16.310890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3117 11:03:16.317374 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3118 11:03:16.320150 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3119 11:03:16.324233 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 11:03:16.331439 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 11:03:16.333350 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 11:03:16.336736 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 11:03:16.343425 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3124 11:03:16.347047 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3125 11:03:16.350019 0 15 28 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (0 0)
3126 11:03:16.356819 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 11:03:16.360002 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 11:03:16.363486 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 11:03:16.370119 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 11:03:16.373392 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 11:03:16.376648 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 11:03:16.382936 1 0 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
3133 11:03:16.386385 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3134 11:03:16.389593 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 11:03:16.396486 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 11:03:16.399472 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 11:03:16.402753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 11:03:16.409444 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 11:03:16.412620 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 11:03:16.415899 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3141 11:03:16.422420 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3142 11:03:16.425911 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 11:03:16.428940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 11:03:16.435772 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:03:16.438933 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:03:16.442257 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:03:16.449014 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:03:16.452167 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:03:16.455488 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:03:16.461979 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:03:16.465633 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:03:16.468758 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:03:16.475372 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:03:16.478598 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:03:16.481935 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:03:16.488375 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3157 11:03:16.491558 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3158 11:03:16.495187 Total UI for P1: 0, mck2ui 16
3159 11:03:16.499079 best dqsien dly found for B1: ( 1, 3, 24)
3160 11:03:16.501510 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 11:03:16.505121 Total UI for P1: 0, mck2ui 16
3162 11:03:16.508284 best dqsien dly found for B0: ( 1, 3, 26)
3163 11:03:16.511212 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3164 11:03:16.515018 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3165 11:03:16.515094
3166 11:03:16.521564 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3167 11:03:16.524288 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3168 11:03:16.528039 [Gating] SW calibration Done
3169 11:03:16.528117 ==
3170 11:03:16.531062 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 11:03:16.534606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 11:03:16.534690 ==
3173 11:03:16.534767 RX Vref Scan: 0
3174 11:03:16.534839
3175 11:03:16.537675 RX Vref 0 -> 0, step: 1
3176 11:03:16.537760
3177 11:03:16.541237 RX Delay -40 -> 252, step: 8
3178 11:03:16.544481 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3179 11:03:16.547466 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3180 11:03:16.554175 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3181 11:03:16.557597 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3182 11:03:16.561008 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3183 11:03:16.564055 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3184 11:03:16.567378 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3185 11:03:16.573982 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3186 11:03:16.577593 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3187 11:03:16.580940 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3188 11:03:16.584063 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3189 11:03:16.587343 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3190 11:03:16.593928 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3191 11:03:16.597176 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3192 11:03:16.600452 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3193 11:03:16.603719 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3194 11:03:16.603828 ==
3195 11:03:16.607157 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 11:03:16.613825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 11:03:16.613905 ==
3198 11:03:16.613966 DQS Delay:
3199 11:03:16.617058 DQS0 = 0, DQS1 = 0
3200 11:03:16.617180 DQM Delay:
3201 11:03:16.620459 DQM0 = 117, DQM1 = 113
3202 11:03:16.620557 DQ Delay:
3203 11:03:16.624174 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3204 11:03:16.627132 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3205 11:03:16.630501 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
3206 11:03:16.633772 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3207 11:03:16.633849
3208 11:03:16.633908
3209 11:03:16.633962 ==
3210 11:03:16.636688 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 11:03:16.643473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 11:03:16.643550 ==
3213 11:03:16.643609
3214 11:03:16.643664
3215 11:03:16.643716 TX Vref Scan disable
3216 11:03:16.647067 == TX Byte 0 ==
3217 11:03:16.650067 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3218 11:03:16.656750 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3219 11:03:16.656826 == TX Byte 1 ==
3220 11:03:16.660114 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3221 11:03:16.666503 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3222 11:03:16.666584 ==
3223 11:03:16.670098 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 11:03:16.673252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 11:03:16.673329 ==
3226 11:03:16.684872 TX Vref=22, minBit 2, minWin=25, winSum=413
3227 11:03:16.687976 TX Vref=24, minBit 2, minWin=25, winSum=416
3228 11:03:16.691268 TX Vref=26, minBit 3, minWin=25, winSum=423
3229 11:03:16.694807 TX Vref=28, minBit 3, minWin=25, winSum=429
3230 11:03:16.698526 TX Vref=30, minBit 2, minWin=26, winSum=429
3231 11:03:16.704742 TX Vref=32, minBit 3, minWin=26, winSum=429
3232 11:03:16.708199 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3233 11:03:16.708293
3234 11:03:16.711492 Final TX Range 1 Vref 30
3235 11:03:16.711577
3236 11:03:16.711636 ==
3237 11:03:16.714720 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 11:03:16.718027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 11:03:16.721367 ==
3240 11:03:16.721444
3241 11:03:16.721503
3242 11:03:16.721559 TX Vref Scan disable
3243 11:03:16.724726 == TX Byte 0 ==
3244 11:03:16.727786 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3245 11:03:16.734667 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3246 11:03:16.734746 == TX Byte 1 ==
3247 11:03:16.737942 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3248 11:03:16.744895 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3249 11:03:16.744973
3250 11:03:16.745032 [DATLAT]
3251 11:03:16.745086 Freq=1200, CH1 RK0
3252 11:03:16.745147
3253 11:03:16.747569 DATLAT Default: 0xd
3254 11:03:16.751118 0, 0xFFFF, sum = 0
3255 11:03:16.751195 1, 0xFFFF, sum = 0
3256 11:03:16.754510 2, 0xFFFF, sum = 0
3257 11:03:16.754587 3, 0xFFFF, sum = 0
3258 11:03:16.757628 4, 0xFFFF, sum = 0
3259 11:03:16.757705 5, 0xFFFF, sum = 0
3260 11:03:16.761417 6, 0xFFFF, sum = 0
3261 11:03:16.761496 7, 0xFFFF, sum = 0
3262 11:03:16.764307 8, 0xFFFF, sum = 0
3263 11:03:16.764384 9, 0xFFFF, sum = 0
3264 11:03:16.767522 10, 0xFFFF, sum = 0
3265 11:03:16.767600 11, 0xFFFF, sum = 0
3266 11:03:16.770745 12, 0x0, sum = 1
3267 11:03:16.770823 13, 0x0, sum = 2
3268 11:03:16.774695 14, 0x0, sum = 3
3269 11:03:16.774772 15, 0x0, sum = 4
3270 11:03:16.778140 best_step = 13
3271 11:03:16.778216
3272 11:03:16.778274 ==
3273 11:03:16.780614 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 11:03:16.784215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 11:03:16.784298 ==
3276 11:03:16.787403 RX Vref Scan: 1
3277 11:03:16.787479
3278 11:03:16.787538 Set Vref Range= 32 -> 127
3279 11:03:16.787594
3280 11:03:16.790645 RX Vref 32 -> 127, step: 1
3281 11:03:16.790720
3282 11:03:16.794370 RX Delay -13 -> 252, step: 4
3283 11:03:16.794445
3284 11:03:16.797129 Set Vref, RX VrefLevel [Byte0]: 32
3285 11:03:16.800883 [Byte1]: 32
3286 11:03:16.800959
3287 11:03:16.804291 Set Vref, RX VrefLevel [Byte0]: 33
3288 11:03:16.807015 [Byte1]: 33
3289 11:03:16.811222
3290 11:03:16.811297 Set Vref, RX VrefLevel [Byte0]: 34
3291 11:03:16.814399 [Byte1]: 34
3292 11:03:16.818889
3293 11:03:16.818965 Set Vref, RX VrefLevel [Byte0]: 35
3294 11:03:16.822067 [Byte1]: 35
3295 11:03:16.826643
3296 11:03:16.826726 Set Vref, RX VrefLevel [Byte0]: 36
3297 11:03:16.830135 [Byte1]: 36
3298 11:03:16.835166
3299 11:03:16.835244 Set Vref, RX VrefLevel [Byte0]: 37
3300 11:03:16.837927 [Byte1]: 37
3301 11:03:16.843044
3302 11:03:16.843121 Set Vref, RX VrefLevel [Byte0]: 38
3303 11:03:16.845889 [Byte1]: 38
3304 11:03:16.850409
3305 11:03:16.850484 Set Vref, RX VrefLevel [Byte0]: 39
3306 11:03:16.854185 [Byte1]: 39
3307 11:03:16.858403
3308 11:03:16.858479 Set Vref, RX VrefLevel [Byte0]: 40
3309 11:03:16.862011 [Byte1]: 40
3310 11:03:16.866348
3311 11:03:16.866423 Set Vref, RX VrefLevel [Byte0]: 41
3312 11:03:16.869446 [Byte1]: 41
3313 11:03:16.874156
3314 11:03:16.874230 Set Vref, RX VrefLevel [Byte0]: 42
3315 11:03:16.877129 [Byte1]: 42
3316 11:03:16.881873
3317 11:03:16.881948 Set Vref, RX VrefLevel [Byte0]: 43
3318 11:03:16.885026 [Byte1]: 43
3319 11:03:16.890104
3320 11:03:16.890180 Set Vref, RX VrefLevel [Byte0]: 44
3321 11:03:16.893320 [Byte1]: 44
3322 11:03:16.897857
3323 11:03:16.897932 Set Vref, RX VrefLevel [Byte0]: 45
3324 11:03:16.900904 [Byte1]: 45
3325 11:03:16.905653
3326 11:03:16.905729 Set Vref, RX VrefLevel [Byte0]: 46
3327 11:03:16.909403 [Byte1]: 46
3328 11:03:16.913491
3329 11:03:16.913568 Set Vref, RX VrefLevel [Byte0]: 47
3330 11:03:16.916638 [Byte1]: 47
3331 11:03:16.921522
3332 11:03:16.921598 Set Vref, RX VrefLevel [Byte0]: 48
3333 11:03:16.924522 [Byte1]: 48
3334 11:03:16.929541
3335 11:03:16.929616 Set Vref, RX VrefLevel [Byte0]: 49
3336 11:03:16.932375 [Byte1]: 49
3337 11:03:16.936984
3338 11:03:16.937061 Set Vref, RX VrefLevel [Byte0]: 50
3339 11:03:16.940233 [Byte1]: 50
3340 11:03:16.944961
3341 11:03:16.945037 Set Vref, RX VrefLevel [Byte0]: 51
3342 11:03:16.948202 [Byte1]: 51
3343 11:03:16.952970
3344 11:03:16.953074 Set Vref, RX VrefLevel [Byte0]: 52
3345 11:03:16.956337 [Byte1]: 52
3346 11:03:16.960916
3347 11:03:16.961012 Set Vref, RX VrefLevel [Byte0]: 53
3348 11:03:16.963973 [Byte1]: 53
3349 11:03:16.968958
3350 11:03:16.969051 Set Vref, RX VrefLevel [Byte0]: 54
3351 11:03:16.971905 [Byte1]: 54
3352 11:03:16.976963
3353 11:03:16.977059 Set Vref, RX VrefLevel [Byte0]: 55
3354 11:03:16.979883 [Byte1]: 55
3355 11:03:16.984489
3356 11:03:16.984585 Set Vref, RX VrefLevel [Byte0]: 56
3357 11:03:16.987895 [Byte1]: 56
3358 11:03:16.992135
3359 11:03:16.992228 Set Vref, RX VrefLevel [Byte0]: 57
3360 11:03:16.995595 [Byte1]: 57
3361 11:03:16.999904
3362 11:03:17.000002 Set Vref, RX VrefLevel [Byte0]: 58
3363 11:03:17.003749 [Byte1]: 58
3364 11:03:17.008487
3365 11:03:17.008581 Set Vref, RX VrefLevel [Byte0]: 59
3366 11:03:17.011297 [Byte1]: 59
3367 11:03:17.015678
3368 11:03:17.015769 Set Vref, RX VrefLevel [Byte0]: 60
3369 11:03:17.018921 [Byte1]: 60
3370 11:03:17.023534
3371 11:03:17.023613 Set Vref, RX VrefLevel [Byte0]: 61
3372 11:03:17.027120 [Byte1]: 61
3373 11:03:17.031401
3374 11:03:17.031476 Set Vref, RX VrefLevel [Byte0]: 62
3375 11:03:17.035369 [Byte1]: 62
3376 11:03:17.039540
3377 11:03:17.039616 Set Vref, RX VrefLevel [Byte0]: 63
3378 11:03:17.043370 [Byte1]: 63
3379 11:03:17.047313
3380 11:03:17.047388 Set Vref, RX VrefLevel [Byte0]: 64
3381 11:03:17.050416 [Byte1]: 64
3382 11:03:17.055353
3383 11:03:17.055454 Set Vref, RX VrefLevel [Byte0]: 65
3384 11:03:17.058420 [Byte1]: 65
3385 11:03:17.063073
3386 11:03:17.063173 Set Vref, RX VrefLevel [Byte0]: 66
3387 11:03:17.066409 [Byte1]: 66
3388 11:03:17.070923
3389 11:03:17.071026 Final RX Vref Byte 0 = 52 to rank0
3390 11:03:17.074582 Final RX Vref Byte 1 = 52 to rank0
3391 11:03:17.077680 Final RX Vref Byte 0 = 52 to rank1
3392 11:03:17.080874 Final RX Vref Byte 1 = 52 to rank1==
3393 11:03:17.084119 Dram Type= 6, Freq= 0, CH_1, rank 0
3394 11:03:17.090919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3395 11:03:17.091000 ==
3396 11:03:17.091060 DQS Delay:
3397 11:03:17.094298 DQS0 = 0, DQS1 = 0
3398 11:03:17.094378 DQM Delay:
3399 11:03:17.094438 DQM0 = 117, DQM1 = 114
3400 11:03:17.097343 DQ Delay:
3401 11:03:17.100968 DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118
3402 11:03:17.103929 DQ4 =112, DQ5 =124, DQ6 =128, DQ7 =112
3403 11:03:17.107209 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =108
3404 11:03:17.110295 DQ12 =124, DQ13 =122, DQ14 =120, DQ15 =122
3405 11:03:17.110389
3406 11:03:17.110471
3407 11:03:17.120318 [DQSOSCAuto] RK0, (LSB)MR18= 0xfb08, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3408 11:03:17.120426 CH1 RK0: MR19=304, MR18=FB08
3409 11:03:17.127053 CH1_RK0: MR19=0x304, MR18=0xFB08, DQSOSC=406, MR23=63, INC=39, DEC=26
3410 11:03:17.127138
3411 11:03:17.130338 ----->DramcWriteLeveling(PI) begin...
3412 11:03:17.133403 ==
3413 11:03:17.133505 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 11:03:17.140078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 11:03:17.140180 ==
3416 11:03:17.143621 Write leveling (Byte 0): 24 => 24
3417 11:03:17.147029 Write leveling (Byte 1): 27 => 27
3418 11:03:17.149872 DramcWriteLeveling(PI) end<-----
3419 11:03:17.149938
3420 11:03:17.150018 ==
3421 11:03:17.153129 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 11:03:17.156437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 11:03:17.156517 ==
3424 11:03:17.160267 [Gating] SW mode calibration
3425 11:03:17.166502 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3426 11:03:17.173272 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3427 11:03:17.176758 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 11:03:17.179704 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 11:03:17.186115 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 11:03:17.189500 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 11:03:17.193132 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 11:03:17.199842 0 15 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
3433 11:03:17.203105 0 15 24 | B1->B0 | 3434 2525 | 0 0 | (0 1) (1 0)
3434 11:03:17.205964 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3435 11:03:17.212715 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 11:03:17.215788 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 11:03:17.219096 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 11:03:17.225884 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 11:03:17.229425 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 11:03:17.232287 1 0 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3441 11:03:17.239357 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3442 11:03:17.242161 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3443 11:03:17.245659 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 11:03:17.252118 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 11:03:17.255888 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 11:03:17.259175 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 11:03:17.265658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 11:03:17.268778 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 11:03:17.271781 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3450 11:03:17.278268 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3451 11:03:17.281878 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 11:03:17.285288 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 11:03:17.291470 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 11:03:17.294734 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 11:03:17.298334 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 11:03:17.304870 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 11:03:17.308120 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 11:03:17.311161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 11:03:17.427850 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 11:03:17.428032 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:03:17.428132 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:03:17.428224 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:03:17.428311 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:03:17.428397 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3465 11:03:17.428481 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3466 11:03:17.428565 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3467 11:03:17.428647 Total UI for P1: 0, mck2ui 16
3468 11:03:17.428730 best dqsien dly found for B0: ( 1, 3, 22)
3469 11:03:17.428811 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 11:03:17.428893 Total UI for P1: 0, mck2ui 16
3471 11:03:17.428974 best dqsien dly found for B1: ( 1, 3, 28)
3472 11:03:17.429055 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3473 11:03:17.429147 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3474 11:03:17.429253
3475 11:03:17.429336 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3476 11:03:17.429417 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3477 11:03:17.429497 [Gating] SW calibration Done
3478 11:03:17.429575 ==
3479 11:03:17.429655 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 11:03:17.429737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 11:03:17.429819 ==
3482 11:03:17.429899 RX Vref Scan: 0
3483 11:03:17.429981
3484 11:03:17.430060 RX Vref 0 -> 0, step: 1
3485 11:03:17.430140
3486 11:03:17.430229 RX Delay -40 -> 252, step: 8
3487 11:03:17.430299 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3488 11:03:17.430368 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3489 11:03:17.430439 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3490 11:03:17.430510 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3491 11:03:17.430580 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3492 11:03:17.430650 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3493 11:03:17.430719 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3494 11:03:17.430992 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3495 11:03:17.433116 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3496 11:03:17.436538 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3497 11:03:17.439841 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3498 11:03:17.443284 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3499 11:03:17.449446 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3500 11:03:17.453087 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3501 11:03:17.456038 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3502 11:03:17.459525 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3503 11:03:17.459603 ==
3504 11:03:17.463020 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 11:03:17.469606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 11:03:17.469688 ==
3507 11:03:17.469749 DQS Delay:
3508 11:03:17.472721 DQS0 = 0, DQS1 = 0
3509 11:03:17.472798 DQM Delay:
3510 11:03:17.476490 DQM0 = 117, DQM1 = 115
3511 11:03:17.476567 DQ Delay:
3512 11:03:17.479427 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =115
3513 11:03:17.482838 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =115
3514 11:03:17.485949 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =107
3515 11:03:17.489746 DQ12 =123, DQ13 =123, DQ14 =123, DQ15 =123
3516 11:03:17.489824
3517 11:03:17.489883
3518 11:03:17.489938 ==
3519 11:03:17.492492 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 11:03:17.499137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 11:03:17.499217 ==
3522 11:03:17.499277
3523 11:03:17.499332
3524 11:03:17.499384 TX Vref Scan disable
3525 11:03:17.502863 == TX Byte 0 ==
3526 11:03:17.506437 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3527 11:03:17.513657 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3528 11:03:17.513741 == TX Byte 1 ==
3529 11:03:17.516082 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3530 11:03:17.522475 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3531 11:03:17.522560 ==
3532 11:03:17.525569 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 11:03:17.529066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 11:03:17.529167 ==
3535 11:03:17.540627 TX Vref=22, minBit 1, minWin=25, winSum=421
3536 11:03:17.544106 TX Vref=24, minBit 7, minWin=25, winSum=423
3537 11:03:17.547751 TX Vref=26, minBit 2, minWin=26, winSum=431
3538 11:03:17.550684 TX Vref=28, minBit 1, minWin=26, winSum=433
3539 11:03:17.553975 TX Vref=30, minBit 8, minWin=26, winSum=436
3540 11:03:17.557257 TX Vref=32, minBit 3, minWin=26, winSum=433
3541 11:03:17.564155 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3542 11:03:17.564289
3543 11:03:17.567493 Final TX Range 1 Vref 30
3544 11:03:17.567607
3545 11:03:17.567695 ==
3546 11:03:17.570760 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 11:03:17.574127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 11:03:17.574251 ==
3549 11:03:17.574312
3550 11:03:17.577172
3551 11:03:17.577283 TX Vref Scan disable
3552 11:03:17.580385 == TX Byte 0 ==
3553 11:03:17.583513 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3554 11:03:17.587057 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3555 11:03:17.590307 == TX Byte 1 ==
3556 11:03:17.593663 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3557 11:03:17.596966 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3558 11:03:17.600504
3559 11:03:17.600580 [DATLAT]
3560 11:03:17.600639 Freq=1200, CH1 RK1
3561 11:03:17.600694
3562 11:03:17.603784 DATLAT Default: 0xd
3563 11:03:17.603860 0, 0xFFFF, sum = 0
3564 11:03:17.606570 1, 0xFFFF, sum = 0
3565 11:03:17.610015 2, 0xFFFF, sum = 0
3566 11:03:17.610095 3, 0xFFFF, sum = 0
3567 11:03:17.613379 4, 0xFFFF, sum = 0
3568 11:03:17.613455 5, 0xFFFF, sum = 0
3569 11:03:17.616715 6, 0xFFFF, sum = 0
3570 11:03:17.616792 7, 0xFFFF, sum = 0
3571 11:03:17.620047 8, 0xFFFF, sum = 0
3572 11:03:17.620124 9, 0xFFFF, sum = 0
3573 11:03:17.623284 10, 0xFFFF, sum = 0
3574 11:03:17.623362 11, 0xFFFF, sum = 0
3575 11:03:17.626635 12, 0x0, sum = 1
3576 11:03:17.626711 13, 0x0, sum = 2
3577 11:03:17.630113 14, 0x0, sum = 3
3578 11:03:17.630190 15, 0x0, sum = 4
3579 11:03:17.632904 best_step = 13
3580 11:03:17.633001
3581 11:03:17.633086 ==
3582 11:03:17.636906 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 11:03:17.640456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 11:03:17.640533 ==
3585 11:03:17.640593 RX Vref Scan: 0
3586 11:03:17.643156
3587 11:03:17.643240 RX Vref 0 -> 0, step: 1
3588 11:03:17.643330
3589 11:03:17.646454 RX Delay -5 -> 252, step: 4
3590 11:03:17.649839 iDelay=191, Bit 0, Center 118 (51 ~ 186) 136
3591 11:03:17.656274 iDelay=191, Bit 1, Center 114 (47 ~ 182) 136
3592 11:03:17.659713 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3593 11:03:17.663002 iDelay=191, Bit 3, Center 114 (51 ~ 178) 128
3594 11:03:17.666103 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3595 11:03:17.669851 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3596 11:03:17.676516 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3597 11:03:17.679366 iDelay=191, Bit 7, Center 114 (47 ~ 182) 136
3598 11:03:17.682827 iDelay=191, Bit 8, Center 102 (43 ~ 162) 120
3599 11:03:17.686314 iDelay=191, Bit 9, Center 104 (43 ~ 166) 124
3600 11:03:17.689485 iDelay=191, Bit 10, Center 116 (55 ~ 178) 124
3601 11:03:17.696304 iDelay=191, Bit 11, Center 108 (47 ~ 170) 124
3602 11:03:17.699632 iDelay=191, Bit 12, Center 122 (63 ~ 182) 120
3603 11:03:17.703294 iDelay=191, Bit 13, Center 120 (59 ~ 182) 124
3604 11:03:17.706403 iDelay=191, Bit 14, Center 118 (59 ~ 178) 120
3605 11:03:17.712840 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3606 11:03:17.712919 ==
3607 11:03:17.715947 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 11:03:17.719601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 11:03:17.719679 ==
3610 11:03:17.719738 DQS Delay:
3611 11:03:17.722817 DQS0 = 0, DQS1 = 0
3612 11:03:17.722943 DQM Delay:
3613 11:03:17.725706 DQM0 = 116, DQM1 = 114
3614 11:03:17.725783 DQ Delay:
3615 11:03:17.729494 DQ0 =118, DQ1 =114, DQ2 =108, DQ3 =114
3616 11:03:17.732452 DQ4 =116, DQ5 =124, DQ6 =124, DQ7 =114
3617 11:03:17.735657 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =108
3618 11:03:17.738732 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =122
3619 11:03:17.738810
3620 11:03:17.742055
3621 11:03:17.748732 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3622 11:03:17.752383 CH1 RK1: MR19=304, MR18=F90B
3623 11:03:17.759189 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3624 11:03:17.761901 [RxdqsGatingPostProcess] freq 1200
3625 11:03:17.765682 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3626 11:03:17.768627 best DQS0 dly(2T, 0.5T) = (0, 11)
3627 11:03:17.772266 best DQS1 dly(2T, 0.5T) = (0, 11)
3628 11:03:17.775253 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3629 11:03:17.778845 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3630 11:03:17.781763 best DQS0 dly(2T, 0.5T) = (0, 11)
3631 11:03:17.785076 best DQS1 dly(2T, 0.5T) = (0, 11)
3632 11:03:17.788545 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3633 11:03:17.791748 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3634 11:03:17.794998 Pre-setting of DQS Precalculation
3635 11:03:17.798487 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3636 11:03:17.808360 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3637 11:03:17.814822 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3638 11:03:17.814907
3639 11:03:17.814967
3640 11:03:17.818138 [Calibration Summary] 2400 Mbps
3641 11:03:17.818214 CH 0, Rank 0
3642 11:03:17.821519 SW Impedance : PASS
3643 11:03:17.821596 DUTY Scan : NO K
3644 11:03:17.824585 ZQ Calibration : PASS
3645 11:03:17.828078 Jitter Meter : NO K
3646 11:03:17.828156 CBT Training : PASS
3647 11:03:17.831199 Write leveling : PASS
3648 11:03:17.834984 RX DQS gating : PASS
3649 11:03:17.835061 RX DQ/DQS(RDDQC) : PASS
3650 11:03:17.838411 TX DQ/DQS : PASS
3651 11:03:17.840932 RX DATLAT : PASS
3652 11:03:17.841008 RX DQ/DQS(Engine): PASS
3653 11:03:17.844451 TX OE : NO K
3654 11:03:17.844560 All Pass.
3655 11:03:17.844633
3656 11:03:17.847640 CH 0, Rank 1
3657 11:03:17.847717 SW Impedance : PASS
3658 11:03:17.850777 DUTY Scan : NO K
3659 11:03:17.854457 ZQ Calibration : PASS
3660 11:03:17.854560 Jitter Meter : NO K
3661 11:03:17.857695 CBT Training : PASS
3662 11:03:17.861028 Write leveling : PASS
3663 11:03:17.861120 RX DQS gating : PASS
3664 11:03:17.864384 RX DQ/DQS(RDDQC) : PASS
3665 11:03:17.864473 TX DQ/DQS : PASS
3666 11:03:17.867505 RX DATLAT : PASS
3667 11:03:17.870693 RX DQ/DQS(Engine): PASS
3668 11:03:17.870783 TX OE : NO K
3669 11:03:17.874831 All Pass.
3670 11:03:17.874925
3671 11:03:17.875009 CH 1, Rank 0
3672 11:03:17.877391 SW Impedance : PASS
3673 11:03:17.877483 DUTY Scan : NO K
3674 11:03:17.880809 ZQ Calibration : PASS
3675 11:03:17.883955 Jitter Meter : NO K
3676 11:03:17.884045 CBT Training : PASS
3677 11:03:17.887357 Write leveling : PASS
3678 11:03:17.890529 RX DQS gating : PASS
3679 11:03:17.890622 RX DQ/DQS(RDDQC) : PASS
3680 11:03:17.893748 TX DQ/DQS : PASS
3681 11:03:17.897126 RX DATLAT : PASS
3682 11:03:17.897244 RX DQ/DQS(Engine): PASS
3683 11:03:17.900483 TX OE : NO K
3684 11:03:17.900559 All Pass.
3685 11:03:17.900617
3686 11:03:17.904060 CH 1, Rank 1
3687 11:03:17.904136 SW Impedance : PASS
3688 11:03:17.906870 DUTY Scan : NO K
3689 11:03:17.910087 ZQ Calibration : PASS
3690 11:03:17.910163 Jitter Meter : NO K
3691 11:03:17.913974 CBT Training : PASS
3692 11:03:17.917022 Write leveling : PASS
3693 11:03:17.917116 RX DQS gating : PASS
3694 11:03:17.920379 RX DQ/DQS(RDDQC) : PASS
3695 11:03:17.923536 TX DQ/DQS : PASS
3696 11:03:17.923613 RX DATLAT : PASS
3697 11:03:17.927136 RX DQ/DQS(Engine): PASS
3698 11:03:17.930205 TX OE : NO K
3699 11:03:17.930303 All Pass.
3700 11:03:17.930388
3701 11:03:17.930470 DramC Write-DBI off
3702 11:03:17.933304 PER_BANK_REFRESH: Hybrid Mode
3703 11:03:17.936700 TX_TRACKING: ON
3704 11:03:17.943200 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3705 11:03:17.946506 [FAST_K] Save calibration result to emmc
3706 11:03:17.953039 dramc_set_vcore_voltage set vcore to 650000
3707 11:03:17.953146 Read voltage for 600, 5
3708 11:03:17.956508 Vio18 = 0
3709 11:03:17.956602 Vcore = 650000
3710 11:03:17.956684 Vdram = 0
3711 11:03:17.959755 Vddq = 0
3712 11:03:17.959842 Vmddr = 0
3713 11:03:17.963066 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3714 11:03:17.969369 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3715 11:03:17.972658 MEM_TYPE=3, freq_sel=19
3716 11:03:17.976845 sv_algorithm_assistance_LP4_1600
3717 11:03:17.979278 ============ PULL DRAM RESETB DOWN ============
3718 11:03:17.982971 ========== PULL DRAM RESETB DOWN end =========
3719 11:03:17.989408 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3720 11:03:17.992777 ===================================
3721 11:03:17.992867 LPDDR4 DRAM CONFIGURATION
3722 11:03:17.996090 ===================================
3723 11:03:17.999335 EX_ROW_EN[0] = 0x0
3724 11:03:17.999428 EX_ROW_EN[1] = 0x0
3725 11:03:18.002357 LP4Y_EN = 0x0
3726 11:03:18.005810 WORK_FSP = 0x0
3727 11:03:18.005886 WL = 0x2
3728 11:03:18.009070 RL = 0x2
3729 11:03:18.009172 BL = 0x2
3730 11:03:18.012475 RPST = 0x0
3731 11:03:18.012551 RD_PRE = 0x0
3732 11:03:18.015799 WR_PRE = 0x1
3733 11:03:18.015889 WR_PST = 0x0
3734 11:03:18.019003 DBI_WR = 0x0
3735 11:03:18.019079 DBI_RD = 0x0
3736 11:03:18.022498 OTF = 0x1
3737 11:03:18.025689 ===================================
3738 11:03:18.029023 ===================================
3739 11:03:18.029126 ANA top config
3740 11:03:18.032231 ===================================
3741 11:03:18.035234 DLL_ASYNC_EN = 0
3742 11:03:18.038829 ALL_SLAVE_EN = 1
3743 11:03:18.038923 NEW_RANK_MODE = 1
3744 11:03:18.042052 DLL_IDLE_MODE = 1
3745 11:03:18.045295 LP45_APHY_COMB_EN = 1
3746 11:03:18.048710 TX_ODT_DIS = 1
3747 11:03:18.051982 NEW_8X_MODE = 1
3748 11:03:18.055318 ===================================
3749 11:03:18.058722 ===================================
3750 11:03:18.062023 data_rate = 1200
3751 11:03:18.062121 CKR = 1
3752 11:03:18.064970 DQ_P2S_RATIO = 8
3753 11:03:18.068255 ===================================
3754 11:03:18.071355 CA_P2S_RATIO = 8
3755 11:03:18.074946 DQ_CA_OPEN = 0
3756 11:03:18.078780 DQ_SEMI_OPEN = 0
3757 11:03:18.081351 CA_SEMI_OPEN = 0
3758 11:03:18.081447 CA_FULL_RATE = 0
3759 11:03:18.084954 DQ_CKDIV4_EN = 1
3760 11:03:18.088195 CA_CKDIV4_EN = 1
3761 11:03:18.091845 CA_PREDIV_EN = 0
3762 11:03:18.094988 PH8_DLY = 0
3763 11:03:18.098077 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3764 11:03:18.098196 DQ_AAMCK_DIV = 4
3765 11:03:18.101480 CA_AAMCK_DIV = 4
3766 11:03:18.104719 CA_ADMCK_DIV = 4
3767 11:03:18.107668 DQ_TRACK_CA_EN = 0
3768 11:03:18.111215 CA_PICK = 600
3769 11:03:18.114526 CA_MCKIO = 600
3770 11:03:18.117918 MCKIO_SEMI = 0
3771 11:03:18.118052 PLL_FREQ = 2288
3772 11:03:18.121126 DQ_UI_PI_RATIO = 32
3773 11:03:18.124017 CA_UI_PI_RATIO = 0
3774 11:03:18.127920 ===================================
3775 11:03:18.131101 ===================================
3776 11:03:18.134139 memory_type:LPDDR4
3777 11:03:18.137487 GP_NUM : 10
3778 11:03:18.137564 SRAM_EN : 1
3779 11:03:18.141268 MD32_EN : 0
3780 11:03:18.144401 ===================================
3781 11:03:18.144478 [ANA_INIT] >>>>>>>>>>>>>>
3782 11:03:18.147752 <<<<<< [CONFIGURE PHASE]: ANA_TX
3783 11:03:18.150629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3784 11:03:18.153771 ===================================
3785 11:03:18.157077 data_rate = 1200,PCW = 0X5800
3786 11:03:18.160866 ===================================
3787 11:03:18.163980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3788 11:03:18.170186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3789 11:03:18.176722 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3790 11:03:18.180413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3791 11:03:18.183456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3792 11:03:18.187151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3793 11:03:18.190171 [ANA_INIT] flow start
3794 11:03:18.190247 [ANA_INIT] PLL >>>>>>>>
3795 11:03:18.193466 [ANA_INIT] PLL <<<<<<<<
3796 11:03:18.196538 [ANA_INIT] MIDPI >>>>>>>>
3797 11:03:18.200034 [ANA_INIT] MIDPI <<<<<<<<
3798 11:03:18.200110 [ANA_INIT] DLL >>>>>>>>
3799 11:03:18.203324 [ANA_INIT] flow end
3800 11:03:18.206609 ============ LP4 DIFF to SE enter ============
3801 11:03:18.209702 ============ LP4 DIFF to SE exit ============
3802 11:03:18.213784 [ANA_INIT] <<<<<<<<<<<<<
3803 11:03:18.216760 [Flow] Enable top DCM control >>>>>
3804 11:03:18.219930 [Flow] Enable top DCM control <<<<<
3805 11:03:18.223228 Enable DLL master slave shuffle
3806 11:03:18.229959 ==============================================================
3807 11:03:18.230046 Gating Mode config
3808 11:03:18.235959 ==============================================================
3809 11:03:18.236042 Config description:
3810 11:03:18.246203 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3811 11:03:18.252845 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3812 11:03:18.259749 SELPH_MODE 0: By rank 1: By Phase
3813 11:03:18.262631 ==============================================================
3814 11:03:18.266273 GAT_TRACK_EN = 1
3815 11:03:18.269426 RX_GATING_MODE = 2
3816 11:03:18.272588 RX_GATING_TRACK_MODE = 2
3817 11:03:18.275885 SELPH_MODE = 1
3818 11:03:18.279022 PICG_EARLY_EN = 1
3819 11:03:18.282333 VALID_LAT_VALUE = 1
3820 11:03:18.289104 ==============================================================
3821 11:03:18.292337 Enter into Gating configuration >>>>
3822 11:03:18.295597 Exit from Gating configuration <<<<
3823 11:03:18.299072 Enter into DVFS_PRE_config >>>>>
3824 11:03:18.308938 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3825 11:03:18.312249 Exit from DVFS_PRE_config <<<<<
3826 11:03:18.315489 Enter into PICG configuration >>>>
3827 11:03:18.318727 Exit from PICG configuration <<<<
3828 11:03:18.321956 [RX_INPUT] configuration >>>>>
3829 11:03:18.322036 [RX_INPUT] configuration <<<<<
3830 11:03:18.328775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3831 11:03:18.335671 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3832 11:03:18.341630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3833 11:03:18.345370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3834 11:03:18.351736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3835 11:03:18.358072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3836 11:03:18.361290 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3837 11:03:18.367902 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3838 11:03:18.371187 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3839 11:03:18.374750 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3840 11:03:18.377849 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3841 11:03:18.384679 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3842 11:03:18.387986 ===================================
3843 11:03:18.388066 LPDDR4 DRAM CONFIGURATION
3844 11:03:18.391283 ===================================
3845 11:03:18.394435 EX_ROW_EN[0] = 0x0
3846 11:03:18.397604 EX_ROW_EN[1] = 0x0
3847 11:03:18.397682 LP4Y_EN = 0x0
3848 11:03:18.400905 WORK_FSP = 0x0
3849 11:03:18.400982 WL = 0x2
3850 11:03:18.404614 RL = 0x2
3851 11:03:18.404692 BL = 0x2
3852 11:03:18.407639 RPST = 0x0
3853 11:03:18.407716 RD_PRE = 0x0
3854 11:03:18.411542 WR_PRE = 0x1
3855 11:03:18.411619 WR_PST = 0x0
3856 11:03:18.414080 DBI_WR = 0x0
3857 11:03:18.414158 DBI_RD = 0x0
3858 11:03:18.417468 OTF = 0x1
3859 11:03:18.420909 ===================================
3860 11:03:18.424118 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3861 11:03:18.427643 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3862 11:03:18.433847 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3863 11:03:18.437188 ===================================
3864 11:03:18.440676 LPDDR4 DRAM CONFIGURATION
3865 11:03:18.440756 ===================================
3866 11:03:18.444146 EX_ROW_EN[0] = 0x10
3867 11:03:18.447277 EX_ROW_EN[1] = 0x0
3868 11:03:18.447372 LP4Y_EN = 0x0
3869 11:03:18.450399 WORK_FSP = 0x0
3870 11:03:18.450477 WL = 0x2
3871 11:03:18.454073 RL = 0x2
3872 11:03:18.454152 BL = 0x2
3873 11:03:18.457101 RPST = 0x0
3874 11:03:18.457202 RD_PRE = 0x0
3875 11:03:18.460762 WR_PRE = 0x1
3876 11:03:18.460839 WR_PST = 0x0
3877 11:03:18.463575 DBI_WR = 0x0
3878 11:03:18.463652 DBI_RD = 0x0
3879 11:03:18.466878 OTF = 0x1
3880 11:03:18.470426 ===================================
3881 11:03:18.477286 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3882 11:03:18.480100 nWR fixed to 30
3883 11:03:18.483451 [ModeRegInit_LP4] CH0 RK0
3884 11:03:18.483529 [ModeRegInit_LP4] CH0 RK1
3885 11:03:18.486677 [ModeRegInit_LP4] CH1 RK0
3886 11:03:18.490144 [ModeRegInit_LP4] CH1 RK1
3887 11:03:18.490222 match AC timing 17
3888 11:03:18.496556 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3889 11:03:18.500015 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3890 11:03:18.503644 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3891 11:03:18.509767 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3892 11:03:18.512936 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3893 11:03:18.513017 ==
3894 11:03:18.516419 Dram Type= 6, Freq= 0, CH_0, rank 0
3895 11:03:18.519445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3896 11:03:18.519523 ==
3897 11:03:18.526199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3898 11:03:18.533340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3899 11:03:18.536194 [CA 0] Center 36 (6~67) winsize 62
3900 11:03:18.539741 [CA 1] Center 36 (6~67) winsize 62
3901 11:03:18.542608 [CA 2] Center 34 (4~65) winsize 62
3902 11:03:18.545815 [CA 3] Center 34 (4~65) winsize 62
3903 11:03:18.549334 [CA 4] Center 34 (3~65) winsize 63
3904 11:03:18.552400 [CA 5] Center 33 (3~64) winsize 62
3905 11:03:18.552493
3906 11:03:18.556228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3907 11:03:18.556305
3908 11:03:18.559034 [CATrainingPosCal] consider 1 rank data
3909 11:03:18.562789 u2DelayCellTimex100 = 270/100 ps
3910 11:03:18.565553 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3911 11:03:18.569050 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3912 11:03:18.572120 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3913 11:03:18.578914 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3914 11:03:18.582059 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3915 11:03:18.585436 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3916 11:03:18.585512
3917 11:03:18.588882 CA PerBit enable=1, Macro0, CA PI delay=33
3918 11:03:18.588957
3919 11:03:18.592083 [CBTSetCACLKResult] CA Dly = 33
3920 11:03:18.592160 CS Dly: 4 (0~35)
3921 11:03:18.592219 ==
3922 11:03:18.595155 Dram Type= 6, Freq= 0, CH_0, rank 1
3923 11:03:18.602068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 11:03:18.602172 ==
3925 11:03:18.605446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 11:03:18.611801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3927 11:03:18.615456 [CA 0] Center 36 (6~67) winsize 62
3928 11:03:18.618855 [CA 1] Center 36 (6~67) winsize 62
3929 11:03:18.622050 [CA 2] Center 35 (4~66) winsize 63
3930 11:03:18.625527 [CA 3] Center 35 (4~66) winsize 63
3931 11:03:18.628378 [CA 4] Center 34 (3~65) winsize 63
3932 11:03:18.631843 [CA 5] Center 33 (3~64) winsize 62
3933 11:03:18.631936
3934 11:03:18.635219 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3935 11:03:18.635311
3936 11:03:18.638685 [CATrainingPosCal] consider 2 rank data
3937 11:03:18.641660 u2DelayCellTimex100 = 270/100 ps
3938 11:03:18.648051 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3939 11:03:18.651809 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3940 11:03:18.655131 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3941 11:03:18.658391 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3942 11:03:18.661459 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3943 11:03:18.664711 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 11:03:18.664786
3945 11:03:18.668340 CA PerBit enable=1, Macro0, CA PI delay=33
3946 11:03:18.668415
3947 11:03:18.671680 [CBTSetCACLKResult] CA Dly = 33
3948 11:03:18.674693 CS Dly: 4 (0~36)
3949 11:03:18.674770
3950 11:03:18.677550 ----->DramcWriteLeveling(PI) begin...
3951 11:03:18.677628 ==
3952 11:03:18.681379 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 11:03:18.684722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 11:03:18.684832 ==
3955 11:03:18.687988 Write leveling (Byte 0): 35 => 35
3956 11:03:18.691097 Write leveling (Byte 1): 30 => 30
3957 11:03:18.694348 DramcWriteLeveling(PI) end<-----
3958 11:03:18.694440
3959 11:03:18.694524 ==
3960 11:03:18.697912 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 11:03:18.700850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 11:03:18.700957 ==
3963 11:03:18.704378 [Gating] SW mode calibration
3964 11:03:18.710582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3965 11:03:18.717366 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3966 11:03:18.720631 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 11:03:18.727606 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 11:03:18.731069 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 11:03:18.734462 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
3970 11:03:18.737096 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
3971 11:03:18.744049 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 11:03:18.747057 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 11:03:18.750297 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 11:03:18.757348 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 11:03:18.760252 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 11:03:18.763478 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 11:03:18.770467 0 10 12 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (0 0)
3978 11:03:18.773452 0 10 16 | B1->B0 | 3a3a 4545 | 0 1 | (0 0) (0 0)
3979 11:03:18.776673 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 11:03:18.783579 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 11:03:18.786993 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 11:03:18.790057 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 11:03:18.796968 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 11:03:18.800502 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 11:03:18.803501 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3986 11:03:18.810503 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3987 11:03:18.813542 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 11:03:18.817309 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 11:03:18.823340 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 11:03:18.826650 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 11:03:18.830194 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:03:18.836213 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:03:18.839685 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:03:18.843016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:03:18.849693 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:03:18.852797 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:03:18.856553 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:03:18.862803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:03:18.866195 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:03:18.869721 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:03:18.875838 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4002 11:03:18.880162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 11:03:18.882954 Total UI for P1: 0, mck2ui 16
4004 11:03:18.886280 best dqsien dly found for B0: ( 0, 13, 12)
4005 11:03:18.889552 Total UI for P1: 0, mck2ui 16
4006 11:03:18.892383 best dqsien dly found for B1: ( 0, 13, 14)
4007 11:03:18.896174 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4008 11:03:18.899273 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4009 11:03:18.899349
4010 11:03:18.902394 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4011 11:03:18.908806 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4012 11:03:18.908909 [Gating] SW calibration Done
4013 11:03:18.908997 ==
4014 11:03:18.912387 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 11:03:18.918793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 11:03:18.918893 ==
4017 11:03:18.919032 RX Vref Scan: 0
4018 11:03:18.919124
4019 11:03:18.922091 RX Vref 0 -> 0, step: 1
4020 11:03:18.922157
4021 11:03:18.925602 RX Delay -230 -> 252, step: 16
4022 11:03:18.928877 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4023 11:03:18.932143 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4024 11:03:18.938791 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4025 11:03:18.941956 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4026 11:03:18.945112 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4027 11:03:18.948285 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4028 11:03:18.951891 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4029 11:03:18.958632 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4030 11:03:18.961975 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4031 11:03:18.964983 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4032 11:03:18.968393 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4033 11:03:18.975033 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4034 11:03:18.978237 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4035 11:03:18.981793 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4036 11:03:18.985247 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4037 11:03:18.991354 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4038 11:03:18.991475 ==
4039 11:03:18.994847 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 11:03:18.998186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 11:03:18.998273 ==
4042 11:03:18.998333 DQS Delay:
4043 11:03:19.001270 DQS0 = 0, DQS1 = 0
4044 11:03:19.001346 DQM Delay:
4045 11:03:19.004850 DQM0 = 43, DQM1 = 34
4046 11:03:19.004926 DQ Delay:
4047 11:03:19.008642 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4048 11:03:19.011730 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4049 11:03:19.014689 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4050 11:03:19.017924 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4051 11:03:19.018037
4052 11:03:19.018096
4053 11:03:19.018150 ==
4054 11:03:19.020999 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 11:03:19.024804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 11:03:19.028097 ==
4057 11:03:19.028234
4058 11:03:19.028298
4059 11:03:19.028357 TX Vref Scan disable
4060 11:03:19.031143 == TX Byte 0 ==
4061 11:03:19.035223 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4062 11:03:19.037576 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4063 11:03:19.041071 == TX Byte 1 ==
4064 11:03:19.044471 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4065 11:03:19.047849 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4066 11:03:19.051143 ==
4067 11:03:19.054304 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 11:03:19.057639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 11:03:19.057830 ==
4070 11:03:19.057933
4071 11:03:19.058023
4072 11:03:19.060979 TX Vref Scan disable
4073 11:03:19.064028 == TX Byte 0 ==
4074 11:03:19.067270 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4075 11:03:19.070748 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4076 11:03:19.073984 == TX Byte 1 ==
4077 11:03:19.077397 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4078 11:03:19.080826 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4079 11:03:19.080987
4080 11:03:19.081111 [DATLAT]
4081 11:03:19.083728 Freq=600, CH0 RK0
4082 11:03:19.083889
4083 11:03:19.087307 DATLAT Default: 0x9
4084 11:03:19.087470 0, 0xFFFF, sum = 0
4085 11:03:19.090510 1, 0xFFFF, sum = 0
4086 11:03:19.090647 2, 0xFFFF, sum = 0
4087 11:03:19.093516 3, 0xFFFF, sum = 0
4088 11:03:19.093594 4, 0xFFFF, sum = 0
4089 11:03:19.097064 5, 0xFFFF, sum = 0
4090 11:03:19.097163 6, 0xFFFF, sum = 0
4091 11:03:19.100379 7, 0xFFFF, sum = 0
4092 11:03:19.100457 8, 0x0, sum = 1
4093 11:03:19.103505 9, 0x0, sum = 2
4094 11:03:19.103583 10, 0x0, sum = 3
4095 11:03:19.107436 11, 0x0, sum = 4
4096 11:03:19.107512 best_step = 9
4097 11:03:19.107569
4098 11:03:19.107623 ==
4099 11:03:19.110459 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 11:03:19.113574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 11:03:19.113656 ==
4102 11:03:19.117367 RX Vref Scan: 1
4103 11:03:19.117442
4104 11:03:19.120544 RX Vref 0 -> 0, step: 1
4105 11:03:19.120620
4106 11:03:19.120679 RX Delay -195 -> 252, step: 8
4107 11:03:19.120735
4108 11:03:19.123360 Set Vref, RX VrefLevel [Byte0]: 53
4109 11:03:19.126502 [Byte1]: 59
4110 11:03:19.131766
4111 11:03:19.131844 Final RX Vref Byte 0 = 53 to rank0
4112 11:03:19.135162 Final RX Vref Byte 1 = 59 to rank0
4113 11:03:19.138526 Final RX Vref Byte 0 = 53 to rank1
4114 11:03:19.141437 Final RX Vref Byte 1 = 59 to rank1==
4115 11:03:19.144849 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 11:03:19.151591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 11:03:19.151689 ==
4118 11:03:19.151772 DQS Delay:
4119 11:03:19.151830 DQS0 = 0, DQS1 = 0
4120 11:03:19.154721 DQM Delay:
4121 11:03:19.154797 DQM0 = 42, DQM1 = 32
4122 11:03:19.158283 DQ Delay:
4123 11:03:19.161587 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4124 11:03:19.164842 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4125 11:03:19.167732 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =28
4126 11:03:19.171357 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4127 11:03:19.171436
4128 11:03:19.171514
4129 11:03:19.177913 [DQSOSCAuto] RK0, (LSB)MR18= 0x5148, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4130 11:03:19.181215 CH0 RK0: MR19=808, MR18=5148
4131 11:03:19.187573 CH0_RK0: MR19=0x808, MR18=0x5148, DQSOSC=394, MR23=63, INC=168, DEC=112
4132 11:03:19.187652
4133 11:03:19.191141 ----->DramcWriteLeveling(PI) begin...
4134 11:03:19.191221 ==
4135 11:03:19.194506 Dram Type= 6, Freq= 0, CH_0, rank 1
4136 11:03:19.197831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 11:03:19.197908 ==
4138 11:03:19.201052 Write leveling (Byte 0): 32 => 32
4139 11:03:19.203981 Write leveling (Byte 1): 29 => 29
4140 11:03:19.207482 DramcWriteLeveling(PI) end<-----
4141 11:03:19.207559
4142 11:03:19.207618 ==
4143 11:03:19.210542 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 11:03:19.214214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 11:03:19.217294 ==
4146 11:03:19.217370 [Gating] SW mode calibration
4147 11:03:19.227007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4148 11:03:19.230344 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4149 11:03:19.233905 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 11:03:19.240446 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 11:03:19.243912 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4152 11:03:19.247270 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4153 11:03:19.253682 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
4154 11:03:19.256770 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 11:03:19.260679 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 11:03:19.266917 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 11:03:19.270155 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 11:03:19.273361 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 11:03:19.279842 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 11:03:19.283637 0 10 12 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
4161 11:03:19.286686 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
4162 11:03:19.293213 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 11:03:19.296355 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 11:03:19.299806 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 11:03:19.306559 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 11:03:19.309501 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 11:03:19.313323 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 11:03:19.319812 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 11:03:19.323564 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4170 11:03:19.326381 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 11:03:19.333109 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 11:03:19.336133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 11:03:19.339613 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 11:03:19.346384 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 11:03:19.349602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 11:03:19.352821 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 11:03:19.359392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 11:03:19.362739 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 11:03:19.366546 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 11:03:19.373210 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:03:19.376445 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:03:19.379206 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:03:19.386221 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4184 11:03:19.389347 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4185 11:03:19.392334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 11:03:19.395855 Total UI for P1: 0, mck2ui 16
4187 11:03:19.399041 best dqsien dly found for B0: ( 0, 13, 10)
4188 11:03:19.402392 Total UI for P1: 0, mck2ui 16
4189 11:03:19.405767 best dqsien dly found for B1: ( 0, 13, 14)
4190 11:03:19.409165 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4191 11:03:19.412404 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4192 11:03:19.412765
4193 11:03:19.418999 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4194 11:03:19.422290 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4195 11:03:19.425867 [Gating] SW calibration Done
4196 11:03:19.426311 ==
4197 11:03:19.429103 Dram Type= 6, Freq= 0, CH_0, rank 1
4198 11:03:19.432552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 11:03:19.433014 ==
4200 11:03:19.433394 RX Vref Scan: 0
4201 11:03:19.433663
4202 11:03:19.435590 RX Vref 0 -> 0, step: 1
4203 11:03:19.435959
4204 11:03:19.438735 RX Delay -230 -> 252, step: 16
4205 11:03:19.441959 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4206 11:03:19.445603 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4207 11:03:19.451942 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4208 11:03:19.455479 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4209 11:03:19.458750 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4210 11:03:19.462124 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4211 11:03:19.468505 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4212 11:03:19.471563 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4213 11:03:19.475372 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4214 11:03:19.478095 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4215 11:03:19.484906 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4216 11:03:19.488348 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4217 11:03:19.491428 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4218 11:03:19.494969 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4219 11:03:19.501217 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4220 11:03:19.504754 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4221 11:03:19.504839 ==
4222 11:03:19.507708 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 11:03:19.511329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 11:03:19.511405 ==
4225 11:03:19.514942 DQS Delay:
4226 11:03:19.515019 DQS0 = 0, DQS1 = 0
4227 11:03:19.515078 DQM Delay:
4228 11:03:19.518279 DQM0 = 41, DQM1 = 36
4229 11:03:19.518355 DQ Delay:
4230 11:03:19.521397 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4231 11:03:19.524794 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =57
4232 11:03:19.527687 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4233 11:03:19.530992 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4234 11:03:19.531068
4235 11:03:19.531126
4236 11:03:19.531181 ==
4237 11:03:19.534296 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 11:03:19.540610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 11:03:19.540723 ==
4240 11:03:19.540818
4241 11:03:19.540909
4242 11:03:19.540998 TX Vref Scan disable
4243 11:03:19.544486 == TX Byte 0 ==
4244 11:03:19.548425 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4245 11:03:19.554386 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4246 11:03:19.554494 == TX Byte 1 ==
4247 11:03:19.557530 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4248 11:03:19.564972 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4249 11:03:19.565081 ==
4250 11:03:19.567340 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 11:03:19.570700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 11:03:19.570837 ==
4253 11:03:19.570923
4254 11:03:19.570998
4255 11:03:19.574009 TX Vref Scan disable
4256 11:03:19.577268 == TX Byte 0 ==
4257 11:03:19.580458 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4258 11:03:19.583769 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4259 11:03:19.587285 == TX Byte 1 ==
4260 11:03:19.590590 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4261 11:03:19.593618 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4262 11:03:19.593696
4263 11:03:19.597143 [DATLAT]
4264 11:03:19.597219 Freq=600, CH0 RK1
4265 11:03:19.597280
4266 11:03:19.600632 DATLAT Default: 0x9
4267 11:03:19.600709 0, 0xFFFF, sum = 0
4268 11:03:19.604029 1, 0xFFFF, sum = 0
4269 11:03:19.604107 2, 0xFFFF, sum = 0
4270 11:03:19.606942 3, 0xFFFF, sum = 0
4271 11:03:19.607048 4, 0xFFFF, sum = 0
4272 11:03:19.610791 5, 0xFFFF, sum = 0
4273 11:03:19.610881 6, 0xFFFF, sum = 0
4274 11:03:19.613571 7, 0xFFFF, sum = 0
4275 11:03:19.613661 8, 0x0, sum = 1
4276 11:03:19.616700 9, 0x0, sum = 2
4277 11:03:19.616818 10, 0x0, sum = 3
4278 11:03:19.620587 11, 0x0, sum = 4
4279 11:03:19.620693 best_step = 9
4280 11:03:19.620774
4281 11:03:19.620850 ==
4282 11:03:19.623658 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 11:03:19.627028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 11:03:19.630214 ==
4285 11:03:19.630344 RX Vref Scan: 0
4286 11:03:19.630446
4287 11:03:19.633300 RX Vref 0 -> 0, step: 1
4288 11:03:19.633430
4289 11:03:19.636689 RX Delay -179 -> 252, step: 8
4290 11:03:19.640213 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4291 11:03:19.643307 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4292 11:03:19.649950 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4293 11:03:19.653169 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4294 11:03:19.656823 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4295 11:03:19.659757 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4296 11:03:19.666667 iDelay=197, Bit 6, Center 44 (-107 ~ 196) 304
4297 11:03:19.669682 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4298 11:03:19.673082 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4299 11:03:19.676412 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4300 11:03:19.680141 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4301 11:03:19.686319 iDelay=197, Bit 11, Center 24 (-131 ~ 180) 312
4302 11:03:19.689575 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4303 11:03:19.692654 iDelay=197, Bit 13, Center 36 (-123 ~ 196) 320
4304 11:03:19.696352 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4305 11:03:19.702451 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4306 11:03:19.702549 ==
4307 11:03:19.706108 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 11:03:19.709073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 11:03:19.709215 ==
4310 11:03:19.709300 DQS Delay:
4311 11:03:19.712357 DQS0 = 0, DQS1 = 0
4312 11:03:19.712434 DQM Delay:
4313 11:03:19.715923 DQM0 = 40, DQM1 = 32
4314 11:03:19.716004 DQ Delay:
4315 11:03:19.719300 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4316 11:03:19.722697 DQ4 =44, DQ5 =28, DQ6 =44, DQ7 =48
4317 11:03:19.725779 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4318 11:03:19.728969 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4319 11:03:19.729047
4320 11:03:19.729106
4321 11:03:19.738935 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4322 11:03:19.739021 CH0 RK1: MR19=808, MR18=4A45
4323 11:03:19.745710 CH0_RK1: MR19=0x808, MR18=0x4A45, DQSOSC=395, MR23=63, INC=168, DEC=112
4324 11:03:19.749177 [RxdqsGatingPostProcess] freq 600
4325 11:03:19.755453 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4326 11:03:19.758849 Pre-setting of DQS Precalculation
4327 11:03:19.762184 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4328 11:03:19.762264 ==
4329 11:03:19.765572 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 11:03:19.772075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 11:03:19.772174 ==
4332 11:03:19.775760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4333 11:03:19.781979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4334 11:03:19.785080 [CA 0] Center 36 (6~66) winsize 61
4335 11:03:19.788354 [CA 1] Center 35 (5~66) winsize 62
4336 11:03:19.791578 [CA 2] Center 34 (4~65) winsize 62
4337 11:03:19.795491 [CA 3] Center 34 (3~65) winsize 63
4338 11:03:19.798308 [CA 4] Center 34 (4~65) winsize 62
4339 11:03:19.801746 [CA 5] Center 33 (3~64) winsize 62
4340 11:03:19.801840
4341 11:03:19.805187 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4342 11:03:19.805264
4343 11:03:19.808663 [CATrainingPosCal] consider 1 rank data
4344 11:03:19.811708 u2DelayCellTimex100 = 270/100 ps
4345 11:03:19.815131 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4346 11:03:19.818179 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4347 11:03:19.825017 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4348 11:03:19.828032 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4349 11:03:19.831500 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4350 11:03:19.834562 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4351 11:03:19.834656
4352 11:03:19.838315 CA PerBit enable=1, Macro0, CA PI delay=33
4353 11:03:19.838417
4354 11:03:19.841309 [CBTSetCACLKResult] CA Dly = 33
4355 11:03:19.841422 CS Dly: 5 (0~36)
4356 11:03:19.844751 ==
4357 11:03:19.848090 Dram Type= 6, Freq= 0, CH_1, rank 1
4358 11:03:19.851453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 11:03:19.851595 ==
4360 11:03:19.854583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4361 11:03:19.861032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4362 11:03:19.865228 [CA 0] Center 35 (5~66) winsize 62
4363 11:03:19.868779 [CA 1] Center 36 (6~66) winsize 61
4364 11:03:19.871811 [CA 2] Center 34 (4~65) winsize 62
4365 11:03:19.875490 [CA 3] Center 34 (3~65) winsize 63
4366 11:03:19.878387 [CA 4] Center 34 (4~65) winsize 62
4367 11:03:19.881775 [CA 5] Center 34 (3~65) winsize 63
4368 11:03:19.882131
4369 11:03:19.885219 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4370 11:03:19.885579
4371 11:03:19.888521 [CATrainingPosCal] consider 2 rank data
4372 11:03:19.891876 u2DelayCellTimex100 = 270/100 ps
4373 11:03:19.895572 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4374 11:03:19.901839 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4375 11:03:19.904894 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 11:03:19.908494 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4377 11:03:19.911874 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4378 11:03:19.914661 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 11:03:19.915019
4380 11:03:19.918373 CA PerBit enable=1, Macro0, CA PI delay=33
4381 11:03:19.918730
4382 11:03:19.921711 [CBTSetCACLKResult] CA Dly = 33
4383 11:03:19.924649 CS Dly: 5 (0~36)
4384 11:03:19.925004
4385 11:03:19.927939 ----->DramcWriteLeveling(PI) begin...
4386 11:03:19.928304 ==
4387 11:03:19.931408 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 11:03:19.934683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 11:03:19.935046 ==
4390 11:03:19.938160 Write leveling (Byte 0): 28 => 28
4391 11:03:19.941543 Write leveling (Byte 1): 28 => 28
4392 11:03:19.944602 DramcWriteLeveling(PI) end<-----
4393 11:03:19.944960
4394 11:03:19.945288 ==
4395 11:03:19.947986 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:03:19.951197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:03:19.951758 ==
4398 11:03:19.954174 [Gating] SW mode calibration
4399 11:03:19.960995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4400 11:03:19.968023 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4401 11:03:19.971062 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 11:03:19.974314 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 11:03:19.981161 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4404 11:03:19.984205 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 0)
4405 11:03:19.987613 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 11:03:19.994094 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 11:03:19.997226 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 11:03:20.001221 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 11:03:20.007294 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 11:03:20.010543 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 11:03:20.013904 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4412 11:03:20.020555 0 10 12 | B1->B0 | 3a3a 3a3a | 0 0 | (0 0) (0 0)
4413 11:03:20.023919 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 11:03:20.027322 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 11:03:20.033637 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 11:03:20.036924 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 11:03:20.040793 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 11:03:20.047040 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 11:03:20.049836 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 11:03:20.053237 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4421 11:03:20.059969 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:03:20.063436 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:03:20.066490 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:03:20.072935 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 11:03:20.076784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 11:03:20.080107 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 11:03:20.086804 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 11:03:20.090090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 11:03:20.093069 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:03:20.100022 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:03:20.103183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:03:20.106245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:03:20.113184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:03:20.116628 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:03:20.119759 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:03:20.126154 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4437 11:03:20.129268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 11:03:20.132512 Total UI for P1: 0, mck2ui 16
4439 11:03:20.135994 best dqsien dly found for B0: ( 0, 13, 12)
4440 11:03:20.139411 Total UI for P1: 0, mck2ui 16
4441 11:03:20.142736 best dqsien dly found for B1: ( 0, 13, 12)
4442 11:03:20.145983 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4443 11:03:20.149590 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4444 11:03:20.149979
4445 11:03:20.152606 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4446 11:03:20.156071 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4447 11:03:20.159259 [Gating] SW calibration Done
4448 11:03:20.159647 ==
4449 11:03:20.162334 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 11:03:20.169339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 11:03:20.169731 ==
4452 11:03:20.170034 RX Vref Scan: 0
4453 11:03:20.170317
4454 11:03:20.172655 RX Vref 0 -> 0, step: 1
4455 11:03:20.173120
4456 11:03:20.176228 RX Delay -230 -> 252, step: 16
4457 11:03:20.179370 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4458 11:03:20.182130 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4459 11:03:20.185718 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4460 11:03:20.192731 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4461 11:03:20.195440 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4462 11:03:20.198738 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4463 11:03:20.201927 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4464 11:03:20.208733 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4465 11:03:20.211855 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4466 11:03:20.215438 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4467 11:03:20.218770 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4468 11:03:20.221987 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4469 11:03:20.228607 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4470 11:03:20.232032 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4471 11:03:20.235783 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4472 11:03:20.241728 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4473 11:03:20.242118 ==
4474 11:03:20.245219 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 11:03:20.248432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 11:03:20.248826 ==
4477 11:03:20.249129 DQS Delay:
4478 11:03:20.251399 DQS0 = 0, DQS1 = 0
4479 11:03:20.251790 DQM Delay:
4480 11:03:20.255380 DQM0 = 46, DQM1 = 38
4481 11:03:20.255768 DQ Delay:
4482 11:03:20.258003 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4483 11:03:20.261825 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4484 11:03:20.264566 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4485 11:03:20.267884 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4486 11:03:20.268274
4487 11:03:20.268570
4488 11:03:20.268852 ==
4489 11:03:20.271413 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 11:03:20.275013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 11:03:20.275408 ==
4492 11:03:20.275710
4493 11:03:20.278141
4494 11:03:20.278531 TX Vref Scan disable
4495 11:03:20.281393 == TX Byte 0 ==
4496 11:03:20.284595 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4497 11:03:20.288167 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4498 11:03:20.291308 == TX Byte 1 ==
4499 11:03:20.294677 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4500 11:03:20.297627 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4501 11:03:20.301194 ==
4502 11:03:20.301578 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 11:03:20.307747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 11:03:20.308133 ==
4505 11:03:20.308433
4506 11:03:20.308702
4507 11:03:20.310643 TX Vref Scan disable
4508 11:03:20.311025 == TX Byte 0 ==
4509 11:03:20.317300 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4510 11:03:20.321257 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4511 11:03:20.321644 == TX Byte 1 ==
4512 11:03:20.327334 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4513 11:03:20.330658 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4514 11:03:20.331081
4515 11:03:20.331381 [DATLAT]
4516 11:03:20.334071 Freq=600, CH1 RK0
4517 11:03:20.334453
4518 11:03:20.334753 DATLAT Default: 0x9
4519 11:03:20.337677 0, 0xFFFF, sum = 0
4520 11:03:20.338117 1, 0xFFFF, sum = 0
4521 11:03:20.340935 2, 0xFFFF, sum = 0
4522 11:03:20.341361 3, 0xFFFF, sum = 0
4523 11:03:20.343712 4, 0xFFFF, sum = 0
4524 11:03:20.347201 5, 0xFFFF, sum = 0
4525 11:03:20.347598 6, 0xFFFF, sum = 0
4526 11:03:20.350390 7, 0xFFFF, sum = 0
4527 11:03:20.350819 8, 0x0, sum = 1
4528 11:03:20.351141 9, 0x0, sum = 2
4529 11:03:20.353941 10, 0x0, sum = 3
4530 11:03:20.354341 11, 0x0, sum = 4
4531 11:03:20.357314 best_step = 9
4532 11:03:20.357825
4533 11:03:20.358300 ==
4534 11:03:20.360992 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 11:03:20.363820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 11:03:20.364207 ==
4537 11:03:20.367697 RX Vref Scan: 1
4538 11:03:20.368077
4539 11:03:20.368375 RX Vref 0 -> 0, step: 1
4540 11:03:20.368761
4541 11:03:20.371058 RX Delay -179 -> 252, step: 8
4542 11:03:20.371479
4543 11:03:20.373777 Set Vref, RX VrefLevel [Byte0]: 52
4544 11:03:20.376765 [Byte1]: 52
4545 11:03:20.381600
4546 11:03:20.382118 Final RX Vref Byte 0 = 52 to rank0
4547 11:03:20.384353 Final RX Vref Byte 1 = 52 to rank0
4548 11:03:20.387691 Final RX Vref Byte 0 = 52 to rank1
4549 11:03:20.391260 Final RX Vref Byte 1 = 52 to rank1==
4550 11:03:20.394546 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 11:03:20.400941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 11:03:20.401419 ==
4553 11:03:20.401919 DQS Delay:
4554 11:03:20.403934 DQS0 = 0, DQS1 = 0
4555 11:03:20.404337 DQM Delay:
4556 11:03:20.404635 DQM0 = 44, DQM1 = 36
4557 11:03:20.407767 DQ Delay:
4558 11:03:20.410898 DQ0 =52, DQ1 =44, DQ2 =32, DQ3 =44
4559 11:03:20.414121 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =36
4560 11:03:20.417438 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4561 11:03:20.420780 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4562 11:03:20.421185
4563 11:03:20.421493
4564 11:03:20.427569 [DQSOSCAuto] RK0, (LSB)MR18= 0x354f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4565 11:03:20.430563 CH1 RK0: MR19=808, MR18=354F
4566 11:03:20.437470 CH1_RK0: MR19=0x808, MR18=0x354F, DQSOSC=394, MR23=63, INC=168, DEC=112
4567 11:03:20.437855
4568 11:03:20.440500 ----->DramcWriteLeveling(PI) begin...
4569 11:03:20.440899 ==
4570 11:03:20.444004 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 11:03:20.447197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 11:03:20.447591 ==
4573 11:03:20.450638 Write leveling (Byte 0): 29 => 29
4574 11:03:20.453711 Write leveling (Byte 1): 28 => 28
4575 11:03:20.457428 DramcWriteLeveling(PI) end<-----
4576 11:03:20.457819
4577 11:03:20.458122 ==
4578 11:03:20.460767 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 11:03:20.463767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 11:03:20.467206 ==
4581 11:03:20.467599 [Gating] SW mode calibration
4582 11:03:20.473601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4583 11:03:20.480241 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4584 11:03:20.483632 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 11:03:20.490347 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 11:03:20.493553 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4587 11:03:20.496898 0 9 12 | B1->B0 | 2f2f 2a2a | 0 1 | (0 0) (1 0)
4588 11:03:20.503381 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4589 11:03:20.506745 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 11:03:20.510188 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 11:03:20.516785 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 11:03:20.520364 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 11:03:20.523906 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 11:03:20.530473 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4595 11:03:20.533603 0 10 12 | B1->B0 | 3131 4040 | 0 0 | (0 0) (0 0)
4596 11:03:20.536443 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 11:03:20.543458 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 11:03:20.546242 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 11:03:20.549803 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 11:03:20.556557 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 11:03:20.559676 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 11:03:20.563210 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 11:03:20.569792 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4604 11:03:20.573134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 11:03:20.576487 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 11:03:20.582826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 11:03:20.586254 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 11:03:20.589492 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 11:03:20.595879 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 11:03:20.599540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 11:03:20.602545 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 11:03:20.609051 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 11:03:20.612251 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 11:03:20.615793 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:03:20.622614 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:03:20.625827 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:03:20.628897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:03:20.635547 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4619 11:03:20.638890 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 11:03:20.642370 Total UI for P1: 0, mck2ui 16
4621 11:03:20.645648 best dqsien dly found for B0: ( 0, 13, 8)
4622 11:03:20.649017 Total UI for P1: 0, mck2ui 16
4623 11:03:20.652517 best dqsien dly found for B1: ( 0, 13, 10)
4624 11:03:20.656046 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4625 11:03:20.658563 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4626 11:03:20.658955
4627 11:03:20.662040 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4628 11:03:20.665582 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4629 11:03:20.668473 [Gating] SW calibration Done
4630 11:03:20.668862 ==
4631 11:03:20.671868 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 11:03:20.674945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 11:03:20.675339 ==
4634 11:03:20.678555 RX Vref Scan: 0
4635 11:03:20.679058
4636 11:03:20.681909 RX Vref 0 -> 0, step: 1
4637 11:03:20.682403
4638 11:03:20.685246 RX Delay -230 -> 252, step: 16
4639 11:03:20.688624 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4640 11:03:20.691446 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4641 11:03:20.694683 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4642 11:03:20.701738 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4643 11:03:20.704698 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4644 11:03:20.708178 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4645 11:03:20.711942 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4646 11:03:20.714410 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4647 11:03:20.721269 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4648 11:03:20.724664 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4649 11:03:20.727838 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4650 11:03:20.730824 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4651 11:03:20.737915 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4652 11:03:20.740905 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4653 11:03:20.744046 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4654 11:03:20.747160 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4655 11:03:20.750791 ==
4656 11:03:20.754060 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 11:03:20.757253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 11:03:20.757665 ==
4659 11:03:20.758064 DQS Delay:
4660 11:03:20.760723 DQS0 = 0, DQS1 = 0
4661 11:03:20.761127 DQM Delay:
4662 11:03:20.763678 DQM0 = 46, DQM1 = 44
4663 11:03:20.764079 DQ Delay:
4664 11:03:20.767153 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4665 11:03:20.770350 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4666 11:03:20.773558 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4667 11:03:20.776794 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4668 11:03:20.777231
4669 11:03:20.777629
4670 11:03:20.777999 ==
4671 11:03:20.780658 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 11:03:20.783738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 11:03:20.784146 ==
4674 11:03:20.784542
4675 11:03:20.784912
4676 11:03:20.787139 TX Vref Scan disable
4677 11:03:20.790170 == TX Byte 0 ==
4678 11:03:20.793431 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4679 11:03:20.796998 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4680 11:03:20.800057 == TX Byte 1 ==
4681 11:03:20.803394 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4682 11:03:20.807435 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4683 11:03:20.807837 ==
4684 11:03:20.810345 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 11:03:20.816666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 11:03:20.817054 ==
4687 11:03:20.817403
4688 11:03:20.817678
4689 11:03:20.817943 TX Vref Scan disable
4690 11:03:20.821181 == TX Byte 0 ==
4691 11:03:20.824745 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4692 11:03:20.831049 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4693 11:03:20.831437 == TX Byte 1 ==
4694 11:03:20.834229 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4695 11:03:20.841201 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4696 11:03:20.841608
4697 11:03:20.842002 [DATLAT]
4698 11:03:20.842425 Freq=600, CH1 RK1
4699 11:03:20.842774
4700 11:03:20.844327 DATLAT Default: 0x9
4701 11:03:20.844729 0, 0xFFFF, sum = 0
4702 11:03:20.847623 1, 0xFFFF, sum = 0
4703 11:03:20.851046 2, 0xFFFF, sum = 0
4704 11:03:20.851454 3, 0xFFFF, sum = 0
4705 11:03:20.854383 4, 0xFFFF, sum = 0
4706 11:03:20.854796 5, 0xFFFF, sum = 0
4707 11:03:20.857329 6, 0xFFFF, sum = 0
4708 11:03:20.857875 7, 0xFFFF, sum = 0
4709 11:03:20.860892 8, 0x0, sum = 1
4710 11:03:20.861424 9, 0x0, sum = 2
4711 11:03:20.861884 10, 0x0, sum = 3
4712 11:03:20.864300 11, 0x0, sum = 4
4713 11:03:20.864804 best_step = 9
4714 11:03:20.865312
4715 11:03:20.865763 ==
4716 11:03:20.867779 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 11:03:20.874069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 11:03:20.874617 ==
4719 11:03:20.875087 RX Vref Scan: 0
4720 11:03:20.875509
4721 11:03:20.877078 RX Vref 0 -> 0, step: 1
4722 11:03:20.877650
4723 11:03:20.880769 RX Delay -179 -> 252, step: 8
4724 11:03:20.887126 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4725 11:03:20.890346 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4726 11:03:20.893757 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4727 11:03:20.896785 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4728 11:03:20.900373 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4729 11:03:20.906969 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4730 11:03:20.909986 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4731 11:03:20.913205 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4732 11:03:20.917242 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4733 11:03:20.923512 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4734 11:03:20.926684 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4735 11:03:20.930247 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4736 11:03:20.933456 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4737 11:03:20.939836 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4738 11:03:20.943122 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4739 11:03:20.946730 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4740 11:03:20.947119 ==
4741 11:03:20.949733 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 11:03:20.953088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 11:03:20.956404 ==
4744 11:03:20.956923 DQS Delay:
4745 11:03:20.957436 DQS0 = 0, DQS1 = 0
4746 11:03:20.959581 DQM Delay:
4747 11:03:20.960100 DQM0 = 40, DQM1 = 38
4748 11:03:20.963136 DQ Delay:
4749 11:03:20.963652 DQ0 =44, DQ1 =36, DQ2 =32, DQ3 =40
4750 11:03:20.966558 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4751 11:03:20.969809 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4752 11:03:20.972980 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4753 11:03:20.973526
4754 11:03:20.976299
4755 11:03:20.982704 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f63, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
4756 11:03:20.986078 CH1 RK1: MR19=808, MR18=3F63
4757 11:03:20.992634 CH1_RK1: MR19=0x808, MR18=0x3F63, DQSOSC=391, MR23=63, INC=171, DEC=114
4758 11:03:20.996546 [RxdqsGatingPostProcess] freq 600
4759 11:03:20.999655 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4760 11:03:21.002420 Pre-setting of DQS Precalculation
4761 11:03:21.009182 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4762 11:03:21.015823 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4763 11:03:21.022574 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4764 11:03:21.022959
4765 11:03:21.023251
4766 11:03:21.025646 [Calibration Summary] 1200 Mbps
4767 11:03:21.026047 CH 0, Rank 0
4768 11:03:21.029286 SW Impedance : PASS
4769 11:03:21.032201 DUTY Scan : NO K
4770 11:03:21.032601 ZQ Calibration : PASS
4771 11:03:21.035772 Jitter Meter : NO K
4772 11:03:21.038987 CBT Training : PASS
4773 11:03:21.039396 Write leveling : PASS
4774 11:03:21.042107 RX DQS gating : PASS
4775 11:03:21.045634 RX DQ/DQS(RDDQC) : PASS
4776 11:03:21.046023 TX DQ/DQS : PASS
4777 11:03:21.048406 RX DATLAT : PASS
4778 11:03:21.051918 RX DQ/DQS(Engine): PASS
4779 11:03:21.052305 TX OE : NO K
4780 11:03:21.052612 All Pass.
4781 11:03:21.055304
4782 11:03:21.055762 CH 0, Rank 1
4783 11:03:21.059295 SW Impedance : PASS
4784 11:03:21.059732 DUTY Scan : NO K
4785 11:03:21.061815 ZQ Calibration : PASS
4786 11:03:21.065071 Jitter Meter : NO K
4787 11:03:21.065609 CBT Training : PASS
4788 11:03:21.068648 Write leveling : PASS
4789 11:03:21.069067 RX DQS gating : PASS
4790 11:03:21.071739 RX DQ/DQS(RDDQC) : PASS
4791 11:03:21.075250 TX DQ/DQS : PASS
4792 11:03:21.075636 RX DATLAT : PASS
4793 11:03:21.078449 RX DQ/DQS(Engine): PASS
4794 11:03:21.081429 TX OE : NO K
4795 11:03:21.081839 All Pass.
4796 11:03:21.082146
4797 11:03:21.082425 CH 1, Rank 0
4798 11:03:21.085052 SW Impedance : PASS
4799 11:03:21.088268 DUTY Scan : NO K
4800 11:03:21.088666 ZQ Calibration : PASS
4801 11:03:21.091277 Jitter Meter : NO K
4802 11:03:21.095056 CBT Training : PASS
4803 11:03:21.095439 Write leveling : PASS
4804 11:03:21.097981 RX DQS gating : PASS
4805 11:03:21.101110 RX DQ/DQS(RDDQC) : PASS
4806 11:03:21.101531 TX DQ/DQS : PASS
4807 11:03:21.104684 RX DATLAT : PASS
4808 11:03:21.108649 RX DQ/DQS(Engine): PASS
4809 11:03:21.109035 TX OE : NO K
4810 11:03:21.111748 All Pass.
4811 11:03:21.112214
4812 11:03:21.112651 CH 1, Rank 1
4813 11:03:21.114376 SW Impedance : PASS
4814 11:03:21.114760 DUTY Scan : NO K
4815 11:03:21.117840 ZQ Calibration : PASS
4816 11:03:21.121004 Jitter Meter : NO K
4817 11:03:21.121439 CBT Training : PASS
4818 11:03:21.124388 Write leveling : PASS
4819 11:03:21.127712 RX DQS gating : PASS
4820 11:03:21.128109 RX DQ/DQS(RDDQC) : PASS
4821 11:03:21.130699 TX DQ/DQS : PASS
4822 11:03:21.134298 RX DATLAT : PASS
4823 11:03:21.134683 RX DQ/DQS(Engine): PASS
4824 11:03:21.137635 TX OE : NO K
4825 11:03:21.138021 All Pass.
4826 11:03:21.138321
4827 11:03:21.140801 DramC Write-DBI off
4828 11:03:21.143755 PER_BANK_REFRESH: Hybrid Mode
4829 11:03:21.144148 TX_TRACKING: ON
4830 11:03:21.153943 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4831 11:03:21.157559 [FAST_K] Save calibration result to emmc
4832 11:03:21.160397 dramc_set_vcore_voltage set vcore to 662500
4833 11:03:21.163638 Read voltage for 933, 3
4834 11:03:21.164028 Vio18 = 0
4835 11:03:21.164327 Vcore = 662500
4836 11:03:21.167422 Vdram = 0
4837 11:03:21.167858 Vddq = 0
4838 11:03:21.168180 Vmddr = 0
4839 11:03:21.173704 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4840 11:03:21.177238 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4841 11:03:21.180467 MEM_TYPE=3, freq_sel=17
4842 11:03:21.183337 sv_algorithm_assistance_LP4_1600
4843 11:03:21.186582 ============ PULL DRAM RESETB DOWN ============
4844 11:03:21.189828 ========== PULL DRAM RESETB DOWN end =========
4845 11:03:21.196844 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4846 11:03:21.200268 ===================================
4847 11:03:21.203604 LPDDR4 DRAM CONFIGURATION
4848 11:03:21.206838 ===================================
4849 11:03:21.207227 EX_ROW_EN[0] = 0x0
4850 11:03:21.209699 EX_ROW_EN[1] = 0x0
4851 11:03:21.210090 LP4Y_EN = 0x0
4852 11:03:21.213308 WORK_FSP = 0x0
4853 11:03:21.213699 WL = 0x3
4854 11:03:21.216331 RL = 0x3
4855 11:03:21.216719 BL = 0x2
4856 11:03:21.219401 RPST = 0x0
4857 11:03:21.219891 RD_PRE = 0x0
4858 11:03:21.223023 WR_PRE = 0x1
4859 11:03:21.226297 WR_PST = 0x0
4860 11:03:21.226809 DBI_WR = 0x0
4861 11:03:21.229400 DBI_RD = 0x0
4862 11:03:21.229943 OTF = 0x1
4863 11:03:21.232759 ===================================
4864 11:03:21.235994 ===================================
4865 11:03:21.239175 ANA top config
4866 11:03:21.239557 ===================================
4867 11:03:21.242490 DLL_ASYNC_EN = 0
4868 11:03:21.246122 ALL_SLAVE_EN = 1
4869 11:03:21.249531 NEW_RANK_MODE = 1
4870 11:03:21.252345 DLL_IDLE_MODE = 1
4871 11:03:21.252728 LP45_APHY_COMB_EN = 1
4872 11:03:21.255693 TX_ODT_DIS = 1
4873 11:03:21.258994 NEW_8X_MODE = 1
4874 11:03:21.262376 ===================================
4875 11:03:21.265752 ===================================
4876 11:03:21.269197 data_rate = 1866
4877 11:03:21.272436 CKR = 1
4878 11:03:21.275545 DQ_P2S_RATIO = 8
4879 11:03:21.279237 ===================================
4880 11:03:21.279626 CA_P2S_RATIO = 8
4881 11:03:21.282410 DQ_CA_OPEN = 0
4882 11:03:21.285798 DQ_SEMI_OPEN = 0
4883 11:03:21.289212 CA_SEMI_OPEN = 0
4884 11:03:21.292248 CA_FULL_RATE = 0
4885 11:03:21.295418 DQ_CKDIV4_EN = 1
4886 11:03:21.295805 CA_CKDIV4_EN = 1
4887 11:03:21.299119 CA_PREDIV_EN = 0
4888 11:03:21.302470 PH8_DLY = 0
4889 11:03:21.305623 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4890 11:03:21.308695 DQ_AAMCK_DIV = 4
4891 11:03:21.312139 CA_AAMCK_DIV = 4
4892 11:03:21.312531 CA_ADMCK_DIV = 4
4893 11:03:21.315339 DQ_TRACK_CA_EN = 0
4894 11:03:21.318546 CA_PICK = 933
4895 11:03:21.322036 CA_MCKIO = 933
4896 11:03:21.324970 MCKIO_SEMI = 0
4897 11:03:21.328168 PLL_FREQ = 3732
4898 11:03:21.331590 DQ_UI_PI_RATIO = 32
4899 11:03:21.332104 CA_UI_PI_RATIO = 0
4900 11:03:21.334899 ===================================
4901 11:03:21.338248 ===================================
4902 11:03:21.341780 memory_type:LPDDR4
4903 11:03:21.344909 GP_NUM : 10
4904 11:03:21.345345 SRAM_EN : 1
4905 11:03:21.348265 MD32_EN : 0
4906 11:03:21.351135 ===================================
4907 11:03:21.354704 [ANA_INIT] >>>>>>>>>>>>>>
4908 11:03:21.357915 <<<<<< [CONFIGURE PHASE]: ANA_TX
4909 11:03:21.361477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4910 11:03:21.364372 ===================================
4911 11:03:21.367666 data_rate = 1866,PCW = 0X8f00
4912 11:03:21.371350 ===================================
4913 11:03:21.374227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4914 11:03:21.377863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 11:03:21.384535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 11:03:21.387337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4917 11:03:21.391168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4918 11:03:21.393820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4919 11:03:21.397555 [ANA_INIT] flow start
4920 11:03:21.400548 [ANA_INIT] PLL >>>>>>>>
4921 11:03:21.400932 [ANA_INIT] PLL <<<<<<<<
4922 11:03:21.403799 [ANA_INIT] MIDPI >>>>>>>>
4923 11:03:21.407306 [ANA_INIT] MIDPI <<<<<<<<
4924 11:03:21.410788 [ANA_INIT] DLL >>>>>>>>
4925 11:03:21.411173 [ANA_INIT] flow end
4926 11:03:21.413741 ============ LP4 DIFF to SE enter ============
4927 11:03:21.420618 ============ LP4 DIFF to SE exit ============
4928 11:03:21.421008 [ANA_INIT] <<<<<<<<<<<<<
4929 11:03:21.423548 [Flow] Enable top DCM control >>>>>
4930 11:03:21.426828 [Flow] Enable top DCM control <<<<<
4931 11:03:21.430519 Enable DLL master slave shuffle
4932 11:03:21.437249 ==============================================================
4933 11:03:21.437721 Gating Mode config
4934 11:03:21.443704 ==============================================================
4935 11:03:21.447150 Config description:
4936 11:03:21.456625 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4937 11:03:21.463417 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4938 11:03:21.466913 SELPH_MODE 0: By rank 1: By Phase
4939 11:03:21.473120 ==============================================================
4940 11:03:21.476773 GAT_TRACK_EN = 1
4941 11:03:21.479667 RX_GATING_MODE = 2
4942 11:03:21.480055 RX_GATING_TRACK_MODE = 2
4943 11:03:21.483386 SELPH_MODE = 1
4944 11:03:21.486243 PICG_EARLY_EN = 1
4945 11:03:21.489645 VALID_LAT_VALUE = 1
4946 11:03:21.496307 ==============================================================
4947 11:03:21.499873 Enter into Gating configuration >>>>
4948 11:03:21.502982 Exit from Gating configuration <<<<
4949 11:03:21.506451 Enter into DVFS_PRE_config >>>>>
4950 11:03:21.515999 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4951 11:03:21.518980 Exit from DVFS_PRE_config <<<<<
4952 11:03:21.522599 Enter into PICG configuration >>>>
4953 11:03:21.525877 Exit from PICG configuration <<<<
4954 11:03:21.528916 [RX_INPUT] configuration >>>>>
4955 11:03:21.532564 [RX_INPUT] configuration <<<<<
4956 11:03:21.536206 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4957 11:03:21.542324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4958 11:03:21.548853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4959 11:03:21.555354 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4960 11:03:21.562223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4961 11:03:21.568432 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4962 11:03:21.571922 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4963 11:03:21.575332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4964 11:03:21.578506 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4965 11:03:21.584745 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4966 11:03:21.588138 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4967 11:03:21.591669 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4968 11:03:21.594563 ===================================
4969 11:03:21.597897 LPDDR4 DRAM CONFIGURATION
4970 11:03:21.601637 ===================================
4971 11:03:21.601745 EX_ROW_EN[0] = 0x0
4972 11:03:21.605115 EX_ROW_EN[1] = 0x0
4973 11:03:21.607913 LP4Y_EN = 0x0
4974 11:03:21.608008 WORK_FSP = 0x0
4975 11:03:21.611098 WL = 0x3
4976 11:03:21.611183 RL = 0x3
4977 11:03:21.614516 BL = 0x2
4978 11:03:21.614604 RPST = 0x0
4979 11:03:21.617771 RD_PRE = 0x0
4980 11:03:21.617850 WR_PRE = 0x1
4981 11:03:21.621265 WR_PST = 0x0
4982 11:03:21.621341 DBI_WR = 0x0
4983 11:03:21.624012 DBI_RD = 0x0
4984 11:03:21.624088 OTF = 0x1
4985 11:03:21.627299 ===================================
4986 11:03:21.630794 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4987 11:03:21.637782 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4988 11:03:21.640832 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 11:03:21.644267 ===================================
4990 11:03:21.647764 LPDDR4 DRAM CONFIGURATION
4991 11:03:21.650726 ===================================
4992 11:03:21.650830 EX_ROW_EN[0] = 0x10
4993 11:03:21.654306 EX_ROW_EN[1] = 0x0
4994 11:03:21.657091 LP4Y_EN = 0x0
4995 11:03:21.657189 WORK_FSP = 0x0
4996 11:03:21.660382 WL = 0x3
4997 11:03:21.660510 RL = 0x3
4998 11:03:21.663770 BL = 0x2
4999 11:03:21.663885 RPST = 0x0
5000 11:03:21.666945 RD_PRE = 0x0
5001 11:03:21.667070 WR_PRE = 0x1
5002 11:03:21.670440 WR_PST = 0x0
5003 11:03:21.670575 DBI_WR = 0x0
5004 11:03:21.673702 DBI_RD = 0x0
5005 11:03:21.673841 OTF = 0x1
5006 11:03:21.677155 ===================================
5007 11:03:21.683489 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5008 11:03:21.688534 nWR fixed to 30
5009 11:03:21.691528 [ModeRegInit_LP4] CH0 RK0
5010 11:03:21.691758 [ModeRegInit_LP4] CH0 RK1
5011 11:03:21.694824 [ModeRegInit_LP4] CH1 RK0
5012 11:03:21.698420 [ModeRegInit_LP4] CH1 RK1
5013 11:03:21.698707 match AC timing 9
5014 11:03:21.704826 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5015 11:03:21.708222 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5016 11:03:21.711673 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5017 11:03:21.718131 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5018 11:03:21.721416 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5019 11:03:21.721929 ==
5020 11:03:21.725014 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 11:03:21.728053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5022 11:03:21.728558 ==
5023 11:03:21.734498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5024 11:03:21.741232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5025 11:03:21.744424 [CA 0] Center 37 (7~68) winsize 62
5026 11:03:21.748528 [CA 1] Center 37 (7~68) winsize 62
5027 11:03:21.751143 [CA 2] Center 34 (4~65) winsize 62
5028 11:03:21.754243 [CA 3] Center 34 (4~65) winsize 62
5029 11:03:21.757452 [CA 4] Center 33 (3~63) winsize 61
5030 11:03:21.761041 [CA 5] Center 32 (2~63) winsize 62
5031 11:03:21.761478
5032 11:03:21.764367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5033 11:03:21.764757
5034 11:03:21.767640 [CATrainingPosCal] consider 1 rank data
5035 11:03:21.770582 u2DelayCellTimex100 = 270/100 ps
5036 11:03:21.773838 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5037 11:03:21.777409 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5038 11:03:21.780645 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5039 11:03:21.787354 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5040 11:03:21.790653 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5041 11:03:21.793787 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5042 11:03:21.794182
5043 11:03:21.797314 CA PerBit enable=1, Macro0, CA PI delay=32
5044 11:03:21.797868
5045 11:03:21.800688 [CBTSetCACLKResult] CA Dly = 32
5046 11:03:21.801265 CS Dly: 6 (0~37)
5047 11:03:21.801766 ==
5048 11:03:21.803546 Dram Type= 6, Freq= 0, CH_0, rank 1
5049 11:03:21.810206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 11:03:21.810751 ==
5051 11:03:21.813905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 11:03:21.820612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5053 11:03:21.824086 [CA 0] Center 37 (7~68) winsize 62
5054 11:03:21.827129 [CA 1] Center 37 (7~68) winsize 62
5055 11:03:21.830141 [CA 2] Center 34 (4~65) winsize 62
5056 11:03:21.833672 [CA 3] Center 34 (4~65) winsize 62
5057 11:03:21.836824 [CA 4] Center 33 (3~64) winsize 62
5058 11:03:21.840137 [CA 5] Center 32 (2~63) winsize 62
5059 11:03:21.840591
5060 11:03:21.843390 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5061 11:03:21.843969
5062 11:03:21.846910 [CATrainingPosCal] consider 2 rank data
5063 11:03:21.850349 u2DelayCellTimex100 = 270/100 ps
5064 11:03:21.853275 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 11:03:21.860053 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5066 11:03:21.863403 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5067 11:03:21.867015 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5068 11:03:21.870244 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5069 11:03:21.873669 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5070 11:03:21.874062
5071 11:03:21.876703 CA PerBit enable=1, Macro0, CA PI delay=32
5072 11:03:21.877282
5073 11:03:21.879770 [CBTSetCACLKResult] CA Dly = 32
5074 11:03:21.883023 CS Dly: 7 (0~39)
5075 11:03:21.883411
5076 11:03:21.886653 ----->DramcWriteLeveling(PI) begin...
5077 11:03:21.887206 ==
5078 11:03:21.889907 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 11:03:21.893629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 11:03:21.894025 ==
5081 11:03:21.896820 Write leveling (Byte 0): 30 => 30
5082 11:03:21.899583 Write leveling (Byte 1): 29 => 29
5083 11:03:21.902987 DramcWriteLeveling(PI) end<-----
5084 11:03:21.903532
5085 11:03:21.904019 ==
5086 11:03:21.906540 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 11:03:21.909517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 11:03:21.909908 ==
5089 11:03:21.912936 [Gating] SW mode calibration
5090 11:03:21.919529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5091 11:03:21.926265 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5092 11:03:21.929230 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5093 11:03:21.932434 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 11:03:21.939364 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 11:03:21.942207 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 11:03:21.945629 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 11:03:21.952699 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 11:03:21.955522 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5099 11:03:21.958839 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
5100 11:03:21.965581 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5101 11:03:21.968919 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 11:03:21.972341 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 11:03:21.978739 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 11:03:21.981972 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 11:03:21.986254 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 11:03:21.992176 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5107 11:03:21.995389 0 15 28 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
5108 11:03:21.998993 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5109 11:03:22.005303 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 11:03:22.008922 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 11:03:22.012080 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 11:03:22.018739 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 11:03:22.022032 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 11:03:22.024945 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 11:03:22.031655 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5116 11:03:22.035168 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5117 11:03:22.038454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5118 11:03:22.044697 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:03:22.048432 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:03:22.051538 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 11:03:22.058029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 11:03:22.061450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 11:03:22.064589 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 11:03:22.071306 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 11:03:22.074607 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:03:22.077707 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:03:22.084324 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:03:22.087762 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:03:22.090939 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:03:22.097556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:03:22.100951 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 11:03:22.104044 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5133 11:03:22.107489 Total UI for P1: 0, mck2ui 16
5134 11:03:22.110817 best dqsien dly found for B0: ( 1, 2, 28)
5135 11:03:22.117234 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 11:03:22.117627 Total UI for P1: 0, mck2ui 16
5137 11:03:22.124219 best dqsien dly found for B1: ( 1, 3, 0)
5138 11:03:22.127374 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5139 11:03:22.130690 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5140 11:03:22.131080
5141 11:03:22.133948 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5142 11:03:22.136954 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5143 11:03:22.140510 [Gating] SW calibration Done
5144 11:03:22.140914 ==
5145 11:03:22.143736 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 11:03:22.147355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:03:22.147889 ==
5148 11:03:22.150358 RX Vref Scan: 0
5149 11:03:22.150743
5150 11:03:22.151072 RX Vref 0 -> 0, step: 1
5151 11:03:22.151349
5152 11:03:22.153954 RX Delay -80 -> 252, step: 8
5153 11:03:22.160601 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5154 11:03:22.163770 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5155 11:03:22.166896 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5156 11:03:22.170240 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5157 11:03:22.173286 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5158 11:03:22.176797 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5159 11:03:22.183522 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5160 11:03:22.186399 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5161 11:03:22.190507 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5162 11:03:22.193355 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5163 11:03:22.196557 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5164 11:03:22.199715 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5165 11:03:22.206438 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5166 11:03:22.210429 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5167 11:03:22.212977 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5168 11:03:22.216344 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5169 11:03:22.216735 ==
5170 11:03:22.219471 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 11:03:22.223125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 11:03:22.226048 ==
5173 11:03:22.226435 DQS Delay:
5174 11:03:22.226742 DQS0 = 0, DQS1 = 0
5175 11:03:22.229316 DQM Delay:
5176 11:03:22.229710 DQM0 = 99, DQM1 = 89
5177 11:03:22.232868 DQ Delay:
5178 11:03:22.233320 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5179 11:03:22.239583 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5180 11:03:22.239972 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5181 11:03:22.246524 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5182 11:03:22.246907
5183 11:03:22.247201
5184 11:03:22.247474 ==
5185 11:03:22.249644 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 11:03:22.253018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 11:03:22.253445 ==
5188 11:03:22.253743
5189 11:03:22.254013
5190 11:03:22.255797 TX Vref Scan disable
5191 11:03:22.256181 == TX Byte 0 ==
5192 11:03:22.262705 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5193 11:03:22.265832 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5194 11:03:22.266216 == TX Byte 1 ==
5195 11:03:22.272688 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5196 11:03:22.275795 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5197 11:03:22.276180 ==
5198 11:03:22.279141 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 11:03:22.282254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 11:03:22.282641 ==
5201 11:03:22.282943
5202 11:03:22.285703
5203 11:03:22.286085 TX Vref Scan disable
5204 11:03:22.289206 == TX Byte 0 ==
5205 11:03:22.292319 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5206 11:03:22.295607 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5207 11:03:22.299190 == TX Byte 1 ==
5208 11:03:22.302442 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5209 11:03:22.305514 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5210 11:03:22.308881
5211 11:03:22.309389 [DATLAT]
5212 11:03:22.309854 Freq=933, CH0 RK0
5213 11:03:22.310307
5214 11:03:22.312434 DATLAT Default: 0xd
5215 11:03:22.312921 0, 0xFFFF, sum = 0
5216 11:03:22.315514 1, 0xFFFF, sum = 0
5217 11:03:22.316029 2, 0xFFFF, sum = 0
5218 11:03:22.318760 3, 0xFFFF, sum = 0
5219 11:03:22.319261 4, 0xFFFF, sum = 0
5220 11:03:22.322022 5, 0xFFFF, sum = 0
5221 11:03:22.325324 6, 0xFFFF, sum = 0
5222 11:03:22.325715 7, 0xFFFF, sum = 0
5223 11:03:22.328630 8, 0xFFFF, sum = 0
5224 11:03:22.329020 9, 0xFFFF, sum = 0
5225 11:03:22.332356 10, 0x0, sum = 1
5226 11:03:22.332744 11, 0x0, sum = 2
5227 11:03:22.335003 12, 0x0, sum = 3
5228 11:03:22.335394 13, 0x0, sum = 4
5229 11:03:22.335851 best_step = 11
5230 11:03:22.336157
5231 11:03:22.338693 ==
5232 11:03:22.342108 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 11:03:22.345459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 11:03:22.345846 ==
5235 11:03:22.346143 RX Vref Scan: 1
5236 11:03:22.346419
5237 11:03:22.348699 RX Vref 0 -> 0, step: 1
5238 11:03:22.349270
5239 11:03:22.351712 RX Delay -61 -> 252, step: 4
5240 11:03:22.352214
5241 11:03:22.355059 Set Vref, RX VrefLevel [Byte0]: 53
5242 11:03:22.358567 [Byte1]: 59
5243 11:03:22.359059
5244 11:03:22.361541 Final RX Vref Byte 0 = 53 to rank0
5245 11:03:22.365397 Final RX Vref Byte 1 = 59 to rank0
5246 11:03:22.367926 Final RX Vref Byte 0 = 53 to rank1
5247 11:03:22.371556 Final RX Vref Byte 1 = 59 to rank1==
5248 11:03:22.374939 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 11:03:22.378636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 11:03:22.381638 ==
5251 11:03:22.382120 DQS Delay:
5252 11:03:22.382575 DQS0 = 0, DQS1 = 0
5253 11:03:22.385056 DQM Delay:
5254 11:03:22.385574 DQM0 = 98, DQM1 = 88
5255 11:03:22.388043 DQ Delay:
5256 11:03:22.391186 DQ0 =100, DQ1 =98, DQ2 =96, DQ3 =96
5257 11:03:22.394771 DQ4 =98, DQ5 =90, DQ6 =106, DQ7 =104
5258 11:03:22.398242 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5259 11:03:22.401457 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5260 11:03:22.401962
5261 11:03:22.402420
5262 11:03:22.407770 [DQSOSCAuto] RK0, (LSB)MR18= 0x221c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5263 11:03:22.411191 CH0 RK0: MR19=505, MR18=221C
5264 11:03:22.417629 CH0_RK0: MR19=0x505, MR18=0x221C, DQSOSC=411, MR23=63, INC=64, DEC=42
5265 11:03:22.418156
5266 11:03:22.421177 ----->DramcWriteLeveling(PI) begin...
5267 11:03:22.421698 ==
5268 11:03:22.424349 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 11:03:22.428046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 11:03:22.428577 ==
5271 11:03:22.431234 Write leveling (Byte 0): 30 => 30
5272 11:03:22.434680 Write leveling (Byte 1): 28 => 28
5273 11:03:22.437691 DramcWriteLeveling(PI) end<-----
5274 11:03:22.438186
5275 11:03:22.438581 ==
5276 11:03:22.440944 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 11:03:22.444180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 11:03:22.444568 ==
5279 11:03:22.447703 [Gating] SW mode calibration
5280 11:03:22.454471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5281 11:03:22.460832 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5282 11:03:22.464172 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5283 11:03:22.470586 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 11:03:22.473809 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 11:03:22.477476 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 11:03:22.483908 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 11:03:22.487233 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 11:03:22.490678 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5289 11:03:22.496947 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
5290 11:03:22.500302 0 15 0 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
5291 11:03:22.503585 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 11:03:22.510400 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 11:03:22.513616 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 11:03:22.516873 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 11:03:22.523599 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 11:03:22.527161 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5297 11:03:22.530567 0 15 28 | B1->B0 | 2a2a 3e3e | 0 1 | (0 0) (0 0)
5298 11:03:22.537290 1 0 0 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5299 11:03:22.540198 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 11:03:22.543241 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 11:03:22.550137 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 11:03:22.553217 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 11:03:22.556608 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 11:03:22.563121 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5305 11:03:22.566526 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5306 11:03:22.570065 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 11:03:22.576706 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 11:03:22.580299 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 11:03:22.583128 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 11:03:22.589728 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 11:03:22.592756 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 11:03:22.595925 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 11:03:22.602570 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 11:03:22.606164 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 11:03:22.609336 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 11:03:22.616072 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 11:03:22.619391 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 11:03:22.622880 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:03:22.625968 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:03:22.632884 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:03:22.636004 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5322 11:03:22.639274 Total UI for P1: 0, mck2ui 16
5323 11:03:22.642839 best dqsien dly found for B0: ( 1, 2, 26)
5324 11:03:22.645750 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 11:03:22.648941 Total UI for P1: 0, mck2ui 16
5326 11:03:22.652185 best dqsien dly found for B1: ( 1, 2, 28)
5327 11:03:22.655649 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5328 11:03:22.662389 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5329 11:03:22.662777
5330 11:03:22.665881 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5331 11:03:22.669044 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5332 11:03:22.672296 [Gating] SW calibration Done
5333 11:03:22.672684 ==
5334 11:03:22.675607 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 11:03:22.679051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 11:03:22.679442 ==
5337 11:03:22.682040 RX Vref Scan: 0
5338 11:03:22.682425
5339 11:03:22.682723 RX Vref 0 -> 0, step: 1
5340 11:03:22.683011
5341 11:03:22.685450 RX Delay -80 -> 252, step: 8
5342 11:03:22.688479 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5343 11:03:22.695159 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5344 11:03:22.698787 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5345 11:03:22.701956 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5346 11:03:22.705058 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5347 11:03:22.708471 iDelay=200, Bit 5, Center 83 (-8 ~ 175) 184
5348 11:03:22.711593 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5349 11:03:22.718018 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5350 11:03:22.721513 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5351 11:03:22.725170 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5352 11:03:22.728434 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5353 11:03:22.731944 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5354 11:03:22.735342 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5355 11:03:22.741697 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5356 11:03:22.745089 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5357 11:03:22.748040 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5358 11:03:22.748429 ==
5359 11:03:22.751237 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 11:03:22.754635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 11:03:22.755029 ==
5362 11:03:22.757889 DQS Delay:
5363 11:03:22.758341 DQS0 = 0, DQS1 = 0
5364 11:03:22.761427 DQM Delay:
5365 11:03:22.761819 DQM0 = 98, DQM1 = 90
5366 11:03:22.762123 DQ Delay:
5367 11:03:22.764517 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5368 11:03:22.767823 DQ4 =103, DQ5 =83, DQ6 =103, DQ7 =103
5369 11:03:22.770837 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5370 11:03:22.774498 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5371 11:03:22.774971
5372 11:03:22.775280
5373 11:03:22.777746 ==
5374 11:03:22.780895 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 11:03:22.784409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 11:03:22.784804 ==
5377 11:03:22.785111
5378 11:03:22.785447
5379 11:03:22.787831 TX Vref Scan disable
5380 11:03:22.788237 == TX Byte 0 ==
5381 11:03:22.794566 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5382 11:03:22.797381 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5383 11:03:22.797766 == TX Byte 1 ==
5384 11:03:22.804307 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5385 11:03:22.807548 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5386 11:03:22.807958 ==
5387 11:03:22.810845 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 11:03:22.813949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 11:03:22.814634 ==
5390 11:03:22.815250
5391 11:03:22.815814
5392 11:03:22.817079 TX Vref Scan disable
5393 11:03:22.820534 == TX Byte 0 ==
5394 11:03:22.824163 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5395 11:03:22.827135 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5396 11:03:22.830361 == TX Byte 1 ==
5397 11:03:22.833605 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5398 11:03:22.837250 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5399 11:03:22.837734
5400 11:03:22.840716 [DATLAT]
5401 11:03:22.841289 Freq=933, CH0 RK1
5402 11:03:22.841745
5403 11:03:22.843436 DATLAT Default: 0xb
5404 11:03:22.843921 0, 0xFFFF, sum = 0
5405 11:03:22.847058 1, 0xFFFF, sum = 0
5406 11:03:22.847456 2, 0xFFFF, sum = 0
5407 11:03:22.850226 3, 0xFFFF, sum = 0
5408 11:03:22.850719 4, 0xFFFF, sum = 0
5409 11:03:22.853505 5, 0xFFFF, sum = 0
5410 11:03:22.853901 6, 0xFFFF, sum = 0
5411 11:03:22.857187 7, 0xFFFF, sum = 0
5412 11:03:22.857586 8, 0xFFFF, sum = 0
5413 11:03:22.860723 9, 0xFFFF, sum = 0
5414 11:03:22.861119 10, 0x0, sum = 1
5415 11:03:22.863798 11, 0x0, sum = 2
5416 11:03:22.864266 12, 0x0, sum = 3
5417 11:03:22.867027 13, 0x0, sum = 4
5418 11:03:22.867480 best_step = 11
5419 11:03:22.867809
5420 11:03:22.868153 ==
5421 11:03:22.870129 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 11:03:22.876436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 11:03:22.876829 ==
5424 11:03:22.877133 RX Vref Scan: 0
5425 11:03:22.877469
5426 11:03:22.880282 RX Vref 0 -> 0, step: 1
5427 11:03:22.880683
5428 11:03:22.883282 RX Delay -53 -> 252, step: 4
5429 11:03:22.886749 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5430 11:03:22.890382 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5431 11:03:22.896632 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5432 11:03:22.899906 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5433 11:03:22.902929 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5434 11:03:22.906300 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5435 11:03:22.910081 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5436 11:03:22.916660 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5437 11:03:22.920056 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5438 11:03:22.923061 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5439 11:03:22.926599 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5440 11:03:22.929611 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5441 11:03:22.932911 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5442 11:03:22.939451 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5443 11:03:22.942738 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5444 11:03:22.945919 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5445 11:03:22.946307 ==
5446 11:03:22.949175 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 11:03:22.952567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 11:03:22.952852 ==
5449 11:03:22.955577 DQS Delay:
5450 11:03:22.955826 DQS0 = 0, DQS1 = 0
5451 11:03:22.959247 DQM Delay:
5452 11:03:22.959455 DQM0 = 98, DQM1 = 88
5453 11:03:22.959615 DQ Delay:
5454 11:03:22.962295 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =96
5455 11:03:22.965554 DQ4 =102, DQ5 =88, DQ6 =108, DQ7 =104
5456 11:03:22.969309 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5457 11:03:22.972005 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =94
5458 11:03:22.975497
5459 11:03:22.975635
5460 11:03:22.982303 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5461 11:03:22.985499 CH0 RK1: MR19=505, MR18=1A16
5462 11:03:22.991848 CH0_RK1: MR19=0x505, MR18=0x1A16, DQSOSC=413, MR23=63, INC=63, DEC=42
5463 11:03:22.995558 [RxdqsGatingPostProcess] freq 933
5464 11:03:22.998746 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5465 11:03:23.001570 best DQS0 dly(2T, 0.5T) = (0, 10)
5466 11:03:23.004941 best DQS1 dly(2T, 0.5T) = (0, 11)
5467 11:03:23.008466 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5468 11:03:23.011692 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5469 11:03:23.015170 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 11:03:23.018398 best DQS1 dly(2T, 0.5T) = (0, 10)
5471 11:03:23.021746 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 11:03:23.024691 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5473 11:03:23.028016 Pre-setting of DQS Precalculation
5474 11:03:23.031252 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5475 11:03:23.031386 ==
5476 11:03:23.034687 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 11:03:23.041278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 11:03:23.041364 ==
5479 11:03:23.044452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5480 11:03:23.051206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5481 11:03:23.054609 [CA 0] Center 36 (6~67) winsize 62
5482 11:03:23.057836 [CA 1] Center 36 (6~67) winsize 62
5483 11:03:23.061101 [CA 2] Center 34 (4~65) winsize 62
5484 11:03:23.064440 [CA 3] Center 34 (3~65) winsize 63
5485 11:03:23.068108 [CA 4] Center 34 (4~65) winsize 62
5486 11:03:23.071072 [CA 5] Center 33 (3~64) winsize 62
5487 11:03:23.071157
5488 11:03:23.074552 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5489 11:03:23.074635
5490 11:03:23.077710 [CATrainingPosCal] consider 1 rank data
5491 11:03:23.080716 u2DelayCellTimex100 = 270/100 ps
5492 11:03:23.087552 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 11:03:23.091117 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5494 11:03:23.094294 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5495 11:03:23.097331 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5496 11:03:23.100552 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5497 11:03:23.104052 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5498 11:03:23.104161
5499 11:03:23.107549 CA PerBit enable=1, Macro0, CA PI delay=33
5500 11:03:23.107658
5501 11:03:23.111127 [CBTSetCACLKResult] CA Dly = 33
5502 11:03:23.113732 CS Dly: 5 (0~36)
5503 11:03:23.113837 ==
5504 11:03:23.117038 Dram Type= 6, Freq= 0, CH_1, rank 1
5505 11:03:23.120364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 11:03:23.120470 ==
5507 11:03:23.127193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 11:03:23.130582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5509 11:03:23.134818 [CA 0] Center 36 (6~67) winsize 62
5510 11:03:23.138268 [CA 1] Center 36 (6~67) winsize 62
5511 11:03:23.141702 [CA 2] Center 34 (4~65) winsize 62
5512 11:03:23.144552 [CA 3] Center 33 (3~64) winsize 62
5513 11:03:23.148042 [CA 4] Center 33 (3~64) winsize 62
5514 11:03:23.150939 [CA 5] Center 33 (3~64) winsize 62
5515 11:03:23.151172
5516 11:03:23.154249 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5517 11:03:23.154483
5518 11:03:23.157823 [CATrainingPosCal] consider 2 rank data
5519 11:03:23.161015 u2DelayCellTimex100 = 270/100 ps
5520 11:03:23.164226 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 11:03:23.170882 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 11:03:23.174607 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5523 11:03:23.177780 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5524 11:03:23.180700 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 11:03:23.184283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5526 11:03:23.184664
5527 11:03:23.187257 CA PerBit enable=1, Macro0, CA PI delay=33
5528 11:03:23.187643
5529 11:03:23.190475 [CBTSetCACLKResult] CA Dly = 33
5530 11:03:23.193976 CS Dly: 6 (0~38)
5531 11:03:23.194418
5532 11:03:23.197549 ----->DramcWriteLeveling(PI) begin...
5533 11:03:23.197935 ==
5534 11:03:23.200346 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 11:03:23.203725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 11:03:23.204094 ==
5537 11:03:23.206947 Write leveling (Byte 0): 25 => 25
5538 11:03:23.210418 Write leveling (Byte 1): 26 => 26
5539 11:03:23.213609 DramcWriteLeveling(PI) end<-----
5540 11:03:23.213957
5541 11:03:23.214290 ==
5542 11:03:23.216868 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 11:03:23.220233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 11:03:23.220402 ==
5545 11:03:23.223193 [Gating] SW mode calibration
5546 11:03:23.229948 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5547 11:03:23.236669 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5548 11:03:23.240230 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 11:03:23.246410 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 11:03:23.249544 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 11:03:23.253065 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 11:03:23.256602 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 11:03:23.262978 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 11:03:23.266068 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5555 11:03:23.269597 0 14 28 | B1->B0 | 2d2d 2424 | 0 0 | (1 1) (1 0)
5556 11:03:23.276094 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 11:03:23.279809 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 11:03:23.282981 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 11:03:23.289407 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 11:03:23.292608 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 11:03:23.296022 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 11:03:23.303000 0 15 24 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
5563 11:03:23.305821 0 15 28 | B1->B0 | 3939 3f3f | 1 1 | (0 0) (0 0)
5564 11:03:23.312268 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 11:03:23.315992 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 11:03:23.319307 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 11:03:23.322474 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 11:03:23.328962 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 11:03:23.332937 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 11:03:23.336103 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5571 11:03:23.342504 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5572 11:03:23.345715 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5573 11:03:23.349173 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 11:03:23.355890 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 11:03:23.358683 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 11:03:23.362077 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 11:03:23.368724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 11:03:23.372171 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 11:03:23.375067 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 11:03:23.382042 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 11:03:23.385587 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:03:23.388596 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:03:23.395475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:03:23.398573 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:03:23.401847 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:03:23.408078 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:03:23.411549 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5588 11:03:23.415165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 11:03:23.418470 Total UI for P1: 0, mck2ui 16
5590 11:03:23.421814 best dqsien dly found for B0: ( 1, 2, 28)
5591 11:03:23.424811 Total UI for P1: 0, mck2ui 16
5592 11:03:23.428413 best dqsien dly found for B1: ( 1, 2, 28)
5593 11:03:23.431263 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5594 11:03:23.434870 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5595 11:03:23.435206
5596 11:03:23.441374 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5597 11:03:23.444886 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5598 11:03:23.447890 [Gating] SW calibration Done
5599 11:03:23.448272 ==
5600 11:03:23.451007 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 11:03:23.454678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 11:03:23.454956 ==
5603 11:03:23.455171 RX Vref Scan: 0
5604 11:03:23.458487
5605 11:03:23.458840 RX Vref 0 -> 0, step: 1
5606 11:03:23.459215
5607 11:03:23.461464 RX Delay -80 -> 252, step: 8
5608 11:03:23.464791 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5609 11:03:23.468204 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5610 11:03:23.474469 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5611 11:03:23.477929 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5612 11:03:23.481407 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5613 11:03:23.484611 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5614 11:03:23.487372 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5615 11:03:23.490906 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5616 11:03:23.497684 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5617 11:03:23.500514 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5618 11:03:23.503814 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5619 11:03:23.507165 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5620 11:03:23.513998 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5621 11:03:23.516946 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5622 11:03:23.520197 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5623 11:03:23.523852 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5624 11:03:23.524129 ==
5625 11:03:23.526897 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 11:03:23.530000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 11:03:23.530305 ==
5628 11:03:23.533528 DQS Delay:
5629 11:03:23.533873 DQS0 = 0, DQS1 = 0
5630 11:03:23.536636 DQM Delay:
5631 11:03:23.536974 DQM0 = 98, DQM1 = 93
5632 11:03:23.537312 DQ Delay:
5633 11:03:23.540518 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5634 11:03:23.543389 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5635 11:03:23.547066 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5636 11:03:23.553228 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5637 11:03:23.553626
5638 11:03:23.553927
5639 11:03:23.554207 ==
5640 11:03:23.556558 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 11:03:23.560029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 11:03:23.560373 ==
5643 11:03:23.560715
5644 11:03:23.561022
5645 11:03:23.563237 TX Vref Scan disable
5646 11:03:23.563530 == TX Byte 0 ==
5647 11:03:23.569628 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5648 11:03:23.573226 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5649 11:03:23.573401 == TX Byte 1 ==
5650 11:03:23.579589 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5651 11:03:23.582929 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5652 11:03:23.583049 ==
5653 11:03:23.586164 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 11:03:23.589190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 11:03:23.589315 ==
5656 11:03:23.592530
5657 11:03:23.592653
5658 11:03:23.592800 TX Vref Scan disable
5659 11:03:23.595893 == TX Byte 0 ==
5660 11:03:23.599049 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5661 11:03:23.605876 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5662 11:03:23.606001 == TX Byte 1 ==
5663 11:03:23.609259 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5664 11:03:23.615799 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5665 11:03:23.615938
5666 11:03:23.616103 [DATLAT]
5667 11:03:23.616233 Freq=933, CH1 RK0
5668 11:03:23.616359
5669 11:03:23.618737 DATLAT Default: 0xd
5670 11:03:23.622213 0, 0xFFFF, sum = 0
5671 11:03:23.622373 1, 0xFFFF, sum = 0
5672 11:03:23.625491 2, 0xFFFF, sum = 0
5673 11:03:23.625675 3, 0xFFFF, sum = 0
5674 11:03:23.628666 4, 0xFFFF, sum = 0
5675 11:03:23.628851 5, 0xFFFF, sum = 0
5676 11:03:23.632364 6, 0xFFFF, sum = 0
5677 11:03:23.632548 7, 0xFFFF, sum = 0
5678 11:03:23.635646 8, 0xFFFF, sum = 0
5679 11:03:23.635904 9, 0xFFFF, sum = 0
5680 11:03:23.638499 10, 0x0, sum = 1
5681 11:03:23.638716 11, 0x0, sum = 2
5682 11:03:23.642228 12, 0x0, sum = 3
5683 11:03:23.642492 13, 0x0, sum = 4
5684 11:03:23.645116 best_step = 11
5685 11:03:23.645492
5686 11:03:23.645870 ==
5687 11:03:23.648964 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 11:03:23.652203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 11:03:23.652677 ==
5690 11:03:23.653134 RX Vref Scan: 1
5691 11:03:23.655441
5692 11:03:23.655902 RX Vref 0 -> 0, step: 1
5693 11:03:23.656319
5694 11:03:23.658711 RX Delay -61 -> 252, step: 4
5695 11:03:23.659185
5696 11:03:23.662297 Set Vref, RX VrefLevel [Byte0]: 52
5697 11:03:23.665249 [Byte1]: 52
5698 11:03:23.669070
5699 11:03:23.669593 Final RX Vref Byte 0 = 52 to rank0
5700 11:03:23.672036 Final RX Vref Byte 1 = 52 to rank0
5701 11:03:23.675142 Final RX Vref Byte 0 = 52 to rank1
5702 11:03:23.678526 Final RX Vref Byte 1 = 52 to rank1==
5703 11:03:23.681753 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 11:03:23.688687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 11:03:23.689089 ==
5706 11:03:23.689523 DQS Delay:
5707 11:03:23.691333 DQS0 = 0, DQS1 = 0
5708 11:03:23.691729 DQM Delay:
5709 11:03:23.692125 DQM0 = 98, DQM1 = 95
5710 11:03:23.695054 DQ Delay:
5711 11:03:23.698214 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =98
5712 11:03:23.701310 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5713 11:03:23.704822 DQ8 =84, DQ9 =86, DQ10 =94, DQ11 =88
5714 11:03:23.707962 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =104
5715 11:03:23.708180
5716 11:03:23.708365
5717 11:03:23.714616 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5718 11:03:23.717837 CH1 RK0: MR19=505, MR18=C1C
5719 11:03:23.724362 CH1_RK0: MR19=0x505, MR18=0xC1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5720 11:03:23.724545
5721 11:03:23.727732 ----->DramcWriteLeveling(PI) begin...
5722 11:03:23.727917 ==
5723 11:03:23.730658 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 11:03:23.734505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 11:03:23.737376 ==
5726 11:03:23.737521 Write leveling (Byte 0): 27 => 27
5727 11:03:23.740572 Write leveling (Byte 1): 27 => 27
5728 11:03:23.744090 DramcWriteLeveling(PI) end<-----
5729 11:03:23.744293
5730 11:03:23.744434 ==
5731 11:03:23.747434 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 11:03:23.753596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 11:03:23.753756 ==
5734 11:03:23.757318 [Gating] SW mode calibration
5735 11:03:23.764034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5736 11:03:23.766887 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5737 11:03:23.773921 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 11:03:23.777089 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 11:03:23.780264 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 11:03:23.787041 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 11:03:23.790378 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 11:03:23.793883 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 11:03:23.800026 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
5744 11:03:23.803280 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5745 11:03:23.806641 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 11:03:23.813094 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 11:03:23.816742 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 11:03:23.820106 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 11:03:23.826237 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 11:03:23.829477 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 11:03:23.832757 0 15 24 | B1->B0 | 2828 3737 | 0 0 | (0 0) (0 0)
5752 11:03:23.839405 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5753 11:03:23.843034 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 11:03:23.846318 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 11:03:23.852472 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 11:03:23.856358 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 11:03:23.859514 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 11:03:23.866185 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 11:03:23.869073 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5760 11:03:23.872706 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5761 11:03:23.878945 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 11:03:23.882667 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 11:03:23.885811 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 11:03:23.892577 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 11:03:23.895842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 11:03:23.899013 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 11:03:23.906017 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 11:03:23.909290 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 11:03:23.912560 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 11:03:23.919242 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 11:03:23.922156 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:03:23.925615 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:03:23.932269 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:03:23.935191 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:03:23.938853 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5776 11:03:23.945916 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5777 11:03:23.946356 Total UI for P1: 0, mck2ui 16
5778 11:03:23.952224 best dqsien dly found for B0: ( 1, 2, 24)
5779 11:03:23.955444 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 11:03:23.958442 Total UI for P1: 0, mck2ui 16
5781 11:03:23.961343 best dqsien dly found for B1: ( 1, 2, 26)
5782 11:03:23.964674 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5783 11:03:23.967996 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5784 11:03:23.968270
5785 11:03:23.971381 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5786 11:03:23.975145 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5787 11:03:23.978031 [Gating] SW calibration Done
5788 11:03:23.978302 ==
5789 11:03:23.981214 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 11:03:23.984627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 11:03:23.988168 ==
5792 11:03:23.988448 RX Vref Scan: 0
5793 11:03:23.988692
5794 11:03:23.991177 RX Vref 0 -> 0, step: 1
5795 11:03:23.991448
5796 11:03:23.994442 RX Delay -80 -> 252, step: 8
5797 11:03:23.998042 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5798 11:03:24.001199 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5799 11:03:24.004532 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5800 11:03:24.007578 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5801 11:03:24.010932 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5802 11:03:24.017815 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5803 11:03:24.020841 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5804 11:03:24.024031 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5805 11:03:24.027753 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5806 11:03:24.030614 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5807 11:03:24.037295 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5808 11:03:24.040525 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5809 11:03:24.044069 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5810 11:03:24.047190 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5811 11:03:24.050488 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5812 11:03:24.053858 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5813 11:03:24.056980 ==
5814 11:03:24.057483 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 11:03:24.063869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 11:03:24.064459 ==
5817 11:03:24.064772 DQS Delay:
5818 11:03:24.066831 DQS0 = 0, DQS1 = 0
5819 11:03:24.067217 DQM Delay:
5820 11:03:24.070366 DQM0 = 96, DQM1 = 92
5821 11:03:24.070803 DQ Delay:
5822 11:03:24.073886 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5823 11:03:24.076631 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =95
5824 11:03:24.080662 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5825 11:03:24.083364 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =99
5826 11:03:24.083849
5827 11:03:24.084287
5828 11:03:24.084588 ==
5829 11:03:24.086676 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 11:03:24.090174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 11:03:24.090404 ==
5832 11:03:24.090568
5833 11:03:24.090715
5834 11:03:24.092855 TX Vref Scan disable
5835 11:03:24.096348 == TX Byte 0 ==
5836 11:03:24.099741 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5837 11:03:24.103408 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5838 11:03:24.106234 == TX Byte 1 ==
5839 11:03:24.109638 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5840 11:03:24.113112 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5841 11:03:24.113343 ==
5842 11:03:24.116423 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 11:03:24.123164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 11:03:24.123417 ==
5845 11:03:24.123612
5846 11:03:24.123793
5847 11:03:24.123964 TX Vref Scan disable
5848 11:03:24.127046 == TX Byte 0 ==
5849 11:03:24.131015 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 11:03:24.136901 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 11:03:24.137321 == TX Byte 1 ==
5852 11:03:24.140446 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5853 11:03:24.146718 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5854 11:03:24.147102
5855 11:03:24.147397 [DATLAT]
5856 11:03:24.147668 Freq=933, CH1 RK1
5857 11:03:24.147933
5858 11:03:24.150298 DATLAT Default: 0xb
5859 11:03:24.153644 0, 0xFFFF, sum = 0
5860 11:03:24.154035 1, 0xFFFF, sum = 0
5861 11:03:24.156305 2, 0xFFFF, sum = 0
5862 11:03:24.156695 3, 0xFFFF, sum = 0
5863 11:03:24.159820 4, 0xFFFF, sum = 0
5864 11:03:24.160280 5, 0xFFFF, sum = 0
5865 11:03:24.163277 6, 0xFFFF, sum = 0
5866 11:03:24.163846 7, 0xFFFF, sum = 0
5867 11:03:24.166326 8, 0xFFFF, sum = 0
5868 11:03:24.166892 9, 0xFFFF, sum = 0
5869 11:03:24.169703 10, 0x0, sum = 1
5870 11:03:24.170092 11, 0x0, sum = 2
5871 11:03:24.173094 12, 0x0, sum = 3
5872 11:03:24.173674 13, 0x0, sum = 4
5873 11:03:24.176437 best_step = 11
5874 11:03:24.176863
5875 11:03:24.177375 ==
5876 11:03:24.179403 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 11:03:24.182720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 11:03:24.183130 ==
5879 11:03:24.183435 RX Vref Scan: 0
5880 11:03:24.186230
5881 11:03:24.186614 RX Vref 0 -> 0, step: 1
5882 11:03:24.186917
5883 11:03:24.189762 RX Delay -61 -> 252, step: 4
5884 11:03:24.196703 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5885 11:03:24.199399 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5886 11:03:24.202720 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5887 11:03:24.206038 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5888 11:03:24.209391 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5889 11:03:24.212674 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5890 11:03:24.219313 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5891 11:03:24.222751 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5892 11:03:24.225597 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5893 11:03:24.228833 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5894 11:03:24.232359 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5895 11:03:24.239523 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5896 11:03:24.242655 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5897 11:03:24.245728 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5898 11:03:24.248870 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5899 11:03:24.252151 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5900 11:03:24.255740 ==
5901 11:03:24.259085 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 11:03:24.262375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 11:03:24.262764 ==
5904 11:03:24.263065 DQS Delay:
5905 11:03:24.265513 DQS0 = 0, DQS1 = 0
5906 11:03:24.265902 DQM Delay:
5907 11:03:24.268516 DQM0 = 97, DQM1 = 95
5908 11:03:24.268900 DQ Delay:
5909 11:03:24.272364 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5910 11:03:24.275273 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5911 11:03:24.278841 DQ8 =82, DQ9 =84, DQ10 =98, DQ11 =88
5912 11:03:24.282120 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =104
5913 11:03:24.282505
5914 11:03:24.282801
5915 11:03:24.292031 [DQSOSCAuto] RK1, (LSB)MR18= 0x1128, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5916 11:03:24.292423 CH1 RK1: MR19=505, MR18=1128
5917 11:03:24.298740 CH1_RK1: MR19=0x505, MR18=0x1128, DQSOSC=409, MR23=63, INC=64, DEC=43
5918 11:03:24.301978 [RxdqsGatingPostProcess] freq 933
5919 11:03:24.308402 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5920 11:03:24.311914 best DQS0 dly(2T, 0.5T) = (0, 10)
5921 11:03:24.315133 best DQS1 dly(2T, 0.5T) = (0, 10)
5922 11:03:24.318740 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5923 11:03:24.321787 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5924 11:03:24.324538 best DQS0 dly(2T, 0.5T) = (0, 10)
5925 11:03:24.324814 best DQS1 dly(2T, 0.5T) = (0, 10)
5926 11:03:24.328447 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5927 11:03:24.331545 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5928 11:03:24.334337 Pre-setting of DQS Precalculation
5929 11:03:24.340750 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5930 11:03:24.347759 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5931 11:03:24.354421 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5932 11:03:24.354590
5933 11:03:24.354720
5934 11:03:24.357838 [Calibration Summary] 1866 Mbps
5935 11:03:24.360771 CH 0, Rank 0
5936 11:03:24.360938 SW Impedance : PASS
5937 11:03:24.364373 DUTY Scan : NO K
5938 11:03:24.367478 ZQ Calibration : PASS
5939 11:03:24.367679 Jitter Meter : NO K
5940 11:03:24.370729 CBT Training : PASS
5941 11:03:24.374100 Write leveling : PASS
5942 11:03:24.374340 RX DQS gating : PASS
5943 11:03:24.377698 RX DQ/DQS(RDDQC) : PASS
5944 11:03:24.380824 TX DQ/DQS : PASS
5945 11:03:24.381266 RX DATLAT : PASS
5946 11:03:24.384067 RX DQ/DQS(Engine): PASS
5947 11:03:24.384457 TX OE : NO K
5948 11:03:24.387561 All Pass.
5949 11:03:24.387944
5950 11:03:24.388246 CH 0, Rank 1
5951 11:03:24.390763 SW Impedance : PASS
5952 11:03:24.394187 DUTY Scan : NO K
5953 11:03:24.394574 ZQ Calibration : PASS
5954 11:03:24.397659 Jitter Meter : NO K
5955 11:03:24.398048 CBT Training : PASS
5956 11:03:24.400646 Write leveling : PASS
5957 11:03:24.403587 RX DQS gating : PASS
5958 11:03:24.403978 RX DQ/DQS(RDDQC) : PASS
5959 11:03:24.406935 TX DQ/DQS : PASS
5960 11:03:24.410117 RX DATLAT : PASS
5961 11:03:24.410519 RX DQ/DQS(Engine): PASS
5962 11:03:24.413572 TX OE : NO K
5963 11:03:24.413974 All Pass.
5964 11:03:24.414367
5965 11:03:24.416967 CH 1, Rank 0
5966 11:03:24.417519 SW Impedance : PASS
5967 11:03:24.420053 DUTY Scan : NO K
5968 11:03:24.423491 ZQ Calibration : PASS
5969 11:03:24.424038 Jitter Meter : NO K
5970 11:03:24.426532 CBT Training : PASS
5971 11:03:24.430081 Write leveling : PASS
5972 11:03:24.430578 RX DQS gating : PASS
5973 11:03:24.433470 RX DQ/DQS(RDDQC) : PASS
5974 11:03:24.436352 TX DQ/DQS : PASS
5975 11:03:24.436693 RX DATLAT : PASS
5976 11:03:24.439454 RX DQ/DQS(Engine): PASS
5977 11:03:24.442789 TX OE : NO K
5978 11:03:24.443044 All Pass.
5979 11:03:24.443288
5980 11:03:24.443522 CH 1, Rank 1
5981 11:03:24.446197 SW Impedance : PASS
5982 11:03:24.449501 DUTY Scan : NO K
5983 11:03:24.449672 ZQ Calibration : PASS
5984 11:03:24.453269 Jitter Meter : NO K
5985 11:03:24.456363 CBT Training : PASS
5986 11:03:24.456514 Write leveling : PASS
5987 11:03:24.459487 RX DQS gating : PASS
5988 11:03:24.462671 RX DQ/DQS(RDDQC) : PASS
5989 11:03:24.462808 TX DQ/DQS : PASS
5990 11:03:24.465768 RX DATLAT : PASS
5991 11:03:24.469071 RX DQ/DQS(Engine): PASS
5992 11:03:24.469207 TX OE : NO K
5993 11:03:24.469329 All Pass.
5994 11:03:24.472602
5995 11:03:24.472731 DramC Write-DBI off
5996 11:03:24.475935 PER_BANK_REFRESH: Hybrid Mode
5997 11:03:24.476065 TX_TRACKING: ON
5998 11:03:24.486009 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5999 11:03:24.489442 [FAST_K] Save calibration result to emmc
6000 11:03:24.492963 dramc_set_vcore_voltage set vcore to 650000
6001 11:03:24.495922 Read voltage for 400, 6
6002 11:03:24.496081 Vio18 = 0
6003 11:03:24.499227 Vcore = 650000
6004 11:03:24.499358 Vdram = 0
6005 11:03:24.499459 Vddq = 0
6006 11:03:24.499566 Vmddr = 0
6007 11:03:24.506232 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6008 11:03:24.512625 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6009 11:03:24.512892 MEM_TYPE=3, freq_sel=20
6010 11:03:24.515847 sv_algorithm_assistance_LP4_800
6011 11:03:24.519112 ============ PULL DRAM RESETB DOWN ============
6012 11:03:24.525657 ========== PULL DRAM RESETB DOWN end =========
6013 11:03:24.528914 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6014 11:03:24.532373 ===================================
6015 11:03:24.535404 LPDDR4 DRAM CONFIGURATION
6016 11:03:24.538890 ===================================
6017 11:03:24.539409 EX_ROW_EN[0] = 0x0
6018 11:03:24.542043 EX_ROW_EN[1] = 0x0
6019 11:03:24.545556 LP4Y_EN = 0x0
6020 11:03:24.545955 WORK_FSP = 0x0
6021 11:03:24.548707 WL = 0x2
6022 11:03:24.549091 RL = 0x2
6023 11:03:24.551876 BL = 0x2
6024 11:03:24.552257 RPST = 0x0
6025 11:03:24.555701 RD_PRE = 0x0
6026 11:03:24.556087 WR_PRE = 0x1
6027 11:03:24.558461 WR_PST = 0x0
6028 11:03:24.558858 DBI_WR = 0x0
6029 11:03:24.562182 DBI_RD = 0x0
6030 11:03:24.562565 OTF = 0x1
6031 11:03:24.565006 ===================================
6032 11:03:24.568720 ===================================
6033 11:03:24.572230 ANA top config
6034 11:03:24.574839 ===================================
6035 11:03:24.575235 DLL_ASYNC_EN = 0
6036 11:03:24.578523 ALL_SLAVE_EN = 1
6037 11:03:24.581876 NEW_RANK_MODE = 1
6038 11:03:24.585131 DLL_IDLE_MODE = 1
6039 11:03:24.588531 LP45_APHY_COMB_EN = 1
6040 11:03:24.588921 TX_ODT_DIS = 1
6041 11:03:24.591902 NEW_8X_MODE = 1
6042 11:03:24.594933 ===================================
6043 11:03:24.598207 ===================================
6044 11:03:24.601709 data_rate = 800
6045 11:03:24.604489 CKR = 1
6046 11:03:24.607781 DQ_P2S_RATIO = 4
6047 11:03:24.611108 ===================================
6048 11:03:24.614731 CA_P2S_RATIO = 4
6049 11:03:24.615199 DQ_CA_OPEN = 0
6050 11:03:24.618235 DQ_SEMI_OPEN = 1
6051 11:03:24.620935 CA_SEMI_OPEN = 1
6052 11:03:24.624768 CA_FULL_RATE = 0
6053 11:03:24.628416 DQ_CKDIV4_EN = 0
6054 11:03:24.631308 CA_CKDIV4_EN = 1
6055 11:03:24.631831 CA_PREDIV_EN = 0
6056 11:03:24.634419 PH8_DLY = 0
6057 11:03:24.637766 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6058 11:03:24.641239 DQ_AAMCK_DIV = 0
6059 11:03:24.644202 CA_AAMCK_DIV = 0
6060 11:03:24.647543 CA_ADMCK_DIV = 4
6061 11:03:24.648096 DQ_TRACK_CA_EN = 0
6062 11:03:24.651113 CA_PICK = 800
6063 11:03:24.654504 CA_MCKIO = 400
6064 11:03:24.657410 MCKIO_SEMI = 400
6065 11:03:24.660618 PLL_FREQ = 3016
6066 11:03:24.663979 DQ_UI_PI_RATIO = 32
6067 11:03:24.667654 CA_UI_PI_RATIO = 32
6068 11:03:24.670601 ===================================
6069 11:03:24.673930 ===================================
6070 11:03:24.677169 memory_type:LPDDR4
6071 11:03:24.677687 GP_NUM : 10
6072 11:03:24.680182 SRAM_EN : 1
6073 11:03:24.680675 MD32_EN : 0
6074 11:03:24.683622 ===================================
6075 11:03:24.686923 [ANA_INIT] >>>>>>>>>>>>>>
6076 11:03:24.690364 <<<<<< [CONFIGURE PHASE]: ANA_TX
6077 11:03:24.693449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6078 11:03:24.696681 ===================================
6079 11:03:24.700428 data_rate = 800,PCW = 0X7400
6080 11:03:24.703396 ===================================
6081 11:03:24.706579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6082 11:03:24.713067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6083 11:03:24.723378 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 11:03:24.726476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6085 11:03:24.729619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6086 11:03:24.733296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6087 11:03:24.736332 [ANA_INIT] flow start
6088 11:03:24.739936 [ANA_INIT] PLL >>>>>>>>
6089 11:03:24.740350 [ANA_INIT] PLL <<<<<<<<
6090 11:03:24.743284 [ANA_INIT] MIDPI >>>>>>>>
6091 11:03:24.746180 [ANA_INIT] MIDPI <<<<<<<<
6092 11:03:24.749978 [ANA_INIT] DLL >>>>>>>>
6093 11:03:24.750309 [ANA_INIT] flow end
6094 11:03:24.752789 ============ LP4 DIFF to SE enter ============
6095 11:03:24.759261 ============ LP4 DIFF to SE exit ============
6096 11:03:24.759776 [ANA_INIT] <<<<<<<<<<<<<
6097 11:03:24.762794 [Flow] Enable top DCM control >>>>>
6098 11:03:24.766425 [Flow] Enable top DCM control <<<<<
6099 11:03:24.769600 Enable DLL master slave shuffle
6100 11:03:24.775888 ==============================================================
6101 11:03:24.776318 Gating Mode config
6102 11:03:24.782807 ==============================================================
6103 11:03:24.785854 Config description:
6104 11:03:24.795611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6105 11:03:24.802566 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6106 11:03:24.806196 SELPH_MODE 0: By rank 1: By Phase
6107 11:03:24.812478 ==============================================================
6108 11:03:24.815621 GAT_TRACK_EN = 0
6109 11:03:24.819147 RX_GATING_MODE = 2
6110 11:03:24.822089 RX_GATING_TRACK_MODE = 2
6111 11:03:24.822578 SELPH_MODE = 1
6112 11:03:24.825961 PICG_EARLY_EN = 1
6113 11:03:24.828830 VALID_LAT_VALUE = 1
6114 11:03:24.835536 ==============================================================
6115 11:03:24.838975 Enter into Gating configuration >>>>
6116 11:03:24.842106 Exit from Gating configuration <<<<
6117 11:03:24.845949 Enter into DVFS_PRE_config >>>>>
6118 11:03:24.855347 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6119 11:03:24.858638 Exit from DVFS_PRE_config <<<<<
6120 11:03:24.861578 Enter into PICG configuration >>>>
6121 11:03:24.865061 Exit from PICG configuration <<<<
6122 11:03:24.868301 [RX_INPUT] configuration >>>>>
6123 11:03:24.871856 [RX_INPUT] configuration <<<<<
6124 11:03:24.875530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6125 11:03:24.881555 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6126 11:03:24.888320 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 11:03:24.894949 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 11:03:24.901292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 11:03:24.905029 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 11:03:24.911369 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6131 11:03:24.914970 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6132 11:03:24.918078 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6133 11:03:24.921244 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6134 11:03:24.927987 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6135 11:03:24.931168 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6136 11:03:24.934702 ===================================
6137 11:03:24.937828 LPDDR4 DRAM CONFIGURATION
6138 11:03:24.941499 ===================================
6139 11:03:24.942001 EX_ROW_EN[0] = 0x0
6140 11:03:24.944351 EX_ROW_EN[1] = 0x0
6141 11:03:24.944829 LP4Y_EN = 0x0
6142 11:03:24.947804 WORK_FSP = 0x0
6143 11:03:24.948286 WL = 0x2
6144 11:03:24.951173 RL = 0x2
6145 11:03:24.954989 BL = 0x2
6146 11:03:24.955407 RPST = 0x0
6147 11:03:24.957642 RD_PRE = 0x0
6148 11:03:24.958077 WR_PRE = 0x1
6149 11:03:24.960734 WR_PST = 0x0
6150 11:03:24.961316 DBI_WR = 0x0
6151 11:03:24.964404 DBI_RD = 0x0
6152 11:03:24.964789 OTF = 0x1
6153 11:03:24.967832 ===================================
6154 11:03:24.971060 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6155 11:03:24.977504 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6156 11:03:24.981045 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6157 11:03:24.984263 ===================================
6158 11:03:24.987567 LPDDR4 DRAM CONFIGURATION
6159 11:03:24.990345 ===================================
6160 11:03:24.990553 EX_ROW_EN[0] = 0x10
6161 11:03:24.993666 EX_ROW_EN[1] = 0x0
6162 11:03:24.993900 LP4Y_EN = 0x0
6163 11:03:24.997181 WORK_FSP = 0x0
6164 11:03:25.000617 WL = 0x2
6165 11:03:25.000824 RL = 0x2
6166 11:03:25.003873 BL = 0x2
6167 11:03:25.004080 RPST = 0x0
6168 11:03:25.006735 RD_PRE = 0x0
6169 11:03:25.006943 WR_PRE = 0x1
6170 11:03:25.010070 WR_PST = 0x0
6171 11:03:25.010277 DBI_WR = 0x0
6172 11:03:25.013794 DBI_RD = 0x0
6173 11:03:25.014002 OTF = 0x1
6174 11:03:25.016900 ===================================
6175 11:03:25.023338 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6176 11:03:25.027963 nWR fixed to 30
6177 11:03:25.031189 [ModeRegInit_LP4] CH0 RK0
6178 11:03:25.031813 [ModeRegInit_LP4] CH0 RK1
6179 11:03:25.034473 [ModeRegInit_LP4] CH1 RK0
6180 11:03:25.037459 [ModeRegInit_LP4] CH1 RK1
6181 11:03:25.037937 match AC timing 19
6182 11:03:25.044203 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6183 11:03:25.047324 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6184 11:03:25.050608 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6185 11:03:25.057103 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6186 11:03:25.060485 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6187 11:03:25.060989 ==
6188 11:03:25.064012 Dram Type= 6, Freq= 0, CH_0, rank 0
6189 11:03:25.067685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6190 11:03:25.068072 ==
6191 11:03:25.073695 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6192 11:03:25.080280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6193 11:03:25.083946 [CA 0] Center 36 (8~64) winsize 57
6194 11:03:25.086826 [CA 1] Center 36 (8~64) winsize 57
6195 11:03:25.090843 [CA 2] Center 36 (8~64) winsize 57
6196 11:03:25.093586 [CA 3] Center 36 (8~64) winsize 57
6197 11:03:25.096867 [CA 4] Center 36 (8~64) winsize 57
6198 11:03:25.097418 [CA 5] Center 36 (8~64) winsize 57
6199 11:03:25.100147
6200 11:03:25.103634 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6201 11:03:25.104126
6202 11:03:25.107162 [CATrainingPosCal] consider 1 rank data
6203 11:03:25.110734 u2DelayCellTimex100 = 270/100 ps
6204 11:03:25.113731 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 11:03:25.117163 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 11:03:25.120201 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 11:03:25.124122 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 11:03:25.126899 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 11:03:25.130131 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 11:03:25.130690
6211 11:03:25.133636 CA PerBit enable=1, Macro0, CA PI delay=36
6212 11:03:25.134022
6213 11:03:25.136680 [CBTSetCACLKResult] CA Dly = 36
6214 11:03:25.139864 CS Dly: 1 (0~32)
6215 11:03:25.140248 ==
6216 11:03:25.143297 Dram Type= 6, Freq= 0, CH_0, rank 1
6217 11:03:25.146882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 11:03:25.147271 ==
6219 11:03:25.153619 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 11:03:25.159682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6221 11:03:25.163044 [CA 0] Center 36 (8~64) winsize 57
6222 11:03:25.166425 [CA 1] Center 36 (8~64) winsize 57
6223 11:03:25.169720 [CA 2] Center 36 (8~64) winsize 57
6224 11:03:25.170228 [CA 3] Center 36 (8~64) winsize 57
6225 11:03:25.173017 [CA 4] Center 36 (8~64) winsize 57
6226 11:03:25.176415 [CA 5] Center 36 (8~64) winsize 57
6227 11:03:25.176902
6228 11:03:25.179738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6229 11:03:25.183144
6230 11:03:25.185979 [CATrainingPosCal] consider 2 rank data
6231 11:03:25.189782 u2DelayCellTimex100 = 270/100 ps
6232 11:03:25.192717 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 11:03:25.196070 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 11:03:25.199454 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 11:03:25.202678 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 11:03:25.205988 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 11:03:25.209052 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 11:03:25.209489
6239 11:03:25.212494 CA PerBit enable=1, Macro0, CA PI delay=36
6240 11:03:25.212905
6241 11:03:25.215599 [CBTSetCACLKResult] CA Dly = 36
6242 11:03:25.219072 CS Dly: 1 (0~32)
6243 11:03:25.219456
6244 11:03:25.222136 ----->DramcWriteLeveling(PI) begin...
6245 11:03:25.222526 ==
6246 11:03:25.225412 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 11:03:25.229514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 11:03:25.229901 ==
6249 11:03:25.232428 Write leveling (Byte 0): 40 => 8
6250 11:03:25.236098 Write leveling (Byte 1): 40 => 8
6251 11:03:25.238864 DramcWriteLeveling(PI) end<-----
6252 11:03:25.239251
6253 11:03:25.239549 ==
6254 11:03:25.242443 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 11:03:25.245401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 11:03:25.245785 ==
6257 11:03:25.248793 [Gating] SW mode calibration
6258 11:03:25.255601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6259 11:03:25.262144 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6260 11:03:25.265670 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 11:03:25.271710 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 11:03:25.275447 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 11:03:25.278310 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 11:03:25.284735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 11:03:25.287896 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 11:03:25.291461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 11:03:25.298279 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 11:03:25.301234 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 11:03:25.304467 Total UI for P1: 0, mck2ui 16
6270 11:03:25.308028 best dqsien dly found for B0: ( 0, 14, 24)
6271 11:03:25.311197 Total UI for P1: 0, mck2ui 16
6272 11:03:25.314655 best dqsien dly found for B1: ( 0, 14, 24)
6273 11:03:25.317703 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6274 11:03:25.321245 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6275 11:03:25.321637
6276 11:03:25.324168 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6277 11:03:25.327728 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 11:03:25.331315 [Gating] SW calibration Done
6279 11:03:25.331700 ==
6280 11:03:25.334451 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 11:03:25.341042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 11:03:25.341542 ==
6283 11:03:25.341909 RX Vref Scan: 0
6284 11:03:25.342211
6285 11:03:25.344323 RX Vref 0 -> 0, step: 1
6286 11:03:25.344708
6287 11:03:25.347251 RX Delay -410 -> 252, step: 16
6288 11:03:25.350738 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6289 11:03:25.353742 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6290 11:03:25.360387 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6291 11:03:25.363871 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6292 11:03:25.367114 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6293 11:03:25.370420 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6294 11:03:25.377227 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6295 11:03:25.380226 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6296 11:03:25.383508 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6297 11:03:25.387067 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6298 11:03:25.393582 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6299 11:03:25.396797 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6300 11:03:25.400148 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6301 11:03:25.403580 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6302 11:03:25.409854 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6303 11:03:25.413012 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6304 11:03:25.413430 ==
6305 11:03:25.416534 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 11:03:25.420148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 11:03:25.420534 ==
6308 11:03:25.423169 DQS Delay:
6309 11:03:25.423556 DQS0 = 35, DQS1 = 59
6310 11:03:25.426232 DQM Delay:
6311 11:03:25.426735 DQM0 = 4, DQM1 = 17
6312 11:03:25.429519 DQ Delay:
6313 11:03:25.430042 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6314 11:03:25.432641 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6315 11:03:25.436161 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6316 11:03:25.439481 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6317 11:03:25.439856
6318 11:03:25.440176
6319 11:03:25.440485 ==
6320 11:03:25.442531 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 11:03:25.449216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 11:03:25.449511 ==
6323 11:03:25.449722
6324 11:03:25.449915
6325 11:03:25.450101 TX Vref Scan disable
6326 11:03:25.452374 == TX Byte 0 ==
6327 11:03:25.456076 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 11:03:25.459132 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 11:03:25.462676 == TX Byte 1 ==
6330 11:03:25.465821 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 11:03:25.469055 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 11:03:25.472281 ==
6333 11:03:25.475490 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 11:03:25.478713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 11:03:25.479069 ==
6336 11:03:25.479383
6337 11:03:25.479685
6338 11:03:25.481996 TX Vref Scan disable
6339 11:03:25.482285 == TX Byte 0 ==
6340 11:03:25.485661 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 11:03:25.491884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 11:03:25.492158 == TX Byte 1 ==
6343 11:03:25.495175 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 11:03:25.502073 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 11:03:25.502427
6346 11:03:25.502698 [DATLAT]
6347 11:03:25.502968 Freq=400, CH0 RK0
6348 11:03:25.503214
6349 11:03:25.505541 DATLAT Default: 0xf
6350 11:03:25.508451 0, 0xFFFF, sum = 0
6351 11:03:25.508839 1, 0xFFFF, sum = 0
6352 11:03:25.511735 2, 0xFFFF, sum = 0
6353 11:03:25.512136 3, 0xFFFF, sum = 0
6354 11:03:25.515063 4, 0xFFFF, sum = 0
6355 11:03:25.515451 5, 0xFFFF, sum = 0
6356 11:03:25.518492 6, 0xFFFF, sum = 0
6357 11:03:25.518881 7, 0xFFFF, sum = 0
6358 11:03:25.522035 8, 0xFFFF, sum = 0
6359 11:03:25.522425 9, 0xFFFF, sum = 0
6360 11:03:25.524934 10, 0xFFFF, sum = 0
6361 11:03:25.525374 11, 0xFFFF, sum = 0
6362 11:03:25.528347 12, 0xFFFF, sum = 0
6363 11:03:25.528864 13, 0x0, sum = 1
6364 11:03:25.531621 14, 0x0, sum = 2
6365 11:03:25.532012 15, 0x0, sum = 3
6366 11:03:25.534898 16, 0x0, sum = 4
6367 11:03:25.535285 best_step = 14
6368 11:03:25.535580
6369 11:03:25.535853 ==
6370 11:03:25.538416 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 11:03:25.544994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 11:03:25.545546 ==
6373 11:03:25.545860 RX Vref Scan: 1
6374 11:03:25.546142
6375 11:03:25.548469 RX Vref 0 -> 0, step: 1
6376 11:03:25.548847
6377 11:03:25.551522 RX Delay -359 -> 252, step: 8
6378 11:03:25.552052
6379 11:03:25.555123 Set Vref, RX VrefLevel [Byte0]: 53
6380 11:03:25.557910 [Byte1]: 59
6381 11:03:25.558299
6382 11:03:25.561203 Final RX Vref Byte 0 = 53 to rank0
6383 11:03:25.564720 Final RX Vref Byte 1 = 59 to rank0
6384 11:03:25.567860 Final RX Vref Byte 0 = 53 to rank1
6385 11:03:25.571526 Final RX Vref Byte 1 = 59 to rank1==
6386 11:03:25.575083 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 11:03:25.581177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 11:03:25.581596 ==
6389 11:03:25.581903 DQS Delay:
6390 11:03:25.582223 DQS0 = 44, DQS1 = 60
6391 11:03:25.584518 DQM Delay:
6392 11:03:25.584912 DQM0 = 10, DQM1 = 16
6393 11:03:25.587922 DQ Delay:
6394 11:03:25.591207 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6395 11:03:25.594562 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6396 11:03:25.594952 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6397 11:03:25.597937 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6398 11:03:25.601384
6399 11:03:25.601833
6400 11:03:25.607206 [DQSOSCAuto] RK0, (LSB)MR18= 0xa497, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6401 11:03:25.610697 CH0 RK0: MR19=C0C, MR18=A497
6402 11:03:25.617674 CH0_RK0: MR19=0xC0C, MR18=0xA497, DQSOSC=389, MR23=63, INC=390, DEC=260
6403 11:03:25.618066 ==
6404 11:03:25.620486 Dram Type= 6, Freq= 0, CH_0, rank 1
6405 11:03:25.623682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 11:03:25.624077 ==
6407 11:03:25.627226 [Gating] SW mode calibration
6408 11:03:25.633815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6409 11:03:25.640262 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6410 11:03:25.643269 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6411 11:03:25.646768 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 11:03:25.653797 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 11:03:25.656409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 11:03:25.659860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 11:03:25.666607 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 11:03:25.670084 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 11:03:25.673356 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 11:03:25.679477 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 11:03:25.683392 Total UI for P1: 0, mck2ui 16
6420 11:03:25.686715 best dqsien dly found for B0: ( 0, 14, 24)
6421 11:03:25.689602 Total UI for P1: 0, mck2ui 16
6422 11:03:25.693400 best dqsien dly found for B1: ( 0, 14, 24)
6423 11:03:25.696429 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6424 11:03:25.699489 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6425 11:03:25.699891
6426 11:03:25.702667 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6427 11:03:25.706008 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 11:03:25.709359 [Gating] SW calibration Done
6429 11:03:25.709913 ==
6430 11:03:25.713346 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 11:03:25.716078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 11:03:25.716469 ==
6433 11:03:25.719515 RX Vref Scan: 0
6434 11:03:25.719911
6435 11:03:25.722860 RX Vref 0 -> 0, step: 1
6436 11:03:25.723265
6437 11:03:25.725641 RX Delay -410 -> 252, step: 16
6438 11:03:25.729202 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6439 11:03:25.732546 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6440 11:03:25.735609 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6441 11:03:25.742315 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6442 11:03:25.745624 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6443 11:03:25.749049 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6444 11:03:25.751953 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6445 11:03:25.758611 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6446 11:03:25.762224 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6447 11:03:25.765116 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6448 11:03:25.768934 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6449 11:03:25.775319 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6450 11:03:25.778401 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6451 11:03:25.782358 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6452 11:03:25.788587 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6453 11:03:25.791612 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6454 11:03:25.792017 ==
6455 11:03:25.795330 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 11:03:25.798549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 11:03:25.798991 ==
6458 11:03:25.801892 DQS Delay:
6459 11:03:25.802297 DQS0 = 35, DQS1 = 59
6460 11:03:25.802697 DQM Delay:
6461 11:03:25.805253 DQM0 = 6, DQM1 = 16
6462 11:03:25.805660 DQ Delay:
6463 11:03:25.808122 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6464 11:03:25.811741 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6465 11:03:25.815144 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6466 11:03:25.818906 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6467 11:03:25.819392
6468 11:03:25.819723
6469 11:03:25.820011 ==
6470 11:03:25.821192 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 11:03:25.825176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 11:03:25.828169 ==
6473 11:03:25.828569
6474 11:03:25.828968
6475 11:03:25.829402 TX Vref Scan disable
6476 11:03:25.831440 == TX Byte 0 ==
6477 11:03:25.834684 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6478 11:03:25.837902 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6479 11:03:25.841418 == TX Byte 1 ==
6480 11:03:25.844509 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6481 11:03:25.847932 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6482 11:03:25.848338 ==
6483 11:03:25.851175 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 11:03:25.857829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 11:03:25.858236 ==
6486 11:03:25.858631
6487 11:03:25.859000
6488 11:03:25.859362 TX Vref Scan disable
6489 11:03:25.860894 == TX Byte 0 ==
6490 11:03:25.864143 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6491 11:03:25.867395 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6492 11:03:25.870691 == TX Byte 1 ==
6493 11:03:25.874012 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6494 11:03:25.877066 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6495 11:03:25.877656
6496 11:03:25.880587 [DATLAT]
6497 11:03:25.880989 Freq=400, CH0 RK1
6498 11:03:25.881428
6499 11:03:25.883779 DATLAT Default: 0xe
6500 11:03:25.884181 0, 0xFFFF, sum = 0
6501 11:03:25.887425 1, 0xFFFF, sum = 0
6502 11:03:25.887970 2, 0xFFFF, sum = 0
6503 11:03:25.890574 3, 0xFFFF, sum = 0
6504 11:03:25.891100 4, 0xFFFF, sum = 0
6505 11:03:25.893396 5, 0xFFFF, sum = 0
6506 11:03:25.893824 6, 0xFFFF, sum = 0
6507 11:03:25.896673 7, 0xFFFF, sum = 0
6508 11:03:25.900289 8, 0xFFFF, sum = 0
6509 11:03:25.900700 9, 0xFFFF, sum = 0
6510 11:03:25.903781 10, 0xFFFF, sum = 0
6511 11:03:25.904190 11, 0xFFFF, sum = 0
6512 11:03:25.906818 12, 0xFFFF, sum = 0
6513 11:03:25.907229 13, 0x0, sum = 1
6514 11:03:25.910469 14, 0x0, sum = 2
6515 11:03:25.910876 15, 0x0, sum = 3
6516 11:03:25.913368 16, 0x0, sum = 4
6517 11:03:25.913779 best_step = 14
6518 11:03:25.914178
6519 11:03:25.914550 ==
6520 11:03:25.916545 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 11:03:25.920014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 11:03:25.920417 ==
6523 11:03:25.923624 RX Vref Scan: 0
6524 11:03:25.924168
6525 11:03:25.926681 RX Vref 0 -> 0, step: 1
6526 11:03:25.927210
6527 11:03:25.927683 RX Delay -359 -> 252, step: 8
6528 11:03:25.935239 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6529 11:03:25.938664 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6530 11:03:25.942263 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6531 11:03:25.948540 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6532 11:03:25.952170 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6533 11:03:25.955243 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6534 11:03:25.958908 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6535 11:03:25.964947 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6536 11:03:25.968835 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6537 11:03:25.971864 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6538 11:03:25.975145 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6539 11:03:25.981825 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6540 11:03:25.985211 iDelay=209, Bit 12, Center -40 (-287 ~ 208) 496
6541 11:03:25.988290 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6542 11:03:25.991447 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6543 11:03:25.998423 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6544 11:03:25.998825 ==
6545 11:03:26.001426 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 11:03:26.004893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 11:03:26.005379 ==
6548 11:03:26.005692 DQS Delay:
6549 11:03:26.008423 DQS0 = 44, DQS1 = 60
6550 11:03:26.008814 DQM Delay:
6551 11:03:26.011199 DQM0 = 9, DQM1 = 15
6552 11:03:26.011589 DQ Delay:
6553 11:03:26.015129 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6554 11:03:26.017785 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6555 11:03:26.021288 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6556 11:03:26.024730 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6557 11:03:26.025119
6558 11:03:26.025464
6559 11:03:26.034219 [DQSOSCAuto] RK1, (LSB)MR18= 0x968e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6560 11:03:26.034617 CH0 RK1: MR19=C0C, MR18=968E
6561 11:03:26.041082 CH0_RK1: MR19=0xC0C, MR18=0x968E, DQSOSC=391, MR23=63, INC=386, DEC=257
6562 11:03:26.044388 [RxdqsGatingPostProcess] freq 400
6563 11:03:26.050860 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6564 11:03:26.054481 best DQS0 dly(2T, 0.5T) = (0, 10)
6565 11:03:26.057664 best DQS1 dly(2T, 0.5T) = (0, 10)
6566 11:03:26.060912 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6567 11:03:26.064654 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6568 11:03:26.067455 best DQS0 dly(2T, 0.5T) = (0, 10)
6569 11:03:26.067907 best DQS1 dly(2T, 0.5T) = (0, 10)
6570 11:03:26.070539 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6571 11:03:26.073902 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6572 11:03:26.077567 Pre-setting of DQS Precalculation
6573 11:03:26.084043 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6574 11:03:26.084449 ==
6575 11:03:26.087254 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 11:03:26.090407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 11:03:26.090883 ==
6578 11:03:26.096945 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6579 11:03:26.103383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6580 11:03:26.108188 [CA 0] Center 36 (8~64) winsize 57
6581 11:03:26.110575 [CA 1] Center 36 (8~64) winsize 57
6582 11:03:26.113605 [CA 2] Center 36 (8~64) winsize 57
6583 11:03:26.113993 [CA 3] Center 36 (8~64) winsize 57
6584 11:03:26.116951 [CA 4] Center 36 (8~64) winsize 57
6585 11:03:26.119835 [CA 5] Center 36 (8~64) winsize 57
6586 11:03:26.120221
6587 11:03:26.126417 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6588 11:03:26.126803
6589 11:03:26.129744 [CATrainingPosCal] consider 1 rank data
6590 11:03:26.133076 u2DelayCellTimex100 = 270/100 ps
6591 11:03:26.136673 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 11:03:26.139676 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 11:03:26.142914 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 11:03:26.146844 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 11:03:26.149662 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 11:03:26.152900 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 11:03:26.153325
6598 11:03:26.156415 CA PerBit enable=1, Macro0, CA PI delay=36
6599 11:03:26.156978
6600 11:03:26.159458 [CBTSetCACLKResult] CA Dly = 36
6601 11:03:26.162963 CS Dly: 1 (0~32)
6602 11:03:26.163474 ==
6603 11:03:26.166501 Dram Type= 6, Freq= 0, CH_1, rank 1
6604 11:03:26.169643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 11:03:26.170033 ==
6606 11:03:26.175693 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 11:03:26.182852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6608 11:03:26.185683 [CA 0] Center 36 (8~64) winsize 57
6609 11:03:26.186164 [CA 1] Center 36 (8~64) winsize 57
6610 11:03:26.189113 [CA 2] Center 36 (8~64) winsize 57
6611 11:03:26.192476 [CA 3] Center 36 (8~64) winsize 57
6612 11:03:26.195707 [CA 4] Center 36 (8~64) winsize 57
6613 11:03:26.198760 [CA 5] Center 36 (8~64) winsize 57
6614 11:03:26.199313
6615 11:03:26.202625 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6616 11:03:26.203174
6617 11:03:26.208415 [CATrainingPosCal] consider 2 rank data
6618 11:03:26.208492 u2DelayCellTimex100 = 270/100 ps
6619 11:03:26.215639 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 11:03:26.218516 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 11:03:26.221808 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 11:03:26.225227 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 11:03:26.228583 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 11:03:26.231866 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 11:03:26.231941
6626 11:03:26.235118 CA PerBit enable=1, Macro0, CA PI delay=36
6627 11:03:26.235193
6628 11:03:26.238121 [CBTSetCACLKResult] CA Dly = 36
6629 11:03:26.241642 CS Dly: 1 (0~32)
6630 11:03:26.241737
6631 11:03:26.245034 ----->DramcWriteLeveling(PI) begin...
6632 11:03:26.245131 ==
6633 11:03:26.248435 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 11:03:26.251762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 11:03:26.251857 ==
6636 11:03:26.254854 Write leveling (Byte 0): 40 => 8
6637 11:03:26.259033 Write leveling (Byte 1): 40 => 8
6638 11:03:26.261576 DramcWriteLeveling(PI) end<-----
6639 11:03:26.261652
6640 11:03:26.261712 ==
6641 11:03:26.264835 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 11:03:26.267775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:03:26.267872 ==
6644 11:03:26.271475 [Gating] SW mode calibration
6645 11:03:26.277762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6646 11:03:26.284307 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6647 11:03:26.287376 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 11:03:26.290944 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 11:03:26.297467 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 11:03:26.300892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 11:03:26.304262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 11:03:26.310830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 11:03:26.314096 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 11:03:26.317782 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 11:03:26.323998 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 11:03:26.327468 Total UI for P1: 0, mck2ui 16
6657 11:03:26.330942 best dqsien dly found for B0: ( 0, 14, 24)
6658 11:03:26.333577 Total UI for P1: 0, mck2ui 16
6659 11:03:26.336834 best dqsien dly found for B1: ( 0, 14, 24)
6660 11:03:26.340351 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6661 11:03:26.343553 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6662 11:03:26.343629
6663 11:03:26.346855 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6664 11:03:26.350102 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 11:03:26.353315 [Gating] SW calibration Done
6666 11:03:26.353390 ==
6667 11:03:26.357283 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 11:03:26.360323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 11:03:26.360423 ==
6670 11:03:26.363508 RX Vref Scan: 0
6671 11:03:26.363624
6672 11:03:26.367016 RX Vref 0 -> 0, step: 1
6673 11:03:26.367110
6674 11:03:26.369790 RX Delay -410 -> 252, step: 16
6675 11:03:26.373212 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6676 11:03:26.376509 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6677 11:03:26.380315 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6678 11:03:26.386840 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6679 11:03:26.390405 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6680 11:03:26.393439 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6681 11:03:26.397015 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6682 11:03:26.403128 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6683 11:03:26.406327 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6684 11:03:26.409780 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6685 11:03:26.413144 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6686 11:03:26.420534 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6687 11:03:26.423056 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6688 11:03:26.426464 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6689 11:03:26.429677 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6690 11:03:26.436016 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6691 11:03:26.436092 ==
6692 11:03:26.439406 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 11:03:26.443049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 11:03:26.443143 ==
6695 11:03:26.443202 DQS Delay:
6696 11:03:26.445950 DQS0 = 43, DQS1 = 51
6697 11:03:26.446025 DQM Delay:
6698 11:03:26.449405 DQM0 = 13, DQM1 = 13
6699 11:03:26.449479 DQ Delay:
6700 11:03:26.452917 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6701 11:03:26.456337 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6702 11:03:26.459631 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6703 11:03:26.462785 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6704 11:03:26.462861
6705 11:03:26.462920
6706 11:03:26.462974 ==
6707 11:03:26.466202 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 11:03:26.469624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 11:03:26.469723 ==
6710 11:03:26.472233
6711 11:03:26.472307
6712 11:03:26.472365 TX Vref Scan disable
6713 11:03:26.475925 == TX Byte 0 ==
6714 11:03:26.478777 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 11:03:26.482604 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 11:03:26.485788 == TX Byte 1 ==
6717 11:03:26.488742 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 11:03:26.492369 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 11:03:26.492466 ==
6720 11:03:26.495471 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 11:03:26.501953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 11:03:26.502052 ==
6723 11:03:26.502139
6724 11:03:26.502223
6725 11:03:26.502305 TX Vref Scan disable
6726 11:03:26.505107 == TX Byte 0 ==
6727 11:03:26.508816 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 11:03:26.512231 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 11:03:26.515559 == TX Byte 1 ==
6730 11:03:26.518829 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 11:03:26.522244 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 11:03:26.522320
6733 11:03:26.525519 [DATLAT]
6734 11:03:26.525594 Freq=400, CH1 RK0
6735 11:03:26.525653
6736 11:03:26.528340 DATLAT Default: 0xf
6737 11:03:26.528445 0, 0xFFFF, sum = 0
6738 11:03:26.531796 1, 0xFFFF, sum = 0
6739 11:03:26.531897 2, 0xFFFF, sum = 0
6740 11:03:26.534876 3, 0xFFFF, sum = 0
6741 11:03:26.534960 4, 0xFFFF, sum = 0
6742 11:03:26.538001 5, 0xFFFF, sum = 0
6743 11:03:26.538078 6, 0xFFFF, sum = 0
6744 11:03:26.542251 7, 0xFFFF, sum = 0
6745 11:03:26.542329 8, 0xFFFF, sum = 0
6746 11:03:26.544997 9, 0xFFFF, sum = 0
6747 11:03:26.548135 10, 0xFFFF, sum = 0
6748 11:03:26.548212 11, 0xFFFF, sum = 0
6749 11:03:26.551306 12, 0xFFFF, sum = 0
6750 11:03:26.551383 13, 0x0, sum = 1
6751 11:03:26.554496 14, 0x0, sum = 2
6752 11:03:26.554573 15, 0x0, sum = 3
6753 11:03:26.558487 16, 0x0, sum = 4
6754 11:03:26.558563 best_step = 14
6755 11:03:26.558622
6756 11:03:26.558675 ==
6757 11:03:26.561342 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 11:03:26.564997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 11:03:26.565097 ==
6760 11:03:26.567929 RX Vref Scan: 1
6761 11:03:26.568004
6762 11:03:26.571378 RX Vref 0 -> 0, step: 1
6763 11:03:26.571453
6764 11:03:26.571512 RX Delay -343 -> 252, step: 8
6765 11:03:26.571566
6766 11:03:26.574694 Set Vref, RX VrefLevel [Byte0]: 52
6767 11:03:26.577811 [Byte1]: 52
6768 11:03:26.583759
6769 11:03:26.583834 Final RX Vref Byte 0 = 52 to rank0
6770 11:03:26.586453 Final RX Vref Byte 1 = 52 to rank0
6771 11:03:26.590084 Final RX Vref Byte 0 = 52 to rank1
6772 11:03:26.593478 Final RX Vref Byte 1 = 52 to rank1==
6773 11:03:26.597061 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 11:03:26.603080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 11:03:26.603156 ==
6776 11:03:26.603215 DQS Delay:
6777 11:03:26.606790 DQS0 = 44, DQS1 = 52
6778 11:03:26.606866 DQM Delay:
6779 11:03:26.606925 DQM0 = 11, DQM1 = 10
6780 11:03:26.609666 DQ Delay:
6781 11:03:26.612912 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6782 11:03:26.616533 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6783 11:03:26.616612 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6784 11:03:26.619399 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6785 11:03:26.622952
6786 11:03:26.623050
6787 11:03:26.629816 [DQSOSCAuto] RK0, (LSB)MR18= 0x7ba2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
6788 11:03:26.632877 CH1 RK0: MR19=C0C, MR18=7BA2
6789 11:03:26.640038 CH1_RK0: MR19=0xC0C, MR18=0x7BA2, DQSOSC=389, MR23=63, INC=390, DEC=260
6790 11:03:26.640113 ==
6791 11:03:26.642707 Dram Type= 6, Freq= 0, CH_1, rank 1
6792 11:03:26.646038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 11:03:26.646115 ==
6794 11:03:26.649669 [Gating] SW mode calibration
6795 11:03:26.655808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6796 11:03:26.662495 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6797 11:03:26.665690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6798 11:03:26.669222 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 11:03:26.675347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 11:03:26.679031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 11:03:26.682066 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 11:03:26.688807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 11:03:26.692139 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 11:03:26.695543 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 11:03:26.702389 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 11:03:26.705764 Total UI for P1: 0, mck2ui 16
6807 11:03:26.708363 best dqsien dly found for B0: ( 0, 14, 24)
6808 11:03:26.712343 Total UI for P1: 0, mck2ui 16
6809 11:03:26.715255 best dqsien dly found for B1: ( 0, 14, 24)
6810 11:03:26.718626 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6811 11:03:26.722104 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6812 11:03:26.722187
6813 11:03:26.724957 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6814 11:03:26.728059 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 11:03:26.731474 [Gating] SW calibration Done
6816 11:03:26.731561 ==
6817 11:03:26.735035 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 11:03:26.738306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 11:03:26.738390 ==
6820 11:03:26.741596 RX Vref Scan: 0
6821 11:03:26.741678
6822 11:03:26.744447 RX Vref 0 -> 0, step: 1
6823 11:03:26.744524
6824 11:03:26.744583 RX Delay -410 -> 252, step: 16
6825 11:03:26.751682 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6826 11:03:26.754587 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6827 11:03:26.758205 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6828 11:03:26.765059 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6829 11:03:26.768126 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6830 11:03:26.771059 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6831 11:03:26.774812 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6832 11:03:26.780961 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6833 11:03:26.784348 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6834 11:03:26.788232 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6835 11:03:26.790976 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6836 11:03:26.797647 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6837 11:03:26.800903 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6838 11:03:26.804173 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6839 11:03:26.807724 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6840 11:03:26.814251 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6841 11:03:26.814352 ==
6842 11:03:26.817544 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 11:03:26.820883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 11:03:26.820967 ==
6845 11:03:26.821027 DQS Delay:
6846 11:03:26.824317 DQS0 = 43, DQS1 = 51
6847 11:03:26.824398 DQM Delay:
6848 11:03:26.827372 DQM0 = 10, DQM1 = 15
6849 11:03:26.827453 DQ Delay:
6850 11:03:26.830461 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6851 11:03:26.833917 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6852 11:03:26.837316 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6853 11:03:26.840605 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6854 11:03:26.840681
6855 11:03:26.840741
6856 11:03:26.840815 ==
6857 11:03:26.843727 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 11:03:26.846797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 11:03:26.850317 ==
6860 11:03:26.850393
6861 11:03:26.850451
6862 11:03:26.850506 TX Vref Scan disable
6863 11:03:26.854144 == TX Byte 0 ==
6864 11:03:26.857043 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6865 11:03:26.860408 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6866 11:03:26.863619 == TX Byte 1 ==
6867 11:03:26.866821 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6868 11:03:26.870703 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6869 11:03:26.870781 ==
6870 11:03:26.873436 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 11:03:26.876833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 11:03:26.880125 ==
6873 11:03:26.880200
6874 11:03:26.880266
6875 11:03:26.880333 TX Vref Scan disable
6876 11:03:26.883050 == TX Byte 0 ==
6877 11:03:26.886683 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6878 11:03:26.890036 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6879 11:03:26.893506 == TX Byte 1 ==
6880 11:03:26.896643 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6881 11:03:26.899966 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6882 11:03:26.900045
6883 11:03:26.902974 [DATLAT]
6884 11:03:26.903050 Freq=400, CH1 RK1
6885 11:03:26.903109
6886 11:03:26.906671 DATLAT Default: 0xe
6887 11:03:26.906746 0, 0xFFFF, sum = 0
6888 11:03:26.909667 1, 0xFFFF, sum = 0
6889 11:03:26.909764 2, 0xFFFF, sum = 0
6890 11:03:26.912937 3, 0xFFFF, sum = 0
6891 11:03:26.913014 4, 0xFFFF, sum = 0
6892 11:03:26.916206 5, 0xFFFF, sum = 0
6893 11:03:26.916283 6, 0xFFFF, sum = 0
6894 11:03:26.919751 7, 0xFFFF, sum = 0
6895 11:03:26.919827 8, 0xFFFF, sum = 0
6896 11:03:26.922847 9, 0xFFFF, sum = 0
6897 11:03:26.922924 10, 0xFFFF, sum = 0
6898 11:03:26.926074 11, 0xFFFF, sum = 0
6899 11:03:26.929469 12, 0xFFFF, sum = 0
6900 11:03:26.929546 13, 0x0, sum = 1
6901 11:03:26.929607 14, 0x0, sum = 2
6902 11:03:26.933174 15, 0x0, sum = 3
6903 11:03:26.933266 16, 0x0, sum = 4
6904 11:03:26.936179 best_step = 14
6905 11:03:26.936254
6906 11:03:26.936313 ==
6907 11:03:26.939175 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 11:03:26.942671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 11:03:26.942747 ==
6910 11:03:26.946014 RX Vref Scan: 0
6911 11:03:26.946089
6912 11:03:26.946147 RX Vref 0 -> 0, step: 1
6913 11:03:26.949434
6914 11:03:26.949509 RX Delay -343 -> 252, step: 8
6915 11:03:26.957753 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6916 11:03:26.960853 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6917 11:03:26.964642 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6918 11:03:26.970519 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6919 11:03:26.974172 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6920 11:03:26.977457 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6921 11:03:26.980802 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6922 11:03:26.986940 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6923 11:03:26.990656 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6924 11:03:26.994036 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6925 11:03:26.997247 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6926 11:03:27.003849 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6927 11:03:27.007304 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6928 11:03:27.010150 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6929 11:03:27.013641 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6930 11:03:27.020433 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6931 11:03:27.020509 ==
6932 11:03:27.023511 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 11:03:27.027136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 11:03:27.027214 ==
6935 11:03:27.027273 DQS Delay:
6936 11:03:27.030520 DQS0 = 48, DQS1 = 52
6937 11:03:27.030586 DQM Delay:
6938 11:03:27.033905 DQM0 = 11, DQM1 = 10
6939 11:03:27.033980 DQ Delay:
6940 11:03:27.036659 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6941 11:03:27.040275 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6942 11:03:27.043229 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6943 11:03:27.046460 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6944 11:03:27.046551
6945 11:03:27.046624
6946 11:03:27.056549 [DQSOSCAuto] RK1, (LSB)MR18= 0x7db5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6947 11:03:27.056649 CH1 RK1: MR19=C0C, MR18=7DB5
6948 11:03:27.062969 CH1_RK1: MR19=0xC0C, MR18=0x7DB5, DQSOSC=387, MR23=63, INC=394, DEC=262
6949 11:03:27.066496 [RxdqsGatingPostProcess] freq 400
6950 11:03:27.072900 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6951 11:03:27.076181 best DQS0 dly(2T, 0.5T) = (0, 10)
6952 11:03:27.079612 best DQS1 dly(2T, 0.5T) = (0, 10)
6953 11:03:27.082748 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6954 11:03:27.085938 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6955 11:03:27.089399 best DQS0 dly(2T, 0.5T) = (0, 10)
6956 11:03:27.092901 best DQS1 dly(2T, 0.5T) = (0, 10)
6957 11:03:27.096114 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6958 11:03:27.099164 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6959 11:03:27.099241 Pre-setting of DQS Precalculation
6960 11:03:27.105619 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6961 11:03:27.112323 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6962 11:03:27.119280 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6963 11:03:27.119355
6964 11:03:27.119413
6965 11:03:27.121944 [Calibration Summary] 800 Mbps
6966 11:03:27.125681 CH 0, Rank 0
6967 11:03:27.125756 SW Impedance : PASS
6968 11:03:27.128909 DUTY Scan : NO K
6969 11:03:27.131956 ZQ Calibration : PASS
6970 11:03:27.132032 Jitter Meter : NO K
6971 11:03:27.135429 CBT Training : PASS
6972 11:03:27.138737 Write leveling : PASS
6973 11:03:27.138814 RX DQS gating : PASS
6974 11:03:27.141916 RX DQ/DQS(RDDQC) : PASS
6975 11:03:27.145052 TX DQ/DQS : PASS
6976 11:03:27.145163 RX DATLAT : PASS
6977 11:03:27.148591 RX DQ/DQS(Engine): PASS
6978 11:03:27.152071 TX OE : NO K
6979 11:03:27.152171 All Pass.
6980 11:03:27.152261
6981 11:03:27.152354 CH 0, Rank 1
6982 11:03:27.155107 SW Impedance : PASS
6983 11:03:27.158834 DUTY Scan : NO K
6984 11:03:27.158922 ZQ Calibration : PASS
6985 11:03:27.161581 Jitter Meter : NO K
6986 11:03:27.165232 CBT Training : PASS
6987 11:03:27.165308 Write leveling : NO K
6988 11:03:27.168226 RX DQS gating : PASS
6989 11:03:27.168302 RX DQ/DQS(RDDQC) : PASS
6990 11:03:27.171805 TX DQ/DQS : PASS
6991 11:03:27.174767 RX DATLAT : PASS
6992 11:03:27.174842 RX DQ/DQS(Engine): PASS
6993 11:03:27.178539 TX OE : NO K
6994 11:03:27.178615 All Pass.
6995 11:03:27.178673
6996 11:03:27.181424 CH 1, Rank 0
6997 11:03:27.181499 SW Impedance : PASS
6998 11:03:27.184463 DUTY Scan : NO K
6999 11:03:27.187992 ZQ Calibration : PASS
7000 11:03:27.188067 Jitter Meter : NO K
7001 11:03:27.191182 CBT Training : PASS
7002 11:03:27.194440 Write leveling : PASS
7003 11:03:27.194540 RX DQS gating : PASS
7004 11:03:27.197569 RX DQ/DQS(RDDQC) : PASS
7005 11:03:27.200954 TX DQ/DQS : PASS
7006 11:03:27.201029 RX DATLAT : PASS
7007 11:03:27.204885 RX DQ/DQS(Engine): PASS
7008 11:03:27.207803 TX OE : NO K
7009 11:03:27.207879 All Pass.
7010 11:03:27.207938
7011 11:03:27.207992 CH 1, Rank 1
7012 11:03:27.211227 SW Impedance : PASS
7013 11:03:27.214194 DUTY Scan : NO K
7014 11:03:27.214269 ZQ Calibration : PASS
7015 11:03:27.217293 Jitter Meter : NO K
7016 11:03:27.220829 CBT Training : PASS
7017 11:03:27.220904 Write leveling : NO K
7018 11:03:27.223981 RX DQS gating : PASS
7019 11:03:27.227558 RX DQ/DQS(RDDQC) : PASS
7020 11:03:27.227634 TX DQ/DQS : PASS
7021 11:03:27.230559 RX DATLAT : PASS
7022 11:03:27.233922 RX DQ/DQS(Engine): PASS
7023 11:03:27.233997 TX OE : NO K
7024 11:03:27.237383 All Pass.
7025 11:03:27.237467
7026 11:03:27.237526 DramC Write-DBI off
7027 11:03:27.240933 PER_BANK_REFRESH: Hybrid Mode
7028 11:03:27.241008 TX_TRACKING: ON
7029 11:03:27.250573 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7030 11:03:27.253736 [FAST_K] Save calibration result to emmc
7031 11:03:27.257327 dramc_set_vcore_voltage set vcore to 725000
7032 11:03:27.260531 Read voltage for 1600, 0
7033 11:03:27.260605 Vio18 = 0
7034 11:03:27.263756 Vcore = 725000
7035 11:03:27.263831 Vdram = 0
7036 11:03:27.263891 Vddq = 0
7037 11:03:27.267261 Vmddr = 0
7038 11:03:27.270249 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7039 11:03:27.276807 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7040 11:03:27.276884 MEM_TYPE=3, freq_sel=13
7041 11:03:27.279937 sv_algorithm_assistance_LP4_3733
7042 11:03:27.287091 ============ PULL DRAM RESETB DOWN ============
7043 11:03:27.289961 ========== PULL DRAM RESETB DOWN end =========
7044 11:03:27.292937 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7045 11:03:27.296233 ===================================
7046 11:03:27.300157 LPDDR4 DRAM CONFIGURATION
7047 11:03:27.302777 ===================================
7048 11:03:27.306224 EX_ROW_EN[0] = 0x0
7049 11:03:27.306299 EX_ROW_EN[1] = 0x0
7050 11:03:27.309674 LP4Y_EN = 0x0
7051 11:03:27.309749 WORK_FSP = 0x1
7052 11:03:27.312658 WL = 0x5
7053 11:03:27.312733 RL = 0x5
7054 11:03:27.316313 BL = 0x2
7055 11:03:27.316387 RPST = 0x0
7056 11:03:27.319704 RD_PRE = 0x0
7057 11:03:27.319780 WR_PRE = 0x1
7058 11:03:27.322491 WR_PST = 0x1
7059 11:03:27.322566 DBI_WR = 0x0
7060 11:03:27.326118 DBI_RD = 0x0
7061 11:03:27.326202 OTF = 0x1
7062 11:03:27.329730 ===================================
7063 11:03:27.332610 ===================================
7064 11:03:27.335868 ANA top config
7065 11:03:27.339598 ===================================
7066 11:03:27.342445 DLL_ASYNC_EN = 0
7067 11:03:27.342520 ALL_SLAVE_EN = 0
7068 11:03:27.346109 NEW_RANK_MODE = 1
7069 11:03:27.349512 DLL_IDLE_MODE = 1
7070 11:03:27.352621 LP45_APHY_COMB_EN = 1
7071 11:03:27.355951 TX_ODT_DIS = 0
7072 11:03:27.356027 NEW_8X_MODE = 1
7073 11:03:27.359132 ===================================
7074 11:03:27.362518 ===================================
7075 11:03:27.365753 data_rate = 3200
7076 11:03:27.368878 CKR = 1
7077 11:03:27.372272 DQ_P2S_RATIO = 8
7078 11:03:27.375625 ===================================
7079 11:03:27.379044 CA_P2S_RATIO = 8
7080 11:03:27.381909 DQ_CA_OPEN = 0
7081 11:03:27.381984 DQ_SEMI_OPEN = 0
7082 11:03:27.385326 CA_SEMI_OPEN = 0
7083 11:03:27.388797 CA_FULL_RATE = 0
7084 11:03:27.392144 DQ_CKDIV4_EN = 0
7085 11:03:27.395268 CA_CKDIV4_EN = 0
7086 11:03:27.398430 CA_PREDIV_EN = 0
7087 11:03:27.398507 PH8_DLY = 12
7088 11:03:27.402196 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7089 11:03:27.405105 DQ_AAMCK_DIV = 4
7090 11:03:27.408464 CA_AAMCK_DIV = 4
7091 11:03:27.412203 CA_ADMCK_DIV = 4
7092 11:03:27.415081 DQ_TRACK_CA_EN = 0
7093 11:03:27.418501 CA_PICK = 1600
7094 11:03:27.418577 CA_MCKIO = 1600
7095 11:03:27.421434 MCKIO_SEMI = 0
7096 11:03:27.424931 PLL_FREQ = 3068
7097 11:03:27.428262 DQ_UI_PI_RATIO = 32
7098 11:03:27.431528 CA_UI_PI_RATIO = 0
7099 11:03:27.434739 ===================================
7100 11:03:27.438279 ===================================
7101 11:03:27.441323 memory_type:LPDDR4
7102 11:03:27.441398 GP_NUM : 10
7103 11:03:27.445054 SRAM_EN : 1
7104 11:03:27.447883 MD32_EN : 0
7105 11:03:27.451218 ===================================
7106 11:03:27.451294 [ANA_INIT] >>>>>>>>>>>>>>
7107 11:03:27.454602 <<<<<< [CONFIGURE PHASE]: ANA_TX
7108 11:03:27.458068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7109 11:03:27.461202 ===================================
7110 11:03:27.464756 data_rate = 3200,PCW = 0X7600
7111 11:03:27.467964 ===================================
7112 11:03:27.471341 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7113 11:03:27.477466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7114 11:03:27.481378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 11:03:27.487489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7116 11:03:27.490782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7117 11:03:27.493860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7118 11:03:27.497397 [ANA_INIT] flow start
7119 11:03:27.497493 [ANA_INIT] PLL >>>>>>>>
7120 11:03:27.500857 [ANA_INIT] PLL <<<<<<<<
7121 11:03:27.504331 [ANA_INIT] MIDPI >>>>>>>>
7122 11:03:27.504427 [ANA_INIT] MIDPI <<<<<<<<
7123 11:03:27.507279 [ANA_INIT] DLL >>>>>>>>
7124 11:03:27.510820 [ANA_INIT] DLL <<<<<<<<
7125 11:03:27.510916 [ANA_INIT] flow end
7126 11:03:27.517102 ============ LP4 DIFF to SE enter ============
7127 11:03:27.520404 ============ LP4 DIFF to SE exit ============
7128 11:03:27.523619 [ANA_INIT] <<<<<<<<<<<<<
7129 11:03:27.526910 [Flow] Enable top DCM control >>>>>
7130 11:03:27.527008 [Flow] Enable top DCM control <<<<<
7131 11:03:27.530534 Enable DLL master slave shuffle
7132 11:03:27.537112 ==============================================================
7133 11:03:27.540157 Gating Mode config
7134 11:03:27.543208 ==============================================================
7135 11:03:27.546564 Config description:
7136 11:03:27.556320 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7137 11:03:27.563549 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7138 11:03:27.566321 SELPH_MODE 0: By rank 1: By Phase
7139 11:03:27.573018 ==============================================================
7140 11:03:27.576284 GAT_TRACK_EN = 1
7141 11:03:27.579571 RX_GATING_MODE = 2
7142 11:03:27.583272 RX_GATING_TRACK_MODE = 2
7143 11:03:27.586683 SELPH_MODE = 1
7144 11:03:27.586797 PICG_EARLY_EN = 1
7145 11:03:27.589370 VALID_LAT_VALUE = 1
7146 11:03:27.596140 ==============================================================
7147 11:03:27.599419 Enter into Gating configuration >>>>
7148 11:03:27.603317 Exit from Gating configuration <<<<
7149 11:03:27.606158 Enter into DVFS_PRE_config >>>>>
7150 11:03:27.616302 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7151 11:03:27.619393 Exit from DVFS_PRE_config <<<<<
7152 11:03:27.622197 Enter into PICG configuration >>>>
7153 11:03:27.625867 Exit from PICG configuration <<<<
7154 11:03:27.629064 [RX_INPUT] configuration >>>>>
7155 11:03:27.632359 [RX_INPUT] configuration <<<<<
7156 11:03:27.639066 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7157 11:03:27.642082 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7158 11:03:27.648592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 11:03:27.655638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 11:03:27.661741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 11:03:27.669000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 11:03:27.671930 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7163 11:03:27.675324 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7164 11:03:27.678826 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7165 11:03:27.685109 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7166 11:03:27.688300 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7167 11:03:27.692177 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 11:03:27.694884 ===================================
7169 11:03:27.698446 LPDDR4 DRAM CONFIGURATION
7170 11:03:27.701629 ===================================
7171 11:03:27.704855 EX_ROW_EN[0] = 0x0
7172 11:03:27.704931 EX_ROW_EN[1] = 0x0
7173 11:03:27.708437 LP4Y_EN = 0x0
7174 11:03:27.708512 WORK_FSP = 0x1
7175 11:03:27.711766 WL = 0x5
7176 11:03:27.711842 RL = 0x5
7177 11:03:27.714902 BL = 0x2
7178 11:03:27.714978 RPST = 0x0
7179 11:03:27.717980 RD_PRE = 0x0
7180 11:03:27.718055 WR_PRE = 0x1
7181 11:03:27.721598 WR_PST = 0x1
7182 11:03:27.721675 DBI_WR = 0x0
7183 11:03:27.724830 DBI_RD = 0x0
7184 11:03:27.724905 OTF = 0x1
7185 11:03:27.728252 ===================================
7186 11:03:27.734380 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7187 11:03:27.737559 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7188 11:03:27.740958 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7189 11:03:27.744193 ===================================
7190 11:03:27.747637 LPDDR4 DRAM CONFIGURATION
7191 11:03:27.751062 ===================================
7192 11:03:27.754485 EX_ROW_EN[0] = 0x10
7193 11:03:27.754561 EX_ROW_EN[1] = 0x0
7194 11:03:27.758244 LP4Y_EN = 0x0
7195 11:03:27.758321 WORK_FSP = 0x1
7196 11:03:27.761172 WL = 0x5
7197 11:03:27.761249 RL = 0x5
7198 11:03:27.764487 BL = 0x2
7199 11:03:27.764594 RPST = 0x0
7200 11:03:27.767523 RD_PRE = 0x0
7201 11:03:27.767599 WR_PRE = 0x1
7202 11:03:27.770680 WR_PST = 0x1
7203 11:03:27.770757 DBI_WR = 0x0
7204 11:03:27.774206 DBI_RD = 0x0
7205 11:03:27.774281 OTF = 0x1
7206 11:03:27.777127 ===================================
7207 11:03:27.783981 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7208 11:03:27.784058 ==
7209 11:03:27.787263 Dram Type= 6, Freq= 0, CH_0, rank 0
7210 11:03:27.794118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7211 11:03:27.794194 ==
7212 11:03:27.794253 [Duty_Offset_Calibration]
7213 11:03:27.797261 B0:2 B1:0 CA:4
7214 11:03:27.797337
7215 11:03:27.800300 [DutyScan_Calibration_Flow] k_type=0
7216 11:03:27.808866
7217 11:03:27.808941 ==CLK 0==
7218 11:03:27.812291 Final CLK duty delay cell = -4
7219 11:03:27.815801 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7220 11:03:27.818963 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7221 11:03:27.821942 [-4] AVG Duty = 4922%(X100)
7222 11:03:27.822018
7223 11:03:27.825608 CH0 CLK Duty spec in!! Max-Min= 156%
7224 11:03:27.828711 [DutyScan_Calibration_Flow] ====Done====
7225 11:03:27.828788
7226 11:03:27.832303 [DutyScan_Calibration_Flow] k_type=1
7227 11:03:27.849386
7228 11:03:27.849463 ==DQS 0 ==
7229 11:03:27.852613 Final DQS duty delay cell = 0
7230 11:03:27.856201 [0] MAX Duty = 5249%(X100), DQS PI = 38
7231 11:03:27.858983 [0] MIN Duty = 5093%(X100), DQS PI = 12
7232 11:03:27.862661 [0] AVG Duty = 5171%(X100)
7233 11:03:27.862736
7234 11:03:27.862796 ==DQS 1 ==
7235 11:03:27.865860 Final DQS duty delay cell = 0
7236 11:03:27.869124 [0] MAX Duty = 5187%(X100), DQS PI = 0
7237 11:03:27.872205 [0] MIN Duty = 4969%(X100), DQS PI = 10
7238 11:03:27.876066 [0] AVG Duty = 5078%(X100)
7239 11:03:27.876141
7240 11:03:27.879258 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7241 11:03:27.879333
7242 11:03:27.881965 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7243 11:03:27.885430 [DutyScan_Calibration_Flow] ====Done====
7244 11:03:27.885505
7245 11:03:27.888734 [DutyScan_Calibration_Flow] k_type=3
7246 11:03:27.906955
7247 11:03:27.907032 ==DQM 0 ==
7248 11:03:27.909998 Final DQM duty delay cell = 0
7249 11:03:27.913083 [0] MAX Duty = 5124%(X100), DQS PI = 22
7250 11:03:27.916822 [0] MIN Duty = 4844%(X100), DQS PI = 56
7251 11:03:27.919673 [0] AVG Duty = 4984%(X100)
7252 11:03:27.919748
7253 11:03:27.919807 ==DQM 1 ==
7254 11:03:27.923000 Final DQM duty delay cell = 0
7255 11:03:27.926420 [0] MAX Duty = 5000%(X100), DQS PI = 2
7256 11:03:27.929803 [0] MIN Duty = 4844%(X100), DQS PI = 16
7257 11:03:27.932746 [0] AVG Duty = 4922%(X100)
7258 11:03:27.932821
7259 11:03:27.936083 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7260 11:03:27.936159
7261 11:03:27.939879 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7262 11:03:27.942914 [DutyScan_Calibration_Flow] ====Done====
7263 11:03:27.942989
7264 11:03:27.946564 [DutyScan_Calibration_Flow] k_type=2
7265 11:03:27.963595
7266 11:03:27.963675 ==DQ 0 ==
7267 11:03:27.967158 Final DQ duty delay cell = 0
7268 11:03:27.969965 [0] MAX Duty = 5156%(X100), DQS PI = 22
7269 11:03:27.973392 [0] MIN Duty = 4938%(X100), DQS PI = 12
7270 11:03:27.976737 [0] AVG Duty = 5047%(X100)
7271 11:03:27.976813
7272 11:03:27.976871 ==DQ 1 ==
7273 11:03:27.979952 Final DQ duty delay cell = 0
7274 11:03:27.983480 [0] MAX Duty = 5187%(X100), DQS PI = 2
7275 11:03:27.986903 [0] MIN Duty = 4907%(X100), DQS PI = 32
7276 11:03:27.986979 [0] AVG Duty = 5047%(X100)
7277 11:03:27.990232
7278 11:03:27.993319 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7279 11:03:27.993394
7280 11:03:27.996652 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7281 11:03:28.000324 [DutyScan_Calibration_Flow] ====Done====
7282 11:03:28.000424 ==
7283 11:03:28.003336 Dram Type= 6, Freq= 0, CH_1, rank 0
7284 11:03:28.007098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 11:03:28.007175 ==
7286 11:03:28.009844 [Duty_Offset_Calibration]
7287 11:03:28.009919 B0:0 B1:-1 CA:3
7288 11:03:28.009978
7289 11:03:28.013176 [DutyScan_Calibration_Flow] k_type=0
7290 11:03:28.023100
7291 11:03:28.023175 ==CLK 0==
7292 11:03:28.026921 Final CLK duty delay cell = -4
7293 11:03:28.029577 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7294 11:03:28.033032 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7295 11:03:28.036408 [-4] AVG Duty = 4906%(X100)
7296 11:03:28.036483
7297 11:03:28.039798 CH1 CLK Duty spec in!! Max-Min= 187%
7298 11:03:28.042629 [DutyScan_Calibration_Flow] ====Done====
7299 11:03:28.042730
7300 11:03:28.046181 [DutyScan_Calibration_Flow] k_type=1
7301 11:03:28.062546
7302 11:03:28.062624 ==DQS 0 ==
7303 11:03:28.065349 Final DQS duty delay cell = 0
7304 11:03:28.068810 [0] MAX Duty = 5218%(X100), DQS PI = 20
7305 11:03:28.072150 [0] MIN Duty = 4907%(X100), DQS PI = 60
7306 11:03:28.075295 [0] AVG Duty = 5062%(X100)
7307 11:03:28.075387
7308 11:03:28.075474 ==DQS 1 ==
7309 11:03:28.078967 Final DQS duty delay cell = -4
7310 11:03:28.082028 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7311 11:03:28.085723 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7312 11:03:28.088934 [-4] AVG Duty = 4906%(X100)
7313 11:03:28.089025
7314 11:03:28.091927 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7315 11:03:28.092016
7316 11:03:28.095233 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7317 11:03:28.098741 [DutyScan_Calibration_Flow] ====Done====
7318 11:03:28.098834
7319 11:03:28.101815 [DutyScan_Calibration_Flow] k_type=3
7320 11:03:28.119535
7321 11:03:28.119610 ==DQM 0 ==
7322 11:03:28.122666 Final DQM duty delay cell = 0
7323 11:03:28.125899 [0] MAX Duty = 5062%(X100), DQS PI = 30
7324 11:03:28.129521 [0] MIN Duty = 4782%(X100), DQS PI = 40
7325 11:03:28.132577 [0] AVG Duty = 4922%(X100)
7326 11:03:28.132668
7327 11:03:28.132750 ==DQM 1 ==
7328 11:03:28.136511 Final DQM duty delay cell = 0
7329 11:03:28.139184 [0] MAX Duty = 4969%(X100), DQS PI = 32
7330 11:03:28.142538 [0] MIN Duty = 4813%(X100), DQS PI = 60
7331 11:03:28.145600 [0] AVG Duty = 4891%(X100)
7332 11:03:28.145674
7333 11:03:28.149193 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7334 11:03:28.149290
7335 11:03:28.152401 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7336 11:03:28.155802 [DutyScan_Calibration_Flow] ====Done====
7337 11:03:28.155896
7338 11:03:28.159326 [DutyScan_Calibration_Flow] k_type=2
7339 11:03:28.175254
7340 11:03:28.175354 ==DQ 0 ==
7341 11:03:28.178677 Final DQ duty delay cell = -4
7342 11:03:28.182118 [-4] MAX Duty = 4938%(X100), DQS PI = 32
7343 11:03:28.185236 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7344 11:03:28.188854 [-4] AVG Duty = 4875%(X100)
7345 11:03:28.188944
7346 11:03:28.189030 ==DQ 1 ==
7347 11:03:28.191780 Final DQ duty delay cell = 0
7348 11:03:28.195519 [0] MAX Duty = 5031%(X100), DQS PI = 32
7349 11:03:28.198901 [0] MIN Duty = 4844%(X100), DQS PI = 58
7350 11:03:28.202080 [0] AVG Duty = 4937%(X100)
7351 11:03:28.202181
7352 11:03:28.205279 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7353 11:03:28.205344
7354 11:03:28.208515 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7355 11:03:28.211698 [DutyScan_Calibration_Flow] ====Done====
7356 11:03:28.215268 nWR fixed to 30
7357 11:03:28.218418 [ModeRegInit_LP4] CH0 RK0
7358 11:03:28.218513 [ModeRegInit_LP4] CH0 RK1
7359 11:03:28.221570 [ModeRegInit_LP4] CH1 RK0
7360 11:03:28.224953 [ModeRegInit_LP4] CH1 RK1
7361 11:03:28.225046 match AC timing 5
7362 11:03:28.231520 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7363 11:03:28.234825 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7364 11:03:28.238149 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7365 11:03:28.244678 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7366 11:03:28.247823 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7367 11:03:28.251192 [MiockJmeterHQA]
7368 11:03:28.251267
7369 11:03:28.254603 [DramcMiockJmeter] u1RxGatingPI = 0
7370 11:03:28.254678 0 : 4252, 4027
7371 11:03:28.254739 4 : 4255, 4029
7372 11:03:28.257952 8 : 4255, 4029
7373 11:03:28.258077 12 : 4252, 4027
7374 11:03:28.261280 16 : 4361, 4138
7375 11:03:28.261356 20 : 4253, 4027
7376 11:03:28.264706 24 : 4255, 4030
7377 11:03:28.264782 28 : 4252, 4027
7378 11:03:28.264841 32 : 4363, 4137
7379 11:03:28.268081 36 : 4363, 4137
7380 11:03:28.268157 40 : 4252, 4027
7381 11:03:28.270950 44 : 4252, 4027
7382 11:03:28.271026 48 : 4252, 4027
7383 11:03:28.274401 52 : 4252, 4027
7384 11:03:28.274477 56 : 4252, 4027
7385 11:03:28.277946 60 : 4253, 4026
7386 11:03:28.278024 64 : 4252, 4027
7387 11:03:28.278084 68 : 4253, 4027
7388 11:03:28.281036 72 : 4250, 4027
7389 11:03:28.281186 76 : 4253, 4029
7390 11:03:28.284663 80 : 4252, 4027
7391 11:03:28.284740 84 : 4363, 4137
7392 11:03:28.287624 88 : 4361, 4137
7393 11:03:28.287701 92 : 4250, 4027
7394 11:03:28.290804 96 : 4250, 2589
7395 11:03:28.290880 100 : 4250, 0
7396 11:03:28.290940 104 : 4363, 0
7397 11:03:28.294011 108 : 4252, 0
7398 11:03:28.294087 112 : 4250, 0
7399 11:03:28.297453 116 : 4250, 0
7400 11:03:28.297529 120 : 4252, 0
7401 11:03:28.297590 124 : 4250, 0
7402 11:03:28.300961 128 : 4250, 0
7403 11:03:28.301071 132 : 4250, 0
7404 11:03:28.301202 136 : 4363, 0
7405 11:03:28.304159 140 : 4249, 0
7406 11:03:28.304235 144 : 4250, 0
7407 11:03:28.307240 148 : 4361, 0
7408 11:03:28.307316 152 : 4365, 0
7409 11:03:28.307375 156 : 4363, 0
7410 11:03:28.310460 160 : 4250, 0
7411 11:03:28.310536 164 : 4252, 0
7412 11:03:28.313868 168 : 4250, 0
7413 11:03:28.313945 172 : 4361, 0
7414 11:03:28.314006 176 : 4250, 0
7415 11:03:28.317043 180 : 4250, 0
7416 11:03:28.317172 184 : 4250, 0
7417 11:03:28.320509 188 : 4250, 0
7418 11:03:28.320588 192 : 4250, 0
7419 11:03:28.320666 196 : 4252, 0
7420 11:03:28.324019 200 : 4250, 0
7421 11:03:28.324098 204 : 4360, 0
7422 11:03:28.328113 208 : 4363, 0
7423 11:03:28.328192 212 : 4250, 0
7424 11:03:28.328271 216 : 4250, 0
7425 11:03:28.330678 220 : 4255, 853
7426 11:03:28.330781 224 : 4360, 4127
7427 11:03:28.334099 228 : 4250, 4027
7428 11:03:28.334179 232 : 4250, 4027
7429 11:03:28.336893 236 : 4253, 4029
7430 11:03:28.336973 240 : 4250, 4027
7431 11:03:28.340209 244 : 4255, 4029
7432 11:03:28.340288 248 : 4250, 4027
7433 11:03:28.340367 252 : 4253, 4029
7434 11:03:28.344048 256 : 4250, 4026
7435 11:03:28.344128 260 : 4360, 4137
7436 11:03:28.347049 264 : 4250, 4027
7437 11:03:28.347129 268 : 4361, 4137
7438 11:03:28.350069 272 : 4250, 4026
7439 11:03:28.350149 276 : 4250, 4027
7440 11:03:28.353412 280 : 4250, 4027
7441 11:03:28.353517 284 : 4250, 4027
7442 11:03:28.357376 288 : 4250, 4027
7443 11:03:28.357470 292 : 4255, 4029
7444 11:03:28.360289 296 : 4250, 4027
7445 11:03:28.360367 300 : 4253, 4029
7446 11:03:28.363393 304 : 4249, 4027
7447 11:03:28.363471 308 : 4250, 4026
7448 11:03:28.367194 312 : 4360, 4138
7449 11:03:28.367271 316 : 4250, 4027
7450 11:03:28.367332 320 : 4361, 4138
7451 11:03:28.369990 324 : 4250, 4027
7452 11:03:28.370067 328 : 4250, 4027
7453 11:03:28.373488 332 : 4250, 3911
7454 11:03:28.373591 336 : 4250, 1307
7455 11:03:28.373663
7456 11:03:28.376877 MIOCK jitter meter ch=0
7457 11:03:28.376953
7458 11:03:28.380229 1T = (336-100) = 236 dly cells
7459 11:03:28.386823 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7460 11:03:28.386900 ==
7461 11:03:28.390326 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 11:03:28.393997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7463 11:03:28.394074 ==
7464 11:03:28.399852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7465 11:03:28.403565 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7466 11:03:28.406757 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7467 11:03:28.413372 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7468 11:03:28.422240 [CA 0] Center 43 (13~73) winsize 61
7469 11:03:28.425472 [CA 1] Center 42 (12~73) winsize 62
7470 11:03:28.428600 [CA 2] Center 37 (8~67) winsize 60
7471 11:03:28.432099 [CA 3] Center 37 (8~67) winsize 60
7472 11:03:28.435655 [CA 4] Center 36 (6~66) winsize 61
7473 11:03:28.438472 [CA 5] Center 35 (5~66) winsize 62
7474 11:03:28.438547
7475 11:03:28.442187 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7476 11:03:28.442263
7477 11:03:28.445148 [CATrainingPosCal] consider 1 rank data
7478 11:03:28.448602 u2DelayCellTimex100 = 275/100 ps
7479 11:03:28.455155 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7480 11:03:28.458420 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7481 11:03:28.461916 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7482 11:03:28.465302 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7483 11:03:28.468257 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7484 11:03:28.471724 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7485 11:03:28.471801
7486 11:03:28.474779 CA PerBit enable=1, Macro0, CA PI delay=35
7487 11:03:28.474855
7488 11:03:28.478126 [CBTSetCACLKResult] CA Dly = 35
7489 11:03:28.481766 CS Dly: 10 (0~41)
7490 11:03:28.484902 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7491 11:03:28.488301 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7492 11:03:28.488377 ==
7493 11:03:28.491187 Dram Type= 6, Freq= 0, CH_0, rank 1
7494 11:03:28.498165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 11:03:28.498242 ==
7496 11:03:28.501408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 11:03:28.508004 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 11:03:28.510879 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 11:03:28.517493 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 11:03:28.525849 [CA 0] Center 44 (14~75) winsize 62
7501 11:03:28.528892 [CA 1] Center 44 (14~74) winsize 61
7502 11:03:28.532322 [CA 2] Center 38 (9~68) winsize 60
7503 11:03:28.535651 [CA 3] Center 39 (10~68) winsize 59
7504 11:03:28.539004 [CA 4] Center 37 (7~67) winsize 61
7505 11:03:28.542158 [CA 5] Center 36 (7~66) winsize 60
7506 11:03:28.542275
7507 11:03:28.545836 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 11:03:28.545912
7509 11:03:28.551906 [CATrainingPosCal] consider 2 rank data
7510 11:03:28.551982 u2DelayCellTimex100 = 275/100 ps
7511 11:03:28.558896 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7512 11:03:28.562229 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7513 11:03:28.565380 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7514 11:03:28.568161 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7515 11:03:28.571580 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7516 11:03:28.575190 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7517 11:03:28.575267
7518 11:03:28.578593 CA PerBit enable=1, Macro0, CA PI delay=36
7519 11:03:28.578669
7520 11:03:28.582078 [CBTSetCACLKResult] CA Dly = 36
7521 11:03:28.584901 CS Dly: 11 (0~44)
7522 11:03:28.588218 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 11:03:28.591623 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 11:03:28.591699
7525 11:03:28.594915 ----->DramcWriteLeveling(PI) begin...
7526 11:03:28.594993 ==
7527 11:03:28.598557 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 11:03:28.604921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 11:03:28.604998 ==
7530 11:03:28.608774 Write leveling (Byte 0): 34 => 34
7531 11:03:28.611488 Write leveling (Byte 1): 26 => 26
7532 11:03:28.615015 DramcWriteLeveling(PI) end<-----
7533 11:03:28.615091
7534 11:03:28.615149 ==
7535 11:03:28.618023 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 11:03:28.621581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 11:03:28.621657 ==
7538 11:03:28.624458 [Gating] SW mode calibration
7539 11:03:28.631103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7540 11:03:28.637534 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7541 11:03:28.640809 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 11:03:28.644690 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 11:03:28.650979 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7544 11:03:28.654227 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7545 11:03:28.657639 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7546 11:03:28.661156 1 4 20 | B1->B0 | 302f 3434 | 1 1 | (1 1) (1 1)
7547 11:03:28.667708 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 11:03:28.671591 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 11:03:28.674596 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 11:03:28.680635 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7551 11:03:28.684264 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7552 11:03:28.687186 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 1)
7553 11:03:28.693996 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7554 11:03:28.697332 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
7555 11:03:28.700514 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7556 11:03:28.707500 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 11:03:28.710235 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 11:03:28.713994 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 11:03:28.720146 1 6 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7560 11:03:28.723392 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7561 11:03:28.726661 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7562 11:03:28.733474 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7563 11:03:28.736639 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 11:03:28.740191 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 11:03:28.747415 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 11:03:28.749794 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 11:03:28.753155 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 11:03:28.759653 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 11:03:28.763149 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7570 11:03:28.766415 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7571 11:03:28.772828 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 11:03:28.776209 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 11:03:28.783074 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 11:03:28.786435 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 11:03:28.789480 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 11:03:28.793064 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 11:03:28.799249 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 11:03:28.802561 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 11:03:28.806160 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 11:03:28.812351 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:03:28.815975 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 11:03:28.819154 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:03:28.825574 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 11:03:28.828906 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7585 11:03:28.832266 Total UI for P1: 0, mck2ui 16
7586 11:03:28.835392 best dqsien dly found for B0: ( 1, 9, 8)
7587 11:03:28.839180 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 11:03:28.845695 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7589 11:03:28.848871 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 11:03:28.852189 Total UI for P1: 0, mck2ui 16
7591 11:03:28.855565 best dqsien dly found for B1: ( 1, 9, 18)
7592 11:03:28.858944 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7593 11:03:28.861858 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7594 11:03:28.861935
7595 11:03:28.865346 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7596 11:03:28.872008 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7597 11:03:28.872088 [Gating] SW calibration Done
7598 11:03:28.872148 ==
7599 11:03:28.875174 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 11:03:28.881591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 11:03:28.881671 ==
7602 11:03:28.881740 RX Vref Scan: 0
7603 11:03:28.881796
7604 11:03:28.885130 RX Vref 0 -> 0, step: 1
7605 11:03:28.885245
7606 11:03:28.888432 RX Delay 0 -> 252, step: 8
7607 11:03:28.891885 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7608 11:03:28.895095 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7609 11:03:28.898095 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7610 11:03:28.904830 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7611 11:03:28.908010 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7612 11:03:28.911579 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7613 11:03:28.915054 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7614 11:03:28.918089 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7615 11:03:28.924570 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7616 11:03:28.928201 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7617 11:03:28.931335 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7618 11:03:28.934929 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7619 11:03:28.937974 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7620 11:03:28.944740 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7621 11:03:28.948123 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7622 11:03:28.951491 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7623 11:03:28.951566 ==
7624 11:03:28.955347 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 11:03:28.958132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 11:03:28.958223 ==
7627 11:03:28.961009 DQS Delay:
7628 11:03:28.961085 DQS0 = 0, DQS1 = 0
7629 11:03:28.964579 DQM Delay:
7630 11:03:28.964654 DQM0 = 131, DQM1 = 126
7631 11:03:28.967781 DQ Delay:
7632 11:03:28.971047 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7633 11:03:28.974561 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7634 11:03:28.977845 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7635 11:03:28.981245 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7636 11:03:28.981316
7637 11:03:28.981380
7638 11:03:28.981435 ==
7639 11:03:28.984592 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 11:03:28.987640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 11:03:28.987736 ==
7642 11:03:28.987821
7643 11:03:28.990583
7644 11:03:28.990696 TX Vref Scan disable
7645 11:03:28.994007 == TX Byte 0 ==
7646 11:03:28.997463 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7647 11:03:29.000798 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7648 11:03:29.003768 == TX Byte 1 ==
7649 11:03:29.007129 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7650 11:03:29.010659 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7651 11:03:29.010734 ==
7652 11:03:29.014375 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 11:03:29.020114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 11:03:29.020190 ==
7655 11:03:29.034175
7656 11:03:29.037473 TX Vref early break, caculate TX vref
7657 11:03:29.040869 TX Vref=16, minBit 6, minWin=22, winSum=369
7658 11:03:29.044293 TX Vref=18, minBit 1, minWin=22, winSum=382
7659 11:03:29.047266 TX Vref=20, minBit 7, minWin=23, winSum=393
7660 11:03:29.050775 TX Vref=22, minBit 3, minWin=24, winSum=403
7661 11:03:29.053774 TX Vref=24, minBit 7, minWin=24, winSum=411
7662 11:03:29.060425 TX Vref=26, minBit 1, minWin=25, winSum=417
7663 11:03:29.063966 TX Vref=28, minBit 1, minWin=25, winSum=417
7664 11:03:29.066890 TX Vref=30, minBit 2, minWin=25, winSum=414
7665 11:03:29.070567 TX Vref=32, minBit 9, minWin=24, winSum=411
7666 11:03:29.073798 TX Vref=34, minBit 2, minWin=23, winSum=398
7667 11:03:29.077374 TX Vref=36, minBit 2, minWin=23, winSum=387
7668 11:03:29.083501 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 26
7669 11:03:29.083582
7670 11:03:29.086911 Final TX Range 0 Vref 26
7671 11:03:29.086986
7672 11:03:29.087044 ==
7673 11:03:29.090241 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 11:03:29.093395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 11:03:29.093494 ==
7676 11:03:29.096563
7677 11:03:29.096637
7678 11:03:29.096696 TX Vref Scan disable
7679 11:03:29.103362 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7680 11:03:29.103438 == TX Byte 0 ==
7681 11:03:29.106933 u2DelayCellOfst[0]=14 cells (4 PI)
7682 11:03:29.109738 u2DelayCellOfst[1]=17 cells (5 PI)
7683 11:03:29.112946 u2DelayCellOfst[2]=10 cells (3 PI)
7684 11:03:29.116589 u2DelayCellOfst[3]=14 cells (4 PI)
7685 11:03:29.119871 u2DelayCellOfst[4]=7 cells (2 PI)
7686 11:03:29.122933 u2DelayCellOfst[5]=0 cells (0 PI)
7687 11:03:29.126031 u2DelayCellOfst[6]=17 cells (5 PI)
7688 11:03:29.129342 u2DelayCellOfst[7]=17 cells (5 PI)
7689 11:03:29.133010 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7690 11:03:29.139148 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7691 11:03:29.139225 == TX Byte 1 ==
7692 11:03:29.142724 u2DelayCellOfst[8]=0 cells (0 PI)
7693 11:03:29.146137 u2DelayCellOfst[9]=0 cells (0 PI)
7694 11:03:29.149466 u2DelayCellOfst[10]=3 cells (1 PI)
7695 11:03:29.152573 u2DelayCellOfst[11]=0 cells (0 PI)
7696 11:03:29.156290 u2DelayCellOfst[12]=7 cells (2 PI)
7697 11:03:29.159301 u2DelayCellOfst[13]=10 cells (3 PI)
7698 11:03:29.162913 u2DelayCellOfst[14]=14 cells (4 PI)
7699 11:03:29.165866 u2DelayCellOfst[15]=10 cells (3 PI)
7700 11:03:29.168819 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7701 11:03:29.172155 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7702 11:03:29.175359 DramC Write-DBI on
7703 11:03:29.175436 ==
7704 11:03:29.178967 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 11:03:29.182275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 11:03:29.182343 ==
7707 11:03:29.182405
7708 11:03:29.182461
7709 11:03:29.185390 TX Vref Scan disable
7710 11:03:29.188629 == TX Byte 0 ==
7711 11:03:29.192385 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7712 11:03:29.192453 == TX Byte 1 ==
7713 11:03:29.199165 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7714 11:03:29.199268 DramC Write-DBI off
7715 11:03:29.199353
7716 11:03:29.199438 [DATLAT]
7717 11:03:29.201960 Freq=1600, CH0 RK0
7718 11:03:29.202024
7719 11:03:29.205421 DATLAT Default: 0xf
7720 11:03:29.205488 0, 0xFFFF, sum = 0
7721 11:03:29.208413 1, 0xFFFF, sum = 0
7722 11:03:29.208484 2, 0xFFFF, sum = 0
7723 11:03:29.212650 3, 0xFFFF, sum = 0
7724 11:03:29.212718 4, 0xFFFF, sum = 0
7725 11:03:29.215891 5, 0xFFFF, sum = 0
7726 11:03:29.215982 6, 0xFFFF, sum = 0
7727 11:03:29.218642 7, 0xFFFF, sum = 0
7728 11:03:29.218710 8, 0xFFFF, sum = 0
7729 11:03:29.222408 9, 0xFFFF, sum = 0
7730 11:03:29.222474 10, 0xFFFF, sum = 0
7731 11:03:29.224980 11, 0xFFFF, sum = 0
7732 11:03:29.225078 12, 0xFFFF, sum = 0
7733 11:03:29.229007 13, 0xFFFF, sum = 0
7734 11:03:29.229128 14, 0x0, sum = 1
7735 11:03:29.231958 15, 0x0, sum = 2
7736 11:03:29.232029 16, 0x0, sum = 3
7737 11:03:29.235120 17, 0x0, sum = 4
7738 11:03:29.235184 best_step = 15
7739 11:03:29.235238
7740 11:03:29.235299 ==
7741 11:03:29.238593 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 11:03:29.245069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 11:03:29.245161 ==
7744 11:03:29.245233 RX Vref Scan: 1
7745 11:03:29.245295
7746 11:03:29.248497 Set Vref Range= 24 -> 127
7747 11:03:29.248563
7748 11:03:29.251221 RX Vref 24 -> 127, step: 1
7749 11:03:29.251291
7750 11:03:29.254661 RX Delay 11 -> 252, step: 4
7751 11:03:29.254730
7752 11:03:29.258171 Set Vref, RX VrefLevel [Byte0]: 24
7753 11:03:29.261284 [Byte1]: 24
7754 11:03:29.261354
7755 11:03:29.264820 Set Vref, RX VrefLevel [Byte0]: 25
7756 11:03:29.268143 [Byte1]: 25
7757 11:03:29.268220
7758 11:03:29.271603 Set Vref, RX VrefLevel [Byte0]: 26
7759 11:03:29.274539 [Byte1]: 26
7760 11:03:29.277756
7761 11:03:29.277831 Set Vref, RX VrefLevel [Byte0]: 27
7762 11:03:29.281158 [Byte1]: 27
7763 11:03:29.285338
7764 11:03:29.285413 Set Vref, RX VrefLevel [Byte0]: 28
7765 11:03:29.288635 [Byte1]: 28
7766 11:03:29.292870
7767 11:03:29.292945 Set Vref, RX VrefLevel [Byte0]: 29
7768 11:03:29.296019 [Byte1]: 29
7769 11:03:29.300459
7770 11:03:29.300534 Set Vref, RX VrefLevel [Byte0]: 30
7771 11:03:29.303900 [Byte1]: 30
7772 11:03:29.308670
7773 11:03:29.308746 Set Vref, RX VrefLevel [Byte0]: 31
7774 11:03:29.311386 [Byte1]: 31
7775 11:03:29.315891
7776 11:03:29.315989 Set Vref, RX VrefLevel [Byte0]: 32
7777 11:03:29.319144 [Byte1]: 32
7778 11:03:29.323334
7779 11:03:29.323410 Set Vref, RX VrefLevel [Byte0]: 33
7780 11:03:29.326838 [Byte1]: 33
7781 11:03:29.331132
7782 11:03:29.331206 Set Vref, RX VrefLevel [Byte0]: 34
7783 11:03:29.334596 [Byte1]: 34
7784 11:03:29.338772
7785 11:03:29.338842 Set Vref, RX VrefLevel [Byte0]: 35
7786 11:03:29.342517 [Byte1]: 35
7787 11:03:29.346486
7788 11:03:29.346554 Set Vref, RX VrefLevel [Byte0]: 36
7789 11:03:29.349767 [Byte1]: 36
7790 11:03:29.353845
7791 11:03:29.353921 Set Vref, RX VrefLevel [Byte0]: 37
7792 11:03:29.356967 [Byte1]: 37
7793 11:03:29.361754
7794 11:03:29.361826 Set Vref, RX VrefLevel [Byte0]: 38
7795 11:03:29.364727 [Byte1]: 38
7796 11:03:29.369214
7797 11:03:29.369310 Set Vref, RX VrefLevel [Byte0]: 39
7798 11:03:29.372307 [Byte1]: 39
7799 11:03:29.377055
7800 11:03:29.377184 Set Vref, RX VrefLevel [Byte0]: 40
7801 11:03:29.379942 [Byte1]: 40
7802 11:03:29.384606
7803 11:03:29.384680 Set Vref, RX VrefLevel [Byte0]: 41
7804 11:03:29.387633 [Byte1]: 41
7805 11:03:29.392144
7806 11:03:29.392220 Set Vref, RX VrefLevel [Byte0]: 42
7807 11:03:29.395323 [Byte1]: 42
7808 11:03:29.400050
7809 11:03:29.400125 Set Vref, RX VrefLevel [Byte0]: 43
7810 11:03:29.402949 [Byte1]: 43
7811 11:03:29.407318
7812 11:03:29.407396 Set Vref, RX VrefLevel [Byte0]: 44
7813 11:03:29.410173 [Byte1]: 44
7814 11:03:29.414892
7815 11:03:29.414967 Set Vref, RX VrefLevel [Byte0]: 45
7816 11:03:29.417869 [Byte1]: 45
7817 11:03:29.422121
7818 11:03:29.422202 Set Vref, RX VrefLevel [Byte0]: 46
7819 11:03:29.425757 [Byte1]: 46
7820 11:03:29.430016
7821 11:03:29.430089 Set Vref, RX VrefLevel [Byte0]: 47
7822 11:03:29.433406 [Byte1]: 47
7823 11:03:29.437366
7824 11:03:29.437442 Set Vref, RX VrefLevel [Byte0]: 48
7825 11:03:29.440728 [Byte1]: 48
7826 11:03:29.445664
7827 11:03:29.445738 Set Vref, RX VrefLevel [Byte0]: 49
7828 11:03:29.448619 [Byte1]: 49
7829 11:03:29.453151
7830 11:03:29.453259 Set Vref, RX VrefLevel [Byte0]: 50
7831 11:03:29.456304 [Byte1]: 50
7832 11:03:29.460778
7833 11:03:29.460859 Set Vref, RX VrefLevel [Byte0]: 51
7834 11:03:29.463507 [Byte1]: 51
7835 11:03:29.468230
7836 11:03:29.468307 Set Vref, RX VrefLevel [Byte0]: 52
7837 11:03:29.471093 [Byte1]: 52
7838 11:03:29.475592
7839 11:03:29.475676 Set Vref, RX VrefLevel [Byte0]: 53
7840 11:03:29.479243 [Byte1]: 53
7841 11:03:29.483356
7842 11:03:29.483431 Set Vref, RX VrefLevel [Byte0]: 54
7843 11:03:29.487153 [Byte1]: 54
7844 11:03:29.491069
7845 11:03:29.491144 Set Vref, RX VrefLevel [Byte0]: 55
7846 11:03:29.494605 [Byte1]: 55
7847 11:03:29.498671
7848 11:03:29.498747 Set Vref, RX VrefLevel [Byte0]: 56
7849 11:03:29.502023 [Byte1]: 56
7850 11:03:29.505914
7851 11:03:29.505989 Set Vref, RX VrefLevel [Byte0]: 57
7852 11:03:29.509723 [Byte1]: 57
7853 11:03:29.513463
7854 11:03:29.513538 Set Vref, RX VrefLevel [Byte0]: 58
7855 11:03:29.516871 [Byte1]: 58
7856 11:03:29.521385
7857 11:03:29.521461 Set Vref, RX VrefLevel [Byte0]: 59
7858 11:03:29.524387 [Byte1]: 59
7859 11:03:29.528894
7860 11:03:29.528969 Set Vref, RX VrefLevel [Byte0]: 60
7861 11:03:29.532264 [Byte1]: 60
7862 11:03:29.536830
7863 11:03:29.536931 Set Vref, RX VrefLevel [Byte0]: 61
7864 11:03:29.539764 [Byte1]: 61
7865 11:03:29.544109
7866 11:03:29.544183 Set Vref, RX VrefLevel [Byte0]: 62
7867 11:03:29.547526 [Byte1]: 62
7868 11:03:29.552107
7869 11:03:29.552182 Set Vref, RX VrefLevel [Byte0]: 63
7870 11:03:29.555251 [Byte1]: 63
7871 11:03:29.559194
7872 11:03:29.559269 Set Vref, RX VrefLevel [Byte0]: 64
7873 11:03:29.562621 [Byte1]: 64
7874 11:03:29.566981
7875 11:03:29.567074 Set Vref, RX VrefLevel [Byte0]: 65
7876 11:03:29.570343 [Byte1]: 65
7877 11:03:29.574313
7878 11:03:29.574392 Set Vref, RX VrefLevel [Byte0]: 66
7879 11:03:29.577742 [Byte1]: 66
7880 11:03:29.582406
7881 11:03:29.582481 Set Vref, RX VrefLevel [Byte0]: 67
7882 11:03:29.585626 [Byte1]: 67
7883 11:03:29.589763
7884 11:03:29.589838 Set Vref, RX VrefLevel [Byte0]: 68
7885 11:03:29.593174 [Byte1]: 68
7886 11:03:29.597863
7887 11:03:29.597938 Set Vref, RX VrefLevel [Byte0]: 69
7888 11:03:29.601040 [Byte1]: 69
7889 11:03:29.605347
7890 11:03:29.605423 Set Vref, RX VrefLevel [Byte0]: 70
7891 11:03:29.608177 [Byte1]: 70
7892 11:03:29.612818
7893 11:03:29.612893 Set Vref, RX VrefLevel [Byte0]: 71
7894 11:03:29.616020 [Byte1]: 71
7895 11:03:29.620519
7896 11:03:29.620595 Set Vref, RX VrefLevel [Byte0]: 72
7897 11:03:29.623667 [Byte1]: 72
7898 11:03:29.627935
7899 11:03:29.628003 Set Vref, RX VrefLevel [Byte0]: 73
7900 11:03:29.631290 [Byte1]: 73
7901 11:03:29.635504
7902 11:03:29.635578 Set Vref, RX VrefLevel [Byte0]: 74
7903 11:03:29.638705 [Byte1]: 74
7904 11:03:29.643070
7905 11:03:29.643145 Set Vref, RX VrefLevel [Byte0]: 75
7906 11:03:29.646605 [Byte1]: 75
7907 11:03:29.650633
7908 11:03:29.650726 Set Vref, RX VrefLevel [Byte0]: 76
7909 11:03:29.653949 [Byte1]: 76
7910 11:03:29.658363
7911 11:03:29.658435 Final RX Vref Byte 0 = 55 to rank0
7912 11:03:29.661639 Final RX Vref Byte 1 = 60 to rank0
7913 11:03:29.665082 Final RX Vref Byte 0 = 55 to rank1
7914 11:03:29.668167 Final RX Vref Byte 1 = 60 to rank1==
7915 11:03:29.671278 Dram Type= 6, Freq= 0, CH_0, rank 0
7916 11:03:29.677927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7917 11:03:29.678003 ==
7918 11:03:29.678065 DQS Delay:
7919 11:03:29.681516 DQS0 = 0, DQS1 = 0
7920 11:03:29.681580 DQM Delay:
7921 11:03:29.681633 DQM0 = 128, DQM1 = 124
7922 11:03:29.684913 DQ Delay:
7923 11:03:29.687661 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7924 11:03:29.691032 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7925 11:03:29.694403 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7926 11:03:29.697768 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =132
7927 11:03:29.697843
7928 11:03:29.697902
7929 11:03:29.697955
7930 11:03:29.700807 [DramC_TX_OE_Calibration] TA2
7931 11:03:29.704480 Original DQ_B0 (3 6) =30, OEN = 27
7932 11:03:29.707443 Original DQ_B1 (3 6) =30, OEN = 27
7933 11:03:29.711294 24, 0x0, End_B0=24 End_B1=24
7934 11:03:29.714084 25, 0x0, End_B0=25 End_B1=25
7935 11:03:29.714161 26, 0x0, End_B0=26 End_B1=26
7936 11:03:29.717908 27, 0x0, End_B0=27 End_B1=27
7937 11:03:29.720594 28, 0x0, End_B0=28 End_B1=28
7938 11:03:29.724348 29, 0x0, End_B0=29 End_B1=29
7939 11:03:29.724425 30, 0x0, End_B0=30 End_B1=30
7940 11:03:29.727469 31, 0x4141, End_B0=30 End_B1=30
7941 11:03:29.730816 Byte0 end_step=30 best_step=27
7942 11:03:29.734012 Byte1 end_step=30 best_step=27
7943 11:03:29.737480 Byte0 TX OE(2T, 0.5T) = (3, 3)
7944 11:03:29.741147 Byte1 TX OE(2T, 0.5T) = (3, 3)
7945 11:03:29.741232
7946 11:03:29.741294
7947 11:03:29.747099 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7948 11:03:29.750416 CH0 RK0: MR19=303, MR18=1916
7949 11:03:29.757298 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7950 11:03:29.757373
7951 11:03:29.760458 ----->DramcWriteLeveling(PI) begin...
7952 11:03:29.760535 ==
7953 11:03:29.764189 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 11:03:29.767001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 11:03:29.767078 ==
7956 11:03:29.770068 Write leveling (Byte 0): 33 => 33
7957 11:03:29.773327 Write leveling (Byte 1): 27 => 27
7958 11:03:29.777571 DramcWriteLeveling(PI) end<-----
7959 11:03:29.777647
7960 11:03:29.777707 ==
7961 11:03:29.780076 Dram Type= 6, Freq= 0, CH_0, rank 1
7962 11:03:29.787261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 11:03:29.787337 ==
7964 11:03:29.787402 [Gating] SW mode calibration
7965 11:03:29.796822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7966 11:03:29.800295 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7967 11:03:29.803424 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 11:03:29.809923 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 11:03:29.813047 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7970 11:03:29.816797 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7971 11:03:29.823385 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7972 11:03:29.827027 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 11:03:29.830095 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7974 11:03:29.836032 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7975 11:03:29.839397 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7976 11:03:29.843086 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7977 11:03:29.849484 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7978 11:03:29.852877 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7979 11:03:29.856496 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7980 11:03:29.862978 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7981 11:03:29.865806 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 11:03:29.869089 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 11:03:29.875818 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 11:03:29.879107 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 11:03:29.882514 1 6 8 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
7986 11:03:29.888855 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7987 11:03:29.892474 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7988 11:03:29.895585 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 11:03:29.902359 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 11:03:29.905238 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 11:03:29.912065 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 11:03:29.915078 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7993 11:03:29.918173 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7994 11:03:29.925018 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7995 11:03:29.928252 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7996 11:03:29.931898 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7997 11:03:29.938369 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 11:03:29.941476 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 11:03:29.944955 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 11:03:29.951410 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 11:03:29.954938 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:03:29.958055 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:03:29.964467 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:03:29.968170 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:03:29.971270 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:03:29.978032 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 11:03:29.981213 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 11:03:29.984658 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8009 11:03:29.991554 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8010 11:03:29.994300 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8011 11:03:29.997567 Total UI for P1: 0, mck2ui 16
8012 11:03:30.000760 best dqsien dly found for B0: ( 1, 9, 6)
8013 11:03:30.004480 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8014 11:03:30.007790 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 11:03:30.011022 Total UI for P1: 0, mck2ui 16
8016 11:03:30.014198 best dqsien dly found for B1: ( 1, 9, 18)
8017 11:03:30.017243 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8018 11:03:30.024132 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8019 11:03:30.024207
8020 11:03:30.027336 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8021 11:03:30.030562 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8022 11:03:30.033491 [Gating] SW calibration Done
8023 11:03:30.033629 ==
8024 11:03:30.037257 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 11:03:30.040602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 11:03:30.040670 ==
8027 11:03:30.043660 RX Vref Scan: 0
8028 11:03:30.043724
8029 11:03:30.043785 RX Vref 0 -> 0, step: 1
8030 11:03:30.043842
8031 11:03:30.046871 RX Delay 0 -> 252, step: 8
8032 11:03:30.050305 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8033 11:03:30.056982 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8034 11:03:30.060679 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8035 11:03:30.063535 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8036 11:03:30.067308 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8037 11:03:30.069959 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8038 11:03:30.076671 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8039 11:03:30.080171 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8040 11:03:30.083093 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8041 11:03:30.086986 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8042 11:03:30.090066 iDelay=192, Bit 10, Center 131 (72 ~ 191) 120
8043 11:03:30.096730 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8044 11:03:30.099587 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
8045 11:03:30.102831 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8046 11:03:30.106447 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8047 11:03:30.113022 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8048 11:03:30.113097 ==
8049 11:03:30.116346 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 11:03:30.119755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 11:03:30.119840 ==
8052 11:03:30.119900 DQS Delay:
8053 11:03:30.122851 DQS0 = 0, DQS1 = 0
8054 11:03:30.122926 DQM Delay:
8055 11:03:30.126173 DQM0 = 131, DQM1 = 127
8056 11:03:30.126249 DQ Delay:
8057 11:03:30.129769 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8058 11:03:30.132483 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8059 11:03:30.136078 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8060 11:03:30.139281 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8061 11:03:30.139356
8062 11:03:30.139415
8063 11:03:30.142240 ==
8064 11:03:30.145583 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 11:03:30.148910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 11:03:30.148986 ==
8067 11:03:30.149044
8068 11:03:30.149098
8069 11:03:30.152639 TX Vref Scan disable
8070 11:03:30.152715 == TX Byte 0 ==
8071 11:03:30.159145 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8072 11:03:30.162032 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8073 11:03:30.162107 == TX Byte 1 ==
8074 11:03:30.168683 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8075 11:03:30.172468 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8076 11:03:30.172542 ==
8077 11:03:30.175191 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 11:03:30.178603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 11:03:30.178672 ==
8080 11:03:30.194194
8081 11:03:30.197071 TX Vref early break, caculate TX vref
8082 11:03:30.200357 TX Vref=16, minBit 9, minWin=22, winSum=379
8083 11:03:30.203437 TX Vref=18, minBit 3, minWin=24, winSum=393
8084 11:03:30.207065 TX Vref=20, minBit 8, minWin=23, winSum=400
8085 11:03:30.210299 TX Vref=22, minBit 0, minWin=25, winSum=409
8086 11:03:30.213636 TX Vref=24, minBit 1, minWin=25, winSum=412
8087 11:03:30.220057 TX Vref=26, minBit 1, minWin=25, winSum=417
8088 11:03:30.223761 TX Vref=28, minBit 4, minWin=25, winSum=422
8089 11:03:30.226678 TX Vref=30, minBit 1, minWin=25, winSum=416
8090 11:03:30.229976 TX Vref=32, minBit 0, minWin=25, winSum=406
8091 11:03:30.233546 TX Vref=34, minBit 0, minWin=24, winSum=405
8092 11:03:30.236885 TX Vref=36, minBit 1, minWin=23, winSum=392
8093 11:03:30.243564 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
8094 11:03:30.243647
8095 11:03:30.246671 Final TX Range 0 Vref 28
8096 11:03:30.246739
8097 11:03:30.246802 ==
8098 11:03:30.250410 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 11:03:30.253222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 11:03:30.253293 ==
8101 11:03:30.253357
8102 11:03:30.256532
8103 11:03:30.256600 TX Vref Scan disable
8104 11:03:30.263287 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8105 11:03:30.263363 == TX Byte 0 ==
8106 11:03:30.266366 u2DelayCellOfst[0]=14 cells (4 PI)
8107 11:03:30.269823 u2DelayCellOfst[1]=14 cells (4 PI)
8108 11:03:30.273333 u2DelayCellOfst[2]=10 cells (3 PI)
8109 11:03:30.276956 u2DelayCellOfst[3]=10 cells (3 PI)
8110 11:03:30.279606 u2DelayCellOfst[4]=10 cells (3 PI)
8111 11:03:30.282896 u2DelayCellOfst[5]=0 cells (0 PI)
8112 11:03:30.286203 u2DelayCellOfst[6]=17 cells (5 PI)
8113 11:03:30.289849 u2DelayCellOfst[7]=17 cells (5 PI)
8114 11:03:30.292556 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8115 11:03:30.296475 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8116 11:03:30.299522 == TX Byte 1 ==
8117 11:03:30.303022 u2DelayCellOfst[8]=0 cells (0 PI)
8118 11:03:30.306102 u2DelayCellOfst[9]=0 cells (0 PI)
8119 11:03:30.309578 u2DelayCellOfst[10]=3 cells (1 PI)
8120 11:03:30.312878 u2DelayCellOfst[11]=0 cells (0 PI)
8121 11:03:30.316095 u2DelayCellOfst[12]=10 cells (3 PI)
8122 11:03:30.319764 u2DelayCellOfst[13]=10 cells (3 PI)
8123 11:03:30.319853 u2DelayCellOfst[14]=14 cells (4 PI)
8124 11:03:30.322517 u2DelayCellOfst[15]=10 cells (3 PI)
8125 11:03:30.329100 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8126 11:03:30.332568 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8127 11:03:30.335661 DramC Write-DBI on
8128 11:03:30.335737 ==
8129 11:03:30.338834 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 11:03:30.342466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 11:03:30.342542 ==
8132 11:03:30.342600
8133 11:03:30.342653
8134 11:03:30.345513 TX Vref Scan disable
8135 11:03:30.345598 == TX Byte 0 ==
8136 11:03:30.352063 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8137 11:03:30.352139 == TX Byte 1 ==
8138 11:03:30.355966 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8139 11:03:30.358638 DramC Write-DBI off
8140 11:03:30.358712
8141 11:03:30.358772 [DATLAT]
8142 11:03:30.362312 Freq=1600, CH0 RK1
8143 11:03:30.362388
8144 11:03:30.362446 DATLAT Default: 0xf
8145 11:03:30.365363 0, 0xFFFF, sum = 0
8146 11:03:30.368622 1, 0xFFFF, sum = 0
8147 11:03:30.368699 2, 0xFFFF, sum = 0
8148 11:03:30.372005 3, 0xFFFF, sum = 0
8149 11:03:30.372090 4, 0xFFFF, sum = 0
8150 11:03:30.375186 5, 0xFFFF, sum = 0
8151 11:03:30.375262 6, 0xFFFF, sum = 0
8152 11:03:30.378886 7, 0xFFFF, sum = 0
8153 11:03:30.378962 8, 0xFFFF, sum = 0
8154 11:03:30.381975 9, 0xFFFF, sum = 0
8155 11:03:30.382051 10, 0xFFFF, sum = 0
8156 11:03:30.385878 11, 0xFFFF, sum = 0
8157 11:03:30.385954 12, 0xFFFF, sum = 0
8158 11:03:30.388677 13, 0xFFFF, sum = 0
8159 11:03:30.388753 14, 0x0, sum = 1
8160 11:03:30.391658 15, 0x0, sum = 2
8161 11:03:30.391733 16, 0x0, sum = 3
8162 11:03:30.394733 17, 0x0, sum = 4
8163 11:03:30.394809 best_step = 15
8164 11:03:30.394867
8165 11:03:30.394921 ==
8166 11:03:30.398178 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 11:03:30.405047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 11:03:30.405123 ==
8169 11:03:30.405192 RX Vref Scan: 0
8170 11:03:30.405248
8171 11:03:30.408164 RX Vref 0 -> 0, step: 1
8172 11:03:30.408238
8173 11:03:30.411422 RX Delay 11 -> 252, step: 4
8174 11:03:30.415170 iDelay=187, Bit 0, Center 124 (75 ~ 174) 100
8175 11:03:30.417954 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8176 11:03:30.424803 iDelay=187, Bit 2, Center 122 (71 ~ 174) 104
8177 11:03:30.427748 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8178 11:03:30.431291 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8179 11:03:30.434483 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8180 11:03:30.437758 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8181 11:03:30.444170 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8182 11:03:30.447584 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8183 11:03:30.450919 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8184 11:03:30.454451 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8185 11:03:30.458112 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8186 11:03:30.464236 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8187 11:03:30.467840 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8188 11:03:30.470666 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8189 11:03:30.473944 iDelay=187, Bit 15, Center 130 (79 ~ 182) 104
8190 11:03:30.474021 ==
8191 11:03:30.477396 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 11:03:30.484042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 11:03:30.484118 ==
8194 11:03:30.484178 DQS Delay:
8195 11:03:30.487380 DQS0 = 0, DQS1 = 0
8196 11:03:30.487456 DQM Delay:
8197 11:03:30.487515 DQM0 = 128, DQM1 = 123
8198 11:03:30.490557 DQ Delay:
8199 11:03:30.494452 DQ0 =124, DQ1 =132, DQ2 =122, DQ3 =126
8200 11:03:30.497212 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
8201 11:03:30.500595 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8202 11:03:30.504064 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8203 11:03:30.504139
8204 11:03:30.504198
8205 11:03:30.504266
8206 11:03:30.507588 [DramC_TX_OE_Calibration] TA2
8207 11:03:30.510506 Original DQ_B0 (3 6) =30, OEN = 27
8208 11:03:30.513833 Original DQ_B1 (3 6) =30, OEN = 27
8209 11:03:30.516982 24, 0x0, End_B0=24 End_B1=24
8210 11:03:30.517059 25, 0x0, End_B0=25 End_B1=25
8211 11:03:30.520463 26, 0x0, End_B0=26 End_B1=26
8212 11:03:30.523550 27, 0x0, End_B0=27 End_B1=27
8213 11:03:30.526990 28, 0x0, End_B0=28 End_B1=28
8214 11:03:30.530640 29, 0x0, End_B0=29 End_B1=29
8215 11:03:30.530717 30, 0x0, End_B0=30 End_B1=30
8216 11:03:30.533370 31, 0x4141, End_B0=30 End_B1=30
8217 11:03:30.536925 Byte0 end_step=30 best_step=27
8218 11:03:30.540374 Byte1 end_step=30 best_step=27
8219 11:03:30.543641 Byte0 TX OE(2T, 0.5T) = (3, 3)
8220 11:03:30.547206 Byte1 TX OE(2T, 0.5T) = (3, 3)
8221 11:03:30.547282
8222 11:03:30.547379
8223 11:03:30.553366 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8224 11:03:30.556722 CH0 RK1: MR19=303, MR18=1513
8225 11:03:30.563256 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8226 11:03:30.566519 [RxdqsGatingPostProcess] freq 1600
8227 11:03:30.573105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8228 11:03:30.573221 best DQS0 dly(2T, 0.5T) = (1, 1)
8229 11:03:30.576602 best DQS1 dly(2T, 0.5T) = (1, 1)
8230 11:03:30.579944 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8231 11:03:30.582828 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8232 11:03:30.586537 best DQS0 dly(2T, 0.5T) = (1, 1)
8233 11:03:30.589778 best DQS1 dly(2T, 0.5T) = (1, 1)
8234 11:03:30.592886 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8235 11:03:30.596199 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8236 11:03:30.599929 Pre-setting of DQS Precalculation
8237 11:03:30.603071 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8238 11:03:30.603147 ==
8239 11:03:30.606412 Dram Type= 6, Freq= 0, CH_1, rank 0
8240 11:03:30.612731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 11:03:30.612808 ==
8242 11:03:30.615805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8243 11:03:30.622614 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8244 11:03:30.626257 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8245 11:03:30.632695 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8246 11:03:30.640341 [CA 0] Center 42 (13~72) winsize 60
8247 11:03:30.643514 [CA 1] Center 42 (13~72) winsize 60
8248 11:03:30.646992 [CA 2] Center 38 (9~68) winsize 60
8249 11:03:30.650462 [CA 3] Center 37 (8~67) winsize 60
8250 11:03:30.653891 [CA 4] Center 38 (8~69) winsize 62
8251 11:03:30.656865 [CA 5] Center 37 (7~67) winsize 61
8252 11:03:30.656940
8253 11:03:30.660150 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8254 11:03:30.660226
8255 11:03:30.667139 [CATrainingPosCal] consider 1 rank data
8256 11:03:30.667215 u2DelayCellTimex100 = 275/100 ps
8257 11:03:30.673192 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8258 11:03:30.676428 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8259 11:03:30.680202 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8260 11:03:30.683235 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8261 11:03:30.686694 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8262 11:03:30.689939 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8263 11:03:30.690014
8264 11:03:30.693270 CA PerBit enable=1, Macro0, CA PI delay=37
8265 11:03:30.693346
8266 11:03:30.696495 [CBTSetCACLKResult] CA Dly = 37
8267 11:03:30.699852 CS Dly: 8 (0~39)
8268 11:03:30.703032 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8269 11:03:30.706325 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8270 11:03:30.706400 ==
8271 11:03:30.709439 Dram Type= 6, Freq= 0, CH_1, rank 1
8272 11:03:30.715948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 11:03:30.716024 ==
8274 11:03:30.719308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8275 11:03:30.726102 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8276 11:03:30.729358 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8277 11:03:30.735695 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8278 11:03:30.743726 [CA 0] Center 42 (12~72) winsize 61
8279 11:03:30.746780 [CA 1] Center 42 (13~72) winsize 60
8280 11:03:30.750034 [CA 2] Center 38 (8~68) winsize 61
8281 11:03:30.753627 [CA 3] Center 37 (7~67) winsize 61
8282 11:03:30.756763 [CA 4] Center 37 (8~67) winsize 60
8283 11:03:30.759787 [CA 5] Center 37 (7~67) winsize 61
8284 11:03:30.759862
8285 11:03:30.763727 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8286 11:03:30.763802
8287 11:03:30.766455 [CATrainingPosCal] consider 2 rank data
8288 11:03:30.769969 u2DelayCellTimex100 = 275/100 ps
8289 11:03:30.776377 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8290 11:03:30.779835 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8291 11:03:30.783003 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8292 11:03:30.786727 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8293 11:03:30.789726 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8294 11:03:30.793397 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8295 11:03:30.793473
8296 11:03:30.796175 CA PerBit enable=1, Macro0, CA PI delay=37
8297 11:03:30.796253
8298 11:03:30.799574 [CBTSetCACLKResult] CA Dly = 37
8299 11:03:30.802890 CS Dly: 9 (0~42)
8300 11:03:30.806309 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8301 11:03:30.809404 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8302 11:03:30.809480
8303 11:03:30.813002 ----->DramcWriteLeveling(PI) begin...
8304 11:03:30.813102 ==
8305 11:03:30.815877 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 11:03:30.822697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 11:03:30.822773 ==
8308 11:03:30.825950 Write leveling (Byte 0): 26 => 26
8309 11:03:30.829487 Write leveling (Byte 1): 26 => 26
8310 11:03:30.829563 DramcWriteLeveling(PI) end<-----
8311 11:03:30.829621
8312 11:03:30.832534 ==
8313 11:03:30.836100 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 11:03:30.840098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 11:03:30.840200 ==
8316 11:03:30.842441 [Gating] SW mode calibration
8317 11:03:30.849294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8318 11:03:30.852286 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8319 11:03:30.859574 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 11:03:30.862144 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 11:03:30.866162 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 11:03:30.872251 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8323 11:03:30.875716 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 11:03:30.878951 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 11:03:30.885546 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 11:03:30.888709 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 11:03:30.891981 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 11:03:30.898392 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 11:03:30.902047 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8330 11:03:30.905414 1 5 12 | B1->B0 | 3232 2626 | 1 1 | (1 1) (1 0)
8331 11:03:30.911784 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8332 11:03:30.915419 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 11:03:30.918952 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 11:03:30.924721 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 11:03:30.928554 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 11:03:30.931386 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 11:03:30.937923 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8338 11:03:30.941829 1 6 12 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8339 11:03:30.945284 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 11:03:30.951348 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 11:03:30.954704 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 11:03:30.958269 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 11:03:30.964854 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 11:03:30.967796 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 11:03:30.971183 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8346 11:03:30.978003 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8347 11:03:30.981301 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8348 11:03:30.984554 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 11:03:30.991434 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 11:03:30.994254 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:03:30.997983 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:03:31.004253 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:03:31.007387 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:03:31.010941 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:03:31.017755 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:03:31.021146 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 11:03:31.024704 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 11:03:31.031158 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 11:03:31.033959 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:03:31.037217 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:03:31.044166 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8362 11:03:31.047324 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8363 11:03:31.050788 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 11:03:31.054127 Total UI for P1: 0, mck2ui 16
8365 11:03:31.057302 best dqsien dly found for B0: ( 1, 9, 10)
8366 11:03:31.060955 Total UI for P1: 0, mck2ui 16
8367 11:03:31.063828 best dqsien dly found for B1: ( 1, 9, 12)
8368 11:03:31.067239 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8369 11:03:31.070775 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8370 11:03:31.070850
8371 11:03:31.077006 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8372 11:03:31.080190 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8373 11:03:31.080266 [Gating] SW calibration Done
8374 11:03:31.083577 ==
8375 11:03:31.087107 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 11:03:31.090425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 11:03:31.090502 ==
8378 11:03:31.090561 RX Vref Scan: 0
8379 11:03:31.090616
8380 11:03:31.093537 RX Vref 0 -> 0, step: 1
8381 11:03:31.093612
8382 11:03:31.097173 RX Delay 0 -> 252, step: 8
8383 11:03:31.100418 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8384 11:03:31.103633 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8385 11:03:31.110045 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8386 11:03:31.113354 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8387 11:03:31.116829 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8388 11:03:31.120016 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8389 11:03:31.122825 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8390 11:03:31.129870 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8391 11:03:31.133095 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8392 11:03:31.136323 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8393 11:03:31.139721 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8394 11:03:31.143203 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8395 11:03:31.149287 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8396 11:03:31.153002 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8397 11:03:31.155784 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8398 11:03:31.159712 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8399 11:03:31.159788 ==
8400 11:03:31.162638 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 11:03:31.169245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 11:03:31.169345 ==
8403 11:03:31.169430 DQS Delay:
8404 11:03:31.172648 DQS0 = 0, DQS1 = 0
8405 11:03:31.172723 DQM Delay:
8406 11:03:31.175729 DQM0 = 135, DQM1 = 130
8407 11:03:31.175804 DQ Delay:
8408 11:03:31.179411 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8409 11:03:31.182438 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8410 11:03:31.185944 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8411 11:03:31.189060 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8412 11:03:31.189140
8413 11:03:31.189200
8414 11:03:31.189254 ==
8415 11:03:31.192070 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 11:03:31.198810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 11:03:31.198886 ==
8418 11:03:31.198945
8419 11:03:31.198998
8420 11:03:31.199050 TX Vref Scan disable
8421 11:03:31.202307 == TX Byte 0 ==
8422 11:03:31.205672 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8423 11:03:31.212056 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8424 11:03:31.212132 == TX Byte 1 ==
8425 11:03:31.215704 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8426 11:03:31.222183 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8427 11:03:31.222262 ==
8428 11:03:31.225536 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 11:03:31.228842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 11:03:31.228918 ==
8431 11:03:31.240840
8432 11:03:31.244182 TX Vref early break, caculate TX vref
8433 11:03:31.247282 TX Vref=16, minBit 8, minWin=22, winSum=368
8434 11:03:31.250918 TX Vref=18, minBit 8, minWin=22, winSum=378
8435 11:03:31.253836 TX Vref=20, minBit 3, minWin=23, winSum=384
8436 11:03:31.257042 TX Vref=22, minBit 8, minWin=23, winSum=398
8437 11:03:31.260498 TX Vref=24, minBit 8, minWin=23, winSum=409
8438 11:03:31.267589 TX Vref=26, minBit 3, minWin=25, winSum=415
8439 11:03:31.270682 TX Vref=28, minBit 8, minWin=25, winSum=417
8440 11:03:31.273780 TX Vref=30, minBit 5, minWin=25, winSum=415
8441 11:03:31.277106 TX Vref=32, minBit 0, minWin=24, winSum=401
8442 11:03:31.280772 TX Vref=34, minBit 9, minWin=23, winSum=393
8443 11:03:31.287122 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8444 11:03:31.287198
8445 11:03:31.290008 Final TX Range 0 Vref 28
8446 11:03:31.290084
8447 11:03:31.290142 ==
8448 11:03:31.293491 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 11:03:31.297179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 11:03:31.297270 ==
8451 11:03:31.297329
8452 11:03:31.297383
8453 11:03:31.299932 TX Vref Scan disable
8454 11:03:31.306565 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8455 11:03:31.306640 == TX Byte 0 ==
8456 11:03:31.309838 u2DelayCellOfst[0]=14 cells (4 PI)
8457 11:03:31.313324 u2DelayCellOfst[1]=10 cells (3 PI)
8458 11:03:31.316997 u2DelayCellOfst[2]=0 cells (0 PI)
8459 11:03:31.320060 u2DelayCellOfst[3]=7 cells (2 PI)
8460 11:03:31.323083 u2DelayCellOfst[4]=10 cells (3 PI)
8461 11:03:31.326463 u2DelayCellOfst[5]=14 cells (4 PI)
8462 11:03:31.329933 u2DelayCellOfst[6]=14 cells (4 PI)
8463 11:03:31.333146 u2DelayCellOfst[7]=7 cells (2 PI)
8464 11:03:31.336493 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8465 11:03:31.339509 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8466 11:03:31.343297 == TX Byte 1 ==
8467 11:03:31.346185 u2DelayCellOfst[8]=0 cells (0 PI)
8468 11:03:31.349960 u2DelayCellOfst[9]=7 cells (2 PI)
8469 11:03:31.350036 u2DelayCellOfst[10]=14 cells (4 PI)
8470 11:03:31.352718 u2DelayCellOfst[11]=7 cells (2 PI)
8471 11:03:31.356083 u2DelayCellOfst[12]=17 cells (5 PI)
8472 11:03:31.359402 u2DelayCellOfst[13]=17 cells (5 PI)
8473 11:03:31.363121 u2DelayCellOfst[14]=21 cells (6 PI)
8474 11:03:31.366314 u2DelayCellOfst[15]=21 cells (6 PI)
8475 11:03:31.372523 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8476 11:03:31.376334 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8477 11:03:31.376414 DramC Write-DBI on
8478 11:03:31.376474 ==
8479 11:03:31.379258 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 11:03:31.386126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 11:03:31.386202 ==
8482 11:03:31.386261
8483 11:03:31.386315
8484 11:03:31.389070 TX Vref Scan disable
8485 11:03:31.389150 == TX Byte 0 ==
8486 11:03:31.395956 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8487 11:03:31.396033 == TX Byte 1 ==
8488 11:03:31.399142 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8489 11:03:31.402437 DramC Write-DBI off
8490 11:03:31.402513
8491 11:03:31.402572 [DATLAT]
8492 11:03:31.405464 Freq=1600, CH1 RK0
8493 11:03:31.405540
8494 11:03:31.405626 DATLAT Default: 0xf
8495 11:03:31.408737 0, 0xFFFF, sum = 0
8496 11:03:31.408814 1, 0xFFFF, sum = 0
8497 11:03:31.412193 2, 0xFFFF, sum = 0
8498 11:03:31.412270 3, 0xFFFF, sum = 0
8499 11:03:31.415444 4, 0xFFFF, sum = 0
8500 11:03:31.415521 5, 0xFFFF, sum = 0
8501 11:03:31.418937 6, 0xFFFF, sum = 0
8502 11:03:31.419013 7, 0xFFFF, sum = 0
8503 11:03:31.422140 8, 0xFFFF, sum = 0
8504 11:03:31.425391 9, 0xFFFF, sum = 0
8505 11:03:31.425468 10, 0xFFFF, sum = 0
8506 11:03:31.428888 11, 0xFFFF, sum = 0
8507 11:03:31.428965 12, 0xFFFF, sum = 0
8508 11:03:31.432083 13, 0xFFFF, sum = 0
8509 11:03:31.432211 14, 0x0, sum = 1
8510 11:03:31.435475 15, 0x0, sum = 2
8511 11:03:31.435552 16, 0x0, sum = 3
8512 11:03:31.438713 17, 0x0, sum = 4
8513 11:03:31.438790 best_step = 15
8514 11:03:31.438849
8515 11:03:31.438903 ==
8516 11:03:31.441735 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 11:03:31.444976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 11:03:31.445052 ==
8519 11:03:31.448671 RX Vref Scan: 1
8520 11:03:31.448747
8521 11:03:31.451704 Set Vref Range= 24 -> 127
8522 11:03:31.451779
8523 11:03:31.451838 RX Vref 24 -> 127, step: 1
8524 11:03:31.451892
8525 11:03:31.455156 RX Delay 19 -> 252, step: 4
8526 11:03:31.455231
8527 11:03:31.458592 Set Vref, RX VrefLevel [Byte0]: 24
8528 11:03:31.462267 [Byte1]: 24
8529 11:03:31.465150
8530 11:03:31.465266 Set Vref, RX VrefLevel [Byte0]: 25
8531 11:03:31.468564 [Byte1]: 25
8532 11:03:31.472798
8533 11:03:31.472874 Set Vref, RX VrefLevel [Byte0]: 26
8534 11:03:31.475910 [Byte1]: 26
8535 11:03:31.480281
8536 11:03:31.480357 Set Vref, RX VrefLevel [Byte0]: 27
8537 11:03:31.483780 [Byte1]: 27
8538 11:03:31.487797
8539 11:03:31.487873 Set Vref, RX VrefLevel [Byte0]: 28
8540 11:03:31.491352 [Byte1]: 28
8541 11:03:31.495681
8542 11:03:31.495756 Set Vref, RX VrefLevel [Byte0]: 29
8543 11:03:31.498750 [Byte1]: 29
8544 11:03:31.503104
8545 11:03:31.503192 Set Vref, RX VrefLevel [Byte0]: 30
8546 11:03:31.506357 [Byte1]: 30
8547 11:03:31.510623
8548 11:03:31.510698 Set Vref, RX VrefLevel [Byte0]: 31
8549 11:03:31.513833 [Byte1]: 31
8550 11:03:31.518070
8551 11:03:31.518145 Set Vref, RX VrefLevel [Byte0]: 32
8552 11:03:31.521721 [Byte1]: 32
8553 11:03:31.525793
8554 11:03:31.525868 Set Vref, RX VrefLevel [Byte0]: 33
8555 11:03:31.529076 [Byte1]: 33
8556 11:03:31.533473
8557 11:03:31.533552 Set Vref, RX VrefLevel [Byte0]: 34
8558 11:03:31.536767 [Byte1]: 34
8559 11:03:31.540845
8560 11:03:31.540920 Set Vref, RX VrefLevel [Byte0]: 35
8561 11:03:31.544125 [Byte1]: 35
8562 11:03:31.548614
8563 11:03:31.548689 Set Vref, RX VrefLevel [Byte0]: 36
8564 11:03:31.552258 [Byte1]: 36
8565 11:03:31.556123
8566 11:03:31.556198 Set Vref, RX VrefLevel [Byte0]: 37
8567 11:03:31.559288 [Byte1]: 37
8568 11:03:31.563500
8569 11:03:31.563576 Set Vref, RX VrefLevel [Byte0]: 38
8570 11:03:31.567139 [Byte1]: 38
8571 11:03:31.571454
8572 11:03:31.571529 Set Vref, RX VrefLevel [Byte0]: 39
8573 11:03:31.574630 [Byte1]: 39
8574 11:03:31.579208
8575 11:03:31.579283 Set Vref, RX VrefLevel [Byte0]: 40
8576 11:03:31.582030 [Byte1]: 40
8577 11:03:31.586469
8578 11:03:31.586544 Set Vref, RX VrefLevel [Byte0]: 41
8579 11:03:31.589959 [Byte1]: 41
8580 11:03:31.594138
8581 11:03:31.594213 Set Vref, RX VrefLevel [Byte0]: 42
8582 11:03:31.597631 [Byte1]: 42
8583 11:03:31.601348
8584 11:03:31.601424 Set Vref, RX VrefLevel [Byte0]: 43
8585 11:03:31.604840 [Byte1]: 43
8586 11:03:31.609368
8587 11:03:31.609443 Set Vref, RX VrefLevel [Byte0]: 44
8588 11:03:31.612300 [Byte1]: 44
8589 11:03:31.617061
8590 11:03:31.617158 Set Vref, RX VrefLevel [Byte0]: 45
8591 11:03:31.620153 [Byte1]: 45
8592 11:03:31.624554
8593 11:03:31.624629 Set Vref, RX VrefLevel [Byte0]: 46
8594 11:03:31.627709 [Byte1]: 46
8595 11:03:31.631858
8596 11:03:31.631934 Set Vref, RX VrefLevel [Byte0]: 47
8597 11:03:31.635141 [Byte1]: 47
8598 11:03:31.639361
8599 11:03:31.639436 Set Vref, RX VrefLevel [Byte0]: 48
8600 11:03:31.642566 [Byte1]: 48
8601 11:03:31.647142
8602 11:03:31.647217 Set Vref, RX VrefLevel [Byte0]: 49
8603 11:03:31.650213 [Byte1]: 49
8604 11:03:31.654644
8605 11:03:31.654720 Set Vref, RX VrefLevel [Byte0]: 50
8606 11:03:31.658311 [Byte1]: 50
8607 11:03:31.661809
8608 11:03:31.661884 Set Vref, RX VrefLevel [Byte0]: 51
8609 11:03:31.665392 [Byte1]: 51
8610 11:03:31.669926
8611 11:03:31.670004 Set Vref, RX VrefLevel [Byte0]: 52
8612 11:03:31.672890 [Byte1]: 52
8613 11:03:31.677530
8614 11:03:31.677605 Set Vref, RX VrefLevel [Byte0]: 53
8615 11:03:31.680254 [Byte1]: 53
8616 11:03:31.684862
8617 11:03:31.684937 Set Vref, RX VrefLevel [Byte0]: 54
8618 11:03:31.688448 [Byte1]: 54
8619 11:03:31.692635
8620 11:03:31.692711 Set Vref, RX VrefLevel [Byte0]: 55
8621 11:03:31.695929 [Byte1]: 55
8622 11:03:31.699967
8623 11:03:31.700042 Set Vref, RX VrefLevel [Byte0]: 56
8624 11:03:31.703168 [Byte1]: 56
8625 11:03:31.707339
8626 11:03:31.707441 Set Vref, RX VrefLevel [Byte0]: 57
8627 11:03:31.710873 [Byte1]: 57
8628 11:03:31.715304
8629 11:03:31.715380 Set Vref, RX VrefLevel [Byte0]: 58
8630 11:03:31.718743 [Byte1]: 58
8631 11:03:31.722787
8632 11:03:31.722862 Set Vref, RX VrefLevel [Byte0]: 59
8633 11:03:31.726274 [Byte1]: 59
8634 11:03:31.730447
8635 11:03:31.730522 Set Vref, RX VrefLevel [Byte0]: 60
8636 11:03:31.733872 [Byte1]: 60
8637 11:03:31.737779
8638 11:03:31.737854 Set Vref, RX VrefLevel [Byte0]: 61
8639 11:03:31.741662 [Byte1]: 61
8640 11:03:31.745348
8641 11:03:31.748754 Set Vref, RX VrefLevel [Byte0]: 62
8642 11:03:31.751949 [Byte1]: 62
8643 11:03:31.752024
8644 11:03:31.755246 Set Vref, RX VrefLevel [Byte0]: 63
8645 11:03:31.758767 [Byte1]: 63
8646 11:03:31.758843
8647 11:03:31.761808 Set Vref, RX VrefLevel [Byte0]: 64
8648 11:03:31.764979 [Byte1]: 64
8649 11:03:31.765054
8650 11:03:31.768738 Set Vref, RX VrefLevel [Byte0]: 65
8651 11:03:31.771702 [Byte1]: 65
8652 11:03:31.775733
8653 11:03:31.775809 Set Vref, RX VrefLevel [Byte0]: 66
8654 11:03:31.779030 [Byte1]: 66
8655 11:03:31.783146
8656 11:03:31.783221 Set Vref, RX VrefLevel [Byte0]: 67
8657 11:03:31.786640 [Byte1]: 67
8658 11:03:31.791022
8659 11:03:31.791098 Set Vref, RX VrefLevel [Byte0]: 68
8660 11:03:31.794262 [Byte1]: 68
8661 11:03:31.798105
8662 11:03:31.798180 Set Vref, RX VrefLevel [Byte0]: 69
8663 11:03:31.801610 [Byte1]: 69
8664 11:03:31.806162
8665 11:03:31.806239 Set Vref, RX VrefLevel [Byte0]: 70
8666 11:03:31.809409 [Byte1]: 70
8667 11:03:31.813608
8668 11:03:31.813683 Set Vref, RX VrefLevel [Byte0]: 71
8669 11:03:31.816773 [Byte1]: 71
8670 11:03:31.821117
8671 11:03:31.821201 Set Vref, RX VrefLevel [Byte0]: 72
8672 11:03:31.824506 [Byte1]: 72
8673 11:03:31.828911
8674 11:03:31.828987 Set Vref, RX VrefLevel [Byte0]: 73
8675 11:03:31.832023 [Byte1]: 73
8676 11:03:31.836596
8677 11:03:31.836680 Final RX Vref Byte 0 = 57 to rank0
8678 11:03:31.839514 Final RX Vref Byte 1 = 59 to rank0
8679 11:03:31.842890 Final RX Vref Byte 0 = 57 to rank1
8680 11:03:31.845986 Final RX Vref Byte 1 = 59 to rank1==
8681 11:03:31.849145 Dram Type= 6, Freq= 0, CH_1, rank 0
8682 11:03:31.855944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8683 11:03:31.856021 ==
8684 11:03:31.856080 DQS Delay:
8685 11:03:31.859647 DQS0 = 0, DQS1 = 0
8686 11:03:31.859722 DQM Delay:
8687 11:03:31.859781 DQM0 = 132, DQM1 = 127
8688 11:03:31.862573 DQ Delay:
8689 11:03:31.866090 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =132
8690 11:03:31.869277 DQ4 =128, DQ5 =140, DQ6 =144, DQ7 =126
8691 11:03:31.872819 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8692 11:03:31.875725 DQ12 =136, DQ13 =138, DQ14 =134, DQ15 =138
8693 11:03:31.875800
8694 11:03:31.875859
8695 11:03:31.875912
8696 11:03:31.878931 [DramC_TX_OE_Calibration] TA2
8697 11:03:31.883106 Original DQ_B0 (3 6) =30, OEN = 27
8698 11:03:31.885779 Original DQ_B1 (3 6) =30, OEN = 27
8699 11:03:31.889121 24, 0x0, End_B0=24 End_B1=24
8700 11:03:31.892518 25, 0x0, End_B0=25 End_B1=25
8701 11:03:31.892595 26, 0x0, End_B0=26 End_B1=26
8702 11:03:31.895530 27, 0x0, End_B0=27 End_B1=27
8703 11:03:31.899338 28, 0x0, End_B0=28 End_B1=28
8704 11:03:31.902458 29, 0x0, End_B0=29 End_B1=29
8705 11:03:31.902534 30, 0x0, End_B0=30 End_B1=30
8706 11:03:31.905700 31, 0x4141, End_B0=30 End_B1=30
8707 11:03:31.908915 Byte0 end_step=30 best_step=27
8708 11:03:31.911777 Byte1 end_step=30 best_step=27
8709 11:03:31.915561 Byte0 TX OE(2T, 0.5T) = (3, 3)
8710 11:03:31.918624 Byte1 TX OE(2T, 0.5T) = (3, 3)
8711 11:03:31.918700
8712 11:03:31.918758
8713 11:03:31.925231 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8714 11:03:31.928347 CH1 RK0: MR19=303, MR18=F19
8715 11:03:31.935222 CH1_RK0: MR19=0x303, MR18=0xF19, DQSOSC=397, MR23=63, INC=23, DEC=15
8716 11:03:31.935298
8717 11:03:31.938455 ----->DramcWriteLeveling(PI) begin...
8718 11:03:31.938531 ==
8719 11:03:31.941609 Dram Type= 6, Freq= 0, CH_1, rank 1
8720 11:03:31.944784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 11:03:31.944884 ==
8722 11:03:31.948002 Write leveling (Byte 0): 23 => 23
8723 11:03:31.951246 Write leveling (Byte 1): 26 => 26
8724 11:03:31.954915 DramcWriteLeveling(PI) end<-----
8725 11:03:31.954991
8726 11:03:31.955050 ==
8727 11:03:31.957902 Dram Type= 6, Freq= 0, CH_1, rank 1
8728 11:03:31.961120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 11:03:31.964924 ==
8730 11:03:31.965000 [Gating] SW mode calibration
8731 11:03:31.974911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8732 11:03:31.977956 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8733 11:03:31.981142 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 11:03:31.987772 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8735 11:03:31.990703 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8736 11:03:31.994354 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8737 11:03:32.000623 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 11:03:32.004454 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 11:03:32.007507 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 11:03:32.014103 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 11:03:32.016947 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 11:03:32.020220 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8743 11:03:32.027103 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8744 11:03:32.030470 1 5 12 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8745 11:03:32.036878 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 11:03:32.040166 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 11:03:32.043241 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 11:03:32.049857 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 11:03:32.053754 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 11:03:32.056774 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8751 11:03:32.063097 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8752 11:03:32.066753 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8753 11:03:32.069711 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 11:03:32.076484 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 11:03:32.079843 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 11:03:32.083436 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 11:03:32.086248 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 11:03:32.092783 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8759 11:03:32.096502 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8760 11:03:32.099964 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8761 11:03:32.106319 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 11:03:32.109767 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 11:03:32.112775 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 11:03:32.119473 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 11:03:32.122742 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 11:03:32.125766 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 11:03:32.132528 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 11:03:32.136128 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 11:03:32.139065 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 11:03:32.146207 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 11:03:32.149253 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 11:03:32.152387 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 11:03:32.159073 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 11:03:32.162277 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 11:03:32.165545 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8776 11:03:32.172257 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8777 11:03:32.175473 Total UI for P1: 0, mck2ui 16
8778 11:03:32.178526 best dqsien dly found for B0: ( 1, 9, 8)
8779 11:03:32.182060 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 11:03:32.185318 Total UI for P1: 0, mck2ui 16
8781 11:03:32.188644 best dqsien dly found for B1: ( 1, 9, 12)
8782 11:03:32.191755 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8783 11:03:32.195641 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8784 11:03:32.195717
8785 11:03:32.198702 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8786 11:03:32.204944 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8787 11:03:32.205019 [Gating] SW calibration Done
8788 11:03:32.205079 ==
8789 11:03:32.208214 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 11:03:32.214719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 11:03:32.214795 ==
8792 11:03:32.214855 RX Vref Scan: 0
8793 11:03:32.214910
8794 11:03:32.218420 RX Vref 0 -> 0, step: 1
8795 11:03:32.218496
8796 11:03:32.221379 RX Delay 0 -> 252, step: 8
8797 11:03:32.224782 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8798 11:03:32.228347 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8799 11:03:32.231525 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8800 11:03:32.237868 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8801 11:03:32.241090 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8802 11:03:32.244586 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8803 11:03:32.247747 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8804 11:03:32.250917 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8805 11:03:32.257717 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8806 11:03:32.261192 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8807 11:03:32.264358 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8808 11:03:32.267379 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8809 11:03:32.271281 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8810 11:03:32.277944 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8811 11:03:32.281110 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8812 11:03:32.284215 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8813 11:03:32.284389 ==
8814 11:03:32.287939 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 11:03:32.290497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 11:03:32.293992 ==
8817 11:03:32.294067 DQS Delay:
8818 11:03:32.294126 DQS0 = 0, DQS1 = 0
8819 11:03:32.297276 DQM Delay:
8820 11:03:32.297351 DQM0 = 132, DQM1 = 130
8821 11:03:32.301140 DQ Delay:
8822 11:03:32.303811 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =127
8823 11:03:32.307218 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =135
8824 11:03:32.310876 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8825 11:03:32.313832 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8826 11:03:32.313908
8827 11:03:32.313967
8828 11:03:32.314021 ==
8829 11:03:32.316805 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 11:03:32.320114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 11:03:32.323865 ==
8832 11:03:32.323940
8833 11:03:32.323998
8834 11:03:32.324053 TX Vref Scan disable
8835 11:03:32.326970 == TX Byte 0 ==
8836 11:03:32.330410 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8837 11:03:32.333320 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8838 11:03:32.336682 == TX Byte 1 ==
8839 11:03:32.340254 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8840 11:03:32.343528 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8841 11:03:32.346640 ==
8842 11:03:32.349821 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 11:03:32.352994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 11:03:32.353070 ==
8845 11:03:32.366502
8846 11:03:32.369951 TX Vref early break, caculate TX vref
8847 11:03:32.373410 TX Vref=16, minBit 9, minWin=22, winSum=378
8848 11:03:32.376620 TX Vref=18, minBit 8, minWin=23, winSum=389
8849 11:03:32.379446 TX Vref=20, minBit 9, minWin=22, winSum=396
8850 11:03:32.383122 TX Vref=22, minBit 9, minWin=23, winSum=404
8851 11:03:32.386256 TX Vref=24, minBit 9, minWin=23, winSum=406
8852 11:03:32.392814 TX Vref=26, minBit 9, minWin=24, winSum=415
8853 11:03:32.396343 TX Vref=28, minBit 15, minWin=25, winSum=421
8854 11:03:32.399398 TX Vref=30, minBit 9, minWin=24, winSum=421
8855 11:03:32.402492 TX Vref=32, minBit 9, minWin=24, winSum=410
8856 11:03:32.405946 TX Vref=34, minBit 9, minWin=23, winSum=403
8857 11:03:32.412673 TX Vref=36, minBit 8, minWin=23, winSum=395
8858 11:03:32.416101 [TxChooseVref] Worse bit 15, Min win 25, Win sum 421, Final Vref 28
8859 11:03:32.416177
8860 11:03:32.419016 Final TX Range 0 Vref 28
8861 11:03:32.419092
8862 11:03:32.419151 ==
8863 11:03:32.422694 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 11:03:32.425684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 11:03:32.429026 ==
8866 11:03:32.429101
8867 11:03:32.429165
8868 11:03:32.429220 TX Vref Scan disable
8869 11:03:32.436247 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8870 11:03:32.436323 == TX Byte 0 ==
8871 11:03:32.438994 u2DelayCellOfst[0]=14 cells (4 PI)
8872 11:03:32.442642 u2DelayCellOfst[1]=10 cells (3 PI)
8873 11:03:32.446166 u2DelayCellOfst[2]=0 cells (0 PI)
8874 11:03:32.449089 u2DelayCellOfst[3]=7 cells (2 PI)
8875 11:03:32.452339 u2DelayCellOfst[4]=7 cells (2 PI)
8876 11:03:32.455895 u2DelayCellOfst[5]=14 cells (4 PI)
8877 11:03:32.459125 u2DelayCellOfst[6]=14 cells (4 PI)
8878 11:03:32.462318 u2DelayCellOfst[7]=7 cells (2 PI)
8879 11:03:32.465619 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8880 11:03:32.468883 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8881 11:03:32.472185 == TX Byte 1 ==
8882 11:03:32.475452 u2DelayCellOfst[8]=0 cells (0 PI)
8883 11:03:32.478897 u2DelayCellOfst[9]=3 cells (1 PI)
8884 11:03:32.482071 u2DelayCellOfst[10]=14 cells (4 PI)
8885 11:03:32.485393 u2DelayCellOfst[11]=7 cells (2 PI)
8886 11:03:32.488599 u2DelayCellOfst[12]=14 cells (4 PI)
8887 11:03:32.492035 u2DelayCellOfst[13]=17 cells (5 PI)
8888 11:03:32.495318 u2DelayCellOfst[14]=21 cells (6 PI)
8889 11:03:32.498845 u2DelayCellOfst[15]=17 cells (5 PI)
8890 11:03:32.501666 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8891 11:03:32.505067 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8892 11:03:32.508185 DramC Write-DBI on
8893 11:03:32.508260 ==
8894 11:03:32.511401 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 11:03:32.515066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 11:03:32.515142 ==
8897 11:03:32.515200
8898 11:03:32.515254
8899 11:03:32.518932 TX Vref Scan disable
8900 11:03:32.519008 == TX Byte 0 ==
8901 11:03:32.525024 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8902 11:03:32.525100 == TX Byte 1 ==
8903 11:03:32.528334 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8904 11:03:32.531242 DramC Write-DBI off
8905 11:03:32.531318
8906 11:03:32.531378 [DATLAT]
8907 11:03:32.534657 Freq=1600, CH1 RK1
8908 11:03:32.534757
8909 11:03:32.534843 DATLAT Default: 0xf
8910 11:03:32.537795 0, 0xFFFF, sum = 0
8911 11:03:32.537873 1, 0xFFFF, sum = 0
8912 11:03:32.541731 2, 0xFFFF, sum = 0
8913 11:03:32.544647 3, 0xFFFF, sum = 0
8914 11:03:32.544724 4, 0xFFFF, sum = 0
8915 11:03:32.548056 5, 0xFFFF, sum = 0
8916 11:03:32.548135 6, 0xFFFF, sum = 0
8917 11:03:32.551528 7, 0xFFFF, sum = 0
8918 11:03:32.551606 8, 0xFFFF, sum = 0
8919 11:03:32.555078 9, 0xFFFF, sum = 0
8920 11:03:32.555155 10, 0xFFFF, sum = 0
8921 11:03:32.557990 11, 0xFFFF, sum = 0
8922 11:03:32.558067 12, 0xFFFF, sum = 0
8923 11:03:32.561419 13, 0xFFFF, sum = 0
8924 11:03:32.561496 14, 0x0, sum = 1
8925 11:03:32.564795 15, 0x0, sum = 2
8926 11:03:32.564872 16, 0x0, sum = 3
8927 11:03:32.567843 17, 0x0, sum = 4
8928 11:03:32.567920 best_step = 15
8929 11:03:32.567979
8930 11:03:32.568032 ==
8931 11:03:32.570879 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 11:03:32.577957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 11:03:32.578038 ==
8934 11:03:32.578097 RX Vref Scan: 0
8935 11:03:32.578153
8936 11:03:32.580897 RX Vref 0 -> 0, step: 1
8937 11:03:32.580973
8938 11:03:32.584471 RX Delay 19 -> 252, step: 4
8939 11:03:32.587462 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8940 11:03:32.590918 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8941 11:03:32.593988 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8942 11:03:32.600911 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8943 11:03:32.604128 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8944 11:03:32.607060 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8945 11:03:32.610766 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8946 11:03:32.613829 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8947 11:03:32.620366 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8948 11:03:32.623955 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8949 11:03:32.626766 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8950 11:03:32.630497 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8951 11:03:32.637109 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8952 11:03:32.640469 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8953 11:03:32.643645 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8954 11:03:32.646944 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8955 11:03:32.647020 ==
8956 11:03:32.650348 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 11:03:32.656762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 11:03:32.656838 ==
8959 11:03:32.656897 DQS Delay:
8960 11:03:32.659668 DQS0 = 0, DQS1 = 0
8961 11:03:32.659743 DQM Delay:
8962 11:03:32.659845 DQM0 = 131, DQM1 = 127
8963 11:03:32.663171 DQ Delay:
8964 11:03:32.666987 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8965 11:03:32.669939 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =130
8966 11:03:32.673494 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8967 11:03:32.677047 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8968 11:03:32.677123
8969 11:03:32.677224
8970 11:03:32.677279
8971 11:03:32.679768 [DramC_TX_OE_Calibration] TA2
8972 11:03:32.683520 Original DQ_B0 (3 6) =30, OEN = 27
8973 11:03:32.686577 Original DQ_B1 (3 6) =30, OEN = 27
8974 11:03:32.690063 24, 0x0, End_B0=24 End_B1=24
8975 11:03:32.690140 25, 0x0, End_B0=25 End_B1=25
8976 11:03:32.693076 26, 0x0, End_B0=26 End_B1=26
8977 11:03:32.696532 27, 0x0, End_B0=27 End_B1=27
8978 11:03:32.699555 28, 0x0, End_B0=28 End_B1=28
8979 11:03:32.702764 29, 0x0, End_B0=29 End_B1=29
8980 11:03:32.702840 30, 0x0, End_B0=30 End_B1=30
8981 11:03:32.706475 31, 0x4141, End_B0=30 End_B1=30
8982 11:03:32.710075 Byte0 end_step=30 best_step=27
8983 11:03:32.712741 Byte1 end_step=30 best_step=27
8984 11:03:32.716263 Byte0 TX OE(2T, 0.5T) = (3, 3)
8985 11:03:32.719415 Byte1 TX OE(2T, 0.5T) = (3, 3)
8986 11:03:32.719515
8987 11:03:32.719604
8988 11:03:32.726406 [DQSOSCAuto] RK1, (LSB)MR18= 0x101d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
8989 11:03:32.729667 CH1 RK1: MR19=303, MR18=101D
8990 11:03:32.735928 CH1_RK1: MR19=0x303, MR18=0x101D, DQSOSC=395, MR23=63, INC=23, DEC=15
8991 11:03:32.739406 [RxdqsGatingPostProcess] freq 1600
8992 11:03:32.742821 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8993 11:03:32.746076 best DQS0 dly(2T, 0.5T) = (1, 1)
8994 11:03:32.749569 best DQS1 dly(2T, 0.5T) = (1, 1)
8995 11:03:32.752296 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8996 11:03:32.755877 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8997 11:03:32.759233 best DQS0 dly(2T, 0.5T) = (1, 1)
8998 11:03:32.762245 best DQS1 dly(2T, 0.5T) = (1, 1)
8999 11:03:32.765862 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9000 11:03:32.768860 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9001 11:03:32.772799 Pre-setting of DQS Precalculation
9002 11:03:32.775598 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9003 11:03:32.785070 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9004 11:03:32.791666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9005 11:03:32.791765
9006 11:03:32.791849
9007 11:03:32.795146 [Calibration Summary] 3200 Mbps
9008 11:03:32.795222 CH 0, Rank 0
9009 11:03:32.798737 SW Impedance : PASS
9010 11:03:32.798813 DUTY Scan : NO K
9011 11:03:32.801926 ZQ Calibration : PASS
9012 11:03:32.804949 Jitter Meter : NO K
9013 11:03:32.805030 CBT Training : PASS
9014 11:03:32.808320 Write leveling : PASS
9015 11:03:32.811616 RX DQS gating : PASS
9016 11:03:32.811704 RX DQ/DQS(RDDQC) : PASS
9017 11:03:32.815171 TX DQ/DQS : PASS
9018 11:03:32.818290 RX DATLAT : PASS
9019 11:03:32.818365 RX DQ/DQS(Engine): PASS
9020 11:03:32.821541 TX OE : PASS
9021 11:03:32.821617 All Pass.
9022 11:03:32.821676
9023 11:03:32.824766 CH 0, Rank 1
9024 11:03:32.824842 SW Impedance : PASS
9025 11:03:32.827980 DUTY Scan : NO K
9026 11:03:32.831341 ZQ Calibration : PASS
9027 11:03:32.831440 Jitter Meter : NO K
9028 11:03:32.835018 CBT Training : PASS
9029 11:03:32.837885 Write leveling : PASS
9030 11:03:32.837960 RX DQS gating : PASS
9031 11:03:32.841257 RX DQ/DQS(RDDQC) : PASS
9032 11:03:32.844584 TX DQ/DQS : PASS
9033 11:03:32.844659 RX DATLAT : PASS
9034 11:03:32.848365 RX DQ/DQS(Engine): PASS
9035 11:03:32.848441 TX OE : PASS
9036 11:03:32.850922 All Pass.
9037 11:03:32.850997
9038 11:03:32.851056 CH 1, Rank 0
9039 11:03:32.854556 SW Impedance : PASS
9040 11:03:32.857917 DUTY Scan : NO K
9041 11:03:32.857993 ZQ Calibration : PASS
9042 11:03:32.861437 Jitter Meter : NO K
9043 11:03:32.861513 CBT Training : PASS
9044 11:03:32.864650 Write leveling : PASS
9045 11:03:32.867786 RX DQS gating : PASS
9046 11:03:32.867862 RX DQ/DQS(RDDQC) : PASS
9047 11:03:32.871465 TX DQ/DQS : PASS
9048 11:03:32.874238 RX DATLAT : PASS
9049 11:03:32.874313 RX DQ/DQS(Engine): PASS
9050 11:03:32.877472 TX OE : PASS
9051 11:03:32.877548 All Pass.
9052 11:03:32.877607
9053 11:03:32.880922 CH 1, Rank 1
9054 11:03:32.881023 SW Impedance : PASS
9055 11:03:32.884021 DUTY Scan : NO K
9056 11:03:32.887521 ZQ Calibration : PASS
9057 11:03:32.887597 Jitter Meter : NO K
9058 11:03:32.890982 CBT Training : PASS
9059 11:03:32.894368 Write leveling : PASS
9060 11:03:32.894443 RX DQS gating : PASS
9061 11:03:32.897489 RX DQ/DQS(RDDQC) : PASS
9062 11:03:32.900749 TX DQ/DQS : PASS
9063 11:03:32.900848 RX DATLAT : PASS
9064 11:03:32.904143 RX DQ/DQS(Engine): PASS
9065 11:03:32.907518 TX OE : PASS
9066 11:03:32.907594 All Pass.
9067 11:03:32.907652
9068 11:03:32.907706 DramC Write-DBI on
9069 11:03:32.910782 PER_BANK_REFRESH: Hybrid Mode
9070 11:03:32.913798 TX_TRACKING: ON
9071 11:03:32.920458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9072 11:03:32.930244 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9073 11:03:32.936916 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9074 11:03:32.940250 [FAST_K] Save calibration result to emmc
9075 11:03:32.943367 sync common calibartion params.
9076 11:03:32.946901 sync cbt_mode0:1, 1:1
9077 11:03:32.946978 dram_init: ddr_geometry: 2
9078 11:03:32.950507 dram_init: ddr_geometry: 2
9079 11:03:32.953800 dram_init: ddr_geometry: 2
9080 11:03:32.956674 0:dram_rank_size:100000000
9081 11:03:32.956751 1:dram_rank_size:100000000
9082 11:03:32.963174 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9083 11:03:32.966531 DFS_SHUFFLE_HW_MODE: ON
9084 11:03:32.970250 dramc_set_vcore_voltage set vcore to 725000
9085 11:03:32.970326 Read voltage for 1600, 0
9086 11:03:32.973287 Vio18 = 0
9087 11:03:32.973363 Vcore = 725000
9088 11:03:32.973422 Vdram = 0
9089 11:03:32.976533 Vddq = 0
9090 11:03:32.976609 Vmddr = 0
9091 11:03:32.980090 switch to 3200 Mbps bootup
9092 11:03:32.980165 [DramcRunTimeConfig]
9093 11:03:32.983368 PHYPLL
9094 11:03:32.983444 DPM_CONTROL_AFTERK: ON
9095 11:03:32.986782 PER_BANK_REFRESH: ON
9096 11:03:32.989831 REFRESH_OVERHEAD_REDUCTION: ON
9097 11:03:32.989907 CMD_PICG_NEW_MODE: OFF
9098 11:03:32.993183 XRTWTW_NEW_MODE: ON
9099 11:03:32.993260 XRTRTR_NEW_MODE: ON
9100 11:03:32.996509 TX_TRACKING: ON
9101 11:03:32.996586 RDSEL_TRACKING: OFF
9102 11:03:32.999359 DQS Precalculation for DVFS: ON
9103 11:03:33.002861 RX_TRACKING: OFF
9104 11:03:33.002937 HW_GATING DBG: ON
9105 11:03:33.006323 ZQCS_ENABLE_LP4: ON
9106 11:03:33.006399 RX_PICG_NEW_MODE: ON
9107 11:03:33.009425 TX_PICG_NEW_MODE: ON
9108 11:03:33.009502 ENABLE_RX_DCM_DPHY: ON
9109 11:03:33.013351 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9110 11:03:33.016343 DUMMY_READ_FOR_TRACKING: OFF
9111 11:03:33.019204 !!! SPM_CONTROL_AFTERK: OFF
9112 11:03:33.022619 !!! SPM could not control APHY
9113 11:03:33.022695 IMPEDANCE_TRACKING: ON
9114 11:03:33.025803 TEMP_SENSOR: ON
9115 11:03:33.025879 HW_SAVE_FOR_SR: OFF
9116 11:03:33.029335 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9117 11:03:33.032288 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9118 11:03:33.035756 Read ODT Tracking: ON
9119 11:03:33.039402 Refresh Rate DeBounce: ON
9120 11:03:33.039477 DFS_NO_QUEUE_FLUSH: ON
9121 11:03:33.042366 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9122 11:03:33.045460 ENABLE_DFS_RUNTIME_MRW: OFF
9123 11:03:33.048722 DDR_RESERVE_NEW_MODE: ON
9124 11:03:33.048831 MR_CBT_SWITCH_FREQ: ON
9125 11:03:33.052296 =========================
9126 11:03:33.071603 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9127 11:03:33.074442 dram_init: ddr_geometry: 2
9128 11:03:33.092661 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9129 11:03:33.096522 dram_init: dram init end (result: 0)
9130 11:03:33.102679 DRAM-K: Full calibration passed in 24446 msecs
9131 11:03:33.105993 MRC: failed to locate region type 0.
9132 11:03:33.106069 DRAM rank0 size:0x100000000,
9133 11:03:33.109227 DRAM rank1 size=0x100000000
9134 11:03:33.119224 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9135 11:03:33.126034 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9136 11:03:33.135542 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9137 11:03:33.142530 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9138 11:03:33.142606 DRAM rank0 size:0x100000000,
9139 11:03:33.145397 DRAM rank1 size=0x100000000
9140 11:03:33.145480 CBMEM:
9141 11:03:33.148649 IMD: root @ 0xfffff000 254 entries.
9142 11:03:33.151915 IMD: root @ 0xffffec00 62 entries.
9143 11:03:33.158790 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9144 11:03:33.161902 WARNING: RO_VPD is uninitialized or empty.
9145 11:03:33.165303 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9146 11:03:33.173176 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9147 11:03:33.185855 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9148 11:03:33.197382 BS: romstage times (exec / console): total (unknown) / 23965 ms
9149 11:03:33.197461
9150 11:03:33.197538
9151 11:03:33.206871 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9152 11:03:33.210395 ARM64: Exception handlers installed.
9153 11:03:33.213747 ARM64: Testing exception
9154 11:03:33.217243 ARM64: Done test exception
9155 11:03:33.217321 Enumerating buses...
9156 11:03:33.220517 Show all devs... Before device enumeration.
9157 11:03:33.223566 Root Device: enabled 1
9158 11:03:33.227209 CPU_CLUSTER: 0: enabled 1
9159 11:03:33.227288 CPU: 00: enabled 1
9160 11:03:33.230504 Compare with tree...
9161 11:03:33.230581 Root Device: enabled 1
9162 11:03:33.233420 CPU_CLUSTER: 0: enabled 1
9163 11:03:33.236861 CPU: 00: enabled 1
9164 11:03:33.236939 Root Device scanning...
9165 11:03:33.239994 scan_static_bus for Root Device
9166 11:03:33.243394 CPU_CLUSTER: 0 enabled
9167 11:03:33.246606 scan_static_bus for Root Device done
9168 11:03:33.249886 scan_bus: bus Root Device finished in 8 msecs
9169 11:03:33.249964 done
9170 11:03:33.256267 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9171 11:03:33.259809 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9172 11:03:33.266374 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9173 11:03:33.269717 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9174 11:03:33.272730 Allocating resources...
9175 11:03:33.276255 Reading resources...
9176 11:03:33.279839 Root Device read_resources bus 0 link: 0
9177 11:03:33.283180 DRAM rank0 size:0x100000000,
9178 11:03:33.283257 DRAM rank1 size=0x100000000
9179 11:03:33.290033 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9180 11:03:33.290134 CPU: 00 missing read_resources
9181 11:03:33.296244 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9182 11:03:33.299594 Root Device read_resources bus 0 link: 0 done
9183 11:03:33.302920 Done reading resources.
9184 11:03:33.306255 Show resources in subtree (Root Device)...After reading.
9185 11:03:33.309133 Root Device child on link 0 CPU_CLUSTER: 0
9186 11:03:33.312638 CPU_CLUSTER: 0 child on link 0 CPU: 00
9187 11:03:33.322873 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9188 11:03:33.322949 CPU: 00
9189 11:03:33.325604 Root Device assign_resources, bus 0 link: 0
9190 11:03:33.328951 CPU_CLUSTER: 0 missing set_resources
9191 11:03:33.335938 Root Device assign_resources, bus 0 link: 0 done
9192 11:03:33.336015 Done setting resources.
9193 11:03:33.342065 Show resources in subtree (Root Device)...After assigning values.
9194 11:03:33.345835 Root Device child on link 0 CPU_CLUSTER: 0
9195 11:03:33.349103 CPU_CLUSTER: 0 child on link 0 CPU: 00
9196 11:03:33.359121 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9197 11:03:33.359197 CPU: 00
9198 11:03:33.362145 Done allocating resources.
9199 11:03:33.368529 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9200 11:03:33.368606 Enabling resources...
9201 11:03:33.371832 done.
9202 11:03:33.375266 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9203 11:03:33.378520 Initializing devices...
9204 11:03:33.378622 Root Device init
9205 11:03:33.381921 init hardware done!
9206 11:03:33.381997 0x00000018: ctrlr->caps
9207 11:03:33.384800 52.000 MHz: ctrlr->f_max
9208 11:03:33.388491 0.400 MHz: ctrlr->f_min
9209 11:03:33.388568 0x40ff8080: ctrlr->voltages
9210 11:03:33.391687 sclk: 390625
9211 11:03:33.391762 Bus Width = 1
9212 11:03:33.395053 sclk: 390625
9213 11:03:33.395129 Bus Width = 1
9214 11:03:33.398129 Early init status = 3
9215 11:03:33.401375 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9216 11:03:33.405502 in-header: 03 fc 00 00 01 00 00 00
9217 11:03:33.408836 in-data: 00
9218 11:03:33.412135 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9219 11:03:33.417977 in-header: 03 fd 00 00 00 00 00 00
9220 11:03:33.421387 in-data:
9221 11:03:33.424320 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9222 11:03:33.428727 in-header: 03 fc 00 00 01 00 00 00
9223 11:03:33.432089 in-data: 00
9224 11:03:33.435180 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9225 11:03:33.441219 in-header: 03 fd 00 00 00 00 00 00
9226 11:03:33.444415 in-data:
9227 11:03:33.447644 [SSUSB] Setting up USB HOST controller...
9228 11:03:33.451376 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9229 11:03:33.454119 [SSUSB] phy power-on done.
9230 11:03:33.457500 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9231 11:03:33.464366 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9232 11:03:33.467976 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9233 11:03:33.473895 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9234 11:03:33.480958 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9235 11:03:33.487430 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9236 11:03:33.493706 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9237 11:03:33.500491 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9238 11:03:33.504025 SPM: binary array size = 0x9dc
9239 11:03:33.506955 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9240 11:03:33.513590 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9241 11:03:33.520262 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9242 11:03:33.526922 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9243 11:03:33.530126 configure_display: Starting display init
9244 11:03:33.564519 anx7625_power_on_init: Init interface.
9245 11:03:33.567783 anx7625_disable_pd_protocol: Disabled PD feature.
9246 11:03:33.570684 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9247 11:03:33.598982 anx7625_start_dp_work: Secure OCM version=00
9248 11:03:33.601781 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9249 11:03:33.617078 sp_tx_get_edid_block: EDID Block = 1
9250 11:03:33.719800 Extracted contents:
9251 11:03:33.722682 header: 00 ff ff ff ff ff ff 00
9252 11:03:33.725897 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9253 11:03:33.729628 version: 01 04
9254 11:03:33.732682 basic params: 95 1f 11 78 0a
9255 11:03:33.735935 chroma info: 76 90 94 55 54 90 27 21 50 54
9256 11:03:33.739183 established: 00 00 00
9257 11:03:33.745576 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9258 11:03:33.752681 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9259 11:03:33.755466 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9260 11:03:33.762285 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9261 11:03:33.768942 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9262 11:03:33.772209 extensions: 00
9263 11:03:33.772285 checksum: fb
9264 11:03:33.772344
9265 11:03:33.779040 Manufacturer: IVO Model 57d Serial Number 0
9266 11:03:33.779116 Made week 0 of 2020
9267 11:03:33.781798 EDID version: 1.4
9268 11:03:33.781873 Digital display
9269 11:03:33.785118 6 bits per primary color channel
9270 11:03:33.785232 DisplayPort interface
9271 11:03:33.788646 Maximum image size: 31 cm x 17 cm
9272 11:03:33.791897 Gamma: 220%
9273 11:03:33.791972 Check DPMS levels
9274 11:03:33.798327 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9275 11:03:33.801791 First detailed timing is preferred timing
9276 11:03:33.801868 Established timings supported:
9277 11:03:33.804959 Standard timings supported:
9278 11:03:33.808746 Detailed timings
9279 11:03:33.811801 Hex of detail: 383680a07038204018303c0035ae10000019
9280 11:03:33.818503 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9281 11:03:33.821953 0780 0798 07c8 0820 hborder 0
9282 11:03:33.825111 0438 043b 0447 0458 vborder 0
9283 11:03:33.828098 -hsync -vsync
9284 11:03:33.828174 Did detailed timing
9285 11:03:33.834772 Hex of detail: 000000000000000000000000000000000000
9286 11:03:33.838291 Manufacturer-specified data, tag 0
9287 11:03:33.841303 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9288 11:03:33.844913 ASCII string: InfoVision
9289 11:03:33.847736 Hex of detail: 000000fe00523134304e574635205248200a
9290 11:03:33.851599 ASCII string: R140NWF5 RH
9291 11:03:33.851699 Checksum
9292 11:03:33.854531 Checksum: 0xfb (valid)
9293 11:03:33.857826 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9294 11:03:33.861119 DSI data_rate: 832800000 bps
9295 11:03:33.867408 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9296 11:03:33.871197 anx7625_parse_edid: pixelclock(138800).
9297 11:03:33.874614 hactive(1920), hsync(48), hfp(24), hbp(88)
9298 11:03:33.877846 vactive(1080), vsync(12), vfp(3), vbp(17)
9299 11:03:33.881306 anx7625_dsi_config: config dsi.
9300 11:03:33.887437 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9301 11:03:33.901637 anx7625_dsi_config: success to config DSI
9302 11:03:33.904724 anx7625_dp_start: MIPI phy setup OK.
9303 11:03:33.908332 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9304 11:03:33.911236 mtk_ddp_mode_set invalid vrefresh 60
9305 11:03:33.914481 main_disp_path_setup
9306 11:03:33.914556 ovl_layer_smi_id_en
9307 11:03:33.918244 ovl_layer_smi_id_en
9308 11:03:33.918318 ccorr_config
9309 11:03:33.918376 aal_config
9310 11:03:33.921354 gamma_config
9311 11:03:33.921440 postmask_config
9312 11:03:33.924623 dither_config
9313 11:03:33.928146 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9314 11:03:33.934557 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9315 11:03:33.938109 Root Device init finished in 555 msecs
9316 11:03:33.940705 CPU_CLUSTER: 0 init
9317 11:03:33.947811 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9318 11:03:33.954084 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9319 11:03:33.954159 APU_MBOX 0x190000b0 = 0x10001
9320 11:03:33.957679 APU_MBOX 0x190001b0 = 0x10001
9321 11:03:33.960831 APU_MBOX 0x190005b0 = 0x10001
9322 11:03:33.964251 APU_MBOX 0x190006b0 = 0x10001
9323 11:03:33.970333 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9324 11:03:33.980736 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9325 11:03:33.992584 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9326 11:03:33.999759 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9327 11:03:34.011396 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9328 11:03:34.020274 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9329 11:03:34.023610 CPU_CLUSTER: 0 init finished in 81 msecs
9330 11:03:34.026998 Devices initialized
9331 11:03:34.030132 Show all devs... After init.
9332 11:03:34.030208 Root Device: enabled 1
9333 11:03:34.033516 CPU_CLUSTER: 0: enabled 1
9334 11:03:34.036515 CPU: 00: enabled 1
9335 11:03:34.039879 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9336 11:03:34.043102 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9337 11:03:34.046352 ELOG: NV offset 0x57f000 size 0x1000
9338 11:03:34.053666 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9339 11:03:34.060077 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9340 11:03:34.063456 ELOG: Event(17) added with size 13 at 2024-07-10 11:03:33 UTC
9341 11:03:34.069821 out: cmd=0x121: 03 db 21 01 00 00 00 00
9342 11:03:34.073327 in-header: 03 3e 00 00 2c 00 00 00
9343 11:03:34.083091 in-data: 00 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9344 11:03:34.090105 ELOG: Event(A1) added with size 10 at 2024-07-10 11:03:33 UTC
9345 11:03:34.095918 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9346 11:03:34.102943 ELOG: Event(A0) added with size 9 at 2024-07-10 11:03:33 UTC
9347 11:03:34.106237 elog_add_boot_reason: Logged dev mode boot
9348 11:03:34.112949 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9349 11:03:34.113025 Finalize devices...
9350 11:03:34.116160 Devices finalized
9351 11:03:34.119033 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9352 11:03:34.122500 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9353 11:03:34.125983 in-header: 03 07 00 00 08 00 00 00
9354 11:03:34.129122 in-data: aa e4 47 04 13 02 00 00
9355 11:03:34.132660 Chrome EC: UHEPI supported
9356 11:03:34.139386 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9357 11:03:34.142120 in-header: 03 a9 00 00 08 00 00 00
9358 11:03:34.145454 in-data: 84 60 60 08 00 00 00 00
9359 11:03:34.152082 ELOG: Event(91) added with size 10 at 2024-07-10 11:03:33 UTC
9360 11:03:34.155829 Chrome EC: clear events_b mask to 0x0000000020004000
9361 11:03:34.162468 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9362 11:03:34.166138 in-header: 03 fd 00 00 00 00 00 00
9363 11:03:34.169376 in-data:
9364 11:03:34.172915 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9365 11:03:34.175970 Writing coreboot table at 0xffe64000
9366 11:03:34.182745 0. 000000000010a000-0000000000113fff: RAMSTAGE
9367 11:03:34.186090 1. 0000000040000000-00000000400fffff: RAM
9368 11:03:34.189684 2. 0000000040100000-000000004032afff: RAMSTAGE
9369 11:03:34.192652 3. 000000004032b000-00000000545fffff: RAM
9370 11:03:34.196082 4. 0000000054600000-000000005465ffff: BL31
9371 11:03:34.199122 5. 0000000054660000-00000000ffe63fff: RAM
9372 11:03:34.205939 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9373 11:03:34.209370 7. 0000000100000000-000000023fffffff: RAM
9374 11:03:34.212373 Passing 5 GPIOs to payload:
9375 11:03:34.215768 NAME | PORT | POLARITY | VALUE
9376 11:03:34.222363 EC in RW | 0x000000aa | low | undefined
9377 11:03:34.225348 EC interrupt | 0x00000005 | low | undefined
9378 11:03:34.232299 TPM interrupt | 0x000000ab | high | undefined
9379 11:03:34.235434 SD card detect | 0x00000011 | high | undefined
9380 11:03:34.238916 speaker enable | 0x00000093 | high | undefined
9381 11:03:34.245066 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9382 11:03:34.248520 in-header: 03 f9 00 00 02 00 00 00
9383 11:03:34.248596 in-data: 02 00
9384 11:03:34.251739 ADC[4]: Raw value=902586 ID=7
9385 11:03:34.255422 ADC[3]: Raw value=213546 ID=1
9386 11:03:34.255498 RAM Code: 0x71
9387 11:03:34.258424 ADC[6]: Raw value=75000 ID=0
9388 11:03:34.261918 ADC[5]: Raw value=213177 ID=1
9389 11:03:34.261993 SKU Code: 0x1
9390 11:03:34.268290 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8b8b
9391 11:03:34.271594 coreboot table: 964 bytes.
9392 11:03:34.274586 IMD ROOT 0. 0xfffff000 0x00001000
9393 11:03:34.278407 IMD SMALL 1. 0xffffe000 0x00001000
9394 11:03:34.281164 RO MCACHE 2. 0xffffc000 0x00001104
9395 11:03:34.284543 CONSOLE 3. 0xfff7c000 0x00080000
9396 11:03:34.288441 FMAP 4. 0xfff7b000 0x00000452
9397 11:03:34.288533 TIME STAMP 5. 0xfff7a000 0x00000910
9398 11:03:34.291566 VBOOT WORK 6. 0xfff66000 0x00014000
9399 11:03:34.294778 RAMOOPS 7. 0xffe66000 0x00100000
9400 11:03:34.297773 COREBOOT 8. 0xffe64000 0x00002000
9401 11:03:34.301323 IMD small region:
9402 11:03:34.304699 IMD ROOT 0. 0xffffec00 0x00000400
9403 11:03:34.307874 VPD 1. 0xffffeb80 0x0000006c
9404 11:03:34.311128 MMC STATUS 2. 0xffffeb60 0x00000004
9405 11:03:34.318128 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9406 11:03:34.324158 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9407 11:03:34.363282 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9408 11:03:34.366396 Checking segment from ROM address 0x40100000
9409 11:03:34.369749 Checking segment from ROM address 0x4010001c
9410 11:03:34.376402 Loading segment from ROM address 0x40100000
9411 11:03:34.376479 code (compression=0)
9412 11:03:34.386145 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9413 11:03:34.393073 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9414 11:03:34.393158 it's not compressed!
9415 11:03:34.399547 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9416 11:03:34.406014 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9417 11:03:34.423309 Loading segment from ROM address 0x4010001c
9418 11:03:34.423386 Entry Point 0x80000000
9419 11:03:34.426764 Loaded segments
9420 11:03:34.430225 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9421 11:03:34.436670 Jumping to boot code at 0x80000000(0xffe64000)
9422 11:03:34.443359 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9423 11:03:34.449432 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9424 11:03:34.457992 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9425 11:03:34.461372 Checking segment from ROM address 0x40100000
9426 11:03:34.464844 Checking segment from ROM address 0x4010001c
9427 11:03:34.471324 Loading segment from ROM address 0x40100000
9428 11:03:34.471400 code (compression=1)
9429 11:03:34.478054 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9430 11:03:34.487495 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9431 11:03:34.487572 using LZMA
9432 11:03:34.496032 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9433 11:03:34.502765 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9434 11:03:34.506417 Loading segment from ROM address 0x4010001c
9435 11:03:34.506486 Entry Point 0x54601000
9436 11:03:34.509461 Loaded segments
9437 11:03:34.512917 NOTICE: MT8192 bl31_setup
9438 11:03:34.520163 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9439 11:03:34.523078 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9440 11:03:34.527006 WARNING: region 0:
9441 11:03:34.529786 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 11:03:34.529863 WARNING: region 1:
9443 11:03:34.536397 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9444 11:03:34.539862 WARNING: region 2:
9445 11:03:34.543287 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9446 11:03:34.546468 WARNING: region 3:
9447 11:03:34.549569 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9448 11:03:34.553064 WARNING: region 4:
9449 11:03:34.559486 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 11:03:34.559563 WARNING: region 5:
9451 11:03:34.563004 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 11:03:34.566468 WARNING: region 6:
9453 11:03:34.569886 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 11:03:34.572859 WARNING: region 7:
9455 11:03:34.576301 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 11:03:34.582726 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9457 11:03:34.586194 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9458 11:03:34.589782 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9459 11:03:34.596484 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9460 11:03:34.599240 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9461 11:03:34.605957 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9462 11:03:34.609284 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9463 11:03:34.612473 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9464 11:03:34.619188 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9465 11:03:34.622880 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9466 11:03:34.629213 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9467 11:03:34.632139 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9468 11:03:34.635666 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9469 11:03:34.642345 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9470 11:03:34.645662 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9471 11:03:34.648623 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9472 11:03:34.655594 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9473 11:03:34.658461 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9474 11:03:34.665492 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9475 11:03:34.668662 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9476 11:03:34.671767 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9477 11:03:34.678708 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9478 11:03:34.682070 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9479 11:03:34.688359 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9480 11:03:34.691829 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9481 11:03:34.694924 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9482 11:03:34.701524 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9483 11:03:34.704930 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9484 11:03:34.711240 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9485 11:03:34.714796 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9486 11:03:34.721014 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9487 11:03:34.724458 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9488 11:03:34.727564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9489 11:03:34.731109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9490 11:03:34.737900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9491 11:03:34.740752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9492 11:03:34.744366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9493 11:03:34.747643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9494 11:03:34.754396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9495 11:03:34.757801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9496 11:03:34.760574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9497 11:03:34.767002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9498 11:03:34.770257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9499 11:03:34.773663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9500 11:03:34.776912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9501 11:03:34.783466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9502 11:03:34.786995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9503 11:03:34.790667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9504 11:03:34.796732 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9505 11:03:34.800049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9506 11:03:34.807137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9507 11:03:34.810023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9508 11:03:34.813388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9509 11:03:34.819790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9510 11:03:34.823770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9511 11:03:34.830029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9512 11:03:34.833262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9513 11:03:34.839737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9514 11:03:34.843114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9515 11:03:34.849652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9516 11:03:34.852703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9517 11:03:34.856288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9518 11:03:34.862777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9519 11:03:34.865916 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9520 11:03:34.872643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9521 11:03:34.876014 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9522 11:03:34.882515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9523 11:03:34.885903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9524 11:03:34.892787 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9525 11:03:34.896125 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9526 11:03:34.898855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9527 11:03:34.905902 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9528 11:03:34.908892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9529 11:03:34.915490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9530 11:03:34.918567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9531 11:03:34.925075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9532 11:03:34.928601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9533 11:03:34.935226 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9534 11:03:34.938194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9535 11:03:34.945072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9536 11:03:34.948718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9537 11:03:34.951623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9538 11:03:34.958165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9539 11:03:34.961526 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9540 11:03:34.968299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9541 11:03:34.971216 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9542 11:03:34.978245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9543 11:03:34.981877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9544 11:03:34.987862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9545 11:03:34.991401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9546 11:03:34.994832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9547 11:03:35.001695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9548 11:03:35.004771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9549 11:03:35.010966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9550 11:03:35.014146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9551 11:03:35.021210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9552 11:03:35.024208 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9553 11:03:35.027569 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9554 11:03:35.030870 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9555 11:03:35.037519 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9556 11:03:35.040789 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9557 11:03:35.043885 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9558 11:03:35.050795 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9559 11:03:35.053666 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9560 11:03:35.060432 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9561 11:03:35.063856 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9562 11:03:35.066989 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9563 11:03:35.073714 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9564 11:03:35.076750 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9565 11:03:35.083614 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9566 11:03:35.086957 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9567 11:03:35.093113 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9568 11:03:35.096327 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9569 11:03:35.099703 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9570 11:03:35.106627 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9571 11:03:35.109947 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9572 11:03:35.113167 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9573 11:03:35.120005 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9574 11:03:35.122894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9575 11:03:35.126203 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9576 11:03:35.132802 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9577 11:03:35.135797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9578 11:03:35.139177 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9579 11:03:35.142744 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9580 11:03:35.149294 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9581 11:03:35.152698 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9582 11:03:35.159286 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9583 11:03:35.162581 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9584 11:03:35.168703 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9585 11:03:35.172030 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9586 11:03:35.175462 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9587 11:03:35.182212 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9588 11:03:35.185668 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9589 11:03:35.188800 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9590 11:03:35.195397 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9591 11:03:35.198698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9592 11:03:35.205129 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9593 11:03:35.208686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9594 11:03:35.214856 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9595 11:03:35.218068 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9596 11:03:35.221444 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9597 11:03:35.228003 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9598 11:03:35.231385 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9599 11:03:35.238333 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9600 11:03:35.241267 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9601 11:03:35.244439 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9602 11:03:35.251236 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9603 11:03:35.254743 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9604 11:03:35.261454 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9605 11:03:35.264587 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9606 11:03:35.267682 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9607 11:03:35.274448 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9608 11:03:35.277855 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9609 11:03:35.283955 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9610 11:03:35.287412 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9611 11:03:35.290849 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9612 11:03:35.297248 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9613 11:03:35.300729 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9614 11:03:35.307575 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9615 11:03:35.310569 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9616 11:03:35.313890 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9617 11:03:35.320285 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9618 11:03:35.324173 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9619 11:03:35.330286 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9620 11:03:35.333616 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9621 11:03:35.337077 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9622 11:03:35.343786 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9623 11:03:35.347291 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9624 11:03:35.353573 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9625 11:03:35.356978 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9626 11:03:35.359882 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9627 11:03:35.366904 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9628 11:03:35.369978 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9629 11:03:35.376878 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9630 11:03:35.380006 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9631 11:03:35.383123 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9632 11:03:35.389802 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9633 11:03:35.393091 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9634 11:03:35.399303 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9635 11:03:35.402822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9636 11:03:35.406085 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9637 11:03:35.412800 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9638 11:03:35.415976 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9639 11:03:35.422900 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9640 11:03:35.425735 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9641 11:03:35.429036 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9642 11:03:35.435659 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9643 11:03:35.438812 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9644 11:03:35.445911 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9645 11:03:35.448963 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9646 11:03:35.455481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9647 11:03:35.458704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9648 11:03:35.462417 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9649 11:03:35.468575 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9650 11:03:35.472087 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9651 11:03:35.478893 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9652 11:03:35.481641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9653 11:03:35.488449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9654 11:03:35.491687 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9655 11:03:35.495090 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9656 11:03:35.501561 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9657 11:03:35.505276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9658 11:03:35.511488 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9659 11:03:35.514740 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9660 11:03:35.517820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9661 11:03:35.524804 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9662 11:03:35.528010 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9663 11:03:35.534746 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9664 11:03:35.537564 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9665 11:03:35.544511 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9666 11:03:35.548207 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9667 11:03:35.551087 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9668 11:03:35.557984 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9669 11:03:35.561280 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9670 11:03:35.567190 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9671 11:03:35.570683 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9672 11:03:35.577084 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9673 11:03:35.580543 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9674 11:03:35.587597 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9675 11:03:35.590665 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9676 11:03:35.593970 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9677 11:03:35.600470 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9678 11:03:35.603890 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9679 11:03:35.610118 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9680 11:03:35.613524 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9681 11:03:35.619822 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9682 11:03:35.623226 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9683 11:03:35.626694 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9684 11:03:35.632970 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9685 11:03:35.636582 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9686 11:03:35.640033 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9687 11:03:35.642793 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9688 11:03:35.649820 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9689 11:03:35.653360 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9690 11:03:35.656183 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9691 11:03:35.663020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9692 11:03:35.666282 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9693 11:03:35.672491 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9694 11:03:35.675857 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9695 11:03:35.679383 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9696 11:03:35.685640 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9697 11:03:35.689013 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9698 11:03:35.692746 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9699 11:03:35.699212 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9700 11:03:35.701985 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9701 11:03:35.708784 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9702 11:03:35.712249 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9703 11:03:35.715415 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9704 11:03:35.722128 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9705 11:03:35.725076 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9706 11:03:35.729001 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9707 11:03:35.735403 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9708 11:03:35.738702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9709 11:03:35.741819 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9710 11:03:35.748463 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9711 11:03:35.751978 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9712 11:03:35.758403 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9713 11:03:35.762313 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9714 11:03:35.765333 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9715 11:03:35.771806 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9716 11:03:35.775010 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9717 11:03:35.781700 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9718 11:03:35.785005 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9719 11:03:35.788239 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9720 11:03:35.794395 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9721 11:03:35.797850 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9722 11:03:35.801417 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9723 11:03:35.807651 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9724 11:03:35.811211 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9725 11:03:35.814494 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9726 11:03:35.820994 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9727 11:03:35.824416 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9728 11:03:35.827992 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9729 11:03:35.830685 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9730 11:03:35.834084 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9731 11:03:35.840995 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9732 11:03:35.843847 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9733 11:03:35.847497 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9734 11:03:35.854169 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9735 11:03:35.856914 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9736 11:03:35.860534 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9737 11:03:35.864005 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9738 11:03:35.870709 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9739 11:03:35.874183 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9740 11:03:35.880437 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9741 11:03:35.883893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9742 11:03:35.890219 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9743 11:03:35.893443 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9744 11:03:35.896778 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9745 11:03:35.903196 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9746 11:03:35.907652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9747 11:03:35.913388 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9748 11:03:35.916687 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9749 11:03:35.919650 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9750 11:03:35.926525 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9751 11:03:35.929556 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9752 11:03:35.936067 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9753 11:03:35.940042 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9754 11:03:35.946259 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9755 11:03:35.949398 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9756 11:03:35.952575 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9757 11:03:35.959466 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9758 11:03:35.962962 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9759 11:03:35.969636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9760 11:03:35.972787 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9761 11:03:35.975911 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9762 11:03:35.982732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9763 11:03:35.985869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9764 11:03:35.992024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9765 11:03:35.995353 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9766 11:03:36.002507 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9767 11:03:36.005988 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9768 11:03:36.008817 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9769 11:03:36.015609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9770 11:03:36.018629 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9771 11:03:36.025881 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9772 11:03:36.029041 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9773 11:03:36.031845 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9774 11:03:36.038633 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9775 11:03:36.041688 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9776 11:03:36.048898 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9777 11:03:36.052011 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9778 11:03:36.058721 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9779 11:03:36.061684 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9780 11:03:36.064933 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9781 11:03:36.071775 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9782 11:03:36.074919 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9783 11:03:36.081398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9784 11:03:36.084913 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9785 11:03:36.088282 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9786 11:03:36.094528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9787 11:03:36.097886 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9788 11:03:36.104451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9789 11:03:36.108113 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9790 11:03:36.114404 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9791 11:03:36.118074 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9792 11:03:36.121055 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9793 11:03:36.127841 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9794 11:03:36.131332 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9795 11:03:36.137507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9796 11:03:36.140911 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9797 11:03:36.147377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9798 11:03:36.150916 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9799 11:03:36.154172 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9800 11:03:36.160655 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9801 11:03:36.163952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9802 11:03:36.170423 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9803 11:03:36.174032 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9804 11:03:36.176819 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9805 11:03:36.183349 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9806 11:03:36.186620 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9807 11:03:36.193439 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9808 11:03:36.196950 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9809 11:03:36.199992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9810 11:03:36.206663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9811 11:03:36.210176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9812 11:03:36.216417 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9813 11:03:36.219667 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9814 11:03:36.227048 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9815 11:03:36.229857 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9816 11:03:36.236294 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9817 11:03:36.239668 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9818 11:03:36.242875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9819 11:03:36.249319 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9820 11:03:36.253130 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9821 11:03:36.259424 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9822 11:03:36.262578 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9823 11:03:36.269346 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9824 11:03:36.273427 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9825 11:03:36.279435 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9826 11:03:36.282342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9827 11:03:36.288936 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9828 11:03:36.291849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9829 11:03:36.298559 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9830 11:03:36.301720 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9831 11:03:36.305597 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9832 11:03:36.312212 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9833 11:03:36.315738 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9834 11:03:36.321959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9835 11:03:36.325258 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9836 11:03:36.331916 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9837 11:03:36.334757 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9838 11:03:36.341608 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9839 11:03:36.344895 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9840 11:03:36.351288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9841 11:03:36.354489 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9842 11:03:36.357686 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9843 11:03:36.364395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9844 11:03:36.367757 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9845 11:03:36.374676 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9846 11:03:36.377744 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9847 11:03:36.384304 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9848 11:03:36.387724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9849 11:03:36.391087 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9850 11:03:36.397867 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9851 11:03:36.400549 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9852 11:03:36.407373 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9853 11:03:36.410621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9854 11:03:36.417365 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9855 11:03:36.420563 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9856 11:03:36.427048 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9857 11:03:36.431127 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9858 11:03:36.434140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9859 11:03:36.440568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9860 11:03:36.444096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9861 11:03:36.450464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9862 11:03:36.453727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9863 11:03:36.460881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9864 11:03:36.464339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9865 11:03:36.470758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9866 11:03:36.473453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9867 11:03:36.477085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9868 11:03:36.483693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9869 11:03:36.486722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9870 11:03:36.493611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9871 11:03:36.496882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9872 11:03:36.503919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9873 11:03:36.506741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9874 11:03:36.513260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9875 11:03:36.516745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9876 11:03:36.523408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9877 11:03:36.526484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9878 11:03:36.533163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9879 11:03:36.536595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9880 11:03:36.543277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9881 11:03:36.546437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9882 11:03:36.553084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9883 11:03:36.556519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9884 11:03:36.562665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9885 11:03:36.566222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9886 11:03:36.572818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9887 11:03:36.579618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9888 11:03:36.582528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9889 11:03:36.589424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9890 11:03:36.592630 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9891 11:03:36.592732 INFO: [APUAPC] vio 0
9892 11:03:36.600162 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9893 11:03:36.602897 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9894 11:03:36.606798 INFO: [APUAPC] D0_APC_0: 0x400510
9895 11:03:36.609748 INFO: [APUAPC] D0_APC_1: 0x0
9896 11:03:36.613189 INFO: [APUAPC] D0_APC_2: 0x1540
9897 11:03:36.616386 INFO: [APUAPC] D0_APC_3: 0x0
9898 11:03:36.619772 INFO: [APUAPC] D1_APC_0: 0xffffffff
9899 11:03:36.622849 INFO: [APUAPC] D1_APC_1: 0xffffffff
9900 11:03:36.626730 INFO: [APUAPC] D1_APC_2: 0x3fffff
9901 11:03:36.629843 INFO: [APUAPC] D1_APC_3: 0x0
9902 11:03:36.632701 INFO: [APUAPC] D2_APC_0: 0xffffffff
9903 11:03:36.636113 INFO: [APUAPC] D2_APC_1: 0xffffffff
9904 11:03:36.639490 INFO: [APUAPC] D2_APC_2: 0x3fffff
9905 11:03:36.642944 INFO: [APUAPC] D2_APC_3: 0x0
9906 11:03:36.645694 INFO: [APUAPC] D3_APC_0: 0xffffffff
9907 11:03:36.649202 INFO: [APUAPC] D3_APC_1: 0xffffffff
9908 11:03:36.652604 INFO: [APUAPC] D3_APC_2: 0x3fffff
9909 11:03:36.656091 INFO: [APUAPC] D3_APC_3: 0x0
9910 11:03:36.659479 INFO: [APUAPC] D4_APC_0: 0xffffffff
9911 11:03:36.662487 INFO: [APUAPC] D4_APC_1: 0xffffffff
9912 11:03:36.665946 INFO: [APUAPC] D4_APC_2: 0x3fffff
9913 11:03:36.669027 INFO: [APUAPC] D4_APC_3: 0x0
9914 11:03:36.672565 INFO: [APUAPC] D5_APC_0: 0xffffffff
9915 11:03:36.675492 INFO: [APUAPC] D5_APC_1: 0xffffffff
9916 11:03:36.678681 INFO: [APUAPC] D5_APC_2: 0x3fffff
9917 11:03:36.682269 INFO: [APUAPC] D5_APC_3: 0x0
9918 11:03:36.685473 INFO: [APUAPC] D6_APC_0: 0xffffffff
9919 11:03:36.688761 INFO: [APUAPC] D6_APC_1: 0xffffffff
9920 11:03:36.692382 INFO: [APUAPC] D6_APC_2: 0x3fffff
9921 11:03:36.692458 INFO: [APUAPC] D6_APC_3: 0x0
9922 11:03:36.698629 INFO: [APUAPC] D7_APC_0: 0xffffffff
9923 11:03:36.702066 INFO: [APUAPC] D7_APC_1: 0xffffffff
9924 11:03:36.705376 INFO: [APUAPC] D7_APC_2: 0x3fffff
9925 11:03:36.705451 INFO: [APUAPC] D7_APC_3: 0x0
9926 11:03:36.708991 INFO: [APUAPC] D8_APC_0: 0xffffffff
9927 11:03:36.715387 INFO: [APUAPC] D8_APC_1: 0xffffffff
9928 11:03:36.718456 INFO: [APUAPC] D8_APC_2: 0x3fffff
9929 11:03:36.718534 INFO: [APUAPC] D8_APC_3: 0x0
9930 11:03:36.721980 INFO: [APUAPC] D9_APC_0: 0xffffffff
9931 11:03:36.725113 INFO: [APUAPC] D9_APC_1: 0xffffffff
9932 11:03:36.728536 INFO: [APUAPC] D9_APC_2: 0x3fffff
9933 11:03:36.731719 INFO: [APUAPC] D9_APC_3: 0x0
9934 11:03:36.734960 INFO: [APUAPC] D10_APC_0: 0xffffffff
9935 11:03:36.738408 INFO: [APUAPC] D10_APC_1: 0xffffffff
9936 11:03:36.741500 INFO: [APUAPC] D10_APC_2: 0x3fffff
9937 11:03:36.745500 INFO: [APUAPC] D10_APC_3: 0x0
9938 11:03:36.748246 INFO: [APUAPC] D11_APC_0: 0xffffffff
9939 11:03:36.751583 INFO: [APUAPC] D11_APC_1: 0xffffffff
9940 11:03:36.755030 INFO: [APUAPC] D11_APC_2: 0x3fffff
9941 11:03:36.758272 INFO: [APUAPC] D11_APC_3: 0x0
9942 11:03:36.761982 INFO: [APUAPC] D12_APC_0: 0xffffffff
9943 11:03:36.768081 INFO: [APUAPC] D12_APC_1: 0xffffffff
9944 11:03:36.771536 INFO: [APUAPC] D12_APC_2: 0x3fffff
9945 11:03:36.771613 INFO: [APUAPC] D12_APC_3: 0x0
9946 11:03:36.774623 INFO: [APUAPC] D13_APC_0: 0xffffffff
9947 11:03:36.781327 INFO: [APUAPC] D13_APC_1: 0xffffffff
9948 11:03:36.784965 INFO: [APUAPC] D13_APC_2: 0x3fffff
9949 11:03:36.785041 INFO: [APUAPC] D13_APC_3: 0x0
9950 11:03:36.791584 INFO: [APUAPC] D14_APC_0: 0xffffffff
9951 11:03:36.794778 INFO: [APUAPC] D14_APC_1: 0xffffffff
9952 11:03:36.797857 INFO: [APUAPC] D14_APC_2: 0x3fffff
9953 11:03:36.797933 INFO: [APUAPC] D14_APC_3: 0x0
9954 11:03:36.804492 INFO: [APUAPC] D15_APC_0: 0xffffffff
9955 11:03:36.808169 INFO: [APUAPC] D15_APC_1: 0xffffffff
9956 11:03:36.811102 INFO: [APUAPC] D15_APC_2: 0x3fffff
9957 11:03:36.814612 INFO: [APUAPC] D15_APC_3: 0x0
9958 11:03:36.814688 INFO: [APUAPC] APC_CON: 0x4
9959 11:03:36.817759 INFO: [NOCDAPC] D0_APC_0: 0x0
9960 11:03:36.821245 INFO: [NOCDAPC] D0_APC_1: 0x0
9961 11:03:36.824450 INFO: [NOCDAPC] D1_APC_0: 0x0
9962 11:03:36.827844 INFO: [NOCDAPC] D1_APC_1: 0xfff
9963 11:03:36.831036 INFO: [NOCDAPC] D2_APC_0: 0x0
9964 11:03:36.834670 INFO: [NOCDAPC] D2_APC_1: 0xfff
9965 11:03:36.837825 INFO: [NOCDAPC] D3_APC_0: 0x0
9966 11:03:36.841168 INFO: [NOCDAPC] D3_APC_1: 0xfff
9967 11:03:36.844587 INFO: [NOCDAPC] D4_APC_0: 0x0
9968 11:03:36.844663 INFO: [NOCDAPC] D4_APC_1: 0xfff
9969 11:03:36.847673 INFO: [NOCDAPC] D5_APC_0: 0x0
9970 11:03:36.850706 INFO: [NOCDAPC] D5_APC_1: 0xfff
9971 11:03:36.854095 INFO: [NOCDAPC] D6_APC_0: 0x0
9972 11:03:36.857416 INFO: [NOCDAPC] D6_APC_1: 0xfff
9973 11:03:36.860841 INFO: [NOCDAPC] D7_APC_0: 0x0
9974 11:03:36.863659 INFO: [NOCDAPC] D7_APC_1: 0xfff
9975 11:03:36.867203 INFO: [NOCDAPC] D8_APC_0: 0x0
9976 11:03:36.870696 INFO: [NOCDAPC] D8_APC_1: 0xfff
9977 11:03:36.873618 INFO: [NOCDAPC] D9_APC_0: 0x0
9978 11:03:36.876938 INFO: [NOCDAPC] D9_APC_1: 0xfff
9979 11:03:36.880357 INFO: [NOCDAPC] D10_APC_0: 0x0
9980 11:03:36.883927 INFO: [NOCDAPC] D10_APC_1: 0xfff
9981 11:03:36.884002 INFO: [NOCDAPC] D11_APC_0: 0x0
9982 11:03:36.887180 INFO: [NOCDAPC] D11_APC_1: 0xfff
9983 11:03:36.890169 INFO: [NOCDAPC] D12_APC_0: 0x0
9984 11:03:36.893533 INFO: [NOCDAPC] D12_APC_1: 0xfff
9985 11:03:36.896760 INFO: [NOCDAPC] D13_APC_0: 0x0
9986 11:03:36.900186 INFO: [NOCDAPC] D13_APC_1: 0xfff
9987 11:03:36.903105 INFO: [NOCDAPC] D14_APC_0: 0x0
9988 11:03:36.906378 INFO: [NOCDAPC] D14_APC_1: 0xfff
9989 11:03:36.910046 INFO: [NOCDAPC] D15_APC_0: 0x0
9990 11:03:36.913558 INFO: [NOCDAPC] D15_APC_1: 0xfff
9991 11:03:36.916302 INFO: [NOCDAPC] APC_CON: 0x4
9992 11:03:36.919557 INFO: [APUAPC] set_apusys_apc done
9993 11:03:36.923123 INFO: [DEVAPC] devapc_init done
9994 11:03:36.926702 INFO: GICv3 without legacy support detected.
9995 11:03:36.929481 INFO: ARM GICv3 driver initialized in EL3
9996 11:03:36.932959 INFO: Maximum SPI INTID supported: 639
9997 11:03:36.939432 INFO: BL31: Initializing runtime services
9998 11:03:36.942723 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9999 11:03:36.946436 INFO: SPM: enable CPC mode
10000 11:03:36.952525 INFO: mcdi ready for mcusys-off-idle and system suspend
10001 11:03:36.956055 INFO: BL31: Preparing for EL3 exit to normal world
10002 11:03:36.959599 INFO: Entry point address = 0x80000000
10003 11:03:36.962515 INFO: SPSR = 0x8
10004 11:03:36.968128
10005 11:03:36.968196
10006 11:03:36.968258
10007 11:03:36.971542 Starting depthcharge on Spherion...
10008 11:03:36.971617
10009 11:03:36.971678 Wipe memory regions:
10010 11:03:36.971732
10011 11:03:36.972379 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10012 11:03:36.972475 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10013 11:03:36.972548 Setting prompt string to ['asurada:']
10014 11:03:36.972620 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10015 11:03:36.974654 [0x00000040000000, 0x00000054600000)
10016 11:03:37.096490
10017 11:03:37.096588 [0x00000054660000, 0x00000080000000)
10018 11:03:37.357080
10019 11:03:37.357229 [0x000000821a7280, 0x000000ffe64000)
10020 11:03:38.101082
10021 11:03:38.101235 [0x00000100000000, 0x00000240000000)
10022 11:03:39.989552
10023 11:03:39.993038 Initializing XHCI USB controller at 0x11200000.
10024 11:03:41.030944
10025 11:03:41.034385 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10026 11:03:41.034470
10027 11:03:41.034530
10028 11:03:41.034793 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10029 11:03:41.034870 Sending line: 'tftpboot 192.168.201.1 14786858/tftp-deploy-wtiz35rr/kernel/image.itb 14786858/tftp-deploy-wtiz35rr/kernel/cmdline '
10031 11:03:41.135314 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 11:03:41.135391 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10033 11:03:41.139709 asurada: tftpboot 192.168.201.1 14786858/tftp-deploy-wtiz35rr/kernel/image.ittp-deploy-wtiz35rr/kernel/cmdline
10034 11:03:41.139808
10035 11:03:41.139903 Waiting for link
10036 11:03:41.297617
10037 11:03:41.297726 R8152: Initializing
10038 11:03:41.297787
10039 11:03:41.301114 Version 6 (ocp_data = 5c30)
10040 11:03:41.301253
10041 11:03:41.304123 R8152: Done initializing
10042 11:03:41.304217
10043 11:03:41.304299 Adding net device
10044 11:03:43.303662
10045 11:03:43.303777 done.
10046 11:03:43.303837
10047 11:03:43.303892 MAC: 00:24:32:30:7c:7b
10048 11:03:43.303945
10049 11:03:43.307117 Sending DHCP discover... done.
10050 11:03:43.307191
10051 11:03:43.310924 Waiting for reply... done.
10052 11:03:43.311037
10053 11:03:43.313510 Sending DHCP request... done.
10054 11:03:43.313579
10055 11:03:43.313636 Waiting for reply... done.
10056 11:03:43.313690
10057 11:03:43.317013 My ip is 192.168.201.14
10058 11:03:43.317102
10059 11:03:43.319982 The DHCP server ip is 192.168.201.1
10060 11:03:43.320051
10061 11:03:43.323508 TFTP server IP predefined by user: 192.168.201.1
10062 11:03:43.323575
10063 11:03:43.329846 Bootfile predefined by user: 14786858/tftp-deploy-wtiz35rr/kernel/image.itb
10064 11:03:43.329921
10065 11:03:43.333658 Sending tftp read request... done.
10066 11:03:43.333754
10067 11:03:43.340172 Waiting for the transfer...
10068 11:03:43.340249
10069 11:03:43.884630 00000000 ################################################################
10070 11:03:43.884741
10071 11:03:44.431713 00080000 ################################################################
10072 11:03:44.431829
10073 11:03:44.971286 00100000 ################################################################
10074 11:03:44.971399
10075 11:03:45.531291 00180000 ################################################################
10076 11:03:45.531441
10077 11:03:46.093836 00200000 ################################################################
10078 11:03:46.093952
10079 11:03:46.637392 00280000 ################################################################
10080 11:03:46.637508
10081 11:03:47.172006 00300000 ################################################################
10082 11:03:47.172123
10083 11:03:47.693578 00380000 ################################################################
10084 11:03:47.693701
10085 11:03:48.223991 00400000 ################################################################
10086 11:03:48.224111
10087 11:03:48.759387 00480000 ################################################################
10088 11:03:48.759502
10089 11:03:49.287138 00500000 ################################################################
10090 11:03:49.287253
10091 11:03:49.822146 00580000 ################################################################
10092 11:03:49.822258
10093 11:03:50.358830 00600000 ################################################################
10094 11:03:50.358945
10095 11:03:50.889371 00680000 ################################################################
10096 11:03:50.889487
10097 11:03:51.415830 00700000 ################################################################
10098 11:03:51.415972
10099 11:03:51.952522 00780000 ################################################################
10100 11:03:51.952637
10101 11:03:52.487806 00800000 ################################################################
10102 11:03:52.487947
10103 11:03:53.017990 00880000 ################################################################
10104 11:03:53.018110
10105 11:03:53.579742 00900000 ################################################################
10106 11:03:53.579885
10107 11:03:54.114353 00980000 ################################################################
10108 11:03:54.114507
10109 11:03:54.646199 00a00000 ################################################################
10110 11:03:54.646324
10111 11:03:55.163033 00a80000 ################################################################
10112 11:03:55.163166
10113 11:03:55.682646 00b00000 ################################################################
10114 11:03:55.682786
10115 11:03:56.203662 00b80000 ################################################################
10116 11:03:56.203782
10117 11:03:56.723693 00c00000 ################################################################
10118 11:03:56.723836
10119 11:03:57.248261 00c80000 ################################################################
10120 11:03:57.248396
10121 11:03:57.777399 00d00000 ################################################################
10122 11:03:57.777547
10123 11:03:58.301257 00d80000 ################################################################
10124 11:03:58.301404
10125 11:03:58.819891 00e00000 ################################################################
10126 11:03:58.820050
10127 11:03:59.336159 00e80000 ################################################################
10128 11:03:59.336282
10129 11:03:59.852968 00f00000 ################################################################
10130 11:03:59.853109
10131 11:04:00.368998 00f80000 ################################################################
10132 11:04:00.369146
10133 11:04:00.883922 01000000 ################################################################
10134 11:04:00.884059
10135 11:04:01.411764 01080000 ################################################################
10136 11:04:01.411878
10137 11:04:01.924050 01100000 ################################################################
10138 11:04:01.924171
10139 11:04:02.432336 01180000 ################################################################
10140 11:04:02.432451
10141 11:04:02.942193 01200000 ################################################################
10142 11:04:02.942307
10143 11:04:03.452751 01280000 ################################################################
10144 11:04:03.452866
10145 11:04:03.960273 01300000 ################################################################
10146 11:04:03.960428
10147 11:04:04.472652 01380000 ################################################################
10148 11:04:04.472778
10149 11:04:05.006594 01400000 ################################################################
10150 11:04:05.006706
10151 11:04:05.516910 01480000 ################################################################
10152 11:04:05.517040
10153 11:04:06.029757 01500000 ################################################################
10154 11:04:06.029881
10155 11:04:06.534712 01580000 ################################################################
10156 11:04:06.534838
10157 11:04:07.055527 01600000 ################################################################
10158 11:04:07.055676
10159 11:04:07.567784 01680000 ################################################################
10160 11:04:07.567906
10161 11:04:08.080667 01700000 ################################################################
10162 11:04:08.080810
10163 11:04:08.594704 01780000 ################################################################
10164 11:04:08.594847
10165 11:04:09.110651 01800000 ################################################################
10166 11:04:09.110764
10167 11:04:09.622899 01880000 ################################################################
10168 11:04:09.623088
10169 11:04:10.182707 01900000 ################################################################
10170 11:04:10.182882
10171 11:04:10.793371 01980000 ################################################################
10172 11:04:10.793497
10173 11:04:11.421142 01a00000 ################################################################
10174 11:04:11.421324
10175 11:04:12.049919 01a80000 ################################################################
10176 11:04:12.050035
10177 11:04:12.707746 01b00000 ################################################################
10178 11:04:12.708258
10179 11:04:13.374532 01b80000 ################################################################
10180 11:04:13.374986
10181 11:04:14.028837 01c00000 ################################################################
10182 11:04:14.029324
10183 11:04:14.677932 01c80000 ################################################################
10184 11:04:14.678385
10185 11:04:15.357612 01d00000 ################################################################
10186 11:04:15.358062
10187 11:04:16.040594 01d80000 ################################################################
10188 11:04:16.041125
10189 11:04:16.720816 01e00000 ################################################################
10190 11:04:16.721334
10191 11:04:17.392439 01e80000 ################################################################
10192 11:04:17.393062
10193 11:04:18.074165 01f00000 ################################################################
10194 11:04:18.074630
10195 11:04:18.747844 01f80000 ################################################################
10196 11:04:18.748290
10197 11:04:19.398131 02000000 ################################################################
10198 11:04:19.398240
10199 11:04:19.907645 02080000 ##################################################### done.
10200 11:04:19.907756
10201 11:04:19.911376 The bootfile was 34507974 bytes long.
10202 11:04:19.911517
10203 11:04:19.914424 Sending tftp read request... done.
10204 11:04:19.914508
10205 11:04:19.914576 Waiting for the transfer...
10206 11:04:19.914643
10207 11:04:19.917733 00000000 # done.
10208 11:04:19.917824
10209 11:04:19.924547 Command line loaded dynamically from TFTP file: 14786858/tftp-deploy-wtiz35rr/kernel/cmdline
10210 11:04:19.924645
10211 11:04:19.937843 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10212 11:04:19.940711
10213 11:04:19.940849 Loading FIT.
10214 11:04:19.940999
10215 11:04:19.944430 Image ramdisk-1 has 21342431 bytes.
10216 11:04:19.944636
10217 11:04:19.947263 Image fdt-1 has 47258 bytes.
10218 11:04:19.947427
10219 11:04:19.950846 Image kernel-1 has 13116259 bytes.
10220 11:04:19.951031
10221 11:04:19.957318 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10222 11:04:19.957541
10223 11:04:19.977215 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10224 11:04:19.977720
10225 11:04:19.980501 Choosing best match conf-1 for compat google,spherion-rev2.
10226 11:04:19.985571
10227 11:04:19.989731 Connected to device vid:did:rid of 1ae0:0028:00
10228 11:04:19.998038
10229 11:04:20.001085 tpm_get_response: command 0x17b, return code 0x0
10230 11:04:20.001524
10231 11:04:20.004423 ec_init: CrosEC protocol v3 supported (256, 248)
10232 11:04:20.008276
10233 11:04:20.011770 tpm_cleanup: add release locality here.
10234 11:04:20.012164
10235 11:04:20.012486 Shutting down all USB controllers.
10236 11:04:20.015289
10237 11:04:20.015692 Removing current net device
10238 11:04:20.016030
10239 11:04:20.021941 Exiting depthcharge with code 4 at timestamp: 72330987
10240 11:04:20.022335
10241 11:04:20.025423 LZMA decompressing kernel-1 to 0x821a6718
10242 11:04:20.025819
10243 11:04:20.028614 LZMA decompressing kernel-1 to 0x40000000
10244 11:04:21.644054
10245 11:04:21.644534 jumping to kernel
10246 11:04:21.646464 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10247 11:04:21.646933 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10248 11:04:21.647274 Setting prompt string to ['Linux version [0-9]']
10249 11:04:21.647593 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10250 11:04:21.647927 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10251 11:04:21.725394
10252 11:04:21.728809 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10253 11:04:21.732285 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10254 11:04:21.732864 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10255 11:04:21.733290 Setting prompt string to []
10256 11:04:21.733695 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10257 11:04:21.734099 Using line separator: #'\n'#
10258 11:04:21.734485 No login prompt set.
10259 11:04:21.734834 Parsing kernel messages
10260 11:04:21.735127 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10261 11:04:21.735663 [login-action] Waiting for messages, (timeout 00:03:36)
10262 11:04:21.736114 Waiting using forced prompt support (timeout 00:01:48)
10263 11:04:21.751316 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10264 11:04:21.754747 [ 0.000000] random: crng init done
10265 11:04:21.757803 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10266 11:04:21.761334 [ 0.000000] efi: UEFI not found.
10267 11:04:21.771054 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10268 11:04:21.777980 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10269 11:04:21.788016 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10270 11:04:21.797787 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10271 11:04:21.804164 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10272 11:04:21.807304 [ 0.000000] printk: bootconsole [mtk8250] enabled
10273 11:04:21.816391 [ 0.000000] NUMA: No NUMA configuration found
10274 11:04:21.822959 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10275 11:04:21.829707 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10276 11:04:21.830127 [ 0.000000] Zone ranges:
10277 11:04:21.836175 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10278 11:04:21.839074 [ 0.000000] DMA32 empty
10279 11:04:21.845818 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10280 11:04:21.849176 [ 0.000000] Movable zone start for each node
10281 11:04:21.852689 [ 0.000000] Early memory node ranges
10282 11:04:21.858929 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10283 11:04:21.865474 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10284 11:04:21.871877 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10285 11:04:21.878574 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10286 11:04:21.885256 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10287 11:04:21.891688 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10288 11:04:21.949658 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10289 11:04:21.956317 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10290 11:04:21.963177 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10291 11:04:21.966397 [ 0.000000] psci: probing for conduit method from DT.
10292 11:04:21.972493 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10293 11:04:21.976133 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10294 11:04:21.982633 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10295 11:04:21.985668 [ 0.000000] psci: SMC Calling Convention v1.2
10296 11:04:21.992404 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10297 11:04:21.995862 [ 0.000000] Detected VIPT I-cache on CPU0
10298 11:04:22.002496 [ 0.000000] CPU features: detected: GIC system register CPU interface
10299 11:04:22.008880 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10300 11:04:22.015563 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10301 11:04:22.022370 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10302 11:04:22.032141 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10303 11:04:22.038792 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10304 11:04:22.042148 [ 0.000000] alternatives: applying boot alternatives
10305 11:04:22.048650 [ 0.000000] Fallback order for Node 0: 0
10306 11:04:22.054991 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10307 11:04:22.058389 [ 0.000000] Policy zone: Normal
10308 11:04:22.071678 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10309 11:04:22.081227 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10310 11:04:22.094205 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10311 11:04:22.103861 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10312 11:04:22.110651 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10313 11:04:22.113809 <6>[ 0.000000] software IO TLB: area num 8.
10314 11:04:22.171701 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10315 11:04:22.320908 <6>[ 0.000000] Memory: 7943216K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 409552K reserved, 32768K cma-reserved)
10316 11:04:22.327806 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10317 11:04:22.334655 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10318 11:04:22.337686 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10319 11:04:22.343999 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10320 11:04:22.351081 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10321 11:04:22.354143 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10322 11:04:22.363824 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10323 11:04:22.370861 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10324 11:04:22.377072 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10325 11:04:22.383470 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10326 11:04:22.386864 <6>[ 0.000000] GICv3: 608 SPIs implemented
10327 11:04:22.390570 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10328 11:04:22.397104 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10329 11:04:22.400094 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10330 11:04:22.407538 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10331 11:04:22.419868 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10332 11:04:22.433305 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10333 11:04:22.439570 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10334 11:04:22.447579 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10335 11:04:22.461039 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10336 11:04:22.467307 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10337 11:04:22.474052 <6>[ 0.009178] Console: colour dummy device 80x25
10338 11:04:22.484003 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10339 11:04:22.490673 <6>[ 0.024407] pid_max: default: 32768 minimum: 301
10340 11:04:22.494065 <6>[ 0.029280] LSM: Security Framework initializing
10341 11:04:22.500856 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10342 11:04:22.510060 <6>[ 0.042033] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10343 11:04:22.519980 <6>[ 0.051445] cblist_init_generic: Setting adjustable number of callback queues.
10344 11:04:22.526692 <6>[ 0.058888] cblist_init_generic: Setting shift to 3 and lim to 1.
10345 11:04:22.532953 <6>[ 0.065227] cblist_init_generic: Setting adjustable number of callback queues.
10346 11:04:22.539628 <6>[ 0.072699] cblist_init_generic: Setting shift to 3 and lim to 1.
10347 11:04:22.542889 <6>[ 0.079100] rcu: Hierarchical SRCU implementation.
10348 11:04:22.549531 <6>[ 0.084115] rcu: Max phase no-delay instances is 1000.
10349 11:04:22.556730 <6>[ 0.091140] EFI services will not be available.
10350 11:04:22.559630 <6>[ 0.096108] smp: Bringing up secondary CPUs ...
10351 11:04:22.568562 <6>[ 0.101161] Detected VIPT I-cache on CPU1
10352 11:04:22.575280 <6>[ 0.101233] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10353 11:04:22.581919 <6>[ 0.101265] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10354 11:04:22.585235 <6>[ 0.101611] Detected VIPT I-cache on CPU2
10355 11:04:22.594739 <6>[ 0.101664] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10356 11:04:22.601560 <6>[ 0.101682] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10357 11:04:22.605028 <6>[ 0.101947] Detected VIPT I-cache on CPU3
10358 11:04:22.611471 <6>[ 0.101995] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10359 11:04:22.618019 <6>[ 0.102011] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10360 11:04:22.624779 <6>[ 0.102318] CPU features: detected: Spectre-v4
10361 11:04:22.627937 <6>[ 0.102324] CPU features: detected: Spectre-BHB
10362 11:04:22.631110 <6>[ 0.102330] Detected PIPT I-cache on CPU4
10363 11:04:22.638229 <6>[ 0.102391] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10364 11:04:22.647258 <6>[ 0.102409] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10365 11:04:22.650794 <6>[ 0.102703] Detected PIPT I-cache on CPU5
10366 11:04:22.657230 <6>[ 0.102766] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10367 11:04:22.663955 <6>[ 0.102782] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10368 11:04:22.667583 <6>[ 0.103068] Detected PIPT I-cache on CPU6
10369 11:04:22.677314 <6>[ 0.103136] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10370 11:04:22.683671 <6>[ 0.103151] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10371 11:04:22.687207 <6>[ 0.103451] Detected PIPT I-cache on CPU7
10372 11:04:22.693524 <6>[ 0.103517] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10373 11:04:22.699896 <6>[ 0.103533] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10374 11:04:22.703362 <6>[ 0.103581] smp: Brought up 1 node, 8 CPUs
10375 11:04:22.710092 <6>[ 0.244892] SMP: Total of 8 processors activated.
10376 11:04:22.716936 <6>[ 0.249844] CPU features: detected: 32-bit EL0 Support
10377 11:04:22.723307 <6>[ 0.255207] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10378 11:04:22.730270 <6>[ 0.264062] CPU features: detected: Common not Private translations
10379 11:04:22.736412 <6>[ 0.270538] CPU features: detected: CRC32 instructions
10380 11:04:22.743168 <6>[ 0.275890] CPU features: detected: RCpc load-acquire (LDAPR)
10381 11:04:22.746582 <6>[ 0.281887] CPU features: detected: LSE atomic instructions
10382 11:04:22.753007 <6>[ 0.287696] CPU features: detected: Privileged Access Never
10383 11:04:22.759355 <6>[ 0.293475] CPU features: detected: RAS Extension Support
10384 11:04:22.766101 <6>[ 0.299083] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10385 11:04:22.769464 <6>[ 0.306350] CPU: All CPU(s) started at EL2
10386 11:04:22.776465 <6>[ 0.310667] alternatives: applying system-wide alternatives
10387 11:04:22.786667 <6>[ 0.321552] devtmpfs: initialized
10388 11:04:22.801519 <6>[ 0.330346] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10389 11:04:22.808367 <6>[ 0.340307] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10390 11:04:22.815493 <6>[ 0.348545] pinctrl core: initialized pinctrl subsystem
10391 11:04:22.818634 <6>[ 0.355208] DMI not present or invalid.
10392 11:04:22.824829 <6>[ 0.359623] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10393 11:04:22.834842 <6>[ 0.366389] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10394 11:04:22.841210 <6>[ 0.373972] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10395 11:04:22.851460 <6>[ 0.382203] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10396 11:04:22.854820 <6>[ 0.390445] audit: initializing netlink subsys (disabled)
10397 11:04:22.864449 <5>[ 0.396134] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10398 11:04:22.870938 <6>[ 0.396840] thermal_sys: Registered thermal governor 'step_wise'
10399 11:04:22.877436 <6>[ 0.404099] thermal_sys: Registered thermal governor 'power_allocator'
10400 11:04:22.880856 <6>[ 0.410353] cpuidle: using governor menu
10401 11:04:22.887259 <6>[ 0.421313] NET: Registered PF_QIPCRTR protocol family
10402 11:04:22.893751 <6>[ 0.426805] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10403 11:04:22.900555 <6>[ 0.433909] ASID allocator initialised with 32768 entries
10404 11:04:22.903504 <6>[ 0.440483] Serial: AMBA PL011 UART driver
10405 11:04:22.914686 <4>[ 0.449812] Trying to register duplicate clock ID: 134
10406 11:04:22.972843 <6>[ 0.511021] KASLR enabled
10407 11:04:22.986853 <6>[ 0.518655] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10408 11:04:22.993320 <6>[ 0.525668] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10409 11:04:23.000068 <6>[ 0.532156] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10410 11:04:23.006245 <6>[ 0.539163] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10411 11:04:23.013421 <6>[ 0.545649] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10412 11:04:23.019984 <6>[ 0.552653] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10413 11:04:23.026016 <6>[ 0.559140] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10414 11:04:23.033043 <6>[ 0.566143] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10415 11:04:23.036401 <6>[ 0.573665] ACPI: Interpreter disabled.
10416 11:04:23.044580 <6>[ 0.580095] iommu: Default domain type: Translated
10417 11:04:23.051430 <6>[ 0.585207] iommu: DMA domain TLB invalidation policy: strict mode
10418 11:04:23.054713 <5>[ 0.591854] SCSI subsystem initialized
10419 11:04:23.061269 <6>[ 0.596015] usbcore: registered new interface driver usbfs
10420 11:04:23.067666 <6>[ 0.601747] usbcore: registered new interface driver hub
10421 11:04:23.071401 <6>[ 0.607298] usbcore: registered new device driver usb
10422 11:04:23.077942 <6>[ 0.613405] pps_core: LinuxPPS API ver. 1 registered
10423 11:04:23.087997 <6>[ 0.618599] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10424 11:04:23.091077 <6>[ 0.627942] PTP clock support registered
10425 11:04:23.094664 <6>[ 0.632186] EDAC MC: Ver: 3.0.0
10426 11:04:23.101802 <6>[ 0.637345] FPGA manager framework
10427 11:04:23.108520 <6>[ 0.641031] Advanced Linux Sound Architecture Driver Initialized.
10428 11:04:23.111771 <6>[ 0.647822] vgaarb: loaded
10429 11:04:23.118558 <6>[ 0.650916] clocksource: Switched to clocksource arch_sys_counter
10430 11:04:23.121557 <5>[ 0.657352] VFS: Disk quotas dquot_6.6.0
10431 11:04:23.128218 <6>[ 0.661535] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10432 11:04:23.131614 <6>[ 0.668725] pnp: PnP ACPI: disabled
10433 11:04:23.139977 <6>[ 0.675412] NET: Registered PF_INET protocol family
10434 11:04:23.150006 <6>[ 0.681006] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10435 11:04:23.161082 <6>[ 0.693352] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10436 11:04:23.170802 <6>[ 0.702161] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10437 11:04:23.177543 <6>[ 0.710133] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10438 11:04:23.187177 <6>[ 0.718836] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10439 11:04:23.193917 <6>[ 0.728595] TCP: Hash tables configured (established 65536 bind 65536)
10440 11:04:23.200494 <6>[ 0.735457] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10441 11:04:23.210425 <6>[ 0.742652] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10442 11:04:23.217309 <6>[ 0.750353] NET: Registered PF_UNIX/PF_LOCAL protocol family
10443 11:04:23.223927 <6>[ 0.756512] RPC: Registered named UNIX socket transport module.
10444 11:04:23.227082 <6>[ 0.762665] RPC: Registered udp transport module.
10445 11:04:23.233587 <6>[ 0.767600] RPC: Registered tcp transport module.
10446 11:04:23.240202 <6>[ 0.772529] RPC: Registered tcp NFSv4.1 backchannel transport module.
10447 11:04:23.243514 <6>[ 0.779192] PCI: CLS 0 bytes, default 64
10448 11:04:23.246679 <6>[ 0.783515] Unpacking initramfs...
10449 11:04:23.263315 <6>[ 0.795449] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10450 11:04:23.272933 <6>[ 0.804091] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10451 11:04:23.276211 <6>[ 0.812928] kvm [1]: IPA Size Limit: 40 bits
10452 11:04:23.282912 <6>[ 0.817460] kvm [1]: GICv3: no GICV resource entry
10453 11:04:23.286114 <6>[ 0.822480] kvm [1]: disabling GICv2 emulation
10454 11:04:23.292716 <6>[ 0.827167] kvm [1]: GIC system register CPU interface enabled
10455 11:04:23.296418 <6>[ 0.833335] kvm [1]: vgic interrupt IRQ18
10456 11:04:23.303347 <6>[ 0.837704] kvm [1]: VHE mode initialized successfully
10457 11:04:23.309255 <5>[ 0.844192] Initialise system trusted keyrings
10458 11:04:23.315918 <6>[ 0.848999] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10459 11:04:23.323691 <6>[ 0.858978] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10460 11:04:23.330406 <5>[ 0.865372] NFS: Registering the id_resolver key type
10461 11:04:23.333142 <5>[ 0.870673] Key type id_resolver registered
10462 11:04:23.339696 <5>[ 0.875087] Key type id_legacy registered
10463 11:04:23.346898 <6>[ 0.879367] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10464 11:04:23.353106 <6>[ 0.886286] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10465 11:04:23.359476 <6>[ 0.893994] 9p: Installing v9fs 9p2000 file system support
10466 11:04:23.396937 <5>[ 0.932468] Key type asymmetric registered
10467 11:04:23.400570 <5>[ 0.936805] Asymmetric key parser 'x509' registered
10468 11:04:23.410014 <6>[ 0.941952] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10469 11:04:23.413228 <6>[ 0.949565] io scheduler mq-deadline registered
10470 11:04:23.416714 <6>[ 0.954341] io scheduler kyber registered
10471 11:04:23.435722 <6>[ 0.971467] EINJ: ACPI disabled.
10472 11:04:23.468574 <4>[ 0.997655] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10473 11:04:23.478241 <4>[ 1.008281] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10474 11:04:23.493703 <6>[ 1.029090] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10475 11:04:23.501480 <6>[ 1.037051] printk: console [ttyS0] disabled
10476 11:04:23.529443 <6>[ 1.061690] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10477 11:04:23.536427 <6>[ 1.071167] printk: console [ttyS0] enabled
10478 11:04:23.539167 <6>[ 1.071167] printk: console [ttyS0] enabled
10479 11:04:23.545952 <6>[ 1.080063] printk: bootconsole [mtk8250] disabled
10480 11:04:23.549515 <6>[ 1.080063] printk: bootconsole [mtk8250] disabled
10481 11:04:23.556111 <6>[ 1.091252] SuperH (H)SCI(F) driver initialized
10482 11:04:23.559207 <6>[ 1.096557] msm_serial: driver initialized
10483 11:04:23.573583 <6>[ 1.105566] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10484 11:04:23.583549 <6>[ 1.114116] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10485 11:04:23.590307 <6>[ 1.122661] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10486 11:04:23.600372 <6>[ 1.131289] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10487 11:04:23.606543 <6>[ 1.139995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10488 11:04:23.616319 <6>[ 1.148710] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10489 11:04:23.626343 <6>[ 1.157249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10490 11:04:23.632827 <6>[ 1.166079] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10491 11:04:23.642935 <6>[ 1.174622] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10492 11:04:23.654436 <6>[ 1.190208] loop: module loaded
10493 11:04:23.661416 <6>[ 1.196321] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10494 11:04:23.684034 <4>[ 1.219518] mtk-pmic-keys: Failed to locate of_node [id: -1]
10495 11:04:23.690709 <6>[ 1.226397] megasas: 07.719.03.00-rc1
10496 11:04:23.700879 <6>[ 1.236086] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10497 11:04:23.711122 <6>[ 1.246312] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10498 11:04:23.727887 <6>[ 1.262973] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10499 11:04:23.784324 <6>[ 1.313261] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10500 11:04:24.160471 <6>[ 1.696128] Freeing initrd memory: 20840K
10501 11:04:24.176593 <6>[ 1.712141] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10502 11:04:24.187950 <6>[ 1.723050] tun: Universal TUN/TAP device driver, 1.6
10503 11:04:24.190969 <6>[ 1.729119] thunder_xcv, ver 1.0
10504 11:04:24.194317 <6>[ 1.732625] thunder_bgx, ver 1.0
10505 11:04:24.197310 <6>[ 1.736118] nicpf, ver 1.0
10506 11:04:24.207998 <6>[ 1.740142] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10507 11:04:24.210979 <6>[ 1.747618] hns3: Copyright (c) 2017 Huawei Corporation.
10508 11:04:24.217967 <6>[ 1.753223] hclge is initializing
10509 11:04:24.221112 <6>[ 1.756798] e1000: Intel(R) PRO/1000 Network Driver
10510 11:04:24.228107 <6>[ 1.761927] e1000: Copyright (c) 1999-2006 Intel Corporation.
10511 11:04:24.230941 <6>[ 1.767940] e1000e: Intel(R) PRO/1000 Network Driver
10512 11:04:24.237556 <6>[ 1.773156] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10513 11:04:24.244591 <6>[ 1.779343] igb: Intel(R) Gigabit Ethernet Network Driver
10514 11:04:24.250710 <6>[ 1.784993] igb: Copyright (c) 2007-2014 Intel Corporation.
10515 11:04:24.257356 <6>[ 1.790828] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10516 11:04:24.264211 <6>[ 1.797346] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10517 11:04:24.267651 <6>[ 1.803807] sky2: driver version 1.30
10518 11:04:24.273792 <6>[ 1.808750] usbcore: registered new device driver r8152-cfgselector
10519 11:04:24.280920 <6>[ 1.815285] usbcore: registered new interface driver r8152
10520 11:04:24.287190 <6>[ 1.821115] VFIO - User Level meta-driver version: 0.3
10521 11:04:24.293606 <6>[ 1.829359] usbcore: registered new interface driver usb-storage
10522 11:04:24.300608 <6>[ 1.835806] usbcore: registered new device driver onboard-usb-hub
10523 11:04:24.309584 <6>[ 1.845021] mt6397-rtc mt6359-rtc: registered as rtc0
10524 11:04:24.319446 <6>[ 1.850489] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:04:24 UTC (1720609464)
10525 11:04:24.322591 <6>[ 1.860063] i2c_dev: i2c /dev entries driver
10526 11:04:24.336474 <4>[ 1.872230] cpu cpu0: supply cpu not found, using dummy regulator
10527 11:04:24.343325 <4>[ 1.878651] cpu cpu1: supply cpu not found, using dummy regulator
10528 11:04:24.350124 <4>[ 1.885055] cpu cpu2: supply cpu not found, using dummy regulator
10529 11:04:24.356930 <4>[ 1.891456] cpu cpu3: supply cpu not found, using dummy regulator
10530 11:04:24.363412 <4>[ 1.897851] cpu cpu4: supply cpu not found, using dummy regulator
10531 11:04:24.369842 <4>[ 1.904264] cpu cpu5: supply cpu not found, using dummy regulator
10532 11:04:24.376278 <4>[ 1.910657] cpu cpu6: supply cpu not found, using dummy regulator
10533 11:04:24.382859 <4>[ 1.917049] cpu cpu7: supply cpu not found, using dummy regulator
10534 11:04:24.403505 <6>[ 1.938692] cpu cpu0: EM: created perf domain
10535 11:04:24.406578 <6>[ 1.943638] cpu cpu4: EM: created perf domain
10536 11:04:24.413828 <6>[ 1.949267] sdhci: Secure Digital Host Controller Interface driver
10537 11:04:24.420172 <6>[ 1.955699] sdhci: Copyright(c) Pierre Ossman
10538 11:04:24.426912 <6>[ 1.960657] Synopsys Designware Multimedia Card Interface Driver
10539 11:04:24.433445 <6>[ 1.967312] sdhci-pltfm: SDHCI platform and OF driver helper
10540 11:04:24.436679 <6>[ 1.967350] mmc0: CQHCI version 5.10
10541 11:04:24.443289 <6>[ 1.977342] ledtrig-cpu: registered to indicate activity on CPUs
10542 11:04:24.450077 <6>[ 1.984415] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10543 11:04:24.456819 <6>[ 1.991451] usbcore: registered new interface driver usbhid
10544 11:04:24.460073 <6>[ 1.997273] usbhid: USB HID core driver
10545 11:04:24.466280 <6>[ 2.001472] spi_master spi0: will run message pump with realtime priority
10546 11:04:24.515423 <6>[ 2.044138] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10547 11:04:24.534271 <6>[ 2.059685] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10548 11:04:24.537605 <6>[ 2.071294] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10549 11:04:24.544257 <6>[ 2.074527] cros-ec-spi spi0.0: Chrome EC device registered
10550 11:04:24.547581 <6>[ 2.085158] mmc0: Command Queue Engine enabled
10551 11:04:24.554567 <6>[ 2.089885] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10552 11:04:24.561523 <6>[ 2.097280] mmcblk0: mmc0:0001 DA4128 116 GiB
10553 11:04:24.572082 <6>[ 2.099113] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10554 11:04:24.575135 <6>[ 2.106241] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10555 11:04:24.581627 <6>[ 2.112465] NET: Registered PF_PACKET protocol family
10556 11:04:24.588186 <6>[ 2.118672] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10557 11:04:24.591594 <6>[ 2.122575] 9pnet: Installing 9P2000 support
10558 11:04:24.598345 <6>[ 2.128397] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10559 11:04:24.601345 <5>[ 2.132284] Key type dns_resolver registered
10560 11:04:24.608136 <6>[ 2.138079] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10561 11:04:24.611417 <6>[ 2.142377] registered taskstats version 1
10562 11:04:24.617755 <5>[ 2.152895] Loading compiled-in X.509 certificates
10563 11:04:24.652792 <4>[ 2.181915] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 11:04:24.662901 <4>[ 2.192649] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 11:04:24.679110 <6>[ 2.214328] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10566 11:04:24.685778 <6>[ 2.221487] xhci-mtk 11200000.usb: xHCI Host Controller
10567 11:04:24.692566 <6>[ 2.227005] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10568 11:04:24.702386 <6>[ 2.234847] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10569 11:04:24.708873 <6>[ 2.244270] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10570 11:04:24.716192 <6>[ 2.250339] xhci-mtk 11200000.usb: xHCI Host Controller
10571 11:04:24.722388 <6>[ 2.255816] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10572 11:04:24.728912 <6>[ 2.263466] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10573 11:04:24.735334 <6>[ 2.271149] hub 1-0:1.0: USB hub found
10574 11:04:24.739145 <6>[ 2.275164] hub 1-0:1.0: 1 port detected
10575 11:04:24.749015 <6>[ 2.279445] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10576 11:04:24.752039 <6>[ 2.288137] hub 2-0:1.0: USB hub found
10577 11:04:24.755298 <6>[ 2.292162] hub 2-0:1.0: 1 port detected
10578 11:04:24.763929 <6>[ 2.299373] mtk-msdc 11f70000.mmc: Got CD GPIO
10579 11:04:24.777596 <6>[ 2.310051] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10580 11:04:24.787561 <6>[ 2.318413] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10581 11:04:24.794592 <6>[ 2.326754] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10582 11:04:24.803977 <6>[ 2.335092] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10583 11:04:24.810855 <6>[ 2.343435] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10584 11:04:24.820507 <6>[ 2.351774] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10585 11:04:24.827233 <6>[ 2.360113] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10586 11:04:24.836893 <6>[ 2.368451] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10587 11:04:24.843854 <6>[ 2.376792] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10588 11:04:24.853901 <6>[ 2.385131] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10589 11:04:24.860638 <6>[ 2.393469] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10590 11:04:24.870735 <6>[ 2.401817] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10591 11:04:24.876878 <6>[ 2.410156] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10592 11:04:24.886691 <6>[ 2.418495] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10593 11:04:24.893169 <6>[ 2.426834] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10594 11:04:24.900206 <6>[ 2.435547] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10595 11:04:24.906781 <6>[ 2.442695] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10596 11:04:24.913752 <6>[ 2.449498] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10597 11:04:24.924691 <6>[ 2.456259] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10598 11:04:24.930300 <6>[ 2.463209] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10599 11:04:24.937382 <6>[ 2.470088] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10600 11:04:24.947202 <6>[ 2.479222] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10601 11:04:24.957362 <6>[ 2.488345] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10602 11:04:24.966910 <6>[ 2.497639] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10603 11:04:24.976879 <6>[ 2.507112] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10604 11:04:24.983345 <6>[ 2.516580] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10605 11:04:24.993482 <6>[ 2.525701] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10606 11:04:25.003051 <6>[ 2.535170] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10607 11:04:25.013354 <6>[ 2.544290] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10608 11:04:25.023383 <6>[ 2.553588] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10609 11:04:25.033081 <6>[ 2.563749] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10610 11:04:25.042515 <6>[ 2.575242] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10611 11:04:25.167096 <6>[ 2.699206] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10612 11:04:25.321544 <6>[ 2.857094] hub 1-1:1.0: USB hub found
10613 11:04:25.324649 <6>[ 2.861627] hub 1-1:1.0: 4 ports detected
10614 11:04:25.336627 <6>[ 2.871976] hub 1-1:1.0: USB hub found
10615 11:04:25.339540 <6>[ 2.876501] hub 1-1:1.0: 4 ports detected
10616 11:04:25.446868 <6>[ 2.979571] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10617 11:04:25.473358 <6>[ 3.009033] hub 2-1:1.0: USB hub found
10618 11:04:25.476655 <6>[ 3.013540] hub 2-1:1.0: 3 ports detected
10619 11:04:25.488574 <6>[ 3.023926] hub 2-1:1.0: USB hub found
10620 11:04:25.491627 <6>[ 3.028327] hub 2-1:1.0: 3 ports detected
10621 11:04:25.659082 <6>[ 3.191235] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10622 11:04:25.790710 <6>[ 3.326138] hub 1-1.4:1.0: USB hub found
10623 11:04:25.794062 <6>[ 3.330711] hub 1-1.4:1.0: 2 ports detected
10624 11:04:25.805532 <6>[ 3.341286] hub 1-1.4:1.0: USB hub found
10625 11:04:25.808601 <6>[ 3.345906] hub 1-1.4:1.0: 2 ports detected
10626 11:04:25.870875 <6>[ 3.403303] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10627 11:04:25.979354 <6>[ 3.511609] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10628 11:04:26.011344 <4>[ 3.543736] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10629 11:04:26.021408 <4>[ 3.552834] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10630 11:04:26.056380 <6>[ 3.592349] r8152 2-1.3:1.0 eth0: v1.12.13
10631 11:04:26.106422 <6>[ 3.639237] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10632 11:04:26.302776 <6>[ 3.835072] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10633 11:04:27.793744 <6>[ 5.329551] r8152 2-1.3:1.0 eth0: carrier on
10634 11:04:30.662581 <5>[ 5.351042] Sending DHCP requests .., OK
10635 11:04:30.669265 <6>[ 8.203471] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10636 11:04:30.672758 <6>[ 8.211813] IP-Config: Complete:
10637 11:04:30.686137 <6>[ 8.215320] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10638 11:04:30.692395 <6>[ 8.226028] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10639 11:04:30.702187 <6>[ 8.234650] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10640 11:04:30.705999 <6>[ 8.234659] nameserver0=192.168.201.1
10641 11:04:30.709256 <6>[ 8.246808] clk: Disabling unused clocks
10642 11:04:30.712966 <6>[ 8.252423] ALSA device list:
10643 11:04:30.719323 <6>[ 8.255784] No soundcards found.
10644 11:04:30.727160 <6>[ 8.263431] Freeing unused kernel memory: 8512K
10645 11:04:30.730384 <6>[ 8.268356] Run /init as init process
10646 11:04:30.758449 Starting syslogd: OK
10647 11:04:30.767221 Starting klogd: OK
10648 11:04:30.775107 Running sysctl: OK
10649 11:04:30.784663 Populating /dev using udev: <30>[ 8.320145] udevd[198]: starting version 3.2.9
10650 11:04:30.791686 <27>[ 8.327954] udevd[198]: specified user 'tss' unknown
10651 11:04:30.798506 <27>[ 8.333340] udevd[198]: specified group 'tss' unknown
10652 11:04:30.801431 <30>[ 8.339844] udevd[199]: starting eudev-3.2.9
10653 11:04:30.823657 <27>[ 8.360042] udevd[199]: specified user 'tss' unknown
10654 11:04:30.830147 <27>[ 8.365494] udevd[199]: specified group 'tss' unknown
10655 11:04:30.910942 <6>[ 8.443684] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10656 11:04:30.920520 <6>[ 8.453396] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10657 11:04:30.931573 <6>[ 8.467907] remoteproc remoteproc0: scp is available
10658 11:04:30.938057 <6>[ 8.472291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10659 11:04:30.944813 <6>[ 8.473480] remoteproc remoteproc0: powering up scp
10660 11:04:30.951475 <6>[ 8.481379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10661 11:04:30.961838 <6>[ 8.482396] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10662 11:04:30.968188 <6>[ 8.482578] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10663 11:04:30.978552 <6>[ 8.482610] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10664 11:04:30.985309 <6>[ 8.486404] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10665 11:04:30.992027 <6>[ 8.486435] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10666 11:04:31.001263 <4>[ 8.494477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10667 11:04:31.011143 <6>[ 8.542934] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10668 11:04:31.017865 <6>[ 8.551097] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10669 11:04:31.024158 <6>[ 8.559208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10670 11:04:31.033879 <6>[ 8.567147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10671 11:04:31.040672 <6>[ 8.574968] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10672 11:04:31.050950 <6>[ 8.582786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10673 11:04:31.072200 <6>[ 8.608187] mc: Linux media interface: v0.10
10674 11:04:31.078408 <3>[ 8.609908] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 11:04:31.085405 <6>[ 8.620922] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10676 11:04:31.094889 <6>[ 8.627030] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10677 11:04:31.102076 <6>[ 8.627147] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10678 11:04:31.108591 <6>[ 8.627157] remoteproc remoteproc0: remote processor scp is now up
10679 11:04:31.114855 <6>[ 8.627816] pci_bus 0000:00: root bus resource [bus 00-ff]
10680 11:04:31.121521 <3>[ 8.649972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 11:04:31.128260 <6>[ 8.655574] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10682 11:04:31.138010 <3>[ 8.663739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 11:04:31.148188 <6>[ 8.670774] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10684 11:04:31.154846 <6>[ 8.670830] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10685 11:04:31.161496 <3>[ 8.682446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 11:04:31.171170 <6>[ 8.684882] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10687 11:04:31.174380 <6>[ 8.689558] videodev: Linux video capture interface: v2.00
10688 11:04:31.183890 <3>[ 8.695067] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 11:04:31.190918 <3>[ 8.695075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 11:04:31.201103 <3>[ 8.695086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 11:04:31.207455 <3>[ 8.695092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 11:04:31.217514 <3>[ 8.695169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 11:04:31.223649 <6>[ 8.695299] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10694 11:04:31.227175 <6>[ 8.695387] pci 0000:00:00.0: supports D1 D2
10695 11:04:31.234148 <6>[ 8.695390] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10696 11:04:31.243762 <6>[ 8.697336] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10697 11:04:31.250044 <6>[ 8.697724] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10698 11:04:31.256808 <6>[ 8.697757] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10699 11:04:31.263424 <6>[ 8.697783] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10700 11:04:31.269898 <6>[ 8.697800] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10701 11:04:31.276722 <6>[ 8.697938] pci 0000:01:00.0: supports D1 D2
10702 11:04:31.283277 <6>[ 8.697944] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10703 11:04:31.289923 <6>[ 8.707328] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10704 11:04:31.296716 <3>[ 8.710901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 11:04:31.306622 <4>[ 8.711317] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10706 11:04:31.313320 <4>[ 8.711439] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10707 11:04:31.316611 <6>[ 8.712346] Bluetooth: Core ver 2.22
10708 11:04:31.322771 <6>[ 8.712414] NET: Registered PF_BLUETOOTH protocol family
10709 11:04:31.329559 <6>[ 8.712417] Bluetooth: HCI device and connection manager initialized
10710 11:04:31.333079 <6>[ 8.712442] Bluetooth: HCI socket layer initialized
10711 11:04:31.340042 <6>[ 8.712453] Bluetooth: L2CAP socket layer initialized
10712 11:04:31.342813 <6>[ 8.712471] Bluetooth: SCO socket layer initialized
10713 11:04:31.352960 <6>[ 8.716605] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10714 11:04:31.359399 <3>[ 8.724784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 11:04:31.370430 <6>[ 8.734996] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10716 11:04:31.376631 <3>[ 8.741050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 11:04:31.383622 <6>[ 8.749159] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10718 11:04:31.393485 <3>[ 8.757598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 11:04:31.400124 <6>[ 8.764755] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10720 11:04:31.409541 <3>[ 8.769290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 11:04:31.416175 <6>[ 8.776220] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10722 11:04:31.426219 <3>[ 8.784372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 11:04:31.429468 <6>[ 8.790625] pci 0000:00:00.0: PCI bridge to [bus 01]
10724 11:04:31.439600 <6>[ 8.791711] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10725 11:04:31.446169 <6>[ 8.793492] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10726 11:04:31.455858 <3>[ 8.798101] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 11:04:31.462416 <6>[ 8.805566] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10728 11:04:31.469053 <6>[ 8.805741] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10729 11:04:31.476236 <3>[ 8.813075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 11:04:31.485947 <6>[ 8.816143] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10731 11:04:31.496105 <6>[ 8.816423] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10732 11:04:31.502736 <6>[ 8.818027] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10733 11:04:31.513010 <6>[ 8.819144] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10734 11:04:31.519040 <3>[ 8.824521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 11:04:31.526085 <6>[ 8.831871] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10736 11:04:31.535549 <4>[ 8.863402] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10737 11:04:31.539098 <4>[ 8.863402] Fallback method does not support PEC.
10738 11:04:31.545616 <6>[ 8.865050] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10739 11:04:31.558729 <6>[ 8.866122] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10740 11:04:31.565416 <6>[ 8.866220] usbcore: registered new interface driver uvcvideo
10741 11:04:31.571925 <6>[ 8.872153] usbcore: registered new interface driver btusb
10742 11:04:31.581872 <4>[ 8.873262] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10743 11:04:31.588479 <3>[ 8.873277] Bluetooth: hci0: Failed to load firmware file (-2)
10744 11:04:31.592042 <3>[ 8.873281] Bluetooth: hci0: Failed to set up firmware (-2)
10745 11:04:31.601861 <4>[ 8.873285] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10746 11:04:31.608452 <6>[ 8.887421] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10747 11:04:31.618575 <5>[ 8.887660] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10748 11:04:31.624650 <3>[ 8.910216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10749 11:04:31.634623 <5>[ 8.910480] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10750 11:04:31.641198 <5>[ 8.910712] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10751 11:04:31.651057 <4>[ 8.910769] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10752 11:04:31.655395 <6>[ 8.910774] cfg80211: failed to load regulatory.db
10753 11:04:31.664512 <6>[ 9.006486] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10754 11:04:31.670807 <3>[ 9.034106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10755 11:04:31.677586 <6>[ 9.037721] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10756 11:04:31.702892 <6>[ 9.239243] mt7921e 0000:01:00.0: ASIC revision: 79610010
10757 11:04:31.806201 <6>[ 9.339339] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10758 11:04:31.809116 <6>[ 9.339339]
10759 11:04:31.819986 done
10760 11:04:31.832772 Saving random seed: OK
10761 11:04:31.844813 Starting network: ip: RTNETLINK answers: File exists
10762 11:04:31.848062 FAIL
10763 11:04:31.886728 Starting dropbear sshd: <6>[ 9.423075] NET: Registered PF_INET6 protocol family
10764 11:04:31.893545 <6>[ 9.430115] Segment Routing with IPv6
10765 11:04:31.896906 <6>[ 9.434119] In-situ OAM (IOAM) with IPv6
10766 11:04:31.900538 OK
10767 11:04:31.909642 /bin/sh: can't access tty; job control turned off
10768 11:04:31.909981 Matched prompt #10: / #
10770 11:04:31.910167 Setting prompt string to ['/ #']
10771 11:04:31.910252 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10773 11:04:31.910433 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10774 11:04:31.910516 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10775 11:04:31.910581 Setting prompt string to ['/ #']
10776 11:04:31.910635 Forcing a shell prompt, looking for ['/ #']
10777 11:04:31.910690 Sending line: ''
10779 11:04:31.961043 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10780 11:04:31.961166 Waiting using forced prompt support (timeout 00:02:30)
10781 11:04:31.965976 / #
10782 11:04:31.966265 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10783 11:04:31.966380 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10784 11:04:31.966489 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10785 11:04:31.966605 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10786 11:04:31.966711 end: 2 depthcharge-action (duration 00:01:35) [common]
10787 11:04:31.966819 start: 3 lava-test-retry (timeout 00:01:00) [common]
10788 11:04:31.966972 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10789 11:04:31.967067 Using namespace: common
10790 11:04:31.967163 Sending line: '#'
10792 11:04:32.067644 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10793 11:04:32.078495 / # #<6>[ 9.611572] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10794 11:04:32.078615
10795 11:04:32.078860 Using /lava-14786858
10796 11:04:32.078922 Sending line: 'export SHELL=/bin/sh'
10798 11:04:32.185060 / # export SHELL=/bin/sh
10799 11:04:32.185335 Sending line: '. /lava-14786858/environment'
10801 11:04:32.291471 / # . /lava-14786858/environment
10802 11:04:32.291730 Sending line: '/lava-14786858/bin/lava-test-runner /lava-14786858/0'
10804 11:04:32.392425 Test shell timeout: 10s (minimum of the action and connection timeout)
10805 11:04:32.398027 / # /lava-14786858/bin/lava-test-runner /lava-14786858/0
10806 11:04:32.417207 + export 'TESTRUN_ID=0_dmesg'
10807 11:04:32.423587 +<8>[ 9.958698] <LAVA_SIGNAL_STARTRUN 0_dmesg 14786858_1.5.2.3.1>
10808 11:04:32.424193 Received signal: <STARTRUN> 0_dmesg 14786858_1.5.2.3.1
10809 11:04:32.424303 Starting test lava.0_dmesg (14786858_1.5.2.3.1)
10810 11:04:32.424406 Skipping test definition patterns.
10811 11:04:32.427442 cd /lava-14786858/0/tests/0_dmesg
10812 11:04:32.427531 + cat uuid
10813 11:04:32.430115 + UUID=14786858_1.5.2.3.1
10814 11:04:32.430224 + set +x
10815 11:04:32.437149 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10816 11:04:32.446996 <8>[ 9.978682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10817 11:04:32.447635 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10819 11:04:32.465790 <8>[ 9.998096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10820 11:04:32.466485 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10822 11:04:32.486028 <8>[ 10.018659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10823 11:04:32.486706 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10825 11:04:32.489227 + set +x
10826 11:04:32.492277 <8>[ 10.028237] <LAVA_SIGNAL_ENDRUN 0_dmesg 14786858_1.5.2.3.1>
10827 11:04:32.492869 Received signal: <ENDRUN> 0_dmesg 14786858_1.5.2.3.1
10828 11:04:32.493243 Ending use of test pattern.
10829 11:04:32.493524 Ending test lava.0_dmesg (14786858_1.5.2.3.1), duration 0.07
10831 11:04:32.496477 <LAVA_TEST_RUNNER EXIT>
10832 11:04:32.497214 ok: lava_test_shell seems to have completed
10833 11:04:32.497689 crit: pass
alert: pass
emerg: pass
10834 11:04:32.498064 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10835 11:04:32.498427 end: 3 lava-test-retry (duration 00:00:01) [common]
10836 11:04:32.498799 start: 4 finalize (timeout 00:08:05) [common]
10837 11:04:32.499174 start: 4.1 power-off (timeout 00:00:30) [common]
10838 11:04:32.499740 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
10839 11:04:34.595249 >> Command sent successfully.
10840 11:04:34.600363 Returned 0 in 2 seconds
10841 11:04:34.600497 end: 4.1 power-off (duration 00:00:02) [common]
10843 11:04:34.600687 start: 4.2 read-feedback (timeout 00:08:03) [common]
10844 11:04:34.600818 Listened to connection for namespace 'common' for up to 1s
10845 11:04:35.601247 Finalising connection for namespace 'common'
10846 11:04:35.601444 Disconnecting from shell: Finalise
10847 11:04:35.601560 / #
10848 11:04:35.701843 end: 4.2 read-feedback (duration 00:00:01) [common]
10849 11:04:35.702035 end: 4 finalize (duration 00:00:03) [common]
10850 11:04:35.702174 Cleaning after the job
10851 11:04:35.702296 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/ramdisk
10852 11:04:35.705654 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/kernel
10853 11:04:35.716011 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/dtb
10854 11:04:35.716287 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786858/tftp-deploy-wtiz35rr/modules
10855 11:04:35.723828 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786858
10856 11:04:35.774157 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786858
10857 11:04:35.774322 Job finished correctly