Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:06:40.141384 lava-dispatcher, installed at version: 2024.05
2 11:06:40.141581 start: 0 validate
3 11:06:40.141700 Start time: 2024-07-10 11:06:40.141694+00:00 (UTC)
4 11:06:40.141827 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:06:40.141970 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:06:40.415029 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:06:40.415745 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:06:55.325626 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:06:55.326355 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:06:55.599898 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:06:55.600505 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:06:55.875138 validate duration: 15.73
14 11:06:55.876330 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:06:55.876824 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:06:55.877397 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:06:55.878184 Not decompressing ramdisk as can be used compressed.
18 11:06:55.878621 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 11:06:55.878926 saving as /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/ramdisk/rootfs.cpio.gz
20 11:06:55.879239 total size: 39026414 (37 MB)
21 11:06:56.150338 progress 0 % (0 MB)
22 11:06:56.190145 progress 5 % (1 MB)
23 11:06:56.205782 progress 10 % (3 MB)
24 11:06:56.217027 progress 15 % (5 MB)
25 11:06:56.226658 progress 20 % (7 MB)
26 11:06:56.236241 progress 25 % (9 MB)
27 11:06:56.245850 progress 30 % (11 MB)
28 11:06:56.255183 progress 35 % (13 MB)
29 11:06:56.264686 progress 40 % (14 MB)
30 11:06:56.274174 progress 45 % (16 MB)
31 11:06:56.283677 progress 50 % (18 MB)
32 11:06:56.293043 progress 55 % (20 MB)
33 11:06:56.302390 progress 60 % (22 MB)
34 11:06:56.311939 progress 65 % (24 MB)
35 11:06:56.321396 progress 70 % (26 MB)
36 11:06:56.331065 progress 75 % (27 MB)
37 11:06:56.340452 progress 80 % (29 MB)
38 11:06:56.350157 progress 85 % (31 MB)
39 11:06:56.359443 progress 90 % (33 MB)
40 11:06:56.368853 progress 95 % (35 MB)
41 11:06:56.378196 progress 100 % (37 MB)
42 11:06:56.378441 37 MB downloaded in 0.50 s (74.55 MB/s)
43 11:06:56.378595 end: 1.1.1 http-download (duration 00:00:01) [common]
45 11:06:56.378814 end: 1.1 download-retry (duration 00:00:01) [common]
46 11:06:56.378893 start: 1.2 download-retry (timeout 00:09:59) [common]
47 11:06:56.378968 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 11:06:56.379097 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:06:56.379158 saving as /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/kernel/Image
50 11:06:56.379214 total size: 54813184 (52 MB)
51 11:06:56.379268 No compression specified
52 11:06:56.380273 progress 0 % (0 MB)
53 11:06:56.393405 progress 5 % (2 MB)
54 11:06:56.406463 progress 10 % (5 MB)
55 11:06:56.419434 progress 15 % (7 MB)
56 11:06:56.432822 progress 20 % (10 MB)
57 11:06:56.446100 progress 25 % (13 MB)
58 11:06:56.459128 progress 30 % (15 MB)
59 11:06:56.472550 progress 35 % (18 MB)
60 11:06:56.485827 progress 40 % (20 MB)
61 11:06:56.498845 progress 45 % (23 MB)
62 11:06:56.512161 progress 50 % (26 MB)
63 11:06:56.525347 progress 55 % (28 MB)
64 11:06:56.538459 progress 60 % (31 MB)
65 11:06:56.551816 progress 65 % (34 MB)
66 11:06:56.564784 progress 70 % (36 MB)
67 11:06:56.578253 progress 75 % (39 MB)
68 11:06:56.591624 progress 80 % (41 MB)
69 11:06:56.604562 progress 85 % (44 MB)
70 11:06:56.617846 progress 90 % (47 MB)
71 11:06:56.631057 progress 95 % (49 MB)
72 11:06:56.644245 progress 100 % (52 MB)
73 11:06:56.644471 52 MB downloaded in 0.27 s (197.07 MB/s)
74 11:06:56.644666 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:06:56.645106 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:06:56.645241 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:06:56.645342 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:06:56.645494 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:06:56.645574 saving as /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/dtb/mt8192-asurada-spherion-r0.dtb
81 11:06:56.645629 total size: 47258 (0 MB)
82 11:06:56.645686 No compression specified
83 11:06:56.646747 progress 69 % (0 MB)
84 11:06:56.646996 progress 100 % (0 MB)
85 11:06:56.647137 0 MB downloaded in 0.00 s (29.92 MB/s)
86 11:06:56.647248 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:06:56.647446 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:06:56.647521 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:06:56.647600 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:06:56.647705 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:06:56.647765 saving as /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/modules/modules.tar
93 11:06:56.647818 total size: 8607984 (8 MB)
94 11:06:56.647871 Using unxz to decompress xz
95 11:06:56.649195 progress 0 % (0 MB)
96 11:06:56.669393 progress 5 % (0 MB)
97 11:06:56.693602 progress 10 % (0 MB)
98 11:06:56.717813 progress 15 % (1 MB)
99 11:06:56.741687 progress 20 % (1 MB)
100 11:06:56.764719 progress 25 % (2 MB)
101 11:06:56.788130 progress 30 % (2 MB)
102 11:06:56.809897 progress 35 % (2 MB)
103 11:06:56.835872 progress 40 % (3 MB)
104 11:06:56.859614 progress 45 % (3 MB)
105 11:06:56.882917 progress 50 % (4 MB)
106 11:06:56.906531 progress 55 % (4 MB)
107 11:06:56.929695 progress 60 % (4 MB)
108 11:06:56.952484 progress 65 % (5 MB)
109 11:06:56.977791 progress 70 % (5 MB)
110 11:06:57.003954 progress 75 % (6 MB)
111 11:06:57.031015 progress 80 % (6 MB)
112 11:06:57.054149 progress 85 % (7 MB)
113 11:06:57.076880 progress 90 % (7 MB)
114 11:06:57.099602 progress 95 % (7 MB)
115 11:06:57.122248 progress 100 % (8 MB)
116 11:06:57.127486 8 MB downloaded in 0.48 s (17.11 MB/s)
117 11:06:57.127628 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:06:57.127837 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:06:57.127916 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:06:57.127991 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:06:57.128060 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:06:57.128130 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:06:57.128295 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b
125 11:06:57.128412 makedir: /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin
126 11:06:57.128516 makedir: /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/tests
127 11:06:57.128603 makedir: /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/results
128 11:06:57.128698 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-add-keys
129 11:06:57.128825 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-add-sources
130 11:06:57.128995 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-background-process-start
131 11:06:57.129181 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-background-process-stop
132 11:06:57.129312 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-common-functions
133 11:06:57.129425 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-echo-ipv4
134 11:06:57.129535 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-install-packages
135 11:06:57.129645 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-installed-packages
136 11:06:57.129753 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-os-build
137 11:06:57.129860 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-probe-channel
138 11:06:57.129974 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-probe-ip
139 11:06:57.130083 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-target-ip
140 11:06:57.130190 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-target-mac
141 11:06:57.130297 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-target-storage
142 11:06:57.130407 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-test-case
143 11:06:57.130516 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-test-event
144 11:06:57.130624 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-test-feedback
145 11:06:57.130731 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-test-raise
146 11:06:57.130844 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-test-reference
147 11:06:57.130952 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-test-runner
148 11:06:57.131061 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-test-set
149 11:06:57.131170 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-test-shell
150 11:06:57.131284 Updating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-install-packages (oe)
151 11:06:57.131415 Updating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/bin/lava-installed-packages (oe)
152 11:06:57.131522 Creating /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/environment
153 11:06:57.131610 LAVA metadata
154 11:06:57.131672 - LAVA_JOB_ID=14786855
155 11:06:57.131727 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:06:57.131814 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:06:57.131869 skipped lava-vland-overlay
158 11:06:57.131934 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:06:57.132003 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:06:57.132055 skipped lava-multinode-overlay
161 11:06:57.132118 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:06:57.132188 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:06:57.132250 Loading test definitions
164 11:06:57.132324 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:06:57.132381 Using /lava-14786855 at stage 0
166 11:06:57.132670 uuid=14786855_1.5.2.3.1 testdef=None
167 11:06:57.132754 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:06:57.132829 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:06:57.133289 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:06:57.133484 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:06:57.134053 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:06:57.134267 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:06:57.134819 runner path: /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/0/tests/0_cros-ec test_uuid 14786855_1.5.2.3.1
176 11:06:57.134962 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:06:57.135148 Creating lava-test-runner.conf files
179 11:06:57.135203 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786855/lava-overlay-62qdsr0b/lava-14786855/0 for stage 0
180 11:06:57.135282 - 0_cros-ec
181 11:06:57.135369 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:06:57.135442 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:06:57.141603 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:06:57.141695 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:06:57.141771 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:06:57.141845 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:06:57.141918 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:06:58.220507 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:06:58.220637 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:06:58.220713 extracting modules file /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786855/extract-overlay-ramdisk-cxxj02mb/ramdisk
191 11:06:58.453354 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:06:58.453493 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:06:58.453569 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786855/compress-overlay-wt_64n1u/overlay-1.5.2.4.tar.gz to ramdisk
194 11:06:58.453628 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786855/compress-overlay-wt_64n1u/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786855/extract-overlay-ramdisk-cxxj02mb/ramdisk
195 11:06:58.459857 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:06:58.459949 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:06:58.460032 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:06:58.460108 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:06:58.460171 Building ramdisk /var/lib/lava/dispatcher/tmp/14786855/extract-overlay-ramdisk-cxxj02mb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786855/extract-overlay-ramdisk-cxxj02mb/ramdisk
200 11:06:59.159635 >> 335381 blocks
201 11:07:04.368361 rename /var/lib/lava/dispatcher/tmp/14786855/extract-overlay-ramdisk-cxxj02mb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/ramdisk/ramdisk.cpio.gz
202 11:07:04.368528 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 11:07:04.368615 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 11:07:04.368696 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 11:07:04.368774 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/kernel/Image']
206 11:07:18.005051 Returned 0 in 13 seconds
207 11:07:18.005231 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/kernel/image.itb
208 11:07:18.717539 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:07:18.717668 output: Created: Wed Jul 10 12:07:18 2024
210 11:07:18.717729 output: Image 0 (kernel-1)
211 11:07:18.717784 output: Description:
212 11:07:18.717837 output: Created: Wed Jul 10 12:07:18 2024
213 11:07:18.717889 output: Type: Kernel Image
214 11:07:18.717940 output: Compression: lzma compressed
215 11:07:18.717992 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
216 11:07:18.718042 output: Architecture: AArch64
217 11:07:18.718091 output: OS: Linux
218 11:07:18.718140 output: Load Address: 0x00000000
219 11:07:18.718189 output: Entry Point: 0x00000000
220 11:07:18.718237 output: Hash algo: crc32
221 11:07:18.718286 output: Hash value: 9bb85fb9
222 11:07:18.718334 output: Image 1 (fdt-1)
223 11:07:18.718382 output: Description: mt8192-asurada-spherion-r0
224 11:07:18.718430 output: Created: Wed Jul 10 12:07:18 2024
225 11:07:18.718478 output: Type: Flat Device Tree
226 11:07:18.718526 output: Compression: uncompressed
227 11:07:18.718573 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:07:18.718622 output: Architecture: AArch64
229 11:07:18.718728 output: Hash algo: crc32
230 11:07:18.718780 output: Hash value: 0f8e4d2e
231 11:07:18.718861 output: Image 2 (ramdisk-1)
232 11:07:18.718979 output: Description: unavailable
233 11:07:18.719034 output: Created: Wed Jul 10 12:07:18 2024
234 11:07:18.719083 output: Type: RAMDisk Image
235 11:07:18.719151 output: Compression: uncompressed
236 11:07:18.719237 output: Data Size: 52110070 Bytes = 50888.74 KiB = 49.70 MiB
237 11:07:18.719300 output: Architecture: AArch64
238 11:07:18.719348 output: OS: Linux
239 11:07:18.719396 output: Load Address: unavailable
240 11:07:18.719443 output: Entry Point: unavailable
241 11:07:18.719490 output: Hash algo: crc32
242 11:07:18.719537 output: Hash value: 3552e2b0
243 11:07:18.719584 output: Default Configuration: 'conf-1'
244 11:07:18.719632 output: Configuration 0 (conf-1)
245 11:07:18.719680 output: Description: mt8192-asurada-spherion-r0
246 11:07:18.719728 output: Kernel: kernel-1
247 11:07:18.719776 output: Init Ramdisk: ramdisk-1
248 11:07:18.719825 output: FDT: fdt-1
249 11:07:18.719872 output: Loadables: kernel-1
250 11:07:18.719920 output:
251 11:07:18.720024 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:07:18.720097 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:07:18.720171 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 11:07:18.720245 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 11:07:18.720303 No LXC device requested
256 11:07:18.720372 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:07:18.720443 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 11:07:18.720511 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:07:18.720566 Checking files for TFTP limit of 4294967296 bytes.
260 11:07:18.721072 end: 1 tftp-deploy (duration 00:00:23) [common]
261 11:07:18.721214 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:07:18.721322 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:07:18.721453 substitutions:
264 11:07:18.721528 - {DTB}: 14786855/tftp-deploy-n63_asce/dtb/mt8192-asurada-spherion-r0.dtb
265 11:07:18.721609 - {INITRD}: 14786855/tftp-deploy-n63_asce/ramdisk/ramdisk.cpio.gz
266 11:07:18.721677 - {KERNEL}: 14786855/tftp-deploy-n63_asce/kernel/Image
267 11:07:18.721728 - {LAVA_MAC}: None
268 11:07:18.721778 - {PRESEED_CONFIG}: None
269 11:07:18.721828 - {PRESEED_LOCAL}: None
270 11:07:18.721877 - {RAMDISK}: 14786855/tftp-deploy-n63_asce/ramdisk/ramdisk.cpio.gz
271 11:07:18.721931 - {ROOT_PART}: None
272 11:07:18.721980 - {ROOT}: None
273 11:07:18.722029 - {SERVER_IP}: 192.168.201.1
274 11:07:18.722078 - {TEE}: None
275 11:07:18.722128 Parsed boot commands:
276 11:07:18.722176 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:07:18.722313 Parsed boot commands: tftpboot 192.168.201.1 14786855/tftp-deploy-n63_asce/kernel/image.itb 14786855/tftp-deploy-n63_asce/kernel/cmdline
278 11:07:18.722392 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:07:18.722465 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:07:18.722537 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:07:18.722607 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:07:18.722662 Not connected, no need to disconnect.
283 11:07:18.722728 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:07:18.722797 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:07:18.722851 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 11:07:18.726019 Setting prompt string to ['lava-test: # ']
287 11:07:18.726334 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:07:18.726428 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:07:18.726515 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:07:18.726620 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:07:18.726837 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 11:07:27.863662 >> Command sent successfully.
293 11:07:27.867160 Returned 0 in 9 seconds
294 11:07:27.867332 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:07:27.867533 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:07:27.867619 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:07:27.867690 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:07:27.867748 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:07:27.867804 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:07:27.868141 [Enter `^Ec?' for help]
302 11:07:29.444619
303 11:07:29.444751
304 11:07:29.444812 F0: 102B 0000
305 11:07:29.444871
306 11:07:29.444924 F3: 1001 0000 [0200]
307 11:07:29.448441
308 11:07:29.448519 F3: 1001 0000
309 11:07:29.448576
310 11:07:29.448632 F7: 102D 0000
311 11:07:29.448686
312 11:07:29.452612 F1: 0000 0000
313 11:07:29.452733
314 11:07:29.452791 V0: 0000 0000 [0001]
315 11:07:29.452850
316 11:07:29.452904 00: 0007 8000
317 11:07:29.452956
318 11:07:29.455449 01: 0000 0000
319 11:07:29.455526
320 11:07:29.455584 BP: 0C00 0209 [0000]
321 11:07:29.455638
322 11:07:29.460004 G0: 1182 0000
323 11:07:29.460085
324 11:07:29.460144 EC: 0000 0021 [4000]
325 11:07:29.460198
326 11:07:29.462990 S7: 0000 0000 [0000]
327 11:07:29.463080
328 11:07:29.463138 CC: 0000 0000 [0001]
329 11:07:29.463192
330 11:07:29.466531 T0: 0000 0040 [010F]
331 11:07:29.466606
332 11:07:29.466666 Jump to BL
333 11:07:29.466720
334 11:07:29.491835
335 11:07:29.491960
336 11:07:29.498169 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:07:29.502254 ARM64: Exception handlers installed.
338 11:07:29.505207 ARM64: Testing exception
339 11:07:29.508558 ARM64: Done test exception
340 11:07:29.515319 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:07:29.525110 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:07:29.531843 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:07:29.542544 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:07:29.549337 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:07:29.559677 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:07:29.569688 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:07:29.576373 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:07:29.594554 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:07:29.597873 WDT: Last reset was cold boot
350 11:07:29.601791 SPI1(PAD0) initialized at 2873684 Hz
351 11:07:29.604366 SPI5(PAD0) initialized at 992727 Hz
352 11:07:29.608160 VBOOT: Loading verstage.
353 11:07:29.614461 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:07:29.617942 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:07:29.621276 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:07:29.624386 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:07:29.631734 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:07:29.638100 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:07:29.649217 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
360 11:07:29.649377
361 11:07:29.649440
362 11:07:29.659628 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:07:29.662564 ARM64: Exception handlers installed.
364 11:07:29.666283 ARM64: Testing exception
365 11:07:29.666393 ARM64: Done test exception
366 11:07:29.672763 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:07:29.676119 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:07:29.690515 Probing TPM: . done!
369 11:07:29.690649 TPM ready after 0 ms
370 11:07:29.697595 Connected to device vid:did:rid of 1ae0:0028:00
371 11:07:29.707392 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 11:07:29.745043 Initialized TPM device CR50 revision 0
373 11:07:29.756428 tlcl_send_startup: Startup return code is 0
374 11:07:29.756548 TPM: setup succeeded
375 11:07:29.767995 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:07:29.776492 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:07:29.786483 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:07:29.795647 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:07:29.799146 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:07:29.802326 in-header: 03 07 00 00 08 00 00 00
381 11:07:29.805514 in-data: aa e4 47 04 13 02 00 00
382 11:07:29.809052 Chrome EC: UHEPI supported
383 11:07:29.815639 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:07:29.819086 in-header: 03 a9 00 00 08 00 00 00
385 11:07:29.822769 in-data: 84 60 60 08 00 00 00 00
386 11:07:29.822898 Phase 1
387 11:07:29.826104 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:07:29.832691 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:07:29.839507 VB2:vb2_check_recovery() Recovery was requested manually
390 11:07:29.842640 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:07:29.846322 Recovery requested (1009000e)
392 11:07:29.854090 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:07:29.859830 tlcl_extend: response is 0
394 11:07:29.867947 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:07:29.873270 tlcl_extend: response is 0
396 11:07:29.879979 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:07:29.900121 read SPI 0x210d4 0x2173b: 15148 us, 9045 KB/s, 72.360 Mbps
398 11:07:29.907585 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:07:29.907678
400 11:07:29.907737
401 11:07:29.916988 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:07:29.920355 ARM64: Exception handlers installed.
403 11:07:29.924113 ARM64: Testing exception
404 11:07:29.924194 ARM64: Done test exception
405 11:07:29.947278 pmic_efuse_setting: Set efuses in 11 msecs
406 11:07:29.950230 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:07:29.954044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:07:29.960906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:07:29.964556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:07:29.970750 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:07:29.974721 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:07:29.977589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:07:29.984998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:07:29.987599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:07:29.994486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:07:29.997933 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:07:30.005041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:07:30.007720 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:07:30.011112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:07:30.018652 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:07:30.024574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:07:30.027883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:07:30.034598 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:07:30.041066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:07:30.048142 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:07:30.051870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:07:30.058038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:07:30.065036 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:07:30.068354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:07:30.074695 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:07:30.078873 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:07:30.084892 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:07:30.091339 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:07:30.094727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:07:30.098103 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:07:30.105539 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:07:30.108312 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:07:30.115801 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:07:30.119042 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:07:30.125006 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:07:30.128856 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:07:30.135166 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:07:30.138950 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:07:30.145468 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:07:30.149550 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:07:30.153127 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:07:30.159481 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:07:30.163094 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:07:30.166168 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:07:30.169825 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:07:30.176257 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:07:30.179564 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:07:30.183508 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:07:30.190123 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:07:30.192960 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:07:30.196369 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:07:30.200137 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:07:30.209954 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:07:30.216942 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:07:30.221000 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:07:30.231200 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:07:30.237503 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:07:30.243842 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:07:30.247279 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:07:30.250463 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:07:30.259010 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x37
467 11:07:30.265294 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:07:30.268866 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:07:30.272143 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:07:30.283424 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 11:07:30.293055 [RTC]rtc_get_frequency_meter,154: input=23, output=980
472 11:07:30.302455 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 11:07:30.311713 [RTC]rtc_get_frequency_meter,154: input=17, output=838
474 11:07:30.321010 [RTC]rtc_get_frequency_meter,154: input=16, output=813
475 11:07:30.330569 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 11:07:30.340717 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 11:07:30.343453 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 11:07:30.350841 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 11:07:30.354203 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:07:30.357799 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 11:07:30.364494 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:07:30.367510 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 11:07:30.371468 ADC[4]: Raw value=901697 ID=7
484 11:07:30.371550 ADC[3]: Raw value=213336 ID=1
485 11:07:30.373928 RAM Code: 0x71
486 11:07:30.378072 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:07:30.383926 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:07:30.390612 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:07:30.397534 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:07:30.400669 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:07:30.404168 in-header: 03 07 00 00 08 00 00 00
492 11:07:30.407677 in-data: aa e4 47 04 13 02 00 00
493 11:07:30.410368 Chrome EC: UHEPI supported
494 11:07:30.417337 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:07:30.420707 in-header: 03 a9 00 00 08 00 00 00
496 11:07:30.423977 in-data: 84 60 60 08 00 00 00 00
497 11:07:30.427660 MRC: failed to locate region type 0.
498 11:07:30.434131 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:07:30.437598 DRAM-K: Running full calibration
500 11:07:30.444213 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:07:30.444309 header.status = 0x0
502 11:07:30.447723 header.version = 0x6 (expected: 0x6)
503 11:07:30.450689 header.size = 0xd00 (expected: 0xd00)
504 11:07:30.454744 header.flags = 0x0
505 11:07:30.460971 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:07:30.476894 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
507 11:07:30.483850 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:07:30.487302 dram_init: ddr_geometry: 2
509 11:07:30.487383 [EMI] MDL number = 2
510 11:07:30.490515 [EMI] Get MDL freq = 0
511 11:07:30.493644 dram_init: ddr_type: 0
512 11:07:30.493724 is_discrete_lpddr4: 1
513 11:07:30.497062 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:07:30.497168
515 11:07:30.497254
516 11:07:30.500466 [Bian_co] ETT version 0.0.0.1
517 11:07:30.503921 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:07:30.507202
519 11:07:30.510396 dramc_set_vcore_voltage set vcore to 650000
520 11:07:30.510479 Read voltage for 800, 4
521 11:07:30.514305 Vio18 = 0
522 11:07:30.514383 Vcore = 650000
523 11:07:30.514443 Vdram = 0
524 11:07:30.517422 Vddq = 0
525 11:07:30.517498 Vmddr = 0
526 11:07:30.521312 dram_init: config_dvfs: 1
527 11:07:30.524065 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:07:30.530510 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:07:30.534104 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 11:07:30.537555 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 11:07:30.540372 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 11:07:30.544115 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 11:07:30.547356 MEM_TYPE=3, freq_sel=18
534 11:07:30.550568 sv_algorithm_assistance_LP4_1600
535 11:07:30.553867 ============ PULL DRAM RESETB DOWN ============
536 11:07:30.557869 ========== PULL DRAM RESETB DOWN end =========
537 11:07:30.563977 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:07:30.567638 ===================================
539 11:07:30.567714 LPDDR4 DRAM CONFIGURATION
540 11:07:30.570807 ===================================
541 11:07:30.574254 EX_ROW_EN[0] = 0x0
542 11:07:30.577389 EX_ROW_EN[1] = 0x0
543 11:07:30.577465 LP4Y_EN = 0x0
544 11:07:30.581098 WORK_FSP = 0x0
545 11:07:30.581215 WL = 0x2
546 11:07:30.583846 RL = 0x2
547 11:07:30.583922 BL = 0x2
548 11:07:30.587618 RPST = 0x0
549 11:07:30.587694 RD_PRE = 0x0
550 11:07:30.591085 WR_PRE = 0x1
551 11:07:30.591185 WR_PST = 0x0
552 11:07:30.594847 DBI_WR = 0x0
553 11:07:30.594924 DBI_RD = 0x0
554 11:07:30.597669 OTF = 0x1
555 11:07:30.601068 ===================================
556 11:07:30.605330 ===================================
557 11:07:30.605408 ANA top config
558 11:07:30.609508 ===================================
559 11:07:30.609588 DLL_ASYNC_EN = 0
560 11:07:30.612950 ALL_SLAVE_EN = 1
561 11:07:30.616128 NEW_RANK_MODE = 1
562 11:07:30.620107 DLL_IDLE_MODE = 1
563 11:07:30.620186 LP45_APHY_COMB_EN = 1
564 11:07:30.623841 TX_ODT_DIS = 1
565 11:07:30.628472 NEW_8X_MODE = 1
566 11:07:30.628552 ===================================
567 11:07:30.631868 ===================================
568 11:07:30.634672 data_rate = 1600
569 11:07:30.637846 CKR = 1
570 11:07:30.641308 DQ_P2S_RATIO = 8
571 11:07:30.644843 ===================================
572 11:07:30.648741 CA_P2S_RATIO = 8
573 11:07:30.648820 DQ_CA_OPEN = 0
574 11:07:30.651446 DQ_SEMI_OPEN = 0
575 11:07:30.655176 CA_SEMI_OPEN = 0
576 11:07:30.658459 CA_FULL_RATE = 0
577 11:07:30.661839 DQ_CKDIV4_EN = 1
578 11:07:30.664789 CA_CKDIV4_EN = 1
579 11:07:30.664867 CA_PREDIV_EN = 0
580 11:07:30.668068 PH8_DLY = 0
581 11:07:30.671741 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:07:30.675205 DQ_AAMCK_DIV = 4
583 11:07:30.678135 CA_AAMCK_DIV = 4
584 11:07:30.681728 CA_ADMCK_DIV = 4
585 11:07:30.681808 DQ_TRACK_CA_EN = 0
586 11:07:30.684859 CA_PICK = 800
587 11:07:30.688392 CA_MCKIO = 800
588 11:07:30.691856 MCKIO_SEMI = 0
589 11:07:30.695147 PLL_FREQ = 3068
590 11:07:30.698966 DQ_UI_PI_RATIO = 32
591 11:07:30.699042 CA_UI_PI_RATIO = 0
592 11:07:30.701764 ===================================
593 11:07:30.705334 ===================================
594 11:07:30.708896 memory_type:LPDDR4
595 11:07:30.712072 GP_NUM : 10
596 11:07:30.712151 SRAM_EN : 1
597 11:07:30.715130 MD32_EN : 0
598 11:07:30.718537 ===================================
599 11:07:30.721995 [ANA_INIT] >>>>>>>>>>>>>>
600 11:07:30.725600 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:07:30.728688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:07:30.731725 ===================================
603 11:07:30.731824 data_rate = 1600,PCW = 0X7600
604 11:07:30.735087 ===================================
605 11:07:30.738853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:07:30.745531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:07:30.752289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:07:30.755318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:07:30.759022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:07:30.762291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:07:30.765849 [ANA_INIT] flow start
612 11:07:30.765928 [ANA_INIT] PLL >>>>>>>>
613 11:07:30.768782 [ANA_INIT] PLL <<<<<<<<
614 11:07:30.772515 [ANA_INIT] MIDPI >>>>>>>>
615 11:07:30.772606 [ANA_INIT] MIDPI <<<<<<<<
616 11:07:30.775720 [ANA_INIT] DLL >>>>>>>>
617 11:07:30.779258 [ANA_INIT] flow end
618 11:07:30.782507 ============ LP4 DIFF to SE enter ============
619 11:07:30.786342 ============ LP4 DIFF to SE exit ============
620 11:07:30.789212 [ANA_INIT] <<<<<<<<<<<<<
621 11:07:30.792347 [Flow] Enable top DCM control >>>>>
622 11:07:30.796021 [Flow] Enable top DCM control <<<<<
623 11:07:30.799110 Enable DLL master slave shuffle
624 11:07:30.802490 ==============================================================
625 11:07:30.805891 Gating Mode config
626 11:07:30.809087 ==============================================================
627 11:07:30.812621 Config description:
628 11:07:30.823056 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:07:30.829389 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:07:30.832663 SELPH_MODE 0: By rank 1: By Phase
631 11:07:30.839302 ==============================================================
632 11:07:30.842947 GAT_TRACK_EN = 1
633 11:07:30.846130 RX_GATING_MODE = 2
634 11:07:30.849301 RX_GATING_TRACK_MODE = 2
635 11:07:30.852562 SELPH_MODE = 1
636 11:07:30.852681 PICG_EARLY_EN = 1
637 11:07:30.856318 VALID_LAT_VALUE = 1
638 11:07:30.863332 ==============================================================
639 11:07:30.866099 Enter into Gating configuration >>>>
640 11:07:30.869342 Exit from Gating configuration <<<<
641 11:07:30.873171 Enter into DVFS_PRE_config >>>>>
642 11:07:30.883000 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:07:30.886702 Exit from DVFS_PRE_config <<<<<
644 11:07:30.889873 Enter into PICG configuration >>>>
645 11:07:30.892982 Exit from PICG configuration <<<<
646 11:07:30.897070 [RX_INPUT] configuration >>>>>
647 11:07:30.899821 [RX_INPUT] configuration <<<<<
648 11:07:30.903997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:07:30.909809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:07:30.916388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:07:30.920504 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:07:30.927203 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:07:30.933617 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:07:30.937412 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:07:30.940002 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:07:30.947320 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:07:30.950536 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:07:30.953447 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:07:30.960532 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:07:30.963557 ===================================
661 11:07:30.963661 LPDDR4 DRAM CONFIGURATION
662 11:07:30.966897 ===================================
663 11:07:30.970625 EX_ROW_EN[0] = 0x0
664 11:07:30.970725 EX_ROW_EN[1] = 0x0
665 11:07:30.973940 LP4Y_EN = 0x0
666 11:07:30.974038 WORK_FSP = 0x0
667 11:07:30.977000 WL = 0x2
668 11:07:30.977098 RL = 0x2
669 11:07:30.980687 BL = 0x2
670 11:07:30.980786 RPST = 0x0
671 11:07:30.983973 RD_PRE = 0x0
672 11:07:30.987000 WR_PRE = 0x1
673 11:07:30.987101 WR_PST = 0x0
674 11:07:30.990275 DBI_WR = 0x0
675 11:07:30.990373 DBI_RD = 0x0
676 11:07:30.993951 OTF = 0x1
677 11:07:30.997014 ===================================
678 11:07:31.000421 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:07:31.003826 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:07:31.007099 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:07:31.010412 ===================================
682 11:07:31.014528 LPDDR4 DRAM CONFIGURATION
683 11:07:31.017374 ===================================
684 11:07:31.021047 EX_ROW_EN[0] = 0x10
685 11:07:31.021152 EX_ROW_EN[1] = 0x0
686 11:07:31.023817 LP4Y_EN = 0x0
687 11:07:31.023914 WORK_FSP = 0x0
688 11:07:31.027615 WL = 0x2
689 11:07:31.027712 RL = 0x2
690 11:07:31.030596 BL = 0x2
691 11:07:31.030693 RPST = 0x0
692 11:07:31.034615 RD_PRE = 0x0
693 11:07:31.034712 WR_PRE = 0x1
694 11:07:31.037890 WR_PST = 0x0
695 11:07:31.037989 DBI_WR = 0x0
696 11:07:31.040928 DBI_RD = 0x0
697 11:07:31.041025 OTF = 0x1
698 11:07:31.044429 ===================================
699 11:07:31.050715 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:07:31.055982 nWR fixed to 40
701 11:07:31.059030 [ModeRegInit_LP4] CH0 RK0
702 11:07:31.059128 [ModeRegInit_LP4] CH0 RK1
703 11:07:31.062387 [ModeRegInit_LP4] CH1 RK0
704 11:07:31.065498 [ModeRegInit_LP4] CH1 RK1
705 11:07:31.065594 match AC timing 13
706 11:07:31.072085 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:07:31.075682 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:07:31.078599 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:07:31.085651 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:07:31.088931 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:07:31.089031 [EMI DOE] emi_dcm 0
712 11:07:31.095658 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:07:31.095770 ==
714 11:07:31.099071 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:07:31.102437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:07:31.102536 ==
717 11:07:31.109418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:07:31.112952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:07:31.122544 [CA 0] Center 37 (7~68) winsize 62
720 11:07:31.125975 [CA 1] Center 37 (6~68) winsize 63
721 11:07:31.129919 [CA 2] Center 35 (5~66) winsize 62
722 11:07:31.133395 [CA 3] Center 34 (4~65) winsize 62
723 11:07:31.135856 [CA 4] Center 34 (3~65) winsize 63
724 11:07:31.139755 [CA 5] Center 33 (3~64) winsize 62
725 11:07:31.139853
726 11:07:31.142688 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:07:31.142785
728 11:07:31.146144 [CATrainingPosCal] consider 1 rank data
729 11:07:31.149936 u2DelayCellTimex100 = 270/100 ps
730 11:07:31.154045 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:07:31.157054 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:07:31.160312 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 11:07:31.163430 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:07:31.167054 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 11:07:31.173860 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:07:31.173959
737 11:07:31.177007 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:07:31.177105
739 11:07:31.181007 [CBTSetCACLKResult] CA Dly = 33
740 11:07:31.181107 CS Dly: 5 (0~36)
741 11:07:31.181244 ==
742 11:07:31.184432 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:07:31.188194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:07:31.188293 ==
745 11:07:31.194483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:07:31.201327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:07:31.209534 [CA 0] Center 37 (7~68) winsize 62
748 11:07:31.212414 [CA 1] Center 37 (7~68) winsize 62
749 11:07:31.215856 [CA 2] Center 35 (5~66) winsize 62
750 11:07:31.219515 [CA 3] Center 35 (4~66) winsize 63
751 11:07:31.222553 [CA 4] Center 34 (3~65) winsize 63
752 11:07:31.226398 [CA 5] Center 33 (3~64) winsize 62
753 11:07:31.226498
754 11:07:31.228923 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 11:07:31.229019
756 11:07:31.232813 [CATrainingPosCal] consider 2 rank data
757 11:07:31.236052 u2DelayCellTimex100 = 270/100 ps
758 11:07:31.239476 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:07:31.242459 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:07:31.246967 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:07:31.252890 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:07:31.255902 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 11:07:31.259538 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:07:31.259640
765 11:07:31.262794 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:07:31.262894
767 11:07:31.267062 [CBTSetCACLKResult] CA Dly = 33
768 11:07:31.267161 CS Dly: 5 (0~37)
769 11:07:31.267247
770 11:07:31.269697 ----->DramcWriteLeveling(PI) begin...
771 11:07:31.269796 ==
772 11:07:31.273261 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:07:31.279738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:07:31.279841 ==
775 11:07:31.282971 Write leveling (Byte 0): 30 => 30
776 11:07:31.283070 Write leveling (Byte 1): 29 => 29
777 11:07:31.286332 DramcWriteLeveling(PI) end<-----
778 11:07:31.286429
779 11:07:31.286515 ==
780 11:07:31.290265 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:07:31.296576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:07:31.296679 ==
783 11:07:31.300355 [Gating] SW mode calibration
784 11:07:31.306921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:07:31.310179 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:07:31.313430 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:07:31.319706 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 11:07:31.323746 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
789 11:07:31.326533 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:07:31.333610 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:07:31.336533 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:07:31.340041 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:07:31.346706 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:07:31.350974 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:07:31.353864 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:07:31.360598 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:07:31.363956 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:07:31.367081 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:07:31.370698 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:07:31.377044 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:07:31.380552 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:07:31.384193 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:07:31.390696 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:07:31.393673 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 11:07:31.397468 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:07:31.404222 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:07:31.407782 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:07:31.410804 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:07:31.418131 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:07:31.421066 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:07:31.424698 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:07:31.427389 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:07:31.434944 0 9 12 | B1->B0 | 2626 3131 | 0 1 | (0 0) (1 1)
814 11:07:31.437475 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:07:31.441423 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:07:31.447767 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:07:31.450932 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:07:31.454931 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:07:31.461529 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
820 11:07:31.465313 0 10 8 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (1 0)
821 11:07:31.468364 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 11:07:31.475253 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:07:31.478116 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:07:31.481417 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:07:31.484783 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:07:31.491464 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:07:31.495049 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:07:31.498316 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
829 11:07:31.505561 0 11 12 | B1->B0 | 4040 4141 | 0 0 | (0 0) (0 0)
830 11:07:31.508479 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:07:31.511499 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:07:31.518735 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:07:31.522179 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:07:31.524985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:07:31.531994 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 11:07:31.535236 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:07:31.538390 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:07:31.541774 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:07:31.548689 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:07:31.552098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:07:31.555880 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:07:31.562506 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:07:31.565103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:07:31.568889 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:07:31.575618 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:07:31.579106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:07:31.582234 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:07:31.589281 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:07:31.592442 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:07:31.595734 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:07:31.598738 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:07:31.606320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 11:07:31.609050 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 11:07:31.612522 Total UI for P1: 0, mck2ui 16
855 11:07:31.615885 best dqsien dly found for B0: ( 0, 14, 8)
856 11:07:31.619326 Total UI for P1: 0, mck2ui 16
857 11:07:31.622337 best dqsien dly found for B1: ( 0, 14, 8)
858 11:07:31.626430 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 11:07:31.629203 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:07:31.629284
861 11:07:31.632345 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 11:07:31.636035 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:07:31.639052 [Gating] SW calibration Done
864 11:07:31.639116 ==
865 11:07:31.643072 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:07:31.645668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:07:31.645739 ==
868 11:07:31.649706 RX Vref Scan: 0
869 11:07:31.649785
870 11:07:31.652443 RX Vref 0 -> 0, step: 1
871 11:07:31.652534
872 11:07:31.652615 RX Delay -130 -> 252, step: 16
873 11:07:31.659524 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:07:31.663284 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 11:07:31.666068 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:07:31.669352 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:07:31.672804 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 11:07:31.679787 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 11:07:31.682703 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:07:31.686283 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 11:07:31.689310 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
882 11:07:31.692728 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 11:07:31.699591 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 11:07:31.702875 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:07:31.706436 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:07:31.710096 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 11:07:31.712899 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 11:07:31.719870 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 11:07:31.719951 ==
890 11:07:31.723377 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:07:31.726951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:07:31.727027 ==
893 11:07:31.727086 DQS Delay:
894 11:07:31.730019 DQS0 = 0, DQS1 = 0
895 11:07:31.730094 DQM Delay:
896 11:07:31.733420 DQM0 = 86, DQM1 = 77
897 11:07:31.733495 DQ Delay:
898 11:07:31.737189 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 11:07:31.739897 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
900 11:07:31.743335 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
901 11:07:31.746981 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 11:07:31.747058
903 11:07:31.747116
904 11:07:31.747169 ==
905 11:07:31.750533 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:07:31.753310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:07:31.753390 ==
908 11:07:31.753448
909 11:07:31.753502
910 11:07:31.756954 TX Vref Scan disable
911 11:07:31.760533 == TX Byte 0 ==
912 11:07:31.763307 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 11:07:31.766806 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 11:07:31.770594 == TX Byte 1 ==
915 11:07:31.773868 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 11:07:31.776688 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 11:07:31.776765 ==
918 11:07:31.781033 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:07:31.783360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:07:31.786824 ==
921 11:07:31.798121 TX Vref=22, minBit 5, minWin=27, winSum=438
922 11:07:31.802246 TX Vref=24, minBit 3, minWin=27, winSum=444
923 11:07:31.805001 TX Vref=26, minBit 9, minWin=27, winSum=449
924 11:07:31.808132 TX Vref=28, minBit 12, minWin=27, winSum=454
925 11:07:31.811498 TX Vref=30, minBit 1, minWin=28, winSum=454
926 11:07:31.814866 TX Vref=32, minBit 2, minWin=28, winSum=455
927 11:07:31.822070 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 32
928 11:07:31.822157
929 11:07:31.825432 Final TX Range 1 Vref 32
930 11:07:31.825501
931 11:07:31.825555 ==
932 11:07:31.828426 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:07:31.832760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:07:31.832838 ==
935 11:07:31.832897
936 11:07:31.832951
937 11:07:31.835432 TX Vref Scan disable
938 11:07:31.838841 == TX Byte 0 ==
939 11:07:31.842497 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 11:07:31.845303 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 11:07:31.849296 == TX Byte 1 ==
942 11:07:31.852180 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 11:07:31.855398 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 11:07:31.855475
945 11:07:31.858923 [DATLAT]
946 11:07:31.859000 Freq=800, CH0 RK0
947 11:07:31.859063
948 11:07:31.862645 DATLAT Default: 0xa
949 11:07:31.862723 0, 0xFFFF, sum = 0
950 11:07:31.865717 1, 0xFFFF, sum = 0
951 11:07:31.865796 2, 0xFFFF, sum = 0
952 11:07:31.868924 3, 0xFFFF, sum = 0
953 11:07:31.869027 4, 0xFFFF, sum = 0
954 11:07:31.872329 5, 0xFFFF, sum = 0
955 11:07:31.872408 6, 0xFFFF, sum = 0
956 11:07:31.875402 7, 0xFFFF, sum = 0
957 11:07:31.875479 8, 0xFFFF, sum = 0
958 11:07:31.879209 9, 0x0, sum = 1
959 11:07:31.879286 10, 0x0, sum = 2
960 11:07:31.882315 11, 0x0, sum = 3
961 11:07:31.882394 12, 0x0, sum = 4
962 11:07:31.885621 best_step = 10
963 11:07:31.885699
964 11:07:31.885759 ==
965 11:07:31.889484 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:07:31.892345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:07:31.892426 ==
968 11:07:31.892487 RX Vref Scan: 1
969 11:07:31.892543
970 11:07:31.895614 Set Vref Range= 32 -> 127
971 11:07:31.895691
972 11:07:31.899164 RX Vref 32 -> 127, step: 1
973 11:07:31.899241
974 11:07:31.902779 RX Delay -95 -> 252, step: 8
975 11:07:31.902857
976 11:07:31.905831 Set Vref, RX VrefLevel [Byte0]: 32
977 11:07:31.909045 [Byte1]: 32
978 11:07:31.909181
979 11:07:31.912346 Set Vref, RX VrefLevel [Byte0]: 33
980 11:07:31.916058 [Byte1]: 33
981 11:07:31.916135
982 11:07:31.919631 Set Vref, RX VrefLevel [Byte0]: 34
983 11:07:31.922959 [Byte1]: 34
984 11:07:31.926087
985 11:07:31.926164 Set Vref, RX VrefLevel [Byte0]: 35
986 11:07:31.929086 [Byte1]: 35
987 11:07:31.933721
988 11:07:31.933858 Set Vref, RX VrefLevel [Byte0]: 36
989 11:07:31.936981 [Byte1]: 36
990 11:07:31.941258
991 11:07:31.941335 Set Vref, RX VrefLevel [Byte0]: 37
992 11:07:31.944719 [Byte1]: 37
993 11:07:31.948785
994 11:07:31.948863 Set Vref, RX VrefLevel [Byte0]: 38
995 11:07:31.952143 [Byte1]: 38
996 11:07:31.956570
997 11:07:31.956648 Set Vref, RX VrefLevel [Byte0]: 39
998 11:07:31.959569 [Byte1]: 39
999 11:07:31.964093
1000 11:07:31.964197 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:07:31.967288 [Byte1]: 40
1002 11:07:31.972019
1003 11:07:31.972097 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:07:31.974595 [Byte1]: 41
1005 11:07:31.979250
1006 11:07:31.979329 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:07:31.982700 [Byte1]: 42
1008 11:07:31.986574
1009 11:07:31.986769 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:07:31.990384 [Byte1]: 43
1011 11:07:31.994902
1012 11:07:31.994985 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:07:31.997873 [Byte1]: 44
1014 11:07:32.001752
1015 11:07:32.001853 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:07:32.005717 [Byte1]: 45
1017 11:07:32.009594
1018 11:07:32.009675 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:07:32.013033 [Byte1]: 46
1020 11:07:32.017489
1021 11:07:32.017593 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:07:32.020361 [Byte1]: 47
1023 11:07:32.024487
1024 11:07:32.024567 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:07:32.027947 [Byte1]: 48
1026 11:07:32.031971
1027 11:07:32.032050 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:07:32.035699 [Byte1]: 49
1029 11:07:32.040454
1030 11:07:32.040537 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:07:32.043573 [Byte1]: 50
1032 11:07:32.047743
1033 11:07:32.047821 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:07:32.050557 [Byte1]: 51
1035 11:07:32.055017
1036 11:07:32.055095 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:07:32.058664 [Byte1]: 52
1038 11:07:32.062798
1039 11:07:32.062878 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:07:32.066432 [Byte1]: 53
1041 11:07:32.070970
1042 11:07:32.071051 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:07:32.073853 [Byte1]: 54
1044 11:07:32.078043
1045 11:07:32.078123 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:07:32.080838 [Byte1]: 55
1047 11:07:32.085820
1048 11:07:32.085902 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:07:32.088691 [Byte1]: 56
1050 11:07:32.093054
1051 11:07:32.093171 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:07:32.096108 [Byte1]: 57
1053 11:07:32.100971
1054 11:07:32.101051 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:07:32.103978 [Byte1]: 58
1056 11:07:32.108889
1057 11:07:32.108967 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:07:32.112252 [Byte1]: 59
1059 11:07:32.115723
1060 11:07:32.115807 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:07:32.119455 [Byte1]: 60
1062 11:07:32.123194
1063 11:07:32.123274 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:07:32.126594 [Byte1]: 61
1065 11:07:32.131038
1066 11:07:32.131117 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:07:32.134123 [Byte1]: 62
1068 11:07:32.138780
1069 11:07:32.138862 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:07:32.142228 [Byte1]: 63
1071 11:07:32.146306
1072 11:07:32.146413 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:07:32.149323 [Byte1]: 64
1074 11:07:32.154144
1075 11:07:32.154223 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:07:32.157492 [Byte1]: 65
1077 11:07:32.161362
1078 11:07:32.161442 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:07:32.164937 [Byte1]: 66
1080 11:07:32.169374
1081 11:07:32.169455 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:07:32.172112 [Byte1]: 67
1083 11:07:32.176662
1084 11:07:32.176741 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:07:32.179695 [Byte1]: 68
1086 11:07:32.184657
1087 11:07:32.184737 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:07:32.187297 [Byte1]: 69
1089 11:07:32.191761
1090 11:07:32.191839 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:07:32.195172 [Byte1]: 70
1092 11:07:32.199519
1093 11:07:32.199601 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:07:32.202795 [Byte1]: 71
1095 11:07:32.207284
1096 11:07:32.207362 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:07:32.210109 [Byte1]: 72
1098 11:07:32.214368
1099 11:07:32.214446 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:07:32.218019 [Byte1]: 73
1101 11:07:32.222370
1102 11:07:32.222447 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:07:32.225675 [Byte1]: 74
1104 11:07:32.229966
1105 11:07:32.230043 Set Vref, RX VrefLevel [Byte0]: 75
1106 11:07:32.233843 [Byte1]: 75
1107 11:07:32.237379
1108 11:07:32.237467 Set Vref, RX VrefLevel [Byte0]: 76
1109 11:07:32.240529 [Byte1]: 76
1110 11:07:32.244850
1111 11:07:32.244926 Final RX Vref Byte 0 = 61 to rank0
1112 11:07:32.248098 Final RX Vref Byte 1 = 56 to rank0
1113 11:07:32.251978 Final RX Vref Byte 0 = 61 to rank1
1114 11:07:32.254975 Final RX Vref Byte 1 = 56 to rank1==
1115 11:07:32.258372 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 11:07:32.261744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 11:07:32.265167 ==
1118 11:07:32.265244 DQS Delay:
1119 11:07:32.265304 DQS0 = 0, DQS1 = 0
1120 11:07:32.268713 DQM Delay:
1121 11:07:32.268793 DQM0 = 88, DQM1 = 78
1122 11:07:32.271791 DQ Delay:
1123 11:07:32.271867 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 11:07:32.275385 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1125 11:07:32.278427 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1126 11:07:32.281617 DQ12 =80, DQ13 =80, DQ14 =92, DQ15 =88
1127 11:07:32.281694
1128 11:07:32.284955
1129 11:07:32.291869 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
1130 11:07:32.295390 CH0 RK0: MR19=606, MR18=2F16
1131 11:07:32.301926 CH0_RK0: MR19=0x606, MR18=0x2F16, DQSOSC=397, MR23=63, INC=93, DEC=62
1132 11:07:32.302016
1133 11:07:32.305141 ----->DramcWriteLeveling(PI) begin...
1134 11:07:32.305236 ==
1135 11:07:32.308973 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 11:07:32.312886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 11:07:32.312992 ==
1138 11:07:32.315244 Write leveling (Byte 0): 32 => 32
1139 11:07:32.318828 Write leveling (Byte 1): 27 => 27
1140 11:07:32.322551 DramcWriteLeveling(PI) end<-----
1141 11:07:32.322629
1142 11:07:32.322687 ==
1143 11:07:32.325853 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 11:07:32.328430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 11:07:32.328519 ==
1146 11:07:32.332527 [Gating] SW mode calibration
1147 11:07:32.338824 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 11:07:32.345400 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 11:07:32.348682 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 11:07:32.352550 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 11:07:32.355910 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 11:07:32.362091 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:07:32.366309 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:07:32.368989 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:07:32.376027 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:07:32.379145 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:07:32.419956 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:07:32.420449 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:07:32.421004 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:07:32.421081 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:07:32.421355 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:07:32.421594 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:07:32.421831 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:07:32.422329 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:07:32.422405 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 11:07:32.425080 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 11:07:32.428728 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1168 11:07:32.431693 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:07:32.435327 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:07:32.441809 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:07:32.445499 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:07:32.448668 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:07:32.455436 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:07:32.459265 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:07:32.462056 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1176 11:07:32.465507 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1177 11:07:32.472546 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 11:07:32.476197 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 11:07:32.479310 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 11:07:32.485737 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:07:32.488903 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:07:32.492430 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1183 11:07:32.499430 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1184 11:07:32.502865 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:07:32.505704 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:07:32.512329 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:07:32.515479 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:07:32.519185 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:07:32.522697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:07:32.528959 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1191 11:07:32.532259 0 11 8 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (0 0)
1192 11:07:32.535819 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1193 11:07:32.542371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 11:07:32.545923 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 11:07:32.549061 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 11:07:32.555724 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:07:32.559236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:07:32.562494 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:07:32.569298 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 11:07:32.572461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:07:32.576245 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:07:32.582489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:07:32.585936 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:07:32.589334 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:07:32.592592 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:07:32.599230 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:07:32.602882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:07:32.606103 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:07:32.613308 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:07:32.616198 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:07:32.619824 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:07:32.626031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:07:32.629944 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:07:32.633483 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 11:07:32.639335 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 11:07:32.639415 Total UI for P1: 0, mck2ui 16
1217 11:07:32.646053 best dqsien dly found for B0: ( 0, 14, 4)
1218 11:07:32.646132 Total UI for P1: 0, mck2ui 16
1219 11:07:32.650058 best dqsien dly found for B1: ( 0, 14, 6)
1220 11:07:32.656141 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1221 11:07:32.659606 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1222 11:07:32.659716
1223 11:07:32.663192 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1224 11:07:32.666872 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1225 11:07:32.670279 [Gating] SW calibration Done
1226 11:07:32.670356 ==
1227 11:07:32.673126 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 11:07:32.676575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 11:07:32.676650 ==
1230 11:07:32.676709 RX Vref Scan: 0
1231 11:07:32.676764
1232 11:07:32.680152 RX Vref 0 -> 0, step: 1
1233 11:07:32.680227
1234 11:07:32.683272 RX Delay -130 -> 252, step: 16
1235 11:07:32.686456 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 11:07:32.690366 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1237 11:07:32.696519 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1238 11:07:32.700198 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1239 11:07:32.703669 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1240 11:07:32.706776 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1241 11:07:32.710198 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 11:07:32.713681 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1243 11:07:32.719930 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1244 11:07:32.723447 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1245 11:07:32.726695 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1246 11:07:32.730265 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1247 11:07:32.733566 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1248 11:07:32.740136 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1249 11:07:32.743870 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1250 11:07:32.746837 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1251 11:07:32.746913 ==
1252 11:07:32.750195 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 11:07:32.753770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 11:07:32.753846 ==
1255 11:07:32.757306 DQS Delay:
1256 11:07:32.757381 DQS0 = 0, DQS1 = 0
1257 11:07:32.760671 DQM Delay:
1258 11:07:32.760746 DQM0 = 86, DQM1 = 74
1259 11:07:32.760804 DQ Delay:
1260 11:07:32.763945 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1261 11:07:32.767157 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1262 11:07:32.770249 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1263 11:07:32.773443 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1264 11:07:32.773519
1265 11:07:32.773577
1266 11:07:32.777667 ==
1267 11:07:32.780608 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 11:07:32.783769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 11:07:32.783846 ==
1270 11:07:32.783905
1271 11:07:32.783959
1272 11:07:32.787259 TX Vref Scan disable
1273 11:07:32.787335 == TX Byte 0 ==
1274 11:07:32.790319 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1275 11:07:32.796943 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1276 11:07:32.797023 == TX Byte 1 ==
1277 11:07:32.800854 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1278 11:07:32.807681 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1279 11:07:32.807765 ==
1280 11:07:32.810650 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 11:07:32.814016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 11:07:32.814092 ==
1283 11:07:32.827753 TX Vref=22, minBit 5, minWin=27, winSum=443
1284 11:07:32.830636 TX Vref=24, minBit 3, minWin=27, winSum=447
1285 11:07:32.834591 TX Vref=26, minBit 10, minWin=27, winSum=449
1286 11:07:32.837608 TX Vref=28, minBit 9, minWin=27, winSum=451
1287 11:07:32.841083 TX Vref=30, minBit 9, minWin=27, winSum=453
1288 11:07:32.844414 TX Vref=32, minBit 9, minWin=27, winSum=452
1289 11:07:32.850980 [TxChooseVref] Worse bit 9, Min win 27, Win sum 453, Final Vref 30
1290 11:07:32.851060
1291 11:07:32.854371 Final TX Range 1 Vref 30
1292 11:07:32.854448
1293 11:07:32.854506 ==
1294 11:07:32.857453 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 11:07:32.860826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 11:07:32.860902 ==
1297 11:07:32.860961
1298 11:07:32.864013
1299 11:07:32.864088 TX Vref Scan disable
1300 11:07:32.867507 == TX Byte 0 ==
1301 11:07:32.871643 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1302 11:07:32.874479 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1303 11:07:32.878166 == TX Byte 1 ==
1304 11:07:32.881745 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1305 11:07:32.884532 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1306 11:07:32.884610
1307 11:07:32.888045 [DATLAT]
1308 11:07:32.888120 Freq=800, CH0 RK1
1309 11:07:32.888179
1310 11:07:32.891316 DATLAT Default: 0xa
1311 11:07:32.891392 0, 0xFFFF, sum = 0
1312 11:07:32.894651 1, 0xFFFF, sum = 0
1313 11:07:32.894728 2, 0xFFFF, sum = 0
1314 11:07:32.897853 3, 0xFFFF, sum = 0
1315 11:07:32.897929 4, 0xFFFF, sum = 0
1316 11:07:32.901275 5, 0xFFFF, sum = 0
1317 11:07:32.901351 6, 0xFFFF, sum = 0
1318 11:07:32.905008 7, 0xFFFF, sum = 0
1319 11:07:32.905113 8, 0xFFFF, sum = 0
1320 11:07:32.908156 9, 0x0, sum = 1
1321 11:07:32.908232 10, 0x0, sum = 2
1322 11:07:32.911421 11, 0x0, sum = 3
1323 11:07:32.911524 12, 0x0, sum = 4
1324 11:07:32.915506 best_step = 10
1325 11:07:32.915581
1326 11:07:32.915639 ==
1327 11:07:32.917832 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 11:07:32.921395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 11:07:32.921494 ==
1330 11:07:32.925253 RX Vref Scan: 0
1331 11:07:32.925328
1332 11:07:32.925386 RX Vref 0 -> 0, step: 1
1333 11:07:32.925440
1334 11:07:32.928195 RX Delay -111 -> 252, step: 8
1335 11:07:32.934976 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 11:07:32.938494 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1337 11:07:32.941638 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1338 11:07:32.944772 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1339 11:07:32.948048 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1340 11:07:32.951407 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1341 11:07:32.958780 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1342 11:07:32.961692 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1343 11:07:32.966219 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1344 11:07:32.968728 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 11:07:32.972221 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1346 11:07:32.978844 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1347 11:07:32.982247 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1348 11:07:32.985635 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1349 11:07:32.988726 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1350 11:07:32.991871 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1351 11:07:32.991948 ==
1352 11:07:32.995369 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 11:07:33.002009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 11:07:33.002092 ==
1355 11:07:33.002151 DQS Delay:
1356 11:07:33.005818 DQS0 = 0, DQS1 = 0
1357 11:07:33.005893 DQM Delay:
1358 11:07:33.005952 DQM0 = 87, DQM1 = 77
1359 11:07:33.009081 DQ Delay:
1360 11:07:33.012580 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1361 11:07:33.016079 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1362 11:07:33.019096 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1363 11:07:33.022459 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1364 11:07:33.022534
1365 11:07:33.022591
1366 11:07:33.029011 [DQSOSCAuto] RK1, (LSB)MR18= 0x3019, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1367 11:07:33.032656 CH0 RK1: MR19=606, MR18=3019
1368 11:07:33.039037 CH0_RK1: MR19=0x606, MR18=0x3019, DQSOSC=397, MR23=63, INC=93, DEC=62
1369 11:07:33.042775 [RxdqsGatingPostProcess] freq 800
1370 11:07:33.046158 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 11:07:33.049321 Pre-setting of DQS Precalculation
1372 11:07:33.055970 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 11:07:33.056048 ==
1374 11:07:33.059442 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 11:07:33.062626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 11:07:33.062702 ==
1377 11:07:33.066150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 11:07:33.072709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 11:07:33.082289 [CA 0] Center 36 (6~67) winsize 62
1380 11:07:33.086216 [CA 1] Center 36 (5~67) winsize 63
1381 11:07:33.090054 [CA 2] Center 34 (4~64) winsize 61
1382 11:07:33.092463 [CA 3] Center 33 (3~64) winsize 62
1383 11:07:33.096436 [CA 4] Center 34 (3~65) winsize 63
1384 11:07:33.099726 [CA 5] Center 33 (3~64) winsize 62
1385 11:07:33.099802
1386 11:07:33.102824 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1387 11:07:33.102899
1388 11:07:33.106293 [CATrainingPosCal] consider 1 rank data
1389 11:07:33.110165 u2DelayCellTimex100 = 270/100 ps
1390 11:07:33.112964 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1391 11:07:33.116013 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1392 11:07:33.122521 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1393 11:07:33.126606 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1394 11:07:33.129542 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1395 11:07:33.132734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 11:07:33.132810
1397 11:07:33.135983 CA PerBit enable=1, Macro0, CA PI delay=33
1398 11:07:33.136058
1399 11:07:33.139505 [CBTSetCACLKResult] CA Dly = 33
1400 11:07:33.139583 CS Dly: 4 (0~35)
1401 11:07:33.139642 ==
1402 11:07:33.142830 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 11:07:33.149632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 11:07:33.149711 ==
1405 11:07:33.153154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 11:07:33.159363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 11:07:33.168792 [CA 0] Center 36 (5~67) winsize 63
1408 11:07:33.171931 [CA 1] Center 36 (5~67) winsize 63
1409 11:07:33.175832 [CA 2] Center 34 (4~64) winsize 61
1410 11:07:33.179119 [CA 3] Center 33 (3~64) winsize 62
1411 11:07:33.182832 [CA 4] Center 34 (3~65) winsize 63
1412 11:07:33.185618 [CA 5] Center 33 (3~64) winsize 62
1413 11:07:33.185694
1414 11:07:33.188972 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1415 11:07:33.189047
1416 11:07:33.192201 [CATrainingPosCal] consider 2 rank data
1417 11:07:33.195797 u2DelayCellTimex100 = 270/100 ps
1418 11:07:33.199296 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1419 11:07:33.202611 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1420 11:07:33.205743 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1421 11:07:33.209296 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1422 11:07:33.215850 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1423 11:07:33.219446 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 11:07:33.219522
1425 11:07:33.222482 CA PerBit enable=1, Macro0, CA PI delay=33
1426 11:07:33.222557
1427 11:07:33.226217 [CBTSetCACLKResult] CA Dly = 33
1428 11:07:33.226292 CS Dly: 4 (0~36)
1429 11:07:33.226351
1430 11:07:33.229364 ----->DramcWriteLeveling(PI) begin...
1431 11:07:33.229440 ==
1432 11:07:33.233339 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 11:07:33.239956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 11:07:33.240032 ==
1435 11:07:33.243576 Write leveling (Byte 0): 28 => 28
1436 11:07:33.243652 Write leveling (Byte 1): 28 => 28
1437 11:07:33.246321 DramcWriteLeveling(PI) end<-----
1438 11:07:33.246395
1439 11:07:33.246453 ==
1440 11:07:33.249405 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 11:07:33.256990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 11:07:33.257066 ==
1443 11:07:33.257150 [Gating] SW mode calibration
1444 11:07:33.266489 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 11:07:33.269882 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 11:07:33.272930 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 11:07:33.279596 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1448 11:07:33.283480 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1449 11:07:33.286371 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:07:33.292839 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:07:33.296175 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:07:33.299635 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:07:33.306799 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:07:33.310214 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:07:33.313150 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:07:33.319849 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:07:33.323311 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:07:33.327273 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:07:33.333568 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1460 11:07:33.337062 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:07:33.340397 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1462 11:07:33.343676 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1463 11:07:33.350136 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1464 11:07:33.353542 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:07:33.357079 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:07:33.363643 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:07:33.367107 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:07:33.370141 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:07:33.376947 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:07:33.380381 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:07:33.383759 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:07:33.390642 0 9 8 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
1473 11:07:33.393563 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 11:07:33.396940 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 11:07:33.400425 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1476 11:07:33.407073 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 11:07:33.411145 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 11:07:33.413735 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:07:33.420775 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1480 11:07:33.423620 0 10 8 | B1->B0 | 2c2c 2d2d | 0 0 | (1 1) (1 1)
1481 11:07:33.427994 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:07:33.433816 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:07:33.437384 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:07:33.440624 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:07:33.447085 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:07:33.450620 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:07:33.454058 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:07:33.460569 0 11 8 | B1->B0 | 3939 3737 | 0 0 | (0 0) (1 1)
1489 11:07:33.463827 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 11:07:33.467165 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 11:07:33.471100 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 11:07:33.477581 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 11:07:33.480827 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:07:33.483851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:07:33.490813 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1496 11:07:33.494018 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1497 11:07:33.497399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1498 11:07:33.504534 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:07:33.507608 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:07:33.511433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:07:33.517627 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:07:33.521387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:07:33.524508 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:07:33.527735 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:07:33.534392 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:07:33.538017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:07:33.541338 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:07:33.548247 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:07:33.551304 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:07:33.554719 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:07:33.561572 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:07:33.564721 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 11:07:33.567804 Total UI for P1: 0, mck2ui 16
1514 11:07:33.572406 best dqsien dly found for B0: ( 0, 14, 6)
1515 11:07:33.574775 Total UI for P1: 0, mck2ui 16
1516 11:07:33.578306 best dqsien dly found for B1: ( 0, 14, 6)
1517 11:07:33.581211 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1518 11:07:33.584921 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1519 11:07:33.585000
1520 11:07:33.588972 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1521 11:07:33.591511 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 11:07:33.594824 [Gating] SW calibration Done
1523 11:07:33.594905 ==
1524 11:07:33.598636 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 11:07:33.601819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 11:07:33.601906 ==
1527 11:07:33.605562 RX Vref Scan: 0
1528 11:07:33.605720
1529 11:07:33.605808 RX Vref 0 -> 0, step: 1
1530 11:07:33.608708
1531 11:07:33.608864 RX Delay -130 -> 252, step: 16
1532 11:07:33.614769 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1533 11:07:33.618147 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1534 11:07:33.621531 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1535 11:07:33.624860 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1536 11:07:33.628372 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1537 11:07:33.631882 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1538 11:07:33.638199 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1539 11:07:33.642449 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1540 11:07:33.645057 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1541 11:07:33.648810 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1542 11:07:33.651810 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1543 11:07:33.659154 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1544 11:07:33.661656 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1545 11:07:33.665717 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1546 11:07:33.668609 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1547 11:07:33.672815 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1548 11:07:33.675638 ==
1549 11:07:33.675758 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 11:07:33.682640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 11:07:33.682758 ==
1552 11:07:33.682820 DQS Delay:
1553 11:07:33.685696 DQS0 = 0, DQS1 = 0
1554 11:07:33.685781 DQM Delay:
1555 11:07:33.685837 DQM0 = 81, DQM1 = 74
1556 11:07:33.688764 DQ Delay:
1557 11:07:33.692561 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1558 11:07:33.695618 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1559 11:07:33.699267 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1560 11:07:33.702984 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1561 11:07:33.703084
1562 11:07:33.703160
1563 11:07:33.703233 ==
1564 11:07:33.705540 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 11:07:33.708851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 11:07:33.708928 ==
1567 11:07:33.709020
1568 11:07:33.709110
1569 11:07:33.712833 TX Vref Scan disable
1570 11:07:33.712910 == TX Byte 0 ==
1571 11:07:33.719367 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1572 11:07:33.722761 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1573 11:07:33.722839 == TX Byte 1 ==
1574 11:07:33.729312 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 11:07:33.732809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 11:07:33.732886 ==
1577 11:07:33.736006 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 11:07:33.739178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 11:07:33.739256 ==
1580 11:07:33.752692 TX Vref=22, minBit 13, minWin=26, winSum=434
1581 11:07:33.756308 TX Vref=24, minBit 4, minWin=27, winSum=444
1582 11:07:33.759683 TX Vref=26, minBit 10, minWin=26, winSum=445
1583 11:07:33.762678 TX Vref=28, minBit 10, minWin=27, winSum=452
1584 11:07:33.766190 TX Vref=30, minBit 9, minWin=27, winSum=451
1585 11:07:33.772780 TX Vref=32, minBit 11, minWin=27, winSum=454
1586 11:07:33.776599 [TxChooseVref] Worse bit 11, Min win 27, Win sum 454, Final Vref 32
1587 11:07:33.776678
1588 11:07:33.779736 Final TX Range 1 Vref 32
1589 11:07:33.779820
1590 11:07:33.779897 ==
1591 11:07:33.783033 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 11:07:33.786251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 11:07:33.786328 ==
1594 11:07:33.789425
1595 11:07:33.789501
1596 11:07:33.789560 TX Vref Scan disable
1597 11:07:33.793000 == TX Byte 0 ==
1598 11:07:33.797224 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1599 11:07:33.800200 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1600 11:07:33.803100 == TX Byte 1 ==
1601 11:07:33.806452 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1602 11:07:33.809612 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1603 11:07:33.812910
1604 11:07:33.812987 [DATLAT]
1605 11:07:33.813098 Freq=800, CH1 RK0
1606 11:07:33.813195
1607 11:07:33.816605 DATLAT Default: 0xa
1608 11:07:33.816682 0, 0xFFFF, sum = 0
1609 11:07:33.820445 1, 0xFFFF, sum = 0
1610 11:07:33.820522 2, 0xFFFF, sum = 0
1611 11:07:33.823793 3, 0xFFFF, sum = 0
1612 11:07:33.823863 4, 0xFFFF, sum = 0
1613 11:07:33.827295 5, 0xFFFF, sum = 0
1614 11:07:33.827396 6, 0xFFFF, sum = 0
1615 11:07:33.830719 7, 0xFFFF, sum = 0
1616 11:07:33.830797 8, 0xFFFF, sum = 0
1617 11:07:33.833531 9, 0x0, sum = 1
1618 11:07:33.833610 10, 0x0, sum = 2
1619 11:07:33.836607 11, 0x0, sum = 3
1620 11:07:33.836687 12, 0x0, sum = 4
1621 11:07:33.839868 best_step = 10
1622 11:07:33.839945
1623 11:07:33.840021 ==
1624 11:07:33.843439 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:07:33.846813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:07:33.846892 ==
1627 11:07:33.849926 RX Vref Scan: 1
1628 11:07:33.850003
1629 11:07:33.850080 Set Vref Range= 32 -> 127
1630 11:07:33.850151
1631 11:07:33.854231 RX Vref 32 -> 127, step: 1
1632 11:07:33.854308
1633 11:07:33.856775 RX Delay -111 -> 252, step: 8
1634 11:07:33.856852
1635 11:07:33.860668 Set Vref, RX VrefLevel [Byte0]: 32
1636 11:07:33.864470 [Byte1]: 32
1637 11:07:33.864549
1638 11:07:33.867223 Set Vref, RX VrefLevel [Byte0]: 33
1639 11:07:33.870881 [Byte1]: 33
1640 11:07:33.873564
1641 11:07:33.873642 Set Vref, RX VrefLevel [Byte0]: 34
1642 11:07:33.877059 [Byte1]: 34
1643 11:07:33.881208
1644 11:07:33.881286 Set Vref, RX VrefLevel [Byte0]: 35
1645 11:07:33.885055 [Byte1]: 35
1646 11:07:33.888868
1647 11:07:33.888946 Set Vref, RX VrefLevel [Byte0]: 36
1648 11:07:33.892111 [Byte1]: 36
1649 11:07:33.896596
1650 11:07:33.896674 Set Vref, RX VrefLevel [Byte0]: 37
1651 11:07:33.899800 [Byte1]: 37
1652 11:07:33.904099
1653 11:07:33.904176 Set Vref, RX VrefLevel [Byte0]: 38
1654 11:07:33.907431 [Byte1]: 38
1655 11:07:33.912269
1656 11:07:33.912347 Set Vref, RX VrefLevel [Byte0]: 39
1657 11:07:33.915310 [Byte1]: 39
1658 11:07:33.919725
1659 11:07:33.919813 Set Vref, RX VrefLevel [Byte0]: 40
1660 11:07:33.922859 [Byte1]: 40
1661 11:07:33.927217
1662 11:07:33.927294 Set Vref, RX VrefLevel [Byte0]: 41
1663 11:07:33.931177 [Byte1]: 41
1664 11:07:33.934832
1665 11:07:33.934909 Set Vref, RX VrefLevel [Byte0]: 42
1666 11:07:33.938355 [Byte1]: 42
1667 11:07:33.942302
1668 11:07:33.942380 Set Vref, RX VrefLevel [Byte0]: 43
1669 11:07:33.945938 [Byte1]: 43
1670 11:07:33.950555
1671 11:07:33.950631 Set Vref, RX VrefLevel [Byte0]: 44
1672 11:07:33.953677 [Byte1]: 44
1673 11:07:33.957780
1674 11:07:33.957855 Set Vref, RX VrefLevel [Byte0]: 45
1675 11:07:33.961073 [Byte1]: 45
1676 11:07:33.965474
1677 11:07:33.965549 Set Vref, RX VrefLevel [Byte0]: 46
1678 11:07:33.968799 [Byte1]: 46
1679 11:07:33.973397
1680 11:07:33.973472 Set Vref, RX VrefLevel [Byte0]: 47
1681 11:07:33.976604 [Byte1]: 47
1682 11:07:33.980689
1683 11:07:33.980765 Set Vref, RX VrefLevel [Byte0]: 48
1684 11:07:33.984175 [Byte1]: 48
1685 11:07:33.988414
1686 11:07:33.988490 Set Vref, RX VrefLevel [Byte0]: 49
1687 11:07:33.991581 [Byte1]: 49
1688 11:07:33.996176
1689 11:07:33.996252 Set Vref, RX VrefLevel [Byte0]: 50
1690 11:07:33.999362 [Byte1]: 50
1691 11:07:34.003816
1692 11:07:34.003896 Set Vref, RX VrefLevel [Byte0]: 51
1693 11:07:34.006809 [Byte1]: 51
1694 11:07:34.011595
1695 11:07:34.011671 Set Vref, RX VrefLevel [Byte0]: 52
1696 11:07:34.014669 [Byte1]: 52
1697 11:07:34.019345
1698 11:07:34.019421 Set Vref, RX VrefLevel [Byte0]: 53
1699 11:07:34.022540 [Byte1]: 53
1700 11:07:34.026578
1701 11:07:34.026653 Set Vref, RX VrefLevel [Byte0]: 54
1702 11:07:34.030311 [Byte1]: 54
1703 11:07:34.034003
1704 11:07:34.034078 Set Vref, RX VrefLevel [Byte0]: 55
1705 11:07:34.037607 [Byte1]: 55
1706 11:07:34.041929
1707 11:07:34.042006 Set Vref, RX VrefLevel [Byte0]: 56
1708 11:07:34.045749 [Byte1]: 56
1709 11:07:34.049487
1710 11:07:34.049562 Set Vref, RX VrefLevel [Byte0]: 57
1711 11:07:34.052889 [Byte1]: 57
1712 11:07:34.057431
1713 11:07:34.057507 Set Vref, RX VrefLevel [Byte0]: 58
1714 11:07:34.060745 [Byte1]: 58
1715 11:07:34.064838
1716 11:07:34.064914 Set Vref, RX VrefLevel [Byte0]: 59
1717 11:07:34.068109 [Byte1]: 59
1718 11:07:34.072849
1719 11:07:34.072925 Set Vref, RX VrefLevel [Byte0]: 60
1720 11:07:34.076185 [Byte1]: 60
1721 11:07:34.079950
1722 11:07:34.080026 Set Vref, RX VrefLevel [Byte0]: 61
1723 11:07:34.084053 [Byte1]: 61
1724 11:07:34.087506
1725 11:07:34.087582 Set Vref, RX VrefLevel [Byte0]: 62
1726 11:07:34.091136 [Byte1]: 62
1727 11:07:34.095553
1728 11:07:34.095628 Set Vref, RX VrefLevel [Byte0]: 63
1729 11:07:34.098656 [Byte1]: 63
1730 11:07:34.103167
1731 11:07:34.103243 Set Vref, RX VrefLevel [Byte0]: 64
1732 11:07:34.106149 [Byte1]: 64
1733 11:07:34.110898
1734 11:07:34.110975 Set Vref, RX VrefLevel [Byte0]: 65
1735 11:07:34.114139 [Byte1]: 65
1736 11:07:34.118722
1737 11:07:34.118798 Set Vref, RX VrefLevel [Byte0]: 66
1738 11:07:34.121683 [Byte1]: 66
1739 11:07:34.126193
1740 11:07:34.126268 Set Vref, RX VrefLevel [Byte0]: 67
1741 11:07:34.129244 [Byte1]: 67
1742 11:07:34.133454
1743 11:07:34.133529 Set Vref, RX VrefLevel [Byte0]: 68
1744 11:07:34.137405 [Byte1]: 68
1745 11:07:34.141045
1746 11:07:34.141170 Set Vref, RX VrefLevel [Byte0]: 69
1747 11:07:34.144546 [Byte1]: 69
1748 11:07:34.148964
1749 11:07:34.149040 Set Vref, RX VrefLevel [Byte0]: 70
1750 11:07:34.151987 [Byte1]: 70
1751 11:07:34.156560
1752 11:07:34.156636 Set Vref, RX VrefLevel [Byte0]: 71
1753 11:07:34.160205 [Byte1]: 71
1754 11:07:34.164263
1755 11:07:34.164339 Set Vref, RX VrefLevel [Byte0]: 72
1756 11:07:34.167263 [Byte1]: 72
1757 11:07:34.172705
1758 11:07:34.172781 Set Vref, RX VrefLevel [Byte0]: 73
1759 11:07:34.175067 [Byte1]: 73
1760 11:07:34.179714
1761 11:07:34.179788 Set Vref, RX VrefLevel [Byte0]: 74
1762 11:07:34.182679 [Byte1]: 74
1763 11:07:34.187019
1764 11:07:34.187095 Set Vref, RX VrefLevel [Byte0]: 75
1765 11:07:34.190537 [Byte1]: 75
1766 11:07:34.194693
1767 11:07:34.194769 Set Vref, RX VrefLevel [Byte0]: 76
1768 11:07:34.198157 [Byte1]: 76
1769 11:07:34.202970
1770 11:07:34.203046 Final RX Vref Byte 0 = 63 to rank0
1771 11:07:34.205699 Final RX Vref Byte 1 = 56 to rank0
1772 11:07:34.209237 Final RX Vref Byte 0 = 63 to rank1
1773 11:07:34.212300 Final RX Vref Byte 1 = 56 to rank1==
1774 11:07:34.215726 Dram Type= 6, Freq= 0, CH_1, rank 0
1775 11:07:34.222516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1776 11:07:34.222595 ==
1777 11:07:34.222673 DQS Delay:
1778 11:07:34.222745 DQS0 = 0, DQS1 = 0
1779 11:07:34.226020 DQM Delay:
1780 11:07:34.226103 DQM0 = 82, DQM1 = 72
1781 11:07:34.229376 DQ Delay:
1782 11:07:34.232390 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1783 11:07:34.232467 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1784 11:07:34.235988 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1785 11:07:34.239123 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1786 11:07:34.242657
1787 11:07:34.242733
1788 11:07:34.249372 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1789 11:07:34.252428 CH1 RK0: MR19=606, MR18=2B00
1790 11:07:34.259850 CH1_RK0: MR19=0x606, MR18=0x2B00, DQSOSC=398, MR23=63, INC=93, DEC=62
1791 11:07:34.259929
1792 11:07:34.262864 ----->DramcWriteLeveling(PI) begin...
1793 11:07:34.262942 ==
1794 11:07:34.265888 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 11:07:34.269708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 11:07:34.269819 ==
1797 11:07:34.273373 Write leveling (Byte 0): 31 => 31
1798 11:07:34.276164 Write leveling (Byte 1): 30 => 30
1799 11:07:34.280434 DramcWriteLeveling(PI) end<-----
1800 11:07:34.280512
1801 11:07:34.280588 ==
1802 11:07:34.282767 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 11:07:34.286422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 11:07:34.286499 ==
1805 11:07:34.289784 [Gating] SW mode calibration
1806 11:07:34.296314 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1807 11:07:34.303102 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1808 11:07:34.306432 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1809 11:07:34.309796 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1810 11:07:34.312836 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:07:34.319721 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:07:34.322924 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:07:34.326587 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:07:34.333329 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:07:34.336351 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:07:34.339795 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:07:34.346542 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:07:34.349885 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:07:34.353267 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:07:34.360512 0 7 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1821 11:07:34.363814 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1822 11:07:34.366716 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:07:34.370107 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1824 11:07:34.376906 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1825 11:07:34.380741 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1826 11:07:34.383984 0 8 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1827 11:07:34.390102 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:07:34.393867 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:07:34.396942 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:07:34.403488 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:07:34.407454 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:07:34.411018 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:07:34.414355 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1834 11:07:34.421522 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1835 11:07:34.423890 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 11:07:34.427420 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 11:07:34.434252 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 11:07:34.437449 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 11:07:34.441068 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:07:34.447508 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:07:34.450570 0 10 4 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 1)
1842 11:07:34.454202 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 11:07:34.460772 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:07:34.464345 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1845 11:07:34.467706 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:07:34.474370 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:07:34.477885 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:07:34.480995 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:07:34.484441 0 11 4 | B1->B0 | 2f2f 3939 | 0 0 | (1 1) (0 0)
1850 11:07:34.490781 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1851 11:07:34.494207 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 11:07:34.497644 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 11:07:34.504547 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 11:07:34.507596 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 11:07:34.511776 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:07:34.517724 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:07:34.521225 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1858 11:07:34.524943 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:07:34.531662 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:07:34.534891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:07:34.538341 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:07:34.544444 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:07:34.547946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:07:34.551112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:07:34.554592 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:07:34.561287 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:07:34.564821 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:07:34.568120 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:07:34.574705 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:07:34.578189 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:07:34.581610 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:07:34.588414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:07:34.591272 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1874 11:07:34.594835 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1875 11:07:34.598399 Total UI for P1: 0, mck2ui 16
1876 11:07:34.601260 best dqsien dly found for B0: ( 0, 14, 4)
1877 11:07:34.608377 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 11:07:34.608474 Total UI for P1: 0, mck2ui 16
1879 11:07:34.611362 best dqsien dly found for B1: ( 0, 14, 8)
1880 11:07:34.615075 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1881 11:07:34.621833 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1882 11:07:34.621937
1883 11:07:34.625360 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1884 11:07:34.628376 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1885 11:07:34.632171 [Gating] SW calibration Done
1886 11:07:34.632260 ==
1887 11:07:34.635075 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 11:07:34.639024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 11:07:34.639112 ==
1890 11:07:34.639172 RX Vref Scan: 0
1891 11:07:34.639227
1892 11:07:34.642032 RX Vref 0 -> 0, step: 1
1893 11:07:34.642109
1894 11:07:34.645426 RX Delay -130 -> 252, step: 16
1895 11:07:34.648407 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1896 11:07:34.651837 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1897 11:07:34.658728 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1898 11:07:34.661707 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1899 11:07:34.665246 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1900 11:07:34.669107 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1901 11:07:34.672090 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1902 11:07:34.675430 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1903 11:07:34.681972 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1904 11:07:34.685606 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1905 11:07:34.688641 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1906 11:07:34.692161 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1907 11:07:34.696072 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1908 11:07:34.702133 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1909 11:07:34.705765 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1910 11:07:34.709067 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1911 11:07:34.709204 ==
1912 11:07:34.712316 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 11:07:34.716204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 11:07:34.716379 ==
1915 11:07:34.718975 DQS Delay:
1916 11:07:34.719131 DQS0 = 0, DQS1 = 0
1917 11:07:34.722455 DQM Delay:
1918 11:07:34.722641 DQM0 = 78, DQM1 = 77
1919 11:07:34.722785 DQ Delay:
1920 11:07:34.726092 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1921 11:07:34.729423 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1922 11:07:34.732584 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1923 11:07:34.735561 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1924 11:07:34.735952
1925 11:07:34.736319
1926 11:07:34.736567 ==
1927 11:07:34.739433 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 11:07:34.746063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 11:07:34.746416 ==
1930 11:07:34.746729
1931 11:07:34.746999
1932 11:07:34.747449 TX Vref Scan disable
1933 11:07:34.749957 == TX Byte 0 ==
1934 11:07:34.753643 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1935 11:07:34.756738 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1936 11:07:34.759869 == TX Byte 1 ==
1937 11:07:34.763618 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1938 11:07:34.766893 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1939 11:07:34.769808 ==
1940 11:07:34.770159 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 11:07:34.777029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 11:07:34.777442 ==
1943 11:07:34.788907 TX Vref=22, minBit 9, minWin=27, winSum=443
1944 11:07:34.792074 TX Vref=24, minBit 14, minWin=27, winSum=448
1945 11:07:34.795634 TX Vref=26, minBit 15, minWin=27, winSum=450
1946 11:07:34.799076 TX Vref=28, minBit 15, minWin=27, winSum=454
1947 11:07:34.802395 TX Vref=30, minBit 7, minWin=28, winSum=457
1948 11:07:34.805644 TX Vref=32, minBit 8, minWin=28, winSum=458
1949 11:07:34.812741 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1950 11:07:34.813150
1951 11:07:34.815459 Final TX Range 1 Vref 32
1952 11:07:34.815811
1953 11:07:34.816175 ==
1954 11:07:34.818852 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 11:07:34.822196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 11:07:34.822550 ==
1957 11:07:34.822823
1958 11:07:34.823077
1959 11:07:34.826212 TX Vref Scan disable
1960 11:07:34.829106 == TX Byte 0 ==
1961 11:07:34.832712 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1962 11:07:34.836043 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1963 11:07:34.839672 == TX Byte 1 ==
1964 11:07:34.842543 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1965 11:07:34.846297 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1966 11:07:34.846824
1967 11:07:34.849408 [DATLAT]
1968 11:07:34.849770 Freq=800, CH1 RK1
1969 11:07:34.850049
1970 11:07:34.852887 DATLAT Default: 0xa
1971 11:07:34.853275 0, 0xFFFF, sum = 0
1972 11:07:34.856539 1, 0xFFFF, sum = 0
1973 11:07:34.856899 2, 0xFFFF, sum = 0
1974 11:07:34.859258 3, 0xFFFF, sum = 0
1975 11:07:34.859668 4, 0xFFFF, sum = 0
1976 11:07:34.862632 5, 0xFFFF, sum = 0
1977 11:07:34.862994 6, 0xFFFF, sum = 0
1978 11:07:34.866194 7, 0xFFFF, sum = 0
1979 11:07:34.866566 8, 0xFFFF, sum = 0
1980 11:07:34.869638 9, 0x0, sum = 1
1981 11:07:34.870010 10, 0x0, sum = 2
1982 11:07:34.873344 11, 0x0, sum = 3
1983 11:07:34.873705 12, 0x0, sum = 4
1984 11:07:34.875835 best_step = 10
1985 11:07:34.876328
1986 11:07:34.876620 ==
1987 11:07:34.879722 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 11:07:34.883063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 11:07:34.883416 ==
1990 11:07:34.885936 RX Vref Scan: 0
1991 11:07:34.886296
1992 11:07:34.886573 RX Vref 0 -> 0, step: 1
1993 11:07:34.886885
1994 11:07:34.889567 RX Delay -111 -> 252, step: 8
1995 11:07:34.896507 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
1996 11:07:34.899860 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
1997 11:07:34.902892 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
1998 11:07:34.906352 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
1999 11:07:34.909788 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2000 11:07:34.913415 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2001 11:07:34.920030 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2002 11:07:34.924223 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2003 11:07:34.926339 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2004 11:07:34.930569 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2005 11:07:34.933314 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2006 11:07:34.940275 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2007 11:07:34.943347 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2008 11:07:34.946880 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2009 11:07:34.950158 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2010 11:07:34.953112 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2011 11:07:34.953513 ==
2012 11:07:34.956992 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 11:07:34.963309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 11:07:34.963843 ==
2015 11:07:34.964299 DQS Delay:
2016 11:07:34.967124 DQS0 = 0, DQS1 = 0
2017 11:07:34.967621 DQM Delay:
2018 11:07:34.968052 DQM0 = 79, DQM1 = 75
2019 11:07:34.970121 DQ Delay:
2020 11:07:34.973611 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2021 11:07:34.977080 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
2022 11:07:34.977462 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2023 11:07:34.983907 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2024 11:07:34.984261
2025 11:07:34.984538
2026 11:07:34.990434 [DQSOSCAuto] RK1, (LSB)MR18= 0x2430, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2027 11:07:34.994018 CH1 RK1: MR19=606, MR18=2430
2028 11:07:35.000882 CH1_RK1: MR19=0x606, MR18=0x2430, DQSOSC=397, MR23=63, INC=93, DEC=62
2029 11:07:35.003890 [RxdqsGatingPostProcess] freq 800
2030 11:07:35.007254 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 11:07:35.010802 Pre-setting of DQS Precalculation
2032 11:07:35.017320 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 11:07:35.024103 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 11:07:35.031051 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 11:07:35.031406
2036 11:07:35.031678
2037 11:07:35.033936 [Calibration Summary] 1600 Mbps
2038 11:07:35.034288 CH 0, Rank 0
2039 11:07:35.037807 SW Impedance : PASS
2040 11:07:35.038160 DUTY Scan : NO K
2041 11:07:35.040903 ZQ Calibration : PASS
2042 11:07:35.044211 Jitter Meter : NO K
2043 11:07:35.044565 CBT Training : PASS
2044 11:07:35.047615 Write leveling : PASS
2045 11:07:35.051081 RX DQS gating : PASS
2046 11:07:35.051433 RX DQ/DQS(RDDQC) : PASS
2047 11:07:35.054237 TX DQ/DQS : PASS
2048 11:07:35.057531 RX DATLAT : PASS
2049 11:07:35.057883 RX DQ/DQS(Engine): PASS
2050 11:07:35.060759 TX OE : NO K
2051 11:07:35.061114 All Pass.
2052 11:07:35.061417
2053 11:07:35.064556 CH 0, Rank 1
2054 11:07:35.064907 SW Impedance : PASS
2055 11:07:35.067780 DUTY Scan : NO K
2056 11:07:35.068136 ZQ Calibration : PASS
2057 11:07:35.070740 Jitter Meter : NO K
2058 11:07:35.074854 CBT Training : PASS
2059 11:07:35.075209 Write leveling : PASS
2060 11:07:35.077584 RX DQS gating : PASS
2061 11:07:35.081170 RX DQ/DQS(RDDQC) : PASS
2062 11:07:35.081541 TX DQ/DQS : PASS
2063 11:07:35.084671 RX DATLAT : PASS
2064 11:07:35.087842 RX DQ/DQS(Engine): PASS
2065 11:07:35.088201 TX OE : NO K
2066 11:07:35.091141 All Pass.
2067 11:07:35.091495
2068 11:07:35.091773 CH 1, Rank 0
2069 11:07:35.095026 SW Impedance : PASS
2070 11:07:35.095382 DUTY Scan : NO K
2071 11:07:35.097876 ZQ Calibration : PASS
2072 11:07:35.101060 Jitter Meter : NO K
2073 11:07:35.101660 CBT Training : PASS
2074 11:07:35.104634 Write leveling : PASS
2075 11:07:35.105031 RX DQS gating : PASS
2076 11:07:35.107806 RX DQ/DQS(RDDQC) : PASS
2077 11:07:35.111321 TX DQ/DQS : PASS
2078 11:07:35.111731 RX DATLAT : PASS
2079 11:07:35.114795 RX DQ/DQS(Engine): PASS
2080 11:07:35.117844 TX OE : NO K
2081 11:07:35.118202 All Pass.
2082 11:07:35.118474
2083 11:07:35.118726 CH 1, Rank 1
2084 11:07:35.121378 SW Impedance : PASS
2085 11:07:35.124800 DUTY Scan : NO K
2086 11:07:35.125179 ZQ Calibration : PASS
2087 11:07:35.128308 Jitter Meter : NO K
2088 11:07:35.131343 CBT Training : PASS
2089 11:07:35.131696 Write leveling : PASS
2090 11:07:35.134722 RX DQS gating : PASS
2091 11:07:35.135078 RX DQ/DQS(RDDQC) : PASS
2092 11:07:35.138118 TX DQ/DQS : PASS
2093 11:07:35.141599 RX DATLAT : PASS
2094 11:07:35.141951 RX DQ/DQS(Engine): PASS
2095 11:07:35.145176 TX OE : NO K
2096 11:07:35.145537 All Pass.
2097 11:07:35.145813
2098 11:07:35.148208 DramC Write-DBI off
2099 11:07:35.151879 PER_BANK_REFRESH: Hybrid Mode
2100 11:07:35.152234 TX_TRACKING: ON
2101 11:07:35.155110 [GetDramInforAfterCalByMRR] Vendor 6.
2102 11:07:35.158484 [GetDramInforAfterCalByMRR] Revision 606.
2103 11:07:35.161687 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 11:07:35.164796 MR0 0x3b3b
2105 11:07:35.165179 MR8 0x5151
2106 11:07:35.168485 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 11:07:35.168997
2108 11:07:35.169411 MR0 0x3b3b
2109 11:07:35.171968 MR8 0x5151
2110 11:07:35.175005 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 11:07:35.175356
2112 11:07:35.185843 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 11:07:35.188276 [FAST_K] Save calibration result to emmc
2114 11:07:35.191421 [FAST_K] Save calibration result to emmc
2115 11:07:35.191795 dram_init: config_dvfs: 1
2116 11:07:35.198415 dramc_set_vcore_voltage set vcore to 662500
2117 11:07:35.198772 Read voltage for 1200, 2
2118 11:07:35.201782 Vio18 = 0
2119 11:07:35.202135 Vcore = 662500
2120 11:07:35.202410 Vdram = 0
2121 11:07:35.202664 Vddq = 0
2122 11:07:35.204849 Vmddr = 0
2123 11:07:35.208276 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 11:07:35.215309 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 11:07:35.215675 MEM_TYPE=3, freq_sel=15
2126 11:07:35.218694 sv_algorithm_assistance_LP4_1600
2127 11:07:35.225279 ============ PULL DRAM RESETB DOWN ============
2128 11:07:35.228696 ========== PULL DRAM RESETB DOWN end =========
2129 11:07:35.232296 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 11:07:35.235314 ===================================
2131 11:07:35.238571 LPDDR4 DRAM CONFIGURATION
2132 11:07:35.242156 ===================================
2133 11:07:35.246065 EX_ROW_EN[0] = 0x0
2134 11:07:35.246535 EX_ROW_EN[1] = 0x0
2135 11:07:35.248762 LP4Y_EN = 0x0
2136 11:07:35.249235 WORK_FSP = 0x0
2137 11:07:35.252075 WL = 0x4
2138 11:07:35.252430 RL = 0x4
2139 11:07:35.255639 BL = 0x2
2140 11:07:35.255995 RPST = 0x0
2141 11:07:35.258992 RD_PRE = 0x0
2142 11:07:35.259351 WR_PRE = 0x1
2143 11:07:35.262119 WR_PST = 0x0
2144 11:07:35.262600 DBI_WR = 0x0
2145 11:07:35.265608 DBI_RD = 0x0
2146 11:07:35.265970 OTF = 0x1
2147 11:07:35.268664 ===================================
2148 11:07:35.272234 ===================================
2149 11:07:35.275758 ANA top config
2150 11:07:35.279028 ===================================
2151 11:07:35.279416 DLL_ASYNC_EN = 0
2152 11:07:35.282118 ALL_SLAVE_EN = 0
2153 11:07:35.285584 NEW_RANK_MODE = 1
2154 11:07:35.289345 DLL_IDLE_MODE = 1
2155 11:07:35.289703 LP45_APHY_COMB_EN = 1
2156 11:07:35.292042 TX_ODT_DIS = 1
2157 11:07:35.295755 NEW_8X_MODE = 1
2158 11:07:35.298730 ===================================
2159 11:07:35.302571 ===================================
2160 11:07:35.305843 data_rate = 2400
2161 11:07:35.308942 CKR = 1
2162 11:07:35.312379 DQ_P2S_RATIO = 8
2163 11:07:35.315944 ===================================
2164 11:07:35.316300 CA_P2S_RATIO = 8
2165 11:07:35.318985 DQ_CA_OPEN = 0
2166 11:07:35.322302 DQ_SEMI_OPEN = 0
2167 11:07:35.325911 CA_SEMI_OPEN = 0
2168 11:07:35.329104 CA_FULL_RATE = 0
2169 11:07:35.329488 DQ_CKDIV4_EN = 0
2170 11:07:35.332443 CA_CKDIV4_EN = 0
2171 11:07:35.336534 CA_PREDIV_EN = 0
2172 11:07:35.339296 PH8_DLY = 17
2173 11:07:35.342456 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 11:07:35.346789 DQ_AAMCK_DIV = 4
2175 11:07:35.347145 CA_AAMCK_DIV = 4
2176 11:07:35.349436 CA_ADMCK_DIV = 4
2177 11:07:35.352728 DQ_TRACK_CA_EN = 0
2178 11:07:35.356265 CA_PICK = 1200
2179 11:07:35.360114 CA_MCKIO = 1200
2180 11:07:35.363033 MCKIO_SEMI = 0
2181 11:07:35.366159 PLL_FREQ = 2366
2182 11:07:35.366518 DQ_UI_PI_RATIO = 32
2183 11:07:35.369574 CA_UI_PI_RATIO = 0
2184 11:07:35.373052 ===================================
2185 11:07:35.376685 ===================================
2186 11:07:35.379729 memory_type:LPDDR4
2187 11:07:35.382984 GP_NUM : 10
2188 11:07:35.383508 SRAM_EN : 1
2189 11:07:35.386598 MD32_EN : 0
2190 11:07:35.390116 ===================================
2191 11:07:35.390476 [ANA_INIT] >>>>>>>>>>>>>>
2192 11:07:35.392928 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 11:07:35.396830 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 11:07:35.399542 ===================================
2195 11:07:35.402868 data_rate = 2400,PCW = 0X5b00
2196 11:07:35.406505 ===================================
2197 11:07:35.410215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 11:07:35.416900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 11:07:35.419596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 11:07:35.426618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 11:07:35.429978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 11:07:35.433157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 11:07:35.433597 [ANA_INIT] flow start
2204 11:07:35.436899 [ANA_INIT] PLL >>>>>>>>
2205 11:07:35.439914 [ANA_INIT] PLL <<<<<<<<
2206 11:07:35.440360 [ANA_INIT] MIDPI >>>>>>>>
2207 11:07:35.443684 [ANA_INIT] MIDPI <<<<<<<<
2208 11:07:35.446682 [ANA_INIT] DLL >>>>>>>>
2209 11:07:35.447115 [ANA_INIT] DLL <<<<<<<<
2210 11:07:35.450024 [ANA_INIT] flow end
2211 11:07:35.453417 ============ LP4 DIFF to SE enter ============
2212 11:07:35.460942 ============ LP4 DIFF to SE exit ============
2213 11:07:35.461439 [ANA_INIT] <<<<<<<<<<<<<
2214 11:07:35.463539 [Flow] Enable top DCM control >>>>>
2215 11:07:35.466565 [Flow] Enable top DCM control <<<<<
2216 11:07:35.470826 Enable DLL master slave shuffle
2217 11:07:35.476539 ==============================================================
2218 11:07:35.476995 Gating Mode config
2219 11:07:35.483651 ==============================================================
2220 11:07:35.484100 Config description:
2221 11:07:35.494163 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 11:07:35.500329 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 11:07:35.507284 SELPH_MODE 0: By rank 1: By Phase
2224 11:07:35.510255 ==============================================================
2225 11:07:35.513913 GAT_TRACK_EN = 1
2226 11:07:35.517052 RX_GATING_MODE = 2
2227 11:07:35.520812 RX_GATING_TRACK_MODE = 2
2228 11:07:35.523649 SELPH_MODE = 1
2229 11:07:35.527052 PICG_EARLY_EN = 1
2230 11:07:35.531013 VALID_LAT_VALUE = 1
2231 11:07:35.534280 ==============================================================
2232 11:07:35.537742 Enter into Gating configuration >>>>
2233 11:07:35.540660 Exit from Gating configuration <<<<
2234 11:07:35.544089 Enter into DVFS_PRE_config >>>>>
2235 11:07:35.557582 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 11:07:35.558141 Exit from DVFS_PRE_config <<<<<
2237 11:07:35.561171 Enter into PICG configuration >>>>
2238 11:07:35.564422 Exit from PICG configuration <<<<
2239 11:07:35.567678 [RX_INPUT] configuration >>>>>
2240 11:07:35.571102 [RX_INPUT] configuration <<<<<
2241 11:07:35.577456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 11:07:35.581050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 11:07:35.588056 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 11:07:35.595195 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 11:07:35.601355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 11:07:35.608398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 11:07:35.611816 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 11:07:35.615377 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 11:07:35.618806 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 11:07:35.621592 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 11:07:35.628570 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 11:07:35.631712 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 11:07:35.635803 ===================================
2254 11:07:35.638191 LPDDR4 DRAM CONFIGURATION
2255 11:07:35.641533 ===================================
2256 11:07:35.641928 EX_ROW_EN[0] = 0x0
2257 11:07:35.645236 EX_ROW_EN[1] = 0x0
2258 11:07:35.645631 LP4Y_EN = 0x0
2259 11:07:35.648246 WORK_FSP = 0x0
2260 11:07:35.648766 WL = 0x4
2261 11:07:35.652025 RL = 0x4
2262 11:07:35.652583 BL = 0x2
2263 11:07:35.655195 RPST = 0x0
2264 11:07:35.655584 RD_PRE = 0x0
2265 11:07:35.658656 WR_PRE = 0x1
2266 11:07:35.659223 WR_PST = 0x0
2267 11:07:35.661758 DBI_WR = 0x0
2268 11:07:35.662146 DBI_RD = 0x0
2269 11:07:35.665349 OTF = 0x1
2270 11:07:35.668673 ===================================
2271 11:07:35.671695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 11:07:35.675315 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 11:07:35.682117 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 11:07:35.685657 ===================================
2275 11:07:35.686193 LPDDR4 DRAM CONFIGURATION
2276 11:07:35.688754 ===================================
2277 11:07:35.691738 EX_ROW_EN[0] = 0x10
2278 11:07:35.695706 EX_ROW_EN[1] = 0x0
2279 11:07:35.696149 LP4Y_EN = 0x0
2280 11:07:35.698650 WORK_FSP = 0x0
2281 11:07:35.699033 WL = 0x4
2282 11:07:35.701981 RL = 0x4
2283 11:07:35.702611 BL = 0x2
2284 11:07:35.705727 RPST = 0x0
2285 11:07:35.706274 RD_PRE = 0x0
2286 11:07:35.708540 WR_PRE = 0x1
2287 11:07:35.709054 WR_PST = 0x0
2288 11:07:35.712032 DBI_WR = 0x0
2289 11:07:35.712421 DBI_RD = 0x0
2290 11:07:35.715169 OTF = 0x1
2291 11:07:35.718816 ===================================
2292 11:07:35.725354 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 11:07:35.725800 ==
2294 11:07:35.728831 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 11:07:35.732264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 11:07:35.732657 ==
2297 11:07:35.735489 [Duty_Offset_Calibration]
2298 11:07:35.735881 B0:2 B1:-1 CA:1
2299 11:07:35.736194
2300 11:07:35.738711 [DutyScan_Calibration_Flow] k_type=0
2301 11:07:35.747692
2302 11:07:35.748079 ==CLK 0==
2303 11:07:35.750951 Final CLK duty delay cell = -4
2304 11:07:35.754621 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2305 11:07:35.757972 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2306 11:07:35.761198 [-4] AVG Duty = 4953%(X100)
2307 11:07:35.761862
2308 11:07:35.764690 CH0 CLK Duty spec in!! Max-Min= 156%
2309 11:07:35.767770 [DutyScan_Calibration_Flow] ====Done====
2310 11:07:35.768044
2311 11:07:35.770861 [DutyScan_Calibration_Flow] k_type=1
2312 11:07:35.786421
2313 11:07:35.786588 ==DQS 0 ==
2314 11:07:35.789494 Final DQS duty delay cell = 0
2315 11:07:35.793018 [0] MAX Duty = 5125%(X100), DQS PI = 48
2316 11:07:35.796763 [0] MIN Duty = 5000%(X100), DQS PI = 12
2317 11:07:35.796978 [0] AVG Duty = 5062%(X100)
2318 11:07:35.800000
2319 11:07:35.800165 ==DQS 1 ==
2320 11:07:35.802973 Final DQS duty delay cell = -4
2321 11:07:35.806672 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2322 11:07:35.809799 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2323 11:07:35.813358 [-4] AVG Duty = 5062%(X100)
2324 11:07:35.813549
2325 11:07:35.816598 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2326 11:07:35.816672
2327 11:07:35.819770 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2328 11:07:35.823826 [DutyScan_Calibration_Flow] ====Done====
2329 11:07:35.823900
2330 11:07:35.826695 [DutyScan_Calibration_Flow] k_type=3
2331 11:07:35.843617
2332 11:07:35.843749 ==DQM 0 ==
2333 11:07:35.846626 Final DQM duty delay cell = 0
2334 11:07:35.850223 [0] MAX Duty = 5000%(X100), DQS PI = 54
2335 11:07:35.853602 [0] MIN Duty = 4907%(X100), DQS PI = 2
2336 11:07:35.853758 [0] AVG Duty = 4953%(X100)
2337 11:07:35.853901
2338 11:07:35.856722 ==DQM 1 ==
2339 11:07:35.860626 Final DQM duty delay cell = 0
2340 11:07:35.863476 [0] MAX Duty = 5124%(X100), DQS PI = 32
2341 11:07:35.866923 [0] MIN Duty = 4969%(X100), DQS PI = 10
2342 11:07:35.867145 [0] AVG Duty = 5046%(X100)
2343 11:07:35.867360
2344 11:07:35.870059 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2345 11:07:35.873261
2346 11:07:35.876937 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2347 11:07:35.880024 [DutyScan_Calibration_Flow] ====Done====
2348 11:07:35.880372
2349 11:07:35.883674 [DutyScan_Calibration_Flow] k_type=2
2350 11:07:35.899270
2351 11:07:35.899805 ==DQ 0 ==
2352 11:07:35.902822 Final DQ duty delay cell = -4
2353 11:07:35.906118 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2354 11:07:35.908977 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2355 11:07:35.912408 [-4] AVG Duty = 4953%(X100)
2356 11:07:35.912924
2357 11:07:35.913276 ==DQ 1 ==
2358 11:07:35.916313 Final DQ duty delay cell = 0
2359 11:07:35.919205 [0] MAX Duty = 5031%(X100), DQS PI = 26
2360 11:07:35.923038 [0] MIN Duty = 4907%(X100), DQS PI = 46
2361 11:07:35.923419 [0] AVG Duty = 4969%(X100)
2362 11:07:35.923785
2363 11:07:35.929362 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2364 11:07:35.929746
2365 11:07:35.932590 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2366 11:07:35.935982 [DutyScan_Calibration_Flow] ====Done====
2367 11:07:35.936402 ==
2368 11:07:35.939478 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 11:07:35.942939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 11:07:35.943328 ==
2371 11:07:35.946568 [Duty_Offset_Calibration]
2372 11:07:35.947009 B0:1 B1:1 CA:2
2373 11:07:35.947311
2374 11:07:35.949260 [DutyScan_Calibration_Flow] k_type=0
2375 11:07:35.959603
2376 11:07:35.959978 ==CLK 0==
2377 11:07:35.962854 Final CLK duty delay cell = 0
2378 11:07:35.967067 [0] MAX Duty = 5125%(X100), DQS PI = 24
2379 11:07:35.969611 [0] MIN Duty = 4938%(X100), DQS PI = 46
2380 11:07:35.969998 [0] AVG Duty = 5031%(X100)
2381 11:07:35.973035
2382 11:07:35.973625 CH1 CLK Duty spec in!! Max-Min= 187%
2383 11:07:35.979681 [DutyScan_Calibration_Flow] ====Done====
2384 11:07:35.980068
2385 11:07:35.982777 [DutyScan_Calibration_Flow] k_type=1
2386 11:07:35.999600
2387 11:07:36.000187 ==DQS 0 ==
2388 11:07:36.002640 Final DQS duty delay cell = 0
2389 11:07:36.005250 [0] MAX Duty = 5031%(X100), DQS PI = 18
2390 11:07:36.009211 [0] MIN Duty = 4813%(X100), DQS PI = 50
2391 11:07:36.009604 [0] AVG Duty = 4922%(X100)
2392 11:07:36.012185
2393 11:07:36.012566 ==DQS 1 ==
2394 11:07:36.015780 Final DQS duty delay cell = 0
2395 11:07:36.018698 [0] MAX Duty = 5062%(X100), DQS PI = 36
2396 11:07:36.021998 [0] MIN Duty = 4907%(X100), DQS PI = 16
2397 11:07:36.022377 [0] AVG Duty = 4984%(X100)
2398 11:07:36.025681
2399 11:07:36.028685 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2400 11:07:36.029067
2401 11:07:36.032451 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2402 11:07:36.035537 [DutyScan_Calibration_Flow] ====Done====
2403 11:07:36.035957
2404 11:07:36.039659 [DutyScan_Calibration_Flow] k_type=3
2405 11:07:36.055625
2406 11:07:36.056011 ==DQM 0 ==
2407 11:07:36.059003 Final DQM duty delay cell = 0
2408 11:07:36.062002 [0] MAX Duty = 5093%(X100), DQS PI = 18
2409 11:07:36.065610 [0] MIN Duty = 4907%(X100), DQS PI = 48
2410 11:07:36.066003 [0] AVG Duty = 5000%(X100)
2411 11:07:36.068749
2412 11:07:36.069160 ==DQM 1 ==
2413 11:07:36.072192 Final DQM duty delay cell = 0
2414 11:07:36.076115 [0] MAX Duty = 5125%(X100), DQS PI = 0
2415 11:07:36.079476 [0] MIN Duty = 4969%(X100), DQS PI = 4
2416 11:07:36.079869 [0] AVG Duty = 5047%(X100)
2417 11:07:36.080176
2418 11:07:36.082367 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2419 11:07:36.086113
2420 11:07:36.088820 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2421 11:07:36.092003 [DutyScan_Calibration_Flow] ====Done====
2422 11:07:36.092388
2423 11:07:36.095441 [DutyScan_Calibration_Flow] k_type=2
2424 11:07:36.111722
2425 11:07:36.112266 ==DQ 0 ==
2426 11:07:36.114885 Final DQ duty delay cell = 0
2427 11:07:36.118699 [0] MAX Duty = 5093%(X100), DQS PI = 16
2428 11:07:36.121930 [0] MIN Duty = 4907%(X100), DQS PI = 50
2429 11:07:36.122319 [0] AVG Duty = 5000%(X100)
2430 11:07:36.122618
2431 11:07:36.125553 ==DQ 1 ==
2432 11:07:36.128883 Final DQ duty delay cell = 0
2433 11:07:36.132500 [0] MAX Duty = 5093%(X100), DQS PI = 10
2434 11:07:36.135131 [0] MIN Duty = 5000%(X100), DQS PI = 2
2435 11:07:36.135518 [0] AVG Duty = 5046%(X100)
2436 11:07:36.135819
2437 11:07:36.138791 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2438 11:07:36.139178
2439 11:07:36.142249 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2440 11:07:36.145452 [DutyScan_Calibration_Flow] ====Done====
2441 11:07:36.150557 nWR fixed to 30
2442 11:07:36.154111 [ModeRegInit_LP4] CH0 RK0
2443 11:07:36.154636 [ModeRegInit_LP4] CH0 RK1
2444 11:07:36.157393 [ModeRegInit_LP4] CH1 RK0
2445 11:07:36.160553 [ModeRegInit_LP4] CH1 RK1
2446 11:07:36.161044 match AC timing 7
2447 11:07:36.167513 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 11:07:36.171269 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 11:07:36.174193 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 11:07:36.181253 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 11:07:36.184207 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 11:07:36.184702 ==
2453 11:07:36.187655 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 11:07:36.191077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 11:07:36.191576 ==
2456 11:07:36.197722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 11:07:36.204016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2458 11:07:36.211950 [CA 0] Center 40 (10~71) winsize 62
2459 11:07:36.214904 [CA 1] Center 39 (9~70) winsize 62
2460 11:07:36.218062 [CA 2] Center 36 (6~67) winsize 62
2461 11:07:36.221693 [CA 3] Center 36 (6~66) winsize 61
2462 11:07:36.225304 [CA 4] Center 34 (4~65) winsize 62
2463 11:07:36.228423 [CA 5] Center 34 (4~64) winsize 61
2464 11:07:36.228813
2465 11:07:36.231685 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2466 11:07:36.232074
2467 11:07:36.235116 [CATrainingPosCal] consider 1 rank data
2468 11:07:36.238537 u2DelayCellTimex100 = 270/100 ps
2469 11:07:36.241648 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2470 11:07:36.245405 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2471 11:07:36.252070 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2472 11:07:36.255082 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2473 11:07:36.258766 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2474 11:07:36.262018 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2475 11:07:36.262405
2476 11:07:36.265090 CA PerBit enable=1, Macro0, CA PI delay=34
2477 11:07:36.265710
2478 11:07:36.268624 [CBTSetCACLKResult] CA Dly = 34
2479 11:07:36.269011 CS Dly: 7 (0~38)
2480 11:07:36.269405 ==
2481 11:07:36.272265 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 11:07:36.278872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 11:07:36.279308 ==
2484 11:07:36.281938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 11:07:36.288888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2486 11:07:36.297491 [CA 0] Center 39 (9~70) winsize 62
2487 11:07:36.300797 [CA 1] Center 39 (9~70) winsize 62
2488 11:07:36.304356 [CA 2] Center 36 (6~67) winsize 62
2489 11:07:36.307799 [CA 3] Center 36 (5~67) winsize 63
2490 11:07:36.311183 [CA 4] Center 34 (4~65) winsize 62
2491 11:07:36.314942 [CA 5] Center 34 (4~64) winsize 61
2492 11:07:36.315328
2493 11:07:36.318038 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2494 11:07:36.318425
2495 11:07:36.321270 [CATrainingPosCal] consider 2 rank data
2496 11:07:36.324957 u2DelayCellTimex100 = 270/100 ps
2497 11:07:36.327900 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2498 11:07:36.330961 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2499 11:07:36.334369 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2500 11:07:36.340972 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2501 11:07:36.344790 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2502 11:07:36.348289 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2503 11:07:36.348674
2504 11:07:36.351226 CA PerBit enable=1, Macro0, CA PI delay=34
2505 11:07:36.351614
2506 11:07:36.354402 [CBTSetCACLKResult] CA Dly = 34
2507 11:07:36.354791 CS Dly: 8 (0~41)
2508 11:07:36.355092
2509 11:07:36.358225 ----->DramcWriteLeveling(PI) begin...
2510 11:07:36.358616 ==
2511 11:07:36.361165 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 11:07:36.367864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 11:07:36.368250 ==
2514 11:07:36.371299 Write leveling (Byte 0): 30 => 30
2515 11:07:36.374769 Write leveling (Byte 1): 30 => 30
2516 11:07:36.375153 DramcWriteLeveling(PI) end<-----
2517 11:07:36.375453
2518 11:07:36.378475 ==
2519 11:07:36.378859 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 11:07:36.385030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 11:07:36.385473 ==
2522 11:07:36.387993 [Gating] SW mode calibration
2523 11:07:36.394776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 11:07:36.398527 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 11:07:36.405148 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 11:07:36.408576 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2527 11:07:36.412333 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2528 11:07:36.421901 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 11:07:36.422303 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 11:07:36.425191 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:07:36.428559 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 11:07:36.435801 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:07:36.438627 1 0 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2534 11:07:36.441664 1 0 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2535 11:07:36.448670 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 11:07:36.452164 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 11:07:36.455116 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:07:36.461986 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:07:36.465682 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:07:36.468835 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:07:36.471720 1 1 0 | B1->B0 | 2424 2727 | 0 1 | (0 0) (0 0)
2542 11:07:36.478983 1 1 4 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
2543 11:07:36.481802 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 11:07:36.485742 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 11:07:36.492235 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 11:07:36.495134 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:07:36.499093 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:07:36.505479 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:07:36.508962 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2550 11:07:36.512446 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 11:07:36.519093 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:07:36.522359 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:07:36.525580 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:07:36.529060 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:07:36.535530 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:07:36.539270 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:07:36.542248 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:07:36.549014 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:07:36.552622 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:07:36.556119 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:07:36.562364 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:07:36.566023 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:07:36.569427 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:07:36.576133 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 11:07:36.579990 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2566 11:07:36.582793 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2567 11:07:36.586194 Total UI for P1: 0, mck2ui 16
2568 11:07:36.589614 best dqsien dly found for B0: ( 1, 3, 30)
2569 11:07:36.592642 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 11:07:36.596389 Total UI for P1: 0, mck2ui 16
2571 11:07:36.599578 best dqsien dly found for B1: ( 1, 4, 2)
2572 11:07:36.603192 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2573 11:07:36.606610 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2574 11:07:36.607007
2575 11:07:36.613252 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2576 11:07:36.616922 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2577 11:07:36.619882 [Gating] SW calibration Done
2578 11:07:36.620274 ==
2579 11:07:36.623370 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 11:07:36.626878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 11:07:36.627263 ==
2582 11:07:36.627565 RX Vref Scan: 0
2583 11:07:36.627840
2584 11:07:36.630653 RX Vref 0 -> 0, step: 1
2585 11:07:36.631072
2586 11:07:36.633242 RX Delay -40 -> 252, step: 8
2587 11:07:36.637155 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2588 11:07:36.640241 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2589 11:07:36.643371 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2590 11:07:36.650181 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2591 11:07:36.653790 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2592 11:07:36.657642 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2593 11:07:36.660040 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2594 11:07:36.663324 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2595 11:07:36.669931 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2596 11:07:36.674011 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2597 11:07:36.677206 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2598 11:07:36.680344 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2599 11:07:36.683761 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2600 11:07:36.689994 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2601 11:07:36.693513 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2602 11:07:36.696761 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2603 11:07:36.697180 ==
2604 11:07:36.700725 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 11:07:36.703937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 11:07:36.704359 ==
2607 11:07:36.708030 DQS Delay:
2608 11:07:36.708606 DQS0 = 0, DQS1 = 0
2609 11:07:36.709049 DQM Delay:
2610 11:07:36.710501 DQM0 = 115, DQM1 = 107
2611 11:07:36.710892 DQ Delay:
2612 11:07:36.713420 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2613 11:07:36.717434 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2614 11:07:36.720398 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2615 11:07:36.723950 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2616 11:07:36.727367
2617 11:07:36.727760
2618 11:07:36.728154 ==
2619 11:07:36.730564 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 11:07:36.734214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 11:07:36.734614 ==
2622 11:07:36.735011
2623 11:07:36.735380
2624 11:07:36.737653 TX Vref Scan disable
2625 11:07:36.738039 == TX Byte 0 ==
2626 11:07:36.744001 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2627 11:07:36.747618 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2628 11:07:36.748005 == TX Byte 1 ==
2629 11:07:36.750646 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2630 11:07:36.757460 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2631 11:07:36.757847 ==
2632 11:07:36.761479 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 11:07:36.764388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 11:07:36.764776 ==
2635 11:07:36.776582 TX Vref=22, minBit 1, minWin=24, winSum=416
2636 11:07:36.779404 TX Vref=24, minBit 12, minWin=25, winSum=424
2637 11:07:36.783048 TX Vref=26, minBit 7, minWin=25, winSum=427
2638 11:07:36.786146 TX Vref=28, minBit 1, minWin=26, winSum=431
2639 11:07:36.789834 TX Vref=30, minBit 1, minWin=26, winSum=432
2640 11:07:36.793040 TX Vref=32, minBit 0, minWin=26, winSum=434
2641 11:07:36.800058 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 32
2642 11:07:36.800442
2643 11:07:36.802975 Final TX Range 1 Vref 32
2644 11:07:36.803360
2645 11:07:36.803737 ==
2646 11:07:36.806088 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 11:07:36.809667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 11:07:36.810221 ==
2649 11:07:36.810634
2650 11:07:36.811025
2651 11:07:36.812893 TX Vref Scan disable
2652 11:07:36.816310 == TX Byte 0 ==
2653 11:07:36.819987 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2654 11:07:36.822797 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2655 11:07:36.826159 == TX Byte 1 ==
2656 11:07:36.829874 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2657 11:07:36.833752 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2658 11:07:36.834207
2659 11:07:36.836507 [DATLAT]
2660 11:07:36.836914 Freq=1200, CH0 RK0
2661 11:07:36.837260
2662 11:07:36.839973 DATLAT Default: 0xd
2663 11:07:36.840451 0, 0xFFFF, sum = 0
2664 11:07:36.842973 1, 0xFFFF, sum = 0
2665 11:07:36.843386 2, 0xFFFF, sum = 0
2666 11:07:36.846921 3, 0xFFFF, sum = 0
2667 11:07:36.847351 4, 0xFFFF, sum = 0
2668 11:07:36.849773 5, 0xFFFF, sum = 0
2669 11:07:36.850161 6, 0xFFFF, sum = 0
2670 11:07:36.853468 7, 0xFFFF, sum = 0
2671 11:07:36.853888 8, 0xFFFF, sum = 0
2672 11:07:36.856943 9, 0xFFFF, sum = 0
2673 11:07:36.857632 10, 0xFFFF, sum = 0
2674 11:07:36.860068 11, 0xFFFF, sum = 0
2675 11:07:36.860471 12, 0x0, sum = 1
2676 11:07:36.863208 13, 0x0, sum = 2
2677 11:07:36.863653 14, 0x0, sum = 3
2678 11:07:36.867046 15, 0x0, sum = 4
2679 11:07:36.867694 best_step = 13
2680 11:07:36.868274
2681 11:07:36.868669 ==
2682 11:07:36.870001 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:07:36.877029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:07:36.877504 ==
2685 11:07:36.877900 RX Vref Scan: 1
2686 11:07:36.878275
2687 11:07:36.880539 Set Vref Range= 32 -> 127
2688 11:07:36.880933
2689 11:07:36.883783 RX Vref 32 -> 127, step: 1
2690 11:07:36.884179
2691 11:07:36.884571 RX Delay -21 -> 252, step: 4
2692 11:07:36.884940
2693 11:07:36.886859 Set Vref, RX VrefLevel [Byte0]: 32
2694 11:07:36.890047 [Byte1]: 32
2695 11:07:36.894502
2696 11:07:36.894883 Set Vref, RX VrefLevel [Byte0]: 33
2697 11:07:36.897758 [Byte1]: 33
2698 11:07:36.902291
2699 11:07:36.902668 Set Vref, RX VrefLevel [Byte0]: 34
2700 11:07:36.905678 [Byte1]: 34
2701 11:07:36.910386
2702 11:07:36.910780 Set Vref, RX VrefLevel [Byte0]: 35
2703 11:07:36.913841 [Byte1]: 35
2704 11:07:36.918379
2705 11:07:36.918764 Set Vref, RX VrefLevel [Byte0]: 36
2706 11:07:36.922011 [Byte1]: 36
2707 11:07:36.926168
2708 11:07:36.926617 Set Vref, RX VrefLevel [Byte0]: 37
2709 11:07:36.929641 [Byte1]: 37
2710 11:07:36.934404
2711 11:07:36.934778 Set Vref, RX VrefLevel [Byte0]: 38
2712 11:07:36.936965 [Byte1]: 38
2713 11:07:36.941933
2714 11:07:36.942499 Set Vref, RX VrefLevel [Byte0]: 39
2715 11:07:36.945207 [Byte1]: 39
2716 11:07:36.949707
2717 11:07:36.950100 Set Vref, RX VrefLevel [Byte0]: 40
2718 11:07:36.953078 [Byte1]: 40
2719 11:07:36.958034
2720 11:07:36.958619 Set Vref, RX VrefLevel [Byte0]: 41
2721 11:07:36.961094 [Byte1]: 41
2722 11:07:36.965394
2723 11:07:36.965897 Set Vref, RX VrefLevel [Byte0]: 42
2724 11:07:36.968784 [Byte1]: 42
2725 11:07:36.973708
2726 11:07:36.974099 Set Vref, RX VrefLevel [Byte0]: 43
2727 11:07:36.976975 [Byte1]: 43
2728 11:07:36.981645
2729 11:07:36.982025 Set Vref, RX VrefLevel [Byte0]: 44
2730 11:07:36.984816 [Byte1]: 44
2731 11:07:36.989671
2732 11:07:36.990051 Set Vref, RX VrefLevel [Byte0]: 45
2733 11:07:36.992740 [Byte1]: 45
2734 11:07:36.997633
2735 11:07:36.998013 Set Vref, RX VrefLevel [Byte0]: 46
2736 11:07:37.000550 [Byte1]: 46
2737 11:07:37.005385
2738 11:07:37.005768 Set Vref, RX VrefLevel [Byte0]: 47
2739 11:07:37.008986 [Byte1]: 47
2740 11:07:37.013438
2741 11:07:37.013819 Set Vref, RX VrefLevel [Byte0]: 48
2742 11:07:37.016968 [Byte1]: 48
2743 11:07:37.021315
2744 11:07:37.021696 Set Vref, RX VrefLevel [Byte0]: 49
2745 11:07:37.024565 [Byte1]: 49
2746 11:07:37.029010
2747 11:07:37.029483 Set Vref, RX VrefLevel [Byte0]: 50
2748 11:07:37.032435 [Byte1]: 50
2749 11:07:37.037154
2750 11:07:37.037538 Set Vref, RX VrefLevel [Byte0]: 51
2751 11:07:37.040368 [Byte1]: 51
2752 11:07:37.045004
2753 11:07:37.045462 Set Vref, RX VrefLevel [Byte0]: 52
2754 11:07:37.048576 [Byte1]: 52
2755 11:07:37.053095
2756 11:07:37.053511 Set Vref, RX VrefLevel [Byte0]: 53
2757 11:07:37.056526 [Byte1]: 53
2758 11:07:37.060727
2759 11:07:37.061209 Set Vref, RX VrefLevel [Byte0]: 54
2760 11:07:37.064400 [Byte1]: 54
2761 11:07:37.068913
2762 11:07:37.069408 Set Vref, RX VrefLevel [Byte0]: 55
2763 11:07:37.072232 [Byte1]: 55
2764 11:07:37.076760
2765 11:07:37.077171 Set Vref, RX VrefLevel [Byte0]: 56
2766 11:07:37.080050 [Byte1]: 56
2767 11:07:37.084716
2768 11:07:37.085108 Set Vref, RX VrefLevel [Byte0]: 57
2769 11:07:37.088128 [Byte1]: 57
2770 11:07:37.092288
2771 11:07:37.092866 Set Vref, RX VrefLevel [Byte0]: 58
2772 11:07:37.095779 [Byte1]: 58
2773 11:07:37.100542
2774 11:07:37.100921 Set Vref, RX VrefLevel [Byte0]: 59
2775 11:07:37.103602 [Byte1]: 59
2776 11:07:37.108331
2777 11:07:37.108884 Set Vref, RX VrefLevel [Byte0]: 60
2778 11:07:37.111724 [Byte1]: 60
2779 11:07:37.116248
2780 11:07:37.116626 Set Vref, RX VrefLevel [Byte0]: 61
2781 11:07:37.120116 [Byte1]: 61
2782 11:07:37.123893
2783 11:07:37.124278 Set Vref, RX VrefLevel [Byte0]: 62
2784 11:07:37.127398 [Byte1]: 62
2785 11:07:37.132290
2786 11:07:37.132669 Set Vref, RX VrefLevel [Byte0]: 63
2787 11:07:37.135680 [Byte1]: 63
2788 11:07:37.140122
2789 11:07:37.140534 Set Vref, RX VrefLevel [Byte0]: 64
2790 11:07:37.143803 [Byte1]: 64
2791 11:07:37.148820
2792 11:07:37.149232 Set Vref, RX VrefLevel [Byte0]: 65
2793 11:07:37.151679 [Byte1]: 65
2794 11:07:37.155891
2795 11:07:37.156345 Set Vref, RX VrefLevel [Byte0]: 66
2796 11:07:37.159102 [Byte1]: 66
2797 11:07:37.163988
2798 11:07:37.164369 Set Vref, RX VrefLevel [Byte0]: 67
2799 11:07:37.166906 [Byte1]: 67
2800 11:07:37.171582
2801 11:07:37.171984 Set Vref, RX VrefLevel [Byte0]: 68
2802 11:07:37.175061 [Byte1]: 68
2803 11:07:37.179554
2804 11:07:37.179949 Final RX Vref Byte 0 = 52 to rank0
2805 11:07:37.183279 Final RX Vref Byte 1 = 51 to rank0
2806 11:07:37.186273 Final RX Vref Byte 0 = 52 to rank1
2807 11:07:37.190352 Final RX Vref Byte 1 = 51 to rank1==
2808 11:07:37.193521 Dram Type= 6, Freq= 0, CH_0, rank 0
2809 11:07:37.196946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2810 11:07:37.199991 ==
2811 11:07:37.200455 DQS Delay:
2812 11:07:37.200760 DQS0 = 0, DQS1 = 0
2813 11:07:37.203005 DQM Delay:
2814 11:07:37.203425 DQM0 = 114, DQM1 = 104
2815 11:07:37.206678 DQ Delay:
2816 11:07:37.209771 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =114
2817 11:07:37.213961 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =120
2818 11:07:37.216586 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2819 11:07:37.219798 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2820 11:07:37.220190
2821 11:07:37.220580
2822 11:07:37.226993 [DQSOSCAuto] RK0, (LSB)MR18= 0xfded, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
2823 11:07:37.230394 CH0 RK0: MR19=303, MR18=FDED
2824 11:07:37.236940 CH0_RK0: MR19=0x303, MR18=0xFDED, DQSOSC=411, MR23=63, INC=38, DEC=25
2825 11:07:37.237376
2826 11:07:37.239859 ----->DramcWriteLeveling(PI) begin...
2827 11:07:37.240255 ==
2828 11:07:37.243347 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 11:07:37.247046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 11:07:37.247428 ==
2831 11:07:37.249872 Write leveling (Byte 0): 32 => 32
2832 11:07:37.253273 Write leveling (Byte 1): 29 => 29
2833 11:07:37.256675 DramcWriteLeveling(PI) end<-----
2834 11:07:37.257055
2835 11:07:37.257408 ==
2836 11:07:37.259952 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 11:07:37.262985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 11:07:37.266754 ==
2839 11:07:37.267190 [Gating] SW mode calibration
2840 11:07:37.273305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2841 11:07:37.280152 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2842 11:07:37.283983 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2843 11:07:37.289705 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2844 11:07:37.293165 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 11:07:37.296432 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 11:07:37.303816 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 11:07:37.307500 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 11:07:37.309902 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2849 11:07:37.316921 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2850 11:07:37.320295 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
2851 11:07:37.323991 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2852 11:07:37.326898 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 11:07:37.333836 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 11:07:37.337014 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 11:07:37.340205 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 11:07:37.346945 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
2857 11:07:37.350312 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2858 11:07:37.353523 1 1 0 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
2859 11:07:37.360647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 11:07:37.364271 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 11:07:37.367225 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 11:07:37.373907 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 11:07:37.377551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 11:07:37.380521 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 11:07:37.384041 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2866 11:07:37.391402 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2867 11:07:37.394575 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:07:37.397612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:07:37.404335 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:07:37.407373 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:07:37.410940 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:07:37.417579 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:07:37.421111 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:07:37.424563 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:07:37.431122 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:07:37.434510 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:07:37.437563 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:07:37.444055 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:07:37.447634 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:07:37.450836 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2881 11:07:37.454228 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2882 11:07:37.461387 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2883 11:07:37.464386 Total UI for P1: 0, mck2ui 16
2884 11:07:37.467935 best dqsien dly found for B0: ( 1, 3, 26)
2885 11:07:37.472038 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 11:07:37.475143 Total UI for P1: 0, mck2ui 16
2887 11:07:37.478008 best dqsien dly found for B1: ( 1, 4, 0)
2888 11:07:37.481176 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2889 11:07:37.484293 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2890 11:07:37.484676
2891 11:07:37.487867 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2892 11:07:37.491187 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2893 11:07:37.494968 [Gating] SW calibration Done
2894 11:07:37.495352 ==
2895 11:07:37.497916 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 11:07:37.501061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 11:07:37.501598 ==
2898 11:07:37.505426 RX Vref Scan: 0
2899 11:07:37.505847
2900 11:07:37.508349 RX Vref 0 -> 0, step: 1
2901 11:07:37.508730
2902 11:07:37.509027 RX Delay -40 -> 252, step: 8
2903 11:07:37.514473 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2904 11:07:37.518527 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2905 11:07:37.521091 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2906 11:07:37.524500 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2907 11:07:37.527679 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2908 11:07:37.534713 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2909 11:07:37.537844 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2910 11:07:37.541408 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2911 11:07:37.544615 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2912 11:07:37.547840 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2913 11:07:37.554265 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2914 11:07:37.558029 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2915 11:07:37.561065 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2916 11:07:37.564327 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2917 11:07:37.567758 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2918 11:07:37.574557 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2919 11:07:37.574941 ==
2920 11:07:37.577570 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 11:07:37.581178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 11:07:37.581568 ==
2923 11:07:37.581870 DQS Delay:
2924 11:07:37.584395 DQS0 = 0, DQS1 = 0
2925 11:07:37.584966 DQM Delay:
2926 11:07:37.587473 DQM0 = 115, DQM1 = 105
2927 11:07:37.587877 DQ Delay:
2928 11:07:37.591117 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2929 11:07:37.594384 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2930 11:07:37.598016 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2931 11:07:37.600836 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2932 11:07:37.601277
2933 11:07:37.601585
2934 11:07:37.601862 ==
2935 11:07:37.604216 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 11:07:37.610797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 11:07:37.611185 ==
2938 11:07:37.611598
2939 11:07:37.611973
2940 11:07:37.614726 TX Vref Scan disable
2941 11:07:37.615112 == TX Byte 0 ==
2942 11:07:37.617749 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2943 11:07:37.624537 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2944 11:07:37.624926 == TX Byte 1 ==
2945 11:07:37.627623 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2946 11:07:37.633988 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2947 11:07:37.634373 ==
2948 11:07:37.637453 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 11:07:37.641205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 11:07:37.641526 ==
2951 11:07:37.652644 TX Vref=22, minBit 4, minWin=25, winSum=423
2952 11:07:37.655988 TX Vref=24, minBit 12, minWin=25, winSum=425
2953 11:07:37.659063 TX Vref=26, minBit 3, minWin=26, winSum=432
2954 11:07:37.662682 TX Vref=28, minBit 3, minWin=26, winSum=437
2955 11:07:37.666146 TX Vref=30, minBit 3, minWin=26, winSum=434
2956 11:07:37.672532 TX Vref=32, minBit 12, minWin=26, winSum=441
2957 11:07:37.675808 [TxChooseVref] Worse bit 12, Min win 26, Win sum 441, Final Vref 32
2958 11:07:37.675930
2959 11:07:37.678995 Final TX Range 1 Vref 32
2960 11:07:37.679134
2961 11:07:37.679234 ==
2962 11:07:37.682616 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 11:07:37.685870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 11:07:37.686015 ==
2965 11:07:37.686122
2966 11:07:37.689736
2967 11:07:37.689873 TX Vref Scan disable
2968 11:07:37.692545 == TX Byte 0 ==
2969 11:07:37.696058 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2970 11:07:37.700004 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2971 11:07:37.702781 == TX Byte 1 ==
2972 11:07:37.706341 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2973 11:07:37.709746 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2974 11:07:37.709831
2975 11:07:37.712537 [DATLAT]
2976 11:07:37.712628 Freq=1200, CH0 RK1
2977 11:07:37.712700
2978 11:07:37.716389 DATLAT Default: 0xd
2979 11:07:37.716584 0, 0xFFFF, sum = 0
2980 11:07:37.719456 1, 0xFFFF, sum = 0
2981 11:07:37.719619 2, 0xFFFF, sum = 0
2982 11:07:37.722907 3, 0xFFFF, sum = 0
2983 11:07:37.723053 4, 0xFFFF, sum = 0
2984 11:07:37.726265 5, 0xFFFF, sum = 0
2985 11:07:37.726421 6, 0xFFFF, sum = 0
2986 11:07:37.729432 7, 0xFFFF, sum = 0
2987 11:07:37.732972 8, 0xFFFF, sum = 0
2988 11:07:37.733129 9, 0xFFFF, sum = 0
2989 11:07:37.735990 10, 0xFFFF, sum = 0
2990 11:07:37.736136 11, 0xFFFF, sum = 0
2991 11:07:37.739254 12, 0x0, sum = 1
2992 11:07:37.739407 13, 0x0, sum = 2
2993 11:07:37.742825 14, 0x0, sum = 3
2994 11:07:37.742969 15, 0x0, sum = 4
2995 11:07:37.743090 best_step = 13
2996 11:07:37.743206
2997 11:07:37.746546 ==
2998 11:07:37.749469 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 11:07:37.753113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 11:07:37.753236 ==
3001 11:07:37.753342 RX Vref Scan: 0
3002 11:07:37.753442
3003 11:07:37.756080 RX Vref 0 -> 0, step: 1
3004 11:07:37.756193
3005 11:07:37.759436 RX Delay -21 -> 252, step: 4
3006 11:07:37.762502 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3007 11:07:37.768944 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3008 11:07:37.772498 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3009 11:07:37.775774 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3010 11:07:37.779429 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3011 11:07:37.782205 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3012 11:07:37.789194 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3013 11:07:37.792432 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3014 11:07:37.795638 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3015 11:07:37.799043 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3016 11:07:37.802643 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3017 11:07:37.806121 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3018 11:07:37.812596 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3019 11:07:37.815805 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3020 11:07:37.818850 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3021 11:07:37.823342 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3022 11:07:37.823424 ==
3023 11:07:37.825985 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 11:07:37.832149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 11:07:37.832239 ==
3026 11:07:37.832301 DQS Delay:
3027 11:07:37.835733 DQS0 = 0, DQS1 = 0
3028 11:07:37.835856 DQM Delay:
3029 11:07:37.835968 DQM0 = 113, DQM1 = 104
3030 11:07:37.839230 DQ Delay:
3031 11:07:37.842531 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3032 11:07:37.846099 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3033 11:07:37.849313 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3034 11:07:37.852625 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3035 11:07:37.852737
3036 11:07:37.852834
3037 11:07:37.859039 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3038 11:07:37.862594 CH0 RK1: MR19=403, MR18=5F7
3039 11:07:37.869303 CH0_RK1: MR19=0x403, MR18=0x5F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3040 11:07:37.872560 [RxdqsGatingPostProcess] freq 1200
3041 11:07:37.878985 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3042 11:07:37.882383 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 11:07:37.882459 best DQS1 dly(2T, 0.5T) = (0, 12)
3044 11:07:37.886048 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 11:07:37.889109 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3046 11:07:37.892763 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 11:07:37.895792 best DQS1 dly(2T, 0.5T) = (0, 12)
3048 11:07:37.899217 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 11:07:37.902671 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3050 11:07:37.905792 Pre-setting of DQS Precalculation
3051 11:07:37.909940 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3052 11:07:37.913360 ==
3053 11:07:37.913462 Dram Type= 6, Freq= 0, CH_1, rank 0
3054 11:07:37.919161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 11:07:37.919273 ==
3056 11:07:37.923402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3057 11:07:37.929384 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3058 11:07:37.938784 [CA 0] Center 38 (9~68) winsize 60
3059 11:07:37.941557 [CA 1] Center 38 (8~68) winsize 61
3060 11:07:37.945391 [CA 2] Center 35 (5~65) winsize 61
3061 11:07:37.948640 [CA 3] Center 34 (4~65) winsize 62
3062 11:07:37.951527 [CA 4] Center 34 (4~65) winsize 62
3063 11:07:37.955143 [CA 5] Center 34 (4~64) winsize 61
3064 11:07:37.955499
3065 11:07:37.958564 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3066 11:07:37.958952
3067 11:07:37.961997 [CATrainingPosCal] consider 1 rank data
3068 11:07:37.964867 u2DelayCellTimex100 = 270/100 ps
3069 11:07:37.968299 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3070 11:07:37.975533 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3071 11:07:37.978572 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3072 11:07:37.982149 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3073 11:07:37.984793 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3074 11:07:37.988844 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3075 11:07:37.989279
3076 11:07:37.991786 CA PerBit enable=1, Macro0, CA PI delay=34
3077 11:07:37.992163
3078 11:07:37.994688 [CBTSetCACLKResult] CA Dly = 34
3079 11:07:37.995039 CS Dly: 6 (0~37)
3080 11:07:37.998483 ==
3081 11:07:38.001918 Dram Type= 6, Freq= 0, CH_1, rank 1
3082 11:07:38.005145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:07:38.005338 ==
3084 11:07:38.008243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3085 11:07:38.014525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3086 11:07:38.023932 [CA 0] Center 38 (8~68) winsize 61
3087 11:07:38.027036 [CA 1] Center 38 (8~68) winsize 61
3088 11:07:38.030363 [CA 2] Center 34 (4~65) winsize 62
3089 11:07:38.034054 [CA 3] Center 34 (4~65) winsize 62
3090 11:07:38.037147 [CA 4] Center 34 (4~65) winsize 62
3091 11:07:38.041292 [CA 5] Center 34 (4~64) winsize 61
3092 11:07:38.041369
3093 11:07:38.043798 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3094 11:07:38.043875
3095 11:07:38.047207 [CATrainingPosCal] consider 2 rank data
3096 11:07:38.050709 u2DelayCellTimex100 = 270/100 ps
3097 11:07:38.054165 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3098 11:07:38.060462 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3099 11:07:38.063509 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3100 11:07:38.067376 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3101 11:07:38.070407 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3102 11:07:38.073588 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3103 11:07:38.073684
3104 11:07:38.076849 CA PerBit enable=1, Macro0, CA PI delay=34
3105 11:07:38.076975
3106 11:07:38.080774 [CBTSetCACLKResult] CA Dly = 34
3107 11:07:38.080871 CS Dly: 7 (0~40)
3108 11:07:38.080946
3109 11:07:38.084121 ----->DramcWriteLeveling(PI) begin...
3110 11:07:38.087078 ==
3111 11:07:38.090324 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 11:07:38.093830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 11:07:38.093954 ==
3114 11:07:38.097272 Write leveling (Byte 0): 27 => 27
3115 11:07:38.100509 Write leveling (Byte 1): 27 => 27
3116 11:07:38.103894 DramcWriteLeveling(PI) end<-----
3117 11:07:38.104056
3118 11:07:38.104185 ==
3119 11:07:38.107408 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 11:07:38.110438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 11:07:38.110640 ==
3122 11:07:38.114061 [Gating] SW mode calibration
3123 11:07:38.120497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3124 11:07:38.124270 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3125 11:07:38.130747 0 15 0 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
3126 11:07:38.134193 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 11:07:38.137396 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 11:07:38.144018 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 11:07:38.147525 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 11:07:38.150649 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 11:07:38.158173 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 11:07:38.161007 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3133 11:07:38.163973 1 0 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3134 11:07:38.171282 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 11:07:38.174350 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 11:07:38.177654 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 11:07:38.184034 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 11:07:38.187236 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 11:07:38.191384 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 11:07:38.198059 1 0 28 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
3141 11:07:38.200855 1 1 0 | B1->B0 | 4141 3232 | 0 0 | (0 0) (0 0)
3142 11:07:38.204409 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 11:07:38.211036 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 11:07:38.214380 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 11:07:38.217222 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 11:07:38.220817 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 11:07:38.227815 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 11:07:38.231287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 11:07:38.234188 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3150 11:07:38.241058 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:07:38.243984 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:07:38.247371 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:07:38.254544 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:07:38.257723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:07:38.260757 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:07:38.267533 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:07:38.271147 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:07:38.274204 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:07:38.280741 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:07:38.284075 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:07:38.287738 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:07:38.294286 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:07:38.298015 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:07:38.300691 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3165 11:07:38.304031 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 11:07:38.308434 Total UI for P1: 0, mck2ui 16
3167 11:07:38.311249 best dqsien dly found for B0: ( 1, 3, 28)
3168 11:07:38.314266 Total UI for P1: 0, mck2ui 16
3169 11:07:38.317389 best dqsien dly found for B1: ( 1, 3, 30)
3170 11:07:38.321324 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3171 11:07:38.324124 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3172 11:07:38.328417
3173 11:07:38.330934 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3174 11:07:38.334436 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3175 11:07:38.337887 [Gating] SW calibration Done
3176 11:07:38.338424 ==
3177 11:07:38.341549 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 11:07:38.344863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 11:07:38.345410 ==
3180 11:07:38.345770 RX Vref Scan: 0
3181 11:07:38.346055
3182 11:07:38.348071 RX Vref 0 -> 0, step: 1
3183 11:07:38.348599
3184 11:07:38.350940 RX Delay -40 -> 252, step: 8
3185 11:07:38.355012 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3186 11:07:38.357913 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3187 11:07:38.364480 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3188 11:07:38.367968 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3189 11:07:38.371577 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3190 11:07:38.374309 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3191 11:07:38.378279 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3192 11:07:38.381409 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3193 11:07:38.388110 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3194 11:07:38.391081 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3195 11:07:38.394398 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3196 11:07:38.397885 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3197 11:07:38.401469 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3198 11:07:38.408047 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3199 11:07:38.411345 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3200 11:07:38.414523 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3201 11:07:38.414913 ==
3202 11:07:38.417735 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 11:07:38.421844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 11:07:38.422238 ==
3205 11:07:38.424587 DQS Delay:
3206 11:07:38.424977 DQS0 = 0, DQS1 = 0
3207 11:07:38.427929 DQM Delay:
3208 11:07:38.428318 DQM0 = 115, DQM1 = 108
3209 11:07:38.428620 DQ Delay:
3210 11:07:38.431491 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3211 11:07:38.434785 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3212 11:07:38.441371 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3213 11:07:38.445164 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3214 11:07:38.445597
3215 11:07:38.445939
3216 11:07:38.446399 ==
3217 11:07:38.448151 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 11:07:38.451633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 11:07:38.452022 ==
3220 11:07:38.452324
3221 11:07:38.452599
3222 11:07:38.454739 TX Vref Scan disable
3223 11:07:38.455127 == TX Byte 0 ==
3224 11:07:38.461244 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3225 11:07:38.465211 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3226 11:07:38.465655 == TX Byte 1 ==
3227 11:07:38.471770 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3228 11:07:38.475019 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3229 11:07:38.475412 ==
3230 11:07:38.478312 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 11:07:38.481281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 11:07:38.481674 ==
3233 11:07:38.494115 TX Vref=22, minBit 9, minWin=24, winSum=408
3234 11:07:38.497647 TX Vref=24, minBit 1, minWin=25, winSum=419
3235 11:07:38.501305 TX Vref=26, minBit 8, minWin=25, winSum=423
3236 11:07:38.504129 TX Vref=28, minBit 7, minWin=26, winSum=427
3237 11:07:38.508481 TX Vref=30, minBit 3, minWin=26, winSum=431
3238 11:07:38.511184 TX Vref=32, minBit 9, minWin=25, winSum=430
3239 11:07:38.517546 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 30
3240 11:07:38.517966
3241 11:07:38.520925 Final TX Range 1 Vref 30
3242 11:07:38.521372
3243 11:07:38.521769 ==
3244 11:07:38.524395 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 11:07:38.527800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 11:07:38.528201 ==
3247 11:07:38.528603
3248 11:07:38.528977
3249 11:07:38.531118 TX Vref Scan disable
3250 11:07:38.534558 == TX Byte 0 ==
3251 11:07:38.537856 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3252 11:07:38.540989 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3253 11:07:38.544268 == TX Byte 1 ==
3254 11:07:38.547760 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3255 11:07:38.550787 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3256 11:07:38.551170
3257 11:07:38.554769 [DATLAT]
3258 11:07:38.555151 Freq=1200, CH1 RK0
3259 11:07:38.555462
3260 11:07:38.557704 DATLAT Default: 0xd
3261 11:07:38.558087 0, 0xFFFF, sum = 0
3262 11:07:38.560980 1, 0xFFFF, sum = 0
3263 11:07:38.561410 2, 0xFFFF, sum = 0
3264 11:07:38.564437 3, 0xFFFF, sum = 0
3265 11:07:38.564823 4, 0xFFFF, sum = 0
3266 11:07:38.567882 5, 0xFFFF, sum = 0
3267 11:07:38.568266 6, 0xFFFF, sum = 0
3268 11:07:38.571111 7, 0xFFFF, sum = 0
3269 11:07:38.571500 8, 0xFFFF, sum = 0
3270 11:07:38.574296 9, 0xFFFF, sum = 0
3271 11:07:38.577481 10, 0xFFFF, sum = 0
3272 11:07:38.577868 11, 0xFFFF, sum = 0
3273 11:07:38.581264 12, 0x0, sum = 1
3274 11:07:38.581749 13, 0x0, sum = 2
3275 11:07:38.582074 14, 0x0, sum = 3
3276 11:07:38.584066 15, 0x0, sum = 4
3277 11:07:38.584455 best_step = 13
3278 11:07:38.584754
3279 11:07:38.587485 ==
3280 11:07:38.587865 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 11:07:38.594139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 11:07:38.594527 ==
3283 11:07:38.594828 RX Vref Scan: 1
3284 11:07:38.595102
3285 11:07:38.597377 Set Vref Range= 32 -> 127
3286 11:07:38.597759
3287 11:07:38.600757 RX Vref 32 -> 127, step: 1
3288 11:07:38.601180
3289 11:07:38.604734 RX Delay -21 -> 252, step: 4
3290 11:07:38.605144
3291 11:07:38.607752 Set Vref, RX VrefLevel [Byte0]: 32
3292 11:07:38.610649 [Byte1]: 32
3293 11:07:38.611222
3294 11:07:38.614096 Set Vref, RX VrefLevel [Byte0]: 33
3295 11:07:38.617187 [Byte1]: 33
3296 11:07:38.617580
3297 11:07:38.620808 Set Vref, RX VrefLevel [Byte0]: 34
3298 11:07:38.623879 [Byte1]: 34
3299 11:07:38.628316
3300 11:07:38.628883 Set Vref, RX VrefLevel [Byte0]: 35
3301 11:07:38.631479 [Byte1]: 35
3302 11:07:38.636586
3303 11:07:38.636968 Set Vref, RX VrefLevel [Byte0]: 36
3304 11:07:38.640117 [Byte1]: 36
3305 11:07:38.644539
3306 11:07:38.644916 Set Vref, RX VrefLevel [Byte0]: 37
3307 11:07:38.647301 [Byte1]: 37
3308 11:07:38.652169
3309 11:07:38.652547 Set Vref, RX VrefLevel [Byte0]: 38
3310 11:07:38.655530 [Byte1]: 38
3311 11:07:38.659969
3312 11:07:38.660480 Set Vref, RX VrefLevel [Byte0]: 39
3313 11:07:38.663589 [Byte1]: 39
3314 11:07:38.668055
3315 11:07:38.668404 Set Vref, RX VrefLevel [Byte0]: 40
3316 11:07:38.670895 [Byte1]: 40
3317 11:07:38.675429
3318 11:07:38.675695 Set Vref, RX VrefLevel [Byte0]: 41
3319 11:07:38.679569 [Byte1]: 41
3320 11:07:38.684069
3321 11:07:38.684336 Set Vref, RX VrefLevel [Byte0]: 42
3322 11:07:38.686940 [Byte1]: 42
3323 11:07:38.691843
3324 11:07:38.692109 Set Vref, RX VrefLevel [Byte0]: 43
3325 11:07:38.695669 [Byte1]: 43
3326 11:07:38.699712
3327 11:07:38.700068 Set Vref, RX VrefLevel [Byte0]: 44
3328 11:07:38.703575 [Byte1]: 44
3329 11:07:38.707982
3330 11:07:38.708415 Set Vref, RX VrefLevel [Byte0]: 45
3331 11:07:38.710657 [Byte1]: 45
3332 11:07:38.715280
3333 11:07:38.715814 Set Vref, RX VrefLevel [Byte0]: 46
3334 11:07:38.718605 [Byte1]: 46
3335 11:07:38.723674
3336 11:07:38.724053 Set Vref, RX VrefLevel [Byte0]: 47
3337 11:07:38.726774 [Byte1]: 47
3338 11:07:38.731159
3339 11:07:38.731538 Set Vref, RX VrefLevel [Byte0]: 48
3340 11:07:38.734537 [Byte1]: 48
3341 11:07:38.739569
3342 11:07:38.739989 Set Vref, RX VrefLevel [Byte0]: 49
3343 11:07:38.742504 [Byte1]: 49
3344 11:07:38.746890
3345 11:07:38.747266 Set Vref, RX VrefLevel [Byte0]: 50
3346 11:07:38.750741 [Byte1]: 50
3347 11:07:38.755719
3348 11:07:38.756097 Set Vref, RX VrefLevel [Byte0]: 51
3349 11:07:38.759031 [Byte1]: 51
3350 11:07:38.763093
3351 11:07:38.763470 Set Vref, RX VrefLevel [Byte0]: 52
3352 11:07:38.766414 [Byte1]: 52
3353 11:07:38.770609
3354 11:07:38.771088 Set Vref, RX VrefLevel [Byte0]: 53
3355 11:07:38.774278 [Byte1]: 53
3356 11:07:38.778741
3357 11:07:38.779116 Set Vref, RX VrefLevel [Byte0]: 54
3358 11:07:38.782393 [Byte1]: 54
3359 11:07:38.786582
3360 11:07:38.786957 Set Vref, RX VrefLevel [Byte0]: 55
3361 11:07:38.789873 [Byte1]: 55
3362 11:07:38.794974
3363 11:07:38.795351 Set Vref, RX VrefLevel [Byte0]: 56
3364 11:07:38.798429 [Byte1]: 56
3365 11:07:38.802482
3366 11:07:38.802859 Set Vref, RX VrefLevel [Byte0]: 57
3367 11:07:38.805551 [Byte1]: 57
3368 11:07:38.810757
3369 11:07:38.811135 Set Vref, RX VrefLevel [Byte0]: 58
3370 11:07:38.813737 [Byte1]: 58
3371 11:07:38.818643
3372 11:07:38.819021 Set Vref, RX VrefLevel [Byte0]: 59
3373 11:07:38.822166 [Byte1]: 59
3374 11:07:38.826348
3375 11:07:38.826727 Set Vref, RX VrefLevel [Byte0]: 60
3376 11:07:38.829454 [Byte1]: 60
3377 11:07:38.834496
3378 11:07:38.834977 Set Vref, RX VrefLevel [Byte0]: 61
3379 11:07:38.837599 [Byte1]: 61
3380 11:07:38.842032
3381 11:07:38.842533 Set Vref, RX VrefLevel [Byte0]: 62
3382 11:07:38.845306 [Byte1]: 62
3383 11:07:38.849984
3384 11:07:38.850367 Set Vref, RX VrefLevel [Byte0]: 63
3385 11:07:38.853532 [Byte1]: 63
3386 11:07:38.857961
3387 11:07:38.858341 Set Vref, RX VrefLevel [Byte0]: 64
3388 11:07:38.861370 [Byte1]: 64
3389 11:07:38.866289
3390 11:07:38.866668 Set Vref, RX VrefLevel [Byte0]: 65
3391 11:07:38.869003 [Byte1]: 65
3392 11:07:38.873637
3393 11:07:38.874017 Set Vref, RX VrefLevel [Byte0]: 66
3394 11:07:38.876998 [Byte1]: 66
3395 11:07:38.881797
3396 11:07:38.882178 Set Vref, RX VrefLevel [Byte0]: 67
3397 11:07:38.885427 [Byte1]: 67
3398 11:07:38.890042
3399 11:07:38.890434 Set Vref, RX VrefLevel [Byte0]: 68
3400 11:07:38.893220 [Byte1]: 68
3401 11:07:38.897414
3402 11:07:38.897827 Set Vref, RX VrefLevel [Byte0]: 69
3403 11:07:38.901041 [Byte1]: 69
3404 11:07:38.905525
3405 11:07:38.905906 Set Vref, RX VrefLevel [Byte0]: 70
3406 11:07:38.908917 [Byte1]: 70
3407 11:07:38.913851
3408 11:07:38.914391 Final RX Vref Byte 0 = 56 to rank0
3409 11:07:38.917439 Final RX Vref Byte 1 = 50 to rank0
3410 11:07:38.920427 Final RX Vref Byte 0 = 56 to rank1
3411 11:07:38.923533 Final RX Vref Byte 1 = 50 to rank1==
3412 11:07:38.926831 Dram Type= 6, Freq= 0, CH_1, rank 0
3413 11:07:38.933286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 11:07:38.933841 ==
3415 11:07:38.934260 DQS Delay:
3416 11:07:38.934635 DQS0 = 0, DQS1 = 0
3417 11:07:38.937212 DQM Delay:
3418 11:07:38.937717 DQM0 = 116, DQM1 = 108
3419 11:07:38.940285 DQ Delay:
3420 11:07:38.943644 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3421 11:07:38.946989 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3422 11:07:38.950444 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =104
3423 11:07:38.953732 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3424 11:07:38.954124
3425 11:07:38.954516
3426 11:07:38.960303 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3427 11:07:38.963656 CH1 RK0: MR19=303, MR18=FEE2
3428 11:07:38.970240 CH1_RK0: MR19=0x303, MR18=0xFEE2, DQSOSC=410, MR23=63, INC=39, DEC=26
3429 11:07:38.970671
3430 11:07:38.973692 ----->DramcWriteLeveling(PI) begin...
3431 11:07:38.974088 ==
3432 11:07:38.977269 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 11:07:38.980311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 11:07:38.980864 ==
3435 11:07:38.983710 Write leveling (Byte 0): 26 => 26
3436 11:07:38.986995 Write leveling (Byte 1): 28 => 28
3437 11:07:38.990435 DramcWriteLeveling(PI) end<-----
3438 11:07:38.990965
3439 11:07:38.991360 ==
3440 11:07:38.994117 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 11:07:38.997409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 11:07:39.000497 ==
3443 11:07:39.000889 [Gating] SW mode calibration
3444 11:07:39.007122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3445 11:07:39.013993 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3446 11:07:39.017442 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3447 11:07:39.023847 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 11:07:39.027349 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 11:07:39.030972 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 11:07:39.037332 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3451 11:07:39.041089 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 11:07:39.044093 0 15 24 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 1)
3453 11:07:39.050708 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
3454 11:07:39.054288 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3455 11:07:39.057425 1 0 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3456 11:07:39.060889 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 11:07:39.067103 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 11:07:39.070900 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 11:07:39.073781 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3460 11:07:39.080797 1 0 24 | B1->B0 | 2929 3a3a | 0 0 | (0 0) (0 0)
3461 11:07:39.084162 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 11:07:39.087475 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 11:07:39.094482 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 11:07:39.097369 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 11:07:39.100542 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 11:07:39.107462 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 11:07:39.110885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3468 11:07:39.113776 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3469 11:07:39.120722 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3470 11:07:39.124417 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:07:39.127645 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:07:39.134413 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:07:39.137397 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:07:39.140889 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:07:39.147942 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:07:39.151279 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:07:39.154336 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:07:39.157432 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 11:07:39.163969 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:07:39.167329 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:07:39.170731 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 11:07:39.177854 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 11:07:39.180735 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 11:07:39.184179 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3485 11:07:39.190793 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3486 11:07:39.191192 Total UI for P1: 0, mck2ui 16
3487 11:07:39.197740 best dqsien dly found for B0: ( 1, 3, 24)
3488 11:07:39.200573 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 11:07:39.204166 Total UI for P1: 0, mck2ui 16
3490 11:07:39.207607 best dqsien dly found for B1: ( 1, 3, 28)
3491 11:07:39.210765 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3492 11:07:39.214073 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3493 11:07:39.214475
3494 11:07:39.217225 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3495 11:07:39.220836 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3496 11:07:39.224725 [Gating] SW calibration Done
3497 11:07:39.225149 ==
3498 11:07:39.227951 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 11:07:39.231027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 11:07:39.231440 ==
3501 11:07:39.233892 RX Vref Scan: 0
3502 11:07:39.234287
3503 11:07:39.237725 RX Vref 0 -> 0, step: 1
3504 11:07:39.238119
3505 11:07:39.238517 RX Delay -40 -> 252, step: 8
3506 11:07:39.243949 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3507 11:07:39.247319 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3508 11:07:39.250875 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3509 11:07:39.254358 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3510 11:07:39.257617 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3511 11:07:39.264422 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3512 11:07:39.267617 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3513 11:07:39.270949 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3514 11:07:39.274028 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3515 11:07:39.277636 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3516 11:07:39.284201 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3517 11:07:39.287291 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3518 11:07:39.290666 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3519 11:07:39.293912 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3520 11:07:39.297205 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3521 11:07:39.304302 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3522 11:07:39.304701 ==
3523 11:07:39.307526 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 11:07:39.310964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 11:07:39.311478 ==
3526 11:07:39.311875 DQS Delay:
3527 11:07:39.314677 DQS0 = 0, DQS1 = 0
3528 11:07:39.315071 DQM Delay:
3529 11:07:39.317582 DQM0 = 113, DQM1 = 110
3530 11:07:39.318063 DQ Delay:
3531 11:07:39.320646 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3532 11:07:39.324002 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3533 11:07:39.327475 DQ8 =103, DQ9 =99, DQ10 =111, DQ11 =99
3534 11:07:39.330756 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3535 11:07:39.331151
3536 11:07:39.331544
3537 11:07:39.334085 ==
3538 11:07:39.334613 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 11:07:39.340770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 11:07:39.341302 ==
3541 11:07:39.341701
3542 11:07:39.342072
3543 11:07:39.344026 TX Vref Scan disable
3544 11:07:39.344423 == TX Byte 0 ==
3545 11:07:39.348092 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3546 11:07:39.354699 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3547 11:07:39.355236 == TX Byte 1 ==
3548 11:07:39.357499 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3549 11:07:39.364733 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3550 11:07:39.365331 ==
3551 11:07:39.367494 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 11:07:39.370822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 11:07:39.371209 ==
3554 11:07:39.382327 TX Vref=22, minBit 1, minWin=25, winSum=418
3555 11:07:39.385830 TX Vref=24, minBit 1, minWin=25, winSum=419
3556 11:07:39.389246 TX Vref=26, minBit 0, minWin=26, winSum=426
3557 11:07:39.392582 TX Vref=28, minBit 1, minWin=26, winSum=430
3558 11:07:39.395853 TX Vref=30, minBit 9, minWin=26, winSum=431
3559 11:07:39.402908 TX Vref=32, minBit 15, minWin=26, winSum=434
3560 11:07:39.405891 [TxChooseVref] Worse bit 15, Min win 26, Win sum 434, Final Vref 32
3561 11:07:39.406202
3562 11:07:39.409069 Final TX Range 1 Vref 32
3563 11:07:39.409354
3564 11:07:39.409581 ==
3565 11:07:39.412818 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 11:07:39.415895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 11:07:39.416105 ==
3568 11:07:39.418853
3569 11:07:39.419134
3570 11:07:39.419351 TX Vref Scan disable
3571 11:07:39.422378 == TX Byte 0 ==
3572 11:07:39.425778 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3573 11:07:39.428910 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3574 11:07:39.432952 == TX Byte 1 ==
3575 11:07:39.435439 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3576 11:07:39.439129 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3577 11:07:39.439260
3578 11:07:39.442409 [DATLAT]
3579 11:07:39.442547 Freq=1200, CH1 RK1
3580 11:07:39.442640
3581 11:07:39.445527 DATLAT Default: 0xd
3582 11:07:39.445609 0, 0xFFFF, sum = 0
3583 11:07:39.448657 1, 0xFFFF, sum = 0
3584 11:07:39.448735 2, 0xFFFF, sum = 0
3585 11:07:39.452300 3, 0xFFFF, sum = 0
3586 11:07:39.452379 4, 0xFFFF, sum = 0
3587 11:07:39.455726 5, 0xFFFF, sum = 0
3588 11:07:39.455828 6, 0xFFFF, sum = 0
3589 11:07:39.459108 7, 0xFFFF, sum = 0
3590 11:07:39.459185 8, 0xFFFF, sum = 0
3591 11:07:39.462359 9, 0xFFFF, sum = 0
3592 11:07:39.466123 10, 0xFFFF, sum = 0
3593 11:07:39.466201 11, 0xFFFF, sum = 0
3594 11:07:39.468791 12, 0x0, sum = 1
3595 11:07:39.468867 13, 0x0, sum = 2
3596 11:07:39.468928 14, 0x0, sum = 3
3597 11:07:39.472428 15, 0x0, sum = 4
3598 11:07:39.472505 best_step = 13
3599 11:07:39.472566
3600 11:07:39.475919 ==
3601 11:07:39.476019 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 11:07:39.483281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 11:07:39.483402 ==
3604 11:07:39.483504 RX Vref Scan: 0
3605 11:07:39.483600
3606 11:07:39.485385 RX Vref 0 -> 0, step: 1
3607 11:07:39.485491
3608 11:07:39.489270 RX Delay -13 -> 252, step: 4
3609 11:07:39.492319 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3610 11:07:39.495850 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3611 11:07:39.502212 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3612 11:07:39.505642 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3613 11:07:39.508941 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3614 11:07:39.512048 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3615 11:07:39.515346 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3616 11:07:39.522441 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3617 11:07:39.525609 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3618 11:07:39.529887 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3619 11:07:39.532600 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3620 11:07:39.536110 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3621 11:07:39.542830 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3622 11:07:39.546289 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3623 11:07:39.549110 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3624 11:07:39.552769 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3625 11:07:39.553312 ==
3626 11:07:39.556591 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 11:07:39.559534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 11:07:39.562945 ==
3629 11:07:39.563332 DQS Delay:
3630 11:07:39.563636 DQS0 = 0, DQS1 = 0
3631 11:07:39.566556 DQM Delay:
3632 11:07:39.566943 DQM0 = 113, DQM1 = 109
3633 11:07:39.570135 DQ Delay:
3634 11:07:39.573350 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3635 11:07:39.576220 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3636 11:07:39.580041 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3637 11:07:39.583101 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3638 11:07:39.583489
3639 11:07:39.583790
3640 11:07:39.589597 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3641 11:07:39.592649 CH1 RK1: MR19=304, MR18=FB02
3642 11:07:39.599575 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3643 11:07:39.602950 [RxdqsGatingPostProcess] freq 1200
3644 11:07:39.609227 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3645 11:07:39.612536 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 11:07:39.612939 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 11:07:39.616700 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 11:07:39.619366 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 11:07:39.622806 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 11:07:39.626265 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 11:07:39.629378 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 11:07:39.632525 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 11:07:39.636318 Pre-setting of DQS Precalculation
3654 11:07:39.639746 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3655 11:07:39.649543 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3656 11:07:39.656692 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3657 11:07:39.657321
3658 11:07:39.657802
3659 11:07:39.659661 [Calibration Summary] 2400 Mbps
3660 11:07:39.660050 CH 0, Rank 0
3661 11:07:39.663058 SW Impedance : PASS
3662 11:07:39.663611 DUTY Scan : NO K
3663 11:07:39.666571 ZQ Calibration : PASS
3664 11:07:39.670029 Jitter Meter : NO K
3665 11:07:39.670416 CBT Training : PASS
3666 11:07:39.673057 Write leveling : PASS
3667 11:07:39.676587 RX DQS gating : PASS
3668 11:07:39.676977 RX DQ/DQS(RDDQC) : PASS
3669 11:07:39.679671 TX DQ/DQS : PASS
3670 11:07:39.682972 RX DATLAT : PASS
3671 11:07:39.683363 RX DQ/DQS(Engine): PASS
3672 11:07:39.685988 TX OE : NO K
3673 11:07:39.686379 All Pass.
3674 11:07:39.686682
3675 11:07:39.689566 CH 0, Rank 1
3676 11:07:39.689955 SW Impedance : PASS
3677 11:07:39.692626 DUTY Scan : NO K
3678 11:07:39.696218 ZQ Calibration : PASS
3679 11:07:39.696756 Jitter Meter : NO K
3680 11:07:39.699337 CBT Training : PASS
3681 11:07:39.699867 Write leveling : PASS
3682 11:07:39.702981 RX DQS gating : PASS
3683 11:07:39.706528 RX DQ/DQS(RDDQC) : PASS
3684 11:07:39.707020 TX DQ/DQS : PASS
3685 11:07:39.709546 RX DATLAT : PASS
3686 11:07:39.713252 RX DQ/DQS(Engine): PASS
3687 11:07:39.713733 TX OE : NO K
3688 11:07:39.716194 All Pass.
3689 11:07:39.716684
3690 11:07:39.717171 CH 1, Rank 0
3691 11:07:39.719725 SW Impedance : PASS
3692 11:07:39.720229 DUTY Scan : NO K
3693 11:07:39.722972 ZQ Calibration : PASS
3694 11:07:39.726313 Jitter Meter : NO K
3695 11:07:39.726817 CBT Training : PASS
3696 11:07:39.730058 Write leveling : PASS
3697 11:07:39.733626 RX DQS gating : PASS
3698 11:07:39.733979 RX DQ/DQS(RDDQC) : PASS
3699 11:07:39.736128 TX DQ/DQS : PASS
3700 11:07:39.739360 RX DATLAT : PASS
3701 11:07:39.739747 RX DQ/DQS(Engine): PASS
3702 11:07:39.742909 TX OE : NO K
3703 11:07:39.743303 All Pass.
3704 11:07:39.743607
3705 11:07:39.746480 CH 1, Rank 1
3706 11:07:39.746868 SW Impedance : PASS
3707 11:07:39.749504 DUTY Scan : NO K
3708 11:07:39.749893 ZQ Calibration : PASS
3709 11:07:39.752689 Jitter Meter : NO K
3710 11:07:39.755893 CBT Training : PASS
3711 11:07:39.756285 Write leveling : PASS
3712 11:07:39.759459 RX DQS gating : PASS
3713 11:07:39.762681 RX DQ/DQS(RDDQC) : PASS
3714 11:07:39.763099 TX DQ/DQS : PASS
3715 11:07:39.766163 RX DATLAT : PASS
3716 11:07:39.769350 RX DQ/DQS(Engine): PASS
3717 11:07:39.769742 TX OE : NO K
3718 11:07:39.772656 All Pass.
3719 11:07:39.773086
3720 11:07:39.773540 DramC Write-DBI off
3721 11:07:39.776148 PER_BANK_REFRESH: Hybrid Mode
3722 11:07:39.776535 TX_TRACKING: ON
3723 11:07:39.785938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3724 11:07:39.789564 [FAST_K] Save calibration result to emmc
3725 11:07:39.792719 dramc_set_vcore_voltage set vcore to 650000
3726 11:07:39.796192 Read voltage for 600, 5
3727 11:07:39.796584 Vio18 = 0
3728 11:07:39.799492 Vcore = 650000
3729 11:07:39.799882 Vdram = 0
3730 11:07:39.800186 Vddq = 0
3731 11:07:39.802681 Vmddr = 0
3732 11:07:39.806326 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3733 11:07:39.812721 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3734 11:07:39.813114 MEM_TYPE=3, freq_sel=19
3735 11:07:39.816042 sv_algorithm_assistance_LP4_1600
3736 11:07:39.822991 ============ PULL DRAM RESETB DOWN ============
3737 11:07:39.826535 ========== PULL DRAM RESETB DOWN end =========
3738 11:07:39.829166 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3739 11:07:39.832688 ===================================
3740 11:07:39.835754 LPDDR4 DRAM CONFIGURATION
3741 11:07:39.839441 ===================================
3742 11:07:39.839830 EX_ROW_EN[0] = 0x0
3743 11:07:39.842730 EX_ROW_EN[1] = 0x0
3744 11:07:39.843118 LP4Y_EN = 0x0
3745 11:07:39.845899 WORK_FSP = 0x0
3746 11:07:39.848991 WL = 0x2
3747 11:07:39.849424 RL = 0x2
3748 11:07:39.852446 BL = 0x2
3749 11:07:39.852835 RPST = 0x0
3750 11:07:39.855722 RD_PRE = 0x0
3751 11:07:39.856108 WR_PRE = 0x1
3752 11:07:39.859280 WR_PST = 0x0
3753 11:07:39.859670 DBI_WR = 0x0
3754 11:07:39.862362 DBI_RD = 0x0
3755 11:07:39.862752 OTF = 0x1
3756 11:07:39.866443 ===================================
3757 11:07:39.869322 ===================================
3758 11:07:39.872631 ANA top config
3759 11:07:39.875809 ===================================
3760 11:07:39.876333 DLL_ASYNC_EN = 0
3761 11:07:39.879499 ALL_SLAVE_EN = 1
3762 11:07:39.882965 NEW_RANK_MODE = 1
3763 11:07:39.885822 DLL_IDLE_MODE = 1
3764 11:07:39.886208 LP45_APHY_COMB_EN = 1
3765 11:07:39.889786 TX_ODT_DIS = 1
3766 11:07:39.893145 NEW_8X_MODE = 1
3767 11:07:39.897363 ===================================
3768 11:07:39.899712 ===================================
3769 11:07:39.903153 data_rate = 1200
3770 11:07:39.906471 CKR = 1
3771 11:07:39.906995 DQ_P2S_RATIO = 8
3772 11:07:39.909711 ===================================
3773 11:07:39.912915 CA_P2S_RATIO = 8
3774 11:07:39.916088 DQ_CA_OPEN = 0
3775 11:07:39.919556 DQ_SEMI_OPEN = 0
3776 11:07:39.922805 CA_SEMI_OPEN = 0
3777 11:07:39.926283 CA_FULL_RATE = 0
3778 11:07:39.926676 DQ_CKDIV4_EN = 1
3779 11:07:39.929647 CA_CKDIV4_EN = 1
3780 11:07:39.933066 CA_PREDIV_EN = 0
3781 11:07:39.936539 PH8_DLY = 0
3782 11:07:39.939822 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3783 11:07:39.942562 DQ_AAMCK_DIV = 4
3784 11:07:39.942956 CA_AAMCK_DIV = 4
3785 11:07:39.946344 CA_ADMCK_DIV = 4
3786 11:07:39.949546 DQ_TRACK_CA_EN = 0
3787 11:07:39.953112 CA_PICK = 600
3788 11:07:39.955996 CA_MCKIO = 600
3789 11:07:39.959426 MCKIO_SEMI = 0
3790 11:07:39.959812 PLL_FREQ = 2288
3791 11:07:39.963258 DQ_UI_PI_RATIO = 32
3792 11:07:39.966010 CA_UI_PI_RATIO = 0
3793 11:07:39.969969 ===================================
3794 11:07:39.972905 ===================================
3795 11:07:39.976870 memory_type:LPDDR4
3796 11:07:39.977426 GP_NUM : 10
3797 11:07:39.980023 SRAM_EN : 1
3798 11:07:39.983230 MD32_EN : 0
3799 11:07:39.986245 ===================================
3800 11:07:39.986635 [ANA_INIT] >>>>>>>>>>>>>>
3801 11:07:39.989399 <<<<<< [CONFIGURE PHASE]: ANA_TX
3802 11:07:39.992944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3803 11:07:39.996262 ===================================
3804 11:07:40.000184 data_rate = 1200,PCW = 0X5800
3805 11:07:40.002804 ===================================
3806 11:07:40.006587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3807 11:07:40.012820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 11:07:40.016026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 11:07:40.022816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3810 11:07:40.026022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3811 11:07:40.029446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3812 11:07:40.029850 [ANA_INIT] flow start
3813 11:07:40.032897 [ANA_INIT] PLL >>>>>>>>
3814 11:07:40.036631 [ANA_INIT] PLL <<<<<<<<
3815 11:07:40.039661 [ANA_INIT] MIDPI >>>>>>>>
3816 11:07:40.040049 [ANA_INIT] MIDPI <<<<<<<<
3817 11:07:40.043003 [ANA_INIT] DLL >>>>>>>>
3818 11:07:40.043391 [ANA_INIT] flow end
3819 11:07:40.050071 ============ LP4 DIFF to SE enter ============
3820 11:07:40.052994 ============ LP4 DIFF to SE exit ============
3821 11:07:40.056208 [ANA_INIT] <<<<<<<<<<<<<
3822 11:07:40.059894 [Flow] Enable top DCM control >>>>>
3823 11:07:40.062797 [Flow] Enable top DCM control <<<<<
3824 11:07:40.063191 Enable DLL master slave shuffle
3825 11:07:40.070067 ==============================================================
3826 11:07:40.073008 Gating Mode config
3827 11:07:40.076789 ==============================================================
3828 11:07:40.079715 Config description:
3829 11:07:40.089587 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3830 11:07:40.096343 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3831 11:07:40.099523 SELPH_MODE 0: By rank 1: By Phase
3832 11:07:40.106612 ==============================================================
3833 11:07:40.110413 GAT_TRACK_EN = 1
3834 11:07:40.113184 RX_GATING_MODE = 2
3835 11:07:40.116691 RX_GATING_TRACK_MODE = 2
3836 11:07:40.117239 SELPH_MODE = 1
3837 11:07:40.120100 PICG_EARLY_EN = 1
3838 11:07:40.123445 VALID_LAT_VALUE = 1
3839 11:07:40.130301 ==============================================================
3840 11:07:40.133432 Enter into Gating configuration >>>>
3841 11:07:40.136670 Exit from Gating configuration <<<<
3842 11:07:40.139711 Enter into DVFS_PRE_config >>>>>
3843 11:07:40.149724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3844 11:07:40.153419 Exit from DVFS_PRE_config <<<<<
3845 11:07:40.156381 Enter into PICG configuration >>>>
3846 11:07:40.160098 Exit from PICG configuration <<<<
3847 11:07:40.163070 [RX_INPUT] configuration >>>>>
3848 11:07:40.166826 [RX_INPUT] configuration <<<<<
3849 11:07:40.169919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3850 11:07:40.177210 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3851 11:07:40.183221 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 11:07:40.189953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 11:07:40.193234 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3854 11:07:40.200016 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3855 11:07:40.203358 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3856 11:07:40.210641 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3857 11:07:40.213647 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3858 11:07:40.217216 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3859 11:07:40.220619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3860 11:07:40.226897 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3861 11:07:40.230023 ===================================
3862 11:07:40.230407 LPDDR4 DRAM CONFIGURATION
3863 11:07:40.233617 ===================================
3864 11:07:40.236934 EX_ROW_EN[0] = 0x0
3865 11:07:40.239952 EX_ROW_EN[1] = 0x0
3866 11:07:40.240334 LP4Y_EN = 0x0
3867 11:07:40.243483 WORK_FSP = 0x0
3868 11:07:40.243865 WL = 0x2
3869 11:07:40.247180 RL = 0x2
3870 11:07:40.247559 BL = 0x2
3871 11:07:40.250621 RPST = 0x0
3872 11:07:40.250999 RD_PRE = 0x0
3873 11:07:40.253520 WR_PRE = 0x1
3874 11:07:40.253900 WR_PST = 0x0
3875 11:07:40.257145 DBI_WR = 0x0
3876 11:07:40.257531 DBI_RD = 0x0
3877 11:07:40.260551 OTF = 0x1
3878 11:07:40.263264 ===================================
3879 11:07:40.267072 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3880 11:07:40.270295 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3881 11:07:40.276829 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 11:07:40.277273 ===================================
3883 11:07:40.279686 LPDDR4 DRAM CONFIGURATION
3884 11:07:40.283554 ===================================
3885 11:07:40.286733 EX_ROW_EN[0] = 0x10
3886 11:07:40.287116 EX_ROW_EN[1] = 0x0
3887 11:07:40.289880 LP4Y_EN = 0x0
3888 11:07:40.290264 WORK_FSP = 0x0
3889 11:07:40.293556 WL = 0x2
3890 11:07:40.293938 RL = 0x2
3891 11:07:40.297002 BL = 0x2
3892 11:07:40.297412 RPST = 0x0
3893 11:07:40.300241 RD_PRE = 0x0
3894 11:07:40.303416 WR_PRE = 0x1
3895 11:07:40.303797 WR_PST = 0x0
3896 11:07:40.306913 DBI_WR = 0x0
3897 11:07:40.307297 DBI_RD = 0x0
3898 11:07:40.310293 OTF = 0x1
3899 11:07:40.313540 ===================================
3900 11:07:40.316816 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3901 11:07:40.322313 nWR fixed to 30
3902 11:07:40.325863 [ModeRegInit_LP4] CH0 RK0
3903 11:07:40.326345 [ModeRegInit_LP4] CH0 RK1
3904 11:07:40.328738 [ModeRegInit_LP4] CH1 RK0
3905 11:07:40.332019 [ModeRegInit_LP4] CH1 RK1
3906 11:07:40.332399 match AC timing 17
3907 11:07:40.338831 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3908 11:07:40.341848 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3909 11:07:40.345685 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3910 11:07:40.351996 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3911 11:07:40.355759 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3912 11:07:40.356144 ==
3913 11:07:40.358692 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 11:07:40.362370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3915 11:07:40.362756 ==
3916 11:07:40.368906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3917 11:07:40.375144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3918 11:07:40.378747 [CA 0] Center 36 (6~66) winsize 61
3919 11:07:40.381914 [CA 1] Center 36 (6~66) winsize 61
3920 11:07:40.385522 [CA 2] Center 34 (4~64) winsize 61
3921 11:07:40.388696 [CA 3] Center 34 (4~64) winsize 61
3922 11:07:40.392409 [CA 4] Center 33 (3~64) winsize 62
3923 11:07:40.395469 [CA 5] Center 33 (3~64) winsize 62
3924 11:07:40.395908
3925 11:07:40.398550 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3926 11:07:40.398933
3927 11:07:40.402631 [CATrainingPosCal] consider 1 rank data
3928 11:07:40.404916 u2DelayCellTimex100 = 270/100 ps
3929 11:07:40.408623 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3930 11:07:40.411548 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3931 11:07:40.415193 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3932 11:07:40.419070 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3933 11:07:40.422181 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3934 11:07:40.425521 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 11:07:40.426017
3936 11:07:40.431756 CA PerBit enable=1, Macro0, CA PI delay=33
3937 11:07:40.432170
3938 11:07:40.432478 [CBTSetCACLKResult] CA Dly = 33
3939 11:07:40.435303 CS Dly: 6 (0~37)
3940 11:07:40.435683 ==
3941 11:07:40.438480 Dram Type= 6, Freq= 0, CH_0, rank 1
3942 11:07:40.442000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 11:07:40.442414 ==
3944 11:07:40.448711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 11:07:40.455143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3946 11:07:40.458835 [CA 0] Center 36 (6~66) winsize 61
3947 11:07:40.461803 [CA 1] Center 35 (5~66) winsize 62
3948 11:07:40.465102 [CA 2] Center 34 (4~65) winsize 62
3949 11:07:40.468794 [CA 3] Center 34 (4~64) winsize 61
3950 11:07:40.472156 [CA 4] Center 33 (3~64) winsize 62
3951 11:07:40.475228 [CA 5] Center 33 (3~64) winsize 62
3952 11:07:40.475628
3953 11:07:40.479089 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3954 11:07:40.479501
3955 11:07:40.482378 [CATrainingPosCal] consider 2 rank data
3956 11:07:40.485185 u2DelayCellTimex100 = 270/100 ps
3957 11:07:40.488331 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 11:07:40.492255 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3959 11:07:40.495404 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3960 11:07:40.498328 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3961 11:07:40.501942 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 11:07:40.505434 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 11:07:40.505907
3964 11:07:40.511970 CA PerBit enable=1, Macro0, CA PI delay=33
3965 11:07:40.512452
3966 11:07:40.515349 [CBTSetCACLKResult] CA Dly = 33
3967 11:07:40.515826 CS Dly: 6 (0~37)
3968 11:07:40.516262
3969 11:07:40.518681 ----->DramcWriteLeveling(PI) begin...
3970 11:07:40.519173 ==
3971 11:07:40.522092 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 11:07:40.525054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 11:07:40.525497 ==
3974 11:07:40.528437 Write leveling (Byte 0): 31 => 31
3975 11:07:40.532071 Write leveling (Byte 1): 27 => 27
3976 11:07:40.535437 DramcWriteLeveling(PI) end<-----
3977 11:07:40.535928
3978 11:07:40.536403 ==
3979 11:07:40.539336 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 11:07:40.541995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 11:07:40.545442 ==
3982 11:07:40.545821 [Gating] SW mode calibration
3983 11:07:40.555510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3984 11:07:40.558836 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3985 11:07:40.562165 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 11:07:40.568814 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 11:07:40.572113 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 11:07:40.575334 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 11:07:40.581891 0 9 16 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
3990 11:07:40.585867 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3991 11:07:40.589523 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 11:07:40.592493 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 11:07:40.598785 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 11:07:40.602002 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 11:07:40.606019 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 11:07:40.612554 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3997 11:07:40.616057 0 10 16 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (1 1)
3998 11:07:40.618659 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 11:07:40.625691 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 11:07:40.629181 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 11:07:40.632272 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 11:07:40.639466 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 11:07:40.642415 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 11:07:40.645686 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 11:07:40.652525 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4006 11:07:40.655748 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:07:40.659176 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:07:40.665608 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:07:40.669171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:07:40.672255 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:07:40.679297 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:07:40.682534 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:07:40.686239 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:07:40.689158 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:07:40.695481 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:07:40.698878 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:07:40.702491 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:07:40.708997 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:07:40.712410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 11:07:40.715790 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 11:07:40.722935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4022 11:07:40.725931 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 11:07:40.728946 Total UI for P1: 0, mck2ui 16
4024 11:07:40.732515 best dqsien dly found for B0: ( 0, 13, 16)
4025 11:07:40.735673 Total UI for P1: 0, mck2ui 16
4026 11:07:40.738738 best dqsien dly found for B1: ( 0, 13, 16)
4027 11:07:40.742645 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4028 11:07:40.745694 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4029 11:07:40.746117
4030 11:07:40.749051 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4031 11:07:40.752448 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4032 11:07:40.755852 [Gating] SW calibration Done
4033 11:07:40.756244 ==
4034 11:07:40.758973 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 11:07:40.762172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 11:07:40.765656 ==
4037 11:07:40.766038 RX Vref Scan: 0
4038 11:07:40.766339
4039 11:07:40.769393 RX Vref 0 -> 0, step: 1
4040 11:07:40.769940
4041 11:07:40.772690 RX Delay -230 -> 252, step: 16
4042 11:07:40.775593 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4043 11:07:40.779204 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4044 11:07:40.782749 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4045 11:07:40.785923 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4046 11:07:40.792522 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4047 11:07:40.795498 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4048 11:07:40.798911 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4049 11:07:40.802793 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4050 11:07:40.808902 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4051 11:07:40.812300 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4052 11:07:40.815855 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4053 11:07:40.819153 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4054 11:07:40.822594 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4055 11:07:40.829105 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4056 11:07:40.832474 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4057 11:07:40.836075 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4058 11:07:40.836466 ==
4059 11:07:40.839573 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 11:07:40.842344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 11:07:40.846053 ==
4062 11:07:40.846551 DQS Delay:
4063 11:07:40.847022 DQS0 = 0, DQS1 = 0
4064 11:07:40.849416 DQM Delay:
4065 11:07:40.849925 DQM0 = 45, DQM1 = 33
4066 11:07:40.852742 DQ Delay:
4067 11:07:40.853282 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4068 11:07:40.855953 DQ4 =57, DQ5 =33, DQ6 =57, DQ7 =57
4069 11:07:40.859273 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4070 11:07:40.862349 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4071 11:07:40.862737
4072 11:07:40.866322
4073 11:07:40.866673 ==
4074 11:07:40.868687 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 11:07:40.872007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 11:07:40.872228 ==
4077 11:07:40.872391
4078 11:07:40.872538
4079 11:07:40.875785 TX Vref Scan disable
4080 11:07:40.875996 == TX Byte 0 ==
4081 11:07:40.882262 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4082 11:07:40.885097 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4083 11:07:40.885253 == TX Byte 1 ==
4084 11:07:40.892043 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4085 11:07:40.895367 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4086 11:07:40.895472 ==
4087 11:07:40.898894 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 11:07:40.901905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 11:07:40.901990 ==
4090 11:07:40.902056
4091 11:07:40.902117
4092 11:07:40.905224 TX Vref Scan disable
4093 11:07:40.909004 == TX Byte 0 ==
4094 11:07:40.912291 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4095 11:07:40.915142 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4096 11:07:40.918775 == TX Byte 1 ==
4097 11:07:40.922074 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4098 11:07:40.925728 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4099 11:07:40.925810
4100 11:07:40.928657 [DATLAT]
4101 11:07:40.928745 Freq=600, CH0 RK0
4102 11:07:40.928825
4103 11:07:40.932317 DATLAT Default: 0x9
4104 11:07:40.932417 0, 0xFFFF, sum = 0
4105 11:07:40.935707 1, 0xFFFF, sum = 0
4106 11:07:40.935808 2, 0xFFFF, sum = 0
4107 11:07:40.938723 3, 0xFFFF, sum = 0
4108 11:07:40.938821 4, 0xFFFF, sum = 0
4109 11:07:40.942268 5, 0xFFFF, sum = 0
4110 11:07:40.942364 6, 0xFFFF, sum = 0
4111 11:07:40.946174 7, 0xFFFF, sum = 0
4112 11:07:40.946269 8, 0x0, sum = 1
4113 11:07:40.949015 9, 0x0, sum = 2
4114 11:07:40.949111 10, 0x0, sum = 3
4115 11:07:40.951999 11, 0x0, sum = 4
4116 11:07:40.952095 best_step = 9
4117 11:07:40.952177
4118 11:07:40.952261 ==
4119 11:07:40.956173 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 11:07:40.959173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 11:07:40.962028 ==
4122 11:07:40.962121 RX Vref Scan: 1
4123 11:07:40.962208
4124 11:07:40.965740 RX Vref 0 -> 0, step: 1
4125 11:07:40.965838
4126 11:07:40.968825 RX Delay -195 -> 252, step: 8
4127 11:07:40.968916
4128 11:07:40.971944 Set Vref, RX VrefLevel [Byte0]: 52
4129 11:07:40.976095 [Byte1]: 51
4130 11:07:40.976193
4131 11:07:40.979013 Final RX Vref Byte 0 = 52 to rank0
4132 11:07:40.982600 Final RX Vref Byte 1 = 51 to rank0
4133 11:07:40.985608 Final RX Vref Byte 0 = 52 to rank1
4134 11:07:40.988735 Final RX Vref Byte 1 = 51 to rank1==
4135 11:07:40.992151 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 11:07:40.995790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 11:07:40.995868 ==
4138 11:07:40.995927 DQS Delay:
4139 11:07:40.998980 DQS0 = 0, DQS1 = 0
4140 11:07:40.999066 DQM Delay:
4141 11:07:41.001896 DQM0 = 43, DQM1 = 33
4142 11:07:41.001979 DQ Delay:
4143 11:07:41.005865 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4144 11:07:41.008963 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4145 11:07:41.012041 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4146 11:07:41.015773 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4147 11:07:41.015850
4148 11:07:41.015909
4149 11:07:41.025597 [DQSOSCAuto] RK0, (LSB)MR18= 0x4727, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4150 11:07:41.025680 CH0 RK0: MR19=808, MR18=4727
4151 11:07:41.032594 CH0_RK0: MR19=0x808, MR18=0x4727, DQSOSC=396, MR23=63, INC=167, DEC=111
4152 11:07:41.032673
4153 11:07:41.035960 ----->DramcWriteLeveling(PI) begin...
4154 11:07:41.036038 ==
4155 11:07:41.039321 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 11:07:41.045473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 11:07:41.045552 ==
4158 11:07:41.049109 Write leveling (Byte 0): 34 => 34
4159 11:07:41.049209 Write leveling (Byte 1): 30 => 30
4160 11:07:41.052128 DramcWriteLeveling(PI) end<-----
4161 11:07:41.052205
4162 11:07:41.052264 ==
4163 11:07:41.055425 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 11:07:41.063501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 11:07:41.063579 ==
4166 11:07:41.065854 [Gating] SW mode calibration
4167 11:07:41.072314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 11:07:41.075562 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 11:07:41.082285 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 11:07:41.085689 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 11:07:41.089014 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 11:07:41.093238 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4173 11:07:41.099693 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4174 11:07:41.102566 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 11:07:41.105931 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 11:07:41.112859 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 11:07:41.115764 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 11:07:41.118998 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 11:07:41.125788 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 11:07:41.129493 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
4181 11:07:41.132210 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4182 11:07:41.138918 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 11:07:41.142875 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 11:07:41.146350 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 11:07:41.152424 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 11:07:41.156012 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 11:07:41.159419 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 11:07:41.165857 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 11:07:41.169030 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4190 11:07:41.172596 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:07:41.175662 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:07:41.182653 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:07:41.185890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:07:41.189057 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:07:41.196164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:07:41.199063 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:07:41.202933 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:07:41.210249 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:07:41.212845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:07:41.216362 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:07:41.222949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 11:07:41.227065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 11:07:41.229398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 11:07:41.236015 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4205 11:07:41.239884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 11:07:41.243963 Total UI for P1: 0, mck2ui 16
4207 11:07:41.245817 best dqsien dly found for B0: ( 0, 13, 12)
4208 11:07:41.249306 Total UI for P1: 0, mck2ui 16
4209 11:07:41.252757 best dqsien dly found for B1: ( 0, 13, 12)
4210 11:07:41.256174 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4211 11:07:41.258840 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4212 11:07:41.259078
4213 11:07:41.262582 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 11:07:41.265350 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4215 11:07:41.269021 [Gating] SW calibration Done
4216 11:07:41.269250 ==
4217 11:07:41.272756 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 11:07:41.275702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 11:07:41.278934 ==
4220 11:07:41.279117 RX Vref Scan: 0
4221 11:07:41.279262
4222 11:07:41.282252 RX Vref 0 -> 0, step: 1
4223 11:07:41.282421
4224 11:07:41.285493 RX Delay -230 -> 252, step: 16
4225 11:07:41.288977 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4226 11:07:41.292792 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4227 11:07:41.296005 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4228 11:07:41.302511 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4229 11:07:41.305753 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4230 11:07:41.308767 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4231 11:07:41.312427 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4232 11:07:41.316623 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4233 11:07:41.322505 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4234 11:07:41.325988 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4235 11:07:41.329189 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4236 11:07:41.332346 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4237 11:07:41.338848 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4238 11:07:41.342368 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4239 11:07:41.345626 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4240 11:07:41.349208 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4241 11:07:41.349601 ==
4242 11:07:41.352525 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 11:07:41.359026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 11:07:41.359536 ==
4245 11:07:41.360038 DQS Delay:
4246 11:07:41.360448 DQS0 = 0, DQS1 = 0
4247 11:07:41.362669 DQM Delay:
4248 11:07:41.363197 DQM0 = 38, DQM1 = 30
4249 11:07:41.365820 DQ Delay:
4250 11:07:41.369235 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4251 11:07:41.373067 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4252 11:07:41.373622 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4253 11:07:41.379464 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4254 11:07:41.379851
4255 11:07:41.380151
4256 11:07:41.380428 ==
4257 11:07:41.382658 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 11:07:41.386154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 11:07:41.386550 ==
4260 11:07:41.386857
4261 11:07:41.387136
4262 11:07:41.389444 TX Vref Scan disable
4263 11:07:41.389834 == TX Byte 0 ==
4264 11:07:41.395867 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4265 11:07:41.399150 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4266 11:07:41.399538 == TX Byte 1 ==
4267 11:07:41.405983 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4268 11:07:41.409409 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4269 11:07:41.409921 ==
4270 11:07:41.412604 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 11:07:41.416217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 11:07:41.416608 ==
4273 11:07:41.416981
4274 11:07:41.417380
4275 11:07:41.419511 TX Vref Scan disable
4276 11:07:41.423200 == TX Byte 0 ==
4277 11:07:41.425838 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4278 11:07:41.429472 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4279 11:07:41.432519 == TX Byte 1 ==
4280 11:07:41.436286 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4281 11:07:41.439351 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4282 11:07:41.439742
4283 11:07:41.443408 [DATLAT]
4284 11:07:41.443960 Freq=600, CH0 RK1
4285 11:07:41.444436
4286 11:07:41.446066 DATLAT Default: 0x9
4287 11:07:41.446553 0, 0xFFFF, sum = 0
4288 11:07:41.449430 1, 0xFFFF, sum = 0
4289 11:07:41.449949 2, 0xFFFF, sum = 0
4290 11:07:41.452968 3, 0xFFFF, sum = 0
4291 11:07:41.453525 4, 0xFFFF, sum = 0
4292 11:07:41.456023 5, 0xFFFF, sum = 0
4293 11:07:41.456525 6, 0xFFFF, sum = 0
4294 11:07:41.459869 7, 0xFFFF, sum = 0
4295 11:07:41.460354 8, 0x0, sum = 1
4296 11:07:41.462882 9, 0x0, sum = 2
4297 11:07:41.463369 10, 0x0, sum = 3
4298 11:07:41.466202 11, 0x0, sum = 4
4299 11:07:41.466699 best_step = 9
4300 11:07:41.467143
4301 11:07:41.467574 ==
4302 11:07:41.469402 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 11:07:41.472783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 11:07:41.475819 ==
4305 11:07:41.476202 RX Vref Scan: 0
4306 11:07:41.476496
4307 11:07:41.479366 RX Vref 0 -> 0, step: 1
4308 11:07:41.479877
4309 11:07:41.482546 RX Delay -195 -> 252, step: 8
4310 11:07:41.486173 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4311 11:07:41.489329 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4312 11:07:41.496144 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4313 11:07:41.499163 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4314 11:07:41.503006 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4315 11:07:41.506012 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4316 11:07:41.512457 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4317 11:07:41.515960 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4318 11:07:41.519611 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4319 11:07:41.522573 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4320 11:07:41.525714 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4321 11:07:41.532783 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4322 11:07:41.535819 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4323 11:07:41.539290 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4324 11:07:41.542647 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4325 11:07:41.549835 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4326 11:07:41.550079 ==
4327 11:07:41.552582 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 11:07:41.555892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 11:07:41.556110 ==
4330 11:07:41.556274 DQS Delay:
4331 11:07:41.559244 DQS0 = 0, DQS1 = 0
4332 11:07:41.559467 DQM Delay:
4333 11:07:41.562946 DQM0 = 39, DQM1 = 31
4334 11:07:41.563156 DQ Delay:
4335 11:07:41.566537 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4336 11:07:41.569153 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4337 11:07:41.572827 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4338 11:07:41.575993 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =40
4339 11:07:41.576201
4340 11:07:41.576362
4341 11:07:41.582819 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4342 11:07:41.586559 CH0 RK1: MR19=808, MR18=4A2D
4343 11:07:41.592695 CH0_RK1: MR19=0x808, MR18=0x4A2D, DQSOSC=395, MR23=63, INC=168, DEC=112
4344 11:07:41.596449 [RxdqsGatingPostProcess] freq 600
4345 11:07:41.603087 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 11:07:41.606424 Pre-setting of DQS Precalculation
4347 11:07:41.609662 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 11:07:41.610248 ==
4349 11:07:41.612660 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 11:07:41.616352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 11:07:41.616771 ==
4352 11:07:41.622622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 11:07:41.629160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4354 11:07:41.632735 [CA 0] Center 35 (5~66) winsize 62
4355 11:07:41.636015 [CA 1] Center 35 (5~66) winsize 62
4356 11:07:41.639105 [CA 2] Center 34 (3~65) winsize 63
4357 11:07:41.643353 [CA 3] Center 33 (3~64) winsize 62
4358 11:07:41.646607 [CA 4] Center 34 (3~65) winsize 63
4359 11:07:41.649325 [CA 5] Center 33 (3~64) winsize 62
4360 11:07:41.649455
4361 11:07:41.652780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4362 11:07:41.652876
4363 11:07:41.655708 [CATrainingPosCal] consider 1 rank data
4364 11:07:41.659617 u2DelayCellTimex100 = 270/100 ps
4365 11:07:41.662560 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 11:07:41.666640 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 11:07:41.670131 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4368 11:07:41.672959 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4369 11:07:41.676417 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4370 11:07:41.679269 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 11:07:41.679351
4372 11:07:41.682910 CA PerBit enable=1, Macro0, CA PI delay=33
4373 11:07:41.686182
4374 11:07:41.686283 [CBTSetCACLKResult] CA Dly = 33
4375 11:07:41.689316 CS Dly: 4 (0~35)
4376 11:07:41.689417 ==
4377 11:07:41.692949 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 11:07:41.696354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 11:07:41.696437 ==
4380 11:07:41.702681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 11:07:41.709396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4382 11:07:41.713077 [CA 0] Center 35 (5~66) winsize 62
4383 11:07:41.716321 [CA 1] Center 35 (5~66) winsize 62
4384 11:07:41.720075 [CA 2] Center 34 (3~65) winsize 63
4385 11:07:41.722948 [CA 3] Center 34 (3~65) winsize 63
4386 11:07:41.726240 [CA 4] Center 34 (3~65) winsize 63
4387 11:07:41.730550 [CA 5] Center 33 (3~64) winsize 62
4388 11:07:41.730738
4389 11:07:41.732832 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4390 11:07:41.732927
4391 11:07:41.736447 [CATrainingPosCal] consider 2 rank data
4392 11:07:41.739549 u2DelayCellTimex100 = 270/100 ps
4393 11:07:41.742838 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 11:07:41.746274 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 11:07:41.750040 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4396 11:07:41.752929 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 11:07:41.756020 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4398 11:07:41.760063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 11:07:41.760152
4400 11:07:41.763378 CA PerBit enable=1, Macro0, CA PI delay=33
4401 11:07:41.763455
4402 11:07:41.766065 [CBTSetCACLKResult] CA Dly = 33
4403 11:07:41.769885 CS Dly: 5 (0~37)
4404 11:07:41.769961
4405 11:07:41.773490 ----->DramcWriteLeveling(PI) begin...
4406 11:07:41.773592 ==
4407 11:07:41.776534 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 11:07:41.779650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 11:07:41.779729 ==
4410 11:07:41.782641 Write leveling (Byte 0): 31 => 31
4411 11:07:41.786394 Write leveling (Byte 1): 31 => 31
4412 11:07:41.789604 DramcWriteLeveling(PI) end<-----
4413 11:07:41.789681
4414 11:07:41.789739 ==
4415 11:07:41.792782 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 11:07:41.796351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 11:07:41.796429 ==
4418 11:07:41.799940 [Gating] SW mode calibration
4419 11:07:41.806522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 11:07:41.813235 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 11:07:41.816269 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 11:07:41.823540 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 11:07:41.826033 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 11:07:41.829872 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4425 11:07:41.833542 0 9 16 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
4426 11:07:41.840185 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:07:41.842935 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4428 11:07:41.846587 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 11:07:41.853460 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 11:07:41.856928 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 11:07:41.860059 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 11:07:41.866613 0 10 12 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4433 11:07:41.869937 0 10 16 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)
4434 11:07:41.873399 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:07:41.879701 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 11:07:41.883746 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 11:07:41.887223 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 11:07:41.893280 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 11:07:41.896587 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 11:07:41.899911 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4441 11:07:41.906564 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:07:41.910262 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:07:41.913650 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:07:41.920261 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:07:41.923327 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:07:41.927081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:07:41.930465 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:07:41.936860 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:07:41.940133 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:07:41.943293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:07:41.950348 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:07:41.953663 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:07:41.956747 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 11:07:41.963703 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 11:07:41.967021 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 11:07:41.970611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 11:07:41.977613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 11:07:41.978002 Total UI for P1: 0, mck2ui 16
4459 11:07:41.980591 best dqsien dly found for B0: ( 0, 13, 14)
4460 11:07:41.983901 Total UI for P1: 0, mck2ui 16
4461 11:07:41.986992 best dqsien dly found for B1: ( 0, 13, 14)
4462 11:07:41.991184 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4463 11:07:41.997616 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4464 11:07:41.998003
4465 11:07:42.000612 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4466 11:07:42.004118 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4467 11:07:42.007337 [Gating] SW calibration Done
4468 11:07:42.007718 ==
4469 11:07:42.010529 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 11:07:42.014141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 11:07:42.014524 ==
4472 11:07:42.014858 RX Vref Scan: 0
4473 11:07:42.015140
4474 11:07:42.017421 RX Vref 0 -> 0, step: 1
4475 11:07:42.017812
4476 11:07:42.020584 RX Delay -230 -> 252, step: 16
4477 11:07:42.024181 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4478 11:07:42.027342 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4479 11:07:42.034091 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4480 11:07:42.037477 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4481 11:07:42.041220 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4482 11:07:42.044137 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4483 11:07:42.051109 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4484 11:07:42.054348 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4485 11:07:42.057805 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4486 11:07:42.061035 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4487 11:07:42.064000 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4488 11:07:42.070906 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4489 11:07:42.074333 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4490 11:07:42.077022 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4491 11:07:42.080696 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4492 11:07:42.087658 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4493 11:07:42.088064 ==
4494 11:07:42.090861 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 11:07:42.094187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 11:07:42.094578 ==
4497 11:07:42.094883 DQS Delay:
4498 11:07:42.097057 DQS0 = 0, DQS1 = 0
4499 11:07:42.097497 DQM Delay:
4500 11:07:42.100564 DQM0 = 42, DQM1 = 33
4501 11:07:42.100952 DQ Delay:
4502 11:07:42.104218 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4503 11:07:42.106979 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4504 11:07:42.110592 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4505 11:07:42.113984 DQ12 =49, DQ13 =41, DQ14 =33, DQ15 =33
4506 11:07:42.114481
4507 11:07:42.114788
4508 11:07:42.115069 ==
4509 11:07:42.117100 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 11:07:42.120349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 11:07:42.120741 ==
4512 11:07:42.123812
4513 11:07:42.124255
4514 11:07:42.124663 TX Vref Scan disable
4515 11:07:42.127556 == TX Byte 0 ==
4516 11:07:42.130642 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4517 11:07:42.133958 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4518 11:07:42.137332 == TX Byte 1 ==
4519 11:07:42.140521 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4520 11:07:42.143808 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4521 11:07:42.144203 ==
4522 11:07:42.147066 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 11:07:42.153701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 11:07:42.154090 ==
4525 11:07:42.154393
4526 11:07:42.154674
4527 11:07:42.154941 TX Vref Scan disable
4528 11:07:42.158578 == TX Byte 0 ==
4529 11:07:42.162031 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4530 11:07:42.165387 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4531 11:07:42.168214 == TX Byte 1 ==
4532 11:07:42.171921 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4533 11:07:42.174906 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4534 11:07:42.178792
4535 11:07:42.179188 [DATLAT]
4536 11:07:42.179491 Freq=600, CH1 RK0
4537 11:07:42.179775
4538 11:07:42.181914 DATLAT Default: 0x9
4539 11:07:42.182407 0, 0xFFFF, sum = 0
4540 11:07:42.185060 1, 0xFFFF, sum = 0
4541 11:07:42.185502 2, 0xFFFF, sum = 0
4542 11:07:42.189029 3, 0xFFFF, sum = 0
4543 11:07:42.189466 4, 0xFFFF, sum = 0
4544 11:07:42.191561 5, 0xFFFF, sum = 0
4545 11:07:42.194774 6, 0xFFFF, sum = 0
4546 11:07:42.195171 7, 0xFFFF, sum = 0
4547 11:07:42.195479 8, 0x0, sum = 1
4548 11:07:42.198501 9, 0x0, sum = 2
4549 11:07:42.198896 10, 0x0, sum = 3
4550 11:07:42.201689 11, 0x0, sum = 4
4551 11:07:42.202084 best_step = 9
4552 11:07:42.202388
4553 11:07:42.202764 ==
4554 11:07:42.205376 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 11:07:42.212088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 11:07:42.212488 ==
4557 11:07:42.212818 RX Vref Scan: 1
4558 11:07:42.213100
4559 11:07:42.215059 RX Vref 0 -> 0, step: 1
4560 11:07:42.215450
4561 11:07:42.218526 RX Delay -195 -> 252, step: 8
4562 11:07:42.218913
4563 11:07:42.222127 Set Vref, RX VrefLevel [Byte0]: 56
4564 11:07:42.225100 [Byte1]: 50
4565 11:07:42.225530
4566 11:07:42.228383 Final RX Vref Byte 0 = 56 to rank0
4567 11:07:42.231820 Final RX Vref Byte 1 = 50 to rank0
4568 11:07:42.235468 Final RX Vref Byte 0 = 56 to rank1
4569 11:07:42.238572 Final RX Vref Byte 1 = 50 to rank1==
4570 11:07:42.241595 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 11:07:42.245412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 11:07:42.245837 ==
4573 11:07:42.248497 DQS Delay:
4574 11:07:42.248884 DQS0 = 0, DQS1 = 0
4575 11:07:42.249223 DQM Delay:
4576 11:07:42.251552 DQM0 = 41, DQM1 = 32
4577 11:07:42.251941 DQ Delay:
4578 11:07:42.254919 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4579 11:07:42.258898 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4580 11:07:42.261823 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4581 11:07:42.265736 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4582 11:07:42.266127
4583 11:07:42.266477
4584 11:07:42.275433 [DQSOSCAuto] RK0, (LSB)MR18= 0x490e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4585 11:07:42.275860 CH1 RK0: MR19=808, MR18=490E
4586 11:07:42.281718 CH1_RK0: MR19=0x808, MR18=0x490E, DQSOSC=396, MR23=63, INC=167, DEC=111
4587 11:07:42.282107
4588 11:07:42.285156 ----->DramcWriteLeveling(PI) begin...
4589 11:07:42.285647 ==
4590 11:07:42.288803 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 11:07:42.295050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 11:07:42.295446 ==
4593 11:07:42.299289 Write leveling (Byte 0): 31 => 31
4594 11:07:42.302318 Write leveling (Byte 1): 31 => 31
4595 11:07:42.302724 DramcWriteLeveling(PI) end<-----
4596 11:07:42.303033
4597 11:07:42.305387 ==
4598 11:07:42.308987 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 11:07:42.311792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 11:07:42.312180 ==
4601 11:07:42.315268 [Gating] SW mode calibration
4602 11:07:42.321914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4603 11:07:42.325609 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4604 11:07:42.331792 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 11:07:42.335747 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 11:07:42.338929 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4607 11:07:42.345434 0 9 12 | B1->B0 | 2f2f 2a2a | 1 0 | (1 1) (0 0)
4608 11:07:42.348704 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 11:07:42.352030 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 11:07:42.358986 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 11:07:42.362132 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 11:07:42.365053 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 11:07:42.372149 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 11:07:42.375194 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4615 11:07:42.378457 0 10 12 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (1 1)
4616 11:07:42.382120 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 11:07:42.388297 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 11:07:42.391944 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 11:07:42.395153 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 11:07:42.401587 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 11:07:42.405446 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 11:07:42.408429 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4623 11:07:42.415224 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4624 11:07:42.419088 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:07:42.421769 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:07:42.429154 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:07:42.431892 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:07:42.435099 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:07:42.441824 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:07:42.445594 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:07:42.448877 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:07:42.455302 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:07:42.458412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:07:42.462200 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 11:07:42.465510 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:07:42.472248 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 11:07:42.475258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 11:07:42.478582 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 11:07:42.485814 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4640 11:07:42.488743 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 11:07:42.492272 Total UI for P1: 0, mck2ui 16
4642 11:07:42.495459 best dqsien dly found for B0: ( 0, 13, 12)
4643 11:07:42.498631 Total UI for P1: 0, mck2ui 16
4644 11:07:42.502007 best dqsien dly found for B1: ( 0, 13, 14)
4645 11:07:42.505280 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4646 11:07:42.508915 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4647 11:07:42.509362
4648 11:07:42.512295 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4649 11:07:42.515097 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4650 11:07:42.518643 [Gating] SW calibration Done
4651 11:07:42.519033 ==
4652 11:07:42.521920 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 11:07:42.529025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 11:07:42.529457 ==
4655 11:07:42.529776 RX Vref Scan: 0
4656 11:07:42.530059
4657 11:07:42.531942 RX Vref 0 -> 0, step: 1
4658 11:07:42.532332
4659 11:07:42.535309 RX Delay -230 -> 252, step: 16
4660 11:07:42.538885 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4661 11:07:42.542411 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4662 11:07:42.545236 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4663 11:07:42.551855 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4664 11:07:42.555116 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4665 11:07:42.558663 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4666 11:07:42.562100 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4667 11:07:42.564956 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4668 11:07:42.571840 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4669 11:07:42.575158 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4670 11:07:42.578909 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4671 11:07:42.582218 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4672 11:07:42.588184 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4673 11:07:42.592325 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4674 11:07:42.595000 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4675 11:07:42.598542 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4676 11:07:42.598931 ==
4677 11:07:42.601462 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 11:07:42.608272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 11:07:42.608668 ==
4680 11:07:42.608971 DQS Delay:
4681 11:07:42.611927 DQS0 = 0, DQS1 = 0
4682 11:07:42.612324 DQM Delay:
4683 11:07:42.612658 DQM0 = 41, DQM1 = 36
4684 11:07:42.615164 DQ Delay:
4685 11:07:42.618325 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4686 11:07:42.622018 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4687 11:07:42.625399 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4688 11:07:42.628730 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4689 11:07:42.629154
4690 11:07:42.629471
4691 11:07:42.629749 ==
4692 11:07:42.631965 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 11:07:42.635240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 11:07:42.635674 ==
4695 11:07:42.635986
4696 11:07:42.636276
4697 11:07:42.638505 TX Vref Scan disable
4698 11:07:42.638893 == TX Byte 0 ==
4699 11:07:42.645248 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4700 11:07:42.648732 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4701 11:07:42.649152 == TX Byte 1 ==
4702 11:07:42.656060 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4703 11:07:42.658345 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4704 11:07:42.658734 ==
4705 11:07:42.661764 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 11:07:42.665175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 11:07:42.665650 ==
4708 11:07:42.665963
4709 11:07:42.666246
4710 11:07:42.668524 TX Vref Scan disable
4711 11:07:42.671739 == TX Byte 0 ==
4712 11:07:42.675276 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4713 11:07:42.682129 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4714 11:07:42.682522 == TX Byte 1 ==
4715 11:07:42.684960 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4716 11:07:42.689397 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4717 11:07:42.692149
4718 11:07:42.692536 [DATLAT]
4719 11:07:42.692836 Freq=600, CH1 RK1
4720 11:07:42.693144
4721 11:07:42.695218 DATLAT Default: 0x9
4722 11:07:42.695608 0, 0xFFFF, sum = 0
4723 11:07:42.699005 1, 0xFFFF, sum = 0
4724 11:07:42.699503 2, 0xFFFF, sum = 0
4725 11:07:42.702041 3, 0xFFFF, sum = 0
4726 11:07:42.702434 4, 0xFFFF, sum = 0
4727 11:07:42.705497 5, 0xFFFF, sum = 0
4728 11:07:42.705889 6, 0xFFFF, sum = 0
4729 11:07:42.708784 7, 0xFFFF, sum = 0
4730 11:07:42.709221 8, 0x0, sum = 1
4731 11:07:42.711928 9, 0x0, sum = 2
4732 11:07:42.712325 10, 0x0, sum = 3
4733 11:07:42.715388 11, 0x0, sum = 4
4734 11:07:42.715934 best_step = 9
4735 11:07:42.716298
4736 11:07:42.716598 ==
4737 11:07:42.718568 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 11:07:42.725380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 11:07:42.725800 ==
4740 11:07:42.726108 RX Vref Scan: 0
4741 11:07:42.726393
4742 11:07:42.728355 RX Vref 0 -> 0, step: 1
4743 11:07:42.728847
4744 11:07:42.731852 RX Delay -179 -> 252, step: 8
4745 11:07:42.735420 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4746 11:07:42.742315 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4747 11:07:42.746439 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4748 11:07:42.748479 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4749 11:07:42.752113 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4750 11:07:42.755502 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4751 11:07:42.762024 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4752 11:07:42.765454 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4753 11:07:42.768638 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4754 11:07:42.772015 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4755 11:07:42.775269 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4756 11:07:42.782088 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4757 11:07:42.785264 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4758 11:07:42.789811 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4759 11:07:42.792862 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4760 11:07:42.798598 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4761 11:07:42.799001 ==
4762 11:07:42.802465 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 11:07:42.805459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 11:07:42.805847 ==
4765 11:07:42.806157 DQS Delay:
4766 11:07:42.809302 DQS0 = 0, DQS1 = 0
4767 11:07:42.809691 DQM Delay:
4768 11:07:42.812361 DQM0 = 38, DQM1 = 32
4769 11:07:42.812753 DQ Delay:
4770 11:07:42.815766 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4771 11:07:42.819057 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4772 11:07:42.822310 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4773 11:07:42.825338 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4774 11:07:42.825725
4775 11:07:42.826031
4776 11:07:42.832221 [DQSOSCAuto] RK1, (LSB)MR18= 0x404e, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
4777 11:07:42.836235 CH1 RK1: MR19=808, MR18=404E
4778 11:07:42.841894 CH1_RK1: MR19=0x808, MR18=0x404E, DQSOSC=395, MR23=63, INC=168, DEC=112
4779 11:07:42.846071 [RxdqsGatingPostProcess] freq 600
4780 11:07:42.852413 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4781 11:07:42.855383 Pre-setting of DQS Precalculation
4782 11:07:42.858701 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4783 11:07:42.865643 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4784 11:07:42.871989 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4785 11:07:42.872407
4786 11:07:42.872731
4787 11:07:42.875669 [Calibration Summary] 1200 Mbps
4788 11:07:42.879148 CH 0, Rank 0
4789 11:07:42.879544 SW Impedance : PASS
4790 11:07:42.882152 DUTY Scan : NO K
4791 11:07:42.886009 ZQ Calibration : PASS
4792 11:07:42.886456 Jitter Meter : NO K
4793 11:07:42.888680 CBT Training : PASS
4794 11:07:42.889240 Write leveling : PASS
4795 11:07:42.892545 RX DQS gating : PASS
4796 11:07:42.895552 RX DQ/DQS(RDDQC) : PASS
4797 11:07:42.895938 TX DQ/DQS : PASS
4798 11:07:42.899048 RX DATLAT : PASS
4799 11:07:42.903002 RX DQ/DQS(Engine): PASS
4800 11:07:42.903388 TX OE : NO K
4801 11:07:42.905643 All Pass.
4802 11:07:42.906027
4803 11:07:42.906328 CH 0, Rank 1
4804 11:07:42.909337 SW Impedance : PASS
4805 11:07:42.909722 DUTY Scan : NO K
4806 11:07:42.912224 ZQ Calibration : PASS
4807 11:07:42.915752 Jitter Meter : NO K
4808 11:07:42.916136 CBT Training : PASS
4809 11:07:42.918957 Write leveling : PASS
4810 11:07:42.922331 RX DQS gating : PASS
4811 11:07:42.922716 RX DQ/DQS(RDDQC) : PASS
4812 11:07:42.926040 TX DQ/DQS : PASS
4813 11:07:42.926589 RX DATLAT : PASS
4814 11:07:42.928673 RX DQ/DQS(Engine): PASS
4815 11:07:42.932523 TX OE : NO K
4816 11:07:42.932923 All Pass.
4817 11:07:42.933271
4818 11:07:42.933554 CH 1, Rank 0
4819 11:07:42.935481 SW Impedance : PASS
4820 11:07:42.939172 DUTY Scan : NO K
4821 11:07:42.939555 ZQ Calibration : PASS
4822 11:07:42.942376 Jitter Meter : NO K
4823 11:07:42.945375 CBT Training : PASS
4824 11:07:42.945807 Write leveling : PASS
4825 11:07:42.948696 RX DQS gating : PASS
4826 11:07:42.952138 RX DQ/DQS(RDDQC) : PASS
4827 11:07:42.952525 TX DQ/DQS : PASS
4828 11:07:42.955834 RX DATLAT : PASS
4829 11:07:42.959435 RX DQ/DQS(Engine): PASS
4830 11:07:42.960018 TX OE : NO K
4831 11:07:42.960423 All Pass.
4832 11:07:42.962284
4833 11:07:42.962668 CH 1, Rank 1
4834 11:07:42.965443 SW Impedance : PASS
4835 11:07:42.965826 DUTY Scan : NO K
4836 11:07:42.968624 ZQ Calibration : PASS
4837 11:07:42.969004 Jitter Meter : NO K
4838 11:07:42.972365 CBT Training : PASS
4839 11:07:42.976144 Write leveling : PASS
4840 11:07:42.976697 RX DQS gating : PASS
4841 11:07:42.979312 RX DQ/DQS(RDDQC) : PASS
4842 11:07:42.982529 TX DQ/DQS : PASS
4843 11:07:42.982912 RX DATLAT : PASS
4844 11:07:42.985783 RX DQ/DQS(Engine): PASS
4845 11:07:42.988871 TX OE : NO K
4846 11:07:42.989615 All Pass.
4847 11:07:42.989976
4848 11:07:42.992317 DramC Write-DBI off
4849 11:07:42.992729 PER_BANK_REFRESH: Hybrid Mode
4850 11:07:42.995590 TX_TRACKING: ON
4851 11:07:43.002228 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4852 11:07:43.005494 [FAST_K] Save calibration result to emmc
4853 11:07:43.012180 dramc_set_vcore_voltage set vcore to 662500
4854 11:07:43.012707 Read voltage for 933, 3
4855 11:07:43.015387 Vio18 = 0
4856 11:07:43.015770 Vcore = 662500
4857 11:07:43.016071 Vdram = 0
4858 11:07:43.018979 Vddq = 0
4859 11:07:43.019366 Vmddr = 0
4860 11:07:43.022490 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4861 11:07:43.028717 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4862 11:07:43.032188 MEM_TYPE=3, freq_sel=17
4863 11:07:43.035562 sv_algorithm_assistance_LP4_1600
4864 11:07:43.038780 ============ PULL DRAM RESETB DOWN ============
4865 11:07:43.042297 ========== PULL DRAM RESETB DOWN end =========
4866 11:07:43.045587 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4867 11:07:43.048638 ===================================
4868 11:07:43.052425 LPDDR4 DRAM CONFIGURATION
4869 11:07:43.055769 ===================================
4870 11:07:43.059246 EX_ROW_EN[0] = 0x0
4871 11:07:43.059629 EX_ROW_EN[1] = 0x0
4872 11:07:43.062141 LP4Y_EN = 0x0
4873 11:07:43.062574 WORK_FSP = 0x0
4874 11:07:43.065977 WL = 0x3
4875 11:07:43.066381 RL = 0x3
4876 11:07:43.069076 BL = 0x2
4877 11:07:43.069486 RPST = 0x0
4878 11:07:43.072317 RD_PRE = 0x0
4879 11:07:43.072729 WR_PRE = 0x1
4880 11:07:43.075576 WR_PST = 0x0
4881 11:07:43.076023 DBI_WR = 0x0
4882 11:07:43.079030 DBI_RD = 0x0
4883 11:07:43.079470 OTF = 0x1
4884 11:07:43.082614 ===================================
4885 11:07:43.085963 ===================================
4886 11:07:43.089584 ANA top config
4887 11:07:43.092281 ===================================
4888 11:07:43.095584 DLL_ASYNC_EN = 0
4889 11:07:43.096056 ALL_SLAVE_EN = 1
4890 11:07:43.099027 NEW_RANK_MODE = 1
4891 11:07:43.102136 DLL_IDLE_MODE = 1
4892 11:07:43.105673 LP45_APHY_COMB_EN = 1
4893 11:07:43.106172 TX_ODT_DIS = 1
4894 11:07:43.109017 NEW_8X_MODE = 1
4895 11:07:43.112433 ===================================
4896 11:07:43.115433 ===================================
4897 11:07:43.119145 data_rate = 1866
4898 11:07:43.123193 CKR = 1
4899 11:07:43.126053 DQ_P2S_RATIO = 8
4900 11:07:43.129369 ===================================
4901 11:07:43.132536 CA_P2S_RATIO = 8
4902 11:07:43.132929 DQ_CA_OPEN = 0
4903 11:07:43.135522 DQ_SEMI_OPEN = 0
4904 11:07:43.139287 CA_SEMI_OPEN = 0
4905 11:07:43.142308 CA_FULL_RATE = 0
4906 11:07:43.146410 DQ_CKDIV4_EN = 1
4907 11:07:43.149171 CA_CKDIV4_EN = 1
4908 11:07:43.149559 CA_PREDIV_EN = 0
4909 11:07:43.152720 PH8_DLY = 0
4910 11:07:43.155773 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4911 11:07:43.159342 DQ_AAMCK_DIV = 4
4912 11:07:43.162546 CA_AAMCK_DIV = 4
4913 11:07:43.162927 CA_ADMCK_DIV = 4
4914 11:07:43.165578 DQ_TRACK_CA_EN = 0
4915 11:07:43.168980 CA_PICK = 933
4916 11:07:43.173040 CA_MCKIO = 933
4917 11:07:43.176393 MCKIO_SEMI = 0
4918 11:07:43.179347 PLL_FREQ = 3732
4919 11:07:43.182588 DQ_UI_PI_RATIO = 32
4920 11:07:43.183010 CA_UI_PI_RATIO = 0
4921 11:07:43.185779 ===================================
4922 11:07:43.189637 ===================================
4923 11:07:43.192575 memory_type:LPDDR4
4924 11:07:43.195886 GP_NUM : 10
4925 11:07:43.196273 SRAM_EN : 1
4926 11:07:43.199366 MD32_EN : 0
4927 11:07:43.202751 ===================================
4928 11:07:43.205737 [ANA_INIT] >>>>>>>>>>>>>>
4929 11:07:43.206184 <<<<<< [CONFIGURE PHASE]: ANA_TX
4930 11:07:43.212842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4931 11:07:43.215732 ===================================
4932 11:07:43.216123 data_rate = 1866,PCW = 0X8f00
4933 11:07:43.219304 ===================================
4934 11:07:43.222477 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4935 11:07:43.229223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 11:07:43.235778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 11:07:43.239186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4938 11:07:43.242814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4939 11:07:43.245817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4940 11:07:43.249084 [ANA_INIT] flow start
4941 11:07:43.249525 [ANA_INIT] PLL >>>>>>>>
4942 11:07:43.252696 [ANA_INIT] PLL <<<<<<<<
4943 11:07:43.256214 [ANA_INIT] MIDPI >>>>>>>>
4944 11:07:43.259029 [ANA_INIT] MIDPI <<<<<<<<
4945 11:07:43.259419 [ANA_INIT] DLL >>>>>>>>
4946 11:07:43.262639 [ANA_INIT] flow end
4947 11:07:43.266375 ============ LP4 DIFF to SE enter ============
4948 11:07:43.269082 ============ LP4 DIFF to SE exit ============
4949 11:07:43.273027 [ANA_INIT] <<<<<<<<<<<<<
4950 11:07:43.275867 [Flow] Enable top DCM control >>>>>
4951 11:07:43.279226 [Flow] Enable top DCM control <<<<<
4952 11:07:43.282489 Enable DLL master slave shuffle
4953 11:07:43.286157 ==============================================================
4954 11:07:43.289417 Gating Mode config
4955 11:07:43.296247 ==============================================================
4956 11:07:43.296633 Config description:
4957 11:07:43.305891 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4958 11:07:43.312879 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4959 11:07:43.319690 SELPH_MODE 0: By rank 1: By Phase
4960 11:07:43.322507 ==============================================================
4961 11:07:43.325925 GAT_TRACK_EN = 1
4962 11:07:43.329482 RX_GATING_MODE = 2
4963 11:07:43.332558 RX_GATING_TRACK_MODE = 2
4964 11:07:43.336470 SELPH_MODE = 1
4965 11:07:43.339307 PICG_EARLY_EN = 1
4966 11:07:43.342995 VALID_LAT_VALUE = 1
4967 11:07:43.345944 ==============================================================
4968 11:07:43.349755 Enter into Gating configuration >>>>
4969 11:07:43.352592 Exit from Gating configuration <<<<
4970 11:07:43.356182 Enter into DVFS_PRE_config >>>>>
4971 11:07:43.369389 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4972 11:07:43.369781 Exit from DVFS_PRE_config <<<<<
4973 11:07:43.372675 Enter into PICG configuration >>>>
4974 11:07:43.376251 Exit from PICG configuration <<<<
4975 11:07:43.379326 [RX_INPUT] configuration >>>>>
4976 11:07:43.383111 [RX_INPUT] configuration <<<<<
4977 11:07:43.389464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4978 11:07:43.392853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4979 11:07:43.399508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 11:07:43.405967 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 11:07:43.412822 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 11:07:43.419566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 11:07:43.422848 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4984 11:07:43.426270 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4985 11:07:43.429457 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4986 11:07:43.436173 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4987 11:07:43.439693 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4988 11:07:43.442920 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 11:07:43.446868 ===================================
4990 11:07:43.450208 LPDDR4 DRAM CONFIGURATION
4991 11:07:43.452576 ===================================
4992 11:07:43.452959 EX_ROW_EN[0] = 0x0
4993 11:07:43.456549 EX_ROW_EN[1] = 0x0
4994 11:07:43.457013 LP4Y_EN = 0x0
4995 11:07:43.460023 WORK_FSP = 0x0
4996 11:07:43.460405 WL = 0x3
4997 11:07:43.463475 RL = 0x3
4998 11:07:43.463979 BL = 0x2
4999 11:07:43.466283 RPST = 0x0
5000 11:07:43.466679 RD_PRE = 0x0
5001 11:07:43.470304 WR_PRE = 0x1
5002 11:07:43.470686 WR_PST = 0x0
5003 11:07:43.472931 DBI_WR = 0x0
5004 11:07:43.476373 DBI_RD = 0x0
5005 11:07:43.476898 OTF = 0x1
5006 11:07:43.479649 ===================================
5007 11:07:43.483118 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5008 11:07:43.486297 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5009 11:07:43.492828 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 11:07:43.496615 ===================================
5011 11:07:43.496995 LPDDR4 DRAM CONFIGURATION
5012 11:07:43.499659 ===================================
5013 11:07:43.502911 EX_ROW_EN[0] = 0x10
5014 11:07:43.506488 EX_ROW_EN[1] = 0x0
5015 11:07:43.506984 LP4Y_EN = 0x0
5016 11:07:43.509603 WORK_FSP = 0x0
5017 11:07:43.509986 WL = 0x3
5018 11:07:43.512806 RL = 0x3
5019 11:07:43.513217 BL = 0x2
5020 11:07:43.516227 RPST = 0x0
5021 11:07:43.516612 RD_PRE = 0x0
5022 11:07:43.519900 WR_PRE = 0x1
5023 11:07:43.520284 WR_PST = 0x0
5024 11:07:43.522765 DBI_WR = 0x0
5025 11:07:43.523148 DBI_RD = 0x0
5026 11:07:43.526172 OTF = 0x1
5027 11:07:43.529594 ===================================
5028 11:07:43.536203 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5029 11:07:43.539735 nWR fixed to 30
5030 11:07:43.540239 [ModeRegInit_LP4] CH0 RK0
5031 11:07:43.543407 [ModeRegInit_LP4] CH0 RK1
5032 11:07:43.546094 [ModeRegInit_LP4] CH1 RK0
5033 11:07:43.549656 [ModeRegInit_LP4] CH1 RK1
5034 11:07:43.550035 match AC timing 9
5035 11:07:43.553226 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5036 11:07:43.559586 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5037 11:07:43.563093 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5038 11:07:43.569875 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5039 11:07:43.573514 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5040 11:07:43.573898 ==
5041 11:07:43.576906 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 11:07:43.579868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 11:07:43.580253 ==
5044 11:07:43.586353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 11:07:43.593229 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5046 11:07:43.596293 [CA 0] Center 38 (8~69) winsize 62
5047 11:07:43.599631 [CA 1] Center 38 (7~69) winsize 63
5048 11:07:43.603141 [CA 2] Center 35 (5~66) winsize 62
5049 11:07:43.606061 [CA 3] Center 35 (5~66) winsize 62
5050 11:07:43.609629 [CA 4] Center 34 (4~64) winsize 61
5051 11:07:43.612752 [CA 5] Center 34 (4~64) winsize 61
5052 11:07:43.613274
5053 11:07:43.616198 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5054 11:07:43.616682
5055 11:07:43.619932 [CATrainingPosCal] consider 1 rank data
5056 11:07:43.623054 u2DelayCellTimex100 = 270/100 ps
5057 11:07:43.626133 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5058 11:07:43.629693 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5059 11:07:43.633230 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5060 11:07:43.636061 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5061 11:07:43.639801 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5062 11:07:43.643285 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5063 11:07:43.643762
5064 11:07:43.646673 CA PerBit enable=1, Macro0, CA PI delay=34
5065 11:07:43.647145
5066 11:07:43.649833 [CBTSetCACLKResult] CA Dly = 34
5067 11:07:43.652912 CS Dly: 6 (0~37)
5068 11:07:43.653377 ==
5069 11:07:43.656703 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 11:07:43.659607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 11:07:43.659993 ==
5072 11:07:43.666292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 11:07:43.672815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5074 11:07:43.676541 [CA 0] Center 38 (7~69) winsize 63
5075 11:07:43.679548 [CA 1] Center 38 (7~69) winsize 63
5076 11:07:43.682841 [CA 2] Center 35 (5~66) winsize 62
5077 11:07:43.686665 [CA 3] Center 35 (5~66) winsize 62
5078 11:07:43.689821 [CA 4] Center 34 (4~64) winsize 61
5079 11:07:43.690204 [CA 5] Center 33 (3~64) winsize 62
5080 11:07:43.693225
5081 11:07:43.696630 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5082 11:07:43.697167
5083 11:07:43.700115 [CATrainingPosCal] consider 2 rank data
5084 11:07:43.703302 u2DelayCellTimex100 = 270/100 ps
5085 11:07:43.706199 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5086 11:07:43.709633 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5087 11:07:43.713216 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5088 11:07:43.716157 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5089 11:07:43.719586 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5090 11:07:43.722992 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5091 11:07:43.723382
5092 11:07:43.726463 CA PerBit enable=1, Macro0, CA PI delay=34
5093 11:07:43.726852
5094 11:07:43.729746 [CBTSetCACLKResult] CA Dly = 34
5095 11:07:43.733180 CS Dly: 7 (0~39)
5096 11:07:43.733572
5097 11:07:43.736356 ----->DramcWriteLeveling(PI) begin...
5098 11:07:43.736748 ==
5099 11:07:43.739677 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 11:07:43.743449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 11:07:43.743951 ==
5102 11:07:43.745926 Write leveling (Byte 0): 31 => 31
5103 11:07:43.750182 Write leveling (Byte 1): 27 => 27
5104 11:07:43.752859 DramcWriteLeveling(PI) end<-----
5105 11:07:43.753328
5106 11:07:43.753667 ==
5107 11:07:43.756385 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 11:07:43.760150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 11:07:43.760663 ==
5110 11:07:43.762634 [Gating] SW mode calibration
5111 11:07:43.769323 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5112 11:07:43.776824 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5113 11:07:43.779102 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5114 11:07:43.786419 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5115 11:07:43.789447 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 11:07:43.792505 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 11:07:43.799052 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 11:07:43.802583 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 11:07:43.805993 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 11:07:43.809151 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5121 11:07:43.816171 0 15 0 | B1->B0 | 3131 2727 | 0 0 | (0 0) (0 1)
5122 11:07:43.819545 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:07:43.822514 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 11:07:43.829447 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 11:07:43.832693 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 11:07:43.835904 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 11:07:43.842528 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 11:07:43.846223 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5129 11:07:43.849862 1 0 0 | B1->B0 | 2f2f 3e3e | 0 0 | (1 1) (0 0)
5130 11:07:43.856362 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:07:43.859887 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 11:07:43.862951 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 11:07:43.869856 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 11:07:43.872884 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 11:07:43.876169 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 11:07:43.882716 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 11:07:43.886056 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5138 11:07:43.889710 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5139 11:07:43.892915 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:07:43.899337 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:07:43.902934 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:07:43.906122 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:07:43.912946 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:07:43.916166 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:07:43.919940 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:07:43.926666 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:07:43.929833 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:07:43.932821 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 11:07:43.939928 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 11:07:43.942968 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 11:07:43.947371 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 11:07:43.953222 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5153 11:07:43.956764 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5154 11:07:43.959863 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5155 11:07:43.966804 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 11:07:43.967313 Total UI for P1: 0, mck2ui 16
5157 11:07:43.969573 best dqsien dly found for B0: ( 1, 3, 0)
5158 11:07:43.973406 Total UI for P1: 0, mck2ui 16
5159 11:07:43.976196 best dqsien dly found for B1: ( 1, 3, 4)
5160 11:07:43.979442 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5161 11:07:43.982675 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5162 11:07:43.987151
5163 11:07:43.989920 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5164 11:07:43.992811 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5165 11:07:43.996166 [Gating] SW calibration Done
5166 11:07:43.996551 ==
5167 11:07:43.999734 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 11:07:44.003076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 11:07:44.003462 ==
5170 11:07:44.003763 RX Vref Scan: 0
5171 11:07:44.004039
5172 11:07:44.006131 RX Vref 0 -> 0, step: 1
5173 11:07:44.006528
5174 11:07:44.009824 RX Delay -80 -> 252, step: 8
5175 11:07:44.012698 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5176 11:07:44.016446 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5177 11:07:44.019576 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5178 11:07:44.026460 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5179 11:07:44.029271 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5180 11:07:44.033317 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5181 11:07:44.036139 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5182 11:07:44.039810 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5183 11:07:44.043411 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5184 11:07:44.049958 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5185 11:07:44.053357 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5186 11:07:44.056653 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5187 11:07:44.059812 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5188 11:07:44.063115 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5189 11:07:44.066695 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5190 11:07:44.073448 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5191 11:07:44.073959 ==
5192 11:07:44.077334 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 11:07:44.080064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 11:07:44.080490 ==
5195 11:07:44.080827 DQS Delay:
5196 11:07:44.083182 DQS0 = 0, DQS1 = 0
5197 11:07:44.083608 DQM Delay:
5198 11:07:44.086516 DQM0 = 98, DQM1 = 87
5199 11:07:44.087022 DQ Delay:
5200 11:07:44.089878 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5201 11:07:44.093298 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5202 11:07:44.096713 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5203 11:07:44.101110 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5204 11:07:44.101585
5205 11:07:44.101922
5206 11:07:44.102230 ==
5207 11:07:44.103247 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 11:07:44.106362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 11:07:44.106806 ==
5210 11:07:44.107138
5211 11:07:44.109911
5212 11:07:44.110333 TX Vref Scan disable
5213 11:07:44.113548 == TX Byte 0 ==
5214 11:07:44.117423 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5215 11:07:44.120532 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5216 11:07:44.124115 == TX Byte 1 ==
5217 11:07:44.126602 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5218 11:07:44.130707 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5219 11:07:44.131218 ==
5220 11:07:44.133515 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 11:07:44.140306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 11:07:44.140814 ==
5223 11:07:44.141213
5224 11:07:44.141537
5225 11:07:44.141835 TX Vref Scan disable
5226 11:07:44.143977 == TX Byte 0 ==
5227 11:07:44.147704 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5228 11:07:44.150841 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5229 11:07:44.154247 == TX Byte 1 ==
5230 11:07:44.157586 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5231 11:07:44.160964 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5232 11:07:44.163735
5233 11:07:44.164161 [DATLAT]
5234 11:07:44.164493 Freq=933, CH0 RK0
5235 11:07:44.164805
5236 11:07:44.167845 DATLAT Default: 0xd
5237 11:07:44.168363 0, 0xFFFF, sum = 0
5238 11:07:44.170618 1, 0xFFFF, sum = 0
5239 11:07:44.171130 2, 0xFFFF, sum = 0
5240 11:07:44.174148 3, 0xFFFF, sum = 0
5241 11:07:44.174658 4, 0xFFFF, sum = 0
5242 11:07:44.177538 5, 0xFFFF, sum = 0
5243 11:07:44.180465 6, 0xFFFF, sum = 0
5244 11:07:44.180904 7, 0xFFFF, sum = 0
5245 11:07:44.184003 8, 0xFFFF, sum = 0
5246 11:07:44.184586 9, 0xFFFF, sum = 0
5247 11:07:44.187608 10, 0x0, sum = 1
5248 11:07:44.188046 11, 0x0, sum = 2
5249 11:07:44.188389 12, 0x0, sum = 3
5250 11:07:44.190673 13, 0x0, sum = 4
5251 11:07:44.191106 best_step = 11
5252 11:07:44.191434
5253 11:07:44.191740 ==
5254 11:07:44.193916 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 11:07:44.200666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 11:07:44.201190 ==
5257 11:07:44.201527 RX Vref Scan: 1
5258 11:07:44.201813
5259 11:07:44.204029 RX Vref 0 -> 0, step: 1
5260 11:07:44.204438
5261 11:07:44.207212 RX Delay -61 -> 252, step: 4
5262 11:07:44.207604
5263 11:07:44.210908 Set Vref, RX VrefLevel [Byte0]: 52
5264 11:07:44.213985 [Byte1]: 51
5265 11:07:44.214368
5266 11:07:44.217371 Final RX Vref Byte 0 = 52 to rank0
5267 11:07:44.220685 Final RX Vref Byte 1 = 51 to rank0
5268 11:07:44.224456 Final RX Vref Byte 0 = 52 to rank1
5269 11:07:44.227211 Final RX Vref Byte 1 = 51 to rank1==
5270 11:07:44.230833 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:07:44.234287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:07:44.234719 ==
5273 11:07:44.237617 DQS Delay:
5274 11:07:44.237998 DQS0 = 0, DQS1 = 0
5275 11:07:44.238298 DQM Delay:
5276 11:07:44.240920 DQM0 = 97, DQM1 = 88
5277 11:07:44.241330 DQ Delay:
5278 11:07:44.244093 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5279 11:07:44.247159 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5280 11:07:44.250806 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5281 11:07:44.253987 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =98
5282 11:07:44.254601
5283 11:07:44.254977
5284 11:07:44.264177 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5285 11:07:44.267362 CH0 RK0: MR19=504, MR18=13FE
5286 11:07:44.270790 CH0_RK0: MR19=0x504, MR18=0x13FE, DQSOSC=415, MR23=63, INC=62, DEC=41
5287 11:07:44.271411
5288 11:07:44.274039 ----->DramcWriteLeveling(PI) begin...
5289 11:07:44.277712 ==
5290 11:07:44.278192 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 11:07:44.283932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 11:07:44.284319 ==
5293 11:07:44.287428 Write leveling (Byte 0): 30 => 30
5294 11:07:44.290836 Write leveling (Byte 1): 30 => 30
5295 11:07:44.294102 DramcWriteLeveling(PI) end<-----
5296 11:07:44.294488
5297 11:07:44.294797 ==
5298 11:07:44.297253 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 11:07:44.300937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 11:07:44.301406 ==
5301 11:07:44.304518 [Gating] SW mode calibration
5302 11:07:44.310653 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5303 11:07:44.314285 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5304 11:07:44.320648 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5305 11:07:44.324138 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5306 11:07:44.327182 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 11:07:44.334061 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 11:07:44.337328 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 11:07:44.340841 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 11:07:44.347190 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5311 11:07:44.351005 0 14 28 | B1->B0 | 3232 2d2d | 1 0 | (1 1) (0 0)
5312 11:07:44.354171 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5313 11:07:44.360519 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 11:07:44.364048 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 11:07:44.367278 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 11:07:44.373812 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 11:07:44.377288 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 11:07:44.381248 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 11:07:44.384544 0 15 28 | B1->B0 | 2a2a 3838 | 0 0 | (0 0) (0 0)
5320 11:07:44.390945 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
5321 11:07:44.395034 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 11:07:44.397437 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 11:07:44.404304 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 11:07:44.407962 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 11:07:44.411606 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 11:07:44.418091 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 11:07:44.421396 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5328 11:07:44.424653 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5329 11:07:44.431785 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:07:44.434555 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:07:44.437763 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:07:44.444333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:07:44.447990 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:07:44.450998 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:07:44.457765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:07:44.461397 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 11:07:44.464610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 11:07:44.471085 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 11:07:44.474584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 11:07:44.478258 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 11:07:44.481031 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 11:07:44.488617 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 11:07:44.491459 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5344 11:07:44.494373 Total UI for P1: 0, mck2ui 16
5345 11:07:44.497949 best dqsien dly found for B0: ( 1, 2, 26)
5346 11:07:44.500918 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5347 11:07:44.507479 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 11:07:44.511627 Total UI for P1: 0, mck2ui 16
5349 11:07:44.514544 best dqsien dly found for B1: ( 1, 2, 30)
5350 11:07:44.517816 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5351 11:07:44.521391 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5352 11:07:44.521904
5353 11:07:44.524456 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5354 11:07:44.527490 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5355 11:07:44.531112 [Gating] SW calibration Done
5356 11:07:44.531528 ==
5357 11:07:44.534866 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 11:07:44.537445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 11:07:44.537863 ==
5360 11:07:44.541650 RX Vref Scan: 0
5361 11:07:44.542117
5362 11:07:44.542420 RX Vref 0 -> 0, step: 1
5363 11:07:44.542695
5364 11:07:44.544267 RX Delay -80 -> 252, step: 8
5365 11:07:44.548350 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5366 11:07:44.554094 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5367 11:07:44.558007 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5368 11:07:44.561239 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5369 11:07:44.564524 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5370 11:07:44.567997 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5371 11:07:44.571585 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5372 11:07:44.574249 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5373 11:07:44.581340 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5374 11:07:44.584387 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5375 11:07:44.588224 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5376 11:07:44.591804 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5377 11:07:44.594466 iDelay=200, Bit 12, Center 87 (-8 ~ 183) 192
5378 11:07:44.601566 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5379 11:07:44.604376 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5380 11:07:44.607775 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5381 11:07:44.608160 ==
5382 11:07:44.611075 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 11:07:44.614707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 11:07:44.615171 ==
5385 11:07:44.617666 DQS Delay:
5386 11:07:44.618055 DQS0 = 0, DQS1 = 0
5387 11:07:44.618354 DQM Delay:
5388 11:07:44.620882 DQM0 = 97, DQM1 = 87
5389 11:07:44.621370 DQ Delay:
5390 11:07:44.624503 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5391 11:07:44.627688 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5392 11:07:44.631442 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5393 11:07:44.635019 DQ12 =87, DQ13 =91, DQ14 =99, DQ15 =95
5394 11:07:44.635411
5395 11:07:44.635711
5396 11:07:44.638011 ==
5397 11:07:44.638434 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 11:07:44.644003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 11:07:44.644457 ==
5400 11:07:44.644764
5401 11:07:44.645039
5402 11:07:44.647852 TX Vref Scan disable
5403 11:07:44.648232 == TX Byte 0 ==
5404 11:07:44.651015 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5405 11:07:44.657823 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5406 11:07:44.658306 == TX Byte 1 ==
5407 11:07:44.662137 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5408 11:07:44.667859 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5409 11:07:44.668325 ==
5410 11:07:44.670908 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 11:07:44.674264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 11:07:44.674651 ==
5413 11:07:44.674954
5414 11:07:44.675230
5415 11:07:44.677537 TX Vref Scan disable
5416 11:07:44.681153 == TX Byte 0 ==
5417 11:07:44.684187 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5418 11:07:44.687575 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5419 11:07:44.690797 == TX Byte 1 ==
5420 11:07:44.693940 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5421 11:07:44.697511 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5422 11:07:44.697898
5423 11:07:44.698195 [DATLAT]
5424 11:07:44.700624 Freq=933, CH0 RK1
5425 11:07:44.701010
5426 11:07:44.701403 DATLAT Default: 0xb
5427 11:07:44.704277 0, 0xFFFF, sum = 0
5428 11:07:44.704668 1, 0xFFFF, sum = 0
5429 11:07:44.708392 2, 0xFFFF, sum = 0
5430 11:07:44.711012 3, 0xFFFF, sum = 0
5431 11:07:44.711402 4, 0xFFFF, sum = 0
5432 11:07:44.714147 5, 0xFFFF, sum = 0
5433 11:07:44.714537 6, 0xFFFF, sum = 0
5434 11:07:44.717798 7, 0xFFFF, sum = 0
5435 11:07:44.718185 8, 0xFFFF, sum = 0
5436 11:07:44.721032 9, 0xFFFF, sum = 0
5437 11:07:44.721460 10, 0x0, sum = 1
5438 11:07:44.724509 11, 0x0, sum = 2
5439 11:07:44.724897 12, 0x0, sum = 3
5440 11:07:44.725232 13, 0x0, sum = 4
5441 11:07:44.728073 best_step = 11
5442 11:07:44.728450
5443 11:07:44.728744 ==
5444 11:07:44.731040 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 11:07:44.734274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 11:07:44.734657 ==
5447 11:07:44.737570 RX Vref Scan: 0
5448 11:07:44.737955
5449 11:07:44.740751 RX Vref 0 -> 0, step: 1
5450 11:07:44.741272
5451 11:07:44.741588 RX Delay -61 -> 252, step: 4
5452 11:07:44.748589 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5453 11:07:44.752163 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5454 11:07:44.754957 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5455 11:07:44.758765 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5456 11:07:44.762101 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5457 11:07:44.765581 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5458 11:07:44.772918 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5459 11:07:44.775761 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5460 11:07:44.778599 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5461 11:07:44.782318 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5462 11:07:44.785755 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5463 11:07:44.788682 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5464 11:07:44.795287 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5465 11:07:44.798636 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5466 11:07:44.802947 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5467 11:07:44.805387 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5468 11:07:44.805775 ==
5469 11:07:44.808736 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 11:07:44.812377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 11:07:44.816110 ==
5472 11:07:44.816495 DQS Delay:
5473 11:07:44.816793 DQS0 = 0, DQS1 = 0
5474 11:07:44.818954 DQM Delay:
5475 11:07:44.819424 DQM0 = 95, DQM1 = 87
5476 11:07:44.822429 DQ Delay:
5477 11:07:44.822810 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5478 11:07:44.825665 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5479 11:07:44.828670 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5480 11:07:44.832123 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =92
5481 11:07:44.835615
5482 11:07:44.836097
5483 11:07:44.842106 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
5484 11:07:44.845281 CH0 RK1: MR19=505, MR18=210F
5485 11:07:44.851724 CH0_RK1: MR19=0x505, MR18=0x210F, DQSOSC=411, MR23=63, INC=64, DEC=42
5486 11:07:44.855226 [RxdqsGatingPostProcess] freq 933
5487 11:07:44.858655 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5488 11:07:44.861922 best DQS0 dly(2T, 0.5T) = (0, 11)
5489 11:07:44.865787 best DQS1 dly(2T, 0.5T) = (0, 11)
5490 11:07:44.868661 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5491 11:07:44.872030 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5492 11:07:44.875658 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 11:07:44.878824 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 11:07:44.882471 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 11:07:44.885676 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 11:07:44.888991 Pre-setting of DQS Precalculation
5497 11:07:44.892565 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5498 11:07:44.893048 ==
5499 11:07:44.895703 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 11:07:44.899096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 11:07:44.901929 ==
5502 11:07:44.905484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5503 11:07:44.912163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5504 11:07:44.915630 [CA 0] Center 36 (6~67) winsize 62
5505 11:07:44.919324 [CA 1] Center 36 (6~67) winsize 62
5506 11:07:44.921901 [CA 2] Center 33 (3~64) winsize 62
5507 11:07:44.925858 [CA 3] Center 33 (3~64) winsize 62
5508 11:07:44.928373 [CA 4] Center 34 (4~64) winsize 61
5509 11:07:44.932195 [CA 5] Center 33 (3~64) winsize 62
5510 11:07:44.932578
5511 11:07:44.935329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5512 11:07:44.935714
5513 11:07:44.939029 [CATrainingPosCal] consider 1 rank data
5514 11:07:44.941879 u2DelayCellTimex100 = 270/100 ps
5515 11:07:44.945510 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5516 11:07:44.948698 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 11:07:44.951865 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5518 11:07:44.955607 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5519 11:07:44.959771 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5520 11:07:44.966086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5521 11:07:44.966568
5522 11:07:44.968846 CA PerBit enable=1, Macro0, CA PI delay=33
5523 11:07:44.969265
5524 11:07:44.972250 [CBTSetCACLKResult] CA Dly = 33
5525 11:07:44.972707 CS Dly: 5 (0~36)
5526 11:07:44.973010 ==
5527 11:07:44.975561 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 11:07:44.979519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 11:07:44.979903 ==
5530 11:07:44.986025 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 11:07:44.992321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5532 11:07:44.996040 [CA 0] Center 36 (6~67) winsize 62
5533 11:07:44.998661 [CA 1] Center 36 (6~67) winsize 62
5534 11:07:45.002101 [CA 2] Center 33 (3~64) winsize 62
5535 11:07:45.005661 [CA 3] Center 33 (3~64) winsize 62
5536 11:07:45.009096 [CA 4] Center 33 (3~64) winsize 62
5537 11:07:45.012026 [CA 5] Center 32 (2~63) winsize 62
5538 11:07:45.012413
5539 11:07:45.016061 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5540 11:07:45.016441
5541 11:07:45.018771 [CATrainingPosCal] consider 2 rank data
5542 11:07:45.022495 u2DelayCellTimex100 = 270/100 ps
5543 11:07:45.025495 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5544 11:07:45.029213 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5545 11:07:45.032653 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5546 11:07:45.035484 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 11:07:45.038953 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5548 11:07:45.043419 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5549 11:07:45.043881
5550 11:07:45.048831 CA PerBit enable=1, Macro0, CA PI delay=33
5551 11:07:45.049347
5552 11:07:45.052824 [CBTSetCACLKResult] CA Dly = 33
5553 11:07:45.053332 CS Dly: 6 (0~38)
5554 11:07:45.053639
5555 11:07:45.055523 ----->DramcWriteLeveling(PI) begin...
5556 11:07:45.055912 ==
5557 11:07:45.059241 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 11:07:45.063137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 11:07:45.063608 ==
5560 11:07:45.065742 Write leveling (Byte 0): 28 => 28
5561 11:07:45.069104 Write leveling (Byte 1): 28 => 28
5562 11:07:45.072816 DramcWriteLeveling(PI) end<-----
5563 11:07:45.073237
5564 11:07:45.073542 ==
5565 11:07:45.075518 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 11:07:45.082219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 11:07:45.082686 ==
5568 11:07:45.083023 [Gating] SW mode calibration
5569 11:07:45.092315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5570 11:07:45.096249 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5571 11:07:45.099080 0 14 0 | B1->B0 | 3232 3232 | 1 1 | (1 1) (0 0)
5572 11:07:45.105854 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 11:07:45.108867 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 11:07:45.112215 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 11:07:45.119384 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 11:07:45.122745 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 11:07:45.125824 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 11:07:45.132903 0 14 28 | B1->B0 | 3030 3131 | 1 0 | (1 0) (0 1)
5579 11:07:45.135682 0 15 0 | B1->B0 | 2828 2828 | 0 0 | (0 0) (1 1)
5580 11:07:45.139786 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 11:07:45.145936 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 11:07:45.148893 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 11:07:45.152409 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 11:07:45.158980 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5585 11:07:45.162615 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 11:07:45.165676 0 15 28 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
5587 11:07:45.169767 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 11:07:45.176248 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 11:07:45.179498 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 11:07:45.183051 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 11:07:45.189270 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 11:07:45.192460 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 11:07:45.196064 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 11:07:45.202975 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5595 11:07:45.206682 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5596 11:07:45.210011 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:07:45.216557 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:07:45.219740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:07:45.222703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:07:45.229090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:07:45.232663 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:07:45.236433 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:07:45.239099 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 11:07:45.246360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 11:07:45.249367 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 11:07:45.253233 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 11:07:45.259269 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 11:07:45.262791 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 11:07:45.266511 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5610 11:07:45.272694 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 11:07:45.273169 Total UI for P1: 0, mck2ui 16
5612 11:07:45.279422 best dqsien dly found for B0: ( 1, 2, 24)
5613 11:07:45.279807 Total UI for P1: 0, mck2ui 16
5614 11:07:45.286128 best dqsien dly found for B1: ( 1, 2, 24)
5615 11:07:45.290106 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5616 11:07:45.293292 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5617 11:07:45.293752
5618 11:07:45.296360 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5619 11:07:45.300531 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5620 11:07:45.303130 [Gating] SW calibration Done
5621 11:07:45.303518 ==
5622 11:07:45.306240 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 11:07:45.310047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 11:07:45.310555 ==
5625 11:07:45.312782 RX Vref Scan: 0
5626 11:07:45.313308
5627 11:07:45.313645 RX Vref 0 -> 0, step: 1
5628 11:07:45.313951
5629 11:07:45.316515 RX Delay -80 -> 252, step: 8
5630 11:07:45.319685 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5631 11:07:45.326023 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5632 11:07:45.329659 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5633 11:07:45.333549 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5634 11:07:45.336377 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5635 11:07:45.339373 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5636 11:07:45.343526 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5637 11:07:45.346835 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5638 11:07:45.353177 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5639 11:07:45.356105 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5640 11:07:45.359990 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5641 11:07:45.363098 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5642 11:07:45.366657 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5643 11:07:45.373070 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5644 11:07:45.376576 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5645 11:07:45.379657 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5646 11:07:45.380045 ==
5647 11:07:45.383148 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 11:07:45.386452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 11:07:45.386841 ==
5650 11:07:45.389713 DQS Delay:
5651 11:07:45.390177 DQS0 = 0, DQS1 = 0
5652 11:07:45.390484 DQM Delay:
5653 11:07:45.393616 DQM0 = 95, DQM1 = 87
5654 11:07:45.394076 DQ Delay:
5655 11:07:45.397016 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5656 11:07:45.399531 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5657 11:07:45.402921 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5658 11:07:45.407109 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5659 11:07:45.407575
5660 11:07:45.407892
5661 11:07:45.408172 ==
5662 11:07:45.409443 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 11:07:45.416612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 11:07:45.417162 ==
5665 11:07:45.417517
5666 11:07:45.417843
5667 11:07:45.418187 TX Vref Scan disable
5668 11:07:45.420490 == TX Byte 0 ==
5669 11:07:45.423484 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5670 11:07:45.426548 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5671 11:07:45.430098 == TX Byte 1 ==
5672 11:07:45.433068 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5673 11:07:45.436386 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5674 11:07:45.439685 ==
5675 11:07:45.443201 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 11:07:45.446770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 11:07:45.447161 ==
5678 11:07:45.447460
5679 11:07:45.447736
5680 11:07:45.449758 TX Vref Scan disable
5681 11:07:45.450252 == TX Byte 0 ==
5682 11:07:45.456533 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5683 11:07:45.459625 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5684 11:07:45.460009 == TX Byte 1 ==
5685 11:07:45.466234 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5686 11:07:45.469691 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5687 11:07:45.470083
5688 11:07:45.470387 [DATLAT]
5689 11:07:45.473034 Freq=933, CH1 RK0
5690 11:07:45.473464
5691 11:07:45.473765 DATLAT Default: 0xd
5692 11:07:45.476228 0, 0xFFFF, sum = 0
5693 11:07:45.476621 1, 0xFFFF, sum = 0
5694 11:07:45.480071 2, 0xFFFF, sum = 0
5695 11:07:45.480508 3, 0xFFFF, sum = 0
5696 11:07:45.483202 4, 0xFFFF, sum = 0
5697 11:07:45.483643 5, 0xFFFF, sum = 0
5698 11:07:45.486335 6, 0xFFFF, sum = 0
5699 11:07:45.486725 7, 0xFFFF, sum = 0
5700 11:07:45.489735 8, 0xFFFF, sum = 0
5701 11:07:45.490125 9, 0xFFFF, sum = 0
5702 11:07:45.493827 10, 0x0, sum = 1
5703 11:07:45.494285 11, 0x0, sum = 2
5704 11:07:45.496516 12, 0x0, sum = 3
5705 11:07:45.496906 13, 0x0, sum = 4
5706 11:07:45.500572 best_step = 11
5707 11:07:45.501315
5708 11:07:45.501652 ==
5709 11:07:45.503157 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 11:07:45.507062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 11:07:45.507537 ==
5712 11:07:45.510237 RX Vref Scan: 1
5713 11:07:45.510622
5714 11:07:45.510923 RX Vref 0 -> 0, step: 1
5715 11:07:45.511204
5716 11:07:45.513884 RX Delay -69 -> 252, step: 4
5717 11:07:45.514325
5718 11:07:45.516551 Set Vref, RX VrefLevel [Byte0]: 56
5719 11:07:45.520948 [Byte1]: 50
5720 11:07:45.523395
5721 11:07:45.523920 Final RX Vref Byte 0 = 56 to rank0
5722 11:07:45.527065 Final RX Vref Byte 1 = 50 to rank0
5723 11:07:45.530373 Final RX Vref Byte 0 = 56 to rank1
5724 11:07:45.533400 Final RX Vref Byte 1 = 50 to rank1==
5725 11:07:45.537357 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 11:07:45.544086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 11:07:45.544604 ==
5728 11:07:45.545080 DQS Delay:
5729 11:07:45.545453 DQS0 = 0, DQS1 = 0
5730 11:07:45.547093 DQM Delay:
5731 11:07:45.547478 DQM0 = 97, DQM1 = 89
5732 11:07:45.550429 DQ Delay:
5733 11:07:45.553812 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5734 11:07:45.557007 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5735 11:07:45.560072 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =86
5736 11:07:45.563738 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5737 11:07:45.564122
5738 11:07:45.564419
5739 11:07:45.570223 [DQSOSCAuto] RK0, (LSB)MR18= 0x19f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5740 11:07:45.573893 CH1 RK0: MR19=504, MR18=19F6
5741 11:07:45.580311 CH1_RK0: MR19=0x504, MR18=0x19F6, DQSOSC=413, MR23=63, INC=63, DEC=42
5742 11:07:45.580694
5743 11:07:45.583640 ----->DramcWriteLeveling(PI) begin...
5744 11:07:45.584029 ==
5745 11:07:45.587312 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 11:07:45.590564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 11:07:45.590952 ==
5748 11:07:45.594055 Write leveling (Byte 0): 27 => 27
5749 11:07:45.596847 Write leveling (Byte 1): 29 => 29
5750 11:07:45.600506 DramcWriteLeveling(PI) end<-----
5751 11:07:45.600889
5752 11:07:45.601238 ==
5753 11:07:45.603603 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 11:07:45.607327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 11:07:45.607857 ==
5756 11:07:45.610823 [Gating] SW mode calibration
5757 11:07:45.617318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5758 11:07:45.623785 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5759 11:07:45.627383 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 11:07:45.630309 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 11:07:45.637403 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 11:07:45.640556 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 11:07:45.644635 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 11:07:45.650337 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5765 11:07:45.654295 0 14 24 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
5766 11:07:45.657187 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5767 11:07:45.664387 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 11:07:45.667213 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 11:07:45.670924 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 11:07:45.677513 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 11:07:45.682605 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 11:07:45.684437 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 11:07:45.687749 0 15 24 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
5774 11:07:45.694097 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5775 11:07:45.697158 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 11:07:45.700716 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 11:07:45.707537 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 11:07:45.710957 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 11:07:45.714546 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 11:07:45.720999 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5781 11:07:45.724103 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5782 11:07:45.727573 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5783 11:07:45.734116 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:07:45.737622 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:07:45.740839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:07:45.747286 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:07:45.750638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:07:45.754177 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:07:45.761355 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:07:45.764033 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:07:45.767404 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 11:07:45.774115 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 11:07:45.777726 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 11:07:45.780545 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 11:07:45.784494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 11:07:45.790953 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 11:07:45.794546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5798 11:07:45.798067 Total UI for P1: 0, mck2ui 16
5799 11:07:45.800672 best dqsien dly found for B0: ( 1, 2, 22)
5800 11:07:45.804037 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5801 11:07:45.811293 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 11:07:45.811903 Total UI for P1: 0, mck2ui 16
5803 11:07:45.818142 best dqsien dly found for B1: ( 1, 2, 26)
5804 11:07:45.820943 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5805 11:07:45.824126 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5806 11:07:45.824514
5807 11:07:45.827989 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5808 11:07:45.831335 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5809 11:07:45.834066 [Gating] SW calibration Done
5810 11:07:45.834457 ==
5811 11:07:45.837949 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 11:07:45.841106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 11:07:45.841565 ==
5814 11:07:45.844396 RX Vref Scan: 0
5815 11:07:45.844783
5816 11:07:45.845086 RX Vref 0 -> 0, step: 1
5817 11:07:45.845429
5818 11:07:45.847589 RX Delay -80 -> 252, step: 8
5819 11:07:45.851017 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5820 11:07:45.857869 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5821 11:07:45.860753 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5822 11:07:45.865187 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5823 11:07:45.867555 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5824 11:07:45.870982 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5825 11:07:45.874510 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5826 11:07:45.877842 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5827 11:07:45.884119 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5828 11:07:45.888572 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5829 11:07:45.891336 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5830 11:07:45.894425 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5831 11:07:45.897995 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5832 11:07:45.901510 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5833 11:07:45.907606 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5834 11:07:45.910971 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5835 11:07:45.911369 ==
5836 11:07:45.914353 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 11:07:45.917813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 11:07:45.918273 ==
5839 11:07:45.918578 DQS Delay:
5840 11:07:45.921564 DQS0 = 0, DQS1 = 0
5841 11:07:45.921953 DQM Delay:
5842 11:07:45.924443 DQM0 = 94, DQM1 = 89
5843 11:07:45.924780 DQ Delay:
5844 11:07:45.927979 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5845 11:07:45.931624 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5846 11:07:45.934817 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5847 11:07:45.938002 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5848 11:07:45.938393
5849 11:07:45.938694
5850 11:07:45.938972 ==
5851 11:07:45.941697 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 11:07:45.944712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 11:07:45.947669 ==
5854 11:07:45.948100
5855 11:07:45.948406
5856 11:07:45.948685 TX Vref Scan disable
5857 11:07:45.951278 == TX Byte 0 ==
5858 11:07:45.954364 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5859 11:07:45.957675 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5860 11:07:45.961217 == TX Byte 1 ==
5861 11:07:45.964477 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5862 11:07:45.967630 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5863 11:07:45.971995 ==
5864 11:07:45.972457 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 11:07:45.977903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 11:07:45.978365 ==
5867 11:07:45.978670
5868 11:07:45.978951
5869 11:07:45.979251 TX Vref Scan disable
5870 11:07:45.983073 == TX Byte 0 ==
5871 11:07:45.985402 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5872 11:07:45.988822 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5873 11:07:45.993051 == TX Byte 1 ==
5874 11:07:45.995651 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5875 11:07:45.999062 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5876 11:07:46.002328
5877 11:07:46.002737 [DATLAT]
5878 11:07:46.003043 Freq=933, CH1 RK1
5879 11:07:46.003395
5880 11:07:46.005560 DATLAT Default: 0xb
5881 11:07:46.005954 0, 0xFFFF, sum = 0
5882 11:07:46.008992 1, 0xFFFF, sum = 0
5883 11:07:46.009474 2, 0xFFFF, sum = 0
5884 11:07:46.012336 3, 0xFFFF, sum = 0
5885 11:07:46.012731 4, 0xFFFF, sum = 0
5886 11:07:46.015848 5, 0xFFFF, sum = 0
5887 11:07:46.016255 6, 0xFFFF, sum = 0
5888 11:07:46.019792 7, 0xFFFF, sum = 0
5889 11:07:46.022323 8, 0xFFFF, sum = 0
5890 11:07:46.022734 9, 0xFFFF, sum = 0
5891 11:07:46.023078 10, 0x0, sum = 1
5892 11:07:46.025933 11, 0x0, sum = 2
5893 11:07:46.026326 12, 0x0, sum = 3
5894 11:07:46.029076 13, 0x0, sum = 4
5895 11:07:46.029514 best_step = 11
5896 11:07:46.029830
5897 11:07:46.030206 ==
5898 11:07:46.032191 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 11:07:46.039403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 11:07:46.039795 ==
5901 11:07:46.040099 RX Vref Scan: 0
5902 11:07:46.040398
5903 11:07:46.042019 RX Vref 0 -> 0, step: 1
5904 11:07:46.042422
5905 11:07:46.045403 RX Delay -61 -> 252, step: 4
5906 11:07:46.048782 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5907 11:07:46.056072 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5908 11:07:46.058837 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5909 11:07:46.062156 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5910 11:07:46.065596 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5911 11:07:46.069397 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5912 11:07:46.072576 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5913 11:07:46.076063 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5914 11:07:46.083118 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5915 11:07:46.086284 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5916 11:07:46.088720 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5917 11:07:46.093017 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5918 11:07:46.096202 iDelay=199, Bit 12, Center 100 (15 ~ 186) 172
5919 11:07:46.102922 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5920 11:07:46.105901 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5921 11:07:46.109310 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5922 11:07:46.109767 ==
5923 11:07:46.112382 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 11:07:46.115653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 11:07:46.116063 ==
5926 11:07:46.119590 DQS Delay:
5927 11:07:46.119988 DQS0 = 0, DQS1 = 0
5928 11:07:46.120299 DQM Delay:
5929 11:07:46.122437 DQM0 = 94, DQM1 = 91
5930 11:07:46.122820 DQ Delay:
5931 11:07:46.126020 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
5932 11:07:46.129301 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
5933 11:07:46.132442 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5934 11:07:46.136150 DQ12 =100, DQ13 =98, DQ14 =98, DQ15 =98
5935 11:07:46.136536
5936 11:07:46.136834
5937 11:07:46.145918 [DQSOSCAuto] RK1, (LSB)MR18= 0xe16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5938 11:07:46.146308 CH1 RK1: MR19=505, MR18=E16
5939 11:07:46.153075 CH1_RK1: MR19=0x505, MR18=0xE16, DQSOSC=414, MR23=63, INC=63, DEC=42
5940 11:07:46.156280 [RxdqsGatingPostProcess] freq 933
5941 11:07:46.162602 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5942 11:07:46.165913 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 11:07:46.169335 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 11:07:46.172855 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 11:07:46.176022 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 11:07:46.179199 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 11:07:46.179626 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 11:07:46.182804 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 11:07:46.185721 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 11:07:46.189068 Pre-setting of DQS Precalculation
5951 11:07:46.196304 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5952 11:07:46.202726 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5953 11:07:46.209188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5954 11:07:46.209718
5955 11:07:46.210053
5956 11:07:46.212497 [Calibration Summary] 1866 Mbps
5957 11:07:46.215653 CH 0, Rank 0
5958 11:07:46.216076 SW Impedance : PASS
5959 11:07:46.219064 DUTY Scan : NO K
5960 11:07:46.219505 ZQ Calibration : PASS
5961 11:07:46.223257 Jitter Meter : NO K
5962 11:07:46.225787 CBT Training : PASS
5963 11:07:46.226174 Write leveling : PASS
5964 11:07:46.229073 RX DQS gating : PASS
5965 11:07:46.232674 RX DQ/DQS(RDDQC) : PASS
5966 11:07:46.233058 TX DQ/DQS : PASS
5967 11:07:46.237300 RX DATLAT : PASS
5968 11:07:46.239033 RX DQ/DQS(Engine): PASS
5969 11:07:46.239418 TX OE : NO K
5970 11:07:46.242387 All Pass.
5971 11:07:46.242770
5972 11:07:46.243071 CH 0, Rank 1
5973 11:07:46.245469 SW Impedance : PASS
5974 11:07:46.245854 DUTY Scan : NO K
5975 11:07:46.249286 ZQ Calibration : PASS
5976 11:07:46.252390 Jitter Meter : NO K
5977 11:07:46.252777 CBT Training : PASS
5978 11:07:46.255827 Write leveling : PASS
5979 11:07:46.256225 RX DQS gating : PASS
5980 11:07:46.259083 RX DQ/DQS(RDDQC) : PASS
5981 11:07:46.262414 TX DQ/DQS : PASS
5982 11:07:46.262832 RX DATLAT : PASS
5983 11:07:46.265753 RX DQ/DQS(Engine): PASS
5984 11:07:46.269298 TX OE : NO K
5985 11:07:46.269683 All Pass.
5986 11:07:46.269984
5987 11:07:46.270264 CH 1, Rank 0
5988 11:07:46.272808 SW Impedance : PASS
5989 11:07:46.275714 DUTY Scan : NO K
5990 11:07:46.276106 ZQ Calibration : PASS
5991 11:07:46.279550 Jitter Meter : NO K
5992 11:07:46.282044 CBT Training : PASS
5993 11:07:46.282210 Write leveling : PASS
5994 11:07:46.285504 RX DQS gating : PASS
5995 11:07:46.289030 RX DQ/DQS(RDDQC) : PASS
5996 11:07:46.289243 TX DQ/DQS : PASS
5997 11:07:46.292215 RX DATLAT : PASS
5998 11:07:46.295404 RX DQ/DQS(Engine): PASS
5999 11:07:46.295628 TX OE : NO K
6000 11:07:46.295787 All Pass.
6001 11:07:46.299156
6002 11:07:46.299362 CH 1, Rank 1
6003 11:07:46.301979 SW Impedance : PASS
6004 11:07:46.302192 DUTY Scan : NO K
6005 11:07:46.305784 ZQ Calibration : PASS
6006 11:07:46.305999 Jitter Meter : NO K
6007 11:07:46.308783 CBT Training : PASS
6008 11:07:46.311887 Write leveling : PASS
6009 11:07:46.312097 RX DQS gating : PASS
6010 11:07:46.315253 RX DQ/DQS(RDDQC) : PASS
6011 11:07:46.318718 TX DQ/DQS : PASS
6012 11:07:46.318996 RX DATLAT : PASS
6013 11:07:46.321850 RX DQ/DQS(Engine): PASS
6014 11:07:46.325217 TX OE : NO K
6015 11:07:46.325353 All Pass.
6016 11:07:46.325446
6017 11:07:46.325530 DramC Write-DBI off
6018 11:07:46.328591 PER_BANK_REFRESH: Hybrid Mode
6019 11:07:46.332268 TX_TRACKING: ON
6020 11:07:46.338571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6021 11:07:46.342094 [FAST_K] Save calibration result to emmc
6022 11:07:46.348992 dramc_set_vcore_voltage set vcore to 650000
6023 11:07:46.349104 Read voltage for 400, 6
6024 11:07:46.351844 Vio18 = 0
6025 11:07:46.351942 Vcore = 650000
6026 11:07:46.352038 Vdram = 0
6027 11:07:46.355484 Vddq = 0
6028 11:07:46.355559 Vmddr = 0
6029 11:07:46.358752 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6030 11:07:46.365776 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6031 11:07:46.368827 MEM_TYPE=3, freq_sel=20
6032 11:07:46.368904 sv_algorithm_assistance_LP4_800
6033 11:07:46.375865 ============ PULL DRAM RESETB DOWN ============
6034 11:07:46.379159 ========== PULL DRAM RESETB DOWN end =========
6035 11:07:46.382566 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6036 11:07:46.385305 ===================================
6037 11:07:46.388658 LPDDR4 DRAM CONFIGURATION
6038 11:07:46.391987 ===================================
6039 11:07:46.395476 EX_ROW_EN[0] = 0x0
6040 11:07:46.395552 EX_ROW_EN[1] = 0x0
6041 11:07:46.398901 LP4Y_EN = 0x0
6042 11:07:46.398977 WORK_FSP = 0x0
6043 11:07:46.402726 WL = 0x2
6044 11:07:46.402810 RL = 0x2
6045 11:07:46.405555 BL = 0x2
6046 11:07:46.405637 RPST = 0x0
6047 11:07:46.408905 RD_PRE = 0x0
6048 11:07:46.408985 WR_PRE = 0x1
6049 11:07:46.412201 WR_PST = 0x0
6050 11:07:46.412281 DBI_WR = 0x0
6051 11:07:46.415386 DBI_RD = 0x0
6052 11:07:46.415468 OTF = 0x1
6053 11:07:46.418960 ===================================
6054 11:07:46.422226 ===================================
6055 11:07:46.425668 ANA top config
6056 11:07:46.428670 ===================================
6057 11:07:46.428783 DLL_ASYNC_EN = 0
6058 11:07:46.432601 ALL_SLAVE_EN = 1
6059 11:07:46.435732 NEW_RANK_MODE = 1
6060 11:07:46.439496 DLL_IDLE_MODE = 1
6061 11:07:46.442217 LP45_APHY_COMB_EN = 1
6062 11:07:46.442312 TX_ODT_DIS = 1
6063 11:07:46.445844 NEW_8X_MODE = 1
6064 11:07:46.449089 ===================================
6065 11:07:46.452093 ===================================
6066 11:07:46.455741 data_rate = 800
6067 11:07:46.459054 CKR = 1
6068 11:07:46.462213 DQ_P2S_RATIO = 4
6069 11:07:46.465517 ===================================
6070 11:07:46.465631 CA_P2S_RATIO = 4
6071 11:07:46.469262 DQ_CA_OPEN = 0
6072 11:07:46.472058 DQ_SEMI_OPEN = 1
6073 11:07:46.475814 CA_SEMI_OPEN = 1
6074 11:07:46.479029 CA_FULL_RATE = 0
6075 11:07:46.482169 DQ_CKDIV4_EN = 0
6076 11:07:46.482256 CA_CKDIV4_EN = 1
6077 11:07:46.485911 CA_PREDIV_EN = 0
6078 11:07:46.489351 PH8_DLY = 0
6079 11:07:46.492661 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6080 11:07:46.496141 DQ_AAMCK_DIV = 0
6081 11:07:46.499121 CA_AAMCK_DIV = 0
6082 11:07:46.499207 CA_ADMCK_DIV = 4
6083 11:07:46.502257 DQ_TRACK_CA_EN = 0
6084 11:07:46.505855 CA_PICK = 800
6085 11:07:46.509261 CA_MCKIO = 400
6086 11:07:46.512643 MCKIO_SEMI = 400
6087 11:07:46.516594 PLL_FREQ = 3016
6088 11:07:46.519813 DQ_UI_PI_RATIO = 32
6089 11:07:46.520017 CA_UI_PI_RATIO = 32
6090 11:07:46.523012 ===================================
6091 11:07:46.526126 ===================================
6092 11:07:46.529527 memory_type:LPDDR4
6093 11:07:46.533306 GP_NUM : 10
6094 11:07:46.533562 SRAM_EN : 1
6095 11:07:46.536107 MD32_EN : 0
6096 11:07:46.539637 ===================================
6097 11:07:46.543494 [ANA_INIT] >>>>>>>>>>>>>>
6098 11:07:46.543843 <<<<<< [CONFIGURE PHASE]: ANA_TX
6099 11:07:46.550050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6100 11:07:46.550509 ===================================
6101 11:07:46.553071 data_rate = 800,PCW = 0X7400
6102 11:07:46.556193 ===================================
6103 11:07:46.559876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6104 11:07:46.566261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6105 11:07:46.576440 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 11:07:46.583274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6107 11:07:46.586172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6108 11:07:46.589715 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6109 11:07:46.590269 [ANA_INIT] flow start
6110 11:07:46.592934 [ANA_INIT] PLL >>>>>>>>
6111 11:07:46.596661 [ANA_INIT] PLL <<<<<<<<
6112 11:07:46.599704 [ANA_INIT] MIDPI >>>>>>>>
6113 11:07:46.600173 [ANA_INIT] MIDPI <<<<<<<<
6114 11:07:46.603011 [ANA_INIT] DLL >>>>>>>>
6115 11:07:46.603527 [ANA_INIT] flow end
6116 11:07:46.610118 ============ LP4 DIFF to SE enter ============
6117 11:07:46.613331 ============ LP4 DIFF to SE exit ============
6118 11:07:46.616460 [ANA_INIT] <<<<<<<<<<<<<
6119 11:07:46.619864 [Flow] Enable top DCM control >>>>>
6120 11:07:46.623151 [Flow] Enable top DCM control <<<<<
6121 11:07:46.623650 Enable DLL master slave shuffle
6122 11:07:46.630119 ==============================================================
6123 11:07:46.632973 Gating Mode config
6124 11:07:46.636129 ==============================================================
6125 11:07:46.639959 Config description:
6126 11:07:46.649633 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6127 11:07:46.656445 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6128 11:07:46.659678 SELPH_MODE 0: By rank 1: By Phase
6129 11:07:46.666732 ==============================================================
6130 11:07:46.669361 GAT_TRACK_EN = 0
6131 11:07:46.672793 RX_GATING_MODE = 2
6132 11:07:46.676381 RX_GATING_TRACK_MODE = 2
6133 11:07:46.680308 SELPH_MODE = 1
6134 11:07:46.681093 PICG_EARLY_EN = 1
6135 11:07:46.682803 VALID_LAT_VALUE = 1
6136 11:07:46.689499 ==============================================================
6137 11:07:46.692782 Enter into Gating configuration >>>>
6138 11:07:46.696142 Exit from Gating configuration <<<<
6139 11:07:46.699429 Enter into DVFS_PRE_config >>>>>
6140 11:07:46.709445 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6141 11:07:46.712927 Exit from DVFS_PRE_config <<<<<
6142 11:07:46.717094 Enter into PICG configuration >>>>
6143 11:07:46.719889 Exit from PICG configuration <<<<
6144 11:07:46.723137 [RX_INPUT] configuration >>>>>
6145 11:07:46.726503 [RX_INPUT] configuration <<<<<
6146 11:07:46.729993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6147 11:07:46.736803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6148 11:07:46.743722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 11:07:46.750449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 11:07:46.753257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 11:07:46.760499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 11:07:46.763597 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6153 11:07:46.770177 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6154 11:07:46.773259 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6155 11:07:46.776784 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6156 11:07:46.779903 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6157 11:07:46.786740 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6158 11:07:46.790086 ===================================
6159 11:07:46.790518 LPDDR4 DRAM CONFIGURATION
6160 11:07:46.793268 ===================================
6161 11:07:46.796511 EX_ROW_EN[0] = 0x0
6162 11:07:46.799781 EX_ROW_EN[1] = 0x0
6163 11:07:46.800320 LP4Y_EN = 0x0
6164 11:07:46.803295 WORK_FSP = 0x0
6165 11:07:46.803678 WL = 0x2
6166 11:07:46.806963 RL = 0x2
6167 11:07:46.807343 BL = 0x2
6168 11:07:46.810294 RPST = 0x0
6169 11:07:46.810797 RD_PRE = 0x0
6170 11:07:46.813533 WR_PRE = 0x1
6171 11:07:46.813921 WR_PST = 0x0
6172 11:07:46.816742 DBI_WR = 0x0
6173 11:07:46.817275 DBI_RD = 0x0
6174 11:07:46.819991 OTF = 0x1
6175 11:07:46.823861 ===================================
6176 11:07:46.826865 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6177 11:07:46.829884 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6178 11:07:46.833770 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 11:07:46.837203 ===================================
6180 11:07:46.840271 LPDDR4 DRAM CONFIGURATION
6181 11:07:46.843555 ===================================
6182 11:07:46.846727 EX_ROW_EN[0] = 0x10
6183 11:07:46.847118 EX_ROW_EN[1] = 0x0
6184 11:07:46.850350 LP4Y_EN = 0x0
6185 11:07:46.850735 WORK_FSP = 0x0
6186 11:07:46.853464 WL = 0x2
6187 11:07:46.853857 RL = 0x2
6188 11:07:46.856677 BL = 0x2
6189 11:07:46.857057 RPST = 0x0
6190 11:07:46.860127 RD_PRE = 0x0
6191 11:07:46.860512 WR_PRE = 0x1
6192 11:07:46.863344 WR_PST = 0x0
6193 11:07:46.866755 DBI_WR = 0x0
6194 11:07:46.867144 DBI_RD = 0x0
6195 11:07:46.870800 OTF = 0x1
6196 11:07:46.874023 ===================================
6197 11:07:46.876832 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6198 11:07:46.882061 nWR fixed to 30
6199 11:07:46.885430 [ModeRegInit_LP4] CH0 RK0
6200 11:07:46.885943 [ModeRegInit_LP4] CH0 RK1
6201 11:07:46.888639 [ModeRegInit_LP4] CH1 RK0
6202 11:07:46.891927 [ModeRegInit_LP4] CH1 RK1
6203 11:07:46.892329 match AC timing 19
6204 11:07:46.898850 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6205 11:07:46.901782 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6206 11:07:46.905101 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6207 11:07:46.911852 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6208 11:07:46.915653 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6209 11:07:46.916125 ==
6210 11:07:46.918784 Dram Type= 6, Freq= 0, CH_0, rank 0
6211 11:07:46.921986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6212 11:07:46.922394 ==
6213 11:07:46.928450 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6214 11:07:46.935222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6215 11:07:46.938554 [CA 0] Center 36 (8~64) winsize 57
6216 11:07:46.941997 [CA 1] Center 36 (8~64) winsize 57
6217 11:07:46.942503 [CA 2] Center 36 (8~64) winsize 57
6218 11:07:46.945525 [CA 3] Center 36 (8~64) winsize 57
6219 11:07:46.948941 [CA 4] Center 36 (8~64) winsize 57
6220 11:07:46.952004 [CA 5] Center 36 (8~64) winsize 57
6221 11:07:46.952393
6222 11:07:46.955908 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6223 11:07:46.956390
6224 11:07:46.962284 [CATrainingPosCal] consider 1 rank data
6225 11:07:46.962740 u2DelayCellTimex100 = 270/100 ps
6226 11:07:46.965739 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:07:46.972466 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 11:07:46.975641 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 11:07:46.979009 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 11:07:46.981968 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 11:07:46.985336 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 11:07:46.985725
6233 11:07:46.988876 CA PerBit enable=1, Macro0, CA PI delay=36
6234 11:07:46.989325
6235 11:07:46.992563 [CBTSetCACLKResult] CA Dly = 36
6236 11:07:46.993029 CS Dly: 1 (0~32)
6237 11:07:46.995547 ==
6238 11:07:46.998690 Dram Type= 6, Freq= 0, CH_0, rank 1
6239 11:07:47.002329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6240 11:07:47.002802 ==
6241 11:07:47.005669 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6242 11:07:47.012976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6243 11:07:47.015931 [CA 0] Center 36 (8~64) winsize 57
6244 11:07:47.019280 [CA 1] Center 36 (8~64) winsize 57
6245 11:07:47.022360 [CA 2] Center 36 (8~64) winsize 57
6246 11:07:47.025640 [CA 3] Center 36 (8~64) winsize 57
6247 11:07:47.029329 [CA 4] Center 36 (8~64) winsize 57
6248 11:07:47.032444 [CA 5] Center 36 (8~64) winsize 57
6249 11:07:47.032836
6250 11:07:47.036129 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6251 11:07:47.036595
6252 11:07:47.038986 [CATrainingPosCal] consider 2 rank data
6253 11:07:47.042630 u2DelayCellTimex100 = 270/100 ps
6254 11:07:47.046092 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:07:47.049052 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 11:07:47.052623 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 11:07:47.056072 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 11:07:47.059489 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 11:07:47.063181 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 11:07:47.063609
6261 11:07:47.069476 CA PerBit enable=1, Macro0, CA PI delay=36
6262 11:07:47.069990
6263 11:07:47.070326 [CBTSetCACLKResult] CA Dly = 36
6264 11:07:47.073366 CS Dly: 1 (0~32)
6265 11:07:47.073870
6266 11:07:47.076623 ----->DramcWriteLeveling(PI) begin...
6267 11:07:47.077184 ==
6268 11:07:47.079754 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 11:07:47.082656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 11:07:47.083085 ==
6271 11:07:47.086093 Write leveling (Byte 0): 40 => 8
6272 11:07:47.089473 Write leveling (Byte 1): 32 => 0
6273 11:07:47.092760 DramcWriteLeveling(PI) end<-----
6274 11:07:47.093480
6275 11:07:47.093832 ==
6276 11:07:47.096198 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 11:07:47.098996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 11:07:47.102409 ==
6279 11:07:47.102914 [Gating] SW mode calibration
6280 11:07:47.109575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6281 11:07:47.115974 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6282 11:07:47.119657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6283 11:07:47.125476 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 11:07:47.129101 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 11:07:47.132741 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 11:07:47.139121 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 11:07:47.142833 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 11:07:47.145937 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 11:07:47.152619 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 11:07:47.155882 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 11:07:47.159255 Total UI for P1: 0, mck2ui 16
6292 11:07:47.163023 best dqsien dly found for B0: ( 0, 14, 24)
6293 11:07:47.166108 Total UI for P1: 0, mck2ui 16
6294 11:07:47.169358 best dqsien dly found for B1: ( 0, 14, 24)
6295 11:07:47.173224 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6296 11:07:47.176364 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6297 11:07:47.176868
6298 11:07:47.179483 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6299 11:07:47.182810 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 11:07:47.185809 [Gating] SW calibration Done
6301 11:07:47.186321 ==
6302 11:07:47.188636 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 11:07:47.192173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 11:07:47.192603 ==
6305 11:07:47.195436 RX Vref Scan: 0
6306 11:07:47.195856
6307 11:07:47.198763 RX Vref 0 -> 0, step: 1
6308 11:07:47.199184
6309 11:07:47.202279 RX Delay -410 -> 252, step: 16
6310 11:07:47.205591 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6311 11:07:47.208776 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6312 11:07:47.212164 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6313 11:07:47.219033 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6314 11:07:47.222489 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6315 11:07:47.225860 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6316 11:07:47.228578 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6317 11:07:47.235539 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6318 11:07:47.239430 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6319 11:07:47.242171 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6320 11:07:47.245914 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6321 11:07:47.252155 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6322 11:07:47.255828 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6323 11:07:47.258775 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6324 11:07:47.262546 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6325 11:07:47.269661 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6326 11:07:47.270183 ==
6327 11:07:47.272765 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 11:07:47.275904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 11:07:47.276405 ==
6330 11:07:47.276741 DQS Delay:
6331 11:07:47.279149 DQS0 = 35, DQS1 = 51
6332 11:07:47.279580 DQM Delay:
6333 11:07:47.282195 DQM0 = 6, DQM1 = 10
6334 11:07:47.282621 DQ Delay:
6335 11:07:47.286259 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6336 11:07:47.288771 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6337 11:07:47.292406 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6338 11:07:47.295976 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6339 11:07:47.296472
6340 11:07:47.296803
6341 11:07:47.297106 ==
6342 11:07:47.299750 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 11:07:47.302875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 11:07:47.303392 ==
6345 11:07:47.303768
6346 11:07:47.304078
6347 11:07:47.305686 TX Vref Scan disable
6348 11:07:47.306105 == TX Byte 0 ==
6349 11:07:47.312970 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 11:07:47.315974 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 11:07:47.316470 == TX Byte 1 ==
6352 11:07:47.322499 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6353 11:07:47.326406 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6354 11:07:47.326905 ==
6355 11:07:47.328803 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 11:07:47.332479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 11:07:47.332978 ==
6358 11:07:47.333350
6359 11:07:47.333658
6360 11:07:47.335837 TX Vref Scan disable
6361 11:07:47.336259 == TX Byte 0 ==
6362 11:07:47.342635 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 11:07:47.345834 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 11:07:47.346331 == TX Byte 1 ==
6365 11:07:47.352397 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6366 11:07:47.356074 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6367 11:07:47.356514
6368 11:07:47.356846 [DATLAT]
6369 11:07:47.358939 Freq=400, CH0 RK0
6370 11:07:47.359365
6371 11:07:47.359662 DATLAT Default: 0xf
6372 11:07:47.362687 0, 0xFFFF, sum = 0
6373 11:07:47.363077 1, 0xFFFF, sum = 0
6374 11:07:47.365844 2, 0xFFFF, sum = 0
6375 11:07:47.366306 3, 0xFFFF, sum = 0
6376 11:07:47.369020 4, 0xFFFF, sum = 0
6377 11:07:47.369531 5, 0xFFFF, sum = 0
6378 11:07:47.372835 6, 0xFFFF, sum = 0
6379 11:07:47.373404 7, 0xFFFF, sum = 0
6380 11:07:47.376341 8, 0xFFFF, sum = 0
6381 11:07:47.376852 9, 0xFFFF, sum = 0
6382 11:07:47.379108 10, 0xFFFF, sum = 0
6383 11:07:47.382298 11, 0xFFFF, sum = 0
6384 11:07:47.382731 12, 0xFFFF, sum = 0
6385 11:07:47.385753 13, 0x0, sum = 1
6386 11:07:47.386300 14, 0x0, sum = 2
6387 11:07:47.386652 15, 0x0, sum = 3
6388 11:07:47.388741 16, 0x0, sum = 4
6389 11:07:47.389244 best_step = 14
6390 11:07:47.389741
6391 11:07:47.392486 ==
6392 11:07:47.392915 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 11:07:47.399259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 11:07:47.399767 ==
6395 11:07:47.400107 RX Vref Scan: 1
6396 11:07:47.400415
6397 11:07:47.402601 RX Vref 0 -> 0, step: 1
6398 11:07:47.403033
6399 11:07:47.406127 RX Delay -343 -> 252, step: 8
6400 11:07:47.406634
6401 11:07:47.409028 Set Vref, RX VrefLevel [Byte0]: 52
6402 11:07:47.412973 [Byte1]: 51
6403 11:07:47.416266
6404 11:07:47.416772 Final RX Vref Byte 0 = 52 to rank0
6405 11:07:47.419240 Final RX Vref Byte 1 = 51 to rank0
6406 11:07:47.422469 Final RX Vref Byte 0 = 52 to rank1
6407 11:07:47.426059 Final RX Vref Byte 1 = 51 to rank1==
6408 11:07:47.429375 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 11:07:47.435886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 11:07:47.436288 ==
6411 11:07:47.436597 DQS Delay:
6412 11:07:47.436881 DQS0 = 44, DQS1 = 60
6413 11:07:47.439390 DQM Delay:
6414 11:07:47.439791 DQM0 = 12, DQM1 = 15
6415 11:07:47.442535 DQ Delay:
6416 11:07:47.446098 DQ0 =16, DQ1 =12, DQ2 =8, DQ3 =8
6417 11:07:47.446486 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6418 11:07:47.449452 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6419 11:07:47.452946 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6420 11:07:47.453450
6421 11:07:47.453762
6422 11:07:47.462529 [DQSOSCAuto] RK0, (LSB)MR18= 0x8655, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6423 11:07:47.466275 CH0 RK0: MR19=C0C, MR18=8655
6424 11:07:47.472623 CH0_RK0: MR19=0xC0C, MR18=0x8655, DQSOSC=393, MR23=63, INC=382, DEC=254
6425 11:07:47.473104 ==
6426 11:07:47.476077 Dram Type= 6, Freq= 0, CH_0, rank 1
6427 11:07:47.479382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 11:07:47.479852 ==
6429 11:07:47.482775 [Gating] SW mode calibration
6430 11:07:47.490322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6431 11:07:47.492620 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6432 11:07:47.499352 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6433 11:07:47.502557 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 11:07:47.506255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 11:07:47.512958 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 11:07:47.516303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 11:07:47.519172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 11:07:47.526428 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 11:07:47.530245 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 11:07:47.532673 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 11:07:47.536248 Total UI for P1: 0, mck2ui 16
6442 11:07:47.539531 best dqsien dly found for B0: ( 0, 14, 24)
6443 11:07:47.543169 Total UI for P1: 0, mck2ui 16
6444 11:07:47.546422 best dqsien dly found for B1: ( 0, 14, 24)
6445 11:07:47.549325 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6446 11:07:47.552601 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6447 11:07:47.552991
6448 11:07:47.556186 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6449 11:07:47.563206 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 11:07:47.563670 [Gating] SW calibration Done
6451 11:07:47.563981 ==
6452 11:07:47.566622 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 11:07:47.573353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 11:07:47.573820 ==
6455 11:07:47.574129 RX Vref Scan: 0
6456 11:07:47.574407
6457 11:07:47.576201 RX Vref 0 -> 0, step: 1
6458 11:07:47.576681
6459 11:07:47.579346 RX Delay -410 -> 252, step: 16
6460 11:07:47.583112 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6461 11:07:47.586206 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6462 11:07:47.593779 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6463 11:07:47.596795 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6464 11:07:47.600096 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6465 11:07:47.603138 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6466 11:07:47.606596 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6467 11:07:47.613711 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6468 11:07:47.617170 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6469 11:07:47.619478 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6470 11:07:47.626437 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6471 11:07:47.629710 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6472 11:07:47.632631 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6473 11:07:47.636491 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6474 11:07:47.642896 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6475 11:07:47.646227 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6476 11:07:47.646745 ==
6477 11:07:47.649500 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 11:07:47.652561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 11:07:47.652997 ==
6480 11:07:47.656335 DQS Delay:
6481 11:07:47.656765 DQS0 = 43, DQS1 = 51
6482 11:07:47.657105 DQM Delay:
6483 11:07:47.659246 DQM0 = 11, DQM1 = 10
6484 11:07:47.659637 DQ Delay:
6485 11:07:47.662987 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6486 11:07:47.666586 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6487 11:07:47.669816 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6488 11:07:47.673190 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6489 11:07:47.673693
6490 11:07:47.674028
6491 11:07:47.674340 ==
6492 11:07:47.676469 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 11:07:47.679644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 11:07:47.680077 ==
6495 11:07:47.680413
6496 11:07:47.682845
6497 11:07:47.683355 TX Vref Scan disable
6498 11:07:47.686274 == TX Byte 0 ==
6499 11:07:47.689454 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6500 11:07:47.693251 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6501 11:07:47.695919 == TX Byte 1 ==
6502 11:07:47.699365 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6503 11:07:47.702617 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6504 11:07:47.703048 ==
6505 11:07:47.706220 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 11:07:47.709509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 11:07:47.713030 ==
6508 11:07:47.713586
6509 11:07:47.713927
6510 11:07:47.714300 TX Vref Scan disable
6511 11:07:47.716344 == TX Byte 0 ==
6512 11:07:47.719515 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6513 11:07:47.722923 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6514 11:07:47.725784 == TX Byte 1 ==
6515 11:07:47.729730 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6516 11:07:47.733284 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6517 11:07:47.733850
6518 11:07:47.734194 [DATLAT]
6519 11:07:47.735896 Freq=400, CH0 RK1
6520 11:07:47.736325
6521 11:07:47.736660 DATLAT Default: 0xe
6522 11:07:47.739402 0, 0xFFFF, sum = 0
6523 11:07:47.742461 1, 0xFFFF, sum = 0
6524 11:07:47.742897 2, 0xFFFF, sum = 0
6525 11:07:47.746197 3, 0xFFFF, sum = 0
6526 11:07:47.746703 4, 0xFFFF, sum = 0
6527 11:07:47.749347 5, 0xFFFF, sum = 0
6528 11:07:47.749784 6, 0xFFFF, sum = 0
6529 11:07:47.753053 7, 0xFFFF, sum = 0
6530 11:07:47.753608 8, 0xFFFF, sum = 0
6531 11:07:47.755904 9, 0xFFFF, sum = 0
6532 11:07:47.756340 10, 0xFFFF, sum = 0
6533 11:07:47.759740 11, 0xFFFF, sum = 0
6534 11:07:47.760176 12, 0xFFFF, sum = 0
6535 11:07:47.762711 13, 0x0, sum = 1
6536 11:07:47.763143 14, 0x0, sum = 2
6537 11:07:47.766125 15, 0x0, sum = 3
6538 11:07:47.766617 16, 0x0, sum = 4
6539 11:07:47.769105 best_step = 14
6540 11:07:47.769581
6541 11:07:47.769917 ==
6542 11:07:47.772483 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 11:07:47.775623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 11:07:47.776054 ==
6545 11:07:47.776392 RX Vref Scan: 0
6546 11:07:47.779194
6547 11:07:47.779625 RX Vref 0 -> 0, step: 1
6548 11:07:47.779963
6549 11:07:47.782519 RX Delay -343 -> 252, step: 8
6550 11:07:47.789916 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6551 11:07:47.793497 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6552 11:07:47.796628 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6553 11:07:47.800451 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6554 11:07:47.806852 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6555 11:07:47.810021 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6556 11:07:47.813288 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6557 11:07:47.816814 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6558 11:07:47.823304 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6559 11:07:47.826837 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6560 11:07:47.829675 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6561 11:07:47.833280 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6562 11:07:47.840543 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6563 11:07:47.842979 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6564 11:07:47.846534 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6565 11:07:47.853094 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6566 11:07:47.853537 ==
6567 11:07:47.856786 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 11:07:47.860513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 11:07:47.861065 ==
6570 11:07:47.861480 DQS Delay:
6571 11:07:47.863888 DQS0 = 48, DQS1 = 60
6572 11:07:47.864390 DQM Delay:
6573 11:07:47.866907 DQM0 = 13, DQM1 = 13
6574 11:07:47.867420 DQ Delay:
6575 11:07:47.869961 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6576 11:07:47.873257 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6577 11:07:47.877522 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6578 11:07:47.880413 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6579 11:07:47.880916
6580 11:07:47.881353
6581 11:07:47.886678 [DQSOSCAuto] RK1, (LSB)MR18= 0x9b6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6582 11:07:47.890010 CH0 RK1: MR19=C0C, MR18=9B6F
6583 11:07:47.897035 CH0_RK1: MR19=0xC0C, MR18=0x9B6F, DQSOSC=390, MR23=63, INC=388, DEC=258
6584 11:07:47.900238 [RxdqsGatingPostProcess] freq 400
6585 11:07:47.903702 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6586 11:07:47.906605 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 11:07:47.909949 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 11:07:47.914236 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 11:07:47.916959 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 11:07:47.919887 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 11:07:47.923593 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 11:07:47.926641 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 11:07:47.929919 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 11:07:47.933741 Pre-setting of DQS Precalculation
6595 11:07:47.937069 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6596 11:07:47.937501 ==
6597 11:07:47.940653 Dram Type= 6, Freq= 0, CH_1, rank 0
6598 11:07:47.946867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 11:07:47.947421 ==
6600 11:07:47.950382 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6601 11:07:47.956788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6602 11:07:47.960754 [CA 0] Center 36 (8~64) winsize 57
6603 11:07:47.963686 [CA 1] Center 36 (8~64) winsize 57
6604 11:07:47.967192 [CA 2] Center 36 (8~64) winsize 57
6605 11:07:47.970238 [CA 3] Center 36 (8~64) winsize 57
6606 11:07:47.973850 [CA 4] Center 36 (8~64) winsize 57
6607 11:07:47.977146 [CA 5] Center 36 (8~64) winsize 57
6608 11:07:47.977546
6609 11:07:47.980307 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6610 11:07:47.980762
6611 11:07:47.984013 [CATrainingPosCal] consider 1 rank data
6612 11:07:47.987122 u2DelayCellTimex100 = 270/100 ps
6613 11:07:47.990745 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:07:47.993800 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 11:07:47.997378 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 11:07:48.000387 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 11:07:48.003490 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 11:07:48.007608 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 11:07:48.008081
6620 11:07:48.011139 CA PerBit enable=1, Macro0, CA PI delay=36
6621 11:07:48.013685
6622 11:07:48.014069 [CBTSetCACLKResult] CA Dly = 36
6623 11:07:48.017087 CS Dly: 1 (0~32)
6624 11:07:48.017508 ==
6625 11:07:48.020485 Dram Type= 6, Freq= 0, CH_1, rank 1
6626 11:07:48.023585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 11:07:48.023974 ==
6628 11:07:48.030827 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6629 11:07:48.037350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6630 11:07:48.040345 [CA 0] Center 36 (8~64) winsize 57
6631 11:07:48.043903 [CA 1] Center 36 (8~64) winsize 57
6632 11:07:48.044412 [CA 2] Center 36 (8~64) winsize 57
6633 11:07:48.047396 [CA 3] Center 36 (8~64) winsize 57
6634 11:07:48.050955 [CA 4] Center 36 (8~64) winsize 57
6635 11:07:48.053992 [CA 5] Center 36 (8~64) winsize 57
6636 11:07:48.054397
6637 11:07:48.056877 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6638 11:07:48.057303
6639 11:07:48.064382 [CATrainingPosCal] consider 2 rank data
6640 11:07:48.064850 u2DelayCellTimex100 = 270/100 ps
6641 11:07:48.071003 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:07:48.074052 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 11:07:48.077197 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 11:07:48.080810 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 11:07:48.083855 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 11:07:48.087131 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 11:07:48.087521
6648 11:07:48.090566 CA PerBit enable=1, Macro0, CA PI delay=36
6649 11:07:48.090951
6650 11:07:48.093609 [CBTSetCACLKResult] CA Dly = 36
6651 11:07:48.094008 CS Dly: 1 (0~32)
6652 11:07:48.097890
6653 11:07:48.100850 ----->DramcWriteLeveling(PI) begin...
6654 11:07:48.101361 ==
6655 11:07:48.104206 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 11:07:48.107109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 11:07:48.107499 ==
6658 11:07:48.110240 Write leveling (Byte 0): 40 => 8
6659 11:07:48.113763 Write leveling (Byte 1): 40 => 8
6660 11:07:48.117016 DramcWriteLeveling(PI) end<-----
6661 11:07:48.117507
6662 11:07:48.117834 ==
6663 11:07:48.120582 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 11:07:48.124006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 11:07:48.124392 ==
6666 11:07:48.127128 [Gating] SW mode calibration
6667 11:07:48.134200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6668 11:07:48.140562 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6669 11:07:48.144233 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6670 11:07:48.147255 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 11:07:48.150830 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 11:07:48.157483 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 11:07:48.160367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 11:07:48.163769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 11:07:48.170784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 11:07:48.174435 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 11:07:48.177509 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 11:07:48.180471 Total UI for P1: 0, mck2ui 16
6679 11:07:48.184415 best dqsien dly found for B0: ( 0, 14, 24)
6680 11:07:48.187723 Total UI for P1: 0, mck2ui 16
6681 11:07:48.191096 best dqsien dly found for B1: ( 0, 14, 24)
6682 11:07:48.194247 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6683 11:07:48.197172 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6684 11:07:48.197557
6685 11:07:48.204382 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6686 11:07:48.207452 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 11:07:48.207919 [Gating] SW calibration Done
6688 11:07:48.210903 ==
6689 11:07:48.214171 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 11:07:48.217267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 11:07:48.217697 ==
6692 11:07:48.218038 RX Vref Scan: 0
6693 11:07:48.218346
6694 11:07:48.220708 RX Vref 0 -> 0, step: 1
6695 11:07:48.221377
6696 11:07:48.224296 RX Delay -410 -> 252, step: 16
6697 11:07:48.227412 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6698 11:07:48.231146 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6699 11:07:48.237904 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6700 11:07:48.241521 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6701 11:07:48.244138 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6702 11:07:48.247993 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6703 11:07:48.254580 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6704 11:07:48.257697 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6705 11:07:48.260670 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6706 11:07:48.264567 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6707 11:07:48.271468 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6708 11:07:48.274814 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6709 11:07:48.277843 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6710 11:07:48.281236 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6711 11:07:48.287374 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6712 11:07:48.290764 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6713 11:07:48.291192 ==
6714 11:07:48.296001 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 11:07:48.297947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 11:07:48.298378 ==
6717 11:07:48.301243 DQS Delay:
6718 11:07:48.301757 DQS0 = 51, DQS1 = 59
6719 11:07:48.304218 DQM Delay:
6720 11:07:48.304700 DQM0 = 18, DQM1 = 16
6721 11:07:48.305051 DQ Delay:
6722 11:07:48.308112 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6723 11:07:48.311232 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6724 11:07:48.314597 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6725 11:07:48.317978 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6726 11:07:48.318480
6727 11:07:48.318813
6728 11:07:48.319118 ==
6729 11:07:48.321729 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 11:07:48.328414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 11:07:48.328941 ==
6732 11:07:48.329349
6733 11:07:48.329660
6734 11:07:48.329954 TX Vref Scan disable
6735 11:07:48.331675 == TX Byte 0 ==
6736 11:07:48.334966 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 11:07:48.337492 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 11:07:48.341488 == TX Byte 1 ==
6739 11:07:48.344126 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 11:07:48.347902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 11:07:48.348410 ==
6742 11:07:48.351418 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 11:07:48.358109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 11:07:48.358646 ==
6745 11:07:48.358985
6746 11:07:48.359299
6747 11:07:48.359594 TX Vref Scan disable
6748 11:07:48.360998 == TX Byte 0 ==
6749 11:07:48.364462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 11:07:48.368014 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 11:07:48.371589 == TX Byte 1 ==
6752 11:07:48.374751 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 11:07:48.377923 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 11:07:48.378426
6755 11:07:48.381750 [DATLAT]
6756 11:07:48.382254 Freq=400, CH1 RK0
6757 11:07:48.382593
6758 11:07:48.384576 DATLAT Default: 0xf
6759 11:07:48.384999 0, 0xFFFF, sum = 0
6760 11:07:48.387608 1, 0xFFFF, sum = 0
6761 11:07:48.388037 2, 0xFFFF, sum = 0
6762 11:07:48.391042 3, 0xFFFF, sum = 0
6763 11:07:48.391471 4, 0xFFFF, sum = 0
6764 11:07:48.395206 5, 0xFFFF, sum = 0
6765 11:07:48.395718 6, 0xFFFF, sum = 0
6766 11:07:48.397694 7, 0xFFFF, sum = 0
6767 11:07:48.398123 8, 0xFFFF, sum = 0
6768 11:07:48.401044 9, 0xFFFF, sum = 0
6769 11:07:48.401566 10, 0xFFFF, sum = 0
6770 11:07:48.404953 11, 0xFFFF, sum = 0
6771 11:07:48.405419 12, 0xFFFF, sum = 0
6772 11:07:48.407641 13, 0x0, sum = 1
6773 11:07:48.408110 14, 0x0, sum = 2
6774 11:07:48.411312 15, 0x0, sum = 3
6775 11:07:48.411821 16, 0x0, sum = 4
6776 11:07:48.414813 best_step = 14
6777 11:07:48.415235
6778 11:07:48.415563 ==
6779 11:07:48.418025 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 11:07:48.421378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 11:07:48.421884 ==
6782 11:07:48.424290 RX Vref Scan: 1
6783 11:07:48.424716
6784 11:07:48.425054 RX Vref 0 -> 0, step: 1
6785 11:07:48.425409
6786 11:07:48.427779 RX Delay -359 -> 252, step: 8
6787 11:07:48.428203
6788 11:07:48.431154 Set Vref, RX VrefLevel [Byte0]: 56
6789 11:07:48.434133 [Byte1]: 50
6790 11:07:48.439078
6791 11:07:48.439581 Final RX Vref Byte 0 = 56 to rank0
6792 11:07:48.442958 Final RX Vref Byte 1 = 50 to rank0
6793 11:07:48.446196 Final RX Vref Byte 0 = 56 to rank1
6794 11:07:48.449331 Final RX Vref Byte 1 = 50 to rank1==
6795 11:07:48.452974 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 11:07:48.455701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 11:07:48.459342 ==
6798 11:07:48.459769 DQS Delay:
6799 11:07:48.460160 DQS0 = 48, DQS1 = 60
6800 11:07:48.462335 DQM Delay:
6801 11:07:48.462773 DQM0 = 12, DQM1 = 12
6802 11:07:48.465679 DQ Delay:
6803 11:07:48.469344 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6804 11:07:48.469843 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6805 11:07:48.472996 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6806 11:07:48.476500 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6807 11:07:48.477053
6808 11:07:48.477440
6809 11:07:48.485848 [DQSOSCAuto] RK0, (LSB)MR18= 0x953c, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6810 11:07:48.489191 CH1 RK0: MR19=C0C, MR18=953C
6811 11:07:48.496215 CH1_RK0: MR19=0xC0C, MR18=0x953C, DQSOSC=391, MR23=63, INC=386, DEC=257
6812 11:07:48.496720 ==
6813 11:07:48.499780 Dram Type= 6, Freq= 0, CH_1, rank 1
6814 11:07:48.503257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 11:07:48.503762 ==
6816 11:07:48.505939 [Gating] SW mode calibration
6817 11:07:48.512468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6818 11:07:48.516107 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6819 11:07:48.522962 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6820 11:07:48.525907 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 11:07:48.529331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 11:07:48.536038 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 11:07:48.539551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 11:07:48.542653 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 11:07:48.550058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 11:07:48.552860 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 11:07:48.556533 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 11:07:48.559600 Total UI for P1: 0, mck2ui 16
6829 11:07:48.562553 best dqsien dly found for B0: ( 0, 14, 24)
6830 11:07:48.566126 Total UI for P1: 0, mck2ui 16
6831 11:07:48.569844 best dqsien dly found for B1: ( 0, 14, 24)
6832 11:07:48.572822 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6833 11:07:48.576076 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6834 11:07:48.576724
6835 11:07:48.579143 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6836 11:07:48.586199 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 11:07:48.586822 [Gating] SW calibration Done
6838 11:07:48.587306 ==
6839 11:07:48.589286 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 11:07:48.596131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 11:07:48.596565 ==
6842 11:07:48.596904 RX Vref Scan: 0
6843 11:07:48.597264
6844 11:07:48.600471 RX Vref 0 -> 0, step: 1
6845 11:07:48.600975
6846 11:07:48.602809 RX Delay -410 -> 252, step: 16
6847 11:07:48.607083 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6848 11:07:48.609941 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6849 11:07:48.616576 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6850 11:07:48.619849 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6851 11:07:48.623413 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6852 11:07:48.626625 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6853 11:07:48.633580 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6854 11:07:48.636324 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6855 11:07:48.639917 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6856 11:07:48.642632 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6857 11:07:48.646418 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6858 11:07:48.653642 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6859 11:07:48.656282 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6860 11:07:48.659552 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6861 11:07:48.666188 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6862 11:07:48.669325 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6863 11:07:48.669760 ==
6864 11:07:48.673273 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 11:07:48.676915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 11:07:48.677477 ==
6867 11:07:48.679352 DQS Delay:
6868 11:07:48.679777 DQS0 = 43, DQS1 = 59
6869 11:07:48.680114 DQM Delay:
6870 11:07:48.682867 DQM0 = 9, DQM1 = 17
6871 11:07:48.683368 DQ Delay:
6872 11:07:48.686555 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6873 11:07:48.689511 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6874 11:07:48.693279 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6875 11:07:48.696206 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6876 11:07:48.696725
6877 11:07:48.697061
6878 11:07:48.697433 ==
6879 11:07:48.700141 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 11:07:48.703035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 11:07:48.703467 ==
6882 11:07:48.703801
6883 11:07:48.706217
6884 11:07:48.706640 TX Vref Scan disable
6885 11:07:48.710645 == TX Byte 0 ==
6886 11:07:48.712904 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6887 11:07:48.716562 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6888 11:07:48.720271 == TX Byte 1 ==
6889 11:07:48.723234 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6890 11:07:48.727247 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6891 11:07:48.727772 ==
6892 11:07:48.729740 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 11:07:48.734071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 11:07:48.734598 ==
6895 11:07:48.734995
6896 11:07:48.735308
6897 11:07:48.736423 TX Vref Scan disable
6898 11:07:48.740092 == TX Byte 0 ==
6899 11:07:48.742921 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6900 11:07:48.746139 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6901 11:07:48.749834 == TX Byte 1 ==
6902 11:07:48.752839 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6903 11:07:48.756239 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6904 11:07:48.756672
6905 11:07:48.757006 [DATLAT]
6906 11:07:48.759836 Freq=400, CH1 RK1
6907 11:07:48.760222
6908 11:07:48.760523 DATLAT Default: 0xe
6909 11:07:48.762872 0, 0xFFFF, sum = 0
6910 11:07:48.763266 1, 0xFFFF, sum = 0
6911 11:07:48.766329 2, 0xFFFF, sum = 0
6912 11:07:48.766810 3, 0xFFFF, sum = 0
6913 11:07:48.769733 4, 0xFFFF, sum = 0
6914 11:07:48.770208 5, 0xFFFF, sum = 0
6915 11:07:48.773320 6, 0xFFFF, sum = 0
6916 11:07:48.773890 7, 0xFFFF, sum = 0
6917 11:07:48.776761 8, 0xFFFF, sum = 0
6918 11:07:48.779861 9, 0xFFFF, sum = 0
6919 11:07:48.780268 10, 0xFFFF, sum = 0
6920 11:07:48.783543 11, 0xFFFF, sum = 0
6921 11:07:48.783941 12, 0xFFFF, sum = 0
6922 11:07:48.786444 13, 0x0, sum = 1
6923 11:07:48.786844 14, 0x0, sum = 2
6924 11:07:48.790009 15, 0x0, sum = 3
6925 11:07:48.790422 16, 0x0, sum = 4
6926 11:07:48.790826 best_step = 14
6927 11:07:48.791195
6928 11:07:48.793043 ==
6929 11:07:48.796255 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 11:07:48.799469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 11:07:48.799867 ==
6932 11:07:48.800349 RX Vref Scan: 0
6933 11:07:48.800741
6934 11:07:48.803229 RX Vref 0 -> 0, step: 1
6935 11:07:48.803700
6936 11:07:48.806317 RX Delay -359 -> 252, step: 8
6937 11:07:48.813507 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6938 11:07:48.817105 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6939 11:07:48.820611 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6940 11:07:48.823820 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6941 11:07:48.830482 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6942 11:07:48.833465 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6943 11:07:48.837166 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6944 11:07:48.840992 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6945 11:07:48.846977 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6946 11:07:48.849847 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6947 11:07:48.853916 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6948 11:07:48.857471 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6949 11:07:48.863597 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6950 11:07:48.867039 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6951 11:07:48.870026 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6952 11:07:48.873693 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6953 11:07:48.876858 ==
6954 11:07:48.877419 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 11:07:48.883661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 11:07:48.884172 ==
6957 11:07:48.884514 DQS Delay:
6958 11:07:48.886992 DQS0 = 52, DQS1 = 60
6959 11:07:48.887503 DQM Delay:
6960 11:07:48.890577 DQM0 = 13, DQM1 = 13
6961 11:07:48.891014 DQ Delay:
6962 11:07:48.894288 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6963 11:07:48.897537 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6964 11:07:48.900485 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6965 11:07:48.903761 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6966 11:07:48.904259
6967 11:07:48.904594
6968 11:07:48.910676 [DQSOSCAuto] RK1, (LSB)MR18= 0x7d93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6969 11:07:48.913833 CH1 RK1: MR19=C0C, MR18=7D93
6970 11:07:48.920523 CH1_RK1: MR19=0xC0C, MR18=0x7D93, DQSOSC=391, MR23=63, INC=386, DEC=257
6971 11:07:48.923839 [RxdqsGatingPostProcess] freq 400
6972 11:07:48.927129 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6973 11:07:48.930633 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 11:07:48.933608 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 11:07:48.937236 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 11:07:48.940415 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 11:07:48.943943 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 11:07:48.947704 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 11:07:48.951198 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 11:07:48.953854 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 11:07:48.957354 Pre-setting of DQS Precalculation
6982 11:07:48.960651 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6983 11:07:48.967356 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6984 11:07:48.977317 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6985 11:07:48.977831
6986 11:07:48.978166
6987 11:07:48.978476 [Calibration Summary] 800 Mbps
6988 11:07:48.980885 CH 0, Rank 0
6989 11:07:48.981353 SW Impedance : PASS
6990 11:07:48.984043 DUTY Scan : NO K
6991 11:07:48.987528 ZQ Calibration : PASS
6992 11:07:48.988040 Jitter Meter : NO K
6993 11:07:48.990372 CBT Training : PASS
6994 11:07:48.993908 Write leveling : PASS
6995 11:07:48.994391 RX DQS gating : PASS
6996 11:07:48.997480 RX DQ/DQS(RDDQC) : PASS
6997 11:07:49.001053 TX DQ/DQS : PASS
6998 11:07:49.001609 RX DATLAT : PASS
6999 11:07:49.004229 RX DQ/DQS(Engine): PASS
7000 11:07:49.007988 TX OE : NO K
7001 11:07:49.008502 All Pass.
7002 11:07:49.008841
7003 11:07:49.009210 CH 0, Rank 1
7004 11:07:49.011197 SW Impedance : PASS
7005 11:07:49.013839 DUTY Scan : NO K
7006 11:07:49.014273 ZQ Calibration : PASS
7007 11:07:49.017847 Jitter Meter : NO K
7008 11:07:49.018363 CBT Training : PASS
7009 11:07:49.020973 Write leveling : NO K
7010 11:07:49.024486 RX DQS gating : PASS
7011 11:07:49.024997 RX DQ/DQS(RDDQC) : PASS
7012 11:07:49.027298 TX DQ/DQS : PASS
7013 11:07:49.030845 RX DATLAT : PASS
7014 11:07:49.031276 RX DQ/DQS(Engine): PASS
7015 11:07:49.034599 TX OE : NO K
7016 11:07:49.035032 All Pass.
7017 11:07:49.035430
7018 11:07:49.037343 CH 1, Rank 0
7019 11:07:49.037732 SW Impedance : PASS
7020 11:07:49.040426 DUTY Scan : NO K
7021 11:07:49.043819 ZQ Calibration : PASS
7022 11:07:49.044293 Jitter Meter : NO K
7023 11:07:49.047144 CBT Training : PASS
7024 11:07:49.051047 Write leveling : PASS
7025 11:07:49.051520 RX DQS gating : PASS
7026 11:07:49.054327 RX DQ/DQS(RDDQC) : PASS
7027 11:07:49.058050 TX DQ/DQS : PASS
7028 11:07:49.058735 RX DATLAT : PASS
7029 11:07:49.061195 RX DQ/DQS(Engine): PASS
7030 11:07:49.061670 TX OE : NO K
7031 11:07:49.064117 All Pass.
7032 11:07:49.064587
7033 11:07:49.064896 CH 1, Rank 1
7034 11:07:49.067635 SW Impedance : PASS
7035 11:07:49.068120 DUTY Scan : NO K
7036 11:07:49.070355 ZQ Calibration : PASS
7037 11:07:49.073836 Jitter Meter : NO K
7038 11:07:49.074244 CBT Training : PASS
7039 11:07:49.077187 Write leveling : NO K
7040 11:07:49.080969 RX DQS gating : PASS
7041 11:07:49.081484 RX DQ/DQS(RDDQC) : PASS
7042 11:07:49.085009 TX DQ/DQS : PASS
7043 11:07:49.087421 RX DATLAT : PASS
7044 11:07:49.087890 RX DQ/DQS(Engine): PASS
7045 11:07:49.090512 TX OE : NO K
7046 11:07:49.090905 All Pass.
7047 11:07:49.091208
7048 11:07:49.093612 DramC Write-DBI off
7049 11:07:49.097180 PER_BANK_REFRESH: Hybrid Mode
7050 11:07:49.097572 TX_TRACKING: ON
7051 11:07:49.107376 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7052 11:07:49.110491 [FAST_K] Save calibration result to emmc
7053 11:07:49.113817 dramc_set_vcore_voltage set vcore to 725000
7054 11:07:49.117679 Read voltage for 1600, 0
7055 11:07:49.118189 Vio18 = 0
7056 11:07:49.118529 Vcore = 725000
7057 11:07:49.120653 Vdram = 0
7058 11:07:49.121196 Vddq = 0
7059 11:07:49.121541 Vmddr = 0
7060 11:07:49.127659 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7061 11:07:49.130639 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7062 11:07:49.133868 MEM_TYPE=3, freq_sel=13
7063 11:07:49.137321 sv_algorithm_assistance_LP4_3733
7064 11:07:49.140770 ============ PULL DRAM RESETB DOWN ============
7065 11:07:49.143556 ========== PULL DRAM RESETB DOWN end =========
7066 11:07:49.150639 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7067 11:07:49.154329 ===================================
7068 11:07:49.154840 LPDDR4 DRAM CONFIGURATION
7069 11:07:49.157055 ===================================
7070 11:07:49.160664 EX_ROW_EN[0] = 0x0
7071 11:07:49.164042 EX_ROW_EN[1] = 0x0
7072 11:07:49.164553 LP4Y_EN = 0x0
7073 11:07:49.167716 WORK_FSP = 0x1
7074 11:07:49.168226 WL = 0x5
7075 11:07:49.170740 RL = 0x5
7076 11:07:49.171253 BL = 0x2
7077 11:07:49.174097 RPST = 0x0
7078 11:07:49.174524 RD_PRE = 0x0
7079 11:07:49.177566 WR_PRE = 0x1
7080 11:07:49.178078 WR_PST = 0x1
7081 11:07:49.180690 DBI_WR = 0x0
7082 11:07:49.181237 DBI_RD = 0x0
7083 11:07:49.183657 OTF = 0x1
7084 11:07:49.187137 ===================================
7085 11:07:49.190699 ===================================
7086 11:07:49.191128 ANA top config
7087 11:07:49.193907 ===================================
7088 11:07:49.197374 DLL_ASYNC_EN = 0
7089 11:07:49.200353 ALL_SLAVE_EN = 0
7090 11:07:49.200867 NEW_RANK_MODE = 1
7091 11:07:49.203658 DLL_IDLE_MODE = 1
7092 11:07:49.206823 LP45_APHY_COMB_EN = 1
7093 11:07:49.210291 TX_ODT_DIS = 0
7094 11:07:49.213883 NEW_8X_MODE = 1
7095 11:07:49.217175 ===================================
7096 11:07:49.220224 ===================================
7097 11:07:49.220614 data_rate = 3200
7098 11:07:49.223902 CKR = 1
7099 11:07:49.226896 DQ_P2S_RATIO = 8
7100 11:07:49.230109 ===================================
7101 11:07:49.233680 CA_P2S_RATIO = 8
7102 11:07:49.237313 DQ_CA_OPEN = 0
7103 11:07:49.240188 DQ_SEMI_OPEN = 0
7104 11:07:49.240578 CA_SEMI_OPEN = 0
7105 11:07:49.244194 CA_FULL_RATE = 0
7106 11:07:49.247071 DQ_CKDIV4_EN = 0
7107 11:07:49.250522 CA_CKDIV4_EN = 0
7108 11:07:49.253616 CA_PREDIV_EN = 0
7109 11:07:49.257533 PH8_DLY = 12
7110 11:07:49.258309 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7111 11:07:49.260987 DQ_AAMCK_DIV = 4
7112 11:07:49.263781 CA_AAMCK_DIV = 4
7113 11:07:49.267564 CA_ADMCK_DIV = 4
7114 11:07:49.271377 DQ_TRACK_CA_EN = 0
7115 11:07:49.274186 CA_PICK = 1600
7116 11:07:49.274691 CA_MCKIO = 1600
7117 11:07:49.277102 MCKIO_SEMI = 0
7118 11:07:49.280516 PLL_FREQ = 3068
7119 11:07:49.283933 DQ_UI_PI_RATIO = 32
7120 11:07:49.287198 CA_UI_PI_RATIO = 0
7121 11:07:49.290520 ===================================
7122 11:07:49.293977 ===================================
7123 11:07:49.297074 memory_type:LPDDR4
7124 11:07:49.297495 GP_NUM : 10
7125 11:07:49.300331 SRAM_EN : 1
7126 11:07:49.300719 MD32_EN : 0
7127 11:07:49.303634 ===================================
7128 11:07:49.307142 [ANA_INIT] >>>>>>>>>>>>>>
7129 11:07:49.310144 <<<<<< [CONFIGURE PHASE]: ANA_TX
7130 11:07:49.313825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7131 11:07:49.317083 ===================================
7132 11:07:49.321151 data_rate = 3200,PCW = 0X7600
7133 11:07:49.324106 ===================================
7134 11:07:49.327228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7135 11:07:49.330490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7136 11:07:49.336993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 11:07:49.344380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7138 11:07:49.347165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7139 11:07:49.351231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7140 11:07:49.351715 [ANA_INIT] flow start
7141 11:07:49.354068 [ANA_INIT] PLL >>>>>>>>
7142 11:07:49.357233 [ANA_INIT] PLL <<<<<<<<
7143 11:07:49.357656 [ANA_INIT] MIDPI >>>>>>>>
7144 11:07:49.360884 [ANA_INIT] MIDPI <<<<<<<<
7145 11:07:49.364125 [ANA_INIT] DLL >>>>>>>>
7146 11:07:49.364562 [ANA_INIT] DLL <<<<<<<<
7147 11:07:49.367620 [ANA_INIT] flow end
7148 11:07:49.370284 ============ LP4 DIFF to SE enter ============
7149 11:07:49.373991 ============ LP4 DIFF to SE exit ============
7150 11:07:49.377372 [ANA_INIT] <<<<<<<<<<<<<
7151 11:07:49.380485 [Flow] Enable top DCM control >>>>>
7152 11:07:49.383815 [Flow] Enable top DCM control <<<<<
7153 11:07:49.388145 Enable DLL master slave shuffle
7154 11:07:49.394386 ==============================================================
7155 11:07:49.394834 Gating Mode config
7156 11:07:49.400832 ==============================================================
7157 11:07:49.401407 Config description:
7158 11:07:49.410836 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7159 11:07:49.418047 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7160 11:07:49.424044 SELPH_MODE 0: By rank 1: By Phase
7161 11:07:49.427752 ==============================================================
7162 11:07:49.430860 GAT_TRACK_EN = 1
7163 11:07:49.434706 RX_GATING_MODE = 2
7164 11:07:49.437629 RX_GATING_TRACK_MODE = 2
7165 11:07:49.440987 SELPH_MODE = 1
7166 11:07:49.444414 PICG_EARLY_EN = 1
7167 11:07:49.447515 VALID_LAT_VALUE = 1
7168 11:07:49.450830 ==============================================================
7169 11:07:49.454126 Enter into Gating configuration >>>>
7170 11:07:49.457743 Exit from Gating configuration <<<<
7171 11:07:49.460988 Enter into DVFS_PRE_config >>>>>
7172 11:07:49.474647 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7173 11:07:49.477692 Exit from DVFS_PRE_config <<<<<
7174 11:07:49.478084 Enter into PICG configuration >>>>
7175 11:07:49.480747 Exit from PICG configuration <<<<
7176 11:07:49.484233 [RX_INPUT] configuration >>>>>
7177 11:07:49.488511 [RX_INPUT] configuration <<<<<
7178 11:07:49.494852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7179 11:07:49.497077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7180 11:07:49.504200 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 11:07:49.511519 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 11:07:49.517972 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 11:07:49.524519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 11:07:49.527726 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7185 11:07:49.531260 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7186 11:07:49.534938 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7187 11:07:49.541015 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7188 11:07:49.544755 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7189 11:07:49.547703 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7190 11:07:49.550958 ===================================
7191 11:07:49.554937 LPDDR4 DRAM CONFIGURATION
7192 11:07:49.557694 ===================================
7193 11:07:49.558129 EX_ROW_EN[0] = 0x0
7194 11:07:49.561215 EX_ROW_EN[1] = 0x0
7195 11:07:49.564189 LP4Y_EN = 0x0
7196 11:07:49.564617 WORK_FSP = 0x1
7197 11:07:49.567553 WL = 0x5
7198 11:07:49.567938 RL = 0x5
7199 11:07:49.571055 BL = 0x2
7200 11:07:49.571519 RPST = 0x0
7201 11:07:49.574394 RD_PRE = 0x0
7202 11:07:49.574886 WR_PRE = 0x1
7203 11:07:49.577886 WR_PST = 0x1
7204 11:07:49.578349 DBI_WR = 0x0
7205 11:07:49.581261 DBI_RD = 0x0
7206 11:07:49.581763 OTF = 0x1
7207 11:07:49.584372 ===================================
7208 11:07:49.588032 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7209 11:07:49.594601 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7210 11:07:49.597860 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 11:07:49.601295 ===================================
7212 11:07:49.604759 LPDDR4 DRAM CONFIGURATION
7213 11:07:49.607706 ===================================
7214 11:07:49.608214 EX_ROW_EN[0] = 0x10
7215 11:07:49.611390 EX_ROW_EN[1] = 0x0
7216 11:07:49.611893 LP4Y_EN = 0x0
7217 11:07:49.614044 WORK_FSP = 0x1
7218 11:07:49.614468 WL = 0x5
7219 11:07:49.617521 RL = 0x5
7220 11:07:49.617945 BL = 0x2
7221 11:07:49.621070 RPST = 0x0
7222 11:07:49.621628 RD_PRE = 0x0
7223 11:07:49.624476 WR_PRE = 0x1
7224 11:07:49.627713 WR_PST = 0x1
7225 11:07:49.628150 DBI_WR = 0x0
7226 11:07:49.630647 DBI_RD = 0x0
7227 11:07:49.631070 OTF = 0x1
7228 11:07:49.634998 ===================================
7229 11:07:49.640905 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7230 11:07:49.641385 ==
7231 11:07:49.644089 Dram Type= 6, Freq= 0, CH_0, rank 0
7232 11:07:49.647521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7233 11:07:49.647908 ==
7234 11:07:49.651176 [Duty_Offset_Calibration]
7235 11:07:49.651724 B0:2 B1:-1 CA:1
7236 11:07:49.654688
7237 11:07:49.655070 [DutyScan_Calibration_Flow] k_type=0
7238 11:07:49.665098
7239 11:07:49.665686 ==CLK 0==
7240 11:07:49.667867 Final CLK duty delay cell = -4
7241 11:07:49.671881 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7242 11:07:49.674502 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7243 11:07:49.678601 [-4] AVG Duty = 4937%(X100)
7244 11:07:49.679061
7245 11:07:49.681389 CH0 CLK Duty spec in!! Max-Min= 187%
7246 11:07:49.685153 [DutyScan_Calibration_Flow] ====Done====
7247 11:07:49.685713
7248 11:07:49.688599 [DutyScan_Calibration_Flow] k_type=1
7249 11:07:49.704534
7250 11:07:49.705034 ==DQS 0 ==
7251 11:07:49.707618 Final DQS duty delay cell = 0
7252 11:07:49.710516 [0] MAX Duty = 5125%(X100), DQS PI = 20
7253 11:07:49.714359 [0] MIN Duty = 5000%(X100), DQS PI = 14
7254 11:07:49.717781 [0] AVG Duty = 5062%(X100)
7255 11:07:49.718285
7256 11:07:49.718616 ==DQS 1 ==
7257 11:07:49.721383 Final DQS duty delay cell = -4
7258 11:07:49.724442 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7259 11:07:49.728307 [-4] MIN Duty = 5031%(X100), DQS PI = 24
7260 11:07:49.730744 [-4] AVG Duty = 5062%(X100)
7261 11:07:49.731172
7262 11:07:49.733913 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7263 11:07:49.734338
7264 11:07:49.737526 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7265 11:07:49.741843 [DutyScan_Calibration_Flow] ====Done====
7266 11:07:49.742352
7267 11:07:49.744191 [DutyScan_Calibration_Flow] k_type=3
7268 11:07:49.761954
7269 11:07:49.762464 ==DQM 0 ==
7270 11:07:49.765493 Final DQM duty delay cell = 0
7271 11:07:49.768595 [0] MAX Duty = 5000%(X100), DQS PI = 18
7272 11:07:49.771995 [0] MIN Duty = 4875%(X100), DQS PI = 4
7273 11:07:49.772505 [0] AVG Duty = 4937%(X100)
7274 11:07:49.775335
7275 11:07:49.775857 ==DQM 1 ==
7276 11:07:49.778191 Final DQM duty delay cell = 0
7277 11:07:49.781440 [0] MAX Duty = 5187%(X100), DQS PI = 58
7278 11:07:49.784745 [0] MIN Duty = 4969%(X100), DQS PI = 18
7279 11:07:49.785213 [0] AVG Duty = 5078%(X100)
7280 11:07:49.788567
7281 11:07:49.791443 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7282 11:07:49.791870
7283 11:07:49.794423 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7284 11:07:49.797920 [DutyScan_Calibration_Flow] ====Done====
7285 11:07:49.798306
7286 11:07:49.801770 [DutyScan_Calibration_Flow] k_type=2
7287 11:07:49.818488
7288 11:07:49.818994 ==DQ 0 ==
7289 11:07:49.821847 Final DQ duty delay cell = -4
7290 11:07:49.824864 [-4] MAX Duty = 5000%(X100), DQS PI = 56
7291 11:07:49.827972 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7292 11:07:49.831252 [-4] AVG Duty = 4922%(X100)
7293 11:07:49.831755
7294 11:07:49.832089 ==DQ 1 ==
7295 11:07:49.835001 Final DQ duty delay cell = 0
7296 11:07:49.837748 [0] MAX Duty = 5031%(X100), DQS PI = 30
7297 11:07:49.841542 [0] MIN Duty = 4907%(X100), DQS PI = 18
7298 11:07:49.844721 [0] AVG Duty = 4969%(X100)
7299 11:07:49.845287
7300 11:07:49.848525 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7301 11:07:49.848959
7302 11:07:49.851411 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7303 11:07:49.854455 [DutyScan_Calibration_Flow] ====Done====
7304 11:07:49.854901 ==
7305 11:07:49.857870 Dram Type= 6, Freq= 0, CH_1, rank 0
7306 11:07:49.861008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7307 11:07:49.861422 ==
7308 11:07:49.865322 [Duty_Offset_Calibration]
7309 11:07:49.865703 B0:1 B1:1 CA:2
7310 11:07:49.866024
7311 11:07:49.867780 [DutyScan_Calibration_Flow] k_type=0
7312 11:07:49.878524
7313 11:07:49.878906 ==CLK 0==
7314 11:07:49.881488 Final CLK duty delay cell = 0
7315 11:07:49.884843 [0] MAX Duty = 5187%(X100), DQS PI = 24
7316 11:07:49.888379 [0] MIN Duty = 4969%(X100), DQS PI = 40
7317 11:07:49.888761 [0] AVG Duty = 5078%(X100)
7318 11:07:49.891660
7319 11:07:49.892037 CH1 CLK Duty spec in!! Max-Min= 218%
7320 11:07:49.898169 [DutyScan_Calibration_Flow] ====Done====
7321 11:07:49.898552
7322 11:07:49.902191 [DutyScan_Calibration_Flow] k_type=1
7323 11:07:49.918442
7324 11:07:49.919039 ==DQS 0 ==
7325 11:07:49.921240 Final DQS duty delay cell = 0
7326 11:07:49.924939 [0] MAX Duty = 5062%(X100), DQS PI = 22
7327 11:07:49.927861 [0] MIN Duty = 4813%(X100), DQS PI = 52
7328 11:07:49.931765 [0] AVG Duty = 4937%(X100)
7329 11:07:49.932274
7330 11:07:49.932607 ==DQS 1 ==
7331 11:07:49.935066 Final DQS duty delay cell = 0
7332 11:07:49.938068 [0] MAX Duty = 5031%(X100), DQS PI = 54
7333 11:07:49.941838 [0] MIN Duty = 4938%(X100), DQS PI = 12
7334 11:07:49.942349 [0] AVG Duty = 4984%(X100)
7335 11:07:49.942684
7336 11:07:49.948387 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7337 11:07:49.948889
7338 11:07:49.951718 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7339 11:07:49.955140 [DutyScan_Calibration_Flow] ====Done====
7340 11:07:49.955650
7341 11:07:49.958047 [DutyScan_Calibration_Flow] k_type=3
7342 11:07:49.975271
7343 11:07:49.975780 ==DQM 0 ==
7344 11:07:49.977982 Final DQM duty delay cell = 0
7345 11:07:49.981093 [0] MAX Duty = 5124%(X100), DQS PI = 18
7346 11:07:49.984886 [0] MIN Duty = 4844%(X100), DQS PI = 50
7347 11:07:49.987910 [0] AVG Duty = 4984%(X100)
7348 11:07:49.988337
7349 11:07:49.988663 ==DQM 1 ==
7350 11:07:49.991182 Final DQM duty delay cell = 0
7351 11:07:49.994748 [0] MAX Duty = 5156%(X100), DQS PI = 60
7352 11:07:49.998266 [0] MIN Duty = 4907%(X100), DQS PI = 18
7353 11:07:50.001060 [0] AVG Duty = 5031%(X100)
7354 11:07:50.001473
7355 11:07:50.004827 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7356 11:07:50.005249
7357 11:07:50.008104 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7358 11:07:50.011397 [DutyScan_Calibration_Flow] ====Done====
7359 11:07:50.011780
7360 11:07:50.014549 [DutyScan_Calibration_Flow] k_type=2
7361 11:07:50.031467
7362 11:07:50.031967 ==DQ 0 ==
7363 11:07:50.034978 Final DQ duty delay cell = 0
7364 11:07:50.038327 [0] MAX Duty = 5125%(X100), DQS PI = 18
7365 11:07:50.041671 [0] MIN Duty = 4907%(X100), DQS PI = 52
7366 11:07:50.042052 [0] AVG Duty = 5016%(X100)
7367 11:07:50.042351
7368 11:07:50.045401 ==DQ 1 ==
7369 11:07:50.048364 Final DQ duty delay cell = 0
7370 11:07:50.052090 [0] MAX Duty = 5093%(X100), DQS PI = 6
7371 11:07:50.055129 [0] MIN Duty = 5031%(X100), DQS PI = 0
7372 11:07:50.055593 [0] AVG Duty = 5062%(X100)
7373 11:07:50.055896
7374 11:07:50.058214 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7375 11:07:50.058593
7376 11:07:50.061745 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7377 11:07:50.069081 [DutyScan_Calibration_Flow] ====Done====
7378 11:07:50.072154 nWR fixed to 30
7379 11:07:50.072614 [ModeRegInit_LP4] CH0 RK0
7380 11:07:50.075597 [ModeRegInit_LP4] CH0 RK1
7381 11:07:50.079028 [ModeRegInit_LP4] CH1 RK0
7382 11:07:50.079489 [ModeRegInit_LP4] CH1 RK1
7383 11:07:50.081780 match AC timing 5
7384 11:07:50.085798 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7385 11:07:50.088601 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7386 11:07:50.094819 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7387 11:07:50.099140 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7388 11:07:50.105349 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7389 11:07:50.105870 [MiockJmeterHQA]
7390 11:07:50.106208
7391 11:07:50.108484 [DramcMiockJmeter] u1RxGatingPI = 0
7392 11:07:50.108971 0 : 4253, 4027
7393 11:07:50.111599 4 : 4254, 4029
7394 11:07:50.112024 8 : 4252, 4027
7395 11:07:50.115208 12 : 4260, 4035
7396 11:07:50.115725 16 : 4252, 4027
7397 11:07:50.119317 20 : 4252, 4027
7398 11:07:50.120058 24 : 4254, 4029
7399 11:07:50.120418 28 : 4363, 4137
7400 11:07:50.121719 32 : 4253, 4027
7401 11:07:50.122156 36 : 4258, 4029
7402 11:07:50.125024 40 : 4255, 4030
7403 11:07:50.125515 44 : 4252, 4026
7404 11:07:50.129452 48 : 4252, 4027
7405 11:07:50.130034 52 : 4252, 4026
7406 11:07:50.130357 56 : 4252, 4027
7407 11:07:50.132067 60 : 4361, 4137
7408 11:07:50.132461 64 : 4365, 4140
7409 11:07:50.135345 68 : 4361, 4137
7410 11:07:50.135761 72 : 4250, 4027
7411 11:07:50.138608 76 : 4252, 4029
7412 11:07:50.138996 80 : 4253, 4027
7413 11:07:50.141636 84 : 4254, 4029
7414 11:07:50.142165 88 : 4361, 4137
7415 11:07:50.142486 92 : 4257, 4029
7416 11:07:50.145492 96 : 4361, 3558
7417 11:07:50.146011 100 : 4252, 0
7418 11:07:50.148651 104 : 4250, 0
7419 11:07:50.149043 108 : 4253, 0
7420 11:07:50.149416 112 : 4252, 0
7421 11:07:50.152177 116 : 4253, 0
7422 11:07:50.152647 120 : 4252, 0
7423 11:07:50.155765 124 : 4361, 0
7424 11:07:50.156242 128 : 4255, 0
7425 11:07:50.156553 132 : 4255, 0
7426 11:07:50.158714 136 : 4255, 0
7427 11:07:50.159103 140 : 4365, 0
7428 11:07:50.161797 144 : 4252, 0
7429 11:07:50.162189 148 : 4365, 0
7430 11:07:50.162493 152 : 4252, 0
7431 11:07:50.165406 156 : 4255, 0
7432 11:07:50.165796 160 : 4257, 0
7433 11:07:50.166097 164 : 4252, 0
7434 11:07:50.169368 168 : 4253, 0
7435 11:07:50.169845 172 : 4255, 0
7436 11:07:50.171894 176 : 4250, 0
7437 11:07:50.172282 180 : 4250, 0
7438 11:07:50.172586 184 : 4361, 0
7439 11:07:50.175875 188 : 4366, 0
7440 11:07:50.176356 192 : 4252, 0
7441 11:07:50.179481 196 : 4361, 0
7442 11:07:50.179875 200 : 4250, 0
7443 11:07:50.180181 204 : 4255, 0
7444 11:07:50.182416 208 : 4250, 0
7445 11:07:50.182895 212 : 4252, 66
7446 11:07:50.185972 216 : 4250, 3806
7447 11:07:50.186459 220 : 4363, 4137
7448 11:07:50.189086 224 : 4252, 4029
7449 11:07:50.189519 228 : 4360, 4137
7450 11:07:50.189826 232 : 4363, 4139
7451 11:07:50.191875 236 : 4250, 4026
7452 11:07:50.192263 240 : 4250, 4027
7453 11:07:50.196042 244 : 4361, 4137
7454 11:07:50.196505 248 : 4250, 4027
7455 11:07:50.198750 252 : 4250, 4027
7456 11:07:50.199139 256 : 4250, 4027
7457 11:07:50.202188 260 : 4255, 4032
7458 11:07:50.202667 264 : 4255, 4029
7459 11:07:50.205374 268 : 4361, 4137
7460 11:07:50.205844 272 : 4252, 4029
7461 11:07:50.209572 276 : 4255, 4029
7462 11:07:50.210049 280 : 4365, 4140
7463 11:07:50.211710 284 : 4360, 4138
7464 11:07:50.212170 288 : 4250, 4026
7465 11:07:50.212481 292 : 4250, 4026
7466 11:07:50.215794 296 : 4255, 4029
7467 11:07:50.216266 300 : 4250, 4026
7468 11:07:50.219226 304 : 4252, 4029
7469 11:07:50.219695 308 : 4363, 4139
7470 11:07:50.222445 312 : 4250, 4027
7471 11:07:50.222919 316 : 4363, 4140
7472 11:07:50.225309 320 : 4360, 4137
7473 11:07:50.225700 324 : 4361, 4137
7474 11:07:50.228588 328 : 4247, 4025
7475 11:07:50.229060 332 : 4250, 3236
7476 11:07:50.231870 336 : 4360, 88
7477 11:07:50.232262
7478 11:07:50.232563 MIOCK jitter meter ch=0
7479 11:07:50.232841
7480 11:07:50.234912 1T = (336-100) = 236 dly cells
7481 11:07:50.242064 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7482 11:07:50.242452 ==
7483 11:07:50.244908 Dram Type= 6, Freq= 0, CH_0, rank 0
7484 11:07:50.249006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7485 11:07:50.249432 ==
7486 11:07:50.255413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7487 11:07:50.258473 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7488 11:07:50.262061 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7489 11:07:50.269271 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7490 11:07:50.278325 [CA 0] Center 44 (14~75) winsize 62
7491 11:07:50.281526 [CA 1] Center 44 (14~74) winsize 61
7492 11:07:50.284969 [CA 2] Center 39 (10~68) winsize 59
7493 11:07:50.288533 [CA 3] Center 39 (10~68) winsize 59
7494 11:07:50.291581 [CA 4] Center 37 (7~67) winsize 61
7495 11:07:50.294540 [CA 5] Center 37 (7~67) winsize 61
7496 11:07:50.294969
7497 11:07:50.297816 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7498 11:07:50.298202
7499 11:07:50.301656 [CATrainingPosCal] consider 1 rank data
7500 11:07:50.305073 u2DelayCellTimex100 = 275/100 ps
7501 11:07:50.308529 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7502 11:07:50.315166 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7503 11:07:50.318605 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7504 11:07:50.321578 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7505 11:07:50.325143 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7506 11:07:50.328003 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7507 11:07:50.328430
7508 11:07:50.331720 CA PerBit enable=1, Macro0, CA PI delay=37
7509 11:07:50.332230
7510 11:07:50.335322 [CBTSetCACLKResult] CA Dly = 37
7511 11:07:50.338000 CS Dly: 11 (0~42)
7512 11:07:50.341221 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7513 11:07:50.345667 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7514 11:07:50.346168 ==
7515 11:07:50.348186 Dram Type= 6, Freq= 0, CH_0, rank 1
7516 11:07:50.351360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 11:07:50.351844 ==
7518 11:07:50.358099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 11:07:50.361684 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 11:07:50.368300 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 11:07:50.371684 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 11:07:50.381586 [CA 0] Center 44 (14~75) winsize 62
7523 11:07:50.385113 [CA 1] Center 44 (14~75) winsize 62
7524 11:07:50.388584 [CA 2] Center 40 (10~70) winsize 61
7525 11:07:50.392330 [CA 3] Center 39 (10~69) winsize 60
7526 11:07:50.395072 [CA 4] Center 37 (8~67) winsize 60
7527 11:07:50.398657 [CA 5] Center 37 (7~67) winsize 61
7528 11:07:50.399119
7529 11:07:50.401984 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7530 11:07:50.402376
7531 11:07:50.404978 [CATrainingPosCal] consider 2 rank data
7532 11:07:50.408495 u2DelayCellTimex100 = 275/100 ps
7533 11:07:50.411857 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7534 11:07:50.418452 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7535 11:07:50.421572 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7536 11:07:50.425305 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7537 11:07:50.428444 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7538 11:07:50.431670 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7539 11:07:50.432060
7540 11:07:50.435137 CA PerBit enable=1, Macro0, CA PI delay=37
7541 11:07:50.435525
7542 11:07:50.438529 [CBTSetCACLKResult] CA Dly = 37
7543 11:07:50.441647 CS Dly: 12 (0~44)
7544 11:07:50.444648 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 11:07:50.448493 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 11:07:50.448884
7547 11:07:50.452036 ----->DramcWriteLeveling(PI) begin...
7548 11:07:50.452512 ==
7549 11:07:50.454624 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 11:07:50.461631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 11:07:50.462088 ==
7552 11:07:50.465008 Write leveling (Byte 0): 32 => 32
7553 11:07:50.465458 Write leveling (Byte 1): 27 => 27
7554 11:07:50.468529 DramcWriteLeveling(PI) end<-----
7555 11:07:50.468918
7556 11:07:50.469311 ==
7557 11:07:50.471554 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 11:07:50.478243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 11:07:50.478636 ==
7560 11:07:50.481634 [Gating] SW mode calibration
7561 11:07:50.488402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7562 11:07:50.491496 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7563 11:07:50.497994 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 11:07:50.501204 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 11:07:50.504843 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:07:50.511831 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 11:07:50.515523 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7568 11:07:50.518227 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7569 11:07:50.521484 1 4 24 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
7570 11:07:50.527816 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 11:07:50.531779 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 11:07:50.537875 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 11:07:50.540852 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 11:07:50.544680 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 11:07:50.547765 1 5 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7576 11:07:50.554674 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7577 11:07:50.557923 1 5 24 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7578 11:07:50.561365 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 11:07:50.567884 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 11:07:50.571639 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 11:07:50.574821 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 11:07:50.581109 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7583 11:07:50.584612 1 6 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7584 11:07:50.587522 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7585 11:07:50.594169 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7586 11:07:50.597573 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 11:07:50.601164 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 11:07:50.607589 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 11:07:50.611007 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 11:07:50.614731 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 11:07:50.621625 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 11:07:50.624798 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7593 11:07:50.628077 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 11:07:50.634522 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 11:07:50.637854 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:07:50.641446 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 11:07:50.645010 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 11:07:50.651783 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 11:07:50.654781 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 11:07:50.658115 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 11:07:50.664927 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 11:07:50.667790 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 11:07:50.671144 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 11:07:50.678087 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 11:07:50.681658 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 11:07:50.684933 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7607 11:07:50.692095 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 11:07:50.694842 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7609 11:07:50.698154 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 11:07:50.701084 Total UI for P1: 0, mck2ui 16
7611 11:07:50.704484 best dqsien dly found for B0: ( 1, 9, 16)
7612 11:07:50.707868 Total UI for P1: 0, mck2ui 16
7613 11:07:50.711484 best dqsien dly found for B1: ( 1, 9, 20)
7614 11:07:50.714794 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7615 11:07:50.717903 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7616 11:07:50.718296
7617 11:07:50.721655 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7618 11:07:50.728166 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7619 11:07:50.728682 [Gating] SW calibration Done
7620 11:07:50.729047 ==
7621 11:07:50.731260 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 11:07:50.738018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 11:07:50.738414 ==
7624 11:07:50.738720 RX Vref Scan: 0
7625 11:07:50.739005
7626 11:07:50.741078 RX Vref 0 -> 0, step: 1
7627 11:07:50.741506
7628 11:07:50.744610 RX Delay 0 -> 252, step: 8
7629 11:07:50.748324 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7630 11:07:50.751282 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7631 11:07:50.754765 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7632 11:07:50.761470 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7633 11:07:50.765019 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7634 11:07:50.768281 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7635 11:07:50.771777 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7636 11:07:50.774767 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7637 11:07:50.778166 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7638 11:07:50.785551 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7639 11:07:50.788274 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7640 11:07:50.792059 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7641 11:07:50.794870 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7642 11:07:50.798326 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7643 11:07:50.804980 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7644 11:07:50.808308 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7645 11:07:50.808702 ==
7646 11:07:50.811374 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 11:07:50.814468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 11:07:50.814861 ==
7649 11:07:50.818227 DQS Delay:
7650 11:07:50.818616 DQS0 = 0, DQS1 = 0
7651 11:07:50.818922 DQM Delay:
7652 11:07:50.821230 DQM0 = 132, DQM1 = 124
7653 11:07:50.821710 DQ Delay:
7654 11:07:50.824558 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7655 11:07:50.828077 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7656 11:07:50.831366 DQ8 =111, DQ9 =115, DQ10 =119, DQ11 =119
7657 11:07:50.837988 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7658 11:07:50.838377
7659 11:07:50.838677
7660 11:07:50.839063 ==
7661 11:07:50.841428 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 11:07:50.844562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 11:07:50.844951 ==
7664 11:07:50.845353
7665 11:07:50.845654
7666 11:07:50.848009 TX Vref Scan disable
7667 11:07:50.848397 == TX Byte 0 ==
7668 11:07:50.854900 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7669 11:07:50.858634 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7670 11:07:50.859055 == TX Byte 1 ==
7671 11:07:50.865449 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7672 11:07:50.868557 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7673 11:07:50.869042 ==
7674 11:07:50.871702 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 11:07:50.875273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 11:07:50.875736 ==
7677 11:07:50.890110
7678 11:07:50.893661 TX Vref early break, caculate TX vref
7679 11:07:50.897356 TX Vref=16, minBit 1, minWin=21, winSum=352
7680 11:07:50.900965 TX Vref=18, minBit 1, minWin=21, winSum=365
7681 11:07:50.903468 TX Vref=20, minBit 4, minWin=22, winSum=379
7682 11:07:50.906720 TX Vref=22, minBit 1, minWin=22, winSum=380
7683 11:07:50.909946 TX Vref=24, minBit 1, minWin=23, winSum=395
7684 11:07:50.917080 TX Vref=26, minBit 1, minWin=24, winSum=406
7685 11:07:50.920697 TX Vref=28, minBit 3, minWin=24, winSum=413
7686 11:07:50.923769 TX Vref=30, minBit 4, minWin=24, winSum=415
7687 11:07:50.926846 TX Vref=32, minBit 4, minWin=23, winSum=406
7688 11:07:50.930205 TX Vref=34, minBit 4, minWin=23, winSum=396
7689 11:07:50.933553 TX Vref=36, minBit 0, minWin=23, winSum=383
7690 11:07:50.940361 [TxChooseVref] Worse bit 4, Min win 24, Win sum 415, Final Vref 30
7691 11:07:50.940826
7692 11:07:50.944282 Final TX Range 0 Vref 30
7693 11:07:50.944676
7694 11:07:50.944975 ==
7695 11:07:50.947041 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 11:07:50.950240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 11:07:50.950631 ==
7698 11:07:50.950935
7699 11:07:50.951227
7700 11:07:50.953623 TX Vref Scan disable
7701 11:07:50.960456 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7702 11:07:50.960916 == TX Byte 0 ==
7703 11:07:50.964272 u2DelayCellOfst[0]=14 cells (4 PI)
7704 11:07:50.967368 u2DelayCellOfst[1]=17 cells (5 PI)
7705 11:07:50.970496 u2DelayCellOfst[2]=10 cells (3 PI)
7706 11:07:50.974065 u2DelayCellOfst[3]=10 cells (3 PI)
7707 11:07:50.977335 u2DelayCellOfst[4]=7 cells (2 PI)
7708 11:07:50.980348 u2DelayCellOfst[5]=0 cells (0 PI)
7709 11:07:50.983921 u2DelayCellOfst[6]=17 cells (5 PI)
7710 11:07:50.984314 u2DelayCellOfst[7]=17 cells (5 PI)
7711 11:07:50.990952 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7712 11:07:50.993930 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7713 11:07:50.994362 == TX Byte 1 ==
7714 11:07:50.997286 u2DelayCellOfst[8]=0 cells (0 PI)
7715 11:07:51.000447 u2DelayCellOfst[9]=0 cells (0 PI)
7716 11:07:51.004136 u2DelayCellOfst[10]=7 cells (2 PI)
7717 11:07:51.007174 u2DelayCellOfst[11]=0 cells (0 PI)
7718 11:07:51.010535 u2DelayCellOfst[12]=14 cells (4 PI)
7719 11:07:51.013947 u2DelayCellOfst[13]=10 cells (3 PI)
7720 11:07:51.017760 u2DelayCellOfst[14]=17 cells (5 PI)
7721 11:07:51.020636 u2DelayCellOfst[15]=14 cells (4 PI)
7722 11:07:51.024426 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7723 11:07:51.027269 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7724 11:07:51.031631 DramC Write-DBI on
7725 11:07:51.032132 ==
7726 11:07:51.033926 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 11:07:51.037301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 11:07:51.037806 ==
7729 11:07:51.038149
7730 11:07:51.038460
7731 11:07:51.040505 TX Vref Scan disable
7732 11:07:51.044249 == TX Byte 0 ==
7733 11:07:51.047272 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7734 11:07:51.050732 == TX Byte 1 ==
7735 11:07:51.054139 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7736 11:07:51.054645 DramC Write-DBI off
7737 11:07:51.054986
7738 11:07:51.057435 [DATLAT]
7739 11:07:51.057869 Freq=1600, CH0 RK0
7740 11:07:51.058212
7741 11:07:51.060730 DATLAT Default: 0xf
7742 11:07:51.061210 0, 0xFFFF, sum = 0
7743 11:07:51.064003 1, 0xFFFF, sum = 0
7744 11:07:51.064431 2, 0xFFFF, sum = 0
7745 11:07:51.068221 3, 0xFFFF, sum = 0
7746 11:07:51.068740 4, 0xFFFF, sum = 0
7747 11:07:51.071966 5, 0xFFFF, sum = 0
7748 11:07:51.072480 6, 0xFFFF, sum = 0
7749 11:07:51.074216 7, 0xFFFF, sum = 0
7750 11:07:51.074651 8, 0xFFFF, sum = 0
7751 11:07:51.078021 9, 0xFFFF, sum = 0
7752 11:07:51.078679 10, 0xFFFF, sum = 0
7753 11:07:51.080601 11, 0xFFFF, sum = 0
7754 11:07:51.083733 12, 0xFFFF, sum = 0
7755 11:07:51.084276 13, 0xFFFF, sum = 0
7756 11:07:51.087504 14, 0x0, sum = 1
7757 11:07:51.087958 15, 0x0, sum = 2
7758 11:07:51.090961 16, 0x0, sum = 3
7759 11:07:51.091351 17, 0x0, sum = 4
7760 11:07:51.091658 best_step = 15
7761 11:07:51.091964
7762 11:07:51.094212 ==
7763 11:07:51.097177 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 11:07:51.100571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 11:07:51.100974 ==
7766 11:07:51.101333 RX Vref Scan: 1
7767 11:07:51.101621
7768 11:07:51.104475 Set Vref Range= 24 -> 127
7769 11:07:51.104963
7770 11:07:51.108567 RX Vref 24 -> 127, step: 1
7771 11:07:51.109041
7772 11:07:51.110669 RX Delay 11 -> 252, step: 4
7773 11:07:51.111054
7774 11:07:51.114007 Set Vref, RX VrefLevel [Byte0]: 24
7775 11:07:51.117513 [Byte1]: 24
7776 11:07:51.117983
7777 11:07:51.121076 Set Vref, RX VrefLevel [Byte0]: 25
7778 11:07:51.124048 [Byte1]: 25
7779 11:07:51.124435
7780 11:07:51.127840 Set Vref, RX VrefLevel [Byte0]: 26
7781 11:07:51.131116 [Byte1]: 26
7782 11:07:51.133762
7783 11:07:51.134144 Set Vref, RX VrefLevel [Byte0]: 27
7784 11:07:51.137370 [Byte1]: 27
7785 11:07:51.142179
7786 11:07:51.142638 Set Vref, RX VrefLevel [Byte0]: 28
7787 11:07:51.145240 [Byte1]: 28
7788 11:07:51.149193
7789 11:07:51.149604 Set Vref, RX VrefLevel [Byte0]: 29
7790 11:07:51.153111 [Byte1]: 29
7791 11:07:51.157225
7792 11:07:51.157689 Set Vref, RX VrefLevel [Byte0]: 30
7793 11:07:51.160673 [Byte1]: 30
7794 11:07:51.164420
7795 11:07:51.164800 Set Vref, RX VrefLevel [Byte0]: 31
7796 11:07:51.168270 [Byte1]: 31
7797 11:07:51.172000
7798 11:07:51.172476 Set Vref, RX VrefLevel [Byte0]: 32
7799 11:07:51.175497 [Byte1]: 32
7800 11:07:51.180069
7801 11:07:51.180536 Set Vref, RX VrefLevel [Byte0]: 33
7802 11:07:51.183456 [Byte1]: 33
7803 11:07:51.187175
7804 11:07:51.187647 Set Vref, RX VrefLevel [Byte0]: 34
7805 11:07:51.190466 [Byte1]: 34
7806 11:07:51.194678
7807 11:07:51.195069 Set Vref, RX VrefLevel [Byte0]: 35
7808 11:07:51.198027 [Byte1]: 35
7809 11:07:51.202297
7810 11:07:51.202710 Set Vref, RX VrefLevel [Byte0]: 36
7811 11:07:51.205801 [Byte1]: 36
7812 11:07:51.210420
7813 11:07:51.210908 Set Vref, RX VrefLevel [Byte0]: 37
7814 11:07:51.214030 [Byte1]: 37
7815 11:07:51.217769
7816 11:07:51.218257 Set Vref, RX VrefLevel [Byte0]: 38
7817 11:07:51.221550 [Byte1]: 38
7818 11:07:51.225102
7819 11:07:51.225546 Set Vref, RX VrefLevel [Byte0]: 39
7820 11:07:51.228708 [Byte1]: 39
7821 11:07:51.232836
7822 11:07:51.233271 Set Vref, RX VrefLevel [Byte0]: 40
7823 11:07:51.236943 [Byte1]: 40
7824 11:07:51.240333
7825 11:07:51.240770 Set Vref, RX VrefLevel [Byte0]: 41
7826 11:07:51.243519 [Byte1]: 41
7827 11:07:51.247914
7828 11:07:51.248323 Set Vref, RX VrefLevel [Byte0]: 42
7829 11:07:51.251290 [Byte1]: 42
7830 11:07:51.255693
7831 11:07:51.256136 Set Vref, RX VrefLevel [Byte0]: 43
7832 11:07:51.259497 [Byte1]: 43
7833 11:07:51.264248
7834 11:07:51.264788 Set Vref, RX VrefLevel [Byte0]: 44
7835 11:07:51.267009 [Byte1]: 44
7836 11:07:51.270588
7837 11:07:51.270998 Set Vref, RX VrefLevel [Byte0]: 45
7838 11:07:51.274199 [Byte1]: 45
7839 11:07:51.278633
7840 11:07:51.279045 Set Vref, RX VrefLevel [Byte0]: 46
7841 11:07:51.281891 [Byte1]: 46
7842 11:07:51.285935
7843 11:07:51.286102 Set Vref, RX VrefLevel [Byte0]: 47
7844 11:07:51.289268 [Byte1]: 47
7845 11:07:51.293662
7846 11:07:51.294099 Set Vref, RX VrefLevel [Byte0]: 48
7847 11:07:51.297188 [Byte1]: 48
7848 11:07:51.301819
7849 11:07:51.302209 Set Vref, RX VrefLevel [Byte0]: 49
7850 11:07:51.305299 [Byte1]: 49
7851 11:07:51.309147
7852 11:07:51.309539 Set Vref, RX VrefLevel [Byte0]: 50
7853 11:07:51.312203 [Byte1]: 50
7854 11:07:51.317197
7855 11:07:51.317701 Set Vref, RX VrefLevel [Byte0]: 51
7856 11:07:51.320499 [Byte1]: 51
7857 11:07:51.324078
7858 11:07:51.324572 Set Vref, RX VrefLevel [Byte0]: 52
7859 11:07:51.327616 [Byte1]: 52
7860 11:07:51.332027
7861 11:07:51.332459 Set Vref, RX VrefLevel [Byte0]: 53
7862 11:07:51.334908 [Byte1]: 53
7863 11:07:51.339990
7864 11:07:51.340473 Set Vref, RX VrefLevel [Byte0]: 54
7865 11:07:51.343031 [Byte1]: 54
7866 11:07:51.347695
7867 11:07:51.348103 Set Vref, RX VrefLevel [Byte0]: 55
7868 11:07:51.350341 [Byte1]: 55
7869 11:07:51.354815
7870 11:07:51.355287 Set Vref, RX VrefLevel [Byte0]: 56
7871 11:07:51.357859 [Byte1]: 56
7872 11:07:51.362085
7873 11:07:51.365453 Set Vref, RX VrefLevel [Byte0]: 57
7874 11:07:51.369166 [Byte1]: 57
7875 11:07:51.369567
7876 11:07:51.372287 Set Vref, RX VrefLevel [Byte0]: 58
7877 11:07:51.375461 [Byte1]: 58
7878 11:07:51.375877
7879 11:07:51.378537 Set Vref, RX VrefLevel [Byte0]: 59
7880 11:07:51.382331 [Byte1]: 59
7881 11:07:51.382831
7882 11:07:51.385666 Set Vref, RX VrefLevel [Byte0]: 60
7883 11:07:51.389339 [Byte1]: 60
7884 11:07:51.393348
7885 11:07:51.393811 Set Vref, RX VrefLevel [Byte0]: 61
7886 11:07:51.396063 [Byte1]: 61
7887 11:07:51.400476
7888 11:07:51.400862 Set Vref, RX VrefLevel [Byte0]: 62
7889 11:07:51.404020 [Byte1]: 62
7890 11:07:51.408175
7891 11:07:51.408615 Set Vref, RX VrefLevel [Byte0]: 63
7892 11:07:51.411508 [Byte1]: 63
7893 11:07:51.415540
7894 11:07:51.415962 Set Vref, RX VrefLevel [Byte0]: 64
7895 11:07:51.419361 [Byte1]: 64
7896 11:07:51.423578
7897 11:07:51.424105 Set Vref, RX VrefLevel [Byte0]: 65
7898 11:07:51.426902 [Byte1]: 65
7899 11:07:51.431190
7900 11:07:51.431667 Set Vref, RX VrefLevel [Byte0]: 66
7901 11:07:51.434398 [Byte1]: 66
7902 11:07:51.438421
7903 11:07:51.438893 Set Vref, RX VrefLevel [Byte0]: 67
7904 11:07:51.442070 [Byte1]: 67
7905 11:07:51.446422
7906 11:07:51.446897 Set Vref, RX VrefLevel [Byte0]: 68
7907 11:07:51.449210 [Byte1]: 68
7908 11:07:51.453720
7909 11:07:51.454114 Set Vref, RX VrefLevel [Byte0]: 69
7910 11:07:51.456686 [Byte1]: 69
7911 11:07:51.461397
7912 11:07:51.461808 Set Vref, RX VrefLevel [Byte0]: 70
7913 11:07:51.464951 [Byte1]: 70
7914 11:07:51.469198
7915 11:07:51.469674 Set Vref, RX VrefLevel [Byte0]: 71
7916 11:07:51.472106 [Byte1]: 71
7917 11:07:51.476347
7918 11:07:51.476735 Set Vref, RX VrefLevel [Byte0]: 72
7919 11:07:51.479933 [Byte1]: 72
7920 11:07:51.484567
7921 11:07:51.484957 Set Vref, RX VrefLevel [Byte0]: 73
7922 11:07:51.487694 [Byte1]: 73
7923 11:07:51.492122
7924 11:07:51.492511 Set Vref, RX VrefLevel [Byte0]: 74
7925 11:07:51.494694 [Byte1]: 74
7926 11:07:51.499396
7927 11:07:51.499783 Set Vref, RX VrefLevel [Byte0]: 75
7928 11:07:51.502598 [Byte1]: 75
7929 11:07:51.506935
7930 11:07:51.507373 Set Vref, RX VrefLevel [Byte0]: 76
7931 11:07:51.510023 [Byte1]: 76
7932 11:07:51.514257
7933 11:07:51.514659 Final RX Vref Byte 0 = 57 to rank0
7934 11:07:51.517995 Final RX Vref Byte 1 = 62 to rank0
7935 11:07:51.521829 Final RX Vref Byte 0 = 57 to rank1
7936 11:07:51.524471 Final RX Vref Byte 1 = 62 to rank1==
7937 11:07:51.527931 Dram Type= 6, Freq= 0, CH_0, rank 0
7938 11:07:51.534418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 11:07:51.534816 ==
7940 11:07:51.535120 DQS Delay:
7941 11:07:51.535398 DQS0 = 0, DQS1 = 0
7942 11:07:51.537596 DQM Delay:
7943 11:07:51.537982 DQM0 = 128, DQM1 = 122
7944 11:07:51.541215 DQ Delay:
7945 11:07:51.545043 DQ0 =128, DQ1 =132, DQ2 =122, DQ3 =126
7946 11:07:51.547911 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =136
7947 11:07:51.551603 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7948 11:07:51.554557 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7949 11:07:51.554944
7950 11:07:51.555244
7951 11:07:51.555523
7952 11:07:51.557486 [DramC_TX_OE_Calibration] TA2
7953 11:07:51.561065 Original DQ_B0 (3 6) =30, OEN = 27
7954 11:07:51.564450 Original DQ_B1 (3 6) =30, OEN = 27
7955 11:07:51.567666 24, 0x0, End_B0=24 End_B1=24
7956 11:07:51.568076 25, 0x0, End_B0=25 End_B1=25
7957 11:07:51.570964 26, 0x0, End_B0=26 End_B1=26
7958 11:07:51.574531 27, 0x0, End_B0=27 End_B1=27
7959 11:07:51.577824 28, 0x0, End_B0=28 End_B1=28
7960 11:07:51.581264 29, 0x0, End_B0=29 End_B1=29
7961 11:07:51.581679 30, 0x0, End_B0=30 End_B1=30
7962 11:07:51.585021 31, 0x5151, End_B0=30 End_B1=30
7963 11:07:51.587749 Byte0 end_step=30 best_step=27
7964 11:07:51.590671 Byte1 end_step=30 best_step=27
7965 11:07:51.594026 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 11:07:51.597631 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 11:07:51.598021
7968 11:07:51.598319
7969 11:07:51.603966 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7970 11:07:51.607676 CH0 RK0: MR19=303, MR18=1408
7971 11:07:51.614322 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
7972 11:07:51.614746
7973 11:07:51.617561 ----->DramcWriteLeveling(PI) begin...
7974 11:07:51.617955 ==
7975 11:07:51.620923 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 11:07:51.624300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 11:07:51.624744 ==
7978 11:07:51.627422 Write leveling (Byte 0): 33 => 33
7979 11:07:51.630646 Write leveling (Byte 1): 27 => 27
7980 11:07:51.633773 DramcWriteLeveling(PI) end<-----
7981 11:07:51.634166
7982 11:07:51.634513 ==
7983 11:07:51.637725 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 11:07:51.640559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 11:07:51.640974 ==
7986 11:07:51.644258 [Gating] SW mode calibration
7987 11:07:51.650760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7988 11:07:51.657382 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7989 11:07:51.660853 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 11:07:51.664568 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 11:07:51.670992 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 11:07:51.673938 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7993 11:07:51.677502 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7994 11:07:51.684197 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7995 11:07:51.687773 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 11:07:51.690817 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 11:07:51.697095 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 11:07:51.700470 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 11:07:51.704538 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
8000 11:07:51.710699 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8001 11:07:51.714265 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8002 11:07:51.717319 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8003 11:07:51.723531 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 11:07:51.727248 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 11:07:51.730668 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 11:07:51.737006 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 11:07:51.740441 1 6 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8008 11:07:51.743746 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8009 11:07:51.746982 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8010 11:07:51.753777 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8011 11:07:51.756795 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 11:07:51.760018 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 11:07:51.767120 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 11:07:51.770104 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 11:07:51.773663 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8016 11:07:51.780220 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 11:07:51.783806 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8018 11:07:51.787142 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 11:07:51.794071 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8020 11:07:51.796740 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 11:07:51.800534 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 11:07:51.807338 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 11:07:51.810022 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 11:07:51.813797 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 11:07:51.820214 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 11:07:51.823453 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 11:07:51.826936 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 11:07:51.833485 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 11:07:51.837496 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 11:07:51.840560 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 11:07:51.843670 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8032 11:07:51.850816 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8033 11:07:51.854152 Total UI for P1: 0, mck2ui 16
8034 11:07:51.856828 best dqsien dly found for B0: ( 1, 9, 8)
8035 11:07:51.861009 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8036 11:07:51.864003 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8037 11:07:51.870749 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 11:07:51.870900 Total UI for P1: 0, mck2ui 16
8039 11:07:51.877154 best dqsien dly found for B1: ( 1, 9, 20)
8040 11:07:51.880376 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8041 11:07:51.884045 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8042 11:07:51.884257
8043 11:07:51.887252 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8044 11:07:51.890901 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8045 11:07:51.894453 [Gating] SW calibration Done
8046 11:07:51.894766 ==
8047 11:07:51.897569 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 11:07:51.900815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 11:07:51.901090 ==
8050 11:07:51.903948 RX Vref Scan: 0
8051 11:07:51.904244
8052 11:07:51.904543 RX Vref 0 -> 0, step: 1
8053 11:07:51.904809
8054 11:07:51.908207 RX Delay 0 -> 252, step: 8
8055 11:07:51.910665 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8056 11:07:51.917500 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8057 11:07:51.921171 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8058 11:07:51.924747 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8059 11:07:51.927823 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8060 11:07:51.931925 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8061 11:07:51.933982 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8062 11:07:51.941220 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8063 11:07:51.944582 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8064 11:07:51.947965 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8065 11:07:51.951053 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8066 11:07:51.954207 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8067 11:07:51.960913 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8068 11:07:51.964712 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8069 11:07:51.967830 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8070 11:07:51.970984 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8071 11:07:51.971373 ==
8072 11:07:51.974147 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 11:07:51.980617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 11:07:51.981009 ==
8075 11:07:51.981367 DQS Delay:
8076 11:07:51.984269 DQS0 = 0, DQS1 = 0
8077 11:07:51.984761 DQM Delay:
8078 11:07:51.985205 DQM0 = 131, DQM1 = 124
8079 11:07:51.987588 DQ Delay:
8080 11:07:51.991201 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8081 11:07:51.994264 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8082 11:07:51.997439 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8083 11:07:52.001671 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8084 11:07:52.002143
8085 11:07:52.002442
8086 11:07:52.002713 ==
8087 11:07:52.004541 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 11:07:52.007608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 11:07:52.011273 ==
8090 11:07:52.011678
8091 11:07:52.011974
8092 11:07:52.012247 TX Vref Scan disable
8093 11:07:52.014355 == TX Byte 0 ==
8094 11:07:52.017671 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8095 11:07:52.020974 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8096 11:07:52.024593 == TX Byte 1 ==
8097 11:07:52.028282 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8098 11:07:52.031004 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8099 11:07:52.031418 ==
8100 11:07:52.034156 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 11:07:52.041267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 11:07:52.041759 ==
8103 11:07:52.055265
8104 11:07:52.057788 TX Vref early break, caculate TX vref
8105 11:07:52.061375 TX Vref=16, minBit 9, minWin=22, winSum=373
8106 11:07:52.064723 TX Vref=18, minBit 0, minWin=23, winSum=381
8107 11:07:52.068274 TX Vref=20, minBit 1, minWin=23, winSum=389
8108 11:07:52.071270 TX Vref=22, minBit 4, minWin=24, winSum=400
8109 11:07:52.074535 TX Vref=24, minBit 1, minWin=24, winSum=405
8110 11:07:52.081304 TX Vref=26, minBit 1, minWin=25, winSum=412
8111 11:07:52.084446 TX Vref=28, minBit 0, minWin=25, winSum=417
8112 11:07:52.087786 TX Vref=30, minBit 0, minWin=25, winSum=416
8113 11:07:52.091686 TX Vref=32, minBit 0, minWin=24, winSum=404
8114 11:07:52.094495 TX Vref=34, minBit 4, minWin=23, winSum=397
8115 11:07:52.097866 TX Vref=36, minBit 4, minWin=23, winSum=391
8116 11:07:52.105055 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8117 11:07:52.105512
8118 11:07:52.108328 Final TX Range 0 Vref 28
8119 11:07:52.108783
8120 11:07:52.109262 ==
8121 11:07:52.111000 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 11:07:52.114672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 11:07:52.115061 ==
8124 11:07:52.115469
8125 11:07:52.115778
8126 11:07:52.118480 TX Vref Scan disable
8127 11:07:52.124613 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8128 11:07:52.125044 == TX Byte 0 ==
8129 11:07:52.127916 u2DelayCellOfst[0]=14 cells (4 PI)
8130 11:07:52.131110 u2DelayCellOfst[1]=17 cells (5 PI)
8131 11:07:52.134917 u2DelayCellOfst[2]=10 cells (3 PI)
8132 11:07:52.138132 u2DelayCellOfst[3]=10 cells (3 PI)
8133 11:07:52.141783 u2DelayCellOfst[4]=10 cells (3 PI)
8134 11:07:52.144743 u2DelayCellOfst[5]=0 cells (0 PI)
8135 11:07:52.148448 u2DelayCellOfst[6]=17 cells (5 PI)
8136 11:07:52.151527 u2DelayCellOfst[7]=17 cells (5 PI)
8137 11:07:52.155189 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8138 11:07:52.158167 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8139 11:07:52.161517 == TX Byte 1 ==
8140 11:07:52.161901 u2DelayCellOfst[8]=0 cells (0 PI)
8141 11:07:52.164568 u2DelayCellOfst[9]=0 cells (0 PI)
8142 11:07:52.168075 u2DelayCellOfst[10]=7 cells (2 PI)
8143 11:07:52.171448 u2DelayCellOfst[11]=0 cells (0 PI)
8144 11:07:52.175502 u2DelayCellOfst[12]=14 cells (4 PI)
8145 11:07:52.177893 u2DelayCellOfst[13]=10 cells (3 PI)
8146 11:07:52.181398 u2DelayCellOfst[14]=14 cells (4 PI)
8147 11:07:52.185132 u2DelayCellOfst[15]=10 cells (3 PI)
8148 11:07:52.187802 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8149 11:07:52.195055 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8150 11:07:52.195475 DramC Write-DBI on
8151 11:07:52.195811 ==
8152 11:07:52.198343 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 11:07:52.201476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 11:07:52.204649 ==
8155 11:07:52.205111
8156 11:07:52.205577
8157 11:07:52.205985 TX Vref Scan disable
8158 11:07:52.208190 == TX Byte 0 ==
8159 11:07:52.212084 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8160 11:07:52.215224 == TX Byte 1 ==
8161 11:07:52.218389 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8162 11:07:52.218862 DramC Write-DBI off
8163 11:07:52.221532
8164 11:07:52.221996 [DATLAT]
8165 11:07:52.222304 Freq=1600, CH0 RK1
8166 11:07:52.222587
8167 11:07:52.225180 DATLAT Default: 0xf
8168 11:07:52.225653 0, 0xFFFF, sum = 0
8169 11:07:52.228475 1, 0xFFFF, sum = 0
8170 11:07:52.228948 2, 0xFFFF, sum = 0
8171 11:07:52.231347 3, 0xFFFF, sum = 0
8172 11:07:52.234894 4, 0xFFFF, sum = 0
8173 11:07:52.235290 5, 0xFFFF, sum = 0
8174 11:07:52.238065 6, 0xFFFF, sum = 0
8175 11:07:52.238466 7, 0xFFFF, sum = 0
8176 11:07:52.241528 8, 0xFFFF, sum = 0
8177 11:07:52.241938 9, 0xFFFF, sum = 0
8178 11:07:52.244938 10, 0xFFFF, sum = 0
8179 11:07:52.245372 11, 0xFFFF, sum = 0
8180 11:07:52.248548 12, 0xFFFF, sum = 0
8181 11:07:52.249024 13, 0xFFFF, sum = 0
8182 11:07:52.251810 14, 0x0, sum = 1
8183 11:07:52.252224 15, 0x0, sum = 2
8184 11:07:52.255146 16, 0x0, sum = 3
8185 11:07:52.255630 17, 0x0, sum = 4
8186 11:07:52.258091 best_step = 15
8187 11:07:52.258556
8188 11:07:52.258861 ==
8189 11:07:52.261468 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 11:07:52.264755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 11:07:52.265182 ==
8192 11:07:52.265528 RX Vref Scan: 0
8193 11:07:52.265817
8194 11:07:52.268358 RX Vref 0 -> 0, step: 1
8195 11:07:52.268743
8196 11:07:52.271641 RX Delay 11 -> 252, step: 4
8197 11:07:52.274804 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8198 11:07:52.281688 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8199 11:07:52.285356 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8200 11:07:52.287978 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8201 11:07:52.291916 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8202 11:07:52.295056 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8203 11:07:52.298097 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8204 11:07:52.305208 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8205 11:07:52.307958 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8206 11:07:52.311436 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8207 11:07:52.314743 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8208 11:07:52.318018 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8209 11:07:52.325225 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8210 11:07:52.328340 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8211 11:07:52.331298 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8212 11:07:52.334801 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8213 11:07:52.335198 ==
8214 11:07:52.338618 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 11:07:52.344738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 11:07:52.345224 ==
8217 11:07:52.345556 DQS Delay:
8218 11:07:52.348247 DQS0 = 0, DQS1 = 0
8219 11:07:52.348709 DQM Delay:
8220 11:07:52.349012 DQM0 = 126, DQM1 = 122
8221 11:07:52.352045 DQ Delay:
8222 11:07:52.355384 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8223 11:07:52.358617 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =136
8224 11:07:52.361327 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8225 11:07:52.364929 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8226 11:07:52.365445
8227 11:07:52.365784
8228 11:07:52.366106
8229 11:07:52.368437 [DramC_TX_OE_Calibration] TA2
8230 11:07:52.372169 Original DQ_B0 (3 6) =30, OEN = 27
8231 11:07:52.375161 Original DQ_B1 (3 6) =30, OEN = 27
8232 11:07:52.378223 24, 0x0, End_B0=24 End_B1=24
8233 11:07:52.378669 25, 0x0, End_B0=25 End_B1=25
8234 11:07:52.381633 26, 0x0, End_B0=26 End_B1=26
8235 11:07:52.385274 27, 0x0, End_B0=27 End_B1=27
8236 11:07:52.388606 28, 0x0, End_B0=28 End_B1=28
8237 11:07:52.391591 29, 0x0, End_B0=29 End_B1=29
8238 11:07:52.391989 30, 0x0, End_B0=30 End_B1=30
8239 11:07:52.394939 31, 0x4141, End_B0=30 End_B1=30
8240 11:07:52.398284 Byte0 end_step=30 best_step=27
8241 11:07:52.401629 Byte1 end_step=30 best_step=27
8242 11:07:52.404886 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 11:07:52.408060 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 11:07:52.408499
8245 11:07:52.408802
8246 11:07:52.415042 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8247 11:07:52.418580 CH0 RK1: MR19=303, MR18=1B10
8248 11:07:52.425062 CH0_RK1: MR19=0x303, MR18=0x1B10, DQSOSC=396, MR23=63, INC=23, DEC=15
8249 11:07:52.428558 [RxdqsGatingPostProcess] freq 1600
8250 11:07:52.431448 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 11:07:52.434963 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 11:07:52.438595 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 11:07:52.441427 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 11:07:52.445014 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 11:07:52.448424 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 11:07:52.451937 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 11:07:52.455872 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 11:07:52.456346 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 11:07:52.458941 Pre-setting of DQS Precalculation
8260 11:07:52.465186 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 11:07:52.465634 ==
8262 11:07:52.468524 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 11:07:52.472363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 11:07:52.472870 ==
8265 11:07:52.478995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 11:07:52.481862 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 11:07:52.485047 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 11:07:52.491744 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 11:07:52.500958 [CA 0] Center 43 (14~72) winsize 59
8270 11:07:52.504419 [CA 1] Center 43 (15~72) winsize 58
8271 11:07:52.507705 [CA 2] Center 39 (11~67) winsize 57
8272 11:07:52.511117 [CA 3] Center 37 (8~66) winsize 59
8273 11:07:52.514595 [CA 4] Center 38 (9~67) winsize 59
8274 11:07:52.517710 [CA 5] Center 37 (9~66) winsize 58
8275 11:07:52.518128
8276 11:07:52.521399 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 11:07:52.521824
8278 11:07:52.524605 [CATrainingPosCal] consider 1 rank data
8279 11:07:52.527962 u2DelayCellTimex100 = 275/100 ps
8280 11:07:52.531315 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8281 11:07:52.537867 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8282 11:07:52.541425 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8283 11:07:52.544749 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8284 11:07:52.548138 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8285 11:07:52.551267 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8286 11:07:52.551665
8287 11:07:52.555161 CA PerBit enable=1, Macro0, CA PI delay=37
8288 11:07:52.555555
8289 11:07:52.558736 [CBTSetCACLKResult] CA Dly = 37
8290 11:07:52.559208 CS Dly: 9 (0~40)
8291 11:07:52.564268 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 11:07:52.568379 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 11:07:52.568828 ==
8294 11:07:52.571124 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 11:07:52.574458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 11:07:52.575012 ==
8297 11:07:52.581359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 11:07:52.584548 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 11:07:52.587886 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 11:07:52.594414 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 11:07:52.604444 [CA 0] Center 43 (14~73) winsize 60
8302 11:07:52.607726 [CA 1] Center 43 (14~72) winsize 59
8303 11:07:52.611093 [CA 2] Center 38 (9~67) winsize 59
8304 11:07:52.614545 [CA 3] Center 37 (8~66) winsize 59
8305 11:07:52.617621 [CA 4] Center 38 (9~68) winsize 60
8306 11:07:52.621070 [CA 5] Center 37 (8~66) winsize 59
8307 11:07:52.621494
8308 11:07:52.624890 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 11:07:52.625316
8310 11:07:52.627805 [CATrainingPosCal] consider 2 rank data
8311 11:07:52.631175 u2DelayCellTimex100 = 275/100 ps
8312 11:07:52.634445 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8313 11:07:52.641161 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8314 11:07:52.644229 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8315 11:07:52.647759 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8316 11:07:52.651001 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8317 11:07:52.654254 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8318 11:07:52.654686
8319 11:07:52.657491 CA PerBit enable=1, Macro0, CA PI delay=37
8320 11:07:52.658137
8321 11:07:52.660983 [CBTSetCACLKResult] CA Dly = 37
8322 11:07:52.664338 CS Dly: 11 (0~45)
8323 11:07:52.667764 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 11:07:52.670986 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 11:07:52.671467
8326 11:07:52.674675 ----->DramcWriteLeveling(PI) begin...
8327 11:07:52.675062 ==
8328 11:07:52.677805 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 11:07:52.680801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 11:07:52.684439 ==
8331 11:07:52.684874 Write leveling (Byte 0): 27 => 27
8332 11:07:52.687966 Write leveling (Byte 1): 28 => 28
8333 11:07:52.691289 DramcWriteLeveling(PI) end<-----
8334 11:07:52.691672
8335 11:07:52.691966 ==
8336 11:07:52.694224 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 11:07:52.701215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 11:07:52.701687 ==
8339 11:07:52.701992 [Gating] SW mode calibration
8340 11:07:52.711081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 11:07:52.714607 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 11:07:52.718081 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 11:07:52.724547 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 11:07:52.728211 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 11:07:52.731017 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 11:07:52.737630 1 4 16 | B1->B0 | 2626 2424 | 1 0 | (0 0) (1 1)
8347 11:07:52.741597 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 11:07:52.745204 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 11:07:52.751150 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 11:07:52.755205 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 11:07:52.757852 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 11:07:52.764490 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 11:07:52.767929 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 11:07:52.771026 1 5 16 | B1->B0 | 2525 2e2e | 0 0 | (1 0) (0 1)
8355 11:07:52.777796 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8356 11:07:52.781109 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:07:52.785312 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:07:52.787710 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 11:07:52.794519 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:07:52.798412 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 11:07:52.801590 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8362 11:07:52.808278 1 6 16 | B1->B0 | 4444 3636 | 0 0 | (0 0) (0 0)
8363 11:07:52.811473 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 11:07:52.814527 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 11:07:52.821437 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 11:07:52.825029 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 11:07:52.828044 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 11:07:52.834805 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 11:07:52.838433 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 11:07:52.841235 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 11:07:52.847725 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8372 11:07:52.852269 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:07:52.854403 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:07:52.861534 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 11:07:52.864604 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 11:07:52.868292 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 11:07:52.874572 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 11:07:52.877975 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 11:07:52.881398 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 11:07:52.884766 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 11:07:52.891040 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 11:07:52.894744 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 11:07:52.898092 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 11:07:52.904969 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 11:07:52.907976 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8386 11:07:52.911141 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 11:07:52.918122 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 11:07:52.918547 Total UI for P1: 0, mck2ui 16
8389 11:07:52.925153 best dqsien dly found for B0: ( 1, 9, 14)
8390 11:07:52.925553 Total UI for P1: 0, mck2ui 16
8391 11:07:52.931548 best dqsien dly found for B1: ( 1, 9, 16)
8392 11:07:52.934744 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8393 11:07:52.938088 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8394 11:07:52.938685
8395 11:07:52.941783 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8396 11:07:52.944855 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8397 11:07:52.947892 [Gating] SW calibration Done
8398 11:07:52.948423 ==
8399 11:07:52.951773 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 11:07:52.955439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 11:07:52.955837 ==
8402 11:07:52.958191 RX Vref Scan: 0
8403 11:07:52.958579
8404 11:07:52.958883 RX Vref 0 -> 0, step: 1
8405 11:07:52.959166
8406 11:07:52.961158 RX Delay 0 -> 252, step: 8
8407 11:07:52.965259 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8408 11:07:52.971615 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8409 11:07:52.974553 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8410 11:07:52.978074 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8411 11:07:52.982252 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8412 11:07:52.984566 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8413 11:07:52.988766 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8414 11:07:52.994911 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8415 11:07:52.998016 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8416 11:07:53.001229 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8417 11:07:53.004922 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8418 11:07:53.008226 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8419 11:07:53.014643 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8420 11:07:53.018261 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8421 11:07:53.021658 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8422 11:07:53.025065 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8423 11:07:53.025596 ==
8424 11:07:53.028763 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 11:07:53.034993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 11:07:53.035384 ==
8427 11:07:53.035691 DQS Delay:
8428 11:07:53.038223 DQS0 = 0, DQS1 = 0
8429 11:07:53.038614 DQM Delay:
8430 11:07:53.038916 DQM0 = 133, DQM1 = 128
8431 11:07:53.041811 DQ Delay:
8432 11:07:53.045319 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8433 11:07:53.048619 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8434 11:07:53.051533 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8435 11:07:53.055124 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8436 11:07:53.055513
8437 11:07:53.055914
8438 11:07:53.056209 ==
8439 11:07:53.058506 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 11:07:53.061865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 11:07:53.062257 ==
8442 11:07:53.064841
8443 11:07:53.065286
8444 11:07:53.065594 TX Vref Scan disable
8445 11:07:53.068687 == TX Byte 0 ==
8446 11:07:53.071577 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8447 11:07:53.075003 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8448 11:07:53.078299 == TX Byte 1 ==
8449 11:07:53.081545 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8450 11:07:53.085090 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8451 11:07:53.085522 ==
8452 11:07:53.088601 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 11:07:53.095198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 11:07:53.095593 ==
8455 11:07:53.107681
8456 11:07:53.110909 TX Vref early break, caculate TX vref
8457 11:07:53.115164 TX Vref=16, minBit 8, minWin=21, winSum=358
8458 11:07:53.117462 TX Vref=18, minBit 8, minWin=21, winSum=367
8459 11:07:53.120883 TX Vref=20, minBit 5, minWin=22, winSum=379
8460 11:07:53.124236 TX Vref=22, minBit 0, minWin=23, winSum=388
8461 11:07:53.127541 TX Vref=24, minBit 8, minWin=23, winSum=401
8462 11:07:53.134318 TX Vref=26, minBit 5, minWin=24, winSum=409
8463 11:07:53.137398 TX Vref=28, minBit 3, minWin=25, winSum=415
8464 11:07:53.140889 TX Vref=30, minBit 8, minWin=25, winSum=417
8465 11:07:53.144233 TX Vref=32, minBit 9, minWin=24, winSum=410
8466 11:07:53.147636 TX Vref=34, minBit 8, minWin=23, winSum=396
8467 11:07:53.151172 TX Vref=36, minBit 8, minWin=23, winSum=386
8468 11:07:53.158093 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 30
8469 11:07:53.158489
8470 11:07:53.161236 Final TX Range 0 Vref 30
8471 11:07:53.161631
8472 11:07:53.161985 ==
8473 11:07:53.164348 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 11:07:53.167587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 11:07:53.167955 ==
8476 11:07:53.168249
8477 11:07:53.168523
8478 11:07:53.171660 TX Vref Scan disable
8479 11:07:53.178175 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8480 11:07:53.178686 == TX Byte 0 ==
8481 11:07:53.180752 u2DelayCellOfst[0]=17 cells (5 PI)
8482 11:07:53.183943 u2DelayCellOfst[1]=10 cells (3 PI)
8483 11:07:53.187227 u2DelayCellOfst[2]=0 cells (0 PI)
8484 11:07:53.190866 u2DelayCellOfst[3]=7 cells (2 PI)
8485 11:07:53.194240 u2DelayCellOfst[4]=7 cells (2 PI)
8486 11:07:53.197543 u2DelayCellOfst[5]=17 cells (5 PI)
8487 11:07:53.200970 u2DelayCellOfst[6]=17 cells (5 PI)
8488 11:07:53.204235 u2DelayCellOfst[7]=7 cells (2 PI)
8489 11:07:53.207464 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8490 11:07:53.210694 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8491 11:07:53.214479 == TX Byte 1 ==
8492 11:07:53.214876 u2DelayCellOfst[8]=0 cells (0 PI)
8493 11:07:53.217299 u2DelayCellOfst[9]=3 cells (1 PI)
8494 11:07:53.221039 u2DelayCellOfst[10]=10 cells (3 PI)
8495 11:07:53.224184 u2DelayCellOfst[11]=7 cells (2 PI)
8496 11:07:53.227415 u2DelayCellOfst[12]=14 cells (4 PI)
8497 11:07:53.231389 u2DelayCellOfst[13]=17 cells (5 PI)
8498 11:07:53.234735 u2DelayCellOfst[14]=17 cells (5 PI)
8499 11:07:53.237508 u2DelayCellOfst[15]=17 cells (5 PI)
8500 11:07:53.241287 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8501 11:07:53.247259 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8502 11:07:53.247647 DramC Write-DBI on
8503 11:07:53.247949 ==
8504 11:07:53.251195 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 11:07:53.254157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 11:07:53.254548 ==
8507 11:07:53.259049
8508 11:07:53.259547
8509 11:07:53.260021 TX Vref Scan disable
8510 11:07:53.261962 == TX Byte 0 ==
8511 11:07:53.264361 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8512 11:07:53.267438 == TX Byte 1 ==
8513 11:07:53.270773 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8514 11:07:53.271162 DramC Write-DBI off
8515 11:07:53.274258
8516 11:07:53.274647 [DATLAT]
8517 11:07:53.274948 Freq=1600, CH1 RK0
8518 11:07:53.275231
8519 11:07:53.277764 DATLAT Default: 0xf
8520 11:07:53.278160 0, 0xFFFF, sum = 0
8521 11:07:53.281106 1, 0xFFFF, sum = 0
8522 11:07:53.281633 2, 0xFFFF, sum = 0
8523 11:07:53.284911 3, 0xFFFF, sum = 0
8524 11:07:53.285363 4, 0xFFFF, sum = 0
8525 11:07:53.287714 5, 0xFFFF, sum = 0
8526 11:07:53.290606 6, 0xFFFF, sum = 0
8527 11:07:53.290999 7, 0xFFFF, sum = 0
8528 11:07:53.294516 8, 0xFFFF, sum = 0
8529 11:07:53.294917 9, 0xFFFF, sum = 0
8530 11:07:53.297806 10, 0xFFFF, sum = 0
8531 11:07:53.298204 11, 0xFFFF, sum = 0
8532 11:07:53.301181 12, 0xFFFF, sum = 0
8533 11:07:53.301584 13, 0xFFFF, sum = 0
8534 11:07:53.304284 14, 0x0, sum = 1
8535 11:07:53.304680 15, 0x0, sum = 2
8536 11:07:53.307866 16, 0x0, sum = 3
8537 11:07:53.308372 17, 0x0, sum = 4
8538 11:07:53.308691 best_step = 15
8539 11:07:53.311216
8540 11:07:53.311685 ==
8541 11:07:53.314134 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 11:07:53.317475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 11:07:53.317869 ==
8544 11:07:53.318176 RX Vref Scan: 1
8545 11:07:53.318458
8546 11:07:53.321269 Set Vref Range= 24 -> 127
8547 11:07:53.321660
8548 11:07:53.324576 RX Vref 24 -> 127, step: 1
8549 11:07:53.325038
8550 11:07:53.328208 RX Delay 19 -> 252, step: 4
8551 11:07:53.328668
8552 11:07:53.331245 Set Vref, RX VrefLevel [Byte0]: 24
8553 11:07:53.334576 [Byte1]: 24
8554 11:07:53.335071
8555 11:07:53.337511 Set Vref, RX VrefLevel [Byte0]: 25
8556 11:07:53.340792 [Byte1]: 25
8557 11:07:53.341266
8558 11:07:53.344844 Set Vref, RX VrefLevel [Byte0]: 26
8559 11:07:53.348080 [Byte1]: 26
8560 11:07:53.350992
8561 11:07:53.351454 Set Vref, RX VrefLevel [Byte0]: 27
8562 11:07:53.354856 [Byte1]: 27
8563 11:07:53.358629
8564 11:07:53.359122 Set Vref, RX VrefLevel [Byte0]: 28
8565 11:07:53.361847 [Byte1]: 28
8566 11:07:53.366128
8567 11:07:53.366560 Set Vref, RX VrefLevel [Byte0]: 29
8568 11:07:53.371810 [Byte1]: 29
8569 11:07:53.373653
8570 11:07:53.374085 Set Vref, RX VrefLevel [Byte0]: 30
8571 11:07:53.377819 [Byte1]: 30
8572 11:07:53.381674
8573 11:07:53.382188 Set Vref, RX VrefLevel [Byte0]: 31
8574 11:07:53.384427 [Byte1]: 31
8575 11:07:53.389094
8576 11:07:53.389575 Set Vref, RX VrefLevel [Byte0]: 32
8577 11:07:53.392114 [Byte1]: 32
8578 11:07:53.396923
8579 11:07:53.397406 Set Vref, RX VrefLevel [Byte0]: 33
8580 11:07:53.399627 [Byte1]: 33
8581 11:07:53.404113
8582 11:07:53.404564 Set Vref, RX VrefLevel [Byte0]: 34
8583 11:07:53.407145 [Byte1]: 34
8584 11:07:53.411423
8585 11:07:53.411883 Set Vref, RX VrefLevel [Byte0]: 35
8586 11:07:53.415096 [Byte1]: 35
8587 11:07:53.418871
8588 11:07:53.419269 Set Vref, RX VrefLevel [Byte0]: 36
8589 11:07:53.422821 [Byte1]: 36
8590 11:07:53.427033
8591 11:07:53.427516 Set Vref, RX VrefLevel [Byte0]: 37
8592 11:07:53.430325 [Byte1]: 37
8593 11:07:53.434803
8594 11:07:53.435266 Set Vref, RX VrefLevel [Byte0]: 38
8595 11:07:53.438240 [Byte1]: 38
8596 11:07:53.442271
8597 11:07:53.442661 Set Vref, RX VrefLevel [Byte0]: 39
8598 11:07:53.445314 [Byte1]: 39
8599 11:07:53.449531
8600 11:07:53.450006 Set Vref, RX VrefLevel [Byte0]: 40
8601 11:07:53.452800 [Byte1]: 40
8602 11:07:53.457370
8603 11:07:53.457853 Set Vref, RX VrefLevel [Byte0]: 41
8604 11:07:53.460685 [Byte1]: 41
8605 11:07:53.464486
8606 11:07:53.464891 Set Vref, RX VrefLevel [Byte0]: 42
8607 11:07:53.468561 [Byte1]: 42
8608 11:07:53.472214
8609 11:07:53.472676 Set Vref, RX VrefLevel [Byte0]: 43
8610 11:07:53.475823 [Byte1]: 43
8611 11:07:53.479545
8612 11:07:53.479930 Set Vref, RX VrefLevel [Byte0]: 44
8613 11:07:53.483048 [Byte1]: 44
8614 11:07:53.487512
8615 11:07:53.487976 Set Vref, RX VrefLevel [Byte0]: 45
8616 11:07:53.490545 [Byte1]: 45
8617 11:07:53.495442
8618 11:07:53.495833 Set Vref, RX VrefLevel [Byte0]: 46
8619 11:07:53.498518 [Byte1]: 46
8620 11:07:53.502466
8621 11:07:53.502871 Set Vref, RX VrefLevel [Byte0]: 47
8622 11:07:53.505844 [Byte1]: 47
8623 11:07:53.510348
8624 11:07:53.510811 Set Vref, RX VrefLevel [Byte0]: 48
8625 11:07:53.513703 [Byte1]: 48
8626 11:07:53.517695
8627 11:07:53.518223 Set Vref, RX VrefLevel [Byte0]: 49
8628 11:07:53.521611 [Byte1]: 49
8629 11:07:53.524961
8630 11:07:53.525470 Set Vref, RX VrefLevel [Byte0]: 50
8631 11:07:53.528508 [Byte1]: 50
8632 11:07:53.532959
8633 11:07:53.533507 Set Vref, RX VrefLevel [Byte0]: 51
8634 11:07:53.536656 [Byte1]: 51
8635 11:07:53.540508
8636 11:07:53.540933 Set Vref, RX VrefLevel [Byte0]: 52
8637 11:07:53.544155 [Byte1]: 52
8638 11:07:53.548133
8639 11:07:53.548561 Set Vref, RX VrefLevel [Byte0]: 53
8640 11:07:53.551703 [Byte1]: 53
8641 11:07:53.555498
8642 11:07:53.555911 Set Vref, RX VrefLevel [Byte0]: 54
8643 11:07:53.558496 [Byte1]: 54
8644 11:07:53.562940
8645 11:07:53.563410 Set Vref, RX VrefLevel [Byte0]: 55
8646 11:07:53.566295 [Byte1]: 55
8647 11:07:53.570371
8648 11:07:53.570904 Set Vref, RX VrefLevel [Byte0]: 56
8649 11:07:53.574198 [Byte1]: 56
8650 11:07:53.578014
8651 11:07:53.578493 Set Vref, RX VrefLevel [Byte0]: 57
8652 11:07:53.581630 [Byte1]: 57
8653 11:07:53.585682
8654 11:07:53.586167 Set Vref, RX VrefLevel [Byte0]: 58
8655 11:07:53.589372 [Byte1]: 58
8656 11:07:53.593298
8657 11:07:53.593757 Set Vref, RX VrefLevel [Byte0]: 59
8658 11:07:53.597013 [Byte1]: 59
8659 11:07:53.600706
8660 11:07:53.600910 Set Vref, RX VrefLevel [Byte0]: 60
8661 11:07:53.603927 [Byte1]: 60
8662 11:07:53.608696
8663 11:07:53.608974 Set Vref, RX VrefLevel [Byte0]: 61
8664 11:07:53.612003 [Byte1]: 61
8665 11:07:53.615853
8666 11:07:53.616133 Set Vref, RX VrefLevel [Byte0]: 62
8667 11:07:53.618847 [Byte1]: 62
8668 11:07:53.623397
8669 11:07:53.623617 Set Vref, RX VrefLevel [Byte0]: 63
8670 11:07:53.626444 [Byte1]: 63
8671 11:07:53.631213
8672 11:07:53.631533 Set Vref, RX VrefLevel [Byte0]: 64
8673 11:07:53.634619 [Byte1]: 64
8674 11:07:53.638471
8675 11:07:53.638680 Set Vref, RX VrefLevel [Byte0]: 65
8676 11:07:53.641783 [Byte1]: 65
8677 11:07:53.646974
8678 11:07:53.647179 Set Vref, RX VrefLevel [Byte0]: 66
8679 11:07:53.649264 [Byte1]: 66
8680 11:07:53.653861
8681 11:07:53.654066 Set Vref, RX VrefLevel [Byte0]: 67
8682 11:07:53.657599 [Byte1]: 67
8683 11:07:53.662007
8684 11:07:53.662400 Set Vref, RX VrefLevel [Byte0]: 68
8685 11:07:53.664871 [Byte1]: 68
8686 11:07:53.669509
8687 11:07:53.669964 Set Vref, RX VrefLevel [Byte0]: 69
8688 11:07:53.672221 [Byte1]: 69
8689 11:07:53.676500
8690 11:07:53.676882 Set Vref, RX VrefLevel [Byte0]: 70
8691 11:07:53.679736 [Byte1]: 70
8692 11:07:53.684435
8693 11:07:53.684818 Set Vref, RX VrefLevel [Byte0]: 71
8694 11:07:53.687626 [Byte1]: 71
8695 11:07:53.692221
8696 11:07:53.692675 Set Vref, RX VrefLevel [Byte0]: 72
8697 11:07:53.695231 [Byte1]: 72
8698 11:07:53.699268
8699 11:07:53.699652 Set Vref, RX VrefLevel [Byte0]: 73
8700 11:07:53.702568 [Byte1]: 73
8701 11:07:53.707210
8702 11:07:53.707640 Set Vref, RX VrefLevel [Byte0]: 74
8703 11:07:53.711314 [Byte1]: 74
8704 11:07:53.714703
8705 11:07:53.715127 Final RX Vref Byte 0 = 57 to rank0
8706 11:07:53.718249 Final RX Vref Byte 1 = 52 to rank0
8707 11:07:53.721955 Final RX Vref Byte 0 = 57 to rank1
8708 11:07:53.724802 Final RX Vref Byte 1 = 52 to rank1==
8709 11:07:53.728290 Dram Type= 6, Freq= 0, CH_1, rank 0
8710 11:07:53.731549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8711 11:07:53.734557 ==
8712 11:07:53.734981 DQS Delay:
8713 11:07:53.735312 DQS0 = 0, DQS1 = 0
8714 11:07:53.738198 DQM Delay:
8715 11:07:53.738693 DQM0 = 131, DQM1 = 124
8716 11:07:53.741703 DQ Delay:
8717 11:07:53.744792 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8718 11:07:53.748209 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8719 11:07:53.751253 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8720 11:07:53.754589 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8721 11:07:53.755073
8722 11:07:53.755549
8723 11:07:53.756000
8724 11:07:53.758823 [DramC_TX_OE_Calibration] TA2
8725 11:07:53.761967 Original DQ_B0 (3 6) =30, OEN = 27
8726 11:07:53.765374 Original DQ_B1 (3 6) =30, OEN = 27
8727 11:07:53.766021 24, 0x0, End_B0=24 End_B1=24
8728 11:07:53.768241 25, 0x0, End_B0=25 End_B1=25
8729 11:07:53.771641 26, 0x0, End_B0=26 End_B1=26
8730 11:07:53.774936 27, 0x0, End_B0=27 End_B1=27
8731 11:07:53.778496 28, 0x0, End_B0=28 End_B1=28
8732 11:07:53.778893 29, 0x0, End_B0=29 End_B1=29
8733 11:07:53.781324 30, 0x0, End_B0=30 End_B1=30
8734 11:07:53.784947 31, 0x4545, End_B0=30 End_B1=30
8735 11:07:53.788077 Byte0 end_step=30 best_step=27
8736 11:07:53.791282 Byte1 end_step=30 best_step=27
8737 11:07:53.791768 Byte0 TX OE(2T, 0.5T) = (3, 3)
8738 11:07:53.794660 Byte1 TX OE(2T, 0.5T) = (3, 3)
8739 11:07:53.795203
8740 11:07:53.795660
8741 11:07:53.805552 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8742 11:07:53.808232 CH1 RK0: MR19=303, MR18=1701
8743 11:07:53.811993 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8744 11:07:53.812604
8745 11:07:53.815020 ----->DramcWriteLeveling(PI) begin...
8746 11:07:53.818192 ==
8747 11:07:53.821576 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 11:07:53.824889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 11:07:53.825451 ==
8750 11:07:53.828959 Write leveling (Byte 0): 26 => 26
8751 11:07:53.831799 Write leveling (Byte 1): 28 => 28
8752 11:07:53.835112 DramcWriteLeveling(PI) end<-----
8753 11:07:53.835504
8754 11:07:53.835806 ==
8755 11:07:53.838390 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 11:07:53.841484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 11:07:53.841883 ==
8758 11:07:53.844930 [Gating] SW mode calibration
8759 11:07:53.851701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8760 11:07:53.855293 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8761 11:07:53.861832 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 11:07:53.865297 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 11:07:53.868889 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8764 11:07:53.875570 1 4 12 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
8765 11:07:53.878221 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 11:07:53.881752 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 11:07:53.888366 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 11:07:53.891973 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 11:07:53.895145 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 11:07:53.901792 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8771 11:07:53.906133 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 0)
8772 11:07:53.909204 1 5 12 | B1->B0 | 3030 2525 | 0 0 | (1 0) (0 0)
8773 11:07:53.915172 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8774 11:07:53.918500 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 11:07:53.921837 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 11:07:53.929828 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 11:07:53.931787 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 11:07:53.935335 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8779 11:07:53.938519 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8780 11:07:53.945472 1 6 12 | B1->B0 | 3b3b 4545 | 0 1 | (0 0) (0 0)
8781 11:07:53.948809 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 11:07:53.951900 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 11:07:53.958521 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 11:07:53.961737 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 11:07:53.964946 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 11:07:53.972017 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8787 11:07:53.975173 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8788 11:07:53.978731 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8789 11:07:53.985068 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8790 11:07:53.988131 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:07:53.991690 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:07:53.998286 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 11:07:54.001736 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 11:07:54.005174 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 11:07:54.011483 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 11:07:54.014939 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 11:07:54.018142 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 11:07:54.025190 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 11:07:54.028790 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 11:07:54.032184 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 11:07:54.035344 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 11:07:54.041873 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 11:07:54.045113 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8804 11:07:54.048666 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8805 11:07:54.052114 Total UI for P1: 0, mck2ui 16
8806 11:07:54.055273 best dqsien dly found for B0: ( 1, 9, 8)
8807 11:07:54.061919 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 11:07:54.062427 Total UI for P1: 0, mck2ui 16
8809 11:07:54.068989 best dqsien dly found for B1: ( 1, 9, 12)
8810 11:07:54.071687 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8811 11:07:54.075567 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8812 11:07:54.076085
8813 11:07:54.079027 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8814 11:07:54.081656 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8815 11:07:54.085746 [Gating] SW calibration Done
8816 11:07:54.086260 ==
8817 11:07:54.088644 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 11:07:54.092201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 11:07:54.092716 ==
8820 11:07:54.095697 RX Vref Scan: 0
8821 11:07:54.096221
8822 11:07:54.096664 RX Vref 0 -> 0, step: 1
8823 11:07:54.097076
8824 11:07:54.098503 RX Delay 0 -> 252, step: 8
8825 11:07:54.102335 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8826 11:07:54.108818 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8827 11:07:54.112566 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8828 11:07:54.115509 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8829 11:07:54.119092 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8830 11:07:54.122267 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8831 11:07:54.128883 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8832 11:07:54.132021 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8833 11:07:54.135037 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8834 11:07:54.138499 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8835 11:07:54.142038 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8836 11:07:54.145084 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8837 11:07:54.151929 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8838 11:07:54.154957 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8839 11:07:54.158533 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8840 11:07:54.162113 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8841 11:07:54.162681 ==
8842 11:07:54.165435 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 11:07:54.172383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 11:07:54.172859 ==
8845 11:07:54.173209 DQS Delay:
8846 11:07:54.175402 DQS0 = 0, DQS1 = 0
8847 11:07:54.175903 DQM Delay:
8848 11:07:54.176219 DQM0 = 131, DQM1 = 128
8849 11:07:54.178799 DQ Delay:
8850 11:07:54.182013 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8851 11:07:54.185205 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8852 11:07:54.189048 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8853 11:07:54.191997 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8854 11:07:54.192382
8855 11:07:54.192711
8856 11:07:54.193031 ==
8857 11:07:54.195967 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 11:07:54.198698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 11:07:54.201817 ==
8860 11:07:54.202208
8861 11:07:54.202509
8862 11:07:54.202789 TX Vref Scan disable
8863 11:07:54.205449 == TX Byte 0 ==
8864 11:07:54.208895 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8865 11:07:54.211829 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8866 11:07:54.215626 == TX Byte 1 ==
8867 11:07:54.218624 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8868 11:07:54.222047 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8869 11:07:54.222559 ==
8870 11:07:54.225458 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 11:07:54.232397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 11:07:54.232907 ==
8873 11:07:54.244732
8874 11:07:54.247975 TX Vref early break, caculate TX vref
8875 11:07:54.251422 TX Vref=16, minBit 8, minWin=21, winSum=376
8876 11:07:54.254909 TX Vref=18, minBit 6, minWin=23, winSum=384
8877 11:07:54.258018 TX Vref=20, minBit 8, minWin=23, winSum=396
8878 11:07:54.261712 TX Vref=22, minBit 8, minWin=24, winSum=399
8879 11:07:54.264896 TX Vref=24, minBit 11, minWin=24, winSum=409
8880 11:07:54.271446 TX Vref=26, minBit 0, minWin=25, winSum=416
8881 11:07:54.275207 TX Vref=28, minBit 0, minWin=25, winSum=417
8882 11:07:54.278126 TX Vref=30, minBit 13, minWin=25, winSum=421
8883 11:07:54.281615 TX Vref=32, minBit 0, minWin=25, winSum=412
8884 11:07:54.285112 TX Vref=34, minBit 9, minWin=24, winSum=404
8885 11:07:54.288484 TX Vref=36, minBit 9, minWin=23, winSum=394
8886 11:07:54.295387 [TxChooseVref] Worse bit 13, Min win 25, Win sum 421, Final Vref 30
8887 11:07:54.295841
8888 11:07:54.298530 Final TX Range 0 Vref 30
8889 11:07:54.298945
8890 11:07:54.299279 ==
8891 11:07:54.301730 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 11:07:54.305345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 11:07:54.305752 ==
8894 11:07:54.306115
8895 11:07:54.306416
8896 11:07:54.309361 TX Vref Scan disable
8897 11:07:54.315304 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8898 11:07:54.315775 == TX Byte 0 ==
8899 11:07:54.318338 u2DelayCellOfst[0]=17 cells (5 PI)
8900 11:07:54.321787 u2DelayCellOfst[1]=10 cells (3 PI)
8901 11:07:54.325547 u2DelayCellOfst[2]=0 cells (0 PI)
8902 11:07:54.328531 u2DelayCellOfst[3]=7 cells (2 PI)
8903 11:07:54.332093 u2DelayCellOfst[4]=7 cells (2 PI)
8904 11:07:54.335794 u2DelayCellOfst[5]=17 cells (5 PI)
8905 11:07:54.338839 u2DelayCellOfst[6]=17 cells (5 PI)
8906 11:07:54.342097 u2DelayCellOfst[7]=7 cells (2 PI)
8907 11:07:54.345090 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8908 11:07:54.348994 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8909 11:07:54.349485 == TX Byte 1 ==
8910 11:07:54.352257 u2DelayCellOfst[8]=0 cells (0 PI)
8911 11:07:54.355461 u2DelayCellOfst[9]=7 cells (2 PI)
8912 11:07:54.358432 u2DelayCellOfst[10]=10 cells (3 PI)
8913 11:07:54.362388 u2DelayCellOfst[11]=7 cells (2 PI)
8914 11:07:54.365273 u2DelayCellOfst[12]=14 cells (4 PI)
8915 11:07:54.368982 u2DelayCellOfst[13]=17 cells (5 PI)
8916 11:07:54.371718 u2DelayCellOfst[14]=17 cells (5 PI)
8917 11:07:54.375584 u2DelayCellOfst[15]=17 cells (5 PI)
8918 11:07:54.378845 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8919 11:07:54.385084 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8920 11:07:54.385546 DramC Write-DBI on
8921 11:07:54.385851 ==
8922 11:07:54.388698 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 11:07:54.392133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 11:07:54.392519 ==
8925 11:07:54.392817
8926 11:07:54.395254
8927 11:07:54.395636 TX Vref Scan disable
8928 11:07:54.398464 == TX Byte 0 ==
8929 11:07:54.401684 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8930 11:07:54.405394 == TX Byte 1 ==
8931 11:07:54.408792 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8932 11:07:54.409509 DramC Write-DBI off
8933 11:07:54.410045
8934 11:07:54.411943 [DATLAT]
8935 11:07:54.412327 Freq=1600, CH1 RK1
8936 11:07:54.412631
8937 11:07:54.416000 DATLAT Default: 0xf
8938 11:07:54.416392 0, 0xFFFF, sum = 0
8939 11:07:54.418588 1, 0xFFFF, sum = 0
8940 11:07:54.419218 2, 0xFFFF, sum = 0
8941 11:07:54.421938 3, 0xFFFF, sum = 0
8942 11:07:54.422340 4, 0xFFFF, sum = 0
8943 11:07:54.425467 5, 0xFFFF, sum = 0
8944 11:07:54.425862 6, 0xFFFF, sum = 0
8945 11:07:54.428687 7, 0xFFFF, sum = 0
8946 11:07:54.429241 8, 0xFFFF, sum = 0
8947 11:07:54.431859 9, 0xFFFF, sum = 0
8948 11:07:54.435251 10, 0xFFFF, sum = 0
8949 11:07:54.435651 11, 0xFFFF, sum = 0
8950 11:07:54.439280 12, 0xFFFF, sum = 0
8951 11:07:54.439771 13, 0xFFFF, sum = 0
8952 11:07:54.442077 14, 0x0, sum = 1
8953 11:07:54.442469 15, 0x0, sum = 2
8954 11:07:54.445007 16, 0x0, sum = 3
8955 11:07:54.445457 17, 0x0, sum = 4
8956 11:07:54.445771 best_step = 15
8957 11:07:54.448317
8958 11:07:54.448701 ==
8959 11:07:54.452532 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 11:07:54.455214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 11:07:54.455625 ==
8962 11:07:54.455933 RX Vref Scan: 0
8963 11:07:54.456216
8964 11:07:54.458619 RX Vref 0 -> 0, step: 1
8965 11:07:54.459092
8966 11:07:54.461646 RX Delay 11 -> 252, step: 4
8967 11:07:54.465176 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8968 11:07:54.468546 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8969 11:07:54.475238 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8970 11:07:54.478471 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8971 11:07:54.482074 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8972 11:07:54.485156 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8973 11:07:54.488807 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8974 11:07:54.495376 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8975 11:07:54.499002 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8976 11:07:54.501818 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8977 11:07:54.505326 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8978 11:07:54.508329 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8979 11:07:54.514955 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8980 11:07:54.518398 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8981 11:07:54.521825 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8982 11:07:54.524964 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8983 11:07:54.525401 ==
8984 11:07:54.528824 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 11:07:54.534958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 11:07:54.535390 ==
8987 11:07:54.535697 DQS Delay:
8988 11:07:54.538786 DQS0 = 0, DQS1 = 0
8989 11:07:54.539301 DQM Delay:
8990 11:07:54.539615 DQM0 = 129, DQM1 = 126
8991 11:07:54.541803 DQ Delay:
8992 11:07:54.545360 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8993 11:07:54.548972 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
8994 11:07:54.552396 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
8995 11:07:54.555349 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
8996 11:07:54.555789
8997 11:07:54.556097
8998 11:07:54.556377
8999 11:07:54.558525 [DramC_TX_OE_Calibration] TA2
9000 11:07:54.561809 Original DQ_B0 (3 6) =30, OEN = 27
9001 11:07:54.565254 Original DQ_B1 (3 6) =30, OEN = 27
9002 11:07:54.568700 24, 0x0, End_B0=24 End_B1=24
9003 11:07:54.569227 25, 0x0, End_B0=25 End_B1=25
9004 11:07:54.572097 26, 0x0, End_B0=26 End_B1=26
9005 11:07:54.575107 27, 0x0, End_B0=27 End_B1=27
9006 11:07:54.578304 28, 0x0, End_B0=28 End_B1=28
9007 11:07:54.578703 29, 0x0, End_B0=29 End_B1=29
9008 11:07:54.581935 30, 0x0, End_B0=30 End_B1=30
9009 11:07:54.585559 31, 0x4141, End_B0=30 End_B1=30
9010 11:07:54.588492 Byte0 end_step=30 best_step=27
9011 11:07:54.591654 Byte1 end_step=30 best_step=27
9012 11:07:54.595443 Byte0 TX OE(2T, 0.5T) = (3, 3)
9013 11:07:54.595832 Byte1 TX OE(2T, 0.5T) = (3, 3)
9014 11:07:54.599260
9015 11:07:54.599745
9016 11:07:54.605469 [DQSOSCAuto] RK1, (LSB)MR18= 0x1319, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9017 11:07:54.608452 CH1 RK1: MR19=303, MR18=1319
9018 11:07:54.615219 CH1_RK1: MR19=0x303, MR18=0x1319, DQSOSC=397, MR23=63, INC=23, DEC=15
9019 11:07:54.618951 [RxdqsGatingPostProcess] freq 1600
9020 11:07:54.621602 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9021 11:07:54.625610 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 11:07:54.628624 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 11:07:54.632394 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 11:07:54.635273 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 11:07:54.638671 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 11:07:54.642172 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 11:07:54.645043 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 11:07:54.648964 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 11:07:54.649615 Pre-setting of DQS Precalculation
9030 11:07:54.655005 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9031 11:07:54.661876 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9032 11:07:54.668458 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9033 11:07:54.668842
9034 11:07:54.669172
9035 11:07:54.672077 [Calibration Summary] 3200 Mbps
9036 11:07:54.675612 CH 0, Rank 0
9037 11:07:54.676002 SW Impedance : PASS
9038 11:07:54.678620 DUTY Scan : NO K
9039 11:07:54.681793 ZQ Calibration : PASS
9040 11:07:54.682197 Jitter Meter : NO K
9041 11:07:54.685155 CBT Training : PASS
9042 11:07:54.685544 Write leveling : PASS
9043 11:07:54.689219 RX DQS gating : PASS
9044 11:07:54.691983 RX DQ/DQS(RDDQC) : PASS
9045 11:07:54.692368 TX DQ/DQS : PASS
9046 11:07:54.694972 RX DATLAT : PASS
9047 11:07:54.699084 RX DQ/DQS(Engine): PASS
9048 11:07:54.699552 TX OE : PASS
9049 11:07:54.702207 All Pass.
9050 11:07:54.702591
9051 11:07:54.702889 CH 0, Rank 1
9052 11:07:54.705213 SW Impedance : PASS
9053 11:07:54.705703 DUTY Scan : NO K
9054 11:07:54.708819 ZQ Calibration : PASS
9055 11:07:54.712556 Jitter Meter : NO K
9056 11:07:54.713036 CBT Training : PASS
9057 11:07:54.716218 Write leveling : PASS
9058 11:07:54.718909 RX DQS gating : PASS
9059 11:07:54.719374 RX DQ/DQS(RDDQC) : PASS
9060 11:07:54.722237 TX DQ/DQS : PASS
9061 11:07:54.722743 RX DATLAT : PASS
9062 11:07:54.725374 RX DQ/DQS(Engine): PASS
9063 11:07:54.728446 TX OE : PASS
9064 11:07:54.728872 All Pass.
9065 11:07:54.729246
9066 11:07:54.729529 CH 1, Rank 0
9067 11:07:54.731661 SW Impedance : PASS
9068 11:07:54.735857 DUTY Scan : NO K
9069 11:07:54.736322 ZQ Calibration : PASS
9070 11:07:54.738871 Jitter Meter : NO K
9071 11:07:54.742135 CBT Training : PASS
9072 11:07:54.742525 Write leveling : PASS
9073 11:07:54.745629 RX DQS gating : PASS
9074 11:07:54.749207 RX DQ/DQS(RDDQC) : PASS
9075 11:07:54.749671 TX DQ/DQS : PASS
9076 11:07:54.752419 RX DATLAT : PASS
9077 11:07:54.756256 RX DQ/DQS(Engine): PASS
9078 11:07:54.756685 TX OE : PASS
9079 11:07:54.757091 All Pass.
9080 11:07:54.759100
9081 11:07:54.759528 CH 1, Rank 1
9082 11:07:54.762352 SW Impedance : PASS
9083 11:07:54.762820 DUTY Scan : NO K
9084 11:07:54.766020 ZQ Calibration : PASS
9085 11:07:54.766439 Jitter Meter : NO K
9086 11:07:54.768723 CBT Training : PASS
9087 11:07:54.772670 Write leveling : PASS
9088 11:07:54.773176 RX DQS gating : PASS
9089 11:07:54.775441 RX DQ/DQS(RDDQC) : PASS
9090 11:07:54.779148 TX DQ/DQS : PASS
9091 11:07:54.779625 RX DATLAT : PASS
9092 11:07:54.782656 RX DQ/DQS(Engine): PASS
9093 11:07:54.785645 TX OE : PASS
9094 11:07:54.786038 All Pass.
9095 11:07:54.786342
9096 11:07:54.786824 DramC Write-DBI on
9097 11:07:54.788951 PER_BANK_REFRESH: Hybrid Mode
9098 11:07:54.792330 TX_TRACKING: ON
9099 11:07:54.798934 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9100 11:07:54.809453 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9101 11:07:54.815975 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 11:07:54.819051 [FAST_K] Save calibration result to emmc
9103 11:07:54.823155 sync common calibartion params.
9104 11:07:54.823636 sync cbt_mode0:1, 1:1
9105 11:07:54.826499 dram_init: ddr_geometry: 2
9106 11:07:54.829475 dram_init: ddr_geometry: 2
9107 11:07:54.832292 dram_init: ddr_geometry: 2
9108 11:07:54.832675 0:dram_rank_size:100000000
9109 11:07:54.835959 1:dram_rank_size:100000000
9110 11:07:54.842568 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9111 11:07:54.842998 DFS_SHUFFLE_HW_MODE: ON
9112 11:07:54.849353 dramc_set_vcore_voltage set vcore to 725000
9113 11:07:54.849985 Read voltage for 1600, 0
9114 11:07:54.850307 Vio18 = 0
9115 11:07:54.852610 Vcore = 725000
9116 11:07:54.853164 Vdram = 0
9117 11:07:54.853485 Vddq = 0
9118 11:07:54.856524 Vmddr = 0
9119 11:07:54.856929 switch to 3200 Mbps bootup
9120 11:07:54.859445 [DramcRunTimeConfig]
9121 11:07:54.859847 PHYPLL
9122 11:07:54.862210 DPM_CONTROL_AFTERK: ON
9123 11:07:54.862691 PER_BANK_REFRESH: ON
9124 11:07:54.865616 REFRESH_OVERHEAD_REDUCTION: ON
9125 11:07:54.869534 CMD_PICG_NEW_MODE: OFF
9126 11:07:54.870034 XRTWTW_NEW_MODE: ON
9127 11:07:54.872615 XRTRTR_NEW_MODE: ON
9128 11:07:54.873000 TX_TRACKING: ON
9129 11:07:54.875527 RDSEL_TRACKING: OFF
9130 11:07:54.879453 DQS Precalculation for DVFS: ON
9131 11:07:54.879860 RX_TRACKING: OFF
9132 11:07:54.882602 HW_GATING DBG: ON
9133 11:07:54.882989 ZQCS_ENABLE_LP4: ON
9134 11:07:54.886018 RX_PICG_NEW_MODE: ON
9135 11:07:54.886480 TX_PICG_NEW_MODE: ON
9136 11:07:54.889206 ENABLE_RX_DCM_DPHY: ON
9137 11:07:54.892550 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9138 11:07:54.895568 DUMMY_READ_FOR_TRACKING: OFF
9139 11:07:54.895956 !!! SPM_CONTROL_AFTERK: OFF
9140 11:07:54.899191 !!! SPM could not control APHY
9141 11:07:54.902394 IMPEDANCE_TRACKING: ON
9142 11:07:54.902774 TEMP_SENSOR: ON
9143 11:07:54.905774 HW_SAVE_FOR_SR: OFF
9144 11:07:54.908881 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9145 11:07:54.912472 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9146 11:07:54.915994 Read ODT Tracking: ON
9147 11:07:54.916458 Refresh Rate DeBounce: ON
9148 11:07:54.918874 DFS_NO_QUEUE_FLUSH: ON
9149 11:07:54.922947 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9150 11:07:54.925890 ENABLE_DFS_RUNTIME_MRW: OFF
9151 11:07:54.926298 DDR_RESERVE_NEW_MODE: ON
9152 11:07:54.929240 MR_CBT_SWITCH_FREQ: ON
9153 11:07:54.932120 =========================
9154 11:07:54.950056 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9155 11:07:54.953902 dram_init: ddr_geometry: 2
9156 11:07:54.971447 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9157 11:07:54.974874 dram_init: dram init end (result: 0)
9158 11:07:54.981057 DRAM-K: Full calibration passed in 24532 msecs
9159 11:07:54.984689 MRC: failed to locate region type 0.
9160 11:07:54.985204 DRAM rank0 size:0x100000000,
9161 11:07:54.988007 DRAM rank1 size=0x100000000
9162 11:07:54.998073 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9163 11:07:55.004756 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9164 11:07:55.011394 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9165 11:07:55.017884 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9166 11:07:55.021620 DRAM rank0 size:0x100000000,
9167 11:07:55.025020 DRAM rank1 size=0x100000000
9168 11:07:55.025473 CBMEM:
9169 11:07:55.027906 IMD: root @ 0xfffff000 254 entries.
9170 11:07:55.031265 IMD: root @ 0xffffec00 62 entries.
9171 11:07:55.034997 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9172 11:07:55.037406 WARNING: RO_VPD is uninitialized or empty.
9173 11:07:55.044377 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9174 11:07:55.052028 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9175 11:07:55.064413 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9176 11:07:55.076730 BS: romstage times (exec / console): total (unknown) / 24042 ms
9177 11:07:55.077256
9178 11:07:55.077566
9179 11:07:55.085883 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9180 11:07:55.089617 ARM64: Exception handlers installed.
9181 11:07:55.092224 ARM64: Testing exception
9182 11:07:55.092603 ARM64: Done test exception
9183 11:07:55.095682 Enumerating buses...
9184 11:07:55.099456 Show all devs... Before device enumeration.
9185 11:07:55.102678 Root Device: enabled 1
9186 11:07:55.106390 CPU_CLUSTER: 0: enabled 1
9187 11:07:55.106773 CPU: 00: enabled 1
9188 11:07:55.108994 Compare with tree...
9189 11:07:55.109417 Root Device: enabled 1
9190 11:07:55.112352 CPU_CLUSTER: 0: enabled 1
9191 11:07:55.115983 CPU: 00: enabled 1
9192 11:07:55.116446 Root Device scanning...
9193 11:07:55.119253 scan_static_bus for Root Device
9194 11:07:55.122287 CPU_CLUSTER: 0 enabled
9195 11:07:55.125708 scan_static_bus for Root Device done
9196 11:07:55.129485 scan_bus: bus Root Device finished in 8 msecs
9197 11:07:55.129916 done
9198 11:07:55.135766 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9199 11:07:55.140344 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9200 11:07:55.145942 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9201 11:07:55.150036 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9202 11:07:55.152651 Allocating resources...
9203 11:07:55.153037 Reading resources...
9204 11:07:55.155990 Root Device read_resources bus 0 link: 0
9205 11:07:55.159460 DRAM rank0 size:0x100000000,
9206 11:07:55.162380 DRAM rank1 size=0x100000000
9207 11:07:55.165658 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9208 11:07:55.168968 CPU: 00 missing read_resources
9209 11:07:55.172838 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9210 11:07:55.176030 Root Device read_resources bus 0 link: 0 done
9211 11:07:55.179289 Done reading resources.
9212 11:07:55.186015 Show resources in subtree (Root Device)...After reading.
9213 11:07:55.189227 Root Device child on link 0 CPU_CLUSTER: 0
9214 11:07:55.192365 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 11:07:55.202644 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 11:07:55.203074 CPU: 00
9217 11:07:55.205960 Root Device assign_resources, bus 0 link: 0
9218 11:07:55.209452 CPU_CLUSTER: 0 missing set_resources
9219 11:07:55.213190 Root Device assign_resources, bus 0 link: 0 done
9220 11:07:55.216280 Done setting resources.
9221 11:07:55.222386 Show resources in subtree (Root Device)...After assigning values.
9222 11:07:55.225817 Root Device child on link 0 CPU_CLUSTER: 0
9223 11:07:55.229461 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 11:07:55.239208 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 11:07:55.239655 CPU: 00
9226 11:07:55.242548 Done allocating resources.
9227 11:07:55.245847 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9228 11:07:55.249169 Enabling resources...
9229 11:07:55.249614 done.
9230 11:07:55.252872 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9231 11:07:55.256240 Initializing devices...
9232 11:07:55.256628 Root Device init
9233 11:07:55.259281 init hardware done!
9234 11:07:55.262471 0x00000018: ctrlr->caps
9235 11:07:55.262926 52.000 MHz: ctrlr->f_max
9236 11:07:55.266110 0.400 MHz: ctrlr->f_min
9237 11:07:55.269417 0x40ff8080: ctrlr->voltages
9238 11:07:55.269931 sclk: 390625
9239 11:07:55.270272 Bus Width = 1
9240 11:07:55.272820 sclk: 390625
9241 11:07:55.273296 Bus Width = 1
9242 11:07:55.275690 Early init status = 3
9243 11:07:55.278998 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9244 11:07:55.283084 in-header: 03 fc 00 00 01 00 00 00
9245 11:07:55.286435 in-data: 00
9246 11:07:55.289666 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9247 11:07:55.294972 in-header: 03 fd 00 00 00 00 00 00
9248 11:07:55.297866 in-data:
9249 11:07:55.300960 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9250 11:07:55.304452 in-header: 03 fc 00 00 01 00 00 00
9251 11:07:55.307768 in-data: 00
9252 11:07:55.311201 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9253 11:07:55.316249 in-header: 03 fd 00 00 00 00 00 00
9254 11:07:55.318915 in-data:
9255 11:07:55.322385 [SSUSB] Setting up USB HOST controller...
9256 11:07:55.325340 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9257 11:07:55.329008 [SSUSB] phy power-on done.
9258 11:07:55.332205 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9259 11:07:55.338614 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9260 11:07:55.342213 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9261 11:07:55.349349 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9262 11:07:55.356355 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9263 11:07:55.362501 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9264 11:07:55.369450 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9265 11:07:55.376322 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9266 11:07:55.376823 SPM: binary array size = 0x9dc
9267 11:07:55.382781 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9268 11:07:55.388751 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9269 11:07:55.395677 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9270 11:07:55.398689 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9271 11:07:55.402067 configure_display: Starting display init
9272 11:07:55.438579 anx7625_power_on_init: Init interface.
9273 11:07:55.441973 anx7625_disable_pd_protocol: Disabled PD feature.
9274 11:07:55.445585 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9275 11:07:55.473783 anx7625_start_dp_work: Secure OCM version=00
9276 11:07:55.476498 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9277 11:07:55.491295 sp_tx_get_edid_block: EDID Block = 1
9278 11:07:55.594096 Extracted contents:
9279 11:07:55.597222 header: 00 ff ff ff ff ff ff 00
9280 11:07:55.600115 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9281 11:07:55.603396 version: 01 04
9282 11:07:55.607263 basic params: 95 1f 11 78 0a
9283 11:07:55.610373 chroma info: 76 90 94 55 54 90 27 21 50 54
9284 11:07:55.613466 established: 00 00 00
9285 11:07:55.620324 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9286 11:07:55.627023 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9287 11:07:55.630177 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9288 11:07:55.636743 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9289 11:07:55.643478 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9290 11:07:55.647061 extensions: 00
9291 11:07:55.647600 checksum: fb
9292 11:07:55.647950
9293 11:07:55.649862 Manufacturer: IVO Model 57d Serial Number 0
9294 11:07:55.654297 Made week 0 of 2020
9295 11:07:55.654758 EDID version: 1.4
9296 11:07:55.657226 Digital display
9297 11:07:55.660180 6 bits per primary color channel
9298 11:07:55.660618 DisplayPort interface
9299 11:07:55.663682 Maximum image size: 31 cm x 17 cm
9300 11:07:55.666864 Gamma: 220%
9301 11:07:55.667368 Check DPMS levels
9302 11:07:55.670515 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9303 11:07:55.673510 First detailed timing is preferred timing
9304 11:07:55.676574 Established timings supported:
9305 11:07:55.680428 Standard timings supported:
9306 11:07:55.683154 Detailed timings
9307 11:07:55.686763 Hex of detail: 383680a07038204018303c0035ae10000019
9308 11:07:55.689783 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9309 11:07:55.696728 0780 0798 07c8 0820 hborder 0
9310 11:07:55.699798 0438 043b 0447 0458 vborder 0
9311 11:07:55.703632 -hsync -vsync
9312 11:07:55.704016 Did detailed timing
9313 11:07:55.706628 Hex of detail: 000000000000000000000000000000000000
9314 11:07:55.709803 Manufacturer-specified data, tag 0
9315 11:07:55.716931 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9316 11:07:55.717356 ASCII string: InfoVision
9317 11:07:55.723240 Hex of detail: 000000fe00523134304e574635205248200a
9318 11:07:55.726812 ASCII string: R140NWF5 RH
9319 11:07:55.727146 Checksum
9320 11:07:55.727431 Checksum: 0xfb (valid)
9321 11:07:55.733420 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9322 11:07:55.736780 DSI data_rate: 832800000 bps
9323 11:07:55.739716 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9324 11:07:55.746729 anx7625_parse_edid: pixelclock(138800).
9325 11:07:55.750022 hactive(1920), hsync(48), hfp(24), hbp(88)
9326 11:07:55.752936 vactive(1080), vsync(12), vfp(3), vbp(17)
9327 11:07:55.756416 anx7625_dsi_config: config dsi.
9328 11:07:55.763549 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9329 11:07:55.776331 anx7625_dsi_config: success to config DSI
9330 11:07:55.779857 anx7625_dp_start: MIPI phy setup OK.
9331 11:07:55.782787 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9332 11:07:55.786353 mtk_ddp_mode_set invalid vrefresh 60
9333 11:07:55.789218 main_disp_path_setup
9334 11:07:55.789661 ovl_layer_smi_id_en
9335 11:07:55.792970 ovl_layer_smi_id_en
9336 11:07:55.793404 ccorr_config
9337 11:07:55.793707 aal_config
9338 11:07:55.796347 gamma_config
9339 11:07:55.796776 postmask_config
9340 11:07:55.798885 dither_config
9341 11:07:55.803040 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9342 11:07:55.809395 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9343 11:07:55.812696 Root Device init finished in 551 msecs
9344 11:07:55.813170 CPU_CLUSTER: 0 init
9345 11:07:55.822523 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9346 11:07:55.825818 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9347 11:07:55.829692 APU_MBOX 0x190000b0 = 0x10001
9348 11:07:55.832938 APU_MBOX 0x190001b0 = 0x10001
9349 11:07:55.836322 APU_MBOX 0x190005b0 = 0x10001
9350 11:07:55.839642 APU_MBOX 0x190006b0 = 0x10001
9351 11:07:55.842282 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9352 11:07:55.855064 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9353 11:07:55.867693 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9354 11:07:55.874692 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9355 11:07:55.885892 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9356 11:07:55.895022 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9357 11:07:55.898573 CPU_CLUSTER: 0 init finished in 81 msecs
9358 11:07:55.901681 Devices initialized
9359 11:07:55.905162 Show all devs... After init.
9360 11:07:55.905754 Root Device: enabled 1
9361 11:07:55.908801 CPU_CLUSTER: 0: enabled 1
9362 11:07:55.911733 CPU: 00: enabled 1
9363 11:07:55.914823 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9364 11:07:55.917968 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9365 11:07:55.921363 ELOG: NV offset 0x57f000 size 0x1000
9366 11:07:55.928229 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9367 11:07:55.934964 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9368 11:07:55.938451 ELOG: Event(17) added with size 13 at 2024-07-10 11:07:55 UTC
9369 11:07:55.942110 out: cmd=0x121: 03 db 21 01 00 00 00 00
9370 11:07:55.945165 in-header: 03 c7 00 00 2c 00 00 00
9371 11:07:55.958502 in-data: 76 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 11:07:55.965016 ELOG: Event(A1) added with size 10 at 2024-07-10 11:07:55 UTC
9373 11:07:55.971678 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9374 11:07:55.978272 ELOG: Event(A0) added with size 9 at 2024-07-10 11:07:55 UTC
9375 11:07:55.982109 elog_add_boot_reason: Logged dev mode boot
9376 11:07:55.984731 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9377 11:07:55.988612 Finalize devices...
9378 11:07:55.989068 Devices finalized
9379 11:07:55.995057 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9380 11:07:55.998175 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9381 11:07:56.001502 in-header: 03 07 00 00 08 00 00 00
9382 11:07:56.004875 in-data: aa e4 47 04 13 02 00 00
9383 11:07:56.008369 Chrome EC: UHEPI supported
9384 11:07:56.015155 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9385 11:07:56.018594 in-header: 03 a9 00 00 08 00 00 00
9386 11:07:56.021952 in-data: 84 60 60 08 00 00 00 00
9387 11:07:56.028249 ELOG: Event(91) added with size 10 at 2024-07-10 11:07:55 UTC
9388 11:07:56.031997 Chrome EC: clear events_b mask to 0x0000000020004000
9389 11:07:56.038604 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9390 11:07:56.041777 in-header: 03 fd 00 00 00 00 00 00
9391 11:07:56.042170 in-data:
9392 11:07:56.049108 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9393 11:07:56.052170 Writing coreboot table at 0xffe64000
9394 11:07:56.055221 0. 000000000010a000-0000000000113fff: RAMSTAGE
9395 11:07:56.058611 1. 0000000040000000-00000000400fffff: RAM
9396 11:07:56.065824 2. 0000000040100000-000000004032afff: RAMSTAGE
9397 11:07:56.068935 3. 000000004032b000-00000000545fffff: RAM
9398 11:07:56.072003 4. 0000000054600000-000000005465ffff: BL31
9399 11:07:56.075396 5. 0000000054660000-00000000ffe63fff: RAM
9400 11:07:56.082007 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9401 11:07:56.085644 7. 0000000100000000-000000023fffffff: RAM
9402 11:07:56.089690 Passing 5 GPIOs to payload:
9403 11:07:56.091984 NAME | PORT | POLARITY | VALUE
9404 11:07:56.095600 EC in RW | 0x000000aa | low | undefined
9405 11:07:56.102420 EC interrupt | 0x00000005 | low | undefined
9406 11:07:56.105579 TPM interrupt | 0x000000ab | high | undefined
9407 11:07:56.112265 SD card detect | 0x00000011 | high | undefined
9408 11:07:56.115376 speaker enable | 0x00000093 | high | undefined
9409 11:07:56.118687 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9410 11:07:56.122415 in-header: 03 f9 00 00 02 00 00 00
9411 11:07:56.122825 in-data: 02 00
9412 11:07:56.125905 ADC[4]: Raw value=900221 ID=7
9413 11:07:56.129234 ADC[3]: Raw value=213336 ID=1
9414 11:07:56.129521 RAM Code: 0x71
9415 11:07:56.132470 ADC[6]: Raw value=74557 ID=0
9416 11:07:56.135871 ADC[5]: Raw value=212598 ID=1
9417 11:07:56.136091 SKU Code: 0x1
9418 11:07:56.142107 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c866
9419 11:07:56.145160 coreboot table: 964 bytes.
9420 11:07:56.148575 IMD ROOT 0. 0xfffff000 0x00001000
9421 11:07:56.152052 IMD SMALL 1. 0xffffe000 0x00001000
9422 11:07:56.155399 RO MCACHE 2. 0xffffc000 0x00001104
9423 11:07:56.158549 CONSOLE 3. 0xfff7c000 0x00080000
9424 11:07:56.162311 FMAP 4. 0xfff7b000 0x00000452
9425 11:07:56.165331 TIME STAMP 5. 0xfff7a000 0x00000910
9426 11:07:56.169177 VBOOT WORK 6. 0xfff66000 0x00014000
9427 11:07:56.172044 RAMOOPS 7. 0xffe66000 0x00100000
9428 11:07:56.176196 COREBOOT 8. 0xffe64000 0x00002000
9429 11:07:56.176332 IMD small region:
9430 11:07:56.178896 IMD ROOT 0. 0xffffec00 0x00000400
9431 11:07:56.182033 VPD 1. 0xffffeb80 0x0000006c
9432 11:07:56.185812 MMC STATUS 2. 0xffffeb60 0x00000004
9433 11:07:56.192152 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9434 11:07:56.199139 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9435 11:07:56.238383 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9436 11:07:56.242449 Checking segment from ROM address 0x40100000
9437 11:07:56.245174 Checking segment from ROM address 0x4010001c
9438 11:07:56.251783 Loading segment from ROM address 0x40100000
9439 11:07:56.252212 code (compression=0)
9440 11:07:56.261738 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9441 11:07:56.269220 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9442 11:07:56.269700 it's not compressed!
9443 11:07:56.275284 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9444 11:07:56.278414 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9445 11:07:56.299019 Loading segment from ROM address 0x4010001c
9446 11:07:56.299394 Entry Point 0x80000000
9447 11:07:56.302426 Loaded segments
9448 11:07:56.305405 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9449 11:07:56.312632 Jumping to boot code at 0x80000000(0xffe64000)
9450 11:07:56.318815 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9451 11:07:56.325645 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9452 11:07:56.333427 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9453 11:07:56.337220 Checking segment from ROM address 0x40100000
9454 11:07:56.340366 Checking segment from ROM address 0x4010001c
9455 11:07:56.346642 Loading segment from ROM address 0x40100000
9456 11:07:56.347042 code (compression=1)
9457 11:07:56.353184 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9458 11:07:56.363459 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9459 11:07:56.363939 using LZMA
9460 11:07:56.371830 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9461 11:07:56.378589 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9462 11:07:56.381704 Loading segment from ROM address 0x4010001c
9463 11:07:56.382138 Entry Point 0x54601000
9464 11:07:56.384855 Loaded segments
9465 11:07:56.388671 NOTICE: MT8192 bl31_setup
9466 11:07:56.395433 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9467 11:07:56.398611 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9468 11:07:56.402526 WARNING: region 0:
9469 11:07:56.405789 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 11:07:56.406184 WARNING: region 1:
9471 11:07:56.412182 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9472 11:07:56.415253 WARNING: region 2:
9473 11:07:56.418354 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9474 11:07:56.421817 WARNING: region 3:
9475 11:07:56.425005 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9476 11:07:56.428629 WARNING: region 4:
9477 11:07:56.435369 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 11:07:56.435766 WARNING: region 5:
9479 11:07:56.438803 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 11:07:56.442458 WARNING: region 6:
9481 11:07:56.445786 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 11:07:56.446181 WARNING: region 7:
9483 11:07:56.452127 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 11:07:56.458695 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9485 11:07:56.462270 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9486 11:07:56.465429 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9487 11:07:56.472799 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9488 11:07:56.475423 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9489 11:07:56.478682 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9490 11:07:56.485009 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9491 11:07:56.488726 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9492 11:07:56.495172 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9493 11:07:56.498664 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9494 11:07:56.502083 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9495 11:07:56.509159 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9496 11:07:56.511779 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9497 11:07:56.515097 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9498 11:07:56.522468 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9499 11:07:56.525857 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9500 11:07:56.531815 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9501 11:07:56.535000 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9502 11:07:56.538815 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9503 11:07:56.545362 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9504 11:07:56.548616 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9505 11:07:56.551809 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9506 11:07:56.558880 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9507 11:07:56.562119 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9508 11:07:56.568463 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9509 11:07:56.572013 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9510 11:07:56.575316 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9511 11:07:56.581714 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9512 11:07:56.585572 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9513 11:07:56.591701 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9514 11:07:56.595193 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9515 11:07:56.598427 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9516 11:07:56.605409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9517 11:07:56.609069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9518 11:07:56.611688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9519 11:07:56.615359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9520 11:07:56.622216 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9521 11:07:56.625168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9522 11:07:56.628438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9523 11:07:56.632155 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9524 11:07:56.635367 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9525 11:07:56.641821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9526 11:07:56.645224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9527 11:07:56.648642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9528 11:07:56.655316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9529 11:07:56.659072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9530 11:07:56.661742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9531 11:07:56.665380 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9532 11:07:56.672176 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9533 11:07:56.675088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9534 11:07:56.681775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9535 11:07:56.685036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9536 11:07:56.688269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9537 11:07:56.695412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9538 11:07:56.698833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9539 11:07:56.705522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9540 11:07:56.708737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9541 11:07:56.712264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9542 11:07:56.719049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9543 11:07:56.722207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9544 11:07:56.728425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9545 11:07:56.732331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9546 11:07:56.738704 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9547 11:07:56.741892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9548 11:07:56.748303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9549 11:07:56.752258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9550 11:07:56.755020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9551 11:07:56.761642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9552 11:07:56.764835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9553 11:07:56.771677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9554 11:07:56.775086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9555 11:07:56.781432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9556 11:07:56.785197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9557 11:07:56.788143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9558 11:07:56.795236 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9559 11:07:56.798725 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9560 11:07:56.805413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9561 11:07:56.808936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9562 11:07:56.815906 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9563 11:07:56.818897 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9564 11:07:56.825456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9565 11:07:56.828485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9566 11:07:56.831761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9567 11:07:56.838611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9568 11:07:56.841773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9569 11:07:56.848364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9570 11:07:56.851729 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9571 11:07:56.855257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9572 11:07:56.862021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9573 11:07:56.865201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9574 11:07:56.871857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9575 11:07:56.875019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9576 11:07:56.882276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9577 11:07:56.884995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9578 11:07:56.892014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9579 11:07:56.894917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9580 11:07:56.898262 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9581 11:07:56.904592 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9582 11:07:56.907939 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9583 11:07:56.911235 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9584 11:07:56.914663 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9585 11:07:56.922200 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9586 11:07:56.924569 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9587 11:07:56.931684 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9588 11:07:56.935105 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9589 11:07:56.938118 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9590 11:07:56.944591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9591 11:07:56.948798 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9592 11:07:56.955491 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9593 11:07:56.958413 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9594 11:07:56.961636 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9595 11:07:56.968150 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9596 11:07:56.971451 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9597 11:07:56.978418 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9598 11:07:56.981609 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9599 11:07:56.985011 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9600 11:07:56.988125 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9601 11:07:56.995131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9602 11:07:56.998224 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9603 11:07:57.001922 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9604 11:07:57.008189 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9605 11:07:57.011652 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9606 11:07:57.015026 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9607 11:07:57.017764 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9608 11:07:57.024762 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9609 11:07:57.027824 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9610 11:07:57.034789 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9611 11:07:57.037905 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9612 11:07:57.041086 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9613 11:07:57.048322 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9614 11:07:57.051283 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9615 11:07:57.058646 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9616 11:07:57.061163 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9617 11:07:57.064468 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9618 11:07:57.071487 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9619 11:07:57.074917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9620 11:07:57.081463 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9621 11:07:57.085198 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9622 11:07:57.088432 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9623 11:07:57.094692 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9624 11:07:57.098083 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9625 11:07:57.101605 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9626 11:07:57.108002 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9627 11:07:57.111471 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9628 11:07:57.115808 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9629 11:07:57.121667 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9630 11:07:57.125212 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9631 11:07:57.131388 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9632 11:07:57.134657 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9633 11:07:57.138039 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9634 11:07:57.144565 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9635 11:07:57.149042 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9636 11:07:57.154987 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9637 11:07:57.158316 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9638 11:07:57.161725 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9639 11:07:57.168627 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9640 11:07:57.172470 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9641 11:07:57.175521 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9642 11:07:57.182458 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9643 11:07:57.185223 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9644 11:07:57.191588 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9645 11:07:57.194743 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9646 11:07:57.198330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9647 11:07:57.204940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9648 11:07:57.208362 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9649 11:07:57.211562 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9650 11:07:57.218497 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9651 11:07:57.221588 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9652 11:07:57.228137 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9653 11:07:57.231733 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9654 11:07:57.238519 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9655 11:07:57.241392 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9656 11:07:57.244831 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9657 11:07:57.251604 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9658 11:07:57.254689 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9659 11:07:57.261078 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9660 11:07:57.265011 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9661 11:07:57.268388 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9662 11:07:57.274643 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9663 11:07:57.278644 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9664 11:07:57.281422 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9665 11:07:57.288444 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9666 11:07:57.292149 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9667 11:07:57.298232 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9668 11:07:57.301239 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9669 11:07:57.304945 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9670 11:07:57.311469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9671 11:07:57.315441 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9672 11:07:57.317956 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9673 11:07:57.324789 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9674 11:07:57.328921 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9675 11:07:57.334942 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9676 11:07:57.338357 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9677 11:07:57.344836 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9678 11:07:57.348133 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9679 11:07:57.351319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9680 11:07:57.357899 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9681 11:07:57.361077 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9682 11:07:57.367750 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9683 11:07:57.371488 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9684 11:07:57.374820 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9685 11:07:57.381745 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9686 11:07:57.384658 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9687 11:07:57.391199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9688 11:07:57.394738 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9689 11:07:57.401105 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9690 11:07:57.404793 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9691 11:07:57.408132 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9692 11:07:57.415135 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9693 11:07:57.417780 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9694 11:07:57.424963 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9695 11:07:57.428702 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9696 11:07:57.431572 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9697 11:07:57.438183 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9698 11:07:57.441879 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9699 11:07:57.447926 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9700 11:07:57.451301 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9701 11:07:57.454529 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9702 11:07:57.461556 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9703 11:07:57.465040 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9704 11:07:57.471894 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9705 11:07:57.474721 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9706 11:07:57.478076 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9707 11:07:57.484800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9708 11:07:57.487840 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9709 11:07:57.494490 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9710 11:07:57.497852 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9711 11:07:57.504605 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9712 11:07:57.508236 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9713 11:07:57.511361 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9714 11:07:57.515161 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9715 11:07:57.521083 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9716 11:07:57.524854 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9717 11:07:57.528314 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9718 11:07:57.531343 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9719 11:07:57.537827 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9720 11:07:57.541708 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9721 11:07:57.547873 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9722 11:07:57.550969 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9723 11:07:57.554432 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9724 11:07:57.561559 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9725 11:07:57.565199 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9726 11:07:57.568147 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9727 11:07:57.574498 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9728 11:07:57.577969 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9729 11:07:57.581257 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9730 11:07:57.588040 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9731 11:07:57.590894 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9732 11:07:57.594314 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9733 11:07:57.600819 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9734 11:07:57.604299 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9735 11:07:57.611414 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9736 11:07:57.614451 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9737 11:07:57.617904 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9738 11:07:57.624515 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9739 11:07:57.627940 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9740 11:07:57.631602 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9741 11:07:57.637861 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9742 11:07:57.641819 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9743 11:07:57.644474 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9744 11:07:57.650964 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9745 11:07:57.654520 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9746 11:07:57.660837 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9747 11:07:57.664543 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9748 11:07:57.667410 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9749 11:07:57.674153 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9750 11:07:57.677483 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9751 11:07:57.680889 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9752 11:07:57.687595 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9753 11:07:57.690611 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9754 11:07:57.694311 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9755 11:07:57.697176 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9756 11:07:57.704034 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9757 11:07:57.707511 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9758 11:07:57.710811 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9759 11:07:57.714296 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9760 11:07:57.721082 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9761 11:07:57.724397 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9762 11:07:57.727385 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9763 11:07:57.730890 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9764 11:07:57.737591 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9765 11:07:57.740929 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9766 11:07:57.744835 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9767 11:07:57.750787 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9768 11:07:57.754186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9769 11:07:57.760510 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9770 11:07:57.763818 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9771 11:07:57.767874 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9772 11:07:57.774164 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9773 11:07:57.777239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9774 11:07:57.783687 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9775 11:07:57.787472 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9776 11:07:57.790520 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9777 11:07:57.797291 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9778 11:07:57.800642 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9779 11:07:57.807502 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9780 11:07:57.811091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9781 11:07:57.814490 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9782 11:07:57.820933 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9783 11:07:57.824145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9784 11:07:57.831024 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9785 11:07:57.834036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9786 11:07:57.837217 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9787 11:07:57.844585 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9788 11:07:57.847507 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9789 11:07:57.854450 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9790 11:07:57.857383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9791 11:07:57.860631 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9792 11:07:57.867573 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9793 11:07:57.871125 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9794 11:07:57.877381 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9795 11:07:57.880904 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9796 11:07:57.887749 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9797 11:07:57.890959 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9798 11:07:57.893715 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9799 11:07:57.900559 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9800 11:07:57.904051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9801 11:07:57.910656 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9802 11:07:57.913973 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9803 11:07:57.917617 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9804 11:07:57.924128 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9805 11:07:57.927188 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9806 11:07:57.931443 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9807 11:07:57.937402 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9808 11:07:57.941166 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9809 11:07:57.947181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9810 11:07:57.950850 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9811 11:07:57.957389 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9812 11:07:57.961208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9813 11:07:57.964123 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9814 11:07:57.971159 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9815 11:07:57.974714 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9816 11:07:57.980781 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9817 11:07:57.984333 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9818 11:07:57.988613 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9819 11:07:57.994185 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9820 11:07:57.997401 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9821 11:07:58.000560 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9822 11:07:58.007582 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9823 11:07:58.010978 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9824 11:07:58.017726 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9825 11:07:58.020457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9826 11:07:58.027268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9827 11:07:58.030432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9828 11:07:58.034279 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9829 11:07:58.040735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9830 11:07:58.044153 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9831 11:07:58.050775 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9832 11:07:58.054106 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9833 11:07:58.057855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9834 11:07:58.064306 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9835 11:07:58.067122 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9836 11:07:58.073834 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9837 11:07:58.077538 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9838 11:07:58.080684 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9839 11:07:58.087451 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9840 11:07:58.090499 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9841 11:07:58.097110 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9842 11:07:58.100664 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9843 11:07:58.107734 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9844 11:07:58.110478 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9845 11:07:58.115036 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9846 11:07:58.120776 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9847 11:07:58.124456 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9848 11:07:58.130574 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9849 11:07:58.134071 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9850 11:07:58.140724 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9851 11:07:58.144143 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9852 11:07:58.147678 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9853 11:07:58.154232 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9854 11:07:58.157368 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9855 11:07:58.164214 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9856 11:07:58.167668 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9857 11:07:58.174390 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9858 11:07:58.177286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9859 11:07:58.181399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9860 11:07:58.187512 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9861 11:07:58.190618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9862 11:07:58.197308 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9863 11:07:58.200553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9864 11:07:58.207216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9865 11:07:58.210851 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9866 11:07:58.213946 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9867 11:07:58.221480 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9868 11:07:58.224375 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9869 11:07:58.231088 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9870 11:07:58.233747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9871 11:07:58.237365 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9872 11:07:58.244231 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9873 11:07:58.247256 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9874 11:07:58.253892 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9875 11:07:58.257603 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9876 11:07:58.263936 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9877 11:07:58.267857 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9878 11:07:58.270639 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9879 11:07:58.277429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9880 11:07:58.281364 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9881 11:07:58.287822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9882 11:07:58.290731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9883 11:07:58.297632 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9884 11:07:58.301227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9885 11:07:58.304533 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9886 11:07:58.310706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9887 11:07:58.313883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9888 11:07:58.321482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9889 11:07:58.324022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9890 11:07:58.330937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9891 11:07:58.334152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9892 11:07:58.341239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9893 11:07:58.344028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9894 11:07:58.350812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9895 11:07:58.354657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9896 11:07:58.357504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9897 11:07:58.364220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9898 11:07:58.367754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9899 11:07:58.375035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9900 11:07:58.377437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9901 11:07:58.383925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9902 11:07:58.387159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9903 11:07:58.394391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9904 11:07:58.397466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9905 11:07:58.404233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9906 11:07:58.407417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9907 11:07:58.415320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9908 11:07:58.417424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9909 11:07:58.423905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9910 11:07:58.427190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9911 11:07:58.434400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9912 11:07:58.437842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9913 11:07:58.444581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9914 11:07:58.447947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9915 11:07:58.454604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9916 11:07:58.457779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9917 11:07:58.464552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9918 11:07:58.467861 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9919 11:07:58.471147 INFO: [APUAPC] vio 0
9920 11:07:58.474281 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9921 11:07:58.478096 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9922 11:07:58.481703 INFO: [APUAPC] D0_APC_0: 0x400510
9923 11:07:58.484172 INFO: [APUAPC] D0_APC_1: 0x0
9924 11:07:58.487763 INFO: [APUAPC] D0_APC_2: 0x1540
9925 11:07:58.490814 INFO: [APUAPC] D0_APC_3: 0x0
9926 11:07:58.494579 INFO: [APUAPC] D1_APC_0: 0xffffffff
9927 11:07:58.497574 INFO: [APUAPC] D1_APC_1: 0xffffffff
9928 11:07:58.501211 INFO: [APUAPC] D1_APC_2: 0x3fffff
9929 11:07:58.504294 INFO: [APUAPC] D1_APC_3: 0x0
9930 11:07:58.508109 INFO: [APUAPC] D2_APC_0: 0xffffffff
9931 11:07:58.511044 INFO: [APUAPC] D2_APC_1: 0xffffffff
9932 11:07:58.514328 INFO: [APUAPC] D2_APC_2: 0x3fffff
9933 11:07:58.517970 INFO: [APUAPC] D2_APC_3: 0x0
9934 11:07:58.522127 INFO: [APUAPC] D3_APC_0: 0xffffffff
9935 11:07:58.524117 INFO: [APUAPC] D3_APC_1: 0xffffffff
9936 11:07:58.527791 INFO: [APUAPC] D3_APC_2: 0x3fffff
9937 11:07:58.531119 INFO: [APUAPC] D3_APC_3: 0x0
9938 11:07:58.534246 INFO: [APUAPC] D4_APC_0: 0xffffffff
9939 11:07:58.538047 INFO: [APUAPC] D4_APC_1: 0xffffffff
9940 11:07:58.541088 INFO: [APUAPC] D4_APC_2: 0x3fffff
9941 11:07:58.544267 INFO: [APUAPC] D4_APC_3: 0x0
9942 11:07:58.548262 INFO: [APUAPC] D5_APC_0: 0xffffffff
9943 11:07:58.551094 INFO: [APUAPC] D5_APC_1: 0xffffffff
9944 11:07:58.554663 INFO: [APUAPC] D5_APC_2: 0x3fffff
9945 11:07:58.557738 INFO: [APUAPC] D5_APC_3: 0x0
9946 11:07:58.561171 INFO: [APUAPC] D6_APC_0: 0xffffffff
9947 11:07:58.564150 INFO: [APUAPC] D6_APC_1: 0xffffffff
9948 11:07:58.568107 INFO: [APUAPC] D6_APC_2: 0x3fffff
9949 11:07:58.568579 INFO: [APUAPC] D6_APC_3: 0x0
9950 11:07:58.571544 INFO: [APUAPC] D7_APC_0: 0xffffffff
9951 11:07:58.577770 INFO: [APUAPC] D7_APC_1: 0xffffffff
9952 11:07:58.578238 INFO: [APUAPC] D7_APC_2: 0x3fffff
9953 11:07:58.581427 INFO: [APUAPC] D7_APC_3: 0x0
9954 11:07:58.584501 INFO: [APUAPC] D8_APC_0: 0xffffffff
9955 11:07:58.587463 INFO: [APUAPC] D8_APC_1: 0xffffffff
9956 11:07:58.591438 INFO: [APUAPC] D8_APC_2: 0x3fffff
9957 11:07:58.594513 INFO: [APUAPC] D8_APC_3: 0x0
9958 11:07:58.598182 INFO: [APUAPC] D9_APC_0: 0xffffffff
9959 11:07:58.601077 INFO: [APUAPC] D9_APC_1: 0xffffffff
9960 11:07:58.604190 INFO: [APUAPC] D9_APC_2: 0x3fffff
9961 11:07:58.608012 INFO: [APUAPC] D9_APC_3: 0x0
9962 11:07:58.611301 INFO: [APUAPC] D10_APC_0: 0xffffffff
9963 11:07:58.614720 INFO: [APUAPC] D10_APC_1: 0xffffffff
9964 11:07:58.617657 INFO: [APUAPC] D10_APC_2: 0x3fffff
9965 11:07:58.621321 INFO: [APUAPC] D10_APC_3: 0x0
9966 11:07:58.624246 INFO: [APUAPC] D11_APC_0: 0xffffffff
9967 11:07:58.628082 INFO: [APUAPC] D11_APC_1: 0xffffffff
9968 11:07:58.631186 INFO: [APUAPC] D11_APC_2: 0x3fffff
9969 11:07:58.634591 INFO: [APUAPC] D11_APC_3: 0x0
9970 11:07:58.638337 INFO: [APUAPC] D12_APC_0: 0xffffffff
9971 11:07:58.641091 INFO: [APUAPC] D12_APC_1: 0xffffffff
9972 11:07:58.644551 INFO: [APUAPC] D12_APC_2: 0x3fffff
9973 11:07:58.647955 INFO: [APUAPC] D12_APC_3: 0x0
9974 11:07:58.651531 INFO: [APUAPC] D13_APC_0: 0xffffffff
9975 11:07:58.654486 INFO: [APUAPC] D13_APC_1: 0xffffffff
9976 11:07:58.657988 INFO: [APUAPC] D13_APC_2: 0x3fffff
9977 11:07:58.661012 INFO: [APUAPC] D13_APC_3: 0x0
9978 11:07:58.664575 INFO: [APUAPC] D14_APC_0: 0xffffffff
9979 11:07:58.668525 INFO: [APUAPC] D14_APC_1: 0xffffffff
9980 11:07:58.671230 INFO: [APUAPC] D14_APC_2: 0x3fffff
9981 11:07:58.674713 INFO: [APUAPC] D14_APC_3: 0x0
9982 11:07:58.677706 INFO: [APUAPC] D15_APC_0: 0xffffffff
9983 11:07:58.681573 INFO: [APUAPC] D15_APC_1: 0xffffffff
9984 11:07:58.684948 INFO: [APUAPC] D15_APC_2: 0x3fffff
9985 11:07:58.687943 INFO: [APUAPC] D15_APC_3: 0x0
9986 11:07:58.691980 INFO: [APUAPC] APC_CON: 0x4
9987 11:07:58.694552 INFO: [NOCDAPC] D0_APC_0: 0x0
9988 11:07:58.697665 INFO: [NOCDAPC] D0_APC_1: 0x0
9989 11:07:58.701049 INFO: [NOCDAPC] D1_APC_0: 0x0
9990 11:07:58.704391 INFO: [NOCDAPC] D1_APC_1: 0xfff
9991 11:07:58.704803 INFO: [NOCDAPC] D2_APC_0: 0x0
9992 11:07:58.707665 INFO: [NOCDAPC] D2_APC_1: 0xfff
9993 11:07:58.711014 INFO: [NOCDAPC] D3_APC_0: 0x0
9994 11:07:58.714618 INFO: [NOCDAPC] D3_APC_1: 0xfff
9995 11:07:58.717828 INFO: [NOCDAPC] D4_APC_0: 0x0
9996 11:07:58.720868 INFO: [NOCDAPC] D4_APC_1: 0xfff
9997 11:07:58.724116 INFO: [NOCDAPC] D5_APC_0: 0x0
9998 11:07:58.728211 INFO: [NOCDAPC] D5_APC_1: 0xfff
9999 11:07:58.731405 INFO: [NOCDAPC] D6_APC_0: 0x0
10000 11:07:58.735074 INFO: [NOCDAPC] D6_APC_1: 0xfff
10001 11:07:58.735574 INFO: [NOCDAPC] D7_APC_0: 0x0
10002 11:07:58.738047 INFO: [NOCDAPC] D7_APC_1: 0xfff
10003 11:07:58.741313 INFO: [NOCDAPC] D8_APC_0: 0x0
10004 11:07:58.744511 INFO: [NOCDAPC] D8_APC_1: 0xfff
10005 11:07:58.748386 INFO: [NOCDAPC] D9_APC_0: 0x0
10006 11:07:58.751083 INFO: [NOCDAPC] D9_APC_1: 0xfff
10007 11:07:58.755029 INFO: [NOCDAPC] D10_APC_0: 0x0
10008 11:07:58.757967 INFO: [NOCDAPC] D10_APC_1: 0xfff
10009 11:07:58.761034 INFO: [NOCDAPC] D11_APC_0: 0x0
10010 11:07:58.764300 INFO: [NOCDAPC] D11_APC_1: 0xfff
10011 11:07:58.768292 INFO: [NOCDAPC] D12_APC_0: 0x0
10012 11:07:58.771525 INFO: [NOCDAPC] D12_APC_1: 0xfff
10013 11:07:58.774359 INFO: [NOCDAPC] D13_APC_0: 0x0
10014 11:07:58.774742 INFO: [NOCDAPC] D13_APC_1: 0xfff
10015 11:07:58.777609 INFO: [NOCDAPC] D14_APC_0: 0x0
10016 11:07:58.781325 INFO: [NOCDAPC] D14_APC_1: 0xfff
10017 11:07:58.784896 INFO: [NOCDAPC] D15_APC_0: 0x0
10018 11:07:58.787424 INFO: [NOCDAPC] D15_APC_1: 0xfff
10019 11:07:58.791530 INFO: [NOCDAPC] APC_CON: 0x4
10020 11:07:58.794516 INFO: [APUAPC] set_apusys_apc done
10021 11:07:58.797727 INFO: [DEVAPC] devapc_init done
10022 11:07:58.800912 INFO: GICv3 without legacy support detected.
10023 11:07:58.804392 INFO: ARM GICv3 driver initialized in EL3
10024 11:07:58.810862 INFO: Maximum SPI INTID supported: 639
10025 11:07:58.814469 INFO: BL31: Initializing runtime services
10026 11:07:58.821218 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10027 11:07:58.821665 INFO: SPM: enable CPC mode
10028 11:07:58.827288 INFO: mcdi ready for mcusys-off-idle and system suspend
10029 11:07:58.830954 INFO: BL31: Preparing for EL3 exit to normal world
10030 11:07:58.834107 INFO: Entry point address = 0x80000000
10031 11:07:58.837583 INFO: SPSR = 0x8
10032 11:07:58.843318
10033 11:07:58.843778
10034 11:07:58.844079
10035 11:07:58.846666 Starting depthcharge on Spherion...
10036 11:07:58.847052
10037 11:07:58.847353 Wipe memory regions:
10038 11:07:58.847630
10039 11:07:58.849970 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10040 11:07:58.850441 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10041 11:07:58.850804 Setting prompt string to ['asurada:']
10042 11:07:58.851131 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10043 11:07:58.851716 [0x00000040000000, 0x00000054600000)
10044 11:07:58.972448
10045 11:07:58.972959 [0x00000054660000, 0x00000080000000)
10046 11:07:59.233052
10047 11:07:59.233633 [0x000000821a7280, 0x000000ffe64000)
10048 11:07:59.977520
10049 11:07:59.977990 [0x00000100000000, 0x00000240000000)
10050 11:08:01.867744
10051 11:08:01.871099 Initializing XHCI USB controller at 0x11200000.
10052 11:08:02.909150
10053 11:08:02.912409 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10054 11:08:02.912793
10055 11:08:02.913097
10056 11:08:02.913818 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10057 11:08:02.914339 Sending line: 'tftpboot 192.168.201.1 14786855/tftp-deploy-n63_asce/kernel/image.itb 14786855/tftp-deploy-n63_asce/kernel/cmdline '
10059 11:08:03.015633 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 11:08:03.016039 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10061 11:08:03.020345 asurada: tftpboot 192.168.201.1 14786855/tftp-deploy-n63_asce/kernel/image.itp-deploy-n63_asce/kernel/cmdline
10062 11:08:03.020778
10063 11:08:03.021300 Waiting for link
10064 11:08:03.178460
10065 11:08:03.179000 R8152: Initializing
10066 11:08:03.179402
10067 11:08:03.182104 Version 6 (ocp_data = 5c30)
10068 11:08:03.182489
10069 11:08:03.185221 R8152: Done initializing
10070 11:08:03.185607
10071 11:08:03.185906 Adding net device
10072 11:08:05.151557
10073 11:08:05.152082 done.
10074 11:08:05.152439
10075 11:08:05.152766 MAC: 00:24:32:30:78:52
10076 11:08:05.153108
10077 11:08:05.154066 Sending DHCP discover... done.
10078 11:08:05.154488
10079 11:08:05.157877 Waiting for reply... done.
10080 11:08:05.158503
10081 11:08:05.160881 Sending DHCP request... done.
10082 11:08:05.161294
10083 11:08:05.165805 Waiting for reply... done.
10084 11:08:05.165970
10085 11:08:05.166097 My ip is 192.168.201.14
10086 11:08:05.166242
10087 11:08:05.169465 The DHCP server ip is 192.168.201.1
10088 11:08:05.169688
10089 11:08:05.175926 TFTP server IP predefined by user: 192.168.201.1
10090 11:08:05.176092
10091 11:08:05.182760 Bootfile predefined by user: 14786855/tftp-deploy-n63_asce/kernel/image.itb
10092 11:08:05.183027
10093 11:08:05.183194 Sending tftp read request... done.
10094 11:08:05.183341
10095 11:08:05.190943 Waiting for the transfer...
10096 11:08:05.191253
10097 11:08:05.889168 00000000 ################################################################
10098 11:08:05.889622
10099 11:08:06.546865 00080000 ################################################################
10100 11:08:06.546982
10101 11:08:07.229158 00100000 ################################################################
10102 11:08:07.229645
10103 11:08:07.933907 00180000 ################################################################
10104 11:08:07.934397
10105 11:08:08.646953 00200000 ################################################################
10106 11:08:08.647460
10107 11:08:09.346862 00280000 ################################################################
10108 11:08:09.347322
10109 11:08:09.906562 00300000 ################################################################
10110 11:08:09.906675
10111 11:08:10.474607 00380000 ################################################################
10112 11:08:10.474783
10113 11:08:11.049810 00400000 ################################################################
10114 11:08:11.049955
10115 11:08:11.613287 00480000 ################################################################
10116 11:08:11.613407
10117 11:08:12.187958 00500000 ################################################################
10118 11:08:12.188082
10119 11:08:12.736946 00580000 ################################################################
10120 11:08:12.737075
10121 11:08:13.281980 00600000 ################################################################
10122 11:08:13.282106
10123 11:08:13.824885 00680000 ################################################################
10124 11:08:13.825011
10125 11:08:14.367089 00700000 ################################################################
10126 11:08:14.367213
10127 11:08:14.907936 00780000 ################################################################
10128 11:08:14.908053
10129 11:08:15.451154 00800000 ################################################################
10130 11:08:15.451272
10131 11:08:15.993191 00880000 ################################################################
10132 11:08:15.993315
10133 11:08:16.536267 00900000 ################################################################
10134 11:08:16.536387
10135 11:08:17.077462 00980000 ################################################################
10136 11:08:17.077578
10137 11:08:17.619003 00a00000 ################################################################
10138 11:08:17.619115
10139 11:08:18.166730 00a80000 ################################################################
10140 11:08:18.166857
10141 11:08:18.708377 00b00000 ################################################################
10142 11:08:18.708544
10143 11:08:19.254224 00b80000 ################################################################
10144 11:08:19.254357
10145 11:08:19.797405 00c00000 ################################################################
10146 11:08:19.797529
10147 11:08:20.339655 00c80000 ################################################################
10148 11:08:20.339787
10149 11:08:20.888733 00d00000 ################################################################
10150 11:08:20.888862
10151 11:08:21.431294 00d80000 ################################################################
10152 11:08:21.431421
10153 11:08:21.980795 00e00000 ################################################################
10154 11:08:21.980922
10155 11:08:22.528676 00e80000 ################################################################
10156 11:08:22.528823
10157 11:08:23.078625 00f00000 ################################################################
10158 11:08:23.078740
10159 11:08:23.623393 00f80000 ################################################################
10160 11:08:23.623521
10161 11:08:24.165568 01000000 ################################################################
10162 11:08:24.165696
10163 11:08:24.709903 01080000 ################################################################
10164 11:08:24.710031
10165 11:08:25.260079 01100000 ################################################################
10166 11:08:25.260226
10167 11:08:25.807136 01180000 ################################################################
10168 11:08:25.807285
10169 11:08:26.359434 01200000 ################################################################
10170 11:08:26.359566
10171 11:08:26.902452 01280000 ################################################################
10172 11:08:26.902579
10173 11:08:27.441304 01300000 ################################################################
10174 11:08:27.441422
10175 11:08:27.993605 01380000 ################################################################
10176 11:08:27.993728
10177 11:08:28.544389 01400000 ################################################################
10178 11:08:28.544522
10179 11:08:29.134040 01480000 ################################################################
10180 11:08:29.134156
10181 11:08:29.709894 01500000 ################################################################
10182 11:08:29.710020
10183 11:08:30.254635 01580000 ################################################################
10184 11:08:30.254763
10185 11:08:30.799972 01600000 ################################################################
10186 11:08:30.800101
10187 11:08:31.363898 01680000 ################################################################
10188 11:08:31.364016
10189 11:08:31.930423 01700000 ################################################################
10190 11:08:31.930544
10191 11:08:32.482780 01780000 ################################################################
10192 11:08:32.482900
10193 11:08:33.022921 01800000 ################################################################
10194 11:08:33.023040
10195 11:08:33.569974 01880000 ################################################################
10196 11:08:33.570098
10197 11:08:34.126525 01900000 ################################################################
10198 11:08:34.126647
10199 11:08:34.664628 01980000 ################################################################
10200 11:08:34.664751
10201 11:08:35.226812 01a00000 ################################################################
10202 11:08:35.226937
10203 11:08:35.771803 01a80000 ################################################################
10204 11:08:35.771933
10205 11:08:36.314334 01b00000 ################################################################
10206 11:08:36.314456
10207 11:08:36.854847 01b80000 ################################################################
10208 11:08:36.855041
10209 11:08:37.404603 01c00000 ################################################################
10210 11:08:37.404716
10211 11:08:37.944188 01c80000 ################################################################
10212 11:08:37.944322
10213 11:08:38.485382 01d00000 ################################################################
10214 11:08:38.485505
10215 11:08:39.026881 01d80000 ################################################################
10216 11:08:39.027003
10217 11:08:39.566286 01e00000 ################################################################
10218 11:08:39.566413
10219 11:08:40.111903 01e80000 ################################################################
10220 11:08:40.112073
10221 11:08:40.668572 01f00000 ################################################################
10222 11:08:40.668700
10223 11:08:41.226087 01f80000 ################################################################
10224 11:08:41.226200
10225 11:08:41.766599 02000000 ################################################################
10226 11:08:41.766752
10227 11:08:42.301173 02080000 ################################################################
10228 11:08:42.301326
10229 11:08:42.841689 02100000 ################################################################
10230 11:08:42.841822
10231 11:08:43.385667 02180000 ################################################################
10232 11:08:43.385800
10233 11:08:43.940212 02200000 ################################################################
10234 11:08:43.940342
10235 11:08:44.512748 02280000 ################################################################
10236 11:08:44.512906
10237 11:08:45.060597 02300000 ################################################################
10238 11:08:45.060733
10239 11:08:45.606884 02380000 ################################################################
10240 11:08:45.607013
10241 11:08:46.172904 02400000 ################################################################
10242 11:08:46.173068
10243 11:08:46.720306 02480000 ################################################################
10244 11:08:46.720430
10245 11:08:47.275718 02500000 ################################################################
10246 11:08:47.275844
10247 11:08:47.820685 02580000 ################################################################
10248 11:08:47.820855
10249 11:08:48.391250 02600000 ################################################################
10250 11:08:48.391370
10251 11:08:48.997468 02680000 ################################################################
10252 11:08:48.997600
10253 11:08:49.582758 02700000 ################################################################
10254 11:08:49.582884
10255 11:08:50.181947 02780000 ################################################################
10256 11:08:50.182076
10257 11:08:50.765774 02800000 ################################################################
10258 11:08:50.765891
10259 11:08:51.330809 02880000 ################################################################
10260 11:08:51.330935
10261 11:08:51.888175 02900000 ################################################################
10262 11:08:51.888305
10263 11:08:52.480060 02980000 ################################################################
10264 11:08:52.480196
10265 11:08:53.071498 02a00000 ################################################################
10266 11:08:53.071661
10267 11:08:53.630950 02a80000 ################################################################
10268 11:08:53.631087
10269 11:08:54.191135 02b00000 ################################################################
10270 11:08:54.191273
10271 11:08:54.766787 02b80000 ################################################################
10272 11:08:54.766908
10273 11:08:55.349694 02c00000 ################################################################
10274 11:08:55.349849
10275 11:08:55.922711 02c80000 ################################################################
10276 11:08:55.922847
10277 11:08:56.478564 02d00000 ################################################################
10278 11:08:56.478695
10279 11:08:57.037686 02d80000 ################################################################
10280 11:08:57.037822
10281 11:08:57.621235 02e00000 ################################################################
10282 11:08:57.621375
10283 11:08:58.196550 02e80000 ################################################################
10284 11:08:58.196713
10285 11:08:58.773540 02f00000 ################################################################
10286 11:08:58.773673
10287 11:08:59.344770 02f80000 ################################################################
10288 11:08:59.344901
10289 11:08:59.922390 03000000 ################################################################
10290 11:08:59.922537
10291 11:09:00.515483 03080000 ################################################################
10292 11:09:00.515607
10293 11:09:01.090105 03100000 ################################################################
10294 11:09:01.090227
10295 11:09:01.664573 03180000 ################################################################
10296 11:09:01.664784
10297 11:09:02.244639 03200000 ################################################################
10298 11:09:02.244777
10299 11:09:02.813268 03280000 ################################################################
10300 11:09:02.813384
10301 11:09:03.374439 03300000 ################################################################
10302 11:09:03.374580
10303 11:09:03.941043 03380000 ################################################################
10304 11:09:03.941199
10305 11:09:04.511344 03400000 ################################################################
10306 11:09:04.511491
10307 11:09:05.106515 03480000 ################################################################
10308 11:09:05.106630
10309 11:09:05.689493 03500000 ################################################################
10310 11:09:05.689678
10311 11:09:06.317517 03580000 ################################################################
10312 11:09:06.317936
10313 11:09:06.998104 03600000 ################################################################
10314 11:09:06.998546
10315 11:09:07.688681 03680000 ################################################################
10316 11:09:07.688798
10317 11:09:08.371031 03700000 ################################################################
10318 11:09:08.371590
10319 11:09:09.059774 03780000 ################################################################
10320 11:09:09.060354
10321 11:09:09.617887 03800000 ################################################################
10322 11:09:09.618016
10323 11:09:10.151481 03880000 ################################################################
10324 11:09:10.151609
10325 11:09:10.760649 03900000 ################################################################
10326 11:09:10.761284
10327 11:09:11.441915 03980000 ################################################################
10328 11:09:11.442373
10329 11:09:12.138056 03a00000 ################################################################
10330 11:09:12.138515
10331 11:09:12.759541 03a80000 ################################################################
10332 11:09:12.759788
10333 11:09:13.413193 03b00000 ################################################################
10334 11:09:13.413728
10335 11:09:14.092503 03b80000 ################################################################
10336 11:09:14.093173
10337 11:09:14.803929 03c00000 ################################################################
10338 11:09:14.804509
10339 11:09:15.501473 03c80000 ################################################################
10340 11:09:15.501934
10341 11:09:16.161914 03d00000 ################################################################
10342 11:09:16.162402
10343 11:09:16.889321 03d80000 ################################################################
10344 11:09:16.889803
10345 11:09:17.253476 03e00000 ################################# done.
10346 11:09:17.253978
10347 11:09:17.257094 The bootfile was 65275614 bytes long.
10348 11:09:17.257556
10349 11:09:17.259985 Sending tftp read request... done.
10350 11:09:17.260378
10351 11:09:17.266824 Waiting for the transfer...
10352 11:09:17.267274
10353 11:09:17.267606 00000000 # done.
10354 11:09:17.267905
10355 11:09:17.273327 Command line loaded dynamically from TFTP file: 14786855/tftp-deploy-n63_asce/kernel/cmdline
10356 11:09:17.273792
10357 11:09:17.286393 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10358 11:09:17.286809
10359 11:09:17.289754 Loading FIT.
10360 11:09:17.290138
10361 11:09:17.293762 Image ramdisk-1 has 52110070 bytes.
10362 11:09:17.294243
10363 11:09:17.297254 Image fdt-1 has 47258 bytes.
10364 11:09:17.297723
10365 11:09:17.298028 Image kernel-1 has 13116259 bytes.
10366 11:09:17.300069
10367 11:09:17.306858 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10368 11:09:17.307325
10369 11:09:17.323327 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10370 11:09:17.323847
10371 11:09:17.330084 Choosing best match conf-1 for compat google,spherion-rev2.
10372 11:09:17.334576
10373 11:09:17.339866 Connected to device vid:did:rid of 1ae0:0028:00
10374 11:09:17.346925
10375 11:09:17.350378 tpm_get_response: command 0x17b, return code 0x0
10376 11:09:17.350843
10377 11:09:17.353700 ec_init: CrosEC protocol v3 supported (256, 248)
10378 11:09:17.358096
10379 11:09:17.361223 tpm_cleanup: add release locality here.
10380 11:09:17.361611
10381 11:09:17.361912 Shutting down all USB controllers.
10382 11:09:17.362194
10383 11:09:17.364089 Removing current net device
10384 11:09:17.364474
10385 11:09:17.370708 Exiting depthcharge with code 4 at timestamp: 107875543
10386 11:09:17.371100
10387 11:09:17.374603 LZMA decompressing kernel-1 to 0x821a6718
10388 11:09:17.375070
10389 11:09:17.377730 LZMA decompressing kernel-1 to 0x40000000
10390 11:09:18.994049
10391 11:09:18.994552 jumping to kernel
10392 11:09:18.996800 end: 2.2.4 bootloader-commands (duration 00:01:20) [common]
10393 11:09:18.997333 start: 2.2.5 auto-login-action (timeout 00:03:00) [common]
10394 11:09:18.997715 Setting prompt string to ['Linux version [0-9]']
10395 11:09:18.998070 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10396 11:09:18.998444 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10397 11:09:19.074353
10398 11:09:19.077726 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10399 11:09:19.081678 start: 2.2.5.1 login-action (timeout 00:03:00) [common]
10400 11:09:19.082166 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10401 11:09:19.082542 Setting prompt string to []
10402 11:09:19.082951 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10403 11:09:19.083325 Using line separator: #'\n'#
10404 11:09:19.083628 No login prompt set.
10405 11:09:19.083933 Parsing kernel messages
10406 11:09:19.084218 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10407 11:09:19.084758 [login-action] Waiting for messages, (timeout 00:03:00)
10408 11:09:19.085082 Waiting using forced prompt support (timeout 00:01:30)
10409 11:09:19.100993 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10410 11:09:19.104425 [ 0.000000] random: crng init done
10411 11:09:19.108008 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10412 11:09:19.110851 [ 0.000000] efi: UEFI not found.
10413 11:09:19.121367 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10414 11:09:19.128261 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10415 11:09:19.138426 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10416 11:09:19.148441 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10417 11:09:19.155003 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10418 11:09:19.158473 [ 0.000000] printk: bootconsole [mtk8250] enabled
10419 11:09:19.165888 [ 0.000000] NUMA: No NUMA configuration found
10420 11:09:19.172944 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10421 11:09:19.178678 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10422 11:09:19.179113 [ 0.000000] Zone ranges:
10423 11:09:19.185211 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10424 11:09:19.188578 [ 0.000000] DMA32 empty
10425 11:09:19.196228 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10426 11:09:19.198883 [ 0.000000] Movable zone start for each node
10427 11:09:19.201936 [ 0.000000] Early memory node ranges
10428 11:09:19.209414 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10429 11:09:19.215459 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10430 11:09:19.221939 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10431 11:09:19.228870 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10432 11:09:19.236344 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10433 11:09:19.241919 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10434 11:09:19.298959 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10435 11:09:19.305813 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10436 11:09:19.312480 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10437 11:09:19.316041 [ 0.000000] psci: probing for conduit method from DT.
10438 11:09:19.322373 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10439 11:09:19.325319 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10440 11:09:19.332439 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10441 11:09:19.335886 [ 0.000000] psci: SMC Calling Convention v1.2
10442 11:09:19.342447 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10443 11:09:19.345815 [ 0.000000] Detected VIPT I-cache on CPU0
10444 11:09:19.352213 [ 0.000000] CPU features: detected: GIC system register CPU interface
10445 11:09:19.359362 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10446 11:09:19.365551 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10447 11:09:19.372828 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10448 11:09:19.379717 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10449 11:09:19.386010 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10450 11:09:19.392315 [ 0.000000] alternatives: applying boot alternatives
10451 11:09:19.395279 [ 0.000000] Fallback order for Node 0: 0
10452 11:09:19.402362 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10453 11:09:19.405959 [ 0.000000] Policy zone: Normal
10454 11:09:19.422714 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10455 11:09:19.432909 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10456 11:09:19.443678 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10457 11:09:19.454538 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10458 11:09:19.460110 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10459 11:09:19.463626 <6>[ 0.000000] software IO TLB: area num 8.
10460 11:09:19.520683 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10461 11:09:19.669508 <6>[ 0.000000] Memory: 7913168K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 439600K reserved, 32768K cma-reserved)
10462 11:09:19.676867 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10463 11:09:19.683538 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10464 11:09:19.686570 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10465 11:09:19.693102 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10466 11:09:19.699804 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10467 11:09:19.702838 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10468 11:09:19.712831 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10469 11:09:19.719774 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10470 11:09:19.722707 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10471 11:09:19.730789 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10472 11:09:19.734186 <6>[ 0.000000] GICv3: 608 SPIs implemented
10473 11:09:19.740730 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10474 11:09:19.744319 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10475 11:09:19.747667 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10476 11:09:19.757849 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10477 11:09:19.767233 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10478 11:09:19.780794 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10479 11:09:19.787779 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10480 11:09:19.796144 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10481 11:09:19.809771 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10482 11:09:19.816166 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10483 11:09:19.823184 <6>[ 0.009176] Console: colour dummy device 80x25
10484 11:09:19.833014 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10485 11:09:19.836082 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10486 11:09:19.842947 <6>[ 0.029221] LSM: Security Framework initializing
10487 11:09:19.849540 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10488 11:09:19.859909 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10489 11:09:19.866733 <6>[ 0.051441] cblist_init_generic: Setting adjustable number of callback queues.
10490 11:09:19.872884 <6>[ 0.058880] cblist_init_generic: Setting shift to 3 and lim to 1.
10491 11:09:19.879450 <6>[ 0.065219] cblist_init_generic: Setting adjustable number of callback queues.
10492 11:09:19.886027 <6>[ 0.072646] cblist_init_generic: Setting shift to 3 and lim to 1.
10493 11:09:19.893165 <6>[ 0.079048] rcu: Hierarchical SRCU implementation.
10494 11:09:19.899544 <6>[ 0.084093] rcu: Max phase no-delay instances is 1000.
10495 11:09:19.905870 <6>[ 0.091148] EFI services will not be available.
10496 11:09:19.909112 <6>[ 0.096106] smp: Bringing up secondary CPUs ...
10497 11:09:19.916624 <6>[ 0.101161] Detected VIPT I-cache on CPU1
10498 11:09:19.923178 <6>[ 0.101233] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10499 11:09:19.929893 <6>[ 0.101262] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10500 11:09:19.933331 <6>[ 0.101607] Detected VIPT I-cache on CPU2
10501 11:09:19.940055 <6>[ 0.101660] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10502 11:09:19.946786 <6>[ 0.101678] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10503 11:09:19.953815 <6>[ 0.101938] Detected VIPT I-cache on CPU3
10504 11:09:19.960431 <6>[ 0.101987] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10505 11:09:19.967654 <6>[ 0.102002] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10506 11:09:19.970817 <6>[ 0.102308] CPU features: detected: Spectre-v4
10507 11:09:19.976984 <6>[ 0.102315] CPU features: detected: Spectre-BHB
10508 11:09:19.980380 <6>[ 0.102320] Detected PIPT I-cache on CPU4
10509 11:09:19.987443 <6>[ 0.102379] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10510 11:09:19.993780 <6>[ 0.102397] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10511 11:09:19.996739 <6>[ 0.102692] Detected PIPT I-cache on CPU5
10512 11:09:20.007122 <6>[ 0.102754] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10513 11:09:20.013649 <6>[ 0.102770] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10514 11:09:20.016784 <6>[ 0.103051] Detected PIPT I-cache on CPU6
10515 11:09:20.023847 <6>[ 0.103116] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10516 11:09:20.030741 <6>[ 0.103132] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10517 11:09:20.034145 <6>[ 0.103431] Detected PIPT I-cache on CPU7
10518 11:09:20.040271 <6>[ 0.103497] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10519 11:09:20.050837 <6>[ 0.103512] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10520 11:09:20.053376 <6>[ 0.103560] smp: Brought up 1 node, 8 CPUs
10521 11:09:20.056690 <6>[ 0.244781] SMP: Total of 8 processors activated.
10522 11:09:20.063755 <6>[ 0.249702] CPU features: detected: 32-bit EL0 Support
10523 11:09:20.073583 <6>[ 0.255065] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10524 11:09:20.080610 <6>[ 0.263866] CPU features: detected: Common not Private translations
10525 11:09:20.083443 <6>[ 0.270342] CPU features: detected: CRC32 instructions
10526 11:09:20.090417 <6>[ 0.275726] CPU features: detected: RCpc load-acquire (LDAPR)
10527 11:09:20.097003 <6>[ 0.281723] CPU features: detected: LSE atomic instructions
10528 11:09:20.100325 <6>[ 0.287504] CPU features: detected: Privileged Access Never
10529 11:09:20.106813 <6>[ 0.293320] CPU features: detected: RAS Extension Support
10530 11:09:20.113527 <6>[ 0.298963] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10531 11:09:20.120095 <6>[ 0.306181] CPU: All CPU(s) started at EL2
10532 11:09:20.123797 <6>[ 0.310524] alternatives: applying system-wide alternatives
10533 11:09:20.135171 <6>[ 0.321406] devtmpfs: initialized
10534 11:09:20.146721 <6>[ 0.330216] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10535 11:09:20.156858 <6>[ 0.340175] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10536 11:09:20.163576 <6>[ 0.348416] pinctrl core: initialized pinctrl subsystem
10537 11:09:20.167095 <6>[ 0.355080] DMI not present or invalid.
10538 11:09:20.173424 <6>[ 0.359490] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10539 11:09:20.183417 <6>[ 0.366375] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10540 11:09:20.190288 <6>[ 0.373958] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10541 11:09:20.199826 <6>[ 0.382169] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10542 11:09:20.203249 <6>[ 0.390412] audit: initializing netlink subsys (disabled)
10543 11:09:20.213702 <5>[ 0.396103] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10544 11:09:20.219801 <6>[ 0.396813] thermal_sys: Registered thermal governor 'step_wise'
10545 11:09:20.227201 <6>[ 0.404068] thermal_sys: Registered thermal governor 'power_allocator'
10546 11:09:20.229698 <6>[ 0.410323] cpuidle: using governor menu
10547 11:09:20.236301 <6>[ 0.421282] NET: Registered PF_QIPCRTR protocol family
10548 11:09:20.242930 <6>[ 0.426772] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10549 11:09:20.246763 <6>[ 0.433871] ASID allocator initialised with 32768 entries
10550 11:09:20.254225 <6>[ 0.440447] Serial: AMBA PL011 UART driver
10551 11:09:20.263219 <4>[ 0.449780] Trying to register duplicate clock ID: 134
10552 11:09:20.321824 <6>[ 0.510942] KASLR enabled
10553 11:09:20.335386 <6>[ 0.518600] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10554 11:09:20.341785 <6>[ 0.525612] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10555 11:09:20.348430 <6>[ 0.532099] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10556 11:09:20.355508 <6>[ 0.539104] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10557 11:09:20.362595 <6>[ 0.545591] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10558 11:09:20.368609 <6>[ 0.552595] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10559 11:09:20.375939 <6>[ 0.559080] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10560 11:09:20.382045 <6>[ 0.566084] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10561 11:09:20.385376 <6>[ 0.573601] ACPI: Interpreter disabled.
10562 11:09:20.393220 <6>[ 0.580045] iommu: Default domain type: Translated
10563 11:09:20.400480 <6>[ 0.585157] iommu: DMA domain TLB invalidation policy: strict mode
10564 11:09:20.403892 <5>[ 0.591808] SCSI subsystem initialized
10565 11:09:20.410538 <6>[ 0.595970] usbcore: registered new interface driver usbfs
10566 11:09:20.416415 <6>[ 0.601704] usbcore: registered new interface driver hub
10567 11:09:20.419826 <6>[ 0.607255] usbcore: registered new device driver usb
10568 11:09:20.426826 <6>[ 0.613360] pps_core: LinuxPPS API ver. 1 registered
10569 11:09:20.437108 <6>[ 0.618556] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10570 11:09:20.440462 <6>[ 0.627900] PTP clock support registered
10571 11:09:20.443872 <6>[ 0.632144] EDAC MC: Ver: 3.0.0
10572 11:09:20.451182 <6>[ 0.637308] FPGA manager framework
10573 11:09:20.457873 <6>[ 0.640992] Advanced Linux Sound Architecture Driver Initialized.
10574 11:09:20.460285 <6>[ 0.647781] vgaarb: loaded
10575 11:09:20.466946 <6>[ 0.650947] clocksource: Switched to clocksource arch_sys_counter
10576 11:09:20.470376 <5>[ 0.657398] VFS: Disk quotas dquot_6.6.0
10577 11:09:20.477094 <6>[ 0.661586] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10578 11:09:20.480332 <6>[ 0.668773] pnp: PnP ACPI: disabled
10579 11:09:20.488980 <6>[ 0.675525] NET: Registered PF_INET protocol family
10580 11:09:20.498782 <6>[ 0.681136] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10581 11:09:20.510341 <6>[ 0.693488] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10582 11:09:20.520069 <6>[ 0.702302] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10583 11:09:20.527050 <6>[ 0.710272] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10584 11:09:20.533444 <6>[ 0.718974] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10585 11:09:20.546074 <6>[ 0.728724] TCP: Hash tables configured (established 65536 bind 65536)
10586 11:09:20.552375 <6>[ 0.735590] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10587 11:09:20.558887 <6>[ 0.742790] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10588 11:09:20.565688 <6>[ 0.750493] NET: Registered PF_UNIX/PF_LOCAL protocol family
10589 11:09:20.572115 <6>[ 0.756643] RPC: Registered named UNIX socket transport module.
10590 11:09:20.575658 <6>[ 0.762796] RPC: Registered udp transport module.
10591 11:09:20.581791 <6>[ 0.767728] RPC: Registered tcp transport module.
10592 11:09:20.589173 <6>[ 0.772661] RPC: Registered tcp NFSv4.1 backchannel transport module.
10593 11:09:20.591928 <6>[ 0.779328] PCI: CLS 0 bytes, default 64
10594 11:09:20.595825 <6>[ 0.783656] Unpacking initramfs...
10595 11:09:20.619801 <6>[ 0.803122] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10596 11:09:20.629958 <6>[ 0.811751] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10597 11:09:20.633588 <6>[ 0.820585] kvm [1]: IPA Size Limit: 40 bits
10598 11:09:20.640784 <6>[ 0.825111] kvm [1]: GICv3: no GICV resource entry
10599 11:09:20.643418 <6>[ 0.830131] kvm [1]: disabling GICv2 emulation
10600 11:09:20.650333 <6>[ 0.834817] kvm [1]: GIC system register CPU interface enabled
10601 11:09:20.653104 <6>[ 0.840974] kvm [1]: vgic interrupt IRQ18
10602 11:09:20.660186 <6>[ 0.845327] kvm [1]: VHE mode initialized successfully
10603 11:09:20.662903 <5>[ 0.851594] Initialise system trusted keyrings
10604 11:09:20.672898 <6>[ 0.856397] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10605 11:09:20.679926 <6>[ 0.866327] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10606 11:09:20.686763 <5>[ 0.872713] NFS: Registering the id_resolver key type
10607 11:09:20.690343 <5>[ 0.878013] Key type id_resolver registered
10608 11:09:20.696624 <5>[ 0.882427] Key type id_legacy registered
10609 11:09:20.703290 <6>[ 0.886706] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10610 11:09:20.709899 <6>[ 0.893626] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10611 11:09:20.716562 <6>[ 0.901340] 9p: Installing v9fs 9p2000 file system support
10612 11:09:20.754044 <5>[ 0.940029] Key type asymmetric registered
10613 11:09:20.756751 <5>[ 0.944360] Asymmetric key parser 'x509' registered
10614 11:09:20.766568 <6>[ 0.949500] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10615 11:09:20.770084 <6>[ 0.957115] io scheduler mq-deadline registered
10616 11:09:20.773804 <6>[ 0.961897] io scheduler kyber registered
10617 11:09:20.792729 <6>[ 0.978969] EINJ: ACPI disabled.
10618 11:09:20.825448 <4>[ 1.005443] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 11:09:20.835416 <4>[ 1.016076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 11:09:20.850883 <6>[ 1.037234] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10621 11:09:20.858930 <6>[ 1.045288] printk: console [ttyS0] disabled
10622 11:09:20.886432 <6>[ 1.069922] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10623 11:09:20.893750 <6>[ 1.079396] printk: console [ttyS0] enabled
10624 11:09:20.897331 <6>[ 1.079396] printk: console [ttyS0] enabled
10625 11:09:20.903342 <6>[ 1.088296] printk: bootconsole [mtk8250] disabled
10626 11:09:20.906186 <6>[ 1.088296] printk: bootconsole [mtk8250] disabled
10627 11:09:20.913251 <6>[ 1.099649] SuperH (H)SCI(F) driver initialized
10628 11:09:20.916063 <6>[ 1.104955] msm_serial: driver initialized
10629 11:09:20.930471 <6>[ 1.113985] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10630 11:09:20.940497 <6>[ 1.122544] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10631 11:09:20.947213 <6>[ 1.131085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10632 11:09:20.957313 <6>[ 1.139713] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10633 11:09:20.963848 <6>[ 1.148424] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10634 11:09:20.973633 <6>[ 1.157139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10635 11:09:20.984264 <6>[ 1.165679] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10636 11:09:20.990258 <6>[ 1.174483] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10637 11:09:21.000295 <6>[ 1.183026] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10638 11:09:21.012462 <6>[ 1.198671] loop: module loaded
10639 11:09:21.018566 <6>[ 1.204604] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10640 11:09:21.041491 <4>[ 1.228126] mtk-pmic-keys: Failed to locate of_node [id: -1]
10641 11:09:21.048202 <6>[ 1.235142] megasas: 07.719.03.00-rc1
10642 11:09:21.058363 <6>[ 1.244760] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10643 11:09:21.072026 <6>[ 1.258329] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10644 11:09:21.088985 <6>[ 1.275164] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10645 11:09:21.145546 <6>[ 1.325740] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10646 11:09:22.846000 <6>[ 3.032452] Freeing initrd memory: 50888K
10647 11:09:22.857049 <6>[ 3.044128] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10648 11:09:22.868278 <6>[ 3.055015] tun: Universal TUN/TAP device driver, 1.6
10649 11:09:22.872342 <6>[ 3.061075] thunder_xcv, ver 1.0
10650 11:09:22.874563 <6>[ 3.064580] thunder_bgx, ver 1.0
10651 11:09:22.878281 <6>[ 3.068074] nicpf, ver 1.0
10652 11:09:22.888416 <6>[ 3.072088] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10653 11:09:22.892059 <6>[ 3.079564] hns3: Copyright (c) 2017 Huawei Corporation.
10654 11:09:22.895621 <6>[ 3.085150] hclge is initializing
10655 11:09:22.901776 <6>[ 3.088730] e1000: Intel(R) PRO/1000 Network Driver
10656 11:09:22.908350 <6>[ 3.093858] e1000: Copyright (c) 1999-2006 Intel Corporation.
10657 11:09:22.911710 <6>[ 3.099874] e1000e: Intel(R) PRO/1000 Network Driver
10658 11:09:22.918559 <6>[ 3.105090] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10659 11:09:22.926057 <6>[ 3.111274] igb: Intel(R) Gigabit Ethernet Network Driver
10660 11:09:22.931537 <6>[ 3.116924] igb: Copyright (c) 2007-2014 Intel Corporation.
10661 11:09:22.938393 <6>[ 3.122760] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10662 11:09:22.945321 <6>[ 3.129278] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10663 11:09:22.948262 <6>[ 3.135742] sky2: driver version 1.30
10664 11:09:22.955069 <6>[ 3.140668] usbcore: registered new device driver r8152-cfgselector
10665 11:09:22.961456 <6>[ 3.147202] usbcore: registered new interface driver r8152
10666 11:09:22.968481 <6>[ 3.153022] VFIO - User Level meta-driver version: 0.3
10667 11:09:22.974978 <6>[ 3.161272] usbcore: registered new interface driver usb-storage
10668 11:09:22.981637 <6>[ 3.167719] usbcore: registered new device driver onboard-usb-hub
10669 11:09:22.990344 <6>[ 3.176862] mt6397-rtc mt6359-rtc: registered as rtc0
10670 11:09:23.000113 <6>[ 3.182328] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:09:22 UTC (1720609762)
10671 11:09:23.003333 <6>[ 3.191894] i2c_dev: i2c /dev entries driver
10672 11:09:23.017799 <4>[ 3.203902] cpu cpu0: supply cpu not found, using dummy regulator
10673 11:09:23.023659 <4>[ 3.210331] cpu cpu1: supply cpu not found, using dummy regulator
10674 11:09:23.030498 <4>[ 3.216737] cpu cpu2: supply cpu not found, using dummy regulator
10675 11:09:23.037340 <4>[ 3.223136] cpu cpu3: supply cpu not found, using dummy regulator
10676 11:09:23.044286 <4>[ 3.229552] cpu cpu4: supply cpu not found, using dummy regulator
10677 11:09:23.050316 <4>[ 3.235946] cpu cpu5: supply cpu not found, using dummy regulator
10678 11:09:23.057306 <4>[ 3.242347] cpu cpu6: supply cpu not found, using dummy regulator
10679 11:09:23.063864 <4>[ 3.248742] cpu cpu7: supply cpu not found, using dummy regulator
10680 11:09:23.082217 <6>[ 3.269368] cpu cpu0: EM: created perf domain
10681 11:09:23.085924 <6>[ 3.274319] cpu cpu4: EM: created perf domain
10682 11:09:23.093775 <6>[ 3.279924] sdhci: Secure Digital Host Controller Interface driver
10683 11:09:23.099887 <6>[ 3.286357] sdhci: Copyright(c) Pierre Ossman
10684 11:09:23.106336 <6>[ 3.291307] Synopsys Designware Multimedia Card Interface Driver
10685 11:09:23.113182 <6>[ 3.297949] sdhci-pltfm: SDHCI platform and OF driver helper
10686 11:09:23.116385 <6>[ 3.298002] mmc0: CQHCI version 5.10
10687 11:09:23.122560 <6>[ 3.308280] ledtrig-cpu: registered to indicate activity on CPUs
10688 11:09:23.129400 <6>[ 3.315093] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10689 11:09:23.136525 <6>[ 3.322146] usbcore: registered new interface driver usbhid
10690 11:09:23.139243 <6>[ 3.327967] usbhid: USB HID core driver
10691 11:09:23.146416 <6>[ 3.332163] spi_master spi0: will run message pump with realtime priority
10692 11:09:23.194544 <6>[ 3.374502] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10693 11:09:23.213233 <6>[ 3.390217] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10694 11:09:23.216771 <6>[ 3.403588] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15014
10695 11:09:23.223464 <6>[ 3.409750] mmc0: Command Queue Engine enabled
10696 11:09:23.226539 <6>[ 3.411297] cros-ec-spi spi0.0: Chrome EC device registered
10697 11:09:23.233403 <6>[ 3.414476] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10698 11:09:23.240435 <6>[ 3.427600] mmcblk0: mmc0:0001 DA4128 116 GiB
10699 11:09:23.250786 <6>[ 3.432931] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10700 11:09:23.257381 <6>[ 3.442869] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10701 11:09:23.260759 <6>[ 3.443359] NET: Registered PF_PACKET protocol family
10702 11:09:23.267039 <6>[ 3.450173] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10703 11:09:23.270684 <6>[ 3.454189] 9pnet: Installing 9P2000 support
10704 11:09:23.277494 <6>[ 3.460005] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10705 11:09:23.280504 <5>[ 3.463876] Key type dns_resolver registered
10706 11:09:23.287188 <6>[ 3.469695] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10707 11:09:23.293734 <6>[ 3.474115] registered taskstats version 1
10708 11:09:23.296828 <5>[ 3.484493] Loading compiled-in X.509 certificates
10709 11:09:23.332345 <4>[ 3.512347] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10710 11:09:23.342535 <4>[ 3.523065] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10711 11:09:23.357919 <6>[ 3.544719] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10712 11:09:23.365185 <6>[ 3.551678] xhci-mtk 11200000.usb: xHCI Host Controller
10713 11:09:23.371316 <6>[ 3.557227] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10714 11:09:23.381820 <6>[ 3.565103] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10715 11:09:23.388165 <6>[ 3.574545] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10716 11:09:23.394875 <6>[ 3.580630] xhci-mtk 11200000.usb: xHCI Host Controller
10717 11:09:23.401494 <6>[ 3.586115] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10718 11:09:23.408244 <6>[ 3.593878] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10719 11:09:23.415434 <6>[ 3.601705] hub 1-0:1.0: USB hub found
10720 11:09:23.418349 <6>[ 3.605758] hub 1-0:1.0: 1 port detected
10721 11:09:23.428214 <6>[ 3.610050] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10722 11:09:23.431725 <6>[ 3.618605] hub 2-0:1.0: USB hub found
10723 11:09:23.434398 <6>[ 3.622630] hub 2-0:1.0: 1 port detected
10724 11:09:23.442645 <6>[ 3.629619] mtk-msdc 11f70000.mmc: Got CD GPIO
10725 11:09:23.455255 <6>[ 3.638672] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10726 11:09:23.465325 <6>[ 3.647095] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10727 11:09:23.471765 <6>[ 3.655438] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10728 11:09:23.482076 <6>[ 3.663776] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10729 11:09:23.488267 <6>[ 3.672120] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10730 11:09:23.497973 <6>[ 3.680459] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10731 11:09:23.505042 <6>[ 3.688802] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10732 11:09:23.514591 <6>[ 3.697141] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10733 11:09:23.521714 <6>[ 3.705480] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10734 11:09:23.531417 <6>[ 3.713831] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10735 11:09:23.538100 <6>[ 3.722171] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10736 11:09:23.548015 <6>[ 3.730520] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10737 11:09:23.554211 <6>[ 3.738860] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10738 11:09:23.564251 <6>[ 3.747200] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10739 11:09:23.571397 <6>[ 3.755538] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10740 11:09:23.577548 <6>[ 3.764237] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10741 11:09:23.584467 <6>[ 3.771402] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10742 11:09:23.591329 <6>[ 3.778202] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10743 11:09:23.602101 <6>[ 3.784967] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10744 11:09:23.607641 <6>[ 3.791938] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10745 11:09:23.614497 <6>[ 3.798809] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10746 11:09:23.624265 <6>[ 3.807946] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10747 11:09:23.634349 <6>[ 3.817066] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10748 11:09:23.644631 <6>[ 3.826361] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10749 11:09:23.653819 <6>[ 3.835828] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10750 11:09:23.660806 <6>[ 3.845297] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10751 11:09:23.671202 <6>[ 3.854417] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10752 11:09:23.680880 <6>[ 3.863884] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10753 11:09:23.690903 <6>[ 3.873004] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10754 11:09:23.700680 <6>[ 3.882299] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10755 11:09:23.710253 <6>[ 3.892459] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10756 11:09:23.720628 <6>[ 3.904170] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10757 11:09:23.843604 <6>[ 4.027239] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10758 11:09:23.998763 <6>[ 4.185173] hub 1-1:1.0: USB hub found
10759 11:09:24.001221 <6>[ 4.189700] hub 1-1:1.0: 4 ports detected
10760 11:09:24.013528 <6>[ 4.200698] hub 1-1:1.0: USB hub found
10761 11:09:24.017180 <6>[ 4.205105] hub 1-1:1.0: 4 ports detected
10762 11:09:24.123376 <6>[ 4.307425] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10763 11:09:24.150631 <6>[ 4.337107] hub 2-1:1.0: USB hub found
10764 11:09:24.153506 <6>[ 4.341641] hub 2-1:1.0: 3 ports detected
10765 11:09:24.166156 <6>[ 4.352450] hub 2-1:1.0: USB hub found
10766 11:09:24.169329 <6>[ 4.356889] hub 2-1:1.0: 3 ports detected
10767 11:09:24.339464 <6>[ 4.523271] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10768 11:09:24.472058 <6>[ 4.658676] hub 1-1.4:1.0: USB hub found
10769 11:09:24.475408 <6>[ 4.663228] hub 1-1.4:1.0: 2 ports detected
10770 11:09:24.486433 <6>[ 4.673678] hub 1-1.4:1.0: USB hub found
10771 11:09:24.490151 <6>[ 4.678235] hub 1-1.4:1.0: 2 ports detected
10772 11:09:24.551439 <6>[ 4.735326] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10773 11:09:24.660128 <6>[ 4.843680] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10774 11:09:24.692747 <4>[ 4.876106] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10775 11:09:24.702061 <4>[ 4.885211] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10776 11:09:24.737230 <6>[ 4.924463] r8152 2-1.3:1.0 eth0: v1.12.13
10777 11:09:24.787437 <6>[ 4.971245] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10778 11:09:24.983528 <6>[ 5.167289] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10779 11:09:26.392793 <6>[ 6.580239] r8152 2-1.3:1.0 eth0: carrier on
10780 11:09:28.863343 <5>[ 6.603272] Sending DHCP requests .., OK
10781 11:09:28.870418 <6>[ 9.055492] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10782 11:09:28.873421 <6>[ 9.063791] IP-Config: Complete:
10783 11:09:28.887418 <6>[ 9.067297] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10784 11:09:28.893484 <6>[ 9.078009] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10785 11:09:28.901076 <6>[ 9.086629] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10786 11:09:28.906871 <6>[ 9.086639] nameserver0=192.168.201.1
10787 11:09:28.909917 <6>[ 9.098806] clk: Disabling unused clocks
10788 11:09:28.913368 <6>[ 9.104471] ALSA device list:
10789 11:09:28.921040 <6>[ 9.107757] No soundcards found.
10790 11:09:28.928162 <6>[ 9.115785] Freeing unused kernel memory: 8512K
10791 11:09:28.931874 <6>[ 9.120704] Run /init as init process
10792 11:09:28.961956 <6>[ 9.149634] NET: Registered PF_INET6 protocol family
10793 11:09:28.969297 <6>[ 9.156461] Segment Routing with IPv6
10794 11:09:28.972782 <6>[ 9.160502] In-situ OAM (IOAM) with IPv6
10795 11:09:29.013649 <30>[ 9.174634] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10796 11:09:29.020587 <30>[ 9.207684] systemd[1]: Detected architecture arm64.
10797 11:09:29.021016
10798 11:09:29.027089 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10799 11:09:29.027601
10800 11:09:29.039984 <30>[ 9.227388] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10801 11:09:29.170350 <30>[ 9.354782] systemd[1]: Queued start job for default target graphical.target.
10802 11:09:29.205218 <30>[ 9.389049] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10803 11:09:29.211426 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10804 11:09:29.231602 <30>[ 9.415868] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10805 11:09:29.241758 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10806 11:09:29.260355 <30>[ 9.444187] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10807 11:09:29.270339 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10808 11:09:29.287457 <30>[ 9.471762] systemd[1]: Created slice user.slice - User and Session Slice.
10809 11:09:29.294201 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10810 11:09:29.314086 <30>[ 9.495308] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10811 11:09:29.321020 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10812 11:09:29.342336 <30>[ 9.523489] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10813 11:09:29.348908 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10814 11:09:29.377027 <30>[ 9.551490] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10815 11:09:29.386973 <30>[ 9.571321] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10816 11:09:29.393226 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10817 11:09:29.410817 <30>[ 9.595339] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10818 11:09:29.417262 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10819 11:09:29.434712 <30>[ 9.619367] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10820 11:09:29.444635 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10821 11:09:29.459956 <30>[ 9.647842] systemd[1]: Reached target paths.target - Path Units.
10822 11:09:29.470881 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10823 11:09:29.488234 <30>[ 9.671730] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10824 11:09:29.493792 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10825 11:09:29.508136 <30>[ 9.695306] systemd[1]: Reached target slices.target - Slice Units.
10826 11:09:29.517888 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10827 11:09:29.532048 <30>[ 9.719798] systemd[1]: Reached target swap.target - Swaps.
10828 11:09:29.538778 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10829 11:09:29.559318 <30>[ 9.743825] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10830 11:09:29.569411 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10831 11:09:29.588413 <30>[ 9.772259] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10832 11:09:29.597792 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10833 11:09:29.616390 <30>[ 9.800771] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10834 11:09:29.626427 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10835 11:09:29.643499 <30>[ 9.828012] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10836 11:09:29.653499 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10837 11:09:29.671686 <30>[ 9.855953] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10838 11:09:29.678542 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10839 11:09:29.695348 <30>[ 9.880064] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10840 11:09:29.705535 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10841 11:09:29.724115 <30>[ 9.908695] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10842 11:09:29.734431 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10843 11:09:29.751418 <30>[ 9.935798] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10844 11:09:29.761345 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10845 11:09:29.803147 <30>[ 9.987320] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10846 11:09:29.809658 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10847 11:09:29.831847 <30>[ 10.016206] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10848 11:09:29.838046 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10849 11:09:29.863652 <30>[ 10.048240] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10850 11:09:29.870681 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10851 11:09:29.898760 <30>[ 10.075772] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10852 11:09:29.947459 <30>[ 10.131763] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10853 11:09:29.957748 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10854 11:09:29.980802 <30>[ 10.164957] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10855 11:09:29.987373 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10856 11:09:30.012774 <30>[ 10.197063] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10857 11:09:30.026055 Starting [0;1;39mmodpr<6>[ 10.208130] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10858 11:09:30.029378 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10859 11:09:30.071393 <30>[ 10.255637] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10860 11:09:30.078018 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10861 11:09:30.100464 <30>[ 10.284573] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10862 11:09:30.109882 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10863 11:09:30.132949 <30>[ 10.317258] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10864 11:09:30.139551 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10865 11:09:30.191427 <30>[ 10.375650] systemd[1]: Starting systemd-journald.service - Journal Service...
10866 11:09:30.197689 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10867 11:09:30.217961 <30>[ 10.402428] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10868 11:09:30.224436 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10869 11:09:30.250807 <30>[ 10.430912] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10870 11:09:30.257021 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10871 11:09:30.278487 <30>[ 10.462764] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10872 11:09:30.288315 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10873 11:09:30.312576 <30>[ 10.496650] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10874 11:09:30.318852 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10875 11:09:30.349625 <30>[ 10.533526] systemd[1]: Started systemd-journald.service - Journal Service.
10876 11:09:30.355737 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10877 11:09:30.380152 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10878 11:09:30.400587 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10879 11:09:30.419615 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10880 11:09:30.441171 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10881 11:09:30.463201 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10882 11:09:30.481742 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10883 11:09:30.501972 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10884 11:09:30.523297 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10885 11:09:30.544081 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10886 11:09:30.565793 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10887 11:09:30.584941 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10888 11:09:30.605952 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10889 11:09:30.612663 See 'systemctl status systemd-remount-fs.service' for details.
10890 11:09:30.622270 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10891 11:09:30.641983 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10892 11:09:30.703865 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10893 11:09:30.728190 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10894 11:09:30.749599 <46>[ 10.934059] systemd-journald[194]: Received client request to flush runtime journal.
10895 11:09:30.755822 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10896 11:09:30.778722 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10897 11:09:30.799185 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10898 11:09:30.830247 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10899 11:09:30.848585 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10900 11:09:30.867832 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10901 11:09:30.888925 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10902 11:09:30.907946 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10903 11:09:30.963956 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10904 11:09:30.986679 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10905 11:09:31.006871 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10906 11:09:31.027494 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10907 11:09:31.083255 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10908 11:09:31.108684 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10909 11:09:31.131312 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10910 11:09:31.178047 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10911 11:09:31.207046 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10912 11:09:31.227387 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10913 11:09:31.273855 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10914 11:09:31.298645 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10915 11:09:31.335589 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10916 11:09:31.457481 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10917 11:09:31.475273 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10918 11:09:31.491184 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10919 11:09:31.511958 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10920 11:09:31.530954 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10921 11:09:31.552328 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bu<6>[ 11.738886] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10922 11:09:31.562735 s System Message<6>[ 11.739580] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10923 11:09:31.573065 <6>[ 11.747085] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10924 11:09:31.582755 <6>[ 11.747103] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10925 11:09:31.583245 Bus Socket.
10926 11:09:31.589218 <3>[ 11.757534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 11:09:31.598947 <6>[ 11.771440] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10928 11:09:31.606246 <3>[ 11.774239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10929 11:09:31.615648 <6>[ 11.783279] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10930 11:09:31.622153 <3>[ 11.791251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 11:09:31.629281 <3>[ 11.799711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10932 11:09:31.639114 <4>[ 11.807554] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10933 11:09:31.649279 <3>[ 11.815514] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 11:09:31.655891 <6>[ 11.824077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10935 11:09:31.662416 <3>[ 11.832712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 11:09:31.672660 <6>[ 11.840681] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10937 11:09:31.679370 <3>[ 11.848700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10938 11:09:31.685410 <6>[ 11.851918] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10939 11:09:31.691965 <6>[ 11.857711] mc: Linux media interface: v0.10
10940 11:09:31.699199 <6>[ 11.857786] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10941 11:09:31.709343 <3>[ 11.864880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10942 11:09:31.715624 <6>[ 11.870472] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10943 11:09:31.722172 <6>[ 11.870492] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10944 11:09:31.729448 <6>[ 11.870496] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10945 11:09:31.739383 <6>[ 11.870500] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10946 11:09:31.746796 <6>[ 11.877102] remoteproc remoteproc0: scp is available
10947 11:09:31.752785 <4>[ 11.885295] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10948 11:09:31.760599 <4>[ 11.885295] Fallback method does not support PEC.
10949 11:09:31.766547 <3>[ 11.889391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10950 11:09:31.773400 <6>[ 11.891209] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10951 11:09:31.781886 <6>[ 11.891216] pci_bus 0000:00: root bus resource [bus 00-ff]
10952 11:09:31.786604 <6>[ 11.891220] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10953 11:09:31.796920 <6>[ 11.891223] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10954 11:09:31.803314 <6>[ 11.891252] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10955 11:09:31.810129 <6>[ 11.891267] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10956 11:09:31.816765 <6>[ 11.891336] pci 0000:00:00.0: supports D1 D2
10957 11:09:31.823668 <6>[ 11.891338] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10958 11:09:31.831322 <3>[ 11.892083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10959 11:09:31.840263 <3>[ 11.892100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10960 11:09:31.846512 <3>[ 11.892108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10961 11:09:31.853074 <6>[ 11.892747] remoteproc remoteproc0: powering up scp
10962 11:09:31.859865 <3>[ 11.894034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 11:09:31.866326 <3>[ 11.894218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10964 11:09:31.876605 <3>[ 11.894331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10965 11:09:31.883264 <3>[ 11.894515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10966 11:09:31.893429 <3>[ 11.894662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10967 11:09:31.900689 <6>[ 11.894708] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10968 11:09:31.906908 <6>[ 11.896273] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10969 11:09:31.913941 <6>[ 11.896471] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10970 11:09:31.920070 <6>[ 11.896493] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10971 11:09:31.927664 <6>[ 11.896508] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10972 11:09:31.934236 <6>[ 11.896622] pci 0000:01:00.0: supports D1 D2
10973 11:09:31.941477 <6>[ 11.896624] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10974 11:09:31.948050 <4>[ 11.897583] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10975 11:09:31.955243 <3>[ 11.899783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 11:09:31.964571 <4>[ 11.899804] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10977 11:09:31.972725 <6>[ 11.924065] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10978 11:09:31.978141 <3>[ 11.924268] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 11:09:31.987838 <6>[ 11.933105] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10980 11:09:31.994223 <6>[ 11.933127] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10981 11:09:31.997684 <6>[ 11.939388] videodev: Linux video capture interface: v2.00
10982 11:09:32.008210 <3>[ 11.950922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 11:09:32.014962 <6>[ 11.955240] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10984 11:09:32.024734 <6>[ 11.976934] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10985 11:09:32.034081 <6>[ 11.980049] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10986 11:09:32.044124 <6>[ 11.990306] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10987 11:09:32.051056 <6>[ 11.996207] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10988 11:09:32.057591 <6>[ 11.996222] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10989 11:09:32.067934 <6>[ 11.996235] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10990 11:09:32.071148 <6>[ 11.996247] pci 0000:00:00.0: PCI bridge to [bus 01]
10991 11:09:32.081093 <6>[ 11.996253] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10992 11:09:32.088389 <6>[ 11.996419] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10993 11:09:32.094147 <6>[ 12.008053] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10994 11:09:32.100658 <6>[ 12.008804] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10995 11:09:32.104558 <6>[ 12.061313] Bluetooth: Core ver 2.22
10996 11:09:32.114262 <3>[ 12.064987] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 11:09:32.121096 <6>[ 12.069219] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10998 11:09:32.127091 <6>[ 12.069908] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10999 11:09:32.140749 <6>[ 12.070998] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11000 11:09:32.143846 <6>[ 12.071113] usbcore: registered new interface driver uvcvideo
11001 11:09:32.153801 <6>[ 12.072919] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11002 11:09:32.160885 <6>[ 12.072931] remoteproc remoteproc0: remote processor scp is now up
11003 11:09:32.167232 <6>[ 12.072931] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11004 11:09:32.173940 <6>[ 12.077277] NET: Registered PF_BLUETOOTH protocol family
11005 11:09:32.180394 <6>[ 12.100741] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11006 11:09:32.187132 <3>[ 12.101173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 11:09:32.193342 <6>[ 12.107227] Bluetooth: HCI device and connection manager initialized
11008 11:09:32.203870 <6>[ 12.115840] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11009 11:09:32.210310 <5>[ 12.116177] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11010 11:09:32.220033 <3>[ 12.120768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 11:09:32.223468 <6>[ 12.122199] Bluetooth: HCI socket layer initialized
11012 11:09:32.234340 <6>[ 12.129497] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11013 11:09:32.240168 <5>[ 12.131230] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11014 11:09:32.246882 <5>[ 12.131740] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11015 11:09:32.257187 <4>[ 12.131831] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11016 11:09:32.263322 <6>[ 12.131839] cfg80211: failed to load regulatory.db
11017 11:09:32.266794 <6>[ 12.133539] Bluetooth: L2CAP socket layer initialized
11018 11:09:32.273196 <6>[ 12.133555] Bluetooth: SCO socket layer initialized
11019 11:09:32.280468 <3>[ 12.147205] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 11:09:32.287436 <6>[ 12.201319] usbcore: registered new interface driver btusb
11021 11:09:32.296721 <4>[ 12.202669] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11022 11:09:32.302996 <3>[ 12.202690] Bluetooth: hci0: Failed to load firmware file (-2)
11023 11:09:32.310214 <3>[ 12.202695] Bluetooth: hci0: Failed to set up firmware (-2)
11024 11:09:32.319733 <4>[ 12.202699] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11025 11:09:32.326346 <6>[ 12.227897] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11026 11:09:32.333609 <6>[ 12.520627] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11027 11:09:32.339864 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11028 11:09:32.358813 <6>[ 12.547161] mt7921e 0000:01:00.0: ASIC revision: 79610010
11029 11:09:32.407011 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11030 11:09:32.426495 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11031 11:09:32.442912 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11032 11:09:32.466083 <6>[ 12.650605] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11033 11:09:32.468864 <6>[ 12.650605]
11034 11:09:32.485422 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11035 11:09:32.495937 <3>[ 12.680723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11036 11:09:32.508102 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11037 11:09:32.535989 <3>[ 12.720917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11038 11:09:32.546292 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11039 11:09:32.570734 <3>[ 12.755655] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 11:09:32.589601 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11041 11:09:32.601731 <3>[ 12.786606] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11042 11:09:32.615364 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11043 11:09:32.632721 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11044 11:09:32.648578 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11045 11:09:32.667936 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11046 11:09:32.735538 <6>[ 12.919800] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11047 11:09:32.745061 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11048 11:09:32.770275 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11049 11:09:32.793622 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11050 11:09:32.814267 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11051 11:09:32.869277 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11052 11:09:32.924250 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11053 11:09:32.944391 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11054 11:09:32.959541 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11055 11:09:32.979475 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11056 11:09:33.036340 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11057 11:09:33.062348 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11058 11:09:33.085038 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11059 11:09:33.128001 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11060 11:09:33.172031
11061 11:09:33.175424 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11062 11:09:33.175850
11063 11:09:33.178635 debian-bookworm-arm64 login: root (automatic login)
11064 11:09:33.179055
11065 11:09:33.191368 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11066 11:09:33.191877
11067 11:09:33.198204 The programs included with the Debian GNU/Linux system are free software;
11068 11:09:33.205267 the exact distribution terms for each program are described in the
11069 11:09:33.208461 individual files in /usr/share/doc/*/copyright.
11070 11:09:33.208881
11071 11:09:33.214952 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11072 11:09:33.217794 permitted by applicable law.
11073 11:09:33.219239 Matched prompt #10: / #
11075 11:09:33.220450 Setting prompt string to ['/ #']
11076 11:09:33.220953 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11078 11:09:33.221988 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11079 11:09:33.222441 start: 2.2.6 expect-shell-connection (timeout 00:02:45) [common]
11080 11:09:33.222773 Setting prompt string to ['/ #']
11081 11:09:33.223104 Forcing a shell prompt, looking for ['/ #']
11082 11:09:33.223446 Sending line: ''
11084 11:09:33.274559 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11085 11:09:33.274943 Waiting using forced prompt support (timeout 00:02:30)
11086 11:09:33.280594 / #
11087 11:09:33.281580 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11088 11:09:33.282104 start: 2.2.7 export-device-env (timeout 00:02:45) [common]
11089 11:09:33.282577 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11090 11:09:33.283011 end: 2.2 depthcharge-retry (duration 00:02:15) [common]
11091 11:09:33.283457 end: 2 depthcharge-action (duration 00:02:15) [common]
11092 11:09:33.283972 start: 3 lava-test-retry (timeout 00:05:00) [common]
11093 11:09:33.284462 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11094 11:09:33.284833 Using namespace: common
11095 11:09:33.285207 Sending line: '#'
11097 11:09:33.386777 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11098 11:09:33.393030 / # #
11099 11:09:33.393890 Using /lava-14786855
11100 11:09:33.394409 Sending line: 'export SHELL=/bin/sh'
11102 11:09:33.501562 / # export SHELL=/bin/sh
11103 11:09:33.502170 Sending line: '. /lava-14786855/environment'
11105 11:09:33.607610 / # . /lava-14786855/environment<6>[ 13.795206] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11106 11:09:33.608034
11107 11:09:33.649930 Sending line: '/lava-14786855/bin/lava-test-runner /lava-14786855/0'
11109 11:09:33.751556 Test shell timeout: 10s (minimum of the action and connection timeout)
11110 11:09:33.758076 / # /lava-14786855/bin/lava-test-runner /lava-14786855/0
11111 11:09:33.774603 + export TESTRUN_ID=0_cros-ec
11112 11:09:33.781262 +<8>[ 13.968627] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14786855_1.5.2.3.1>
11113 11:09:33.781963 Received signal: <STARTRUN> 0_cros-ec 14786855_1.5.2.3.1
11114 11:09:33.782348 Starting test lava.0_cros-ec (14786855_1.5.2.3.1)
11115 11:09:33.782744 Skipping test definition patterns.
11116 11:09:33.784635 cd /lava-14786855/0/tests/0_cros-ec
11117 11:09:33.785059 + cat uuid
11118 11:09:33.788191 + UUID=14786855_1.5.2.3.1
11119 11:09:33.788697 + set +x
11120 11:09:33.795158 + python3 -m cros.runners.lava_runner -v
11121 11:09:34.234622 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11122 11:09:34.241436 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11123 11:09:34.241863
11124 11:09:34.248424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11125 11:09:34.249093 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11127 11:09:34.258363 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11128 11:09:34.268179 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11129 11:09:34.268689
11130 11:09:34.274669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11131 11:09:34.275551 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11133 11:09:34.285250 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11134 11:09:34.291253 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11135 11:09:34.291657
11136 11:09:34.298013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11137 11:09:34.298653 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11139 11:09:34.304709 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11140 11:09:34.308411 Checks the standard ABI for the main Embedded Controller. ... ok
11141 11:09:34.308800
11142 11:09:34.314596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11143 11:09:34.315369 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11145 11:09:34.321101 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11146 11:09:34.328440 Checks the main Embedded controller character device. ... ok
11147 11:09:34.328928
11148 11:09:34.334446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11149 11:09:34.335078 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11151 11:09:34.340838 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11152 11:09:34.347779 Checks basic comunication with the main Embedded controller. ... ok
11153 11:09:34.348233
11154 11:09:34.350631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11155 11:09:34.351363 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11157 11:09:34.357947 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11158 11:09:34.367490 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11159 11:09:34.367900
11160 11:09:34.370898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11161 11:09:34.371635 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11163 11:09:34.380945 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11164 11:09:34.387853 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11165 11:09:34.388336
11166 11:09:34.394371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11167 11:09:34.394998 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11169 11:09:34.400821 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11170 11:09:34.407852 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11171 11:09:34.408312
11172 11:09:34.414522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11173 11:09:34.415209 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11175 11:09:34.420944 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11176 11:09:34.427277 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11177 11:09:34.427933
11178 11:09:34.434286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11179 11:09:34.435130 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11181 11:09:34.440952 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11182 11:09:34.447549 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11183 11:09:34.447705
11184 11:09:34.454272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11185 11:09:34.454630 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11187 11:09:34.460477 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11188 11:09:34.467474 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11189 11:09:34.467645
11190 11:09:34.473699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11191 11:09:34.474171 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11193 11:09:34.480388 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11194 11:09:34.490890 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11195 11:09:34.491261
11196 11:09:34.497677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11197 11:09:34.498254 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11199 11:09:34.504159 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11200 11:09:34.514176 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11201 11:09:34.514557
11202 11:09:34.520538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11203 11:09:34.521180 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11205 11:09:34.527306 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11206 11:09:34.533738 Check the cros battery ABI. ... skipped 'No BAT found'
11207 11:09:34.534126
11208 11:09:34.540350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11209 11:09:34.541074 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11211 11:09:34.546760 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11212 11:09:34.553386 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11213 11:09:34.556683
11214 11:09:34.563375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11215 11:09:34.564032 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11217 11:09:34.570728 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11218 11:09:34.576692 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11219 11:09:34.577095
11220 11:09:34.584028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11221 11:09:34.584816 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11223 11:09:34.593169 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11224 11:09:34.596932 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11225 11:09:34.597415
11226 11:09:34.604000 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8
11227 11:09:34.604596 Bad test result: ski<8
11228 11:09:34.609824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8>[ 14.796956] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14786855_1.5.2.3.1>
11229 11:09:34.610229 p>
11230 11:09:34.610675
11231 11:09:34.611313 Received signal: <ENDRUN> 0_cros-ec 14786855_1.5.2.3.1
11232 11:09:34.611752 Ending use of test pattern.
11233 11:09:34.612077 Ending test lava.0_cros-ec (14786855_1.5.2.3.1), duration 0.83
11235 11:09:34.616595 ----------------------------------------------------------------------
11236 11:09:34.620030 Ran 18 tests in 0.338s
11237 11:09:34.620438
11238 11:09:34.620757 OK (skipped=15)
11239 11:09:34.622870 + set +x
11240 11:09:34.623393 <LAVA_TEST_RUNNER EXIT>
11241 11:09:34.623944 ok: lava_test_shell seems to have completed
11242 11:09:34.624801 test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_abi: pass
test_cros_ec_chardev: pass
test_cros_ec_hello: pass
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
test_cros_ec_pwm_backlight: skip
test_cros_ec_battery_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_ec_rtc_abi: skip
11243 11:09:34.625356 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11244 11:09:34.625768 end: 3 lava-test-retry (duration 00:00:01) [common]
11245 11:09:34.626334 start: 4 finalize (timeout 00:07:21) [common]
11246 11:09:34.626996 start: 4.1 power-off (timeout 00:00:30) [common]
11247 11:09:34.627899 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11248 11:09:36.759593 >> Command sent successfully.
11249 11:09:36.762937 Returned 0 in 2 seconds
11250 11:09:36.763075 end: 4.1 power-off (duration 00:00:02) [common]
11252 11:09:36.763268 start: 4.2 read-feedback (timeout 00:07:19) [common]
11253 11:09:36.763403 Listened to connection for namespace 'common' for up to 1s
11254 11:09:37.764112 Finalising connection for namespace 'common'
11255 11:09:37.764261 Disconnecting from shell: Finalise
11256 11:09:37.764354 / #
11257 11:09:37.864634 end: 4.2 read-feedback (duration 00:00:01) [common]
11258 11:09:37.864784 end: 4 finalize (duration 00:00:03) [common]
11259 11:09:37.864923 Cleaning after the job
11260 11:09:37.865050 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/ramdisk
11261 11:09:37.870852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/kernel
11262 11:09:37.886264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/dtb
11263 11:09:37.886457 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786855/tftp-deploy-n63_asce/modules
11264 11:09:37.892097 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786855
11265 11:09:37.981076 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786855
11266 11:09:37.981316 Job finished correctly