Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 47
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 11:02:04.364474 lava-dispatcher, installed at version: 2024.05
2 11:02:04.364675 start: 0 validate
3 11:02:04.364785 Start time: 2024-07-10 11:02:04.364780+00:00 (UTC)
4 11:02:04.364916 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:04.365062 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:02:04.633855 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:04.634670 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:02:33.913911 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:02:33.914829 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:02:34.183857 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:02:34.184463 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:02:34.448996 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:02:34.449598 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:02:37.461019 validate duration: 33.10
16 11:02:37.462289 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:02:37.462816 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:02:37.463252 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:02:37.463974 Not decompressing ramdisk as can be used compressed.
20 11:02:37.464435 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:02:37.464776 saving as /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/ramdisk/initrd.cpio.gz
22 11:02:37.465096 total size: 5628169 (5 MB)
23 11:02:37.733272 progress 0 % (0 MB)
24 11:02:37.734928 progress 5 % (0 MB)
25 11:02:37.736453 progress 10 % (0 MB)
26 11:02:37.737816 progress 15 % (0 MB)
27 11:02:37.739376 progress 20 % (1 MB)
28 11:02:37.740698 progress 25 % (1 MB)
29 11:02:37.742217 progress 30 % (1 MB)
30 11:02:37.743716 progress 35 % (1 MB)
31 11:02:37.745076 progress 40 % (2 MB)
32 11:02:37.746578 progress 45 % (2 MB)
33 11:02:37.747881 progress 50 % (2 MB)
34 11:02:37.749341 progress 55 % (2 MB)
35 11:02:37.750869 progress 60 % (3 MB)
36 11:02:37.752163 progress 65 % (3 MB)
37 11:02:37.753683 progress 70 % (3 MB)
38 11:02:37.755023 progress 75 % (4 MB)
39 11:02:37.756460 progress 80 % (4 MB)
40 11:02:37.757855 progress 85 % (4 MB)
41 11:02:37.759451 progress 90 % (4 MB)
42 11:02:37.761051 progress 95 % (5 MB)
43 11:02:37.762402 progress 100 % (5 MB)
44 11:02:37.762607 5 MB downloaded in 0.30 s (18.04 MB/s)
45 11:02:37.762790 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:02:37.763008 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:02:37.763085 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:02:37.763159 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:02:37.763293 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:02:37.763353 saving as /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/kernel/Image
52 11:02:37.763422 total size: 54813184 (52 MB)
53 11:02:37.763516 No compression specified
54 11:02:37.764615 progress 0 % (0 MB)
55 11:02:37.778425 progress 5 % (2 MB)
56 11:02:37.792245 progress 10 % (5 MB)
57 11:02:37.805360 progress 15 % (7 MB)
58 11:02:37.818831 progress 20 % (10 MB)
59 11:02:37.831999 progress 25 % (13 MB)
60 11:02:37.845322 progress 30 % (15 MB)
61 11:02:37.858774 progress 35 % (18 MB)
62 11:02:37.872134 progress 40 % (20 MB)
63 11:02:37.885321 progress 45 % (23 MB)
64 11:02:37.899347 progress 50 % (26 MB)
65 11:02:37.912927 progress 55 % (28 MB)
66 11:02:37.926334 progress 60 % (31 MB)
67 11:02:37.939933 progress 65 % (34 MB)
68 11:02:37.953248 progress 70 % (36 MB)
69 11:02:37.966566 progress 75 % (39 MB)
70 11:02:37.980162 progress 80 % (41 MB)
71 11:02:37.994232 progress 85 % (44 MB)
72 11:02:38.009380 progress 90 % (47 MB)
73 11:02:38.025360 progress 95 % (49 MB)
74 11:02:38.040608 progress 100 % (52 MB)
75 11:02:38.040855 52 MB downloaded in 0.28 s (188.42 MB/s)
76 11:02:38.041001 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:02:38.041205 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:02:38.041284 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:02:38.041359 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:02:38.041487 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 11:02:38.041548 saving as /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 11:02:38.041601 total size: 57695 (0 MB)
84 11:02:38.041653 No compression specified
85 11:02:38.042821 progress 56 % (0 MB)
86 11:02:38.043146 progress 100 % (0 MB)
87 11:02:38.043366 0 MB downloaded in 0.00 s (31.21 MB/s)
88 11:02:38.043493 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:02:38.043719 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:02:38.043792 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:02:38.043865 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:02:38.043972 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:02:38.044030 saving as /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/nfsrootfs/full.rootfs.tar
95 11:02:38.044101 total size: 120894716 (115 MB)
96 11:02:38.044157 Using unxz to decompress xz
97 11:02:38.045564 progress 0 % (0 MB)
98 11:02:38.393422 progress 5 % (5 MB)
99 11:02:38.747036 progress 10 % (11 MB)
100 11:02:39.090707 progress 15 % (17 MB)
101 11:02:39.416506 progress 20 % (23 MB)
102 11:02:39.727133 progress 25 % (28 MB)
103 11:02:40.070556 progress 30 % (34 MB)
104 11:02:40.407846 progress 35 % (40 MB)
105 11:02:40.585104 progress 40 % (46 MB)
106 11:02:40.769556 progress 45 % (51 MB)
107 11:02:41.079195 progress 50 % (57 MB)
108 11:02:41.444816 progress 55 % (63 MB)
109 11:02:41.783847 progress 60 % (69 MB)
110 11:02:42.122675 progress 65 % (74 MB)
111 11:02:42.468483 progress 70 % (80 MB)
112 11:02:42.818471 progress 75 % (86 MB)
113 11:02:43.147873 progress 80 % (92 MB)
114 11:02:43.496541 progress 85 % (98 MB)
115 11:02:43.833229 progress 90 % (103 MB)
116 11:02:44.154193 progress 95 % (109 MB)
117 11:02:44.509984 progress 100 % (115 MB)
118 11:02:44.515539 115 MB downloaded in 6.47 s (17.82 MB/s)
119 11:02:44.515699 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:02:44.515911 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:02:44.515989 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:02:44.516062 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:02:44.516190 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:02:44.516250 saving as /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/modules/modules.tar
126 11:02:44.516302 total size: 8607984 (8 MB)
127 11:02:44.516355 Using unxz to decompress xz
128 11:02:44.517561 progress 0 % (0 MB)
129 11:02:44.538060 progress 5 % (0 MB)
130 11:02:44.562915 progress 10 % (0 MB)
131 11:02:44.587155 progress 15 % (1 MB)
132 11:02:44.612627 progress 20 % (1 MB)
133 11:02:44.637299 progress 25 % (2 MB)
134 11:02:44.661559 progress 30 % (2 MB)
135 11:02:44.684452 progress 35 % (2 MB)
136 11:02:44.711237 progress 40 % (3 MB)
137 11:02:44.736536 progress 45 % (3 MB)
138 11:02:44.761851 progress 50 % (4 MB)
139 11:02:44.787315 progress 55 % (4 MB)
140 11:02:44.812120 progress 60 % (4 MB)
141 11:02:44.836945 progress 65 % (5 MB)
142 11:02:44.862484 progress 70 % (5 MB)
143 11:02:44.889438 progress 75 % (6 MB)
144 11:02:44.917611 progress 80 % (6 MB)
145 11:02:44.941004 progress 85 % (7 MB)
146 11:02:44.963923 progress 90 % (7 MB)
147 11:02:44.987066 progress 95 % (7 MB)
148 11:02:45.009587 progress 100 % (8 MB)
149 11:02:45.015059 8 MB downloaded in 0.50 s (16.46 MB/s)
150 11:02:45.015234 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:02:45.015444 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:02:45.015519 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 11:02:45.015595 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 11:02:48.713592 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786791/extract-nfsrootfs-ow0ibkbq
156 11:02:48.713765 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:02:48.713853 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:02:48.714030 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf
159 11:02:48.714154 makedir: /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin
160 11:02:48.714257 makedir: /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/tests
161 11:02:48.714381 makedir: /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/results
162 11:02:48.714505 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-add-keys
163 11:02:48.714675 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-add-sources
164 11:02:48.714827 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-background-process-start
165 11:02:48.714978 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-background-process-stop
166 11:02:48.715143 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-common-functions
167 11:02:48.715282 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-echo-ipv4
168 11:02:48.715409 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-install-packages
169 11:02:48.715526 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-installed-packages
170 11:02:48.715659 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-os-build
171 11:02:48.715810 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-probe-channel
172 11:02:48.715927 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-probe-ip
173 11:02:48.716041 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-target-ip
174 11:02:48.716155 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-target-mac
175 11:02:48.716268 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-target-storage
176 11:02:48.716382 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-test-case
177 11:02:48.716495 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-test-event
178 11:02:48.716607 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-test-feedback
179 11:02:48.716718 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-test-raise
180 11:02:48.716828 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-test-reference
181 11:02:48.716939 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-test-runner
182 11:02:48.717050 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-test-set
183 11:02:48.717161 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-test-shell
184 11:02:48.717286 Updating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-add-keys (debian)
185 11:02:48.717436 Updating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-add-sources (debian)
186 11:02:48.717568 Updating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-install-packages (debian)
187 11:02:48.717702 Updating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-installed-packages (debian)
188 11:02:48.717828 Updating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/bin/lava-os-build (debian)
189 11:02:48.717938 Creating /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/environment
190 11:02:48.718033 LAVA metadata
191 11:02:48.718120 - LAVA_JOB_ID=14786791
192 11:02:48.718179 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:02:48.718282 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 11:02:48.718354 skipped lava-vland-overlay
195 11:02:48.718423 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:02:48.718523 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 11:02:48.718580 skipped lava-multinode-overlay
198 11:02:48.718648 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:02:48.718745 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 11:02:48.718811 Loading test definitions
201 11:02:48.718903 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 11:02:48.718968 Using /lava-14786791 at stage 0
203 11:02:48.719257 uuid=14786791_1.6.2.3.1 testdef=None
204 11:02:48.719346 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:02:48.719421 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 11:02:48.719939 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:02:48.720272 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 11:02:48.720968 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:02:48.721205 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 11:02:48.721747 runner path: /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/0/tests/0_timesync-off test_uuid 14786791_1.6.2.3.1
213 11:02:48.721897 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:02:48.722158 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 11:02:48.722224 Using /lava-14786791 at stage 0
217 11:02:48.722313 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:02:48.722387 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/0/tests/1_kselftest-alsa'
219 11:02:52.456798 Running '/usr/bin/git checkout kernelci.org
220 11:02:52.607410 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:02:52.607791 uuid=14786791_1.6.2.3.5 testdef=None
222 11:02:52.607902 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 11:02:52.608164 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 11:02:52.608796 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:02:52.608990 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 11:02:52.609934 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:02:52.610197 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 11:02:52.611032 runner path: /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/0/tests/1_kselftest-alsa test_uuid 14786791_1.6.2.3.5
232 11:02:52.611109 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 11:02:52.611164 BRANCH='cip'
234 11:02:52.611215 SKIPFILE='/dev/null'
235 11:02:52.611265 SKIP_INSTALL='True'
236 11:02:52.611312 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:02:52.611362 TST_CASENAME=''
238 11:02:52.611408 TST_CMDFILES='alsa'
239 11:02:52.611551 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:02:52.611725 Creating lava-test-runner.conf files
242 11:02:52.611778 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786791/lava-overlay-mekly1sf/lava-14786791/0 for stage 0
243 11:02:52.611858 - 0_timesync-off
244 11:02:52.611927 - 1_kselftest-alsa
245 11:02:52.612010 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 11:02:52.612083 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 11:02:59.861765 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:02:59.861894 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 11:02:59.861976 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:02:59.862092 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:02:59.862167 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 11:03:00.008113 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:03:00.008289 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 11:03:00.008361 extracting modules file /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786791/extract-nfsrootfs-ow0ibkbq
255 11:03:00.243880 extracting modules file /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786791/extract-overlay-ramdisk-8lnll5jo/ramdisk
256 11:03:00.471960 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:03:00.472097 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 11:03:00.472181 [common] Applying overlay to NFS
259 11:03:00.472242 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786791/compress-overlay-r7xj3j0_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786791/extract-nfsrootfs-ow0ibkbq
260 11:03:01.399807 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:03:01.399966 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 11:03:01.400085 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:03:01.400190 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 11:03:01.400288 Building ramdisk /var/lib/lava/dispatcher/tmp/14786791/extract-overlay-ramdisk-8lnll5jo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786791/extract-overlay-ramdisk-8lnll5jo/ramdisk
265 11:03:01.688691 >> 129845 blocks
266 11:03:03.800655 rename /var/lib/lava/dispatcher/tmp/14786791/extract-overlay-ramdisk-8lnll5jo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/ramdisk/ramdisk.cpio.gz
267 11:03:03.800817 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:03:03.800906 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 11:03:03.800983 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 11:03:03.801059 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/kernel/Image']
271 11:03:18.462352 Returned 0 in 14 seconds
272 11:03:18.462517 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/kernel/image.itb
273 11:03:18.814118 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:03:18.814249 output: Created: Wed Jul 10 12:03:18 2024
275 11:03:18.814357 output: Image 0 (kernel-1)
276 11:03:18.814465 output: Description:
277 11:03:18.814537 output: Created: Wed Jul 10 12:03:18 2024
278 11:03:18.814602 output: Type: Kernel Image
279 11:03:18.814666 output: Compression: lzma compressed
280 11:03:18.814771 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
281 11:03:18.814849 output: Architecture: AArch64
282 11:03:18.814926 output: OS: Linux
283 11:03:18.815002 output: Load Address: 0x00000000
284 11:03:18.815079 output: Entry Point: 0x00000000
285 11:03:18.815154 output: Hash algo: crc32
286 11:03:18.815261 output: Hash value: 9bb85fb9
287 11:03:18.815365 output: Image 1 (fdt-1)
288 11:03:18.815478 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 11:03:18.815575 output: Created: Wed Jul 10 12:03:18 2024
290 11:03:18.815664 output: Type: Flat Device Tree
291 11:03:18.815742 output: Compression: uncompressed
292 11:03:18.815817 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 11:03:18.815922 output: Architecture: AArch64
294 11:03:18.815998 output: Hash algo: crc32
295 11:03:18.816074 output: Hash value: a9713552
296 11:03:18.816184 output: Image 2 (ramdisk-1)
297 11:03:18.816260 output: Description: unavailable
298 11:03:18.816372 output: Created: Wed Jul 10 12:03:18 2024
299 11:03:18.816466 output: Type: RAMDisk Image
300 11:03:18.816542 output: Compression: uncompressed
301 11:03:18.816632 output: Data Size: 18708500 Bytes = 18270.02 KiB = 17.84 MiB
302 11:03:18.816736 output: Architecture: AArch64
303 11:03:18.816813 output: OS: Linux
304 11:03:18.816886 output: Load Address: unavailable
305 11:03:18.816963 output: Entry Point: unavailable
306 11:03:18.817037 output: Hash algo: crc32
307 11:03:18.817127 output: Hash value: 2dd00fd6
308 11:03:18.817214 output: Default Configuration: 'conf-1'
309 11:03:18.817289 output: Configuration 0 (conf-1)
310 11:03:18.817362 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 11:03:18.817452 output: Kernel: kernel-1
312 11:03:18.817540 output: Init Ramdisk: ramdisk-1
313 11:03:18.817630 output: FDT: fdt-1
314 11:03:18.817716 output: Loadables: kernel-1
315 11:03:18.817807 output:
316 11:03:18.817941 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 11:03:18.818067 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 11:03:18.818206 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 11:03:18.818340 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 11:03:18.818446 No LXC device requested
321 11:03:18.818542 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:03:18.818642 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 11:03:18.818774 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:03:18.818884 Checking files for TFTP limit of 4294967296 bytes.
325 11:03:18.819492 end: 1 tftp-deploy (duration 00:00:41) [common]
326 11:03:18.819605 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:03:18.819712 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:03:18.819847 substitutions:
329 11:03:18.819945 - {DTB}: 14786791/tftp-deploy-i61yb_1y/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 11:03:18.820042 - {INITRD}: 14786791/tftp-deploy-i61yb_1y/ramdisk/ramdisk.cpio.gz
331 11:03:18.820155 - {KERNEL}: 14786791/tftp-deploy-i61yb_1y/kernel/Image
332 11:03:18.820234 - {LAVA_MAC}: None
333 11:03:18.820313 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786791/extract-nfsrootfs-ow0ibkbq
334 11:03:18.820420 - {NFS_SERVER_IP}: 192.168.201.1
335 11:03:18.820543 - {PRESEED_CONFIG}: None
336 11:03:18.820674 - {PRESEED_LOCAL}: None
337 11:03:18.820752 - {RAMDISK}: 14786791/tftp-deploy-i61yb_1y/ramdisk/ramdisk.cpio.gz
338 11:03:18.820857 - {ROOT_PART}: None
339 11:03:18.820932 - {ROOT}: None
340 11:03:18.821011 - {SERVER_IP}: 192.168.201.1
341 11:03:18.821087 - {TEE}: None
342 11:03:18.821163 Parsed boot commands:
343 11:03:18.821240 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:03:18.821444 Parsed boot commands: tftpboot 192.168.201.1 14786791/tftp-deploy-i61yb_1y/kernel/image.itb 14786791/tftp-deploy-i61yb_1y/kernel/cmdline
345 11:03:18.821550 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:03:18.821650 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:03:18.821769 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:03:18.821873 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:03:18.821954 Not connected, no need to disconnect.
350 11:03:18.822071 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:03:18.822170 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:03:18.822252 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-4'
353 11:03:18.825592 Setting prompt string to ['lava-test: # ']
354 11:03:18.825990 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:03:18.826139 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:03:18.826259 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:03:18.826369 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:03:18.826679 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4', '--port=1', '--command=reboot']
359 11:03:27.970993 >> Command sent successfully.
360 11:03:27.974357 Returned 0 in 9 seconds
361 11:03:27.974502 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:03:27.974700 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:03:27.974785 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:03:27.974854 Setting prompt string to 'Starting depthcharge on Juniper...'
366 11:03:27.974911 Changing prompt to 'Starting depthcharge on Juniper...'
367 11:03:27.974968 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
368 11:03:27.975297 [Enter `^Ec?' for help]
369 11:03:33.818549 [DL] 00000000 00000000 010701
370 11:03:33.823767
371 11:03:33.823846
372 11:03:33.823905 F0: 102B 0000
373 11:03:33.823965
374 11:03:33.824016 F3: 1006 0033 [0200]
375 11:03:33.826798
376 11:03:33.826873 F3: 4001 00E0 [0200]
377 11:03:33.826932
378 11:03:33.826985 F3: 0000 0000
379 11:03:33.827037
380 11:03:33.830796 V0: 0000 0000 [0001]
381 11:03:33.830897
382 11:03:33.830988 00: 1027 0002
383 11:03:33.831115
384 11:03:33.833766 01: 0000 0000
385 11:03:33.833857
386 11:03:33.833937 BP: 0C00 0251 [0000]
387 11:03:33.834044
388 11:03:33.837289 G0: 1182 0000
389 11:03:33.837384
390 11:03:33.837464 EC: 0004 0000 [0001]
391 11:03:33.837543
392 11:03:33.840596 S7: 0000 0000 [0000]
393 11:03:33.840688
394 11:03:33.843833 CC: 0000 0000 [0001]
395 11:03:33.843929
396 11:03:33.844011 T0: 0000 00DB [000F]
397 11:03:33.844097
398 11:03:33.844175 Jump to BL
399 11:03:33.844255
400 11:03:33.879469
401 11:03:33.879589
402 11:03:33.889815 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
403 11:03:33.893016 ARM64: Exception handlers installed.
404 11:03:33.893111 ARM64: Testing exception
405 11:03:33.896373 ARM64: Done test exception
406 11:03:33.900355 WDT: Last reset was cold boot
407 11:03:33.903352 SPI0(PAD0) initialized at 992727 Hz
408 11:03:33.906870 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
409 11:03:33.906984 Manufacturer: ef
410 11:03:33.913125 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
411 11:03:33.926130 Probing TPM: . done!
412 11:03:33.926231 TPM ready after 0 ms
413 11:03:33.933207 Connected to device vid:did:rid of 1ae0:0028:00
414 11:03:33.943625 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
415 11:03:33.973822 Initialized TPM device CR50 revision 0
416 11:03:33.986479 tlcl_send_startup: Startup return code is 0
417 11:03:33.986616 TPM: setup succeeded
418 11:03:33.995301 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
419 11:03:33.998460 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
420 11:03:34.001915 in-header: 03 19 00 00 08 00 00 00
421 11:03:34.005345 in-data: a2 e0 47 00 13 00 00 00
422 11:03:34.009086 Chrome EC: UHEPI supported
423 11:03:34.015541 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
424 11:03:34.018611 in-header: 03 a1 00 00 08 00 00 00
425 11:03:34.022140 in-data: 84 60 60 10 00 00 00 00
426 11:03:34.022227 Phase 1
427 11:03:34.025403 FMAP: area GBB found @ 3f5000 (12032 bytes)
428 11:03:34.031548 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
429 11:03:34.038416 VB2:vb2_check_recovery() Recovery was requested manually
430 11:03:34.041668 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
431 11:03:34.048281 Recovery requested (1009000e)
432 11:03:34.056805 tlcl_extend: response is 0
433 11:03:34.061951 tlcl_extend: response is 0
434 11:03:34.087020
435 11:03:34.087155
436 11:03:34.093934 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
437 11:03:34.097448 ARM64: Exception handlers installed.
438 11:03:34.100726 ARM64: Testing exception
439 11:03:34.104060 ARM64: Done test exception
440 11:03:34.119796 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x9a6d, sec=0x2007
441 11:03:34.125811 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
442 11:03:34.129263 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
443 11:03:34.137763 [RTC]rtc_get_frequency_meter,134: input=0xf, output=823
444 11:03:34.144688 [RTC]rtc_get_frequency_meter,134: input=0x7, output=697
445 11:03:34.151304 [RTC]rtc_get_frequency_meter,134: input=0xb, output=760
446 11:03:34.158256 [RTC]rtc_get_frequency_meter,134: input=0xd, output=792
447 11:03:34.165198 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x9a6d
448 11:03:34.168474 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
449 11:03:34.171745 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
450 11:03:34.174881 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
451 11:03:34.181841 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
452 11:03:34.185184 in-header: 03 19 00 00 08 00 00 00
453 11:03:34.185262 in-data: a2 e0 47 00 13 00 00 00
454 11:03:34.188064 Chrome EC: UHEPI supported
455 11:03:34.195317 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
456 11:03:34.198170 in-header: 03 a1 00 00 08 00 00 00
457 11:03:34.201674 in-data: 84 60 60 10 00 00 00 00
458 11:03:34.204716 Skip loading cached calibration data
459 11:03:34.211381 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
460 11:03:34.214641 in-header: 03 a1 00 00 08 00 00 00
461 11:03:34.217887 in-data: 84 60 60 10 00 00 00 00
462 11:03:34.224570 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
463 11:03:34.228477 in-header: 03 a1 00 00 08 00 00 00
464 11:03:34.231396 in-data: 84 60 60 10 00 00 00 00
465 11:03:34.234480 ADC[3]: Raw value=214183 ID=1
466 11:03:34.234579 Manufacturer: ef
467 11:03:34.241187 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
468 11:03:34.245253 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
469 11:03:34.247972 CBFS @ 21000 size 3d4000
470 11:03:34.254775 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
471 11:03:34.257912 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
472 11:03:34.261099 CBFS: Found @ offset 3c700 size 44
473 11:03:34.264131 DRAM-K: Full Calibration
474 11:03:34.267900 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
475 11:03:34.271265 CBFS @ 21000 size 3d4000
476 11:03:34.274274 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
477 11:03:34.277477 CBFS: Locating 'fallback/dram'
478 11:03:34.280909 CBFS: Found @ offset 24b00 size 12268
479 11:03:34.309716 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
480 11:03:34.312775 ddr_geometry: 1, config: 0x0
481 11:03:34.315943 header.status = 0x0
482 11:03:34.319342 header.magic = 0x44524d4b (expected: 0x44524d4b)
483 11:03:34.322594 header.version = 0x5 (expected: 0x5)
484 11:03:34.325885 header.size = 0x8f0 (expected: 0x8f0)
485 11:03:34.325961 header.config = 0x0
486 11:03:34.329421 header.flags = 0x0
487 11:03:34.332953 header.checksum = 0x0
488 11:03:34.339357 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
489 11:03:34.342605 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
490 11:03:34.348978 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
491 11:03:34.349094 ddr_geometry:1
492 11:03:34.352730 [EMI] new MDL number = 1
493 11:03:34.352806 dram_cbt_mode_extern: 0
494 11:03:34.355978 dram_cbt_mode [RK0]: 0, [RK1]: 0
495 11:03:34.362215 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
496 11:03:34.362324
497 11:03:34.362407
498 11:03:34.365822 [Bianco] ETT version 0.0.0.1
499 11:03:34.368855 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
500 11:03:34.368929
501 11:03:34.372646 vSetVcoreByFreq with vcore:762500, freq=1600
502 11:03:34.372711
503 11:03:34.375719 [DramcInit]
504 11:03:34.378859 AutoRefreshCKEOff AutoREF OFF
505 11:03:34.378928 DDRPhyPLLSetting-CKEOFF
506 11:03:34.382502 DDRPhyPLLSetting-CKEON
507 11:03:34.382565
508 11:03:34.382618 Enable WDQS
509 11:03:34.386691 [ModeRegInit_LP4] CH0 RK0
510 11:03:34.390500 Write Rank0 MR13 =0x18
511 11:03:34.390569 Write Rank0 MR12 =0x5d
512 11:03:34.393579 Write Rank0 MR1 =0x56
513 11:03:34.396668 Write Rank0 MR2 =0x1a
514 11:03:34.396747 Write Rank0 MR11 =0x0
515 11:03:34.400584 Write Rank0 MR22 =0x38
516 11:03:34.403075 Write Rank0 MR14 =0x5d
517 11:03:34.403144 Write Rank0 MR3 =0x30
518 11:03:34.406255 Write Rank0 MR13 =0x58
519 11:03:34.406322 Write Rank0 MR12 =0x5d
520 11:03:34.409745 Write Rank0 MR1 =0x56
521 11:03:34.413596 Write Rank0 MR2 =0x2d
522 11:03:34.413733 Write Rank0 MR11 =0x23
523 11:03:34.416287 Write Rank0 MR22 =0x34
524 11:03:34.416378 Write Rank0 MR14 =0x10
525 11:03:34.419884 Write Rank0 MR3 =0x30
526 11:03:34.423458 Write Rank0 MR13 =0xd8
527 11:03:34.423567 [ModeRegInit_LP4] CH0 RK1
528 11:03:34.426534 Write Rank1 MR13 =0x18
529 11:03:34.429776 Write Rank1 MR12 =0x5d
530 11:03:34.429871 Write Rank1 MR1 =0x56
531 11:03:34.432997 Write Rank1 MR2 =0x1a
532 11:03:34.433089 Write Rank1 MR11 =0x0
533 11:03:34.436361 Write Rank1 MR22 =0x38
534 11:03:34.439983 Write Rank1 MR14 =0x5d
535 11:03:34.440064 Write Rank1 MR3 =0x30
536 11:03:34.442655 Write Rank1 MR13 =0x58
537 11:03:34.446325 Write Rank1 MR12 =0x5d
538 11:03:34.446401 Write Rank1 MR1 =0x56
539 11:03:34.449336 Write Rank1 MR2 =0x2d
540 11:03:34.449433 Write Rank1 MR11 =0x23
541 11:03:34.452603 Write Rank1 MR22 =0x34
542 11:03:34.456498 Write Rank1 MR14 =0x10
543 11:03:34.456571 Write Rank1 MR3 =0x30
544 11:03:34.459476 Write Rank1 MR13 =0xd8
545 11:03:34.462664 [ModeRegInit_LP4] CH1 RK0
546 11:03:34.462759 Write Rank0 MR13 =0x18
547 11:03:34.465731 Write Rank0 MR12 =0x5d
548 11:03:34.465796 Write Rank0 MR1 =0x56
549 11:03:34.469448 Write Rank0 MR2 =0x1a
550 11:03:34.472664 Write Rank0 MR11 =0x0
551 11:03:34.472735 Write Rank0 MR22 =0x38
552 11:03:34.475764 Write Rank0 MR14 =0x5d
553 11:03:34.475830 Write Rank0 MR3 =0x30
554 11:03:34.479437 Write Rank0 MR13 =0x58
555 11:03:34.482705 Write Rank0 MR12 =0x5d
556 11:03:34.482781 Write Rank0 MR1 =0x56
557 11:03:34.485875 Write Rank0 MR2 =0x2d
558 11:03:34.488917 Write Rank0 MR11 =0x23
559 11:03:34.488986 Write Rank0 MR22 =0x34
560 11:03:34.492547 Write Rank0 MR14 =0x10
561 11:03:34.492618 Write Rank0 MR3 =0x30
562 11:03:34.495773 Write Rank0 MR13 =0xd8
563 11:03:34.498935 [ModeRegInit_LP4] CH1 RK1
564 11:03:34.499001 Write Rank1 MR13 =0x18
565 11:03:34.502358 Write Rank1 MR12 =0x5d
566 11:03:34.505179 Write Rank1 MR1 =0x56
567 11:03:34.505258 Write Rank1 MR2 =0x1a
568 11:03:34.508429 Write Rank1 MR11 =0x0
569 11:03:34.508508 Write Rank1 MR22 =0x38
570 11:03:34.511661 Write Rank1 MR14 =0x5d
571 11:03:34.515418 Write Rank1 MR3 =0x30
572 11:03:34.515517 Write Rank1 MR13 =0x58
573 11:03:34.518341 Write Rank1 MR12 =0x5d
574 11:03:34.522129 Write Rank1 MR1 =0x56
575 11:03:34.522241 Write Rank1 MR2 =0x2d
576 11:03:34.524855 Write Rank1 MR11 =0x23
577 11:03:34.524944 Write Rank1 MR22 =0x34
578 11:03:34.528507 Write Rank1 MR14 =0x10
579 11:03:34.533912 Write Rank1 MR3 =0x30
580 11:03:34.534020 Write Rank1 MR13 =0xd8
581 11:03:34.535768 match AC timing 3
582 11:03:34.545584 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
583 11:03:34.545685 [MiockJmeterHQA]
584 11:03:34.548430 vSetVcoreByFreq with vcore:762500, freq=1600
585 11:03:34.656158
586 11:03:34.656267 MIOCK jitter meter ch=0
587 11:03:34.656331
588 11:03:34.658898 1T = (103-19) = 84 dly cells
589 11:03:34.665608 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 744/100 ps
590 11:03:34.669479 vSetVcoreByFreq with vcore:725000, freq=1200
591 11:03:34.769601
592 11:03:34.769726 MIOCK jitter meter ch=0
593 11:03:34.769809
594 11:03:34.773059 1T = (97-19) = 78 dly cells
595 11:03:34.779467 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
596 11:03:34.782491 vSetVcoreByFreq with vcore:725000, freq=800
597 11:03:34.882679
598 11:03:34.882791 MIOCK jitter meter ch=0
599 11:03:34.882852
600 11:03:34.885915 1T = (97-19) = 78 dly cells
601 11:03:34.892403 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
602 11:03:34.895621 vSetVcoreByFreq with vcore:762500, freq=1600
603 11:03:34.899302 vSetVcoreByFreq with vcore:762500, freq=1600
604 11:03:34.899385
605 11:03:34.899443 K DRVP
606 11:03:34.902264 1. OCD DRVP=0 CALOUT=0
607 11:03:34.905407 1. OCD DRVP=1 CALOUT=0
608 11:03:34.905488 1. OCD DRVP=2 CALOUT=0
609 11:03:34.908875 1. OCD DRVP=3 CALOUT=0
610 11:03:34.912492 1. OCD DRVP=4 CALOUT=0
611 11:03:34.912574 1. OCD DRVP=5 CALOUT=0
612 11:03:34.915694 1. OCD DRVP=6 CALOUT=0
613 11:03:34.915770 1. OCD DRVP=7 CALOUT=0
614 11:03:34.918910 1. OCD DRVP=8 CALOUT=1
615 11:03:34.918987
616 11:03:34.921904 1. OCD DRVP calibration OK! DRVP=8
617 11:03:34.922016
618 11:03:34.922095
619 11:03:34.922148
620 11:03:34.922200 K ODTN
621 11:03:34.925627 3. OCD ODTN=0 ,CALOUT=1
622 11:03:34.928729 3. OCD ODTN=1 ,CALOUT=1
623 11:03:34.928809 3. OCD ODTN=2 ,CALOUT=1
624 11:03:34.932023 3. OCD ODTN=3 ,CALOUT=1
625 11:03:34.935375 3. OCD ODTN=4 ,CALOUT=1
626 11:03:34.935455 3. OCD ODTN=5 ,CALOUT=1
627 11:03:34.939010 3. OCD ODTN=6 ,CALOUT=1
628 11:03:34.941873 3. OCD ODTN=7 ,CALOUT=0
629 11:03:34.941986
630 11:03:34.945276 3. OCD ODTN calibration OK! ODTN=7
631 11:03:34.945357
632 11:03:34.948523 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
633 11:03:34.951769 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
634 11:03:34.958828 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
635 11:03:34.958925
636 11:03:34.958985 K DRVP
637 11:03:34.959037 1. OCD DRVP=0 CALOUT=0
638 11:03:34.961691 1. OCD DRVP=1 CALOUT=0
639 11:03:34.964807 1. OCD DRVP=2 CALOUT=0
640 11:03:34.964886 1. OCD DRVP=3 CALOUT=0
641 11:03:34.968018 1. OCD DRVP=4 CALOUT=0
642 11:03:34.971698 1. OCD DRVP=5 CALOUT=0
643 11:03:34.971779 1. OCD DRVP=6 CALOUT=0
644 11:03:34.974949 1. OCD DRVP=7 CALOUT=0
645 11:03:34.978249 1. OCD DRVP=8 CALOUT=0
646 11:03:34.978329 1. OCD DRVP=9 CALOUT=1
647 11:03:34.978388
648 11:03:34.981426 1. OCD DRVP calibration OK! DRVP=9
649 11:03:34.981503
650 11:03:34.981560
651 11:03:34.981612
652 11:03:34.984547 K ODTN
653 11:03:34.984621 3. OCD ODTN=0 ,CALOUT=1
654 11:03:34.988504 3. OCD ODTN=1 ,CALOUT=1
655 11:03:34.988583 3. OCD ODTN=2 ,CALOUT=1
656 11:03:34.991709 3. OCD ODTN=3 ,CALOUT=1
657 11:03:34.995022 3. OCD ODTN=4 ,CALOUT=1
658 11:03:34.995102 3. OCD ODTN=5 ,CALOUT=1
659 11:03:34.997958 3. OCD ODTN=6 ,CALOUT=1
660 11:03:35.001353 3. OCD ODTN=7 ,CALOUT=1
661 11:03:35.001430 3. OCD ODTN=8 ,CALOUT=1
662 11:03:35.005154 3. OCD ODTN=9 ,CALOUT=1
663 11:03:35.008341 3. OCD ODTN=10 ,CALOUT=1
664 11:03:35.008422 3. OCD ODTN=11 ,CALOUT=1
665 11:03:35.011379 3. OCD ODTN=12 ,CALOUT=1
666 11:03:35.014751 3. OCD ODTN=13 ,CALOUT=0
667 11:03:35.014832
668 11:03:35.018477 3. OCD ODTN calibration OK! ODTN=13
669 11:03:35.018602
670 11:03:35.021085 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=13
671 11:03:35.024226 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13
672 11:03:35.031394 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13 (After Adjust)
673 11:03:35.031484
674 11:03:35.031545 [DramcInit]
675 11:03:35.034431 AutoRefreshCKEOff AutoREF OFF
676 11:03:35.034507 DDRPhyPLLSetting-CKEOFF
677 11:03:35.037883 DDRPhyPLLSetting-CKEON
678 11:03:35.037969
679 11:03:35.041145 Enable WDQS
680 11:03:35.041224 ==
681 11:03:35.044417 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
682 11:03:35.047441 fsp= 1, odt_onoff= 1, Byte mode= 0
683 11:03:35.047518 ==
684 11:03:35.051226 [Duty_Offset_Calibration]
685 11:03:35.051304
686 11:03:35.054482 ===========================
687 11:03:35.054563 B0:2 B1:2 CA:1
688 11:03:35.076318 ==
689 11:03:35.079385 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
690 11:03:35.082650 fsp= 1, odt_onoff= 1, Byte mode= 0
691 11:03:35.082731 ==
692 11:03:35.085956 [Duty_Offset_Calibration]
693 11:03:35.086055
694 11:03:35.089531 ===========================
695 11:03:35.089607 B0:0 B1:0 CA:-1
696 11:03:35.121763 [ModeRegInit_LP4] CH0 RK0
697 11:03:35.124828 Write Rank0 MR13 =0x18
698 11:03:35.124908 Write Rank0 MR12 =0x5d
699 11:03:35.128075 Write Rank0 MR1 =0x56
700 11:03:35.131263 Write Rank0 MR2 =0x1a
701 11:03:35.131341 Write Rank0 MR11 =0x0
702 11:03:35.135205 Write Rank0 MR22 =0x38
703 11:03:35.138303 Write Rank0 MR14 =0x5d
704 11:03:35.138383 Write Rank0 MR3 =0x30
705 11:03:35.141238 Write Rank0 MR13 =0x58
706 11:03:35.141337 Write Rank0 MR12 =0x5d
707 11:03:35.144805 Write Rank0 MR1 =0x56
708 11:03:35.148323 Write Rank0 MR2 =0x2d
709 11:03:35.148410 Write Rank0 MR11 =0x23
710 11:03:35.151362 Write Rank0 MR22 =0x34
711 11:03:35.151438 Write Rank0 MR14 =0x10
712 11:03:35.154668 Write Rank0 MR3 =0x30
713 11:03:35.158200 Write Rank0 MR13 =0xd8
714 11:03:35.158277 [ModeRegInit_LP4] CH0 RK1
715 11:03:35.161608 Write Rank1 MR13 =0x18
716 11:03:35.164569 Write Rank1 MR12 =0x5d
717 11:03:35.164648 Write Rank1 MR1 =0x56
718 11:03:35.167978 Write Rank1 MR2 =0x1a
719 11:03:35.168056 Write Rank1 MR11 =0x0
720 11:03:35.171436 Write Rank1 MR22 =0x38
721 11:03:35.174427 Write Rank1 MR14 =0x5d
722 11:03:35.174504 Write Rank1 MR3 =0x30
723 11:03:35.178096 Write Rank1 MR13 =0x58
724 11:03:35.178176 Write Rank1 MR12 =0x5d
725 11:03:35.181288 Write Rank1 MR1 =0x56
726 11:03:35.184522 Write Rank1 MR2 =0x2d
727 11:03:35.184599 Write Rank1 MR11 =0x23
728 11:03:35.187750 Write Rank1 MR22 =0x34
729 11:03:35.190846 Write Rank1 MR14 =0x10
730 11:03:35.190941 Write Rank1 MR3 =0x30
731 11:03:35.194714 Write Rank1 MR13 =0xd8
732 11:03:35.194794 [ModeRegInit_LP4] CH1 RK0
733 11:03:35.197911 Write Rank0 MR13 =0x18
734 11:03:35.200879 Write Rank0 MR12 =0x5d
735 11:03:35.200956 Write Rank0 MR1 =0x56
736 11:03:35.204577 Write Rank0 MR2 =0x1a
737 11:03:35.207799 Write Rank0 MR11 =0x0
738 11:03:35.207878 Write Rank0 MR22 =0x38
739 11:03:35.210993 Write Rank0 MR14 =0x5d
740 11:03:35.211069 Write Rank0 MR3 =0x30
741 11:03:35.214182 Write Rank0 MR13 =0x58
742 11:03:35.217615 Write Rank0 MR12 =0x5d
743 11:03:35.217693 Write Rank0 MR1 =0x56
744 11:03:35.221158 Write Rank0 MR2 =0x2d
745 11:03:35.221233 Write Rank0 MR11 =0x23
746 11:03:35.224432 Write Rank0 MR22 =0x34
747 11:03:35.227643 Write Rank0 MR14 =0x10
748 11:03:35.227721 Write Rank0 MR3 =0x30
749 11:03:35.230737 Write Rank0 MR13 =0xd8
750 11:03:35.234598 [ModeRegInit_LP4] CH1 RK1
751 11:03:35.234679 Write Rank1 MR13 =0x18
752 11:03:35.237652 Write Rank1 MR12 =0x5d
753 11:03:35.237731 Write Rank1 MR1 =0x56
754 11:03:35.240784 Write Rank1 MR2 =0x1a
755 11:03:35.244094 Write Rank1 MR11 =0x0
756 11:03:35.244177 Write Rank1 MR22 =0x38
757 11:03:35.247695 Write Rank1 MR14 =0x5d
758 11:03:35.247783 Write Rank1 MR3 =0x30
759 11:03:35.250887 Write Rank1 MR13 =0x58
760 11:03:35.254021 Write Rank1 MR12 =0x5d
761 11:03:35.254116 Write Rank1 MR1 =0x56
762 11:03:35.257756 Write Rank1 MR2 =0x2d
763 11:03:35.260893 Write Rank1 MR11 =0x23
764 11:03:35.260972 Write Rank1 MR22 =0x34
765 11:03:35.263884 Write Rank1 MR14 =0x10
766 11:03:35.263961 Write Rank1 MR3 =0x30
767 11:03:35.267589 Write Rank1 MR13 =0xd8
768 11:03:35.270469 match AC timing 3
769 11:03:35.277401 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
770 11:03:35.280517 DramC Write-DBI off
771 11:03:35.283678 DramC Read-DBI off
772 11:03:35.283759 Write Rank0 MR13 =0x59
773 11:03:35.283822 ==
774 11:03:35.290669 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
775 11:03:35.293484 fsp= 1, odt_onoff= 1, Byte mode= 0
776 11:03:35.293567 ==
777 11:03:35.297096 === u2Vref_new: 0x56 --> 0x2d
778 11:03:35.300156 === u2Vref_new: 0x58 --> 0x38
779 11:03:35.300235 === u2Vref_new: 0x5a --> 0x39
780 11:03:35.303594 === u2Vref_new: 0x5c --> 0x3c
781 11:03:35.307482 === u2Vref_new: 0x5e --> 0x3d
782 11:03:35.310408 === u2Vref_new: 0x60 --> 0xa0
783 11:03:35.313646 [CA 0] Center 34 (6~63) winsize 58
784 11:03:35.317482 [CA 1] Center 35 (8~63) winsize 56
785 11:03:35.320749 [CA 2] Center 30 (1~59) winsize 59
786 11:03:35.323828 [CA 3] Center 24 (-3~52) winsize 56
787 11:03:35.327274 [CA 4] Center 26 (-2~54) winsize 57
788 11:03:35.330314 [CA 5] Center 31 (2~60) winsize 59
789 11:03:35.330394
790 11:03:35.333553 [CATrainingPosCal] consider 1 rank data
791 11:03:35.336911 u2DelayCellTimex100 = 744/100 ps
792 11:03:35.340172 CA0 delay=34 (6~63),Diff = 10 PI (13 cell)
793 11:03:35.343844 CA1 delay=35 (8~63),Diff = 11 PI (14 cell)
794 11:03:35.346818 CA2 delay=30 (1~59),Diff = 6 PI (7 cell)
795 11:03:35.353372 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
796 11:03:35.356888 CA4 delay=26 (-2~54),Diff = 2 PI (2 cell)
797 11:03:35.360292 CA5 delay=31 (2~60),Diff = 7 PI (9 cell)
798 11:03:35.360371
799 11:03:35.363393 CA PerBit enable=1, Macro0, CA PI delay=24
800 11:03:35.367021 === u2Vref_new: 0x5e --> 0x3d
801 11:03:35.367100
802 11:03:35.367163 Vref(ca) range 1: 30
803 11:03:35.367224
804 11:03:35.370111 CS Dly= 7 (38-0-32)
805 11:03:35.373576 Write Rank0 MR13 =0xd8
806 11:03:35.373658 Write Rank0 MR13 =0xd8
807 11:03:35.376751 Write Rank0 MR12 =0x5e
808 11:03:35.376828 Write Rank1 MR13 =0x59
809 11:03:35.380413 ==
810 11:03:35.383404 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
811 11:03:35.386677 fsp= 1, odt_onoff= 1, Byte mode= 0
812 11:03:35.386756 ==
813 11:03:35.389970 === u2Vref_new: 0x56 --> 0x2d
814 11:03:35.392966 === u2Vref_new: 0x58 --> 0x38
815 11:03:35.396631 === u2Vref_new: 0x5a --> 0x39
816 11:03:35.399906 === u2Vref_new: 0x5c --> 0x3c
817 11:03:35.403362 === u2Vref_new: 0x5e --> 0x3d
818 11:03:35.406368 === u2Vref_new: 0x60 --> 0xa0
819 11:03:35.409394 [CA 0] Center 35 (8~63) winsize 56
820 11:03:35.412946 [CA 1] Center 35 (8~63) winsize 56
821 11:03:35.416435 [CA 2] Center 31 (2~60) winsize 59
822 11:03:35.419295 [CA 3] Center 26 (-2~54) winsize 57
823 11:03:35.419379 [CA 4] Center 26 (-2~54) winsize 57
824 11:03:35.422460 [CA 5] Center 32 (3~61) winsize 59
825 11:03:35.422540
826 11:03:35.429344 [CATrainingPosCal] consider 2 rank data
827 11:03:35.429448 u2DelayCellTimex100 = 744/100 ps
828 11:03:35.435801 CA0 delay=35 (8~63),Diff = 10 PI (13 cell)
829 11:03:35.439332 CA1 delay=35 (8~63),Diff = 10 PI (13 cell)
830 11:03:35.442639 CA2 delay=30 (2~59),Diff = 5 PI (6 cell)
831 11:03:35.445806 CA3 delay=25 (-2~52),Diff = 0 PI (0 cell)
832 11:03:35.448891 CA4 delay=26 (-2~54),Diff = 1 PI (1 cell)
833 11:03:35.452857 CA5 delay=31 (3~60),Diff = 6 PI (7 cell)
834 11:03:35.452980
835 11:03:35.456087 CA PerBit enable=1, Macro0, CA PI delay=25
836 11:03:35.458957 === u2Vref_new: 0x5e --> 0x3d
837 11:03:35.459035
838 11:03:35.462725 Vref(ca) range 1: 30
839 11:03:35.462822
840 11:03:35.462882 CS Dly= 7 (38-0-32)
841 11:03:35.465915 Write Rank1 MR13 =0xd8
842 11:03:35.468996 Write Rank1 MR13 =0xd8
843 11:03:35.469073 Write Rank1 MR12 =0x5e
844 11:03:35.472259 [RankSwap] Rank num 2, (Multi 1), Rank 0
845 11:03:35.475523 Write Rank0 MR2 =0xad
846 11:03:35.475600 [Write Leveling]
847 11:03:35.478680 delay byte0 byte1 byte2 byte3
848 11:03:35.478754
849 11:03:35.481882 10 0 0
850 11:03:35.481960 11 0 0
851 11:03:35.485324 12 0 0
852 11:03:35.485415 13 0 0
853 11:03:35.488828 14 0 0
854 11:03:35.488905 15 0 0
855 11:03:35.488965 16 0 0
856 11:03:35.491986 17 0 0
857 11:03:35.492064 18 0 0
858 11:03:35.495142 19 0 0
859 11:03:35.495219 20 0 0
860 11:03:35.498677 21 0 0
861 11:03:35.498754 22 0 0
862 11:03:35.498812 23 0 ff
863 11:03:35.501773 24 0 ff
864 11:03:35.501848 25 0 ff
865 11:03:35.505082 26 0 ff
866 11:03:35.505159 27 0 ff
867 11:03:35.508749 28 0 ff
868 11:03:35.508827 29 0 ff
869 11:03:35.508886 30 0 ff
870 11:03:35.511728 31 0 ff
871 11:03:35.511814 32 ff ff
872 11:03:35.515053 33 ff ff
873 11:03:35.515148 34 ff ff
874 11:03:35.518512 35 ff ff
875 11:03:35.518593 36 ff ff
876 11:03:35.521434 37 ff ff
877 11:03:35.521511 38 ff ff
878 11:03:35.525020 pass bytecount = 0xff (0xff: all bytes pass)
879 11:03:35.525095
880 11:03:35.528480 DQS0 dly: 32
881 11:03:35.528557 DQS1 dly: 23
882 11:03:35.531650 Write Rank0 MR2 =0x2d
883 11:03:35.535308 [RankSwap] Rank num 2, (Multi 1), Rank 0
884 11:03:35.535388 Write Rank0 MR1 =0xd6
885 11:03:35.538303 [Gating]
886 11:03:35.538380 ==
887 11:03:35.541390 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
888 11:03:35.544571 fsp= 1, odt_onoff= 1, Byte mode= 0
889 11:03:35.544651 ==
890 11:03:35.551134 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
891 11:03:35.554916 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
892 11:03:35.558357 3 1 8 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
893 11:03:35.564765 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
894 11:03:35.567754 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
895 11:03:35.571161 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
896 11:03:35.578141 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
897 11:03:35.581292 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
898 11:03:35.584505 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
899 11:03:35.590831 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
900 11:03:35.594407 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
901 11:03:35.597659 3 2 12 |504 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
902 11:03:35.600908 3 2 16 |3d3d 807 |(11 11)(11 11) |(1 1)(0 0)| 0
903 11:03:35.607955 3 2 20 |3d3d 606 |(11 11)(11 11) |(1 1)(0 0)| 0
904 11:03:35.610966 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
905 11:03:35.614237 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
906 11:03:35.620596 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
907 11:03:35.624130 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
908 11:03:35.626935 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
909 11:03:35.633538 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
910 11:03:35.637731 3 3 16 |1a1a 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
911 11:03:35.640703 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
912 11:03:35.647241 [Byte 0] Lead/lag Transition tap number (1)
913 11:03:35.650627 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
914 11:03:35.653476 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
915 11:03:35.657036 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
916 11:03:35.663553 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
917 11:03:35.666819 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
918 11:03:35.670559 3 4 12 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
919 11:03:35.677200 3 4 16 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
920 11:03:35.680186 3 4 20 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
921 11:03:35.683192 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
922 11:03:35.689806 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
923 11:03:35.692975 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
924 11:03:35.696858 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 11:03:35.703407 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 11:03:35.706377 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 11:03:35.710377 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 11:03:35.716452 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 11:03:35.719783 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 11:03:35.722826 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 11:03:35.729307 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 11:03:35.733091 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 11:03:35.736665 [Byte 0] Lead/lag falling Transition (3, 6, 4)
934 11:03:35.739346 [Byte 1] Lead/lag falling Transition (3, 6, 4)
935 11:03:35.745941 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
936 11:03:35.749578 [Byte 0] Lead/lag Transition tap number (2)
937 11:03:35.752624 3 6 12 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
938 11:03:35.756036 [Byte 1] Lead/lag Transition tap number (3)
939 11:03:35.762795 3 6 16 |3030 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
940 11:03:35.765780 3 6 20 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
941 11:03:35.769337 [Byte 0]First pass (3, 6, 20)
942 11:03:35.772252 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
943 11:03:35.775514 [Byte 1]First pass (3, 6, 24)
944 11:03:35.779227 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
945 11:03:35.782388 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
946 11:03:35.785715 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 11:03:35.792113 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 11:03:35.795396 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 11:03:35.798858 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 11:03:35.801821 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 11:03:35.808744 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 11:03:35.811995 All bytes gating window > 1UI, Early break!
953 11:03:35.812103
954 11:03:35.815069 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 8)
955 11:03:35.815144
956 11:03:35.818540 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
957 11:03:35.818627
958 11:03:35.818685
959 11:03:35.818737
960 11:03:35.821633 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
961 11:03:35.821724
962 11:03:35.828703 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
963 11:03:35.828809
964 11:03:35.828904
965 11:03:35.828985 Write Rank0 MR1 =0x56
966 11:03:35.829066
967 11:03:35.831532 best RODT dly(2T, 0.5T) = (2, 3)
968 11:03:35.831613
969 11:03:35.835085 best RODT dly(2T, 0.5T) = (2, 3)
970 11:03:35.835178 ==
971 11:03:35.841561 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
972 11:03:35.844670 fsp= 1, odt_onoff= 1, Byte mode= 0
973 11:03:35.844771 ==
974 11:03:35.847912 Start DQ dly to find pass range UseTestEngine =0
975 11:03:35.851237 x-axis: bit #, y-axis: DQ dly (-127~63)
976 11:03:35.854724 RX Vref Scan = 0
977 11:03:35.857703 -26, [0] xxxxxxxx xxxxxxxx [MSB]
978 11:03:35.857807 -25, [0] xxxxxxxx xxxxxxxx [MSB]
979 11:03:35.861281 -24, [0] xxxxxxxx xxxxxxxx [MSB]
980 11:03:35.864580 -23, [0] xxxxxxxx xxxxxxxx [MSB]
981 11:03:35.867583 -22, [0] xxxxxxxx xxxxxxxx [MSB]
982 11:03:35.871407 -21, [0] xxxxxxxx xxxxxxxx [MSB]
983 11:03:35.874876 -20, [0] xxxxxxxx xxxxxxxx [MSB]
984 11:03:35.877524 -19, [0] xxxxxxxx xxxxxxxx [MSB]
985 11:03:35.881123 -18, [0] xxxxxxxx xxxxxxxx [MSB]
986 11:03:35.884605 -17, [0] xxxxxxxx xxxxxxxx [MSB]
987 11:03:35.884711 -16, [0] xxxxxxxx xxxxxxxx [MSB]
988 11:03:35.887342 -15, [0] xxxxxxxx xxxxxxxx [MSB]
989 11:03:35.891201 -14, [0] xxxxxxxx xxxxxxxx [MSB]
990 11:03:35.894494 -13, [0] xxxxxxxx xxxxxxxx [MSB]
991 11:03:35.897783 -12, [0] xxxxxxxx xxxxxxxx [MSB]
992 11:03:35.900830 -11, [0] xxxxxxxx xxxxxxxx [MSB]
993 11:03:35.904238 -10, [0] xxxxxxxx xxxxxxxx [MSB]
994 11:03:35.907133 -9, [0] xxxxxxxx xxxxxxxx [MSB]
995 11:03:35.910574 -8, [0] xxxxxxxx xxxxxxxx [MSB]
996 11:03:35.910683 -7, [0] xxxxxxxx xxxxxxxx [MSB]
997 11:03:35.913902 -6, [0] xxxxxxxx xxxxxxxx [MSB]
998 11:03:35.917075 -5, [0] xxxxxxxx xxxxxxxx [MSB]
999 11:03:35.920352 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1000 11:03:35.923651 -3, [0] xxxoxxxx xxxxxxxx [MSB]
1001 11:03:35.926881 -2, [0] xxxoxxxx oxxxxxxx [MSB]
1002 11:03:35.930279 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1003 11:03:35.930367 0, [0] xxxoxoxx ooxooxxx [MSB]
1004 11:03:35.933613 1, [0] xxxoxoox ooxooxxx [MSB]
1005 11:03:35.936698 2, [0] xxxoxoox ooxoooxx [MSB]
1006 11:03:35.940023 3, [0] xxxoxooo ooxoooox [MSB]
1007 11:03:35.944233 4, [0] xxxoxooo ooxoooox [MSB]
1008 11:03:35.946790 5, [0] xoxooooo ooxooooo [MSB]
1009 11:03:35.946875 6, [0] xooooooo ooxooooo [MSB]
1010 11:03:35.949812 7, [0] oooooooo ooxooooo [MSB]
1011 11:03:35.953646 32, [0] oooxoooo oooooooo [MSB]
1012 11:03:35.957015 33, [0] oooxoooo oooooooo [MSB]
1013 11:03:35.959772 34, [0] oooxoxoo xooooooo [MSB]
1014 11:03:35.963426 35, [0] oooxoxoo xxoooooo [MSB]
1015 11:03:35.966822 36, [0] oooxoxoo xxoxxooo [MSB]
1016 11:03:35.966907 37, [0] oooxoxxo xxoxxxxo [MSB]
1017 11:03:35.970136 38, [0] oooxoxxx xxoxxxxo [MSB]
1018 11:03:35.973224 39, [0] xxoxoxxx xxoxxxxo [MSB]
1019 11:03:35.976981 40, [0] xxoxoxxx xxoxxxxo [MSB]
1020 11:03:35.979775 41, [0] xxxxxxxx xxoxxxxx [MSB]
1021 11:03:35.982984 42, [0] xxxxxxxx xxoxxxxx [MSB]
1022 11:03:35.986508 43, [0] xxxxxxxx xxxxxxxx [MSB]
1023 11:03:35.989727 iDelay=43, Bit 0, Center 22 (7 ~ 38) 32
1024 11:03:35.993432 iDelay=43, Bit 1, Center 21 (5 ~ 38) 34
1025 11:03:35.996451 iDelay=43, Bit 2, Center 23 (6 ~ 40) 35
1026 11:03:35.999981 iDelay=43, Bit 3, Center 14 (-3 ~ 31) 35
1027 11:03:36.003287 iDelay=43, Bit 4, Center 22 (5 ~ 40) 36
1028 11:03:36.006260 iDelay=43, Bit 5, Center 16 (0 ~ 33) 34
1029 11:03:36.009485 iDelay=43, Bit 6, Center 18 (1 ~ 36) 36
1030 11:03:36.012720 iDelay=43, Bit 7, Center 20 (3 ~ 37) 35
1031 11:03:36.016720 iDelay=43, Bit 8, Center 15 (-2 ~ 33) 36
1032 11:03:36.019558 iDelay=43, Bit 9, Center 17 (0 ~ 34) 35
1033 11:03:36.022811 iDelay=43, Bit 10, Center 25 (8 ~ 42) 35
1034 11:03:36.029244 iDelay=43, Bit 11, Center 17 (-1 ~ 35) 37
1035 11:03:36.033092 iDelay=43, Bit 12, Center 17 (0 ~ 35) 36
1036 11:03:36.036299 iDelay=43, Bit 13, Center 19 (2 ~ 36) 35
1037 11:03:36.039372 iDelay=43, Bit 14, Center 19 (3 ~ 36) 34
1038 11:03:36.042825 iDelay=43, Bit 15, Center 22 (5 ~ 40) 36
1039 11:03:36.042912 ==
1040 11:03:36.049172 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1041 11:03:36.049258 fsp= 1, odt_onoff= 1, Byte mode= 0
1042 11:03:36.052904 ==
1043 11:03:36.052988 DQS Delay:
1044 11:03:36.053049 DQS0 = 0, DQS1 = 0
1045 11:03:36.055936 DQM Delay:
1046 11:03:36.056014 DQM0 = 19, DQM1 = 18
1047 11:03:36.059211 DQ Delay:
1048 11:03:36.062464 DQ0 =22, DQ1 =21, DQ2 =23, DQ3 =14
1049 11:03:36.062537 DQ4 =22, DQ5 =16, DQ6 =18, DQ7 =20
1050 11:03:36.065868 DQ8 =15, DQ9 =17, DQ10 =25, DQ11 =17
1051 11:03:36.072710 DQ12 =17, DQ13 =19, DQ14 =19, DQ15 =22
1052 11:03:36.072825
1053 11:03:36.072914
1054 11:03:36.072997 DramC Write-DBI off
1055 11:03:36.073080 ==
1056 11:03:36.079013 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1057 11:03:36.082017 fsp= 1, odt_onoff= 1, Byte mode= 0
1058 11:03:36.082098 ==
1059 11:03:36.085578 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1060 11:03:36.085661
1061 11:03:36.089048 Begin, DQ Scan Range 919~1175
1062 11:03:36.089129
1063 11:03:36.089188
1064 11:03:36.092469 TX Vref Scan disable
1065 11:03:36.095254 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1066 11:03:36.099023 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1067 11:03:36.102220 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1068 11:03:36.105484 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1069 11:03:36.108844 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1070 11:03:36.112322 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1071 11:03:36.115467 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1072 11:03:36.118779 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1073 11:03:36.121830 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1074 11:03:36.125436 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1075 11:03:36.128710 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1076 11:03:36.132107 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1077 11:03:36.138568 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1078 11:03:36.141915 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1079 11:03:36.144943 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1080 11:03:36.148777 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1081 11:03:36.151562 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1082 11:03:36.155655 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1083 11:03:36.158809 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1084 11:03:36.161831 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1085 11:03:36.165032 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1086 11:03:36.168108 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1087 11:03:36.171333 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1088 11:03:36.174994 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1089 11:03:36.177902 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1090 11:03:36.181500 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1091 11:03:36.187879 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1092 11:03:36.191103 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1093 11:03:36.194741 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1094 11:03:36.197776 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1095 11:03:36.201548 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1096 11:03:36.204680 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1097 11:03:36.207723 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1098 11:03:36.211512 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1099 11:03:36.214320 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1100 11:03:36.217851 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1101 11:03:36.221405 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1102 11:03:36.224603 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1103 11:03:36.227455 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1104 11:03:36.231316 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1105 11:03:36.234844 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1106 11:03:36.241392 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1107 11:03:36.244614 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1108 11:03:36.247472 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1109 11:03:36.250441 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1110 11:03:36.254103 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1111 11:03:36.257378 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1112 11:03:36.260498 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1113 11:03:36.264116 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1114 11:03:36.267480 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1115 11:03:36.270211 969 |3 6 9|[0] xxxxxxxx ooxoooxx [MSB]
1116 11:03:36.273654 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1117 11:03:36.276985 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1118 11:03:36.280039 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1119 11:03:36.283420 973 |3 6 13|[0] xxxxxxxx ooxooooo [MSB]
1120 11:03:36.286995 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1121 11:03:36.290305 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1122 11:03:36.296824 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1123 11:03:36.300516 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1124 11:03:36.303652 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1125 11:03:36.306573 979 |3 6 19|[0] xxxooooo oooooooo [MSB]
1126 11:03:36.310165 980 |3 6 20|[0] xoxooooo oooooooo [MSB]
1127 11:03:36.313280 981 |3 6 21|[0] xooooooo oooooooo [MSB]
1128 11:03:36.316573 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1129 11:03:36.320039 988 |3 6 28|[0] oooooooo xooxoooo [MSB]
1130 11:03:36.323076 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1131 11:03:36.326366 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1132 11:03:36.329500 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1133 11:03:36.336815 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1134 11:03:36.339807 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1135 11:03:36.342735 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1136 11:03:36.346151 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1137 11:03:36.349588 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1138 11:03:36.352476 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1139 11:03:36.356303 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB]
1140 11:03:36.359559 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1141 11:03:36.362622 Byte0, DQ PI dly=988, DQM PI dly= 988
1142 11:03:36.365772 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
1143 11:03:36.365867
1144 11:03:36.372531 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
1145 11:03:36.372635
1146 11:03:36.375700 Byte1, DQ PI dly=979, DQM PI dly= 979
1147 11:03:36.378979 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1148 11:03:36.379072
1149 11:03:36.382172 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1150 11:03:36.385946
1151 11:03:36.386067 ==
1152 11:03:36.389338 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1153 11:03:36.392114 fsp= 1, odt_onoff= 1, Byte mode= 0
1154 11:03:36.392198 ==
1155 11:03:36.395195 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1156 11:03:36.398511
1157 11:03:36.398591 Begin, DQ Scan Range 955~1019
1158 11:03:36.402170 Write Rank0 MR14 =0x0
1159 11:03:36.410147
1160 11:03:36.410242 CH=0, VrefRange= 0, VrefLevel = 0
1161 11:03:36.416870 TX Bit0 (984~997) 14 990, Bit8 (970~982) 13 976,
1162 11:03:36.420560 TX Bit1 (983~995) 13 989, Bit9 (973~983) 11 978,
1163 11:03:36.427427 TX Bit2 (984~996) 13 990, Bit10 (976~988) 13 982,
1164 11:03:36.430204 TX Bit3 (977~990) 14 983, Bit11 (972~982) 11 977,
1165 11:03:36.433669 TX Bit4 (983~992) 10 987, Bit12 (972~983) 12 977,
1166 11:03:36.440254 TX Bit5 (980~991) 12 985, Bit13 (973~983) 11 978,
1167 11:03:36.443951 TX Bit6 (981~993) 13 987, Bit14 (974~987) 14 980,
1168 11:03:36.447148 TX Bit7 (983~993) 11 988, Bit15 (975~989) 15 982,
1169 11:03:36.449899
1170 11:03:36.450028 Write Rank0 MR14 =0x2
1171 11:03:36.459208
1172 11:03:36.459308 CH=0, VrefRange= 0, VrefLevel = 2
1173 11:03:36.465472 TX Bit0 (984~998) 15 991, Bit8 (969~982) 14 975,
1174 11:03:36.468755 TX Bit1 (982~996) 15 989, Bit9 (972~983) 12 977,
1175 11:03:36.475335 TX Bit2 (983~996) 14 989, Bit10 (976~989) 14 982,
1176 11:03:36.478667 TX Bit3 (977~991) 15 984, Bit11 (971~982) 12 976,
1177 11:03:36.482262 TX Bit4 (983~993) 11 988, Bit12 (972~984) 13 978,
1178 11:03:36.488704 TX Bit5 (979~991) 13 985, Bit13 (973~983) 11 978,
1179 11:03:36.491997 TX Bit6 (980~993) 14 986, Bit14 (973~988) 16 980,
1180 11:03:36.498578 TX Bit7 (983~993) 11 988, Bit15 (974~990) 17 982,
1181 11:03:36.498676
1182 11:03:36.498766 Write Rank0 MR14 =0x4
1183 11:03:36.508303
1184 11:03:36.508405 CH=0, VrefRange= 0, VrefLevel = 4
1185 11:03:36.514463 TX Bit0 (983~998) 16 990, Bit8 (969~983) 15 976,
1186 11:03:36.517852 TX Bit1 (982~997) 16 989, Bit9 (971~984) 14 977,
1187 11:03:36.524368 TX Bit2 (983~998) 16 990, Bit10 (976~990) 15 983,
1188 11:03:36.527485 TX Bit3 (976~991) 16 983, Bit11 (971~983) 13 977,
1189 11:03:36.530629 TX Bit4 (982~994) 13 988, Bit12 (972~985) 14 978,
1190 11:03:36.537112 TX Bit5 (979~992) 14 985, Bit13 (972~984) 13 978,
1191 11:03:36.540609 TX Bit6 (980~994) 15 987, Bit14 (973~988) 16 980,
1192 11:03:36.547452 TX Bit7 (982~994) 13 988, Bit15 (974~990) 17 982,
1193 11:03:36.547570
1194 11:03:36.547644 Write Rank0 MR14 =0x6
1195 11:03:36.556714
1196 11:03:36.556840 CH=0, VrefRange= 0, VrefLevel = 6
1197 11:03:36.564718 TX Bit0 (983~999) 17 991, Bit8 (969~983) 15 976,
1198 11:03:36.614209 TX Bit1 (982~997) 16 989, Bit9 (971~985) 15 978,
1199 11:03:36.614917 TX Bit2 (983~999) 17 991, Bit10 (975~990) 16 982,
1200 11:03:36.615200 TX Bit3 (976~992) 17 984, Bit11 (970~983) 14 976,
1201 11:03:36.615265 TX Bit4 (982~994) 13 988, Bit12 (971~985) 15 978,
1202 11:03:36.615524 TX Bit5 (978~993) 16 985, Bit13 (972~984) 13 978,
1203 11:03:36.616319 TX Bit6 (979~995) 17 987, Bit14 (972~988) 17 980,
1204 11:03:36.616649 TX Bit7 (982~995) 14 988, Bit15 (974~991) 18 982,
1205 11:03:36.616749
1206 11:03:36.616809 Write Rank0 MR14 =0x8
1207 11:03:36.616862
1208 11:03:36.616914 CH=0, VrefRange= 0, VrefLevel = 8
1209 11:03:36.616965 TX Bit0 (983~999) 17 991, Bit8 (968~984) 17 976,
1210 11:03:36.617015 TX Bit1 (981~998) 18 989, Bit9 (970~986) 17 978,
1211 11:03:36.645287 TX Bit2 (982~999) 18 990, Bit10 (975~991) 17 983,
1212 11:03:36.645849 TX Bit3 (976~992) 17 984, Bit11 (969~984) 16 976,
1213 11:03:36.646396 TX Bit4 (981~996) 16 988, Bit12 (971~986) 16 978,
1214 11:03:36.646668 TX Bit5 (978~993) 16 985, Bit13 (972~986) 15 979,
1215 11:03:36.646911 TX Bit6 (979~996) 18 987, Bit14 (972~989) 18 980,
1216 11:03:36.646971 TX Bit7 (981~996) 16 988, Bit15 (974~991) 18 982,
1217 11:03:36.647024
1218 11:03:36.650202 Write Rank0 MR14 =0xa
1219 11:03:36.654671
1220 11:03:36.657806 CH=0, VrefRange= 0, VrefLevel = 10
1221 11:03:36.661076 TX Bit0 (983~999) 17 991, Bit8 (968~984) 17 976,
1222 11:03:36.664296 TX Bit1 (981~999) 19 990, Bit9 (970~986) 17 978,
1223 11:03:36.671139 TX Bit2 (982~999) 18 990, Bit10 (975~992) 18 983,
1224 11:03:36.673915 TX Bit3 (976~993) 18 984, Bit11 (969~984) 16 976,
1225 11:03:36.677966 TX Bit4 (981~997) 17 989, Bit12 (970~987) 18 978,
1226 11:03:36.684685 TX Bit5 (978~994) 17 986, Bit13 (970~986) 17 978,
1227 11:03:36.687439 TX Bit6 (978~997) 20 987, Bit14 (971~989) 19 980,
1228 11:03:36.690580 TX Bit7 (980~997) 18 988, Bit15 (973~992) 20 982,
1229 11:03:36.693778
1230 11:03:36.693893 Write Rank0 MR14 =0xc
1231 11:03:36.703804
1232 11:03:36.707025 CH=0, VrefRange= 0, VrefLevel = 12
1233 11:03:36.710316 TX Bit0 (983~1000) 18 991, Bit8 (968~984) 17 976,
1234 11:03:36.713441 TX Bit1 (980~999) 20 989, Bit9 (970~987) 18 978,
1235 11:03:36.720493 TX Bit2 (981~1000) 20 990, Bit10 (974~992) 19 983,
1236 11:03:36.723600 TX Bit3 (976~993) 18 984, Bit11 (968~985) 18 976,
1237 11:03:36.726585 TX Bit4 (980~998) 19 989, Bit12 (970~988) 19 979,
1238 11:03:36.733229 TX Bit5 (978~994) 17 986, Bit13 (970~987) 18 978,
1239 11:03:36.736314 TX Bit6 (978~997) 20 987, Bit14 (971~990) 20 980,
1240 11:03:36.742819 TX Bit7 (980~998) 19 989, Bit15 (974~992) 19 983,
1241 11:03:36.742946
1242 11:03:36.743082 Write Rank0 MR14 =0xe
1243 11:03:36.752926
1244 11:03:36.756144 CH=0, VrefRange= 0, VrefLevel = 14
1245 11:03:36.759340 TX Bit0 (982~1000) 19 991, Bit8 (968~985) 18 976,
1246 11:03:36.763125 TX Bit1 (981~999) 19 990, Bit9 (969~988) 20 978,
1247 11:03:36.769558 TX Bit2 (981~1000) 20 990, Bit10 (974~993) 20 983,
1248 11:03:36.772362 TX Bit3 (975~994) 20 984, Bit11 (968~986) 19 977,
1249 11:03:36.776099 TX Bit4 (980~998) 19 989, Bit12 (969~989) 21 979,
1250 11:03:36.782999 TX Bit5 (977~996) 20 986, Bit13 (970~988) 19 979,
1251 11:03:36.785911 TX Bit6 (978~997) 20 987, Bit14 (970~990) 21 980,
1252 11:03:36.792348 TX Bit7 (980~998) 19 989, Bit15 (973~993) 21 983,
1253 11:03:36.792447
1254 11:03:36.792555 Write Rank0 MR14 =0x10
1255 11:03:36.802200
1256 11:03:36.805760 CH=0, VrefRange= 0, VrefLevel = 16
1257 11:03:36.808788 TX Bit0 (982~1001) 20 991, Bit8 (967~987) 21 977,
1258 11:03:36.812327 TX Bit1 (979~1000) 22 989, Bit9 (969~988) 20 978,
1259 11:03:36.818908 TX Bit2 (981~1000) 20 990, Bit10 (974~994) 21 984,
1260 11:03:36.821902 TX Bit3 (975~994) 20 984, Bit11 (968~987) 20 977,
1261 11:03:36.825070 TX Bit4 (979~999) 21 989, Bit12 (969~989) 21 979,
1262 11:03:36.831927 TX Bit5 (977~996) 20 986, Bit13 (970~989) 20 979,
1263 11:03:36.835336 TX Bit6 (977~998) 22 987, Bit14 (970~990) 21 980,
1264 11:03:36.841939 TX Bit7 (979~999) 21 989, Bit15 (973~994) 22 983,
1265 11:03:36.842057
1266 11:03:36.842122 Write Rank0 MR14 =0x12
1267 11:03:36.851890
1268 11:03:36.855722 CH=0, VrefRange= 0, VrefLevel = 18
1269 11:03:36.858602 TX Bit0 (982~1002) 21 992, Bit8 (967~987) 21 977,
1270 11:03:36.861657 TX Bit1 (979~1000) 22 989, Bit9 (969~989) 21 979,
1271 11:03:36.868294 TX Bit2 (981~1001) 21 991, Bit10 (974~994) 21 984,
1272 11:03:36.871422 TX Bit3 (975~995) 21 985, Bit11 (968~987) 20 977,
1273 11:03:36.875245 TX Bit4 (979~999) 21 989, Bit12 (968~990) 23 979,
1274 11:03:36.881409 TX Bit5 (977~997) 21 987, Bit13 (969~989) 21 979,
1275 11:03:36.885032 TX Bit6 (977~998) 22 987, Bit14 (969~991) 23 980,
1276 11:03:36.891306 TX Bit7 (979~999) 21 989, Bit15 (973~994) 22 983,
1277 11:03:36.891397
1278 11:03:36.891456 Write Rank0 MR14 =0x14
1279 11:03:36.902015
1280 11:03:36.904856 CH=0, VrefRange= 0, VrefLevel = 20
1281 11:03:36.908642 TX Bit0 (981~1002) 22 991, Bit8 (967~988) 22 977,
1282 11:03:36.911763 TX Bit1 (979~1000) 22 989, Bit9 (968~989) 22 978,
1283 11:03:36.918085 TX Bit2 (981~1001) 21 991, Bit10 (973~995) 23 984,
1284 11:03:36.921635 TX Bit3 (975~995) 21 985, Bit11 (967~988) 22 977,
1285 11:03:36.924932 TX Bit4 (978~999) 22 988, Bit12 (968~990) 23 979,
1286 11:03:36.931257 TX Bit5 (977~998) 22 987, Bit13 (969~990) 22 979,
1287 11:03:36.934562 TX Bit6 (977~999) 23 988, Bit14 (969~991) 23 980,
1288 11:03:36.941401 TX Bit7 (979~999) 21 989, Bit15 (972~995) 24 983,
1289 11:03:36.941519
1290 11:03:36.941583 Write Rank0 MR14 =0x16
1291 11:03:36.951707
1292 11:03:36.954972 CH=0, VrefRange= 0, VrefLevel = 22
1293 11:03:36.958135 TX Bit0 (981~1003) 23 992, Bit8 (967~989) 23 978,
1294 11:03:36.961399 TX Bit1 (978~1001) 24 989, Bit9 (968~990) 23 979,
1295 11:03:36.968146 TX Bit2 (980~1002) 23 991, Bit10 (973~996) 24 984,
1296 11:03:36.971864 TX Bit3 (975~996) 22 985, Bit11 (967~989) 23 978,
1297 11:03:36.974887 TX Bit4 (978~999) 22 988, Bit12 (968~990) 23 979,
1298 11:03:36.981802 TX Bit5 (977~998) 22 987, Bit13 (969~990) 22 979,
1299 11:03:36.984836 TX Bit6 (977~999) 23 988, Bit14 (969~992) 24 980,
1300 11:03:36.990889 TX Bit7 (978~1000) 23 989, Bit15 (972~996) 25 984,
1301 11:03:36.990976
1302 11:03:36.991037 Write Rank0 MR14 =0x18
1303 11:03:37.001534
1304 11:03:37.005031 CH=0, VrefRange= 0, VrefLevel = 24
1305 11:03:37.008262 TX Bit0 (980~1002) 23 991, Bit8 (967~989) 23 978,
1306 11:03:37.011662 TX Bit1 (978~1001) 24 989, Bit9 (968~990) 23 979,
1307 11:03:37.017979 TX Bit2 (979~1002) 24 990, Bit10 (973~996) 24 984,
1308 11:03:37.021629 TX Bit3 (974~997) 24 985, Bit11 (967~989) 23 978,
1309 11:03:37.024640 TX Bit4 (978~1000) 23 989, Bit12 (968~991) 24 979,
1310 11:03:37.031001 TX Bit5 (976~998) 23 987, Bit13 (968~990) 23 979,
1311 11:03:37.034250 TX Bit6 (976~999) 24 987, Bit14 (968~992) 25 980,
1312 11:03:37.040928 TX Bit7 (978~1000) 23 989, Bit15 (972~995) 24 983,
1313 11:03:37.041026
1314 11:03:37.041109 Write Rank0 MR14 =0x1a
1315 11:03:37.051350
1316 11:03:37.055185 CH=0, VrefRange= 0, VrefLevel = 26
1317 11:03:37.058216 TX Bit0 (980~1003) 24 991, Bit8 (967~989) 23 978,
1318 11:03:37.061898 TX Bit1 (978~1002) 25 990, Bit9 (968~990) 23 979,
1319 11:03:37.068028 TX Bit2 (979~1003) 25 991, Bit10 (973~997) 25 985,
1320 11:03:37.071342 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1321 11:03:37.078234 TX Bit4 (978~1000) 23 989, Bit12 (968~991) 24 979,
1322 11:03:37.081223 TX Bit5 (976~998) 23 987, Bit13 (968~991) 24 979,
1323 11:03:37.084962 TX Bit6 (977~1000) 24 988, Bit14 (969~993) 25 981,
1324 11:03:37.090977 TX Bit7 (978~1001) 24 989, Bit15 (971~996) 26 983,
1325 11:03:37.091089
1326 11:03:37.091177 Write Rank0 MR14 =0x1c
1327 11:03:37.101980
1328 11:03:37.102123 CH=0, VrefRange= 0, VrefLevel = 28
1329 11:03:37.109028 TX Bit0 (980~1004) 25 992, Bit8 (966~989) 24 977,
1330 11:03:37.112309 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
1331 11:03:37.118393 TX Bit2 (979~1003) 25 991, Bit10 (972~997) 26 984,
1332 11:03:37.121922 TX Bit3 (973~997) 25 985, Bit11 (967~990) 24 978,
1333 11:03:37.125745 TX Bit4 (977~1001) 25 989, Bit12 (967~991) 25 979,
1334 11:03:37.132165 TX Bit5 (976~998) 23 987, Bit13 (968~991) 24 979,
1335 11:03:37.135267 TX Bit6 (976~1000) 25 988, Bit14 (968~993) 26 980,
1336 11:03:37.141564 TX Bit7 (978~1001) 24 989, Bit15 (970~996) 27 983,
1337 11:03:37.141692
1338 11:03:37.141778 Write Rank0 MR14 =0x1e
1339 11:03:37.152582
1340 11:03:37.155372 CH=0, VrefRange= 0, VrefLevel = 30
1341 11:03:37.158612 TX Bit0 (979~1004) 26 991, Bit8 (966~989) 24 977,
1342 11:03:37.162224 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1343 11:03:37.169122 TX Bit2 (979~1003) 25 991, Bit10 (973~997) 25 985,
1344 11:03:37.172257 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1345 11:03:37.178495 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1346 11:03:37.181744 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1347 11:03:37.185423 TX Bit6 (976~1000) 25 988, Bit14 (968~993) 26 980,
1348 11:03:37.191630 TX Bit7 (977~1001) 25 989, Bit15 (971~995) 25 983,
1349 11:03:37.191725
1350 11:03:37.191787 Write Rank0 MR14 =0x20
1351 11:03:37.202927
1352 11:03:37.205524 CH=0, VrefRange= 0, VrefLevel = 32
1353 11:03:37.209808 TX Bit0 (979~1004) 26 991, Bit8 (966~989) 24 977,
1354 11:03:37.212633 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1355 11:03:37.218841 TX Bit2 (979~1003) 25 991, Bit10 (973~997) 25 985,
1356 11:03:37.222165 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1357 11:03:37.225866 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1358 11:03:37.232159 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1359 11:03:37.235591 TX Bit6 (976~1000) 25 988, Bit14 (968~993) 26 980,
1360 11:03:37.242084 TX Bit7 (977~1001) 25 989, Bit15 (971~995) 25 983,
1361 11:03:37.242203
1362 11:03:37.242291 Write Rank0 MR14 =0x22
1363 11:03:37.252871
1364 11:03:37.255922 CH=0, VrefRange= 0, VrefLevel = 34
1365 11:03:37.259526 TX Bit0 (979~1004) 26 991, Bit8 (966~989) 24 977,
1366 11:03:37.262942 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1367 11:03:37.269533 TX Bit2 (979~1003) 25 991, Bit10 (973~997) 25 985,
1368 11:03:37.272698 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1369 11:03:37.275657 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1370 11:03:37.282798 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1371 11:03:37.285614 TX Bit6 (976~1000) 25 988, Bit14 (968~993) 26 980,
1372 11:03:37.292473 TX Bit7 (977~1001) 25 989, Bit15 (971~995) 25 983,
1373 11:03:37.292572
1374 11:03:37.292634 Write Rank0 MR14 =0x24
1375 11:03:37.303056
1376 11:03:37.306223 CH=0, VrefRange= 0, VrefLevel = 36
1377 11:03:37.310016 TX Bit0 (979~1004) 26 991, Bit8 (966~989) 24 977,
1378 11:03:37.312451 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1379 11:03:37.319124 TX Bit2 (979~1003) 25 991, Bit10 (973~997) 25 985,
1380 11:03:37.322374 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1381 11:03:37.326067 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1382 11:03:37.332769 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1383 11:03:37.335817 TX Bit6 (976~1000) 25 988, Bit14 (968~993) 26 980,
1384 11:03:37.342670 TX Bit7 (977~1001) 25 989, Bit15 (971~995) 25 983,
1385 11:03:37.342792
1386 11:03:37.342880
1387 11:03:37.345524 TX Vref found, early break! 370< 375
1388 11:03:37.349153 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
1389 11:03:37.352004 u1DelayCellOfst[0]=7 cells (6 PI)
1390 11:03:37.355494 u1DelayCellOfst[1]=6 cells (5 PI)
1391 11:03:37.359215 u1DelayCellOfst[2]=7 cells (6 PI)
1392 11:03:37.362406 u1DelayCellOfst[3]=0 cells (0 PI)
1393 11:03:37.365495 u1DelayCellOfst[4]=5 cells (4 PI)
1394 11:03:37.368626 u1DelayCellOfst[5]=2 cells (2 PI)
1395 11:03:37.372444 u1DelayCellOfst[6]=3 cells (3 PI)
1396 11:03:37.375686 u1DelayCellOfst[7]=5 cells (4 PI)
1397 11:03:37.378856 Byte0, DQ PI dly=985, DQM PI dly= 988
1398 11:03:37.382399 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1399 11:03:37.382479
1400 11:03:37.385117 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1401 11:03:37.385192
1402 11:03:37.388391 u1DelayCellOfst[8]=0 cells (0 PI)
1403 11:03:37.392345 u1DelayCellOfst[9]=1 cells (1 PI)
1404 11:03:37.395278 u1DelayCellOfst[10]=10 cells (8 PI)
1405 11:03:37.398732 u1DelayCellOfst[11]=1 cells (1 PI)
1406 11:03:37.401744 u1DelayCellOfst[12]=2 cells (2 PI)
1407 11:03:37.405204 u1DelayCellOfst[13]=2 cells (2 PI)
1408 11:03:37.408257 u1DelayCellOfst[14]=3 cells (3 PI)
1409 11:03:37.411504 u1DelayCellOfst[15]=7 cells (6 PI)
1410 11:03:37.414908 Byte1, DQ PI dly=977, DQM PI dly= 981
1411 11:03:37.418550 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1412 11:03:37.418631
1413 11:03:37.421683 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1414 11:03:37.424896
1415 11:03:37.424973 Write Rank0 MR14 =0x1e
1416 11:03:37.425030
1417 11:03:37.428386 Final TX Range 0 Vref 30
1418 11:03:37.428461
1419 11:03:37.434836 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1420 11:03:37.434923
1421 11:03:37.441294 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1422 11:03:37.448318 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1423 11:03:37.454701 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1424 11:03:37.458074 Write Rank0 MR3 =0xb0
1425 11:03:37.458164 DramC Write-DBI on
1426 11:03:37.458226 ==
1427 11:03:37.464411 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1428 11:03:37.467738 fsp= 1, odt_onoff= 1, Byte mode= 0
1429 11:03:37.467826 ==
1430 11:03:37.471119 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1431 11:03:37.471201
1432 11:03:37.474323 Begin, DQ Scan Range 701~765
1433 11:03:37.474403
1434 11:03:37.474463
1435 11:03:37.477515 TX Vref Scan disable
1436 11:03:37.480611 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1437 11:03:37.484571 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1438 11:03:37.487499 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1439 11:03:37.491024 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1440 11:03:37.493954 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1441 11:03:37.497117 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1442 11:03:37.500407 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1443 11:03:37.504010 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1444 11:03:37.506909 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1445 11:03:37.510100 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1446 11:03:37.513338 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1447 11:03:37.517022 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1448 11:03:37.523676 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1449 11:03:37.526372 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1450 11:03:37.530272 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1451 11:03:37.533336 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1452 11:03:37.536830 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1453 11:03:37.539858 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1454 11:03:37.543216 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1455 11:03:37.546687 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1456 11:03:37.553847 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1457 11:03:37.557160 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1458 11:03:37.560472 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1459 11:03:37.563420 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1460 11:03:37.567140 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1461 11:03:37.570573 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1462 11:03:37.573477 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1463 11:03:37.577104 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1464 11:03:37.580503 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1465 11:03:37.583323 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1466 11:03:37.586535 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1467 11:03:37.590328 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
1468 11:03:37.593484 748 |2 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
1469 11:03:37.596467 Byte0, DQ PI dly=734, DQM PI dly= 734
1470 11:03:37.603529 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
1471 11:03:37.603626
1472 11:03:37.606525 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
1473 11:03:37.606607
1474 11:03:37.609713 Byte1, DQ PI dly=723, DQM PI dly= 723
1475 11:03:37.616534 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
1476 11:03:37.616630
1477 11:03:37.619586 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
1478 11:03:37.619669
1479 11:03:37.626532 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1480 11:03:37.633233 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1481 11:03:37.639603 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1482 11:03:37.643180 Write Rank0 MR3 =0x30
1483 11:03:37.643269 DramC Write-DBI off
1484 11:03:37.643346
1485 11:03:37.646398 [DATLAT]
1486 11:03:37.649658 Freq=1600, CH0 RK0, use_rxtx_scan=0
1487 11:03:37.649741
1488 11:03:37.649816 DATLAT Default: 0xf
1489 11:03:37.652915 7, 0xFFFF, sum=0
1490 11:03:37.652995 8, 0xFFFF, sum=0
1491 11:03:37.656074 9, 0xFFFF, sum=0
1492 11:03:37.656168 10, 0xFFFF, sum=0
1493 11:03:37.659059 11, 0xFFFF, sum=0
1494 11:03:37.659140 12, 0xFFFF, sum=0
1495 11:03:37.662704 13, 0xFFFF, sum=0
1496 11:03:37.662785 14, 0x0, sum=1
1497 11:03:37.662863 15, 0x0, sum=2
1498 11:03:37.665835 16, 0x0, sum=3
1499 11:03:37.665938 17, 0x0, sum=4
1500 11:03:37.672803 pattern=2 first_step=14 total pass=5 best_step=16
1501 11:03:37.672889 ==
1502 11:03:37.676430 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1503 11:03:37.679343 fsp= 1, odt_onoff= 1, Byte mode= 0
1504 11:03:37.679424 ==
1505 11:03:37.683064 Start DQ dly to find pass range UseTestEngine =1
1506 11:03:37.686237 x-axis: bit #, y-axis: DQ dly (-127~63)
1507 11:03:37.689466 RX Vref Scan = 1
1508 11:03:37.796673
1509 11:03:37.796829 RX Vref found, early break!
1510 11:03:37.796927
1511 11:03:37.802880 Final RX Vref 11, apply to both rank0 and 1
1512 11:03:37.802974 ==
1513 11:03:37.806082 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1514 11:03:37.810193 fsp= 1, odt_onoff= 1, Byte mode= 0
1515 11:03:37.810283 ==
1516 11:03:37.810343 DQS Delay:
1517 11:03:37.813364 DQS0 = 0, DQS1 = 0
1518 11:03:37.813450 DQM Delay:
1519 11:03:37.816597 DQM0 = 19, DQM1 = 18
1520 11:03:37.816704 DQ Delay:
1521 11:03:37.819731 DQ0 =23, DQ1 =22, DQ2 =23, DQ3 =15
1522 11:03:37.823137 DQ4 =21, DQ5 =16, DQ6 =19, DQ7 =20
1523 11:03:37.826360 DQ8 =15, DQ9 =17, DQ10 =25, DQ11 =16
1524 11:03:37.829281 DQ12 =18, DQ13 =18, DQ14 =20, DQ15 =22
1525 11:03:37.829361
1526 11:03:37.829421
1527 11:03:37.829474
1528 11:03:37.833013 [DramC_TX_OE_Calibration] TA2
1529 11:03:37.836163 Original DQ_B0 (3 6) =30, OEN = 27
1530 11:03:37.839283 Original DQ_B1 (3 6) =30, OEN = 27
1531 11:03:37.843102 23, 0x0, End_B0=23 End_B1=23
1532 11:03:37.843188 24, 0x0, End_B0=24 End_B1=24
1533 11:03:37.846544 25, 0x0, End_B0=25 End_B1=25
1534 11:03:37.849561 26, 0x0, End_B0=26 End_B1=26
1535 11:03:37.852960 27, 0x0, End_B0=27 End_B1=27
1536 11:03:37.855755 28, 0x0, End_B0=28 End_B1=28
1537 11:03:37.855839 29, 0x0, End_B0=29 End_B1=29
1538 11:03:37.859594 30, 0x0, End_B0=30 End_B1=30
1539 11:03:37.862864 31, 0xFFFF, End_B0=30 End_B1=30
1540 11:03:37.869617 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1541 11:03:37.872383 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1542 11:03:37.872469
1543 11:03:37.872528
1544 11:03:37.876270 Write Rank0 MR23 =0x3f
1545 11:03:37.876349 [DQSOSC]
1546 11:03:37.885434 [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps
1547 11:03:37.892352 CH0_RK0: MR19=0x202, MR18=0xADAD, DQSOSC=459, MR23=63, INC=11, DEC=17
1548 11:03:37.892456 Write Rank0 MR23 =0x3f
1549 11:03:37.895665 [DQSOSC]
1550 11:03:37.902269 [DQSOSCAuto] RK0, (LSB)MR18= 0xafaf, (MSB)MR19= 0x202, tDQSOscB0 = 458 ps tDQSOscB1 = 458 ps
1551 11:03:37.905735 CH0 RK0: MR19=202, MR18=AFAF
1552 11:03:37.908882 [RankSwap] Rank num 2, (Multi 1), Rank 1
1553 11:03:37.911831 Write Rank0 MR2 =0xad
1554 11:03:37.911916 [Write Leveling]
1555 11:03:37.915620 delay byte0 byte1 byte2 byte3
1556 11:03:37.915702
1557 11:03:37.915781 10 0 0
1558 11:03:37.918582 11 0 0
1559 11:03:37.918663 12 0 0
1560 11:03:37.922137 13 0 0
1561 11:03:37.922242 14 0 0
1562 11:03:37.922344 15 0 0
1563 11:03:37.924948 16 0 0
1564 11:03:37.925028 17 0 0
1565 11:03:37.928811 18 0 0
1566 11:03:37.928885 19 0 0
1567 11:03:37.931635 20 0 0
1568 11:03:37.931715 21 0 0
1569 11:03:37.931808 22 0 0
1570 11:03:37.935503 23 0 ff
1571 11:03:37.935630 24 0 ff
1572 11:03:37.938662 25 0 ff
1573 11:03:37.938758 26 0 ff
1574 11:03:37.942121 27 0 ff
1575 11:03:37.942201 28 0 ff
1576 11:03:37.945099 29 0 ff
1577 11:03:37.945177 30 0 ff
1578 11:03:37.945255 31 ff ff
1579 11:03:37.948099 32 ff ff
1580 11:03:37.948177 33 ff ff
1581 11:03:37.951346 34 ff ff
1582 11:03:37.951449 35 ff ff
1583 11:03:37.955266 36 ff ff
1584 11:03:37.955367 37 ff ff
1585 11:03:37.958330 pass bytecount = 0xff (0xff: all bytes pass)
1586 11:03:37.961570
1587 11:03:37.961647 DQS0 dly: 31
1588 11:03:37.961707 DQS1 dly: 23
1589 11:03:37.965272 Write Rank0 MR2 =0x2d
1590 11:03:37.968230 [RankSwap] Rank num 2, (Multi 1), Rank 0
1591 11:03:37.971147 Write Rank1 MR1 =0xd6
1592 11:03:37.971224 [Gating]
1593 11:03:37.971282 ==
1594 11:03:37.975027 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1595 11:03:37.978415 fsp= 1, odt_onoff= 1, Byte mode= 0
1596 11:03:37.978493 ==
1597 11:03:37.984670 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1598 11:03:37.987708 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1599 11:03:37.991441 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1600 11:03:37.997521 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
1601 11:03:38.001265 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1602 11:03:38.004541 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1603 11:03:38.010871 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1604 11:03:38.014339 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1605 11:03:38.017303 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1606 11:03:38.024246 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1607 11:03:38.027325 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
1608 11:03:38.030533 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
1609 11:03:38.037082 3 2 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1610 11:03:38.040450 3 2 20 |201 2c2c |(11 11)(11 10) |(1 1)(0 0)| 0
1611 11:03:38.043662 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1612 11:03:38.050303 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1613 11:03:38.053497 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1614 11:03:38.057369 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1615 11:03:38.063609 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1616 11:03:38.066896 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1617 11:03:38.070148 3 3 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1618 11:03:38.073399 3 3 20 |707 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1619 11:03:38.079930 [Byte 1] Lead/lag falling Transition (3, 3, 20)
1620 11:03:38.083706 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1621 11:03:38.086998 [Byte 0] Lead/lag Transition tap number (1)
1622 11:03:38.093397 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1623 11:03:38.096646 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1624 11:03:38.100113 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1625 11:03:38.103549 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1626 11:03:38.110132 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1627 11:03:38.113307 3 4 16 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1628 11:03:38.116723 3 4 20 |c0c 3231 |(11 11)(11 11) |(1 1)(1 1)| 0
1629 11:03:38.123450 3 4 24 |3d3d 2f2f |(11 11)(11 11) |(1 1)(1 1)| 0
1630 11:03:38.126555 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1631 11:03:38.130172 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1632 11:03:38.136441 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1633 11:03:38.139798 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1634 11:03:38.142967 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1635 11:03:38.149920 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1636 11:03:38.153158 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1637 11:03:38.156876 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1638 11:03:38.162642 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1639 11:03:38.166441 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1640 11:03:38.169248 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1641 11:03:38.175808 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1642 11:03:38.179327 [Byte 0] Lead/lag falling Transition (3, 6, 8)
1643 11:03:38.182307 [Byte 1] Lead/lag falling Transition (3, 6, 8)
1644 11:03:38.185901 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1645 11:03:38.192225 [Byte 0] Lead/lag Transition tap number (2)
1646 11:03:38.196022 [Byte 1] Lead/lag Transition tap number (2)
1647 11:03:38.199239 3 6 16 |605 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
1648 11:03:38.202299 3 6 20 |1e1e 2c2c |(1 1)(11 11) |(0 0)(0 0)| 0
1649 11:03:38.209046 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1650 11:03:38.209160 [Byte 0]First pass (3, 6, 24)
1651 11:03:38.212305 [Byte 1]First pass (3, 6, 24)
1652 11:03:38.215564 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1653 11:03:38.222367 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1654 11:03:38.225156 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1655 11:03:38.229175 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1656 11:03:38.232029 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1657 11:03:38.238343 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1658 11:03:38.242043 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1659 11:03:38.245236 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1660 11:03:38.248304 All bytes gating window > 1UI, Early break!
1661 11:03:38.248412
1662 11:03:38.251590 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
1663 11:03:38.251691
1664 11:03:38.254651 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 12)
1665 11:03:38.257851
1666 11:03:38.257944
1667 11:03:38.258048
1668 11:03:38.261731 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
1669 11:03:38.261838
1670 11:03:38.264689 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
1671 11:03:38.264787
1672 11:03:38.264870
1673 11:03:38.267922 Write Rank1 MR1 =0x56
1674 11:03:38.267999
1675 11:03:38.271435 best RODT dly(2T, 0.5T) = (2, 3)
1676 11:03:38.271516
1677 11:03:38.274717 best RODT dly(2T, 0.5T) = (2, 3)
1678 11:03:38.274822 ==
1679 11:03:38.277803 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1680 11:03:38.281345 fsp= 1, odt_onoff= 1, Byte mode= 0
1681 11:03:38.281430 ==
1682 11:03:38.287642 Start DQ dly to find pass range UseTestEngine =0
1683 11:03:38.290745 x-axis: bit #, y-axis: DQ dly (-127~63)
1684 11:03:38.290834 RX Vref Scan = 0
1685 11:03:38.294393 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1686 11:03:38.298185 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1687 11:03:38.301355 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1688 11:03:38.304373 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1689 11:03:38.307518 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1690 11:03:38.307607 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1691 11:03:38.310866 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1692 11:03:38.314087 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1693 11:03:38.317779 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1694 11:03:38.320857 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1695 11:03:38.324507 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1696 11:03:38.327589 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1697 11:03:38.330650 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1698 11:03:38.333801 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1699 11:03:38.333884 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1700 11:03:38.337011 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1701 11:03:38.340301 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1702 11:03:38.343574 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1703 11:03:38.347275 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1704 11:03:38.350422 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1705 11:03:38.353512 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1706 11:03:38.356806 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1707 11:03:38.356892 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1708 11:03:38.360539 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1709 11:03:38.363481 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1710 11:03:38.366751 -1, [0] xxxoxxxx xxxxxxxx [MSB]
1711 11:03:38.370635 0, [0] xxxoxoox oxxoxxxx [MSB]
1712 11:03:38.373850 1, [0] xxxoxoox oxxoxxxx [MSB]
1713 11:03:38.377074 2, [0] xxxoxooo oxxoxxxx [MSB]
1714 11:03:38.377155 3, [0] xxxooooo ooxooxxx [MSB]
1715 11:03:38.380308 4, [0] xoxooooo ooxooxxx [MSB]
1716 11:03:38.383278 5, [0] oooooooo ooxoooox [MSB]
1717 11:03:38.386716 6, [0] oooooooo ooxooooo [MSB]
1718 11:03:38.389870 7, [0] oooooooo ooxooooo [MSB]
1719 11:03:38.393407 8, [0] oooooooo ooxooooo [MSB]
1720 11:03:38.393486 9, [0] oooooooo ooxooooo [MSB]
1721 11:03:38.396432 32, [0] oooxoooo oooooooo [MSB]
1722 11:03:38.399924 33, [0] oooxoxoo oooooooo [MSB]
1723 11:03:38.403561 34, [0] oooxoxoo xooooooo [MSB]
1724 11:03:38.406332 35, [0] oooxoxoo xooxoooo [MSB]
1725 11:03:38.410247 36, [0] oooxoxoo xxoxxooo [MSB]
1726 11:03:38.412936 37, [0] oooxoxxx xxoxxoxo [MSB]
1727 11:03:38.413016 38, [0] xooxoxxx xxoxxxxo [MSB]
1728 11:03:38.416314 39, [0] xxoxoxxx xxoxxxxo [MSB]
1729 11:03:38.419992 40, [0] xxxxoxxx xxoxxxxo [MSB]
1730 11:03:38.422729 41, [0] xxxxxxxx xxoxxxxx [MSB]
1731 11:03:38.426232 42, [0] xxxxxxxx xxoxxxxx [MSB]
1732 11:03:38.429538 43, [0] xxxxxxxx xxxxxxxx [MSB]
1733 11:03:38.433459 iDelay=43, Bit 0, Center 21 (5 ~ 37) 33
1734 11:03:38.436117 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
1735 11:03:38.439514 iDelay=43, Bit 2, Center 22 (5 ~ 39) 35
1736 11:03:38.442768 iDelay=43, Bit 3, Center 15 (-1 ~ 31) 33
1737 11:03:38.446457 iDelay=43, Bit 4, Center 21 (3 ~ 40) 38
1738 11:03:38.449606 iDelay=43, Bit 5, Center 16 (0 ~ 32) 33
1739 11:03:38.452976 iDelay=43, Bit 6, Center 18 (0 ~ 36) 37
1740 11:03:38.456027 iDelay=43, Bit 7, Center 19 (2 ~ 36) 35
1741 11:03:38.459030 iDelay=43, Bit 8, Center 16 (0 ~ 33) 34
1742 11:03:38.466148 iDelay=43, Bit 9, Center 19 (3 ~ 35) 33
1743 11:03:38.469256 iDelay=43, Bit 10, Center 26 (10 ~ 42) 33
1744 11:03:38.472730 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35
1745 11:03:38.475885 iDelay=43, Bit 12, Center 19 (3 ~ 35) 33
1746 11:03:38.479007 iDelay=43, Bit 13, Center 21 (5 ~ 37) 33
1747 11:03:38.482250 iDelay=43, Bit 14, Center 20 (5 ~ 36) 32
1748 11:03:38.485547 iDelay=43, Bit 15, Center 23 (6 ~ 40) 35
1749 11:03:38.485625 ==
1750 11:03:38.492126 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1751 11:03:38.495254 fsp= 1, odt_onoff= 1, Byte mode= 0
1752 11:03:38.495339 ==
1753 11:03:38.495397 DQS Delay:
1754 11:03:38.498351 DQS0 = 0, DQS1 = 0
1755 11:03:38.498428 DQM Delay:
1756 11:03:38.502500 DQM0 = 19, DQM1 = 20
1757 11:03:38.502578 DQ Delay:
1758 11:03:38.505842 DQ0 =21, DQ1 =21, DQ2 =22, DQ3 =15
1759 11:03:38.508384 DQ4 =21, DQ5 =16, DQ6 =18, DQ7 =19
1760 11:03:38.511532 DQ8 =16, DQ9 =19, DQ10 =26, DQ11 =17
1761 11:03:38.515349 DQ12 =19, DQ13 =21, DQ14 =20, DQ15 =23
1762 11:03:38.515431
1763 11:03:38.515507
1764 11:03:38.515578 DramC Write-DBI off
1765 11:03:38.515646 ==
1766 11:03:38.521625 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1767 11:03:38.525013 fsp= 1, odt_onoff= 1, Byte mode= 0
1768 11:03:38.525117 ==
1769 11:03:38.528656 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1770 11:03:38.528735
1771 11:03:38.531890 Begin, DQ Scan Range 919~1175
1772 11:03:38.531970
1773 11:03:38.532045
1774 11:03:38.535149 TX Vref Scan disable
1775 11:03:38.538303 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1776 11:03:38.541495 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1777 11:03:38.544749 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1778 11:03:38.547798 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1779 11:03:38.552008 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1780 11:03:38.555006 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1781 11:03:38.557847 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1782 11:03:38.561054 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1783 11:03:38.568062 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1784 11:03:38.570967 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1785 11:03:38.574571 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1786 11:03:38.577834 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1787 11:03:38.581187 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1788 11:03:38.584847 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1789 11:03:38.588341 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1790 11:03:38.590723 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1791 11:03:38.594245 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1792 11:03:38.597164 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1793 11:03:38.600678 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1794 11:03:38.603593 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1795 11:03:38.607652 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1796 11:03:38.613481 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1797 11:03:38.616737 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1798 11:03:38.620421 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1799 11:03:38.623856 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1800 11:03:38.626678 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1801 11:03:38.630013 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1802 11:03:38.633389 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1803 11:03:38.636949 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1804 11:03:38.639878 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1805 11:03:38.643463 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1806 11:03:38.647021 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1807 11:03:38.650374 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1808 11:03:38.653406 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1809 11:03:38.656550 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1810 11:03:38.663573 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1811 11:03:38.666301 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1812 11:03:38.669703 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1813 11:03:38.673434 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1814 11:03:38.676658 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1815 11:03:38.679949 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1816 11:03:38.683198 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1817 11:03:38.686392 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1818 11:03:38.689439 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1819 11:03:38.692594 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1820 11:03:38.696098 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1821 11:03:38.699531 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1822 11:03:38.702692 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1823 11:03:38.705942 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1824 11:03:38.709062 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1825 11:03:38.712937 969 |3 6 9|[0] xxxxxxxx ooxooxox [MSB]
1826 11:03:38.715998 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1827 11:03:38.722096 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1828 11:03:38.725473 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1829 11:03:38.728840 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1830 11:03:38.732268 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1831 11:03:38.735445 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1832 11:03:38.738965 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1833 11:03:38.742190 977 |3 6 17|[0] xxxoxooo oooooooo [MSB]
1834 11:03:38.745811 978 |3 6 18|[0] xoxooooo oooooooo [MSB]
1835 11:03:38.748791 979 |3 6 19|[0] xoxooooo oooooooo [MSB]
1836 11:03:38.751670 980 |3 6 20|[0] xooooooo oooooooo [MSB]
1837 11:03:38.758433 988 |3 6 28|[0] oooooooo xooxoooo [MSB]
1838 11:03:38.762147 989 |3 6 29|[0] oooooooo xooxoooo [MSB]
1839 11:03:38.765565 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1840 11:03:38.768924 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1841 11:03:38.771850 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1842 11:03:38.775391 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1843 11:03:38.778543 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1844 11:03:38.781855 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1845 11:03:38.785145 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1846 11:03:38.788437 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1847 11:03:38.792314 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB]
1848 11:03:38.794894 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1849 11:03:38.798389 Byte0, DQ PI dly=987, DQM PI dly= 987
1850 11:03:38.804802 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
1851 11:03:38.804895
1852 11:03:38.808578 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
1853 11:03:38.808655
1854 11:03:38.811759 Byte1, DQ PI dly=979, DQM PI dly= 979
1855 11:03:38.814820 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1856 11:03:38.814897
1857 11:03:38.821291 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1858 11:03:38.821381
1859 11:03:38.821441 ==
1860 11:03:38.824630 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1861 11:03:38.828226 fsp= 1, odt_onoff= 1, Byte mode= 0
1862 11:03:38.828309 ==
1863 11:03:38.834983 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1864 11:03:38.835088
1865 11:03:38.837968 Begin, DQ Scan Range 955~1019
1866 11:03:38.838130 Write Rank1 MR14 =0x0
1867 11:03:38.846282
1868 11:03:38.846407 CH=0, VrefRange= 0, VrefLevel = 0
1869 11:03:38.853379 TX Bit0 (983~994) 12 988, Bit8 (969~982) 14 975,
1870 11:03:38.856373 TX Bit1 (981~993) 13 987, Bit9 (973~983) 11 978,
1871 11:03:38.862872 TX Bit2 (983~994) 12 988, Bit10 (976~990) 15 983,
1872 11:03:38.866659 TX Bit3 (976~990) 15 983, Bit11 (971~982) 12 976,
1873 11:03:38.869474 TX Bit4 (981~993) 13 987, Bit12 (973~984) 12 978,
1874 11:03:38.876270 TX Bit5 (978~991) 14 984, Bit13 (973~985) 13 979,
1875 11:03:38.879435 TX Bit6 (979~991) 13 985, Bit14 (973~986) 14 979,
1876 11:03:38.882726 TX Bit7 (980~994) 15 987, Bit15 (976~988) 13 982,
1877 11:03:38.886444
1878 11:03:38.886519 Write Rank1 MR14 =0x2
1879 11:03:38.894742
1880 11:03:38.894831 CH=0, VrefRange= 0, VrefLevel = 2
1881 11:03:38.901777 TX Bit0 (983~995) 13 989, Bit8 (969~983) 15 976,
1882 11:03:38.904676 TX Bit1 (982~994) 13 988, Bit9 (971~984) 14 977,
1883 11:03:38.910901 TX Bit2 (983~995) 13 989, Bit10 (976~990) 15 983,
1884 11:03:38.914437 TX Bit3 (976~990) 15 983, Bit11 (971~982) 12 976,
1885 11:03:38.918107 TX Bit4 (981~994) 14 987, Bit12 (972~984) 13 978,
1886 11:03:38.924530 TX Bit5 (978~992) 15 985, Bit13 (972~985) 14 978,
1887 11:03:38.927894 TX Bit6 (978~992) 15 985, Bit14 (973~988) 16 980,
1888 11:03:38.934072 TX Bit7 (980~994) 15 987, Bit15 (976~989) 14 982,
1889 11:03:38.934156
1890 11:03:38.934216 Write Rank1 MR14 =0x4
1891 11:03:38.943598
1892 11:03:38.943686 CH=0, VrefRange= 0, VrefLevel = 4
1893 11:03:38.949891 TX Bit0 (983~997) 15 990, Bit8 (969~983) 15 976,
1894 11:03:38.953349 TX Bit1 (981~995) 15 988, Bit9 (972~984) 13 978,
1895 11:03:38.960125 TX Bit2 (982~996) 15 989, Bit10 (975~991) 17 983,
1896 11:03:38.963400 TX Bit3 (976~991) 16 983, Bit11 (970~983) 14 976,
1897 11:03:38.966631 TX Bit4 (981~995) 15 988, Bit12 (971~985) 15 978,
1898 11:03:38.973421 TX Bit5 (978~992) 15 985, Bit13 (972~986) 15 979,
1899 11:03:38.976257 TX Bit6 (978~993) 16 985, Bit14 (973~988) 16 980,
1900 11:03:38.983415 TX Bit7 (980~996) 17 988, Bit15 (975~989) 15 982,
1901 11:03:38.983505
1902 11:03:38.983566 Write Rank1 MR14 =0x6
1903 11:03:38.992402
1904 11:03:38.992497 CH=0, VrefRange= 0, VrefLevel = 6
1905 11:03:38.998639 TX Bit0 (983~997) 15 990, Bit8 (969~983) 15 976,
1906 11:03:39.001850 TX Bit1 (980~996) 17 988, Bit9 (971~985) 15 978,
1907 11:03:39.008420 TX Bit2 (982~997) 16 989, Bit10 (975~992) 18 983,
1908 11:03:39.011623 TX Bit3 (975~991) 17 983, Bit11 (970~983) 14 976,
1909 11:03:39.015157 TX Bit4 (980~996) 17 988, Bit12 (971~986) 16 978,
1910 11:03:39.021976 TX Bit5 (977~993) 17 985, Bit13 (972~987) 16 979,
1911 11:03:39.024849 TX Bit6 (977~993) 17 985, Bit14 (972~989) 18 980,
1912 11:03:39.031592 TX Bit7 (980~997) 18 988, Bit15 (975~990) 16 982,
1913 11:03:39.031741
1914 11:03:39.031808 Write Rank1 MR14 =0x8
1915 11:03:39.041493
1916 11:03:39.041612 CH=0, VrefRange= 0, VrefLevel = 8
1917 11:03:39.047462 TX Bit0 (982~998) 17 990, Bit8 (968~984) 17 976,
1918 11:03:39.050735 TX Bit1 (980~997) 18 988, Bit9 (971~986) 16 978,
1919 11:03:39.057004 TX Bit2 (982~998) 17 990, Bit10 (975~991) 17 983,
1920 11:03:39.060652 TX Bit3 (976~991) 16 983, Bit11 (969~984) 16 976,
1921 11:03:39.063662 TX Bit4 (980~997) 18 988, Bit12 (971~986) 16 978,
1922 11:03:39.070589 TX Bit5 (977~994) 18 985, Bit13 (971~988) 18 979,
1923 11:03:39.073881 TX Bit6 (977~994) 18 985, Bit14 (972~990) 19 981,
1924 11:03:39.080474 TX Bit7 (978~997) 20 987, Bit15 (975~990) 16 982,
1925 11:03:39.080583
1926 11:03:39.080643 Write Rank1 MR14 =0xa
1927 11:03:39.089576
1928 11:03:39.092805 CH=0, VrefRange= 0, VrefLevel = 10
1929 11:03:39.096481 TX Bit0 (981~998) 18 989, Bit8 (968~985) 18 976,
1930 11:03:39.099632 TX Bit1 (980~998) 19 989, Bit9 (970~987) 18 978,
1931 11:03:39.106219 TX Bit2 (982~999) 18 990, Bit10 (975~993) 19 984,
1932 11:03:39.109914 TX Bit3 (975~992) 18 983, Bit11 (969~985) 17 977,
1933 11:03:39.112796 TX Bit4 (979~998) 20 988, Bit12 (970~988) 19 979,
1934 11:03:39.119570 TX Bit5 (977~994) 18 985, Bit13 (970~989) 20 979,
1935 11:03:39.122564 TX Bit6 (977~995) 19 986, Bit14 (971~990) 20 980,
1936 11:03:39.129045 TX Bit7 (978~998) 21 988, Bit15 (975~991) 17 983,
1937 11:03:39.129139
1938 11:03:39.129199 Write Rank1 MR14 =0xc
1939 11:03:39.138592
1940 11:03:39.141977 CH=0, VrefRange= 0, VrefLevel = 12
1941 11:03:39.145243 TX Bit0 (981~999) 19 990, Bit8 (968~986) 19 977,
1942 11:03:39.148537 TX Bit1 (979~998) 20 988, Bit9 (969~987) 19 978,
1943 11:03:39.155637 TX Bit2 (982~999) 18 990, Bit10 (974~994) 21 984,
1944 11:03:39.158776 TX Bit3 (975~992) 18 983, Bit11 (968~985) 18 976,
1945 11:03:39.162021 TX Bit4 (978~998) 21 988, Bit12 (970~989) 20 979,
1946 11:03:39.168791 TX Bit5 (977~995) 19 986, Bit13 (970~989) 20 979,
1947 11:03:39.171781 TX Bit6 (977~996) 20 986, Bit14 (970~990) 21 980,
1948 11:03:39.178244 TX Bit7 (978~999) 22 988, Bit15 (974~991) 18 982,
1949 11:03:39.178339
1950 11:03:39.178399 Write Rank1 MR14 =0xe
1951 11:03:39.187678
1952 11:03:39.190933 CH=0, VrefRange= 0, VrefLevel = 14
1953 11:03:39.194199 TX Bit0 (981~999) 19 990, Bit8 (967~987) 21 977,
1954 11:03:39.197358 TX Bit1 (979~999) 21 989, Bit9 (969~988) 20 978,
1955 11:03:39.204276 TX Bit2 (980~999) 20 989, Bit10 (974~994) 21 984,
1956 11:03:39.207843 TX Bit3 (975~992) 18 983, Bit11 (968~986) 19 977,
1957 11:03:39.211010 TX Bit4 (978~998) 21 988, Bit12 (969~989) 21 979,
1958 11:03:39.217532 TX Bit5 (976~996) 21 986, Bit13 (969~989) 21 979,
1959 11:03:39.221188 TX Bit6 (977~997) 21 987, Bit14 (970~991) 22 980,
1960 11:03:39.227487 TX Bit7 (978~999) 22 988, Bit15 (974~992) 19 983,
1961 11:03:39.227579
1962 11:03:39.227639 Write Rank1 MR14 =0x10
1963 11:03:39.237655
1964 11:03:39.240225 CH=0, VrefRange= 0, VrefLevel = 16
1965 11:03:39.243622 TX Bit0 (981~999) 19 990, Bit8 (967~988) 22 977,
1966 11:03:39.246538 TX Bit1 (979~999) 21 989, Bit9 (969~989) 21 979,
1967 11:03:39.253573 TX Bit2 (980~999) 20 989, Bit10 (974~995) 22 984,
1968 11:03:39.256911 TX Bit3 (974~993) 20 983, Bit11 (968~987) 20 977,
1969 11:03:39.260336 TX Bit4 (978~999) 22 988, Bit12 (969~990) 22 979,
1970 11:03:39.266313 TX Bit5 (976~996) 21 986, Bit13 (969~990) 22 979,
1971 11:03:39.269674 TX Bit6 (977~998) 22 987, Bit14 (969~991) 23 980,
1972 11:03:39.276707 TX Bit7 (977~999) 23 988, Bit15 (974~993) 20 983,
1973 11:03:39.276797
1974 11:03:39.276862 Write Rank1 MR14 =0x12
1975 11:03:39.286236
1976 11:03:39.289269 CH=0, VrefRange= 0, VrefLevel = 18
1977 11:03:39.292434 TX Bit0 (980~1000) 21 990, Bit8 (967~988) 22 977,
1978 11:03:39.296692 TX Bit1 (978~1000) 23 989, Bit9 (968~989) 22 978,
1979 11:03:39.302803 TX Bit2 (980~1000) 21 990, Bit10 (974~994) 21 984,
1980 11:03:39.306428 TX Bit3 (974~994) 21 984, Bit11 (968~988) 21 978,
1981 11:03:39.309456 TX Bit4 (978~999) 22 988, Bit12 (968~990) 23 979,
1982 11:03:39.315890 TX Bit5 (976~997) 22 986, Bit13 (968~990) 23 979,
1983 11:03:39.319353 TX Bit6 (976~998) 23 987, Bit14 (970~992) 23 981,
1984 11:03:39.325493 TX Bit7 (977~1000) 24 988, Bit15 (974~993) 20 983,
1985 11:03:39.325582
1986 11:03:39.325640 Write Rank1 MR14 =0x14
1987 11:03:39.335765
1988 11:03:39.338959 CH=0, VrefRange= 0, VrefLevel = 20
1989 11:03:39.342740 TX Bit0 (979~1000) 22 989, Bit8 (967~989) 23 978,
1990 11:03:39.345623 TX Bit1 (978~1000) 23 989, Bit9 (968~990) 23 979,
1991 11:03:39.352172 TX Bit2 (980~1001) 22 990, Bit10 (973~996) 24 984,
1992 11:03:39.355865 TX Bit3 (974~994) 21 984, Bit11 (967~989) 23 978,
1993 11:03:39.359121 TX Bit4 (977~999) 23 988, Bit12 (968~990) 23 979,
1994 11:03:39.365678 TX Bit5 (976~997) 22 986, Bit13 (968~991) 24 979,
1995 11:03:39.369159 TX Bit6 (976~998) 23 987, Bit14 (969~992) 24 980,
1996 11:03:39.375413 TX Bit7 (977~1000) 24 988, Bit15 (974~994) 21 984,
1997 11:03:39.375506
1998 11:03:39.378858 wait MRW command Rank1 MR14 =0x16 fired (1)
1999 11:03:39.378938 Write Rank1 MR14 =0x16
2000 11:03:39.389730
2001 11:03:39.393178 CH=0, VrefRange= 0, VrefLevel = 22
2002 11:03:39.396072 TX Bit0 (979~1001) 23 990, Bit8 (966~989) 24 977,
2003 11:03:39.399739 TX Bit1 (977~1000) 24 988, Bit9 (968~990) 23 979,
2004 11:03:39.406076 TX Bit2 (979~1001) 23 990, Bit10 (973~996) 24 984,
2005 11:03:39.409250 TX Bit3 (974~994) 21 984, Bit11 (967~989) 23 978,
2006 11:03:39.415875 TX Bit4 (977~1000) 24 988, Bit12 (968~991) 24 979,
2007 11:03:39.419420 TX Bit5 (976~998) 23 987, Bit13 (968~991) 24 979,
2008 11:03:39.422866 TX Bit6 (976~999) 24 987, Bit14 (969~993) 25 981,
2009 11:03:39.428720 TX Bit7 (977~1000) 24 988, Bit15 (972~995) 24 983,
2010 11:03:39.428811
2011 11:03:39.428873 Write Rank1 MR14 =0x18
2012 11:03:39.439419
2013 11:03:39.442707 CH=0, VrefRange= 0, VrefLevel = 24
2014 11:03:39.446367 TX Bit0 (978~1001) 24 989, Bit8 (966~990) 25 978,
2015 11:03:39.449413 TX Bit1 (977~1000) 24 988, Bit9 (968~990) 23 979,
2016 11:03:39.455970 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2017 11:03:39.459079 TX Bit3 (973~996) 24 984, Bit11 (967~989) 23 978,
2018 11:03:39.465506 TX Bit4 (977~1000) 24 988, Bit12 (968~991) 24 979,
2019 11:03:39.468677 TX Bit5 (976~998) 23 987, Bit13 (968~991) 24 979,
2020 11:03:39.472399 TX Bit6 (976~999) 24 987, Bit14 (968~993) 26 980,
2021 11:03:39.478927 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
2022 11:03:39.479017
2023 11:03:39.479075 Write Rank1 MR14 =0x1a
2024 11:03:39.489296
2025 11:03:39.492928 CH=0, VrefRange= 0, VrefLevel = 26
2026 11:03:39.496057 TX Bit0 (978~1002) 25 990, Bit8 (966~989) 24 977,
2027 11:03:39.499528 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
2028 11:03:39.505769 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2029 11:03:39.509272 TX Bit3 (973~996) 24 984, Bit11 (967~990) 24 978,
2030 11:03:39.512358 TX Bit4 (977~1001) 25 989, Bit12 (968~992) 25 980,
2031 11:03:39.519498 TX Bit5 (975~999) 25 987, Bit13 (968~991) 24 979,
2032 11:03:39.522801 TX Bit6 (976~999) 24 987, Bit14 (968~993) 26 980,
2033 11:03:39.529043 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
2034 11:03:39.529143
2035 11:03:39.529220 Write Rank1 MR14 =0x1c
2036 11:03:39.539876
2037 11:03:39.542884 CH=0, VrefRange= 0, VrefLevel = 28
2038 11:03:39.546344 TX Bit0 (978~1002) 25 990, Bit8 (966~989) 24 977,
2039 11:03:39.549659 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
2040 11:03:39.556121 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2041 11:03:39.559359 TX Bit3 (973~996) 24 984, Bit11 (967~990) 24 978,
2042 11:03:39.563130 TX Bit4 (977~1001) 25 989, Bit12 (968~992) 25 980,
2043 11:03:39.569279 TX Bit5 (975~999) 25 987, Bit13 (968~991) 24 979,
2044 11:03:39.572186 TX Bit6 (976~999) 24 987, Bit14 (968~993) 26 980,
2045 11:03:39.579391 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
2046 11:03:39.579489
2047 11:03:39.579548 Write Rank1 MR14 =0x1e
2048 11:03:39.589802
2049 11:03:39.592911 CH=0, VrefRange= 0, VrefLevel = 30
2050 11:03:39.596100 TX Bit0 (978~1002) 25 990, Bit8 (966~989) 24 977,
2051 11:03:39.599875 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
2052 11:03:39.606227 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2053 11:03:39.609327 TX Bit3 (973~996) 24 984, Bit11 (967~990) 24 978,
2054 11:03:39.613178 TX Bit4 (977~1001) 25 989, Bit12 (968~992) 25 980,
2055 11:03:39.619485 TX Bit5 (975~999) 25 987, Bit13 (968~991) 24 979,
2056 11:03:39.622268 TX Bit6 (976~999) 24 987, Bit14 (968~993) 26 980,
2057 11:03:39.628890 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
2058 11:03:39.628996
2059 11:03:39.629061 Write Rank1 MR14 =0x20
2060 11:03:39.639605
2061 11:03:39.642932 CH=0, VrefRange= 0, VrefLevel = 32
2062 11:03:39.646917 TX Bit0 (978~1002) 25 990, Bit8 (966~989) 24 977,
2063 11:03:39.650163 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
2064 11:03:39.656552 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2065 11:03:39.659676 TX Bit3 (973~996) 24 984, Bit11 (967~990) 24 978,
2066 11:03:39.663028 TX Bit4 (977~1001) 25 989, Bit12 (968~992) 25 980,
2067 11:03:39.669525 TX Bit5 (975~999) 25 987, Bit13 (968~991) 24 979,
2068 11:03:39.672714 TX Bit6 (976~999) 24 987, Bit14 (968~993) 26 980,
2069 11:03:39.679179 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
2070 11:03:39.679285
2071 11:03:39.679361 Write Rank1 MR14 =0x22
2072 11:03:39.689464
2073 11:03:39.693122 CH=0, VrefRange= 0, VrefLevel = 34
2074 11:03:39.696367 TX Bit0 (978~1002) 25 990, Bit8 (966~989) 24 977,
2075 11:03:39.699660 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
2076 11:03:39.706100 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2077 11:03:39.709334 TX Bit3 (973~996) 24 984, Bit11 (967~990) 24 978,
2078 11:03:39.716068 TX Bit4 (977~1001) 25 989, Bit12 (968~992) 25 980,
2079 11:03:39.719210 TX Bit5 (975~999) 25 987, Bit13 (968~991) 24 979,
2080 11:03:39.722593 TX Bit6 (976~999) 24 987, Bit14 (968~993) 26 980,
2081 11:03:39.729380 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
2082 11:03:39.729469
2083 11:03:39.729561 Write Rank1 MR14 =0x24
2084 11:03:39.739829
2085 11:03:39.742961 CH=0, VrefRange= 0, VrefLevel = 36
2086 11:03:39.746261 TX Bit0 (978~1002) 25 990, Bit8 (966~989) 24 977,
2087 11:03:39.749441 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
2088 11:03:39.756418 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2089 11:03:39.759665 TX Bit3 (973~996) 24 984, Bit11 (967~990) 24 978,
2090 11:03:39.765898 TX Bit4 (977~1001) 25 989, Bit12 (968~992) 25 980,
2091 11:03:39.769150 TX Bit5 (975~999) 25 987, Bit13 (968~991) 24 979,
2092 11:03:39.772639 TX Bit6 (976~999) 24 987, Bit14 (968~993) 26 980,
2093 11:03:39.779365 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
2094 11:03:39.779456
2095 11:03:39.779531
2096 11:03:39.782902 TX Vref found, early break! 363< 373
2097 11:03:39.785586 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2098 11:03:39.789010 u1DelayCellOfst[0]=7 cells (6 PI)
2099 11:03:39.792457 u1DelayCellOfst[1]=6 cells (5 PI)
2100 11:03:39.795598 u1DelayCellOfst[2]=6 cells (5 PI)
2101 11:03:39.798729 u1DelayCellOfst[3]=0 cells (0 PI)
2102 11:03:39.802932 u1DelayCellOfst[4]=6 cells (5 PI)
2103 11:03:39.805664 u1DelayCellOfst[5]=3 cells (3 PI)
2104 11:03:39.809117 u1DelayCellOfst[6]=3 cells (3 PI)
2105 11:03:39.812339 u1DelayCellOfst[7]=6 cells (5 PI)
2106 11:03:39.815873 Byte0, DQ PI dly=984, DQM PI dly= 987
2107 11:03:39.818808 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2108 11:03:39.818948
2109 11:03:39.821797 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2110 11:03:39.821912
2111 11:03:39.825377 u1DelayCellOfst[8]=0 cells (0 PI)
2112 11:03:39.828500 u1DelayCellOfst[9]=2 cells (2 PI)
2113 11:03:39.831781 u1DelayCellOfst[10]=10 cells (8 PI)
2114 11:03:39.835309 u1DelayCellOfst[11]=1 cells (1 PI)
2115 11:03:39.838714 u1DelayCellOfst[12]=3 cells (3 PI)
2116 11:03:39.841662 u1DelayCellOfst[13]=2 cells (2 PI)
2117 11:03:39.845522 u1DelayCellOfst[14]=3 cells (3 PI)
2118 11:03:39.848554 u1DelayCellOfst[15]=9 cells (7 PI)
2119 11:03:39.851802 Byte1, DQ PI dly=977, DQM PI dly= 981
2120 11:03:39.855499 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2121 11:03:39.855603
2122 11:03:39.858824 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2123 11:03:39.858900
2124 11:03:39.861869 Write Rank1 MR14 =0x1a
2125 11:03:39.861966
2126 11:03:39.864876 Final TX Range 0 Vref 26
2127 11:03:39.864975
2128 11:03:39.871445 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2129 11:03:39.871534
2130 11:03:39.878455 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2131 11:03:39.884583 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2132 11:03:39.891667 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2133 11:03:39.894574 wait MRW command Rank1 MR3 =0xb0 fired (1)
2134 11:03:39.897827 Write Rank1 MR3 =0xb0
2135 11:03:39.897934 DramC Write-DBI on
2136 11:03:39.901630 ==
2137 11:03:39.904714 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2138 11:03:39.907802 fsp= 1, odt_onoff= 1, Byte mode= 0
2139 11:03:39.907909 ==
2140 11:03:39.910845 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2141 11:03:39.910947
2142 11:03:39.914592 Begin, DQ Scan Range 701~765
2143 11:03:39.914677
2144 11:03:39.914738
2145 11:03:39.917985 TX Vref Scan disable
2146 11:03:39.921012 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2147 11:03:39.924533 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2148 11:03:39.927773 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2149 11:03:39.930850 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2150 11:03:39.934096 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2151 11:03:39.937712 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2152 11:03:39.940658 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2153 11:03:39.944254 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2154 11:03:39.947612 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2155 11:03:39.951396 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2156 11:03:39.954309 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2157 11:03:39.957540 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2158 11:03:39.964049 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2159 11:03:39.967239 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2160 11:03:39.970887 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2161 11:03:39.974386 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2162 11:03:39.977308 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2163 11:03:39.980890 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2164 11:03:39.983733 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2165 11:03:39.987347 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2166 11:03:39.994399 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2167 11:03:39.998213 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2168 11:03:40.001040 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2169 11:03:40.004467 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2170 11:03:40.007949 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2171 11:03:40.010953 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2172 11:03:40.014539 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2173 11:03:40.017742 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2174 11:03:40.020920 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2175 11:03:40.024023 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2176 11:03:40.027689 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
2177 11:03:40.031172 Byte0, DQ PI dly=733, DQM PI dly= 733
2178 11:03:40.037421 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 29)
2179 11:03:40.037539
2180 11:03:40.040532 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 29)
2181 11:03:40.040621
2182 11:03:40.043750 Byte1, DQ PI dly=723, DQM PI dly= 723
2183 11:03:40.047278 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2184 11:03:40.047347
2185 11:03:40.053790 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2186 11:03:40.053913
2187 11:03:40.060307 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2188 11:03:40.067003 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2189 11:03:40.073670 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2190 11:03:40.076799 Write Rank1 MR3 =0x30
2191 11:03:40.076905 DramC Write-DBI off
2192 11:03:40.076990
2193 11:03:40.077072 [DATLAT]
2194 11:03:40.080204 Freq=1600, CH0 RK1, use_rxtx_scan=0
2195 11:03:40.080310
2196 11:03:40.084644 DATLAT Default: 0x10
2197 11:03:40.084740 7, 0xFFFF, sum=0
2198 11:03:40.087528 8, 0xFFFF, sum=0
2199 11:03:40.087606 9, 0xFFFF, sum=0
2200 11:03:40.091005 10, 0xFFFF, sum=0
2201 11:03:40.091100 11, 0xFFFF, sum=0
2202 11:03:40.094630 12, 0xFFFF, sum=0
2203 11:03:40.094705 13, 0xFFFF, sum=0
2204 11:03:40.097613 14, 0x0, sum=1
2205 11:03:40.097705 15, 0x0, sum=2
2206 11:03:40.097790 16, 0x0, sum=3
2207 11:03:40.100780 17, 0x0, sum=4
2208 11:03:40.104026 pattern=2 first_step=14 total pass=5 best_step=16
2209 11:03:40.104115 ==
2210 11:03:40.110477 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2211 11:03:40.113818 fsp= 1, odt_onoff= 1, Byte mode= 0
2212 11:03:40.113929 ==
2213 11:03:40.117383 Start DQ dly to find pass range UseTestEngine =1
2214 11:03:40.120746 x-axis: bit #, y-axis: DQ dly (-127~63)
2215 11:03:40.123790 RX Vref Scan = 0
2216 11:03:40.127177 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2217 11:03:40.127258 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2218 11:03:40.130920 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2219 11:03:40.133710 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2220 11:03:40.136925 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2221 11:03:40.140564 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2222 11:03:40.143627 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2223 11:03:40.147014 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2224 11:03:40.150651 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2225 11:03:40.153457 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2226 11:03:40.153567 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2227 11:03:40.156797 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2228 11:03:40.160393 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2229 11:03:40.163715 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2230 11:03:40.166672 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2231 11:03:40.170232 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2232 11:03:40.173207 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2233 11:03:40.176824 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2234 11:03:40.176903 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2235 11:03:40.179866 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2236 11:03:40.183589 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2237 11:03:40.186210 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2238 11:03:40.189623 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2239 11:03:40.192959 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2240 11:03:40.196487 -2, [0] xxxoxxxx xxxxxxxx [MSB]
2241 11:03:40.200822 -1, [0] xxxoxxxx xxxxxxxx [MSB]
2242 11:03:40.200903 0, [0] xxxoxoxx oxxoxxxx [MSB]
2243 11:03:40.202941 1, [0] xxxoxoox oxxoxxxx [MSB]
2244 11:03:40.206855 2, [0] xoxoxoox ooxoxxxx [MSB]
2245 11:03:40.209589 3, [0] xoxoxoox ooxoooxx [MSB]
2246 11:03:40.213057 4, [0] ooxoxooo ooxoooxx [MSB]
2247 11:03:40.215884 5, [0] oooooooo ooxoooox [MSB]
2248 11:03:40.215965 6, [0] oooooooo ooxooooo [MSB]
2249 11:03:40.219698 7, [0] oooooooo ooxooooo [MSB]
2250 11:03:40.222757 8, [0] oooooooo ooxooooo [MSB]
2251 11:03:40.226545 32, [0] oooxoooo oooooooo [MSB]
2252 11:03:40.229675 33, [0] oooxoxoo oooooooo [MSB]
2253 11:03:40.232966 34, [0] oooxoxoo xooxoooo [MSB]
2254 11:03:40.236318 35, [0] oooxoxoo xooxoooo [MSB]
2255 11:03:40.239657 36, [0] oooxoxxo xxoxoooo [MSB]
2256 11:03:40.243117 37, [0] oooxoxxo xxoxxxoo [MSB]
2257 11:03:40.246270 38, [0] oooxoxxx xxoxxxxo [MSB]
2258 11:03:40.246345 39, [0] xooxxxxx xxoxxxxo [MSB]
2259 11:03:40.249653 40, [0] xxoxxxxx xxoxxxxo [MSB]
2260 11:03:40.252753 41, [0] xxxxxxxx xxoxxxxx [MSB]
2261 11:03:40.256393 42, [0] xxxxxxxx xxoxxxxx [MSB]
2262 11:03:40.259551 43, [0] xxxxxxxx xxxxxxxx [MSB]
2263 11:03:40.262686 iDelay=43, Bit 0, Center 21 (4 ~ 38) 35
2264 11:03:40.266489 iDelay=43, Bit 1, Center 20 (2 ~ 39) 38
2265 11:03:40.269937 iDelay=43, Bit 2, Center 22 (5 ~ 40) 36
2266 11:03:40.273140 iDelay=43, Bit 3, Center 14 (-3 ~ 31) 35
2267 11:03:40.276240 iDelay=43, Bit 4, Center 21 (5 ~ 38) 34
2268 11:03:40.279334 iDelay=43, Bit 5, Center 16 (0 ~ 32) 33
2269 11:03:40.282527 iDelay=43, Bit 6, Center 18 (1 ~ 35) 35
2270 11:03:40.286198 iDelay=43, Bit 7, Center 20 (4 ~ 37) 34
2271 11:03:40.289367 iDelay=43, Bit 8, Center 16 (0 ~ 33) 34
2272 11:03:40.296452 iDelay=43, Bit 9, Center 18 (2 ~ 35) 34
2273 11:03:40.299472 iDelay=43, Bit 10, Center 25 (9 ~ 42) 34
2274 11:03:40.303000 iDelay=43, Bit 11, Center 16 (0 ~ 33) 34
2275 11:03:40.306143 iDelay=43, Bit 12, Center 19 (3 ~ 36) 34
2276 11:03:40.309655 iDelay=43, Bit 13, Center 19 (3 ~ 36) 34
2277 11:03:40.312841 iDelay=43, Bit 14, Center 21 (5 ~ 37) 33
2278 11:03:40.315673 iDelay=43, Bit 15, Center 23 (6 ~ 40) 35
2279 11:03:40.315743 ==
2280 11:03:40.322237 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2281 11:03:40.325723 fsp= 1, odt_onoff= 1, Byte mode= 0
2282 11:03:40.325799 ==
2283 11:03:40.325856 DQS Delay:
2284 11:03:40.329045 DQS0 = 0, DQS1 = 0
2285 11:03:40.329117 DQM Delay:
2286 11:03:40.329172 DQM0 = 19, DQM1 = 19
2287 11:03:40.332447 DQ Delay:
2288 11:03:40.335634 DQ0 =21, DQ1 =20, DQ2 =22, DQ3 =14
2289 11:03:40.338913 DQ4 =21, DQ5 =16, DQ6 =18, DQ7 =20
2290 11:03:40.342457 DQ8 =16, DQ9 =18, DQ10 =25, DQ11 =16
2291 11:03:40.345430 DQ12 =19, DQ13 =19, DQ14 =21, DQ15 =23
2292 11:03:40.345538
2293 11:03:40.345598
2294 11:03:40.345655
2295 11:03:40.348673 [DramC_TX_OE_Calibration] TA2
2296 11:03:40.352214 Original DQ_B0 (3 6) =30, OEN = 27
2297 11:03:40.352320 Original DQ_B1 (3 6) =30, OEN = 27
2298 11:03:40.355108 23, 0x0, End_B0=23 End_B1=23
2299 11:03:40.358923 24, 0x0, End_B0=24 End_B1=24
2300 11:03:40.361840 25, 0x0, End_B0=25 End_B1=25
2301 11:03:40.365492 26, 0x0, End_B0=26 End_B1=26
2302 11:03:40.365572 27, 0x0, End_B0=27 End_B1=27
2303 11:03:40.368342 28, 0x0, End_B0=28 End_B1=28
2304 11:03:40.371614 29, 0x0, End_B0=29 End_B1=29
2305 11:03:40.375442 30, 0x0, End_B0=30 End_B1=30
2306 11:03:40.378243 31, 0xFFFF, End_B0=30 End_B1=30
2307 11:03:40.382168 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2308 11:03:40.388216 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2309 11:03:40.388304
2310 11:03:40.388363
2311 11:03:40.391713 Write Rank1 MR23 =0x3f
2312 11:03:40.391809 [DQSOSC]
2313 11:03:40.398412 [DQSOSCAuto] RK1, (LSB)MR18= 0xb4b4, (MSB)MR19= 0x202, tDQSOscB0 = 455 ps tDQSOscB1 = 455 ps
2314 11:03:40.404673 CH0_RK1: MR19=0x202, MR18=0xB4B4, DQSOSC=455, MR23=63, INC=11, DEC=17
2315 11:03:40.408380 Write Rank1 MR23 =0x3f
2316 11:03:40.408463 [DQSOSC]
2317 11:03:40.417911 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2b2, (MSB)MR19= 0x202, tDQSOscB0 = 456 ps tDQSOscB1 = 456 ps
2318 11:03:40.418046 CH0 RK1: MR19=202, MR18=B2B2
2319 11:03:40.421062 [RxdqsGatingPostProcess] freq 1600
2320 11:03:40.428102 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2321 11:03:40.428224 Rank: 0
2322 11:03:40.431217 best DQS0 dly(2T, 0.5T) = (2, 6)
2323 11:03:40.434522 best DQS1 dly(2T, 0.5T) = (2, 6)
2324 11:03:40.438065 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2325 11:03:40.441086 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2326 11:03:40.441167 Rank: 1
2327 11:03:40.444204 best DQS0 dly(2T, 0.5T) = (2, 6)
2328 11:03:40.447581 best DQS1 dly(2T, 0.5T) = (2, 6)
2329 11:03:40.450995 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2330 11:03:40.454237 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2331 11:03:40.457572 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2332 11:03:40.461424 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2333 11:03:40.467410 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2334 11:03:40.467553 Write Rank0 MR13 =0x59
2335 11:03:40.471145 ==
2336 11:03:40.474093 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2337 11:03:40.477552 fsp= 1, odt_onoff= 1, Byte mode= 0
2338 11:03:40.477655 ==
2339 11:03:40.480922 === u2Vref_new: 0x56 --> 0x3a
2340 11:03:40.483842 === u2Vref_new: 0x58 --> 0x58
2341 11:03:40.487271 === u2Vref_new: 0x5a --> 0x5a
2342 11:03:40.490390 === u2Vref_new: 0x5c --> 0x78
2343 11:03:40.494293 === u2Vref_new: 0x5e --> 0x7a
2344 11:03:40.497260 === u2Vref_new: 0x60 --> 0x90
2345 11:03:40.500280 [CA 0] Center 37 (12~63) winsize 52
2346 11:03:40.504053 [CA 1] Center 36 (10~63) winsize 54
2347 11:03:40.507551 [CA 2] Center 35 (7~63) winsize 57
2348 11:03:40.510479 [CA 3] Center 34 (6~63) winsize 58
2349 11:03:40.513450 [CA 4] Center 34 (5~63) winsize 59
2350 11:03:40.513528 [CA 5] Center 28 (0~57) winsize 58
2351 11:03:40.517263
2352 11:03:40.520305 [CATrainingPosCal] consider 1 rank data
2353 11:03:40.520407 u2DelayCellTimex100 = 744/100 ps
2354 11:03:40.526451 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2355 11:03:40.529770 CA1 delay=36 (10~63),Diff = 8 PI (10 cell)
2356 11:03:40.533039 CA2 delay=35 (7~63),Diff = 7 PI (9 cell)
2357 11:03:40.536896 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2358 11:03:40.540197 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2359 11:03:40.543108 CA5 delay=28 (0~57),Diff = 0 PI (0 cell)
2360 11:03:40.543211
2361 11:03:40.546901 CA PerBit enable=1, Macro0, CA PI delay=28
2362 11:03:40.549532 === u2Vref_new: 0x5e --> 0x7a
2363 11:03:40.549626
2364 11:03:40.553318 Vref(ca) range 1: 30
2365 11:03:40.553416
2366 11:03:40.553500 CS Dly= 11 (42-0-32)
2367 11:03:40.556624 Write Rank0 MR13 =0xd8
2368 11:03:40.559909 Write Rank0 MR13 =0xd8
2369 11:03:40.559990 Write Rank0 MR12 =0x5e
2370 11:03:40.562887 Write Rank1 MR13 =0x59
2371 11:03:40.562965 ==
2372 11:03:40.569220 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2373 11:03:40.573245 fsp= 1, odt_onoff= 1, Byte mode= 0
2374 11:03:40.573353 ==
2375 11:03:40.573448 === u2Vref_new: 0x56 --> 0x3a
2376 11:03:40.576398 === u2Vref_new: 0x58 --> 0x58
2377 11:03:40.579601 === u2Vref_new: 0x5a --> 0x5a
2378 11:03:40.583224 === u2Vref_new: 0x5c --> 0x78
2379 11:03:40.586265 === u2Vref_new: 0x5e --> 0x7a
2380 11:03:40.589929 === u2Vref_new: 0x60 --> 0x90
2381 11:03:40.592871 [CA 0] Center 37 (11~63) winsize 53
2382 11:03:40.596432 [CA 1] Center 37 (11~63) winsize 53
2383 11:03:40.599323 [CA 2] Center 34 (6~63) winsize 58
2384 11:03:40.603178 [CA 3] Center 34 (6~63) winsize 58
2385 11:03:40.605898 [CA 4] Center 34 (5~63) winsize 59
2386 11:03:40.609175 [CA 5] Center 28 (0~57) winsize 58
2387 11:03:40.609247
2388 11:03:40.612693 [CATrainingPosCal] consider 2 rank data
2389 11:03:40.615718 u2DelayCellTimex100 = 744/100 ps
2390 11:03:40.619104 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2391 11:03:40.622408 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2392 11:03:40.626030 CA2 delay=35 (7~63),Diff = 7 PI (9 cell)
2393 11:03:40.629317 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2394 11:03:40.632597 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2395 11:03:40.638883 CA5 delay=28 (0~57),Diff = 0 PI (0 cell)
2396 11:03:40.638989
2397 11:03:40.642238 CA PerBit enable=1, Macro0, CA PI delay=28
2398 11:03:40.645713 === u2Vref_new: 0x5e --> 0x7a
2399 11:03:40.645811
2400 11:03:40.645906 Vref(ca) range 1: 30
2401 11:03:40.645990
2402 11:03:40.648861 CS Dly= 10 (41-0-32)
2403 11:03:40.652182 Write Rank1 MR13 =0xd8
2404 11:03:40.652265 Write Rank1 MR13 =0xd8
2405 11:03:40.655433 Write Rank1 MR12 =0x5e
2406 11:03:40.658704 [RankSwap] Rank num 2, (Multi 1), Rank 0
2407 11:03:40.658779 Write Rank0 MR2 =0xad
2408 11:03:40.661878 [Write Leveling]
2409 11:03:40.665119 delay byte0 byte1 byte2 byte3
2410 11:03:40.665219
2411 11:03:40.665308 10 0 0
2412 11:03:40.668644 11 0 0
2413 11:03:40.668738 12 0 0
2414 11:03:40.671772 13 0 0
2415 11:03:40.671870 14 0 0
2416 11:03:40.671960 15 0 0
2417 11:03:40.675586 16 0 0
2418 11:03:40.675693 17 0 0
2419 11:03:40.678687 18 0 0
2420 11:03:40.678780 19 0 0
2421 11:03:40.678871 20 0 0
2422 11:03:40.681904 21 0 0
2423 11:03:40.682001 22 0 0
2424 11:03:40.685157 23 0 0
2425 11:03:40.685250 24 0 0
2426 11:03:40.688588 25 0 0
2427 11:03:40.688692 26 0 0
2428 11:03:40.688776 27 0 0
2429 11:03:40.691807 28 0 0
2430 11:03:40.691909 29 0 0
2431 11:03:40.695171 30 0 0
2432 11:03:40.695245 31 0 0
2433 11:03:40.698272 32 0 0
2434 11:03:40.698372 33 0 ff
2435 11:03:40.698463 34 0 ff
2436 11:03:40.701871 35 ff ff
2437 11:03:40.701971 36 ff ff
2438 11:03:40.705198 37 ff ff
2439 11:03:40.705268 38 ff ff
2440 11:03:40.708249 39 ff ff
2441 11:03:40.708346 40 ff ff
2442 11:03:40.711480 41 ff ff
2443 11:03:40.715055 pass bytecount = 0xff (0xff: all bytes pass)
2444 11:03:40.715143
2445 11:03:40.715202 DQS0 dly: 35
2446 11:03:40.718187 DQS1 dly: 33
2447 11:03:40.718281 Write Rank0 MR2 =0x2d
2448 11:03:40.721402 [RankSwap] Rank num 2, (Multi 1), Rank 0
2449 11:03:40.724639 Write Rank0 MR1 =0xd6
2450 11:03:40.724731 [Gating]
2451 11:03:40.724817 ==
2452 11:03:40.731063 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2453 11:03:40.734451 fsp= 1, odt_onoff= 1, Byte mode= 0
2454 11:03:40.734523 ==
2455 11:03:40.738134 3 1 0 |2c2b 302 |(11 11)(11 11) |(1 1)(0 0)| 0
2456 11:03:40.744273 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2457 11:03:40.747673 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2458 11:03:40.750912 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2459 11:03:40.757570 3 1 16 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2460 11:03:40.760640 3 1 20 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 0)| 0
2461 11:03:40.764503 3 1 24 |2c2b 2323 |(11 11)(11 11) |(1 0)(1 1)| 0
2462 11:03:40.770716 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2463 11:03:40.773994 3 2 0 |2c2b 3131 |(11 11)(11 11) |(1 0)(1 1)| 0
2464 11:03:40.777262 3 2 4 |2c2b 3434 |(11 11)(11 11) |(1 0)(0 0)| 0
2465 11:03:40.780379 3 2 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2466 11:03:40.787211 3 2 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2467 11:03:40.790451 3 2 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2468 11:03:40.793571 3 2 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2469 11:03:40.800103 3 2 24 |909 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2470 11:03:40.803361 3 2 28 |3534 b0a |(11 11)(11 11) |(0 0)(0 1)| 0
2471 11:03:40.806767 3 3 0 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
2472 11:03:40.813235 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2473 11:03:40.816391 3 3 8 |3534 3d3c |(11 11)(11 11) |(0 0)(1 1)| 0
2474 11:03:40.820272 3 3 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2475 11:03:40.826592 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2476 11:03:40.829790 3 3 20 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2477 11:03:40.833129 3 3 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2478 11:03:40.839484 [Byte 0] Lead/lag Transition tap number (1)
2479 11:03:40.842758 3 3 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2480 11:03:40.845991 3 4 0 |3534 505 |(11 11)(11 11) |(0 0)(1 1)| 0
2481 11:03:40.849709 [Byte 1] Lead/lag Transition tap number (1)
2482 11:03:40.856273 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2483 11:03:40.859065 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2484 11:03:40.862274 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2485 11:03:40.868824 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2486 11:03:40.872205 3 4 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2487 11:03:40.875420 3 4 24 |201 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2488 11:03:40.882265 3 4 28 |3d3d 504 |(11 11)(11 11) |(1 1)(0 1)| 0
2489 11:03:40.885599 3 5 0 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
2490 11:03:40.888817 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2491 11:03:40.895377 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2492 11:03:40.898608 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2493 11:03:40.902153 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2494 11:03:40.908114 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2495 11:03:40.912015 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2496 11:03:40.914795 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2497 11:03:40.921715 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2498 11:03:40.924851 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2499 11:03:40.927867 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2500 11:03:40.934560 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2501 11:03:40.938062 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2502 11:03:40.941245 [Byte 0] Lead/lag falling Transition (3, 6, 16)
2503 11:03:40.947838 3 6 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2504 11:03:40.950936 [Byte 0] Lead/lag Transition tap number (2)
2505 11:03:40.954728 [Byte 1] Lead/lag falling Transition (3, 6, 20)
2506 11:03:40.957735 3 6 24 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2507 11:03:40.961323 [Byte 1] Lead/lag Transition tap number (2)
2508 11:03:40.967333 3 6 28 |4646 3e3d |(10 10)(11 11) |(0 0)(0 0)| 0
2509 11:03:40.970624 3 7 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2510 11:03:40.974293 [Byte 0]First pass (3, 7, 0)
2511 11:03:40.977487 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2512 11:03:40.980511 [Byte 1]First pass (3, 7, 4)
2513 11:03:40.983822 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2514 11:03:40.987468 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2515 11:03:40.990524 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2516 11:03:40.996966 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2517 11:03:41.000494 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2518 11:03:41.004071 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2519 11:03:41.006767 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2520 11:03:41.013885 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2521 11:03:41.016817 All bytes gating window > 1UI, Early break!
2522 11:03:41.016894
2523 11:03:41.020076 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 20)
2524 11:03:41.020151
2525 11:03:41.023009 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 24)
2526 11:03:41.023106
2527 11:03:41.023190
2528 11:03:41.023281
2529 11:03:41.026485 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
2530 11:03:41.026578
2531 11:03:41.032840 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 24)
2532 11:03:41.032934
2533 11:03:41.033028
2534 11:03:41.036567 wait MRW command Rank0 MR1 =0x56 fired (1)
2535 11:03:41.039553 Write Rank0 MR1 =0x56
2536 11:03:41.039649
2537 11:03:41.039741 best RODT dly(2T, 0.5T) = (2, 3)
2538 11:03:41.042721
2539 11:03:41.042823 best RODT dly(2T, 0.5T) = (2, 3)
2540 11:03:41.046183 ==
2541 11:03:41.049811 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2542 11:03:41.052989 fsp= 1, odt_onoff= 1, Byte mode= 0
2543 11:03:41.053092 ==
2544 11:03:41.056491 Start DQ dly to find pass range UseTestEngine =0
2545 11:03:41.059523 x-axis: bit #, y-axis: DQ dly (-127~63)
2546 11:03:41.062710 RX Vref Scan = 0
2547 11:03:41.065680 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2548 11:03:41.069119 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2549 11:03:41.072593 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2550 11:03:41.075848 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2551 11:03:41.075949 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2552 11:03:41.079023 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2553 11:03:41.082422 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2554 11:03:41.085323 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2555 11:03:41.088835 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2556 11:03:41.091934 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2557 11:03:41.095148 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2558 11:03:41.099420 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2559 11:03:41.101825 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2560 11:03:41.101924 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2561 11:03:41.105117 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2562 11:03:41.108222 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2563 11:03:41.111806 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2564 11:03:41.114795 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2565 11:03:41.118191 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2566 11:03:41.121554 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2567 11:03:41.124973 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2568 11:03:41.125070 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2569 11:03:41.128161 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2570 11:03:41.131566 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2571 11:03:41.134628 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2572 11:03:41.138308 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2573 11:03:41.141477 0, [0] xxxoxxxx xoxxxxxo [MSB]
2574 11:03:41.144709 1, [0] xxxoxxxx ooxxxxxo [MSB]
2575 11:03:41.144786 2, [0] xxxoxxxx ooxxxxxo [MSB]
2576 11:03:41.148278 3, [0] xxooxxxx oooxxxxo [MSB]
2577 11:03:41.151371 4, [0] xooooxxo ooooxxxo [MSB]
2578 11:03:41.154743 5, [0] xooooxxo oooooooo [MSB]
2579 11:03:41.157545 6, [0] xooooxxo oooooooo [MSB]
2580 11:03:41.161059 7, [0] xoooooxo oooooooo [MSB]
2581 11:03:41.164216 8, [0] xooooooo oooooooo [MSB]
2582 11:03:41.164319 32, [0] oooooooo ooooooox [MSB]
2583 11:03:41.167428 33, [0] oooxoooo ooooooox [MSB]
2584 11:03:41.170593 34, [0] oooxoooo ooooooox [MSB]
2585 11:03:41.174359 35, [0] oooxoooo xoooooox [MSB]
2586 11:03:41.177423 36, [0] ooxxoooo xxooooox [MSB]
2587 11:03:41.180626 37, [0] ooxxoooo xxooooox [MSB]
2588 11:03:41.184172 38, [0] ooxxooox xxooooox [MSB]
2589 11:03:41.184264 39, [0] xxxxxoox xxooxoox [MSB]
2590 11:03:41.187629 40, [0] xxxxxoox xxxoxoxx [MSB]
2591 11:03:41.190965 41, [0] xxxxxxxx xxxxxxxx [MSB]
2592 11:03:41.193934 iDelay=41, Bit 0, Center 23 (9 ~ 38) 30
2593 11:03:41.197187 iDelay=41, Bit 1, Center 21 (4 ~ 38) 35
2594 11:03:41.200697 iDelay=41, Bit 2, Center 19 (3 ~ 35) 33
2595 11:03:41.206852 iDelay=41, Bit 3, Center 16 (0 ~ 32) 33
2596 11:03:41.210206 iDelay=41, Bit 4, Center 21 (4 ~ 38) 35
2597 11:03:41.213685 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
2598 11:03:41.216876 iDelay=41, Bit 6, Center 24 (8 ~ 40) 33
2599 11:03:41.219890 iDelay=41, Bit 7, Center 20 (4 ~ 37) 34
2600 11:03:41.223125 iDelay=41, Bit 8, Center 17 (1 ~ 34) 34
2601 11:03:41.226697 iDelay=41, Bit 9, Center 17 (0 ~ 35) 36
2602 11:03:41.229992 iDelay=41, Bit 10, Center 21 (3 ~ 39) 37
2603 11:03:41.233076 iDelay=41, Bit 11, Center 22 (4 ~ 40) 37
2604 11:03:41.236173 iDelay=41, Bit 12, Center 21 (5 ~ 38) 34
2605 11:03:41.239718 iDelay=41, Bit 13, Center 22 (5 ~ 40) 36
2606 11:03:41.245903 iDelay=41, Bit 14, Center 22 (5 ~ 39) 35
2607 11:03:41.249517 iDelay=41, Bit 15, Center 14 (-3 ~ 31) 35
2608 11:03:41.249607 ==
2609 11:03:41.252670 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2610 11:03:41.256362 fsp= 1, odt_onoff= 1, Byte mode= 0
2611 11:03:41.256438 ==
2612 11:03:41.259472 DQS Delay:
2613 11:03:41.259548 DQS0 = 0, DQS1 = 0
2614 11:03:41.259623 DQM Delay:
2615 11:03:41.263345 DQM0 = 20, DQM1 = 19
2616 11:03:41.263420 DQ Delay:
2617 11:03:41.265932 DQ0 =23, DQ1 =21, DQ2 =19, DQ3 =16
2618 11:03:41.268949 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =20
2619 11:03:41.272668 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =22
2620 11:03:41.275888 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =14
2621 11:03:41.275963
2622 11:03:41.276037
2623 11:03:41.279149 DramC Write-DBI off
2624 11:03:41.279224 ==
2625 11:03:41.285383 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2626 11:03:41.285482 fsp= 1, odt_onoff= 1, Byte mode= 0
2627 11:03:41.288768 ==
2628 11:03:41.291765 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2629 11:03:41.291832
2630 11:03:41.295007 Begin, DQ Scan Range 929~1185
2631 11:03:41.295079
2632 11:03:41.295153
2633 11:03:41.295208 TX Vref Scan disable
2634 11:03:41.301964 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2635 11:03:41.305569 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2636 11:03:41.308365 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2637 11:03:41.311392 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2638 11:03:41.315616 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2639 11:03:41.318656 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2640 11:03:41.321537 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2641 11:03:41.325142 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2642 11:03:41.328667 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2643 11:03:41.331436 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2644 11:03:41.335056 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2645 11:03:41.338297 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2646 11:03:41.341377 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2647 11:03:41.344552 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2648 11:03:41.350950 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2649 11:03:41.354328 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2650 11:03:41.357431 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2651 11:03:41.361254 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2652 11:03:41.364417 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2653 11:03:41.367652 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2654 11:03:41.370498 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2655 11:03:41.373996 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2656 11:03:41.378018 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2657 11:03:41.380796 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2658 11:03:41.384023 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2659 11:03:41.387025 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2660 11:03:41.390536 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2661 11:03:41.397463 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2662 11:03:41.400644 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2663 11:03:41.403651 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2664 11:03:41.406904 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2665 11:03:41.410238 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2666 11:03:41.413672 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2667 11:03:41.416867 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2668 11:03:41.419996 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2669 11:03:41.423248 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2670 11:03:41.426400 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2671 11:03:41.429786 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2672 11:03:41.432902 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2673 11:03:41.436265 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2674 11:03:41.439762 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2675 11:03:41.443057 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2676 11:03:41.449343 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2677 11:03:41.452575 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2678 11:03:41.456110 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2679 11:03:41.459294 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2680 11:03:41.463161 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2681 11:03:41.465909 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2682 11:03:41.468979 977 |3 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2683 11:03:41.472435 978 |3 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2684 11:03:41.475859 979 |3 6 19|[0] xxxxxxxx xxxxxxxx [MSB]
2685 11:03:41.478898 980 |3 6 20|[0] xxxxxxxx oxxxxxxo [MSB]
2686 11:03:41.482553 981 |3 6 21|[0] xxxxxxxx ooxxxxxo [MSB]
2687 11:03:41.485428 982 |3 6 22|[0] xxxxxxxx ooxxxxxo [MSB]
2688 11:03:41.488946 983 |3 6 23|[0] xxxxxxxx oooxxxxo [MSB]
2689 11:03:41.492153 984 |3 6 24|[0] xooooxoo oooooxoo [MSB]
2690 11:03:41.500423 995 |3 6 35|[0] oooooooo ooooooox [MSB]
2691 11:03:41.503604 996 |3 6 36|[0] oooooooo ooooooox [MSB]
2692 11:03:41.506781 997 |3 6 37|[0] oooooooo ooooooox [MSB]
2693 11:03:41.510700 998 |3 6 38|[0] oooooooo ooooooox [MSB]
2694 11:03:41.513608 999 |3 6 39|[0] oooooooo oxooooox [MSB]
2695 11:03:41.516749 1000 |3 6 40|[0] oooooooo xxooooox [MSB]
2696 11:03:41.520155 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
2697 11:03:41.523413 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2698 11:03:41.526246 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2699 11:03:41.529783 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
2700 11:03:41.536607 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB]
2701 11:03:41.539746 1006 |3 6 46|[0] ooxxooox xxxxxxxx [MSB]
2702 11:03:41.542809 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2703 11:03:41.545932 Byte0, DQ PI dly=993, DQM PI dly= 993
2704 11:03:41.549640 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
2705 11:03:41.549719
2706 11:03:41.552803 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
2707 11:03:41.552881
2708 11:03:41.556022 Byte1, DQ PI dly=989, DQM PI dly= 989
2709 11:03:41.562674 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
2710 11:03:41.562787
2711 11:03:41.566154 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
2712 11:03:41.566259
2713 11:03:41.566347 ==
2714 11:03:41.572323 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2715 11:03:41.576117 fsp= 1, odt_onoff= 1, Byte mode= 0
2716 11:03:41.576196 ==
2717 11:03:41.579374 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2718 11:03:41.579451
2719 11:03:41.582424 Begin, DQ Scan Range 965~1029
2720 11:03:41.585602 Write Rank0 MR14 =0x0
2721 11:03:41.592294
2722 11:03:41.592371 CH=1, VrefRange= 0, VrefLevel = 0
2723 11:03:41.599061 TX Bit0 (986~1003) 18 994, Bit8 (984~994) 11 989,
2724 11:03:41.601870 TX Bit1 (985~1002) 18 993, Bit9 (984~993) 10 988,
2725 11:03:41.609069 TX Bit2 (984~998) 15 991, Bit10 (986~998) 13 992,
2726 11:03:41.611552 TX Bit3 (984~995) 12 989, Bit11 (987~997) 11 992,
2727 11:03:41.615019 TX Bit4 (985~1001) 17 993, Bit12 (986~997) 12 991,
2728 11:03:41.622399 TX Bit5 (986~1002) 17 994, Bit13 (987~996) 10 991,
2729 11:03:41.625133 TX Bit6 (986~1002) 17 994, Bit14 (986~994) 9 990,
2730 11:03:41.631477 TX Bit7 (986~999) 14 992, Bit15 (981~989) 9 985,
2731 11:03:41.631560
2732 11:03:41.631620 Write Rank0 MR14 =0x2
2733 11:03:41.640711
2734 11:03:41.640793 CH=1, VrefRange= 0, VrefLevel = 2
2735 11:03:41.647085 TX Bit0 (986~1004) 19 995, Bit8 (983~995) 13 989,
2736 11:03:41.650216 TX Bit1 (985~1002) 18 993, Bit9 (984~994) 11 989,
2737 11:03:41.656945 TX Bit2 (984~998) 15 991, Bit10 (985~999) 15 992,
2738 11:03:41.660096 TX Bit3 (983~996) 14 989, Bit11 (986~998) 13 992,
2739 11:03:41.663162 TX Bit4 (986~1002) 17 994, Bit12 (986~997) 12 991,
2740 11:03:41.669755 TX Bit5 (986~1003) 18 994, Bit13 (987~997) 11 992,
2741 11:03:41.673751 TX Bit6 (986~1003) 18 994, Bit14 (986~995) 10 990,
2742 11:03:41.679886 TX Bit7 (986~1000) 15 993, Bit15 (980~990) 11 985,
2743 11:03:41.679968
2744 11:03:41.680027 Write Rank0 MR14 =0x4
2745 11:03:41.689365
2746 11:03:41.689448 CH=1, VrefRange= 0, VrefLevel = 4
2747 11:03:41.695430 TX Bit0 (986~1004) 19 995, Bit8 (983~995) 13 989,
2748 11:03:41.698980 TX Bit1 (985~1003) 19 994, Bit9 (983~994) 12 988,
2749 11:03:41.705378 TX Bit2 (984~1000) 17 992, Bit10 (985~1000) 16 992,
2750 11:03:41.708717 TX Bit3 (983~997) 15 990, Bit11 (986~1000) 15 993,
2751 11:03:41.715090 TX Bit4 (985~1003) 19 994, Bit12 (986~999) 14 992,
2752 11:03:41.718271 TX Bit5 (986~1004) 19 995, Bit13 (986~999) 14 992,
2753 11:03:41.721793 TX Bit6 (985~1004) 20 994, Bit14 (986~996) 11 991,
2754 11:03:41.728392 TX Bit7 (985~1001) 17 993, Bit15 (980~992) 13 986,
2755 11:03:41.728474
2756 11:03:41.728535 Write Rank0 MR14 =0x6
2757 11:03:41.738467
2758 11:03:41.738555 CH=1, VrefRange= 0, VrefLevel = 6
2759 11:03:41.744488 TX Bit0 (986~1005) 20 995, Bit8 (983~996) 14 989,
2760 11:03:41.747966 TX Bit1 (985~1005) 21 995, Bit9 (983~995) 13 989,
2761 11:03:41.754538 TX Bit2 (984~1000) 17 992, Bit10 (985~1000) 16 992,
2762 11:03:41.757651 TX Bit3 (982~998) 17 990, Bit11 (986~1000) 15 993,
2763 11:03:41.764697 TX Bit4 (985~1004) 20 994, Bit12 (985~1000) 16 992,
2764 11:03:41.768055 TX Bit5 (986~1005) 20 995, Bit13 (986~1000) 15 993,
2765 11:03:41.770677 TX Bit6 (985~1005) 21 995, Bit14 (986~997) 12 991,
2766 11:03:41.777562 TX Bit7 (985~1002) 18 993, Bit15 (979~992) 14 985,
2767 11:03:41.777648
2768 11:03:41.780513 Write Rank0 MR14 =0x8
2769 11:03:41.787809
2770 11:03:41.787894 CH=1, VrefRange= 0, VrefLevel = 8
2771 11:03:41.793947 TX Bit0 (985~1006) 22 995, Bit8 (982~996) 15 989,
2772 11:03:41.797279 TX Bit1 (985~1005) 21 995, Bit9 (982~995) 14 988,
2773 11:03:41.803948 TX Bit2 (983~1001) 19 992, Bit10 (985~1001) 17 993,
2774 11:03:41.806991 TX Bit3 (982~999) 18 990, Bit11 (986~1000) 15 993,
2775 11:03:41.814145 TX Bit4 (985~1005) 21 995, Bit12 (985~1000) 16 992,
2776 11:03:41.817399 TX Bit5 (985~1005) 21 995, Bit13 (986~1000) 15 993,
2777 11:03:41.820501 TX Bit6 (985~1005) 21 995, Bit14 (985~998) 14 991,
2778 11:03:41.827427 TX Bit7 (985~1003) 19 994, Bit15 (979~993) 15 986,
2779 11:03:41.827553
2780 11:03:41.830317 Write Rank0 MR14 =0xa
2781 11:03:41.836858
2782 11:03:41.839915 CH=1, VrefRange= 0, VrefLevel = 10
2783 11:03:41.843698 TX Bit0 (985~1006) 22 995, Bit8 (981~996) 16 988,
2784 11:03:41.846596 TX Bit1 (984~1005) 22 994, Bit9 (982~996) 15 989,
2785 11:03:41.853620 TX Bit2 (983~1002) 20 992, Bit10 (984~1001) 18 992,
2786 11:03:41.856673 TX Bit3 (982~999) 18 990, Bit11 (986~1001) 16 993,
2787 11:03:41.862886 TX Bit4 (985~1005) 21 995, Bit12 (985~1001) 17 993,
2788 11:03:41.866473 TX Bit5 (985~1005) 21 995, Bit13 (986~1001) 16 993,
2789 11:03:41.869397 TX Bit6 (985~1005) 21 995, Bit14 (985~998) 14 991,
2790 11:03:41.876098 TX Bit7 (985~1004) 20 994, Bit15 (979~993) 15 986,
2791 11:03:41.876197
2792 11:03:41.879228 Write Rank0 MR14 =0xc
2793 11:03:41.886355
2794 11:03:41.889411 CH=1, VrefRange= 0, VrefLevel = 12
2795 11:03:41.893131 TX Bit0 (985~1007) 23 996, Bit8 (982~997) 16 989,
2796 11:03:41.896395 TX Bit1 (984~1006) 23 995, Bit9 (982~997) 16 989,
2797 11:03:41.902894 TX Bit2 (983~1003) 21 993, Bit10 (984~1001) 18 992,
2798 11:03:41.906560 TX Bit3 (981~1000) 20 990, Bit11 (985~1001) 17 993,
2799 11:03:41.912852 TX Bit4 (984~1005) 22 994, Bit12 (985~1001) 17 993,
2800 11:03:41.915791 TX Bit5 (985~1006) 22 995, Bit13 (986~1001) 16 993,
2801 11:03:41.919102 TX Bit6 (985~1006) 22 995, Bit14 (985~1000) 16 992,
2802 11:03:41.926159 TX Bit7 (985~1005) 21 995, Bit15 (978~994) 17 986,
2803 11:03:41.926285
2804 11:03:41.928766 Write Rank0 MR14 =0xe
2805 11:03:41.936375
2806 11:03:41.939589 CH=1, VrefRange= 0, VrefLevel = 14
2807 11:03:41.942630 TX Bit0 (985~1007) 23 996, Bit8 (981~998) 18 989,
2808 11:03:41.945715 TX Bit1 (984~1006) 23 995, Bit9 (981~997) 17 989,
2809 11:03:41.952521 TX Bit2 (983~1003) 21 993, Bit10 (984~1002) 19 993,
2810 11:03:41.955741 TX Bit3 (981~1000) 20 990, Bit11 (985~1002) 18 993,
2811 11:03:41.962533 TX Bit4 (984~1005) 22 994, Bit12 (985~1001) 17 993,
2812 11:03:41.965501 TX Bit5 (985~1006) 22 995, Bit13 (985~1001) 17 993,
2813 11:03:41.972604 TX Bit6 (985~1006) 22 995, Bit14 (985~1000) 16 992,
2814 11:03:41.975710 TX Bit7 (984~1005) 22 994, Bit15 (978~994) 17 986,
2815 11:03:41.975848
2816 11:03:41.978604 Write Rank0 MR14 =0x10
2817 11:03:41.985944
2818 11:03:41.989447 CH=1, VrefRange= 0, VrefLevel = 16
2819 11:03:41.992318 TX Bit0 (985~1007) 23 996, Bit8 (980~1000) 21 990,
2820 11:03:41.996029 TX Bit1 (984~1006) 23 995, Bit9 (981~999) 19 990,
2821 11:03:42.002260 TX Bit2 (983~1004) 22 993, Bit10 (983~1002) 20 992,
2822 11:03:42.005495 TX Bit3 (980~1001) 22 990, Bit11 (985~1002) 18 993,
2823 11:03:42.012070 TX Bit4 (984~1006) 23 995, Bit12 (984~1002) 19 993,
2824 11:03:42.015912 TX Bit5 (985~1006) 22 995, Bit13 (985~1001) 17 993,
2825 11:03:42.021902 TX Bit6 (985~1006) 22 995, Bit14 (984~1001) 18 992,
2826 11:03:42.025271 TX Bit7 (984~1005) 22 994, Bit15 (978~995) 18 986,
2827 11:03:42.025359
2828 11:03:42.028858 Write Rank0 MR14 =0x12
2829 11:03:42.036131
2830 11:03:42.039230 CH=1, VrefRange= 0, VrefLevel = 18
2831 11:03:42.042387 TX Bit0 (985~1007) 23 996, Bit8 (980~1000) 21 990,
2832 11:03:42.046038 TX Bit1 (984~1006) 23 995, Bit9 (980~999) 20 989,
2833 11:03:42.052633 TX Bit2 (982~1005) 24 993, Bit10 (983~1002) 20 992,
2834 11:03:42.055531 TX Bit3 (980~1002) 23 991, Bit11 (985~1002) 18 993,
2835 11:03:42.062539 TX Bit4 (984~1006) 23 995, Bit12 (984~1002) 19 993,
2836 11:03:42.065226 TX Bit5 (985~1006) 22 995, Bit13 (985~1002) 18 993,
2837 11:03:42.071905 TX Bit6 (984~1006) 23 995, Bit14 (984~1001) 18 992,
2838 11:03:42.075556 TX Bit7 (984~1006) 23 995, Bit15 (978~995) 18 986,
2839 11:03:42.075629
2840 11:03:42.078372 Write Rank0 MR14 =0x14
2841 11:03:42.086558
2842 11:03:42.088992 CH=1, VrefRange= 0, VrefLevel = 20
2843 11:03:42.092761 TX Bit0 (985~1008) 24 996, Bit8 (981~1000) 20 990,
2844 11:03:42.095653 TX Bit1 (984~1007) 24 995, Bit9 (980~1000) 21 990,
2845 11:03:42.102086 TX Bit2 (982~1006) 25 994, Bit10 (983~1003) 21 993,
2846 11:03:42.106312 TX Bit3 (979~1002) 24 990, Bit11 (985~1003) 19 994,
2847 11:03:42.112389 TX Bit4 (984~1006) 23 995, Bit12 (984~1002) 19 993,
2848 11:03:42.115360 TX Bit5 (985~1007) 23 996, Bit13 (985~1002) 18 993,
2849 11:03:42.122315 TX Bit6 (984~1007) 24 995, Bit14 (984~1001) 18 992,
2850 11:03:42.125282 TX Bit7 (984~1006) 23 995, Bit15 (977~995) 19 986,
2851 11:03:42.125360
2852 11:03:42.128563 Write Rank0 MR14 =0x16
2853 11:03:42.136226
2854 11:03:42.139290 CH=1, VrefRange= 0, VrefLevel = 22
2855 11:03:42.143094 TX Bit0 (985~1008) 24 996, Bit8 (979~1001) 23 990,
2856 11:03:42.145830 TX Bit1 (984~1007) 24 995, Bit9 (980~1000) 21 990,
2857 11:03:42.152434 TX Bit2 (981~1005) 25 993, Bit10 (983~1003) 21 993,
2858 11:03:42.156023 TX Bit3 (979~1003) 25 991, Bit11 (984~1003) 20 993,
2859 11:03:42.162294 TX Bit4 (984~1007) 24 995, Bit12 (984~1003) 20 993,
2860 11:03:42.165373 TX Bit5 (984~1007) 24 995, Bit13 (985~1003) 19 994,
2861 11:03:42.172241 TX Bit6 (984~1007) 24 995, Bit14 (984~1002) 19 993,
2862 11:03:42.175298 TX Bit7 (984~1006) 23 995, Bit15 (978~996) 19 987,
2863 11:03:42.175391
2864 11:03:42.179131 Write Rank0 MR14 =0x18
2865 11:03:42.186724
2866 11:03:42.190020 CH=1, VrefRange= 0, VrefLevel = 24
2867 11:03:42.192926 TX Bit0 (984~1009) 26 996, Bit8 (979~1001) 23 990,
2868 11:03:42.196148 TX Bit1 (983~1008) 26 995, Bit9 (979~1000) 22 989,
2869 11:03:42.203318 TX Bit2 (981~1006) 26 993, Bit10 (982~1003) 22 992,
2870 11:03:42.206466 TX Bit3 (979~1003) 25 991, Bit11 (983~1004) 22 993,
2871 11:03:42.213031 TX Bit4 (983~1007) 25 995, Bit12 (983~1003) 21 993,
2872 11:03:42.216256 TX Bit5 (984~1008) 25 996, Bit13 (985~1003) 19 994,
2873 11:03:42.222434 TX Bit6 (984~1007) 24 995, Bit14 (983~1002) 20 992,
2874 11:03:42.226143 TX Bit7 (984~1006) 23 995, Bit15 (977~997) 21 987,
2875 11:03:42.226215
2876 11:03:42.229131 Write Rank0 MR14 =0x1a
2877 11:03:42.237633
2878 11:03:42.240377 CH=1, VrefRange= 0, VrefLevel = 26
2879 11:03:42.243552 TX Bit0 (984~1009) 26 996, Bit8 (979~1001) 23 990,
2880 11:03:42.246824 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2881 11:03:42.253340 TX Bit2 (981~1006) 26 993, Bit10 (981~1003) 23 992,
2882 11:03:42.256431 TX Bit3 (979~1004) 26 991, Bit11 (983~1004) 22 993,
2883 11:03:42.263117 TX Bit4 (983~1008) 26 995, Bit12 (983~1004) 22 993,
2884 11:03:42.266575 TX Bit5 (984~1008) 25 996, Bit13 (984~1003) 20 993,
2885 11:03:42.272948 TX Bit6 (984~1008) 25 996, Bit14 (983~1002) 20 992,
2886 11:03:42.276222 TX Bit7 (984~1007) 24 995, Bit15 (976~998) 23 987,
2887 11:03:42.276302
2888 11:03:42.279673 Write Rank0 MR14 =0x1c
2889 11:03:42.287311
2890 11:03:42.290500 CH=1, VrefRange= 0, VrefLevel = 28
2891 11:03:42.293621 TX Bit0 (984~1009) 26 996, Bit8 (979~1002) 24 990,
2892 11:03:42.296761 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2893 11:03:42.303577 TX Bit2 (980~1006) 27 993, Bit10 (982~1003) 22 992,
2894 11:03:42.306849 TX Bit3 (978~1005) 28 991, Bit11 (982~1004) 23 993,
2895 11:03:42.313421 TX Bit4 (984~1008) 25 996, Bit12 (983~1004) 22 993,
2896 11:03:42.316743 TX Bit5 (984~1008) 25 996, Bit13 (984~1004) 21 994,
2897 11:03:42.323124 TX Bit6 (983~1008) 26 995, Bit14 (982~1003) 22 992,
2898 11:03:42.326265 TX Bit7 (983~1007) 25 995, Bit15 (976~998) 23 987,
2899 11:03:42.326343
2900 11:03:42.329510 Write Rank0 MR14 =0x1e
2901 11:03:42.337627
2902 11:03:42.340951 CH=1, VrefRange= 0, VrefLevel = 30
2903 11:03:42.343953 TX Bit0 (984~1009) 26 996, Bit8 (979~1002) 24 990,
2904 11:03:42.347236 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2905 11:03:42.354216 TX Bit2 (980~1006) 27 993, Bit10 (982~1003) 22 992,
2906 11:03:42.357510 TX Bit3 (978~1005) 28 991, Bit11 (982~1004) 23 993,
2907 11:03:42.364104 TX Bit4 (984~1008) 25 996, Bit12 (983~1004) 22 993,
2908 11:03:42.367122 TX Bit5 (984~1008) 25 996, Bit13 (984~1004) 21 994,
2909 11:03:42.373491 TX Bit6 (983~1008) 26 995, Bit14 (982~1003) 22 992,
2910 11:03:42.376669 TX Bit7 (983~1007) 25 995, Bit15 (976~998) 23 987,
2911 11:03:42.376748
2912 11:03:42.380235 Write Rank0 MR14 =0x20
2913 11:03:42.387813
2914 11:03:42.391054 CH=1, VrefRange= 0, VrefLevel = 32
2915 11:03:42.394204 TX Bit0 (984~1009) 26 996, Bit8 (979~1002) 24 990,
2916 11:03:42.397550 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2917 11:03:42.404201 TX Bit2 (980~1006) 27 993, Bit10 (982~1003) 22 992,
2918 11:03:42.407583 TX Bit3 (978~1005) 28 991, Bit11 (982~1004) 23 993,
2919 11:03:42.413891 TX Bit4 (984~1008) 25 996, Bit12 (983~1004) 22 993,
2920 11:03:42.417876 TX Bit5 (984~1008) 25 996, Bit13 (984~1004) 21 994,
2921 11:03:42.423917 TX Bit6 (983~1008) 26 995, Bit14 (982~1003) 22 992,
2922 11:03:42.427259 TX Bit7 (983~1007) 25 995, Bit15 (976~998) 23 987,
2923 11:03:42.427337
2924 11:03:42.430780 Write Rank0 MR14 =0x22
2925 11:03:42.438231
2926 11:03:42.441786 CH=1, VrefRange= 0, VrefLevel = 34
2927 11:03:42.444683 TX Bit0 (984~1009) 26 996, Bit8 (979~1002) 24 990,
2928 11:03:42.447930 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2929 11:03:42.454730 TX Bit2 (980~1006) 27 993, Bit10 (982~1003) 22 992,
2930 11:03:42.458162 TX Bit3 (978~1005) 28 991, Bit11 (982~1004) 23 993,
2931 11:03:42.464368 TX Bit4 (984~1008) 25 996, Bit12 (983~1004) 22 993,
2932 11:03:42.467587 TX Bit5 (984~1008) 25 996, Bit13 (984~1004) 21 994,
2933 11:03:42.473965 TX Bit6 (983~1008) 26 995, Bit14 (982~1003) 22 992,
2934 11:03:42.477681 TX Bit7 (983~1007) 25 995, Bit15 (976~998) 23 987,
2935 11:03:42.477760
2936 11:03:42.477819
2937 11:03:42.480970 TX Vref found, early break! 366< 368
2938 11:03:42.487455 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2939 11:03:42.487534 u1DelayCellOfst[0]=6 cells (5 PI)
2940 11:03:42.490780 u1DelayCellOfst[1]=5 cells (4 PI)
2941 11:03:42.493957 u1DelayCellOfst[2]=2 cells (2 PI)
2942 11:03:42.497393 u1DelayCellOfst[3]=0 cells (0 PI)
2943 11:03:42.500890 u1DelayCellOfst[4]=6 cells (5 PI)
2944 11:03:42.503915 u1DelayCellOfst[5]=6 cells (5 PI)
2945 11:03:42.507763 u1DelayCellOfst[6]=5 cells (4 PI)
2946 11:03:42.510884 u1DelayCellOfst[7]=5 cells (4 PI)
2947 11:03:42.514137 Byte0, DQ PI dly=991, DQM PI dly= 993
2948 11:03:42.516912 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
2949 11:03:42.517006
2950 11:03:42.524006 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
2951 11:03:42.524099
2952 11:03:42.526704 u1DelayCellOfst[8]=3 cells (3 PI)
2953 11:03:42.530390 u1DelayCellOfst[9]=3 cells (3 PI)
2954 11:03:42.530499 u1DelayCellOfst[10]=6 cells (5 PI)
2955 11:03:42.533054 u1DelayCellOfst[11]=7 cells (6 PI)
2956 11:03:42.536929 u1DelayCellOfst[12]=7 cells (6 PI)
2957 11:03:42.539984 u1DelayCellOfst[13]=9 cells (7 PI)
2958 11:03:42.542949 u1DelayCellOfst[14]=6 cells (5 PI)
2959 11:03:42.546477 u1DelayCellOfst[15]=0 cells (0 PI)
2960 11:03:42.549697 Byte1, DQ PI dly=987, DQM PI dly= 990
2961 11:03:42.556016 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
2962 11:03:42.556124
2963 11:03:42.559291 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
2964 11:03:42.559385
2965 11:03:42.562449 Write Rank0 MR14 =0x1c
2966 11:03:42.562517
2967 11:03:42.562574 Final TX Range 0 Vref 28
2968 11:03:42.562709
2969 11:03:42.569446 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2970 11:03:42.569518
2971 11:03:42.575820 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2972 11:03:42.585715 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2973 11:03:42.591766 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2974 11:03:42.591848 Write Rank0 MR3 =0xb0
2975 11:03:42.595199 DramC Write-DBI on
2976 11:03:42.595264 ==
2977 11:03:42.598200 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2978 11:03:42.601942 fsp= 1, odt_onoff= 1, Byte mode= 0
2979 11:03:42.604859 ==
2980 11:03:42.608473 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2981 11:03:42.608568
2982 11:03:42.611766 Begin, DQ Scan Range 710~774
2983 11:03:42.611833
2984 11:03:42.611890
2985 11:03:42.611941 TX Vref Scan disable
2986 11:03:42.614797 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2987 11:03:42.618116 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2988 11:03:42.624927 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2989 11:03:42.628567 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2990 11:03:42.631440 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2991 11:03:42.634921 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2992 11:03:42.637676 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2993 11:03:42.640851 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2994 11:03:42.644758 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2995 11:03:42.647671 719 |2 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2996 11:03:42.651114 720 |2 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2997 11:03:42.654012 721 |2 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2998 11:03:42.657781 722 |2 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2999 11:03:42.660979 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3000 11:03:42.663881 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3001 11:03:42.667327 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3002 11:03:42.673913 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3003 11:03:42.677008 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3004 11:03:42.683890 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3005 11:03:42.687341 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3006 11:03:42.690443 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3007 11:03:42.693611 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3008 11:03:42.697542 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3009 11:03:42.700418 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3010 11:03:42.703810 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
3011 11:03:42.707276 754 |2 6 50|[0] xxxxxxxx xxxxxxxx [MSB]
3012 11:03:42.710614 Byte0, DQ PI dly=740, DQM PI dly= 740
3013 11:03:42.713608 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 36)
3014 11:03:42.713707
3015 11:03:42.720029 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 36)
3016 11:03:42.720136
3017 11:03:42.723176 Byte1, DQ PI dly=734, DQM PI dly= 734
3018 11:03:42.726995 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
3019 11:03:42.727127
3020 11:03:42.733166 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
3021 11:03:42.733307
3022 11:03:42.740105 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3023 11:03:42.746569 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3024 11:03:42.753436 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3025 11:03:42.753558 Write Rank0 MR3 =0x30
3026 11:03:42.756166 DramC Write-DBI off
3027 11:03:42.756291
3028 11:03:42.756407 [DATLAT]
3029 11:03:42.759468 Freq=1600, CH1 RK0, use_rxtx_scan=0
3030 11:03:42.759594
3031 11:03:42.762972 DATLAT Default: 0xf
3032 11:03:42.763101 7, 0xFFFF, sum=0
3033 11:03:42.765987 8, 0xFFFF, sum=0
3034 11:03:42.766103 9, 0xFFFF, sum=0
3035 11:03:42.769656 10, 0xFFFF, sum=0
3036 11:03:42.769757 11, 0xFFFF, sum=0
3037 11:03:42.772818 12, 0xFFFF, sum=0
3038 11:03:42.772924 13, 0xFFFF, sum=0
3039 11:03:42.776469 14, 0x0, sum=1
3040 11:03:42.776575 15, 0x0, sum=2
3041 11:03:42.779400 16, 0x0, sum=3
3042 11:03:42.779516 17, 0x0, sum=4
3043 11:03:42.782499 pattern=2 first_step=14 total pass=5 best_step=16
3044 11:03:42.782622 ==
3045 11:03:42.789376 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3046 11:03:42.792363 fsp= 1, odt_onoff= 1, Byte mode= 0
3047 11:03:42.792495 ==
3048 11:03:42.795505 Start DQ dly to find pass range UseTestEngine =1
3049 11:03:42.799284 x-axis: bit #, y-axis: DQ dly (-127~63)
3050 11:03:42.802468 RX Vref Scan = 1
3051 11:03:42.916320
3052 11:03:42.916459 RX Vref found, early break!
3053 11:03:42.916550
3054 11:03:42.922889 Final RX Vref 11, apply to both rank0 and 1
3055 11:03:42.923002 ==
3056 11:03:42.926143 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3057 11:03:42.929523 fsp= 1, odt_onoff= 1, Byte mode= 0
3058 11:03:42.929715 ==
3059 11:03:42.932539 DQS Delay:
3060 11:03:42.932654 DQS0 = 0, DQS1 = 0
3061 11:03:42.932738 DQM Delay:
3062 11:03:42.936221 DQM0 = 20, DQM1 = 19
3063 11:03:42.936328 DQ Delay:
3064 11:03:42.939591 DQ0 =22, DQ1 =20, DQ2 =19, DQ3 =16
3065 11:03:42.942513 DQ4 =20, DQ5 =22, DQ6 =24, DQ7 =21
3066 11:03:42.945843 DQ8 =17, DQ9 =17, DQ10 =20, DQ11 =21
3067 11:03:42.949336 DQ12 =22, DQ13 =21, DQ14 =22, DQ15 =14
3068 11:03:42.949465
3069 11:03:42.949557
3070 11:03:42.949642
3071 11:03:42.952593 [DramC_TX_OE_Calibration] TA2
3072 11:03:42.955818 Original DQ_B0 (3 6) =30, OEN = 27
3073 11:03:42.958923 Original DQ_B1 (3 6) =30, OEN = 27
3074 11:03:42.962254 23, 0x0, End_B0=23 End_B1=23
3075 11:03:42.965403 24, 0x0, End_B0=24 End_B1=24
3076 11:03:42.965530 25, 0x0, End_B0=25 End_B1=25
3077 11:03:42.968964 26, 0x0, End_B0=26 End_B1=26
3078 11:03:42.972037 27, 0x0, End_B0=27 End_B1=27
3079 11:03:42.975031 28, 0x0, End_B0=28 End_B1=28
3080 11:03:42.978529 29, 0x0, End_B0=29 End_B1=29
3081 11:03:42.978626 30, 0x0, End_B0=30 End_B1=30
3082 11:03:42.981901 31, 0xFFFF, End_B0=30 End_B1=30
3083 11:03:42.988741 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3084 11:03:42.994903 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3085 11:03:42.994998
3086 11:03:42.995080
3087 11:03:42.995163 Write Rank0 MR23 =0x3f
3088 11:03:42.998540 [DQSOSC]
3089 11:03:43.004711 [DQSOSCAuto] RK0, (LSB)MR18= 0xabab, (MSB)MR19= 0x202, tDQSOscB0 = 461 ps tDQSOscB1 = 461 ps
3090 11:03:43.011229 CH1_RK0: MR19=0x202, MR18=0xABAB, DQSOSC=461, MR23=63, INC=11, DEC=17
3091 11:03:43.014813 Write Rank0 MR23 =0x3f
3092 11:03:43.014913 [DQSOSC]
3093 11:03:43.020973 [DQSOSCAuto] RK0, (LSB)MR18= 0xafaf, (MSB)MR19= 0x202, tDQSOscB0 = 458 ps tDQSOscB1 = 458 ps
3094 11:03:43.024454 CH1 RK0: MR19=202, MR18=AFAF
3095 11:03:43.027674 [RankSwap] Rank num 2, (Multi 1), Rank 1
3096 11:03:43.030893 Write Rank0 MR2 =0xad
3097 11:03:43.031028 [Write Leveling]
3098 11:03:43.034649 delay byte0 byte1 byte2 byte3
3099 11:03:43.034736
3100 11:03:43.037997 10 0 0
3101 11:03:43.038143 11 0 0
3102 11:03:43.038246 12 0 0
3103 11:03:43.040888 13 0 0
3104 11:03:43.040967 14 0 0
3105 11:03:43.044662 15 0 0
3106 11:03:43.044758 16 0 0
3107 11:03:43.047872 17 0 0
3108 11:03:43.047952 18 0 0
3109 11:03:43.048013 19 0 0
3110 11:03:43.051091 20 0 0
3111 11:03:43.051168 21 0 0
3112 11:03:43.053949 22 0 0
3113 11:03:43.054082 23 0 0
3114 11:03:43.057287 24 0 0
3115 11:03:43.057399 25 0 0
3116 11:03:43.057493 26 0 0
3117 11:03:43.060521 27 0 0
3118 11:03:43.060648 28 0 0
3119 11:03:43.063709 29 0 ff
3120 11:03:43.063824 30 0 ff
3121 11:03:43.066982 31 0 ff
3122 11:03:43.067090 32 0 ff
3123 11:03:43.067177 33 ff ff
3124 11:03:43.070693 34 ff ff
3125 11:03:43.070794 35 ff ff
3126 11:03:43.073916 36 ff ff
3127 11:03:43.074077 37 ff ff
3128 11:03:43.077149 38 ff ff
3129 11:03:43.077252 39 ff ff
3130 11:03:43.083598 pass bytecount = 0xff (0xff: all bytes pass)
3131 11:03:43.083707
3132 11:03:43.083799 DQS0 dly: 33
3133 11:03:43.083908 DQS1 dly: 29
3134 11:03:43.087128 Write Rank0 MR2 =0x2d
3135 11:03:43.089874 [RankSwap] Rank num 2, (Multi 1), Rank 0
3136 11:03:43.093538 Write Rank1 MR1 =0xd6
3137 11:03:43.093665 [Gating]
3138 11:03:43.093769 ==
3139 11:03:43.100154 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3140 11:03:43.100276 fsp= 1, odt_onoff= 1, Byte mode= 0
3141 11:03:43.103012 ==
3142 11:03:43.106591 3 1 0 |2c2b 3535 |(11 11)(0 0) |(1 1)(0 0)| 0
3143 11:03:43.109786 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3144 11:03:43.113056 3 1 8 |2c2b 3534 |(11 11)(1 1) |(1 1)(0 0)| 0
3145 11:03:43.119504 3 1 12 |2c2b 909 |(11 11)(1 1) |(0 0)(0 0)| 0
3146 11:03:43.122976 3 1 16 |2c2b e0d |(11 11)(11 11) |(1 0)(0 0)| 0
3147 11:03:43.126315 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
3148 11:03:43.133184 3 1 24 |2c2b 3737 |(11 11)(0 0) |(1 0)(1 1)| 0
3149 11:03:43.140270 3 1 28 |2c2b 2f2e |(11 11)(11 11) |(1 0)(1 1)| 0
3150 11:03:43.140576 3 2 0 |2c2b 202 |(11 11)(11 11) |(1 0)(0 0)| 0
3151 11:03:43.146060 3 2 4 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 0)| 0
3152 11:03:43.149423 3 2 8 |2c2b 2626 |(11 11)(1 1) |(1 0)(1 1)| 0
3153 11:03:43.152309 3 2 12 |2c2b 3232 |(11 11)(11 11) |(1 0)(1 1)| 0
3154 11:03:43.155610 [Byte 1] Lead/lag Transition tap number (1)
3155 11:03:43.162256 3 2 16 |2222 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
3156 11:03:43.165833 3 2 20 |303 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
3157 11:03:43.169045 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
3158 11:03:43.175089 3 2 28 |3534 3d3d |(11 11)(10 10) |(0 0)(1 1)| 0
3159 11:03:43.178810 3 3 0 |3534 3b3a |(11 11)(11 11) |(0 0)(1 1)| 0
3160 11:03:43.181911 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3161 11:03:43.188815 3 3 8 |3534 3d3d |(11 11)(0 0) |(0 0)(1 1)| 0
3162 11:03:43.191507 3 3 12 |3534 3b3b |(11 11)(0 0) |(0 0)(1 1)| 0
3163 11:03:43.195355 3 3 16 |3534 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
3164 11:03:43.201524 3 3 20 |3534 1e1d |(11 11)(11 11) |(1 1)(1 1)| 0
3165 11:03:43.205032 [Byte 0] Lead/lag Transition tap number (1)
3166 11:03:43.208230 3 3 24 |3534 3c3c |(11 11)(11 11) |(0 0)(1 1)| 0
3167 11:03:43.211601 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
3168 11:03:43.217901 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
3169 11:03:43.221564 [Byte 1] Lead/lag Transition tap number (1)
3170 11:03:43.224429 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3171 11:03:43.230852 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3172 11:03:43.234421 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3173 11:03:43.237459 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3174 11:03:43.244059 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3175 11:03:43.247868 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3176 11:03:43.250490 3 4 28 |3d3d 2828 |(11 11)(11 11) |(1 1)(1 1)| 0
3177 11:03:43.257289 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3178 11:03:43.260776 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3179 11:03:43.263779 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3180 11:03:43.267656 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3181 11:03:43.273771 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3182 11:03:43.276939 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3183 11:03:43.280890 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3184 11:03:43.286745 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3185 11:03:43.289900 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3186 11:03:43.293412 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3187 11:03:43.300298 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3188 11:03:43.303336 [Byte 0] Lead/lag falling Transition (3, 6, 8)
3189 11:03:43.306625 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3190 11:03:43.313581 [Byte 1] Lead/lag falling Transition (3, 6, 12)
3191 11:03:43.316538 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
3192 11:03:43.319691 [Byte 0] Lead/lag Transition tap number (3)
3193 11:03:43.323369 3 6 20 |202 3e3d |(11 11)(11 11) |(0 0)(1 0)| 0
3194 11:03:43.329725 3 6 24 |4646 605 |(0 0)(11 11) |(0 0)(1 0)| 0
3195 11:03:43.333007 [Byte 0]First pass (3, 6, 24)
3196 11:03:43.336256 [Byte 1] Lead/lag Transition tap number (4)
3197 11:03:43.339425 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3198 11:03:43.343179 [Byte 1]First pass (3, 6, 28)
3199 11:03:43.345910 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3200 11:03:43.349541 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3201 11:03:43.352439 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3202 11:03:43.359351 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3203 11:03:43.362665 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3204 11:03:43.365862 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3205 11:03:43.368996 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3206 11:03:43.375223 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3207 11:03:43.378577 All bytes gating window > 1UI, Early break!
3208 11:03:43.378675
3209 11:03:43.382097 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 14)
3210 11:03:43.382189
3211 11:03:43.385521 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
3212 11:03:43.385616
3213 11:03:43.385697
3214 11:03:43.385771
3215 11:03:43.388600 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
3216 11:03:43.388692
3217 11:03:43.395306 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
3218 11:03:43.395401
3219 11:03:43.395479
3220 11:03:43.395597 Write Rank1 MR1 =0x56
3221 11:03:43.395677
3222 11:03:43.398712 best RODT dly(2T, 0.5T) = (2, 3)
3223 11:03:43.398810
3224 11:03:43.402137 best RODT dly(2T, 0.5T) = (2, 3)
3225 11:03:43.402233 ==
3226 11:03:43.408088 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3227 11:03:43.411288 fsp= 1, odt_onoff= 1, Byte mode= 0
3228 11:03:43.411404 ==
3229 11:03:43.414574 Start DQ dly to find pass range UseTestEngine =0
3230 11:03:43.418685 x-axis: bit #, y-axis: DQ dly (-127~63)
3231 11:03:43.421743 RX Vref Scan = 0
3232 11:03:43.424713 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3233 11:03:43.428358 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3234 11:03:43.428460 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3235 11:03:43.431370 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3236 11:03:43.434638 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3237 11:03:43.437842 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3238 11:03:43.441161 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3239 11:03:43.444299 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3240 11:03:43.447681 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3241 11:03:43.450979 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3242 11:03:43.454499 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3243 11:03:43.454604 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3244 11:03:43.457277 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3245 11:03:43.460452 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3246 11:03:43.464235 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3247 11:03:43.467562 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3248 11:03:43.470637 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3249 11:03:43.473922 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3250 11:03:43.476828 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3251 11:03:43.480218 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3252 11:03:43.480383 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3253 11:03:43.483906 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3254 11:03:43.487187 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3255 11:03:43.490124 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3256 11:03:43.493439 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3257 11:03:43.497026 -1, [0] xxxxxxxx xxxxxxxo [MSB]
3258 11:03:43.500852 0, [0] xxxoxxxx xxxxxxxo [MSB]
3259 11:03:43.500956 1, [0] xxxoxxxx xxxxxxxo [MSB]
3260 11:03:43.503667 2, [0] xxxoxxxx ooxxxxxo [MSB]
3261 11:03:43.506533 3, [0] xoooxxxo ooxxxxxo [MSB]
3262 11:03:43.509658 4, [0] xooooxxo oooxxxxo [MSB]
3263 11:03:43.513179 5, [0] xooooxxo oooxxxxo [MSB]
3264 11:03:43.516435 6, [0] xooooxxo oooxxxxo [MSB]
3265 11:03:43.516536 7, [0] oooooooo oooooxoo [MSB]
3266 11:03:43.519927 32, [0] oooxoooo ooooooox [MSB]
3267 11:03:43.523043 33, [0] oooxoooo ooooooox [MSB]
3268 11:03:43.526248 34, [0] oooxoooo xoooooox [MSB]
3269 11:03:43.529547 35, [0] ooxxoooo xoooooox [MSB]
3270 11:03:43.533259 36, [0] ooxxoooo xxooooox [MSB]
3271 11:03:43.536360 37, [0] ooxxoooo xxooooox [MSB]
3272 11:03:43.539453 38, [0] xxxxooox xxooxoox [MSB]
3273 11:03:43.539558 39, [0] xxxxxoox xxxoxoox [MSB]
3274 11:03:43.542597 40, [0] xxxxxoox xxxoxxox [MSB]
3275 11:03:43.546142 41, [0] xxxxxxxx xxxxxxxx [MSB]
3276 11:03:43.549647 iDelay=41, Bit 0, Center 22 (7 ~ 37) 31
3277 11:03:43.552877 iDelay=41, Bit 1, Center 20 (3 ~ 37) 35
3278 11:03:43.556214 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32
3279 11:03:43.559155 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32
3280 11:03:43.565678 iDelay=41, Bit 4, Center 21 (4 ~ 38) 35
3281 11:03:43.569227 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
3282 11:03:43.572338 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
3283 11:03:43.575933 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35
3284 11:03:43.578968 iDelay=41, Bit 8, Center 17 (2 ~ 33) 32
3285 11:03:43.582080 iDelay=41, Bit 9, Center 18 (2 ~ 35) 34
3286 11:03:43.585210 iDelay=41, Bit 10, Center 21 (4 ~ 38) 35
3287 11:03:43.588968 iDelay=41, Bit 11, Center 23 (7 ~ 40) 34
3288 11:03:43.592285 iDelay=41, Bit 12, Center 22 (7 ~ 37) 31
3289 11:03:43.594997 iDelay=41, Bit 13, Center 23 (8 ~ 39) 32
3290 11:03:43.598661 iDelay=41, Bit 14, Center 23 (7 ~ 40) 34
3291 11:03:43.605074 iDelay=41, Bit 15, Center 15 (-1 ~ 31) 33
3292 11:03:43.605183 ==
3293 11:03:43.608594 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3294 11:03:43.612483 fsp= 1, odt_onoff= 1, Byte mode= 0
3295 11:03:43.612592 ==
3296 11:03:43.615182 DQS Delay:
3297 11:03:43.615281 DQS0 = 0, DQS1 = 0
3298 11:03:43.615368 DQM Delay:
3299 11:03:43.618481 DQM0 = 20, DQM1 = 20
3300 11:03:43.618586 DQ Delay:
3301 11:03:43.621604 DQ0 =22, DQ1 =20, DQ2 =18, DQ3 =15
3302 11:03:43.624753 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
3303 11:03:43.628074 DQ8 =17, DQ9 =18, DQ10 =21, DQ11 =23
3304 11:03:43.631473 DQ12 =22, DQ13 =23, DQ14 =23, DQ15 =15
3305 11:03:43.631575
3306 11:03:43.631661
3307 11:03:43.634926 DramC Write-DBI off
3308 11:03:43.635024 ==
3309 11:03:43.637752 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3310 11:03:43.641310 fsp= 1, odt_onoff= 1, Byte mode= 0
3311 11:03:43.641412 ==
3312 11:03:43.648357 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3313 11:03:43.648460
3314 11:03:43.651509 Begin, DQ Scan Range 925~1181
3315 11:03:43.651609
3316 11:03:43.651695
3317 11:03:43.651777 TX Vref Scan disable
3318 11:03:43.654748 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3319 11:03:43.661051 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3320 11:03:43.664294 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3321 11:03:43.667578 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3322 11:03:43.670551 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3323 11:03:43.674535 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3324 11:03:43.677407 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3325 11:03:43.680647 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3326 11:03:43.683904 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3327 11:03:43.687475 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3328 11:03:43.690383 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3329 11:03:43.694060 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3330 11:03:43.696886 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3331 11:03:43.700950 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3332 11:03:43.703976 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3333 11:03:43.710181 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3334 11:03:43.713836 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3335 11:03:43.716685 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3336 11:03:43.720159 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3337 11:03:43.723641 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3338 11:03:43.726729 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3339 11:03:43.729790 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3340 11:03:43.733550 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3341 11:03:43.736815 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3342 11:03:43.739627 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3343 11:03:43.742979 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3344 11:03:43.746500 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3345 11:03:43.749397 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3346 11:03:43.756458 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3347 11:03:43.759534 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3348 11:03:43.763070 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3349 11:03:43.765728 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3350 11:03:43.769672 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3351 11:03:43.772754 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3352 11:03:43.776009 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3353 11:03:43.779388 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3354 11:03:43.782244 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3355 11:03:43.785715 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3356 11:03:43.788684 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3357 11:03:43.792458 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3358 11:03:43.795404 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3359 11:03:43.798843 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3360 11:03:43.802610 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3361 11:03:43.805487 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3362 11:03:43.811792 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3363 11:03:43.815520 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3364 11:03:43.818615 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3365 11:03:43.821557 972 |3 6 12|[0] xxxxxxxx xxxxxxxo [MSB]
3366 11:03:43.825267 973 |3 6 13|[0] xxxxxxxx xxxxxxxo [MSB]
3367 11:03:43.828284 974 |3 6 14|[0] xxxxxxxx oxxxxxxo [MSB]
3368 11:03:43.831808 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
3369 11:03:43.834794 976 |3 6 16|[0] xxxxxxxx ooxxxxxo [MSB]
3370 11:03:43.838594 977 |3 6 17|[0] xxxxxxxx oooxxxoo [MSB]
3371 11:03:43.841794 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
3372 11:03:43.844643 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
3373 11:03:43.848054 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
3374 11:03:43.851077 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3375 11:03:43.858065 982 |3 6 22|[0] xxxxxxxo oooooooo [MSB]
3376 11:03:43.861080 983 |3 6 23|[0] xooooooo oooooooo [MSB]
3377 11:03:43.865131 992 |3 6 32|[0] oooooooo ooooooox [MSB]
3378 11:03:43.867503 993 |3 6 33|[0] oooooooo oxooooox [MSB]
3379 11:03:43.871238 994 |3 6 34|[0] oooooooo oxooooox [MSB]
3380 11:03:43.874361 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3381 11:03:43.878011 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3382 11:03:43.881294 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3383 11:03:43.884106 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3384 11:03:43.890557 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3385 11:03:43.894036 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
3386 11:03:43.897765 1001 |3 6 41|[0] ooxxoooo xxxxxxxx [MSB]
3387 11:03:43.900574 1002 |3 6 42|[0] ooxxoooo xxxxxxxx [MSB]
3388 11:03:43.903764 1003 |3 6 43|[0] xoxxxxxx xxxxxxxx [MSB]
3389 11:03:43.907660 1004 |3 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
3390 11:03:43.910596 Byte0, DQ PI dly=991, DQM PI dly= 991
3391 11:03:43.913419 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
3392 11:03:43.916637
3393 11:03:43.920407 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
3394 11:03:43.920481
3395 11:03:43.923384 Byte1, DQ PI dly=983, DQM PI dly= 983
3396 11:03:43.926450 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3397 11:03:43.926526
3398 11:03:43.933452 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3399 11:03:43.933539
3400 11:03:43.933594 ==
3401 11:03:43.936508 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3402 11:03:43.939954 fsp= 1, odt_onoff= 1, Byte mode= 0
3403 11:03:43.940024 ==
3404 11:03:43.946509 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3405 11:03:43.946583
3406 11:03:43.946674 Begin, DQ Scan Range 959~1023
3407 11:03:43.950015 Write Rank1 MR14 =0x0
3408 11:03:43.957905
3409 11:03:43.958029 CH=1, VrefRange= 0, VrefLevel = 0
3410 11:03:43.964334 TX Bit0 (985~998) 14 991, Bit8 (977~991) 15 984,
3411 11:03:43.967662 TX Bit1 (984~997) 14 990, Bit9 (977~987) 11 982,
3412 11:03:43.973965 TX Bit2 (982~996) 15 989, Bit10 (979~992) 14 985,
3413 11:03:43.977576 TX Bit3 (980~992) 13 986, Bit11 (980~993) 14 986,
3414 11:03:43.980790 TX Bit4 (984~998) 15 991, Bit12 (980~992) 13 986,
3415 11:03:43.987206 TX Bit5 (985~998) 14 991, Bit13 (980~993) 14 986,
3416 11:03:43.990606 TX Bit6 (984~998) 15 991, Bit14 (980~992) 13 986,
3417 11:03:43.997381 TX Bit7 (984~998) 15 991, Bit15 (975~984) 10 979,
3418 11:03:43.997461
3419 11:03:43.997520 Write Rank1 MR14 =0x2
3420 11:03:44.005924
3421 11:03:44.006071 CH=1, VrefRange= 0, VrefLevel = 2
3422 11:03:44.012623 TX Bit0 (985~999) 15 992, Bit8 (977~991) 15 984,
3423 11:03:44.016368 TX Bit1 (984~998) 15 991, Bit9 (978~988) 11 983,
3424 11:03:44.022490 TX Bit2 (982~996) 15 989, Bit10 (979~993) 15 986,
3425 11:03:44.026251 TX Bit3 (979~993) 15 986, Bit11 (980~993) 14 986,
3426 11:03:44.029158 TX Bit4 (983~999) 17 991, Bit12 (979~993) 15 986,
3427 11:03:44.036071 TX Bit5 (985~998) 14 991, Bit13 (980~994) 15 987,
3428 11:03:44.039015 TX Bit6 (984~999) 16 991, Bit14 (979~992) 14 985,
3429 11:03:44.045310 TX Bit7 (984~999) 16 991, Bit15 (974~985) 12 979,
3430 11:03:44.045388
3431 11:03:44.045448 Write Rank1 MR14 =0x4
3432 11:03:44.054667
3433 11:03:44.054771 CH=1, VrefRange= 0, VrefLevel = 4
3434 11:03:44.061065 TX Bit0 (985~1000) 16 992, Bit8 (977~992) 16 984,
3435 11:03:44.064374 TX Bit1 (983~999) 17 991, Bit9 (977~989) 13 983,
3436 11:03:44.071276 TX Bit2 (982~997) 16 989, Bit10 (979~993) 15 986,
3437 11:03:44.074636 TX Bit3 (979~994) 16 986, Bit11 (979~993) 15 986,
3438 11:03:44.077757 TX Bit4 (983~999) 17 991, Bit12 (979~993) 15 986,
3439 11:03:44.084694 TX Bit5 (984~999) 16 991, Bit13 (980~995) 16 987,
3440 11:03:44.087810 TX Bit6 (983~999) 17 991, Bit14 (979~992) 14 985,
3441 11:03:44.094197 TX Bit7 (984~999) 16 991, Bit15 (973~986) 14 979,
3442 11:03:44.094286
3443 11:03:44.094345 Write Rank1 MR14 =0x6
3444 11:03:44.103094
3445 11:03:44.103181 CH=1, VrefRange= 0, VrefLevel = 6
3446 11:03:44.109893 TX Bit0 (984~1000) 17 992, Bit8 (976~992) 17 984,
3447 11:03:44.112772 TX Bit1 (983~999) 17 991, Bit9 (976~991) 16 983,
3448 11:03:44.119560 TX Bit2 (982~998) 17 990, Bit10 (978~994) 17 986,
3449 11:03:44.122713 TX Bit3 (979~995) 17 987, Bit11 (979~994) 16 986,
3450 11:03:44.125927 TX Bit4 (983~1000) 18 991, Bit12 (980~994) 15 987,
3451 11:03:44.132608 TX Bit5 (984~1000) 17 992, Bit13 (980~995) 16 987,
3452 11:03:44.135996 TX Bit6 (983~1000) 18 991, Bit14 (978~993) 16 985,
3453 11:03:44.142405 TX Bit7 (984~1000) 17 992, Bit15 (973~987) 15 980,
3454 11:03:44.142525
3455 11:03:44.142616 Write Rank1 MR14 =0x8
3456 11:03:44.152270
3457 11:03:44.152393 CH=1, VrefRange= 0, VrefLevel = 8
3458 11:03:44.158812 TX Bit0 (984~1001) 18 992, Bit8 (976~992) 17 984,
3459 11:03:44.161870 TX Bit1 (983~1000) 18 991, Bit9 (976~991) 16 983,
3460 11:03:44.168994 TX Bit2 (981~999) 19 990, Bit10 (978~994) 17 986,
3461 11:03:44.171812 TX Bit3 (978~996) 19 987, Bit11 (979~995) 17 987,
3462 11:03:44.175882 TX Bit4 (983~1000) 18 991, Bit12 (979~994) 16 986,
3463 11:03:44.182105 TX Bit5 (984~1000) 17 992, Bit13 (979~996) 18 987,
3464 11:03:44.185377 TX Bit6 (983~1000) 18 991, Bit14 (978~994) 17 986,
3465 11:03:44.191748 TX Bit7 (983~1000) 18 991, Bit15 (972~988) 17 980,
3466 11:03:44.191831
3467 11:03:44.191890 Write Rank1 MR14 =0xa
3468 11:03:44.201576
3469 11:03:44.205072 CH=1, VrefRange= 0, VrefLevel = 10
3470 11:03:44.208353 TX Bit0 (984~1002) 19 993, Bit8 (976~993) 18 984,
3471 11:03:44.211769 TX Bit1 (982~1000) 19 991, Bit9 (976~991) 16 983,
3472 11:03:44.218174 TX Bit2 (980~999) 20 989, Bit10 (978~995) 18 986,
3473 11:03:44.221114 TX Bit3 (978~997) 20 987, Bit11 (979~996) 18 987,
3474 11:03:44.228132 TX Bit4 (982~1001) 20 991, Bit12 (978~995) 18 986,
3475 11:03:44.231286 TX Bit5 (984~1001) 18 992, Bit13 (979~997) 19 988,
3476 11:03:44.234398 TX Bit6 (983~1001) 19 992, Bit14 (978~994) 17 986,
3477 11:03:44.240837 TX Bit7 (983~1000) 18 991, Bit15 (972~989) 18 980,
3478 11:03:44.240941
3479 11:03:44.241027 Write Rank1 MR14 =0xc
3480 11:03:44.250691
3481 11:03:44.254335 CH=1, VrefRange= 0, VrefLevel = 12
3482 11:03:44.257218 TX Bit0 (984~1002) 19 993, Bit8 (975~993) 19 984,
3483 11:03:44.260551 TX Bit1 (982~1001) 20 991, Bit9 (975~991) 17 983,
3484 11:03:44.267674 TX Bit2 (980~999) 20 989, Bit10 (978~995) 18 986,
3485 11:03:44.270347 TX Bit3 (977~997) 21 987, Bit11 (978~996) 19 987,
3486 11:03:44.277524 TX Bit4 (982~1001) 20 991, Bit12 (978~996) 19 987,
3487 11:03:44.280528 TX Bit5 (984~1002) 19 993, Bit13 (979~998) 20 988,
3488 11:03:44.283794 TX Bit6 (982~1001) 20 991, Bit14 (978~995) 18 986,
3489 11:03:44.290749 TX Bit7 (983~1001) 19 992, Bit15 (972~990) 19 981,
3490 11:03:44.290836
3491 11:03:44.290897 Write Rank1 MR14 =0xe
3492 11:03:44.300935
3493 11:03:44.304076 CH=1, VrefRange= 0, VrefLevel = 14
3494 11:03:44.307296 TX Bit0 (984~1003) 20 993, Bit8 (975~994) 20 984,
3495 11:03:44.310444 TX Bit1 (982~1002) 21 992, Bit9 (975~992) 18 983,
3496 11:03:44.316919 TX Bit2 (979~1000) 22 989, Bit10 (977~996) 20 986,
3497 11:03:44.320372 TX Bit3 (977~998) 22 987, Bit11 (978~997) 20 987,
3498 11:03:44.326553 TX Bit4 (982~1002) 21 992, Bit12 (978~996) 19 987,
3499 11:03:44.330191 TX Bit5 (984~1003) 20 993, Bit13 (979~998) 20 988,
3500 11:03:44.333502 TX Bit6 (982~1002) 21 992, Bit14 (977~996) 20 986,
3501 11:03:44.339824 TX Bit7 (982~1002) 21 992, Bit15 (971~991) 21 981,
3502 11:03:44.339903
3503 11:03:44.339964 Write Rank1 MR14 =0x10
3504 11:03:44.350145
3505 11:03:44.353321 CH=1, VrefRange= 0, VrefLevel = 16
3506 11:03:44.357198 TX Bit0 (984~1003) 20 993, Bit8 (973~994) 22 983,
3507 11:03:44.360268 TX Bit1 (982~1003) 22 992, Bit9 (975~992) 18 983,
3508 11:03:44.366543 TX Bit2 (980~1000) 21 990, Bit10 (977~997) 21 987,
3509 11:03:44.369917 TX Bit3 (977~998) 22 987, Bit11 (978~998) 21 988,
3510 11:03:44.376501 TX Bit4 (982~1002) 21 992, Bit12 (978~997) 20 987,
3511 11:03:44.379559 TX Bit5 (983~1003) 21 993, Bit13 (978~999) 22 988,
3512 11:03:44.383015 TX Bit6 (982~1002) 21 992, Bit14 (977~996) 20 986,
3513 11:03:44.389264 TX Bit7 (982~1002) 21 992, Bit15 (971~991) 21 981,
3514 11:03:44.389349
3515 11:03:44.389410 Write Rank1 MR14 =0x12
3516 11:03:44.400314
3517 11:03:44.403937 CH=1, VrefRange= 0, VrefLevel = 18
3518 11:03:44.408491 TX Bit0 (983~1004) 22 993, Bit8 (973~994) 22 983,
3519 11:03:44.409929 TX Bit1 (981~1004) 24 992, Bit9 (973~992) 20 982,
3520 11:03:44.416449 TX Bit2 (978~1001) 24 989, Bit10 (977~998) 22 987,
3521 11:03:44.420168 TX Bit3 (977~998) 22 987, Bit11 (978~998) 21 988,
3522 11:03:44.426963 TX Bit4 (981~1003) 23 992, Bit12 (977~998) 22 987,
3523 11:03:44.429705 TX Bit5 (983~1004) 22 993, Bit13 (978~999) 22 988,
3524 11:03:44.433060 TX Bit6 (981~1002) 22 991, Bit14 (977~997) 21 987,
3525 11:03:44.439267 TX Bit7 (982~1003) 22 992, Bit15 (971~992) 22 981,
3526 11:03:44.439354
3527 11:03:44.439413 Write Rank1 MR14 =0x14
3528 11:03:44.450115
3529 11:03:44.453345 CH=1, VrefRange= 0, VrefLevel = 20
3530 11:03:44.456628 TX Bit0 (983~1004) 22 993, Bit8 (973~995) 23 984,
3531 11:03:44.459857 TX Bit1 (981~1004) 24 992, Bit9 (974~993) 20 983,
3532 11:03:44.466360 TX Bit2 (978~1001) 24 989, Bit10 (976~998) 23 987,
3533 11:03:44.469433 TX Bit3 (977~999) 23 988, Bit11 (977~999) 23 988,
3534 11:03:44.476096 TX Bit4 (981~1003) 23 992, Bit12 (977~998) 22 987,
3535 11:03:44.479338 TX Bit5 (983~1004) 22 993, Bit13 (978~999) 22 988,
3536 11:03:44.482535 TX Bit6 (981~1002) 22 991, Bit14 (977~998) 22 987,
3537 11:03:44.488962 TX Bit7 (982~1003) 22 992, Bit15 (971~992) 22 981,
3538 11:03:44.489054
3539 11:03:44.492336 Write Rank1 MR14 =0x16
3540 11:03:44.500072
3541 11:03:44.503177 CH=1, VrefRange= 0, VrefLevel = 22
3542 11:03:44.506394 TX Bit0 (983~1005) 23 994, Bit8 (973~996) 24 984,
3543 11:03:44.510090 TX Bit1 (981~1005) 25 993, Bit9 (973~993) 21 983,
3544 11:03:44.516397 TX Bit2 (978~1002) 25 990, Bit10 (976~999) 24 987,
3545 11:03:44.519474 TX Bit3 (977~999) 23 988, Bit11 (977~999) 23 988,
3546 11:03:44.526473 TX Bit4 (980~1004) 25 992, Bit12 (977~999) 23 988,
3547 11:03:44.530207 TX Bit5 (982~1005) 24 993, Bit13 (978~999) 22 988,
3548 11:03:44.533306 TX Bit6 (981~1004) 24 992, Bit14 (976~998) 23 987,
3549 11:03:44.539515 TX Bit7 (981~1004) 24 992, Bit15 (970~992) 23 981,
3550 11:03:44.539614
3551 11:03:44.539705 Write Rank1 MR14 =0x18
3552 11:03:44.550145
3553 11:03:44.553723 CH=1, VrefRange= 0, VrefLevel = 24
3554 11:03:44.556544 TX Bit0 (983~1006) 24 994, Bit8 (972~997) 26 984,
3555 11:03:44.560340 TX Bit1 (980~1005) 26 992, Bit9 (973~994) 22 983,
3556 11:03:44.566955 TX Bit2 (978~1002) 25 990, Bit10 (976~999) 24 987,
3557 11:03:44.570146 TX Bit3 (977~999) 23 988, Bit11 (977~1000) 24 988,
3558 11:03:44.576370 TX Bit4 (980~1005) 26 992, Bit12 (977~999) 23 988,
3559 11:03:44.579487 TX Bit5 (982~1005) 24 993, Bit13 (977~1000) 24 988,
3560 11:03:44.583294 TX Bit6 (980~1005) 26 992, Bit14 (976~999) 24 987,
3561 11:03:44.589763 TX Bit7 (981~1005) 25 993, Bit15 (970~993) 24 981,
3562 11:03:44.589843
3563 11:03:44.592825 Write Rank1 MR14 =0x1a
3564 11:03:44.601101
3565 11:03:44.603883 CH=1, VrefRange= 0, VrefLevel = 26
3566 11:03:44.607406 TX Bit0 (982~1006) 25 994, Bit8 (972~996) 25 984,
3567 11:03:44.610791 TX Bit1 (979~1006) 28 992, Bit9 (973~994) 22 983,
3568 11:03:44.617077 TX Bit2 (978~1003) 26 990, Bit10 (975~999) 25 987,
3569 11:03:44.620852 TX Bit3 (976~1000) 25 988, Bit11 (976~1000) 25 988,
3570 11:03:44.627324 TX Bit4 (980~1006) 27 993, Bit12 (977~1000) 24 988,
3571 11:03:44.630158 TX Bit5 (982~1006) 25 994, Bit13 (977~1000) 24 988,
3572 11:03:44.633405 TX Bit6 (980~1005) 26 992, Bit14 (976~999) 24 987,
3573 11:03:44.640276 TX Bit7 (980~1005) 26 992, Bit15 (970~993) 24 981,
3574 11:03:44.640373
3575 11:03:44.643520 Write Rank1 MR14 =0x1c
3576 11:03:44.651531
3577 11:03:44.654305 CH=1, VrefRange= 0, VrefLevel = 28
3578 11:03:44.657920 TX Bit0 (982~1006) 25 994, Bit8 (972~996) 25 984,
3579 11:03:44.661336 TX Bit1 (979~1006) 28 992, Bit9 (972~994) 23 983,
3580 11:03:44.667972 TX Bit2 (978~1003) 26 990, Bit10 (975~1000) 26 987,
3581 11:03:44.670873 TX Bit3 (976~1000) 25 988, Bit11 (976~999) 24 987,
3582 11:03:44.677513 TX Bit4 (980~1006) 27 993, Bit12 (976~1000) 25 988,
3583 11:03:44.680925 TX Bit5 (982~1006) 25 994, Bit13 (977~1000) 24 988,
3584 11:03:44.684123 TX Bit6 (979~1005) 27 992, Bit14 (975~999) 25 987,
3585 11:03:44.690821 TX Bit7 (980~1006) 27 993, Bit15 (970~993) 24 981,
3586 11:03:44.690930
3587 11:03:44.693660 Write Rank1 MR14 =0x1e
3588 11:03:44.701944
3589 11:03:44.705192 CH=1, VrefRange= 0, VrefLevel = 30
3590 11:03:44.708414 TX Bit0 (982~1007) 26 994, Bit8 (972~996) 25 984,
3591 11:03:44.711876 TX Bit1 (980~1006) 27 993, Bit9 (972~995) 24 983,
3592 11:03:44.717954 TX Bit2 (978~1003) 26 990, Bit10 (975~1000) 26 987,
3593 11:03:44.721875 TX Bit3 (976~1000) 25 988, Bit11 (976~999) 24 987,
3594 11:03:44.727801 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
3595 11:03:44.731327 TX Bit5 (981~1006) 26 993, Bit13 (976~1000) 25 988,
3596 11:03:44.734401 TX Bit6 (980~1006) 27 993, Bit14 (976~999) 24 987,
3597 11:03:44.741426 TX Bit7 (979~1006) 28 992, Bit15 (970~993) 24 981,
3598 11:03:44.741512
3599 11:03:44.744167 Write Rank1 MR14 =0x20
3600 11:03:44.752408
3601 11:03:44.755653 CH=1, VrefRange= 0, VrefLevel = 32
3602 11:03:44.759162 TX Bit0 (982~1007) 26 994, Bit8 (972~996) 25 984,
3603 11:03:44.762447 TX Bit1 (980~1006) 27 993, Bit9 (972~995) 24 983,
3604 11:03:44.769249 TX Bit2 (978~1003) 26 990, Bit10 (975~1000) 26 987,
3605 11:03:44.772241 TX Bit3 (976~1000) 25 988, Bit11 (976~999) 24 987,
3606 11:03:44.778621 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
3607 11:03:44.782573 TX Bit5 (981~1006) 26 993, Bit13 (976~1000) 25 988,
3608 11:03:44.785386 TX Bit6 (980~1006) 27 993, Bit14 (976~999) 24 987,
3609 11:03:44.791887 TX Bit7 (979~1006) 28 992, Bit15 (970~993) 24 981,
3610 11:03:44.791967
3611 11:03:44.795056 Write Rank1 MR14 =0x22
3612 11:03:44.803446
3613 11:03:44.806596 CH=1, VrefRange= 0, VrefLevel = 34
3614 11:03:44.809655 TX Bit0 (982~1007) 26 994, Bit8 (972~996) 25 984,
3615 11:03:44.812801 TX Bit1 (980~1006) 27 993, Bit9 (972~995) 24 983,
3616 11:03:44.819227 TX Bit2 (978~1003) 26 990, Bit10 (975~1000) 26 987,
3617 11:03:44.822781 TX Bit3 (976~1000) 25 988, Bit11 (976~999) 24 987,
3618 11:03:44.829979 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
3619 11:03:44.832838 TX Bit5 (981~1006) 26 993, Bit13 (976~1000) 25 988,
3620 11:03:44.836236 TX Bit6 (980~1006) 27 993, Bit14 (976~999) 24 987,
3621 11:03:44.842267 TX Bit7 (979~1006) 28 992, Bit15 (970~993) 24 981,
3622 11:03:44.842340
3623 11:03:44.845968 Write Rank1 MR14 =0x24
3624 11:03:44.853813
3625 11:03:44.857065 CH=1, VrefRange= 0, VrefLevel = 36
3626 11:03:44.860333 TX Bit0 (982~1007) 26 994, Bit8 (972~996) 25 984,
3627 11:03:44.863570 TX Bit1 (980~1006) 27 993, Bit9 (972~995) 24 983,
3628 11:03:44.870000 TX Bit2 (978~1003) 26 990, Bit10 (975~1000) 26 987,
3629 11:03:44.873688 TX Bit3 (976~1000) 25 988, Bit11 (976~999) 24 987,
3630 11:03:44.880043 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
3631 11:03:44.883276 TX Bit5 (981~1006) 26 993, Bit13 (976~1000) 25 988,
3632 11:03:44.886293 TX Bit6 (980~1006) 27 993, Bit14 (976~999) 24 987,
3633 11:03:44.893398 TX Bit7 (979~1006) 28 992, Bit15 (970~993) 24 981,
3634 11:03:44.893475
3635 11:03:44.893550
3636 11:03:44.896436 TX Vref found, early break! 382< 387
3637 11:03:44.899394 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
3638 11:03:44.902685 u1DelayCellOfst[0]=7 cells (6 PI)
3639 11:03:44.906308 u1DelayCellOfst[1]=6 cells (5 PI)
3640 11:03:44.909264 u1DelayCellOfst[2]=2 cells (2 PI)
3641 11:03:44.912497 u1DelayCellOfst[3]=0 cells (0 PI)
3642 11:03:44.915693 u1DelayCellOfst[4]=6 cells (5 PI)
3643 11:03:44.918912 u1DelayCellOfst[5]=6 cells (5 PI)
3644 11:03:44.922870 u1DelayCellOfst[6]=6 cells (5 PI)
3645 11:03:44.925455 u1DelayCellOfst[7]=5 cells (4 PI)
3646 11:03:44.929124 Byte0, DQ PI dly=988, DQM PI dly= 991
3647 11:03:44.932640 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3648 11:03:44.932718
3649 11:03:44.939164 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3650 11:03:44.939242
3651 11:03:44.939317 u1DelayCellOfst[8]=3 cells (3 PI)
3652 11:03:44.942284 u1DelayCellOfst[9]=2 cells (2 PI)
3653 11:03:44.945799 u1DelayCellOfst[10]=7 cells (6 PI)
3654 11:03:44.948602 u1DelayCellOfst[11]=7 cells (6 PI)
3655 11:03:44.952186 u1DelayCellOfst[12]=7 cells (6 PI)
3656 11:03:44.955152 u1DelayCellOfst[13]=9 cells (7 PI)
3657 11:03:44.958282 u1DelayCellOfst[14]=7 cells (6 PI)
3658 11:03:44.961524 u1DelayCellOfst[15]=0 cells (0 PI)
3659 11:03:44.965141 Byte1, DQ PI dly=981, DQM PI dly= 984
3660 11:03:44.968302 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
3661 11:03:44.968410
3662 11:03:44.975270 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
3663 11:03:44.975340
3664 11:03:44.975400 Write Rank1 MR14 =0x1e
3665 11:03:44.975485
3666 11:03:44.978465 Final TX Range 0 Vref 30
3667 11:03:44.978530
3668 11:03:44.985352 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3669 11:03:44.985452
3670 11:03:44.991583 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3671 11:03:44.998384 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3672 11:03:45.004935 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3673 11:03:45.008037 Write Rank1 MR3 =0xb0
3674 11:03:45.011689 DramC Write-DBI on
3675 11:03:45.011765 ==
3676 11:03:45.014410 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3677 11:03:45.017650 fsp= 1, odt_onoff= 1, Byte mode= 0
3678 11:03:45.017739 ==
3679 11:03:45.024288 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3680 11:03:45.024391
3681 11:03:45.024484 Begin, DQ Scan Range 704~768
3682 11:03:45.024564
3683 11:03:45.024643
3684 11:03:45.027432 TX Vref Scan disable
3685 11:03:45.030567 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3686 11:03:45.034814 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3687 11:03:45.037200 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3688 11:03:45.040972 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3689 11:03:45.043994 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3690 11:03:45.047688 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3691 11:03:45.050091 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3692 11:03:45.057394 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3693 11:03:45.060498 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3694 11:03:45.063286 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3695 11:03:45.066576 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3696 11:03:45.070273 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3697 11:03:45.073167 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3698 11:03:45.076515 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3699 11:03:45.079850 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3700 11:03:45.083231 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3701 11:03:45.086383 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3702 11:03:45.089833 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3703 11:03:45.093182 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3704 11:03:45.096441 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3705 11:03:45.105563 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3706 11:03:45.108837 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3707 11:03:45.112057 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3708 11:03:45.115591 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3709 11:03:45.118502 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3710 11:03:45.121810 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3711 11:03:45.125479 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3712 11:03:45.128723 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3713 11:03:45.131858 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3714 11:03:45.135366 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3715 11:03:45.138987 Byte0, DQ PI dly=737, DQM PI dly= 737
3716 11:03:45.145526 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 33)
3717 11:03:45.145602
3718 11:03:45.148328 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 33)
3719 11:03:45.148420
3720 11:03:45.151399 Byte1, DQ PI dly=729, DQM PI dly= 729
3721 11:03:45.155104 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
3722 11:03:45.155195
3723 11:03:45.161229 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
3724 11:03:45.161341
3725 11:03:45.168163 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3726 11:03:45.174495 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3727 11:03:45.181652 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3728 11:03:45.184353 Write Rank1 MR3 =0x30
3729 11:03:45.184467 DramC Write-DBI off
3730 11:03:45.184525
3731 11:03:45.184578 [DATLAT]
3732 11:03:45.187496 Freq=1600, CH1 RK1, use_rxtx_scan=0
3733 11:03:45.190926
3734 11:03:45.191037 DATLAT Default: 0x10
3735 11:03:45.194194 7, 0xFFFF, sum=0
3736 11:03:45.194270 8, 0xFFFF, sum=0
3737 11:03:45.197455 9, 0xFFFF, sum=0
3738 11:03:45.197544 10, 0xFFFF, sum=0
3739 11:03:45.200543 11, 0xFFFF, sum=0
3740 11:03:45.200618 12, 0xFFFF, sum=0
3741 11:03:45.203911 13, 0xFFFF, sum=0
3742 11:03:45.203987 14, 0x0, sum=1
3743 11:03:45.204045 15, 0x0, sum=2
3744 11:03:45.207720 16, 0x0, sum=3
3745 11:03:45.207802 17, 0x0, sum=4
3746 11:03:45.213920 pattern=2 first_step=14 total pass=5 best_step=16
3747 11:03:45.214029 ==
3748 11:03:45.217127 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3749 11:03:45.220467 fsp= 1, odt_onoff= 1, Byte mode= 0
3750 11:03:45.220557 ==
3751 11:03:45.226875 Start DQ dly to find pass range UseTestEngine =1
3752 11:03:45.230603 x-axis: bit #, y-axis: DQ dly (-127~63)
3753 11:03:45.230671 RX Vref Scan = 0
3754 11:03:45.233818 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3755 11:03:45.237060 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3756 11:03:45.240129 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3757 11:03:45.243358 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3758 11:03:45.246715 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3759 11:03:45.246793 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3760 11:03:45.249680 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3761 11:03:45.253007 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3762 11:03:45.256612 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3763 11:03:45.259726 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3764 11:03:45.263022 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3765 11:03:45.266077 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3766 11:03:45.269624 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3767 11:03:45.273013 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3768 11:03:45.275893 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3769 11:03:45.275993 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3770 11:03:45.279037 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3771 11:03:45.282507 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3772 11:03:45.285688 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3773 11:03:45.289294 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3774 11:03:45.292871 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3775 11:03:45.295588 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3776 11:03:45.298691 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3777 11:03:45.298785 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3778 11:03:45.302479 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3779 11:03:45.305149 -1, [0] xxxxxxxx xxxxxxxo [MSB]
3780 11:03:45.309184 0, [0] xxxoxxxx xxxxxxxo [MSB]
3781 11:03:45.312221 1, [0] xxxoxxxx xxxxxxxo [MSB]
3782 11:03:45.315284 2, [0] xxxoxxxx ooxxxxxo [MSB]
3783 11:03:45.315356 3, [0] xooooxxx ooxxxxxo [MSB]
3784 11:03:45.318191 4, [0] xooooxxo oooxxxxo [MSB]
3785 11:03:45.321937 5, [0] xoooooxo oooxxxoo [MSB]
3786 11:03:45.325177 6, [0] ooooooxo ooooxxoo [MSB]
3787 11:03:45.329013 32, [0] oooxoooo ooooooox [MSB]
3788 11:03:45.332231 33, [0] oooxoooo ooooooox [MSB]
3789 11:03:45.335483 34, [0] oooxoooo ooooooox [MSB]
3790 11:03:45.338531 35, [0] ooxxoooo xxooooox [MSB]
3791 11:03:45.341793 36, [0] ooxxoooo xxooooox [MSB]
3792 11:03:45.345678 37, [0] ooxxoooo xxooooox [MSB]
3793 11:03:45.348922 38, [0] oxxxooox xxooooox [MSB]
3794 11:03:45.349012 39, [0] xxxxxoox xxxoxoox [MSB]
3795 11:03:45.351736 40, [0] xxxxxoox xxxxxxxx [MSB]
3796 11:03:45.355172 41, [0] xxxxxxxx xxxxxxxx [MSB]
3797 11:03:45.358332 iDelay=41, Bit 0, Center 22 (6 ~ 38) 33
3798 11:03:45.361680 iDelay=41, Bit 1, Center 20 (3 ~ 37) 35
3799 11:03:45.364591 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32
3800 11:03:45.368308 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32
3801 11:03:45.375002 iDelay=41, Bit 4, Center 20 (3 ~ 38) 36
3802 11:03:45.377969 iDelay=41, Bit 5, Center 22 (5 ~ 40) 36
3803 11:03:45.381639 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
3804 11:03:45.384687 iDelay=41, Bit 7, Center 20 (4 ~ 37) 34
3805 11:03:45.388086 iDelay=41, Bit 8, Center 18 (2 ~ 34) 33
3806 11:03:45.391465 iDelay=41, Bit 9, Center 18 (2 ~ 34) 33
3807 11:03:45.394178 iDelay=41, Bit 10, Center 21 (4 ~ 38) 35
3808 11:03:45.397867 iDelay=41, Bit 11, Center 22 (6 ~ 39) 34
3809 11:03:45.400872 iDelay=41, Bit 12, Center 22 (7 ~ 38) 32
3810 11:03:45.404588 iDelay=41, Bit 13, Center 23 (7 ~ 39) 33
3811 11:03:45.407321 iDelay=41, Bit 14, Center 22 (5 ~ 39) 35
3812 11:03:45.414470 iDelay=41, Bit 15, Center 15 (-1 ~ 31) 33
3813 11:03:45.414547 ==
3814 11:03:45.417456 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3815 11:03:45.420950 fsp= 1, odt_onoff= 1, Byte mode= 0
3816 11:03:45.421044 ==
3817 11:03:45.423859 DQS Delay:
3818 11:03:45.423965 DQS0 = 0, DQS1 = 0
3819 11:03:45.424050 DQM Delay:
3820 11:03:45.427354 DQM0 = 20, DQM1 = 20
3821 11:03:45.427443 DQ Delay:
3822 11:03:45.430602 DQ0 =22, DQ1 =20, DQ2 =18, DQ3 =15
3823 11:03:45.433868 DQ4 =20, DQ5 =22, DQ6 =23, DQ7 =20
3824 11:03:45.437224 DQ8 =18, DQ9 =18, DQ10 =21, DQ11 =22
3825 11:03:45.440299 DQ12 =22, DQ13 =23, DQ14 =22, DQ15 =15
3826 11:03:45.440373
3827 11:03:45.440431
3828 11:03:45.440483
3829 11:03:45.443626 [DramC_TX_OE_Calibration] TA2
3830 11:03:45.446850 Original DQ_B0 (3 6) =30, OEN = 27
3831 11:03:45.450190 Original DQ_B1 (3 6) =30, OEN = 27
3832 11:03:45.453666 23, 0x0, End_B0=23 End_B1=23
3833 11:03:45.457143 24, 0x0, End_B0=24 End_B1=24
3834 11:03:45.457219 25, 0x0, End_B0=25 End_B1=25
3835 11:03:45.460386 26, 0x0, End_B0=26 End_B1=26
3836 11:03:45.463486 27, 0x0, End_B0=27 End_B1=27
3837 11:03:45.466601 28, 0x0, End_B0=28 End_B1=28
3838 11:03:45.470231 29, 0x0, End_B0=29 End_B1=29
3839 11:03:45.470323 30, 0x0, End_B0=30 End_B1=30
3840 11:03:45.473065 31, 0xFFFF, End_B0=30 End_B1=30
3841 11:03:45.479761 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3842 11:03:45.486785 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3843 11:03:45.486860
3844 11:03:45.486917
3845 11:03:45.486969 Write Rank1 MR23 =0x3f
3846 11:03:45.489978 [DQSOSC]
3847 11:03:45.496377 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1b1, (MSB)MR19= 0x202, tDQSOscB0 = 457 ps tDQSOscB1 = 457 ps
3848 11:03:45.502646 CH1_RK1: MR19=0x202, MR18=0xB1B1, DQSOSC=457, MR23=63, INC=11, DEC=17
3849 11:03:45.506129 Write Rank1 MR23 =0x3f
3850 11:03:45.506235 [DQSOSC]
3851 11:03:45.512428 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0x202, tDQSOscB0 = 454 ps tDQSOscB1 = 454 ps
3852 11:03:45.516021 CH1 RK1: MR19=202, MR18=B5B5
3853 11:03:45.518957 [RxdqsGatingPostProcess] freq 1600
3854 11:03:45.525983 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3855 11:03:45.526104 Rank: 0
3856 11:03:45.528883 best DQS0 dly(2T, 0.5T) = (2, 6)
3857 11:03:45.532179 best DQS1 dly(2T, 0.5T) = (2, 6)
3858 11:03:45.535430 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3859 11:03:45.538793 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3860 11:03:45.538869 Rank: 1
3861 11:03:45.541949 best DQS0 dly(2T, 0.5T) = (2, 6)
3862 11:03:45.545404 best DQS1 dly(2T, 0.5T) = (2, 6)
3863 11:03:45.548862 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3864 11:03:45.552119 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3865 11:03:45.555486 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3866 11:03:45.558404 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3867 11:03:45.564940 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3868 11:03:45.565017
3869 11:03:45.565077
3870 11:03:45.568371 [Calibration Summary] Freqency 1600
3871 11:03:45.568448 CH 0, Rank 0
3872 11:03:45.568524 All Pass.
3873 11:03:45.568595
3874 11:03:45.571360 CH 0, Rank 1
3875 11:03:45.571436 All Pass.
3876 11:03:45.571511
3877 11:03:45.571582 CH 1, Rank 0
3878 11:03:45.574832 All Pass.
3879 11:03:45.574909
3880 11:03:45.574984 CH 1, Rank 1
3881 11:03:45.575056 All Pass.
3882 11:03:45.578135
3883 11:03:45.581323 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3884 11:03:45.591602 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3885 11:03:45.597913 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3886 11:03:45.598039 Write Rank0 MR3 =0xb0
3887 11:03:45.604351 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3888 11:03:45.611090 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3889 11:03:45.620586 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3890 11:03:45.620667 Write Rank1 MR3 =0xb0
3891 11:03:45.627156 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3892 11:03:45.633737 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3893 11:03:45.640840 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3894 11:03:45.644011 Write Rank0 MR3 =0xb0
3895 11:03:45.649928 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3896 11:03:45.656781 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3897 11:03:45.663311 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3898 11:03:45.666982 Write Rank1 MR3 =0xb0
3899 11:03:45.667086 DramC Write-DBI on
3900 11:03:45.670127 [GetDramInforAfterCalByMRR] Vendor 6.
3901 11:03:45.676419 [GetDramInforAfterCalByMRR] Revision 505.
3902 11:03:45.676500 MR8 1111
3903 11:03:45.679650 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3904 11:03:45.684062 MR8 1111
3905 11:03:45.686621 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3906 11:03:45.686698 MR8 1111
3907 11:03:45.692862 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3908 11:03:45.692956 MR8 1111
3909 11:03:45.699876 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3910 11:03:45.705999 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3911 11:03:45.709218 Write Rank0 MR13 =0xd0
3912 11:03:45.712304 Write Rank1 MR13 =0xd0
3913 11:03:45.712380 Write Rank0 MR13 =0xd0
3914 11:03:45.715964 Write Rank1 MR13 =0xd0
3915 11:03:45.719288 Save calibration result to emmc
3916 11:03:45.719362
3917 11:03:45.719420
3918 11:03:45.722375 [DramcModeReg_Check] Freq_1600, FSP_1
3919 11:03:45.722448 FSP_1, CH_0, RK0
3920 11:03:45.725691 Write Rank0 MR13 =0xd8
3921 11:03:45.729215 MR12 = 0x5e (global = 0x5e) match
3922 11:03:45.732459 MR14 = 0x1e (global = 0x1e) match
3923 11:03:45.732533 FSP_1, CH_0, RK1
3924 11:03:45.735597 Write Rank1 MR13 =0xd8
3925 11:03:45.738917 MR12 = 0x5e (global = 0x5e) match
3926 11:03:45.741896 MR14 = 0x1a (global = 0x1a) match
3927 11:03:45.741970 FSP_1, CH_1, RK0
3928 11:03:45.745318 Write Rank0 MR13 =0xd8
3929 11:03:45.748484 MR12 = 0x5e (global = 0x5e) match
3930 11:03:45.751999 MR14 = 0x1c (global = 0x1c) match
3931 11:03:45.752073 FSP_1, CH_1, RK1
3932 11:03:45.755059 Write Rank1 MR13 =0xd8
3933 11:03:45.758757 MR12 = 0x5e (global = 0x5e) match
3934 11:03:45.761381 MR14 = 0x1e (global = 0x1e) match
3935 11:03:45.761455
3936 11:03:45.765096 [MEM_TEST] 02: After DFS, before run time config
3937 11:03:45.776798 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3938 11:03:45.776881
3939 11:03:45.776938 [TA2_TEST]
3940 11:03:45.776991 === TA2 HW
3941 11:03:45.780390 TA2 PAT: XTALK
3942 11:03:45.783488 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3943 11:03:45.789965 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3944 11:03:45.793426 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3945 11:03:45.799965 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3946 11:03:45.800067
3947 11:03:45.800199
3948 11:03:45.800282 Settings after calibration
3949 11:03:45.803035
3950 11:03:45.803131 [DramcRunTimeConfig]
3951 11:03:45.806244 TransferPLLToSPMControl - MODE SW PHYPLL
3952 11:03:45.809572 TX_TRACKING: ON
3953 11:03:45.809668 RX_TRACKING: ON
3954 11:03:45.809754 HW_GATING: ON
3955 11:03:45.812734 HW_GATING DBG: OFF
3956 11:03:45.812827 ddr_geometry:1
3957 11:03:45.816271 ddr_geometry:1
3958 11:03:45.816367 ddr_geometry:1
3959 11:03:45.819425 ddr_geometry:1
3960 11:03:45.819507 ddr_geometry:1
3961 11:03:45.822969 ddr_geometry:1
3962 11:03:45.823077 ddr_geometry:1
3963 11:03:45.823167 ddr_geometry:1
3964 11:03:45.826141 High Freq DUMMY_READ_FOR_TRACKING: ON
3965 11:03:45.829463 ZQCS_ENABLE_LP4: OFF
3966 11:03:45.832684 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3967 11:03:45.835763 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3968 11:03:45.839002 SPM_CONTROL_AFTERK: ON
3969 11:03:45.839097 IMPEDANCE_TRACKING: ON
3970 11:03:45.842554 TEMP_SENSOR: ON
3971 11:03:45.842629 PER_BANK_REFRESH: ON
3972 11:03:45.845958 HW_SAVE_FOR_SR: ON
3973 11:03:45.849050 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3974 11:03:45.852240 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3975 11:03:45.855616 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3976 11:03:45.855700 Read ODT Tracking: ON
3977 11:03:45.859081 =========================
3978 11:03:45.859152
3979 11:03:45.859207 [TA2_TEST]
3980 11:03:45.861854 === TA2 HW
3981 11:03:45.865380 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3982 11:03:45.871984 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3983 11:03:45.875369 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3984 11:03:45.881770 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3985 11:03:45.881856
3986 11:03:45.885254 [MEM_TEST] 03: After run time config
3987 11:03:45.895091 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3988 11:03:45.898174 [complex_mem_test] start addr:0x40024000, len:131072
3989 11:03:46.102540 1st complex R/W mem test pass
3990 11:03:46.108826 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3991 11:03:46.112425 sync preloader write leveling
3992 11:03:46.115434 sync preloader cbt_mr12
3993 11:03:46.118829 sync preloader cbt_clk_dly
3994 11:03:46.118895 sync preloader cbt_cmd_dly
3995 11:03:46.122212 sync preloader cbt_cs
3996 11:03:46.125593 sync preloader cbt_ca_perbit_delay
3997 11:03:46.125661 sync preloader clk_delay
3998 11:03:46.128982 sync preloader dqs_delay
3999 11:03:46.132446 sync preloader u1Gating2T_Save
4000 11:03:46.135852 sync preloader u1Gating05T_Save
4001 11:03:46.138504 sync preloader u1Gatingfine_tune_Save
4002 11:03:46.142315 sync preloader u1Gatingucpass_count_Save
4003 11:03:46.145483 sync preloader u1TxWindowPerbitVref_Save
4004 11:03:46.148669 sync preloader u1TxCenter_min_Save
4005 11:03:46.152147 sync preloader u1TxCenter_max_Save
4006 11:03:46.155268 sync preloader u1Txwin_center_Save
4007 11:03:46.158389 sync preloader u1Txfirst_pass_Save
4008 11:03:46.161655 sync preloader u1Txlast_pass_Save
4009 11:03:46.164672 sync preloader u1RxDatlat_Save
4010 11:03:46.168320 sync preloader u1RxWinPerbitVref_Save
4011 11:03:46.171292 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4012 11:03:46.175025 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4013 11:03:46.178587 sync preloader delay_cell_unit
4014 11:03:46.184790 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4015 11:03:46.187955 sync preloader write leveling
4016 11:03:46.191091 sync preloader cbt_mr12
4017 11:03:46.191183 sync preloader cbt_clk_dly
4018 11:03:46.194940 sync preloader cbt_cmd_dly
4019 11:03:46.197446 sync preloader cbt_cs
4020 11:03:46.200938 sync preloader cbt_ca_perbit_delay
4021 11:03:46.201018 sync preloader clk_delay
4022 11:03:46.204315 sync preloader dqs_delay
4023 11:03:46.207381 sync preloader u1Gating2T_Save
4024 11:03:46.210652 sync preloader u1Gating05T_Save
4025 11:03:46.214637 sync preloader u1Gatingfine_tune_Save
4026 11:03:46.217568 sync preloader u1Gatingucpass_count_Save
4027 11:03:46.220739 sync preloader u1TxWindowPerbitVref_Save
4028 11:03:46.223837 sync preloader u1TxCenter_min_Save
4029 11:03:46.227238 sync preloader u1TxCenter_max_Save
4030 11:03:46.230169 sync preloader u1Txwin_center_Save
4031 11:03:46.233750 sync preloader u1Txfirst_pass_Save
4032 11:03:46.236889 sync preloader u1Txlast_pass_Save
4033 11:03:46.236968 sync preloader u1RxDatlat_Save
4034 11:03:46.243346 sync preloader u1RxWinPerbitVref_Save
4035 11:03:46.246621 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4036 11:03:46.250643 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4037 11:03:46.253611 sync preloader delay_cell_unit
4038 11:03:46.260065 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4039 11:03:46.263379 sync preloader write leveling
4040 11:03:46.263458 sync preloader cbt_mr12
4041 11:03:46.266697 sync preloader cbt_clk_dly
4042 11:03:46.270053 sync preloader cbt_cmd_dly
4043 11:03:46.270129 sync preloader cbt_cs
4044 11:03:46.273325 sync preloader cbt_ca_perbit_delay
4045 11:03:46.276148 sync preloader clk_delay
4046 11:03:46.279810 sync preloader dqs_delay
4047 11:03:46.282948 sync preloader u1Gating2T_Save
4048 11:03:46.283029 sync preloader u1Gating05T_Save
4049 11:03:46.289295 sync preloader u1Gatingfine_tune_Save
4050 11:03:46.292864 sync preloader u1Gatingucpass_count_Save
4051 11:03:46.295879 sync preloader u1TxWindowPerbitVref_Save
4052 11:03:46.299500 sync preloader u1TxCenter_min_Save
4053 11:03:46.302581 sync preloader u1TxCenter_max_Save
4054 11:03:46.305778 sync preloader u1Txwin_center_Save
4055 11:03:46.309332 sync preloader u1Txfirst_pass_Save
4056 11:03:46.309433 sync preloader u1Txlast_pass_Save
4057 11:03:46.312243 sync preloader u1RxDatlat_Save
4058 11:03:46.316154 sync preloader u1RxWinPerbitVref_Save
4059 11:03:46.322270 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4060 11:03:46.325523 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4061 11:03:46.328654 sync preloader delay_cell_unit
4062 11:03:46.332232 just_for_test_dump_coreboot_params dump all params
4063 11:03:46.332309 dump source = 0x0
4064 11:03:46.335156 dump params frequency:1600
4065 11:03:46.338652 dump params rank number:2
4066 11:03:46.338749
4067 11:03:46.342537 dump params write leveling
4068 11:03:46.345265 write leveling[0][0][0] = 0x20
4069 11:03:46.345367 write leveling[0][0][1] = 0x17
4070 11:03:46.348560 write leveling[0][1][0] = 0x1f
4071 11:03:46.352063 write leveling[0][1][1] = 0x17
4072 11:03:46.355186 write leveling[1][0][0] = 0x23
4073 11:03:46.358452 write leveling[1][0][1] = 0x21
4074 11:03:46.361644 write leveling[1][1][0] = 0x21
4075 11:03:46.361754 write leveling[1][1][1] = 0x1d
4076 11:03:46.364989 dump params cbt_cs
4077 11:03:46.368051 cbt_cs[0][0] = 0x7
4078 11:03:46.368159 cbt_cs[0][1] = 0x7
4079 11:03:46.371458 cbt_cs[1][0] = 0xa
4080 11:03:46.371533 cbt_cs[1][1] = 0xa
4081 11:03:46.374585 dump params cbt_mr12
4082 11:03:46.374684 cbt_mr12[0][0] = 0x1e
4083 11:03:46.378635 cbt_mr12[0][1] = 0x1e
4084 11:03:46.378736 cbt_mr12[1][0] = 0x1e
4085 11:03:46.381418 cbt_mr12[1][1] = 0x1e
4086 11:03:46.384492 dump params tx window
4087 11:03:46.384559 tx_center_min[0][0][0] = 985
4088 11:03:46.387858 tx_center_max[0][0][0] = 991
4089 11:03:46.391171 tx_center_min[0][0][1] = 977
4090 11:03:46.394390 tx_center_max[0][0][1] = 985
4091 11:03:46.397969 tx_center_min[0][1][0] = 984
4092 11:03:46.401294 tx_center_max[0][1][0] = 990
4093 11:03:46.401403 tx_center_min[0][1][1] = 977
4094 11:03:46.404090 tx_center_max[0][1][1] = 985
4095 11:03:46.407762 tx_center_min[1][0][0] = 991
4096 11:03:46.411135 tx_center_max[1][0][0] = 996
4097 11:03:46.411205 tx_center_min[1][0][1] = 987
4098 11:03:46.414651 tx_center_max[1][0][1] = 994
4099 11:03:46.417467 tx_center_min[1][1][0] = 988
4100 11:03:46.420903 tx_center_max[1][1][0] = 994
4101 11:03:46.423919 tx_center_min[1][1][1] = 981
4102 11:03:46.427295 tx_center_max[1][1][1] = 988
4103 11:03:46.427361 dump params tx window
4104 11:03:46.430407 tx_win_center[0][0][0] = 991
4105 11:03:46.434156 tx_first_pass[0][0][0] = 979
4106 11:03:46.437149 tx_last_pass[0][0][0] = 1004
4107 11:03:46.437250 tx_win_center[0][0][1] = 990
4108 11:03:46.440490 tx_first_pass[0][0][1] = 978
4109 11:03:46.443804 tx_last_pass[0][0][1] = 1002
4110 11:03:46.446705 tx_win_center[0][0][2] = 991
4111 11:03:46.450608 tx_first_pass[0][0][2] = 979
4112 11:03:46.450684 tx_last_pass[0][0][2] = 1003
4113 11:03:46.453304 tx_win_center[0][0][3] = 985
4114 11:03:46.457190 tx_first_pass[0][0][3] = 974
4115 11:03:46.460075 tx_last_pass[0][0][3] = 997
4116 11:03:46.460153 tx_win_center[0][0][4] = 989
4117 11:03:46.463549 tx_first_pass[0][0][4] = 977
4118 11:03:46.466578 tx_last_pass[0][0][4] = 1001
4119 11:03:46.469748 tx_win_center[0][0][5] = 987
4120 11:03:46.473087 tx_first_pass[0][0][5] = 976
4121 11:03:46.473166 tx_last_pass[0][0][5] = 999
4122 11:03:46.476501 tx_win_center[0][0][6] = 988
4123 11:03:46.479877 tx_first_pass[0][0][6] = 976
4124 11:03:46.482809 tx_last_pass[0][0][6] = 1000
4125 11:03:46.486252 tx_win_center[0][0][7] = 989
4126 11:03:46.486329 tx_first_pass[0][0][7] = 977
4127 11:03:46.489879 tx_last_pass[0][0][7] = 1001
4128 11:03:46.493049 tx_win_center[0][0][8] = 977
4129 11:03:46.496342 tx_first_pass[0][0][8] = 966
4130 11:03:46.499464 tx_last_pass[0][0][8] = 989
4131 11:03:46.499559 tx_win_center[0][0][9] = 978
4132 11:03:46.503115 tx_first_pass[0][0][9] = 967
4133 11:03:46.506181 tx_last_pass[0][0][9] = 990
4134 11:03:46.509416 tx_win_center[0][0][10] = 985
4135 11:03:46.512551 tx_first_pass[0][0][10] = 973
4136 11:03:46.512654 tx_last_pass[0][0][10] = 997
4137 11:03:46.515737 tx_win_center[0][0][11] = 978
4138 11:03:46.518920 tx_first_pass[0][0][11] = 967
4139 11:03:46.522798 tx_last_pass[0][0][11] = 990
4140 11:03:46.525837 tx_win_center[0][0][12] = 979
4141 11:03:46.525945 tx_first_pass[0][0][12] = 968
4142 11:03:46.528875 tx_last_pass[0][0][12] = 991
4143 11:03:46.532305 tx_win_center[0][0][13] = 979
4144 11:03:46.535484 tx_first_pass[0][0][13] = 968
4145 11:03:46.538800 tx_last_pass[0][0][13] = 991
4146 11:03:46.542117 tx_win_center[0][0][14] = 980
4147 11:03:46.542194 tx_first_pass[0][0][14] = 968
4148 11:03:46.545331 tx_last_pass[0][0][14] = 993
4149 11:03:46.548479 tx_win_center[0][0][15] = 983
4150 11:03:46.552292 tx_first_pass[0][0][15] = 971
4151 11:03:46.555593 tx_last_pass[0][0][15] = 995
4152 11:03:46.555669 tx_win_center[0][1][0] = 990
4153 11:03:46.558624 tx_first_pass[0][1][0] = 978
4154 11:03:46.561608 tx_last_pass[0][1][0] = 1002
4155 11:03:46.565288 tx_win_center[0][1][1] = 989
4156 11:03:46.568241 tx_first_pass[0][1][1] = 977
4157 11:03:46.568319 tx_last_pass[0][1][1] = 1001
4158 11:03:46.571480 tx_win_center[0][1][2] = 989
4159 11:03:46.575208 tx_first_pass[0][1][2] = 978
4160 11:03:46.578157 tx_last_pass[0][1][2] = 1001
4161 11:03:46.578235 tx_win_center[0][1][3] = 984
4162 11:03:46.581437 tx_first_pass[0][1][3] = 973
4163 11:03:46.584742 tx_last_pass[0][1][3] = 996
4164 11:03:46.587989 tx_win_center[0][1][4] = 989
4165 11:03:46.591401 tx_first_pass[0][1][4] = 977
4166 11:03:46.591478 tx_last_pass[0][1][4] = 1001
4167 11:03:46.594715 tx_win_center[0][1][5] = 987
4168 11:03:46.597899 tx_first_pass[0][1][5] = 975
4169 11:03:46.601441 tx_last_pass[0][1][5] = 999
4170 11:03:46.604298 tx_win_center[0][1][6] = 987
4171 11:03:46.604376 tx_first_pass[0][1][6] = 976
4172 11:03:46.607522 tx_last_pass[0][1][6] = 999
4173 11:03:46.611088 tx_win_center[0][1][7] = 989
4174 11:03:46.614104 tx_first_pass[0][1][7] = 977
4175 11:03:46.617377 tx_last_pass[0][1][7] = 1001
4176 11:03:46.617455 tx_win_center[0][1][8] = 977
4177 11:03:46.621035 tx_first_pass[0][1][8] = 966
4178 11:03:46.624238 tx_last_pass[0][1][8] = 989
4179 11:03:46.627580 tx_win_center[0][1][9] = 979
4180 11:03:46.630854 tx_first_pass[0][1][9] = 968
4181 11:03:46.630932 tx_last_pass[0][1][9] = 991
4182 11:03:46.634028 tx_win_center[0][1][10] = 985
4183 11:03:46.637513 tx_first_pass[0][1][10] = 973
4184 11:03:46.640726 tx_last_pass[0][1][10] = 997
4185 11:03:46.643528 tx_win_center[0][1][11] = 978
4186 11:03:46.643606 tx_first_pass[0][1][11] = 967
4187 11:03:46.647339 tx_last_pass[0][1][11] = 990
4188 11:03:46.650079 tx_win_center[0][1][12] = 980
4189 11:03:46.653549 tx_first_pass[0][1][12] = 968
4190 11:03:46.656868 tx_last_pass[0][1][12] = 992
4191 11:03:46.659981 tx_win_center[0][1][13] = 979
4192 11:03:46.660059 tx_first_pass[0][1][13] = 968
4193 11:03:46.663333 tx_last_pass[0][1][13] = 991
4194 11:03:46.666671 tx_win_center[0][1][14] = 980
4195 11:03:46.669699 tx_first_pass[0][1][14] = 968
4196 11:03:46.673027 tx_last_pass[0][1][14] = 993
4197 11:03:46.673104 tx_win_center[0][1][15] = 984
4198 11:03:46.676850 tx_first_pass[0][1][15] = 973
4199 11:03:46.679747 tx_last_pass[0][1][15] = 996
4200 11:03:46.683171 tx_win_center[1][0][0] = 996
4201 11:03:46.686442 tx_first_pass[1][0][0] = 984
4202 11:03:46.686519 tx_last_pass[1][0][0] = 1009
4203 11:03:46.689638 tx_win_center[1][0][1] = 995
4204 11:03:46.692898 tx_first_pass[1][0][1] = 983
4205 11:03:46.696456 tx_last_pass[1][0][1] = 1008
4206 11:03:46.699428 tx_win_center[1][0][2] = 993
4207 11:03:46.699505 tx_first_pass[1][0][2] = 980
4208 11:03:46.702644 tx_last_pass[1][0][2] = 1006
4209 11:03:46.706107 tx_win_center[1][0][3] = 991
4210 11:03:46.708931 tx_first_pass[1][0][3] = 978
4211 11:03:46.712503 tx_last_pass[1][0][3] = 1005
4212 11:03:46.712602 tx_win_center[1][0][4] = 996
4213 11:03:46.715431 tx_first_pass[1][0][4] = 984
4214 11:03:46.718795 tx_last_pass[1][0][4] = 1008
4215 11:03:46.722067 tx_win_center[1][0][5] = 996
4216 11:03:46.725379 tx_first_pass[1][0][5] = 984
4217 11:03:46.725450 tx_last_pass[1][0][5] = 1008
4218 11:03:46.728690 tx_win_center[1][0][6] = 995
4219 11:03:46.731941 tx_first_pass[1][0][6] = 983
4220 11:03:46.735418 tx_last_pass[1][0][6] = 1008
4221 11:03:46.738229 tx_win_center[1][0][7] = 995
4222 11:03:46.738299 tx_first_pass[1][0][7] = 983
4223 11:03:46.741509 tx_last_pass[1][0][7] = 1007
4224 11:03:46.745256 tx_win_center[1][0][8] = 990
4225 11:03:46.748699 tx_first_pass[1][0][8] = 979
4226 11:03:46.751775 tx_last_pass[1][0][8] = 1002
4227 11:03:46.751844 tx_win_center[1][0][9] = 990
4228 11:03:46.754954 tx_first_pass[1][0][9] = 979
4229 11:03:46.758068 tx_last_pass[1][0][9] = 1001
4230 11:03:46.761722 tx_win_center[1][0][10] = 992
4231 11:03:46.764896 tx_first_pass[1][0][10] = 982
4232 11:03:46.764980 tx_last_pass[1][0][10] = 1003
4233 11:03:46.768238 tx_win_center[1][0][11] = 993
4234 11:03:46.771078 tx_first_pass[1][0][11] = 982
4235 11:03:46.774811 tx_last_pass[1][0][11] = 1004
4236 11:03:46.778044 tx_win_center[1][0][12] = 993
4237 11:03:46.781041 tx_first_pass[1][0][12] = 983
4238 11:03:46.781119 tx_last_pass[1][0][12] = 1004
4239 11:03:46.784211 tx_win_center[1][0][13] = 994
4240 11:03:46.788070 tx_first_pass[1][0][13] = 984
4241 11:03:46.791233 tx_last_pass[1][0][13] = 1004
4242 11:03:46.794465 tx_win_center[1][0][14] = 992
4243 11:03:46.797690 tx_first_pass[1][0][14] = 982
4244 11:03:46.797767 tx_last_pass[1][0][14] = 1003
4245 11:03:46.800997 tx_win_center[1][0][15] = 987
4246 11:03:46.804035 tx_first_pass[1][0][15] = 976
4247 11:03:46.807189 tx_last_pass[1][0][15] = 998
4248 11:03:46.810434 tx_win_center[1][1][0] = 994
4249 11:03:46.810511 tx_first_pass[1][1][0] = 982
4250 11:03:46.813998 tx_last_pass[1][1][0] = 1007
4251 11:03:46.817414 tx_win_center[1][1][1] = 993
4252 11:03:46.820650 tx_first_pass[1][1][1] = 980
4253 11:03:46.823599 tx_last_pass[1][1][1] = 1006
4254 11:03:46.823675 tx_win_center[1][1][2] = 990
4255 11:03:46.827230 tx_first_pass[1][1][2] = 978
4256 11:03:46.830114 tx_last_pass[1][1][2] = 1003
4257 11:03:46.833446 tx_win_center[1][1][3] = 988
4258 11:03:46.836882 tx_first_pass[1][1][3] = 976
4259 11:03:46.836984 tx_last_pass[1][1][3] = 1000
4260 11:03:46.840535 tx_win_center[1][1][4] = 993
4261 11:03:46.843455 tx_first_pass[1][1][4] = 980
4262 11:03:46.846734 tx_last_pass[1][1][4] = 1006
4263 11:03:46.850078 tx_win_center[1][1][5] = 993
4264 11:03:46.850157 tx_first_pass[1][1][5] = 981
4265 11:03:46.853394 tx_last_pass[1][1][5] = 1006
4266 11:03:46.856298 tx_win_center[1][1][6] = 993
4267 11:03:46.859693 tx_first_pass[1][1][6] = 980
4268 11:03:46.862942 tx_last_pass[1][1][6] = 1006
4269 11:03:46.863018 tx_win_center[1][1][7] = 992
4270 11:03:46.866509 tx_first_pass[1][1][7] = 979
4271 11:03:46.869492 tx_last_pass[1][1][7] = 1006
4272 11:03:46.873199 tx_win_center[1][1][8] = 984
4273 11:03:46.876192 tx_first_pass[1][1][8] = 972
4274 11:03:46.876268 tx_last_pass[1][1][8] = 996
4275 11:03:46.879762 tx_win_center[1][1][9] = 983
4276 11:03:46.882745 tx_first_pass[1][1][9] = 972
4277 11:03:46.886330 tx_last_pass[1][1][9] = 995
4278 11:03:46.886404 tx_win_center[1][1][10] = 987
4279 11:03:46.889325 tx_first_pass[1][1][10] = 975
4280 11:03:46.892868 tx_last_pass[1][1][10] = 1000
4281 11:03:46.896099 tx_win_center[1][1][11] = 987
4282 11:03:46.899436 tx_first_pass[1][1][11] = 976
4283 11:03:46.902706 tx_last_pass[1][1][11] = 999
4284 11:03:46.902781 tx_win_center[1][1][12] = 987
4285 11:03:46.906249 tx_first_pass[1][1][12] = 976
4286 11:03:46.909211 tx_last_pass[1][1][12] = 999
4287 11:03:46.912697 tx_win_center[1][1][13] = 988
4288 11:03:46.915646 tx_first_pass[1][1][13] = 976
4289 11:03:46.915714 tx_last_pass[1][1][13] = 1000
4290 11:03:46.919142 tx_win_center[1][1][14] = 987
4291 11:03:46.922077 tx_first_pass[1][1][14] = 976
4292 11:03:46.925807 tx_last_pass[1][1][14] = 999
4293 11:03:46.929303 tx_win_center[1][1][15] = 981
4294 11:03:46.932337 tx_first_pass[1][1][15] = 970
4295 11:03:46.932402 tx_last_pass[1][1][15] = 993
4296 11:03:46.935663 dump params rx window
4297 11:03:46.938993 rx_firspass[0][0][0] = 5
4298 11:03:46.939058 rx_lastpass[0][0][0] = 39
4299 11:03:46.941897 rx_firspass[0][0][1] = 5
4300 11:03:46.945308 rx_lastpass[0][0][1] = 37
4301 11:03:46.945374 rx_firspass[0][0][2] = 7
4302 11:03:46.948687 rx_lastpass[0][0][2] = 38
4303 11:03:46.951806 rx_firspass[0][0][3] = -1
4304 11:03:46.954712 rx_lastpass[0][0][3] = 30
4305 11:03:46.954804 rx_firspass[0][0][4] = 5
4306 11:03:46.958384 rx_lastpass[0][0][4] = 36
4307 11:03:46.961523 rx_firspass[0][0][5] = 1
4308 11:03:46.965034 rx_lastpass[0][0][5] = 33
4309 11:03:46.965156 rx_firspass[0][0][6] = 4
4310 11:03:46.968192 rx_lastpass[0][0][6] = 34
4311 11:03:46.971240 rx_firspass[0][0][7] = 7
4312 11:03:46.971332 rx_lastpass[0][0][7] = 36
4313 11:03:46.974828 rx_firspass[0][0][8] = -1
4314 11:03:46.977997 rx_lastpass[0][0][8] = 31
4315 11:03:46.978134 rx_firspass[0][0][9] = 1
4316 11:03:46.981412 rx_lastpass[0][0][9] = 32
4317 11:03:46.984419 rx_firspass[0][0][10] = 9
4318 11:03:46.987717 rx_lastpass[0][0][10] = 40
4319 11:03:46.987845 rx_firspass[0][0][11] = 1
4320 11:03:46.990938 rx_lastpass[0][0][11] = 31
4321 11:03:46.994653 rx_firspass[0][0][12] = 1
4322 11:03:46.997952 rx_lastpass[0][0][12] = 34
4323 11:03:46.998068 rx_firspass[0][0][13] = 2
4324 11:03:47.000753 rx_lastpass[0][0][13] = 33
4325 11:03:47.004123 rx_firspass[0][0][14] = 3
4326 11:03:47.007294 rx_lastpass[0][0][14] = 36
4327 11:03:47.007387 rx_firspass[0][0][15] = 6
4328 11:03:47.010748 rx_lastpass[0][0][15] = 38
4329 11:03:47.013753 rx_firspass[0][1][0] = 4
4330 11:03:47.013845 rx_lastpass[0][1][0] = 38
4331 11:03:47.017011 rx_firspass[0][1][1] = 2
4332 11:03:47.020266 rx_lastpass[0][1][1] = 39
4333 11:03:47.023844 rx_firspass[0][1][2] = 5
4334 11:03:47.023916 rx_lastpass[0][1][2] = 40
4335 11:03:47.027379 rx_firspass[0][1][3] = -3
4336 11:03:47.030529 rx_lastpass[0][1][3] = 31
4337 11:03:47.030605 rx_firspass[0][1][4] = 5
4338 11:03:47.033894 rx_lastpass[0][1][4] = 38
4339 11:03:47.036902 rx_firspass[0][1][5] = 0
4340 11:03:47.040211 rx_lastpass[0][1][5] = 32
4341 11:03:47.040287 rx_firspass[0][1][6] = 1
4342 11:03:47.043650 rx_lastpass[0][1][6] = 35
4343 11:03:47.046901 rx_firspass[0][1][7] = 4
4344 11:03:47.046978 rx_lastpass[0][1][7] = 37
4345 11:03:47.050169 rx_firspass[0][1][8] = 0
4346 11:03:47.053259 rx_lastpass[0][1][8] = 33
4347 11:03:47.057127 rx_firspass[0][1][9] = 2
4348 11:03:47.057222 rx_lastpass[0][1][9] = 35
4349 11:03:47.059864 rx_firspass[0][1][10] = 9
4350 11:03:47.063028 rx_lastpass[0][1][10] = 42
4351 11:03:47.063106 rx_firspass[0][1][11] = 0
4352 11:03:47.066884 rx_lastpass[0][1][11] = 33
4353 11:03:47.070267 rx_firspass[0][1][12] = 3
4354 11:03:47.073283 rx_lastpass[0][1][12] = 36
4355 11:03:47.073357 rx_firspass[0][1][13] = 3
4356 11:03:47.076571 rx_lastpass[0][1][13] = 36
4357 11:03:47.079387 rx_firspass[0][1][14] = 5
4358 11:03:47.083001 rx_lastpass[0][1][14] = 37
4359 11:03:47.083075 rx_firspass[0][1][15] = 6
4360 11:03:47.086831 rx_lastpass[0][1][15] = 40
4361 11:03:47.089509 rx_firspass[1][0][0] = 5
4362 11:03:47.089573 rx_lastpass[1][0][0] = 39
4363 11:03:47.092899 rx_firspass[1][0][1] = 4
4364 11:03:47.095857 rx_lastpass[1][0][1] = 36
4365 11:03:47.099403 rx_firspass[1][0][2] = 4
4366 11:03:47.099480 rx_lastpass[1][0][2] = 35
4367 11:03:47.102786 rx_firspass[1][0][3] = -1
4368 11:03:47.106096 rx_lastpass[1][0][3] = 33
4369 11:03:47.106173 rx_firspass[1][0][4] = 5
4370 11:03:47.109273 rx_lastpass[1][0][4] = 35
4371 11:03:47.112462 rx_firspass[1][0][5] = 7
4372 11:03:47.115742 rx_lastpass[1][0][5] = 38
4373 11:03:47.115820 rx_firspass[1][0][6] = 10
4374 11:03:47.119350 rx_lastpass[1][0][6] = 38
4375 11:03:47.122432 rx_firspass[1][0][7] = 6
4376 11:03:47.122509 rx_lastpass[1][0][7] = 36
4377 11:03:47.125581 rx_firspass[1][0][8] = 1
4378 11:03:47.128895 rx_lastpass[1][0][8] = 32
4379 11:03:47.132281 rx_firspass[1][0][9] = 2
4380 11:03:47.132389 rx_lastpass[1][0][9] = 31
4381 11:03:47.135715 rx_firspass[1][0][10] = 7
4382 11:03:47.138414 rx_lastpass[1][0][10] = 35
4383 11:03:47.142483 rx_firspass[1][0][11] = 7
4384 11:03:47.142567 rx_lastpass[1][0][11] = 35
4385 11:03:47.145618 rx_firspass[1][0][12] = 6
4386 11:03:47.148501 rx_lastpass[1][0][12] = 37
4387 11:03:47.148583 rx_firspass[1][0][13] = 7
4388 11:03:47.151640 rx_lastpass[1][0][13] = 35
4389 11:03:47.154873 rx_firspass[1][0][14] = 8
4390 11:03:47.158527 rx_lastpass[1][0][14] = 36
4391 11:03:47.158647 rx_firspass[1][0][15] = 0
4392 11:03:47.161395 rx_lastpass[1][0][15] = 28
4393 11:03:47.164647 rx_firspass[1][1][0] = 6
4394 11:03:47.168526 rx_lastpass[1][1][0] = 38
4395 11:03:47.168602 rx_firspass[1][1][1] = 3
4396 11:03:47.171294 rx_lastpass[1][1][1] = 37
4397 11:03:47.174516 rx_firspass[1][1][2] = 3
4398 11:03:47.174595 rx_lastpass[1][1][2] = 34
4399 11:03:47.177933 rx_firspass[1][1][3] = 0
4400 11:03:47.181010 rx_lastpass[1][1][3] = 31
4401 11:03:47.184830 rx_firspass[1][1][4] = 3
4402 11:03:47.184923 rx_lastpass[1][1][4] = 38
4403 11:03:47.187820 rx_firspass[1][1][5] = 5
4404 11:03:47.191371 rx_lastpass[1][1][5] = 40
4405 11:03:47.191460 rx_firspass[1][1][6] = 7
4406 11:03:47.194520 rx_lastpass[1][1][6] = 40
4407 11:03:47.197838 rx_firspass[1][1][7] = 4
4408 11:03:47.201013 rx_lastpass[1][1][7] = 37
4409 11:03:47.201100 rx_firspass[1][1][8] = 2
4410 11:03:47.204209 rx_lastpass[1][1][8] = 34
4411 11:03:47.207588 rx_firspass[1][1][9] = 2
4412 11:03:47.207658 rx_lastpass[1][1][9] = 34
4413 11:03:47.210570 rx_firspass[1][1][10] = 4
4414 11:03:47.213928 rx_lastpass[1][1][10] = 38
4415 11:03:47.217071 rx_firspass[1][1][11] = 6
4416 11:03:47.217142 rx_lastpass[1][1][11] = 39
4417 11:03:47.220688 rx_firspass[1][1][12] = 7
4418 11:03:47.223589 rx_lastpass[1][1][12] = 38
4419 11:03:47.223655 rx_firspass[1][1][13] = 7
4420 11:03:47.227075 rx_lastpass[1][1][13] = 39
4421 11:03:47.230552 rx_firspass[1][1][14] = 5
4422 11:03:47.233857 rx_lastpass[1][1][14] = 39
4423 11:03:47.233924 rx_firspass[1][1][15] = -1
4424 11:03:47.236689 rx_lastpass[1][1][15] = 31
4425 11:03:47.240669 dump params clk_delay
4426 11:03:47.240754 clk_delay[0] = 1
4427 11:03:47.243449 clk_delay[1] = 0
4428 11:03:47.243524 dump params dqs_delay
4429 11:03:47.246712 dqs_delay[0][0] = 0
4430 11:03:47.246788 dqs_delay[0][1] = 0
4431 11:03:47.249973 dqs_delay[1][0] = -1
4432 11:03:47.253116 dqs_delay[1][1] = 0
4433 11:03:47.256979 dump params delay_cell_unit = 744
4434 11:03:47.257081 dump source = 0x0
4435 11:03:47.260088 dump params frequency:1200
4436 11:03:47.260211 dump params rank number:2
4437 11:03:47.263280
4438 11:03:47.263364 dump params write leveling
4439 11:03:47.266494 write leveling[0][0][0] = 0x0
4440 11:03:47.269409 write leveling[0][0][1] = 0x0
4441 11:03:47.273138 write leveling[0][1][0] = 0x0
4442 11:03:47.276157 write leveling[0][1][1] = 0x0
4443 11:03:47.276231 write leveling[1][0][0] = 0x0
4444 11:03:47.279419 write leveling[1][0][1] = 0x0
4445 11:03:47.282617 write leveling[1][1][0] = 0x0
4446 11:03:47.286304 write leveling[1][1][1] = 0x0
4447 11:03:47.286393 dump params cbt_cs
4448 11:03:47.289302 cbt_cs[0][0] = 0x0
4449 11:03:47.289390 cbt_cs[0][1] = 0x0
4450 11:03:47.292765 cbt_cs[1][0] = 0x0
4451 11:03:47.292858 cbt_cs[1][1] = 0x0
4452 11:03:47.295663 dump params cbt_mr12
4453 11:03:47.299022 cbt_mr12[0][0] = 0x0
4454 11:03:47.299090 cbt_mr12[0][1] = 0x0
4455 11:03:47.302506 cbt_mr12[1][0] = 0x0
4456 11:03:47.302584 cbt_mr12[1][1] = 0x0
4457 11:03:47.305713 dump params tx window
4458 11:03:47.308828 tx_center_min[0][0][0] = 0
4459 11:03:47.308918 tx_center_max[0][0][0] = 0
4460 11:03:47.312171 tx_center_min[0][0][1] = 0
4461 11:03:47.316120 tx_center_max[0][0][1] = 0
4462 11:03:47.318695 tx_center_min[0][1][0] = 0
4463 11:03:47.318758 tx_center_max[0][1][0] = 0
4464 11:03:47.322065 tx_center_min[0][1][1] = 0
4465 11:03:47.325347 tx_center_max[0][1][1] = 0
4466 11:03:47.328413 tx_center_min[1][0][0] = 0
4467 11:03:47.328485 tx_center_max[1][0][0] = 0
4468 11:03:47.332011 tx_center_min[1][0][1] = 0
4469 11:03:47.335275 tx_center_max[1][0][1] = 0
4470 11:03:47.338432 tx_center_min[1][1][0] = 0
4471 11:03:47.338500 tx_center_max[1][1][0] = 0
4472 11:03:47.341968 tx_center_min[1][1][1] = 0
4473 11:03:47.345348 tx_center_max[1][1][1] = 0
4474 11:03:47.345442 dump params tx window
4475 11:03:47.348395 tx_win_center[0][0][0] = 0
4476 11:03:47.351958 tx_first_pass[0][0][0] = 0
4477 11:03:47.355194 tx_last_pass[0][0][0] = 0
4478 11:03:47.355258 tx_win_center[0][0][1] = 0
4479 11:03:47.358649 tx_first_pass[0][0][1] = 0
4480 11:03:47.362161 tx_last_pass[0][0][1] = 0
4481 11:03:47.365160 tx_win_center[0][0][2] = 0
4482 11:03:47.365254 tx_first_pass[0][0][2] = 0
4483 11:03:47.367880 tx_last_pass[0][0][2] = 0
4484 11:03:47.371149 tx_win_center[0][0][3] = 0
4485 11:03:47.374803 tx_first_pass[0][0][3] = 0
4486 11:03:47.374873 tx_last_pass[0][0][3] = 0
4487 11:03:47.377926 tx_win_center[0][0][4] = 0
4488 11:03:47.381327 tx_first_pass[0][0][4] = 0
4489 11:03:47.384551 tx_last_pass[0][0][4] = 0
4490 11:03:47.384617 tx_win_center[0][0][5] = 0
4491 11:03:47.387884 tx_first_pass[0][0][5] = 0
4492 11:03:47.391039 tx_last_pass[0][0][5] = 0
4493 11:03:47.391104 tx_win_center[0][0][6] = 0
4494 11:03:47.394682 tx_first_pass[0][0][6] = 0
4495 11:03:47.398037 tx_last_pass[0][0][6] = 0
4496 11:03:47.400936 tx_win_center[0][0][7] = 0
4497 11:03:47.401002 tx_first_pass[0][0][7] = 0
4498 11:03:47.404413 tx_last_pass[0][0][7] = 0
4499 11:03:47.407293 tx_win_center[0][0][8] = 0
4500 11:03:47.410761 tx_first_pass[0][0][8] = 0
4501 11:03:47.410827 tx_last_pass[0][0][8] = 0
4502 11:03:47.414441 tx_win_center[0][0][9] = 0
4503 11:03:47.417207 tx_first_pass[0][0][9] = 0
4504 11:03:47.420841 tx_last_pass[0][0][9] = 0
4505 11:03:47.420909 tx_win_center[0][0][10] = 0
4506 11:03:47.423880 tx_first_pass[0][0][10] = 0
4507 11:03:47.426918 tx_last_pass[0][0][10] = 0
4508 11:03:47.430106 tx_win_center[0][0][11] = 0
4509 11:03:47.430170 tx_first_pass[0][0][11] = 0
4510 11:03:47.433971 tx_last_pass[0][0][11] = 0
4511 11:03:47.436809 tx_win_center[0][0][12] = 0
4512 11:03:47.440338 tx_first_pass[0][0][12] = 0
4513 11:03:47.440404 tx_last_pass[0][0][12] = 0
4514 11:03:47.443502 tx_win_center[0][0][13] = 0
4515 11:03:47.446573 tx_first_pass[0][0][13] = 0
4516 11:03:47.449746 tx_last_pass[0][0][13] = 0
4517 11:03:47.449811 tx_win_center[0][0][14] = 0
4518 11:03:47.453556 tx_first_pass[0][0][14] = 0
4519 11:03:47.456473 tx_last_pass[0][0][14] = 0
4520 11:03:47.460150 tx_win_center[0][0][15] = 0
4521 11:03:47.463312 tx_first_pass[0][0][15] = 0
4522 11:03:47.463407 tx_last_pass[0][0][15] = 0
4523 11:03:47.466500 tx_win_center[0][1][0] = 0
4524 11:03:47.469970 tx_first_pass[0][1][0] = 0
4525 11:03:47.473079 tx_last_pass[0][1][0] = 0
4526 11:03:47.473152 tx_win_center[0][1][1] = 0
4527 11:03:47.476150 tx_first_pass[0][1][1] = 0
4528 11:03:47.479780 tx_last_pass[0][1][1] = 0
4529 11:03:47.479852 tx_win_center[0][1][2] = 0
4530 11:03:47.483232 tx_first_pass[0][1][2] = 0
4531 11:03:47.486361 tx_last_pass[0][1][2] = 0
4532 11:03:47.489550 tx_win_center[0][1][3] = 0
4533 11:03:47.489628 tx_first_pass[0][1][3] = 0
4534 11:03:47.492501 tx_last_pass[0][1][3] = 0
4535 11:03:47.495730 tx_win_center[0][1][4] = 0
4536 11:03:47.499542 tx_first_pass[0][1][4] = 0
4537 11:03:47.499618 tx_last_pass[0][1][4] = 0
4538 11:03:47.502273 tx_win_center[0][1][5] = 0
4539 11:03:47.505995 tx_first_pass[0][1][5] = 0
4540 11:03:47.509243 tx_last_pass[0][1][5] = 0
4541 11:03:47.509319 tx_win_center[0][1][6] = 0
4542 11:03:47.512606 tx_first_pass[0][1][6] = 0
4543 11:03:47.516054 tx_last_pass[0][1][6] = 0
4544 11:03:47.516131 tx_win_center[0][1][7] = 0
4545 11:03:47.519020 tx_first_pass[0][1][7] = 0
4546 11:03:47.522302 tx_last_pass[0][1][7] = 0
4547 11:03:47.525755 tx_win_center[0][1][8] = 0
4548 11:03:47.525831 tx_first_pass[0][1][8] = 0
4549 11:03:47.528646 tx_last_pass[0][1][8] = 0
4550 11:03:47.531962 tx_win_center[0][1][9] = 0
4551 11:03:47.535652 tx_first_pass[0][1][9] = 0
4552 11:03:47.535727 tx_last_pass[0][1][9] = 0
4553 11:03:47.539049 tx_win_center[0][1][10] = 0
4554 11:03:47.542002 tx_first_pass[0][1][10] = 0
4555 11:03:47.545301 tx_last_pass[0][1][10] = 0
4556 11:03:47.545376 tx_win_center[0][1][11] = 0
4557 11:03:47.548435 tx_first_pass[0][1][11] = 0
4558 11:03:47.551816 tx_last_pass[0][1][11] = 0
4559 11:03:47.555097 tx_win_center[0][1][12] = 0
4560 11:03:47.555173 tx_first_pass[0][1][12] = 0
4561 11:03:47.558428 tx_last_pass[0][1][12] = 0
4562 11:03:47.562132 tx_win_center[0][1][13] = 0
4563 11:03:47.565329 tx_first_pass[0][1][13] = 0
4564 11:03:47.565404 tx_last_pass[0][1][13] = 0
4565 11:03:47.568502 tx_win_center[0][1][14] = 0
4566 11:03:47.571653 tx_first_pass[0][1][14] = 0
4567 11:03:47.574641 tx_last_pass[0][1][14] = 0
4568 11:03:47.578295 tx_win_center[0][1][15] = 0
4569 11:03:47.578371 tx_first_pass[0][1][15] = 0
4570 11:03:47.581619 tx_last_pass[0][1][15] = 0
4571 11:03:47.585526 tx_win_center[1][0][0] = 0
4572 11:03:47.587982 tx_first_pass[1][0][0] = 0
4573 11:03:47.588059 tx_last_pass[1][0][0] = 0
4574 11:03:47.591385 tx_win_center[1][0][1] = 0
4575 11:03:47.594996 tx_first_pass[1][0][1] = 0
4576 11:03:47.595072 tx_last_pass[1][0][1] = 0
4577 11:03:47.597513 tx_win_center[1][0][2] = 0
4578 11:03:47.601471 tx_first_pass[1][0][2] = 0
4579 11:03:47.604410 tx_last_pass[1][0][2] = 0
4580 11:03:47.604486 tx_win_center[1][0][3] = 0
4581 11:03:47.607868 tx_first_pass[1][0][3] = 0
4582 11:03:47.610959 tx_last_pass[1][0][3] = 0
4583 11:03:47.614119 tx_win_center[1][0][4] = 0
4584 11:03:47.614195 tx_first_pass[1][0][4] = 0
4585 11:03:47.617366 tx_last_pass[1][0][4] = 0
4586 11:03:47.620702 tx_win_center[1][0][5] = 0
4587 11:03:47.623855 tx_first_pass[1][0][5] = 0
4588 11:03:47.623930 tx_last_pass[1][0][5] = 0
4589 11:03:47.627319 tx_win_center[1][0][6] = 0
4590 11:03:47.630654 tx_first_pass[1][0][6] = 0
4591 11:03:47.633706 tx_last_pass[1][0][6] = 0
4592 11:03:47.633781 tx_win_center[1][0][7] = 0
4593 11:03:47.636758 tx_first_pass[1][0][7] = 0
4594 11:03:47.640139 tx_last_pass[1][0][7] = 0
4595 11:03:47.640214 tx_win_center[1][0][8] = 0
4596 11:03:47.644269 tx_first_pass[1][0][8] = 0
4597 11:03:47.646578 tx_last_pass[1][0][8] = 0
4598 11:03:47.649904 tx_win_center[1][0][9] = 0
4599 11:03:47.649979 tx_first_pass[1][0][9] = 0
4600 11:03:47.653537 tx_last_pass[1][0][9] = 0
4601 11:03:47.656878 tx_win_center[1][0][10] = 0
4602 11:03:47.659980 tx_first_pass[1][0][10] = 0
4603 11:03:47.660055 tx_last_pass[1][0][10] = 0
4604 11:03:47.663082 tx_win_center[1][0][11] = 0
4605 11:03:47.666358 tx_first_pass[1][0][11] = 0
4606 11:03:47.670159 tx_last_pass[1][0][11] = 0
4607 11:03:47.672782 tx_win_center[1][0][12] = 0
4608 11:03:47.672858 tx_first_pass[1][0][12] = 0
4609 11:03:47.676226 tx_last_pass[1][0][12] = 0
4610 11:03:47.679725 tx_win_center[1][0][13] = 0
4611 11:03:47.682650 tx_first_pass[1][0][13] = 0
4612 11:03:47.682727 tx_last_pass[1][0][13] = 0
4613 11:03:47.686013 tx_win_center[1][0][14] = 0
4614 11:03:47.689365 tx_first_pass[1][0][14] = 0
4615 11:03:47.692479 tx_last_pass[1][0][14] = 0
4616 11:03:47.692556 tx_win_center[1][0][15] = 0
4617 11:03:47.695993 tx_first_pass[1][0][15] = 0
4618 11:03:47.699619 tx_last_pass[1][0][15] = 0
4619 11:03:47.702606 tx_win_center[1][1][0] = 0
4620 11:03:47.702726 tx_first_pass[1][1][0] = 0
4621 11:03:47.705674 tx_last_pass[1][1][0] = 0
4622 11:03:47.708902 tx_win_center[1][1][1] = 0
4623 11:03:47.712386 tx_first_pass[1][1][1] = 0
4624 11:03:47.712496 tx_last_pass[1][1][1] = 0
4625 11:03:47.715385 tx_win_center[1][1][2] = 0
4626 11:03:47.718916 tx_first_pass[1][1][2] = 0
4627 11:03:47.721978 tx_last_pass[1][1][2] = 0
4628 11:03:47.722078 tx_win_center[1][1][3] = 0
4629 11:03:47.725461 tx_first_pass[1][1][3] = 0
4630 11:03:47.728709 tx_last_pass[1][1][3] = 0
4631 11:03:47.728803 tx_win_center[1][1][4] = 0
4632 11:03:47.732361 tx_first_pass[1][1][4] = 0
4633 11:03:47.735477 tx_last_pass[1][1][4] = 0
4634 11:03:47.738451 tx_win_center[1][1][5] = 0
4635 11:03:47.738542 tx_first_pass[1][1][5] = 0
4636 11:03:47.741700 tx_last_pass[1][1][5] = 0
4637 11:03:47.745270 tx_win_center[1][1][6] = 0
4638 11:03:47.748599 tx_first_pass[1][1][6] = 0
4639 11:03:47.748675 tx_last_pass[1][1][6] = 0
4640 11:03:47.751709 tx_win_center[1][1][7] = 0
4641 11:03:47.754867 tx_first_pass[1][1][7] = 0
4642 11:03:47.758607 tx_last_pass[1][1][7] = 0
4643 11:03:47.758684 tx_win_center[1][1][8] = 0
4644 11:03:47.761706 tx_first_pass[1][1][8] = 0
4645 11:03:47.764838 tx_last_pass[1][1][8] = 0
4646 11:03:47.764916 tx_win_center[1][1][9] = 0
4647 11:03:47.768274 tx_first_pass[1][1][9] = 0
4648 11:03:47.771333 tx_last_pass[1][1][9] = 0
4649 11:03:47.775553 tx_win_center[1][1][10] = 0
4650 11:03:47.775630 tx_first_pass[1][1][10] = 0
4651 11:03:47.777972 tx_last_pass[1][1][10] = 0
4652 11:03:47.781241 tx_win_center[1][1][11] = 0
4653 11:03:47.784510 tx_first_pass[1][1][11] = 0
4654 11:03:47.784587 tx_last_pass[1][1][11] = 0
4655 11:03:47.788335 tx_win_center[1][1][12] = 0
4656 11:03:47.791534 tx_first_pass[1][1][12] = 0
4657 11:03:47.794640 tx_last_pass[1][1][12] = 0
4658 11:03:47.794717 tx_win_center[1][1][13] = 0
4659 11:03:47.798157 tx_first_pass[1][1][13] = 0
4660 11:03:47.800919 tx_last_pass[1][1][13] = 0
4661 11:03:47.804266 tx_win_center[1][1][14] = 0
4662 11:03:47.807484 tx_first_pass[1][1][14] = 0
4663 11:03:47.807560 tx_last_pass[1][1][14] = 0
4664 11:03:47.811025 tx_win_center[1][1][15] = 0
4665 11:03:47.814671 tx_first_pass[1][1][15] = 0
4666 11:03:47.817417 tx_last_pass[1][1][15] = 0
4667 11:03:47.817487 dump params rx window
4668 11:03:47.820537 rx_firspass[0][0][0] = 0
4669 11:03:47.824123 rx_lastpass[0][0][0] = 0
4670 11:03:47.824199 rx_firspass[0][0][1] = 0
4671 11:03:47.827506 rx_lastpass[0][0][1] = 0
4672 11:03:47.830813 rx_firspass[0][0][2] = 0
4673 11:03:47.830882 rx_lastpass[0][0][2] = 0
4674 11:03:47.833872 rx_firspass[0][0][3] = 0
4675 11:03:47.837255 rx_lastpass[0][0][3] = 0
4676 11:03:47.837353 rx_firspass[0][0][4] = 0
4677 11:03:47.840372 rx_lastpass[0][0][4] = 0
4678 11:03:47.843555 rx_firspass[0][0][5] = 0
4679 11:03:47.846788 rx_lastpass[0][0][5] = 0
4680 11:03:47.846858 rx_firspass[0][0][6] = 0
4681 11:03:47.850442 rx_lastpass[0][0][6] = 0
4682 11:03:47.853404 rx_firspass[0][0][7] = 0
4683 11:03:47.853469 rx_lastpass[0][0][7] = 0
4684 11:03:47.856515 rx_firspass[0][0][8] = 0
4685 11:03:47.860151 rx_lastpass[0][0][8] = 0
4686 11:03:47.860241 rx_firspass[0][0][9] = 0
4687 11:03:47.863418 rx_lastpass[0][0][9] = 0
4688 11:03:47.866562 rx_firspass[0][0][10] = 0
4689 11:03:47.870143 rx_lastpass[0][0][10] = 0
4690 11:03:47.870218 rx_firspass[0][0][11] = 0
4691 11:03:47.872929 rx_lastpass[0][0][11] = 0
4692 11:03:47.876202 rx_firspass[0][0][12] = 0
4693 11:03:47.876269 rx_lastpass[0][0][12] = 0
4694 11:03:47.879478 rx_firspass[0][0][13] = 0
4695 11:03:47.882832 rx_lastpass[0][0][13] = 0
4696 11:03:47.886536 rx_firspass[0][0][14] = 0
4697 11:03:47.886603 rx_lastpass[0][0][14] = 0
4698 11:03:47.889608 rx_firspass[0][0][15] = 0
4699 11:03:47.892671 rx_lastpass[0][0][15] = 0
4700 11:03:47.896062 rx_firspass[0][1][0] = 0
4701 11:03:47.896127 rx_lastpass[0][1][0] = 0
4702 11:03:47.899685 rx_firspass[0][1][1] = 0
4703 11:03:47.902459 rx_lastpass[0][1][1] = 0
4704 11:03:47.902528 rx_firspass[0][1][2] = 0
4705 11:03:47.905994 rx_lastpass[0][1][2] = 0
4706 11:03:47.908939 rx_firspass[0][1][3] = 0
4707 11:03:47.909009 rx_lastpass[0][1][3] = 0
4708 11:03:47.912480 rx_firspass[0][1][4] = 0
4709 11:03:47.916238 rx_lastpass[0][1][4] = 0
4710 11:03:47.916307 rx_firspass[0][1][5] = 0
4711 11:03:47.919214 rx_lastpass[0][1][5] = 0
4712 11:03:47.922657 rx_firspass[0][1][6] = 0
4713 11:03:47.925533 rx_lastpass[0][1][6] = 0
4714 11:03:47.925602 rx_firspass[0][1][7] = 0
4715 11:03:47.928978 rx_lastpass[0][1][7] = 0
4716 11:03:47.932004 rx_firspass[0][1][8] = 0
4717 11:03:47.932071 rx_lastpass[0][1][8] = 0
4718 11:03:47.935423 rx_firspass[0][1][9] = 0
4719 11:03:47.938462 rx_lastpass[0][1][9] = 0
4720 11:03:47.938532 rx_firspass[0][1][10] = 0
4721 11:03:47.942208 rx_lastpass[0][1][10] = 0
4722 11:03:47.945305 rx_firspass[0][1][11] = 0
4723 11:03:47.949332 rx_lastpass[0][1][11] = 0
4724 11:03:47.949398 rx_firspass[0][1][12] = 0
4725 11:03:47.951710 rx_lastpass[0][1][12] = 0
4726 11:03:47.955190 rx_firspass[0][1][13] = 0
4727 11:03:47.958483 rx_lastpass[0][1][13] = 0
4728 11:03:47.958575 rx_firspass[0][1][14] = 0
4729 11:03:47.961717 rx_lastpass[0][1][14] = 0
4730 11:03:47.965040 rx_firspass[0][1][15] = 0
4731 11:03:47.965134 rx_lastpass[0][1][15] = 0
4732 11:03:47.968469 rx_firspass[1][0][0] = 0
4733 11:03:47.971728 rx_lastpass[1][0][0] = 0
4734 11:03:47.971826 rx_firspass[1][0][1] = 0
4735 11:03:47.974853 rx_lastpass[1][0][1] = 0
4736 11:03:47.978137 rx_firspass[1][0][2] = 0
4737 11:03:47.981351 rx_lastpass[1][0][2] = 0
4738 11:03:47.981424 rx_firspass[1][0][3] = 0
4739 11:03:47.985170 rx_lastpass[1][0][3] = 0
4740 11:03:47.988222 rx_firspass[1][0][4] = 0
4741 11:03:47.988297 rx_lastpass[1][0][4] = 0
4742 11:03:47.991345 rx_firspass[1][0][5] = 0
4743 11:03:47.994338 rx_lastpass[1][0][5] = 0
4744 11:03:47.994412 rx_firspass[1][0][6] = 0
4745 11:03:47.997907 rx_lastpass[1][0][6] = 0
4746 11:03:48.001129 rx_firspass[1][0][7] = 0
4747 11:03:48.004512 rx_lastpass[1][0][7] = 0
4748 11:03:48.004586 rx_firspass[1][0][8] = 0
4749 11:03:48.007637 rx_lastpass[1][0][8] = 0
4750 11:03:48.010901 rx_firspass[1][0][9] = 0
4751 11:03:48.010975 rx_lastpass[1][0][9] = 0
4752 11:03:48.015206 rx_firspass[1][0][10] = 0
4753 11:03:48.017888 rx_lastpass[1][0][10] = 0
4754 11:03:48.018011 rx_firspass[1][0][11] = 0
4755 11:03:48.020740 rx_lastpass[1][0][11] = 0
4756 11:03:48.023971 rx_firspass[1][0][12] = 0
4757 11:03:48.027146 rx_lastpass[1][0][12] = 0
4758 11:03:48.027220 rx_firspass[1][0][13] = 0
4759 11:03:48.030838 rx_lastpass[1][0][13] = 0
4760 11:03:48.033703 rx_firspass[1][0][14] = 0
4761 11:03:48.037271 rx_lastpass[1][0][14] = 0
4762 11:03:48.037344 rx_firspass[1][0][15] = 0
4763 11:03:48.040730 rx_lastpass[1][0][15] = 0
4764 11:03:48.043904 rx_firspass[1][1][0] = 0
4765 11:03:48.043978 rx_lastpass[1][1][0] = 0
4766 11:03:48.047352 rx_firspass[1][1][1] = 0
4767 11:03:48.050469 rx_lastpass[1][1][1] = 0
4768 11:03:48.050566 rx_firspass[1][1][2] = 0
4769 11:03:48.053686 rx_lastpass[1][1][2] = 0
4770 11:03:48.056993 rx_firspass[1][1][3] = 0
4771 11:03:48.059983 rx_lastpass[1][1][3] = 0
4772 11:03:48.060066 rx_firspass[1][1][4] = 0
4773 11:03:48.063455 rx_lastpass[1][1][4] = 0
4774 11:03:48.066689 rx_firspass[1][1][5] = 0
4775 11:03:48.066801 rx_lastpass[1][1][5] = 0
4776 11:03:48.069760 rx_firspass[1][1][6] = 0
4777 11:03:48.073409 rx_lastpass[1][1][6] = 0
4778 11:03:48.073528 rx_firspass[1][1][7] = 0
4779 11:03:48.076505 rx_lastpass[1][1][7] = 0
4780 11:03:48.080238 rx_firspass[1][1][8] = 0
4781 11:03:48.083440 rx_lastpass[1][1][8] = 0
4782 11:03:48.083565 rx_firspass[1][1][9] = 0
4783 11:03:48.086440 rx_lastpass[1][1][9] = 0
4784 11:03:48.089944 rx_firspass[1][1][10] = 0
4785 11:03:48.090083 rx_lastpass[1][1][10] = 0
4786 11:03:48.093089 rx_firspass[1][1][11] = 0
4787 11:03:48.096178 rx_lastpass[1][1][11] = 0
4788 11:03:48.099598 rx_firspass[1][1][12] = 0
4789 11:03:48.099730 rx_lastpass[1][1][12] = 0
4790 11:03:48.103382 rx_firspass[1][1][13] = 0
4791 11:03:48.106132 rx_lastpass[1][1][13] = 0
4792 11:03:48.106211 rx_firspass[1][1][14] = 0
4793 11:03:48.109182 rx_lastpass[1][1][14] = 0
4794 11:03:48.112464 rx_firspass[1][1][15] = 0
4795 11:03:48.116014 rx_lastpass[1][1][15] = 0
4796 11:03:48.116089 dump params clk_delay
4797 11:03:48.119001 clk_delay[0] = 0
4798 11:03:48.119075 clk_delay[1] = 0
4799 11:03:48.122795 dump params dqs_delay
4800 11:03:48.122870 dqs_delay[0][0] = 0
4801 11:03:48.125880 dqs_delay[0][1] = 0
4802 11:03:48.125956 dqs_delay[1][0] = 0
4803 11:03:48.128800 dqs_delay[1][1] = 0
4804 11:03:48.132145 dump params delay_cell_unit = 744
4805 11:03:48.132222 dump source = 0x0
4806 11:03:48.135346 dump params frequency:800
4807 11:03:48.139082 dump params rank number:2
4808 11:03:48.139186
4809 11:03:48.142149 dump params write leveling
4810 11:03:48.142232 write leveling[0][0][0] = 0x0
4811 11:03:48.145358 write leveling[0][0][1] = 0x0
4812 11:03:48.148992 write leveling[0][1][0] = 0x0
4813 11:03:48.152168 write leveling[0][1][1] = 0x0
4814 11:03:48.155645 write leveling[1][0][0] = 0x0
4815 11:03:48.155727 write leveling[1][0][1] = 0x0
4816 11:03:48.158709 write leveling[1][1][0] = 0x0
4817 11:03:48.161931 write leveling[1][1][1] = 0x0
4818 11:03:48.165388 dump params cbt_cs
4819 11:03:48.165470 cbt_cs[0][0] = 0x0
4820 11:03:48.168539 cbt_cs[0][1] = 0x0
4821 11:03:48.168621 cbt_cs[1][0] = 0x0
4822 11:03:48.171630 cbt_cs[1][1] = 0x0
4823 11:03:48.171709 dump params cbt_mr12
4824 11:03:48.175109 cbt_mr12[0][0] = 0x0
4825 11:03:48.175186 cbt_mr12[0][1] = 0x0
4826 11:03:48.178441 cbt_mr12[1][0] = 0x0
4827 11:03:48.182096 cbt_mr12[1][1] = 0x0
4828 11:03:48.182180 dump params tx window
4829 11:03:48.184860 tx_center_min[0][0][0] = 0
4830 11:03:48.188271 tx_center_max[0][0][0] = 0
4831 11:03:48.188370 tx_center_min[0][0][1] = 0
4832 11:03:48.191365 tx_center_max[0][0][1] = 0
4833 11:03:48.194553 tx_center_min[0][1][0] = 0
4834 11:03:48.198222 tx_center_max[0][1][0] = 0
4835 11:03:48.198305 tx_center_min[0][1][1] = 0
4836 11:03:48.201646 tx_center_max[0][1][1] = 0
4837 11:03:48.205133 tx_center_min[1][0][0] = 0
4838 11:03:48.208657 tx_center_max[1][0][0] = 0
4839 11:03:48.208735 tx_center_min[1][0][1] = 0
4840 11:03:48.211343 tx_center_max[1][0][1] = 0
4841 11:03:48.214443 tx_center_min[1][1][0] = 0
4842 11:03:48.218080 tx_center_max[1][1][0] = 0
4843 11:03:48.218169 tx_center_min[1][1][1] = 0
4844 11:03:48.221412 tx_center_max[1][1][1] = 0
4845 11:03:48.224179 dump params tx window
4846 11:03:48.227371 tx_win_center[0][0][0] = 0
4847 11:03:48.227464 tx_first_pass[0][0][0] = 0
4848 11:03:48.231154 tx_last_pass[0][0][0] = 0
4849 11:03:48.234480 tx_win_center[0][0][1] = 0
4850 11:03:48.234573 tx_first_pass[0][0][1] = 0
4851 11:03:48.237139 tx_last_pass[0][0][1] = 0
4852 11:03:48.240881 tx_win_center[0][0][2] = 0
4853 11:03:48.243945 tx_first_pass[0][0][2] = 0
4854 11:03:48.244031 tx_last_pass[0][0][2] = 0
4855 11:03:48.247525 tx_win_center[0][0][3] = 0
4856 11:03:48.250524 tx_first_pass[0][0][3] = 0
4857 11:03:48.253914 tx_last_pass[0][0][3] = 0
4858 11:03:48.254042 tx_win_center[0][0][4] = 0
4859 11:03:48.257170 tx_first_pass[0][0][4] = 0
4860 11:03:48.260352 tx_last_pass[0][0][4] = 0
4861 11:03:48.263697 tx_win_center[0][0][5] = 0
4862 11:03:48.263778 tx_first_pass[0][0][5] = 0
4863 11:03:48.267091 tx_last_pass[0][0][5] = 0
4864 11:03:48.269893 tx_win_center[0][0][6] = 0
4865 11:03:48.273669 tx_first_pass[0][0][6] = 0
4866 11:03:48.273760 tx_last_pass[0][0][6] = 0
4867 11:03:48.277091 tx_win_center[0][0][7] = 0
4868 11:03:48.280385 tx_first_pass[0][0][7] = 0
4869 11:03:48.280474 tx_last_pass[0][0][7] = 0
4870 11:03:48.283508 tx_win_center[0][0][8] = 0
4871 11:03:48.286482 tx_first_pass[0][0][8] = 0
4872 11:03:48.289937 tx_last_pass[0][0][8] = 0
4873 11:03:48.290077 tx_win_center[0][0][9] = 0
4874 11:03:48.292983 tx_first_pass[0][0][9] = 0
4875 11:03:48.296658 tx_last_pass[0][0][9] = 0
4876 11:03:48.299821 tx_win_center[0][0][10] = 0
4877 11:03:48.299906 tx_first_pass[0][0][10] = 0
4878 11:03:48.303341 tx_last_pass[0][0][10] = 0
4879 11:03:48.306236 tx_win_center[0][0][11] = 0
4880 11:03:48.310130 tx_first_pass[0][0][11] = 0
4881 11:03:48.310208 tx_last_pass[0][0][11] = 0
4882 11:03:48.313498 tx_win_center[0][0][12] = 0
4883 11:03:48.316483 tx_first_pass[0][0][12] = 0
4884 11:03:48.319805 tx_last_pass[0][0][12] = 0
4885 11:03:48.319904 tx_win_center[0][0][13] = 0
4886 11:03:48.322912 tx_first_pass[0][0][13] = 0
4887 11:03:48.326383 tx_last_pass[0][0][13] = 0
4888 11:03:48.329412 tx_win_center[0][0][14] = 0
4889 11:03:48.329506 tx_first_pass[0][0][14] = 0
4890 11:03:48.332661 tx_last_pass[0][0][14] = 0
4891 11:03:48.335973 tx_win_center[0][0][15] = 0
4892 11:03:48.339293 tx_first_pass[0][0][15] = 0
4893 11:03:48.339368 tx_last_pass[0][0][15] = 0
4894 11:03:48.342619 tx_win_center[0][1][0] = 0
4895 11:03:48.345902 tx_first_pass[0][1][0] = 0
4896 11:03:48.349255 tx_last_pass[0][1][0] = 0
4897 11:03:48.349331 tx_win_center[0][1][1] = 0
4898 11:03:48.352094 tx_first_pass[0][1][1] = 0
4899 11:03:48.355555 tx_last_pass[0][1][1] = 0
4900 11:03:48.359341 tx_win_center[0][1][2] = 0
4901 11:03:48.359417 tx_first_pass[0][1][2] = 0
4902 11:03:48.362363 tx_last_pass[0][1][2] = 0
4903 11:03:48.365608 tx_win_center[0][1][3] = 0
4904 11:03:48.368906 tx_first_pass[0][1][3] = 0
4905 11:03:48.368982 tx_last_pass[0][1][3] = 0
4906 11:03:48.371866 tx_win_center[0][1][4] = 0
4907 11:03:48.375717 tx_first_pass[0][1][4] = 0
4908 11:03:48.378752 tx_last_pass[0][1][4] = 0
4909 11:03:48.378824 tx_win_center[0][1][5] = 0
4910 11:03:48.382062 tx_first_pass[0][1][5] = 0
4911 11:03:48.385105 tx_last_pass[0][1][5] = 0
4912 11:03:48.385197 tx_win_center[0][1][6] = 0
4913 11:03:48.388797 tx_first_pass[0][1][6] = 0
4914 11:03:48.391446 tx_last_pass[0][1][6] = 0
4915 11:03:48.394840 tx_win_center[0][1][7] = 0
4916 11:03:48.394913 tx_first_pass[0][1][7] = 0
4917 11:03:48.398096 tx_last_pass[0][1][7] = 0
4918 11:03:48.401554 tx_win_center[0][1][8] = 0
4919 11:03:48.405011 tx_first_pass[0][1][8] = 0
4920 11:03:48.405085 tx_last_pass[0][1][8] = 0
4921 11:03:48.407834 tx_win_center[0][1][9] = 0
4922 11:03:48.411836 tx_first_pass[0][1][9] = 0
4923 11:03:48.414607 tx_last_pass[0][1][9] = 0
4924 11:03:48.414683 tx_win_center[0][1][10] = 0
4925 11:03:48.418157 tx_first_pass[0][1][10] = 0
4926 11:03:48.421401 tx_last_pass[0][1][10] = 0
4927 11:03:48.424657 tx_win_center[0][1][11] = 0
4928 11:03:48.424736 tx_first_pass[0][1][11] = 0
4929 11:03:48.427840 tx_last_pass[0][1][11] = 0
4930 11:03:48.430998 tx_win_center[0][1][12] = 0
4931 11:03:48.434400 tx_first_pass[0][1][12] = 0
4932 11:03:48.434511 tx_last_pass[0][1][12] = 0
4933 11:03:48.437720 tx_win_center[0][1][13] = 0
4934 11:03:48.440987 tx_first_pass[0][1][13] = 0
4935 11:03:48.444326 tx_last_pass[0][1][13] = 0
4936 11:03:48.444445 tx_win_center[0][1][14] = 0
4937 11:03:48.447621 tx_first_pass[0][1][14] = 0
4938 11:03:48.451020 tx_last_pass[0][1][14] = 0
4939 11:03:48.453907 tx_win_center[0][1][15] = 0
4940 11:03:48.457004 tx_first_pass[0][1][15] = 0
4941 11:03:48.457124 tx_last_pass[0][1][15] = 0
4942 11:03:48.460312 tx_win_center[1][0][0] = 0
4943 11:03:48.463744 tx_first_pass[1][0][0] = 0
4944 11:03:48.463820 tx_last_pass[1][0][0] = 0
4945 11:03:48.466970 tx_win_center[1][0][1] = 0
4946 11:03:48.470281 tx_first_pass[1][0][1] = 0
4947 11:03:48.473989 tx_last_pass[1][0][1] = 0
4948 11:03:48.474075 tx_win_center[1][0][2] = 0
4949 11:03:48.477286 tx_first_pass[1][0][2] = 0
4950 11:03:48.480407 tx_last_pass[1][0][2] = 0
4951 11:03:48.483567 tx_win_center[1][0][3] = 0
4952 11:03:48.483643 tx_first_pass[1][0][3] = 0
4953 11:03:48.486998 tx_last_pass[1][0][3] = 0
4954 11:03:48.490493 tx_win_center[1][0][4] = 0
4955 11:03:48.493523 tx_first_pass[1][0][4] = 0
4956 11:03:48.493598 tx_last_pass[1][0][4] = 0
4957 11:03:48.496665 tx_win_center[1][0][5] = 0
4958 11:03:48.500028 tx_first_pass[1][0][5] = 0
4959 11:03:48.500104 tx_last_pass[1][0][5] = 0
4960 11:03:48.503479 tx_win_center[1][0][6] = 0
4961 11:03:48.506522 tx_first_pass[1][0][6] = 0
4962 11:03:48.510029 tx_last_pass[1][0][6] = 0
4963 11:03:48.510105 tx_win_center[1][0][7] = 0
4964 11:03:48.512998 tx_first_pass[1][0][7] = 0
4965 11:03:48.516427 tx_last_pass[1][0][7] = 0
4966 11:03:48.519393 tx_win_center[1][0][8] = 0
4967 11:03:48.519469 tx_first_pass[1][0][8] = 0
4968 11:03:48.522959 tx_last_pass[1][0][8] = 0
4969 11:03:48.526422 tx_win_center[1][0][9] = 0
4970 11:03:48.529563 tx_first_pass[1][0][9] = 0
4971 11:03:48.529636 tx_last_pass[1][0][9] = 0
4972 11:03:48.533132 tx_win_center[1][0][10] = 0
4973 11:03:48.536009 tx_first_pass[1][0][10] = 0
4974 11:03:48.539726 tx_last_pass[1][0][10] = 0
4975 11:03:48.539799 tx_win_center[1][0][11] = 0
4976 11:03:48.542332 tx_first_pass[1][0][11] = 0
4977 11:03:48.545884 tx_last_pass[1][0][11] = 0
4978 11:03:48.549486 tx_win_center[1][0][12] = 0
4979 11:03:48.549560 tx_first_pass[1][0][12] = 0
4980 11:03:48.552597 tx_last_pass[1][0][12] = 0
4981 11:03:48.555879 tx_win_center[1][0][13] = 0
4982 11:03:48.559148 tx_first_pass[1][0][13] = 0
4983 11:03:48.559223 tx_last_pass[1][0][13] = 0
4984 11:03:48.562568 tx_win_center[1][0][14] = 0
4985 11:03:48.565828 tx_first_pass[1][0][14] = 0
4986 11:03:48.569167 tx_last_pass[1][0][14] = 0
4987 11:03:48.572437 tx_win_center[1][0][15] = 0
4988 11:03:48.572513 tx_first_pass[1][0][15] = 0
4989 11:03:48.575947 tx_last_pass[1][0][15] = 0
4990 11:03:48.578772 tx_win_center[1][1][0] = 0
4991 11:03:48.582432 tx_first_pass[1][1][0] = 0
4992 11:03:48.582507 tx_last_pass[1][1][0] = 0
4993 11:03:48.585429 tx_win_center[1][1][1] = 0
4994 11:03:48.588582 tx_first_pass[1][1][1] = 0
4995 11:03:48.588673 tx_last_pass[1][1][1] = 0
4996 11:03:48.591972 tx_win_center[1][1][2] = 0
4997 11:03:48.595005 tx_first_pass[1][1][2] = 0
4998 11:03:48.598089 tx_last_pass[1][1][2] = 0
4999 11:03:48.598195 tx_win_center[1][1][3] = 0
5000 11:03:48.601953 tx_first_pass[1][1][3] = 0
5001 11:03:48.605269 tx_last_pass[1][1][3] = 0
5002 11:03:48.608520 tx_win_center[1][1][4] = 0
5003 11:03:48.608595 tx_first_pass[1][1][4] = 0
5004 11:03:48.611761 tx_last_pass[1][1][4] = 0
5005 11:03:48.614872 tx_win_center[1][1][5] = 0
5006 11:03:48.618172 tx_first_pass[1][1][5] = 0
5007 11:03:48.618247 tx_last_pass[1][1][5] = 0
5008 11:03:48.621459 tx_win_center[1][1][6] = 0
5009 11:03:48.625111 tx_first_pass[1][1][6] = 0
5010 11:03:48.625185 tx_last_pass[1][1][6] = 0
5011 11:03:48.628028 tx_win_center[1][1][7] = 0
5012 11:03:48.631251 tx_first_pass[1][1][7] = 0
5013 11:03:48.634643 tx_last_pass[1][1][7] = 0
5014 11:03:48.634718 tx_win_center[1][1][8] = 0
5015 11:03:48.637641 tx_first_pass[1][1][8] = 0
5016 11:03:48.641370 tx_last_pass[1][1][8] = 0
5017 11:03:48.644183 tx_win_center[1][1][9] = 0
5018 11:03:48.644258 tx_first_pass[1][1][9] = 0
5019 11:03:48.647541 tx_last_pass[1][1][9] = 0
5020 11:03:48.650988 tx_win_center[1][1][10] = 0
5021 11:03:48.654636 tx_first_pass[1][1][10] = 0
5022 11:03:48.654711 tx_last_pass[1][1][10] = 0
5023 11:03:48.657364 tx_win_center[1][1][11] = 0
5024 11:03:48.661054 tx_first_pass[1][1][11] = 0
5025 11:03:48.663773 tx_last_pass[1][1][11] = 0
5026 11:03:48.663848 tx_win_center[1][1][12] = 0
5027 11:03:48.667743 tx_first_pass[1][1][12] = 0
5028 11:03:48.670848 tx_last_pass[1][1][12] = 0
5029 11:03:48.674159 tx_win_center[1][1][13] = 0
5030 11:03:48.674234 tx_first_pass[1][1][13] = 0
5031 11:03:48.677404 tx_last_pass[1][1][13] = 0
5032 11:03:48.680614 tx_win_center[1][1][14] = 0
5033 11:03:48.683642 tx_first_pass[1][1][14] = 0
5034 11:03:48.686932 tx_last_pass[1][1][14] = 0
5035 11:03:48.687008 tx_win_center[1][1][15] = 0
5036 11:03:48.690251 tx_first_pass[1][1][15] = 0
5037 11:03:48.693402 tx_last_pass[1][1][15] = 0
5038 11:03:48.693477 dump params rx window
5039 11:03:48.696899 rx_firspass[0][0][0] = 0
5040 11:03:48.699863 rx_lastpass[0][0][0] = 0
5041 11:03:48.699938 rx_firspass[0][0][1] = 0
5042 11:03:48.703677 rx_lastpass[0][0][1] = 0
5043 11:03:48.706380 rx_firspass[0][0][2] = 0
5044 11:03:48.709637 rx_lastpass[0][0][2] = 0
5045 11:03:48.709711 rx_firspass[0][0][3] = 0
5046 11:03:48.712884 rx_lastpass[0][0][3] = 0
5047 11:03:48.716932 rx_firspass[0][0][4] = 0
5048 11:03:48.717007 rx_lastpass[0][0][4] = 0
5049 11:03:48.719715 rx_firspass[0][0][5] = 0
5050 11:03:48.723225 rx_lastpass[0][0][5] = 0
5051 11:03:48.723300 rx_firspass[0][0][6] = 0
5052 11:03:48.726197 rx_lastpass[0][0][6] = 0
5053 11:03:48.729594 rx_firspass[0][0][7] = 0
5054 11:03:48.732821 rx_lastpass[0][0][7] = 0
5055 11:03:48.732895 rx_firspass[0][0][8] = 0
5056 11:03:48.736299 rx_lastpass[0][0][8] = 0
5057 11:03:48.739943 rx_firspass[0][0][9] = 0
5058 11:03:48.740017 rx_lastpass[0][0][9] = 0
5059 11:03:48.742701 rx_firspass[0][0][10] = 0
5060 11:03:48.746017 rx_lastpass[0][0][10] = 0
5061 11:03:48.746108 rx_firspass[0][0][11] = 0
5062 11:03:48.749161 rx_lastpass[0][0][11] = 0
5063 11:03:48.752966 rx_firspass[0][0][12] = 0
5064 11:03:48.755997 rx_lastpass[0][0][12] = 0
5065 11:03:48.756091 rx_firspass[0][0][13] = 0
5066 11:03:48.759206 rx_lastpass[0][0][13] = 0
5067 11:03:48.762683 rx_firspass[0][0][14] = 0
5068 11:03:48.765831 rx_lastpass[0][0][14] = 0
5069 11:03:48.765906 rx_firspass[0][0][15] = 0
5070 11:03:48.769117 rx_lastpass[0][0][15] = 0
5071 11:03:48.772409 rx_firspass[0][1][0] = 0
5072 11:03:48.772482 rx_lastpass[0][1][0] = 0
5073 11:03:48.775311 rx_firspass[0][1][1] = 0
5074 11:03:48.778711 rx_lastpass[0][1][1] = 0
5075 11:03:48.778785 rx_firspass[0][1][2] = 0
5076 11:03:48.782187 rx_lastpass[0][1][2] = 0
5077 11:03:48.785005 rx_firspass[0][1][3] = 0
5078 11:03:48.788678 rx_lastpass[0][1][3] = 0
5079 11:03:48.788752 rx_firspass[0][1][4] = 0
5080 11:03:48.791904 rx_lastpass[0][1][4] = 0
5081 11:03:48.795088 rx_firspass[0][1][5] = 0
5082 11:03:48.795161 rx_lastpass[0][1][5] = 0
5083 11:03:48.798483 rx_firspass[0][1][6] = 0
5084 11:03:48.801612 rx_lastpass[0][1][6] = 0
5085 11:03:48.801718 rx_firspass[0][1][7] = 0
5086 11:03:48.804721 rx_lastpass[0][1][7] = 0
5087 11:03:48.808575 rx_firspass[0][1][8] = 0
5088 11:03:48.811896 rx_lastpass[0][1][8] = 0
5089 11:03:48.811970 rx_firspass[0][1][9] = 0
5090 11:03:48.814654 rx_lastpass[0][1][9] = 0
5091 11:03:48.818199 rx_firspass[0][1][10] = 0
5092 11:03:48.818291 rx_lastpass[0][1][10] = 0
5093 11:03:48.821293 rx_firspass[0][1][11] = 0
5094 11:03:48.824456 rx_lastpass[0][1][11] = 0
5095 11:03:48.827855 rx_firspass[0][1][12] = 0
5096 11:03:48.827947 rx_lastpass[0][1][12] = 0
5097 11:03:48.830937 rx_firspass[0][1][13] = 0
5098 11:03:48.834251 rx_lastpass[0][1][13] = 0
5099 11:03:48.834325 rx_firspass[0][1][14] = 0
5100 11:03:48.837531 rx_lastpass[0][1][14] = 0
5101 11:03:48.840874 rx_firspass[0][1][15] = 0
5102 11:03:48.844512 rx_lastpass[0][1][15] = 0
5103 11:03:48.844586 rx_firspass[1][0][0] = 0
5104 11:03:48.847343 rx_lastpass[1][0][0] = 0
5105 11:03:48.850618 rx_firspass[1][0][1] = 0
5106 11:03:48.850692 rx_lastpass[1][0][1] = 0
5107 11:03:48.853976 rx_firspass[1][0][2] = 0
5108 11:03:48.857206 rx_lastpass[1][0][2] = 0
5109 11:03:48.860539 rx_firspass[1][0][3] = 0
5110 11:03:48.860613 rx_lastpass[1][0][3] = 0
5111 11:03:48.863990 rx_firspass[1][0][4] = 0
5112 11:03:48.867523 rx_lastpass[1][0][4] = 0
5113 11:03:48.867616 rx_firspass[1][0][5] = 0
5114 11:03:48.870482 rx_lastpass[1][0][5] = 0
5115 11:03:48.874037 rx_firspass[1][0][6] = 0
5116 11:03:48.874157 rx_lastpass[1][0][6] = 0
5117 11:03:48.877198 rx_firspass[1][0][7] = 0
5118 11:03:48.880265 rx_lastpass[1][0][7] = 0
5119 11:03:48.880381 rx_firspass[1][0][8] = 0
5120 11:03:48.883401 rx_lastpass[1][0][8] = 0
5121 11:03:48.886838 rx_firspass[1][0][9] = 0
5122 11:03:48.890437 rx_lastpass[1][0][9] = 0
5123 11:03:48.890511 rx_firspass[1][0][10] = 0
5124 11:03:48.893202 rx_lastpass[1][0][10] = 0
5125 11:03:48.896813 rx_firspass[1][0][11] = 0
5126 11:03:48.896889 rx_lastpass[1][0][11] = 0
5127 11:03:48.899706 rx_firspass[1][0][12] = 0
5128 11:03:48.903544 rx_lastpass[1][0][12] = 0
5129 11:03:48.907075 rx_firspass[1][0][13] = 0
5130 11:03:48.907167 rx_lastpass[1][0][13] = 0
5131 11:03:48.909939 rx_firspass[1][0][14] = 0
5132 11:03:48.912984 rx_lastpass[1][0][14] = 0
5133 11:03:48.913059 rx_firspass[1][0][15] = 0
5134 11:03:48.916886 rx_lastpass[1][0][15] = 0
5135 11:03:48.919448 rx_firspass[1][1][0] = 0
5136 11:03:48.922987 rx_lastpass[1][1][0] = 0
5137 11:03:48.923062 rx_firspass[1][1][1] = 0
5138 11:03:48.926197 rx_lastpass[1][1][1] = 0
5139 11:03:48.929266 rx_firspass[1][1][2] = 0
5140 11:03:48.929341 rx_lastpass[1][1][2] = 0
5141 11:03:48.933301 rx_firspass[1][1][3] = 0
5142 11:03:48.936483 rx_lastpass[1][1][3] = 0
5143 11:03:48.936557 rx_firspass[1][1][4] = 0
5144 11:03:48.939168 rx_lastpass[1][1][4] = 0
5145 11:03:48.943154 rx_firspass[1][1][5] = 0
5146 11:03:48.945830 rx_lastpass[1][1][5] = 0
5147 11:03:48.945905 rx_firspass[1][1][6] = 0
5148 11:03:48.949000 rx_lastpass[1][1][6] = 0
5149 11:03:48.952518 rx_firspass[1][1][7] = 0
5150 11:03:48.952592 rx_lastpass[1][1][7] = 0
5151 11:03:48.955693 rx_firspass[1][1][8] = 0
5152 11:03:48.958935 rx_lastpass[1][1][8] = 0
5153 11:03:48.959021 rx_firspass[1][1][9] = 0
5154 11:03:48.962321 rx_lastpass[1][1][9] = 0
5155 11:03:48.965351 rx_firspass[1][1][10] = 0
5156 11:03:48.969120 rx_lastpass[1][1][10] = 0
5157 11:03:48.969196 rx_firspass[1][1][11] = 0
5158 11:03:48.972462 rx_lastpass[1][1][11] = 0
5159 11:03:48.975962 rx_firspass[1][1][12] = 0
5160 11:03:48.976037 rx_lastpass[1][1][12] = 0
5161 11:03:48.978597 rx_firspass[1][1][13] = 0
5162 11:03:48.982283 rx_lastpass[1][1][13] = 0
5163 11:03:48.985553 rx_firspass[1][1][14] = 0
5164 11:03:48.985628 rx_lastpass[1][1][14] = 0
5165 11:03:48.988655 rx_firspass[1][1][15] = 0
5166 11:03:48.991928 rx_lastpass[1][1][15] = 0
5167 11:03:48.992003 dump params clk_delay
5168 11:03:48.994910 clk_delay[0] = 0
5169 11:03:48.994983 clk_delay[1] = 0
5170 11:03:48.998248 dump params dqs_delay
5171 11:03:49.002076 dqs_delay[0][0] = 0
5172 11:03:49.002150 dqs_delay[0][1] = 0
5173 11:03:49.004730 dqs_delay[1][0] = 0
5174 11:03:49.004804 dqs_delay[1][1] = 0
5175 11:03:49.008243 dump params delay_cell_unit = 744
5176 11:03:49.011320 mt_set_emi_preloader end
5177 11:03:49.014937 [mt_mem_init] dram size: 0x100000000, rank number: 2
5178 11:03:49.021037 [complex_mem_test] start addr:0x40000000, len:20480
5179 11:03:49.056617 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5180 11:03:49.063091 [complex_mem_test] start addr:0x80000000, len:20480
5181 11:03:49.099580 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5182 11:03:49.105528 [complex_mem_test] start addr:0xc0000000, len:20480
5183 11:03:49.141919 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5184 11:03:49.148157 [complex_mem_test] start addr:0x56000000, len:8192
5185 11:03:49.164905 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5186 11:03:49.167814 ddr_geometry:1
5187 11:03:49.171420 [complex_mem_test] start addr:0x80000000, len:8192
5188 11:03:49.188582 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5189 11:03:49.192016 dram_init: dram init end (result: 0)
5190 11:03:49.198103 Successfully loaded DRAM blobs and ran DRAM calibration
5191 11:03:49.208269 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5192 11:03:49.208346 CBMEM:
5193 11:03:49.211793 IMD: root @ 00000000fffff000 254 entries.
5194 11:03:49.214589 IMD: root @ 00000000ffffec00 62 entries.
5195 11:03:49.221011 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5196 11:03:49.227560 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5197 11:03:49.230868 in-header: 03 a1 00 00 08 00 00 00
5198 11:03:49.234123 in-data: 84 60 60 10 00 00 00 00
5199 11:03:49.237886 Chrome EC: clear events_b mask to 0x0000000020004000
5200 11:03:49.244431 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5201 11:03:49.248628 in-header: 03 fd 00 00 00 00 00 00
5202 11:03:49.251512 in-data:
5203 11:03:49.255216 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5204 11:03:49.258542 CBFS @ 21000 size 3d4000
5205 11:03:49.261824 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5206 11:03:49.265079 CBFS: Locating 'fallback/ramstage'
5207 11:03:49.268391 CBFS: Found @ offset 10d40 size d563
5208 11:03:49.290243 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5209 11:03:49.302237 Accumulated console time in romstage 13484 ms
5210 11:03:49.302313
5211 11:03:49.302371
5212 11:03:49.311994 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5213 11:03:49.315834 ARM64: Exception handlers installed.
5214 11:03:49.315909 ARM64: Testing exception
5215 11:03:49.319242 ARM64: Done test exception
5216 11:03:49.322710 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5217 11:03:49.325404 Manufacturer: ef
5218 11:03:49.331706 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5219 11:03:49.335052 WARNING: RO_VPD is uninitialized or empty.
5220 11:03:49.338600 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5221 11:03:49.341937 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5222 11:03:49.352130 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5223 11:03:49.355125 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5224 11:03:49.361887 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5225 11:03:49.361995 Enumerating buses...
5226 11:03:49.368384 Show all devs... Before device enumeration.
5227 11:03:49.368483 Root Device: enabled 1
5228 11:03:49.371901 CPU_CLUSTER: 0: enabled 1
5229 11:03:49.375179 CPU: 00: enabled 1
5230 11:03:49.375285 Compare with tree...
5231 11:03:49.378403 Root Device: enabled 1
5232 11:03:49.378477 CPU_CLUSTER: 0: enabled 1
5233 11:03:49.381715 CPU: 00: enabled 1
5234 11:03:49.384914 Root Device scanning...
5235 11:03:49.388392 root_dev_scan_bus for Root Device
5236 11:03:49.388467 CPU_CLUSTER: 0 enabled
5237 11:03:49.391684 root_dev_scan_bus for Root Device done
5238 11:03:49.398286 scan_bus: scanning of bus Root Device took 10689 usecs
5239 11:03:49.398361 done
5240 11:03:49.400916 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5241 11:03:49.404741 Allocating resources...
5242 11:03:49.408266 Reading resources...
5243 11:03:49.411039 Root Device read_resources bus 0 link: 0
5244 11:03:49.414253 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5245 11:03:49.417425 CPU: 00 missing read_resources
5246 11:03:49.421083 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5247 11:03:49.424679 Root Device read_resources bus 0 link: 0 done
5248 11:03:49.427218 Done reading resources.
5249 11:03:49.431031 Show resources in subtree (Root Device)...After reading.
5250 11:03:49.437497 Root Device child on link 0 CPU_CLUSTER: 0
5251 11:03:49.440564 CPU_CLUSTER: 0 child on link 0 CPU: 00
5252 11:03:49.446757 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5253 11:03:49.449995 CPU: 00
5254 11:03:49.450081 Setting resources...
5255 11:03:49.456654 Root Device assign_resources, bus 0 link: 0
5256 11:03:49.460011 CPU_CLUSTER: 0 missing set_resources
5257 11:03:49.463432 Root Device assign_resources, bus 0 link: 0
5258 11:03:49.463510 Done setting resources.
5259 11:03:49.469629 Show resources in subtree (Root Device)...After assigning values.
5260 11:03:49.473391 Root Device child on link 0 CPU_CLUSTER: 0
5261 11:03:49.476554 CPU_CLUSTER: 0 child on link 0 CPU: 00
5262 11:03:49.486438 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5263 11:03:49.486516 CPU: 00
5264 11:03:49.489920 Done allocating resources.
5265 11:03:49.496402 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5266 11:03:49.496479 Enabling resources...
5267 11:03:49.496539 done.
5268 11:03:49.503003 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5269 11:03:49.503080 Initializing devices...
5270 11:03:49.506120 Root Device init ...
5271 11:03:49.509153 mainboard_init: Starting display init.
5272 11:03:49.512394 ADC[4]: Raw value=75908 ID=0
5273 11:03:49.534672 anx7625_power_on_init: Init interface.
5274 11:03:49.537930 anx7625_disable_pd_protocol: Disabled PD feature.
5275 11:03:49.544492 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5276 11:03:49.591420 anx7625_start_dp_work: Secure OCM version=00
5277 11:03:49.595025 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5278 11:03:49.611850 sp_tx_get_edid_block: EDID Block = 1
5279 11:03:49.729170 Extracted contents:
5280 11:03:49.732318 header: 00 ff ff ff ff ff ff 00
5281 11:03:49.736005 serial number: 06 af 5c 14 00 00 00 00 00 1a
5282 11:03:49.739327 version: 01 04
5283 11:03:49.742461 basic params: 95 1a 0e 78 02
5284 11:03:49.746154 chroma info: 99 85 95 55 56 92 28 22 50 54
5285 11:03:49.749177 established: 00 00 00
5286 11:03:49.756134 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5287 11:03:49.758787 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5288 11:03:49.765395 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5289 11:03:49.772338 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5290 11:03:49.778840 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5291 11:03:49.782163 extensions: 00
5292 11:03:49.782238 checksum: ae
5293 11:03:49.782309
5294 11:03:49.788508 Manufacturer: AUO Model 145c Serial Number 0
5295 11:03:49.788583 Made week 0 of 2016
5296 11:03:49.791590 EDID version: 1.4
5297 11:03:49.791664 Digital display
5298 11:03:49.795223 6 bits per primary color channel
5299 11:03:49.798383 DisplayPort interface
5300 11:03:49.798457 Maximum image size: 26 cm x 14 cm
5301 11:03:49.801384 Gamma: 220%
5302 11:03:49.801458 Check DPMS levels
5303 11:03:49.804970 Supported color formats: RGB 4:4:4
5304 11:03:49.808468 First detailed timing is preferred timing
5305 11:03:49.811447 Established timings supported:
5306 11:03:49.814458 Standard timings supported:
5307 11:03:49.814533 Detailed timings
5308 11:03:49.821032 Hex of detail: ce1d56ea50001a3030204600009010000018
5309 11:03:49.824502 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5310 11:03:49.830921 0556 0586 05a6 0640 hborder 0
5311 11:03:49.834421 0300 0304 030a 031a vborder 0
5312 11:03:49.837709 -hsync -vsync
5313 11:03:49.837799 Did detailed timing
5314 11:03:49.844440 Hex of detail: 0000000f0000000000000000000000000020
5315 11:03:49.844533 Manufacturer-specified data, tag 15
5316 11:03:49.850946 Hex of detail: 000000fe0041554f0a202020202020202020
5317 11:03:49.851020 ASCII string: AUO
5318 11:03:49.857280 Hex of detail: 000000fe004231313658414230312e34200a
5319 11:03:49.860502 ASCII string: B116XAB01.4
5320 11:03:49.860601 Checksum
5321 11:03:49.860686 Checksum: 0xae (valid)
5322 11:03:49.867519 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5323 11:03:49.871028 DSI data_rate: 457800000 bps
5324 11:03:49.877185 anx7625_parse_edid: set default k value to 0x3d for panel
5325 11:03:49.880546 anx7625_parse_edid: pixelclock(76300).
5326 11:03:49.883757 hactive(1366), hsync(32), hfp(48), hbp(154)
5327 11:03:49.886872 vactive(768), vsync(6), vfp(4), vbp(16)
5328 11:03:49.890455 anx7625_dsi_config: config dsi.
5329 11:03:49.897748 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5330 11:03:49.918185 anx7625_dsi_config: success to config DSI
5331 11:03:49.921540 anx7625_dp_start: MIPI phy setup OK.
5332 11:03:49.924933 [SSUSB] Setting up USB HOST controller...
5333 11:03:49.928346 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5334 11:03:49.931314 [SSUSB] phy power-on done.
5335 11:03:49.935526 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5336 11:03:49.939219 in-header: 03 fc 01 00 00 00 00 00
5337 11:03:49.939293 in-data:
5338 11:03:49.945915 handle_proto3_response: EC response with error code: 1
5339 11:03:49.945990 SPM: pcm index = 1
5340 11:03:49.948537 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5341 11:03:49.951999 CBFS @ 21000 size 3d4000
5342 11:03:49.958619 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5343 11:03:49.961797 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5344 11:03:49.965183 CBFS: Found @ offset 1e7c0 size 1026
5345 11:03:49.971727 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5346 11:03:49.974997 SPM: binary array size = 2988
5347 11:03:49.978361 SPM: version = pcm_allinone_v1.17.2_20180829
5348 11:03:49.981268 SPM binary loaded in 32 msecs
5349 11:03:49.989797 spm_kick_im_to_fetch: ptr = 000000004021eec2
5350 11:03:49.992637 spm_kick_im_to_fetch: len = 2988
5351 11:03:49.992711 SPM: spm_kick_pcm_to_run
5352 11:03:49.996183 SPM: spm_kick_pcm_to_run done
5353 11:03:49.999369 SPM: spm_init done in 52 msecs
5354 11:03:50.002420 Root Device init finished in 494983 usecs
5355 11:03:50.006121 CPU_CLUSTER: 0 init ...
5356 11:03:50.015721 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5357 11:03:50.018830 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5358 11:03:50.022364 CBFS @ 21000 size 3d4000
5359 11:03:50.025397 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5360 11:03:50.029058 CBFS: Locating 'sspm.bin'
5361 11:03:50.032404 CBFS: Found @ offset 208c0 size 41cb
5362 11:03:50.043105 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5363 11:03:50.050899 CPU_CLUSTER: 0 init finished in 42800 usecs
5364 11:03:50.050973 Devices initialized
5365 11:03:50.053846 Show all devs... After init.
5366 11:03:50.057526 Root Device: enabled 1
5367 11:03:50.057600 CPU_CLUSTER: 0: enabled 1
5368 11:03:50.060292 CPU: 00: enabled 1
5369 11:03:50.063415 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5370 11:03:50.070509 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5371 11:03:50.073414 ELOG: NV offset 0x558000 size 0x1000
5372 11:03:50.076611 read SPI 0x558000 0x1000: 1260 us, 3250 KB/s, 26.000 Mbps
5373 11:03:50.083111 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5374 11:03:50.089596 ELOG: Event(17) added with size 13 at 2024-07-10 11:03:35 UTC
5375 11:03:50.092846 out: cmd=0x121: 03 db 21 01 00 00 00 00
5376 11:03:50.096890 in-header: 03 2d 00 00 2c 00 00 00
5377 11:03:50.109510 in-data: b6 4a 00 00 00 00 00 00 02 10 00 00 06 80 00 00 e7 e8 00 00 06 80 00 00 7c ee 01 00 06 80 00 00 be bb 01 00 06 80 00 00 1f 46 61 00
5378 11:03:50.113045 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5379 11:03:50.115987 in-header: 03 19 00 00 08 00 00 00
5380 11:03:50.119506 in-data: a2 e0 47 00 13 00 00 00
5381 11:03:50.119590 Chrome EC: UHEPI supported
5382 11:03:50.129205 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5383 11:03:50.132605 in-header: 03 e1 00 00 08 00 00 00
5384 11:03:50.132678 in-data: 84 20 60 10 00 00 00 00
5385 11:03:50.139251 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5386 11:03:50.145406 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5387 11:03:50.149025 in-header: 03 e1 00 00 08 00 00 00
5388 11:03:50.152296 in-data: 84 20 60 10 00 00 00 00
5389 11:03:50.155517 ELOG: Event(A1) added with size 10 at 2024-07-10 11:03:35 UTC
5390 11:03:50.165863 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5391 11:03:50.168466 ELOG: Event(A0) added with size 9 at 2024-07-10 11:03:35 UTC
5392 11:03:50.171995 elog_add_boot_reason: Logged dev mode boot
5393 11:03:50.175058 Finalize devices...
5394 11:03:50.175126 Devices finalized
5395 11:03:50.181658 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5396 11:03:50.184930 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5397 11:03:50.191579 ELOG: Event(91) added with size 10 at 2024-07-10 11:03:35 UTC
5398 11:03:50.194794 Writing coreboot table at 0xffeda000
5399 11:03:50.198548 0. 0000000000114000-000000000011efff: RAMSTAGE
5400 11:03:50.205122 1. 0000000040000000-000000004023cfff: RAMSTAGE
5401 11:03:50.207709 2. 000000004023d000-00000000545fffff: RAM
5402 11:03:50.211054 3. 0000000054600000-000000005465ffff: BL31
5403 11:03:50.214335 4. 0000000054660000-00000000ffed9fff: RAM
5404 11:03:50.220970 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5405 11:03:50.224874 6. 0000000100000000-000000013fffffff: RAM
5406 11:03:50.227860 Passing 5 GPIOs to payload:
5407 11:03:50.231284 NAME | PORT | POLARITY | VALUE
5408 11:03:50.234516 write protect | 0x00000096 | low | high
5409 11:03:50.240765 EC in RW | 0x000000b1 | high | undefined
5410 11:03:50.244068 EC interrupt | 0x00000097 | low | undefined
5411 11:03:50.250696 TPM interrupt | 0x00000099 | high | undefined
5412 11:03:50.253906 speaker enable | 0x000000af | high | undefined
5413 11:03:50.257478 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5414 11:03:50.260225 in-header: 03 f7 00 00 02 00 00 00
5415 11:03:50.263707 in-data: 04 00
5416 11:03:50.263782 Board ID: 4
5417 11:03:50.267300 ADC[3]: Raw value=213471 ID=1
5418 11:03:50.267391 RAM code: 1
5419 11:03:50.267485 SKU ID: 16
5420 11:03:50.273474 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5421 11:03:50.273542 CBFS @ 21000 size 3d4000
5422 11:03:50.280146 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5423 11:03:50.286928 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 9629
5424 11:03:50.289975 coreboot table: 940 bytes.
5425 11:03:50.293098 IMD ROOT 0. 00000000fffff000 00001000
5426 11:03:50.296481 IMD SMALL 1. 00000000ffffe000 00001000
5427 11:03:50.299757 CONSOLE 2. 00000000fffde000 00020000
5428 11:03:50.303429 FMAP 3. 00000000fffdd000 0000047c
5429 11:03:50.306591 TIME STAMP 4. 00000000fffdc000 00000910
5430 11:03:50.309673 RAMOOPS 5. 00000000ffedc000 00100000
5431 11:03:50.313339 COREBOOT 6. 00000000ffeda000 00002000
5432 11:03:50.316206 IMD small region:
5433 11:03:50.319526 IMD ROOT 0. 00000000ffffec00 00000400
5434 11:03:50.323322 VBOOT WORK 1. 00000000ffffeb00 00000100
5435 11:03:50.326464 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5436 11:03:50.332683 VPD 3. 00000000ffffea60 0000006c
5437 11:03:50.336124 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5438 11:03:50.342314 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5439 11:03:50.345769 in-header: 03 e1 00 00 08 00 00 00
5440 11:03:50.349486 in-data: 84 20 60 10 00 00 00 00
5441 11:03:50.352598 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5442 11:03:50.356199 CBFS @ 21000 size 3d4000
5443 11:03:50.362633 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5444 11:03:50.365192 CBFS: Locating 'fallback/payload'
5445 11:03:50.372181 CBFS: Found @ offset dc040 size 439a0
5446 11:03:50.460041 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5447 11:03:50.463224 Checking segment from ROM address 0x0000000040003a00
5448 11:03:50.469869 Checking segment from ROM address 0x0000000040003a1c
5449 11:03:50.473542 Loading segment from ROM address 0x0000000040003a00
5450 11:03:50.476803 code (compression=0)
5451 11:03:50.486599 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5452 11:03:50.492905 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5453 11:03:50.496009 it's not compressed!
5454 11:03:50.499540 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5455 11:03:50.505726 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5456 11:03:50.514151 Loading segment from ROM address 0x0000000040003a1c
5457 11:03:50.517696 Entry Point 0x0000000080000000
5458 11:03:50.517770 Loaded segments
5459 11:03:50.524278 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5460 11:03:50.527683 Jumping to boot code at 0000000080000000(00000000ffeda000)
5461 11:03:50.537185 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5462 11:03:50.544044 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5463 11:03:50.544120 CBFS @ 21000 size 3d4000
5464 11:03:50.550273 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5465 11:03:50.553642 CBFS: Locating 'fallback/bl31'
5466 11:03:50.557005 CBFS: Found @ offset 36dc0 size 5820
5467 11:03:50.568044 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5468 11:03:50.571389 Checking segment from ROM address 0x0000000040003a00
5469 11:03:50.578112 Checking segment from ROM address 0x0000000040003a1c
5470 11:03:50.581377 Loading segment from ROM address 0x0000000040003a00
5471 11:03:50.584493 code (compression=1)
5472 11:03:50.594675 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5473 11:03:50.600903 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5474 11:03:50.600978 using LZMA
5475 11:03:50.610388 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5476 11:03:50.616694 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5477 11:03:50.619864 Loading segment from ROM address 0x0000000040003a1c
5478 11:03:50.623349 Entry Point 0x0000000054601000
5479 11:03:50.623424 Loaded segments
5480 11:03:50.627107 NOTICE: MT8183 bl31_setup
5481 11:03:50.633844 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5482 11:03:50.637145 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5483 11:03:50.640845 INFO: [DEVAPC] dump DEVAPC registers:
5484 11:03:50.650370 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5485 11:03:50.657315 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5486 11:03:50.666957 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5487 11:03:50.673699 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5488 11:03:50.683159 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5489 11:03:50.690053 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5490 11:03:50.699633 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5491 11:03:50.706051 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5492 11:03:50.715874 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5493 11:03:50.722841 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5494 11:03:50.732853 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5495 11:03:50.738901 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5496 11:03:50.749055 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5497 11:03:50.755653 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5498 11:03:50.761729 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5499 11:03:50.768884 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5500 11:03:50.778772 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5501 11:03:50.785762 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5502 11:03:50.791783 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5503 11:03:50.798248 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5504 11:03:50.808552 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5505 11:03:50.814617 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5506 11:03:50.817990 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5507 11:03:50.821329 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5508 11:03:50.824285 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5509 11:03:50.827781 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5510 11:03:50.831164 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5511 11:03:50.837879 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5512 11:03:50.841003 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5513 11:03:50.844453 WARNING: region 0:
5514 11:03:50.847228 WARNING: apc:0x168, sa:0x0, ea:0xfff
5515 11:03:50.847302 WARNING: region 1:
5516 11:03:50.850540 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5517 11:03:50.853907 WARNING: region 2:
5518 11:03:50.857240 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5519 11:03:50.860524 WARNING: region 3:
5520 11:03:50.863939 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5521 11:03:50.864013 WARNING: region 4:
5522 11:03:50.867230 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5523 11:03:50.870668 WARNING: region 5:
5524 11:03:50.873530 WARNING: apc:0x0, sa:0x0, ea:0x0
5525 11:03:50.873604 WARNING: region 6:
5526 11:03:50.876802 WARNING: apc:0x0, sa:0x0, ea:0x0
5527 11:03:50.880077 WARNING: region 7:
5528 11:03:50.883327 WARNING: apc:0x0, sa:0x0, ea:0x0
5529 11:03:50.889888 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5530 11:03:50.893172 INFO: SPM: enable SPMC mode
5531 11:03:50.896411 NOTICE: spm_boot_init() start
5532 11:03:50.896516 NOTICE: spm_boot_init() end
5533 11:03:50.903076 INFO: BL31: Initializing runtime services
5534 11:03:50.906561 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5535 11:03:50.912689 INFO: BL31: Preparing for EL3 exit to normal world
5536 11:03:50.916192 INFO: Entry point address = 0x80000000
5537 11:03:50.919379 INFO: SPSR = 0x8
5538 11:03:50.940548
5539 11:03:50.940660
5540 11:03:50.940783
5541 11:03:50.941354 end: 2.2.3 depthcharge-start (duration 00:00:23) [common]
5542 11:03:50.941453 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5543 11:03:50.941528 Setting prompt string to ['jacuzzi:']
5544 11:03:50.941597 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5545 11:03:50.944054 Starting depthcharge on Juniper...
5546 11:03:50.944129
5547 11:03:50.947270 vboot_handoff: creating legacy vboot_handoff structure
5548 11:03:50.947345
5549 11:03:50.950373 ec_init(0): CrosEC protocol v3 supported (544, 544)
5550 11:03:50.953429
5551 11:03:50.953504 Wipe memory regions:
5552 11:03:50.953562
5553 11:03:50.956827 [0x00000040000000, 0x00000054600000)
5554 11:03:50.999718
5555 11:03:50.999798 [0x00000054660000, 0x00000080000000)
5556 11:03:51.091518
5557 11:03:51.091612 [0x000000811994a0, 0x000000ffeda000)
5558 11:03:51.351384
5559 11:03:51.351526 [0x00000100000000, 0x00000140000000)
5560 11:03:51.484234
5561 11:03:51.487646 Initializing XHCI USB controller at 0x11200000.
5562 11:03:51.510253
5563 11:03:51.513395 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5564 11:03:51.513487
5565 11:03:51.513579
5566 11:03:51.513869 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5567 11:03:51.513965 Sending line: 'tftpboot 192.168.201.1 14786791/tftp-deploy-i61yb_1y/kernel/image.itb 14786791/tftp-deploy-i61yb_1y/kernel/cmdline '
5569 11:03:51.614486 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5570 11:03:51.614575 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5571 11:03:51.619132 jacuzzi: tftpboot 192.168.201.1 14786791/tftp-deploy-i61yb_1y/kernel/image.itbtp-deploy-i61yb_1y/kernel/cmdline
5572 11:03:51.619254
5573 11:03:51.619384 Waiting for link
5574 11:03:52.024378
5575 11:03:52.024490 R8152: Initializing
5576 11:03:52.024551
5577 11:03:52.027692 Version 9 (ocp_data = 6010)
5578 11:03:52.027825
5579 11:03:52.030831 R8152: Done initializing
5580 11:03:52.030906
5581 11:03:52.030964 Adding net device
5582 11:03:52.416969
5583 11:03:52.417088 done.
5584 11:03:52.417149
5585 11:03:52.417203 MAC: 00:e0:4c:72:3d:a6
5586 11:03:52.417254
5587 11:03:52.419776 Sending DHCP discover... done.
5588 11:03:52.419843
5589 11:03:52.423005 Waiting for reply... done.
5590 11:03:52.423078
5591 11:03:52.426219 Sending DHCP request... done.
5592 11:03:52.426298
5593 11:03:52.432153 Waiting for reply... done.
5594 11:03:52.432247
5595 11:03:52.432339 My ip is 192.168.201.20
5596 11:03:52.432419
5597 11:03:52.435316 The DHCP server ip is 192.168.201.1
5598 11:03:52.435382
5599 11:03:52.441808 TFTP server IP predefined by user: 192.168.201.1
5600 11:03:52.441900
5601 11:03:52.448599 Bootfile predefined by user: 14786791/tftp-deploy-i61yb_1y/kernel/image.itb
5602 11:03:52.448693
5603 11:03:52.452043 Sending tftp read request... done.
5604 11:03:52.452171
5605 11:03:52.455887 Waiting for the transfer...
5606 11:03:52.455962
5607 11:03:52.716611 00000000 ################################################################
5608 11:03:52.716722
5609 11:03:52.971539 00080000 ################################################################
5610 11:03:52.971654
5611 11:03:53.227432 00100000 ################################################################
5612 11:03:53.227568
5613 11:03:53.480250 00180000 ################################################################
5614 11:03:53.480357
5615 11:03:53.716507 00200000 ################################################################
5616 11:03:53.716620
5617 11:03:53.951667 00280000 ################################################################
5618 11:03:53.951783
5619 11:03:54.190398 00300000 ################################################################
5620 11:03:54.190509
5621 11:03:54.445852 00380000 ################################################################
5622 11:03:54.445963
5623 11:03:54.704893 00400000 ################################################################
5624 11:03:54.705008
5625 11:03:54.957510 00480000 ################################################################
5626 11:03:54.957624
5627 11:03:55.215121 00500000 ################################################################
5628 11:03:55.215242
5629 11:03:55.476874 00580000 ################################################################
5630 11:03:55.477012
5631 11:03:55.725548 00600000 ################################################################
5632 11:03:55.725662
5633 11:03:55.976872 00680000 ################################################################
5634 11:03:55.976984
5635 11:03:56.228487 00700000 ################################################################
5636 11:03:56.228635
5637 11:03:56.484026 00780000 ################################################################
5638 11:03:56.484133
5639 11:03:56.748464 00800000 ################################################################
5640 11:03:56.748597
5641 11:03:57.013928 00880000 ################################################################
5642 11:03:57.014110
5643 11:03:57.276351 00900000 ################################################################
5644 11:03:57.276470
5645 11:03:57.538654 00980000 ################################################################
5646 11:03:57.538796
5647 11:03:57.802740 00a00000 ################################################################
5648 11:03:57.802859
5649 11:03:58.051545 00a80000 ################################################################
5650 11:03:58.051662
5651 11:03:58.303078 00b00000 ################################################################
5652 11:03:58.303187
5653 11:03:58.561994 00b80000 ################################################################
5654 11:03:58.562114
5655 11:03:58.814713 00c00000 ################################################################
5656 11:03:58.814856
5657 11:03:59.073998 00c80000 ################################################################
5658 11:03:59.074143
5659 11:03:59.325077 00d00000 ################################################################
5660 11:03:59.325209
5661 11:03:59.586869 00d80000 ################################################################
5662 11:03:59.586984
5663 11:03:59.877793 00e00000 ################################################################
5664 11:03:59.877937
5665 11:04:00.172631 00e80000 ################################################################
5666 11:04:00.172759
5667 11:04:00.442202 00f00000 ################################################################
5668 11:04:00.442316
5669 11:04:00.728596 00f80000 ################################################################
5670 11:04:00.728717
5671 11:04:01.010014 01000000 ################################################################
5672 11:04:01.010165
5673 11:04:01.306317 01080000 ################################################################
5674 11:04:01.306436
5675 11:04:01.602355 01100000 ################################################################
5676 11:04:01.602495
5677 11:04:01.880371 01180000 ################################################################
5678 11:04:01.880572
5679 11:04:02.149250 01200000 ################################################################
5680 11:04:02.149363
5681 11:04:02.440435 01280000 ################################################################
5682 11:04:02.440544
5683 11:04:02.699907 01300000 ################################################################
5684 11:04:02.700023
5685 11:04:02.960259 01380000 ################################################################
5686 11:04:02.960370
5687 11:04:03.214707 01400000 ################################################################
5688 11:04:03.214818
5689 11:04:03.469445 01480000 ################################################################
5690 11:04:03.469555
5691 11:04:03.726821 01500000 ################################################################
5692 11:04:03.726934
5693 11:04:03.990146 01580000 ################################################################
5694 11:04:03.990260
5695 11:04:04.282715 01600000 ################################################################
5696 11:04:04.282835
5697 11:04:04.550784 01680000 ################################################################
5698 11:04:04.550904
5699 11:04:04.810742 01700000 ################################################################
5700 11:04:04.810872
5701 11:04:05.066409 01780000 ################################################################
5702 11:04:05.066532
5703 11:04:05.341846 01800000 ################################################################
5704 11:04:05.342014
5705 11:04:05.613444 01880000 ################################################################
5706 11:04:05.613562
5707 11:04:05.871202 01900000 ################################################################
5708 11:04:05.871326
5709 11:04:06.123425 01980000 ################################################################
5710 11:04:06.123535
5711 11:04:06.374283 01a00000 ################################################################
5712 11:04:06.374392
5713 11:04:06.627869 01a80000 ################################################################
5714 11:04:06.627981
5715 11:04:06.878100 01b00000 ################################################################
5716 11:04:06.878212
5717 11:04:07.131136 01b80000 ################################################################
5718 11:04:07.131278
5719 11:04:07.384655 01c00000 ################################################################
5720 11:04:07.384800
5721 11:04:07.633506 01c80000 ################################################################
5722 11:04:07.633647
5723 11:04:07.883581 01d00000 ################################################################
5724 11:04:07.883705
5725 11:04:08.142406 01d80000 ################################################################
5726 11:04:08.142528
5727 11:04:08.350526 01e00000 ##################################################### done.
5728 11:04:08.350647
5729 11:04:08.353826 The bootfile was 31884494 bytes long.
5730 11:04:08.353903
5731 11:04:08.357208 Sending tftp read request... done.
5732 11:04:08.357293
5733 11:04:08.360394 Waiting for the transfer...
5734 11:04:08.360470
5735 11:04:08.360528 00000000 # done.
5736 11:04:08.360584
5737 11:04:08.370747 Command line loaded dynamically from TFTP file: 14786791/tftp-deploy-i61yb_1y/kernel/cmdline
5738 11:04:08.370823
5739 11:04:08.393382 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786791/extract-nfsrootfs-ow0ibkbq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5740 11:04:08.393462
5741 11:04:08.396548 Loading FIT.
5742 11:04:08.396623
5743 11:04:08.399812 Image ramdisk-1 has 18708500 bytes.
5744 11:04:08.399887
5745 11:04:08.399945 Image fdt-1 has 57695 bytes.
5746 11:04:08.399998
5747 11:04:08.403063 Image kernel-1 has 13116259 bytes.
5748 11:04:08.403137
5749 11:04:08.412777 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5750 11:04:08.412883
5751 11:04:08.426242 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5752 11:04:08.426319
5753 11:04:08.429549 Choosing best match conf-1 for compat google,juniper-sku16.
5754 11:04:08.434912
5755 11:04:08.439171 Connected to device vid:did:rid of 1ae0:0028:00
5756 11:04:08.445847
5757 11:04:08.449641 tpm_get_response: command 0x17b, return code 0x0
5758 11:04:08.449717
5759 11:04:08.453035 tpm_cleanup: add release locality here.
5760 11:04:08.453110
5761 11:04:08.456166 Shutting down all USB controllers.
5762 11:04:08.456241
5763 11:04:08.459541 Removing current net device
5764 11:04:08.459615
5765 11:04:08.462916 Exiting depthcharge with code 4 at timestamp: 34606027
5766 11:04:08.462990
5767 11:04:08.468758 LZMA decompressing kernel-1 to 0x80193568
5768 11:04:08.468832
5769 11:04:08.472066 LZMA decompressing kernel-1 to 0x40000000
5770 11:04:10.335861
5771 11:04:10.335984 jumping to kernel
5772 11:04:10.336809 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
5773 11:04:10.336926 start: 2.2.5 auto-login-action (timeout 00:04:08) [common]
5774 11:04:10.337023 Setting prompt string to ['Linux version [0-9]']
5775 11:04:10.337118 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5776 11:04:10.337206 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5777 11:04:10.410450
5778 11:04:10.413836 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5779 11:04:10.417354 start: 2.2.5.1 login-action (timeout 00:04:08) [common]
5780 11:04:10.417445 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5781 11:04:10.417513 Setting prompt string to []
5782 11:04:10.417585 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5783 11:04:10.417652 Using line separator: #'\n'#
5784 11:04:10.417707 No login prompt set.
5785 11:04:10.417761 Parsing kernel messages
5786 11:04:10.417810 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5787 11:04:10.417901 [login-action] Waiting for messages, (timeout 00:04:08)
5788 11:04:10.417957 Waiting using forced prompt support (timeout 00:02:04)
5789 11:04:10.436993 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
5790 11:04:10.440314 [ 0.000000] random: crng init done
5791 11:04:10.443504 [ 0.000000] Machine model: Google juniper sku16 board
5792 11:04:10.446824 [ 0.000000] efi: UEFI not found.
5793 11:04:10.456611 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5794 11:04:10.462961 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5795 11:04:10.472826 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5796 11:04:10.475854 [ 0.000000] printk: bootconsole [mtk8250] enabled
5797 11:04:10.484445 [ 0.000000] NUMA: No NUMA configuration found
5798 11:04:10.491153 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5799 11:04:10.497801 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5800 11:04:10.497877 [ 0.000000] Zone ranges:
5801 11:04:10.504356 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5802 11:04:10.507861 [ 0.000000] DMA32 empty
5803 11:04:10.514323 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5804 11:04:10.517282 [ 0.000000] Movable zone start for each node
5805 11:04:10.520884 [ 0.000000] Early memory node ranges
5806 11:04:10.526971 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5807 11:04:10.534300 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5808 11:04:10.540454 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5809 11:04:10.546908 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5810 11:04:10.553349 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5811 11:04:10.559703 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5812 11:04:10.580955 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5813 11:04:10.587552 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5814 11:04:10.594519 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5815 11:04:10.597912 [ 0.000000] psci: probing for conduit method from DT.
5816 11:04:10.603990 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5817 11:04:10.607600 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5818 11:04:10.613981 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5819 11:04:10.617272 [ 0.000000] psci: SMC Calling Convention v1.1
5820 11:04:10.624065 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5821 11:04:10.627003 [ 0.000000] Detected VIPT I-cache on CPU0
5822 11:04:10.633613 [ 0.000000] CPU features: detected: GIC system register CPU interface
5823 11:04:10.640138 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5824 11:04:10.646900 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5825 11:04:10.653286 [ 0.000000] CPU features: detected: ARM erratum 845719
5826 11:04:10.656517 [ 0.000000] alternatives: applying boot alternatives
5827 11:04:10.663389 [ 0.000000] Fallback order for Node 0: 0
5828 11:04:10.670148 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5829 11:04:10.673181 [ 0.000000] Policy zone: Normal
5830 11:04:10.699471 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786791/extract-nfsrootfs-ow0ibkbq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5831 11:04:10.712411 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5832 11:04:10.719396 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5833 11:04:10.728720 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5834 11:04:10.735695 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5835 11:04:10.738521 <6>[ 0.000000] software IO TLB: area num 8.
5836 11:04:10.764992 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5837 11:04:10.823009 <6>[ 0.000000] Memory: 3896804K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 261660K reserved, 32768K cma-reserved)
5838 11:04:10.829428 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5839 11:04:10.835891 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5840 11:04:10.839645 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5841 11:04:10.846291 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5842 11:04:10.852368 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5843 11:04:10.858838 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5844 11:04:10.865567 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5845 11:04:10.872301 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5846 11:04:10.878719 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5847 11:04:10.888925 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5848 11:04:10.892355 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5849 11:04:10.898712 <6>[ 0.000000] GICv3: 640 SPIs implemented
5850 11:04:10.902122 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5851 11:04:10.905171 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5852 11:04:10.911575 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5853 11:04:10.918609 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5854 11:04:10.931372 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5855 11:04:10.941588 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5856 11:04:10.950948 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5857 11:04:10.960441 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5858 11:04:10.973264 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5859 11:04:10.979572 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5860 11:04:10.986555 <6>[ 0.009464] Console: colour dummy device 80x25
5861 11:04:10.990031 <6>[ 0.014503] printk: console [tty1] enabled
5862 11:04:11.003486 <6>[ 0.018896] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5863 11:04:11.007037 <6>[ 0.029361] pid_max: default: 32768 minimum: 301
5864 11:04:11.010195 <6>[ 0.034242] LSM: Security Framework initializing
5865 11:04:11.019572 <6>[ 0.039157] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5866 11:04:11.026412 <6>[ 0.046778] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5867 11:04:11.033152 <4>[ 0.055665] cacheinfo: Unable to detect cache hierarchy for CPU 0
5868 11:04:11.042836 <6>[ 0.062291] cblist_init_generic: Setting adjustable number of callback queues.
5869 11:04:11.049993 <6>[ 0.069737] cblist_init_generic: Setting shift to 3 and lim to 1.
5870 11:04:11.056306 <6>[ 0.076090] cblist_init_generic: Setting adjustable number of callback queues.
5871 11:04:11.062880 <6>[ 0.083535] cblist_init_generic: Setting shift to 3 and lim to 1.
5872 11:04:11.065880 <6>[ 0.089933] rcu: Hierarchical SRCU implementation.
5873 11:04:11.072560 <6>[ 0.094960] rcu: Max phase no-delay instances is 1000.
5874 11:04:11.080377 <6>[ 0.102864] EFI services will not be available.
5875 11:04:11.083189 <6>[ 0.107813] smp: Bringing up secondary CPUs ...
5876 11:04:11.094300 <6>[ 0.113073] Detected VIPT I-cache on CPU1
5877 11:04:11.100779 <4>[ 0.113119] cacheinfo: Unable to detect cache hierarchy for CPU 1
5878 11:04:11.107094 <6>[ 0.113128] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5879 11:04:11.113921 <6>[ 0.113159] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5880 11:04:11.117252 <6>[ 0.113643] Detected VIPT I-cache on CPU2
5881 11:04:11.123959 <4>[ 0.113676] cacheinfo: Unable to detect cache hierarchy for CPU 2
5882 11:04:11.129867 <6>[ 0.113681] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5883 11:04:11.136667 <6>[ 0.113692] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5884 11:04:11.143013 <6>[ 0.114138] Detected VIPT I-cache on CPU3
5885 11:04:11.149898 <4>[ 0.114168] cacheinfo: Unable to detect cache hierarchy for CPU 3
5886 11:04:11.156536 <6>[ 0.114173] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5887 11:04:11.162878 <6>[ 0.114184] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5888 11:04:11.166644 <6>[ 0.114759] CPU features: detected: Spectre-v2
5889 11:04:11.172670 <6>[ 0.114769] CPU features: detected: Spectre-BHB
5890 11:04:11.176561 <6>[ 0.114773] CPU features: detected: ARM erratum 858921
5891 11:04:11.182952 <6>[ 0.114778] Detected VIPT I-cache on CPU4
5892 11:04:11.186326 <4>[ 0.114826] cacheinfo: Unable to detect cache hierarchy for CPU 4
5893 11:04:11.195828 <6>[ 0.114834] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5894 11:04:11.202622 <6>[ 0.114842] arch_timer: Enabling local workaround for ARM erratum 858921
5895 11:04:11.205822 <6>[ 0.114853] arch_timer: CPU4: Trapping CNTVCT access
5896 11:04:11.212618 <6>[ 0.114860] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5897 11:04:11.219161 <6>[ 0.115346] Detected VIPT I-cache on CPU5
5898 11:04:11.225630 <4>[ 0.115386] cacheinfo: Unable to detect cache hierarchy for CPU 5
5899 11:04:11.232106 <6>[ 0.115391] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5900 11:04:11.238760 <6>[ 0.115398] arch_timer: Enabling local workaround for ARM erratum 858921
5901 11:04:11.241738 <6>[ 0.115404] arch_timer: CPU5: Trapping CNTVCT access
5902 11:04:11.251620 <6>[ 0.115409] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5903 11:04:11.255426 <6>[ 0.115846] Detected VIPT I-cache on CPU6
5904 11:04:11.261812 <4>[ 0.115892] cacheinfo: Unable to detect cache hierarchy for CPU 6
5905 11:04:11.267966 <6>[ 0.115898] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5906 11:04:11.274975 <6>[ 0.115904] arch_timer: Enabling local workaround for ARM erratum 858921
5907 11:04:11.281388 <6>[ 0.115911] arch_timer: CPU6: Trapping CNTVCT access
5908 11:04:11.287952 <6>[ 0.115916] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5909 11:04:11.291238 <6>[ 0.116446] Detected VIPT I-cache on CPU7
5910 11:04:11.297974 <4>[ 0.116490] cacheinfo: Unable to detect cache hierarchy for CPU 7
5911 11:04:11.304674 <6>[ 0.116496] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5912 11:04:11.311071 <6>[ 0.116503] arch_timer: Enabling local workaround for ARM erratum 858921
5913 11:04:11.317771 <6>[ 0.116510] arch_timer: CPU7: Trapping CNTVCT access
5914 11:04:11.324118 <6>[ 0.116515] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5915 11:04:11.327178 <6>[ 0.116563] smp: Brought up 1 node, 8 CPUs
5916 11:04:11.334498 <6>[ 0.355482] SMP: Total of 8 processors activated.
5917 11:04:11.337246 <6>[ 0.360417] CPU features: detected: 32-bit EL0 Support
5918 11:04:11.343702 <6>[ 0.365796] CPU features: detected: 32-bit EL1 Support
5919 11:04:11.350364 <6>[ 0.371164] CPU features: detected: CRC32 instructions
5920 11:04:11.353467 <6>[ 0.376589] CPU: All CPU(s) started at EL2
5921 11:04:11.360048 <6>[ 0.380926] alternatives: applying system-wide alternatives
5922 11:04:11.363509 <6>[ 0.388965] devtmpfs: initialized
5923 11:04:11.382152 <6>[ 0.397901] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5924 11:04:11.388078 <6>[ 0.407849] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5925 11:04:11.394563 <6>[ 0.415573] pinctrl core: initialized pinctrl subsystem
5926 11:04:11.397896 <6>[ 0.422687] DMI not present or invalid.
5927 11:04:11.404357 <6>[ 0.427058] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5928 11:04:11.414370 <6>[ 0.433964] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5929 11:04:11.421530 <6>[ 0.441492] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5930 11:04:11.431022 <6>[ 0.449743] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5931 11:04:11.434590 <6>[ 0.457919] audit: initializing netlink subsys (disabled)
5932 11:04:11.444178 <5>[ 0.463624] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5933 11:04:11.450764 <6>[ 0.464594] thermal_sys: Registered thermal governor 'step_wise'
5934 11:04:11.457788 <6>[ 0.471590] thermal_sys: Registered thermal governor 'power_allocator'
5935 11:04:11.460665 <6>[ 0.477889] cpuidle: using governor menu
5936 11:04:11.467401 <6>[ 0.488851] NET: Registered PF_QIPCRTR protocol family
5937 11:04:11.473816 <6>[ 0.494349] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5938 11:04:11.480301 <6>[ 0.501447] ASID allocator initialised with 32768 entries
5939 11:04:11.483452 <6>[ 0.508218] Serial: AMBA PL011 UART driver
5940 11:04:11.496726 <4>[ 0.519563] Trying to register duplicate clock ID: 113
5941 11:04:11.556779 <6>[ 0.576154] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5942 11:04:11.571062 <6>[ 0.590537] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5943 11:04:11.574245 <6>[ 0.600313] KASLR enabled
5944 11:04:11.588897 <6>[ 0.608251] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5945 11:04:11.595688 <6>[ 0.615255] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5946 11:04:11.602410 <6>[ 0.621731] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5947 11:04:11.608499 <6>[ 0.628722] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5948 11:04:11.615048 <6>[ 0.635196] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5949 11:04:11.621896 <6>[ 0.642185] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5950 11:04:11.628438 <6>[ 0.648659] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5951 11:04:11.634842 <6>[ 0.655650] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5952 11:04:11.637993 <6>[ 0.663179] ACPI: Interpreter disabled.
5953 11:04:11.648499 <6>[ 0.671181] iommu: Default domain type: Translated
5954 11:04:11.654831 <6>[ 0.676342] iommu: DMA domain TLB invalidation policy: strict mode
5955 11:04:11.658717 <5>[ 0.682967] SCSI subsystem initialized
5956 11:04:11.665245 <6>[ 0.687413] usbcore: registered new interface driver usbfs
5957 11:04:11.671473 <6>[ 0.693142] usbcore: registered new interface driver hub
5958 11:04:11.674675 <6>[ 0.698685] usbcore: registered new device driver usb
5959 11:04:11.682629 <6>[ 0.705005] pps_core: LinuxPPS API ver. 1 registered
5960 11:04:11.692228 <6>[ 0.710190] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5961 11:04:11.695292 <6>[ 0.719514] PTP clock support registered
5962 11:04:11.698862 <6>[ 0.723767] EDAC MC: Ver: 3.0.0
5963 11:04:11.706758 <6>[ 0.729423] FPGA manager framework
5964 11:04:11.713123 <6>[ 0.733104] Advanced Linux Sound Architecture Driver Initialized.
5965 11:04:11.716414 <6>[ 0.739846] vgaarb: loaded
5966 11:04:11.722765 <6>[ 0.742979] clocksource: Switched to clocksource arch_sys_counter
5967 11:04:11.726524 <5>[ 0.749413] VFS: Disk quotas dquot_6.6.0
5968 11:04:11.732939 <6>[ 0.753587] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5969 11:04:11.736262 <6>[ 0.760762] pnp: PnP ACPI: disabled
5970 11:04:11.745210 <6>[ 0.767633] NET: Registered PF_INET protocol family
5971 11:04:11.751417 <6>[ 0.772856] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5972 11:04:11.763577 <6>[ 0.782770] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5973 11:04:11.773691 <6>[ 0.791523] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5974 11:04:11.780256 <6>[ 0.799472] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5975 11:04:11.786147 <6>[ 0.807703] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5976 11:04:11.796547 <6>[ 0.815795] TCP: Hash tables configured (established 32768 bind 32768)
5977 11:04:11.803010 <6>[ 0.822622] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5978 11:04:11.809601 <6>[ 0.829596] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5979 11:04:11.816044 <6>[ 0.837076] NET: Registered PF_UNIX/PF_LOCAL protocol family
5980 11:04:11.822545 <6>[ 0.843196] RPC: Registered named UNIX socket transport module.
5981 11:04:11.825913 <6>[ 0.849343] RPC: Registered udp transport module.
5982 11:04:11.832339 <6>[ 0.854270] RPC: Registered tcp transport module.
5983 11:04:11.839217 <6>[ 0.859193] RPC: Registered tcp NFSv4.1 backchannel transport module.
5984 11:04:11.842228 <6>[ 0.865845] PCI: CLS 0 bytes, default 64
5985 11:04:11.845702 <6>[ 0.870104] Unpacking initramfs...
5986 11:04:11.864462 <6>[ 0.883594] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5987 11:04:11.874047 <6>[ 0.892278] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5988 11:04:11.877330 <6>[ 0.901192] kvm [1]: IPA Size Limit: 40 bits
5989 11:04:11.885146 <6>[ 0.907536] kvm [1]: vgic-v2@c420000
5990 11:04:11.888419 <6>[ 0.911366] kvm [1]: GIC system register CPU interface enabled
5991 11:04:11.895174 <6>[ 0.917549] kvm [1]: vgic interrupt IRQ18
5992 11:04:11.898138 <6>[ 0.921920] kvm [1]: Hyp mode initialized successfully
5993 11:04:11.905942 <5>[ 0.928291] Initialise system trusted keyrings
5994 11:04:11.912429 <6>[ 0.933131] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5995 11:04:11.920276 <6>[ 0.943074] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5996 11:04:11.926950 <5>[ 0.949488] NFS: Registering the id_resolver key type
5997 11:04:11.930250 <5>[ 0.954794] Key type id_resolver registered
5998 11:04:11.937059 <5>[ 0.959204] Key type id_legacy registered
5999 11:04:11.943605 <6>[ 0.963503] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6000 11:04:11.949998 <6>[ 0.970426] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6001 11:04:11.956479 <6>[ 0.978172] 9p: Installing v9fs 9p2000 file system support
6002 11:04:11.983985 <5>[ 1.006796] Key type asymmetric registered
6003 11:04:11.987505 <5>[ 1.011147] Asymmetric key parser 'x509' registered
6004 11:04:11.997138 <6>[ 1.016300] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6005 11:04:12.000554 <6>[ 1.023917] io scheduler mq-deadline registered
6006 11:04:12.003869 <6>[ 1.028673] io scheduler kyber registered
6007 11:04:12.026588 <6>[ 1.049449] EINJ: ACPI disabled.
6008 11:04:12.033275 <4>[ 1.053198] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6009 11:04:12.072011 <6>[ 1.094199] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6010 11:04:12.080281 <6>[ 1.102720] printk: console [ttyS0] disabled
6011 11:04:12.108213 <6>[ 1.127370] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6012 11:04:12.114752 <6>[ 1.136842] printk: console [ttyS0] enabled
6013 11:04:12.118027 <6>[ 1.136842] printk: console [ttyS0] enabled
6014 11:04:12.124459 <6>[ 1.145764] printk: bootconsole [mtk8250] disabled
6015 11:04:12.127712 <6>[ 1.145764] printk: bootconsole [mtk8250] disabled
6016 11:04:12.137671 <3>[ 1.156288] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6017 11:04:12.144185 <3>[ 1.164671] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6018 11:04:12.173898 <6>[ 1.193075] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6019 11:04:12.180167 <6>[ 1.202727] serial serial0: tty port ttyS1 registered
6020 11:04:12.186802 <6>[ 1.209313] SuperH (H)SCI(F) driver initialized
6021 11:04:12.190463 <6>[ 1.214845] msm_serial: driver initialized
6022 11:04:12.206147 <6>[ 1.225158] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6023 11:04:12.216050 <6>[ 1.233763] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6024 11:04:12.222454 <6>[ 1.242340] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6025 11:04:12.232059 <6>[ 1.250912] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6026 11:04:12.242307 <6>[ 1.259567] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6027 11:04:12.248354 <6>[ 1.268230] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6028 11:04:12.258473 <6>[ 1.276967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6029 11:04:12.265098 <6>[ 1.285708] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6030 11:04:12.274947 <6>[ 1.294269] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6031 11:04:12.284566 <6>[ 1.303077] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6032 11:04:12.293222 <4>[ 1.315500] cacheinfo: Unable to detect cache hierarchy for CPU 0
6033 11:04:12.301919 <6>[ 1.324845] loop: module loaded
6034 11:04:12.313811 <6>[ 1.336811] vsim1: Bringing 1800000uV into 2700000-2700000uV
6035 11:04:12.332162 <6>[ 1.354791] megasas: 07.719.03.00-rc1
6036 11:04:12.341031 <6>[ 1.363655] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6037 11:04:12.355910 <6>[ 1.378365] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6038 11:04:12.372828 <6>[ 1.395121] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6039 11:04:12.429368 <6>[ 1.445463] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1d
6040 11:04:12.477280 <6>[ 1.500107] Freeing initrd memory: 18264K
6041 11:04:12.492349 <4>[ 1.511933] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6042 11:04:12.498942 <4>[ 1.521164] CPU: 5 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6043 11:04:12.505905 <4>[ 1.527861] Hardware name: Google juniper sku16 board (DT)
6044 11:04:12.509139 <4>[ 1.533599] Call trace:
6045 11:04:12.512158 <4>[ 1.536299] dump_backtrace.part.0+0xe0/0xf0
6046 11:04:12.516274 <4>[ 1.540838] show_stack+0x18/0x30
6047 11:04:12.522174 <4>[ 1.544411] dump_stack_lvl+0x64/0x80
6048 11:04:12.525569 <4>[ 1.548331] dump_stack+0x18/0x34
6049 11:04:12.529250 <4>[ 1.551899] sysfs_warn_dup+0x64/0x80
6050 11:04:12.532292 <4>[ 1.555821] sysfs_do_create_link_sd+0xf0/0x100
6051 11:04:12.538599 <4>[ 1.560608] sysfs_create_link+0x20/0x40
6052 11:04:12.541912 <4>[ 1.564788] bus_add_device+0x64/0x120
6053 11:04:12.545616 <4>[ 1.568792] device_add+0x354/0x7ec
6054 11:04:12.548590 <4>[ 1.572539] of_device_add+0x44/0x60
6055 11:04:12.555136 <4>[ 1.576373] of_platform_device_create_pdata+0x90/0x124
6056 11:04:12.559018 <4>[ 1.581855] of_platform_bus_create+0x154/0x380
6057 11:04:12.561894 <4>[ 1.586640] of_platform_populate+0x50/0xfc
6058 11:04:12.568657 <4>[ 1.591078] parse_mtd_partitions+0x1d8/0x4e0
6059 11:04:12.571878 <4>[ 1.595696] mtd_device_parse_register+0xec/0x2e0
6060 11:04:12.578329 <4>[ 1.600656] spi_nor_probe+0x280/0x2f4
6061 11:04:12.582184 <4>[ 1.604662] spi_mem_probe+0x6c/0xc0
6062 11:04:12.585039 <4>[ 1.608494] spi_probe+0x84/0xe4
6063 11:04:12.588709 <4>[ 1.611979] really_probe+0xbc/0x2dc
6064 11:04:12.591606 <4>[ 1.615810] __driver_probe_device+0x78/0x114
6065 11:04:12.598913 <4>[ 1.620422] driver_probe_device+0xd8/0x15c
6066 11:04:12.601549 <4>[ 1.624860] __device_attach_driver+0xb8/0x134
6067 11:04:12.605145 <4>[ 1.629559] bus_for_each_drv+0x7c/0xd4
6068 11:04:12.611732 <4>[ 1.633652] __device_attach+0x9c/0x1a0
6069 11:04:12.615170 <4>[ 1.637742] device_initial_probe+0x14/0x20
6070 11:04:12.618297 <4>[ 1.642179] bus_probe_device+0x98/0xa0
6071 11:04:12.621624 <4>[ 1.646270] device_add+0x3c0/0x7ec
6072 11:04:12.624932 <4>[ 1.650014] __spi_add_device+0x78/0x120
6073 11:04:12.631600 <4>[ 1.654192] spi_add_device+0x44/0x80
6074 11:04:12.634613 <4>[ 1.658108] spi_register_controller+0x704/0xb20
6075 11:04:12.641451 <4>[ 1.662980] devm_spi_register_controller+0x4c/0xac
6076 11:04:12.644737 <4>[ 1.668114] mtk_spi_probe+0x4f4/0x684
6077 11:04:12.648427 <4>[ 1.672117] platform_probe+0x68/0xc0
6078 11:04:12.651662 <4>[ 1.676036] really_probe+0xbc/0x2dc
6079 11:04:12.658240 <4>[ 1.679865] __driver_probe_device+0x78/0x114
6080 11:04:12.661446 <4>[ 1.684477] driver_probe_device+0xd8/0x15c
6081 11:04:12.664570 <4>[ 1.688914] __driver_attach+0x94/0x19c
6082 11:04:12.667939 <4>[ 1.693004] bus_for_each_dev+0x74/0xd0
6083 11:04:12.674923 <4>[ 1.697097] driver_attach+0x24/0x30
6084 11:04:12.678572 <4>[ 1.700926] bus_add_driver+0x154/0x20c
6085 11:04:12.681561 <4>[ 1.705015] driver_register+0x78/0x130
6086 11:04:12.687639 <4>[ 1.709106] __platform_driver_register+0x28/0x34
6087 11:04:12.690975 <4>[ 1.714066] mtk_spi_driver_init+0x1c/0x28
6088 11:04:12.694628 <4>[ 1.718421] do_one_initcall+0x64/0x1dc
6089 11:04:12.700981 <4>[ 1.722512] kernel_init_freeable+0x218/0x284
6090 11:04:12.704284 <4>[ 1.727128] kernel_init+0x24/0x12c
6091 11:04:12.707466 <4>[ 1.730873] ret_from_fork+0x10/0x20
6092 11:04:12.717144 <6>[ 1.739765] tun: Universal TUN/TAP device driver, 1.6
6093 11:04:12.720525 <6>[ 1.746055] thunder_xcv, ver 1.0
6094 11:04:12.726712 <6>[ 1.749568] thunder_bgx, ver 1.0
6095 11:04:12.726781 <6>[ 1.753070] nicpf, ver 1.0
6096 11:04:12.738307 <6>[ 1.757446] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6097 11:04:12.741348 <6>[ 1.764930] hns3: Copyright (c) 2017 Huawei Corporation.
6098 11:04:12.747675 <6>[ 1.770526] hclge is initializing
6099 11:04:12.751453 <6>[ 1.774115] e1000: Intel(R) PRO/1000 Network Driver
6100 11:04:12.757798 <6>[ 1.779250] e1000: Copyright (c) 1999-2006 Intel Corporation.
6101 11:04:12.764954 <6>[ 1.785270] e1000e: Intel(R) PRO/1000 Network Driver
6102 11:04:12.767710 <6>[ 1.790491] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6103 11:04:12.774348 <6>[ 1.796687] igb: Intel(R) Gigabit Ethernet Network Driver
6104 11:04:12.780802 <6>[ 1.802342] igb: Copyright (c) 2007-2014 Intel Corporation.
6105 11:04:12.787780 <6>[ 1.808186] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6106 11:04:12.794218 <6>[ 1.814709] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6107 11:04:12.797971 <6>[ 1.821262] sky2: driver version 1.30
6108 11:04:12.804129 <6>[ 1.826517] usbcore: registered new device driver r8152-cfgselector
6109 11:04:12.810695 <6>[ 1.833058] usbcore: registered new interface driver r8152
6110 11:04:12.817273 <6>[ 1.838892] VFIO - User Level meta-driver version: 0.3
6111 11:04:12.824562 <6>[ 1.846689] mtu3 11201000.usb: uwk - reg:0x420, version:101
6112 11:04:12.830513 <4>[ 1.852564] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6113 11:04:12.837422 <6>[ 1.859837] mtu3 11201000.usb: dr_mode: 1, drd: auto
6114 11:04:12.843721 <6>[ 1.865063] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6115 11:04:12.847079 <6>[ 1.871242] mtu3 11201000.usb: usb3-drd: 0
6116 11:04:12.857531 <6>[ 1.876803] mtu3 11201000.usb: xHCI platform device register success...
6117 11:04:12.863866 <4>[ 1.885415] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6118 11:04:12.870728 <6>[ 1.893340] xhci-mtk 11200000.usb: xHCI Host Controller
6119 11:04:12.877309 <6>[ 1.898844] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6120 11:04:12.884070 <6>[ 1.906581] xhci-mtk 11200000.usb: USB3 root hub has no ports
6121 11:04:12.893740 <6>[ 1.912590] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6122 11:04:12.900856 <6>[ 1.922018] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6123 11:04:12.907416 <6>[ 1.928091] xhci-mtk 11200000.usb: xHCI Host Controller
6124 11:04:12.913690 <6>[ 1.933579] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6125 11:04:12.920466 <6>[ 1.941240] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6126 11:04:12.924182 <6>[ 1.948061] hub 1-0:1.0: USB hub found
6127 11:04:12.926849 <6>[ 1.952090] hub 1-0:1.0: 1 port detected
6128 11:04:12.938624 <6>[ 1.957455] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6129 11:04:12.941372 <6>[ 1.966075] hub 2-0:1.0: USB hub found
6130 11:04:12.950938 <3>[ 1.970102] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6131 11:04:12.957893 <6>[ 1.977981] usbcore: registered new interface driver usb-storage
6132 11:04:12.964087 <6>[ 1.984585] usbcore: registered new device driver onboard-usb-hub
6133 11:04:12.980014 <4>[ 1.999095] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6134 11:04:12.988956 <6>[ 2.011397] mt6397-rtc mt6358-rtc: registered as rtc0
6135 11:04:12.998788 <6>[ 2.016903] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-10T11:03:58 UTC (1720609438)
6136 11:04:13.005502 <6>[ 2.026747] i2c_dev: i2c /dev entries driver
6137 11:04:13.014882 <6>[ 2.033158] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6138 11:04:13.021689 <6>[ 2.041479] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6139 11:04:13.028414 <6>[ 2.050382] i2c 4-0058: Fixed dependency cycle(s) with /panel
6140 11:04:13.034404 <6>[ 2.056417] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6141 11:04:13.053600 <6>[ 2.075834] cpu cpu0: EM: created perf domain
6142 11:04:13.066613 <6>[ 2.081350] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6143 11:04:13.069643 <6>[ 2.092703] cpu cpu4: EM: created perf domain
6144 11:04:13.077078 <6>[ 2.099772] sdhci: Secure Digital Host Controller Interface driver
6145 11:04:13.084149 <6>[ 2.106228] sdhci: Copyright(c) Pierre Ossman
6146 11:04:13.090814 <6>[ 2.111641] Synopsys Designware Multimedia Card Interface Driver
6147 11:04:13.097279 <6>[ 2.112190] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6148 11:04:13.100205 <6>[ 2.118695] sdhci-pltfm: SDHCI platform and OF driver helper
6149 11:04:13.109174 <6>[ 2.131349] ledtrig-cpu: registered to indicate activity on CPUs
6150 11:04:13.116234 <6>[ 2.139044] usbcore: registered new interface driver usbhid
6151 11:04:13.119749 <6>[ 2.144880] usbhid: USB HID core driver
6152 11:04:13.130540 <6>[ 2.149199] spi_master spi2: will run message pump with realtime priority
6153 11:04:13.134354 <4>[ 2.149345] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6154 11:04:13.144856 <4>[ 2.163580] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6155 11:04:13.158103 <6>[ 2.168531] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6156 11:04:13.174798 <6>[ 2.186536] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6157 11:04:13.180949 <4>[ 2.195467] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6158 11:04:13.184758 <6>[ 2.201489] cros-ec-spi spi2.0: Chrome EC device registered
6159 11:04:13.196374 <4>[ 2.215627] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6160 11:04:13.203166 <6>[ 2.225645] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
6161 11:04:13.213308 <4>[ 2.226566] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6162 11:04:13.216364 <6>[ 2.233483] mmc0: new HS400 MMC card at address 0001
6163 11:04:13.223009 <4>[ 2.240512] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6164 11:04:13.229558 <6>[ 2.245815] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6165 11:04:13.238217 <6>[ 2.260909] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6166 11:04:13.247980 <6>[ 2.270907] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6167 11:04:13.254844 <6>[ 2.277209] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6168 11:04:13.262027 <6>[ 2.277570] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6169 11:04:13.271907 <6>[ 2.283695] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6170 11:04:13.281152 <6>[ 2.287246] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6171 11:04:13.287927 <6>[ 2.290401] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6172 11:04:13.294512 <6>[ 2.299208] NET: Registered PF_PACKET protocol family
6173 11:04:13.304548 <6>[ 2.311309] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6174 11:04:13.310967 <6>[ 2.315459] 9pnet: Installing 9P2000 support
6175 11:04:13.320875 <6>[ 2.321199] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6176 11:04:13.324211 <5>[ 2.332820] Key type dns_resolver registered
6177 11:04:13.327520 <6>[ 2.352437] registered taskstats version 1
6178 11:04:13.334009 <5>[ 2.356823] Loading compiled-in X.509 certificates
6179 11:04:13.363633 <6>[ 2.383148] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6180 11:04:13.382783 <3>[ 2.402215] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6181 11:04:13.413348 <6>[ 2.429267] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6182 11:04:13.424285 <6>[ 2.443330] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6183 11:04:13.433709 <6>[ 2.451957] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6184 11:04:13.440553 <6>[ 2.460590] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6185 11:04:13.450309 <6>[ 2.469197] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6186 11:04:13.459956 <6>[ 2.477750] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6187 11:04:13.466798 <6>[ 2.486344] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6188 11:04:13.476445 <6>[ 2.494933] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6189 11:04:13.483507 <6>[ 2.504244] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6190 11:04:13.489828 <6>[ 2.511772] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6191 11:04:13.496562 <6>[ 2.519097] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6192 11:04:13.507128 <6>[ 2.526363] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6193 11:04:13.513604 <6>[ 2.533780] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6194 11:04:13.517081 <6>[ 2.537560] hub 1-1:1.0: USB hub found
6195 11:04:13.523422 <6>[ 2.542106] panfrost 13040000.gpu: clock rate = 511999970
6196 11:04:13.526900 <6>[ 2.544861] hub 1-1:1.0: 3 ports detected
6197 11:04:13.536379 <6>[ 2.550161] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6198 11:04:13.543171 <6>[ 2.564313] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6199 11:04:13.553294 <6>[ 2.572324] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6200 11:04:13.566044 <6>[ 2.580760] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6201 11:04:13.572880 <6>[ 2.592839] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6202 11:04:13.583440 <6>[ 2.602395] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6203 11:04:13.592779 <6>[ 2.611175] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6204 11:04:13.602557 <6>[ 2.620321] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6205 11:04:13.609897 <6>[ 2.629453] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6206 11:04:13.619630 <6>[ 2.638582] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6207 11:04:13.629460 <6>[ 2.647883] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6208 11:04:13.639305 <6>[ 2.657185] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6209 11:04:13.649868 <6>[ 2.666659] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6210 11:04:13.659343 <6>[ 2.676135] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6211 11:04:13.665940 <6>[ 2.685262] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6212 11:04:13.739524 <6>[ 2.758790] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6213 11:04:13.749352 <6>[ 2.767736] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6214 11:04:13.760310 <6>[ 2.780041] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6215 11:04:13.827603 <6>[ 2.847015] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6216 11:04:14.466664 <6>[ 3.039252] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6217 11:04:14.476360 <4>[ 3.156168] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6218 11:04:14.482876 <4>[ 3.156185] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6219 11:04:14.489696 <6>[ 3.201180] r8152 1-1.2:1.0 eth0: v1.12.13
6220 11:04:14.495948 <6>[ 3.283010] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6221 11:04:14.502350 <6>[ 3.469244] Console: switching to colour frame buffer device 170x48
6222 11:04:14.509367 <6>[ 3.529889] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6223 11:04:14.530323 <6>[ 3.546537] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6224 11:04:14.547169 <6>[ 3.563467] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6225 11:04:14.556968 <6>[ 3.575960] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6226 11:04:14.563778 <6>[ 3.584277] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6227 11:04:14.573509 <6>[ 3.591271] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6228 11:04:14.594250 <6>[ 3.610251] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6229 11:04:15.827314 <6>[ 4.849858] r8152 1-1.2:1.0 eth0: carrier on
6230 11:04:18.536281 <5>[ 4.879117] Sending DHCP requests .., OK
6231 11:04:18.543094 <6>[ 7.563325] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.20
6232 11:04:18.546293 <6>[ 7.571783] IP-Config: Complete:
6233 11:04:18.559524 <6>[ 7.575350] device=eth0, hwaddr=00:e0:4c:72:3d:a6, ipaddr=192.168.201.20, mask=255.255.255.0, gw=192.168.201.1
6234 11:04:18.570362 <6>[ 7.586252] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4, domain=lava-rack, nis-domain=(none)
6235 11:04:18.581468 <6>[ 7.600615] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6236 11:04:18.590276 <6>[ 7.600625] nameserver0=192.168.201.1
6237 11:04:18.597817 <6>[ 7.620531] clk: Disabling unused clocks
6238 11:04:18.602522 <6>[ 7.628537] ALSA device list:
6239 11:04:18.611716 <6>[ 7.634627] No soundcards found.
6240 11:04:18.620851 <6>[ 7.643561] Freeing unused kernel memory: 8512K
6241 11:04:18.628316 <6>[ 7.650675] Run /init as init process
6242 11:04:18.640415 Loading, please wait...
6243 11:04:18.671895 Starting systemd-udevd version 252.22-1~deb12u1
6244 11:04:19.013058 <6>[ 8.032401] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6245 11:04:19.023918 <3>[ 8.046310] thermal_sys: Failed to find 'trips' node
6246 11:04:19.034259 <3>[ 8.053499] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6247 11:04:19.037725 <3>[ 8.054409] mtk-scp 10500000.scp: invalid resource
6248 11:04:19.047455 <3>[ 8.060839] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6249 11:04:19.054149 <4>[ 8.060850] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6250 11:04:19.060181 <3>[ 8.063564] thermal_sys: Failed to find 'trips' node
6251 11:04:19.067160 <6>[ 8.066250] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6252 11:04:19.073703 <3>[ 8.074345] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6253 11:04:19.083641 <3>[ 8.082892] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6254 11:04:19.093526 <3>[ 8.084303] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6255 11:04:19.103719 <3>[ 8.084324] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6256 11:04:19.109751 <3>[ 8.084333] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6257 11:04:19.121530 <4>[ 8.085349] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6258 11:04:19.127656 <3>[ 8.087135] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6259 11:04:19.137563 <4>[ 8.087142] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6260 11:04:19.145031 <6>[ 8.088369] remoteproc remoteproc0: scp is available
6261 11:04:19.153811 <4>[ 8.088372] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6262 11:04:19.163495 <4>[ 8.092169] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6263 11:04:19.173861 <3>[ 8.092950] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6264 11:04:19.183266 <3>[ 8.092970] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6265 11:04:19.193162 <3>[ 8.092979] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6266 11:04:19.203731 <3>[ 8.092990] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6267 11:04:19.213628 <3>[ 8.092998] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6268 11:04:19.223898 <6>[ 8.093720] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6269 11:04:19.230589 <3>[ 8.094855] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6270 11:04:19.240328 <3>[ 8.097503] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6271 11:04:19.253519 <6>[ 8.099714] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6272 11:04:19.259947 <4>[ 8.102378] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6273 11:04:19.274150 <3>[ 8.112117] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6274 11:04:19.279970 <3>[ 8.112126] elan_i2c 2-0015: Error applying setting, reverse things back
6275 11:04:19.286691 <6>[ 8.116157] mc: Linux media interface: v0.10
6276 11:04:19.290537 <6>[ 8.120999] remoteproc remoteproc0: powering up scp
6277 11:04:19.303809 <3>[ 8.143279] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6278 11:04:19.313581 <4>[ 8.148126] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6279 11:04:19.316910 <6>[ 8.180673] videodev: Linux video capture interface: v2.00
6280 11:04:19.323184 <3>[ 8.182091] remoteproc remoteproc0: request_firmware failed: -2
6281 11:04:19.329941 <6>[ 8.225384] cs_system_cfg: CoreSight Configuration manager initialised
6282 11:04:19.339189 <6>[ 8.230565] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6283 11:04:19.349174 <5>[ 8.232611] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6284 11:04:19.358930 <6>[ 8.235586] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6285 11:04:19.369364 <6>[ 8.252657] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6286 11:04:19.375655 <6>[ 8.253341] Bluetooth: Core ver 2.22
6287 11:04:19.382703 <6>[ 8.253403] NET: Registered PF_BLUETOOTH protocol family
6288 11:04:19.389015 <6>[ 8.253407] Bluetooth: HCI device and connection manager initialized
6289 11:04:19.396449 <6>[ 8.253422] Bluetooth: HCI socket layer initialized
6290 11:04:19.403890 <6>[ 8.253429] Bluetooth: L2CAP socket layer initialized
6291 11:04:19.410454 <6>[ 8.253442] Bluetooth: SCO socket layer initialized
6292 11:04:19.420819 <5>[ 8.276922] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6293 11:04:19.427162 <6>[ 8.280555] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6294 11:04:19.439158 <5>[ 8.289293] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6295 11:04:19.448711 <6>[ 8.306646] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6296 11:04:19.455225 <6>[ 8.308038] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6297 11:04:19.467038 <4>[ 8.308662] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6298 11:04:19.477173 <6>[ 8.313276] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6299 11:04:19.480956 <6>[ 8.313752] Bluetooth: HCI UART driver ver 2.3
6300 11:04:19.487525 <6>[ 8.313760] Bluetooth: HCI UART protocol H4 registered
6301 11:04:19.494293 <6>[ 8.313800] Bluetooth: HCI UART protocol LL registered
6302 11:04:19.500665 <6>[ 8.313815] Bluetooth: HCI UART protocol Three-wire (H5) registered
6303 11:04:19.503992 <6>[ 8.314093] Bluetooth: HCI UART protocol Broadcom registered
6304 11:04:19.511244 <6>[ 8.314119] Bluetooth: HCI UART protocol QCA registered
6305 11:04:19.517526 Begin: Loading e<6>[ 8.314136] Bluetooth: HCI UART protocol Marvell registered
6306 11:04:19.521040 ssential drivers ... done.
6307 11:04:19.527509 Begin: Running /scri<6>[ 8.314615] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6308 11:04:19.531134 pts/init-premount ... done.
6309 11:04:19.540702 Beg<6>[ 8.315383] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6310 11:04:19.547594 in: Mounting root file system ..<6>[ 8.316917] Bluetooth: hci0: setting up ROME/QCA6390
6311 11:04:19.554160 . Begin: Running /scripts/nfs-to<6>[ 8.318489] cfg80211: failed to load regulatory.db
6312 11:04:19.557889 p ... done.
6313 11:04:19.564057 Begin: Running /scr<6>[ 8.318917] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6314 11:04:19.574162 ipts/nfs-premount ... Waiting up<6>[ 8.320403] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6315 11:04:19.590081 to 60 secs for any ethernet to <6>[ 8.330716] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6316 11:04:19.590167 become available
6317 11:04:19.599936 Device /sys/cl<6>[ 8.330845] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6318 11:04:19.603457 ass/net/eth0 found
6319 11:04:19.603530 done.
6320 11:04:19.609866 Begin<6>[ 8.330904] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6321 11:04:19.623464 : Waiting up to 180 secs for any<6>[ 8.339038] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6322 11:04:19.633055 network device to become availa<6>[ 8.339100] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6323 11:04:19.639726 <6>[ 8.345089] usbcore: registered new interface driver uvcvideo
6324 11:04:19.639833 ble ... done.
6325 11:04:19.655350 <3>[ 8.351510] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6326 11:04:19.665210 <6>[ 8.496503] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6327 11:04:19.678056 <3>[ 8.505975] debugfs: File 'Playback' in directory 'dapm' already present!
6328 11:04:19.689530 <6>[ 8.509053] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6329 11:04:19.702371 <3>[ 8.514387] debugfs: File 'Capture' in directory 'dapm' already present!
6330 11:04:19.717519 <6>[ 8.519864] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6331 11:04:19.733691 <6>[ 8.529037] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6332 11:04:19.736864 <3>[ 8.532910] Bluetooth: hci0: Frame reassembly failed (-84)
6333 11:04:19.753684 IP-Config: eth0 hardware address 00:e0:4c:72:3d:a6 mtu 1500 DHCP<4>[ 8.653555] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6334 11:04:19.756427 <4>[ 8.653555] Fallback method does not support PEC.
6335 11:04:19.756506
6336 11:04:19.770079 IP-Config: eth0 complete (dhcp from 192.168.201.<6>[ 8.681060] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6337 11:04:19.770188 1):
6338 11:04:19.783180 address: 192.168.201.20 broadcast: 192.1<3>[ 8.749752] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6339 11:04:19.786308 68.201.255 netmask: 255.255.255.0
6340 11:04:19.794187 gateway: 192.168.201.1 <6>[ 8.812544] Bluetooth: hci0: QCA Product ID :0x00000008
6341 11:04:19.797131 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6342 11:04:19.807126 host <3>[ 8.821517] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6343 11:04:19.813551 : mt8183-kukui-<6>[ 8.825500] Bluetooth: hci0: QCA SOC Version :0x00000044
6344 11:04:19.820522 jacuzzi-juniper-sku16-cbg-4
6345 11:04:19.826837 domain : l<6>[ 8.825508] Bluetooth: hci0: QCA ROM Version :0x00000302
6346 11:04:19.836778 ava-rack <6>[ 8.825513] Bluetooth: hci0: QCA Patch Version:0x00000111
6347 11:04:19.836857
6348 11:04:19.846465 rootserver: 192.168.201.1 root<6>[ 8.825523] Bluetooth: hci0: QCA controller version 0x00440302
6349 11:04:19.846552 path:
6350 11:04:19.846613 filename :
6351 11:04:19.856801 <6>[ 8.825531] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6352 11:04:19.866741 <4>[ 8.825654] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6353 11:04:19.940773 <3>[ 8.960265] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6354 11:04:19.947836 <3>[ 8.970308] Bluetooth: hci0: QCA Failed to download patch (-2)
6355 11:04:19.981938 done.
6356 11:04:19.988028 Begin: Running /scripts/nfs-bottom ... done.
6357 11:04:20.014349 Begin: Running /scripts/init-bottom ... done.
6358 11:04:20.090293 <6>[ 9.109289] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6359 11:04:20.183019 <4>[ 9.202189] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6360 11:04:20.201700 <4>[ 9.220997] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6361 11:04:20.216697 <4>[ 9.236135] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6362 11:04:20.226809 <4>[ 9.249425] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6363 11:04:21.359031 <6>[ 10.381404] NET: Registered PF_INET6 protocol family
6364 11:04:21.370583 <6>[ 10.393018] Segment Routing with IPv6
6365 11:04:21.377580 <6>[ 10.400071] In-situ OAM (IOAM) with IPv6
6366 11:04:21.552037 <30>[ 10.547972] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6367 11:04:21.572899 <30>[ 10.595599] systemd[1]: Detected architecture arm64.
6368 11:04:21.584445
6369 11:04:21.587682 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6370 11:04:21.587757
6371 11:04:21.609791 <30>[ 10.632539] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6372 11:04:22.573866 <30>[ 11.593045] systemd[1]: Queued start job for default target graphical.target.
6373 11:04:22.612978 <30>[ 11.631812] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6374 11:04:22.625321 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6375 11:04:22.646150 <30>[ 11.665278] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6376 11:04:22.659500 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6377 11:04:22.678063 <30>[ 11.697407] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6378 11:04:22.692719 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6379 11:04:22.709593 <30>[ 11.728614] systemd[1]: Created slice user.slice - User and Session Slice.
6380 11:04:22.721350 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6381 11:04:22.743856 <30>[ 11.759603] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6382 11:04:22.757047 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6383 11:04:22.779494 <30>[ 11.795404] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6384 11:04:22.791966 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6385 11:04:22.817938 <30>[ 11.827360] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6386 11:04:22.837815 <30>[ 11.857345] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6387 11:04:22.846602 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6388 11:04:22.864236 <30>[ 11.883206] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6389 11:04:22.877340 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6390 11:04:22.895862 <30>[ 11.915244] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6391 11:04:22.910757 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6392 11:04:22.924813 <30>[ 11.947272] systemd[1]: Reached target paths.target - Path Units.
6393 11:04:22.939401 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6394 11:04:22.956065 <30>[ 11.975196] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6395 11:04:22.968819 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6396 11:04:22.987623 <30>[ 12.007169] systemd[1]: Reached target slices.target - Slice Units.
6397 11:04:22.999833 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6398 11:04:23.012772 <30>[ 12.035181] systemd[1]: Reached target swap.target - Swaps.
6399 11:04:23.023602 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6400 11:04:23.044354 <30>[ 12.063240] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6401 11:04:23.057178 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6402 11:04:23.076662 <30>[ 12.095626] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6403 11:04:23.090031 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6404 11:04:23.110741 <30>[ 12.129641] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6405 11:04:23.123998 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6406 11:04:23.141543 <30>[ 12.160776] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6407 11:04:23.155480 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6408 11:04:23.172912 <30>[ 12.192082] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6409 11:04:23.185030 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6410 11:04:23.205874 <30>[ 12.225049] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6411 11:04:23.219440 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6412 11:04:23.238790 <30>[ 12.257687] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6413 11:04:23.251839 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6414 11:04:23.268401 <30>[ 12.287787] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6415 11:04:23.281528 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6416 11:04:23.328396 <30>[ 12.347515] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6417 11:04:23.341210 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6418 11:04:23.365806 <30>[ 12.385052] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6419 11:04:23.378871 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6420 11:04:23.400761 <30>[ 12.419644] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6421 11:04:23.411384 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6422 11:04:23.435613 <30>[ 12.447961] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6423 11:04:23.496841 <30>[ 12.515793] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6424 11:04:23.511552 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6425 11:04:23.534553 <30>[ 12.553530] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6426 11:04:23.546489 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6427 11:04:23.570606 <30>[ 12.589486] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6428 11:04:23.581802 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6429 11:04:23.613321 <6>[ 12.632592] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6430 11:04:23.637122 <30>[ 12.656017] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6431 11:04:23.649807 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6432 11:04:23.674164 <30>[ 12.693468] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6433 11:04:23.687169 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6434 11:04:23.710197 <30>[ 12.729575] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6435 11:04:23.721940 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6436 11:04:23.750329 <6>[ 12.772234] fuse: init (API version 7.37)
6437 11:04:23.784661 <30>[ 12.803825] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6438 11:04:23.798546 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6439 11:04:23.827458 <30>[ 12.846668] systemd[1]: Starting systemd-journald.service - Journal Service...
6440 11:04:23.838516 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6441 11:04:23.859513 <30>[ 12.878911] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6442 11:04:23.869261 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6443 11:04:23.895601 <30>[ 12.911533] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6444 11:04:23.906454 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6445 11:04:23.956669 <30>[ 12.975767] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6446 11:04:23.969860 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6447 11:04:23.986644 <3>[ 13.005629] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6448 11:04:23.999199 <30>[ 13.017434] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6449 11:04:24.005579 <3>[ 13.024847] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6450 11:04:24.020301 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6451 11:04:24.031486 <3>[ 13.050568] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6452 11:04:24.051587 <3>[ 13.070378] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6453 11:04:24.058216 <30>[ 13.075831] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6454 11:04:24.080809 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File S<3>[ 13.098994] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6455 11:04:24.080890 ystem.
6456 11:04:24.100593 <3>[ 13.118731] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6457 11:04:24.111525 <30>[ 13.128087] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6458 11:04:24.122489 <3>[ 13.139825] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6459 11:04:24.142665 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 13.159849] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6460 11:04:24.142749 File System.
6461 11:04:24.159147 <30>[ 13.179987] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6462 11:04:24.173341 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6463 11:04:24.192411 <30>[ 13.211898] systemd[1]: Started systemd-journald.service - Journal Service.
6464 11:04:24.204687 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6465 11:04:24.226410 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6466 11:04:24.246538 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6467 11:04:24.266396 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6468 11:04:24.287722 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6469 11:04:24.306995 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6470 11:04:24.329170 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6471 11:04:24.356448 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6472 11:04:24.378417 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6473 11:04:24.398547 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6474 11:04:24.418534 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6475 11:04:24.439691 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6476 11:04:24.480524 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6477 11:04:24.501319 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6478 11:04:24.525471 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6479 11:04:24.548921 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6480 11:04:24.578896 <46>[ 13.597981] systemd-journald[322]: Received client request to flush runtime journal.
6481 11:04:24.616912 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6482 11:04:24.641681 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6483 11:04:24.773189 <4>[ 13.795983] power_supply_show_property: 2 callbacks suppressed
6484 11:04:24.783718 <3>[ 13.795992] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6485 11:04:24.799957 <4>[ 13.811758] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6486 11:04:24.810520 <3>[ 13.829528] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6487 11:04:24.924142 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6488 11:04:24.945631 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6489 11:04:24.965343 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6490 11:04:24.985932 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6491 11:04:25.647239 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6492 11:04:26.033432 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6493 11:04:26.050310 <3>[ 15.069221] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6494 11:04:26.078392 <3>[ 15.097432] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6495 11:04:26.092677 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6496 11:04:26.104522 <3>[ 15.123455] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6497 11:04:26.126238 <3>[ 15.144901] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6498 11:04:26.148192 <3>[ 15.167108] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6499 11:04:26.169322 <3>[ 15.188598] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6500 11:04:26.195289 <3>[ 15.214367] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6501 11:04:26.221036 [[0;32m OK [0m] Finished [0;1;39msystemd-tm<3>[ 15.239115] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6502 11:04:26.224252 pfiles-…reate Static Device Nodes in /dev.
6503 11:04:26.249314 [[0;32m OK [0m] Reached targ<3>[ 15.266379] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6504 11:04:26.255139 et [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6505 11:04:26.272951 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6506 11:04:26.333041 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6507 11:04:26.360198 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6508 11:04:26.417006 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6509 11:04:26.538227 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6510 11:04:26.604500 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6511 11:04:26.645494 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6512 11:04:26.930962 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6513 11:04:26.948449 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6514 11:04:26.965062 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6515 11:04:27.000860 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6516 11:04:27.030959 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6517 11:04:27.143551 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6518 11:04:27.198921 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6519 11:04:27.253251 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6520 11:04:27.279166 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6521 11:04:27.308872 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6522 11:04:27.332009 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6523 11:04:27.351615 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6524 11:04:27.372701 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6525 11:04:27.391871 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6526 11:04:27.452617 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6527 11:04:27.477880 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6528 11:04:27.497948 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6529 11:04:27.516975 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6530 11:04:27.565255 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6531 11:04:27.624559 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6532 11:04:27.644180 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6533 11:04:27.660511 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6534 11:04:27.676319 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6535 11:04:27.698146 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6536 11:04:27.718595 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6537 11:04:27.736509 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6538 11:04:27.754622 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6539 11:04:27.774502 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6540 11:04:27.792404 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6541 11:04:27.819338 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6542 11:04:27.836608 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6543 11:04:27.856541 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6544 11:04:27.900701 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6545 11:04:27.925346 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6546 11:04:27.954961 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6547 11:04:28.061930 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6548 11:04:28.093158 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6549 11:04:28.117796 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6550 11:04:28.138530 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6551 11:04:28.233780 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6552 11:04:28.254599 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6553 11:04:28.297300 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6554 11:04:28.341847 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6555 11:04:28.360565 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6556 11:04:28.383164 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6557 11:04:28.413657 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6558 11:04:28.435679 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6559 11:04:28.457679 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6560 11:04:28.502587 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6561 11:04:28.551128 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6562 11:04:28.629181
6563 11:04:28.632487 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6564 11:04:28.632595
6565 11:04:28.636048 debian-bookworm-arm64 login: root (automatic login)
6566 11:04:28.636127
6567 11:04:28.898454 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
6568 11:04:28.898567
6569 11:04:28.904337 The programs included with the Debian GNU/Linux system are free software;
6570 11:04:28.911434 the exact distribution terms for each program are described in the
6571 11:04:28.914630 individual files in /usr/share/doc/*/copyright.
6572 11:04:28.914704
6573 11:04:28.921668 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6574 11:04:28.924509 permitted by applicable law.
6575 11:04:29.949044 Matched prompt #10: / #
6577 11:04:29.949283 Setting prompt string to ['/ #']
6578 11:04:29.949370 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6580 11:04:29.949545 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6581 11:04:29.949627 start: 2.2.6 expect-shell-connection (timeout 00:03:49) [common]
6582 11:04:29.949686 Setting prompt string to ['/ #']
6583 11:04:29.949739 Forcing a shell prompt, looking for ['/ #']
6584 11:04:29.949791 Sending line: ''
6586 11:04:30.000066 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6587 11:04:30.000165 Waiting using forced prompt support (timeout 00:02:30)
6588 11:04:30.005261 / #
6589 11:04:30.005514 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6590 11:04:30.005600 start: 2.2.7 export-device-env (timeout 00:03:49) [common]
6591 11:04:30.005672 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786791/extract-nfsrootfs-ow0ibkbq'"
6593 11:04:30.110542 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786791/extract-nfsrootfs-ow0ibkbq'
6594 11:04:30.110841 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
6596 11:04:30.216167 / # export NFS_SERVER_IP='192.168.201.1'
6597 11:04:30.216439 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6598 11:04:30.216533 end: 2.2 depthcharge-retry (duration 00:01:11) [common]
6599 11:04:30.216628 end: 2 depthcharge-action (duration 00:01:11) [common]
6600 11:04:30.216719 start: 3 lava-test-retry (timeout 00:08:07) [common]
6601 11:04:30.216800 start: 3.1 lava-test-shell (timeout 00:08:07) [common]
6602 11:04:30.216876 Using namespace: common
6603 11:04:30.216942 Sending line: '#'
6605 11:04:30.317301 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6606 11:04:30.321984 / # #
6607 11:04:30.322239 Using /lava-14786791
6608 11:04:30.322300 Sending line: 'export SHELL=/bin/bash'
6610 11:04:30.428039 / # export SHELL=/bin/bash
6611 11:04:30.428279 Sending line: '. /lava-14786791/environment'
6613 11:04:30.533271 / # . /lava-14786791/environment
6614 11:04:30.538249 Sending line: '/lava-14786791/bin/lava-test-runner /lava-14786791/0'
6616 11:04:30.638621 Test shell timeout: 10s (minimum of the action and connection timeout)
6617 11:04:30.643606 / # /lava-14786791/bin/lava-test-runner /lava-14786791/0
6618 11:04:30.865346 + export TESTRUN_ID=0_timesync-off
6619 11:04:30.868924 + TESTRUN_ID=0_timesync-off
6620 11:04:30.871781 + cd /lava-14786791/0/tests/0_timesync-off
6621 11:04:30.875360 ++ cat uuid
6622 11:04:30.878404 + UUID=14786791_1.6.2.3.1
6623 11:04:30.878506 + set +x
6624 11:04:30.885312 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14786791_1.6.2.3.1>
6625 11:04:30.885620 Received signal: <STARTRUN> 0_timesync-off 14786791_1.6.2.3.1
6626 11:04:30.885701 Starting test lava.0_timesync-off (14786791_1.6.2.3.1)
6627 11:04:30.885780 Skipping test definition patterns.
6628 11:04:30.888317 + systemctl stop systemd-timesyncd
6629 11:04:30.948717 + set +x
6630 11:04:30.952214 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14786791_1.6.2.3.1>
6631 11:04:30.952465 Received signal: <ENDRUN> 0_timesync-off 14786791_1.6.2.3.1
6632 11:04:30.952536 Ending use of test pattern.
6633 11:04:30.952591 Ending test lava.0_timesync-off (14786791_1.6.2.3.1), duration 0.07
6635 11:04:31.009123 + export TESTRUN_ID=1_kselftest-alsa
6636 11:04:31.009220 + TESTRUN_ID=1_kselftest-alsa
6637 11:04:31.015167 + cd /lava-14786791/0/tests/1_kselftest-alsa
6638 11:04:31.015269 ++ cat uuid
6639 11:04:31.018944 + UUID=14786791_1.6.2.3.5
6640 11:04:31.019014 + set +x
6641 11:04:31.025438 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14786791_1.6.2.3.5>
6642 11:04:31.025686 Received signal: <STARTRUN> 1_kselftest-alsa 14786791_1.6.2.3.5
6643 11:04:31.025753 Starting test lava.1_kselftest-alsa (14786791_1.6.2.3.5)
6644 11:04:31.025844 Skipping test definition patterns.
6645 11:04:31.028392 + cd ./automated/linux/kselftest/
6646 11:04:31.054571 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
6647 11:04:31.087523 INFO: install_deps skipped
6648 11:04:31.575744 --2024-07-10 11:04:17-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
6649 11:04:31.582308 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6650 11:04:31.710355 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6651 11:04:31.843898 HTTP request sent, awaiting response... 200 OK
6652 11:04:31.847350 Length: 1919896 (1.8M) [application/octet-stream]
6653 11:04:31.850212 Saving to: 'kselftest_armhf.tar.gz'
6654 11:04:31.850289
6655 11:04:31.850362
6656 11:04:32.109579 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6657 11:04:32.374435 kselftest_armhf.tar 2%[ ] 47.81K 180KB/s
6658 11:04:32.689680 kselftest_armhf.tar 11%[=> ] 214.67K 405KB/s
6659 11:04:32.826895 kselftest_armhf.tar 44%[=======> ] 828.37K 980KB/s
6660 11:04:32.833019 kselftest_armhf.tar 100%[===================>] 1.83M 1.86MB/s in 1.0s
6661 11:04:32.833106
6662 11:04:33.001266 2024-07-10 11:04:18 (1.86 MB/s) - 'kselftest_armhf.tar.gz' saved [1919896/1919896]
6663 11:04:33.001411
6664 11:04:39.648151 skiplist:
6665 11:04:39.651941 ========================================
6666 11:04:39.654630 ========================================
6667 11:04:39.703032 alsa:mixer-test
6668 11:04:39.724458 ============== Tests to run ===============
6669 11:04:39.728099 alsa:mixer-test
6670 11:04:39.731386 ===========End Tests to run ===============
6671 11:04:39.734415 shardfile-alsa pass
6672 11:04:39.846744 <12>[ 28.867998] kselftest: Running tests in alsa
6673 11:04:39.857284 TAP version 13
6674 11:04:39.873187 1..1
6675 11:04:39.889366 # selftests: alsa: mixer-test
6676 11:04:40.018829 <6>[ 29.034270] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6677 11:04:40.032459 <6>[ 29.046642] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6678 11:04:40.045208 <6>[ 29.058918] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6679 11:04:40.054903 <6>[ 29.071191] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6680 11:04:40.068541 <6>[ 29.083405] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6681 11:04:40.081180 <6>[ 29.095604] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6682 11:04:40.091254 <6>[ 29.107105] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6683 11:04:40.104441 <6>[ 29.118477] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6684 11:04:40.114623 <6>[ 29.129826] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6685 11:04:40.124264 <6>[ 29.141162] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6686 11:04:40.137221 <6>[ 29.152501] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6687 11:04:40.147390 <6>[ 29.163834] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6688 11:04:40.160172 <6>[ 29.175164] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6689 11:04:40.170497 <6>[ 29.186497] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6690 11:04:40.183588 <6>[ 29.197831] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6691 11:04:40.193367 <6>[ 29.209177] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6692 11:04:40.203790 <6>[ 29.220512] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6693 11:04:40.216722 <6>[ 29.231867] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6694 11:04:40.226447 <6>[ 29.243207] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6695 11:04:40.239469 <6>[ 29.254560] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6696 11:04:40.249670 <6>[ 29.265927] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6697 11:04:40.263108 <6>[ 29.277288] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6698 11:04:40.272587 <6>[ 29.288662] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6699 11:04:40.285470 <6>[ 29.300026] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6700 11:04:40.295291 <6>[ 29.311406] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6701 11:04:40.308598 <6>[ 29.322790] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6702 11:04:40.318323 # TAP version 13<6>[ 29.334129] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6703 11:04:40.318400
6704 11:04:40.321990 # 1..658
6705 11:04:40.331809 # ok<6>[ 29.346803] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6706 11:04:40.345023 <6>[ 29.359480] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6707 11:04:40.355407 <6>[ 29.370816] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6708 11:04:40.358400 1 get_value.0.93
6709 11:04:40.358778 # ok 2 name.0.93
6710 11:04:40.361728 # ok 3 write_default.0.93
6711 11:04:40.364662 # ok 4 write_valid.0.93
6712 11:04:40.365041 # ok 5 write_invalid.0.93
6713 11:04:40.368276 # ok 6 event_missing.0.93
6714 11:04:40.371308 # ok 7 event_spurious.0.93
6715 11:04:40.371694 # ok 8 get_value.0.92
6716 11:04:40.374685 # ok 9 name.0.92
6717 11:04:40.378121 # ok 10 write_default.0.92
6718 11:04:40.378506 # ok 11 write_valid.0.92
6719 11:04:40.381805 # ok 12 write_invalid.0.92
6720 11:04:40.385139 # ok 13 event_missing.0.92
6721 11:04:40.388052 # ok 14 event_spurious.0.92
6722 11:04:40.388433 # ok 15 get_value.0.91
6723 11:04:40.391715 # ok 16 name.0.91
6724 11:04:40.394619 # ok 17 write_default.0.91
6725 11:04:40.394998 # ok 18 write_valid.0.91
6726 11:04:40.398265 # ok 19 write_invalid.0.91
6727 11:04:40.401309 # ok 20 event_missing.0.91
6728 11:04:40.404167 # ok 21 event_spurious.0.91
6729 11:04:40.407563 # ok 22 get_value.0.90
6730 11:04:40.407970 # ok 23 name.0.90
6731 11:04:40.410969 # ok 24 write_default.0.90
6732 11:04:40.414000 # ok 25 write_valid.0.90
6733 11:04:40.414418 # ok 26 write_invalid.0.90
6734 11:04:40.417744 # ok 27 event_missing.0.90
6735 11:04:40.420654 # ok 28 event_spurious.0.90
6736 11:04:40.421060 # ok 29 get_value.0.89
6737 11:04:40.424712 # ok 30 name.0.89
6738 11:04:40.427158 # ok 31 write_default.0.89
6739 11:04:40.427563 # ok 32 write_valid.0.89
6740 11:04:40.430887 # ok 33 write_invalid.0.89
6741 11:04:40.434157 # ok 34 event_missing.0.89
6742 11:04:40.437609 # ok 35 event_spurious.0.89
6743 11:04:40.438119 # ok 36 get_value.0.88
6744 11:04:40.440559 # ok 37 name.0.88
6745 11:04:40.443816 # ok 38 write_default.0.88
6746 11:04:40.446909 # # Spurious event generated for AIF Out Mux
6747 11:04:40.450268 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6748 11:04:40.456908 # # Spurious event generated for AIF Out Mux
6749 11:04:40.460398 # not ok 39 write_valid.0.88
6750 11:04:40.460786 # ok 40 write_invalid.0.88
6751 11:04:40.463825 # ok 41 event_missing.0.88
6752 11:04:40.467010 # not ok 42 event_spurious.0.88
6753 11:04:40.470464 # ok 43 get_value.0.87
6754 11:04:40.470848 # ok 44 name.0.87
6755 11:04:40.473093 # ok 45 write_default.0.87
6756 11:04:40.476377 # ok 46 write_valid.0.87
6757 11:04:40.476764 # ok 47 write_invalid.0.87
6758 11:04:40.480221 # ok 48 event_missing.0.87
6759 11:04:40.483569 # ok 49 event_spurious.0.87
6760 11:04:40.486556 # ok 50 get_value.0.86
6761 11:04:40.486941 # ok 51 name.0.86
6762 11:04:40.489798 # ok 52 write_default.0.86
6763 11:04:40.493493 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6764 11:04:40.500115 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6765 11:04:40.503497 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6766 11:04:40.506792 # not ok 53 write_valid.0.86
6767 11:04:40.510333 # ok 54 write_invalid.0.86
6768 11:04:40.510725 # ok 55 event_missing.0.86
6769 11:04:40.513418 # ok 56 event_spurious.0.86
6770 11:04:40.516873 # ok 57 get_value.0.85
6771 11:04:40.517363 # ok 58 name.0.85
6772 11:04:40.519807 # ok 59 write_default.0.85
6773 11:04:40.525980 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6774 11:04:40.529300 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6775 11:04:40.532591 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6776 11:04:40.535754 # not ok 60 write_valid.0.85
6777 11:04:40.539195 # ok 61 write_invalid.0.85
6778 11:04:40.542545 # ok 62 event_missing.0.85
6779 11:04:40.546176 # ok 63 event_spurious.0.85
6780 11:04:40.546565 # ok 64 get_value.0.84
6781 11:04:40.549193 # ok 65 name.0.84
6782 11:04:40.549587 # ok 66 write_default.0.84
6783 11:04:40.552133 # ok 67 write_valid.0.84
6784 11:04:40.555422 # ok 68 write_invalid.0.84
6785 11:04:40.559520 # ok 69 event_missing.0.84
6786 11:04:40.559905 # ok 70 event_spurious.0.84
6787 11:04:40.562343 # ok 71 get_value.0.83
6788 11:04:40.565493 # ok 72 name.0.83
6789 11:04:40.565879 # ok 73 write_default.0.83
6790 11:04:40.569243 # ok 74 write_valid.0.83
6791 11:04:40.572141 # ok 75 write_invalid.0.83
6792 11:04:40.575256 # ok 76 event_missing.0.83
6793 11:04:40.575331 # ok 77 event_spurious.0.83
6794 11:04:40.578253 # ok 78 get_value.0.82
6795 11:04:40.581546 # ok 79 name.0.82
6796 11:04:40.584714 # # Headset Jack is not writeable
6797 11:04:40.584789 # ok 80 # SKIP write_default.0.82
6798 11:04:40.588265 # # Headset Jack is not writeable
6799 11:04:40.591859 # ok 81 # SKIP write_valid.0.82
6800 11:04:40.594740 # # Headset Jack is not writeable
6801 11:04:40.597964 # ok 82 # SKIP write_invalid.0.82
6802 11:04:40.601522 # ok 83 event_missing.0.82
6803 11:04:40.604607 # ok 84 event_spurious.0.82
6804 11:04:40.604701 # ok 85 get_value.0.81
6805 11:04:40.608147 # ok 86 name.0.81
6806 11:04:40.611332 # ok 87 write_default.0.81
6807 11:04:40.614627 # # No event generated for Wake-on-Voice Phase2 Switch
6808 11:04:40.621820 # # No event generated for Wake-on-Voice Phase2 Switch
6809 11:04:40.624787 # ok 88 write_valid.0.81
6810 11:04:40.627943 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6811 11:04:40.634346 # # No event generated for Wake-on-Voice Phase2 Switch
6812 11:04:40.634439 # not ok 89 write_invalid.0.81
6813 11:04:40.637523 # not ok 90 event_missing.0.81
6814 11:04:40.641570 # ok 91 event_spurious.0.81
6815 11:04:40.644539 # ok 92 get_value.0.80
6816 11:04:40.644650 # ok 93 name.0.80
6817 11:04:40.647759 # ok 94 write_default.0.80
6818 11:04:40.650831 # ok 95 write_valid.0.80
6819 11:04:40.654042 # ok 96 write_invalid.0.80
6820 11:04:40.654183 # ok 97 event_missing.0.80
6821 11:04:40.657570 # ok 98 event_spurious.0.80
6822 11:04:40.660632 # # Handset Volume.0 value -13 less than minimum 0
6823 11:04:40.664194 # not ok 99 get_value.0.79
6824 11:04:40.667637 # ok 100 name.0.79
6825 11:04:40.670623 # # snd_ctl_elem_write() failed: Invalid argument
6826 11:04:40.673921 # not ok 101 write_default.0.79
6827 11:04:40.677665 # # snd_ctl_elem_write() failed: Invalid argument
6828 11:04:40.680917 # not ok 102 write_valid.0.79
6829 11:04:40.687705 # # snd_ctl_elem_write() failed: Invalid argument
6830 11:04:40.690553 # not ok 103 write_invalid.0.79
6831 11:04:40.690940 # ok 104 event_missing.0.79
6832 11:04:40.694212 # ok 105 event_spurious.0.79
6833 11:04:40.700809 # # Lineout Volume.0 value -13 less than minimum 0
6834 11:04:40.704034 # # Lineout Volume.1 value -13 less than minimum 0
6835 11:04:40.707328 # not ok 106 get_value.0.78
6836 11:04:40.707713 # ok 107 name.0.78
6837 11:04:40.713866 # # snd_ctl_elem_write() failed: Invalid argument
6838 11:04:40.714289 # not ok 108 write_default.0.78
6839 11:04:40.720236 # # snd_ctl_elem_write() failed: Invalid argument
6840 11:04:40.723648 # not ok 109 write_valid.0.78
6841 11:04:40.727236 # # snd_ctl_elem_write() failed: Invalid argument
6842 11:04:40.730275 # not ok 110 write_invalid.0.78
6843 11:04:40.733774 # ok 111 event_missing.0.78
6844 11:04:40.734292 # ok 112 event_spurious.0.78
6845 11:04:40.740230 # # Headphone Volume.0 value -13 less than minimum 0
6846 11:04:40.743269 # # Headphone Volume.1 value -13 less than minimum 0
6847 11:04:40.746507 # not ok 113 get_value.0.77
6848 11:04:40.750055 # ok 114 name.0.77
6849 11:04:40.753563 # # snd_ctl_elem_write() failed: Invalid argument
6850 11:04:40.756895 # not ok 115 write_default.0.77
6851 11:04:40.759939 # # snd_ctl_elem_write() failed: Invalid argument
6852 11:04:40.763236 # not ok 116 write_valid.0.77
6853 11:04:40.766354 # # snd_ctl_elem_write() failed: Invalid argument
6854 11:04:40.769702 # not ok 117 write_invalid.0.77
6855 11:04:40.772935 # ok 118 event_missing.0.77
6856 11:04:40.776110 # ok 119 event_spurious.0.77
6857 11:04:40.776514 # ok 120 get_value.0.76
6858 11:04:40.782744 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6859 11:04:40.786356 # not ok 121 name.0.76
6860 11:04:40.789871 # ok 122 write_default.0.76
6861 11:04:40.790330 # ok 123 write_valid.0.76
6862 11:04:40.793035 # ok 124 write_invalid.0.76
6863 11:04:40.796512 # ok 125 event_missing.0.76
6864 11:04:40.799712 # ok 126 event_spurious.0.76
6865 11:04:40.800275 # ok 127 get_value.0.75
6866 11:04:40.806305 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6867 11:04:40.809451 # not ok 128 name.0.75
6868 11:04:40.812750 # ok 129 write_default.0.75
6869 11:04:40.816119 # ok 130 write_valid.0.75
6870 11:04:40.816651 # ok 131 write_invalid.0.75
6871 11:04:40.819262 # ok 132 event_missing.0.75
6872 11:04:40.822438 # ok 133 event_spurious.0.75
6873 11:04:40.822823 # ok 134 get_value.0.74
6874 11:04:40.829194 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6875 11:04:40.832573 # not ok 135 name.0.74
6876 11:04:40.836255 # ok 136 write_default.0.74
6877 11:04:40.839399 # ok 137 write_valid.0.74
6878 11:04:40.839782 # ok 138 write_invalid.0.74
6879 11:04:40.842657 # ok 139 event_missing.0.74
6880 11:04:40.845909 # ok 140 event_spurious.0.74
6881 11:04:40.848870 # ok 141 get_value.0.73
6882 11:04:40.855858 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6883 11:04:40.856246 # not ok 142 name.0.73
6884 11:04:40.858908 # ok 143 write_default.0.73
6885 11:04:40.862322 # ok 144 write_valid.0.73
6886 11:04:40.862735 # ok 145 write_invalid.0.73
6887 11:04:40.865227 # ok 146 event_missing.0.73
6888 11:04:40.868800 # ok 147 event_spurious.0.73
6889 11:04:40.871922 # ok 148 get_value.0.72
6890 11:04:40.878664 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6891 11:04:40.879053 # not ok 149 name.0.72
6892 11:04:40.881994 # ok 150 write_default.0.72
6893 11:04:40.885441 # ok 151 write_valid.0.72
6894 11:04:40.885825 # ok 152 write_invalid.0.72
6895 11:04:40.888335 # ok 153 event_missing.0.72
6896 11:04:40.892030 # ok 154 event_spurious.0.72
6897 11:04:40.895177 # ok 155 get_value.0.71
6898 11:04:40.901567 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6899 11:04:40.901959 # not ok 156 name.0.71
6900 11:04:40.904791 # ok 157 write_default.0.71
6901 11:04:40.908526 # ok 158 write_valid.0.71
6902 11:04:40.908957 # ok 159 write_invalid.0.71
6903 11:04:40.911627 # ok 160 event_missing.0.71
6904 11:04:40.915427 # ok 161 event_spurious.0.71
6905 11:04:40.918166 # ok 162 get_value.0.70
6906 11:04:40.924740 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6907 11:04:40.925279 # not ok 163 name.0.70
6908 11:04:40.928402 # ok 164 write_default.0.70
6909 11:04:40.931476 # ok 165 write_valid.0.70
6910 11:04:40.931984 # ok 166 write_invalid.0.70
6911 11:04:40.934732 # ok 167 event_missing.0.70
6912 11:04:40.937729 # ok 168 event_spurious.0.70
6913 11:04:40.941692 # ok 169 get_value.0.69
6914 11:04:40.944958 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6915 11:04:40.948116 # not ok 170 name.0.69
6916 11:04:40.951632 # ok 171 write_default.0.69
6917 11:04:40.954539 # ok 172 write_valid.0.69
6918 11:04:40.954933 # ok 173 write_invalid.0.69
6919 11:04:40.957728 # ok 174 event_missing.0.69
6920 11:04:40.961375 # ok 175 event_spurious.0.69
6921 11:04:40.964258 # ok 176 get_value.0.68
6922 11:04:40.967944 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6923 11:04:40.971208 # not ok 177 name.0.68
6924 11:04:40.974509 # ok 178 write_default.0.68
6925 11:04:40.975004 # ok 179 write_valid.0.68
6926 11:04:40.977883 # ok 180 write_invalid.0.68
6927 11:04:40.980949 # ok 181 event_missing.0.68
6928 11:04:40.984848 # ok 182 event_spurious.0.68
6929 11:04:40.985352 # ok 183 get_value.0.67
6930 11:04:40.991321 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6931 11:04:40.994405 # not ok 184 name.0.67
6932 11:04:40.997671 # ok 185 write_default.0.67
6933 11:04:40.998161 # ok 186 write_valid.0.67
6934 11:04:41.000993 # ok 187 write_invalid.0.67
6935 11:04:41.004639 # ok 188 event_missing.0.67
6936 11:04:41.008012 # ok 189 event_spurious.0.67
6937 11:04:41.008400 # ok 190 get_value.0.66
6938 11:04:41.014991 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6939 11:04:41.017466 # not ok 191 name.0.66
6940 11:04:41.021378 # ok 192 write_default.0.66
6941 11:04:41.021884 # ok 193 write_valid.0.66
6942 11:04:41.024189 # ok 194 write_invalid.0.66
6943 11:04:41.027318 # ok 195 event_missing.0.66
6944 11:04:41.030562 # ok 196 event_spurious.0.66
6945 11:04:41.031028 # ok 197 get_value.0.65
6946 11:04:41.037219 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6947 11:04:41.040643 # not ok 198 name.0.65
6948 11:04:41.041107 # ok 199 write_default.0.65
6949 11:04:41.043498 # ok 200 write_valid.0.65
6950 11:04:41.046896 # ok 201 write_invalid.0.65
6951 11:04:41.049913 # ok 202 event_missing.0.65
6952 11:04:41.053224 # ok 203 event_spurious.0.65
6953 11:04:41.053716 # ok 204 get_value.0.64
6954 11:04:41.060226 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6955 11:04:41.063444 # not ok 205 name.0.64
6956 11:04:41.066494 # ok 206 write_default.0.64
6957 11:04:41.066877 # ok 207 write_valid.0.64
6958 11:04:41.069929 # ok 208 write_invalid.0.64
6959 11:04:41.073362 # ok 209 event_missing.0.64
6960 11:04:41.076834 # ok 210 event_spurious.0.64
6961 11:04:41.077229 # ok 211 get_value.0.63
6962 11:04:41.083125 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6963 11:04:41.086478 # not ok 212 name.0.63
6964 11:04:41.089852 # ok 213 write_default.0.63
6965 11:04:41.090284 # ok 214 write_valid.0.63
6966 11:04:41.093256 # ok 215 write_invalid.0.63
6967 11:04:41.096681 # ok 216 event_missing.0.63
6968 11:04:41.100179 # ok 217 event_spurious.0.63
6969 11:04:41.100640 # ok 218 get_value.0.62
6970 11:04:41.106370 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6971 11:04:41.109703 # not ok 219 name.0.62
6972 11:04:41.113120 # ok 220 write_default.0.62
6973 11:04:41.113574 # ok 221 write_valid.0.62
6974 11:04:41.116559 # ok 222 write_invalid.0.62
6975 11:04:41.119572 # ok 223 event_missing.0.62
6976 11:04:41.122798 # ok 224 event_spurious.0.62
6977 11:04:41.123217 # ok 225 get_value.0.61
6978 11:04:41.129293 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
6979 11:04:41.132427 # not ok 226 name.0.61
6980 11:04:41.136342 # ok 227 write_default.0.61
6981 11:04:41.136727 # ok 228 write_valid.0.61
6982 11:04:41.139428 # ok 229 write_invalid.0.61
6983 11:04:41.142616 # ok 230 event_missing.0.61
6984 11:04:41.145948 # ok 231 event_spurious.0.61
6985 11:04:41.146401 # ok 232 get_value.0.60
6986 11:04:41.152447 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
6987 11:04:41.156395 # not ok 233 name.0.60
6988 11:04:41.159791 # ok 234 write_default.0.60
6989 11:04:41.160262 # ok 235 write_valid.0.60
6990 11:04:41.162417 # ok 236 write_invalid.0.60
6991 11:04:41.165600 # ok 237 event_missing.0.60
6992 11:04:41.168990 # ok 238 event_spurious.0.60
6993 11:04:41.169376 # ok 239 get_value.0.59
6994 11:04:41.177091 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
6995 11:04:41.179206 # not ok 240 name.0.59
6996 11:04:41.182002 # ok 241 write_default.0.59
6997 11:04:41.182438 # ok 242 write_valid.0.59
6998 11:04:41.185742 # ok 243 write_invalid.0.59
6999 11:04:41.188829 # ok 244 event_missing.0.59
7000 11:04:41.191810 # ok 245 event_spurious.0.59
7001 11:04:41.192194 # ok 246 get_value.0.58
7002 11:04:41.198603 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
7003 11:04:41.202120 # not ok 247 name.0.58
7004 11:04:41.202583 # ok 248 write_default.0.58
7005 11:04:41.205767 # ok 249 write_valid.0.58
7006 11:04:41.209124 # ok 250 write_invalid.0.58
7007 11:04:41.212173 # ok 251 event_missing.0.58
7008 11:04:41.212558 # ok 252 event_spurious.0.58
7009 11:04:41.215716 # ok 253 get_value.0.57
7010 11:04:41.222405 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
7011 11:04:41.225623 # not ok 254 name.0.57
7012 11:04:41.226037 # ok 255 write_default.0.57
7013 11:04:41.228630 # ok 256 write_valid.0.57
7014 11:04:41.231752 # ok 257 write_invalid.0.57
7015 11:04:41.235063 # ok 258 event_missing.0.57
7016 11:04:41.235450 # ok 259 event_spurious.0.57
7017 11:04:41.238473 # ok 260 get_value.0.56
7018 11:04:41.245275 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
7019 11:04:41.248161 # not ok 261 name.0.56
7020 11:04:41.248587 # ok 262 write_default.0.56
7021 11:04:41.251406 # ok 263 write_valid.0.56
7022 11:04:41.254821 # ok 264 write_invalid.0.56
7023 11:04:41.258229 # ok 265 event_missing.0.56
7024 11:04:41.261466 # ok 266 event_spurious.0.56
7025 11:04:41.262047 # ok 267 get_value.0.55
7026 11:04:41.267891 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
7027 11:04:41.271074 # not ok 268 name.0.55
7028 11:04:41.274332 # ok 269 write_default.0.55
7029 11:04:41.274897 # ok 270 write_valid.0.55
7030 11:04:41.277549 # ok 271 write_invalid.0.55
7031 11:04:41.280647 # ok 272 event_missing.0.55
7032 11:04:41.284859 # ok 273 event_spurious.0.55
7033 11:04:41.285269 # ok 274 get_value.0.54
7034 11:04:41.290978 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
7035 11:04:41.294316 # not ok 275 name.0.54
7036 11:04:41.297291 # ok 276 write_default.0.54
7037 11:04:41.297735 # ok 277 write_valid.0.54
7038 11:04:41.300773 # ok 278 write_invalid.0.54
7039 11:04:41.303931 # ok 279 event_missing.0.54
7040 11:04:41.307378 # ok 280 event_spurious.0.54
7041 11:04:41.307764 # ok 281 get_value.0.53
7042 11:04:41.314148 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
7043 11:04:41.316876 # not ok 282 name.0.53
7044 11:04:41.320275 # ok 283 write_default.0.53
7045 11:04:41.320669 # ok 284 write_valid.0.53
7046 11:04:41.323467 # ok 285 write_invalid.0.53
7047 11:04:41.326862 # ok 286 event_missing.0.53
7048 11:04:41.330435 # ok 287 event_spurious.0.53
7049 11:04:41.333438 # ok 288 get_value.0.52
7050 11:04:41.336842 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
7051 11:04:41.340294 # not ok 289 name.0.52
7052 11:04:41.343626 # ok 290 write_default.0.52
7053 11:04:41.346716 # ok 291 write_valid.0.52
7054 11:04:41.347101 # ok 292 write_invalid.0.52
7055 11:04:41.349880 # ok 293 event_missing.0.52
7056 11:04:41.352981 # ok 294 event_spurious.0.52
7057 11:04:41.356365 # ok 295 get_value.0.51
7058 11:04:41.363698 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
7059 11:04:41.364182 # not ok 296 name.0.51
7060 11:04:41.366482 # ok 297 write_default.0.51
7061 11:04:41.370364 # ok 298 write_valid.0.51
7062 11:04:41.370865 # ok 299 write_invalid.0.51
7063 11:04:41.373613 # ok 300 event_missing.0.51
7064 11:04:41.376291 # ok 301 event_spurious.0.51
7065 11:04:41.379939 # ok 302 get_value.0.50
7066 11:04:41.386615 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
7067 11:04:41.387121 # not ok 303 name.0.50
7068 11:04:41.389577 # ok 304 write_default.0.50
7069 11:04:41.393218 # ok 305 write_valid.0.50
7070 11:04:41.395968 # ok 306 write_invalid.0.50
7071 11:04:41.396460 # ok 307 event_missing.0.50
7072 11:04:41.399204 # ok 308 event_spurious.0.50
7073 11:04:41.402852 # ok 309 get_value.0.49
7074 11:04:41.408843 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
7075 11:04:41.409313 # not ok 310 name.0.49
7076 11:04:41.412677 # ok 311 write_default.0.49
7077 11:04:41.415514 # ok 312 write_valid.0.49
7078 11:04:41.419217 # ok 313 write_invalid.0.49
7079 11:04:41.422556 # ok 314 event_missing.0.49
7080 11:04:41.423047 # ok 315 event_spurious.0.49
7081 11:04:41.425355 # ok 316 get_value.0.48
7082 11:04:41.432190 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
7083 11:04:41.434989 # not ok 317 name.0.48
7084 11:04:41.435539 # ok 318 write_default.0.48
7085 11:04:41.438132 # ok 319 write_valid.0.48
7086 11:04:41.441527 # ok 320 write_invalid.0.48
7087 11:04:41.444595 # ok 321 event_missing.0.48
7088 11:04:41.448130 # ok 322 event_spurious.0.48
7089 11:04:41.448688 # ok 323 get_value.0.47
7090 11:04:41.454780 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
7091 11:04:41.458140 # not ok 324 name.0.47
7092 11:04:41.461052 # ok 325 write_default.0.47
7093 11:04:41.461435 # ok 326 write_valid.0.47
7094 11:04:41.464856 # ok 327 write_invalid.0.47
7095 11:04:41.467927 # ok 328 event_missing.0.47
7096 11:04:41.471199 # ok 329 event_spurious.0.47
7097 11:04:41.471580 # ok 330 get_value.0.46
7098 11:04:41.478067 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
7099 11:04:41.481280 # not ok 331 name.0.46
7100 11:04:41.484360 # ok 332 write_default.0.46
7101 11:04:41.484828 # ok 333 write_valid.0.46
7102 11:04:41.488146 # ok 334 write_invalid.0.46
7103 11:04:41.490911 # ok 335 event_missing.0.46
7104 11:04:41.494761 # ok 336 event_spurious.0.46
7105 11:04:41.495243 # ok 337 get_value.0.45
7106 11:04:41.501404 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
7107 11:04:41.504179 # not ok 338 name.0.45
7108 11:04:41.507051 # ok 339 write_default.0.45
7109 11:04:41.510395 # ok 340 write_valid.0.45
7110 11:04:41.510820 # ok 341 write_invalid.0.45
7111 11:04:41.514419 # ok 342 event_missing.0.45
7112 11:04:41.517541 # ok 343 event_spurious.0.45
7113 11:04:41.520891 # ok 344 get_value.0.44
7114 11:04:41.524228 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
7115 11:04:41.527418 # not ok 345 name.0.44
7116 11:04:41.530279 # ok 346 write_default.0.44
7117 11:04:41.533754 # ok 347 write_valid.0.44
7118 11:04:41.534210 # ok 348 write_invalid.0.44
7119 11:04:41.536853 # ok 349 event_missing.0.44
7120 11:04:41.540301 # ok 350 event_spurious.0.44
7121 11:04:41.543421 # ok 351 get_value.0.43
7122 11:04:41.550649 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
7123 11:04:41.551155 # not ok 352 name.0.43
7124 11:04:41.553519 # ok 353 write_default.0.43
7125 11:04:41.556728 # ok 354 write_valid.0.43
7126 11:04:41.557244 # ok 355 write_invalid.0.43
7127 11:04:41.560533 # ok 356 event_missing.0.43
7128 11:04:41.563648 # ok 357 event_spurious.0.43
7129 11:04:41.566812 # ok 358 get_value.0.42
7130 11:04:41.573294 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
7131 11:04:41.573811 # not ok 359 name.0.42
7132 11:04:41.576626 # ok 360 write_default.0.42
7133 11:04:41.580124 # ok 361 write_valid.0.42
7134 11:04:41.583389 # ok 362 write_invalid.0.42
7135 11:04:41.583891 # ok 363 event_missing.0.42
7136 11:04:41.586586 # ok 364 event_spurious.0.42
7137 11:04:41.589983 # ok 365 get_value.0.41
7138 11:04:41.596837 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
7139 11:04:41.597365 # not ok 366 name.0.41
7140 11:04:41.599670 # ok 367 write_default.0.41
7141 11:04:41.603289 # ok 368 write_valid.0.41
7142 11:04:41.606256 # ok 369 write_invalid.0.41
7143 11:04:41.609639 # ok 370 event_missing.0.41
7144 11:04:41.610338 # ok 371 event_spurious.0.41
7145 11:04:41.612964 # ok 372 get_value.0.40
7146 11:04:41.619265 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
7147 11:04:41.619756 # not ok 373 name.0.40
7148 11:04:41.622820 # ok 374 write_default.0.40
7149 11:04:41.626064 # ok 375 write_valid.0.40
7150 11:04:41.629371 # ok 376 write_invalid.0.40
7151 11:04:41.632520 # ok 377 event_missing.0.40
7152 11:04:41.632964 # ok 378 event_spurious.0.40
7153 11:04:41.635552 # ok 379 get_value.0.39
7154 11:04:41.642232 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7155 11:04:41.645769 # not ok 380 name.0.39
7156 11:04:41.648925 # ok 381 write_default.0.39
7157 11:04:41.649307 # ok 382 write_valid.0.39
7158 11:04:41.652132 # ok 383 write_invalid.0.39
7159 11:04:41.655543 # ok 384 event_missing.0.39
7160 11:04:41.658729 # ok 385 event_spurious.0.39
7161 11:04:41.659114 # ok 386 get_value.0.38
7162 11:04:41.665456 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7163 11:04:41.668921 # not ok 387 name.0.38
7164 11:04:41.671807 # ok 388 write_default.0.38
7165 11:04:41.672281 # ok 389 write_valid.0.38
7166 11:04:41.674905 # ok 390 write_invalid.0.38
7167 11:04:41.678806 # ok 391 event_missing.0.38
7168 11:04:41.681955 # ok 392 event_spurious.0.38
7169 11:04:41.685515 # ok 393 get_value.0.37
7170 11:04:41.691522 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7171 11:04:41.691951 # not ok 394 name.0.37
7172 11:04:41.694709 # ok 395 write_default.0.37
7173 11:04:41.698047 # ok 396 write_valid.0.37
7174 11:04:41.701452 # ok 397 write_invalid.0.37
7175 11:04:41.701957 # ok 398 event_missing.0.37
7176 11:04:41.705080 # ok 399 event_spurious.0.37
7177 11:04:41.707724 # ok 400 get_value.0.36
7178 11:04:41.714510 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7179 11:04:41.717488 # not ok 401 name.0.36
7180 11:04:41.717896 # ok 402 write_default.0.36
7181 11:04:41.721083 # ok 403 write_valid.0.36
7182 11:04:41.724458 # ok 404 write_invalid.0.36
7183 11:04:41.727480 # ok 405 event_missing.0.36
7184 11:04:41.727865 # ok 406 event_spurious.0.36
7185 11:04:41.731159 # ok 407 get_value.0.35
7186 11:04:41.737399 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7187 11:04:41.740895 # not ok 408 name.0.35
7188 11:04:41.744186 # ok 409 write_default.0.35
7189 11:04:41.744669 # ok 410 write_valid.0.35
7190 11:04:41.747308 # ok 411 write_invalid.0.35
7191 11:04:41.751091 # ok 412 event_missing.0.35
7192 11:04:41.754268 # ok 413 event_spurious.0.35
7193 11:04:41.754780 # ok 414 get_value.0.34
7194 11:04:41.760906 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7195 11:04:41.763620 # not ok 415 name.0.34
7196 11:04:41.766772 # ok 416 write_default.0.34
7197 11:04:41.767156 # ok 417 write_valid.0.34
7198 11:04:41.770515 # ok 418 write_invalid.0.34
7199 11:04:41.773817 # ok 419 event_missing.0.34
7200 11:04:41.777034 # ok 420 event_spurious.0.34
7201 11:04:41.777297 # ok 421 get_value.0.33
7202 11:04:41.783779 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7203 11:04:41.786710 # not ok 422 name.0.33
7204 11:04:41.790384 # ok 423 write_default.0.33
7205 11:04:41.791054 # ok 424 write_valid.0.33
7206 11:04:41.793318 # ok 425 write_invalid.0.33
7207 11:04:41.796454 # ok 426 event_missing.0.33
7208 11:04:41.799776 # ok 427 event_spurious.0.33
7209 11:04:41.800162 # ok 428 get_value.0.32
7210 11:04:41.806863 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7211 11:04:41.809945 # not ok 429 name.0.32
7212 11:04:41.813101 # ok 430 write_default.0.32
7213 11:04:41.816538 # ok 431 write_valid.0.32
7214 11:04:41.816925 # ok 432 write_invalid.0.32
7215 11:04:41.820251 # ok 433 event_missing.0.32
7216 11:04:41.823314 # ok 434 event_spurious.0.32
7217 11:04:41.826703 # ok 435 get_value.0.31
7218 11:04:41.832835 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7219 11:04:41.833220 # not ok 436 name.0.31
7220 11:04:41.836054 # ok 437 write_default.0.31
7221 11:04:41.839329 # ok 438 write_valid.0.31
7222 11:04:41.842946 # ok 439 write_invalid.0.31
7223 11:04:41.843334 # ok 440 event_missing.0.31
7224 11:04:41.846058 # ok 441 event_spurious.0.31
7225 11:04:41.849791 # ok 442 get_value.0.30
7226 11:04:41.855945 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7227 11:04:41.859076 # not ok 443 name.0.30
7228 11:04:41.859499 # ok 444 write_default.0.30
7229 11:04:41.862387 # ok 445 write_valid.0.30
7230 11:04:41.865986 # ok 446 write_invalid.0.30
7231 11:04:41.869494 # ok 447 event_missing.0.30
7232 11:04:41.869877 # ok 448 event_spurious.0.30
7233 11:04:41.872696 # ok 449 get_value.0.29
7234 11:04:41.876030 # ok 450 name.0.29
7235 11:04:41.879342 # ok 451 write_default.0.29
7236 11:04:41.879730 # ok 452 write_valid.0.29
7237 11:04:41.882732 # ok 453 write_invalid.0.29
7238 11:04:41.886070 # ok 454 event_missing.0.29
7239 11:04:41.889180 # ok 455 event_spurious.0.29
7240 11:04:41.889647 # ok 456 get_value.0.28
7241 11:04:41.891990 # ok 457 name.0.28
7242 11:04:41.895346 # ok 458 write_default.0.28
7243 11:04:41.895735 # ok 459 write_valid.0.28
7244 11:04:41.898769 # ok 460 write_invalid.0.28
7245 11:04:41.901924 # ok 461 event_missing.0.28
7246 11:04:41.905031 # ok 462 event_spurious.0.28
7247 11:04:41.908237 # ok 463 get_value.0.27
7248 11:04:41.908335 # ok 464 name.0.27
7249 11:04:41.911535 # ok 465 write_default.0.27
7250 11:04:41.914823 # ok 466 write_valid.0.27
7251 11:04:41.914892 # ok 467 write_invalid.0.27
7252 11:04:41.918068 # ok 468 event_missing.0.27
7253 11:04:41.921237 # ok 469 event_spurious.0.27
7254 11:04:41.924576 # ok 470 get_value.0.26
7255 11:04:41.924638 # ok 471 name.0.26
7256 11:04:41.927843 # ok 472 write_default.0.26
7257 11:04:41.931362 # ok 473 write_valid.0.26
7258 11:04:41.931437 # ok 474 write_invalid.0.26
7259 11:04:41.934390 # ok 475 event_missing.0.26
7260 11:04:41.937678 # ok 476 event_spurious.0.26
7261 11:04:41.940907 # ok 477 get_value.0.25
7262 11:04:41.940982 # ok 478 name.0.25
7263 11:04:41.944141 # ok 479 write_default.0.25
7264 11:04:41.947913 # ok 480 write_valid.0.25
7265 11:04:41.947994 # ok 481 write_invalid.0.25
7266 11:04:41.951062 # ok 482 event_missing.0.25
7267 11:04:41.954479 # ok 483 event_spurious.0.25
7268 11:04:41.957879 # ok 484 get_value.0.24
7269 11:04:41.957972 # ok 485 name.0.24
7270 11:04:41.961193 # ok 486 write_default.0.24
7271 11:04:41.964080 # ok 487 write_valid.0.24
7272 11:04:41.964195 # ok 488 write_invalid.0.24
7273 11:04:41.967495 # ok 489 event_missing.0.24
7274 11:04:41.970720 # ok 490 event_spurious.0.24
7275 11:04:41.974284 # ok 491 get_value.0.23
7276 11:04:41.974431 # ok 492 name.0.23
7277 11:04:41.977354 # ok 493 write_default.0.23
7278 11:04:41.980718 # ok 494 write_valid.0.23
7279 11:04:41.980925 # ok 495 write_invalid.0.23
7280 11:04:41.984107 # ok 496 event_missing.0.23
7281 11:04:41.987622 # ok 497 event_spurious.0.23
7282 11:04:41.990780 # ok 498 get_value.0.22
7283 11:04:41.991001 # ok 499 name.0.22
7284 11:04:41.994059 # ok 500 write_default.0.22
7285 11:04:41.997618 # ok 501 write_valid.0.22
7286 11:04:41.997912 # ok 502 write_invalid.0.22
7287 11:04:42.000674 # ok 503 event_missing.0.22
7288 11:04:42.003761 # ok 504 event_spurious.0.22
7289 11:04:42.007319 # ok 505 get_value.0.21
7290 11:04:42.014150 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7291 11:04:42.014543 # not ok 506 name.0.21
7292 11:04:42.017431 # ok 507 write_default.0.21
7293 11:04:42.020321 # ok 508 write_valid.0.21
7294 11:04:42.020787 # ok 509 write_invalid.0.21
7295 11:04:42.024167 # ok 510 event_missing.0.21
7296 11:04:42.027262 # ok 511 event_spurious.0.21
7297 11:04:42.030329 # ok 512 get_value.0.20
7298 11:04:42.037395 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7299 11:04:42.037914 # not ok 513 name.0.20
7300 11:04:42.040530 # ok 514 write_default.0.20
7301 11:04:42.043965 # ok 515 write_valid.0.20
7302 11:04:42.047213 # ok 516 write_invalid.0.20
7303 11:04:42.047722 # ok 517 event_missing.0.20
7304 11:04:42.050705 # ok 518 event_spurious.0.20
7305 11:04:42.054036 # ok 519 get_value.0.19
7306 11:04:42.060360 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7307 11:04:42.060830 # not ok 520 name.0.19
7308 11:04:42.064032 # ok 521 write_default.0.19
7309 11:04:42.067090 # ok 522 write_valid.0.19
7310 11:04:42.069862 # ok 523 write_invalid.0.19
7311 11:04:42.070323 # ok 524 event_missing.0.19
7312 11:04:42.073804 # ok 525 event_spurious.0.19
7313 11:04:42.076725 # ok 526 get_value.0.18
7314 11:04:42.082853 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7315 11:04:42.083286 # not ok 527 name.0.18
7316 11:04:42.086329 # ok 528 write_default.0.18
7317 11:04:42.090101 # ok 529 write_valid.0.18
7318 11:04:42.093395 # ok 530 write_invalid.0.18
7319 11:04:42.096604 # ok 531 event_missing.0.18
7320 11:04:42.097031 # ok 532 event_spurious.0.18
7321 11:04:42.100037 # ok 533 get_value.0.17
7322 11:04:42.106052 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7323 11:04:42.110001 # not ok 534 name.0.17
7324 11:04:42.110568 # ok 535 write_default.0.17
7325 11:04:42.112779 # ok 536 write_valid.0.17
7326 11:04:42.116060 # ok 537 write_invalid.0.17
7327 11:04:42.119028 # ok 538 event_missing.0.17
7328 11:04:42.122857 # ok 539 event_spurious.0.17
7329 11:04:42.123361 # ok 540 get_value.0.16
7330 11:04:42.128885 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7331 11:04:42.132460 # not ok 541 name.0.16
7332 11:04:42.135797 # ok 542 write_default.0.16
7333 11:04:42.136222 # ok 543 write_valid.0.16
7334 11:04:42.139283 # ok 544 write_invalid.0.16
7335 11:04:42.142892 # ok 545 event_missing.0.16
7336 11:04:42.145923 # ok 546 event_spurious.0.16
7337 11:04:42.146476 # ok 547 get_value.0.15
7338 11:04:42.151709 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7339 11:04:42.155660 # not ok 548 name.0.15
7340 11:04:42.158824 # ok 549 write_default.0.15
7341 11:04:42.159332 # ok 550 write_valid.0.15
7342 11:04:42.162390 # ok 551 write_invalid.0.15
7343 11:04:42.165652 # ok 552 event_missing.0.15
7344 11:04:42.168575 # ok 553 event_spurious.0.15
7345 11:04:42.172012 # ok 554 get_value.0.14
7346 11:04:42.174873 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7347 11:04:42.178612 # not ok 555 name.0.14
7348 11:04:42.182042 # ok 556 write_default.0.14
7349 11:04:42.185237 # ok 557 write_valid.0.14
7350 11:04:42.185736 # ok 558 write_invalid.0.14
7351 11:04:42.188531 # ok 559 event_missing.0.14
7352 11:04:42.191416 # ok 560 event_spurious.0.14
7353 11:04:42.194779 # ok 561 get_value.0.13
7354 11:04:42.201307 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7355 11:04:42.201832 # not ok 562 name.0.13
7356 11:04:42.205310 # ok 563 write_default.0.13
7357 11:04:42.208172 # ok 564 write_valid.0.13
7358 11:04:42.210960 # ok 565 write_invalid.0.13
7359 11:04:42.211390 # ok 566 event_missing.0.13
7360 11:04:42.214776 # ok 567 event_spurious.0.13
7361 11:04:42.218196 # ok 568 get_value.0.12
7362 11:04:42.224249 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7363 11:04:42.224759 # not ok 569 name.0.12
7364 11:04:42.227559 # ok 570 write_default.0.12
7365 11:04:42.230682 # ok 571 write_valid.0.12
7366 11:04:42.234359 # ok 572 write_invalid.0.12
7367 11:04:42.237387 # ok 573 event_missing.0.12
7368 11:04:42.237816 # ok 574 event_spurious.0.12
7369 11:04:42.240629 # ok 575 get_value.0.11
7370 11:04:42.247586 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7371 11:04:42.250992 # not ok 576 name.0.11
7372 11:04:42.251492 # ok 577 write_default.0.11
7373 11:04:42.253871 # ok 578 write_valid.0.11
7374 11:04:42.257771 # ok 579 write_invalid.0.11
7375 11:04:42.260678 # ok 580 event_missing.0.11
7376 11:04:42.261185 # ok 581 event_spurious.0.11
7377 11:04:42.264381 # ok 582 get_value.0.10
7378 11:04:42.270727 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7379 11:04:42.273939 # not ok 583 name.0.10
7380 11:04:42.274464 # ok 584 write_default.0.10
7381 11:04:42.277352 # ok 585 write_valid.0.10
7382 11:04:42.280268 # ok 586 write_invalid.0.10
7383 11:04:42.283513 # ok 587 event_missing.0.10
7384 11:04:42.287159 # ok 588 event_spurious.0.10
7385 11:04:42.287584 # ok 589 get_value.0.9
7386 11:04:42.293469 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7387 11:04:42.296931 # not ok 590 name.0.9
7388 11:04:42.297404 # ok 591 write_default.0.9
7389 11:04:42.299809 # ok 592 write_valid.0.9
7390 11:04:42.303412 # ok 593 write_invalid.0.9
7391 11:04:42.306411 # ok 594 event_missing.0.9
7392 11:04:42.310372 # ok 595 event_spurious.0.9
7393 11:04:42.310797 # ok 596 get_value.0.8
7394 11:04:42.317021 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7395 11:04:42.320038 # not ok 597 name.0.8
7396 11:04:42.320466 # ok 598 write_default.0.8
7397 11:04:42.322870 # ok 599 write_valid.0.8
7398 11:04:42.326590 # ok 600 write_invalid.0.8
7399 11:04:42.329610 # ok 601 event_missing.0.8
7400 11:04:42.330070 # ok 602 event_spurious.0.8
7401 11:04:42.332891 # ok 603 get_value.0.7
7402 11:04:42.340092 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7403 11:04:42.343063 # not ok 604 name.0.7
7404 11:04:42.343489 # ok 605 write_default.0.7
7405 11:04:42.346002 # ok 606 write_valid.0.7
7406 11:04:42.349775 # ok 607 write_invalid.0.7
7407 11:04:42.352752 # ok 608 event_missing.0.7
7408 11:04:42.353140 # ok 609 event_spurious.0.7
7409 11:04:42.356052 # ok 610 get_value.0.6
7410 11:04:42.362925 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7411 11:04:42.365909 # not ok 611 name.0.6
7412 11:04:42.366459 # ok 612 write_default.0.6
7413 11:04:42.369610 # ok 613 write_valid.0.6
7414 11:04:42.372418 # ok 614 write_invalid.0.6
7415 11:04:42.376059 # ok 615 event_missing.0.6
7416 11:04:42.376565 # ok 616 event_spurious.0.6
7417 11:04:42.379095 # ok 617 get_value.0.5
7418 11:04:42.382751 # ok 618 name.0.5
7419 11:04:42.383256 # ok 619 write_default.0.5
7420 11:04:42.385883 # # No event generated for MTKAIF_DMIC
7421 11:04:42.388843 # # No event generated for MTKAIF_DMIC
7422 11:04:42.392075 # ok 620 write_valid.0.5
7423 11:04:42.395547 # ok 621 write_invalid.0.5
7424 11:04:42.398809 # not ok 622 event_missing.0.5
7425 11:04:42.401951 # ok 623 event_spurious.0.5
7426 11:04:42.402422 # ok 624 get_value.0.4
7427 11:04:42.405075 # ok 625 name.0.4
7428 11:04:42.408436 # ok 626 write_default.0.4
7429 11:04:42.411598 # # No event generated for I2S5_HD_Mux
7430 11:04:42.415331 # # No event generated for I2S5_HD_Mux
7431 11:04:42.415752 # ok 627 write_valid.0.4
7432 11:04:42.418097 # ok 628 write_invalid.0.4
7433 11:04:42.422067 # not ok 629 event_missing.0.4
7434 11:04:42.425138 # ok 630 event_spurious.0.4
7435 11:04:42.425517 # ok 631 get_value.0.3
7436 11:04:42.428697 # ok 632 name.0.3
7437 11:04:42.431061 # ok 633 write_default.0.3
7438 11:04:42.434653 # # No event generated for I2S3_HD_Mux
7439 11:04:42.437653 # # No event generated for I2S3_HD_Mux
7440 11:04:42.437726 # ok 634 write_valid.0.3
7441 11:04:42.441124 # ok 635 write_invalid.0.3
7442 11:04:42.443928 # not ok 636 event_missing.0.3
7443 11:04:42.447498 # ok 637 event_spurious.0.3
7444 11:04:42.447571 # ok 638 get_value.0.2
7445 11:04:42.450709 # ok 639 name.0.2
7446 11:04:42.454331 # ok 640 write_default.0.2
7447 11:04:42.457199 # # No event generated for I2S2_HD_Mux
7448 11:04:42.460755 # # No event generated for I2S2_HD_Mux
7449 11:04:42.460847 # ok 641 write_valid.0.2
7450 11:04:42.463998 # ok 642 write_invalid.0.2
7451 11:04:42.467013 # not ok 643 event_missing.0.2
7452 11:04:42.471235 # ok 644 event_spurious.0.2
7453 11:04:42.474211 # ok 645 get_value.0.1
7454 11:04:42.474587 # ok 646 name.0.1
7455 11:04:42.477190 # ok 647 write_default.0.1
7456 11:04:42.480857 # # No event generated for I2S1_HD_Mux
7457 11:04:42.484143 # # No event generated for I2S1_HD_Mux
7458 11:04:42.487441 # ok 648 write_valid.0.1
7459 11:04:42.487815 # ok 649 write_invalid.0.1
7460 11:04:42.490758 # not ok 650 event_missing.0.1
7461 11:04:42.494143 # ok 651 event_spurious.0.1
7462 11:04:42.497310 # ok 652 get_value.0.0
7463 11:04:42.497687 # ok 653 name.0.0
7464 11:04:42.500455 # ok 654 write_default.0.0
7465 11:04:42.504108 # # No event generated for I2S0_HD_Mux
7466 11:04:42.507142 # # No event generated for I2S0_HD_Mux
7467 11:04:42.510313 # ok 655 write_valid.0.0
7468 11:04:42.510691 # ok 656 write_invalid.0.0
7469 11:04:42.513577 # not ok 657 event_missing.0.0
7470 11:04:42.516781 # ok 658 event_spurious.0.0
7471 11:04:42.523483 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7472 11:04:42.526915 ok 1 selftests: alsa: mixer-test
7473 11:04:44.156206 alsa_mixer-test_get_value_0_93 pass
7474 11:04:44.159614 alsa_mixer-test_name_0_93 pass
7475 11:04:44.162277 alsa_mixer-test_write_default_0_93 pass
7476 11:04:44.165861 alsa_mixer-test_write_valid_0_93 pass
7477 11:04:44.171894 alsa_mixer-test_write_invalid_0_93 pass
7478 11:04:44.175722 alsa_mixer-test_event_missing_0_93 pass
7479 11:04:44.178395 alsa_mixer-test_event_spurious_0_93 pass
7480 11:04:44.181747 alsa_mixer-test_get_value_0_92 pass
7481 11:04:44.185329 alsa_mixer-test_name_0_92 pass
7482 11:04:44.188620 alsa_mixer-test_write_default_0_92 pass
7483 11:04:44.191836 alsa_mixer-test_write_valid_0_92 pass
7484 11:04:44.195089 alsa_mixer-test_write_invalid_0_92 pass
7485 11:04:44.198383 alsa_mixer-test_event_missing_0_92 pass
7486 11:04:44.201863 alsa_mixer-test_event_spurious_0_92 pass
7487 11:04:44.204727 alsa_mixer-test_get_value_0_91 pass
7488 11:04:44.207934 alsa_mixer-test_name_0_91 pass
7489 11:04:44.211715 alsa_mixer-test_write_default_0_91 pass
7490 11:04:44.214530 alsa_mixer-test_write_valid_0_91 pass
7491 11:04:44.217909 alsa_mixer-test_write_invalid_0_91 pass
7492 11:04:44.221441 alsa_mixer-test_event_missing_0_91 pass
7493 11:04:44.227910 alsa_mixer-test_event_spurious_0_91 pass
7494 11:04:44.232019 alsa_mixer-test_get_value_0_90 pass
7495 11:04:44.232527 alsa_mixer-test_name_0_90 pass
7496 11:04:44.237995 alsa_mixer-test_write_default_0_90 pass
7497 11:04:44.241360 alsa_mixer-test_write_valid_0_90 pass
7498 11:04:44.244339 alsa_mixer-test_write_invalid_0_90 pass
7499 11:04:44.247490 alsa_mixer-test_event_missing_0_90 pass
7500 11:04:44.251144 alsa_mixer-test_event_spurious_0_90 pass
7501 11:04:44.253944 alsa_mixer-test_get_value_0_89 pass
7502 11:04:44.257231 alsa_mixer-test_name_0_89 pass
7503 11:04:44.260795 alsa_mixer-test_write_default_0_89 pass
7504 11:04:44.264272 alsa_mixer-test_write_valid_0_89 pass
7505 11:04:44.267736 alsa_mixer-test_write_invalid_0_89 pass
7506 11:04:44.270652 alsa_mixer-test_event_missing_0_89 pass
7507 11:04:44.274208 alsa_mixer-test_event_spurious_0_89 pass
7508 11:04:44.277441 alsa_mixer-test_get_value_0_88 pass
7509 11:04:44.280827 alsa_mixer-test_name_0_88 pass
7510 11:04:44.283736 alsa_mixer-test_write_default_0_88 pass
7511 11:04:44.286894 alsa_mixer-test_write_valid_0_88 fail
7512 11:04:44.293379 alsa_mixer-test_write_invalid_0_88 pass
7513 11:04:44.297006 alsa_mixer-test_event_missing_0_88 pass
7514 11:04:44.299822 alsa_mixer-test_event_spurious_0_88 fail
7515 11:04:44.303367 alsa_mixer-test_get_value_0_87 pass
7516 11:04:44.306497 alsa_mixer-test_name_0_87 pass
7517 11:04:44.310347 alsa_mixer-test_write_default_0_87 pass
7518 11:04:44.313481 alsa_mixer-test_write_valid_0_87 pass
7519 11:04:44.316514 alsa_mixer-test_write_invalid_0_87 pass
7520 11:04:44.320081 alsa_mixer-test_event_missing_0_87 pass
7521 11:04:44.323112 alsa_mixer-test_event_spurious_0_87 pass
7522 11:04:44.326655 alsa_mixer-test_get_value_0_86 pass
7523 11:04:44.329768 alsa_mixer-test_name_0_86 pass
7524 11:04:44.333180 alsa_mixer-test_write_default_0_86 pass
7525 11:04:44.336258 alsa_mixer-test_write_valid_0_86 fail
7526 11:04:44.343266 alsa_mixer-test_write_invalid_0_86 pass
7527 11:04:44.346357 alsa_mixer-test_event_missing_0_86 pass
7528 11:04:44.349681 alsa_mixer-test_event_spurious_0_86 pass
7529 11:04:44.353094 alsa_mixer-test_get_value_0_85 pass
7530 11:04:44.356300 alsa_mixer-test_name_0_85 pass
7531 11:04:44.359876 alsa_mixer-test_write_default_0_85 pass
7532 11:04:44.362899 alsa_mixer-test_write_valid_0_85 fail
7533 11:04:44.366679 alsa_mixer-test_write_invalid_0_85 pass
7534 11:04:44.369609 alsa_mixer-test_event_missing_0_85 pass
7535 11:04:44.372800 alsa_mixer-test_event_spurious_0_85 pass
7536 11:04:44.376072 alsa_mixer-test_get_value_0_84 pass
7537 11:04:44.379551 alsa_mixer-test_name_0_84 pass
7538 11:04:44.382551 alsa_mixer-test_write_default_0_84 pass
7539 11:04:44.386257 alsa_mixer-test_write_valid_0_84 pass
7540 11:04:44.389042 alsa_mixer-test_write_invalid_0_84 pass
7541 11:04:44.396128 alsa_mixer-test_event_missing_0_84 pass
7542 11:04:44.398972 alsa_mixer-test_event_spurious_0_84 pass
7543 11:04:44.402494 alsa_mixer-test_get_value_0_83 pass
7544 11:04:44.405271 alsa_mixer-test_name_0_83 pass
7545 11:04:44.409184 alsa_mixer-test_write_default_0_83 pass
7546 11:04:44.412323 alsa_mixer-test_write_valid_0_83 pass
7547 11:04:44.415595 alsa_mixer-test_write_invalid_0_83 pass
7548 11:04:44.418645 alsa_mixer-test_event_missing_0_83 pass
7549 11:04:44.421922 alsa_mixer-test_event_spurious_0_83 pass
7550 11:04:44.425173 alsa_mixer-test_get_value_0_82 pass
7551 11:04:44.429163 alsa_mixer-test_name_0_82 pass
7552 11:04:44.431789 alsa_mixer-test_write_default_0_82 skip
7553 11:04:44.434819 alsa_mixer-test_write_valid_0_82 skip
7554 11:04:44.438536 alsa_mixer-test_write_invalid_0_82 skip
7555 11:04:44.445009 alsa_mixer-test_event_missing_0_82 pass
7556 11:04:44.448285 alsa_mixer-test_event_spurious_0_82 pass
7557 11:04:44.451555 alsa_mixer-test_get_value_0_81 pass
7558 11:04:44.454862 alsa_mixer-test_name_0_81 pass
7559 11:04:44.458042 alsa_mixer-test_write_default_0_81 pass
7560 11:04:44.461134 alsa_mixer-test_write_valid_0_81 pass
7561 11:04:44.464446 alsa_mixer-test_write_invalid_0_81 fail
7562 11:04:44.468033 alsa_mixer-test_event_missing_0_81 fail
7563 11:04:44.471424 alsa_mixer-test_event_spurious_0_81 pass
7564 11:04:44.474577 alsa_mixer-test_get_value_0_80 pass
7565 11:04:44.478243 alsa_mixer-test_name_0_80 pass
7566 11:04:44.481096 alsa_mixer-test_write_default_0_80 pass
7567 11:04:44.485222 alsa_mixer-test_write_valid_0_80 pass
7568 11:04:44.487439 alsa_mixer-test_write_invalid_0_80 pass
7569 11:04:44.491673 alsa_mixer-test_event_missing_0_80 pass
7570 11:04:44.497967 alsa_mixer-test_event_spurious_0_80 pass
7571 11:04:44.500924 alsa_mixer-test_get_value_0_79 fail
7572 11:04:44.501434 alsa_mixer-test_name_0_79 pass
7573 11:04:44.507550 alsa_mixer-test_write_default_0_79 fail
7574 11:04:44.511265 alsa_mixer-test_write_valid_0_79 fail
7575 11:04:44.514760 alsa_mixer-test_write_invalid_0_79 fail
7576 11:04:44.517579 alsa_mixer-test_event_missing_0_79 pass
7577 11:04:44.520835 alsa_mixer-test_event_spurious_0_79 pass
7578 11:04:44.524132 alsa_mixer-test_get_value_0_78 fail
7579 11:04:44.527621 alsa_mixer-test_name_0_78 pass
7580 11:04:44.530681 alsa_mixer-test_write_default_0_78 fail
7581 11:04:44.533478 alsa_mixer-test_write_valid_0_78 fail
7582 11:04:44.536801 alsa_mixer-test_write_invalid_0_78 fail
7583 11:04:44.540078 alsa_mixer-test_event_missing_0_78 pass
7584 11:04:44.547362 alsa_mixer-test_event_spurious_0_78 pass
7585 11:04:44.550374 alsa_mixer-test_get_value_0_77 fail
7586 11:04:44.550798 alsa_mixer-test_name_0_77 pass
7587 11:04:44.556779 alsa_mixer-test_write_default_0_77 fail
7588 11:04:44.560075 alsa_mixer-test_write_valid_0_77 fail
7589 11:04:44.563290 alsa_mixer-test_write_invalid_0_77 fail
7590 11:04:44.566413 alsa_mixer-test_event_missing_0_77 pass
7591 11:04:44.570252 alsa_mixer-test_event_spurious_0_77 pass
7592 11:04:44.573285 alsa_mixer-test_get_value_0_76 pass
7593 11:04:44.576673 alsa_mixer-test_name_0_76 fail
7594 11:04:44.579753 alsa_mixer-test_write_default_0_76 pass
7595 11:04:44.583153 alsa_mixer-test_write_valid_0_76 pass
7596 11:04:44.586233 alsa_mixer-test_write_invalid_0_76 pass
7597 11:04:44.589604 alsa_mixer-test_event_missing_0_76 pass
7598 11:04:44.592718 alsa_mixer-test_event_spurious_0_76 pass
7599 11:04:44.596066 alsa_mixer-test_get_value_0_75 pass
7600 11:04:44.599354 alsa_mixer-test_name_0_75 fail
7601 11:04:44.602916 alsa_mixer-test_write_default_0_75 pass
7602 11:04:44.609757 alsa_mixer-test_write_valid_0_75 pass
7603 11:04:44.612987 alsa_mixer-test_write_invalid_0_75 pass
7604 11:04:44.616209 alsa_mixer-test_event_missing_0_75 pass
7605 11:04:44.618819 alsa_mixer-test_event_spurious_0_75 pass
7606 11:04:44.622731 alsa_mixer-test_get_value_0_74 pass
7607 11:04:44.625742 alsa_mixer-test_name_0_74 fail
7608 11:04:44.629443 alsa_mixer-test_write_default_0_74 pass
7609 11:04:44.632520 alsa_mixer-test_write_valid_0_74 pass
7610 11:04:44.636216 alsa_mixer-test_write_invalid_0_74 pass
7611 11:04:44.639118 alsa_mixer-test_event_missing_0_74 pass
7612 11:04:44.642555 alsa_mixer-test_event_spurious_0_74 pass
7613 11:04:44.645450 alsa_mixer-test_get_value_0_73 pass
7614 11:04:44.649582 alsa_mixer-test_name_0_73 fail
7615 11:04:44.652674 alsa_mixer-test_write_default_0_73 pass
7616 11:04:44.655402 alsa_mixer-test_write_valid_0_73 pass
7617 11:04:44.661992 alsa_mixer-test_write_invalid_0_73 pass
7618 11:04:44.665000 alsa_mixer-test_event_missing_0_73 pass
7619 11:04:44.668655 alsa_mixer-test_event_spurious_0_73 pass
7620 11:04:44.672168 alsa_mixer-test_get_value_0_72 pass
7621 11:04:44.675408 alsa_mixer-test_name_0_72 fail
7622 11:04:44.678389 alsa_mixer-test_write_default_0_72 pass
7623 11:04:44.681497 alsa_mixer-test_write_valid_0_72 pass
7624 11:04:44.685026 alsa_mixer-test_write_invalid_0_72 pass
7625 11:04:44.688240 alsa_mixer-test_event_missing_0_72 pass
7626 11:04:44.691499 alsa_mixer-test_event_spurious_0_72 pass
7627 11:04:44.694647 alsa_mixer-test_get_value_0_71 pass
7628 11:04:44.697979 alsa_mixer-test_name_0_71 fail
7629 11:04:44.700954 alsa_mixer-test_write_default_0_71 pass
7630 11:04:44.704289 alsa_mixer-test_write_valid_0_71 pass
7631 11:04:44.710929 alsa_mixer-test_write_invalid_0_71 pass
7632 11:04:44.713994 alsa_mixer-test_event_missing_0_71 pass
7633 11:04:44.717482 alsa_mixer-test_event_spurious_0_71 pass
7634 11:04:44.720390 alsa_mixer-test_get_value_0_70 pass
7635 11:04:44.723640 alsa_mixer-test_name_0_70 fail
7636 11:04:44.726984 alsa_mixer-test_write_default_0_70 pass
7637 11:04:44.730340 alsa_mixer-test_write_valid_0_70 pass
7638 11:04:44.733396 alsa_mixer-test_write_invalid_0_70 pass
7639 11:04:44.737194 alsa_mixer-test_event_missing_0_70 pass
7640 11:04:44.740288 alsa_mixer-test_event_spurious_0_70 pass
7641 11:04:44.743811 alsa_mixer-test_get_value_0_69 pass
7642 11:04:44.746971 alsa_mixer-test_name_0_69 fail
7643 11:04:44.750161 alsa_mixer-test_write_default_0_69 pass
7644 11:04:44.753656 alsa_mixer-test_write_valid_0_69 pass
7645 11:04:44.760018 alsa_mixer-test_write_invalid_0_69 pass
7646 11:04:44.763289 alsa_mixer-test_event_missing_0_69 pass
7647 11:04:44.766998 alsa_mixer-test_event_spurious_0_69 pass
7648 11:04:44.770026 alsa_mixer-test_get_value_0_68 pass
7649 11:04:44.773539 alsa_mixer-test_name_0_68 fail
7650 11:04:44.776635 alsa_mixer-test_write_default_0_68 pass
7651 11:04:44.780105 alsa_mixer-test_write_valid_0_68 pass
7652 11:04:44.783393 alsa_mixer-test_write_invalid_0_68 pass
7653 11:04:44.786606 alsa_mixer-test_event_missing_0_68 pass
7654 11:04:44.790097 alsa_mixer-test_event_spurious_0_68 pass
7655 11:04:44.793072 alsa_mixer-test_get_value_0_67 pass
7656 11:04:44.796436 alsa_mixer-test_name_0_67 fail
7657 11:04:44.799758 alsa_mixer-test_write_default_0_67 pass
7658 11:04:44.803433 alsa_mixer-test_write_valid_0_67 pass
7659 11:04:44.806850 alsa_mixer-test_write_invalid_0_67 pass
7660 11:04:44.810091 alsa_mixer-test_event_missing_0_67 pass
7661 11:04:44.816375 alsa_mixer-test_event_spurious_0_67 pass
7662 11:04:44.819715 alsa_mixer-test_get_value_0_66 pass
7663 11:04:44.822828 alsa_mixer-test_name_0_66 fail
7664 11:04:44.826438 alsa_mixer-test_write_default_0_66 pass
7665 11:04:44.829959 alsa_mixer-test_write_valid_0_66 pass
7666 11:04:44.833138 alsa_mixer-test_write_invalid_0_66 pass
7667 11:04:44.836264 alsa_mixer-test_event_missing_0_66 pass
7668 11:04:44.839385 alsa_mixer-test_event_spurious_0_66 pass
7669 11:04:44.842935 alsa_mixer-test_get_value_0_65 pass
7670 11:04:44.846257 alsa_mixer-test_name_0_65 fail
7671 11:04:44.849028 alsa_mixer-test_write_default_0_65 pass
7672 11:04:44.852964 alsa_mixer-test_write_valid_0_65 pass
7673 11:04:44.856503 alsa_mixer-test_write_invalid_0_65 pass
7674 11:04:44.859582 alsa_mixer-test_event_missing_0_65 pass
7675 11:04:44.862756 alsa_mixer-test_event_spurious_0_65 pass
7676 11:04:44.865655 alsa_mixer-test_get_value_0_64 pass
7677 11:04:44.869466 alsa_mixer-test_name_0_64 fail
7678 11:04:44.872775 alsa_mixer-test_write_default_0_64 pass
7679 11:04:44.876006 alsa_mixer-test_write_valid_0_64 pass
7680 11:04:44.879621 alsa_mixer-test_write_invalid_0_64 pass
7681 11:04:44.885356 alsa_mixer-test_event_missing_0_64 pass
7682 11:04:44.888954 alsa_mixer-test_event_spurious_0_64 pass
7683 11:04:44.891894 alsa_mixer-test_get_value_0_63 pass
7684 11:04:44.895565 alsa_mixer-test_name_0_63 fail
7685 11:04:44.899073 alsa_mixer-test_write_default_0_63 pass
7686 11:04:44.902084 alsa_mixer-test_write_valid_0_63 pass
7687 11:04:44.905608 alsa_mixer-test_write_invalid_0_63 pass
7688 11:04:44.908470 alsa_mixer-test_event_missing_0_63 pass
7689 11:04:44.915086 alsa_mixer-test_event_spurious_0_63 pass
7690 11:04:44.918422 alsa_mixer-test_get_value_0_62 pass
7691 11:04:44.921609 alsa_mixer-test_name_0_62 fail
7692 11:04:44.924930 alsa_mixer-test_write_default_0_62 pass
7693 11:04:44.928702 alsa_mixer-test_write_valid_0_62 pass
7694 11:04:44.932039 alsa_mixer-test_write_invalid_0_62 pass
7695 11:04:44.934963 alsa_mixer-test_event_missing_0_62 pass
7696 11:04:44.938640 alsa_mixer-test_event_spurious_0_62 pass
7697 11:04:44.941408 alsa_mixer-test_get_value_0_61 pass
7698 11:04:44.945285 alsa_mixer-test_name_0_61 fail
7699 11:04:44.948410 alsa_mixer-test_write_default_0_61 pass
7700 11:04:44.951621 alsa_mixer-test_write_valid_0_61 pass
7701 11:04:44.954705 alsa_mixer-test_write_invalid_0_61 pass
7702 11:04:44.958047 alsa_mixer-test_event_missing_0_61 pass
7703 11:04:44.961315 alsa_mixer-test_event_spurious_0_61 pass
7704 11:04:44.964633 alsa_mixer-test_get_value_0_60 pass
7705 11:04:44.967859 alsa_mixer-test_name_0_60 fail
7706 11:04:44.971169 alsa_mixer-test_write_default_0_60 pass
7707 11:04:44.974600 alsa_mixer-test_write_valid_0_60 pass
7708 11:04:44.977922 alsa_mixer-test_write_invalid_0_60 pass
7709 11:04:44.981477 alsa_mixer-test_event_missing_0_60 pass
7710 11:04:44.984470 alsa_mixer-test_event_spurious_0_60 pass
7711 11:04:44.987768 alsa_mixer-test_get_value_0_59 pass
7712 11:04:44.990959 alsa_mixer-test_name_0_59 fail
7713 11:04:44.994469 alsa_mixer-test_write_default_0_59 pass
7714 11:04:44.997616 alsa_mixer-test_write_valid_0_59 pass
7715 11:04:45.000844 alsa_mixer-test_write_invalid_0_59 pass
7716 11:04:45.004602 alsa_mixer-test_event_missing_0_59 pass
7717 11:04:45.010791 alsa_mixer-test_event_spurious_0_59 pass
7718 11:04:45.014190 alsa_mixer-test_get_value_0_58 pass
7719 11:04:45.014583 alsa_mixer-test_name_0_58 fail
7720 11:04:45.017451 alsa_mixer-test_write_default_0_58 pass
7721 11:04:45.021113 alsa_mixer-test_write_valid_0_58 pass
7722 11:04:45.027332 alsa_mixer-test_write_invalid_0_58 pass
7723 11:04:45.030680 alsa_mixer-test_event_missing_0_58 pass
7724 11:04:45.033844 alsa_mixer-test_event_spurious_0_58 pass
7725 11:04:45.036922 alsa_mixer-test_get_value_0_57 pass
7726 11:04:45.040553 alsa_mixer-test_name_0_57 fail
7727 11:04:45.043895 alsa_mixer-test_write_default_0_57 pass
7728 11:04:45.047639 alsa_mixer-test_write_valid_0_57 pass
7729 11:04:45.050341 alsa_mixer-test_write_invalid_0_57 pass
7730 11:04:45.053913 alsa_mixer-test_event_missing_0_57 pass
7731 11:04:45.056782 alsa_mixer-test_event_spurious_0_57 pass
7732 11:04:45.060652 alsa_mixer-test_get_value_0_56 pass
7733 11:04:45.063491 alsa_mixer-test_name_0_56 fail
7734 11:04:45.066888 alsa_mixer-test_write_default_0_56 pass
7735 11:04:45.070119 alsa_mixer-test_write_valid_0_56 pass
7736 11:04:45.073431 alsa_mixer-test_write_invalid_0_56 pass
7737 11:04:45.076573 alsa_mixer-test_event_missing_0_56 pass
7738 11:04:45.079810 alsa_mixer-test_event_spurious_0_56 pass
7739 11:04:45.083300 alsa_mixer-test_get_value_0_55 pass
7740 11:04:45.086040 alsa_mixer-test_name_0_55 fail
7741 11:04:45.089910 alsa_mixer-test_write_default_0_55 pass
7742 11:04:45.093263 alsa_mixer-test_write_valid_0_55 pass
7743 11:04:45.096732 alsa_mixer-test_write_invalid_0_55 pass
7744 11:04:45.099533 alsa_mixer-test_event_missing_0_55 pass
7745 11:04:45.102730 alsa_mixer-test_event_spurious_0_55 pass
7746 11:04:45.105852 alsa_mixer-test_get_value_0_54 pass
7747 11:04:45.109197 alsa_mixer-test_name_0_54 fail
7748 11:04:45.112553 alsa_mixer-test_write_default_0_54 pass
7749 11:04:45.115926 alsa_mixer-test_write_valid_0_54 pass
7750 11:04:45.119112 alsa_mixer-test_write_invalid_0_54 pass
7751 11:04:45.122246 alsa_mixer-test_event_missing_0_54 pass
7752 11:04:45.128864 alsa_mixer-test_event_spurious_0_54 pass
7753 11:04:45.128958 alsa_mixer-test_get_value_0_53 pass
7754 11:04:45.132511 alsa_mixer-test_name_0_53 fail
7755 11:04:45.136098 alsa_mixer-test_write_default_0_53 pass
7756 11:04:45.138665 alsa_mixer-test_write_valid_0_53 pass
7757 11:04:45.145477 alsa_mixer-test_write_invalid_0_53 pass
7758 11:04:45.148981 alsa_mixer-test_event_missing_0_53 pass
7759 11:04:45.152103 alsa_mixer-test_event_spurious_0_53 pass
7760 11:04:45.155264 alsa_mixer-test_get_value_0_52 pass
7761 11:04:45.159314 alsa_mixer-test_name_0_52 fail
7762 11:04:45.162337 alsa_mixer-test_write_default_0_52 pass
7763 11:04:45.165569 alsa_mixer-test_write_valid_0_52 pass
7764 11:04:45.168575 alsa_mixer-test_write_invalid_0_52 pass
7765 11:04:45.172076 alsa_mixer-test_event_missing_0_52 pass
7766 11:04:45.175505 alsa_mixer-test_event_spurious_0_52 pass
7767 11:04:45.178401 alsa_mixer-test_get_value_0_51 pass
7768 11:04:45.181580 alsa_mixer-test_name_0_51 fail
7769 11:04:45.185169 alsa_mixer-test_write_default_0_51 pass
7770 11:04:45.188333 alsa_mixer-test_write_valid_0_51 pass
7771 11:04:45.191965 alsa_mixer-test_write_invalid_0_51 pass
7772 11:04:45.195020 alsa_mixer-test_event_missing_0_51 pass
7773 11:04:45.198590 alsa_mixer-test_event_spurious_0_51 pass
7774 11:04:45.201577 alsa_mixer-test_get_value_0_50 pass
7775 11:04:45.204950 alsa_mixer-test_name_0_50 fail
7776 11:04:45.208666 alsa_mixer-test_write_default_0_50 pass
7777 11:04:45.211623 alsa_mixer-test_write_valid_0_50 pass
7778 11:04:45.214897 alsa_mixer-test_write_invalid_0_50 pass
7779 11:04:45.218242 alsa_mixer-test_event_missing_0_50 pass
7780 11:04:45.221383 alsa_mixer-test_event_spurious_0_50 pass
7781 11:04:45.224796 alsa_mixer-test_get_value_0_49 pass
7782 11:04:45.228181 alsa_mixer-test_name_0_49 fail
7783 11:04:45.231318 alsa_mixer-test_write_default_0_49 pass
7784 11:04:45.234912 alsa_mixer-test_write_valid_0_49 pass
7785 11:04:45.237934 alsa_mixer-test_write_invalid_0_49 pass
7786 11:04:45.241447 alsa_mixer-test_event_missing_0_49 pass
7787 11:04:45.244910 alsa_mixer-test_event_spurious_0_49 pass
7788 11:04:45.248039 alsa_mixer-test_get_value_0_48 pass
7789 11:04:45.251236 alsa_mixer-test_name_0_48 fail
7790 11:04:45.254486 alsa_mixer-test_write_default_0_48 pass
7791 11:04:45.257605 alsa_mixer-test_write_valid_0_48 pass
7792 11:04:45.260702 alsa_mixer-test_write_invalid_0_48 pass
7793 11:04:45.267452 alsa_mixer-test_event_missing_0_48 pass
7794 11:04:45.270956 alsa_mixer-test_event_spurious_0_48 pass
7795 11:04:45.273980 alsa_mixer-test_get_value_0_47 pass
7796 11:04:45.274080 alsa_mixer-test_name_0_47 fail
7797 11:04:45.280982 alsa_mixer-test_write_default_0_47 pass
7798 11:04:45.284278 alsa_mixer-test_write_valid_0_47 pass
7799 11:04:45.287460 alsa_mixer-test_write_invalid_0_47 pass
7800 11:04:45.291226 alsa_mixer-test_event_missing_0_47 pass
7801 11:04:45.294122 alsa_mixer-test_event_spurious_0_47 pass
7802 11:04:45.297255 alsa_mixer-test_get_value_0_46 pass
7803 11:04:45.300729 alsa_mixer-test_name_0_46 fail
7804 11:04:45.304161 alsa_mixer-test_write_default_0_46 pass
7805 11:04:45.307052 alsa_mixer-test_write_valid_0_46 pass
7806 11:04:45.310634 alsa_mixer-test_write_invalid_0_46 pass
7807 11:04:45.313681 alsa_mixer-test_event_missing_0_46 pass
7808 11:04:45.317495 alsa_mixer-test_event_spurious_0_46 pass
7809 11:04:45.320855 alsa_mixer-test_get_value_0_45 pass
7810 11:04:45.324164 alsa_mixer-test_name_0_45 fail
7811 11:04:45.327535 alsa_mixer-test_write_default_0_45 pass
7812 11:04:45.330857 alsa_mixer-test_write_valid_0_45 pass
7813 11:04:45.333501 alsa_mixer-test_write_invalid_0_45 pass
7814 11:04:45.336647 alsa_mixer-test_event_missing_0_45 pass
7815 11:04:45.340537 alsa_mixer-test_event_spurious_0_45 pass
7816 11:04:45.343401 alsa_mixer-test_get_value_0_44 pass
7817 11:04:45.346791 alsa_mixer-test_name_0_44 fail
7818 11:04:45.349984 alsa_mixer-test_write_default_0_44 pass
7819 11:04:45.356475 alsa_mixer-test_write_valid_0_44 pass
7820 11:04:45.360028 alsa_mixer-test_write_invalid_0_44 pass
7821 11:04:45.363222 alsa_mixer-test_event_missing_0_44 pass
7822 11:04:45.366712 alsa_mixer-test_event_spurious_0_44 pass
7823 11:04:45.370467 alsa_mixer-test_get_value_0_43 pass
7824 11:04:45.373519 alsa_mixer-test_name_0_43 fail
7825 11:04:45.376885 alsa_mixer-test_write_default_0_43 pass
7826 11:04:45.379995 alsa_mixer-test_write_valid_0_43 pass
7827 11:04:45.383311 alsa_mixer-test_write_invalid_0_43 pass
7828 11:04:45.386531 alsa_mixer-test_event_missing_0_43 pass
7829 11:04:45.389805 alsa_mixer-test_event_spurious_0_43 pass
7830 11:04:45.393172 alsa_mixer-test_get_value_0_42 pass
7831 11:04:45.396389 alsa_mixer-test_name_0_42 fail
7832 11:04:45.399596 alsa_mixer-test_write_default_0_42 pass
7833 11:04:45.403136 alsa_mixer-test_write_valid_0_42 pass
7834 11:04:45.409471 alsa_mixer-test_write_invalid_0_42 pass
7835 11:04:45.412492 alsa_mixer-test_event_missing_0_42 pass
7836 11:04:45.416084 alsa_mixer-test_event_spurious_0_42 pass
7837 11:04:45.418945 alsa_mixer-test_get_value_0_41 pass
7838 11:04:45.422392 alsa_mixer-test_name_0_41 fail
7839 11:04:45.425719 alsa_mixer-test_write_default_0_41 pass
7840 11:04:45.429188 alsa_mixer-test_write_valid_0_41 pass
7841 11:04:45.432181 alsa_mixer-test_write_invalid_0_41 pass
7842 11:04:45.435515 alsa_mixer-test_event_missing_0_41 pass
7843 11:04:45.439082 alsa_mixer-test_event_spurious_0_41 pass
7844 11:04:45.442341 alsa_mixer-test_get_value_0_40 pass
7845 11:04:45.445472 alsa_mixer-test_name_0_40 fail
7846 11:04:45.449135 alsa_mixer-test_write_default_0_40 pass
7847 11:04:45.452376 alsa_mixer-test_write_valid_0_40 pass
7848 11:04:45.455466 alsa_mixer-test_write_invalid_0_40 pass
7849 11:04:45.458947 alsa_mixer-test_event_missing_0_40 pass
7850 11:04:45.462127 alsa_mixer-test_event_spurious_0_40 pass
7851 11:04:45.464974 alsa_mixer-test_get_value_0_39 pass
7852 11:04:45.468788 alsa_mixer-test_name_0_39 fail
7853 11:04:45.471638 alsa_mixer-test_write_default_0_39 pass
7854 11:04:45.475027 alsa_mixer-test_write_valid_0_39 pass
7855 11:04:45.478505 alsa_mixer-test_write_invalid_0_39 pass
7856 11:04:45.485010 alsa_mixer-test_event_missing_0_39 pass
7857 11:04:45.488651 alsa_mixer-test_event_spurious_0_39 pass
7858 11:04:45.492069 alsa_mixer-test_get_value_0_38 pass
7859 11:04:45.492468 alsa_mixer-test_name_0_38 fail
7860 11:04:45.498350 alsa_mixer-test_write_default_0_38 pass
7861 11:04:45.501386 alsa_mixer-test_write_valid_0_38 pass
7862 11:04:45.504722 alsa_mixer-test_write_invalid_0_38 pass
7863 11:04:45.508070 alsa_mixer-test_event_missing_0_38 pass
7864 11:04:45.511265 alsa_mixer-test_event_spurious_0_38 pass
7865 11:04:45.514138 alsa_mixer-test_get_value_0_37 pass
7866 11:04:45.518230 alsa_mixer-test_name_0_37 fail
7867 11:04:45.521240 alsa_mixer-test_write_default_0_37 pass
7868 11:04:45.524408 alsa_mixer-test_write_valid_0_37 pass
7869 11:04:45.527666 alsa_mixer-test_write_invalid_0_37 pass
7870 11:04:45.530987 alsa_mixer-test_event_missing_0_37 pass
7871 11:04:45.534344 alsa_mixer-test_event_spurious_0_37 pass
7872 11:04:45.537150 alsa_mixer-test_get_value_0_36 pass
7873 11:04:45.540742 alsa_mixer-test_name_0_36 fail
7874 11:04:45.544148 alsa_mixer-test_write_default_0_36 pass
7875 11:04:45.547289 alsa_mixer-test_write_valid_0_36 pass
7876 11:04:45.550549 alsa_mixer-test_write_invalid_0_36 pass
7877 11:04:45.553959 alsa_mixer-test_event_missing_0_36 pass
7878 11:04:45.560692 alsa_mixer-test_event_spurious_0_36 pass
7879 11:04:45.563686 alsa_mixer-test_get_value_0_35 pass
7880 11:04:45.563915 alsa_mixer-test_name_0_35 fail
7881 11:04:45.570793 alsa_mixer-test_write_default_0_35 pass
7882 11:04:45.573827 alsa_mixer-test_write_valid_0_35 pass
7883 11:04:45.577299 alsa_mixer-test_write_invalid_0_35 pass
7884 11:04:45.580708 alsa_mixer-test_event_missing_0_35 pass
7885 11:04:45.583847 alsa_mixer-test_event_spurious_0_35 pass
7886 11:04:45.587073 alsa_mixer-test_get_value_0_34 pass
7887 11:04:45.590353 alsa_mixer-test_name_0_34 fail
7888 11:04:45.593719 alsa_mixer-test_write_default_0_34 pass
7889 11:04:45.597066 alsa_mixer-test_write_valid_0_34 pass
7890 11:04:45.600276 alsa_mixer-test_write_invalid_0_34 pass
7891 11:04:45.603526 alsa_mixer-test_event_missing_0_34 pass
7892 11:04:45.606733 alsa_mixer-test_event_spurious_0_34 pass
7893 11:04:45.613337 alsa_mixer-test_get_value_0_33 pass
7894 11:04:45.613724 alsa_mixer-test_name_0_33 fail
7895 11:04:45.619884 alsa_mixer-test_write_default_0_33 pass
7896 11:04:45.623290 alsa_mixer-test_write_valid_0_33 pass
7897 11:04:45.626263 alsa_mixer-test_write_invalid_0_33 pass
7898 11:04:45.629533 alsa_mixer-test_event_missing_0_33 pass
7899 11:04:45.633024 alsa_mixer-test_event_spurious_0_33 pass
7900 11:04:45.636316 alsa_mixer-test_get_value_0_32 pass
7901 11:04:45.639612 alsa_mixer-test_name_0_32 fail
7902 11:04:45.642993 alsa_mixer-test_write_default_0_32 pass
7903 11:04:45.646263 alsa_mixer-test_write_valid_0_32 pass
7904 11:04:45.649406 alsa_mixer-test_write_invalid_0_32 pass
7905 11:04:45.652659 alsa_mixer-test_event_missing_0_32 pass
7906 11:04:45.655922 alsa_mixer-test_event_spurious_0_32 pass
7907 11:04:45.659206 alsa_mixer-test_get_value_0_31 pass
7908 11:04:45.662837 alsa_mixer-test_name_0_31 fail
7909 11:04:45.665575 alsa_mixer-test_write_default_0_31 pass
7910 11:04:45.672501 alsa_mixer-test_write_valid_0_31 pass
7911 11:04:45.675731 alsa_mixer-test_write_invalid_0_31 pass
7912 11:04:45.679079 alsa_mixer-test_event_missing_0_31 pass
7913 11:04:45.681994 alsa_mixer-test_event_spurious_0_31 pass
7914 11:04:45.685476 alsa_mixer-test_get_value_0_30 pass
7915 11:04:45.689028 alsa_mixer-test_name_0_30 fail
7916 11:04:45.692395 alsa_mixer-test_write_default_0_30 pass
7917 11:04:45.695433 alsa_mixer-test_write_valid_0_30 pass
7918 11:04:45.698543 alsa_mixer-test_write_invalid_0_30 pass
7919 11:04:45.702479 alsa_mixer-test_event_missing_0_30 pass
7920 11:04:45.705632 alsa_mixer-test_event_spurious_0_30 pass
7921 11:04:45.708396 alsa_mixer-test_get_value_0_29 pass
7922 11:04:45.712998 alsa_mixer-test_name_0_29 pass
7923 11:04:45.716369 alsa_mixer-test_write_default_0_29 pass
7924 11:04:45.718509 alsa_mixer-test_write_valid_0_29 pass
7925 11:04:45.724908 alsa_mixer-test_write_invalid_0_29 pass
7926 11:04:45.728832 alsa_mixer-test_event_missing_0_29 pass
7927 11:04:45.731721 alsa_mixer-test_event_spurious_0_29 pass
7928 11:04:45.735136 alsa_mixer-test_get_value_0_28 pass
7929 11:04:45.738422 alsa_mixer-test_name_0_28 pass
7930 11:04:45.741618 alsa_mixer-test_write_default_0_28 pass
7931 11:04:45.744930 alsa_mixer-test_write_valid_0_28 pass
7932 11:04:45.747554 alsa_mixer-test_write_invalid_0_28 pass
7933 11:04:45.751006 alsa_mixer-test_event_missing_0_28 pass
7934 11:04:45.754343 alsa_mixer-test_event_spurious_0_28 pass
7935 11:04:45.757552 alsa_mixer-test_get_value_0_27 pass
7936 11:04:45.760894 alsa_mixer-test_name_0_27 pass
7937 11:04:45.764380 alsa_mixer-test_write_default_0_27 pass
7938 11:04:45.767799 alsa_mixer-test_write_valid_0_27 pass
7939 11:04:45.774434 alsa_mixer-test_write_invalid_0_27 pass
7940 11:04:45.777685 alsa_mixer-test_event_missing_0_27 pass
7941 11:04:45.780971 alsa_mixer-test_event_spurious_0_27 pass
7942 11:04:45.784237 alsa_mixer-test_get_value_0_26 pass
7943 11:04:45.787788 alsa_mixer-test_name_0_26 pass
7944 11:04:45.790513 alsa_mixer-test_write_default_0_26 pass
7945 11:04:45.794087 alsa_mixer-test_write_valid_0_26 pass
7946 11:04:45.797046 alsa_mixer-test_write_invalid_0_26 pass
7947 11:04:45.801234 alsa_mixer-test_event_missing_0_26 pass
7948 11:04:45.803928 alsa_mixer-test_event_spurious_0_26 pass
7949 11:04:45.806926 alsa_mixer-test_get_value_0_25 pass
7950 11:04:45.810647 alsa_mixer-test_name_0_25 pass
7951 11:04:45.813917 alsa_mixer-test_write_default_0_25 pass
7952 11:04:45.817620 alsa_mixer-test_write_valid_0_25 pass
7953 11:04:45.820525 alsa_mixer-test_write_invalid_0_25 pass
7954 11:04:45.826695 alsa_mixer-test_event_missing_0_25 pass
7955 11:04:45.830188 alsa_mixer-test_event_spurious_0_25 pass
7956 11:04:45.834180 alsa_mixer-test_get_value_0_24 pass
7957 11:04:45.837578 alsa_mixer-test_name_0_24 pass
7958 11:04:45.840434 alsa_mixer-test_write_default_0_24 pass
7959 11:04:45.842892 alsa_mixer-test_write_valid_0_24 pass
7960 11:04:45.846290 alsa_mixer-test_write_invalid_0_24 pass
7961 11:04:45.849612 alsa_mixer-test_event_missing_0_24 pass
7962 11:04:45.852899 alsa_mixer-test_event_spurious_0_24 pass
7963 11:04:45.855899 alsa_mixer-test_get_value_0_23 pass
7964 11:04:45.859708 alsa_mixer-test_name_0_23 pass
7965 11:04:45.862891 alsa_mixer-test_write_default_0_23 pass
7966 11:04:45.866404 alsa_mixer-test_write_valid_0_23 pass
7967 11:04:45.869763 alsa_mixer-test_write_invalid_0_23 pass
7968 11:04:45.875855 alsa_mixer-test_event_missing_0_23 pass
7969 11:04:45.878892 alsa_mixer-test_event_spurious_0_23 pass
7970 11:04:45.882675 alsa_mixer-test_get_value_0_22 pass
7971 11:04:45.885359 alsa_mixer-test_name_0_22 pass
7972 11:04:45.888623 alsa_mixer-test_write_default_0_22 pass
7973 11:04:45.892460 alsa_mixer-test_write_valid_0_22 pass
7974 11:04:45.895644 alsa_mixer-test_write_invalid_0_22 pass
7975 11:04:45.898948 alsa_mixer-test_event_missing_0_22 pass
7976 11:04:45.902397 alsa_mixer-test_event_spurious_0_22 pass
7977 11:04:45.905307 alsa_mixer-test_get_value_0_21 pass
7978 11:04:45.908473 alsa_mixer-test_name_0_21 fail
7979 11:04:45.911906 alsa_mixer-test_write_default_0_21 pass
7980 11:04:45.915165 alsa_mixer-test_write_valid_0_21 pass
7981 11:04:45.918526 alsa_mixer-test_write_invalid_0_21 pass
7982 11:04:45.921720 alsa_mixer-test_event_missing_0_21 pass
7983 11:04:45.928300 alsa_mixer-test_event_spurious_0_21 pass
7984 11:04:45.931613 alsa_mixer-test_get_value_0_20 pass
7985 11:04:45.931707 alsa_mixer-test_name_0_20 fail
7986 11:04:45.938413 alsa_mixer-test_write_default_0_20 pass
7987 11:04:45.941088 alsa_mixer-test_write_valid_0_20 pass
7988 11:04:45.944742 alsa_mixer-test_write_invalid_0_20 pass
7989 11:04:45.948235 alsa_mixer-test_event_missing_0_20 pass
7990 11:04:45.951908 alsa_mixer-test_event_spurious_0_20 pass
7991 11:04:45.954471 alsa_mixer-test_get_value_0_19 pass
7992 11:04:45.958237 alsa_mixer-test_name_0_19 fail
7993 11:04:45.961084 alsa_mixer-test_write_default_0_19 pass
7994 11:04:45.964523 alsa_mixer-test_write_valid_0_19 pass
7995 11:04:45.967777 alsa_mixer-test_write_invalid_0_19 pass
7996 11:04:45.970789 alsa_mixer-test_event_missing_0_19 pass
7997 11:04:45.974231 alsa_mixer-test_event_spurious_0_19 pass
7998 11:04:45.977213 alsa_mixer-test_get_value_0_18 pass
7999 11:04:45.980658 alsa_mixer-test_name_0_18 fail
8000 11:04:45.984273 alsa_mixer-test_write_default_0_18 pass
8001 11:04:45.988045 alsa_mixer-test_write_valid_0_18 pass
8002 11:04:45.993855 alsa_mixer-test_write_invalid_0_18 pass
8003 11:04:45.997366 alsa_mixer-test_event_missing_0_18 pass
8004 11:04:46.000851 alsa_mixer-test_event_spurious_0_18 pass
8005 11:04:46.003679 alsa_mixer-test_get_value_0_17 pass
8006 11:04:46.007172 alsa_mixer-test_name_0_17 fail
8007 11:04:46.010232 alsa_mixer-test_write_default_0_17 pass
8008 11:04:46.013581 alsa_mixer-test_write_valid_0_17 pass
8009 11:04:46.017453 alsa_mixer-test_write_invalid_0_17 pass
8010 11:04:46.020405 alsa_mixer-test_event_missing_0_17 pass
8011 11:04:46.023545 alsa_mixer-test_event_spurious_0_17 pass
8012 11:04:46.026745 alsa_mixer-test_get_value_0_16 pass
8013 11:04:46.030043 alsa_mixer-test_name_0_16 fail
8014 11:04:46.033243 alsa_mixer-test_write_default_0_16 pass
8015 11:04:46.036973 alsa_mixer-test_write_valid_0_16 pass
8016 11:04:46.043772 alsa_mixer-test_write_invalid_0_16 pass
8017 11:04:46.046524 alsa_mixer-test_event_missing_0_16 pass
8018 11:04:46.049783 alsa_mixer-test_event_spurious_0_16 pass
8019 11:04:46.052873 alsa_mixer-test_get_value_0_15 pass
8020 11:04:46.056464 alsa_mixer-test_name_0_15 fail
8021 11:04:46.059857 alsa_mixer-test_write_default_0_15 pass
8022 11:04:46.063034 alsa_mixer-test_write_valid_0_15 pass
8023 11:04:46.066269 alsa_mixer-test_write_invalid_0_15 pass
8024 11:04:46.069499 alsa_mixer-test_event_missing_0_15 pass
8025 11:04:46.072559 alsa_mixer-test_event_spurious_0_15 pass
8026 11:04:46.076052 alsa_mixer-test_get_value_0_14 pass
8027 11:04:46.079470 alsa_mixer-test_name_0_14 fail
8028 11:04:46.083128 alsa_mixer-test_write_default_0_14 pass
8029 11:04:46.085889 alsa_mixer-test_write_valid_0_14 pass
8030 11:04:46.089409 alsa_mixer-test_write_invalid_0_14 pass
8031 11:04:46.092960 alsa_mixer-test_event_missing_0_14 pass
8032 11:04:46.095729 alsa_mixer-test_event_spurious_0_14 pass
8033 11:04:46.099826 alsa_mixer-test_get_value_0_13 pass
8034 11:04:46.102520 alsa_mixer-test_name_0_13 fail
8035 11:04:46.105830 alsa_mixer-test_write_default_0_13 pass
8036 11:04:46.109244 alsa_mixer-test_write_valid_0_13 pass
8037 11:04:46.112617 alsa_mixer-test_write_invalid_0_13 pass
8038 11:04:46.115689 alsa_mixer-test_event_missing_0_13 pass
8039 11:04:46.122317 alsa_mixer-test_event_spurious_0_13 pass
8040 11:04:46.125798 alsa_mixer-test_get_value_0_12 pass
8041 11:04:46.125894 alsa_mixer-test_name_0_12 fail
8042 11:04:46.129484 alsa_mixer-test_write_default_0_12 pass
8043 11:04:46.132398 alsa_mixer-test_write_valid_0_12 pass
8044 11:04:46.139094 alsa_mixer-test_write_invalid_0_12 pass
8045 11:04:46.142101 alsa_mixer-test_event_missing_0_12 pass
8046 11:04:46.145238 alsa_mixer-test_event_spurious_0_12 pass
8047 11:04:46.148904 alsa_mixer-test_get_value_0_11 pass
8048 11:04:46.151910 alsa_mixer-test_name_0_11 fail
8049 11:04:46.155559 alsa_mixer-test_write_default_0_11 pass
8050 11:04:46.158322 alsa_mixer-test_write_valid_0_11 pass
8051 11:04:46.161931 alsa_mixer-test_write_invalid_0_11 pass
8052 11:04:46.165353 alsa_mixer-test_event_missing_0_11 pass
8053 11:04:46.168477 alsa_mixer-test_event_spurious_0_11 pass
8054 11:04:46.171884 alsa_mixer-test_get_value_0_10 pass
8055 11:04:46.175276 alsa_mixer-test_name_0_10 fail
8056 11:04:46.178285 alsa_mixer-test_write_default_0_10 pass
8057 11:04:46.181861 alsa_mixer-test_write_valid_0_10 pass
8058 11:04:46.184782 alsa_mixer-test_write_invalid_0_10 pass
8059 11:04:46.191927 alsa_mixer-test_event_missing_0_10 pass
8060 11:04:46.194694 alsa_mixer-test_event_spurious_0_10 pass
8061 11:04:46.198214 alsa_mixer-test_get_value_0_9 pass
8062 11:04:46.201500 alsa_mixer-test_name_0_9 fail
8063 11:04:46.204911 alsa_mixer-test_write_default_0_9 pass
8064 11:04:46.208246 alsa_mixer-test_write_valid_0_9 pass
8065 11:04:46.211841 alsa_mixer-test_write_invalid_0_9 pass
8066 11:04:46.214727 alsa_mixer-test_event_missing_0_9 pass
8067 11:04:46.217715 alsa_mixer-test_event_spurious_0_9 pass
8068 11:04:46.221535 alsa_mixer-test_get_value_0_8 pass
8069 11:04:46.224436 alsa_mixer-test_name_0_8 fail
8070 11:04:46.227642 alsa_mixer-test_write_default_0_8 pass
8071 11:04:46.231193 alsa_mixer-test_write_valid_0_8 pass
8072 11:04:46.234284 alsa_mixer-test_write_invalid_0_8 pass
8073 11:04:46.237570 alsa_mixer-test_event_missing_0_8 pass
8074 11:04:46.240863 alsa_mixer-test_event_spurious_0_8 pass
8075 11:04:46.244146 alsa_mixer-test_get_value_0_7 pass
8076 11:04:46.247583 alsa_mixer-test_name_0_7 fail
8077 11:04:46.250603 alsa_mixer-test_write_default_0_7 pass
8078 11:04:46.254405 alsa_mixer-test_write_valid_0_7 pass
8079 11:04:46.257666 alsa_mixer-test_write_invalid_0_7 pass
8080 11:04:46.260797 alsa_mixer-test_event_missing_0_7 pass
8081 11:04:46.263824 alsa_mixer-test_event_spurious_0_7 pass
8082 11:04:46.267430 alsa_mixer-test_get_value_0_6 pass
8083 11:04:46.270964 alsa_mixer-test_name_0_6 fail
8084 11:04:46.274507 alsa_mixer-test_write_default_0_6 pass
8085 11:04:46.277671 alsa_mixer-test_write_valid_0_6 pass
8086 11:04:46.280659 alsa_mixer-test_write_invalid_0_6 pass
8087 11:04:46.284435 alsa_mixer-test_event_missing_0_6 pass
8088 11:04:46.287265 alsa_mixer-test_event_spurious_0_6 pass
8089 11:04:46.290192 alsa_mixer-test_get_value_0_5 pass
8090 11:04:46.293987 alsa_mixer-test_name_0_5 pass
8091 11:04:46.297103 alsa_mixer-test_write_default_0_5 pass
8092 11:04:46.300492 alsa_mixer-test_write_valid_0_5 pass
8093 11:04:46.303449 alsa_mixer-test_write_invalid_0_5 pass
8094 11:04:46.307006 alsa_mixer-test_event_missing_0_5 fail
8095 11:04:46.310396 alsa_mixer-test_event_spurious_0_5 pass
8096 11:04:46.313375 alsa_mixer-test_get_value_0_4 pass
8097 11:04:46.317058 alsa_mixer-test_name_0_4 pass
8098 11:04:46.320134 alsa_mixer-test_write_default_0_4 pass
8099 11:04:46.323465 alsa_mixer-test_write_valid_0_4 pass
8100 11:04:46.326953 alsa_mixer-test_write_invalid_0_4 pass
8101 11:04:46.329793 alsa_mixer-test_event_missing_0_4 fail
8102 11:04:46.333371 alsa_mixer-test_event_spurious_0_4 pass
8103 11:04:46.336510 alsa_mixer-test_get_value_0_3 pass
8104 11:04:46.339646 alsa_mixer-test_name_0_3 pass
8105 11:04:46.343222 alsa_mixer-test_write_default_0_3 pass
8106 11:04:46.346259 alsa_mixer-test_write_valid_0_3 pass
8107 11:04:46.349535 alsa_mixer-test_write_invalid_0_3 pass
8108 11:04:46.353342 alsa_mixer-test_event_missing_0_3 fail
8109 11:04:46.356830 alsa_mixer-test_event_spurious_0_3 pass
8110 11:04:46.359959 alsa_mixer-test_get_value_0_2 pass
8111 11:04:46.362969 alsa_mixer-test_name_0_2 pass
8112 11:04:46.366146 alsa_mixer-test_write_default_0_2 pass
8113 11:04:46.369921 alsa_mixer-test_write_valid_0_2 pass
8114 11:04:46.373354 alsa_mixer-test_write_invalid_0_2 pass
8115 11:04:46.376283 alsa_mixer-test_event_missing_0_2 fail
8116 11:04:46.379896 alsa_mixer-test_event_spurious_0_2 pass
8117 11:04:46.383322 alsa_mixer-test_get_value_0_1 pass
8118 11:04:46.386558 alsa_mixer-test_name_0_1 pass
8119 11:04:46.390045 alsa_mixer-test_write_default_0_1 pass
8120 11:04:46.392628 alsa_mixer-test_write_valid_0_1 pass
8121 11:04:46.396065 alsa_mixer-test_write_invalid_0_1 pass
8122 11:04:46.399663 alsa_mixer-test_event_missing_0_1 fail
8123 11:04:46.402950 alsa_mixer-test_event_spurious_0_1 pass
8124 11:04:46.406047 alsa_mixer-test_get_value_0_0 pass
8125 11:04:46.409299 alsa_mixer-test_name_0_0 pass
8126 11:04:46.412618 alsa_mixer-test_write_default_0_0 pass
8127 11:04:46.416109 alsa_mixer-test_write_valid_0_0 pass
8128 11:04:46.419119 alsa_mixer-test_write_invalid_0_0 pass
8129 11:04:46.422616 alsa_mixer-test_event_missing_0_0 fail
8130 11:04:46.425620 alsa_mixer-test_event_spurious_0_0 pass
8131 11:04:46.429692 alsa_mixer-test pass
8132 11:04:46.432619 + ../../utils/send-to-lava.sh ./output/result.txt
8133 11:04:46.438966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
8134 11:04:46.439739 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
8136 11:04:46.445601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
8137 11:04:46.446225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
8139 11:04:46.452319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
8140 11:04:46.452946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
8142 11:04:46.458735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
8143 11:04:46.459372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
8145 11:04:46.468415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
8146 11:04:46.469041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
8148 11:04:46.530912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
8149 11:04:46.531573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
8151 11:04:46.591130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
8152 11:04:46.591781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
8154 11:04:46.644413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
8155 11:04:46.644668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
8157 11:04:46.694863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
8158 11:04:46.695137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
8160 11:04:46.737592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8161 11:04:46.738046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8163 11:04:46.797557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8164 11:04:46.798223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8166 11:04:46.856631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8167 11:04:46.856925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8169 11:04:46.906701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8170 11:04:46.906950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8172 11:04:46.954631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8173 11:04:46.954919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8175 11:04:47.002311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8176 11:04:47.002564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8178 11:04:47.060018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8179 11:04:47.060293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8181 11:04:47.105354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8182 11:04:47.105634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8184 11:04:47.155761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8185 11:04:47.156040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8187 11:04:47.202595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8188 11:04:47.202897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8190 11:04:47.260102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8191 11:04:47.260379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8193 11:04:47.308388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8194 11:04:47.308668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8196 11:04:47.367529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8197 11:04:47.367845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8199 11:04:47.419265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8200 11:04:47.419537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8202 11:04:47.461908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8203 11:04:47.462208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8205 11:04:47.518777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8206 11:04:47.519033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8208 11:04:47.568290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8209 11:04:47.568548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8211 11:04:47.624001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8212 11:04:47.624256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8214 11:04:47.676836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8215 11:04:47.677090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8217 11:04:47.725980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8218 11:04:47.726277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8220 11:04:47.771780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8221 11:04:47.772036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8223 11:04:47.816305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8224 11:04:47.816557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8226 11:04:47.863544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8227 11:04:47.863800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8229 11:04:47.909224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8230 11:04:47.909488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8232 11:04:47.961031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8233 11:04:47.961305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8235 11:04:48.009744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8236 11:04:48.010059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8238 11:04:48.057824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8239 11:04:48.058104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8241 11:04:48.104428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8242 11:04:48.104729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8244 11:04:48.146681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8245 11:04:48.146969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8247 11:04:48.196674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8248 11:04:48.197008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8250 11:04:48.241700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8251 11:04:48.241989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8253 11:04:48.283303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8254 11:04:48.283596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8256 11:04:48.325956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8257 11:04:48.326267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8259 11:04:48.363385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8260 11:04:48.363632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8262 11:04:48.409414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8263 11:04:48.409671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8265 11:04:48.452302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8266 11:04:48.452604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8268 11:04:48.499313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8269 11:04:48.499586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8271 11:04:48.543729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8272 11:04:48.543982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8274 11:04:48.589588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8275 11:04:48.589860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8277 11:04:48.629861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8278 11:04:48.630128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8280 11:04:48.674122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8281 11:04:48.674374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8283 11:04:48.711233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8284 11:04:48.711505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8286 11:04:48.750766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8287 11:04:48.751040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8289 11:04:48.796534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8290 11:04:48.796804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8292 11:04:48.832516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8293 11:04:48.832787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8295 11:04:48.871040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8296 11:04:48.871331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8298 11:04:48.909996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8299 11:04:48.910255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8301 11:04:48.952051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8302 11:04:48.952342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8304 11:04:48.970607 <6>[ 37.995529] vaux18: disabling
8305 11:04:48.974904 <6>[ 37.998933] vio28: disabling
8306 11:04:48.995942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8307 11:04:48.996566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8309 11:04:49.042206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8310 11:04:49.042840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8312 11:04:49.093763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8313 11:04:49.094449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8315 11:04:49.149147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8316 11:04:49.149808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8318 11:04:49.204693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8319 11:04:49.205365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8321 11:04:49.262899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8322 11:04:49.263186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8324 11:04:49.306554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8325 11:04:49.306847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8327 11:04:49.355977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8328 11:04:49.356257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8330 11:04:49.397060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8332 11:04:49.400118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8333 11:04:49.440661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8334 11:04:49.440911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8336 11:04:49.482183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8337 11:04:49.482427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8339 11:04:49.519572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8340 11:04:49.519831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8342 11:04:49.559018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8343 11:04:49.559270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8345 11:04:49.596295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8346 11:04:49.596546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8348 11:04:49.635002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8349 11:04:49.635259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8351 11:04:49.669797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8352 11:04:49.670044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8354 11:04:49.716262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8355 11:04:49.716514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8357 11:04:49.757324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8358 11:04:49.757578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8360 11:04:49.803460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8361 11:04:49.803710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8363 11:04:49.850222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8364 11:04:49.850490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8366 11:04:49.893167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8367 11:04:49.893425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8369 11:04:49.932181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8370 11:04:49.932460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8372 11:04:49.965754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8373 11:04:49.966029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8375 11:04:50.007227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8376 11:04:50.007475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8378 11:04:50.047417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8379 11:04:50.047666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8381 11:04:50.084472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8382 11:04:50.084737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8384 11:04:50.126476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8385 11:04:50.126723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8387 11:04:50.168917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8388 11:04:50.169196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8390 11:04:50.211659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8391 11:04:50.211916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8393 11:04:50.253056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8394 11:04:50.253310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8396 11:04:50.296751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8397 11:04:50.296998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8399 11:04:50.342668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8400 11:04:50.342946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8402 11:04:50.388197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8403 11:04:50.388465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8405 11:04:50.431962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8406 11:04:50.432208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8408 11:04:50.473869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8409 11:04:50.474120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8411 11:04:50.517784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8412 11:04:50.518024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8414 11:04:50.559915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8415 11:04:50.560163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8417 11:04:50.609666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8418 11:04:50.609918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8420 11:04:50.653428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8421 11:04:50.653681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8423 11:04:50.699973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8424 11:04:50.700257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8426 11:04:50.746758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8427 11:04:50.747008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8429 11:04:50.791210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8430 11:04:50.791465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8432 11:04:50.833708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8433 11:04:50.833979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8435 11:04:50.872863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8436 11:04:50.873111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8438 11:04:50.924103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8439 11:04:50.924362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8441 11:04:50.969224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8442 11:04:50.969483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8444 11:04:51.010616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8445 11:04:51.010869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8447 11:04:51.055561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8448 11:04:51.055824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8450 11:04:51.097388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8451 11:04:51.097637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8453 11:04:51.134449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8454 11:04:51.134696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8456 11:04:51.172429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8457 11:04:51.172689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8459 11:04:51.216794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8460 11:04:51.217046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8462 11:04:51.259467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8463 11:04:51.259719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8465 11:04:51.300977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8466 11:04:51.301250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8468 11:04:51.337437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8469 11:04:51.337706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8471 11:04:51.379878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8472 11:04:51.380136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8474 11:04:51.418068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8475 11:04:51.418342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8477 11:04:51.452902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8478 11:04:51.453160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8480 11:04:51.493205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8481 11:04:51.493460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8483 11:04:51.532592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8484 11:04:51.532872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8486 11:04:51.571171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8487 11:04:51.571437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8489 11:04:51.610889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8490 11:04:51.611140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8492 11:04:51.648541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8493 11:04:51.648798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8495 11:04:51.690776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8496 11:04:51.691022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8498 11:04:51.725871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8499 11:04:51.726142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8501 11:04:51.766031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8502 11:04:51.766297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8504 11:04:51.807161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8505 11:04:51.807408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8507 11:04:51.845657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8508 11:04:51.845905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8510 11:04:51.885839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8511 11:04:51.886089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8513 11:04:51.926928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8514 11:04:51.927181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8516 11:04:51.968747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8517 11:04:51.969188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8519 11:04:52.012072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8520 11:04:52.012441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8522 11:04:52.057409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8523 11:04:52.057670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8525 11:04:52.100138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8526 11:04:52.100487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8528 11:04:52.144290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8529 11:04:52.144552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8531 11:04:52.187974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8532 11:04:52.188243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8534 11:04:52.232676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8535 11:04:52.232984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8537 11:04:52.277146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8538 11:04:52.277418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8540 11:04:52.317638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8541 11:04:52.317891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8543 11:04:52.364014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8544 11:04:52.364284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8546 11:04:52.406597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8547 11:04:52.406859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8549 11:04:52.447501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8550 11:04:52.447760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8552 11:04:52.489277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8553 11:04:52.489559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8555 11:04:52.528430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8556 11:04:52.528680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8558 11:04:52.567942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8559 11:04:52.568220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8561 11:04:52.601923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8562 11:04:52.602230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8564 11:04:52.641857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8565 11:04:52.642133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8567 11:04:52.680786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8568 11:04:52.681042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8570 11:04:52.721791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8571 11:04:52.722028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8573 11:04:52.761923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8574 11:04:52.762206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8576 11:04:52.802590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8577 11:04:52.802843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8579 11:04:52.838979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8580 11:04:52.839222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8582 11:04:52.876156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8583 11:04:52.876400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8585 11:04:52.919264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8586 11:04:52.919511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8588 11:04:52.958976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8589 11:04:52.959240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8591 11:04:53.007018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8592 11:04:53.007757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8594 11:04:53.058832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8595 11:04:53.059608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8597 11:04:53.112909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8598 11:04:53.113298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8600 11:04:53.157251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8601 11:04:53.158065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8603 11:04:53.200677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8604 11:04:53.201407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8606 11:04:53.254417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8607 11:04:53.254681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8609 11:04:53.303594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8610 11:04:53.303854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8612 11:04:53.348341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8613 11:04:53.348591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8615 11:04:53.391890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8616 11:04:53.392147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8618 11:04:53.436925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8619 11:04:53.437172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8621 11:04:53.484724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8622 11:04:53.485033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8624 11:04:53.528673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8625 11:04:53.528926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8627 11:04:53.585847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8628 11:04:53.586130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8630 11:04:53.634737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8631 11:04:53.634987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8633 11:04:53.683860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8634 11:04:53.684114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8636 11:04:53.731006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8637 11:04:53.731262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8639 11:04:53.780010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8640 11:04:53.780261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8642 11:04:53.832125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8643 11:04:53.832383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8645 11:04:53.876927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8646 11:04:53.877177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8648 11:04:53.925493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8649 11:04:53.925743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8651 11:04:53.975174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8652 11:04:53.975422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8654 11:04:54.027332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8655 11:04:54.027610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8657 11:04:54.074676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8658 11:04:54.074921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8660 11:04:54.123733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8661 11:04:54.123994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8663 11:04:54.169975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8664 11:04:54.170265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8666 11:04:54.212942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8667 11:04:54.213194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8669 11:04:54.264329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8670 11:04:54.264591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8672 11:04:54.304241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8673 11:04:54.304597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8675 11:04:54.350202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8676 11:04:54.350552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8678 11:04:54.404711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8679 11:04:54.405352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8681 11:04:54.460984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8682 11:04:54.461241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8684 11:04:54.509869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8685 11:04:54.510141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8687 11:04:54.553314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8688 11:04:54.553576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8690 11:04:54.604629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8691 11:04:54.604884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8693 11:04:54.650319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8694 11:04:54.650567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8696 11:04:54.694863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8697 11:04:54.695174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8699 11:04:54.745541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8700 11:04:54.746166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8702 11:04:54.795592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8703 11:04:54.796212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8705 11:04:54.840859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8706 11:04:54.841536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8708 11:04:54.887462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8709 11:04:54.888088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8711 11:04:54.947768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8712 11:04:54.948029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8714 11:04:54.992447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8715 11:04:54.992733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8717 11:04:55.035532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8718 11:04:55.035779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8720 11:04:55.077248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8721 11:04:55.077496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8723 11:04:55.117082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8724 11:04:55.117328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8726 11:04:55.153446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8727 11:04:55.153691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8729 11:04:55.191540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8730 11:04:55.191816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8732 11:04:55.231287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8733 11:04:55.231540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8735 11:04:55.272488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8736 11:04:55.272741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8738 11:04:55.315965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8739 11:04:55.316216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8741 11:04:55.359149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8742 11:04:55.359401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8744 11:04:55.409076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8745 11:04:55.409328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8747 11:04:55.448136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8748 11:04:55.448386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8750 11:04:55.490403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8751 11:04:55.490652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8753 11:04:55.535584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8754 11:04:55.535839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8756 11:04:55.573725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8757 11:04:55.573987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8759 11:04:55.613009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8760 11:04:55.613295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8762 11:04:55.653948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8763 11:04:55.654256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8765 11:04:55.697553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8766 11:04:55.697855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8768 11:04:55.745202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8769 11:04:55.745459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8771 11:04:55.785866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8772 11:04:55.786113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8774 11:04:55.832842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8775 11:04:55.833287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8777 11:04:55.883167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8778 11:04:55.883795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8780 11:04:55.937508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8781 11:04:55.938177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8783 11:04:55.987751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8784 11:04:55.988446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8786 11:04:56.042938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8787 11:04:56.043198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8789 11:04:56.096523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8790 11:04:56.097180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8792 11:04:56.142720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8793 11:04:56.143352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8795 11:04:56.192932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8796 11:04:56.193632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8798 11:04:56.245103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8799 11:04:56.245752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8801 11:04:56.297012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8802 11:04:56.297735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8804 11:04:56.351554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8805 11:04:56.352323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8807 11:04:56.402942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8808 11:04:56.403768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8810 11:04:56.454464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8811 11:04:56.455245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8813 11:04:56.499256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8814 11:04:56.500039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8816 11:04:56.555288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8817 11:04:56.556084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8819 11:04:56.608813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8820 11:04:56.609599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8822 11:04:56.664355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8823 11:04:56.664999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8825 11:04:56.719231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8826 11:04:56.719490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8828 11:04:56.769774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8829 11:04:56.770468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8831 11:04:56.817504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8832 11:04:56.818119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8834 11:04:56.863698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8835 11:04:56.864327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8837 11:04:56.917600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8838 11:04:56.918231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8840 11:04:56.973496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8841 11:04:56.974399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8843 11:04:57.026700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8844 11:04:57.027327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8846 11:04:57.078312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8847 11:04:57.079035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8849 11:04:57.128259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8850 11:04:57.128882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8852 11:04:57.183652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8853 11:04:57.184287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8855 11:04:57.230445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8856 11:04:57.231076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8858 11:04:57.284829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8859 11:04:57.285487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8861 11:04:57.331490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8862 11:04:57.332137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8864 11:04:57.382159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8865 11:04:57.382786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8867 11:04:57.428396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8868 11:04:57.429203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8870 11:04:57.478109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8871 11:04:57.478743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8873 11:04:57.531585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8874 11:04:57.532219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8876 11:04:57.576681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8877 11:04:57.577339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8879 11:04:57.628940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8880 11:04:57.629565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8882 11:04:57.677696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8883 11:04:57.678490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8885 11:04:57.727745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8886 11:04:57.728382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8888 11:04:57.781705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8889 11:04:57.782372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8891 11:04:57.832432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8892 11:04:57.832685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8894 11:04:57.873757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8895 11:04:57.874425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8897 11:04:57.916876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8898 11:04:57.917195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8900 11:04:57.963610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8901 11:04:57.963878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8903 11:04:58.007947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8904 11:04:58.008272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8906 11:04:58.053514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8907 11:04:58.053792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8909 11:04:58.094504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8910 11:04:58.094757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8912 11:04:58.134951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8913 11:04:58.135243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8915 11:04:58.174521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8916 11:04:58.174818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8918 11:04:58.211496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8919 11:04:58.211743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8921 11:04:58.257755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8922 11:04:58.258002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8924 11:04:58.297682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8925 11:04:58.297932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8927 11:04:58.335751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8928 11:04:58.336001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8930 11:04:58.380147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8931 11:04:58.380413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8933 11:04:58.420540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8934 11:04:58.420814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8936 11:04:58.460511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8937 11:04:58.460775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8939 11:04:58.496348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8940 11:04:58.496597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8942 11:04:58.539942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8943 11:04:58.540566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8945 11:04:58.590862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8946 11:04:58.591111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8948 11:04:58.631495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8949 11:04:58.631748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8951 11:04:58.668624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8952 11:04:58.668949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8954 11:04:58.705371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8955 11:04:58.705626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8957 11:04:58.743239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8958 11:04:58.743461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8960 11:04:58.777600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8961 11:04:58.777888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
8963 11:04:58.820872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
8964 11:04:58.821119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
8966 11:04:58.855489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
8967 11:04:58.855735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
8969 11:04:58.895327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
8970 11:04:58.895619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
8972 11:04:58.936417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
8973 11:04:58.936708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
8975 11:04:58.977847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
8976 11:04:58.978125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
8978 11:04:59.017972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
8979 11:04:59.018272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
8981 11:04:59.052677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
8982 11:04:59.052926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
8984 11:04:59.099925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
8985 11:04:59.100176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
8987 11:04:59.136237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
8988 11:04:59.136487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
8990 11:04:59.173177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
8991 11:04:59.173430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
8993 11:04:59.210216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
8994 11:04:59.210490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
8996 11:04:59.252148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
8997 11:04:59.252430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
8999 11:04:59.294321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
9000 11:04:59.294572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
9002 11:04:59.332927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
9003 11:04:59.333173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
9005 11:04:59.379518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
9006 11:04:59.380310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
9008 11:04:59.428203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
9009 11:04:59.429000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
9011 11:04:59.477938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
9012 11:04:59.478727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
9014 11:04:59.522542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
9015 11:04:59.523177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
9017 11:04:59.568697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
9018 11:04:59.569274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
9020 11:04:59.610893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
9021 11:04:59.611193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
9023 11:04:59.646740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
9024 11:04:59.646989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
9026 11:04:59.686444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
9027 11:04:59.686695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
9029 11:04:59.725710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
9030 11:04:59.725994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
9032 11:04:59.767088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
9033 11:04:59.767382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
9035 11:04:59.805684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
9036 11:04:59.805964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
9038 11:04:59.840638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
9039 11:04:59.840889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
9041 11:04:59.877033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
9042 11:04:59.877287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
9044 11:04:59.917495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
9045 11:04:59.917747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
9047 11:04:59.966786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
9048 11:04:59.967037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
9050 11:05:00.008901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
9051 11:05:00.009167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
9053 11:05:00.049636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
9054 11:05:00.049878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
9056 11:05:00.096828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
9057 11:05:00.097478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
9059 11:05:00.147524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
9060 11:05:00.148283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
9062 11:05:00.201907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
9063 11:05:00.202638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
9065 11:05:00.253024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
9066 11:05:00.253753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
9068 11:05:00.306384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
9069 11:05:00.307062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
9071 11:05:00.358609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
9072 11:05:00.359288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
9074 11:05:00.409010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
9075 11:05:00.409717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
9077 11:05:00.458508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
9078 11:05:00.459142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
9080 11:05:00.509366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
9081 11:05:00.510116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
9083 11:05:00.562047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
9084 11:05:00.562824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
9086 11:05:00.613004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
9087 11:05:00.613714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
9089 11:05:00.661934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
9090 11:05:00.662243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
9092 11:05:00.700436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
9093 11:05:00.700678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
9095 11:05:00.743994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
9096 11:05:00.744241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
9098 11:05:00.795259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
9099 11:05:00.795512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
9101 11:05:00.842806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
9102 11:05:00.843091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
9104 11:05:00.893029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
9105 11:05:00.893283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
9107 11:05:00.936323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
9108 11:05:00.936601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
9110 11:05:00.982203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
9111 11:05:00.982449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
9113 11:05:01.035700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
9114 11:05:01.035976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
9116 11:05:01.081072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
9117 11:05:01.081326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
9119 11:05:01.129684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
9120 11:05:01.129943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
9122 11:05:01.175318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
9123 11:05:01.175568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
9125 11:05:01.220175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
9126 11:05:01.220429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
9128 11:05:01.268779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
9129 11:05:01.269028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
9131 11:05:01.323630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
9132 11:05:01.323884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
9134 11:05:01.370508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
9135 11:05:01.370763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
9137 11:05:01.420524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
9138 11:05:01.420771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
9140 11:05:01.469901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
9141 11:05:01.470162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
9143 11:05:01.520156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
9144 11:05:01.520412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
9146 11:05:01.568475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
9147 11:05:01.568743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
9149 11:05:01.611517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
9150 11:05:01.611769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
9152 11:05:01.659700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
9153 11:05:01.659959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
9155 11:05:01.704704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
9156 11:05:01.704981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
9158 11:05:01.752717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
9159 11:05:01.752972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9161 11:05:01.805700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9162 11:05:01.805958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9164 11:05:01.860933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9165 11:05:01.861236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9167 11:05:01.912346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9168 11:05:01.912627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9170 11:05:01.956684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9171 11:05:01.956944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9173 11:05:02.006302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9174 11:05:02.006564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9176 11:05:02.058130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9177 11:05:02.058377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9179 11:05:02.105061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9180 11:05:02.105332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9182 11:05:02.157136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9183 11:05:02.157394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9185 11:05:02.203695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9186 11:05:02.203949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9188 11:05:02.250417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9189 11:05:02.250687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9191 11:05:02.293683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9193 11:05:02.296666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9194 11:05:02.344854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9195 11:05:02.345120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9197 11:05:02.395600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9198 11:05:02.395851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9200 11:05:02.447651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9201 11:05:02.447910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9203 11:05:02.492115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9204 11:05:02.492367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9206 11:05:02.539783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9207 11:05:02.540043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9209 11:05:02.593213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9210 11:05:02.593479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9212 11:05:02.641318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9214 11:05:02.644588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9215 11:05:02.704834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9216 11:05:02.705098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9218 11:05:02.756515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9219 11:05:02.756767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9221 11:05:02.808197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9222 11:05:02.808461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9224 11:05:02.857728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9225 11:05:02.857981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9227 11:05:02.904674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9228 11:05:02.904967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9230 11:05:02.952070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9231 11:05:02.952323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9233 11:05:02.994536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9234 11:05:02.994795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9236 11:05:03.039205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9237 11:05:03.039477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9239 11:05:03.083151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9240 11:05:03.083410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9242 11:05:03.138564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9243 11:05:03.138826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9245 11:05:03.187208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9246 11:05:03.187464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9248 11:05:03.234353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9249 11:05:03.234613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9251 11:05:03.283040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9252 11:05:03.283294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9254 11:05:03.328830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9255 11:05:03.329086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9257 11:05:03.384340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9258 11:05:03.384625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9260 11:05:03.430973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9261 11:05:03.431252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9263 11:05:03.479113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9264 11:05:03.479365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9266 11:05:03.526234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9267 11:05:03.526491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9269 11:05:03.572488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9270 11:05:03.572742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9272 11:05:03.614578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9273 11:05:03.614845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9275 11:05:03.658981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9276 11:05:03.659261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9278 11:05:03.707839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9279 11:05:03.708098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9281 11:05:03.753261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9282 11:05:03.753512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9284 11:05:03.798858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9285 11:05:03.799123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9287 11:05:03.845537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9288 11:05:03.845791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9290 11:05:03.892676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9291 11:05:03.892937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9293 11:05:03.940503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9294 11:05:03.940749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9296 11:05:03.983542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9297 11:05:03.983808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9299 11:05:04.036237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9300 11:05:04.036506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9302 11:05:04.083607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9303 11:05:04.083861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9305 11:05:04.129125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9306 11:05:04.129400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9308 11:05:04.173383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9309 11:05:04.173637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9311 11:05:04.221793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9312 11:05:04.222038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9314 11:05:04.268153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9315 11:05:04.268433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9317 11:05:04.308319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9318 11:05:04.308599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9320 11:05:04.357719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9321 11:05:04.357993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9323 11:05:04.404249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9324 11:05:04.404529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9326 11:05:04.451747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9327 11:05:04.452000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9329 11:05:04.500182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9330 11:05:04.500464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9332 11:05:04.545928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9333 11:05:04.546232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9335 11:05:04.594882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9336 11:05:04.595141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9338 11:05:04.637335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9339 11:05:04.637580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9341 11:05:04.687340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9342 11:05:04.687612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9344 11:05:04.728358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9345 11:05:04.728624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9347 11:05:04.769722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9348 11:05:04.769991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9350 11:05:04.811678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9351 11:05:04.811928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9353 11:05:04.857272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9354 11:05:04.857519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9356 11:05:04.903901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9357 11:05:04.904742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9359 11:05:04.954069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9360 11:05:04.954698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9362 11:05:05.010912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9363 11:05:05.011880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9365 11:05:05.056033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9366 11:05:05.056814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9368 11:05:05.108226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9369 11:05:05.109037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9371 11:05:05.157257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9372 11:05:05.157503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9374 11:05:05.200476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9375 11:05:05.200729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9377 11:05:05.249424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9378 11:05:05.249809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9380 11:05:05.297841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9381 11:05:05.298579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9383 11:05:05.356909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9384 11:05:05.357549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9386 11:05:05.412286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9387 11:05:05.413045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9389 11:05:05.463873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9390 11:05:05.464664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9392 11:05:05.519457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9393 11:05:05.520242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9395 11:05:05.572690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9396 11:05:05.573470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9398 11:05:05.623887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9399 11:05:05.624166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9401 11:05:05.660992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9402 11:05:05.661268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9404 11:05:05.708841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9405 11:05:05.709162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9407 11:05:05.752336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9408 11:05:05.752616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9410 11:05:05.791716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9411 11:05:05.791987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9413 11:05:05.836339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9414 11:05:05.836628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9416 11:05:05.877410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9417 11:05:05.877835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9419 11:05:05.925409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9420 11:05:05.926071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9422 11:05:05.974913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9423 11:05:05.975577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9425 11:05:06.033255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9426 11:05:06.034150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9428 11:05:06.074385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9429 11:05:06.074649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9431 11:05:06.118840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9432 11:05:06.119111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9434 11:05:06.163910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9435 11:05:06.164574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9437 11:05:06.219442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9438 11:05:06.219704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9440 11:05:06.267532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9441 11:05:06.267813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9443 11:05:06.311223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9444 11:05:06.311475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9446 11:05:06.358238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9447 11:05:06.358488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9449 11:05:06.404316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9450 11:05:06.404621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9452 11:05:06.461400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9453 11:05:06.462144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9455 11:05:06.515033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9456 11:05:06.515292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9458 11:05:06.561212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9459 11:05:06.561518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9461 11:05:06.603589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9462 11:05:06.603844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9464 11:05:06.643586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9465 11:05:06.644229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9467 11:05:06.700030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9468 11:05:06.700666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9470 11:05:06.754089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9471 11:05:06.754762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9473 11:05:06.805776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9474 11:05:06.806042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9476 11:05:06.843819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9477 11:05:06.844115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9479 11:05:06.885972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9480 11:05:06.886267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9482 11:05:06.929878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9483 11:05:06.930205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9485 11:05:06.980231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9486 11:05:06.980867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9488 11:05:07.037079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9489 11:05:07.037728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9491 11:05:07.082060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9492 11:05:07.082341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9494 11:05:07.127454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9495 11:05:07.127748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9497 11:05:07.167473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9498 11:05:07.167930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9500 11:05:07.211042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9501 11:05:07.211290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9503 11:05:07.251763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9504 11:05:07.252006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9506 11:05:07.295659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9507 11:05:07.295912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9509 11:05:07.344045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9510 11:05:07.344293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9512 11:05:07.389320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9513 11:05:07.389574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9515 11:05:07.434262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9516 11:05:07.434519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9518 11:05:07.483859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9519 11:05:07.484117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9521 11:05:07.529571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9522 11:05:07.529821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9524 11:05:07.576717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9525 11:05:07.576981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9527 11:05:07.621707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9528 11:05:07.621971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9530 11:05:07.673799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9531 11:05:07.674079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9533 11:05:07.720683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9534 11:05:07.720946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9536 11:05:07.768687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9537 11:05:07.768944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9539 11:05:07.818368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9540 11:05:07.818642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9542 11:05:07.865133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9543 11:05:07.865391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9545 11:05:07.916827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9546 11:05:07.917088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9548 11:05:07.957088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9549 11:05:07.957335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9551 11:05:08.006300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9552 11:05:08.006556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9554 11:05:08.056479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9555 11:05:08.056723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9557 11:05:08.104015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9558 11:05:08.104279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9560 11:05:08.148765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9561 11:05:08.149012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9563 11:05:08.194469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9564 11:05:08.194734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9566 11:05:08.244225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9567 11:05:08.244491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9569 11:05:08.290742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9570 11:05:08.291001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9572 11:05:08.343007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9573 11:05:08.343265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9575 11:05:08.389484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9576 11:05:08.389737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9578 11:05:08.439261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9579 11:05:08.439517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9581 11:05:08.483364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9582 11:05:08.483619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9584 11:05:08.527046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9585 11:05:08.527302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9587 11:05:08.571813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9588 11:05:08.572061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9590 11:05:08.617521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9591 11:05:08.617874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9593 11:05:08.668281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9594 11:05:08.668528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9596 11:05:08.718252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9597 11:05:08.718510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9599 11:05:08.766115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9600 11:05:08.766391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9602 11:05:08.815719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9603 11:05:08.815977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9605 11:05:08.864232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9606 11:05:08.864488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9608 11:05:08.915027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9609 11:05:08.915319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9611 11:05:08.959437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9612 11:05:08.959685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9614 11:05:09.006854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9615 11:05:09.007117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9617 11:05:09.052958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9618 11:05:09.053216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9620 11:05:09.099074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9621 11:05:09.099325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9623 11:05:09.147443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9624 11:05:09.147703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9626 11:05:09.198770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9627 11:05:09.199022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9629 11:05:09.245814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9630 11:05:09.246148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9632 11:05:09.289203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9634 11:05:09.292665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9635 11:05:09.343902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9636 11:05:09.344161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9638 11:05:09.396458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9639 11:05:09.396711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9641 11:05:09.445096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9642 11:05:09.445374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9644 11:05:09.493207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9645 11:05:09.493485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9647 11:05:09.539067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9648 11:05:09.539324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9650 11:05:09.588152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9651 11:05:09.588436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9653 11:05:09.642483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9654 11:05:09.642766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9656 11:05:09.695031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9657 11:05:09.695302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9659 11:05:09.744633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9660 11:05:09.744882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9662 11:05:09.797245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9663 11:05:09.797506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9665 11:05:09.853148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9666 11:05:09.853398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9668 11:05:09.904967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9669 11:05:09.905251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9671 11:05:09.953143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9672 11:05:09.953406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9674 11:05:09.994642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9675 11:05:09.994898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9677 11:05:10.046750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9678 11:05:10.047014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9680 11:05:10.098674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9681 11:05:10.098924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9683 11:05:10.145036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9684 11:05:10.145293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9686 11:05:10.193606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9687 11:05:10.193872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9689 11:05:10.239794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9690 11:05:10.240050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9692 11:05:10.291782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9693 11:05:10.292046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9695 11:05:10.335363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9696 11:05:10.335626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9698 11:05:10.383899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9699 11:05:10.384147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9701 11:05:10.432040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9702 11:05:10.432295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9704 11:05:10.481362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9705 11:05:10.481630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9707 11:05:10.526901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9708 11:05:10.527153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9710 11:05:10.579723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9711 11:05:10.580008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9713 11:05:10.625427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9714 11:05:10.625676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9716 11:05:10.670663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9717 11:05:10.670916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9719 11:05:10.722462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9720 11:05:10.722719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9722 11:05:10.769192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9723 11:05:10.769458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9725 11:05:10.816877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9726 11:05:10.817178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9728 11:05:10.862584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9729 11:05:10.862850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9731 11:05:10.911432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9732 11:05:10.912019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9734 11:05:10.963329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9735 11:05:10.964134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9737 11:05:11.011076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9738 11:05:11.011870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9740 11:05:11.071550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9741 11:05:11.072233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9743 11:05:11.130664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9744 11:05:11.131421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9746 11:05:11.181105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9747 11:05:11.181460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9749 11:05:11.233005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9750 11:05:11.233667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9752 11:05:11.292386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9753 11:05:11.293090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9755 11:05:11.348257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9756 11:05:11.348912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9758 11:05:11.401994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9759 11:05:11.402684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9761 11:05:11.460699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9762 11:05:11.461332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9764 11:05:11.517241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9765 11:05:11.517509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9767 11:05:11.562554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9768 11:05:11.562805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9770 11:05:11.616323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9771 11:05:11.616577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9773 11:05:11.666799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9774 11:05:11.667057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9776 11:05:11.715731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9777 11:05:11.715991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9779 11:05:11.761577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9780 11:05:11.761823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9782 11:05:11.816541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9783 11:05:11.816801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9785 11:05:11.865333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9786 11:05:11.865578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9788 11:05:11.914819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9789 11:05:11.915119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9791 11:05:11.964773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9792 11:05:11.965027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9794 11:05:12.014744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9795 11:05:12.015015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9797 11:05:12.062315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9798 11:05:12.062571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9800 11:05:12.105358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9801 11:05:12.105612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9803 11:05:12.157251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9804 11:05:12.157501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9806 11:05:12.202562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9807 11:05:12.202833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9809 11:05:12.249946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9810 11:05:12.250245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9812 11:05:12.298941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9813 11:05:12.299192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9815 11:05:12.348962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9816 11:05:12.349214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9818 11:05:12.396397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9819 11:05:12.396731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9821 11:05:12.441105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9822 11:05:12.441365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9824 11:05:12.488671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9825 11:05:12.488924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9827 11:05:12.531975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9828 11:05:12.532234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9830 11:05:12.576024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9831 11:05:12.576269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9833 11:05:12.627954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9834 11:05:12.628216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9836 11:05:12.674422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9837 11:05:12.674671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9839 11:05:12.719778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9840 11:05:12.720033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9842 11:05:12.763652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9843 11:05:12.763903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9845 11:05:12.813142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9846 11:05:12.813414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9848 11:05:12.862982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9849 11:05:12.863228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9851 11:05:12.910689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9852 11:05:12.910951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9854 11:05:12.958454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9855 11:05:12.958699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9857 11:05:13.006960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9858 11:05:13.007213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9860 11:05:13.055042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9861 11:05:13.055321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9863 11:05:13.101874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9864 11:05:13.102131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9866 11:05:13.149751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9867 11:05:13.150019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9869 11:05:13.197053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9870 11:05:13.197310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9872 11:05:13.245308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9873 11:05:13.245565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9875 11:05:13.291403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9876 11:05:13.291651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9878 11:05:13.337868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9879 11:05:13.338152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9881 11:05:13.383653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9882 11:05:13.383898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9884 11:05:13.431787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9885 11:05:13.432080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9887 11:05:13.484737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9888 11:05:13.484999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9890 11:05:13.528987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9891 11:05:13.529248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9893 11:05:13.577870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9894 11:05:13.578138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9896 11:05:13.625936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9897 11:05:13.626272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9899 11:05:13.676589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9900 11:05:13.676842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9902 11:05:13.723484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9903 11:05:13.723808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9905 11:05:13.765522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9906 11:05:13.765778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9908 11:05:13.818535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9909 11:05:13.818789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9911 11:05:13.864106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9912 11:05:13.864365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9914 11:05:13.910688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9915 11:05:13.910941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9917 11:05:13.955772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9918 11:05:13.956026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9920 11:05:14.004181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9921 11:05:14.004436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9923 11:05:14.048068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9924 11:05:14.048326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9926 11:05:14.091408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9927 11:05:14.091659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9929 11:05:14.138132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9930 11:05:14.138402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9932 11:05:14.185514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9933 11:05:14.185771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9935 11:05:14.229364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9936 11:05:14.229621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9938 11:05:14.271772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9939 11:05:14.272018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9941 11:05:14.318102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9942 11:05:14.318366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9944 11:05:14.366868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9945 11:05:14.367118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9947 11:05:14.407544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9948 11:05:14.407798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9950 11:05:14.456820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9951 11:05:14.457074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9953 11:05:14.504710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9954 11:05:14.505014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9956 11:05:14.554480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9957 11:05:14.554759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9959 11:05:14.602477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9960 11:05:14.602744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9962 11:05:14.650947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
9963 11:05:14.651193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
9965 11:05:14.699696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
9966 11:05:14.699956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
9968 11:05:14.747351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
9970 11:05:14.750746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
9971 11:05:14.801371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
9972 11:05:14.801708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
9974 11:05:14.844945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
9975 11:05:14.845194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
9977 11:05:14.891456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
9978 11:05:14.891706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
9980 11:05:14.937741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
9981 11:05:14.937996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
9983 11:05:14.981788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
9984 11:05:14.982045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
9986 11:05:15.020908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
9988 11:05:15.023960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
9989 11:05:15.060800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
9990 11:05:15.061055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
9992 11:05:15.104333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
9993 11:05:15.104604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
9995 11:05:15.156329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
9996 11:05:15.156606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
9998 11:05:15.205152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
9999 11:05:15.205434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
10001 11:05:15.250224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
10002 11:05:15.250475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
10004 11:05:15.297107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
10005 11:05:15.297363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
10007 11:05:15.344984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
10008 11:05:15.345236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
10010 11:05:15.395967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
10011 11:05:15.396285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
10013 11:05:15.450251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
10014 11:05:15.450514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
10016 11:05:15.502366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
10017 11:05:15.502639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
10019 11:05:15.556831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
10020 11:05:15.557139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
10022 11:05:15.603165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
10023 11:05:15.603466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
10025 11:05:15.650782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
10026 11:05:15.651039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
10028 11:05:15.700702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
10029 11:05:15.700988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
10031 11:05:15.745081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
10032 11:05:15.745335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
10034 11:05:15.798874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
10035 11:05:15.799142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
10037 11:05:15.850828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
10038 11:05:15.851105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
10040 11:05:15.897491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
10041 11:05:15.897777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
10043 11:05:15.947787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
10044 11:05:15.948042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
10046 11:05:16.002133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
10047 11:05:16.002401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
10049 11:05:16.050735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
10050 11:05:16.050983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
10052 11:05:16.104924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
10053 11:05:16.105186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
10055 11:05:16.159736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
10056 11:05:16.159989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
10058 11:05:16.209116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
10059 11:05:16.209391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
10061 11:05:16.257862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
10062 11:05:16.258138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
10064 11:05:16.311366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
10065 11:05:16.311626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
10067 11:05:16.361326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
10068 11:05:16.361581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
10070 11:05:16.408877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
10071 11:05:16.409156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
10073 11:05:16.454508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
10074 11:05:16.454769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
10076 11:05:16.505809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
10077 11:05:16.506121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
10079 11:05:16.553182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
10080 11:05:16.553441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
10082 11:05:16.599975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
10083 11:05:16.600339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
10085 11:05:16.651541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
10086 11:05:16.651810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
10088 11:05:16.698067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
10089 11:05:16.698355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
10091 11:05:16.750183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
10092 11:05:16.750438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
10094 11:05:16.799821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
10095 11:05:16.800106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
10097 11:05:16.856479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
10098 11:05:16.856756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
10100 11:05:16.908396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
10101 11:05:16.908677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
10103 11:05:16.956112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
10104 11:05:16.956394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
10106 11:05:17.008603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
10107 11:05:17.008885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
10109 11:05:17.058029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
10110 11:05:17.058307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
10112 11:05:17.103565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10113 11:05:17.103653 + set +x
10114 11:05:17.103879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10116 11:05:17.110002 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14786791_1.6.2.3.5>
10117 11:05:17.110305 Received signal: <ENDRUN> 1_kselftest-alsa 14786791_1.6.2.3.5
10118 11:05:17.110400 Ending use of test pattern.
10119 11:05:17.110481 Ending test lava.1_kselftest-alsa (14786791_1.6.2.3.5), duration 46.08
10121 11:05:17.113564 <LAVA_TEST_RUNNER EXIT>
10122 11:05:17.113820 ok: lava_test_shell seems to have completed
10123 11:05:17.116717 shardfile-alsa: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_valid_0_93: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test: pass
10124 11:05:17.117080 end: 3.1 lava-test-shell (duration 00:00:47) [common]
10125 11:05:17.117163 end: 3 lava-test-retry (duration 00:00:47) [common]
10126 11:05:17.117244 start: 4 finalize (timeout 00:07:20) [common]
10127 11:05:17.117360 start: 4.1 power-off (timeout 00:00:30) [common]
10128 11:05:17.117518 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4', '--port=1', '--command=off']
10129 11:05:19.192304 >> Command sent successfully.
10130 11:05:19.196982 Returned 0 in 2 seconds
10131 11:05:19.197121 end: 4.1 power-off (duration 00:00:02) [common]
10133 11:05:19.197419 start: 4.2 read-feedback (timeout 00:07:18) [common]
10134 11:05:19.197584 Listened to connection for namespace 'common' for up to 1s
10135 11:05:20.198056 Finalising connection for namespace 'common'
10136 11:05:20.198226 Disconnecting from shell: Finalise
10137 11:05:20.198292 / #
10138 11:05:20.298536 end: 4.2 read-feedback (duration 00:00:01) [common]
10139 11:05:20.298661 end: 4 finalize (duration 00:00:03) [common]
10140 11:05:20.298773 Cleaning after the job
10141 11:05:20.298860 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/ramdisk
10142 11:05:20.301094 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/kernel
10143 11:05:20.312533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/dtb
10144 11:05:20.312746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/nfsrootfs
10145 11:05:20.379653 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786791/tftp-deploy-i61yb_1y/modules
10146 11:05:20.385711 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786791
10147 11:05:21.051190 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786791
10148 11:05:21.051366 Job finished correctly