Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 91
1 11:02:00.348372 lava-dispatcher, installed at version: 2024.05
2 11:02:00.348569 start: 0 validate
3 11:02:00.348689 Start time: 2024-07-10 11:02:00.348680+00:00 (UTC)
4 11:02:00.348816 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:00.348955 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:02:00.616125 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:00.616285 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:02:00.882466 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:02:00.883187 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:03:01.216711 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:03:01.217365 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:03:01.746712 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:03:01.747485 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:03:02.026050 validate duration: 61.68
16 11:03:02.027282 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:03:02.027776 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:03:02.028214 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:03:02.028903 Not decompressing ramdisk as can be used compressed.
20 11:03:02.029379 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:03:02.029708 saving as /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/ramdisk/initrd.cpio.gz
22 11:03:02.030040 total size: 5628169 (5 MB)
23 11:03:06.514733 progress 0 % (0 MB)
24 11:03:06.524226 progress 5 % (0 MB)
25 11:03:06.532795 progress 10 % (0 MB)
26 11:03:06.539590 progress 15 % (0 MB)
27 11:03:06.544779 progress 20 % (1 MB)
28 11:03:06.548471 progress 25 % (1 MB)
29 11:03:06.551879 progress 30 % (1 MB)
30 11:03:06.554979 progress 35 % (1 MB)
31 11:03:06.557448 progress 40 % (2 MB)
32 11:03:06.560025 progress 45 % (2 MB)
33 11:03:06.562134 progress 50 % (2 MB)
34 11:03:06.564429 progress 55 % (2 MB)
35 11:03:06.566433 progress 60 % (3 MB)
36 11:03:06.568218 progress 65 % (3 MB)
37 11:03:06.570146 progress 70 % (3 MB)
38 11:03:06.571822 progress 75 % (4 MB)
39 11:03:06.573606 progress 80 % (4 MB)
40 11:03:06.575116 progress 85 % (4 MB)
41 11:03:06.576750 progress 90 % (4 MB)
42 11:03:06.578369 progress 95 % (5 MB)
43 11:03:06.579785 progress 100 % (5 MB)
44 11:03:06.579986 5 MB downloaded in 4.55 s (1.18 MB/s)
45 11:03:06.580125 end: 1.1.1 http-download (duration 00:00:05) [common]
47 11:03:06.580345 end: 1.1 download-retry (duration 00:00:05) [common]
48 11:03:06.580423 start: 1.2 download-retry (timeout 00:09:55) [common]
49 11:03:06.580497 start: 1.2.1 http-download (timeout 00:09:55) [common]
50 11:03:06.580628 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:03:06.580688 saving as /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/kernel/Image
52 11:03:06.580740 total size: 54813184 (52 MB)
53 11:03:06.580792 No compression specified
54 11:03:19.086129 progress 0 % (0 MB)
55 11:03:19.132844 progress 5 % (2 MB)
56 11:03:19.150656 progress 10 % (5 MB)
57 11:03:19.164023 progress 15 % (7 MB)
58 11:03:19.177467 progress 20 % (10 MB)
59 11:03:19.190732 progress 25 % (13 MB)
60 11:03:19.203910 progress 30 % (15 MB)
61 11:03:19.217196 progress 35 % (18 MB)
62 11:03:19.230290 progress 40 % (20 MB)
63 11:03:19.243327 progress 45 % (23 MB)
64 11:03:19.257821 progress 50 % (26 MB)
65 11:03:19.270994 progress 55 % (28 MB)
66 11:03:19.283923 progress 60 % (31 MB)
67 11:03:19.297323 progress 65 % (34 MB)
68 11:03:19.311070 progress 70 % (36 MB)
69 11:03:19.324174 progress 75 % (39 MB)
70 11:03:19.337376 progress 80 % (41 MB)
71 11:03:19.350698 progress 85 % (44 MB)
72 11:03:19.363862 progress 90 % (47 MB)
73 11:03:19.377212 progress 95 % (49 MB)
74 11:03:19.390147 progress 100 % (52 MB)
75 11:03:19.390359 52 MB downloaded in 12.81 s (4.08 MB/s)
76 11:03:19.390497 end: 1.2.1 http-download (duration 00:00:13) [common]
78 11:03:19.390700 end: 1.2 download-retry (duration 00:00:13) [common]
79 11:03:19.390777 start: 1.3 download-retry (timeout 00:09:43) [common]
80 11:03:19.390852 start: 1.3.1 http-download (timeout 00:09:43) [common]
81 11:03:19.390978 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 11:03:19.391037 saving as /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 11:03:19.391087 total size: 57695 (0 MB)
84 11:03:19.391138 No compression specified
85 11:03:19.658634 progress 56 % (0 MB)
86 11:03:19.660465 progress 100 % (0 MB)
87 11:03:19.662002 0 MB downloaded in 0.27 s (0.20 MB/s)
88 11:03:19.662792 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:03:19.664401 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:03:19.664841 start: 1.4 download-retry (timeout 00:09:42) [common]
92 11:03:19.665418 start: 1.4.1 http-download (timeout 00:09:42) [common]
93 11:03:19.666235 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:03:19.666814 saving as /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/nfsrootfs/full.rootfs.tar
95 11:03:19.667440 total size: 120894716 (115 MB)
96 11:03:19.667943 Using unxz to decompress xz
97 11:03:19.941093 progress 0 % (0 MB)
98 11:03:20.314087 progress 5 % (5 MB)
99 11:03:20.653923 progress 10 % (11 MB)
100 11:03:20.999498 progress 15 % (17 MB)
101 11:03:21.320877 progress 20 % (23 MB)
102 11:03:21.624667 progress 25 % (28 MB)
103 11:03:21.970722 progress 30 % (34 MB)
104 11:03:22.287457 progress 35 % (40 MB)
105 11:03:22.457096 progress 40 % (46 MB)
106 11:03:22.642365 progress 45 % (51 MB)
107 11:03:22.941778 progress 50 % (57 MB)
108 11:03:23.307237 progress 55 % (63 MB)
109 11:03:23.640753 progress 60 % (69 MB)
110 11:03:23.978049 progress 65 % (74 MB)
111 11:03:24.318480 progress 70 % (80 MB)
112 11:03:24.680456 progress 75 % (86 MB)
113 11:03:25.021360 progress 80 % (92 MB)
114 11:03:25.366247 progress 85 % (98 MB)
115 11:03:25.710261 progress 90 % (103 MB)
116 11:03:26.036477 progress 95 % (109 MB)
117 11:03:26.386285 progress 100 % (115 MB)
118 11:03:26.391571 115 MB downloaded in 6.72 s (17.15 MB/s)
119 11:03:26.391781 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:03:26.392099 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:03:26.392208 start: 1.5 download-retry (timeout 00:09:36) [common]
123 11:03:26.392315 start: 1.5.1 http-download (timeout 00:09:36) [common]
124 11:03:26.392492 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:03:26.392583 saving as /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/modules/modules.tar
126 11:03:26.392666 total size: 8607984 (8 MB)
127 11:03:26.392749 Using unxz to decompress xz
128 11:03:26.394447 progress 0 % (0 MB)
129 11:03:26.415320 progress 5 % (0 MB)
130 11:03:26.439815 progress 10 % (0 MB)
131 11:03:26.463530 progress 15 % (1 MB)
132 11:03:26.487570 progress 20 % (1 MB)
133 11:03:26.512889 progress 25 % (2 MB)
134 11:03:26.538193 progress 30 % (2 MB)
135 11:03:26.563297 progress 35 % (2 MB)
136 11:03:26.592163 progress 40 % (3 MB)
137 11:03:26.617904 progress 45 % (3 MB)
138 11:03:26.642457 progress 50 % (4 MB)
139 11:03:26.666749 progress 55 % (4 MB)
140 11:03:26.691162 progress 60 % (4 MB)
141 11:03:26.714716 progress 65 % (5 MB)
142 11:03:26.740717 progress 70 % (5 MB)
143 11:03:26.767902 progress 75 % (6 MB)
144 11:03:26.796168 progress 80 % (6 MB)
145 11:03:26.820521 progress 85 % (7 MB)
146 11:03:26.844764 progress 90 % (7 MB)
147 11:03:26.867965 progress 95 % (7 MB)
148 11:03:26.890306 progress 100 % (8 MB)
149 11:03:26.896240 8 MB downloaded in 0.50 s (16.30 MB/s)
150 11:03:26.896455 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:03:26.896715 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:03:26.896839 start: 1.6 prepare-tftp-overlay (timeout 00:09:35) [common]
154 11:03:26.896930 start: 1.6.1 extract-nfsrootfs (timeout 00:09:35) [common]
155 11:03:30.606835 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786794/extract-nfsrootfs-gd9vxcky
156 11:03:30.607014 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:03:30.607102 start: 1.6.2 lava-overlay (timeout 00:09:31) [common]
158 11:03:30.607252 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi
159 11:03:30.607370 makedir: /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin
160 11:03:30.607462 makedir: /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/tests
161 11:03:30.607583 makedir: /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/results
162 11:03:30.607665 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-add-keys
163 11:03:30.607790 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-add-sources
164 11:03:30.607938 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-background-process-start
165 11:03:30.608109 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-background-process-stop
166 11:03:30.608315 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-common-functions
167 11:03:30.608439 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-echo-ipv4
168 11:03:30.608556 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-install-packages
169 11:03:30.608670 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-installed-packages
170 11:03:30.608784 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-os-build
171 11:03:30.608896 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-probe-channel
172 11:03:30.609010 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-probe-ip
173 11:03:30.609153 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-target-ip
174 11:03:30.609283 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-target-mac
175 11:03:30.609394 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-target-storage
176 11:03:30.609510 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-test-case
177 11:03:30.609623 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-test-event
178 11:03:30.609733 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-test-feedback
179 11:03:30.609844 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-test-raise
180 11:03:30.609953 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-test-reference
181 11:03:30.610064 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-test-runner
182 11:03:30.610174 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-test-set
183 11:03:30.610286 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-test-shell
184 11:03:30.610405 Updating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-add-keys (debian)
185 11:03:30.613880 Updating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-add-sources (debian)
186 11:03:30.614244 Updating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-install-packages (debian)
187 11:03:30.614641 Updating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-installed-packages (debian)
188 11:03:30.614856 Updating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/bin/lava-os-build (debian)
189 11:03:30.615039 Creating /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/environment
190 11:03:30.615136 LAVA metadata
191 11:03:30.615206 - LAVA_JOB_ID=14786794
192 11:03:30.615265 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:03:30.615370 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:31) [common]
194 11:03:30.615429 skipped lava-vland-overlay
195 11:03:30.615497 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:03:30.615569 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:31) [common]
197 11:03:30.615622 skipped lava-multinode-overlay
198 11:03:30.615685 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:03:30.615753 start: 1.6.2.3 test-definition (timeout 00:09:31) [common]
200 11:03:30.615818 Loading test definitions
201 11:03:30.615893 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:31) [common]
202 11:03:30.615951 Using /lava-14786794 at stage 0
203 11:03:30.616228 uuid=14786794_1.6.2.3.1 testdef=None
204 11:03:30.616308 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:03:30.616381 start: 1.6.2.3.2 test-overlay (timeout 00:09:31) [common]
206 11:03:30.616769 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:03:30.616960 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:31) [common]
209 11:03:30.617510 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:03:30.617715 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:31) [common]
212 11:03:30.618270 runner path: /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/0/tests/0_timesync-off test_uuid 14786794_1.6.2.3.1
213 11:03:30.618486 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:03:30.618686 start: 1.6.2.3.5 git-repo-action (timeout 00:09:31) [common]
216 11:03:30.618751 Using /lava-14786794 at stage 0
217 11:03:30.618836 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:03:30.618908 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/0/tests/1_kselftest-arm64'
219 11:03:40.858505 Running '/usr/bin/git checkout kernelci.org
220 11:03:41.005422 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:03:41.005783 uuid=14786794_1.6.2.3.5 testdef=None
222 11:03:41.005886 end: 1.6.2.3.5 git-repo-action (duration 00:00:10) [common]
224 11:03:41.006183 start: 1.6.2.3.6 test-overlay (timeout 00:09:21) [common]
225 11:03:41.006882 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:03:41.007077 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:21) [common]
228 11:03:41.007942 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:03:41.008156 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:21) [common]
231 11:03:41.008992 runner path: /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/0/tests/1_kselftest-arm64 test_uuid 14786794_1.6.2.3.5
232 11:03:41.009070 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 11:03:41.009131 BRANCH='cip'
234 11:03:41.009250 SKIPFILE='/dev/null'
235 11:03:41.009300 SKIP_INSTALL='True'
236 11:03:41.009348 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:03:41.009397 TST_CASENAME=''
238 11:03:41.009444 TST_CMDFILES='arm64'
239 11:03:41.009572 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:03:41.009748 Creating lava-test-runner.conf files
242 11:03:41.009801 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786794/lava-overlay-uuvdemyi/lava-14786794/0 for stage 0
243 11:03:41.009881 - 0_timesync-off
244 11:03:41.009939 - 1_kselftest-arm64
245 11:03:41.010022 end: 1.6.2.3 test-definition (duration 00:00:10) [common]
246 11:03:41.010097 start: 1.6.2.4 compress-overlay (timeout 00:09:21) [common]
247 11:03:48.347691 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:03:48.347850 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:14) [common]
249 11:03:48.347959 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:03:48.348066 end: 1.6.2 lava-overlay (duration 00:00:18) [common]
251 11:03:48.348169 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:14) [common]
252 11:03:48.492376 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:03:48.492517 start: 1.6.4 extract-modules (timeout 00:09:14) [common]
254 11:03:48.492594 extracting modules file /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786794/extract-nfsrootfs-gd9vxcky
255 11:03:48.715494 extracting modules file /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786794/extract-overlay-ramdisk-u7m907bi/ramdisk
256 11:03:48.948842 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:03:48.948981 start: 1.6.5 apply-overlay-tftp (timeout 00:09:13) [common]
258 11:03:48.949056 [common] Applying overlay to NFS
259 11:03:48.949120 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786794/compress-overlay-am5l965h/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786794/extract-nfsrootfs-gd9vxcky
260 11:03:49.772968 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:03:49.773153 start: 1.6.6 configure-preseed-file (timeout 00:09:12) [common]
262 11:03:49.773285 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:03:49.773390 start: 1.6.7 compress-ramdisk (timeout 00:09:12) [common]
264 11:03:49.773483 Building ramdisk /var/lib/lava/dispatcher/tmp/14786794/extract-overlay-ramdisk-u7m907bi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786794/extract-overlay-ramdisk-u7m907bi/ramdisk
265 11:03:50.035740 >> 129845 blocks
266 11:03:52.097435 rename /var/lib/lava/dispatcher/tmp/14786794/extract-overlay-ramdisk-u7m907bi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/ramdisk/ramdisk.cpio.gz
267 11:03:52.097587 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:03:52.097674 start: 1.6.8 prepare-kernel (timeout 00:09:10) [common]
269 11:03:52.097751 start: 1.6.8.1 prepare-fit (timeout 00:09:10) [common]
270 11:03:52.097831 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/kernel/Image']
271 11:04:05.958043 Returned 0 in 13 seconds
272 11:04:05.958196 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/kernel/image.itb
273 11:04:06.293576 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:04:06.293688 output: Created: Wed Jul 10 12:04:06 2024
275 11:04:06.293749 output: Image 0 (kernel-1)
276 11:04:06.293803 output: Description:
277 11:04:06.293886 output: Created: Wed Jul 10 12:04:06 2024
278 11:04:06.293953 output: Type: Kernel Image
279 11:04:06.294005 output: Compression: lzma compressed
280 11:04:06.294057 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
281 11:04:06.294107 output: Architecture: AArch64
282 11:04:06.294156 output: OS: Linux
283 11:04:06.294204 output: Load Address: 0x00000000
284 11:04:06.294253 output: Entry Point: 0x00000000
285 11:04:06.294303 output: Hash algo: crc32
286 11:04:06.294351 output: Hash value: 9bb85fb9
287 11:04:06.294399 output: Image 1 (fdt-1)
288 11:04:06.294447 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 11:04:06.294495 output: Created: Wed Jul 10 12:04:06 2024
290 11:04:06.294544 output: Type: Flat Device Tree
291 11:04:06.294591 output: Compression: uncompressed
292 11:04:06.294639 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 11:04:06.294687 output: Architecture: AArch64
294 11:04:06.294735 output: Hash algo: crc32
295 11:04:06.294782 output: Hash value: a9713552
296 11:04:06.294829 output: Image 2 (ramdisk-1)
297 11:04:06.294877 output: Description: unavailable
298 11:04:06.294925 output: Created: Wed Jul 10 12:04:06 2024
299 11:04:06.294973 output: Type: RAMDisk Image
300 11:04:06.295020 output: Compression: uncompressed
301 11:04:06.295068 output: Data Size: 18710259 Bytes = 18271.74 KiB = 17.84 MiB
302 11:04:06.295116 output: Architecture: AArch64
303 11:04:06.295173 output: OS: Linux
304 11:04:06.295259 output: Load Address: unavailable
305 11:04:06.295343 output: Entry Point: unavailable
306 11:04:06.295391 output: Hash algo: crc32
307 11:04:06.295440 output: Hash value: a1c6c76f
308 11:04:06.295487 output: Default Configuration: 'conf-1'
309 11:04:06.295567 output: Configuration 0 (conf-1)
310 11:04:06.295631 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 11:04:06.295680 output: Kernel: kernel-1
312 11:04:06.295739 output: Init Ramdisk: ramdisk-1
313 11:04:06.295817 output: FDT: fdt-1
314 11:04:06.295906 output: Loadables: kernel-1
315 11:04:06.295974 output:
316 11:04:06.296097 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:04:06.296223 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:04:06.296336 end: 1.6 prepare-tftp-overlay (duration 00:00:39) [common]
319 11:04:06.296416 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
320 11:04:06.296511 No LXC device requested
321 11:04:06.296593 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:04:06.296680 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
323 11:04:06.296807 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:04:06.296861 Checking files for TFTP limit of 4294967296 bytes.
325 11:04:06.297268 end: 1 tftp-deploy (duration 00:01:04) [common]
326 11:04:06.297357 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:04:06.297436 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:04:06.297525 substitutions:
329 11:04:06.297584 - {DTB}: 14786794/tftp-deploy-hhm84oqd/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 11:04:06.297638 - {INITRD}: 14786794/tftp-deploy-hhm84oqd/ramdisk/ramdisk.cpio.gz
331 11:04:06.297692 - {KERNEL}: 14786794/tftp-deploy-hhm84oqd/kernel/Image
332 11:04:06.297742 - {LAVA_MAC}: None
333 11:04:06.297791 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786794/extract-nfsrootfs-gd9vxcky
334 11:04:06.297841 - {NFS_SERVER_IP}: 192.168.201.1
335 11:04:06.297889 - {PRESEED_CONFIG}: None
336 11:04:06.297942 - {PRESEED_LOCAL}: None
337 11:04:06.297990 - {RAMDISK}: 14786794/tftp-deploy-hhm84oqd/ramdisk/ramdisk.cpio.gz
338 11:04:06.298039 - {ROOT_PART}: None
339 11:04:06.298087 - {ROOT}: None
340 11:04:06.298135 - {SERVER_IP}: 192.168.201.1
341 11:04:06.298183 - {TEE}: None
342 11:04:06.298230 Parsed boot commands:
343 11:04:06.298277 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:04:06.298409 Parsed boot commands: tftpboot 192.168.201.1 14786794/tftp-deploy-hhm84oqd/kernel/image.itb 14786794/tftp-deploy-hhm84oqd/kernel/cmdline
345 11:04:06.298488 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:04:06.298560 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:04:06.298633 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:04:06.298703 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:04:06.298758 Not connected, no need to disconnect.
350 11:04:06.298822 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:04:06.298889 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:04:06.298942 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-1'
353 11:04:06.302143 Setting prompt string to ['lava-test: # ']
354 11:04:06.302464 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:04:06.302559 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:04:06.302648 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:04:06.302725 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:04:06.302929 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1', '--port=1', '--command=reboot']
359 11:04:15.446578 >> Command sent successfully.
360 11:04:15.449891 Returned 0 in 9 seconds
361 11:04:15.450024 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:04:15.450227 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:04:15.450309 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:04:15.450377 Setting prompt string to 'Starting depthcharge on Juniper...'
366 11:04:15.450431 Changing prompt to 'Starting depthcharge on Juniper...'
367 11:04:15.450489 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
368 11:04:15.450819 [Enter `^Ec?' for help]
369 11:04:23.426080 [DL] 00000000 00000000 010701
370 11:04:23.430998
371 11:04:23.431085
372 11:04:23.431143 F0: 102B 0000
373 11:04:23.431202
374 11:04:23.431253 F3: 1006 0033 [0200]
375 11:04:23.434370
376 11:04:23.434444 F3: 4001 00E0 [0200]
377 11:04:23.434503
378 11:04:23.434556 F3: 0000 0000
379 11:04:23.437812
380 11:04:23.437909 V0: 0000 0000 [0001]
381 11:04:23.437968
382 11:04:23.438020 00: 1027 0002
383 11:04:23.438073
384 11:04:23.441764 01: 0000 0000
385 11:04:23.441841
386 11:04:23.441901 BP: 0C00 0251 [0000]
387 11:04:23.441955
388 11:04:23.444364 G0: 1182 0000
389 11:04:23.444461
390 11:04:23.444544 EC: 0004 0000 [0001]
391 11:04:23.444627
392 11:04:23.448101 S7: 0000 0000 [0000]
393 11:04:23.448180
394 11:04:23.451518 CC: 0000 0000 [0001]
395 11:04:23.451597
396 11:04:23.451656 T0: 0000 00DB [000F]
397 11:04:23.451710
398 11:04:23.451759 Jump to BL
399 11:04:23.451809
400 11:04:23.487056
401 11:04:23.487187
402 11:04:23.493811 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
403 11:04:23.497058 ARM64: Exception handlers installed.
404 11:04:23.500491 ARM64: Testing exception
405 11:04:23.503727 ARM64: Done test exception
406 11:04:23.507236 WDT: Last reset was cold boot
407 11:04:23.510750 SPI0(PAD0) initialized at 992727 Hz
408 11:04:23.514538 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
409 11:04:23.514631 Manufacturer: ef
410 11:04:23.521363 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
411 11:04:23.533688 Probing TPM: . done!
412 11:04:23.533816 TPM ready after 0 ms
413 11:04:23.540890 Connected to device vid:did:rid of 1ae0:0028:00
414 11:04:23.547242 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
415 11:04:23.551805 Initialized TPM device CR50 revision 0
416 11:04:23.593912 tlcl_send_startup: Startup return code is 0
417 11:04:23.594038 TPM: setup succeeded
418 11:04:23.603107 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
419 11:04:23.606426 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
420 11:04:23.609412 in-header: 03 19 00 00 08 00 00 00
421 11:04:23.612889 in-data: a2 e0 47 00 13 00 00 00
422 11:04:23.616106 Chrome EC: UHEPI supported
423 11:04:23.622751 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
424 11:04:23.626057 in-header: 03 a1 00 00 08 00 00 00
425 11:04:23.629476 in-data: 84 60 60 10 00 00 00 00
426 11:04:23.629568 Phase 1
427 11:04:23.632393 FMAP: area GBB found @ 3f5000 (12032 bytes)
428 11:04:23.639474 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
429 11:04:23.646047 VB2:vb2_check_recovery() Recovery was requested manually
430 11:04:23.649902 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
431 11:04:23.655943 Recovery requested (1009000e)
432 11:04:23.664272 tlcl_extend: response is 0
433 11:04:23.669697 tlcl_extend: response is 0
434 11:04:23.694322
435 11:04:23.694449
436 11:04:23.701779 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
437 11:04:23.704809 ARM64: Exception handlers installed.
438 11:04:23.707659 ARM64: Testing exception
439 11:04:23.711295 ARM64: Done test exception
440 11:04:23.726703 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x826a, sec=0x201b
441 11:04:23.733326 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
442 11:04:23.736647 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
443 11:04:23.744901 [RTC]rtc_get_frequency_meter,134: input=0xf, output=877
444 11:04:23.752270 [RTC]rtc_get_frequency_meter,134: input=0x7, output=744
445 11:04:23.758992 [RTC]rtc_get_frequency_meter,134: input=0xb, output=810
446 11:04:23.765677 [RTC]rtc_get_frequency_meter,134: input=0x9, output=777
447 11:04:23.773069 [RTC]rtc_get_frequency_meter,134: input=0xa, output=794
448 11:04:23.776071 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x826a
449 11:04:23.782820 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
450 11:04:23.786536 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
451 11:04:23.792973 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
452 11:04:23.795956 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
453 11:04:23.799088 in-header: 03 19 00 00 08 00 00 00
454 11:04:23.799164 in-data: a2 e0 47 00 13 00 00 00
455 11:04:23.802669 Chrome EC: UHEPI supported
456 11:04:23.809189 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
457 11:04:23.812838 in-header: 03 a1 00 00 08 00 00 00
458 11:04:23.816029 in-data: 84 60 60 10 00 00 00 00
459 11:04:23.819586 Skip loading cached calibration data
460 11:04:23.826172 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
461 11:04:23.828937 in-header: 03 a1 00 00 08 00 00 00
462 11:04:23.832870 in-data: 84 60 60 10 00 00 00 00
463 11:04:23.839334 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
464 11:04:23.842861 in-header: 03 a1 00 00 08 00 00 00
465 11:04:23.846176 in-data: 84 60 60 10 00 00 00 00
466 11:04:23.849242 ADC[3]: Raw value=217138 ID=1
467 11:04:23.849318 Manufacturer: ef
468 11:04:23.855598 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
469 11:04:23.859469 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
470 11:04:23.862382 CBFS @ 21000 size 3d4000
471 11:04:23.865832 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
472 11:04:23.872538 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
473 11:04:23.875862 CBFS: Found @ offset 3c700 size 44
474 11:04:23.879408 DRAM-K: Full Calibration
475 11:04:23.882277 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
476 11:04:23.886444 CBFS @ 21000 size 3d4000
477 11:04:23.889124 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
478 11:04:23.892487 CBFS: Locating 'fallback/dram'
479 11:04:23.895470 CBFS: Found @ offset 24b00 size 12268
480 11:04:23.924013 read SPI 0x45b44 0x1224c: 22775 us, 3263 KB/s, 26.104 Mbps
481 11:04:23.927474 ddr_geometry: 1, config: 0x0
482 11:04:23.930530 header.status = 0x0
483 11:04:23.934297 header.magic = 0x44524d4b (expected: 0x44524d4b)
484 11:04:23.937456 header.version = 0x5 (expected: 0x5)
485 11:04:23.940520 header.size = 0x8f0 (expected: 0x8f0)
486 11:04:23.940604 header.config = 0x0
487 11:04:23.944599 header.flags = 0x0
488 11:04:23.944675 header.checksum = 0x0
489 11:04:23.951463 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
490 11:04:23.957313 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
491 11:04:23.960727 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
492 11:04:23.964556 ddr_geometry:1
493 11:04:23.964632 [EMI] new MDL number = 1
494 11:04:23.967308 dram_cbt_mode_extern: 0
495 11:04:23.970943 dram_cbt_mode [RK0]: 0, [RK1]: 0
496 11:04:23.977468 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
497 11:04:23.977548
498 11:04:23.977605
499 11:04:23.977660 [Bianco] ETT version 0.0.0.1
500 11:04:23.984254 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
501 11:04:23.984333
502 11:04:23.987534 vSetVcoreByFreq with vcore:762500, freq=1600
503 11:04:23.987613
504 11:04:23.987704 [DramcInit]
505 11:04:23.991482 AutoRefreshCKEOff AutoREF OFF
506 11:04:23.994139 DDRPhyPLLSetting-CKEOFF
507 11:04:23.997267 DDRPhyPLLSetting-CKEON
508 11:04:23.997342
509 11:04:23.997400 Enable WDQS
510 11:04:24.001420 [ModeRegInit_LP4] CH0 RK0
511 11:04:24.004385 Write Rank0 MR13 =0x18
512 11:04:24.004461 Write Rank0 MR12 =0x5d
513 11:04:24.007745 Write Rank0 MR1 =0x56
514 11:04:24.011000 Write Rank0 MR2 =0x1a
515 11:04:24.011077 Write Rank0 MR11 =0x0
516 11:04:24.014270 Write Rank0 MR22 =0x38
517 11:04:24.014345 Write Rank0 MR14 =0x5d
518 11:04:24.018142 Write Rank0 MR3 =0x30
519 11:04:24.020926 Write Rank0 MR13 =0x58
520 11:04:24.021002 Write Rank0 MR12 =0x5d
521 11:04:24.024453 Write Rank0 MR1 =0x56
522 11:04:24.024529 Write Rank0 MR2 =0x2d
523 11:04:24.027927 Write Rank0 MR11 =0x23
524 11:04:24.031458 Write Rank0 MR22 =0x34
525 11:04:24.031560 Write Rank0 MR14 =0x10
526 11:04:24.034342 Write Rank0 MR3 =0x30
527 11:04:24.037657 Write Rank0 MR13 =0xd8
528 11:04:24.037733 [ModeRegInit_LP4] CH0 RK1
529 11:04:24.041124 Write Rank1 MR13 =0x18
530 11:04:24.041215 Write Rank1 MR12 =0x5d
531 11:04:24.044876 Write Rank1 MR1 =0x56
532 11:04:24.047583 Write Rank1 MR2 =0x1a
533 11:04:24.047658 Write Rank1 MR11 =0x0
534 11:04:24.051214 Write Rank1 MR22 =0x38
535 11:04:24.051289 Write Rank1 MR14 =0x5d
536 11:04:24.054445 Write Rank1 MR3 =0x30
537 11:04:24.058225 Write Rank1 MR13 =0x58
538 11:04:24.058300 Write Rank1 MR12 =0x5d
539 11:04:24.061184 Write Rank1 MR1 =0x56
540 11:04:24.061263 Write Rank1 MR2 =0x2d
541 11:04:24.064668 Write Rank1 MR11 =0x23
542 11:04:24.068341 Write Rank1 MR22 =0x34
543 11:04:24.068417 Write Rank1 MR14 =0x10
544 11:04:24.071860 Write Rank1 MR3 =0x30
545 11:04:24.074712 Write Rank1 MR13 =0xd8
546 11:04:24.074790 [ModeRegInit_LP4] CH1 RK0
547 11:04:24.077958 Write Rank0 MR13 =0x18
548 11:04:24.078034 Write Rank0 MR12 =0x5d
549 11:04:24.081962 Write Rank0 MR1 =0x56
550 11:04:24.084945 Write Rank0 MR2 =0x1a
551 11:04:24.085020 Write Rank0 MR11 =0x0
552 11:04:24.087949 Write Rank0 MR22 =0x38
553 11:04:24.088025 Write Rank0 MR14 =0x5d
554 11:04:24.092859 Write Rank0 MR3 =0x30
555 11:04:24.095419 Write Rank0 MR13 =0x58
556 11:04:24.095494 Write Rank0 MR12 =0x5d
557 11:04:24.098738 Write Rank0 MR1 =0x56
558 11:04:24.098817 Write Rank0 MR2 =0x2d
559 11:04:24.101688 Write Rank0 MR11 =0x23
560 11:04:24.104919 Write Rank0 MR22 =0x34
561 11:04:24.104995 Write Rank0 MR14 =0x10
562 11:04:24.108901 Write Rank0 MR3 =0x30
563 11:04:24.111549 Write Rank0 MR13 =0xd8
564 11:04:24.111626 [ModeRegInit_LP4] CH1 RK1
565 11:04:24.115224 Write Rank1 MR13 =0x18
566 11:04:24.115300 Write Rank1 MR12 =0x5d
567 11:04:24.118210 Write Rank1 MR1 =0x56
568 11:04:24.122497 Write Rank1 MR2 =0x1a
569 11:04:24.122577 Write Rank1 MR11 =0x0
570 11:04:24.124891 Write Rank1 MR22 =0x38
571 11:04:24.128833 Write Rank1 MR14 =0x5d
572 11:04:24.128910 Write Rank1 MR3 =0x30
573 11:04:24.131904 Write Rank1 MR13 =0x58
574 11:04:24.132004 Write Rank1 MR12 =0x5d
575 11:04:24.134962 Write Rank1 MR1 =0x56
576 11:04:24.138375 Write Rank1 MR2 =0x2d
577 11:04:24.138452 Write Rank1 MR11 =0x23
578 11:04:24.141835 Write Rank1 MR22 =0x34
579 11:04:24.141911 Write Rank1 MR14 =0x10
580 11:04:24.145429 Write Rank1 MR3 =0x30
581 11:04:24.148373 Write Rank1 MR13 =0xd8
582 11:04:24.148449 match AC timing 3
583 11:04:24.158333 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
584 11:04:24.158423 [MiockJmeterHQA]
585 11:04:24.164781 vSetVcoreByFreq with vcore:762500, freq=1600
586 11:04:24.254827
587 11:04:24.254956 MIOCK jitter meter ch=0
588 11:04:24.255027
589 11:04:24.258748 1T = (88-13) = 75 dly cells
590 11:04:24.264869 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 833/100 ps
591 11:04:24.268380 vSetVcoreByFreq with vcore:725000, freq=1200
592 11:04:24.354458
593 11:04:24.354580 MIOCK jitter meter ch=0
594 11:04:24.354641
595 11:04:24.357468 1T = (83-13) = 70 dly cells
596 11:04:24.364590 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 892/100 ps
597 11:04:24.367712 vSetVcoreByFreq with vcore:725000, freq=800
598 11:04:24.453718
599 11:04:24.453842 MIOCK jitter meter ch=0
600 11:04:24.453902
601 11:04:24.456931 1T = (83-13) = 70 dly cells
602 11:04:24.463441 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 892/100 ps
603 11:04:24.466977 vSetVcoreByFreq with vcore:762500, freq=1600
604 11:04:24.469998 vSetVcoreByFreq with vcore:762500, freq=1600
605 11:04:24.470075
606 11:04:24.470133 K DRVP
607 11:04:24.473713 1. OCD DRVP=0 CALOUT=0
608 11:04:24.476907 1. OCD DRVP=1 CALOUT=0
609 11:04:24.476983 1. OCD DRVP=2 CALOUT=0
610 11:04:24.480323 1. OCD DRVP=3 CALOUT=0
611 11:04:24.480400 1. OCD DRVP=4 CALOUT=0
612 11:04:24.483678 1. OCD DRVP=5 CALOUT=0
613 11:04:24.486860 1. OCD DRVP=6 CALOUT=0
614 11:04:24.486936 1. OCD DRVP=7 CALOUT=0
615 11:04:24.489993 1. OCD DRVP=8 CALOUT=0
616 11:04:24.493834 1. OCD DRVP=9 CALOUT=1
617 11:04:24.493933
618 11:04:24.496771 1. OCD DRVP calibration OK! DRVP=9
619 11:04:24.496863
620 11:04:24.496947
621 11:04:24.497028
622 11:04:24.497110 K ODTN
623 11:04:24.500878 3. OCD ODTN=0 ,CALOUT=1
624 11:04:24.500975 3. OCD ODTN=1 ,CALOUT=1
625 11:04:24.504388 3. OCD ODTN=2 ,CALOUT=1
626 11:04:24.504479 3. OCD ODTN=3 ,CALOUT=1
627 11:04:24.506940 3. OCD ODTN=4 ,CALOUT=1
628 11:04:24.510563 3. OCD ODTN=5 ,CALOUT=1
629 11:04:24.510654 3. OCD ODTN=6 ,CALOUT=1
630 11:04:24.513635 3. OCD ODTN=7 ,CALOUT=1
631 11:04:24.516885 3. OCD ODTN=8 ,CALOUT=0
632 11:04:24.516978
633 11:04:24.520264 3. OCD ODTN calibration OK! ODTN=8
634 11:04:24.520359
635 11:04:24.523546 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=8
636 11:04:24.527414 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15
637 11:04:24.530564 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15 (After Adjust)
638 11:04:24.533892
639 11:04:24.533989 K DRVP
640 11:04:24.534074 1. OCD DRVP=0 CALOUT=0
641 11:04:24.536967 1. OCD DRVP=1 CALOUT=0
642 11:04:24.540244 1. OCD DRVP=2 CALOUT=0
643 11:04:24.540321 1. OCD DRVP=3 CALOUT=0
644 11:04:24.543638 1. OCD DRVP=4 CALOUT=0
645 11:04:24.543715 1. OCD DRVP=5 CALOUT=0
646 11:04:24.546894 1. OCD DRVP=6 CALOUT=0
647 11:04:24.550926 1. OCD DRVP=7 CALOUT=0
648 11:04:24.551004 1. OCD DRVP=8 CALOUT=0
649 11:04:24.553846 1. OCD DRVP=9 CALOUT=0
650 11:04:24.557011 1. OCD DRVP=10 CALOUT=1
651 11:04:24.557114
652 11:04:24.560495 1. OCD DRVP calibration OK! DRVP=10
653 11:04:24.560592
654 11:04:24.560675
655 11:04:24.560759
656 11:04:24.560838 K ODTN
657 11:04:24.564259 3. OCD ODTN=0 ,CALOUT=1
658 11:04:24.564336 3. OCD ODTN=1 ,CALOUT=1
659 11:04:24.567211 3. OCD ODTN=2 ,CALOUT=1
660 11:04:24.570911 3. OCD ODTN=3 ,CALOUT=1
661 11:04:24.570988 3. OCD ODTN=4 ,CALOUT=1
662 11:04:24.574008 3. OCD ODTN=5 ,CALOUT=1
663 11:04:24.574085 3. OCD ODTN=6 ,CALOUT=1
664 11:04:24.577158 3. OCD ODTN=7 ,CALOUT=1
665 11:04:24.580519 3. OCD ODTN=8 ,CALOUT=1
666 11:04:24.580596 3. OCD ODTN=9 ,CALOUT=1
667 11:04:24.583950 3. OCD ODTN=10 ,CALOUT=1
668 11:04:24.588100 3. OCD ODTN=11 ,CALOUT=1
669 11:04:24.588177 3. OCD ODTN=12 ,CALOUT=1
670 11:04:24.591078 3. OCD ODTN=13 ,CALOUT=1
671 11:04:24.594056 3. OCD ODTN=14 ,CALOUT=1
672 11:04:24.594132 3. OCD ODTN=15 ,CALOUT=0
673 11:04:24.594192
674 11:04:24.597394 3. OCD ODTN calibration OK! ODTN=15
675 11:04:24.597472
676 11:04:24.604313 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
677 11:04:24.607433 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
678 11:04:24.611270 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
679 11:04:24.611348
680 11:04:24.614173 [DramcInit]
681 11:04:24.617971 AutoRefreshCKEOff AutoREF OFF
682 11:04:24.618046 DDRPhyPLLSetting-CKEOFF
683 11:04:24.620478 DDRPhyPLLSetting-CKEON
684 11:04:24.620553
685 11:04:24.620612 Enable WDQS
686 11:04:24.620666 ==
687 11:04:24.627382 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
688 11:04:24.630556 fsp= 1, odt_onoff= 1, Byte mode= 0
689 11:04:24.630673 ==
690 11:04:24.634240 [Duty_Offset_Calibration]
691 11:04:24.634316
692 11:04:24.634375 ===========================
693 11:04:24.637290 B0:0 B1:0 CA:2
694 11:04:24.657905 ==
695 11:04:24.661664 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
696 11:04:24.664995 fsp= 1, odt_onoff= 1, Byte mode= 0
697 11:04:24.665071 ==
698 11:04:24.668291 [Duty_Offset_Calibration]
699 11:04:24.668366
700 11:04:24.671080 ===========================
701 11:04:24.671156 B0:0 B1:1 CA:1
702 11:04:24.704404 [ModeRegInit_LP4] CH0 RK0
703 11:04:24.708163 Write Rank0 MR13 =0x18
704 11:04:24.708239 Write Rank0 MR12 =0x5d
705 11:04:24.711400 Write Rank0 MR1 =0x56
706 11:04:24.714828 Write Rank0 MR2 =0x1a
707 11:04:24.714904 Write Rank0 MR11 =0x0
708 11:04:24.717908 Write Rank0 MR22 =0x38
709 11:04:24.717984 Write Rank0 MR14 =0x5d
710 11:04:24.721174 Write Rank0 MR3 =0x30
711 11:04:24.724934 Write Rank0 MR13 =0x58
712 11:04:24.725010 Write Rank0 MR12 =0x5d
713 11:04:24.728110 Write Rank0 MR1 =0x56
714 11:04:24.728186 Write Rank0 MR2 =0x2d
715 11:04:24.731357 Write Rank0 MR11 =0x23
716 11:04:24.734795 Write Rank0 MR22 =0x34
717 11:04:24.734871 Write Rank0 MR14 =0x10
718 11:04:24.738016 Write Rank0 MR3 =0x30
719 11:04:24.741391 Write Rank0 MR13 =0xd8
720 11:04:24.741471 [ModeRegInit_LP4] CH0 RK1
721 11:04:24.744622 Write Rank1 MR13 =0x18
722 11:04:24.744698 Write Rank1 MR12 =0x5d
723 11:04:24.747763 Write Rank1 MR1 =0x56
724 11:04:24.751374 Write Rank1 MR2 =0x1a
725 11:04:24.751451 Write Rank1 MR11 =0x0
726 11:04:24.755037 Write Rank1 MR22 =0x38
727 11:04:24.755112 Write Rank1 MR14 =0x5d
728 11:04:24.757797 Write Rank1 MR3 =0x30
729 11:04:24.762067 Write Rank1 MR13 =0x58
730 11:04:24.762143 Write Rank1 MR12 =0x5d
731 11:04:24.764825 Write Rank1 MR1 =0x56
732 11:04:24.764901 Write Rank1 MR2 =0x2d
733 11:04:24.768244 Write Rank1 MR11 =0x23
734 11:04:24.771499 Write Rank1 MR22 =0x34
735 11:04:24.771575 Write Rank1 MR14 =0x10
736 11:04:24.775275 Write Rank1 MR3 =0x30
737 11:04:24.778754 Write Rank1 MR13 =0xd8
738 11:04:24.778831 [ModeRegInit_LP4] CH1 RK0
739 11:04:24.782014 Write Rank0 MR13 =0x18
740 11:04:24.782091 Write Rank0 MR12 =0x5d
741 11:04:24.785047 Write Rank0 MR1 =0x56
742 11:04:24.788155 Write Rank0 MR2 =0x1a
743 11:04:24.788231 Write Rank0 MR11 =0x0
744 11:04:24.791484 Write Rank0 MR22 =0x38
745 11:04:24.791560 Write Rank0 MR14 =0x5d
746 11:04:24.794780 Write Rank0 MR3 =0x30
747 11:04:24.798711 Write Rank0 MR13 =0x58
748 11:04:24.798788 Write Rank0 MR12 =0x5d
749 11:04:24.801822 Write Rank0 MR1 =0x56
750 11:04:24.801899 Write Rank0 MR2 =0x2d
751 11:04:24.804856 Write Rank0 MR11 =0x23
752 11:04:24.808428 Write Rank0 MR22 =0x34
753 11:04:24.808505 Write Rank0 MR14 =0x10
754 11:04:24.811734 Write Rank0 MR3 =0x30
755 11:04:24.815761 Write Rank0 MR13 =0xd8
756 11:04:24.815838 [ModeRegInit_LP4] CH1 RK1
757 11:04:24.818272 Write Rank1 MR13 =0x18
758 11:04:24.818349 Write Rank1 MR12 =0x5d
759 11:04:24.821797 Write Rank1 MR1 =0x56
760 11:04:24.825387 Write Rank1 MR2 =0x1a
761 11:04:24.825468 Write Rank1 MR11 =0x0
762 11:04:24.828436 Write Rank1 MR22 =0x38
763 11:04:24.828511 Write Rank1 MR14 =0x5d
764 11:04:24.831681 Write Rank1 MR3 =0x30
765 11:04:24.835283 Write Rank1 MR13 =0x58
766 11:04:24.835360 Write Rank1 MR12 =0x5d
767 11:04:24.838605 Write Rank1 MR1 =0x56
768 11:04:24.838681 Write Rank1 MR2 =0x2d
769 11:04:24.842067 Write Rank1 MR11 =0x23
770 11:04:24.845209 Write Rank1 MR22 =0x34
771 11:04:24.845301 Write Rank1 MR14 =0x10
772 11:04:24.848843 Write Rank1 MR3 =0x30
773 11:04:24.852635 Write Rank1 MR13 =0xd8
774 11:04:24.852713 match AC timing 3
775 11:04:24.862126 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
776 11:04:24.862230 DramC Write-DBI off
777 11:04:24.865752 DramC Read-DBI off
778 11:04:24.869024 Write Rank0 MR13 =0x59
779 11:04:24.869133 ==
780 11:04:24.872041 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
781 11:04:24.875148 fsp= 1, odt_onoff= 1, Byte mode= 0
782 11:04:24.875224 ==
783 11:04:24.879025 === u2Vref_new: 0x56 --> 0x2d
784 11:04:24.881884 === u2Vref_new: 0x58 --> 0x38
785 11:04:24.885372 === u2Vref_new: 0x5a --> 0x39
786 11:04:24.888800 === u2Vref_new: 0x5c --> 0x3c
787 11:04:24.892629 === u2Vref_new: 0x5e --> 0x3d
788 11:04:24.895627 === u2Vref_new: 0x60 --> 0xa0
789 11:04:24.898910 [CA 0] Center 35 (8~63) winsize 56
790 11:04:24.901814 [CA 1] Center 36 (10~63) winsize 54
791 11:04:24.905407 [CA 2] Center 31 (3~60) winsize 58
792 11:04:24.908740 [CA 3] Center 27 (-1~55) winsize 57
793 11:04:24.908840 [CA 4] Center 27 (-1~56) winsize 58
794 11:04:24.911873 [CA 5] Center 32 (2~62) winsize 61
795 11:04:24.911973
796 11:04:24.918825 [CATrainingPosCal] consider 1 rank data
797 11:04:24.918929 u2DelayCellTimex100 = 833/100 ps
798 11:04:24.922456 CA0 delay=35 (8~63),Diff = 8 PI (9 cell)
799 11:04:24.929008 CA1 delay=36 (10~63),Diff = 9 PI (10 cell)
800 11:04:24.932202 CA2 delay=31 (3~60),Diff = 4 PI (4 cell)
801 11:04:24.935871 CA3 delay=27 (-1~55),Diff = 0 PI (0 cell)
802 11:04:24.938733 CA4 delay=27 (-1~56),Diff = 0 PI (0 cell)
803 11:04:24.941876 CA5 delay=32 (2~62),Diff = 5 PI (5 cell)
804 11:04:24.941952
805 11:04:24.945782 CA PerBit enable=1, Macro0, CA PI delay=27
806 11:04:24.948503 === u2Vref_new: 0x60 --> 0xa0
807 11:04:24.948580
808 11:04:24.951863 Vref(ca) range 1: 32
809 11:04:24.951939
810 11:04:24.951998 CS Dly= 10 (41-0-32)
811 11:04:24.955604 Write Rank0 MR13 =0xd8
812 11:04:24.959351 Write Rank0 MR13 =0xd8
813 11:04:24.959427 Write Rank0 MR12 =0x60
814 11:04:24.962087 Write Rank1 MR13 =0x59
815 11:04:24.962162 ==
816 11:04:24.965458 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
817 11:04:24.968911 fsp= 1, odt_onoff= 1, Byte mode= 0
818 11:04:24.968986 ==
819 11:04:24.971971 === u2Vref_new: 0x56 --> 0x2d
820 11:04:24.975280 === u2Vref_new: 0x58 --> 0x38
821 11:04:24.978761 === u2Vref_new: 0x5a --> 0x39
822 11:04:24.981911 === u2Vref_new: 0x5c --> 0x3c
823 11:04:24.985642 === u2Vref_new: 0x5e --> 0x3d
824 11:04:24.988678 === u2Vref_new: 0x60 --> 0xa0
825 11:04:24.992071 [CA 0] Center 37 (11~63) winsize 53
826 11:04:24.995819 [CA 1] Center 37 (11~63) winsize 53
827 11:04:24.998785 [CA 2] Center 32 (3~62) winsize 60
828 11:04:25.002221 [CA 3] Center 27 (-1~55) winsize 57
829 11:04:25.005124 [CA 4] Center 26 (-2~55) winsize 58
830 11:04:25.009306 [CA 5] Center 32 (2~62) winsize 61
831 11:04:25.009384
832 11:04:25.012044 [CATrainingPosCal] consider 2 rank data
833 11:04:25.015515 u2DelayCellTimex100 = 833/100 ps
834 11:04:25.019259 CA0 delay=37 (11~63),Diff = 10 PI (11 cell)
835 11:04:25.022137 CA1 delay=37 (11~63),Diff = 10 PI (11 cell)
836 11:04:25.025579 CA2 delay=31 (3~60),Diff = 4 PI (4 cell)
837 11:04:25.029224 CA3 delay=27 (-1~55),Diff = 0 PI (0 cell)
838 11:04:25.032319 CA4 delay=27 (-1~55),Diff = 0 PI (0 cell)
839 11:04:25.035925 CA5 delay=32 (2~62),Diff = 5 PI (5 cell)
840 11:04:25.036002
841 11:04:25.038734 CA PerBit enable=1, Macro0, CA PI delay=27
842 11:04:25.042163 === u2Vref_new: 0x5e --> 0x3d
843 11:04:25.042244
844 11:04:25.045588 Vref(ca) range 1: 30
845 11:04:25.045664
846 11:04:25.045722 CS Dly= 8 (39-0-32)
847 11:04:25.049044 Write Rank1 MR13 =0xd8
848 11:04:25.052645 Write Rank1 MR13 =0xd8
849 11:04:25.052721 Write Rank1 MR12 =0x5e
850 11:04:25.055568 [RankSwap] Rank num 2, (Multi 1), Rank 0
851 11:04:25.058604 Write Rank0 MR2 =0xad
852 11:04:25.058681 [Write Leveling]
853 11:04:25.062084 delay byte0 byte1 byte2 byte3
854 11:04:25.062160
855 11:04:25.065564 10 0 0
856 11:04:25.065642 11 0 0
857 11:04:25.069000 12 0 0
858 11:04:25.069076 13 0 0
859 11:04:25.069173 14 0 0
860 11:04:25.072287 15 0 0
861 11:04:25.072369 16 0 0
862 11:04:25.075403 17 0 0
863 11:04:25.075483 18 0 0
864 11:04:25.079713 19 0 0
865 11:04:25.079791 20 0 0
866 11:04:25.079850 21 0 0
867 11:04:25.082414 22 0 0
868 11:04:25.082490 23 0 0
869 11:04:25.085480 24 0 ff
870 11:04:25.085557 25 0 ff
871 11:04:25.085617 26 0 ff
872 11:04:25.089571 27 0 ff
873 11:04:25.089647 28 0 ff
874 11:04:25.092204 29 0 ff
875 11:04:25.092281 30 0 ff
876 11:04:25.095520 31 0 ff
877 11:04:25.095597 32 ff ff
878 11:04:25.099181 33 ff ff
879 11:04:25.099259 34 ff ff
880 11:04:25.102333 35 ff ff
881 11:04:25.102411 36 ff ff
882 11:04:25.102472 37 ff ff
883 11:04:25.105603 38 ff ff
884 11:04:25.108850 pass bytecount = 0xff (0xff: all bytes pass)
885 11:04:25.108926
886 11:04:25.112908 DQS0 dly: 32
887 11:04:25.112984 DQS1 dly: 24
888 11:04:25.115351 Write Rank0 MR2 =0x2d
889 11:04:25.119486 [RankSwap] Rank num 2, (Multi 1), Rank 0
890 11:04:25.119562 Write Rank0 MR1 =0xd6
891 11:04:25.119621 [Gating]
892 11:04:25.122483 ==
893 11:04:25.125882 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
894 11:04:25.129577 fsp= 1, odt_onoff= 1, Byte mode= 0
895 11:04:25.129655 ==
896 11:04:25.133316 3 1 0 |3534 3535 |(11 11)(11 11) |(0 0)(0 0)| 0
897 11:04:25.139416 3 1 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
898 11:04:25.142933 3 1 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
899 11:04:25.146032 3 1 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
900 11:04:25.152365 3 1 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
901 11:04:25.156189 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
902 11:04:25.159380 3 1 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
903 11:04:25.162740 3 1 28 |3534 3535 |(11 11)(11 11) |(0 0)(0 0)| 0
904 11:04:25.169133 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
905 11:04:25.173012 3 2 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
906 11:04:25.176308 3 2 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
907 11:04:25.182592 3 2 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
908 11:04:25.186536 3 2 16 |706 201 |(11 11)(11 11) |(1 1)(1 1)| 0
909 11:04:25.189945 3 2 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
910 11:04:25.196043 3 2 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
911 11:04:25.199788 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 11:04:25.202774 [Byte 1] Lead/lag Transition tap number (1)
913 11:04:25.206396 3 3 0 |3d3d 3c3c |(11 11)(11 11) |(1 1)(0 0)| 0
914 11:04:25.212853 3 3 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
915 11:04:25.216309 3 3 8 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
916 11:04:25.219536 3 3 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
917 11:04:25.226332 3 3 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
918 11:04:25.229936 3 3 20 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
919 11:04:25.232702 3 3 24 |3534 2f2e |(11 11)(11 11) |(1 1)(1 1)| 0
920 11:04:25.236068 [Byte 0] Lead/lag Transition tap number (1)
921 11:04:25.239511 [Byte 1] Lead/lag Transition tap number (1)
922 11:04:25.245996 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
923 11:04:25.249491 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
924 11:04:25.253036 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
925 11:04:25.259335 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
926 11:04:25.263201 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
927 11:04:25.265927 3 4 16 |707 c0b |(11 11)(11 11) |(0 1)(0 1)| 0
928 11:04:25.273399 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 11:04:25.275987 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 11:04:25.279742 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 11:04:25.283418 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 11:04:25.289402 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 11:04:25.293066 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 11:04:25.296486 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 11:04:25.302940 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 11:04:25.306303 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
937 11:04:25.310065 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
938 11:04:25.316273 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
939 11:04:25.319351 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
940 11:04:25.322865 [Byte 0] Lead/lag falling Transition (3, 6, 0)
941 11:04:25.326254 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
942 11:04:25.332971 [Byte 1] Lead/lag falling Transition (3, 6, 4)
943 11:04:25.336350 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
944 11:04:25.339469 [Byte 0] Lead/lag Transition tap number (3)
945 11:04:25.342671 3 6 12 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
946 11:04:25.349593 [Byte 1] Lead/lag Transition tap number (3)
947 11:04:25.353371 3 6 16 |202 202 |(11 11)(11 11) |(0 0)(0 0)| 0
948 11:04:25.356397 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 11:04:25.359392 [Byte 0]First pass (3, 6, 20)
950 11:04:25.363523 [Byte 1]First pass (3, 6, 20)
951 11:04:25.366846 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 11:04:25.369759 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 11:04:25.372884 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 11:04:25.376404 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 11:04:25.383139 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
956 11:04:25.386276 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
957 11:04:25.389823 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
958 11:04:25.393206 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
959 11:04:25.396706 All bytes gating window > 1UI, Early break!
960 11:04:25.396809
961 11:04:25.403214 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
962 11:04:25.403325
963 11:04:25.406740 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
964 11:04:25.406842
965 11:04:25.406928
966 11:04:25.407010
967 11:04:25.410192 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
968 11:04:25.410293
969 11:04:25.413875 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
970 11:04:25.413977
971 11:04:25.414062
972 11:04:25.416534 Write Rank0 MR1 =0x56
973 11:04:25.416676
974 11:04:25.419853 best RODT dly(2T, 0.5T) = (2, 3)
975 11:04:25.419939
976 11:04:25.423244 best RODT dly(2T, 0.5T) = (2, 3)
977 11:04:25.423343 ==
978 11:04:25.427323 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
979 11:04:25.430559 fsp= 1, odt_onoff= 1, Byte mode= 0
980 11:04:25.430661 ==
981 11:04:25.436808 Start DQ dly to find pass range UseTestEngine =0
982 11:04:25.439869 x-axis: bit #, y-axis: DQ dly (-127~63)
983 11:04:25.440004 RX Vref Scan = 0
984 11:04:25.443270 -26, [0] xxxxxxxx xxxxxxxx [MSB]
985 11:04:25.447130 -25, [0] xxxxxxxx xxxxxxxx [MSB]
986 11:04:25.450040 -24, [0] xxxxxxxx xxxxxxxx [MSB]
987 11:04:25.453507 -23, [0] xxxxxxxx xxxxxxxx [MSB]
988 11:04:25.456547 -22, [0] xxxxxxxx xxxxxxxx [MSB]
989 11:04:25.456625 -21, [0] xxxxxxxx xxxxxxxx [MSB]
990 11:04:25.460119 -20, [0] xxxxxxxx xxxxxxxx [MSB]
991 11:04:25.463715 -19, [0] xxxxxxxx xxxxxxxx [MSB]
992 11:04:25.467504 -18, [0] xxxxxxxx xxxxxxxx [MSB]
993 11:04:25.472212 -17, [0] xxxxxxxx xxxxxxxx [MSB]
994 11:04:25.473575 -16, [0] xxxxxxxx xxxxxxxx [MSB]
995 11:04:25.476603 -15, [0] xxxxxxxx xxxxxxxx [MSB]
996 11:04:25.479924 -14, [0] xxxxxxxx xxxxxxxx [MSB]
997 11:04:25.480000 -13, [0] xxxxxxxx xxxxxxxx [MSB]
998 11:04:25.483459 -12, [0] xxxxxxxx xxxxxxxx [MSB]
999 11:04:25.486778 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1000 11:04:25.490052 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1001 11:04:25.493985 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1002 11:04:25.497112 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1003 11:04:25.500436 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1004 11:04:25.500518 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1005 11:04:25.503977 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1006 11:04:25.507134 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1007 11:04:25.510308 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1008 11:04:25.513687 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1009 11:04:25.517393 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1010 11:04:25.517469 0, [0] xxxxxxxx xxxxxxxx [MSB]
1011 11:04:25.520798 1, [0] xxxxxxxx xxxxxxxx [MSB]
1012 11:04:25.523926 2, [0] xxxoxxxx xxxxxxxx [MSB]
1013 11:04:25.527420 3, [0] xxxoxoxx oxxoxxxx [MSB]
1014 11:04:25.530602 4, [0] xxxoxoxx oxxoxxxx [MSB]
1015 11:04:25.534138 5, [0] xxxoxoxx ooxoxoxx [MSB]
1016 11:04:25.534247 6, [0] xxxoxooo ooxoooox [MSB]
1017 11:04:25.537436 7, [0] ooxoxooo ooxoooox [MSB]
1018 11:04:25.540650 8, [0] ooxoxooo ooxooooo [MSB]
1019 11:04:25.544101 9, [0] oooooooo ooxooooo [MSB]
1020 11:04:25.547305 10, [0] oooooooo ooxooooo [MSB]
1021 11:04:25.550634 31, [0] oooooooo oooooooo [MSB]
1022 11:04:25.550711 32, [0] oooxoooo oooooooo [MSB]
1023 11:04:25.553914 33, [0] oooxoooo xooooooo [MSB]
1024 11:04:25.557586 34, [0] oooxoooo xooooooo [MSB]
1025 11:04:25.560465 35, [0] oooxoooo xooxoooo [MSB]
1026 11:04:25.563813 36, [0] oooxoxxo xxoxxooo [MSB]
1027 11:04:25.567592 37, [0] oooxoxxo xxoxxoxo [MSB]
1028 11:04:25.570954 38, [0] oooxoxxo xxoxxxxo [MSB]
1029 11:04:25.571034 39, [0] oxoxoxxx xxoxxxxo [MSB]
1030 11:04:25.574408 40, [0] xxoxxxxx xxoxxxxo [MSB]
1031 11:04:25.577708 41, [0] xxoxxxxx xxoxxxxx [MSB]
1032 11:04:25.580937 42, [0] xxxxxxxx xxxxxxxx [MSB]
1033 11:04:25.583800 iDelay=42, Bit 0, Center 23 (7 ~ 39) 33
1034 11:04:25.587183 iDelay=42, Bit 1, Center 22 (7 ~ 38) 32
1035 11:04:25.591297 iDelay=42, Bit 2, Center 25 (9 ~ 41) 33
1036 11:04:25.594591 iDelay=42, Bit 3, Center 16 (2 ~ 31) 30
1037 11:04:25.597215 iDelay=42, Bit 4, Center 24 (9 ~ 39) 31
1038 11:04:25.600778 iDelay=42, Bit 5, Center 19 (3 ~ 35) 33
1039 11:04:25.604318 iDelay=42, Bit 6, Center 20 (6 ~ 35) 30
1040 11:04:25.607395 iDelay=42, Bit 7, Center 22 (6 ~ 38) 33
1041 11:04:25.611288 iDelay=42, Bit 8, Center 17 (3 ~ 32) 30
1042 11:04:25.617600 iDelay=42, Bit 9, Center 20 (5 ~ 35) 31
1043 11:04:25.620656 iDelay=42, Bit 10, Center 26 (11 ~ 41) 31
1044 11:04:25.624179 iDelay=42, Bit 11, Center 18 (3 ~ 34) 32
1045 11:04:25.627394 iDelay=42, Bit 12, Center 20 (6 ~ 35) 30
1046 11:04:25.630656 iDelay=42, Bit 13, Center 21 (5 ~ 37) 33
1047 11:04:25.634636 iDelay=42, Bit 14, Center 21 (6 ~ 36) 31
1048 11:04:25.637502 iDelay=42, Bit 15, Center 24 (8 ~ 40) 33
1049 11:04:25.637580 ==
1050 11:04:25.644340 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1051 11:04:25.647323 fsp= 1, odt_onoff= 1, Byte mode= 0
1052 11:04:25.647401 ==
1053 11:04:25.647459 DQS Delay:
1054 11:04:25.647513 DQS0 = 0, DQS1 = 0
1055 11:04:25.650901 DQM Delay:
1056 11:04:25.650976 DQM0 = 21, DQM1 = 20
1057 11:04:25.654068 DQ Delay:
1058 11:04:25.657444 DQ0 =23, DQ1 =22, DQ2 =25, DQ3 =16
1059 11:04:25.657519 DQ4 =24, DQ5 =19, DQ6 =20, DQ7 =22
1060 11:04:25.660782 DQ8 =17, DQ9 =20, DQ10 =26, DQ11 =18
1061 11:04:25.664195 DQ12 =20, DQ13 =21, DQ14 =21, DQ15 =24
1062 11:04:25.667653
1063 11:04:25.667728
1064 11:04:25.667786 DramC Write-DBI off
1065 11:04:25.667840 ==
1066 11:04:25.674408 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1067 11:04:25.677557 fsp= 1, odt_onoff= 1, Byte mode= 0
1068 11:04:25.677634 ==
1069 11:04:25.680881 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1070 11:04:25.680956
1071 11:04:25.684103 Begin, DQ Scan Range 920~1176
1072 11:04:25.684178
1073 11:04:25.684236
1074 11:04:25.687832 TX Vref Scan disable
1075 11:04:25.691002 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1076 11:04:25.694177 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1077 11:04:25.697689 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1078 11:04:25.701012 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1079 11:04:25.704706 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1080 11:04:25.708066 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1081 11:04:25.711386 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1082 11:04:25.715309 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1083 11:04:25.717980 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1084 11:04:25.721107 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1085 11:04:25.724936 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1086 11:04:25.727985 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1087 11:04:25.731190 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1088 11:04:25.734698 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1089 11:04:25.738118 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1090 11:04:25.741256 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1091 11:04:25.748162 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1092 11:04:25.751475 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1093 11:04:25.754565 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1094 11:04:25.757857 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1095 11:04:25.761609 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1096 11:04:25.765752 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1097 11:04:25.767925 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1098 11:04:25.771505 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1099 11:04:25.774971 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1100 11:04:25.778465 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1101 11:04:25.781299 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1102 11:04:25.784897 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1103 11:04:25.788132 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1104 11:04:25.791398 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1105 11:04:25.795131 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1106 11:04:25.798309 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1107 11:04:25.801479 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1108 11:04:25.804854 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1109 11:04:25.808752 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1110 11:04:25.815090 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1111 11:04:25.818332 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1112 11:04:25.821322 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1113 11:04:25.824951 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1114 11:04:25.827985 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1115 11:04:25.831804 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1116 11:04:25.834933 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1117 11:04:25.838275 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1118 11:04:25.842101 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1119 11:04:25.845300 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1120 11:04:25.848733 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1121 11:04:25.852402 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1122 11:04:25.855249 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1123 11:04:25.859277 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1124 11:04:25.861657 969 |3 6 9|[0] xxxxxxxx ooxoooxx [MSB]
1125 11:04:25.865499 970 |3 6 10|[0] xxxxxxxx ooxoooxx [MSB]
1126 11:04:25.868340 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1127 11:04:25.871938 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1128 11:04:25.875027 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1129 11:04:25.878872 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1130 11:04:25.881831 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1131 11:04:25.884919 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1132 11:04:25.888255 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1133 11:04:25.895131 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1134 11:04:25.898713 979 |3 6 19|[0] xxxooooo oooooooo [MSB]
1135 11:04:25.901778 980 |3 6 20|[0] xooooooo oooooooo [MSB]
1136 11:04:25.905238 989 |3 6 29|[0] oooooooo xooxoooo [MSB]
1137 11:04:25.908736 990 |3 6 30|[0] oooooooo xooxxxoo [MSB]
1138 11:04:25.912171 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1139 11:04:25.915479 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1140 11:04:25.918698 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1141 11:04:25.922369 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1142 11:04:25.925134 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1143 11:04:25.928660 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1144 11:04:25.935440 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1145 11:04:25.938807 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1146 11:04:25.942234 Byte0, DQ PI dly=987, DQM PI dly= 987
1147 11:04:25.945422 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
1148 11:04:25.945500
1149 11:04:25.948861 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
1150 11:04:25.948937
1151 11:04:25.952030 Byte1, DQ PI dly=980, DQM PI dly= 980
1152 11:04:25.958846 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1153 11:04:25.958924
1154 11:04:25.962656 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1155 11:04:25.962733
1156 11:04:25.962791 ==
1157 11:04:25.965937 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1158 11:04:25.968997 fsp= 1, odt_onoff= 1, Byte mode= 0
1159 11:04:25.972342 ==
1160 11:04:25.975859 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1161 11:04:25.975935
1162 11:04:25.979007 Begin, DQ Scan Range 956~1020
1163 11:04:25.979082 Write Rank0 MR14 =0x0
1164 11:04:25.987439
1165 11:04:25.987516 CH=0, VrefRange= 0, VrefLevel = 0
1166 11:04:25.994140 TX Bit0 (984~993) 10 988, Bit8 (970~982) 13 976,
1167 11:04:25.997868 TX Bit1 (981~994) 14 987, Bit9 (972~986) 15 979,
1168 11:04:26.004121 TX Bit2 (984~994) 11 989, Bit10 (979~988) 10 983,
1169 11:04:26.007672 TX Bit3 (978~991) 14 984, Bit11 (972~983) 12 977,
1170 11:04:26.010958 TX Bit4 (981~994) 14 987, Bit12 (972~986) 15 979,
1171 11:04:26.017778 TX Bit5 (980~989) 10 984, Bit13 (973~985) 13 979,
1172 11:04:26.021035 TX Bit6 (980~992) 13 986, Bit14 (974~987) 14 980,
1173 11:04:26.024140 TX Bit7 (981~994) 14 987, Bit15 (977~989) 13 983,
1174 11:04:26.024243
1175 11:04:26.027434 Write Rank0 MR14 =0x2
1176 11:04:26.035585
1177 11:04:26.035664 CH=0, VrefRange= 0, VrefLevel = 2
1178 11:04:26.042304 TX Bit0 (983~994) 12 988, Bit8 (969~983) 15 976,
1179 11:04:26.045854 TX Bit1 (981~995) 15 988, Bit9 (972~986) 15 979,
1180 11:04:26.052130 TX Bit2 (982~995) 14 988, Bit10 (977~988) 12 982,
1181 11:04:26.055683 TX Bit3 (978~991) 14 984, Bit11 (971~984) 14 977,
1182 11:04:26.059405 TX Bit4 (981~994) 14 987, Bit12 (972~986) 15 979,
1183 11:04:26.065839 TX Bit5 (980~991) 12 985, Bit13 (972~986) 15 979,
1184 11:04:26.069236 TX Bit6 (980~992) 13 986, Bit14 (973~988) 16 980,
1185 11:04:26.072386 TX Bit7 (980~994) 15 987, Bit15 (977~990) 14 983,
1186 11:04:26.072461
1187 11:04:26.075557 Write Rank0 MR14 =0x4
1188 11:04:26.084197
1189 11:04:26.084274 CH=0, VrefRange= 0, VrefLevel = 4
1190 11:04:26.090883 TX Bit0 (983~994) 12 988, Bit8 (969~984) 16 976,
1191 11:04:26.093912 TX Bit1 (980~996) 17 988, Bit9 (971~987) 17 979,
1192 11:04:26.100715 TX Bit2 (982~996) 15 989, Bit10 (976~989) 14 982,
1193 11:04:26.103776 TX Bit3 (978~992) 15 985, Bit11 (971~985) 15 978,
1194 11:04:26.107321 TX Bit4 (980~995) 16 987, Bit12 (972~987) 16 979,
1195 11:04:26.113768 TX Bit5 (980~992) 13 986, Bit13 (972~987) 16 979,
1196 11:04:26.117400 TX Bit6 (979~993) 15 986, Bit14 (974~988) 15 981,
1197 11:04:26.120487 TX Bit7 (980~995) 16 987, Bit15 (977~990) 14 983,
1198 11:04:26.120563
1199 11:04:26.123797 Write Rank0 MR14 =0x6
1200 11:04:26.132088
1201 11:04:26.132187 CH=0, VrefRange= 0, VrefLevel = 6
1202 11:04:26.138561 TX Bit0 (983~995) 13 989, Bit8 (969~984) 16 976,
1203 11:04:26.142344 TX Bit1 (980~996) 17 988, Bit9 (972~988) 17 980,
1204 11:04:26.149095 TX Bit2 (982~996) 15 989, Bit10 (976~990) 15 983,
1205 11:04:26.151908 TX Bit3 (978~992) 15 985, Bit11 (970~985) 16 977,
1206 11:04:26.155562 TX Bit4 (980~995) 16 987, Bit12 (971~988) 18 979,
1207 11:04:26.162097 TX Bit5 (980~992) 13 986, Bit13 (971~987) 17 979,
1208 11:04:26.165533 TX Bit6 (979~993) 15 986, Bit14 (972~989) 18 980,
1209 11:04:26.168797 TX Bit7 (980~996) 17 988, Bit15 (977~991) 15 984,
1210 11:04:26.168873
1211 11:04:26.171961 Write Rank0 MR14 =0x8
1212 11:04:26.180508
1213 11:04:26.180586 CH=0, VrefRange= 0, VrefLevel = 8
1214 11:04:26.187178 TX Bit0 (981~996) 16 988, Bit8 (968~985) 18 976,
1215 11:04:26.190873 TX Bit1 (980~997) 18 988, Bit9 (971~988) 18 979,
1216 11:04:26.197236 TX Bit2 (982~997) 16 989, Bit10 (976~991) 16 983,
1217 11:04:26.200547 TX Bit3 (978~992) 15 985, Bit11 (970~986) 17 978,
1218 11:04:26.203663 TX Bit4 (980~996) 17 988, Bit12 (971~988) 18 979,
1219 11:04:26.258039 TX Bit5 (980~992) 13 986, Bit13 (971~988) 18 979,
1220 11:04:26.258171 TX Bit6 (979~994) 16 986, Bit14 (973~989) 17 981,
1221 11:04:26.258606 TX Bit7 (980~996) 17 988, Bit15 (976~991) 16 983,
1222 11:04:26.258682
1223 11:04:26.258922 Write Rank0 MR14 =0xa
1224 11:04:26.258984
1225 11:04:26.259038 CH=0, VrefRange= 0, VrefLevel = 10
1226 11:04:26.259277 TX Bit0 (981~996) 16 988, Bit8 (968~986) 19 977,
1227 11:04:26.259600 TX Bit1 (980~998) 19 989, Bit9 (970~988) 19 979,
1228 11:04:26.259856 TX Bit2 (981~998) 18 989, Bit10 (975~991) 17 983,
1229 11:04:26.260282 TX Bit3 (977~993) 17 985, Bit11 (969~987) 19 978,
1230 11:04:26.260358 TX Bit4 (980~997) 18 988, Bit12 (970~988) 19 979,
1231 11:04:26.260789 TX Bit5 (979~993) 15 986, Bit13 (970~987) 18 978,
1232 11:04:26.307320 TX Bit6 (979~994) 16 986, Bit14 (971~990) 20 980,
1233 11:04:26.307636 TX Bit7 (980~997) 18 988, Bit15 (976~992) 17 984,
1234 11:04:26.307704
1235 11:04:26.307761 Write Rank0 MR14 =0xc
1236 11:04:26.307838
1237 11:04:26.307903 CH=0, VrefRange= 0, VrefLevel = 12
1238 11:04:26.308310 TX Bit0 (981~997) 17 989, Bit8 (968~987) 20 977,
1239 11:04:26.308385 TX Bit1 (980~998) 19 989, Bit9 (970~989) 20 979,
1240 11:04:26.309044 TX Bit2 (980~999) 20 989, Bit10 (975~992) 18 983,
1241 11:04:26.309452 TX Bit3 (977~993) 17 985, Bit11 (969~988) 20 978,
1242 11:04:26.310381 TX Bit4 (979~998) 20 988, Bit12 (969~989) 21 979,
1243 11:04:26.310636 TX Bit5 (979~993) 15 986, Bit13 (969~989) 21 979,
1244 11:04:26.312968 TX Bit6 (979~995) 17 987, Bit14 (971~990) 20 980,
1245 11:04:26.316410 TX Bit7 (980~998) 19 989, Bit15 (976~993) 18 984,
1246 11:04:26.316486
1247 11:04:26.316544 Write Rank0 MR14 =0xe
1248 11:04:26.326512
1249 11:04:26.330488 CH=0, VrefRange= 0, VrefLevel = 14
1250 11:04:26.333933 TX Bit0 (981~998) 18 989, Bit8 (968~987) 20 977,
1251 11:04:26.336921 TX Bit1 (979~999) 21 989, Bit9 (969~989) 21 979,
1252 11:04:26.343432 TX Bit2 (980~1000) 21 990, Bit10 (976~992) 17 984,
1253 11:04:26.347184 TX Bit3 (977~993) 17 985, Bit11 (968~988) 21 978,
1254 11:04:26.349833 TX Bit4 (979~998) 20 988, Bit12 (969~989) 21 979,
1255 11:04:26.356773 TX Bit5 (979~994) 16 986, Bit13 (969~989) 21 979,
1256 11:04:26.359949 TX Bit6 (979~995) 17 987, Bit14 (971~991) 21 981,
1257 11:04:26.363325 TX Bit7 (980~998) 19 989, Bit15 (976~993) 18 984,
1258 11:04:26.366598
1259 11:04:26.369790 wait MRW command Rank0 MR14 =0x10 fired (1)
1260 11:04:26.369865 Write Rank0 MR14 =0x10
1261 11:04:26.380580
1262 11:04:26.383103 CH=0, VrefRange= 0, VrefLevel = 16
1263 11:04:26.386661 TX Bit0 (981~999) 19 990, Bit8 (968~988) 21 978,
1264 11:04:26.390377 TX Bit1 (979~1000) 22 989, Bit9 (969~989) 21 979,
1265 11:04:26.396289 TX Bit2 (980~1000) 21 990, Bit10 (975~993) 19 984,
1266 11:04:26.400429 TX Bit3 (976~994) 19 985, Bit11 (968~988) 21 978,
1267 11:04:26.403026 TX Bit4 (979~999) 21 989, Bit12 (969~989) 21 979,
1268 11:04:26.410091 TX Bit5 (979~994) 16 986, Bit13 (969~989) 21 979,
1269 11:04:26.413538 TX Bit6 (979~995) 17 987, Bit14 (970~991) 22 980,
1270 11:04:26.416743 TX Bit7 (979~999) 21 989, Bit15 (975~994) 20 984,
1271 11:04:26.420090
1272 11:04:26.420165 Write Rank0 MR14 =0x12
1273 11:04:26.429072
1274 11:04:26.432574 CH=0, VrefRange= 0, VrefLevel = 18
1275 11:04:26.436111 TX Bit0 (980~1000) 21 990, Bit8 (967~988) 22 977,
1276 11:04:26.438779 TX Bit1 (979~1000) 22 989, Bit9 (969~990) 22 979,
1277 11:04:26.445481 TX Bit2 (980~1001) 22 990, Bit10 (975~993) 19 984,
1278 11:04:26.449296 TX Bit3 (976~994) 19 985, Bit11 (968~989) 22 978,
1279 11:04:26.452390 TX Bit4 (979~1000) 22 989, Bit12 (968~990) 23 979,
1280 11:04:26.458852 TX Bit5 (979~995) 17 987, Bit13 (968~990) 23 979,
1281 11:04:26.462197 TX Bit6 (978~996) 19 987, Bit14 (970~991) 22 980,
1282 11:04:26.468965 TX Bit7 (979~1000) 22 989, Bit15 (975~993) 19 984,
1283 11:04:26.469041
1284 11:04:26.472138 wait MRW command Rank0 MR14 =0x14 fired (1)
1285 11:04:26.472213 Write Rank0 MR14 =0x14
1286 11:04:26.483115
1287 11:04:26.485840 CH=0, VrefRange= 0, VrefLevel = 20
1288 11:04:26.489066 TX Bit0 (980~1000) 21 990, Bit8 (967~988) 22 977,
1289 11:04:26.492932 TX Bit1 (979~1001) 23 990, Bit9 (968~991) 24 979,
1290 11:04:26.499462 TX Bit2 (980~1001) 22 990, Bit10 (974~994) 21 984,
1291 11:04:26.502828 TX Bit3 (976~994) 19 985, Bit11 (968~989) 22 978,
1292 11:04:26.506240 TX Bit4 (979~1001) 23 990, Bit12 (969~990) 22 979,
1293 11:04:26.512624 TX Bit5 (978~995) 18 986, Bit13 (968~990) 23 979,
1294 11:04:26.516238 TX Bit6 (978~997) 20 987, Bit14 (969~992) 24 980,
1295 11:04:26.519595 TX Bit7 (979~1000) 22 989, Bit15 (975~995) 21 985,
1296 11:04:26.523308
1297 11:04:26.523385 Write Rank0 MR14 =0x16
1298 11:04:26.532583
1299 11:04:26.536302 CH=0, VrefRange= 0, VrefLevel = 22
1300 11:04:26.539088 TX Bit0 (980~1001) 22 990, Bit8 (967~989) 23 978,
1301 11:04:26.542750 TX Bit1 (979~1001) 23 990, Bit9 (968~991) 24 979,
1302 11:04:26.549580 TX Bit2 (980~1002) 23 991, Bit10 (974~995) 22 984,
1303 11:04:26.553412 TX Bit3 (975~995) 21 985, Bit11 (968~989) 22 978,
1304 11:04:26.556010 TX Bit4 (979~1001) 23 990, Bit12 (968~991) 24 979,
1305 11:04:26.562678 TX Bit5 (978~996) 19 987, Bit13 (968~990) 23 979,
1306 11:04:26.566008 TX Bit6 (978~997) 20 987, Bit14 (969~993) 25 981,
1307 11:04:26.572769 TX Bit7 (979~1001) 23 990, Bit15 (973~996) 24 984,
1308 11:04:26.572870
1309 11:04:26.572954 Write Rank0 MR14 =0x18
1310 11:04:26.582914
1311 11:04:26.585791 CH=0, VrefRange= 0, VrefLevel = 24
1312 11:04:26.589281 TX Bit0 (980~1002) 23 991, Bit8 (967~989) 23 978,
1313 11:04:26.592079 TX Bit1 (979~1002) 24 990, Bit9 (968~991) 24 979,
1314 11:04:26.598649 TX Bit2 (979~1002) 24 990, Bit10 (974~995) 22 984,
1315 11:04:26.602369 TX Bit3 (975~995) 21 985, Bit11 (968~990) 23 979,
1316 11:04:26.605816 TX Bit4 (979~1002) 24 990, Bit12 (968~991) 24 979,
1317 11:04:26.613308 TX Bit5 (978~996) 19 987, Bit13 (968~991) 24 979,
1318 11:04:26.615534 TX Bit6 (978~998) 21 988, Bit14 (969~993) 25 981,
1319 11:04:26.622336 TX Bit7 (979~1002) 24 990, Bit15 (974~996) 23 985,
1320 11:04:26.622428
1321 11:04:26.622488 Write Rank0 MR14 =0x1a
1322 11:04:26.632482
1323 11:04:26.632569 CH=0, VrefRange= 0, VrefLevel = 26
1324 11:04:26.639373 TX Bit0 (980~1002) 23 991, Bit8 (967~990) 24 978,
1325 11:04:26.642290 TX Bit1 (979~1002) 24 990, Bit9 (968~991) 24 979,
1326 11:04:26.648978 TX Bit2 (980~1003) 24 991, Bit10 (973~996) 24 984,
1327 11:04:26.652520 TX Bit3 (975~995) 21 985, Bit11 (967~990) 24 978,
1328 11:04:26.655547 TX Bit4 (978~1002) 25 990, Bit12 (968~992) 25 980,
1329 11:04:26.662755 TX Bit5 (978~997) 20 987, Bit13 (968~992) 25 980,
1330 11:04:26.665573 TX Bit6 (978~999) 22 988, Bit14 (969~994) 26 981,
1331 11:04:26.672159 TX Bit7 (979~1002) 24 990, Bit15 (974~996) 23 985,
1332 11:04:26.672235
1333 11:04:26.672293 Write Rank0 MR14 =0x1c
1334 11:04:26.682772
1335 11:04:26.685711 CH=0, VrefRange= 0, VrefLevel = 28
1336 11:04:26.689041 TX Bit0 (979~1003) 25 991, Bit8 (967~990) 24 978,
1337 11:04:26.692401 TX Bit1 (979~1003) 25 991, Bit9 (968~991) 24 979,
1338 11:04:26.699046 TX Bit2 (979~1004) 26 991, Bit10 (973~996) 24 984,
1339 11:04:26.702380 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1340 11:04:26.705724 TX Bit4 (979~1003) 25 991, Bit12 (968~992) 25 980,
1341 11:04:26.712474 TX Bit5 (978~998) 21 988, Bit13 (968~992) 25 980,
1342 11:04:26.716157 TX Bit6 (977~999) 23 988, Bit14 (969~994) 26 981,
1343 11:04:26.722511 TX Bit7 (978~1003) 26 990, Bit15 (973~996) 24 984,
1344 11:04:26.722587
1345 11:04:26.722645 Write Rank0 MR14 =0x1e
1346 11:04:26.733050
1347 11:04:26.735558 CH=0, VrefRange= 0, VrefLevel = 30
1348 11:04:26.739163 TX Bit0 (979~1003) 25 991, Bit8 (966~989) 24 977,
1349 11:04:26.742512 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1350 11:04:26.749655 TX Bit2 (979~1004) 26 991, Bit10 (973~996) 24 984,
1351 11:04:26.752464 TX Bit3 (974~996) 23 985, Bit11 (967~990) 24 978,
1352 11:04:26.756028 TX Bit4 (979~1003) 25 991, Bit12 (968~992) 25 980,
1353 11:04:26.763025 TX Bit5 (977~998) 22 987, Bit13 (968~992) 25 980,
1354 11:04:26.765678 TX Bit6 (978~1000) 23 989, Bit14 (968~993) 26 980,
1355 11:04:26.772631 TX Bit7 (979~1002) 24 990, Bit15 (973~996) 24 984,
1356 11:04:26.772708
1357 11:04:26.772766 Write Rank0 MR14 =0x20
1358 11:04:26.783227
1359 11:04:26.786235 CH=0, VrefRange= 0, VrefLevel = 32
1360 11:04:26.789872 TX Bit0 (979~1004) 26 991, Bit8 (967~989) 23 978,
1361 11:04:26.792888 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1362 11:04:26.799632 TX Bit2 (979~1005) 27 992, Bit10 (973~997) 25 985,
1363 11:04:26.802851 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1364 11:04:26.806309 TX Bit4 (979~1003) 25 991, Bit12 (968~991) 24 979,
1365 11:04:26.812937 TX Bit5 (977~999) 23 988, Bit13 (968~991) 24 979,
1366 11:04:26.816041 TX Bit6 (977~1000) 24 988, Bit14 (968~993) 26 980,
1367 11:04:26.823158 TX Bit7 (979~1002) 24 990, Bit15 (972~996) 25 984,
1368 11:04:26.823234
1369 11:04:26.823292 Write Rank0 MR14 =0x22
1370 11:04:26.833554
1371 11:04:26.837311 CH=0, VrefRange= 0, VrefLevel = 34
1372 11:04:26.840029 TX Bit0 (979~1004) 26 991, Bit8 (967~989) 23 978,
1373 11:04:26.843613 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1374 11:04:26.850103 TX Bit2 (979~1005) 27 992, Bit10 (973~997) 25 985,
1375 11:04:26.853386 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1376 11:04:26.856537 TX Bit4 (979~1003) 25 991, Bit12 (968~991) 24 979,
1377 11:04:26.863183 TX Bit5 (977~999) 23 988, Bit13 (968~991) 24 979,
1378 11:04:26.866935 TX Bit6 (977~1000) 24 988, Bit14 (968~993) 26 980,
1379 11:04:26.870200 TX Bit7 (979~1002) 24 990, Bit15 (972~996) 25 984,
1380 11:04:26.873461
1381 11:04:26.873535 Write Rank0 MR14 =0x24
1382 11:04:26.883753
1383 11:04:26.887006 CH=0, VrefRange= 0, VrefLevel = 36
1384 11:04:26.890450 TX Bit0 (979~1004) 26 991, Bit8 (967~989) 23 978,
1385 11:04:26.893691 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1386 11:04:26.900445 TX Bit2 (979~1005) 27 992, Bit10 (973~997) 25 985,
1387 11:04:26.903647 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1388 11:04:26.906816 TX Bit4 (979~1003) 25 991, Bit12 (968~991) 24 979,
1389 11:04:26.913430 TX Bit5 (977~999) 23 988, Bit13 (968~991) 24 979,
1390 11:04:26.916903 TX Bit6 (977~1000) 24 988, Bit14 (968~993) 26 980,
1391 11:04:26.923833 TX Bit7 (979~1002) 24 990, Bit15 (972~996) 25 984,
1392 11:04:26.923909
1393 11:04:26.923967 Write Rank0 MR14 =0x26
1394 11:04:26.934404
1395 11:04:26.937020 CH=0, VrefRange= 0, VrefLevel = 38
1396 11:04:26.940130 TX Bit0 (979~1004) 26 991, Bit8 (967~989) 23 978,
1397 11:04:26.943660 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1398 11:04:26.950412 TX Bit2 (979~1005) 27 992, Bit10 (973~997) 25 985,
1399 11:04:26.953772 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1400 11:04:26.957104 TX Bit4 (979~1003) 25 991, Bit12 (968~991) 24 979,
1401 11:04:26.963556 TX Bit5 (977~999) 23 988, Bit13 (968~991) 24 979,
1402 11:04:26.967075 TX Bit6 (977~1000) 24 988, Bit14 (968~993) 26 980,
1403 11:04:26.973552 TX Bit7 (979~1002) 24 990, Bit15 (972~996) 25 984,
1404 11:04:26.973629
1405 11:04:26.973687
1406 11:04:26.977076 TX Vref found, early break! 369< 370
1407 11:04:26.980188 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =833/100 ps
1408 11:04:26.983772 u1DelayCellOfst[0]=7 cells (6 PI)
1409 11:04:26.987106 u1DelayCellOfst[1]=7 cells (6 PI)
1410 11:04:26.990498 u1DelayCellOfst[2]=8 cells (7 PI)
1411 11:04:26.993905 u1DelayCellOfst[3]=0 cells (0 PI)
1412 11:04:26.997140 u1DelayCellOfst[4]=7 cells (6 PI)
1413 11:04:26.997231 u1DelayCellOfst[5]=3 cells (3 PI)
1414 11:04:27.000224 u1DelayCellOfst[6]=3 cells (3 PI)
1415 11:04:27.003580 u1DelayCellOfst[7]=5 cells (5 PI)
1416 11:04:27.007023 Byte0, DQ PI dly=985, DQM PI dly= 988
1417 11:04:27.013600 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1418 11:04:27.013676
1419 11:04:27.017243 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1420 11:04:27.017318
1421 11:04:27.020232 u1DelayCellOfst[8]=0 cells (0 PI)
1422 11:04:27.023601 u1DelayCellOfst[9]=1 cells (1 PI)
1423 11:04:27.026870 u1DelayCellOfst[10]=8 cells (7 PI)
1424 11:04:27.030473 u1DelayCellOfst[11]=0 cells (0 PI)
1425 11:04:27.033391 u1DelayCellOfst[12]=1 cells (1 PI)
1426 11:04:27.037038 u1DelayCellOfst[13]=1 cells (1 PI)
1427 11:04:27.037113 u1DelayCellOfst[14]=2 cells (2 PI)
1428 11:04:27.041045 u1DelayCellOfst[15]=7 cells (6 PI)
1429 11:04:27.043783 Byte1, DQ PI dly=978, DQM PI dly= 981
1430 11:04:27.050389 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1431 11:04:27.050466
1432 11:04:27.053990 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1433 11:04:27.054065
1434 11:04:27.057536 Write Rank0 MR14 =0x20
1435 11:04:27.057610
1436 11:04:27.057668 Final TX Range 0 Vref 32
1437 11:04:27.057722
1438 11:04:27.063641 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1439 11:04:27.063742
1440 11:04:27.070702 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1441 11:04:27.080587 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1442 11:04:27.086867 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1443 11:04:27.086943 Write Rank0 MR3 =0xb0
1444 11:04:27.090249 DramC Write-DBI on
1445 11:04:27.090323 ==
1446 11:04:27.094108 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1447 11:04:27.097013 fsp= 1, odt_onoff= 1, Byte mode= 0
1448 11:04:27.097088 ==
1449 11:04:27.103856 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1450 11:04:27.103933
1451 11:04:27.103991 Begin, DQ Scan Range 701~765
1452 11:04:27.107688
1453 11:04:27.107763
1454 11:04:27.107819 TX Vref Scan disable
1455 11:04:27.110430 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1456 11:04:27.114248 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1457 11:04:27.116870 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1458 11:04:27.120870 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1459 11:04:27.123506 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1460 11:04:27.126962 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1461 11:04:27.130709 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1462 11:04:27.133832 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1463 11:04:27.140303 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1464 11:04:27.143871 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1465 11:04:27.147076 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1466 11:04:27.150240 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1467 11:04:27.154030 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1468 11:04:27.157010 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1469 11:04:27.160854 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1470 11:04:27.164037 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1471 11:04:27.167565 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1472 11:04:27.170959 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1473 11:04:27.174360 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1474 11:04:27.177380 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1475 11:04:27.180700 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
1476 11:04:27.187992 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1477 11:04:27.191845 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1478 11:04:27.194544 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1479 11:04:27.198206 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1480 11:04:27.201644 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1481 11:04:27.204552 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1482 11:04:27.208852 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1483 11:04:27.211150 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1484 11:04:27.214832 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1485 11:04:27.218137 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1486 11:04:27.221265 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
1487 11:04:27.226046 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
1488 11:04:27.228269 749 |2 6 45|[0] xxxxxxxx xxxxxxxx [MSB]
1489 11:04:27.231597 Byte0, DQ PI dly=735, DQM PI dly= 735
1490 11:04:27.238779 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
1491 11:04:27.238857
1492 11:04:27.241431 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
1493 11:04:27.241507
1494 11:04:27.244780 Byte1, DQ PI dly=724, DQM PI dly= 724
1495 11:04:27.247940 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
1496 11:04:27.248015
1497 11:04:27.254446 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
1498 11:04:27.254522
1499 11:04:27.261224 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1500 11:04:27.268120 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1501 11:04:27.274774 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1502 11:04:27.274850 Write Rank0 MR3 =0x30
1503 11:04:27.277973 DramC Write-DBI off
1504 11:04:27.278047
1505 11:04:27.278105 [DATLAT]
1506 11:04:27.281245 Freq=1600, CH0 RK0, use_rxtx_scan=0
1507 11:04:27.281321
1508 11:04:27.285074 DATLAT Default: 0xf
1509 11:04:27.285173 7, 0xFFFF, sum=0
1510 11:04:27.288088 8, 0xFFFF, sum=0
1511 11:04:27.288163 9, 0xFFFF, sum=0
1512 11:04:27.291961 10, 0xFFFF, sum=0
1513 11:04:27.292038 11, 0xFFFF, sum=0
1514 11:04:27.294824 12, 0xFFFF, sum=0
1515 11:04:27.294900 13, 0xFFFF, sum=0
1516 11:04:27.297922 14, 0x0, sum=1
1517 11:04:27.297998 15, 0x0, sum=2
1518 11:04:27.298058 16, 0x0, sum=3
1519 11:04:27.301697 17, 0x0, sum=4
1520 11:04:27.305084 pattern=2 first_step=14 total pass=5 best_step=16
1521 11:04:27.305191 ==
1522 11:04:27.311536 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1523 11:04:27.314665 fsp= 1, odt_onoff= 1, Byte mode= 0
1524 11:04:27.314741 ==
1525 11:04:27.318210 Start DQ dly to find pass range UseTestEngine =1
1526 11:04:27.321651 x-axis: bit #, y-axis: DQ dly (-127~63)
1527 11:04:27.324591 RX Vref Scan = 1
1528 11:04:27.438469
1529 11:04:27.438588 RX Vref found, early break!
1530 11:04:27.438648
1531 11:04:27.445110 Final RX Vref 12, apply to both rank0 and 1
1532 11:04:27.445219 ==
1533 11:04:27.448336 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1534 11:04:27.452073 fsp= 1, odt_onoff= 1, Byte mode= 0
1535 11:04:27.452148 ==
1536 11:04:27.452206 DQS Delay:
1537 11:04:27.455279 DQS0 = 0, DQS1 = 0
1538 11:04:27.455354 DQM Delay:
1539 11:04:27.458471 DQM0 = 21, DQM1 = 20
1540 11:04:27.458545 DQ Delay:
1541 11:04:27.461823 DQ0 =23, DQ1 =22, DQ2 =24, DQ3 =17
1542 11:04:27.465224 DQ4 =23, DQ5 =18, DQ6 =20, DQ7 =23
1543 11:04:27.468210 DQ8 =17, DQ9 =19, DQ10 =25, DQ11 =18
1544 11:04:27.471936 DQ12 =20, DQ13 =20, DQ14 =21, DQ15 =23
1545 11:04:27.472011
1546 11:04:27.472069
1547 11:04:27.472121
1548 11:04:27.474814 [DramC_TX_OE_Calibration] TA2
1549 11:04:27.478387 Original DQ_B0 (3 6) =30, OEN = 27
1550 11:04:27.482002 Original DQ_B1 (3 6) =30, OEN = 27
1551 11:04:27.484894 23, 0x0, End_B0=23 End_B1=23
1552 11:04:27.484995 24, 0x0, End_B0=24 End_B1=24
1553 11:04:27.488618 25, 0x0, End_B0=25 End_B1=25
1554 11:04:27.492271 26, 0x0, End_B0=26 End_B1=26
1555 11:04:27.495323 27, 0x0, End_B0=27 End_B1=27
1556 11:04:27.495400 28, 0x0, End_B0=28 End_B1=28
1557 11:04:27.498531 29, 0x0, End_B0=29 End_B1=29
1558 11:04:27.501691 30, 0x0, End_B0=30 End_B1=30
1559 11:04:27.505529 31, 0xFFFF, End_B0=30 End_B1=30
1560 11:04:27.508520 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1561 11:04:27.515405 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1562 11:04:27.515482
1563 11:04:27.515540
1564 11:04:27.519077 Write Rank0 MR23 =0x3f
1565 11:04:27.519151 [DQSOSC]
1566 11:04:27.528640 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdcd, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
1567 11:04:27.531898 CH0_RK0: MR19=0x202, MR18=0xCDCD, DQSOSC=439, MR23=63, INC=12, DEC=19
1568 11:04:27.535382 Write Rank0 MR23 =0x3f
1569 11:04:27.535457 [DQSOSC]
1570 11:04:27.545171 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbcb, (MSB)MR19= 0x202, tDQSOscB0 = 440 ps tDQSOscB1 = 440 ps
1571 11:04:27.545254 CH0 RK0: MR19=202, MR18=CBCB
1572 11:04:27.552249 [RankSwap] Rank num 2, (Multi 1), Rank 1
1573 11:04:27.552326 Write Rank0 MR2 =0xad
1574 11:04:27.555514 [Write Leveling]
1575 11:04:27.558918 delay byte0 byte1 byte2 byte3
1576 11:04:27.558992
1577 11:04:27.559051 10 0 0
1578 11:04:27.559107 11 0 0
1579 11:04:27.561910 12 0 0
1580 11:04:27.561986 13 0 0
1581 11:04:27.565576 14 0 0
1582 11:04:27.565652 15 0 0
1583 11:04:27.565710 16 0 0
1584 11:04:27.568430 17 0 0
1585 11:04:27.568505 18 0 0
1586 11:04:27.571816 19 0 0
1587 11:04:27.571891 20 0 0
1588 11:04:27.575550 21 0 0
1589 11:04:27.575625 22 0 0
1590 11:04:27.575683 23 0 0
1591 11:04:27.578663 24 0 0
1592 11:04:27.578738 25 0 ff
1593 11:04:27.581805 26 0 ff
1594 11:04:27.581880 27 0 ff
1595 11:04:27.585329 28 0 ff
1596 11:04:27.585405 29 0 ff
1597 11:04:27.585464 30 0 ff
1598 11:04:27.588798 31 0 ff
1599 11:04:27.588874 32 0 ff
1600 11:04:27.591663 33 0 ff
1601 11:04:27.591740 34 ff ff
1602 11:04:27.595195 35 ff ff
1603 11:04:27.595270 36 ff ff
1604 11:04:27.598640 37 ff ff
1605 11:04:27.598716 38 ff ff
1606 11:04:27.598774 39 ff ff
1607 11:04:27.602084 40 ff ff
1608 11:04:27.605135 pass bytecount = 0xff (0xff: all bytes pass)
1609 11:04:27.605256
1610 11:04:27.608845 DQS0 dly: 34
1611 11:04:27.608950 DQS1 dly: 25
1612 11:04:27.612495 Write Rank0 MR2 =0x2d
1613 11:04:27.615201 [RankSwap] Rank num 2, (Multi 1), Rank 0
1614 11:04:27.615276 Write Rank1 MR1 =0xd6
1615 11:04:27.615334 [Gating]
1616 11:04:27.618927 ==
1617 11:04:27.622343 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1618 11:04:27.625774 fsp= 1, odt_onoff= 1, Byte mode= 0
1619 11:04:27.625850 ==
1620 11:04:27.629414 3 1 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1621 11:04:27.635403 3 1 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1622 11:04:27.638938 3 1 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1623 11:04:27.642410 3 1 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1624 11:04:27.649088 3 1 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1625 11:04:27.652050 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1626 11:04:27.655853 3 1 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1627 11:04:27.658844 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1628 11:04:27.665628 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1629 11:04:27.668922 3 2 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1630 11:04:27.672287 3 2 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
1631 11:04:27.678916 3 2 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1632 11:04:27.682216 3 2 16 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1633 11:04:27.685270 3 2 20 |3d3d 807 |(11 11)(11 11) |(1 1)(1 1)| 0
1634 11:04:27.692008 3 2 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1635 11:04:27.695753 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1636 11:04:27.698869 3 3 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1637 11:04:27.702217 3 3 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1638 11:04:27.708703 3 3 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1639 11:04:27.711900 3 3 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1640 11:04:27.715762 3 3 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1641 11:04:27.722209 3 3 20 |201 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1642 11:04:27.725836 3 3 24 |504 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1643 11:04:27.728825 [Byte 0] Lead/lag Transition tap number (1)
1644 11:04:27.731903 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1645 11:04:27.738990 [Byte 1] Lead/lag Transition tap number (1)
1646 11:04:27.742914 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1647 11:04:27.745858 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1648 11:04:27.749047 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1649 11:04:27.755732 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
1650 11:04:27.759103 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1651 11:04:27.762224 3 4 20 |3d3d 807 |(11 11)(11 11) |(1 1)(0 1)| 0
1652 11:04:27.769257 3 4 24 |3d3d 534c |(11 11)(11 11) |(1 1)(1 1)| 0
1653 11:04:27.772324 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1654 11:04:27.775696 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1655 11:04:27.782385 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1656 11:04:27.785655 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1657 11:04:27.789365 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1658 11:04:27.796120 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1659 11:04:27.799131 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1660 11:04:27.802201 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1661 11:04:27.806017 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1662 11:04:27.812350 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1663 11:04:27.815979 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1664 11:04:27.819252 [Byte 0] Lead/lag falling Transition (3, 6, 4)
1665 11:04:27.826161 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1666 11:04:27.829263 [Byte 1] Lead/lag falling Transition (3, 6, 8)
1667 11:04:27.832615 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1668 11:04:27.836235 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1669 11:04:27.842408 [Byte 0] Lead/lag Transition tap number (4)
1670 11:04:27.846014 [Byte 1] Lead/lag Transition tap number (3)
1671 11:04:27.849056 3 6 20 |202 1010 |(11 11)(11 11) |(0 0)(0 0)| 0
1672 11:04:27.852751 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1673 11:04:27.856596 [Byte 0]First pass (3, 6, 24)
1674 11:04:27.859545 [Byte 1]First pass (3, 6, 24)
1675 11:04:27.862556 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1676 11:04:27.865982 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1677 11:04:27.869754 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1678 11:04:27.876057 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1679 11:04:27.879437 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1680 11:04:27.882757 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1681 11:04:27.885967 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1682 11:04:27.889324 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1683 11:04:27.895895 All bytes gating window > 1UI, Early break!
1684 11:04:27.895979
1685 11:04:27.898924 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
1686 11:04:27.898998
1687 11:04:27.902399 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 14)
1688 11:04:27.902502
1689 11:04:27.902583
1690 11:04:27.902638
1691 11:04:27.905716 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
1692 11:04:27.905814
1693 11:04:27.912443 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
1694 11:04:27.912526
1695 11:04:27.912585
1696 11:04:27.912639 Write Rank1 MR1 =0x56
1697 11:04:27.912690
1698 11:04:27.915487 best RODT dly(2T, 0.5T) = (2, 3)
1699 11:04:27.915561
1700 11:04:27.919587 best RODT dly(2T, 0.5T) = (2, 3)
1701 11:04:27.919662 ==
1702 11:04:27.925644 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1703 11:04:27.929255 fsp= 1, odt_onoff= 1, Byte mode= 0
1704 11:04:27.929331 ==
1705 11:04:27.931986 Start DQ dly to find pass range UseTestEngine =0
1706 11:04:27.935564 x-axis: bit #, y-axis: DQ dly (-127~63)
1707 11:04:27.939362 RX Vref Scan = 0
1708 11:04:27.939437 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1709 11:04:27.943016 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1710 11:04:27.945365 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1711 11:04:27.948955 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1712 11:04:27.952306 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1713 11:04:27.956041 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1714 11:04:27.958814 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1715 11:04:27.962208 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1716 11:04:27.962286 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1717 11:04:27.965679 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1718 11:04:27.968728 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1719 11:04:27.972043 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1720 11:04:27.975488 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1721 11:04:27.978749 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1722 11:04:27.982215 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1723 11:04:27.985851 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1724 11:04:27.989010 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1725 11:04:27.989103 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1726 11:04:27.991937 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1727 11:04:27.995229 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1728 11:04:27.998345 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1729 11:04:28.002084 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1730 11:04:28.005009 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1731 11:04:28.008834 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1732 11:04:28.008903 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1733 11:04:28.012163 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1734 11:04:28.015499 0, [0] xxxxxxxx xxxxxxxx [MSB]
1735 11:04:28.018472 1, [0] xxxxxxxx xxxxxxxx [MSB]
1736 11:04:28.022443 2, [0] xxxxxxxx xxxxxxxx [MSB]
1737 11:04:28.025679 3, [0] xxxoxxxx oxxxxxxx [MSB]
1738 11:04:28.025756 4, [0] xxxoxoxx oxxoxxxx [MSB]
1739 11:04:28.029008 5, [0] xxxoxoox ooxoxxxx [MSB]
1740 11:04:28.032735 6, [0] xxxoxoox ooxoxxxx [MSB]
1741 11:04:28.035376 7, [0] xxxoxooo ooxooxxx [MSB]
1742 11:04:28.038624 8, [0] xoxooooo ooxoooox [MSB]
1743 11:04:28.038701 9, [0] oooooooo ooxoooox [MSB]
1744 11:04:28.041850 10, [0] oooooooo ooxooooo [MSB]
1745 11:04:28.045641 11, [0] oooooooo ooxooooo [MSB]
1746 11:04:28.048680 32, [0] oooooooo oooooooo [MSB]
1747 11:04:28.051995 33, [0] oooxoooo xooooooo [MSB]
1748 11:04:28.056210 34, [0] oooxoooo xooooooo [MSB]
1749 11:04:28.059597 35, [0] oooxoooo xooxoooo [MSB]
1750 11:04:28.059675 36, [0] oooxooxo xxoxxooo [MSB]
1751 11:04:28.062289 37, [0] oooxoxxo xxoxxxoo [MSB]
1752 11:04:28.065831 38, [0] oooxoxxo xxoxxxxo [MSB]
1753 11:04:28.068846 39, [0] oooxoxxx xxoxxxxo [MSB]
1754 11:04:28.072034 40, [0] oxoxxxxx xxoxxxxo [MSB]
1755 11:04:28.075476 41, [0] xxxxxxxx xxoxxxxx [MSB]
1756 11:04:28.075553 42, [0] xxxxxxxx xxoxxxxx [MSB]
1757 11:04:28.079212 43, [0] xxxxxxxx xxoxxxxx [MSB]
1758 11:04:28.083093 44, [0] xxxxxxxx xxxxxxxx [MSB]
1759 11:04:28.085903 iDelay=44, Bit 0, Center 24 (9 ~ 40) 32
1760 11:04:28.089696 iDelay=44, Bit 1, Center 23 (8 ~ 39) 32
1761 11:04:28.092594 iDelay=44, Bit 2, Center 24 (9 ~ 40) 32
1762 11:04:28.095747 iDelay=44, Bit 3, Center 17 (3 ~ 32) 30
1763 11:04:28.102480 iDelay=44, Bit 4, Center 23 (8 ~ 39) 32
1764 11:04:28.105808 iDelay=44, Bit 5, Center 20 (4 ~ 36) 33
1765 11:04:28.109244 iDelay=44, Bit 6, Center 20 (5 ~ 35) 31
1766 11:04:28.112579 iDelay=44, Bit 7, Center 22 (7 ~ 38) 32
1767 11:04:28.115691 iDelay=44, Bit 8, Center 17 (3 ~ 32) 30
1768 11:04:28.119156 iDelay=44, Bit 9, Center 20 (5 ~ 35) 31
1769 11:04:28.122487 iDelay=44, Bit 10, Center 27 (12 ~ 43) 32
1770 11:04:28.125829 iDelay=44, Bit 11, Center 19 (4 ~ 34) 31
1771 11:04:28.128899 iDelay=44, Bit 12, Center 21 (7 ~ 35) 29
1772 11:04:28.132701 iDelay=44, Bit 13, Center 22 (8 ~ 36) 29
1773 11:04:28.136026 iDelay=44, Bit 14, Center 22 (8 ~ 37) 30
1774 11:04:28.140107 iDelay=44, Bit 15, Center 25 (10 ~ 40) 31
1775 11:04:28.140183 ==
1776 11:04:28.145887 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1777 11:04:28.149232 fsp= 1, odt_onoff= 1, Byte mode= 0
1778 11:04:28.149329 ==
1779 11:04:28.149415 DQS Delay:
1780 11:04:28.152478 DQS0 = 0, DQS1 = 0
1781 11:04:28.152570 DQM Delay:
1782 11:04:28.156527 DQM0 = 21, DQM1 = 21
1783 11:04:28.156603 DQ Delay:
1784 11:04:28.158952 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =17
1785 11:04:28.163065 DQ4 =23, DQ5 =20, DQ6 =20, DQ7 =22
1786 11:04:28.166278 DQ8 =17, DQ9 =20, DQ10 =27, DQ11 =19
1787 11:04:28.169594 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =25
1788 11:04:28.169671
1789 11:04:28.169729
1790 11:04:28.169782 DramC Write-DBI off
1791 11:04:28.172588 ==
1792 11:04:28.175596 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1793 11:04:28.179821 fsp= 1, odt_onoff= 1, Byte mode= 0
1794 11:04:28.179898 ==
1795 11:04:28.182770 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1796 11:04:28.182867
1797 11:04:28.186558 Begin, DQ Scan Range 921~1177
1798 11:04:28.186634
1799 11:04:28.186693
1800 11:04:28.189504 TX Vref Scan disable
1801 11:04:28.192458 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1802 11:04:28.195902 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1803 11:04:28.199294 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1804 11:04:28.202340 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1805 11:04:28.205705 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1806 11:04:28.209210 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1807 11:04:28.212473 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1808 11:04:28.215917 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1809 11:04:28.219175 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1810 11:04:28.222721 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1811 11:04:28.228904 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1812 11:04:28.232505 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1813 11:04:28.235778 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1814 11:04:28.239601 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1815 11:04:28.242504 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1816 11:04:28.246092 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1817 11:04:28.249357 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1818 11:04:28.252881 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1819 11:04:28.255832 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1820 11:04:28.258969 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1821 11:04:28.262352 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1822 11:04:28.266124 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1823 11:04:28.269047 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1824 11:04:28.273098 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1825 11:04:28.276052 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1826 11:04:28.279717 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1827 11:04:28.283013 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1828 11:04:28.289011 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1829 11:04:28.292418 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1830 11:04:28.295779 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1831 11:04:28.299487 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1832 11:04:28.302403 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1833 11:04:28.305742 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1834 11:04:28.309047 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1835 11:04:28.312324 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1836 11:04:28.316009 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1837 11:04:28.319115 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1838 11:04:28.322466 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1839 11:04:28.327453 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1840 11:04:28.329004 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1841 11:04:28.332368 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1842 11:04:28.335532 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1843 11:04:28.339454 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1844 11:04:28.342336 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1845 11:04:28.345662 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1846 11:04:28.348990 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1847 11:04:28.355605 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1848 11:04:28.359136 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1849 11:04:28.362779 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1850 11:04:28.366089 970 |3 6 10|[0] xxxxxxxx oxxoxxxx [MSB]
1851 11:04:28.369016 971 |3 6 11|[0] xxxxxxxx oxxoxxxx [MSB]
1852 11:04:28.373112 972 |3 6 12|[0] xxxxxxxx ooxoxxxx [MSB]
1853 11:04:28.375802 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1854 11:04:28.379334 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1855 11:04:28.382454 975 |3 6 15|[0] xxxxxxxx ooxoooox [MSB]
1856 11:04:28.385797 976 |3 6 16|[0] xxxxxxxx ooooooox [MSB]
1857 11:04:28.388959 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1858 11:04:28.392567 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1859 11:04:28.395951 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
1860 11:04:28.399310 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
1861 11:04:28.402574 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
1862 11:04:28.405890 982 |3 6 22|[0] xxxoooox oooooooo [MSB]
1863 11:04:28.409032 983 |3 6 23|[0] xxxooooo oooooooo [MSB]
1864 11:04:28.412167 984 |3 6 24|[0] xooooooo oooooooo [MSB]
1865 11:04:28.420336 990 |3 6 30|[0] oooooooo xooxoooo [MSB]
1866 11:04:28.423554 991 |3 6 31|[0] oooooooo xoxxxxxx [MSB]
1867 11:04:28.426977 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1868 11:04:28.429639 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1869 11:04:28.433485 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1870 11:04:28.436731 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
1871 11:04:28.440063 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
1872 11:04:28.443333 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
1873 11:04:28.446735 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
1874 11:04:28.449686 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
1875 11:04:28.453237 1000 |3 6 40|[0] oooxoxoo xxxxxxxx [MSB]
1876 11:04:28.456560 1001 |3 6 41|[0] oooxoxxo xxxxxxxx [MSB]
1877 11:04:28.460049 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1878 11:04:28.463387 Byte0, DQ PI dly=991, DQM PI dly= 991
1879 11:04:28.469886 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
1880 11:04:28.469966
1881 11:04:28.473282 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
1882 11:04:28.473377
1883 11:04:28.477042 Byte1, DQ PI dly=981, DQM PI dly= 981
1884 11:04:28.480215 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1885 11:04:28.480293
1886 11:04:28.486816 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1887 11:04:28.486896
1888 11:04:28.486957 ==
1889 11:04:28.489943 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1890 11:04:28.493873 fsp= 1, odt_onoff= 1, Byte mode= 0
1891 11:04:28.493949 ==
1892 11:04:28.499959 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1893 11:04:28.500035
1894 11:04:28.500093 Begin, DQ Scan Range 957~1021
1895 11:04:28.503431 Write Rank1 MR14 =0x0
1896 11:04:28.511677
1897 11:04:28.511786 CH=0, VrefRange= 0, VrefLevel = 0
1898 11:04:28.518284 TX Bit0 (986~998) 13 992, Bit8 (972~984) 13 978,
1899 11:04:28.522483 TX Bit1 (986~997) 12 991, Bit9 (974~988) 15 981,
1900 11:04:28.528137 TX Bit2 (986~997) 12 991, Bit10 (979~992) 14 985,
1901 11:04:28.531853 TX Bit3 (980~991) 12 985, Bit11 (973~984) 12 978,
1902 11:04:28.535048 TX Bit4 (985~996) 12 990, Bit12 (975~987) 13 981,
1903 11:04:28.541585 TX Bit5 (983~994) 12 988, Bit13 (976~988) 13 982,
1904 11:04:28.544794 TX Bit6 (982~994) 13 988, Bit14 (976~989) 14 982,
1905 11:04:28.548371 TX Bit7 (986~995) 10 990, Bit15 (979~991) 13 985,
1906 11:04:28.548451
1907 11:04:28.554704 wait MRW command Rank1 MR14 =0x2 fired (1)
1908 11:04:28.554782 Write Rank1 MR14 =0x2
1909 11:04:28.563868
1910 11:04:28.563951 CH=0, VrefRange= 0, VrefLevel = 2
1911 11:04:28.570948 TX Bit0 (986~999) 14 992, Bit8 (972~986) 15 979,
1912 11:04:28.574730 TX Bit1 (986~996) 11 991, Bit9 (974~988) 15 981,
1913 11:04:28.580738 TX Bit2 (986~998) 13 992, Bit10 (979~993) 15 986,
1914 11:04:28.583793 TX Bit3 (980~992) 13 986, Bit11 (973~985) 13 979,
1915 11:04:28.587309 TX Bit4 (985~997) 13 991, Bit12 (975~988) 14 981,
1916 11:04:28.594172 TX Bit5 (982~995) 14 988, Bit13 (975~987) 13 981,
1917 11:04:28.597370 TX Bit6 (982~995) 14 988, Bit14 (976~989) 14 982,
1918 11:04:28.600807 TX Bit7 (986~996) 11 991, Bit15 (979~992) 14 985,
1919 11:04:28.600884
1920 11:04:28.604040 Write Rank1 MR14 =0x4
1921 11:04:28.612770
1922 11:04:28.612852 CH=0, VrefRange= 0, VrefLevel = 4
1923 11:04:28.619603 TX Bit0 (986~1000) 15 993, Bit8 (971~986) 16 978,
1924 11:04:28.623416 TX Bit1 (985~998) 14 991, Bit9 (973~989) 17 981,
1925 11:04:28.629862 TX Bit2 (986~1000) 15 993, Bit10 (978~994) 17 986,
1926 11:04:28.632905 TX Bit3 (980~993) 14 986, Bit11 (973~986) 14 979,
1927 11:04:28.636268 TX Bit4 (984~998) 15 991, Bit12 (974~988) 15 981,
1928 11:04:28.643261 TX Bit5 (982~995) 14 988, Bit13 (975~988) 14 981,
1929 11:04:28.647338 TX Bit6 (982~995) 14 988, Bit14 (975~990) 16 982,
1930 11:04:28.649618 TX Bit7 (986~996) 11 991, Bit15 (978~993) 16 985,
1931 11:04:28.649696
1932 11:04:28.654093 Write Rank1 MR14 =0x6
1933 11:04:28.662052
1934 11:04:28.662129 CH=0, VrefRange= 0, VrefLevel = 6
1935 11:04:28.668746 TX Bit0 (986~1001) 16 993, Bit8 (970~987) 18 978,
1936 11:04:28.672336 TX Bit1 (985~999) 15 992, Bit9 (973~989) 17 981,
1937 11:04:28.678995 TX Bit2 (986~1000) 15 993, Bit10 (978~995) 18 986,
1938 11:04:28.681911 TX Bit3 (980~993) 14 986, Bit11 (972~987) 16 979,
1939 11:04:28.685350 TX Bit4 (983~999) 17 991, Bit12 (974~989) 16 981,
1940 11:04:28.692601 TX Bit5 (981~995) 15 988, Bit13 (974~989) 16 981,
1941 11:04:28.695896 TX Bit6 (982~996) 15 989, Bit14 (975~991) 17 983,
1942 11:04:28.699054 TX Bit7 (986~998) 13 992, Bit15 (978~994) 17 986,
1943 11:04:28.699137
1944 11:04:28.702383 Write Rank1 MR14 =0x8
1945 11:04:28.711144
1946 11:04:28.711218 CH=0, VrefRange= 0, VrefLevel = 8
1947 11:04:28.718232 TX Bit0 (986~1002) 17 994, Bit8 (970~987) 18 978,
1948 11:04:28.721613 TX Bit1 (984~1000) 17 992, Bit9 (973~990) 18 981,
1949 11:04:28.728105 TX Bit2 (986~1001) 16 993, Bit10 (978~995) 18 986,
1950 11:04:28.731571 TX Bit3 (979~994) 16 986, Bit11 (972~987) 16 979,
1951 11:04:28.734910 TX Bit4 (983~1000) 18 991, Bit12 (974~989) 16 981,
1952 11:04:28.741334 TX Bit5 (981~996) 16 988, Bit13 (974~989) 16 981,
1953 11:04:28.744646 TX Bit6 (981~997) 17 989, Bit14 (975~991) 17 983,
1954 11:04:28.748464 TX Bit7 (985~999) 15 992, Bit15 (978~994) 17 986,
1955 11:04:28.748546
1956 11:04:28.751540 Write Rank1 MR14 =0xa
1957 11:04:28.760855
1958 11:04:28.764074 CH=0, VrefRange= 0, VrefLevel = 10
1959 11:04:28.768085 TX Bit0 (986~1003) 18 994, Bit8 (970~988) 19 979,
1960 11:04:28.770930 TX Bit1 (984~1001) 18 992, Bit9 (973~990) 18 981,
1961 11:04:28.777762 TX Bit2 (985~1001) 17 993, Bit10 (977~995) 19 986,
1962 11:04:28.780941 TX Bit3 (979~994) 16 986, Bit11 (971~988) 18 979,
1963 11:04:28.784402 TX Bit4 (983~1000) 18 991, Bit12 (973~990) 18 981,
1964 11:04:28.790956 TX Bit5 (981~997) 17 989, Bit13 (974~990) 17 982,
1965 11:04:28.794074 TX Bit6 (981~997) 17 989, Bit14 (975~992) 18 983,
1966 11:04:28.800661 TX Bit7 (985~1000) 16 992, Bit15 (977~995) 19 986,
1967 11:04:28.800739
1968 11:04:28.800799 Write Rank1 MR14 =0xc
1969 11:04:28.810785
1970 11:04:28.810861 CH=0, VrefRange= 0, VrefLevel = 12
1971 11:04:28.818320 TX Bit0 (985~1004) 20 994, Bit8 (970~988) 19 979,
1972 11:04:28.821034 TX Bit1 (984~1002) 19 993, Bit9 (972~990) 19 981,
1973 11:04:28.827954 TX Bit2 (986~1003) 18 994, Bit10 (977~996) 20 986,
1974 11:04:28.831054 TX Bit3 (979~995) 17 987, Bit11 (971~988) 18 979,
1975 11:04:28.834438 TX Bit4 (983~1001) 19 992, Bit12 (973~990) 18 981,
1976 11:04:28.841241 TX Bit5 (980~998) 19 989, Bit13 (973~991) 19 982,
1977 11:04:28.844516 TX Bit6 (981~999) 19 990, Bit14 (974~993) 20 983,
1978 11:04:28.847732 TX Bit7 (984~1001) 18 992, Bit15 (977~995) 19 986,
1979 11:04:28.850769
1980 11:04:28.850845 Write Rank1 MR14 =0xe
1981 11:04:28.860422
1982 11:04:28.864006 CH=0, VrefRange= 0, VrefLevel = 14
1983 11:04:28.867264 TX Bit0 (985~1003) 19 994, Bit8 (969~988) 20 978,
1984 11:04:28.870526 TX Bit1 (983~1002) 20 992, Bit9 (972~991) 20 981,
1985 11:04:28.877629 TX Bit2 (985~1003) 19 994, Bit10 (977~996) 20 986,
1986 11:04:28.880892 TX Bit3 (979~995) 17 987, Bit11 (971~988) 18 979,
1987 11:04:28.884400 TX Bit4 (982~1002) 21 992, Bit12 (973~990) 18 981,
1988 11:04:28.890956 TX Bit5 (980~998) 19 989, Bit13 (973~991) 19 982,
1989 11:04:28.894272 TX Bit6 (980~999) 20 989, Bit14 (973~994) 22 983,
1990 11:04:28.897627 TX Bit7 (984~1001) 18 992, Bit15 (977~995) 19 986,
1991 11:04:28.900965
1992 11:04:28.901066 Write Rank1 MR14 =0x10
1993 11:04:28.910856
1994 11:04:28.914621 CH=0, VrefRange= 0, VrefLevel = 16
1995 11:04:28.918056 TX Bit0 (985~1005) 21 995, Bit8 (969~989) 21 979,
1996 11:04:28.920605 TX Bit1 (984~1003) 20 993, Bit9 (972~992) 21 982,
1997 11:04:28.927145 TX Bit2 (985~1004) 20 994, Bit10 (976~996) 21 986,
1998 11:04:28.930987 TX Bit3 (979~995) 17 987, Bit11 (970~989) 20 979,
1999 11:04:28.934560 TX Bit4 (982~1002) 21 992, Bit12 (972~991) 20 981,
2000 11:04:28.940881 TX Bit5 (980~999) 20 989, Bit13 (973~992) 20 982,
2001 11:04:28.944416 TX Bit6 (980~1000) 21 990, Bit14 (973~994) 22 983,
2002 11:04:28.950700 TX Bit7 (983~1002) 20 992, Bit15 (977~996) 20 986,
2003 11:04:28.950780
2004 11:04:28.950838 Write Rank1 MR14 =0x12
2005 11:04:28.961007
2006 11:04:28.961111 CH=0, VrefRange= 0, VrefLevel = 18
2007 11:04:28.967697 TX Bit0 (984~1005) 22 994, Bit8 (968~989) 22 978,
2008 11:04:28.971069 TX Bit1 (983~1003) 21 993, Bit9 (971~992) 22 981,
2009 11:04:28.978100 TX Bit2 (984~1005) 22 994, Bit10 (976~997) 22 986,
2010 11:04:28.981297 TX Bit3 (979~996) 18 987, Bit11 (970~989) 20 979,
2011 11:04:28.985102 TX Bit4 (982~1003) 22 992, Bit12 (972~992) 21 982,
2012 11:04:28.991313 TX Bit5 (980~1000) 21 990, Bit13 (972~992) 21 982,
2013 11:04:28.994690 TX Bit6 (980~1001) 22 990, Bit14 (973~995) 23 984,
2014 11:04:29.001279 TX Bit7 (983~1003) 21 993, Bit15 (976~996) 21 986,
2015 11:04:29.001379
2016 11:04:29.001463 Write Rank1 MR14 =0x14
2017 11:04:29.012149
2018 11:04:29.012226 CH=0, VrefRange= 0, VrefLevel = 20
2019 11:04:29.018765 TX Bit0 (984~1006) 23 995, Bit8 (968~990) 23 979,
2020 11:04:29.022096 TX Bit1 (983~1003) 21 993, Bit9 (970~993) 24 981,
2021 11:04:29.025695 TX Bit2 (983~1005) 23 994, Bit10 (976~997) 22 986,
2022 11:04:29.032424 TX Bit3 (979~997) 19 988, Bit11 (969~990) 22 979,
2023 11:04:29.035337 TX Bit4 (981~1004) 24 992, Bit12 (972~992) 21 982,
2024 11:04:29.042122 TX Bit5 (980~1001) 22 990, Bit13 (972~993) 22 982,
2025 11:04:29.045566 TX Bit6 (980~1002) 23 991, Bit14 (972~995) 24 983,
2026 11:04:29.049374 TX Bit7 (982~1003) 22 992, Bit15 (975~996) 22 985,
2027 11:04:29.049452
2028 11:04:29.051992 Write Rank1 MR14 =0x16
2029 11:04:29.062426
2030 11:04:29.065371 CH=0, VrefRange= 0, VrefLevel = 22
2031 11:04:29.069065 TX Bit0 (984~1006) 23 995, Bit8 (968~991) 24 979,
2032 11:04:29.072207 TX Bit1 (982~1004) 23 993, Bit9 (970~994) 25 982,
2033 11:04:29.079232 TX Bit2 (983~1006) 24 994, Bit10 (975~997) 23 986,
2034 11:04:29.081936 TX Bit3 (979~997) 19 988, Bit11 (969~990) 22 979,
2035 11:04:29.085360 TX Bit4 (981~1004) 24 992, Bit12 (971~994) 24 982,
2036 11:04:29.092271 TX Bit5 (979~1001) 23 990, Bit13 (972~994) 23 983,
2037 11:04:29.095408 TX Bit6 (980~1001) 22 990, Bit14 (972~995) 24 983,
2038 11:04:29.102761 TX Bit7 (982~1004) 23 993, Bit15 (975~996) 22 985,
2039 11:04:29.102893
2040 11:04:29.102993 Write Rank1 MR14 =0x18
2041 11:04:29.113556
2042 11:04:29.116290 CH=0, VrefRange= 0, VrefLevel = 24
2043 11:04:29.119414 TX Bit0 (983~1007) 25 995, Bit8 (968~991) 24 979,
2044 11:04:29.122692 TX Bit1 (982~1005) 24 993, Bit9 (970~994) 25 982,
2045 11:04:29.129620 TX Bit2 (983~1006) 24 994, Bit10 (975~997) 23 986,
2046 11:04:29.132679 TX Bit3 (978~997) 20 987, Bit11 (969~991) 23 980,
2047 11:04:29.136516 TX Bit4 (981~1005) 25 993, Bit12 (971~994) 24 982,
2048 11:04:29.143510 TX Bit5 (979~1001) 23 990, Bit13 (971~995) 25 983,
2049 11:04:29.145965 TX Bit6 (980~1003) 24 991, Bit14 (971~995) 25 983,
2050 11:04:29.153127 TX Bit7 (983~1005) 23 994, Bit15 (976~997) 22 986,
2051 11:04:29.153253
2052 11:04:29.153313 Write Rank1 MR14 =0x1a
2053 11:04:29.163581
2054 11:04:29.166699 CH=0, VrefRange= 0, VrefLevel = 26
2055 11:04:29.170255 TX Bit0 (983~1007) 25 995, Bit8 (968~992) 25 980,
2056 11:04:29.173753 TX Bit1 (981~1006) 26 993, Bit9 (969~994) 26 981,
2057 11:04:29.180544 TX Bit2 (983~1007) 25 995, Bit10 (975~997) 23 986,
2058 11:04:29.183355 TX Bit3 (978~998) 21 988, Bit11 (969~992) 24 980,
2059 11:04:29.187093 TX Bit4 (981~1006) 26 993, Bit12 (971~995) 25 983,
2060 11:04:29.193400 TX Bit5 (979~1003) 25 991, Bit13 (971~995) 25 983,
2061 11:04:29.196633 TX Bit6 (980~1004) 25 992, Bit14 (971~996) 26 983,
2062 11:04:29.203327 TX Bit7 (982~1006) 25 994, Bit15 (975~997) 23 986,
2063 11:04:29.203472
2064 11:04:29.203559 Write Rank1 MR14 =0x1c
2065 11:04:29.214290
2066 11:04:29.218059 CH=0, VrefRange= 0, VrefLevel = 28
2067 11:04:29.221379 TX Bit0 (983~1008) 26 995, Bit8 (968~992) 25 980,
2068 11:04:29.224452 TX Bit1 (981~1007) 27 994, Bit9 (969~994) 26 981,
2069 11:04:29.231024 TX Bit2 (982~1007) 26 994, Bit10 (975~998) 24 986,
2070 11:04:29.234521 TX Bit3 (978~999) 22 988, Bit11 (969~992) 24 980,
2071 11:04:29.237625 TX Bit4 (980~1007) 28 993, Bit12 (970~995) 26 982,
2072 11:04:29.244939 TX Bit5 (979~1003) 25 991, Bit13 (970~994) 25 982,
2073 11:04:29.248110 TX Bit6 (979~1003) 25 991, Bit14 (971~996) 26 983,
2074 11:04:29.254806 TX Bit7 (981~1006) 26 993, Bit15 (975~998) 24 986,
2075 11:04:29.254883
2076 11:04:29.254941 Write Rank1 MR14 =0x1e
2077 11:04:29.264888
2078 11:04:29.268467 CH=0, VrefRange= 0, VrefLevel = 30
2079 11:04:29.271802 TX Bit0 (983~1008) 26 995, Bit8 (968~992) 25 980,
2080 11:04:29.274922 TX Bit1 (981~1007) 27 994, Bit9 (969~994) 26 981,
2081 11:04:29.281975 TX Bit2 (982~1007) 26 994, Bit10 (975~998) 24 986,
2082 11:04:29.285113 TX Bit3 (978~999) 22 988, Bit11 (969~992) 24 980,
2083 11:04:29.289030 TX Bit4 (980~1007) 28 993, Bit12 (970~995) 26 982,
2084 11:04:29.292987 TX Bit5 (979~1003) 25 991, Bit13 (970~994) 25 982,
2085 11:04:29.297627 TX Bit6 (979~1003) 25 991, Bit14 (971~996) 26 983,
2086 11:04:29.304911 TX Bit7 (981~1006) 26 993, Bit15 (975~998) 24 986,
2087 11:04:29.304992
2088 11:04:29.305052 Write Rank1 MR14 =0x20
2089 11:04:29.316094
2090 11:04:29.319378 CH=0, VrefRange= 0, VrefLevel = 32
2091 11:04:29.322907 TX Bit0 (983~1008) 26 995, Bit8 (968~991) 24 979,
2092 11:04:29.326310 TX Bit1 (981~1007) 27 994, Bit9 (971~993) 23 982,
2093 11:04:29.332426 TX Bit2 (983~1008) 26 995, Bit10 (975~997) 23 986,
2094 11:04:29.336196 TX Bit3 (978~1000) 23 989, Bit11 (968~993) 26 980,
2095 11:04:29.339547 TX Bit4 (981~1007) 27 994, Bit12 (970~995) 26 982,
2096 11:04:29.346435 TX Bit5 (979~1002) 24 990, Bit13 (970~993) 24 981,
2097 11:04:29.349884 TX Bit6 (980~1004) 25 992, Bit14 (972~995) 24 983,
2098 11:04:29.352826 TX Bit7 (980~1007) 28 993, Bit15 (974~997) 24 985,
2099 11:04:29.352900
2100 11:04:29.356157 Write Rank1 MR14 =0x22
2101 11:04:29.367026
2102 11:04:29.370301 CH=0, VrefRange= 0, VrefLevel = 34
2103 11:04:29.373916 TX Bit0 (983~1008) 26 995, Bit8 (968~991) 24 979,
2104 11:04:29.377625 TX Bit1 (981~1007) 27 994, Bit9 (971~993) 23 982,
2105 11:04:29.380787 TX Bit2 (983~1008) 26 995, Bit10 (975~997) 23 986,
2106 11:04:29.388094 TX Bit3 (978~1000) 23 989, Bit11 (968~993) 26 980,
2107 11:04:29.391383 TX Bit4 (981~1007) 27 994, Bit12 (970~995) 26 982,
2108 11:04:29.398076 TX Bit5 (979~1002) 24 990, Bit13 (970~993) 24 981,
2109 11:04:29.400912 TX Bit6 (980~1004) 25 992, Bit14 (972~995) 24 983,
2110 11:04:29.405042 TX Bit7 (980~1007) 28 993, Bit15 (974~997) 24 985,
2111 11:04:29.405179
2112 11:04:29.407621 Write Rank1 MR14 =0x24
2113 11:04:29.417441
2114 11:04:29.421351 CH=0, VrefRange= 0, VrefLevel = 36
2115 11:04:29.424333 TX Bit0 (983~1008) 26 995, Bit8 (968~991) 24 979,
2116 11:04:29.427667 TX Bit1 (981~1007) 27 994, Bit9 (971~993) 23 982,
2117 11:04:29.434255 TX Bit2 (983~1008) 26 995, Bit10 (975~997) 23 986,
2118 11:04:29.437764 TX Bit3 (978~1000) 23 989, Bit11 (968~993) 26 980,
2119 11:04:29.440966 TX Bit4 (981~1007) 27 994, Bit12 (970~995) 26 982,
2120 11:04:29.448445 TX Bit5 (979~1002) 24 990, Bit13 (970~993) 24 981,
2121 11:04:29.451116 TX Bit6 (980~1004) 25 992, Bit14 (972~995) 24 983,
2122 11:04:29.457868 TX Bit7 (980~1007) 28 993, Bit15 (974~997) 24 985,
2123 11:04:29.457941
2124 11:04:29.457999
2125 11:04:29.461216 TX Vref found, early break! 376< 380
2126 11:04:29.464588 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =833/100 ps
2127 11:04:29.467598 u1DelayCellOfst[0]=7 cells (6 PI)
2128 11:04:29.471399 u1DelayCellOfst[1]=5 cells (5 PI)
2129 11:04:29.474742 u1DelayCellOfst[2]=7 cells (6 PI)
2130 11:04:29.478419 u1DelayCellOfst[3]=0 cells (0 PI)
2131 11:04:29.481191 u1DelayCellOfst[4]=5 cells (5 PI)
2132 11:04:29.481259 u1DelayCellOfst[5]=1 cells (1 PI)
2133 11:04:29.484660 u1DelayCellOfst[6]=3 cells (3 PI)
2134 11:04:29.487761 u1DelayCellOfst[7]=4 cells (4 PI)
2135 11:04:29.491291 Byte0, DQ PI dly=989, DQM PI dly= 992
2136 11:04:29.497975 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
2137 11:04:29.498043
2138 11:04:29.501963 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
2139 11:04:29.502029
2140 11:04:29.504892 u1DelayCellOfst[8]=0 cells (0 PI)
2141 11:04:29.508019 u1DelayCellOfst[9]=3 cells (3 PI)
2142 11:04:29.511521 u1DelayCellOfst[10]=8 cells (7 PI)
2143 11:04:29.514790 u1DelayCellOfst[11]=1 cells (1 PI)
2144 11:04:29.517921 u1DelayCellOfst[12]=3 cells (3 PI)
2145 11:04:29.517986 u1DelayCellOfst[13]=2 cells (2 PI)
2146 11:04:29.521706 u1DelayCellOfst[14]=4 cells (4 PI)
2147 11:04:29.524573 u1DelayCellOfst[15]=7 cells (6 PI)
2148 11:04:29.528464 Byte1, DQ PI dly=979, DQM PI dly= 982
2149 11:04:29.534785 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2150 11:04:29.534862
2151 11:04:29.538303 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2152 11:04:29.538369
2153 11:04:29.541677 Write Rank1 MR14 =0x20
2154 11:04:29.541741
2155 11:04:29.541794 Final TX Range 0 Vref 32
2156 11:04:29.541845
2157 11:04:29.548389 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2158 11:04:29.548462
2159 11:04:29.555033 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2160 11:04:29.561620 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2161 11:04:29.571660 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2162 11:04:29.571743 Write Rank1 MR3 =0xb0
2163 11:04:29.574798 DramC Write-DBI on
2164 11:04:29.574862 ==
2165 11:04:29.578403 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2166 11:04:29.581179 fsp= 1, odt_onoff= 1, Byte mode= 0
2167 11:04:29.581243 ==
2168 11:04:29.588256 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2169 11:04:29.588336
2170 11:04:29.588397 Begin, DQ Scan Range 702~766
2171 11:04:29.588452
2172 11:04:29.588504
2173 11:04:29.592040 TX Vref Scan disable
2174 11:04:29.594913 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2175 11:04:29.597923 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2176 11:04:29.601281 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2177 11:04:29.605085 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2178 11:04:29.608354 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2179 11:04:29.611712 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2180 11:04:29.615191 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2181 11:04:29.618357 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2182 11:04:29.621732 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2183 11:04:29.625076 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2184 11:04:29.628087 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2185 11:04:29.631405 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2186 11:04:29.635211 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2187 11:04:29.641594 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2188 11:04:29.644797 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2189 11:04:29.648640 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2190 11:04:29.651916 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2191 11:04:29.655574 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2192 11:04:29.658404 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2193 11:04:29.661573 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2194 11:04:29.665079 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2195 11:04:29.668672 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
2196 11:04:29.671737 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
2197 11:04:29.679873 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2198 11:04:29.682939 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2199 11:04:29.686690 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2200 11:04:29.689803 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2201 11:04:29.692983 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2202 11:04:29.696546 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2203 11:04:29.699821 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2204 11:04:29.702851 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2205 11:04:29.707153 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2206 11:04:29.709818 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
2207 11:04:29.713895 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
2208 11:04:29.716673 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
2209 11:04:29.719624 Byte0, DQ PI dly=738, DQM PI dly= 738
2210 11:04:29.722932 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 34)
2211 11:04:29.726382
2212 11:04:29.729727 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 34)
2213 11:04:29.729797
2214 11:04:29.733578 Byte1, DQ PI dly=727, DQM PI dly= 727
2215 11:04:29.736808 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 23)
2216 11:04:29.736873
2217 11:04:29.739911 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 23)
2218 11:04:29.739976
2219 11:04:29.746621 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2220 11:04:29.756748 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2221 11:04:29.764169 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2222 11:04:29.764246 Write Rank1 MR3 =0x30
2223 11:04:29.767027 DramC Write-DBI off
2224 11:04:29.767093
2225 11:04:29.767147 [DATLAT]
2226 11:04:29.770977 Freq=1600, CH0 RK1, use_rxtx_scan=0
2227 11:04:29.771042
2228 11:04:29.773672 DATLAT Default: 0x10
2229 11:04:29.773737 7, 0xFFFF, sum=0
2230 11:04:29.776532 8, 0xFFFF, sum=0
2231 11:04:29.776596 9, 0xFFFF, sum=0
2232 11:04:29.780418 10, 0xFFFF, sum=0
2233 11:04:29.780484 11, 0xFFFF, sum=0
2234 11:04:29.780537 12, 0xFFFF, sum=0
2235 11:04:29.783855 13, 0xFFFF, sum=0
2236 11:04:29.783917 14, 0x0, sum=1
2237 11:04:29.786579 15, 0x0, sum=2
2238 11:04:29.786668 16, 0x0, sum=3
2239 11:04:29.789981 17, 0x0, sum=4
2240 11:04:29.793229 pattern=2 first_step=14 total pass=5 best_step=16
2241 11:04:29.793292 ==
2242 11:04:29.799970 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2243 11:04:29.800050 fsp= 1, odt_onoff= 1, Byte mode= 0
2244 11:04:29.803103 ==
2245 11:04:29.806589 Start DQ dly to find pass range UseTestEngine =1
2246 11:04:29.809862 x-axis: bit #, y-axis: DQ dly (-127~63)
2247 11:04:29.809938 RX Vref Scan = 0
2248 11:04:29.813684 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2249 11:04:29.817105 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2250 11:04:29.820044 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2251 11:04:29.824012 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2252 11:04:29.826864 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2253 11:04:29.830103 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2254 11:04:29.833582 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2255 11:04:29.833660 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2256 11:04:29.836721 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2257 11:04:29.840358 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2258 11:04:29.843589 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2259 11:04:29.846841 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2260 11:04:29.850007 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2261 11:04:29.854261 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2262 11:04:29.857272 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2263 11:04:29.857350 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2264 11:04:29.860261 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2265 11:04:29.863590 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2266 11:04:29.867191 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2267 11:04:29.870301 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2268 11:04:29.873998 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2269 11:04:29.877512 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2270 11:04:29.877590 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2271 11:04:29.880884 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2272 11:04:29.883429 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2273 11:04:29.887581 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2274 11:04:29.890242 0, [0] xxxxxxxx xxxxxxxx [MSB]
2275 11:04:29.893682 1, [0] xxxxxxxx xxxxxxxx [MSB]
2276 11:04:29.893761 2, [0] xxxoxxxx xxxxxxxx [MSB]
2277 11:04:29.896958 3, [0] xxxoxxxx oxxxxxxx [MSB]
2278 11:04:29.900610 4, [0] xxxoxoxx oxxoxxxx [MSB]
2279 11:04:29.904079 5, [0] xxxoxoox oxxoxxxx [MSB]
2280 11:04:29.907292 6, [0] xxxoxoox ooxooxxx [MSB]
2281 11:04:29.907370 7, [0] xxxoxooo ooxooxxx [MSB]
2282 11:04:29.911153 8, [0] xoxoxooo ooxoooox [MSB]
2283 11:04:29.914461 9, [0] xoxoxooo ooxoooox [MSB]
2284 11:04:29.917323 10, [0] oooooooo ooxooooo [MSB]
2285 11:04:29.920566 11, [0] oooooooo ooxooooo [MSB]
2286 11:04:29.924233 33, [0] oooxoooo xooxoooo [MSB]
2287 11:04:29.927232 34, [0] oooxoooo xooxoooo [MSB]
2288 11:04:29.930806 35, [0] oooxoxoo xxoxoxoo [MSB]
2289 11:04:29.933924 36, [0] oooxoxxo xxoxoxoo [MSB]
2290 11:04:29.937700 37, [0] oooxoxxo xxoxxxoo [MSB]
2291 11:04:29.937778 38, [0] oooxxxxx xxoxxxxo [MSB]
2292 11:04:29.940993 39, [0] oooxxxxx xxoxxxxo [MSB]
2293 11:04:29.944265 40, [0] xxxxxxxx xxoxxxxx [MSB]
2294 11:04:29.947603 41, [0] xxxxxxxx xxoxxxxx [MSB]
2295 11:04:29.951345 42, [0] xxxxxxxx xxxxxxxx [MSB]
2296 11:04:29.954348 iDelay=42, Bit 0, Center 24 (10 ~ 39) 30
2297 11:04:29.957794 iDelay=42, Bit 1, Center 23 (8 ~ 39) 32
2298 11:04:29.961356 iDelay=42, Bit 2, Center 24 (10 ~ 39) 30
2299 11:04:29.964319 iDelay=42, Bit 3, Center 17 (2 ~ 32) 31
2300 11:04:29.967843 iDelay=42, Bit 4, Center 23 (10 ~ 37) 28
2301 11:04:29.971583 iDelay=42, Bit 5, Center 19 (4 ~ 34) 31
2302 11:04:29.974531 iDelay=42, Bit 6, Center 20 (5 ~ 35) 31
2303 11:04:29.977437 iDelay=42, Bit 7, Center 22 (7 ~ 37) 31
2304 11:04:29.981590 iDelay=42, Bit 8, Center 17 (3 ~ 32) 30
2305 11:04:29.984460 iDelay=42, Bit 9, Center 20 (6 ~ 34) 29
2306 11:04:29.991322 iDelay=42, Bit 10, Center 26 (12 ~ 41) 30
2307 11:04:29.994416 iDelay=42, Bit 11, Center 18 (4 ~ 32) 29
2308 11:04:29.997645 iDelay=42, Bit 12, Center 21 (6 ~ 36) 31
2309 11:04:30.000810 iDelay=42, Bit 13, Center 21 (8 ~ 34) 27
2310 11:04:30.004333 iDelay=42, Bit 14, Center 22 (8 ~ 37) 30
2311 11:04:30.008481 iDelay=42, Bit 15, Center 24 (10 ~ 39) 30
2312 11:04:30.008559 ==
2313 11:04:30.014163 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2314 11:04:30.014240 fsp= 1, odt_onoff= 1, Byte mode= 0
2315 11:04:30.018414 ==
2316 11:04:30.018489 DQS Delay:
2317 11:04:30.018548 DQS0 = 0, DQS1 = 0
2318 11:04:30.020964 DQM Delay:
2319 11:04:30.021039 DQM0 = 21, DQM1 = 21
2320 11:04:30.024698 DQ Delay:
2321 11:04:30.027935 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =17
2322 11:04:30.028011 DQ4 =23, DQ5 =19, DQ6 =20, DQ7 =22
2323 11:04:30.031538 DQ8 =17, DQ9 =20, DQ10 =26, DQ11 =18
2324 11:04:30.034262 DQ12 =21, DQ13 =21, DQ14 =22, DQ15 =24
2325 11:04:30.038142
2326 11:04:30.038219
2327 11:04:30.038278
2328 11:04:30.038331 [DramC_TX_OE_Calibration] TA2
2329 11:04:30.041078 Original DQ_B0 (3 6) =30, OEN = 27
2330 11:04:30.044451 Original DQ_B1 (3 6) =30, OEN = 27
2331 11:04:30.047543 23, 0x0, End_B0=23 End_B1=23
2332 11:04:30.051393 24, 0x0, End_B0=24 End_B1=24
2333 11:04:30.055233 25, 0x0, End_B0=25 End_B1=25
2334 11:04:30.055310 26, 0x0, End_B0=26 End_B1=26
2335 11:04:30.057452 27, 0x0, End_B0=27 End_B1=27
2336 11:04:30.061161 28, 0x0, End_B0=28 End_B1=28
2337 11:04:30.064290 29, 0x0, End_B0=29 End_B1=29
2338 11:04:30.067511 30, 0x0, End_B0=30 End_B1=30
2339 11:04:30.067588 31, 0xFBFF, End_B0=30 End_B1=30
2340 11:04:30.074275 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2341 11:04:30.081013 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2342 11:04:30.081092
2343 11:04:30.081195
2344 11:04:30.081250 Write Rank1 MR23 =0x3f
2345 11:04:30.084161 [DQSOSC]
2346 11:04:30.090849 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
2347 11:04:30.097375 CH0_RK1: MR19=0x202, MR18=0xB7B7, DQSOSC=453, MR23=63, INC=11, DEC=17
2348 11:04:30.100933 Write Rank1 MR23 =0x3f
2349 11:04:30.101033 [DQSOSC]
2350 11:04:30.107854 [DQSOSCAuto] RK1, (LSB)MR18= 0xb8b8, (MSB)MR19= 0x202, tDQSOscB0 = 452 ps tDQSOscB1 = 452 ps
2351 11:04:30.110846 CH0 RK1: MR19=202, MR18=B8B8
2352 11:04:30.114287 [RxdqsGatingPostProcess] freq 1600
2353 11:04:30.120857 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2354 11:04:30.120939 Rank: 0
2355 11:04:30.123877 best DQS0 dly(2T, 0.5T) = (2, 6)
2356 11:04:30.127534 best DQS1 dly(2T, 0.5T) = (2, 6)
2357 11:04:30.131105 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2358 11:04:30.134060 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2359 11:04:30.134142 Rank: 1
2360 11:04:30.137334 best DQS0 dly(2T, 0.5T) = (2, 6)
2361 11:04:30.140805 best DQS1 dly(2T, 0.5T) = (2, 6)
2362 11:04:30.144176 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2363 11:04:30.144282 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2364 11:04:30.150624 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2365 11:04:30.154092 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2366 11:04:30.157730 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2367 11:04:30.160532 Write Rank0 MR13 =0x59
2368 11:04:30.160687 ==
2369 11:04:30.166992 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2370 11:04:30.170948 fsp= 1, odt_onoff= 1, Byte mode= 0
2371 11:04:30.171045 ==
2372 11:04:30.171119 === u2Vref_new: 0x56 --> 0x3a
2373 11:04:30.174201 === u2Vref_new: 0x58 --> 0x58
2374 11:04:30.177310 === u2Vref_new: 0x5a --> 0x5a
2375 11:04:30.180816 === u2Vref_new: 0x5c --> 0x78
2376 11:04:30.184432 === u2Vref_new: 0x5e --> 0x7a
2377 11:04:30.187583 === u2Vref_new: 0x60 --> 0x90
2378 11:04:30.191226 [CA 0] Center 37 (12~63) winsize 52
2379 11:04:30.193921 [CA 1] Center 37 (12~63) winsize 52
2380 11:04:30.197429 [CA 2] Center 34 (6~63) winsize 58
2381 11:04:30.201089 [CA 3] Center 35 (7~63) winsize 57
2382 11:04:30.203904 [CA 4] Center 35 (7~63) winsize 57
2383 11:04:30.207258 [CA 5] Center 29 (0~58) winsize 59
2384 11:04:30.207335
2385 11:04:30.210718 [CATrainingPosCal] consider 1 rank data
2386 11:04:30.214222 u2DelayCellTimex100 = 833/100 ps
2387 11:04:30.217916 CA0 delay=37 (12~63),Diff = 8 PI (9 cell)
2388 11:04:30.221289 CA1 delay=37 (12~63),Diff = 8 PI (9 cell)
2389 11:04:30.223954 CA2 delay=34 (6~63),Diff = 5 PI (5 cell)
2390 11:04:30.227643 CA3 delay=35 (7~63),Diff = 6 PI (7 cell)
2391 11:04:30.231004 CA4 delay=35 (7~63),Diff = 6 PI (7 cell)
2392 11:04:30.234162 CA5 delay=29 (0~58),Diff = 0 PI (0 cell)
2393 11:04:30.234246
2394 11:04:30.240997 CA PerBit enable=1, Macro0, CA PI delay=29
2395 11:04:30.241102 === u2Vref_new: 0x60 --> 0x90
2396 11:04:30.241221
2397 11:04:30.243984 Vref(ca) range 1: 32
2398 11:04:30.244065
2399 11:04:30.247460 CS Dly= 11 (42-0-32)
2400 11:04:30.247536 Write Rank0 MR13 =0xd8
2401 11:04:30.250906 Write Rank0 MR13 =0xd8
2402 11:04:30.250974 Write Rank0 MR12 =0x60
2403 11:04:30.253872 Write Rank1 MR13 =0x59
2404 11:04:30.253947 ==
2405 11:04:30.260518 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2406 11:04:30.264090 fsp= 1, odt_onoff= 1, Byte mode= 0
2407 11:04:30.264164 ==
2408 11:04:30.267400 === u2Vref_new: 0x56 --> 0x3a
2409 11:04:30.267475 === u2Vref_new: 0x58 --> 0x58
2410 11:04:30.270717 === u2Vref_new: 0x5a --> 0x5a
2411 11:04:30.274126 === u2Vref_new: 0x5c --> 0x78
2412 11:04:30.277617 === u2Vref_new: 0x5e --> 0x7a
2413 11:04:30.280996 === u2Vref_new: 0x60 --> 0x90
2414 11:04:30.284286 [CA 0] Center 37 (11~63) winsize 53
2415 11:04:30.287711 [CA 1] Center 37 (11~63) winsize 53
2416 11:04:30.290871 [CA 2] Center 35 (7~63) winsize 57
2417 11:04:30.293842 [CA 3] Center 34 (6~63) winsize 58
2418 11:04:30.297324 [CA 4] Center 33 (4~63) winsize 60
2419 11:04:30.300779 [CA 5] Center 27 (-1~56) winsize 58
2420 11:04:30.300853
2421 11:04:30.304572 [CATrainingPosCal] consider 2 rank data
2422 11:04:30.308003 u2DelayCellTimex100 = 833/100 ps
2423 11:04:30.311221 CA0 delay=37 (12~63),Diff = 9 PI (10 cell)
2424 11:04:30.315241 CA1 delay=37 (12~63),Diff = 9 PI (10 cell)
2425 11:04:30.317834 CA2 delay=35 (7~63),Diff = 7 PI (8 cell)
2426 11:04:30.320909 CA3 delay=35 (7~63),Diff = 7 PI (8 cell)
2427 11:04:30.324072 CA4 delay=35 (7~63),Diff = 7 PI (8 cell)
2428 11:04:30.327714 CA5 delay=28 (0~56),Diff = 0 PI (0 cell)
2429 11:04:30.330882
2430 11:04:30.334235 CA PerBit enable=1, Macro0, CA PI delay=28
2431 11:04:30.334310 === u2Vref_new: 0x5e --> 0x7a
2432 11:04:30.337968
2433 11:04:30.338042 Vref(ca) range 1: 30
2434 11:04:30.338099
2435 11:04:30.340561 CS Dly= 10 (41-0-32)
2436 11:04:30.340635 Write Rank1 MR13 =0xd8
2437 11:04:30.343824 Write Rank1 MR13 =0xd8
2438 11:04:30.347150 Write Rank1 MR12 =0x5e
2439 11:04:30.350505 [RankSwap] Rank num 2, (Multi 1), Rank 0
2440 11:04:30.350579 Write Rank0 MR2 =0xad
2441 11:04:30.353766 [Write Leveling]
2442 11:04:30.357477 delay byte0 byte1 byte2 byte3
2443 11:04:30.357552
2444 11:04:30.357610 10 0 0
2445 11:04:30.360898 11 0 0
2446 11:04:30.360976 12 0 0
2447 11:04:30.361040 13 0 0
2448 11:04:30.363871 14 0 0
2449 11:04:30.363947 15 0 0
2450 11:04:30.367632 16 0 0
2451 11:04:30.367708 17 0 0
2452 11:04:30.367766 18 0 0
2453 11:04:30.370563 19 0 0
2454 11:04:30.370638 20 0 0
2455 11:04:30.374092 21 0 0
2456 11:04:30.374167 22 0 0
2457 11:04:30.377273 23 0 0
2458 11:04:30.377348 24 0 0
2459 11:04:30.377408 25 0 0
2460 11:04:30.380772 26 0 0
2461 11:04:30.380847 27 0 0
2462 11:04:30.383898 28 0 0
2463 11:04:30.383973 29 0 0
2464 11:04:30.384031 30 0 0
2465 11:04:30.387601 31 0 0
2466 11:04:30.387677 32 0 ff
2467 11:04:30.391311 33 0 ff
2468 11:04:30.391388 34 0 ff
2469 11:04:30.394616 35 ff ff
2470 11:04:30.394692 36 ff ff
2471 11:04:30.394752 37 ff ff
2472 11:04:30.397527 38 ff ff
2473 11:04:30.397604 39 ff ff
2474 11:04:30.401360 40 ff ff
2475 11:04:30.401462 41 ff ff
2476 11:04:30.407881 pass bytecount = 0xff (0xff: all bytes pass)
2477 11:04:30.407957
2478 11:04:30.408016 DQS0 dly: 35
2479 11:04:30.408071 DQS1 dly: 32
2480 11:04:30.411485 Write Rank0 MR2 =0x2d
2481 11:04:30.414743 [RankSwap] Rank num 2, (Multi 1), Rank 0
2482 11:04:30.418267 Write Rank0 MR1 =0xd6
2483 11:04:30.418342 [Gating]
2484 11:04:30.418399 ==
2485 11:04:30.421003 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2486 11:04:30.423669 fsp= 1, odt_onoff= 1, Byte mode= 0
2487 11:04:30.427998 ==
2488 11:04:30.430426 3 1 0 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
2489 11:04:30.434126 3 1 4 |3534 2625 |(11 11)(11 11) |(0 0)(0 0)| 0
2490 11:04:30.437083 3 1 8 |3534 3231 |(11 11)(11 11) |(0 0)(1 1)| 0
2491 11:04:30.443845 3 1 12 |3534 1a1a |(11 11)(1 1) |(1 1)(1 1)| 0
2492 11:04:30.447227 3 1 16 |3534 303 |(11 11)(11 11) |(1 1)(1 1)| 0
2493 11:04:30.450637 3 1 20 |3534 302f |(11 11)(11 11) |(1 1)(0 0)| 0
2494 11:04:30.456901 3 1 24 |3534 2e2d |(11 11)(11 11) |(0 1)(1 1)| 0
2495 11:04:30.460531 3 1 28 |3534 2c2c |(11 11)(0 0) |(0 1)(1 1)| 0
2496 11:04:30.463977 3 2 0 |3534 2c2c |(11 11)(0 0) |(0 1)(1 1)| 0
2497 11:04:30.466985 [Byte 1] Lead/lag falling Transition (3, 2, 0)
2498 11:04:30.474042 3 2 4 |3534 1919 |(11 11)(11 11) |(0 1)(0 1)| 0
2499 11:04:30.477393 3 2 8 |3534 2726 |(11 11)(11 11) |(0 1)(0 1)| 0
2500 11:04:30.480497 3 2 12 |3534 2c2c |(11 11)(0 0) |(0 1)(1 0)| 0
2501 11:04:30.487326 3 2 16 |3534 2d2c |(11 11)(11 11) |(0 1)(1 0)| 0
2502 11:04:30.490328 3 2 20 |201 d0c |(11 11)(11 11) |(1 1)(0 1)| 0
2503 11:04:30.493618 3 2 24 |3d3d 2c2b |(11 11)(11 11) |(1 1)(0 1)| 0
2504 11:04:30.497320 [Byte 1] Lead/lag Transition tap number (7)
2505 11:04:30.503688 3 2 28 |3d3d 201 |(11 11)(11 11) |(1 1)(0 0)| 0
2506 11:04:30.507164 3 3 0 |3d3d 1b1b |(11 11)(11 11) |(1 1)(0 0)| 0
2507 11:04:30.510520 3 3 4 |3d3d 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
2508 11:04:30.516753 3 3 8 |3d3d 3636 |(11 11)(11 11) |(1 1)(1 1)| 0
2509 11:04:30.520069 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2510 11:04:30.523602 3 3 16 |3d3d 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
2511 11:04:30.529950 3 3 20 |3d3d 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
2512 11:04:30.533703 3 3 24 |707 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
2513 11:04:30.537416 3 3 28 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2514 11:04:30.540916 [Byte 0] Lead/lag falling Transition (3, 3, 28)
2515 11:04:30.546549 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2516 11:04:30.549964 [Byte 1] Lead/lag falling Transition (3, 4, 0)
2517 11:04:30.553358 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2518 11:04:30.559972 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2519 11:04:30.563301 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2520 11:04:30.566875 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2521 11:04:30.573280 3 4 20 |1515 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2522 11:04:30.576911 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2523 11:04:30.580004 3 4 28 |3d3d 807 |(11 11)(11 11) |(1 1)(1 1)| 0
2524 11:04:30.583481 3 5 0 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
2525 11:04:30.590252 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2526 11:04:30.593482 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2527 11:04:30.596653 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2528 11:04:30.603217 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2529 11:04:30.607113 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2530 11:04:30.610075 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2531 11:04:30.616622 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2532 11:04:30.620145 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2533 11:04:30.623305 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2534 11:04:30.626752 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2535 11:04:30.633149 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2536 11:04:30.636795 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2537 11:04:30.639687 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2538 11:04:30.646464 [Byte 0] Lead/lag Transition tap number (3)
2539 11:04:30.649646 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2540 11:04:30.653303 3 6 20 |404 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2541 11:04:30.656424 3 6 24 |1818 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2542 11:04:30.663109 [Byte 1] Lead/lag Transition tap number (3)
2543 11:04:30.666901 3 6 28 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2544 11:04:30.670195 [Byte 0]First pass (3, 6, 28)
2545 11:04:30.672881 3 7 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2546 11:04:30.676426 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2547 11:04:30.680120 [Byte 1]First pass (3, 7, 4)
2548 11:04:30.683345 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2549 11:04:30.686560 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2550 11:04:30.689583 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2551 11:04:30.696442 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2552 11:04:30.699778 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2553 11:04:30.702922 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2554 11:04:30.706353 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2555 11:04:30.712812 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2556 11:04:30.716013 All bytes gating window > 1UI, Early break!
2557 11:04:30.716087
2558 11:04:30.719697 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 14)
2559 11:04:30.719765
2560 11:04:30.722952 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 22)
2561 11:04:30.723022
2562 11:04:30.723077
2563 11:04:30.723129
2564 11:04:30.726158 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
2565 11:04:30.726219
2566 11:04:30.732561 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 22)
2567 11:04:30.732682
2568 11:04:30.732741
2569 11:04:30.732793 Write Rank0 MR1 =0x56
2570 11:04:30.732878
2571 11:04:30.736076 best RODT dly(2T, 0.5T) = (2, 3)
2572 11:04:30.736191
2573 11:04:30.739715 best RODT dly(2T, 0.5T) = (2, 3)
2574 11:04:30.739829 ==
2575 11:04:30.746257 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2576 11:04:30.749999 fsp= 1, odt_onoff= 1, Byte mode= 0
2577 11:04:30.750118 ==
2578 11:04:30.752953 Start DQ dly to find pass range UseTestEngine =0
2579 11:04:30.756293 x-axis: bit #, y-axis: DQ dly (-127~63)
2580 11:04:30.756394 RX Vref Scan = 0
2581 11:04:30.759501 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2582 11:04:30.763053 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2583 11:04:30.765940 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2584 11:04:30.769575 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2585 11:04:30.772521 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2586 11:04:30.776164 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2587 11:04:30.779612 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2588 11:04:30.782495 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2589 11:04:30.782592 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2590 11:04:30.786397 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2591 11:04:30.789433 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2592 11:04:30.792503 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2593 11:04:30.796200 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2594 11:04:30.799922 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2595 11:04:30.802598 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2596 11:04:30.805930 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2597 11:04:30.809725 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2598 11:04:30.809901 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2599 11:04:30.812922 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2600 11:04:30.815710 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2601 11:04:30.819605 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2602 11:04:30.822467 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2603 11:04:30.826221 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2604 11:04:30.829218 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2605 11:04:30.829541 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2606 11:04:30.832752 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2607 11:04:30.836014 0, [0] xxxxxxxx xxxxxxxo [MSB]
2608 11:04:30.839561 1, [0] xxxxxxxx xxxxxxxo [MSB]
2609 11:04:30.842656 2, [0] xxxxxxxx xoxxxxxo [MSB]
2610 11:04:30.845796 3, [0] xxxoxxxx ooxxxxxo [MSB]
2611 11:04:30.846126 4, [0] xxxoxxxx ooxxxxxo [MSB]
2612 11:04:30.849302 5, [0] xoooxxxx ooxxxxxo [MSB]
2613 11:04:30.852610 6, [0] xoooxxxo ooxxxxxo [MSB]
2614 11:04:30.856014 7, [0] xooooxxo oooxxxoo [MSB]
2615 11:04:30.859440 8, [0] oooooxoo oooooooo [MSB]
2616 11:04:30.863480 31, [0] oooooooo ooooooox [MSB]
2617 11:04:30.863883 32, [0] oooooooo ooooooox [MSB]
2618 11:04:30.865968 33, [0] oooooooo ooooooox [MSB]
2619 11:04:30.869202 34, [0] oooooooo oxooooox [MSB]
2620 11:04:30.872771 35, [0] ooxxoooo xxooooox [MSB]
2621 11:04:30.876411 36, [0] ooxxoooo xxooooox [MSB]
2622 11:04:30.879024 37, [0] ooxxoooo xxooooox [MSB]
2623 11:04:30.882753 38, [0] ooxxxooo xxxxoxox [MSB]
2624 11:04:30.883085 39, [0] oxxxxxox xxxxxxxx [MSB]
2625 11:04:30.886160 40, [0] oxxxxxox xxxxxxxx [MSB]
2626 11:04:30.889502 41, [0] xxxxxxxx xxxxxxxx [MSB]
2627 11:04:30.892772 iDelay=41, Bit 0, Center 24 (8 ~ 40) 33
2628 11:04:30.895878 iDelay=41, Bit 1, Center 21 (5 ~ 38) 34
2629 11:04:30.899754 iDelay=41, Bit 2, Center 19 (5 ~ 34) 30
2630 11:04:30.902896 iDelay=41, Bit 3, Center 18 (3 ~ 34) 32
2631 11:04:30.906024 iDelay=41, Bit 4, Center 22 (7 ~ 37) 31
2632 11:04:30.912697 iDelay=41, Bit 5, Center 23 (9 ~ 38) 30
2633 11:04:30.915710 iDelay=41, Bit 6, Center 24 (8 ~ 40) 33
2634 11:04:30.919494 iDelay=41, Bit 7, Center 22 (6 ~ 38) 33
2635 11:04:30.922753 iDelay=41, Bit 8, Center 18 (3 ~ 34) 32
2636 11:04:30.925682 iDelay=41, Bit 9, Center 17 (2 ~ 33) 32
2637 11:04:30.929075 iDelay=41, Bit 10, Center 22 (7 ~ 37) 31
2638 11:04:30.932282 iDelay=41, Bit 11, Center 22 (8 ~ 37) 30
2639 11:04:30.936271 iDelay=41, Bit 12, Center 23 (8 ~ 38) 31
2640 11:04:30.939207 iDelay=41, Bit 13, Center 22 (8 ~ 37) 30
2641 11:04:30.942561 iDelay=41, Bit 14, Center 22 (7 ~ 38) 32
2642 11:04:30.945706 iDelay=41, Bit 15, Center 15 (0 ~ 30) 31
2643 11:04:30.946092 ==
2644 11:04:30.952595 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2645 11:04:30.955526 fsp= 1, odt_onoff= 1, Byte mode= 0
2646 11:04:30.955910 ==
2647 11:04:30.956211 DQS Delay:
2648 11:04:30.959194 DQS0 = 0, DQS1 = 0
2649 11:04:30.959575 DQM Delay:
2650 11:04:30.962437 DQM0 = 21, DQM1 = 20
2651 11:04:30.962788 DQ Delay:
2652 11:04:30.965601 DQ0 =24, DQ1 =21, DQ2 =19, DQ3 =18
2653 11:04:30.969186 DQ4 =22, DQ5 =23, DQ6 =24, DQ7 =22
2654 11:04:30.972240 DQ8 =18, DQ9 =17, DQ10 =22, DQ11 =22
2655 11:04:30.975469 DQ12 =23, DQ13 =22, DQ14 =22, DQ15 =15
2656 11:04:30.975818
2657 11:04:30.976091
2658 11:04:30.979193 DramC Write-DBI off
2659 11:04:30.979542 ==
2660 11:04:30.981902 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2661 11:04:30.985588 fsp= 1, odt_onoff= 1, Byte mode= 0
2662 11:04:30.985944 ==
2663 11:04:30.988799 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2664 11:04:30.989184
2665 11:04:30.991989 Begin, DQ Scan Range 928~1184
2666 11:04:30.992351
2667 11:04:30.992670
2668 11:04:30.995431 TX Vref Scan disable
2669 11:04:30.998653 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2670 11:04:31.002521 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2671 11:04:31.005693 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2672 11:04:31.008478 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2673 11:04:31.012103 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2674 11:04:31.015441 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2675 11:04:31.018548 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2676 11:04:31.025170 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2677 11:04:31.028408 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2678 11:04:31.031514 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2679 11:04:31.035337 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2680 11:04:31.038244 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2681 11:04:31.042223 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2682 11:04:31.045113 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2683 11:04:31.048916 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2684 11:04:31.052039 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2685 11:04:31.055039 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2686 11:04:31.058683 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2687 11:04:31.061914 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2688 11:04:31.064934 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2689 11:04:31.068540 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2690 11:04:31.071836 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2691 11:04:31.075275 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2692 11:04:31.081881 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2693 11:04:31.085081 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2694 11:04:31.088091 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2695 11:04:31.091366 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2696 11:04:31.094732 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2697 11:04:31.098137 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2698 11:04:31.101498 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2699 11:04:31.104707 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2700 11:04:31.108083 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2701 11:04:31.111504 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2702 11:04:31.114701 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2703 11:04:31.118198 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2704 11:04:31.121839 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2705 11:04:31.124735 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2706 11:04:31.128149 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2707 11:04:31.131016 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2708 11:04:31.134357 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2709 11:04:31.138155 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2710 11:04:31.141358 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2711 11:04:31.148018 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2712 11:04:31.151075 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2713 11:04:31.154824 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2714 11:04:31.158234 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2715 11:04:31.161360 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2716 11:04:31.164734 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2717 11:04:31.168327 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2718 11:04:31.170978 977 |3 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2719 11:04:31.174767 978 |3 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2720 11:04:31.177541 979 |3 6 19|[0] xxxxxxxx ooxxxxxo [MSB]
2721 11:04:31.181391 980 |3 6 20|[0] xxxxxxxx ooxxxxxo [MSB]
2722 11:04:31.184815 981 |3 6 21|[0] xxxxxxxx ooxxxxoo [MSB]
2723 11:04:31.188217 982 |3 6 22|[0] xxxxxxxx oooxoxoo [MSB]
2724 11:04:31.191557 983 |3 6 23|[0] xxxxxxxx oooooxoo [MSB]
2725 11:04:31.194615 984 |3 6 24|[0] xxxxxxxx oooooooo [MSB]
2726 11:04:31.197472 985 |3 6 25|[0] oooooxoo oooooooo [MSB]
2727 11:04:31.206009 995 |3 6 35|[0] oooooooo ooooooox [MSB]
2728 11:04:31.208862 996 |3 6 36|[0] oooooooo ooooooox [MSB]
2729 11:04:31.212251 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2730 11:04:31.215594 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2731 11:04:31.219133 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2732 11:04:31.222617 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
2733 11:04:31.225773 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
2734 11:04:31.228950 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2735 11:04:31.232261 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2736 11:04:31.235585 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
2737 11:04:31.238958 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB]
2738 11:04:31.242284 1006 |3 6 46|[0] oooxoooo xxxxxxxx [MSB]
2739 11:04:31.249173 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2740 11:04:31.252195 Byte0, DQ PI dly=994, DQM PI dly= 994
2741 11:04:31.255955 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 34)
2742 11:04:31.256316
2743 11:04:31.258655 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 34)
2744 11:04:31.259012
2745 11:04:31.262872 Byte1, DQ PI dly=988, DQM PI dly= 988
2746 11:04:31.268857 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2747 11:04:31.269159
2748 11:04:31.271954 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2749 11:04:31.272193
2750 11:04:31.272346 ==
2751 11:04:31.275522 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2752 11:04:31.279254 fsp= 1, odt_onoff= 1, Byte mode= 0
2753 11:04:31.281661 ==
2754 11:04:31.285332 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2755 11:04:31.285602
2756 11:04:31.288406 Begin, DQ Scan Range 964~1028
2757 11:04:31.288522 Write Rank0 MR14 =0x0
2758 11:04:31.296945
2759 11:04:31.297064 CH=1, VrefRange= 0, VrefLevel = 0
2760 11:04:31.303793 TX Bit0 (988~1002) 15 995, Bit8 (981~993) 13 987,
2761 11:04:31.307508 TX Bit1 (986~999) 14 992, Bit9 (981~992) 12 986,
2762 11:04:31.313784 TX Bit2 (984~1000) 17 992, Bit10 (984~995) 12 989,
2763 11:04:31.317344 TX Bit3 (983~994) 12 988, Bit11 (985~996) 12 990,
2764 11:04:31.320506 TX Bit4 (986~1001) 16 993, Bit12 (985~995) 11 990,
2765 11:04:31.327240 TX Bit5 (988~1001) 14 994, Bit13 (985~993) 9 989,
2766 11:04:31.330341 TX Bit6 (986~1002) 17 994, Bit14 (984~995) 12 989,
2767 11:04:31.337154 TX Bit7 (986~1001) 16 993, Bit15 (979~988) 10 983,
2768 11:04:31.337256
2769 11:04:31.337328 Write Rank0 MR14 =0x2
2770 11:04:31.346055
2771 11:04:31.346151 CH=1, VrefRange= 0, VrefLevel = 2
2772 11:04:31.352592 TX Bit0 (987~1004) 18 995, Bit8 (981~993) 13 987,
2773 11:04:31.356107 TX Bit1 (985~1001) 17 993, Bit9 (982~993) 12 987,
2774 11:04:31.362674 TX Bit2 (984~1000) 17 992, Bit10 (984~995) 12 989,
2775 11:04:31.365704 TX Bit3 (983~996) 14 989, Bit11 (984~998) 15 991,
2776 11:04:31.368954 TX Bit4 (985~1002) 18 993, Bit12 (984~996) 13 990,
2777 11:04:31.375965 TX Bit5 (987~1003) 17 995, Bit13 (985~995) 11 990,
2778 11:04:31.379463 TX Bit6 (986~1002) 17 994, Bit14 (984~996) 13 990,
2779 11:04:31.386019 TX Bit7 (986~1001) 16 993, Bit15 (977~990) 14 983,
2780 11:04:31.386402
2781 11:04:31.386675 Write Rank0 MR14 =0x4
2782 11:04:31.394999
2783 11:04:31.395424 CH=1, VrefRange= 0, VrefLevel = 4
2784 11:04:31.401732 TX Bit0 (986~1004) 19 995, Bit8 (981~993) 13 987,
2785 11:04:31.405484 TX Bit1 (986~1001) 16 993, Bit9 (981~993) 13 987,
2786 11:04:31.411928 TX Bit2 (983~1001) 19 992, Bit10 (984~997) 14 990,
2787 11:04:31.415472 TX Bit3 (982~997) 16 989, Bit11 (984~998) 15 991,
2788 11:04:31.418281 TX Bit4 (985~1003) 19 994, Bit12 (984~998) 15 991,
2789 11:04:31.425558 TX Bit5 (987~1003) 17 995, Bit13 (985~996) 12 990,
2790 11:04:31.428773 TX Bit6 (985~1003) 19 994, Bit14 (984~997) 14 990,
2791 11:04:31.434902 TX Bit7 (986~1002) 17 994, Bit15 (977~991) 15 984,
2792 11:04:31.435267
2793 11:04:31.435547 Write Rank0 MR14 =0x6
2794 11:04:31.443897
2795 11:04:31.444301 CH=1, VrefRange= 0, VrefLevel = 6
2796 11:04:31.450755 TX Bit0 (987~1005) 19 996, Bit8 (980~994) 15 987,
2797 11:04:31.454125 TX Bit1 (985~1002) 18 993, Bit9 (980~994) 15 987,
2798 11:04:31.460570 TX Bit2 (983~1002) 20 992, Bit10 (983~997) 15 990,
2799 11:04:31.464050 TX Bit3 (981~998) 18 989, Bit11 (984~998) 15 991,
2800 11:04:31.467458 TX Bit4 (985~1004) 20 994, Bit12 (984~998) 15 991,
2801 11:04:31.474251 TX Bit5 (987~1004) 18 995, Bit13 (985~997) 13 991,
2802 11:04:31.477040 TX Bit6 (985~1004) 20 994, Bit14 (983~998) 16 990,
2803 11:04:31.484358 TX Bit7 (985~1003) 19 994, Bit15 (977~991) 15 984,
2804 11:04:31.484752
2805 11:04:31.485029 Write Rank0 MR14 =0x8
2806 11:04:31.492855
2807 11:04:31.493400 CH=1, VrefRange= 0, VrefLevel = 8
2808 11:04:31.499900 TX Bit0 (986~1005) 20 995, Bit8 (980~994) 15 987,
2809 11:04:31.503126 TX Bit1 (985~1003) 19 994, Bit9 (979~994) 16 986,
2810 11:04:31.509692 TX Bit2 (983~1003) 21 993, Bit10 (983~998) 16 990,
2811 11:04:31.513143 TX Bit3 (981~999) 19 990, Bit11 (984~999) 16 991,
2812 11:04:31.516420 TX Bit4 (985~1005) 21 995, Bit12 (984~999) 16 991,
2813 11:04:31.522874 TX Bit5 (986~1005) 20 995, Bit13 (984~998) 15 991,
2814 11:04:31.526341 TX Bit6 (985~1005) 21 995, Bit14 (983~999) 17 991,
2815 11:04:31.533245 TX Bit7 (985~1004) 20 994, Bit15 (976~992) 17 984,
2816 11:04:31.533628
2817 11:04:31.534027 Write Rank0 MR14 =0xa
2818 11:04:31.542314
2819 11:04:31.542693 CH=1, VrefRange= 0, VrefLevel = 10
2820 11:04:31.548991 TX Bit0 (986~1006) 21 996, Bit8 (979~996) 18 987,
2821 11:04:31.552165 TX Bit1 (985~1004) 20 994, Bit9 (979~995) 17 987,
2822 11:04:31.559203 TX Bit2 (983~1003) 21 993, Bit10 (983~999) 17 991,
2823 11:04:31.562060 TX Bit3 (980~999) 20 989, Bit11 (983~999) 17 991,
2824 11:04:31.565899 TX Bit4 (984~1005) 22 994, Bit12 (983~999) 17 991,
2825 11:04:31.572538 TX Bit5 (986~1005) 20 995, Bit13 (984~999) 16 991,
2826 11:04:31.575610 TX Bit6 (985~1006) 22 995, Bit14 (983~999) 17 991,
2827 11:04:31.582524 TX Bit7 (984~1004) 21 994, Bit15 (977~992) 16 984,
2828 11:04:31.582912
2829 11:04:31.583188 Write Rank0 MR14 =0xc
2830 11:04:31.591410
2831 11:04:31.595211 CH=1, VrefRange= 0, VrefLevel = 12
2832 11:04:31.598128 TX Bit0 (986~1006) 21 996, Bit8 (978~996) 19 987,
2833 11:04:31.602201 TX Bit1 (985~1004) 20 994, Bit9 (979~996) 18 987,
2834 11:04:31.608017 TX Bit2 (982~1004) 23 993, Bit10 (983~999) 17 991,
2835 11:04:31.611546 TX Bit3 (980~1000) 21 990, Bit11 (983~1000) 18 991,
2836 11:04:31.614772 TX Bit4 (984~1006) 23 995, Bit12 (983~999) 17 991,
2837 11:04:31.621879 TX Bit5 (986~1006) 21 996, Bit13 (984~999) 16 991,
2838 11:04:31.624682 TX Bit6 (984~1006) 23 995, Bit14 (982~999) 18 990,
2839 11:04:31.631071 TX Bit7 (985~1005) 21 995, Bit15 (976~992) 17 984,
2840 11:04:31.631508
2841 11:04:31.634796 wait MRW command Rank0 MR14 =0xe fired (1)
2842 11:04:31.635182 Write Rank0 MR14 =0xe
2843 11:04:31.645360
2844 11:04:31.648403 CH=1, VrefRange= 0, VrefLevel = 14
2845 11:04:31.651291 TX Bit0 (986~1007) 22 996, Bit8 (978~997) 20 987,
2846 11:04:31.654654 TX Bit1 (984~1005) 22 994, Bit9 (978~996) 19 987,
2847 11:04:31.661953 TX Bit2 (982~1005) 24 993, Bit10 (982~999) 18 990,
2848 11:04:31.664856 TX Bit3 (980~1001) 22 990, Bit11 (983~1000) 18 991,
2849 11:04:31.668646 TX Bit4 (984~1006) 23 995, Bit12 (983~1000) 18 991,
2850 11:04:31.675076 TX Bit5 (986~1006) 21 996, Bit13 (983~999) 17 991,
2851 11:04:31.678554 TX Bit6 (984~1006) 23 995, Bit14 (982~999) 18 990,
2852 11:04:31.684403 TX Bit7 (984~1005) 22 994, Bit15 (975~993) 19 984,
2853 11:04:31.684823
2854 11:04:31.685299 Write Rank0 MR14 =0x10
2855 11:04:31.694419
2856 11:04:31.697691 CH=1, VrefRange= 0, VrefLevel = 16
2857 11:04:31.701296 TX Bit0 (985~1007) 23 996, Bit8 (978~998) 21 988,
2858 11:04:31.704340 TX Bit1 (984~1006) 23 995, Bit9 (977~997) 21 987,
2859 11:04:31.711106 TX Bit2 (982~1005) 24 993, Bit10 (982~999) 18 990,
2860 11:04:31.714466 TX Bit3 (979~1001) 23 990, Bit11 (982~1000) 19 991,
2861 11:04:31.717988 TX Bit4 (984~1006) 23 995, Bit12 (982~1000) 19 991,
2862 11:04:31.724683 TX Bit5 (986~1006) 21 996, Bit13 (983~999) 17 991,
2863 11:04:31.727797 TX Bit6 (984~1006) 23 995, Bit14 (982~1000) 19 991,
2864 11:04:31.735067 TX Bit7 (984~1006) 23 995, Bit15 (976~993) 18 984,
2865 11:04:31.735454
2866 11:04:31.735726 Write Rank0 MR14 =0x12
2867 11:04:31.744228
2868 11:04:31.747510 CH=1, VrefRange= 0, VrefLevel = 18
2869 11:04:31.750941 TX Bit0 (985~1007) 23 996, Bit8 (977~998) 22 987,
2870 11:04:31.754323 TX Bit1 (984~1006) 23 995, Bit9 (977~997) 21 987,
2871 11:04:31.761087 TX Bit2 (981~1006) 26 993, Bit10 (982~1000) 19 991,
2872 11:04:31.764035 TX Bit3 (979~1002) 24 990, Bit11 (983~1001) 19 992,
2873 11:04:31.771081 TX Bit4 (983~1007) 25 995, Bit12 (982~1000) 19 991,
2874 11:04:31.774800 TX Bit5 (986~1007) 22 996, Bit13 (983~1000) 18 991,
2875 11:04:31.777496 TX Bit6 (984~1007) 24 995, Bit14 (981~1000) 20 990,
2876 11:04:31.784366 TX Bit7 (984~1006) 23 995, Bit15 (974~994) 21 984,
2877 11:04:31.784754
2878 11:04:31.785025 Write Rank0 MR14 =0x14
2879 11:04:31.794809
2880 11:04:31.797888 CH=1, VrefRange= 0, VrefLevel = 20
2881 11:04:31.801380 TX Bit0 (985~1007) 23 996, Bit8 (977~998) 22 987,
2882 11:04:31.804964 TX Bit1 (984~1006) 23 995, Bit9 (977~998) 22 987,
2883 11:04:31.811237 TX Bit2 (981~1006) 26 993, Bit10 (981~1000) 20 990,
2884 11:04:31.814420 TX Bit3 (979~1002) 24 990, Bit11 (982~1001) 20 991,
2885 11:04:31.821176 TX Bit4 (983~1007) 25 995, Bit12 (982~1001) 20 991,
2886 11:04:31.824083 TX Bit5 (985~1007) 23 996, Bit13 (983~1000) 18 991,
2887 11:04:31.827456 TX Bit6 (983~1007) 25 995, Bit14 (981~1000) 20 990,
2888 11:04:31.834294 TX Bit7 (983~1006) 24 994, Bit15 (975~994) 20 984,
2889 11:04:31.834653
2890 11:04:31.834931 Write Rank0 MR14 =0x16
2891 11:04:31.844717
2892 11:04:31.848165 CH=1, VrefRange= 0, VrefLevel = 22
2893 11:04:31.851331 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
2894 11:04:31.854996 TX Bit1 (983~1007) 25 995, Bit9 (977~999) 23 988,
2895 11:04:31.860986 TX Bit2 (980~1006) 27 993, Bit10 (982~1000) 19 991,
2896 11:04:31.864819 TX Bit3 (979~1003) 25 991, Bit11 (982~1001) 20 991,
2897 11:04:31.871101 TX Bit4 (982~1007) 26 994, Bit12 (982~1001) 20 991,
2898 11:04:31.874458 TX Bit5 (985~1007) 23 996, Bit13 (982~1000) 19 991,
2899 11:04:31.877431 TX Bit6 (983~1007) 25 995, Bit14 (981~1000) 20 990,
2900 11:04:31.884367 TX Bit7 (983~1007) 25 995, Bit15 (974~995) 22 984,
2901 11:04:31.884779
2902 11:04:31.887344 Write Rank0 MR14 =0x18
2903 11:04:31.894831
2904 11:04:31.898593 CH=1, VrefRange= 0, VrefLevel = 24
2905 11:04:31.901851 TX Bit0 (984~1008) 25 996, Bit8 (976~999) 24 987,
2906 11:04:31.904575 TX Bit1 (983~1007) 25 995, Bit9 (977~999) 23 988,
2907 11:04:31.911415 TX Bit2 (980~1006) 27 993, Bit10 (980~1001) 22 990,
2908 11:04:31.914682 TX Bit3 (979~1004) 26 991, Bit11 (981~1002) 22 991,
2909 11:04:31.921506 TX Bit4 (982~1007) 26 994, Bit12 (981~1001) 21 991,
2910 11:04:31.924405 TX Bit5 (985~1007) 23 996, Bit13 (982~1001) 20 991,
2911 11:04:31.928075 TX Bit6 (983~1007) 25 995, Bit14 (980~1001) 22 990,
2912 11:04:31.934589 TX Bit7 (983~1007) 25 995, Bit15 (973~995) 23 984,
2913 11:04:31.935061
2914 11:04:31.935489 Write Rank0 MR14 =0x1a
2915 11:04:31.944909
2916 11:04:31.948440 CH=1, VrefRange= 0, VrefLevel = 26
2917 11:04:31.951571 TX Bit0 (984~1008) 25 996, Bit8 (976~999) 24 987,
2918 11:04:31.955496 TX Bit1 (983~1007) 25 995, Bit9 (976~999) 24 987,
2919 11:04:31.961411 TX Bit2 (981~1007) 27 994, Bit10 (980~1001) 22 990,
2920 11:04:31.965042 TX Bit3 (978~1004) 27 991, Bit11 (981~1002) 22 991,
2921 11:04:31.971570 TX Bit4 (982~1007) 26 994, Bit12 (980~1002) 23 991,
2922 11:04:31.975017 TX Bit5 (984~1007) 24 995, Bit13 (982~1001) 20 991,
2923 11:04:31.978030 TX Bit6 (982~1007) 26 994, Bit14 (980~1001) 22 990,
2924 11:04:31.985096 TX Bit7 (982~1007) 26 994, Bit15 (973~997) 25 985,
2925 11:04:31.985532
2926 11:04:31.985830 Write Rank0 MR14 =0x1c
2927 11:04:31.994812
2928 11:04:31.998737 CH=1, VrefRange= 0, VrefLevel = 28
2929 11:04:32.001683 TX Bit0 (984~1008) 25 996, Bit8 (976~1000) 25 988,
2930 11:04:32.005410 TX Bit1 (983~1007) 25 995, Bit9 (976~999) 24 987,
2931 11:04:32.011342 TX Bit2 (980~1006) 27 993, Bit10 (979~1002) 24 990,
2932 11:04:32.015090 TX Bit3 (979~1005) 27 992, Bit11 (980~1002) 23 991,
2933 11:04:32.021435 TX Bit4 (983~1008) 26 995, Bit12 (980~1002) 23 991,
2934 11:04:32.025165 TX Bit5 (984~1008) 25 996, Bit13 (982~1001) 20 991,
2935 11:04:32.027968 TX Bit6 (982~1008) 27 995, Bit14 (979~1001) 23 990,
2936 11:04:32.034767 TX Bit7 (982~1007) 26 994, Bit15 (973~997) 25 985,
2937 11:04:32.035237
2938 11:04:32.037887 Write Rank0 MR14 =0x1e
2939 11:04:32.045636
2940 11:04:32.048547 CH=1, VrefRange= 0, VrefLevel = 30
2941 11:04:32.052281 TX Bit0 (984~1009) 26 996, Bit8 (976~1000) 25 988,
2942 11:04:32.055640 TX Bit1 (982~1007) 26 994, Bit9 (975~999) 25 987,
2943 11:04:32.062242 TX Bit2 (980~1006) 27 993, Bit10 (980~1002) 23 991,
2944 11:04:32.065806 TX Bit3 (978~1005) 28 991, Bit11 (979~1002) 24 990,
2945 11:04:32.071668 TX Bit4 (983~1007) 25 995, Bit12 (981~1001) 21 991,
2946 11:04:32.076096 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
2947 11:04:32.078688 TX Bit6 (982~1008) 27 995, Bit14 (980~1002) 23 991,
2948 11:04:32.085328 TX Bit7 (982~1007) 26 994, Bit15 (971~998) 28 984,
2949 11:04:32.085861
2950 11:04:32.086312 Write Rank0 MR14 =0x20
2951 11:04:32.095974
2952 11:04:32.099147 CH=1, VrefRange= 0, VrefLevel = 32
2953 11:04:32.102401 TX Bit0 (984~1009) 26 996, Bit8 (976~1000) 25 988,
2954 11:04:32.105642 TX Bit1 (982~1007) 26 994, Bit9 (975~999) 25 987,
2955 11:04:32.112528 TX Bit2 (980~1006) 27 993, Bit10 (980~1002) 23 991,
2956 11:04:32.115571 TX Bit3 (978~1005) 28 991, Bit11 (979~1002) 24 990,
2957 11:04:32.122515 TX Bit4 (983~1007) 25 995, Bit12 (981~1001) 21 991,
2958 11:04:32.125907 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
2959 11:04:32.128944 TX Bit6 (982~1008) 27 995, Bit14 (980~1002) 23 991,
2960 11:04:32.135458 TX Bit7 (982~1007) 26 994, Bit15 (971~998) 28 984,
2961 11:04:32.135809
2962 11:04:32.138811 Write Rank0 MR14 =0x22
2963 11:04:32.145985
2964 11:04:32.149674 CH=1, VrefRange= 0, VrefLevel = 34
2965 11:04:32.152760 TX Bit0 (984~1009) 26 996, Bit8 (976~1000) 25 988,
2966 11:04:32.156461 TX Bit1 (982~1007) 26 994, Bit9 (975~999) 25 987,
2967 11:04:32.162759 TX Bit2 (980~1006) 27 993, Bit10 (980~1002) 23 991,
2968 11:04:32.166240 TX Bit3 (978~1005) 28 991, Bit11 (979~1002) 24 990,
2969 11:04:32.172920 TX Bit4 (983~1007) 25 995, Bit12 (981~1001) 21 991,
2970 11:04:32.176353 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
2971 11:04:32.179984 TX Bit6 (982~1008) 27 995, Bit14 (980~1002) 23 991,
2972 11:04:32.185883 TX Bit7 (982~1007) 26 994, Bit15 (971~998) 28 984,
2973 11:04:32.186236
2974 11:04:32.186534 Write Rank0 MR14 =0x24
2975 11:04:32.196392
2976 11:04:32.199673 CH=1, VrefRange= 0, VrefLevel = 36
2977 11:04:32.203082 TX Bit0 (984~1009) 26 996, Bit8 (976~1000) 25 988,
2978 11:04:32.206673 TX Bit1 (982~1007) 26 994, Bit9 (975~999) 25 987,
2979 11:04:32.212870 TX Bit2 (980~1006) 27 993, Bit10 (980~1002) 23 991,
2980 11:04:32.216132 TX Bit3 (978~1005) 28 991, Bit11 (979~1002) 24 990,
2981 11:04:32.222552 TX Bit4 (983~1007) 25 995, Bit12 (981~1001) 21 991,
2982 11:04:32.226616 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
2983 11:04:32.229333 TX Bit6 (982~1008) 27 995, Bit14 (980~1002) 23 991,
2984 11:04:32.236140 TX Bit7 (982~1007) 26 994, Bit15 (971~998) 28 984,
2985 11:04:32.236524
2986 11:04:32.236795
2987 11:04:32.239188 TX Vref found, early break! 377< 380
2988 11:04:32.242545 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =833/100 ps
2989 11:04:32.246152 u1DelayCellOfst[0]=5 cells (5 PI)
2990 11:04:32.249619 u1DelayCellOfst[1]=3 cells (3 PI)
2991 11:04:32.252768 u1DelayCellOfst[2]=2 cells (2 PI)
2992 11:04:32.256459 u1DelayCellOfst[3]=0 cells (0 PI)
2993 11:04:32.259640 u1DelayCellOfst[4]=4 cells (4 PI)
2994 11:04:32.262539 u1DelayCellOfst[5]=5 cells (5 PI)
2995 11:04:32.266093 u1DelayCellOfst[6]=4 cells (4 PI)
2996 11:04:32.269159 u1DelayCellOfst[7]=3 cells (3 PI)
2997 11:04:32.272929 Byte0, DQ PI dly=991, DQM PI dly= 993
2998 11:04:32.275694 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
2999 11:04:32.275916
3000 11:04:32.279121 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
3001 11:04:32.279302
3002 11:04:32.282527 u1DelayCellOfst[8]=4 cells (4 PI)
3003 11:04:32.286131 u1DelayCellOfst[9]=3 cells (3 PI)
3004 11:04:32.289476 u1DelayCellOfst[10]=8 cells (7 PI)
3005 11:04:32.292768 u1DelayCellOfst[11]=7 cells (6 PI)
3006 11:04:32.295848 u1DelayCellOfst[12]=8 cells (7 PI)
3007 11:04:32.299484 u1DelayCellOfst[13]=8 cells (7 PI)
3008 11:04:32.302680 u1DelayCellOfst[14]=8 cells (7 PI)
3009 11:04:32.305684 u1DelayCellOfst[15]=0 cells (0 PI)
3010 11:04:32.309052 Byte1, DQ PI dly=984, DQM PI dly= 987
3011 11:04:32.312497 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
3012 11:04:32.312569
3013 11:04:32.315861 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
3014 11:04:32.315928
3015 11:04:32.318957 Write Rank0 MR14 =0x1e
3016 11:04:32.319024
3017 11:04:32.322232 Final TX Range 0 Vref 30
3018 11:04:32.322300
3019 11:04:32.328886 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3020 11:04:32.328955
3021 11:04:32.335599 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3022 11:04:32.342383 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3023 11:04:32.349070 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3024 11:04:32.351988 Write Rank0 MR3 =0xb0
3025 11:04:32.352108 DramC Write-DBI on
3026 11:04:32.352195 ==
3027 11:04:32.358995 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3028 11:04:32.362125 fsp= 1, odt_onoff= 1, Byte mode= 0
3029 11:04:32.362262 ==
3030 11:04:32.365678 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3031 11:04:32.365815
3032 11:04:32.369114 Begin, DQ Scan Range 707~771
3033 11:04:32.369287
3034 11:04:32.369406
3035 11:04:32.372212 TX Vref Scan disable
3036 11:04:32.375245 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3037 11:04:32.378714 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3038 11:04:32.381937 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3039 11:04:32.385386 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3040 11:04:32.388765 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3041 11:04:32.392275 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3042 11:04:32.395248 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3043 11:04:32.398834 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3044 11:04:32.402345 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3045 11:04:32.405350 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3046 11:04:32.408446 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3047 11:04:32.412347 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3048 11:04:32.415583 719 |2 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
3049 11:04:32.418404 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3050 11:04:32.422043 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3051 11:04:32.425612 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3052 11:04:32.431746 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3053 11:04:32.434783 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3054 11:04:32.438234 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3055 11:04:32.441634 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3056 11:04:32.444973 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3057 11:04:32.451752 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3058 11:04:32.454917 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3059 11:04:32.458503 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3060 11:04:32.461657 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3061 11:04:32.464901 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3062 11:04:32.468261 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3063 11:04:32.471417 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3064 11:04:32.474763 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3065 11:04:32.478142 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
3066 11:04:32.482154 754 |2 6 50|[0] xxxxxxxx xxxxxxxx [MSB]
3067 11:04:32.484995 Byte0, DQ PI dly=740, DQM PI dly= 740
3068 11:04:32.488471 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 36)
3069 11:04:32.491484
3070 11:04:32.495083 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 36)
3071 11:04:32.495178
3072 11:04:32.498559 Byte1, DQ PI dly=732, DQM PI dly= 732
3073 11:04:32.501771 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
3074 11:04:32.501885
3075 11:04:32.508342 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
3076 11:04:32.508468
3077 11:04:32.511786 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3078 11:04:32.521780 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3079 11:04:32.528124 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3080 11:04:32.528431 Write Rank0 MR3 =0x30
3081 11:04:32.532219 DramC Write-DBI off
3082 11:04:32.532585
3083 11:04:32.532950 [DATLAT]
3084 11:04:32.535088 Freq=1600, CH1 RK0, use_rxtx_scan=0
3085 11:04:32.535382
3086 11:04:32.538648 DATLAT Default: 0xf
3087 11:04:32.538976 7, 0xFFFF, sum=0
3088 11:04:32.542176 8, 0xFFFF, sum=0
3089 11:04:32.542616 9, 0xFFFF, sum=0
3090 11:04:32.545159 10, 0xFFFF, sum=0
3091 11:04:32.545540 11, 0xFFFF, sum=0
3092 11:04:32.548619 12, 0xFFFF, sum=0
3093 11:04:32.549112 13, 0xFFFF, sum=0
3094 11:04:32.551810 14, 0x0, sum=1
3095 11:04:32.552176 15, 0x0, sum=2
3096 11:04:32.552530 16, 0x0, sum=3
3097 11:04:32.555399 17, 0x0, sum=4
3098 11:04:32.558613 pattern=2 first_step=14 total pass=5 best_step=16
3099 11:04:32.559201 ==
3100 11:04:32.565202 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3101 11:04:32.568961 fsp= 1, odt_onoff= 1, Byte mode= 0
3102 11:04:32.569474 ==
3103 11:04:32.571945 Start DQ dly to find pass range UseTestEngine =1
3104 11:04:32.574893 x-axis: bit #, y-axis: DQ dly (-127~63)
3105 11:04:32.575313 RX Vref Scan = 1
3106 11:04:32.691557
3107 11:04:32.692000 RX Vref found, early break!
3108 11:04:32.692393
3109 11:04:32.698427 Final RX Vref 12, apply to both rank0 and 1
3110 11:04:32.698898 ==
3111 11:04:32.702135 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3112 11:04:32.705597 fsp= 1, odt_onoff= 1, Byte mode= 0
3113 11:04:32.706045 ==
3114 11:04:32.706361 DQS Delay:
3115 11:04:32.708635 DQS0 = 0, DQS1 = 0
3116 11:04:32.709036 DQM Delay:
3117 11:04:32.712091 DQM0 = 21, DQM1 = 19
3118 11:04:32.712510 DQ Delay:
3119 11:04:32.714956 DQ0 =23, DQ1 =21, DQ2 =20, DQ3 =19
3120 11:04:32.718316 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =23
3121 11:04:32.721701 DQ8 =18, DQ9 =16, DQ10 =21, DQ11 =22
3122 11:04:32.724904 DQ12 =22, DQ13 =22, DQ14 =21, DQ15 =16
3123 11:04:32.725384
3124 11:04:32.725701
3125 11:04:32.726069
3126 11:04:32.728849 [DramC_TX_OE_Calibration] TA2
3127 11:04:32.731411 Original DQ_B0 (3 6) =30, OEN = 27
3128 11:04:32.735373 Original DQ_B1 (3 6) =30, OEN = 27
3129 11:04:32.738355 23, 0x0, End_B0=23 End_B1=23
3130 11:04:32.738898 24, 0x0, End_B0=24 End_B1=24
3131 11:04:32.741354 25, 0x0, End_B0=25 End_B1=25
3132 11:04:32.745093 26, 0x0, End_B0=26 End_B1=26
3133 11:04:32.748535 27, 0x0, End_B0=27 End_B1=27
3134 11:04:32.748926 28, 0x0, End_B0=28 End_B1=28
3135 11:04:32.751820 29, 0x0, End_B0=29 End_B1=29
3136 11:04:32.755238 30, 0x0, End_B0=30 End_B1=30
3137 11:04:32.758350 31, 0xFFFF, End_B0=30 End_B1=30
3138 11:04:32.765235 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3139 11:04:32.768300 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3140 11:04:32.768696
3141 11:04:32.769221
3142 11:04:32.772030 Write Rank0 MR23 =0x3f
3143 11:04:32.772417 [DQSOSC]
3144 11:04:32.781498 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3145 11:04:32.787880 CH1_RK0: MR19=0x202, MR18=0xBFBF, DQSOSC=448, MR23=63, INC=12, DEC=18
3146 11:04:32.788273 Write Rank0 MR23 =0x3f
3147 11:04:32.788578 [DQSOSC]
3148 11:04:32.798014 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c0, (MSB)MR19= 0x202, tDQSOscB0 = 447 ps tDQSOscB1 = 447 ps
3149 11:04:32.801354 CH1 RK0: MR19=202, MR18=C0C0
3150 11:04:32.804600 [RankSwap] Rank num 2, (Multi 1), Rank 1
3151 11:04:32.804991 Write Rank0 MR2 =0xad
3152 11:04:32.807700 [Write Leveling]
3153 11:04:32.811172 delay byte0 byte1 byte2 byte3
3154 11:04:32.811573
3155 11:04:32.811879 10 0 0
3156 11:04:32.814570 11 0 0
3157 11:04:32.814962 12 0 0
3158 11:04:32.815268 13 0 0
3159 11:04:32.818190 14 0 0
3160 11:04:32.818587 15 0 0
3161 11:04:32.821649 16 0 0
3162 11:04:32.822041 17 0 0
3163 11:04:32.824320 18 0 0
3164 11:04:32.824714 19 0 0
3165 11:04:32.825022 20 0 0
3166 11:04:32.827746 21 0 0
3167 11:04:32.828298 22 0 0
3168 11:04:32.830695 23 0 0
3169 11:04:32.831087 24 0 0
3170 11:04:32.831394 25 0 0
3171 11:04:32.834174 26 0 0
3172 11:04:32.834580 27 0 0
3173 11:04:32.837681 28 0 0
3174 11:04:32.838074 29 0 0
3175 11:04:32.840982 30 0 0
3176 11:04:32.841432 31 0 0
3177 11:04:32.841742 32 0 ff
3178 11:04:32.843977 33 0 ff
3179 11:04:32.844370 34 0 ff
3180 11:04:32.847723 35 0 ff
3181 11:04:32.848118 36 ff ff
3182 11:04:32.850532 37 0 ff
3183 11:04:32.850923 38 0 ff
3184 11:04:32.853938 39 0 ff
3185 11:04:32.854403 40 ff ff
3186 11:04:32.854717 41 ff ff
3187 11:04:32.857213 42 ff ff
3188 11:04:32.857611 43 ff ff
3189 11:04:32.860636 44 ff ff
3190 11:04:32.861039 45 ff ff
3191 11:04:32.864084 46 ff ff
3192 11:04:32.867708 pass bytecount = 0xff (0xff: all bytes pass)
3193 11:04:32.868097
3194 11:04:32.868397 DQS0 dly: 40
3195 11:04:32.870772 DQS1 dly: 32
3196 11:04:32.871158 Write Rank0 MR2 =0x2d
3197 11:04:32.874670 [RankSwap] Rank num 2, (Multi 1), Rank 0
3198 11:04:32.877286 Write Rank1 MR1 =0xd6
3199 11:04:32.877674 [Gating]
3200 11:04:32.877976 ==
3201 11:04:32.884067 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3202 11:04:32.887905 fsp= 1, odt_onoff= 1, Byte mode= 0
3203 11:04:32.888298 ==
3204 11:04:32.890905 3 1 0 |3534 2d2c |(11 11)(11 11) |(0 0)(1 1)| 0
3205 11:04:32.897281 3 1 4 |3534 2d2c |(11 11)(11 11) |(1 1)(0 0)| 0
3206 11:04:32.900962 3 1 8 |3534 2d2c |(11 11)(11 11) |(1 1)(1 1)| 0
3207 11:04:32.903877 3 1 12 |3534 2727 |(11 11)(1 1) |(1 1)(1 0)| 0
3208 11:04:32.907453 3 1 16 |3534 2e2e |(11 11)(11 11) |(0 1)(1 0)| 0
3209 11:04:32.913897 3 1 20 |3534 2d2c |(11 11)(11 11) |(0 1)(1 1)| 0
3210 11:04:32.917209 3 1 24 |3534 2d2d |(11 11)(11 11) |(0 1)(0 1)| 0
3211 11:04:32.920626 3 1 28 |3534 1313 |(11 11)(11 11) |(0 1)(0 1)| 0
3212 11:04:32.927404 3 2 0 |3534 2c2c |(11 11)(0 0) |(0 1)(1 0)| 0
3213 11:04:32.930269 3 2 4 |3534 2c2c |(11 11)(0 0) |(0 1)(1 0)| 0
3214 11:04:32.934310 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3215 11:04:32.937205 3 2 12 |201 2626 |(11 11)(11 11) |(1 1)(1 0)| 0
3216 11:04:32.943780 3 2 16 |3d3d 2d2c |(11 11)(11 11) |(1 1)(0 0)| 0
3217 11:04:32.947027 3 2 20 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3218 11:04:32.950392 3 2 24 |3d3d 3433 |(11 11)(11 11) |(1 1)(0 0)| 0
3219 11:04:32.957060 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3220 11:04:32.960251 [Byte 1] Lead/lag Transition tap number (1)
3221 11:04:32.963855 3 3 0 |3d3d 3736 |(11 11)(11 11) |(1 1)(0 0)| 0
3222 11:04:32.966802 3 3 4 |3d3d 3535 |(11 11)(0 0) |(1 1)(0 0)| 0
3223 11:04:32.973528 3 3 8 |3d3d 3535 |(11 11)(10 10) |(1 1)(1 1)| 0
3224 11:04:32.977080 3 3 12 |3d3d 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
3225 11:04:32.979854 3 3 16 |202 2020 |(11 11)(11 11) |(1 1)(1 1)| 0
3226 11:04:32.987145 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3227 11:04:32.990297 [Byte 0] Lead/lag falling Transition (3, 3, 20)
3228 11:04:32.993577 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3229 11:04:32.999581 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3230 11:04:33.003057 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3231 11:04:33.006751 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3232 11:04:33.012944 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3233 11:04:33.016479 3 4 12 |707 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3234 11:04:33.019460 3 4 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3235 11:04:33.026510 3 4 20 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3236 11:04:33.029562 3 4 24 |3d3d 3d3d |(11 11)(10 10) |(1 1)(1 1)| 0
3237 11:04:33.033216 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3238 11:04:33.039772 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3239 11:04:33.042725 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3240 11:04:33.046022 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3241 11:04:33.050029 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3242 11:04:33.055903 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3243 11:04:33.059296 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3244 11:04:33.062777 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3245 11:04:33.069641 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3246 11:04:33.072575 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3247 11:04:33.075868 [Byte 0] Lead/lag falling Transition (3, 6, 0)
3248 11:04:33.082317 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3249 11:04:33.085568 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3250 11:04:33.089169 [Byte 0] Lead/lag Transition tap number (3)
3251 11:04:33.092285 [Byte 1] Lead/lag falling Transition (3, 6, 8)
3252 11:04:33.099061 3 6 12 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3253 11:04:33.102657 [Byte 1] Lead/lag Transition tap number (2)
3254 11:04:33.105626 3 6 16 |4646 3d3d |(0 0)(11 11) |(0 0)(0 0)| 0
3255 11:04:33.109151 [Byte 0]First pass (3, 6, 16)
3256 11:04:33.112412 3 6 20 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
3257 11:04:33.115801 3 6 24 |4646 2020 |(0 0)(1 1) |(0 0)(0 0)| 0
3258 11:04:33.122315 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3259 11:04:33.122734 [Byte 1]First pass (3, 6, 28)
3260 11:04:33.128908 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3261 11:04:33.132537 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3262 11:04:33.135997 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3263 11:04:33.139171 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3264 11:04:33.142514 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3265 11:04:33.148857 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3266 11:04:33.152228 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3267 11:04:33.155501 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3268 11:04:33.158658 All bytes gating window > 1UI, Early break!
3269 11:04:33.159035
3270 11:04:33.162155 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
3271 11:04:33.162677
3272 11:04:33.168704 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 12)
3273 11:04:33.169099
3274 11:04:33.169446
3275 11:04:33.169724
3276 11:04:33.172439 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
3277 11:04:33.172836
3278 11:04:33.175763 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3279 11:04:33.176171
3280 11:04:33.176469
3281 11:04:33.179074 Write Rank1 MR1 =0x56
3282 11:04:33.179457
3283 11:04:33.182269 best RODT dly(2T, 0.5T) = (2, 3)
3284 11:04:33.182679
3285 11:04:33.185487 best RODT dly(2T, 0.5T) = (2, 3)
3286 11:04:33.185906 ==
3287 11:04:33.189001 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3288 11:04:33.192422 fsp= 1, odt_onoff= 1, Byte mode= 0
3289 11:04:33.192805 ==
3290 11:04:33.195715 Start DQ dly to find pass range UseTestEngine =0
3291 11:04:33.202116 x-axis: bit #, y-axis: DQ dly (-127~63)
3292 11:04:33.202502 RX Vref Scan = 0
3293 11:04:33.205914 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3294 11:04:33.209391 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3295 11:04:33.212800 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3296 11:04:33.215631 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3297 11:04:33.216099 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3298 11:04:33.218780 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3299 11:04:33.222316 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3300 11:04:33.225536 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3301 11:04:33.228750 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3302 11:04:33.232422 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3303 11:04:33.235645 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3304 11:04:33.238753 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3305 11:04:33.239323 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3306 11:04:33.242189 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3307 11:04:33.245715 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3308 11:04:33.248853 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3309 11:04:33.252345 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3310 11:04:33.255794 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3311 11:04:33.259205 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3312 11:04:33.262518 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3313 11:04:33.262945 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3314 11:04:33.265246 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3315 11:04:33.269187 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3316 11:04:33.272326 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3317 11:04:33.275640 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3318 11:04:33.278794 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3319 11:04:33.279223 0, [0] xxxxxxxx xxxxxxxx [MSB]
3320 11:04:33.282283 1, [0] xxxxxxxx xoxxxxxo [MSB]
3321 11:04:33.285853 2, [0] xxxoxxxx ooxxxxxo [MSB]
3322 11:04:33.289040 3, [0] xxxoxxxx ooxxxxxo [MSB]
3323 11:04:33.292325 4, [0] xxooxxxx ooxxxxxo [MSB]
3324 11:04:33.295147 5, [0] xxooxxxx oooxxxxo [MSB]
3325 11:04:33.295571 6, [0] xooooxxo oooooooo [MSB]
3326 11:04:33.298478 7, [0] xooooxxo oooooooo [MSB]
3327 11:04:33.302418 8, [0] oooooxxo oooooooo [MSB]
3328 11:04:33.305071 31, [0] oooooooo ooooooox [MSB]
3329 11:04:33.308456 32, [0] oooooooo ooooooox [MSB]
3330 11:04:33.312317 33, [0] oooooooo ooooooox [MSB]
3331 11:04:33.315062 34, [0] oooooooo oxooooox [MSB]
3332 11:04:33.315450 35, [0] oooooooo xxooooox [MSB]
3333 11:04:33.318581 36, [0] ooxxoooo xxooooox [MSB]
3334 11:04:33.322254 37, [0] ooxxoooo xxooooox [MSB]
3335 11:04:33.325430 38, [0] ooxxoooo xxxoooox [MSB]
3336 11:04:33.328808 39, [0] ooxxxoox xxxxxxxx [MSB]
3337 11:04:33.331803 40, [0] oxxxxoox xxxxxxxx [MSB]
3338 11:04:33.335679 41, [0] xxxxxxox xxxxxxxx [MSB]
3339 11:04:33.336108 42, [0] xxxxxxxx xxxxxxxx [MSB]
3340 11:04:33.342086 iDelay=42, Bit 0, Center 24 (8 ~ 40) 33
3341 11:04:33.345509 iDelay=42, Bit 1, Center 22 (6 ~ 39) 34
3342 11:04:33.348567 iDelay=42, Bit 2, Center 19 (4 ~ 35) 32
3343 11:04:33.352151 iDelay=42, Bit 3, Center 18 (2 ~ 35) 34
3344 11:04:33.354957 iDelay=42, Bit 4, Center 22 (6 ~ 38) 33
3345 11:04:33.358728 iDelay=42, Bit 5, Center 24 (9 ~ 40) 32
3346 11:04:33.361605 iDelay=42, Bit 6, Center 25 (9 ~ 41) 33
3347 11:04:33.364938 iDelay=42, Bit 7, Center 22 (6 ~ 38) 33
3348 11:04:33.368378 iDelay=42, Bit 8, Center 18 (2 ~ 34) 33
3349 11:04:33.371467 iDelay=42, Bit 9, Center 17 (1 ~ 33) 33
3350 11:04:33.375256 iDelay=42, Bit 10, Center 21 (5 ~ 37) 33
3351 11:04:33.378558 iDelay=42, Bit 11, Center 22 (6 ~ 38) 33
3352 11:04:33.381795 iDelay=42, Bit 12, Center 22 (6 ~ 38) 33
3353 11:04:33.384807 iDelay=42, Bit 13, Center 22 (6 ~ 38) 33
3354 11:04:33.391729 iDelay=42, Bit 14, Center 22 (6 ~ 38) 33
3355 11:04:33.395315 iDelay=42, Bit 15, Center 15 (1 ~ 30) 30
3356 11:04:33.395735 ==
3357 11:04:33.398162 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3358 11:04:33.401833 fsp= 1, odt_onoff= 1, Byte mode= 0
3359 11:04:33.402253 ==
3360 11:04:33.405034 DQS Delay:
3361 11:04:33.405492 DQS0 = 0, DQS1 = 0
3362 11:04:33.405897 DQM Delay:
3363 11:04:33.408364 DQM0 = 22, DQM1 = 19
3364 11:04:33.408746 DQ Delay:
3365 11:04:33.411666 DQ0 =24, DQ1 =22, DQ2 =19, DQ3 =18
3366 11:04:33.414899 DQ4 =22, DQ5 =24, DQ6 =25, DQ7 =22
3367 11:04:33.418344 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
3368 11:04:33.421485 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =15
3369 11:04:33.422082
3370 11:04:33.422555
3371 11:04:33.425486 DramC Write-DBI off
3372 11:04:33.425900 ==
3373 11:04:33.428428 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3374 11:04:33.432150 fsp= 1, odt_onoff= 1, Byte mode= 0
3375 11:04:33.432534 ==
3376 11:04:33.438266 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3377 11:04:33.438650
3378 11:04:33.441682 Begin, DQ Scan Range 928~1184
3379 11:04:33.442062
3380 11:04:33.442395
3381 11:04:33.442667 TX Vref Scan disable
3382 11:04:33.445319 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3383 11:04:33.448243 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3384 11:04:33.451750 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3385 11:04:33.454680 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3386 11:04:33.458369 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3387 11:04:33.465311 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3388 11:04:33.468230 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3389 11:04:33.471862 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3390 11:04:33.474950 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3391 11:04:33.478226 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3392 11:04:33.481934 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3393 11:04:33.484972 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3394 11:04:33.487919 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3395 11:04:33.491644 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3396 11:04:33.495219 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3397 11:04:33.498426 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3398 11:04:33.501444 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3399 11:04:33.504393 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3400 11:04:33.508360 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3401 11:04:33.511636 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3402 11:04:33.514919 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3403 11:04:33.521482 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3404 11:04:33.524791 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3405 11:04:33.528023 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3406 11:04:33.531257 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3407 11:04:33.534822 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3408 11:04:33.538951 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3409 11:04:33.541749 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3410 11:04:33.544640 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3411 11:04:33.547709 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3412 11:04:33.551309 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3413 11:04:33.554276 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3414 11:04:33.558061 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3415 11:04:33.561189 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3416 11:04:33.564630 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3417 11:04:33.567918 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3418 11:04:33.571091 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3419 11:04:33.574669 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3420 11:04:33.580976 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3421 11:04:33.584099 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3422 11:04:33.587831 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3423 11:04:33.591249 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3424 11:04:33.594268 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3425 11:04:33.597524 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3426 11:04:33.601294 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3427 11:04:33.604265 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3428 11:04:33.607980 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3429 11:04:33.610699 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
3430 11:04:33.614199 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
3431 11:04:33.617953 977 |3 6 17|[0] xxxxxxxx ooxxxxxo [MSB]
3432 11:04:33.620672 978 |3 6 18|[0] xxxxxxxx ooxxxxxo [MSB]
3433 11:04:33.624045 979 |3 6 19|[0] xxxxxxxx oooxxxxo [MSB]
3434 11:04:33.627719 980 |3 6 20|[0] xxxxxxxx ooooxxoo [MSB]
3435 11:04:33.631579 981 |3 6 21|[0] xxxxxxxx oooooxoo [MSB]
3436 11:04:33.634308 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3437 11:04:33.637244 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
3438 11:04:33.644319 984 |3 6 24|[0] xxxxxxxx oooooooo [MSB]
3439 11:04:33.647540 985 |3 6 25|[0] xxoooxoo oooooooo [MSB]
3440 11:04:33.650583 986 |3 6 26|[0] xooooooo oooooooo [MSB]
3441 11:04:33.654398 994 |3 6 34|[0] oooooooo ooooooox [MSB]
3442 11:04:33.657401 995 |3 6 35|[0] oooooooo oxooooox [MSB]
3443 11:04:33.661278 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3444 11:04:33.663892 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3445 11:04:33.667191 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3446 11:04:33.670834 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3447 11:04:33.677262 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
3448 11:04:33.680269 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
3449 11:04:33.684307 1002 |3 6 42|[0] oooooooo xxxxxxxx [MSB]
3450 11:04:33.687441 1003 |3 6 43|[0] oooooooo xxxxxxxx [MSB]
3451 11:04:33.690460 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
3452 11:04:33.694192 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB]
3453 11:04:33.697698 1006 |3 6 46|[0] oooxoooo xxxxxxxx [MSB]
3454 11:04:33.700592 1007 |3 6 47|[0] oxxxooox xxxxxxxx [MSB]
3455 11:04:33.704024 1008 |3 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3456 11:04:33.707242 Byte0, DQ PI dly=995, DQM PI dly= 995
3457 11:04:33.713721 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 35)
3458 11:04:33.714230
3459 11:04:33.717183 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 35)
3460 11:04:33.717629
3461 11:04:33.720658 Byte1, DQ PI dly=986, DQM PI dly= 986
3462 11:04:33.723640 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3463 11:04:33.724089
3464 11:04:33.730170 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3465 11:04:33.730603
3466 11:04:33.730904 ==
3467 11:04:33.734029 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3468 11:04:33.737027 fsp= 1, odt_onoff= 1, Byte mode= 0
3469 11:04:33.737465 ==
3470 11:04:33.743765 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3471 11:04:33.744313
3472 11:04:33.744896 Begin, DQ Scan Range 962~1026
3473 11:04:33.747023 Write Rank1 MR14 =0x0
3474 11:04:33.755332
3475 11:04:33.755725 CH=1, VrefRange= 0, VrefLevel = 0
3476 11:04:33.762199 TX Bit0 (990~1002) 13 996, Bit8 (980~991) 12 985,
3477 11:04:33.765082 TX Bit1 (988~1001) 14 994, Bit9 (980~990) 11 985,
3478 11:04:33.772390 TX Bit2 (986~1000) 15 993, Bit10 (983~993) 11 988,
3479 11:04:33.775864 TX Bit3 (984~997) 14 990, Bit11 (983~995) 13 989,
3480 11:04:33.778803 TX Bit4 (986~1003) 18 994, Bit12 (983~993) 11 988,
3481 11:04:33.785415 TX Bit5 (990~1001) 12 995, Bit13 (984~993) 10 988,
3482 11:04:33.788317 TX Bit6 (987~1001) 15 994, Bit14 (983~993) 11 988,
3483 11:04:33.795346 TX Bit7 (988~1002) 15 995, Bit15 (976~987) 12 981,
3484 11:04:33.795739
3485 11:04:33.796039 Write Rank1 MR14 =0x2
3486 11:04:33.804282
3487 11:04:33.804945 CH=1, VrefRange= 0, VrefLevel = 2
3488 11:04:33.811036 TX Bit0 (990~1003) 14 996, Bit8 (979~992) 14 985,
3489 11:04:33.814719 TX Bit1 (987~1002) 16 994, Bit9 (979~991) 13 985,
3490 11:04:33.821221 TX Bit2 (985~1001) 17 993, Bit10 (983~994) 12 988,
3491 11:04:33.824433 TX Bit3 (984~999) 16 991, Bit11 (983~996) 14 989,
3492 11:04:33.827426 TX Bit4 (986~1003) 18 994, Bit12 (983~994) 12 988,
3493 11:04:33.834319 TX Bit5 (989~1003) 15 996, Bit13 (984~994) 11 989,
3494 11:04:33.837590 TX Bit6 (987~1002) 16 994, Bit14 (982~995) 14 988,
3495 11:04:33.844312 TX Bit7 (987~1003) 17 995, Bit15 (975~988) 14 981,
3496 11:04:33.844704
3497 11:04:33.845006 Write Rank1 MR14 =0x4
3498 11:04:33.853914
3499 11:04:33.854298 CH=1, VrefRange= 0, VrefLevel = 4
3500 11:04:33.860819 TX Bit0 (989~1005) 17 997, Bit8 (979~992) 14 985,
3501 11:04:33.863747 TX Bit1 (987~1003) 17 995, Bit9 (979~991) 13 985,
3502 11:04:33.870979 TX Bit2 (985~1002) 18 993, Bit10 (982~994) 13 988,
3503 11:04:33.873876 TX Bit3 (983~999) 17 991, Bit11 (983~996) 14 989,
3504 11:04:33.877080 TX Bit4 (986~1004) 19 995, Bit12 (983~995) 13 989,
3505 11:04:33.884132 TX Bit5 (989~1003) 15 996, Bit13 (983~995) 13 989,
3506 11:04:33.886991 TX Bit6 (986~1003) 18 994, Bit14 (983~995) 13 989,
3507 11:04:33.893851 TX Bit7 (987~1003) 17 995, Bit15 (975~990) 16 982,
3508 11:04:33.894244
3509 11:04:33.894559 Write Rank1 MR14 =0x6
3510 11:04:33.903140
3511 11:04:33.903545 CH=1, VrefRange= 0, VrefLevel = 6
3512 11:04:33.909738 TX Bit0 (989~1005) 17 997, Bit8 (978~992) 15 985,
3513 11:04:33.913487 TX Bit1 (987~1004) 18 995, Bit9 (978~992) 15 985,
3514 11:04:33.920038 TX Bit2 (985~1002) 18 993, Bit10 (981~995) 15 988,
3515 11:04:33.923031 TX Bit3 (983~1000) 18 991, Bit11 (982~998) 17 990,
3516 11:04:33.926449 TX Bit4 (985~1005) 21 995, Bit12 (983~996) 14 989,
3517 11:04:33.933213 TX Bit5 (987~1004) 18 995, Bit13 (983~995) 13 989,
3518 11:04:33.936509 TX Bit6 (986~1004) 19 995, Bit14 (982~995) 14 988,
3519 11:04:33.942981 TX Bit7 (986~1004) 19 995, Bit15 (975~991) 17 983,
3520 11:04:33.943389
3521 11:04:33.943691 Write Rank1 MR14 =0x8
3522 11:04:33.952810
3523 11:04:33.953253 CH=1, VrefRange= 0, VrefLevel = 8
3524 11:04:33.959723 TX Bit0 (988~1006) 19 997, Bit8 (977~993) 17 985,
3525 11:04:33.962964 TX Bit1 (986~1004) 19 995, Bit9 (978~992) 15 985,
3526 11:04:33.969624 TX Bit2 (985~1003) 19 994, Bit10 (981~995) 15 988,
3527 11:04:33.972962 TX Bit3 (983~1000) 18 991, Bit11 (982~998) 17 990,
3528 11:04:33.975941 TX Bit4 (985~1006) 22 995, Bit12 (982~997) 16 989,
3529 11:04:33.983507 TX Bit5 (987~1005) 19 996, Bit13 (983~996) 14 989,
3530 11:04:33.986193 TX Bit6 (986~1005) 20 995, Bit14 (982~995) 14 988,
3531 11:04:33.992503 TX Bit7 (986~1005) 20 995, Bit15 (974~991) 18 982,
3532 11:04:33.992914
3533 11:04:33.993244 Write Rank1 MR14 =0xa
3534 11:04:34.002869
3535 11:04:34.005858 CH=1, VrefRange= 0, VrefLevel = 10
3536 11:04:34.009464 TX Bit0 (988~1006) 19 997, Bit8 (977~993) 17 985,
3537 11:04:34.012792 TX Bit1 (987~1006) 20 996, Bit9 (977~993) 17 985,
3538 11:04:34.019114 TX Bit2 (984~1004) 21 994, Bit10 (980~997) 18 988,
3539 11:04:34.022605 TX Bit3 (983~1001) 19 992, Bit11 (982~999) 18 990,
3540 11:04:34.025530 TX Bit4 (985~1006) 22 995, Bit12 (982~997) 16 989,
3541 11:04:34.032453 TX Bit5 (987~1006) 20 996, Bit13 (983~997) 15 990,
3542 11:04:34.036089 TX Bit6 (986~1006) 21 996, Bit14 (981~996) 16 988,
3543 11:04:34.042530 TX Bit7 (986~1006) 21 996, Bit15 (974~992) 19 983,
3544 11:04:34.042926
3545 11:04:34.043403 Write Rank1 MR14 =0xc
3546 11:04:34.052202
3547 11:04:34.055482 CH=1, VrefRange= 0, VrefLevel = 12
3548 11:04:34.059005 TX Bit0 (987~1007) 21 997, Bit8 (977~993) 17 985,
3549 11:04:34.062373 TX Bit1 (986~1006) 21 996, Bit9 (977~993) 17 985,
3550 11:04:34.068939 TX Bit2 (984~1005) 22 994, Bit10 (980~997) 18 988,
3551 11:04:34.072277 TX Bit3 (982~1002) 21 992, Bit11 (981~999) 19 990,
3552 11:04:34.075656 TX Bit4 (985~1006) 22 995, Bit12 (981~998) 18 989,
3553 11:04:34.082443 TX Bit5 (986~1006) 21 996, Bit13 (982~998) 17 990,
3554 11:04:34.085880 TX Bit6 (986~1006) 21 996, Bit14 (981~998) 18 989,
3555 11:04:34.091927 TX Bit7 (986~1006) 21 996, Bit15 (974~992) 19 983,
3556 11:04:34.092438
3557 11:04:34.092750 Write Rank1 MR14 =0xe
3558 11:04:34.102605
3559 11:04:34.103023 CH=1, VrefRange= 0, VrefLevel = 14
3560 11:04:34.109027 TX Bit0 (987~1007) 21 997, Bit8 (976~994) 19 985,
3561 11:04:34.112020 TX Bit1 (986~1006) 21 996, Bit9 (977~993) 17 985,
3562 11:04:34.119054 TX Bit2 (984~1005) 22 994, Bit10 (979~998) 20 988,
3563 11:04:34.122117 TX Bit3 (982~1002) 21 992, Bit11 (981~999) 19 990,
3564 11:04:34.125629 TX Bit4 (985~1007) 23 996, Bit12 (981~998) 18 989,
3565 11:04:34.132273 TX Bit5 (986~1007) 22 996, Bit13 (982~999) 18 990,
3566 11:04:34.135625 TX Bit6 (986~1006) 21 996, Bit14 (981~998) 18 989,
3567 11:04:34.141900 TX Bit7 (986~1006) 21 996, Bit15 (973~992) 20 982,
3568 11:04:34.142291
3569 11:04:34.142599 Write Rank1 MR14 =0x10
3570 11:04:34.151951
3571 11:04:34.155560 CH=1, VrefRange= 0, VrefLevel = 16
3572 11:04:34.158768 TX Bit0 (987~1007) 21 997, Bit8 (976~995) 20 985,
3573 11:04:34.162120 TX Bit1 (986~1007) 22 996, Bit9 (976~994) 19 985,
3574 11:04:34.168727 TX Bit2 (984~1006) 23 995, Bit10 (979~998) 20 988,
3575 11:04:34.171931 TX Bit3 (981~1003) 23 992, Bit11 (980~1000) 21 990,
3576 11:04:34.179107 TX Bit4 (985~1007) 23 996, Bit12 (980~999) 20 989,
3577 11:04:34.181809 TX Bit5 (986~1007) 22 996, Bit13 (982~999) 18 990,
3578 11:04:34.185340 TX Bit6 (985~1006) 22 995, Bit14 (980~999) 20 989,
3579 11:04:34.192327 TX Bit7 (985~1007) 23 996, Bit15 (972~993) 22 982,
3580 11:04:34.192764
3581 11:04:34.193148 Write Rank1 MR14 =0x12
3582 11:04:34.202488
3583 11:04:34.205576 CH=1, VrefRange= 0, VrefLevel = 18
3584 11:04:34.209072 TX Bit0 (987~1007) 21 997, Bit8 (976~996) 21 986,
3585 11:04:34.212538 TX Bit1 (985~1007) 23 996, Bit9 (976~994) 19 985,
3586 11:04:34.218654 TX Bit2 (984~1006) 23 995, Bit10 (978~999) 22 988,
3587 11:04:34.221998 TX Bit3 (981~1003) 23 992, Bit11 (979~1000) 22 989,
3588 11:04:34.229290 TX Bit4 (985~1007) 23 996, Bit12 (981~999) 19 990,
3589 11:04:34.231959 TX Bit5 (986~1007) 22 996, Bit13 (982~1000) 19 991,
3590 11:04:34.235263 TX Bit6 (986~1007) 22 996, Bit14 (979~999) 21 989,
3591 11:04:34.241915 TX Bit7 (985~1007) 23 996, Bit15 (972~993) 22 982,
3592 11:04:34.242301
3593 11:04:34.242600 Write Rank1 MR14 =0x14
3594 11:04:34.252391
3595 11:04:34.255946 CH=1, VrefRange= 0, VrefLevel = 20
3596 11:04:34.259287 TX Bit0 (986~1008) 23 997, Bit8 (975~996) 22 985,
3597 11:04:34.262723 TX Bit1 (985~1007) 23 996, Bit9 (976~995) 20 985,
3598 11:04:34.269286 TX Bit2 (983~1006) 24 994, Bit10 (978~999) 22 988,
3599 11:04:34.272870 TX Bit3 (981~1004) 24 992, Bit11 (979~1000) 22 989,
3600 11:04:34.275972 TX Bit4 (984~1007) 24 995, Bit12 (980~999) 20 989,
3601 11:04:34.282436 TX Bit5 (986~1007) 22 996, Bit13 (981~1000) 20 990,
3602 11:04:34.285895 TX Bit6 (985~1007) 23 996, Bit14 (979~999) 21 989,
3603 11:04:34.292366 TX Bit7 (985~1007) 23 996, Bit15 (972~994) 23 983,
3604 11:04:34.292777
3605 11:04:34.293196 Write Rank1 MR14 =0x16
3606 11:04:34.303056
3607 11:04:34.306588 CH=1, VrefRange= 0, VrefLevel = 22
3608 11:04:34.309727 TX Bit0 (986~1008) 23 997, Bit8 (975~997) 23 986,
3609 11:04:34.312721 TX Bit1 (985~1007) 23 996, Bit9 (976~995) 20 985,
3610 11:04:34.319622 TX Bit2 (983~1007) 25 995, Bit10 (978~999) 22 988,
3611 11:04:34.322930 TX Bit3 (980~1004) 25 992, Bit11 (979~1001) 23 990,
3612 11:04:34.326383 TX Bit4 (984~1008) 25 996, Bit12 (979~1000) 22 989,
3613 11:04:34.332668 TX Bit5 (985~1008) 24 996, Bit13 (981~1000) 20 990,
3614 11:04:34.336250 TX Bit6 (985~1007) 23 996, Bit14 (978~999) 22 988,
3615 11:04:34.342619 TX Bit7 (985~1007) 23 996, Bit15 (971~994) 24 982,
3616 11:04:34.343010
3617 11:04:34.343397 Write Rank1 MR14 =0x18
3618 11:04:34.353256
3619 11:04:34.356616 CH=1, VrefRange= 0, VrefLevel = 24
3620 11:04:34.359916 TX Bit0 (986~1008) 23 997, Bit8 (975~998) 24 986,
3621 11:04:34.363367 TX Bit1 (986~1008) 23 997, Bit9 (976~996) 21 986,
3622 11:04:34.370050 TX Bit2 (982~1007) 26 994, Bit10 (977~1000) 24 988,
3623 11:04:34.373945 TX Bit3 (980~1005) 26 992, Bit11 (978~1001) 24 989,
3624 11:04:34.379821 TX Bit4 (984~1008) 25 996, Bit12 (980~1000) 21 990,
3625 11:04:34.382818 TX Bit5 (985~1008) 24 996, Bit13 (980~1000) 21 990,
3626 11:04:34.386268 TX Bit6 (985~1007) 23 996, Bit14 (978~1000) 23 989,
3627 11:04:34.393043 TX Bit7 (985~1007) 23 996, Bit15 (971~995) 25 983,
3628 11:04:34.393465
3629 11:04:34.393763 Write Rank1 MR14 =0x1a
3630 11:04:34.403863
3631 11:04:34.407232 CH=1, VrefRange= 0, VrefLevel = 26
3632 11:04:34.410482 TX Bit0 (986~1008) 23 997, Bit8 (974~998) 25 986,
3633 11:04:34.413668 TX Bit1 (985~1008) 24 996, Bit9 (975~996) 22 985,
3634 11:04:34.420261 TX Bit2 (983~1007) 25 995, Bit10 (977~1000) 24 988,
3635 11:04:34.423762 TX Bit3 (979~1006) 28 992, Bit11 (978~1001) 24 989,
3636 11:04:34.430228 TX Bit4 (984~1008) 25 996, Bit12 (979~1000) 22 989,
3637 11:04:34.433533 TX Bit5 (985~1008) 24 996, Bit13 (979~1001) 23 990,
3638 11:04:34.437337 TX Bit6 (984~1008) 25 996, Bit14 (978~1000) 23 989,
3639 11:04:34.443438 TX Bit7 (985~1008) 24 996, Bit15 (970~995) 26 982,
3640 11:04:34.443904
3641 11:04:34.444215 Write Rank1 MR14 =0x1c
3642 11:04:34.454660
3643 11:04:34.457972 CH=1, VrefRange= 0, VrefLevel = 28
3644 11:04:34.461300 TX Bit0 (986~1009) 24 997, Bit8 (974~998) 25 986,
3645 11:04:34.464689 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3646 11:04:34.471518 TX Bit2 (982~1007) 26 994, Bit10 (977~1000) 24 988,
3647 11:04:34.474462 TX Bit3 (979~1006) 28 992, Bit11 (978~1001) 24 989,
3648 11:04:34.481416 TX Bit4 (985~1008) 24 996, Bit12 (978~1001) 24 989,
3649 11:04:34.484455 TX Bit5 (985~1008) 24 996, Bit13 (979~1001) 23 990,
3650 11:04:34.488263 TX Bit6 (984~1008) 25 996, Bit14 (977~1000) 24 988,
3651 11:04:34.494520 TX Bit7 (984~1008) 25 996, Bit15 (970~995) 26 982,
3652 11:04:34.494921
3653 11:04:34.495218 Write Rank1 MR14 =0x1e
3654 11:04:34.505583
3655 11:04:34.508465 CH=1, VrefRange= 0, VrefLevel = 30
3656 11:04:34.511562 TX Bit0 (986~1009) 24 997, Bit8 (974~998) 25 986,
3657 11:04:34.514994 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3658 11:04:34.521637 TX Bit2 (982~1007) 26 994, Bit10 (977~1000) 24 988,
3659 11:04:34.525248 TX Bit3 (979~1006) 28 992, Bit11 (978~1001) 24 989,
3660 11:04:34.531501 TX Bit4 (985~1008) 24 996, Bit12 (978~1001) 24 989,
3661 11:04:34.535130 TX Bit5 (984~1008) 25 996, Bit13 (979~1001) 23 990,
3662 11:04:34.538305 TX Bit6 (984~1008) 25 996, Bit14 (977~1000) 24 988,
3663 11:04:34.544707 TX Bit7 (984~1008) 25 996, Bit15 (970~995) 26 982,
3664 11:04:34.545142
3665 11:04:34.547974 Write Rank1 MR14 =0x20
3666 11:04:34.555881
3667 11:04:34.559106 CH=1, VrefRange= 0, VrefLevel = 32
3668 11:04:34.562778 TX Bit0 (986~1009) 24 997, Bit8 (974~998) 25 986,
3669 11:04:34.565607 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3670 11:04:34.572733 TX Bit2 (982~1007) 26 994, Bit10 (977~1000) 24 988,
3671 11:04:34.575578 TX Bit3 (979~1006) 28 992, Bit11 (978~1001) 24 989,
3672 11:04:34.582537 TX Bit4 (985~1008) 24 996, Bit12 (978~1001) 24 989,
3673 11:04:34.586011 TX Bit5 (984~1008) 25 996, Bit13 (979~1001) 23 990,
3674 11:04:34.588942 TX Bit6 (984~1008) 25 996, Bit14 (977~1000) 24 988,
3675 11:04:34.595795 TX Bit7 (984~1008) 25 996, Bit15 (970~995) 26 982,
3676 11:04:34.596199
3677 11:04:34.596520 Write Rank1 MR14 =0x22
3678 11:04:34.606765
3679 11:04:34.609984 CH=1, VrefRange= 0, VrefLevel = 34
3680 11:04:34.613285 TX Bit0 (986~1009) 24 997, Bit8 (974~998) 25 986,
3681 11:04:34.616506 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3682 11:04:34.623270 TX Bit2 (982~1007) 26 994, Bit10 (977~1000) 24 988,
3683 11:04:34.626593 TX Bit3 (979~1006) 28 992, Bit11 (978~1001) 24 989,
3684 11:04:34.629977 TX Bit4 (985~1008) 24 996, Bit12 (978~1001) 24 989,
3685 11:04:34.636896 TX Bit5 (984~1008) 25 996, Bit13 (979~1001) 23 990,
3686 11:04:34.640616 TX Bit6 (984~1008) 25 996, Bit14 (977~1000) 24 988,
3687 11:04:34.646925 TX Bit7 (984~1008) 25 996, Bit15 (970~995) 26 982,
3688 11:04:34.647310
3689 11:04:34.647607 Write Rank1 MR14 =0x24
3690 11:04:34.657325
3691 11:04:34.660443 CH=1, VrefRange= 0, VrefLevel = 36
3692 11:04:34.663993 TX Bit0 (986~1009) 24 997, Bit8 (974~998) 25 986,
3693 11:04:34.667334 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3694 11:04:34.673888 TX Bit2 (982~1007) 26 994, Bit10 (977~1000) 24 988,
3695 11:04:34.677583 TX Bit3 (979~1006) 28 992, Bit11 (978~1001) 24 989,
3696 11:04:34.683987 TX Bit4 (985~1008) 24 996, Bit12 (978~1001) 24 989,
3697 11:04:34.687098 TX Bit5 (984~1008) 25 996, Bit13 (979~1001) 23 990,
3698 11:04:34.690781 TX Bit6 (984~1008) 25 996, Bit14 (977~1000) 24 988,
3699 11:04:34.697970 TX Bit7 (984~1008) 25 996, Bit15 (970~995) 26 982,
3700 11:04:34.698358
3701 11:04:34.698659 Write Rank1 MR14 =0x26
3702 11:04:34.708591
3703 11:04:34.711418 CH=1, VrefRange= 0, VrefLevel = 38
3704 11:04:34.714750 TX Bit0 (986~1009) 24 997, Bit8 (974~998) 25 986,
3705 11:04:34.718171 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3706 11:04:34.724845 TX Bit2 (982~1007) 26 994, Bit10 (977~1000) 24 988,
3707 11:04:34.728710 TX Bit3 (979~1006) 28 992, Bit11 (978~1001) 24 989,
3708 11:04:34.734552 TX Bit4 (985~1008) 24 996, Bit12 (978~1001) 24 989,
3709 11:04:34.737783 TX Bit5 (984~1008) 25 996, Bit13 (979~1001) 23 990,
3710 11:04:34.741609 TX Bit6 (984~1008) 25 996, Bit14 (977~1000) 24 988,
3711 11:04:34.748043 TX Bit7 (984~1008) 25 996, Bit15 (970~995) 26 982,
3712 11:04:34.748433
3713 11:04:34.748736
3714 11:04:34.751352 TX Vref found, early break! 373< 377
3715 11:04:34.754780 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =833/100 ps
3716 11:04:34.757552 u1DelayCellOfst[0]=5 cells (5 PI)
3717 11:04:34.761009 u1DelayCellOfst[1]=4 cells (4 PI)
3718 11:04:34.764572 u1DelayCellOfst[2]=2 cells (2 PI)
3719 11:04:34.767537 u1DelayCellOfst[3]=0 cells (0 PI)
3720 11:04:34.771334 u1DelayCellOfst[4]=4 cells (4 PI)
3721 11:04:34.775075 u1DelayCellOfst[5]=4 cells (4 PI)
3722 11:04:34.777835 u1DelayCellOfst[6]=4 cells (4 PI)
3723 11:04:34.781205 u1DelayCellOfst[7]=4 cells (4 PI)
3724 11:04:34.784336 Byte0, DQ PI dly=992, DQM PI dly= 994
3725 11:04:34.787524 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32)
3726 11:04:34.787914
3727 11:04:34.791104 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32)
3728 11:04:34.791495
3729 11:04:34.794328 u1DelayCellOfst[8]=4 cells (4 PI)
3730 11:04:34.797852 u1DelayCellOfst[9]=4 cells (4 PI)
3731 11:04:34.801062 u1DelayCellOfst[10]=7 cells (6 PI)
3732 11:04:34.804549 u1DelayCellOfst[11]=8 cells (7 PI)
3733 11:04:34.807732 u1DelayCellOfst[12]=8 cells (7 PI)
3734 11:04:34.811227 u1DelayCellOfst[13]=9 cells (8 PI)
3735 11:04:34.814256 u1DelayCellOfst[14]=7 cells (6 PI)
3736 11:04:34.817397 u1DelayCellOfst[15]=0 cells (0 PI)
3737 11:04:34.821069 Byte1, DQ PI dly=982, DQM PI dly= 986
3738 11:04:34.824135 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
3739 11:04:34.824537
3740 11:04:34.827797 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
3741 11:04:34.828400
3742 11:04:34.830743 Write Rank1 MR14 =0x1e
3743 11:04:34.831252
3744 11:04:34.833943 Final TX Range 0 Vref 30
3745 11:04:34.834462
3746 11:04:34.840878 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3747 11:04:34.841406
3748 11:04:34.847377 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3749 11:04:34.853945 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3750 11:04:34.860608 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3751 11:04:34.863899 Write Rank1 MR3 =0xb0
3752 11:04:34.864284 DramC Write-DBI on
3753 11:04:34.864584 ==
3754 11:04:34.870845 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3755 11:04:34.873907 fsp= 1, odt_onoff= 1, Byte mode= 0
3756 11:04:34.874292 ==
3757 11:04:34.877536 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3758 11:04:34.878000
3759 11:04:34.881377 Begin, DQ Scan Range 706~770
3760 11:04:34.881771
3761 11:04:34.882072
3762 11:04:34.882348 TX Vref Scan disable
3763 11:04:34.887402 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3764 11:04:34.890909 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3765 11:04:34.894329 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3766 11:04:34.897335 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3767 11:04:34.901422 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3768 11:04:34.903666 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3769 11:04:34.907057 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3770 11:04:34.910440 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3771 11:04:34.914520 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3772 11:04:34.917891 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3773 11:04:34.920807 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3774 11:04:34.923803 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3775 11:04:34.927518 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3776 11:04:34.930852 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3777 11:04:34.934388 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3778 11:04:34.938355 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3779 11:04:34.940859 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3780 11:04:34.943960 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3781 11:04:34.947314 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3782 11:04:34.954292 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3783 11:04:34.957013 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3784 11:04:34.960388 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3785 11:04:34.963878 728 |2 6 24|[0] xxxxxxxx oooooooo [MSB]
3786 11:04:34.970181 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3787 11:04:34.973565 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3788 11:04:34.976984 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3789 11:04:34.980161 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3790 11:04:34.983637 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3791 11:04:34.987285 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3792 11:04:34.990421 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3793 11:04:34.993279 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3794 11:04:34.996565 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3795 11:04:35.000044 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
3796 11:04:35.003588 754 |2 6 50|[0] oooooooo xxxxxxxx [MSB]
3797 11:04:35.006811 755 |2 6 51|[0] xxxxxxxx xxxxxxxx [MSB]
3798 11:04:35.009906 Byte0, DQ PI dly=741, DQM PI dly= 741
3799 11:04:35.016490 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 37)
3800 11:04:35.016882
3801 11:04:35.019725 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 37)
3802 11:04:35.020114
3803 11:04:35.023342 Byte1, DQ PI dly=730, DQM PI dly= 730
3804 11:04:35.026654 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3805 11:04:35.027046
3806 11:04:35.033620 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3807 11:04:35.034009
3808 11:04:35.040871 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3809 11:04:35.046462 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3810 11:04:35.053267 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3811 11:04:35.053662 Write Rank1 MR3 =0x30
3812 11:04:35.056580 DramC Write-DBI off
3813 11:04:35.056961
3814 11:04:35.057289 [DATLAT]
3815 11:04:35.059678 Freq=1600, CH1 RK1, use_rxtx_scan=0
3816 11:04:35.060066
3817 11:04:35.063249 DATLAT Default: 0x10
3818 11:04:35.063637 7, 0xFFFF, sum=0
3819 11:04:35.066937 8, 0xFFFF, sum=0
3820 11:04:35.067345 9, 0xFFFF, sum=0
3821 11:04:35.069938 10, 0xFFFF, sum=0
3822 11:04:35.070330 11, 0xFFFF, sum=0
3823 11:04:35.073237 12, 0xFFFF, sum=0
3824 11:04:35.073637 13, 0xFFFF, sum=0
3825 11:04:35.076397 14, 0x0, sum=1
3826 11:04:35.076790 15, 0x0, sum=2
3827 11:04:35.079819 16, 0x0, sum=3
3828 11:04:35.080213 17, 0x0, sum=4
3829 11:04:35.083272 pattern=2 first_step=14 total pass=5 best_step=16
3830 11:04:35.083660 ==
3831 11:04:35.090286 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3832 11:04:35.093592 fsp= 1, odt_onoff= 1, Byte mode= 0
3833 11:04:35.094062 ==
3834 11:04:35.096654 Start DQ dly to find pass range UseTestEngine =1
3835 11:04:35.100109 x-axis: bit #, y-axis: DQ dly (-127~63)
3836 11:04:35.103307 RX Vref Scan = 0
3837 11:04:35.106660 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3838 11:04:35.107055 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3839 11:04:35.109976 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3840 11:04:35.113253 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3841 11:04:35.116725 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3842 11:04:35.120306 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3843 11:04:35.123279 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3844 11:04:35.126358 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3845 11:04:35.130032 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3846 11:04:35.130431 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3847 11:04:35.133611 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3848 11:04:35.136607 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3849 11:04:35.139859 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3850 11:04:35.143409 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3851 11:04:35.146546 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3852 11:04:35.149940 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3853 11:04:35.153255 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3854 11:04:35.153656 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3855 11:04:35.156792 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3856 11:04:35.160187 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3857 11:04:35.163138 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3858 11:04:35.166608 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3859 11:04:35.170298 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3860 11:04:35.173648 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3861 11:04:35.174041 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3862 11:04:35.176691 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3863 11:04:35.179687 0, [0] xxxxxxxx xxxxxxxx [MSB]
3864 11:04:35.183224 1, [0] xxxxxxxx xxxxxxxo [MSB]
3865 11:04:35.186984 2, [0] xxxxxxxx xoxxxxxo [MSB]
3866 11:04:35.189544 3, [0] xxxoxxxx ooxxxxxo [MSB]
3867 11:04:35.190039 4, [0] xxooxxxx ooxxxxxo [MSB]
3868 11:04:35.194192 5, [0] xxoooxxx ooxxxxxo [MSB]
3869 11:04:35.196588 6, [0] xxoooxxx oooxxxxo [MSB]
3870 11:04:35.199832 7, [0] oooooxxx oooooooo [MSB]
3871 11:04:35.203159 8, [0] ooooooxo oooooooo [MSB]
3872 11:04:35.206430 30, [0] oooooooo ooooooox [MSB]
3873 11:04:35.210036 31, [0] oooooooo ooooooox [MSB]
3874 11:04:35.212888 32, [0] oooooooo ooooooox [MSB]
3875 11:04:35.216772 33, [0] oooooooo oxooooox [MSB]
3876 11:04:35.219618 34, [0] oooxoooo xxooooox [MSB]
3877 11:04:35.220011 35, [0] oooxoooo xxooooox [MSB]
3878 11:04:35.223290 36, [0] ooxxoooo xxooooox [MSB]
3879 11:04:35.226741 37, [0] ooxxooox xxooxoxx [MSB]
3880 11:04:35.230005 38, [0] oxxxxoox xxxxxxxx [MSB]
3881 11:04:35.233355 39, [0] xxxxxoox xxxxxxxx [MSB]
3882 11:04:35.236435 40, [0] xxxxxxox xxxxxxxx [MSB]
3883 11:04:35.236832 41, [0] xxxxxxxx xxxxxxxx [MSB]
3884 11:04:35.243211 iDelay=41, Bit 0, Center 22 (7 ~ 38) 32
3885 11:04:35.246472 iDelay=41, Bit 1, Center 22 (7 ~ 37) 31
3886 11:04:35.249699 iDelay=41, Bit 2, Center 19 (4 ~ 35) 32
3887 11:04:35.253226 iDelay=41, Bit 3, Center 18 (3 ~ 33) 31
3888 11:04:35.256782 iDelay=41, Bit 4, Center 21 (5 ~ 37) 33
3889 11:04:35.259744 iDelay=41, Bit 5, Center 23 (8 ~ 39) 32
3890 11:04:35.263082 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32
3891 11:04:35.266460 iDelay=41, Bit 7, Center 22 (8 ~ 36) 29
3892 11:04:35.269572 iDelay=41, Bit 8, Center 18 (3 ~ 33) 31
3893 11:04:35.273415 iDelay=41, Bit 9, Center 17 (2 ~ 32) 31
3894 11:04:35.276677 iDelay=41, Bit 10, Center 21 (6 ~ 37) 32
3895 11:04:35.279692 iDelay=41, Bit 11, Center 22 (7 ~ 37) 31
3896 11:04:35.283648 iDelay=41, Bit 12, Center 21 (7 ~ 36) 30
3897 11:04:35.286703 iDelay=41, Bit 13, Center 22 (7 ~ 37) 31
3898 11:04:35.293792 iDelay=41, Bit 14, Center 21 (7 ~ 36) 30
3899 11:04:35.296144 iDelay=41, Bit 15, Center 15 (1 ~ 29) 29
3900 11:04:35.296655 ==
3901 11:04:35.299945 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3902 11:04:35.302977 fsp= 1, odt_onoff= 1, Byte mode= 0
3903 11:04:35.303481 ==
3904 11:04:35.305963 DQS Delay:
3905 11:04:35.306458 DQS0 = 0, DQS1 = 0
3906 11:04:35.306917 DQM Delay:
3907 11:04:35.309815 DQM0 = 21, DQM1 = 19
3908 11:04:35.310304 DQ Delay:
3909 11:04:35.312865 DQ0 =22, DQ1 =22, DQ2 =19, DQ3 =18
3910 11:04:35.316450 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
3911 11:04:35.319590 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
3912 11:04:35.322892 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =15
3913 11:04:35.323275
3914 11:04:35.323572
3915 11:04:35.323841
3916 11:04:35.326265 [DramC_TX_OE_Calibration] TA2
3917 11:04:35.329474 Original DQ_B0 (3 6) =30, OEN = 27
3918 11:04:35.333088 Original DQ_B1 (3 6) =30, OEN = 27
3919 11:04:35.336334 23, 0x0, End_B0=23 End_B1=23
3920 11:04:35.339578 24, 0x0, End_B0=24 End_B1=24
3921 11:04:35.339975 25, 0x0, End_B0=25 End_B1=25
3922 11:04:35.343155 26, 0x0, End_B0=26 End_B1=26
3923 11:04:35.346505 27, 0x0, End_B0=27 End_B1=27
3924 11:04:35.349474 28, 0x0, End_B0=28 End_B1=28
3925 11:04:35.349871 29, 0x0, End_B0=29 End_B1=29
3926 11:04:35.353484 30, 0x0, End_B0=30 End_B1=30
3927 11:04:35.356589 31, 0xFFFF, End_B0=30 End_B1=30
3928 11:04:35.363538 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3929 11:04:35.366304 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3930 11:04:35.366693
3931 11:04:35.366992
3932 11:04:35.370036 Write Rank1 MR23 =0x3f
3933 11:04:35.370421 [DQSOSC]
3934 11:04:35.379840 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
3935 11:04:35.386616 CH1_RK1: MR19=0x202, MR18=0xD8D8, DQSOSC=432, MR23=63, INC=13, DEC=19
3936 11:04:35.387005 Write Rank1 MR23 =0x3f
3937 11:04:35.387359 [DQSOSC]
3938 11:04:35.396685 [DQSOSCAuto] RK1, (LSB)MR18= 0xd5d5, (MSB)MR19= 0x202, tDQSOscB0 = 434 ps tDQSOscB1 = 434 ps
3939 11:04:35.399643 CH1 RK1: MR19=202, MR18=D5D5
3940 11:04:35.402870 [RxdqsGatingPostProcess] freq 1600
3941 11:04:35.406237 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3942 11:04:35.409732 Rank: 0
3943 11:04:35.410149 best DQS0 dly(2T, 0.5T) = (2, 6)
3944 11:04:35.412823 best DQS1 dly(2T, 0.5T) = (2, 6)
3945 11:04:35.416528 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3946 11:04:35.419422 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3947 11:04:35.419808 Rank: 1
3948 11:04:35.422675 best DQS0 dly(2T, 0.5T) = (2, 6)
3949 11:04:35.426370 best DQS1 dly(2T, 0.5T) = (2, 6)
3950 11:04:35.429091 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3951 11:04:35.433208 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3952 11:04:35.439344 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3953 11:04:35.442574 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3954 11:04:35.445924 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3955 11:04:35.446310
3956 11:04:35.446606
3957 11:04:35.449089 [Calibration Summary] Freqency 1600
3958 11:04:35.449531 CH 0, Rank 0
3959 11:04:35.452335 All Pass.
3960 11:04:35.452715
3961 11:04:35.453221 CH 0, Rank 1
3962 11:04:35.453591 All Pass.
3963 11:04:35.456037
3964 11:04:35.456419 CH 1, Rank 0
3965 11:04:35.456722 All Pass.
3966 11:04:35.456996
3967 11:04:35.459038 CH 1, Rank 1
3968 11:04:35.459423 All Pass.
3969 11:04:35.459720
3970 11:04:35.465709 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3971 11:04:35.472294 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3972 11:04:35.479048 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3973 11:04:35.482460 Write Rank0 MR3 =0xb0
3974 11:04:35.488970 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3975 11:04:35.495392 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3976 11:04:35.502590 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3977 11:04:35.505985 Write Rank1 MR3 =0xb0
3978 11:04:35.511808 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3979 11:04:35.518871 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3980 11:04:35.525440 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3981 11:04:35.525830 Write Rank0 MR3 =0xb0
3982 11:04:35.532953 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3983 11:04:35.538543 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3984 11:04:35.548341 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3985 11:04:35.548731 Write Rank1 MR3 =0xb0
3986 11:04:35.552169 DramC Write-DBI on
3987 11:04:35.555015 [GetDramInforAfterCalByMRR] Vendor 6.
3988 11:04:35.558203 [GetDramInforAfterCalByMRR] Revision 505.
3989 11:04:35.558585 MR8 1111
3990 11:04:35.564973 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3991 11:04:35.565388 MR8 1111
3992 11:04:35.568210 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3993 11:04:35.568605 MR8 1111
3994 11:04:35.574763 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3995 11:04:35.575309 MR8 1111
3996 11:04:35.581445 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3997 11:04:35.588683 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3998 11:04:35.591438 Write Rank0 MR13 =0xd0
3999 11:04:35.594788 Write Rank1 MR13 =0xd0
4000 11:04:35.595315 Write Rank0 MR13 =0xd0
4001 11:04:35.597902 Write Rank1 MR13 =0xd0
4002 11:04:35.601073 Save calibration result to emmc
4003 11:04:35.601616
4004 11:04:35.602101
4005 11:04:35.604396 [DramcModeReg_Check] Freq_1600, FSP_1
4006 11:04:35.604887 FSP_1, CH_0, RK0
4007 11:04:35.608093 Write Rank0 MR13 =0xd8
4008 11:04:35.611414 MR12 = 0x60 (global = 0x60) match
4009 11:04:35.614773 MR14 = 0x20 (global = 0x20) match
4010 11:04:35.615173 FSP_1, CH_0, RK1
4011 11:04:35.618001 Write Rank1 MR13 =0xd8
4012 11:04:35.621165 MR12 = 0x5e (global = 0x5e) match
4013 11:04:35.624751 MR14 = 0x20 (global = 0x20) match
4014 11:04:35.625196 FSP_1, CH_1, RK0
4015 11:04:35.628186 Write Rank0 MR13 =0xd8
4016 11:04:35.631061 MR12 = 0x60 (global = 0x60) match
4017 11:04:35.634745 MR14 = 0x1e (global = 0x1e) match
4018 11:04:35.635135 FSP_1, CH_1, RK1
4019 11:04:35.637374 Write Rank1 MR13 =0xd8
4020 11:04:35.641151 MR12 = 0x5e (global = 0x5e) match
4021 11:04:35.644616 MR14 = 0x1e (global = 0x1e) match
4022 11:04:35.644999
4023 11:04:35.647667 [MEM_TEST] 02: After DFS, before run time config
4024 11:04:35.659286 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4025 11:04:35.659742
4026 11:04:35.660047 [TA2_TEST]
4027 11:04:35.660418 === TA2 HW
4028 11:04:35.662979 TA2 PAT: XTALK
4029 11:04:35.666423 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
4030 11:04:35.672589 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
4031 11:04:35.676209 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
4032 11:04:35.679248 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
4033 11:04:35.682842
4034 11:04:35.683376
4035 11:04:35.683833 Settings after calibration
4036 11:04:35.684291
4037 11:04:35.686307 [DramcRunTimeConfig]
4038 11:04:35.689304 TransferPLLToSPMControl - MODE SW PHYPLL
4039 11:04:35.689812 TX_TRACKING: ON
4040 11:04:35.692890 RX_TRACKING: ON
4041 11:04:35.693332 HW_GATING: ON
4042 11:04:35.696407 HW_GATING DBG: OFF
4043 11:04:35.696966 ddr_geometry:1
4044 11:04:35.699666 ddr_geometry:1
4045 11:04:35.700169 ddr_geometry:1
4046 11:04:35.700631 ddr_geometry:1
4047 11:04:35.702731 ddr_geometry:1
4048 11:04:35.703140 ddr_geometry:1
4049 11:04:35.706456 ddr_geometry:1
4050 11:04:35.706883 ddr_geometry:1
4051 11:04:35.709211 High Freq DUMMY_READ_FOR_TRACKING: ON
4052 11:04:35.712544 ZQCS_ENABLE_LP4: OFF
4053 11:04:35.716393 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
4054 11:04:35.719339 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
4055 11:04:35.719732 SPM_CONTROL_AFTERK: ON
4056 11:04:35.722966 IMPEDANCE_TRACKING: ON
4057 11:04:35.723349 TEMP_SENSOR: ON
4058 11:04:35.726307 PER_BANK_REFRESH: ON
4059 11:04:35.726686 HW_SAVE_FOR_SR: ON
4060 11:04:35.729834 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4061 11:04:35.732541 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4062 11:04:35.736255 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4063 11:04:35.739647 Read ODT Tracking: ON
4064 11:04:35.742954 =========================
4065 11:04:35.743383
4066 11:04:35.743692 [TA2_TEST]
4067 11:04:35.744024 === TA2 HW
4068 11:04:35.749748 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4069 11:04:35.752910 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4070 11:04:35.759367 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4071 11:04:35.763004 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4072 11:04:35.763456
4073 11:04:35.765727 [MEM_TEST] 03: After run time config
4074 11:04:35.777626 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4075 11:04:35.780939 [complex_mem_test] start addr:0x40024000, len:131072
4076 11:04:35.985088 1st complex R/W mem test pass
4077 11:04:35.991650 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4078 11:04:35.994958 sync preloader write leveling
4079 11:04:35.998729 sync preloader cbt_mr12
4080 11:04:36.001925 sync preloader cbt_clk_dly
4081 11:04:36.002391 sync preloader cbt_cmd_dly
4082 11:04:36.005364 sync preloader cbt_cs
4083 11:04:36.008728 sync preloader cbt_ca_perbit_delay
4084 11:04:36.009174 sync preloader clk_delay
4085 11:04:36.011918 sync preloader dqs_delay
4086 11:04:36.014923 sync preloader u1Gating2T_Save
4087 11:04:36.019062 sync preloader u1Gating05T_Save
4088 11:04:36.022555 sync preloader u1Gatingfine_tune_Save
4089 11:04:36.025109 sync preloader u1Gatingucpass_count_Save
4090 11:04:36.028361 sync preloader u1TxWindowPerbitVref_Save
4091 11:04:36.031604 sync preloader u1TxCenter_min_Save
4092 11:04:36.035076 sync preloader u1TxCenter_max_Save
4093 11:04:36.038518 sync preloader u1Txwin_center_Save
4094 11:04:36.041897 sync preloader u1Txfirst_pass_Save
4095 11:04:36.045268 sync preloader u1Txlast_pass_Save
4096 11:04:36.045715 sync preloader u1RxDatlat_Save
4097 11:04:36.048721 sync preloader u1RxWinPerbitVref_Save
4098 11:04:36.055120 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4099 11:04:36.058649 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4100 11:04:36.061807 sync preloader delay_cell_unit
4101 11:04:36.068475 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4102 11:04:36.071931 sync preloader write leveling
4103 11:04:36.072320 sync preloader cbt_mr12
4104 11:04:36.075149 sync preloader cbt_clk_dly
4105 11:04:36.078478 sync preloader cbt_cmd_dly
4106 11:04:36.079013 sync preloader cbt_cs
4107 11:04:36.082188 sync preloader cbt_ca_perbit_delay
4108 11:04:36.085588 sync preloader clk_delay
4109 11:04:36.086022 sync preloader dqs_delay
4110 11:04:36.088704 sync preloader u1Gating2T_Save
4111 11:04:36.092200 sync preloader u1Gating05T_Save
4112 11:04:36.095183 sync preloader u1Gatingfine_tune_Save
4113 11:04:36.098594 sync preloader u1Gatingucpass_count_Save
4114 11:04:36.101593 sync preloader u1TxWindowPerbitVref_Save
4115 11:04:36.105389 sync preloader u1TxCenter_min_Save
4116 11:04:36.108211 sync preloader u1TxCenter_max_Save
4117 11:04:36.111817 sync preloader u1Txwin_center_Save
4118 11:04:36.115364 sync preloader u1Txfirst_pass_Save
4119 11:04:36.118561 sync preloader u1Txlast_pass_Save
4120 11:04:36.122124 sync preloader u1RxDatlat_Save
4121 11:04:36.125191 sync preloader u1RxWinPerbitVref_Save
4122 11:04:36.128606 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4123 11:04:36.131751 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4124 11:04:36.135052 sync preloader delay_cell_unit
4125 11:04:36.141841 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4126 11:04:36.145103 sync preloader write leveling
4127 11:04:36.148551 sync preloader cbt_mr12
4128 11:04:36.148958 sync preloader cbt_clk_dly
4129 11:04:36.151951 sync preloader cbt_cmd_dly
4130 11:04:36.155074 sync preloader cbt_cs
4131 11:04:36.158727 sync preloader cbt_ca_perbit_delay
4132 11:04:36.159113 sync preloader clk_delay
4133 11:04:36.162473 sync preloader dqs_delay
4134 11:04:36.165385 sync preloader u1Gating2T_Save
4135 11:04:36.168460 sync preloader u1Gating05T_Save
4136 11:04:36.172116 sync preloader u1Gatingfine_tune_Save
4137 11:04:36.175162 sync preloader u1Gatingucpass_count_Save
4138 11:04:36.178497 sync preloader u1TxWindowPerbitVref_Save
4139 11:04:36.182251 sync preloader u1TxCenter_min_Save
4140 11:04:36.185410 sync preloader u1TxCenter_max_Save
4141 11:04:36.188231 sync preloader u1Txwin_center_Save
4142 11:04:36.191527 sync preloader u1Txfirst_pass_Save
4143 11:04:36.191908 sync preloader u1Txlast_pass_Save
4144 11:04:36.195294 sync preloader u1RxDatlat_Save
4145 11:04:36.198381 sync preloader u1RxWinPerbitVref_Save
4146 11:04:36.205629 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4147 11:04:36.208288 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4148 11:04:36.211633 sync preloader delay_cell_unit
4149 11:04:36.214851 just_for_test_dump_coreboot_params dump all params
4150 11:04:36.215400 dump source = 0x0
4151 11:04:36.218103 dump params frequency:1600
4152 11:04:36.221645 dump params rank number:2
4153 11:04:36.222031
4154 11:04:36.225478 dump params write leveling
4155 11:04:36.228531 write leveling[0][0][0] = 0x20
4156 11:04:36.228975 write leveling[0][0][1] = 0x18
4157 11:04:36.231249 write leveling[0][1][0] = 0x22
4158 11:04:36.234636 write leveling[0][1][1] = 0x19
4159 11:04:36.237906 write leveling[1][0][0] = 0x23
4160 11:04:36.241216 write leveling[1][0][1] = 0x20
4161 11:04:36.244833 write leveling[1][1][0] = 0x28
4162 11:04:36.245387 write leveling[1][1][1] = 0x20
4163 11:04:36.247679 dump params cbt_cs
4164 11:04:36.248218 cbt_cs[0][0] = 0x9
4165 11:04:36.251534 cbt_cs[0][1] = 0x9
4166 11:04:36.251925 cbt_cs[1][0] = 0xa
4167 11:04:36.254728 cbt_cs[1][1] = 0xa
4168 11:04:36.257827 dump params cbt_mr12
4169 11:04:36.258210 cbt_mr12[0][0] = 0x20
4170 11:04:36.261358 cbt_mr12[0][1] = 0x1e
4171 11:04:36.261741 cbt_mr12[1][0] = 0x20
4172 11:04:36.264698 cbt_mr12[1][1] = 0x1e
4173 11:04:36.267946 dump params tx window
4174 11:04:36.268329 tx_center_min[0][0][0] = 985
4175 11:04:36.271200 tx_center_max[0][0][0] = 992
4176 11:04:36.274785 tx_center_min[0][0][1] = 978
4177 11:04:36.278163 tx_center_max[0][0][1] = 985
4178 11:04:36.278562 tx_center_min[0][1][0] = 989
4179 11:04:36.280791 tx_center_max[0][1][0] = 995
4180 11:04:36.284192 tx_center_min[0][1][1] = 979
4181 11:04:36.287307 tx_center_max[0][1][1] = 986
4182 11:04:36.291428 tx_center_min[1][0][0] = 991
4183 11:04:36.294660 tx_center_max[1][0][0] = 996
4184 11:04:36.295045 tx_center_min[1][0][1] = 984
4185 11:04:36.297895 tx_center_max[1][0][1] = 991
4186 11:04:36.300558 tx_center_min[1][1][0] = 992
4187 11:04:36.304008 tx_center_max[1][1][0] = 997
4188 11:04:36.304406 tx_center_min[1][1][1] = 982
4189 11:04:36.307541 tx_center_max[1][1][1] = 990
4190 11:04:36.311319 dump params tx window
4191 11:04:36.313718 tx_win_center[0][0][0] = 991
4192 11:04:36.314303 tx_first_pass[0][0][0] = 979
4193 11:04:36.317595 tx_last_pass[0][0][0] = 1004
4194 11:04:36.320496 tx_win_center[0][0][1] = 991
4195 11:04:36.323966 tx_first_pass[0][0][1] = 979
4196 11:04:36.327204 tx_last_pass[0][0][1] = 1003
4197 11:04:36.327589 tx_win_center[0][0][2] = 992
4198 11:04:36.330711 tx_first_pass[0][0][2] = 979
4199 11:04:36.334316 tx_last_pass[0][0][2] = 1005
4200 11:04:36.337349 tx_win_center[0][0][3] = 985
4201 11:04:36.340665 tx_first_pass[0][0][3] = 975
4202 11:04:36.341208 tx_last_pass[0][0][3] = 996
4203 11:04:36.343885 tx_win_center[0][0][4] = 991
4204 11:04:36.347432 tx_first_pass[0][0][4] = 979
4205 11:04:36.350682 tx_last_pass[0][0][4] = 1003
4206 11:04:36.351187 tx_win_center[0][0][5] = 988
4207 11:04:36.353700 tx_first_pass[0][0][5] = 977
4208 11:04:36.357449 tx_last_pass[0][0][5] = 999
4209 11:04:36.360584 tx_win_center[0][0][6] = 988
4210 11:04:36.364314 tx_first_pass[0][0][6] = 977
4211 11:04:36.364703 tx_last_pass[0][0][6] = 1000
4212 11:04:36.367123 tx_win_center[0][0][7] = 990
4213 11:04:36.370677 tx_first_pass[0][0][7] = 979
4214 11:04:36.373840 tx_last_pass[0][0][7] = 1002
4215 11:04:36.374359 tx_win_center[0][0][8] = 978
4216 11:04:36.377513 tx_first_pass[0][0][8] = 967
4217 11:04:36.380397 tx_last_pass[0][0][8] = 989
4218 11:04:36.384010 tx_win_center[0][0][9] = 979
4219 11:04:36.387034 tx_first_pass[0][0][9] = 968
4220 11:04:36.387593 tx_last_pass[0][0][9] = 990
4221 11:04:36.391138 tx_win_center[0][0][10] = 985
4222 11:04:36.393736 tx_first_pass[0][0][10] = 973
4223 11:04:36.397110 tx_last_pass[0][0][10] = 997
4224 11:04:36.400854 tx_win_center[0][0][11] = 978
4225 11:04:36.401071 tx_first_pass[0][0][11] = 967
4226 11:04:36.403426 tx_last_pass[0][0][11] = 990
4227 11:04:36.407150 tx_win_center[0][0][12] = 979
4228 11:04:36.410342 tx_first_pass[0][0][12] = 968
4229 11:04:36.413483 tx_last_pass[0][0][12] = 991
4230 11:04:36.413641 tx_win_center[0][0][13] = 979
4231 11:04:36.416796 tx_first_pass[0][0][13] = 968
4232 11:04:36.420034 tx_last_pass[0][0][13] = 991
4233 11:04:36.423290 tx_win_center[0][0][14] = 980
4234 11:04:36.426956 tx_first_pass[0][0][14] = 968
4235 11:04:36.427032 tx_last_pass[0][0][14] = 993
4236 11:04:36.430145 tx_win_center[0][0][15] = 984
4237 11:04:36.433682 tx_first_pass[0][0][15] = 972
4238 11:04:36.436872 tx_last_pass[0][0][15] = 996
4239 11:04:36.440113 tx_win_center[0][1][0] = 995
4240 11:04:36.440210 tx_first_pass[0][1][0] = 983
4241 11:04:36.443794 tx_last_pass[0][1][0] = 1008
4242 11:04:36.446631 tx_win_center[0][1][1] = 994
4243 11:04:36.450069 tx_first_pass[0][1][1] = 981
4244 11:04:36.453277 tx_last_pass[0][1][1] = 1007
4245 11:04:36.453372 tx_win_center[0][1][2] = 995
4246 11:04:36.457170 tx_first_pass[0][1][2] = 983
4247 11:04:36.460078 tx_last_pass[0][1][2] = 1008
4248 11:04:36.463260 tx_win_center[0][1][3] = 989
4249 11:04:36.466893 tx_first_pass[0][1][3] = 978
4250 11:04:36.466970 tx_last_pass[0][1][3] = 1000
4251 11:04:36.469899 tx_win_center[0][1][4] = 994
4252 11:04:36.473461 tx_first_pass[0][1][4] = 981
4253 11:04:36.476479 tx_last_pass[0][1][4] = 1007
4254 11:04:36.476562 tx_win_center[0][1][5] = 990
4255 11:04:36.479693 tx_first_pass[0][1][5] = 979
4256 11:04:36.483042 tx_last_pass[0][1][5] = 1002
4257 11:04:36.487027 tx_win_center[0][1][6] = 992
4258 11:04:36.489658 tx_first_pass[0][1][6] = 980
4259 11:04:36.489729 tx_last_pass[0][1][6] = 1004
4260 11:04:36.493391 tx_win_center[0][1][7] = 993
4261 11:04:36.496730 tx_first_pass[0][1][7] = 980
4262 11:04:36.499658 tx_last_pass[0][1][7] = 1007
4263 11:04:36.499730 tx_win_center[0][1][8] = 979
4264 11:04:36.503625 tx_first_pass[0][1][8] = 968
4265 11:04:36.506486 tx_last_pass[0][1][8] = 991
4266 11:04:36.510261 tx_win_center[0][1][9] = 982
4267 11:04:36.513271 tx_first_pass[0][1][9] = 971
4268 11:04:36.513336 tx_last_pass[0][1][9] = 993
4269 11:04:36.516655 tx_win_center[0][1][10] = 986
4270 11:04:36.520225 tx_first_pass[0][1][10] = 975
4271 11:04:36.523312 tx_last_pass[0][1][10] = 997
4272 11:04:36.526625 tx_win_center[0][1][11] = 980
4273 11:04:36.526696 tx_first_pass[0][1][11] = 968
4274 11:04:36.529930 tx_last_pass[0][1][11] = 993
4275 11:04:36.533003 tx_win_center[0][1][12] = 982
4276 11:04:36.536327 tx_first_pass[0][1][12] = 970
4277 11:04:36.539651 tx_last_pass[0][1][12] = 995
4278 11:04:36.539868 tx_win_center[0][1][13] = 981
4279 11:04:36.542937 tx_first_pass[0][1][13] = 970
4280 11:04:36.546865 tx_last_pass[0][1][13] = 993
4281 11:04:36.549774 tx_win_center[0][1][14] = 983
4282 11:04:36.553682 tx_first_pass[0][1][14] = 972
4283 11:04:36.553759 tx_last_pass[0][1][14] = 995
4284 11:04:36.556397 tx_win_center[0][1][15] = 985
4285 11:04:36.559958 tx_first_pass[0][1][15] = 974
4286 11:04:36.563374 tx_last_pass[0][1][15] = 997
4287 11:04:36.566759 tx_win_center[1][0][0] = 996
4288 11:04:36.566863 tx_first_pass[1][0][0] = 984
4289 11:04:36.569648 tx_last_pass[1][0][0] = 1009
4290 11:04:36.572875 tx_win_center[1][0][1] = 994
4291 11:04:36.576169 tx_first_pass[1][0][1] = 982
4292 11:04:36.579787 tx_last_pass[1][0][1] = 1007
4293 11:04:36.579868 tx_win_center[1][0][2] = 993
4294 11:04:36.583197 tx_first_pass[1][0][2] = 980
4295 11:04:36.586355 tx_last_pass[1][0][2] = 1006
4296 11:04:36.589709 tx_win_center[1][0][3] = 991
4297 11:04:36.589860 tx_first_pass[1][0][3] = 978
4298 11:04:36.592903 tx_last_pass[1][0][3] = 1005
4299 11:04:36.596272 tx_win_center[1][0][4] = 995
4300 11:04:36.599803 tx_first_pass[1][0][4] = 983
4301 11:04:36.602798 tx_last_pass[1][0][4] = 1007
4302 11:04:36.602911 tx_win_center[1][0][5] = 996
4303 11:04:36.606547 tx_first_pass[1][0][5] = 984
4304 11:04:36.609495 tx_last_pass[1][0][5] = 1008
4305 11:04:36.612906 tx_win_center[1][0][6] = 995
4306 11:04:36.616256 tx_first_pass[1][0][6] = 982
4307 11:04:36.616368 tx_last_pass[1][0][6] = 1008
4308 11:04:36.619593 tx_win_center[1][0][7] = 994
4309 11:04:36.622870 tx_first_pass[1][0][7] = 982
4310 11:04:36.625755 tx_last_pass[1][0][7] = 1007
4311 11:04:36.629469 tx_win_center[1][0][8] = 988
4312 11:04:36.629629 tx_first_pass[1][0][8] = 976
4313 11:04:36.632898 tx_last_pass[1][0][8] = 1000
4314 11:04:36.635795 tx_win_center[1][0][9] = 987
4315 11:04:36.639299 tx_first_pass[1][0][9] = 975
4316 11:04:36.639423 tx_last_pass[1][0][9] = 999
4317 11:04:36.642540 tx_win_center[1][0][10] = 991
4318 11:04:36.646326 tx_first_pass[1][0][10] = 980
4319 11:04:36.649085 tx_last_pass[1][0][10] = 1002
4320 11:04:36.652864 tx_win_center[1][0][11] = 990
4321 11:04:36.656366 tx_first_pass[1][0][11] = 979
4322 11:04:36.656491 tx_last_pass[1][0][11] = 1002
4323 11:04:36.659127 tx_win_center[1][0][12] = 991
4324 11:04:36.662858 tx_first_pass[1][0][12] = 981
4325 11:04:36.666102 tx_last_pass[1][0][12] = 1001
4326 11:04:36.669666 tx_win_center[1][0][13] = 991
4327 11:04:36.669791 tx_first_pass[1][0][13] = 981
4328 11:04:36.672709 tx_last_pass[1][0][13] = 1002
4329 11:04:36.676323 tx_win_center[1][0][14] = 991
4330 11:04:36.679339 tx_first_pass[1][0][14] = 980
4331 11:04:36.682524 tx_last_pass[1][0][14] = 1002
4332 11:04:36.682708 tx_win_center[1][0][15] = 984
4333 11:04:36.685704 tx_first_pass[1][0][15] = 971
4334 11:04:36.689748 tx_last_pass[1][0][15] = 998
4335 11:04:36.692483 tx_win_center[1][1][0] = 997
4336 11:04:36.695672 tx_first_pass[1][1][0] = 986
4337 11:04:36.695944 tx_last_pass[1][1][0] = 1009
4338 11:04:36.699338 tx_win_center[1][1][1] = 996
4339 11:04:36.702629 tx_first_pass[1][1][1] = 984
4340 11:04:36.705680 tx_last_pass[1][1][1] = 1008
4341 11:04:36.709031 tx_win_center[1][1][2] = 994
4342 11:04:36.709422 tx_first_pass[1][1][2] = 982
4343 11:04:36.712535 tx_last_pass[1][1][2] = 1007
4344 11:04:36.715979 tx_win_center[1][1][3] = 992
4345 11:04:36.719426 tx_first_pass[1][1][3] = 979
4346 11:04:36.722562 tx_last_pass[1][1][3] = 1006
4347 11:04:36.723017 tx_win_center[1][1][4] = 996
4348 11:04:36.726622 tx_first_pass[1][1][4] = 985
4349 11:04:36.729023 tx_last_pass[1][1][4] = 1008
4350 11:04:36.732605 tx_win_center[1][1][5] = 996
4351 11:04:36.733024 tx_first_pass[1][1][5] = 984
4352 11:04:36.736139 tx_last_pass[1][1][5] = 1008
4353 11:04:36.739440 tx_win_center[1][1][6] = 996
4354 11:04:36.742959 tx_first_pass[1][1][6] = 984
4355 11:04:36.746153 tx_last_pass[1][1][6] = 1008
4356 11:04:36.746575 tx_win_center[1][1][7] = 996
4357 11:04:36.749406 tx_first_pass[1][1][7] = 984
4358 11:04:36.752567 tx_last_pass[1][1][7] = 1008
4359 11:04:36.756080 tx_win_center[1][1][8] = 986
4360 11:04:36.759566 tx_first_pass[1][1][8] = 974
4361 11:04:36.759949 tx_last_pass[1][1][8] = 998
4362 11:04:36.762489 tx_win_center[1][1][9] = 986
4363 11:04:36.765997 tx_first_pass[1][1][9] = 974
4364 11:04:36.769416 tx_last_pass[1][1][9] = 998
4365 11:04:36.769833 tx_win_center[1][1][10] = 988
4366 11:04:36.772748 tx_first_pass[1][1][10] = 977
4367 11:04:36.775998 tx_last_pass[1][1][10] = 1000
4368 11:04:36.779067 tx_win_center[1][1][11] = 989
4369 11:04:36.782435 tx_first_pass[1][1][11] = 978
4370 11:04:36.782861 tx_last_pass[1][1][11] = 1001
4371 11:04:36.785895 tx_win_center[1][1][12] = 989
4372 11:04:36.789389 tx_first_pass[1][1][12] = 978
4373 11:04:36.792392 tx_last_pass[1][1][12] = 1001
4374 11:04:36.795497 tx_win_center[1][1][13] = 990
4375 11:04:36.799099 tx_first_pass[1][1][13] = 979
4376 11:04:36.799514 tx_last_pass[1][1][13] = 1001
4377 11:04:36.802761 tx_win_center[1][1][14] = 988
4378 11:04:36.805819 tx_first_pass[1][1][14] = 977
4379 11:04:36.808846 tx_last_pass[1][1][14] = 1000
4380 11:04:36.812279 tx_win_center[1][1][15] = 982
4381 11:04:36.815240 tx_first_pass[1][1][15] = 970
4382 11:04:36.815662 tx_last_pass[1][1][15] = 995
4383 11:04:36.818812 dump params rx window
4384 11:04:36.822290 rx_firspass[0][0][0] = 9
4385 11:04:36.822674 rx_lastpass[0][0][0] = 37
4386 11:04:36.825580 rx_firspass[0][0][1] = 8
4387 11:04:36.828632 rx_lastpass[0][0][1] = 37
4388 11:04:36.829046 rx_firspass[0][0][2] = 11
4389 11:04:36.832232 rx_lastpass[0][0][2] = 37
4390 11:04:36.835155 rx_firspass[0][0][3] = 3
4391 11:04:36.838561 rx_lastpass[0][0][3] = 32
4392 11:04:36.838941 rx_firspass[0][0][4] = 9
4393 11:04:36.842218 rx_lastpass[0][0][4] = 36
4394 11:04:36.845278 rx_firspass[0][0][5] = 5
4395 11:04:36.845734 rx_lastpass[0][0][5] = 32
4396 11:04:36.848523 rx_firspass[0][0][6] = 6
4397 11:04:36.851714 rx_lastpass[0][0][6] = 35
4398 11:04:36.852130 rx_firspass[0][0][7] = 10
4399 11:04:36.855351 rx_lastpass[0][0][7] = 35
4400 11:04:36.859069 rx_firspass[0][0][8] = 4
4401 11:04:36.861773 rx_lastpass[0][0][8] = 31
4402 11:04:36.862156 rx_firspass[0][0][9] = 6
4403 11:04:36.865256 rx_lastpass[0][0][9] = 32
4404 11:04:36.868712 rx_firspass[0][0][10] = 12
4405 11:04:36.869096 rx_lastpass[0][0][10] = 39
4406 11:04:36.871712 rx_firspass[0][0][11] = 5
4407 11:04:36.875292 rx_lastpass[0][0][11] = 31
4408 11:04:36.878634 rx_firspass[0][0][12] = 6
4409 11:04:36.879105 rx_lastpass[0][0][12] = 34
4410 11:04:36.881845 rx_firspass[0][0][13] = 7
4411 11:04:36.885091 rx_lastpass[0][0][13] = 32
4412 11:04:36.888498 rx_firspass[0][0][14] = 8
4413 11:04:36.888899 rx_lastpass[0][0][14] = 35
4414 11:04:36.891889 rx_firspass[0][0][15] = 10
4415 11:04:36.895327 rx_lastpass[0][0][15] = 36
4416 11:04:36.895710 rx_firspass[0][1][0] = 10
4417 11:04:36.898346 rx_lastpass[0][1][0] = 39
4418 11:04:36.901644 rx_firspass[0][1][1] = 8
4419 11:04:36.905203 rx_lastpass[0][1][1] = 39
4420 11:04:36.905617 rx_firspass[0][1][2] = 10
4421 11:04:36.908312 rx_lastpass[0][1][2] = 39
4422 11:04:36.911991 rx_firspass[0][1][3] = 2
4423 11:04:36.912386 rx_lastpass[0][1][3] = 32
4424 11:04:36.915068 rx_firspass[0][1][4] = 10
4425 11:04:36.918072 rx_lastpass[0][1][4] = 37
4426 11:04:36.921494 rx_firspass[0][1][5] = 4
4427 11:04:36.922036 rx_lastpass[0][1][5] = 34
4428 11:04:36.925069 rx_firspass[0][1][6] = 5
4429 11:04:36.928236 rx_lastpass[0][1][6] = 35
4430 11:04:36.928617 rx_firspass[0][1][7] = 7
4431 11:04:36.932062 rx_lastpass[0][1][7] = 37
4432 11:04:36.935145 rx_firspass[0][1][8] = 3
4433 11:04:36.935561 rx_lastpass[0][1][8] = 32
4434 11:04:36.938241 rx_firspass[0][1][9] = 6
4435 11:04:36.941760 rx_lastpass[0][1][9] = 34
4436 11:04:36.945230 rx_firspass[0][1][10] = 12
4437 11:04:36.945725 rx_lastpass[0][1][10] = 41
4438 11:04:36.948237 rx_firspass[0][1][11] = 4
4439 11:04:36.951448 rx_lastpass[0][1][11] = 32
4440 11:04:36.951849 rx_firspass[0][1][12] = 6
4441 11:04:36.955266 rx_lastpass[0][1][12] = 36
4442 11:04:36.958136 rx_firspass[0][1][13] = 8
4443 11:04:36.961485 rx_lastpass[0][1][13] = 34
4444 11:04:36.961905 rx_firspass[0][1][14] = 8
4445 11:04:36.964925 rx_lastpass[0][1][14] = 37
4446 11:04:36.968231 rx_firspass[0][1][15] = 10
4447 11:04:36.971400 rx_lastpass[0][1][15] = 39
4448 11:04:36.971782 rx_firspass[1][0][0] = 8
4449 11:04:36.974683 rx_lastpass[1][0][0] = 37
4450 11:04:36.977867 rx_firspass[1][0][1] = 7
4451 11:04:36.978252 rx_lastpass[1][0][1] = 35
4452 11:04:36.981401 rx_firspass[1][0][2] = 5
4453 11:04:36.984488 rx_lastpass[1][0][2] = 35
4454 11:04:36.987921 rx_firspass[1][0][3] = 5
4455 11:04:36.988301 rx_lastpass[1][0][3] = 32
4456 11:04:36.991442 rx_firspass[1][0][4] = 7
4457 11:04:36.994915 rx_lastpass[1][0][4] = 36
4458 11:04:36.995409 rx_firspass[1][0][5] = 9
4459 11:04:36.998066 rx_lastpass[1][0][5] = 37
4460 11:04:37.001627 rx_firspass[1][0][6] = 11
4461 11:04:37.002047 rx_lastpass[1][0][6] = 37
4462 11:04:37.004511 rx_firspass[1][0][7] = 9
4463 11:04:37.007664 rx_lastpass[1][0][7] = 36
4464 11:04:37.008210 rx_firspass[1][0][8] = 5
4465 11:04:37.011372 rx_lastpass[1][0][8] = 32
4466 11:04:37.014823 rx_firspass[1][0][9] = 3
4467 11:04:37.017823 rx_lastpass[1][0][9] = 31
4468 11:04:37.018332 rx_firspass[1][0][10] = 6
4469 11:04:37.021564 rx_lastpass[1][0][10] = 36
4470 11:04:37.024322 rx_firspass[1][0][11] = 7
4471 11:04:37.027647 rx_lastpass[1][0][11] = 36
4472 11:04:37.028196 rx_firspass[1][0][12] = 8
4473 11:04:37.031132 rx_lastpass[1][0][12] = 35
4474 11:04:37.034856 rx_firspass[1][0][13] = 8
4475 11:04:37.035381 rx_lastpass[1][0][13] = 36
4476 11:04:37.037963 rx_firspass[1][0][14] = 8
4477 11:04:37.041068 rx_lastpass[1][0][14] = 34
4478 11:04:37.044440 rx_firspass[1][0][15] = 4
4479 11:04:37.045012 rx_lastpass[1][0][15] = 28
4480 11:04:37.047710 rx_firspass[1][1][0] = 7
4481 11:04:37.051495 rx_lastpass[1][1][0] = 38
4482 11:04:37.051984 rx_firspass[1][1][1] = 7
4483 11:04:37.054749 rx_lastpass[1][1][1] = 37
4484 11:04:37.057920 rx_firspass[1][1][2] = 4
4485 11:04:37.061224 rx_lastpass[1][1][2] = 35
4486 11:04:37.061606 rx_firspass[1][1][3] = 3
4487 11:04:37.064229 rx_lastpass[1][1][3] = 33
4488 11:04:37.068015 rx_firspass[1][1][4] = 5
4489 11:04:37.068441 rx_lastpass[1][1][4] = 37
4490 11:04:37.071351 rx_firspass[1][1][5] = 8
4491 11:04:37.074427 rx_lastpass[1][1][5] = 39
4492 11:04:37.074844 rx_firspass[1][1][6] = 9
4493 11:04:37.077711 rx_lastpass[1][1][6] = 40
4494 11:04:37.081386 rx_firspass[1][1][7] = 8
4495 11:04:37.085196 rx_lastpass[1][1][7] = 36
4496 11:04:37.085833 rx_firspass[1][1][8] = 3
4497 11:04:37.088421 rx_lastpass[1][1][8] = 33
4498 11:04:37.091204 rx_firspass[1][1][9] = 2
4499 11:04:37.091584 rx_lastpass[1][1][9] = 32
4500 11:04:37.094564 rx_firspass[1][1][10] = 6
4501 11:04:37.097671 rx_lastpass[1][1][10] = 37
4502 11:04:37.098121 rx_firspass[1][1][11] = 7
4503 11:04:37.101210 rx_lastpass[1][1][11] = 37
4504 11:04:37.104199 rx_firspass[1][1][12] = 7
4505 11:04:37.107928 rx_lastpass[1][1][12] = 36
4506 11:04:37.108346 rx_firspass[1][1][13] = 7
4507 11:04:37.111527 rx_lastpass[1][1][13] = 37
4508 11:04:37.114773 rx_firspass[1][1][14] = 7
4509 11:04:37.117542 rx_lastpass[1][1][14] = 36
4510 11:04:37.117932 rx_firspass[1][1][15] = 1
4511 11:04:37.121296 rx_lastpass[1][1][15] = 29
4512 11:04:37.124206 dump params clk_delay
4513 11:04:37.124586 clk_delay[0] = 2
4514 11:04:37.127485 clk_delay[1] = 0
4515 11:04:37.127866 dump params dqs_delay
4516 11:04:37.130916 dqs_delay[0][0] = 0
4517 11:04:37.131298 dqs_delay[0][1] = 0
4518 11:04:37.134329 dqs_delay[1][0] = 0
4519 11:04:37.134709 dqs_delay[1][1] = 0
4520 11:04:37.138024 dump params delay_cell_unit = 833
4521 11:04:37.141193 dump source = 0x0
4522 11:04:37.141574 dump params frequency:1200
4523 11:04:37.144242 dump params rank number:2
4524 11:04:37.144635
4525 11:04:37.147778 dump params write leveling
4526 11:04:37.150886 write leveling[0][0][0] = 0x0
4527 11:04:37.154154 write leveling[0][0][1] = 0x0
4528 11:04:37.154567 write leveling[0][1][0] = 0x0
4529 11:04:37.157768 write leveling[0][1][1] = 0x0
4530 11:04:37.160617 write leveling[1][0][0] = 0x0
4531 11:04:37.164451 write leveling[1][0][1] = 0x0
4532 11:04:37.167678 write leveling[1][1][0] = 0x0
4533 11:04:37.168113 write leveling[1][1][1] = 0x0
4534 11:04:37.170783 dump params cbt_cs
4535 11:04:37.171316 cbt_cs[0][0] = 0x0
4536 11:04:37.173837 cbt_cs[0][1] = 0x0
4537 11:04:37.177588 cbt_cs[1][0] = 0x0
4538 11:04:37.177969 cbt_cs[1][1] = 0x0
4539 11:04:37.180764 dump params cbt_mr12
4540 11:04:37.181304 cbt_mr12[0][0] = 0x0
4541 11:04:37.183882 cbt_mr12[0][1] = 0x0
4542 11:04:37.184261 cbt_mr12[1][0] = 0x0
4543 11:04:37.187194 cbt_mr12[1][1] = 0x0
4544 11:04:37.190303 dump params tx window
4545 11:04:37.190686 tx_center_min[0][0][0] = 0
4546 11:04:37.194156 tx_center_max[0][0][0] = 0
4547 11:04:37.197256 tx_center_min[0][0][1] = 0
4548 11:04:37.197676 tx_center_max[0][0][1] = 0
4549 11:04:37.200167 tx_center_min[0][1][0] = 0
4550 11:04:37.203799 tx_center_max[0][1][0] = 0
4551 11:04:37.206915 tx_center_min[0][1][1] = 0
4552 11:04:37.207326 tx_center_max[0][1][1] = 0
4553 11:04:37.210755 tx_center_min[1][0][0] = 0
4554 11:04:37.214277 tx_center_max[1][0][0] = 0
4555 11:04:37.217034 tx_center_min[1][0][1] = 0
4556 11:04:37.217473 tx_center_max[1][0][1] = 0
4557 11:04:37.221228 tx_center_min[1][1][0] = 0
4558 11:04:37.223944 tx_center_max[1][1][0] = 0
4559 11:04:37.227212 tx_center_min[1][1][1] = 0
4560 11:04:37.227625 tx_center_max[1][1][1] = 0
4561 11:04:37.230682 dump params tx window
4562 11:04:37.233987 tx_win_center[0][0][0] = 0
4563 11:04:37.234369 tx_first_pass[0][0][0] = 0
4564 11:04:37.237232 tx_last_pass[0][0][0] = 0
4565 11:04:37.240640 tx_win_center[0][0][1] = 0
4566 11:04:37.244041 tx_first_pass[0][0][1] = 0
4567 11:04:37.244461 tx_last_pass[0][0][1] = 0
4568 11:04:37.247544 tx_win_center[0][0][2] = 0
4569 11:04:37.250442 tx_first_pass[0][0][2] = 0
4570 11:04:37.250861 tx_last_pass[0][0][2] = 0
4571 11:04:37.253825 tx_win_center[0][0][3] = 0
4572 11:04:37.257321 tx_first_pass[0][0][3] = 0
4573 11:04:37.260746 tx_last_pass[0][0][3] = 0
4574 11:04:37.261213 tx_win_center[0][0][4] = 0
4575 11:04:37.264075 tx_first_pass[0][0][4] = 0
4576 11:04:37.267088 tx_last_pass[0][0][4] = 0
4577 11:04:37.270806 tx_win_center[0][0][5] = 0
4578 11:04:37.271258 tx_first_pass[0][0][5] = 0
4579 11:04:37.273962 tx_last_pass[0][0][5] = 0
4580 11:04:37.277395 tx_win_center[0][0][6] = 0
4581 11:04:37.277780 tx_first_pass[0][0][6] = 0
4582 11:04:37.280931 tx_last_pass[0][0][6] = 0
4583 11:04:37.283984 tx_win_center[0][0][7] = 0
4584 11:04:37.287281 tx_first_pass[0][0][7] = 0
4585 11:04:37.287754 tx_last_pass[0][0][7] = 0
4586 11:04:37.290290 tx_win_center[0][0][8] = 0
4587 11:04:37.293680 tx_first_pass[0][0][8] = 0
4588 11:04:37.294099 tx_last_pass[0][0][8] = 0
4589 11:04:37.297145 tx_win_center[0][0][9] = 0
4590 11:04:37.300610 tx_first_pass[0][0][9] = 0
4591 11:04:37.304033 tx_last_pass[0][0][9] = 0
4592 11:04:37.304413 tx_win_center[0][0][10] = 0
4593 11:04:37.307075 tx_first_pass[0][0][10] = 0
4594 11:04:37.310732 tx_last_pass[0][0][10] = 0
4595 11:04:37.313970 tx_win_center[0][0][11] = 0
4596 11:04:37.314458 tx_first_pass[0][0][11] = 0
4597 11:04:37.317160 tx_last_pass[0][0][11] = 0
4598 11:04:37.320371 tx_win_center[0][0][12] = 0
4599 11:04:37.323974 tx_first_pass[0][0][12] = 0
4600 11:04:37.324357 tx_last_pass[0][0][12] = 0
4601 11:04:37.327095 tx_win_center[0][0][13] = 0
4602 11:04:37.330597 tx_first_pass[0][0][13] = 0
4603 11:04:37.333753 tx_last_pass[0][0][13] = 0
4604 11:04:37.334169 tx_win_center[0][0][14] = 0
4605 11:04:37.337547 tx_first_pass[0][0][14] = 0
4606 11:04:37.340489 tx_last_pass[0][0][14] = 0
4607 11:04:37.343617 tx_win_center[0][0][15] = 0
4608 11:04:37.344004 tx_first_pass[0][0][15] = 0
4609 11:04:37.346911 tx_last_pass[0][0][15] = 0
4610 11:04:37.350356 tx_win_center[0][1][0] = 0
4611 11:04:37.353875 tx_first_pass[0][1][0] = 0
4612 11:04:37.354362 tx_last_pass[0][1][0] = 0
4613 11:04:37.357062 tx_win_center[0][1][1] = 0
4614 11:04:37.360300 tx_first_pass[0][1][1] = 0
4615 11:04:37.363518 tx_last_pass[0][1][1] = 0
4616 11:04:37.363933 tx_win_center[0][1][2] = 0
4617 11:04:37.367359 tx_first_pass[0][1][2] = 0
4618 11:04:37.370987 tx_last_pass[0][1][2] = 0
4619 11:04:37.371407 tx_win_center[0][1][3] = 0
4620 11:04:37.373833 tx_first_pass[0][1][3] = 0
4621 11:04:37.377446 tx_last_pass[0][1][3] = 0
4622 11:04:37.380897 tx_win_center[0][1][4] = 0
4623 11:04:37.381339 tx_first_pass[0][1][4] = 0
4624 11:04:37.383830 tx_last_pass[0][1][4] = 0
4625 11:04:37.386915 tx_win_center[0][1][5] = 0
4626 11:04:37.390196 tx_first_pass[0][1][5] = 0
4627 11:04:37.390635 tx_last_pass[0][1][5] = 0
4628 11:04:37.394078 tx_win_center[0][1][6] = 0
4629 11:04:37.396859 tx_first_pass[0][1][6] = 0
4630 11:04:37.397310 tx_last_pass[0][1][6] = 0
4631 11:04:37.400178 tx_win_center[0][1][7] = 0
4632 11:04:37.403458 tx_first_pass[0][1][7] = 0
4633 11:04:37.406836 tx_last_pass[0][1][7] = 0
4634 11:04:37.407224 tx_win_center[0][1][8] = 0
4635 11:04:37.410174 tx_first_pass[0][1][8] = 0
4636 11:04:37.413695 tx_last_pass[0][1][8] = 0
4637 11:04:37.414421 tx_win_center[0][1][9] = 0
4638 11:04:37.417073 tx_first_pass[0][1][9] = 0
4639 11:04:37.420600 tx_last_pass[0][1][9] = 0
4640 11:04:37.423863 tx_win_center[0][1][10] = 0
4641 11:04:37.424505 tx_first_pass[0][1][10] = 0
4642 11:04:37.427085 tx_last_pass[0][1][10] = 0
4643 11:04:37.430133 tx_win_center[0][1][11] = 0
4644 11:04:37.433291 tx_first_pass[0][1][11] = 0
4645 11:04:37.433676 tx_last_pass[0][1][11] = 0
4646 11:04:37.436962 tx_win_center[0][1][12] = 0
4647 11:04:37.439808 tx_first_pass[0][1][12] = 0
4648 11:04:37.443172 tx_last_pass[0][1][12] = 0
4649 11:04:37.443591 tx_win_center[0][1][13] = 0
4650 11:04:37.446714 tx_first_pass[0][1][13] = 0
4651 11:04:37.450257 tx_last_pass[0][1][13] = 0
4652 11:04:37.453522 tx_win_center[0][1][14] = 0
4653 11:04:37.453910 tx_first_pass[0][1][14] = 0
4654 11:04:37.457267 tx_last_pass[0][1][14] = 0
4655 11:04:37.460290 tx_win_center[0][1][15] = 0
4656 11:04:37.463274 tx_first_pass[0][1][15] = 0
4657 11:04:37.463662 tx_last_pass[0][1][15] = 0
4658 11:04:37.466665 tx_win_center[1][0][0] = 0
4659 11:04:37.469735 tx_first_pass[1][0][0] = 0
4660 11:04:37.473171 tx_last_pass[1][0][0] = 0
4661 11:04:37.473590 tx_win_center[1][0][1] = 0
4662 11:04:37.476643 tx_first_pass[1][0][1] = 0
4663 11:04:37.480344 tx_last_pass[1][0][1] = 0
4664 11:04:37.484420 tx_win_center[1][0][2] = 0
4665 11:04:37.484828 tx_first_pass[1][0][2] = 0
4666 11:04:37.486972 tx_last_pass[1][0][2] = 0
4667 11:04:37.489848 tx_win_center[1][0][3] = 0
4668 11:04:37.490356 tx_first_pass[1][0][3] = 0
4669 11:04:37.493576 tx_last_pass[1][0][3] = 0
4670 11:04:37.496770 tx_win_center[1][0][4] = 0
4671 11:04:37.500077 tx_first_pass[1][0][4] = 0
4672 11:04:37.500476 tx_last_pass[1][0][4] = 0
4673 11:04:37.503361 tx_win_center[1][0][5] = 0
4674 11:04:37.506522 tx_first_pass[1][0][5] = 0
4675 11:04:37.509634 tx_last_pass[1][0][5] = 0
4676 11:04:37.510048 tx_win_center[1][0][6] = 0
4677 11:04:37.513021 tx_first_pass[1][0][6] = 0
4678 11:04:37.516692 tx_last_pass[1][0][6] = 0
4679 11:04:37.517088 tx_win_center[1][0][7] = 0
4680 11:04:37.519765 tx_first_pass[1][0][7] = 0
4681 11:04:37.523520 tx_last_pass[1][0][7] = 0
4682 11:04:37.526427 tx_win_center[1][0][8] = 0
4683 11:04:37.526820 tx_first_pass[1][0][8] = 0
4684 11:04:37.529879 tx_last_pass[1][0][8] = 0
4685 11:04:37.533241 tx_win_center[1][0][9] = 0
4686 11:04:37.536326 tx_first_pass[1][0][9] = 0
4687 11:04:37.536848 tx_last_pass[1][0][9] = 0
4688 11:04:37.539557 tx_win_center[1][0][10] = 0
4689 11:04:37.542983 tx_first_pass[1][0][10] = 0
4690 11:04:37.546603 tx_last_pass[1][0][10] = 0
4691 11:04:37.546964 tx_win_center[1][0][11] = 0
4692 11:04:37.549374 tx_first_pass[1][0][11] = 0
4693 11:04:37.552743 tx_last_pass[1][0][11] = 0
4694 11:04:37.555731 tx_win_center[1][0][12] = 0
4695 11:04:37.556145 tx_first_pass[1][0][12] = 0
4696 11:04:37.559781 tx_last_pass[1][0][12] = 0
4697 11:04:37.562622 tx_win_center[1][0][13] = 0
4698 11:04:37.566042 tx_first_pass[1][0][13] = 0
4699 11:04:37.566462 tx_last_pass[1][0][13] = 0
4700 11:04:37.570081 tx_win_center[1][0][14] = 0
4701 11:04:37.572430 tx_first_pass[1][0][14] = 0
4702 11:04:37.576209 tx_last_pass[1][0][14] = 0
4703 11:04:37.576574 tx_win_center[1][0][15] = 0
4704 11:04:37.579498 tx_first_pass[1][0][15] = 0
4705 11:04:37.582569 tx_last_pass[1][0][15] = 0
4706 11:04:37.586257 tx_win_center[1][1][0] = 0
4707 11:04:37.586537 tx_first_pass[1][1][0] = 0
4708 11:04:37.589370 tx_last_pass[1][1][0] = 0
4709 11:04:37.592699 tx_win_center[1][1][1] = 0
4710 11:04:37.595853 tx_first_pass[1][1][1] = 0
4711 11:04:37.596255 tx_last_pass[1][1][1] = 0
4712 11:04:37.599393 tx_win_center[1][1][2] = 0
4713 11:04:37.602505 tx_first_pass[1][1][2] = 0
4714 11:04:37.602797 tx_last_pass[1][1][2] = 0
4715 11:04:37.605808 tx_win_center[1][1][3] = 0
4716 11:04:37.609026 tx_first_pass[1][1][3] = 0
4717 11:04:37.612271 tx_last_pass[1][1][3] = 0
4718 11:04:37.612559 tx_win_center[1][1][4] = 0
4719 11:04:37.615533 tx_first_pass[1][1][4] = 0
4720 11:04:37.619455 tx_last_pass[1][1][4] = 0
4721 11:04:37.622050 tx_win_center[1][1][5] = 0
4722 11:04:37.622266 tx_first_pass[1][1][5] = 0
4723 11:04:37.625661 tx_last_pass[1][1][5] = 0
4724 11:04:37.628866 tx_win_center[1][1][6] = 0
4725 11:04:37.629042 tx_first_pass[1][1][6] = 0
4726 11:04:37.632265 tx_last_pass[1][1][6] = 0
4727 11:04:37.635439 tx_win_center[1][1][7] = 0
4728 11:04:37.638587 tx_first_pass[1][1][7] = 0
4729 11:04:37.638717 tx_last_pass[1][1][7] = 0
4730 11:04:37.642026 tx_win_center[1][1][8] = 0
4731 11:04:37.645274 tx_first_pass[1][1][8] = 0
4732 11:04:37.645385 tx_last_pass[1][1][8] = 0
4733 11:04:37.648918 tx_win_center[1][1][9] = 0
4734 11:04:37.652063 tx_first_pass[1][1][9] = 0
4735 11:04:37.655317 tx_last_pass[1][1][9] = 0
4736 11:04:37.655406 tx_win_center[1][1][10] = 0
4737 11:04:37.658974 tx_first_pass[1][1][10] = 0
4738 11:04:37.661892 tx_last_pass[1][1][10] = 0
4739 11:04:37.665349 tx_win_center[1][1][11] = 0
4740 11:04:37.665436 tx_first_pass[1][1][11] = 0
4741 11:04:37.668814 tx_last_pass[1][1][11] = 0
4742 11:04:37.672124 tx_win_center[1][1][12] = 0
4743 11:04:37.675821 tx_first_pass[1][1][12] = 0
4744 11:04:37.675901 tx_last_pass[1][1][12] = 0
4745 11:04:37.679074 tx_win_center[1][1][13] = 0
4746 11:04:37.682331 tx_first_pass[1][1][13] = 0
4747 11:04:37.685608 tx_last_pass[1][1][13] = 0
4748 11:04:37.685690 tx_win_center[1][1][14] = 0
4749 11:04:37.688752 tx_first_pass[1][1][14] = 0
4750 11:04:37.692155 tx_last_pass[1][1][14] = 0
4751 11:04:37.695336 tx_win_center[1][1][15] = 0
4752 11:04:37.695415 tx_first_pass[1][1][15] = 0
4753 11:04:37.698975 tx_last_pass[1][1][15] = 0
4754 11:04:37.702137 dump params rx window
4755 11:04:37.702234 rx_firspass[0][0][0] = 0
4756 11:04:37.705380 rx_lastpass[0][0][0] = 0
4757 11:04:37.708725 rx_firspass[0][0][1] = 0
4758 11:04:37.708816 rx_lastpass[0][0][1] = 0
4759 11:04:37.712213 rx_firspass[0][0][2] = 0
4760 11:04:37.715510 rx_lastpass[0][0][2] = 0
4761 11:04:37.718663 rx_firspass[0][0][3] = 0
4762 11:04:37.718746 rx_lastpass[0][0][3] = 0
4763 11:04:37.722147 rx_firspass[0][0][4] = 0
4764 11:04:37.726023 rx_lastpass[0][0][4] = 0
4765 11:04:37.726106 rx_firspass[0][0][5] = 0
4766 11:04:37.729153 rx_lastpass[0][0][5] = 0
4767 11:04:37.732708 rx_firspass[0][0][6] = 0
4768 11:04:37.732787 rx_lastpass[0][0][6] = 0
4769 11:04:37.735877 rx_firspass[0][0][7] = 0
4770 11:04:37.738586 rx_lastpass[0][0][7] = 0
4771 11:04:37.738667 rx_firspass[0][0][8] = 0
4772 11:04:37.742194 rx_lastpass[0][0][8] = 0
4773 11:04:37.745313 rx_firspass[0][0][9] = 0
4774 11:04:37.745398 rx_lastpass[0][0][9] = 0
4775 11:04:37.748564 rx_firspass[0][0][10] = 0
4776 11:04:37.751951 rx_lastpass[0][0][10] = 0
4777 11:04:37.755212 rx_firspass[0][0][11] = 0
4778 11:04:37.755295 rx_lastpass[0][0][11] = 0
4779 11:04:37.758834 rx_firspass[0][0][12] = 0
4780 11:04:37.761966 rx_lastpass[0][0][12] = 0
4781 11:04:37.762043 rx_firspass[0][0][13] = 0
4782 11:04:37.765291 rx_lastpass[0][0][13] = 0
4783 11:04:37.768436 rx_firspass[0][0][14] = 0
4784 11:04:37.772299 rx_lastpass[0][0][14] = 0
4785 11:04:37.772374 rx_firspass[0][0][15] = 0
4786 11:04:37.775196 rx_lastpass[0][0][15] = 0
4787 11:04:37.778243 rx_firspass[0][1][0] = 0
4788 11:04:37.778319 rx_lastpass[0][1][0] = 0
4789 11:04:37.781808 rx_firspass[0][1][1] = 0
4790 11:04:37.785764 rx_lastpass[0][1][1] = 0
4791 11:04:37.785840 rx_firspass[0][1][2] = 0
4792 11:04:37.788634 rx_lastpass[0][1][2] = 0
4793 11:04:37.792240 rx_firspass[0][1][3] = 0
4794 11:04:37.795293 rx_lastpass[0][1][3] = 0
4795 11:04:37.795374 rx_firspass[0][1][4] = 0
4796 11:04:37.798485 rx_lastpass[0][1][4] = 0
4797 11:04:37.801580 rx_firspass[0][1][5] = 0
4798 11:04:37.801722 rx_lastpass[0][1][5] = 0
4799 11:04:37.805004 rx_firspass[0][1][6] = 0
4800 11:04:37.808769 rx_lastpass[0][1][6] = 0
4801 11:04:37.808904 rx_firspass[0][1][7] = 0
4802 11:04:37.812060 rx_lastpass[0][1][7] = 0
4803 11:04:37.815271 rx_firspass[0][1][8] = 0
4804 11:04:37.815390 rx_lastpass[0][1][8] = 0
4805 11:04:37.818391 rx_firspass[0][1][9] = 0
4806 11:04:37.821707 rx_lastpass[0][1][9] = 0
4807 11:04:37.821847 rx_firspass[0][1][10] = 0
4808 11:04:37.825360 rx_lastpass[0][1][10] = 0
4809 11:04:37.828366 rx_firspass[0][1][11] = 0
4810 11:04:37.831916 rx_lastpass[0][1][11] = 0
4811 11:04:37.832179 rx_firspass[0][1][12] = 0
4812 11:04:37.835039 rx_lastpass[0][1][12] = 0
4813 11:04:37.838535 rx_firspass[0][1][13] = 0
4814 11:04:37.838820 rx_lastpass[0][1][13] = 0
4815 11:04:37.842055 rx_firspass[0][1][14] = 0
4816 11:04:37.845490 rx_lastpass[0][1][14] = 0
4817 11:04:37.848512 rx_firspass[0][1][15] = 0
4818 11:04:37.848994 rx_lastpass[0][1][15] = 0
4819 11:04:37.852146 rx_firspass[1][0][0] = 0
4820 11:04:37.855613 rx_lastpass[1][0][0] = 0
4821 11:04:37.856006 rx_firspass[1][0][1] = 0
4822 11:04:37.858682 rx_lastpass[1][0][1] = 0
4823 11:04:37.862001 rx_firspass[1][0][2] = 0
4824 11:04:37.862444 rx_lastpass[1][0][2] = 0
4825 11:04:37.865268 rx_firspass[1][0][3] = 0
4826 11:04:37.868766 rx_lastpass[1][0][3] = 0
4827 11:04:37.869214 rx_firspass[1][0][4] = 0
4828 11:04:37.871603 rx_lastpass[1][0][4] = 0
4829 11:04:37.875338 rx_firspass[1][0][5] = 0
4830 11:04:37.878573 rx_lastpass[1][0][5] = 0
4831 11:04:37.879096 rx_firspass[1][0][6] = 0
4832 11:04:37.881690 rx_lastpass[1][0][6] = 0
4833 11:04:37.885074 rx_firspass[1][0][7] = 0
4834 11:04:37.885551 rx_lastpass[1][0][7] = 0
4835 11:04:37.888467 rx_firspass[1][0][8] = 0
4836 11:04:37.891579 rx_lastpass[1][0][8] = 0
4837 11:04:37.891653 rx_firspass[1][0][9] = 0
4838 11:04:37.894769 rx_lastpass[1][0][9] = 0
4839 11:04:37.898364 rx_firspass[1][0][10] = 0
4840 11:04:37.898439 rx_lastpass[1][0][10] = 0
4841 11:04:37.901438 rx_firspass[1][0][11] = 0
4842 11:04:37.905009 rx_lastpass[1][0][11] = 0
4843 11:04:37.908365 rx_firspass[1][0][12] = 0
4844 11:04:37.908440 rx_lastpass[1][0][12] = 0
4845 11:04:37.911777 rx_firspass[1][0][13] = 0
4846 11:04:37.914902 rx_lastpass[1][0][13] = 0
4847 11:04:37.914976 rx_firspass[1][0][14] = 0
4848 11:04:37.918587 rx_lastpass[1][0][14] = 0
4849 11:04:37.921812 rx_firspass[1][0][15] = 0
4850 11:04:37.921885 rx_lastpass[1][0][15] = 0
4851 11:04:37.925214 rx_firspass[1][1][0] = 0
4852 11:04:37.928557 rx_lastpass[1][1][0] = 0
4853 11:04:37.931685 rx_firspass[1][1][1] = 0
4854 11:04:37.931765 rx_lastpass[1][1][1] = 0
4855 11:04:37.934912 rx_firspass[1][1][2] = 0
4856 11:04:37.938724 rx_lastpass[1][1][2] = 0
4857 11:04:37.938799 rx_firspass[1][1][3] = 0
4858 11:04:37.941614 rx_lastpass[1][1][3] = 0
4859 11:04:37.945341 rx_firspass[1][1][4] = 0
4860 11:04:37.945416 rx_lastpass[1][1][4] = 0
4861 11:04:37.949028 rx_firspass[1][1][5] = 0
4862 11:04:37.951653 rx_lastpass[1][1][5] = 0
4863 11:04:37.951738 rx_firspass[1][1][6] = 0
4864 11:04:37.955211 rx_lastpass[1][1][6] = 0
4865 11:04:37.958289 rx_firspass[1][1][7] = 0
4866 11:04:37.961744 rx_lastpass[1][1][7] = 0
4867 11:04:37.961847 rx_firspass[1][1][8] = 0
4868 11:04:37.964769 rx_lastpass[1][1][8] = 0
4869 11:04:37.968159 rx_firspass[1][1][9] = 0
4870 11:04:37.968269 rx_lastpass[1][1][9] = 0
4871 11:04:37.971680 rx_firspass[1][1][10] = 0
4872 11:04:37.975019 rx_lastpass[1][1][10] = 0
4873 11:04:37.975142 rx_firspass[1][1][11] = 0
4874 11:04:37.978242 rx_lastpass[1][1][11] = 0
4875 11:04:37.981599 rx_firspass[1][1][12] = 0
4876 11:04:37.984912 rx_lastpass[1][1][12] = 0
4877 11:04:37.985067 rx_firspass[1][1][13] = 0
4878 11:04:37.988582 rx_lastpass[1][1][13] = 0
4879 11:04:37.991425 rx_firspass[1][1][14] = 0
4880 11:04:37.991646 rx_lastpass[1][1][14] = 0
4881 11:04:37.995029 rx_firspass[1][1][15] = 0
4882 11:04:37.998763 rx_lastpass[1][1][15] = 0
4883 11:04:37.999037 dump params clk_delay
4884 11:04:38.001900 clk_delay[0] = 0
4885 11:04:38.002256 clk_delay[1] = 0
4886 11:04:38.004867 dump params dqs_delay
4887 11:04:38.008431 dqs_delay[0][0] = 0
4888 11:04:38.008811 dqs_delay[0][1] = 0
4889 11:04:38.011581 dqs_delay[1][0] = 0
4890 11:04:38.011969 dqs_delay[1][1] = 0
4891 11:04:38.014970 dump params delay_cell_unit = 833
4892 11:04:38.018175 dump source = 0x0
4893 11:04:38.018738 dump params frequency:800
4894 11:04:38.021805 dump params rank number:2
4895 11:04:38.022309
4896 11:04:38.024797 dump params write leveling
4897 11:04:38.028305 write leveling[0][0][0] = 0x0
4898 11:04:38.028648 write leveling[0][0][1] = 0x0
4899 11:04:38.031797 write leveling[0][1][0] = 0x0
4900 11:04:38.034651 write leveling[0][1][1] = 0x0
4901 11:04:38.038341 write leveling[1][0][0] = 0x0
4902 11:04:38.041368 write leveling[1][0][1] = 0x0
4903 11:04:38.041779 write leveling[1][1][0] = 0x0
4904 11:04:38.044578 write leveling[1][1][1] = 0x0
4905 11:04:38.047995 dump params cbt_cs
4906 11:04:38.048512 cbt_cs[0][0] = 0x0
4907 11:04:38.051460 cbt_cs[0][1] = 0x0
4908 11:04:38.051977 cbt_cs[1][0] = 0x0
4909 11:04:38.055278 cbt_cs[1][1] = 0x0
4910 11:04:38.055763 dump params cbt_mr12
4911 11:04:38.058261 cbt_mr12[0][0] = 0x0
4912 11:04:38.061624 cbt_mr12[0][1] = 0x0
4913 11:04:38.062134 cbt_mr12[1][0] = 0x0
4914 11:04:38.064516 cbt_mr12[1][1] = 0x0
4915 11:04:38.065047 dump params tx window
4916 11:04:38.068368 tx_center_min[0][0][0] = 0
4917 11:04:38.071158 tx_center_max[0][0][0] = 0
4918 11:04:38.074427 tx_center_min[0][0][1] = 0
4919 11:04:38.074921 tx_center_max[0][0][1] = 0
4920 11:04:38.078192 tx_center_min[0][1][0] = 0
4921 11:04:38.081164 tx_center_max[0][1][0] = 0
4922 11:04:38.081659 tx_center_min[0][1][1] = 0
4923 11:04:38.084935 tx_center_max[0][1][1] = 0
4924 11:04:38.087782 tx_center_min[1][0][0] = 0
4925 11:04:38.090963 tx_center_max[1][0][0] = 0
4926 11:04:38.091451 tx_center_min[1][0][1] = 0
4927 11:04:38.094505 tx_center_max[1][0][1] = 0
4928 11:04:38.097895 tx_center_min[1][1][0] = 0
4929 11:04:38.101365 tx_center_max[1][1][0] = 0
4930 11:04:38.101751 tx_center_min[1][1][1] = 0
4931 11:04:38.104698 tx_center_max[1][1][1] = 0
4932 11:04:38.107751 dump params tx window
4933 11:04:38.108133 tx_win_center[0][0][0] = 0
4934 11:04:38.111360 tx_first_pass[0][0][0] = 0
4935 11:04:38.115170 tx_last_pass[0][0][0] = 0
4936 11:04:38.117982 tx_win_center[0][0][1] = 0
4937 11:04:38.118494 tx_first_pass[0][0][1] = 0
4938 11:04:38.121465 tx_last_pass[0][0][1] = 0
4939 11:04:38.124648 tx_win_center[0][0][2] = 0
4940 11:04:38.127693 tx_first_pass[0][0][2] = 0
4941 11:04:38.128187 tx_last_pass[0][0][2] = 0
4942 11:04:38.131904 tx_win_center[0][0][3] = 0
4943 11:04:38.134727 tx_first_pass[0][0][3] = 0
4944 11:04:38.135211 tx_last_pass[0][0][3] = 0
4945 11:04:38.137924 tx_win_center[0][0][4] = 0
4946 11:04:38.141383 tx_first_pass[0][0][4] = 0
4947 11:04:38.144462 tx_last_pass[0][0][4] = 0
4948 11:04:38.144910 tx_win_center[0][0][5] = 0
4949 11:04:38.148277 tx_first_pass[0][0][5] = 0
4950 11:04:38.151168 tx_last_pass[0][0][5] = 0
4951 11:04:38.151554 tx_win_center[0][0][6] = 0
4952 11:04:38.155164 tx_first_pass[0][0][6] = 0
4953 11:04:38.157766 tx_last_pass[0][0][6] = 0
4954 11:04:38.161218 tx_win_center[0][0][7] = 0
4955 11:04:38.161605 tx_first_pass[0][0][7] = 0
4956 11:04:38.164716 tx_last_pass[0][0][7] = 0
4957 11:04:38.168106 tx_win_center[0][0][8] = 0
4958 11:04:38.171528 tx_first_pass[0][0][8] = 0
4959 11:04:38.172029 tx_last_pass[0][0][8] = 0
4960 11:04:38.174348 tx_win_center[0][0][9] = 0
4961 11:04:38.178140 tx_first_pass[0][0][9] = 0
4962 11:04:38.178648 tx_last_pass[0][0][9] = 0
4963 11:04:38.180928 tx_win_center[0][0][10] = 0
4964 11:04:38.184192 tx_first_pass[0][0][10] = 0
4965 11:04:38.187606 tx_last_pass[0][0][10] = 0
4966 11:04:38.188130 tx_win_center[0][0][11] = 0
4967 11:04:38.191030 tx_first_pass[0][0][11] = 0
4968 11:04:38.194399 tx_last_pass[0][0][11] = 0
4969 11:04:38.197563 tx_win_center[0][0][12] = 0
4970 11:04:38.200859 tx_first_pass[0][0][12] = 0
4971 11:04:38.201401 tx_last_pass[0][0][12] = 0
4972 11:04:38.204607 tx_win_center[0][0][13] = 0
4973 11:04:38.207626 tx_first_pass[0][0][13] = 0
4974 11:04:38.208008 tx_last_pass[0][0][13] = 0
4975 11:04:38.211050 tx_win_center[0][0][14] = 0
4976 11:04:38.214092 tx_first_pass[0][0][14] = 0
4977 11:04:38.217548 tx_last_pass[0][0][14] = 0
4978 11:04:38.220683 tx_win_center[0][0][15] = 0
4979 11:04:38.221066 tx_first_pass[0][0][15] = 0
4980 11:04:38.224088 tx_last_pass[0][0][15] = 0
4981 11:04:38.227778 tx_win_center[0][1][0] = 0
4982 11:04:38.228162 tx_first_pass[0][1][0] = 0
4983 11:04:38.231117 tx_last_pass[0][1][0] = 0
4984 11:04:38.234188 tx_win_center[0][1][1] = 0
4985 11:04:38.238059 tx_first_pass[0][1][1] = 0
4986 11:04:38.238464 tx_last_pass[0][1][1] = 0
4987 11:04:38.240648 tx_win_center[0][1][2] = 0
4988 11:04:38.244227 tx_first_pass[0][1][2] = 0
4989 11:04:38.247248 tx_last_pass[0][1][2] = 0
4990 11:04:38.247653 tx_win_center[0][1][3] = 0
4991 11:04:38.250918 tx_first_pass[0][1][3] = 0
4992 11:04:38.254079 tx_last_pass[0][1][3] = 0
4993 11:04:38.254492 tx_win_center[0][1][4] = 0
4994 11:04:38.257423 tx_first_pass[0][1][4] = 0
4995 11:04:38.260630 tx_last_pass[0][1][4] = 0
4996 11:04:38.263739 tx_win_center[0][1][5] = 0
4997 11:04:38.264011 tx_first_pass[0][1][5] = 0
4998 11:04:38.266931 tx_last_pass[0][1][5] = 0
4999 11:04:38.270871 tx_win_center[0][1][6] = 0
5000 11:04:38.273774 tx_first_pass[0][1][6] = 0
5001 11:04:38.273940 tx_last_pass[0][1][6] = 0
5002 11:04:38.276814 tx_win_center[0][1][7] = 0
5003 11:04:38.280313 tx_first_pass[0][1][7] = 0
5004 11:04:38.283777 tx_last_pass[0][1][7] = 0
5005 11:04:38.283915 tx_win_center[0][1][8] = 0
5006 11:04:38.286986 tx_first_pass[0][1][8] = 0
5007 11:04:38.289911 tx_last_pass[0][1][8] = 0
5008 11:04:38.290049 tx_win_center[0][1][9] = 0
5009 11:04:38.293942 tx_first_pass[0][1][9] = 0
5010 11:04:38.296940 tx_last_pass[0][1][9] = 0
5011 11:04:38.301993 tx_win_center[0][1][10] = 0
5012 11:04:38.302131 tx_first_pass[0][1][10] = 0
5013 11:04:38.303451 tx_last_pass[0][1][10] = 0
5014 11:04:38.306658 tx_win_center[0][1][11] = 0
5015 11:04:38.310023 tx_first_pass[0][1][11] = 0
5016 11:04:38.310182 tx_last_pass[0][1][11] = 0
5017 11:04:38.313266 tx_win_center[0][1][12] = 0
5018 11:04:38.316707 tx_first_pass[0][1][12] = 0
5019 11:04:38.320028 tx_last_pass[0][1][12] = 0
5020 11:04:38.320314 tx_win_center[0][1][13] = 0
5021 11:04:38.323442 tx_first_pass[0][1][13] = 0
5022 11:04:38.326568 tx_last_pass[0][1][13] = 0
5023 11:04:38.330433 tx_win_center[0][1][14] = 0
5024 11:04:38.330786 tx_first_pass[0][1][14] = 0
5025 11:04:38.333749 tx_last_pass[0][1][14] = 0
5026 11:04:38.337051 tx_win_center[0][1][15] = 0
5027 11:04:38.340216 tx_first_pass[0][1][15] = 0
5028 11:04:38.340602 tx_last_pass[0][1][15] = 0
5029 11:04:38.343483 tx_win_center[1][0][0] = 0
5030 11:04:38.347200 tx_first_pass[1][0][0] = 0
5031 11:04:38.350233 tx_last_pass[1][0][0] = 0
5032 11:04:38.350617 tx_win_center[1][0][1] = 0
5033 11:04:38.353543 tx_first_pass[1][0][1] = 0
5034 11:04:38.356777 tx_last_pass[1][0][1] = 0
5035 11:04:38.360568 tx_win_center[1][0][2] = 0
5036 11:04:38.361147 tx_first_pass[1][0][2] = 0
5037 11:04:38.363751 tx_last_pass[1][0][2] = 0
5038 11:04:38.366990 tx_win_center[1][0][3] = 0
5039 11:04:38.367373 tx_first_pass[1][0][3] = 0
5040 11:04:38.370072 tx_last_pass[1][0][3] = 0
5041 11:04:38.373319 tx_win_center[1][0][4] = 0
5042 11:04:38.376472 tx_first_pass[1][0][4] = 0
5043 11:04:38.376856 tx_last_pass[1][0][4] = 0
5044 11:04:38.380164 tx_win_center[1][0][5] = 0
5045 11:04:38.383807 tx_first_pass[1][0][5] = 0
5046 11:04:38.386781 tx_last_pass[1][0][5] = 0
5047 11:04:38.387164 tx_win_center[1][0][6] = 0
5048 11:04:38.390254 tx_first_pass[1][0][6] = 0
5049 11:04:38.393025 tx_last_pass[1][0][6] = 0
5050 11:04:38.393456 tx_win_center[1][0][7] = 0
5051 11:04:38.396536 tx_first_pass[1][0][7] = 0
5052 11:04:38.399823 tx_last_pass[1][0][7] = 0
5053 11:04:38.403212 tx_win_center[1][0][8] = 0
5054 11:04:38.403599 tx_first_pass[1][0][8] = 0
5055 11:04:38.406622 tx_last_pass[1][0][8] = 0
5056 11:04:38.409611 tx_win_center[1][0][9] = 0
5057 11:04:38.413529 tx_first_pass[1][0][9] = 0
5058 11:04:38.413941 tx_last_pass[1][0][9] = 0
5059 11:04:38.417152 tx_win_center[1][0][10] = 0
5060 11:04:38.419996 tx_first_pass[1][0][10] = 0
5061 11:04:38.420382 tx_last_pass[1][0][10] = 0
5062 11:04:38.423674 tx_win_center[1][0][11] = 0
5063 11:04:38.427036 tx_first_pass[1][0][11] = 0
5064 11:04:38.429916 tx_last_pass[1][0][11] = 0
5065 11:04:38.430403 tx_win_center[1][0][12] = 0
5066 11:04:38.433354 tx_first_pass[1][0][12] = 0
5067 11:04:38.436472 tx_last_pass[1][0][12] = 0
5068 11:04:38.439918 tx_win_center[1][0][13] = 0
5069 11:04:38.443350 tx_first_pass[1][0][13] = 0
5070 11:04:38.443748 tx_last_pass[1][0][13] = 0
5071 11:04:38.446549 tx_win_center[1][0][14] = 0
5072 11:04:38.449748 tx_first_pass[1][0][14] = 0
5073 11:04:38.450141 tx_last_pass[1][0][14] = 0
5074 11:04:38.453204 tx_win_center[1][0][15] = 0
5075 11:04:38.456723 tx_first_pass[1][0][15] = 0
5076 11:04:38.459838 tx_last_pass[1][0][15] = 0
5077 11:04:38.460238 tx_win_center[1][1][0] = 0
5078 11:04:38.463208 tx_first_pass[1][1][0] = 0
5079 11:04:38.466394 tx_last_pass[1][1][0] = 0
5080 11:04:38.469781 tx_win_center[1][1][1] = 0
5081 11:04:38.470167 tx_first_pass[1][1][1] = 0
5082 11:04:38.473171 tx_last_pass[1][1][1] = 0
5083 11:04:38.476110 tx_win_center[1][1][2] = 0
5084 11:04:38.479963 tx_first_pass[1][1][2] = 0
5085 11:04:38.480393 tx_last_pass[1][1][2] = 0
5086 11:04:38.483217 tx_win_center[1][1][3] = 0
5087 11:04:38.486452 tx_first_pass[1][1][3] = 0
5088 11:04:38.486837 tx_last_pass[1][1][3] = 0
5089 11:04:38.489650 tx_win_center[1][1][4] = 0
5090 11:04:38.493079 tx_first_pass[1][1][4] = 0
5091 11:04:38.496020 tx_last_pass[1][1][4] = 0
5092 11:04:38.496414 tx_win_center[1][1][5] = 0
5093 11:04:38.499712 tx_first_pass[1][1][5] = 0
5094 11:04:38.502972 tx_last_pass[1][1][5] = 0
5095 11:04:38.506502 tx_win_center[1][1][6] = 0
5096 11:04:38.506894 tx_first_pass[1][1][6] = 0
5097 11:04:38.509794 tx_last_pass[1][1][6] = 0
5098 11:04:38.513184 tx_win_center[1][1][7] = 0
5099 11:04:38.513574 tx_first_pass[1][1][7] = 0
5100 11:04:38.516512 tx_last_pass[1][1][7] = 0
5101 11:04:38.519651 tx_win_center[1][1][8] = 0
5102 11:04:38.522918 tx_first_pass[1][1][8] = 0
5103 11:04:38.523302 tx_last_pass[1][1][8] = 0
5104 11:04:38.526051 tx_win_center[1][1][9] = 0
5105 11:04:38.529584 tx_first_pass[1][1][9] = 0
5106 11:04:38.533255 tx_last_pass[1][1][9] = 0
5107 11:04:38.533664 tx_win_center[1][1][10] = 0
5108 11:04:38.536852 tx_first_pass[1][1][10] = 0
5109 11:04:38.539675 tx_last_pass[1][1][10] = 0
5110 11:04:38.543991 tx_win_center[1][1][11] = 0
5111 11:04:38.544396 tx_first_pass[1][1][11] = 0
5112 11:04:38.546153 tx_last_pass[1][1][11] = 0
5113 11:04:38.550443 tx_win_center[1][1][12] = 0
5114 11:04:38.552713 tx_first_pass[1][1][12] = 0
5115 11:04:38.553303 tx_last_pass[1][1][12] = 0
5116 11:04:38.556024 tx_win_center[1][1][13] = 0
5117 11:04:38.559497 tx_first_pass[1][1][13] = 0
5118 11:04:38.562851 tx_last_pass[1][1][13] = 0
5119 11:04:38.563392 tx_win_center[1][1][14] = 0
5120 11:04:38.565933 tx_first_pass[1][1][14] = 0
5121 11:04:38.569307 tx_last_pass[1][1][14] = 0
5122 11:04:38.572513 tx_win_center[1][1][15] = 0
5123 11:04:38.572925 tx_first_pass[1][1][15] = 0
5124 11:04:38.576620 tx_last_pass[1][1][15] = 0
5125 11:04:38.579552 dump params rx window
5126 11:04:38.579937 rx_firspass[0][0][0] = 0
5127 11:04:38.582839 rx_lastpass[0][0][0] = 0
5128 11:04:38.585972 rx_firspass[0][0][1] = 0
5129 11:04:38.586530 rx_lastpass[0][0][1] = 0
5130 11:04:38.589253 rx_firspass[0][0][2] = 0
5131 11:04:38.592940 rx_lastpass[0][0][2] = 0
5132 11:04:38.595913 rx_firspass[0][0][3] = 0
5133 11:04:38.596440 rx_lastpass[0][0][3] = 0
5134 11:04:38.599359 rx_firspass[0][0][4] = 0
5135 11:04:38.602615 rx_lastpass[0][0][4] = 0
5136 11:04:38.603000 rx_firspass[0][0][5] = 0
5137 11:04:38.605994 rx_lastpass[0][0][5] = 0
5138 11:04:38.609155 rx_firspass[0][0][6] = 0
5139 11:04:38.609550 rx_lastpass[0][0][6] = 0
5140 11:04:38.612410 rx_firspass[0][0][7] = 0
5141 11:04:38.615439 rx_lastpass[0][0][7] = 0
5142 11:04:38.615910 rx_firspass[0][0][8] = 0
5143 11:04:38.619095 rx_lastpass[0][0][8] = 0
5144 11:04:38.622259 rx_firspass[0][0][9] = 0
5145 11:04:38.622696 rx_lastpass[0][0][9] = 0
5146 11:04:38.625726 rx_firspass[0][0][10] = 0
5147 11:04:38.628809 rx_lastpass[0][0][10] = 0
5148 11:04:38.632275 rx_firspass[0][0][11] = 0
5149 11:04:38.632664 rx_lastpass[0][0][11] = 0
5150 11:04:38.635747 rx_firspass[0][0][12] = 0
5151 11:04:38.638626 rx_lastpass[0][0][12] = 0
5152 11:04:38.639016 rx_firspass[0][0][13] = 0
5153 11:04:38.642396 rx_lastpass[0][0][13] = 0
5154 11:04:38.645577 rx_firspass[0][0][14] = 0
5155 11:04:38.649036 rx_lastpass[0][0][14] = 0
5156 11:04:38.649489 rx_firspass[0][0][15] = 0
5157 11:04:38.652637 rx_lastpass[0][0][15] = 0
5158 11:04:38.655651 rx_firspass[0][1][0] = 0
5159 11:04:38.656036 rx_lastpass[0][1][0] = 0
5160 11:04:38.660076 rx_firspass[0][1][1] = 0
5161 11:04:38.662351 rx_lastpass[0][1][1] = 0
5162 11:04:38.665305 rx_firspass[0][1][2] = 0
5163 11:04:38.665702 rx_lastpass[0][1][2] = 0
5164 11:04:38.669670 rx_firspass[0][1][3] = 0
5165 11:04:38.672229 rx_lastpass[0][1][3] = 0
5166 11:04:38.672616 rx_firspass[0][1][4] = 0
5167 11:04:38.675517 rx_lastpass[0][1][4] = 0
5168 11:04:38.679075 rx_firspass[0][1][5] = 0
5169 11:04:38.679463 rx_lastpass[0][1][5] = 0
5170 11:04:38.682065 rx_firspass[0][1][6] = 0
5171 11:04:38.685978 rx_lastpass[0][1][6] = 0
5172 11:04:38.686365 rx_firspass[0][1][7] = 0
5173 11:04:38.689269 rx_lastpass[0][1][7] = 0
5174 11:04:38.691941 rx_firspass[0][1][8] = 0
5175 11:04:38.692330 rx_lastpass[0][1][8] = 0
5176 11:04:38.695150 rx_firspass[0][1][9] = 0
5177 11:04:38.698583 rx_lastpass[0][1][9] = 0
5178 11:04:38.701878 rx_firspass[0][1][10] = 0
5179 11:04:38.702314 rx_lastpass[0][1][10] = 0
5180 11:04:38.705466 rx_firspass[0][1][11] = 0
5181 11:04:38.708590 rx_lastpass[0][1][11] = 0
5182 11:04:38.708976 rx_firspass[0][1][12] = 0
5183 11:04:38.712072 rx_lastpass[0][1][12] = 0
5184 11:04:38.715253 rx_firspass[0][1][13] = 0
5185 11:04:38.718562 rx_lastpass[0][1][13] = 0
5186 11:04:38.718947 rx_firspass[0][1][14] = 0
5187 11:04:38.721936 rx_lastpass[0][1][14] = 0
5188 11:04:38.725416 rx_firspass[0][1][15] = 0
5189 11:04:38.725805 rx_lastpass[0][1][15] = 0
5190 11:04:38.728557 rx_firspass[1][0][0] = 0
5191 11:04:38.731922 rx_lastpass[1][0][0] = 0
5192 11:04:38.732309 rx_firspass[1][0][1] = 0
5193 11:04:38.735301 rx_lastpass[1][0][1] = 0
5194 11:04:38.738562 rx_firspass[1][0][2] = 0
5195 11:04:38.738952 rx_lastpass[1][0][2] = 0
5196 11:04:38.742109 rx_firspass[1][0][3] = 0
5197 11:04:38.745560 rx_lastpass[1][0][3] = 0
5198 11:04:38.748713 rx_firspass[1][0][4] = 0
5199 11:04:38.749096 rx_lastpass[1][0][4] = 0
5200 11:04:38.752470 rx_firspass[1][0][5] = 0
5201 11:04:38.755247 rx_lastpass[1][0][5] = 0
5202 11:04:38.755635 rx_firspass[1][0][6] = 0
5203 11:04:38.758352 rx_lastpass[1][0][6] = 0
5204 11:04:38.762418 rx_firspass[1][0][7] = 0
5205 11:04:38.762802 rx_lastpass[1][0][7] = 0
5206 11:04:38.765081 rx_firspass[1][0][8] = 0
5207 11:04:38.768520 rx_lastpass[1][0][8] = 0
5208 11:04:38.768907 rx_firspass[1][0][9] = 0
5209 11:04:38.772315 rx_lastpass[1][0][9] = 0
5210 11:04:38.775543 rx_firspass[1][0][10] = 0
5211 11:04:38.778689 rx_lastpass[1][0][10] = 0
5212 11:04:38.779078 rx_firspass[1][0][11] = 0
5213 11:04:38.782472 rx_lastpass[1][0][11] = 0
5214 11:04:38.785059 rx_firspass[1][0][12] = 0
5215 11:04:38.785509 rx_lastpass[1][0][12] = 0
5216 11:04:38.788746 rx_firspass[1][0][13] = 0
5217 11:04:38.792026 rx_lastpass[1][0][13] = 0
5218 11:04:38.792450 rx_firspass[1][0][14] = 0
5219 11:04:38.795132 rx_lastpass[1][0][14] = 0
5220 11:04:38.798925 rx_firspass[1][0][15] = 0
5221 11:04:38.801864 rx_lastpass[1][0][15] = 0
5222 11:04:38.802251 rx_firspass[1][1][0] = 0
5223 11:04:38.805317 rx_lastpass[1][1][0] = 0
5224 11:04:38.808365 rx_firspass[1][1][1] = 0
5225 11:04:38.808755 rx_lastpass[1][1][1] = 0
5226 11:04:38.811651 rx_firspass[1][1][2] = 0
5227 11:04:38.815110 rx_lastpass[1][1][2] = 0
5228 11:04:38.815587 rx_firspass[1][1][3] = 0
5229 11:04:38.818383 rx_lastpass[1][1][3] = 0
5230 11:04:38.821560 rx_firspass[1][1][4] = 0
5231 11:04:38.824977 rx_lastpass[1][1][4] = 0
5232 11:04:38.825411 rx_firspass[1][1][5] = 0
5233 11:04:38.828135 rx_lastpass[1][1][5] = 0
5234 11:04:38.831536 rx_firspass[1][1][6] = 0
5235 11:04:38.831991 rx_lastpass[1][1][6] = 0
5236 11:04:38.834851 rx_firspass[1][1][7] = 0
5237 11:04:38.838030 rx_lastpass[1][1][7] = 0
5238 11:04:38.838420 rx_firspass[1][1][8] = 0
5239 11:04:38.841503 rx_lastpass[1][1][8] = 0
5240 11:04:38.844536 rx_firspass[1][1][9] = 0
5241 11:04:38.845009 rx_lastpass[1][1][9] = 0
5242 11:04:38.848051 rx_firspass[1][1][10] = 0
5243 11:04:38.851853 rx_lastpass[1][1][10] = 0
5244 11:04:38.855220 rx_firspass[1][1][11] = 0
5245 11:04:38.855662 rx_lastpass[1][1][11] = 0
5246 11:04:38.858410 rx_firspass[1][1][12] = 0
5247 11:04:38.861739 rx_lastpass[1][1][12] = 0
5248 11:04:38.862126 rx_firspass[1][1][13] = 0
5249 11:04:38.865029 rx_lastpass[1][1][13] = 0
5250 11:04:38.868287 rx_firspass[1][1][14] = 0
5251 11:04:38.871876 rx_lastpass[1][1][14] = 0
5252 11:04:38.872264 rx_firspass[1][1][15] = 0
5253 11:04:38.874615 rx_lastpass[1][1][15] = 0
5254 11:04:38.878203 dump params clk_delay
5255 11:04:38.878593 clk_delay[0] = 0
5256 11:04:38.878892 clk_delay[1] = 0
5257 11:04:38.881661 dump params dqs_delay
5258 11:04:38.884487 dqs_delay[0][0] = 0
5259 11:04:38.884873 dqs_delay[0][1] = 0
5260 11:04:38.887970 dqs_delay[1][0] = 0
5261 11:04:38.888355 dqs_delay[1][1] = 0
5262 11:04:38.891666 dump params delay_cell_unit = 833
5263 11:04:38.895162 mt_set_emi_preloader end
5264 11:04:38.898385 [mt_mem_init] dram size: 0x100000000, rank number: 2
5265 11:04:38.904900 [complex_mem_test] start addr:0x40000000, len:20480
5266 11:04:38.940359 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5267 11:04:38.946693 [complex_mem_test] start addr:0x80000000, len:20480
5268 11:04:38.982797 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5269 11:04:38.988959 [complex_mem_test] start addr:0xc0000000, len:20480
5270 11:04:39.025223 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5271 11:04:39.032202 [complex_mem_test] start addr:0x56000000, len:8192
5272 11:04:39.048006 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5273 11:04:39.048400 ddr_geometry:1
5274 11:04:39.054553 [complex_mem_test] start addr:0x80000000, len:8192
5275 11:04:39.072183 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5276 11:04:39.075440 dram_init: dram init end (result: 0)
5277 11:04:39.081923 Successfully loaded DRAM blobs and ran DRAM calibration
5278 11:04:39.092107 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5279 11:04:39.092508 CBMEM:
5280 11:04:39.095170 IMD: root @ 00000000fffff000 254 entries.
5281 11:04:39.098308 IMD: root @ 00000000ffffec00 62 entries.
5282 11:04:39.105236 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5283 11:04:39.111875 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5284 11:04:39.115336 in-header: 03 a1 00 00 08 00 00 00
5285 11:04:39.118386 in-data: 84 60 60 10 00 00 00 00
5286 11:04:39.121662 Chrome EC: clear events_b mask to 0x0000000020004000
5287 11:04:39.129061 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5288 11:04:39.132129 in-header: 03 fd 00 00 00 00 00 00
5289 11:04:39.132514 in-data:
5290 11:04:39.139152 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5291 11:04:39.139570 CBFS @ 21000 size 3d4000
5292 11:04:39.145784 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5293 11:04:39.148755 CBFS: Locating 'fallback/ramstage'
5294 11:04:39.152098 CBFS: Found @ offset 10d40 size d563
5295 11:04:39.174354 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5296 11:04:39.186127 Accumulated console time in romstage 13760 ms
5297 11:04:39.186515
5298 11:04:39.186812
5299 11:04:39.195998 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5300 11:04:39.199119 ARM64: Exception handlers installed.
5301 11:04:39.199525 ARM64: Testing exception
5302 11:04:39.202180 ARM64: Done test exception
5303 11:04:39.205795 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5304 11:04:39.209513 Manufacturer: ef
5305 11:04:39.212583 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5306 11:04:39.219194 WARNING: RO_VPD is uninitialized or empty.
5307 11:04:39.222419 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5308 11:04:39.225729 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5309 11:04:39.235833 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5310 11:04:39.239274 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5311 11:04:39.245584 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5312 11:04:39.246133 Enumerating buses...
5313 11:04:39.252380 Show all devs... Before device enumeration.
5314 11:04:39.252899 Root Device: enabled 1
5315 11:04:39.255471 CPU_CLUSTER: 0: enabled 1
5316 11:04:39.255976 CPU: 00: enabled 1
5317 11:04:39.259332 Compare with tree...
5318 11:04:39.262428 Root Device: enabled 1
5319 11:04:39.262815 CPU_CLUSTER: 0: enabled 1
5320 11:04:39.265695 CPU: 00: enabled 1
5321 11:04:39.269404 Root Device scanning...
5322 11:04:39.269902 root_dev_scan_bus for Root Device
5323 11:04:39.271989 CPU_CLUSTER: 0 enabled
5324 11:04:39.275201 root_dev_scan_bus for Root Device done
5325 11:04:39.282092 scan_bus: scanning of bus Root Device took 10689 usecs
5326 11:04:39.282618 done
5327 11:04:39.285531 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5328 11:04:39.288632 Allocating resources...
5329 11:04:39.289017 Reading resources...
5330 11:04:39.292266 Root Device read_resources bus 0 link: 0
5331 11:04:39.298744 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5332 11:04:39.299136 CPU: 00 missing read_resources
5333 11:04:39.305566 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5334 11:04:39.308794 Root Device read_resources bus 0 link: 0 done
5335 11:04:39.312442 Done reading resources.
5336 11:04:39.315269 Show resources in subtree (Root Device)...After reading.
5337 11:04:39.318624 Root Device child on link 0 CPU_CLUSTER: 0
5338 11:04:39.321923 CPU_CLUSTER: 0 child on link 0 CPU: 00
5339 11:04:39.332142 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5340 11:04:39.332584 CPU: 00
5341 11:04:39.335670 Setting resources...
5342 11:04:39.338839 Root Device assign_resources, bus 0 link: 0
5343 11:04:39.341706 CPU_CLUSTER: 0 missing set_resources
5344 11:04:39.345302 Root Device assign_resources, bus 0 link: 0
5345 11:04:39.348920 Done setting resources.
5346 11:04:39.355371 Show resources in subtree (Root Device)...After assigning values.
5347 11:04:39.358829 Root Device child on link 0 CPU_CLUSTER: 0
5348 11:04:39.361907 CPU_CLUSTER: 0 child on link 0 CPU: 00
5349 11:04:39.372356 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5350 11:04:39.372739 CPU: 00
5351 11:04:39.375435 Done allocating resources.
5352 11:04:39.378917 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5353 11:04:39.381745 Enabling resources...
5354 11:04:39.382126 done.
5355 11:04:39.385210 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5356 11:04:39.388725 Initializing devices...
5357 11:04:39.389102 Root Device init ...
5358 11:04:39.392240 mainboard_init: Starting display init.
5359 11:04:39.395132 ADC[4]: Raw value=75944 ID=0
5360 11:04:39.418639 anx7625_power_on_init: Init interface.
5361 11:04:39.422410 anx7625_disable_pd_protocol: Disabled PD feature.
5362 11:04:39.428305 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5363 11:04:39.485223 anx7625_start_dp_work: Secure OCM version=00
5364 11:04:39.488504 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5365 11:04:39.506104 sp_tx_get_edid_block: EDID Block = 1
5366 11:04:39.623409 Extracted contents:
5367 11:04:39.626201 header: 00 ff ff ff ff ff ff 00
5368 11:04:39.629728 serial number: 06 af 5c 14 00 00 00 00 00 1a
5369 11:04:39.633209 version: 01 04
5370 11:04:39.636243 basic params: 95 1a 0e 78 02
5371 11:04:39.639943 chroma info: 99 85 95 55 56 92 28 22 50 54
5372 11:04:39.642964 established: 00 00 00
5373 11:04:39.649348 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5374 11:04:39.653044 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5375 11:04:39.659850 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5376 11:04:39.666238 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5377 11:04:39.672382 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5378 11:04:39.676027 extensions: 00
5379 11:04:39.676409 checksum: ae
5380 11:04:39.676704
5381 11:04:39.679285 Manufacturer: AUO Model 145c Serial Number 0
5382 11:04:39.682746 Made week 0 of 2016
5383 11:04:39.683156 EDID version: 1.4
5384 11:04:39.686323 Digital display
5385 11:04:39.689013 6 bits per primary color channel
5386 11:04:39.689470 DisplayPort interface
5387 11:04:39.692424 Maximum image size: 26 cm x 14 cm
5388 11:04:39.695748 Gamma: 220%
5389 11:04:39.696128 Check DPMS levels
5390 11:04:39.699188 Supported color formats: RGB 4:4:4
5391 11:04:39.702314 First detailed timing is preferred timing
5392 11:04:39.705949 Established timings supported:
5393 11:04:39.709316 Standard timings supported:
5394 11:04:39.709840 Detailed timings
5395 11:04:39.715838 Hex of detail: ce1d56ea50001a3030204600009010000018
5396 11:04:39.718884 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5397 11:04:39.722339 0556 0586 05a6 0640 hborder 0
5398 11:04:39.729020 0300 0304 030a 031a vborder 0
5399 11:04:39.729481 -hsync -vsync
5400 11:04:39.732168 Did detailed timing
5401 11:04:39.735925 Hex of detail: 0000000f0000000000000000000000000020
5402 11:04:39.738755 Manufacturer-specified data, tag 15
5403 11:04:39.745650 Hex of detail: 000000fe0041554f0a202020202020202020
5404 11:04:39.746113 ASCII string: AUO
5405 11:04:39.748881 Hex of detail: 000000fe004231313658414230312e34200a
5406 11:04:39.752253 ASCII string: B116XAB01.4
5407 11:04:39.752632 Checksum
5408 11:04:39.755363 Checksum: 0xae (valid)
5409 11:04:39.762517 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5410 11:04:39.765459 DSI data_rate: 457800000 bps
5411 11:04:39.769274 anx7625_parse_edid: set default k value to 0x3d for panel
5412 11:04:39.772228 anx7625_parse_edid: pixelclock(76300).
5413 11:04:39.778540 hactive(1366), hsync(32), hfp(48), hbp(154)
5414 11:04:39.782125 vactive(768), vsync(6), vfp(4), vbp(16)
5415 11:04:39.785408 anx7625_dsi_config: config dsi.
5416 11:04:39.792078 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5417 11:04:39.812299 anx7625_dsi_config: success to config DSI
5418 11:04:39.815828 anx7625_dp_start: MIPI phy setup OK.
5419 11:04:39.818810 [SSUSB] Setting up USB HOST controller...
5420 11:04:39.822227 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5421 11:04:39.826003 [SSUSB] phy power-on done.
5422 11:04:39.829559 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5423 11:04:39.832763 in-header: 03 fc 01 00 00 00 00 00
5424 11:04:39.833306 in-data:
5425 11:04:39.839374 handle_proto3_response: EC response with error code: 1
5426 11:04:39.839769 SPM: pcm index = 1
5427 11:04:39.843176 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5428 11:04:39.845867 CBFS @ 21000 size 3d4000
5429 11:04:39.852818 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5430 11:04:39.856130 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5431 11:04:39.859509 CBFS: Found @ offset 1e7c0 size 1026
5432 11:04:39.865822 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5433 11:04:39.869292 SPM: binary array size = 2988
5434 11:04:39.872244 SPM: version = pcm_allinone_v1.17.2_20180829
5435 11:04:39.875371 SPM binary loaded in 32 msecs
5436 11:04:39.883792 spm_kick_im_to_fetch: ptr = 000000004021eec2
5437 11:04:39.886857 spm_kick_im_to_fetch: len = 2988
5438 11:04:39.887314 SPM: spm_kick_pcm_to_run
5439 11:04:39.890597 SPM: spm_kick_pcm_to_run done
5440 11:04:39.893656 SPM: spm_init done in 52 msecs
5441 11:04:39.896920 Root Device init finished in 505264 usecs
5442 11:04:39.900161 CPU_CLUSTER: 0 init ...
5443 11:04:39.909788 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5444 11:04:39.913093 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5445 11:04:39.916704 CBFS @ 21000 size 3d4000
5446 11:04:39.920079 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5447 11:04:39.922983 CBFS: Locating 'sspm.bin'
5448 11:04:39.926838 CBFS: Found @ offset 208c0 size 41cb
5449 11:04:39.937005 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5450 11:04:39.944439 CPU_CLUSTER: 0 init finished in 42803 usecs
5451 11:04:39.944898 Devices initialized
5452 11:04:39.947902 Show all devs... After init.
5453 11:04:39.951666 Root Device: enabled 1
5454 11:04:39.952057 CPU_CLUSTER: 0: enabled 1
5455 11:04:39.954584 CPU: 00: enabled 1
5456 11:04:39.957949 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5457 11:04:39.961309 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5458 11:04:39.965355 ELOG: NV offset 0x558000 size 0x1000
5459 11:04:39.971864 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5460 11:04:39.978946 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5461 11:04:39.982175 ELOG: Event(17) added with size 13 at 2024-07-10 11:04:39 UTC
5462 11:04:39.985698 out: cmd=0x121: 03 db 21 01 00 00 00 00
5463 11:04:39.989111 in-header: 03 f9 00 00 2c 00 00 00
5464 11:04:40.002064 in-data: b8 4d 00 00 00 00 00 00 02 10 00 00 06 80 00 00 70 83 02 00 06 80 00 00 55 87 02 00 06 80 00 00 64 d9 01 00 06 80 00 00 5b de 5f 00
5465 11:04:40.005271 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5466 11:04:40.009500 in-header: 03 19 00 00 08 00 00 00
5467 11:04:40.011994 in-data: a2 e0 47 00 13 00 00 00
5468 11:04:40.015443 Chrome EC: UHEPI supported
5469 11:04:40.022256 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5470 11:04:40.025216 in-header: 03 e1 00 00 08 00 00 00
5471 11:04:40.028772 in-data: 84 20 60 10 00 00 00 00
5472 11:04:40.031952 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5473 11:04:40.038341 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5474 11:04:40.041936 in-header: 03 e1 00 00 08 00 00 00
5475 11:04:40.044765 in-data: 84 20 60 10 00 00 00 00
5476 11:04:40.051588 ELOG: Event(A1) added with size 10 at 2024-07-10 11:04:39 UTC
5477 11:04:40.058220 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5478 11:04:40.061912 ELOG: Event(A0) added with size 9 at 2024-07-10 11:04:39 UTC
5479 11:04:40.068373 elog_add_boot_reason: Logged dev mode boot
5480 11:04:40.068763 Finalize devices...
5481 11:04:40.071438 Devices finalized
5482 11:04:40.075166 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5483 11:04:40.081881 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5484 11:04:40.084898 ELOG: Event(91) added with size 10 at 2024-07-10 11:04:39 UTC
5485 11:04:40.088190 Writing coreboot table at 0xffeda000
5486 11:04:40.091310 0. 0000000000114000-000000000011efff: RAMSTAGE
5487 11:04:40.097874 1. 0000000040000000-000000004023cfff: RAMSTAGE
5488 11:04:40.101759 2. 000000004023d000-00000000545fffff: RAM
5489 11:04:40.104925 3. 0000000054600000-000000005465ffff: BL31
5490 11:04:40.108483 4. 0000000054660000-00000000ffed9fff: RAM
5491 11:04:40.114546 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5492 11:04:40.117765 6. 0000000100000000-000000013fffffff: RAM
5493 11:04:40.121161 Passing 5 GPIOs to payload:
5494 11:04:40.124726 NAME | PORT | POLARITY | VALUE
5495 11:04:40.128093 write protect | 0x00000096 | low | high
5496 11:04:40.134920 EC in RW | 0x000000b1 | high | undefined
5497 11:04:40.138268 EC interrupt | 0x00000097 | low | undefined
5498 11:04:40.144674 TPM interrupt | 0x00000099 | high | undefined
5499 11:04:40.147707 speaker enable | 0x000000af | high | undefined
5500 11:04:40.151364 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5501 11:04:40.154518 in-header: 03 f7 00 00 02 00 00 00
5502 11:04:40.157719 in-data: 04 00
5503 11:04:40.158184 Board ID: 4
5504 11:04:40.160896 ADC[3]: Raw value=216068 ID=1
5505 11:04:40.161420 RAM code: 1
5506 11:04:40.161730 SKU ID: 16
5507 11:04:40.167892 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5508 11:04:40.168351 CBFS @ 21000 size 3d4000
5509 11:04:40.174220 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5510 11:04:40.180801 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 29b8
5511 11:04:40.184483 coreboot table: 940 bytes.
5512 11:04:40.188167 IMD ROOT 0. 00000000fffff000 00001000
5513 11:04:40.190850 IMD SMALL 1. 00000000ffffe000 00001000
5514 11:04:40.194193 CONSOLE 2. 00000000fffde000 00020000
5515 11:04:40.197498 FMAP 3. 00000000fffdd000 0000047c
5516 11:04:40.200674 TIME STAMP 4. 00000000fffdc000 00000910
5517 11:04:40.204473 RAMOOPS 5. 00000000ffedc000 00100000
5518 11:04:40.207631 COREBOOT 6. 00000000ffeda000 00002000
5519 11:04:40.211035 IMD small region:
5520 11:04:40.214247 IMD ROOT 0. 00000000ffffec00 00000400
5521 11:04:40.217445 VBOOT WORK 1. 00000000ffffeb00 00000100
5522 11:04:40.221142 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5523 11:04:40.224044 VPD 3. 00000000ffffea60 0000006c
5524 11:04:40.230668 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5525 11:04:40.237613 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5526 11:04:40.240741 in-header: 03 e1 00 00 08 00 00 00
5527 11:04:40.243845 in-data: 84 20 60 10 00 00 00 00
5528 11:04:40.247171 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5529 11:04:40.250498 CBFS @ 21000 size 3d4000
5530 11:04:40.254351 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5531 11:04:40.257440 CBFS: Locating 'fallback/payload'
5532 11:04:40.266060 CBFS: Found @ offset dc040 size 439a0
5533 11:04:40.354044 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5534 11:04:40.357166 Checking segment from ROM address 0x0000000040003a00
5535 11:04:40.363913 Checking segment from ROM address 0x0000000040003a1c
5536 11:04:40.367732 Loading segment from ROM address 0x0000000040003a00
5537 11:04:40.370464 code (compression=0)
5538 11:04:40.381168 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5539 11:04:40.387270 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5540 11:04:40.390838 it's not compressed!
5541 11:04:40.394739 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5542 11:04:40.401638 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5543 11:04:40.408481 Loading segment from ROM address 0x0000000040003a1c
5544 11:04:40.411551 Entry Point 0x0000000080000000
5545 11:04:40.411941 Loaded segments
5546 11:04:40.418316 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5547 11:04:40.421394 Jumping to boot code at 0000000080000000(00000000ffeda000)
5548 11:04:40.431681 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5549 11:04:40.434719 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5550 11:04:40.438281 CBFS @ 21000 size 3d4000
5551 11:04:40.445080 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5552 11:04:40.448190 CBFS: Locating 'fallback/bl31'
5553 11:04:40.451509 CBFS: Found @ offset 36dc0 size 5820
5554 11:04:40.462363 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5555 11:04:40.465487 Checking segment from ROM address 0x0000000040003a00
5556 11:04:40.471968 Checking segment from ROM address 0x0000000040003a1c
5557 11:04:40.475311 Loading segment from ROM address 0x0000000040003a00
5558 11:04:40.478465 code (compression=1)
5559 11:04:40.485887 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5560 11:04:40.495141 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5561 11:04:40.495615 using LZMA
5562 11:04:40.504549 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5563 11:04:40.511051 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5564 11:04:40.514106 Loading segment from ROM address 0x0000000040003a1c
5565 11:04:40.517552 Entry Point 0x0000000054601000
5566 11:04:40.517959 Loaded segments
5567 11:04:40.520786 NOTICE: MT8183 bl31_setup
5568 11:04:40.527982 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5569 11:04:40.531468 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5570 11:04:40.534486 INFO: [DEVAPC] dump DEVAPC registers:
5571 11:04:40.544491 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5572 11:04:40.551299 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5573 11:04:40.561112 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5574 11:04:40.567832 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5575 11:04:40.577624 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5576 11:04:40.584315 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5577 11:04:40.594316 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5578 11:04:40.601147 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5579 11:04:40.610896 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5580 11:04:40.617490 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5581 11:04:40.623837 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5582 11:04:40.634161 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5583 11:04:40.640771 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5584 11:04:40.650360 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5585 11:04:40.657490 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5586 11:04:40.663596 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5587 11:04:40.670588 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5588 11:04:40.677219 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5589 11:04:40.687107 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5590 11:04:40.693486 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5591 11:04:40.700112 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5592 11:04:40.706914 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5593 11:04:40.710125 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5594 11:04:40.713426 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5595 11:04:40.716543 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5596 11:04:40.719883 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5597 11:04:40.723365 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5598 11:04:40.730049 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5599 11:04:40.736863 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5600 11:04:40.737274 WARNING: region 0:
5601 11:04:40.739918 WARNING: apc:0x168, sa:0x0, ea:0xfff
5602 11:04:40.743450 WARNING: region 1:
5603 11:04:40.747122 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5604 11:04:40.747510 WARNING: region 2:
5605 11:04:40.749989 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5606 11:04:40.753337 WARNING: region 3:
5607 11:04:40.756767 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5608 11:04:40.759871 WARNING: region 4:
5609 11:04:40.763191 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5610 11:04:40.763686 WARNING: region 5:
5611 11:04:40.767331 WARNING: apc:0x0, sa:0x0, ea:0x0
5612 11:04:40.770188 WARNING: region 6:
5613 11:04:40.774195 WARNING: apc:0x0, sa:0x0, ea:0x0
5614 11:04:40.774598 WARNING: region 7:
5615 11:04:40.777216 WARNING: apc:0x0, sa:0x0, ea:0x0
5616 11:04:40.783287 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5617 11:04:40.787322 INFO: SPM: enable SPMC mode
5618 11:04:40.789920 NOTICE: spm_boot_init() start
5619 11:04:40.793421 NOTICE: spm_boot_init() end
5620 11:04:40.796585 INFO: BL31: Initializing runtime services
5621 11:04:40.803466 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5622 11:04:40.806593 INFO: BL31: Preparing for EL3 exit to normal world
5623 11:04:40.809828 INFO: Entry point address = 0x80000000
5624 11:04:40.813275 INFO: SPSR = 0x8
5625 11:04:40.834661
5626 11:04:40.835152
5627 11:04:40.835533
5628 11:04:40.837873 end: 2.2.3 depthcharge-start (duration 00:00:25) [common]
5629 11:04:40.838512 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
5630 11:04:40.839025 Setting prompt string to ['jacuzzi:']
5631 11:04:40.839482 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:25)
5632 11:04:40.840302 Starting depthcharge on Juniper...
5633 11:04:40.840879
5634 11:04:40.841620 vboot_handoff: creating legacy vboot_handoff structure
5635 11:04:40.842146
5636 11:04:40.844252 ec_init(0): CrosEC protocol v3 supported (544, 544)
5637 11:04:40.844845
5638 11:04:40.847572 Wipe memory regions:
5639 11:04:40.848126
5640 11:04:40.850847 [0x00000040000000, 0x00000054600000)
5641 11:04:40.893978
5642 11:04:40.894403 [0x00000054660000, 0x00000080000000)
5643 11:04:40.985925
5644 11:04:40.986361 [0x000000811994a0, 0x000000ffeda000)
5645 11:04:41.245629
5646 11:04:41.246171 [0x00000100000000, 0x00000140000000)
5647 11:04:41.378115
5648 11:04:41.381538 Initializing XHCI USB controller at 0x11200000.
5649 11:04:41.404788
5650 11:04:41.408208 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5651 11:04:41.408727
5652 11:04:41.409063
5653 11:04:41.409844 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5654 11:04:41.410233 Sending line: 'tftpboot 192.168.201.1 14786794/tftp-deploy-hhm84oqd/kernel/image.itb 14786794/tftp-deploy-hhm84oqd/kernel/cmdline '
5656 11:04:41.511727 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5657 11:04:41.512241 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
5658 11:04:41.516646 jacuzzi: tftpboot 192.168.201.1 14786794/tftp-deploy-hhm84oqd/kernel/image.itbtp-deploy-hhm84oqd/kernel/cmdline
5659 11:04:41.517104
5660 11:04:41.517513 Waiting for link
5661 11:04:42.064956
5662 11:04:42.065556 R8152: Initializing
5663 11:04:42.065872
5664 11:04:42.069049 Version 9 (ocp_data = 6010)
5665 11:04:42.069502
5666 11:04:42.071204 R8152: Done initializing
5667 11:04:42.071662
5668 11:04:42.072090 Adding net device
5669 11:04:42.250345
5670 11:04:42.251029 R8152: Initializing
5671 11:04:42.251633
5672 11:04:42.253624 Version 9 (ocp_data = 6010)
5673 11:04:42.254159
5674 11:04:42.256644 R8152: Done initializing
5675 11:04:42.257063
5676 11:04:42.260065 net_add_device: Attemp to include the same device
5677 11:04:42.646510
5678 11:04:42.646997 done.
5679 11:04:42.647502
5680 11:04:42.647801 MAC: 00:e0:4c:72:3d:67
5681 11:04:42.648140
5682 11:04:42.649745 Sending DHCP discover... done.
5683 11:04:42.650122
5684 11:04:42.652952 Waiting for reply... done.
5685 11:04:42.653414
5686 11:04:42.657553 Sending DHCP request... done.
5687 11:04:42.657883
5688 11:04:42.662773 Waiting for reply... done.
5689 11:04:42.662951
5690 11:04:42.663082 My ip is 192.168.201.13
5691 11:04:42.663202
5692 11:04:42.665454 The DHCP server ip is 192.168.201.1
5693 11:04:42.665621
5694 11:04:42.672406 TFTP server IP predefined by user: 192.168.201.1
5695 11:04:42.672641
5696 11:04:42.678593 Bootfile predefined by user: 14786794/tftp-deploy-hhm84oqd/kernel/image.itb
5697 11:04:42.678894
5698 11:04:42.682495 Sending tftp read request... done.
5699 11:04:42.682934
5700 11:04:42.688844 Waiting for the transfer...
5701 11:04:42.689262
5702 11:04:42.963013 00000000 ################################################################
5703 11:04:42.963135
5704 11:04:43.225387 00080000 ################################################################
5705 11:04:43.225511
5706 11:04:43.483296 00100000 ################################################################
5707 11:04:43.483428
5708 11:04:43.772041 00180000 ################################################################
5709 11:04:43.772163
5710 11:04:44.028556 00200000 ################################################################
5711 11:04:44.028679
5712 11:04:44.282683 00280000 ################################################################
5713 11:04:44.282805
5714 11:04:44.541643 00300000 ################################################################
5715 11:04:44.541767
5716 11:04:44.796158 00380000 ################################################################
5717 11:04:44.796282
5718 11:04:45.060029 00400000 ################################################################
5719 11:04:45.060143
5720 11:04:45.330119 00480000 ################################################################
5721 11:04:45.330242
5722 11:04:45.609547 00500000 ################################################################
5723 11:04:45.609667
5724 11:04:45.870698 00580000 ################################################################
5725 11:04:45.870822
5726 11:04:46.156645 00600000 ################################################################
5727 11:04:46.156762
5728 11:04:46.444786 00680000 ################################################################
5729 11:04:46.444906
5730 11:04:46.712392 00700000 ################################################################
5731 11:04:46.712512
5732 11:04:46.982278 00780000 ################################################################
5733 11:04:46.982401
5734 11:04:47.274500 00800000 ################################################################
5735 11:04:47.274629
5736 11:04:47.559419 00880000 ################################################################
5737 11:04:47.559543
5738 11:04:47.848985 00900000 ################################################################
5739 11:04:47.849155
5740 11:04:48.107555 00980000 ################################################################
5741 11:04:48.107674
5742 11:04:48.372290 00a00000 ################################################################
5743 11:04:48.372410
5744 11:04:48.659317 00a80000 ################################################################
5745 11:04:48.659446
5746 11:04:48.947250 00b00000 ################################################################
5747 11:04:48.947366
5748 11:04:49.224311 00b80000 ################################################################
5749 11:04:49.224433
5750 11:04:49.502128 00c00000 ################################################################
5751 11:04:49.502272
5752 11:04:49.777076 00c80000 ################################################################
5753 11:04:49.777237
5754 11:04:50.062486 00d00000 ################################################################
5755 11:04:50.062607
5756 11:04:50.331467 00d80000 ################################################################
5757 11:04:50.331597
5758 11:04:50.615138 00e00000 ################################################################
5759 11:04:50.615259
5760 11:04:50.888081 00e80000 ################################################################
5761 11:04:50.888205
5762 11:04:51.167638 00f00000 ################################################################
5763 11:04:51.167758
5764 11:04:51.428218 00f80000 ################################################################
5765 11:04:51.428342
5766 11:04:51.700403 01000000 ################################################################
5767 11:04:51.700521
5768 11:04:51.975264 01080000 ################################################################
5769 11:04:51.975388
5770 11:04:52.238657 01100000 ################################################################
5771 11:04:52.238775
5772 11:04:52.514851 01180000 ################################################################
5773 11:04:52.514975
5774 11:04:52.797109 01200000 ################################################################
5775 11:04:52.797249
5776 11:04:53.071928 01280000 ################################################################
5777 11:04:53.072048
5778 11:04:53.340559 01300000 ################################################################
5779 11:04:53.340678
5780 11:04:53.625735 01380000 ################################################################
5781 11:04:53.625858
5782 11:04:53.918473 01400000 ################################################################
5783 11:04:53.918589
5784 11:04:54.194567 01480000 ################################################################
5785 11:04:54.194718
5786 11:04:54.468693 01500000 ################################################################
5787 11:04:54.468817
5788 11:04:54.743404 01580000 ################################################################
5789 11:04:54.743526
5790 11:04:55.021757 01600000 ################################################################
5791 11:04:55.021877
5792 11:04:55.286767 01680000 ################################################################
5793 11:04:55.286889
5794 11:04:55.541713 01700000 ################################################################
5795 11:04:55.541837
5796 11:04:55.802344 01780000 ################################################################
5797 11:04:55.802478
5798 11:04:56.066849 01800000 ################################################################
5799 11:04:56.066962
5800 11:04:56.336404 01880000 ################################################################
5801 11:04:56.336540
5802 11:04:56.598006 01900000 ################################################################
5803 11:04:56.598124
5804 11:04:56.861261 01980000 ################################################################
5805 11:04:56.861370
5806 11:04:57.150936 01a00000 ################################################################
5807 11:04:57.151052
5808 11:04:57.417353 01a80000 ################################################################
5809 11:04:57.417466
5810 11:04:57.700128 01b00000 ################################################################
5811 11:04:57.700269
5812 11:04:57.978642 01b80000 ################################################################
5813 11:04:57.978765
5814 11:04:58.256916 01c00000 ################################################################
5815 11:04:58.257026
5816 11:04:58.535360 01c80000 ################################################################
5817 11:04:58.535485
5818 11:04:58.804336 01d00000 ################################################################
5819 11:04:58.804460
5820 11:04:59.065372 01d80000 ################################################################
5821 11:04:59.065514
5822 11:04:59.283623 01e00000 ##################################################### done.
5823 11:04:59.283735
5824 11:04:59.287269 The bootfile was 31886254 bytes long.
5825 11:04:59.287351
5826 11:04:59.290755 Sending tftp read request... done.
5827 11:04:59.290838
5828 11:04:59.293737 Waiting for the transfer...
5829 11:04:59.293825
5830 11:04:59.293891 00000000 # done.
5831 11:04:59.293955
5832 11:04:59.304095 Command line loaded dynamically from TFTP file: 14786794/tftp-deploy-hhm84oqd/kernel/cmdline
5833 11:04:59.304199
5834 11:04:59.327271 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786794/extract-nfsrootfs-gd9vxcky,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5835 11:04:59.327467
5836 11:04:59.330368 Loading FIT.
5837 11:04:59.330560
5838 11:04:59.333823 Image ramdisk-1 has 18710259 bytes.
5839 11:04:59.334048
5840 11:04:59.334222 Image fdt-1 has 57695 bytes.
5841 11:04:59.337541
5842 11:04:59.337818 Image kernel-1 has 13116259 bytes.
5843 11:04:59.338035
5844 11:04:59.348006 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5845 11:04:59.348401
5846 11:04:59.360735 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5847 11:04:59.361162
5848 11:04:59.364111 Choosing best match conf-1 for compat google,juniper-sku16.
5849 11:04:59.369767
5850 11:04:59.374001 Connected to device vid:did:rid of 1ae0:0028:00
5851 11:04:59.382538
5852 11:04:59.385310 tpm_get_response: command 0x17b, return code 0x0
5853 11:04:59.385709
5854 11:04:59.388768 tpm_cleanup: add release locality here.
5855 11:04:59.389187
5856 11:04:59.392546 Shutting down all USB controllers.
5857 11:04:59.392936
5858 11:04:59.395614 Removing current net device
5859 11:04:59.396005
5860 11:04:59.398582 Exiting depthcharge with code 4 at timestamp: 35934464
5861 11:04:59.399027
5862 11:04:59.401984 LZMA decompressing kernel-1 to 0x80193568
5863 11:04:59.402438
5864 11:04:59.408886 LZMA decompressing kernel-1 to 0x40000000
5865 11:05:01.271724
5866 11:05:01.272173 jumping to kernel
5867 11:05:01.273834 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5868 11:05:01.274329 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
5869 11:05:01.274792 Setting prompt string to ['Linux version [0-9]']
5870 11:05:01.275165 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5871 11:05:01.275509 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5872 11:05:01.347274
5873 11:05:01.350138 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5874 11:05:01.353672 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
5875 11:05:01.354115 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5876 11:05:01.354455 Setting prompt string to []
5877 11:05:01.354829 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5878 11:05:01.355160 Using line separator: #'\n'#
5879 11:05:01.355434 No login prompt set.
5880 11:05:01.355711 Parsing kernel messages
5881 11:05:01.355970 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5882 11:05:01.356450 [login-action] Waiting for messages, (timeout 00:04:05)
5883 11:05:01.356747 Waiting using forced prompt support (timeout 00:02:02)
5884 11:05:01.373653 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
5885 11:05:01.376540 [ 0.000000] random: crng init done
5886 11:05:01.380009 [ 0.000000] Machine model: Google juniper sku16 board
5887 11:05:01.383153 [ 0.000000] efi: UEFI not found.
5888 11:05:01.393535 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5889 11:05:01.399986 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5890 11:05:01.406308 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5891 11:05:01.413106 [ 0.000000] printk: bootconsole [mtk8250] enabled
5892 11:05:01.420902 [ 0.000000] NUMA: No NUMA configuration found
5893 11:05:01.427726 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5894 11:05:01.434126 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5895 11:05:01.434519 [ 0.000000] Zone ranges:
5896 11:05:01.440758 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5897 11:05:01.444352 [ 0.000000] DMA32 empty
5898 11:05:01.450628 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5899 11:05:01.454188 [ 0.000000] Movable zone start for each node
5900 11:05:01.457527 [ 0.000000] Early memory node ranges
5901 11:05:01.464036 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5902 11:05:01.470663 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5903 11:05:01.477246 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5904 11:05:01.483838 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5905 11:05:01.490507 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5906 11:05:01.497288 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5907 11:05:01.517624 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5908 11:05:01.524095 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5909 11:05:01.531021 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5910 11:05:01.533917 [ 0.000000] psci: probing for conduit method from DT.
5911 11:05:01.540684 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5912 11:05:01.543778 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5913 11:05:01.550985 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5914 11:05:01.553648 [ 0.000000] psci: SMC Calling Convention v1.1
5915 11:05:01.560310 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5916 11:05:01.564672 [ 0.000000] Detected VIPT I-cache on CPU0
5917 11:05:01.570443 [ 0.000000] CPU features: detected: GIC system register CPU interface
5918 11:05:01.577412 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5919 11:05:01.583975 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5920 11:05:01.590681 [ 0.000000] CPU features: detected: ARM erratum 845719
5921 11:05:01.593686 [ 0.000000] alternatives: applying boot alternatives
5922 11:05:01.597297 [ 0.000000] Fallback order for Node 0: 0
5923 11:05:01.603989 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5924 11:05:01.606843 [ 0.000000] Policy zone: Normal
5925 11:05:01.633452 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786794/extract-nfsrootfs-gd9vxcky,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5926 11:05:01.647047 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5927 11:05:01.656837 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5928 11:05:01.663202 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5929 11:05:01.670040 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5930 11:05:01.676907 <6>[ 0.000000] software IO TLB: area num 8.
5931 11:05:01.701469 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5932 11:05:01.759469 <6>[ 0.000000] Memory: 3896800K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 261664K reserved, 32768K cma-reserved)
5933 11:05:01.765934 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5934 11:05:01.772911 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5935 11:05:01.776090 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5936 11:05:01.782847 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5937 11:05:01.789867 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5938 11:05:01.792753 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5939 11:05:01.802684 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5940 11:05:01.809229 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5941 11:05:01.816060 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5942 11:05:01.825762 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5943 11:05:01.829286 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5944 11:05:01.832301 <6>[ 0.000000] GICv3: 640 SPIs implemented
5945 11:05:01.838917 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5946 11:05:01.842295 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5947 11:05:01.845773 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5948 11:05:01.856107 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5949 11:05:01.865628 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5950 11:05:01.879019 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5951 11:05:01.885208 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5952 11:05:01.896959 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5953 11:05:01.909745 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5954 11:05:01.916447 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5955 11:05:01.923352 <6>[ 0.009467] Console: colour dummy device 80x25
5956 11:05:01.926606 <6>[ 0.014508] printk: console [tty1] enabled
5957 11:05:01.936894 <6>[ 0.018898] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5958 11:05:01.943257 <6>[ 0.029363] pid_max: default: 32768 minimum: 301
5959 11:05:01.947115 <6>[ 0.034243] LSM: Security Framework initializing
5960 11:05:01.956125 <6>[ 0.039159] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5961 11:05:01.962696 <6>[ 0.046782] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5962 11:05:01.969670 <4>[ 0.055660] cacheinfo: Unable to detect cache hierarchy for CPU 0
5963 11:05:01.979067 <6>[ 0.062286] cblist_init_generic: Setting adjustable number of callback queues.
5964 11:05:01.985998 <6>[ 0.069732] cblist_init_generic: Setting shift to 3 and lim to 1.
5965 11:05:01.992563 <6>[ 0.076085] cblist_init_generic: Setting adjustable number of callback queues.
5966 11:05:01.999261 <6>[ 0.083529] cblist_init_generic: Setting shift to 3 and lim to 1.
5967 11:05:02.002434 <6>[ 0.089928] rcu: Hierarchical SRCU implementation.
5968 11:05:02.008883 <6>[ 0.094955] rcu: Max phase no-delay instances is 1000.
5969 11:05:02.016519 <6>[ 0.102859] EFI services will not be available.
5970 11:05:02.019544 <6>[ 0.107808] smp: Bringing up secondary CPUs ...
5971 11:05:02.030056 <6>[ 0.113070] Detected VIPT I-cache on CPU1
5972 11:05:02.036933 <4>[ 0.113117] cacheinfo: Unable to detect cache hierarchy for CPU 1
5973 11:05:02.043215 <6>[ 0.113124] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5974 11:05:02.050305 <6>[ 0.113157] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5975 11:05:02.053640 <6>[ 0.113640] Detected VIPT I-cache on CPU2
5976 11:05:02.060509 <4>[ 0.113674] cacheinfo: Unable to detect cache hierarchy for CPU 2
5977 11:05:02.066899 <6>[ 0.113679] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5978 11:05:02.073177 <6>[ 0.113690] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5979 11:05:02.079908 <6>[ 0.114135] Detected VIPT I-cache on CPU3
5980 11:05:02.083297 <4>[ 0.114165] cacheinfo: Unable to detect cache hierarchy for CPU 3
5981 11:05:02.093089 <6>[ 0.114170] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5982 11:05:02.099480 <6>[ 0.114182] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5983 11:05:02.102976 <6>[ 0.114755] CPU features: detected: Spectre-v2
5984 11:05:02.106534 <6>[ 0.114765] CPU features: detected: Spectre-BHB
5985 11:05:02.113426 <6>[ 0.114769] CPU features: detected: ARM erratum 858921
5986 11:05:02.116639 <6>[ 0.114774] Detected VIPT I-cache on CPU4
5987 11:05:02.122645 <4>[ 0.114823] cacheinfo: Unable to detect cache hierarchy for CPU 4
5988 11:05:02.129578 <6>[ 0.114831] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5989 11:05:02.136377 <6>[ 0.114839] arch_timer: Enabling local workaround for ARM erratum 858921
5990 11:05:02.142595 <6>[ 0.114850] arch_timer: CPU4: Trapping CNTVCT access
5991 11:05:02.149401 <6>[ 0.114857] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5992 11:05:02.153051 <6>[ 0.115342] Detected VIPT I-cache on CPU5
5993 11:05:02.159513 <4>[ 0.115382] cacheinfo: Unable to detect cache hierarchy for CPU 5
5994 11:05:02.166336 <6>[ 0.115387] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5995 11:05:02.176205 <6>[ 0.115394] arch_timer: Enabling local workaround for ARM erratum 858921
5996 11:05:02.179612 <6>[ 0.115400] arch_timer: CPU5: Trapping CNTVCT access
5997 11:05:02.186128 <6>[ 0.115405] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5998 11:05:02.189505 <6>[ 0.115842] Detected VIPT I-cache on CPU6
5999 11:05:02.195740 <4>[ 0.115887] cacheinfo: Unable to detect cache hierarchy for CPU 6
6000 11:05:02.206528 <6>[ 0.115893] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
6001 11:05:02.212485 <6>[ 0.115900] arch_timer: Enabling local workaround for ARM erratum 858921
6002 11:05:02.215901 <6>[ 0.115906] arch_timer: CPU6: Trapping CNTVCT access
6003 11:05:02.222224 <6>[ 0.115911] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
6004 11:05:02.225998 <6>[ 0.116443] Detected VIPT I-cache on CPU7
6005 11:05:02.232416 <4>[ 0.116484] cacheinfo: Unable to detect cache hierarchy for CPU 7
6006 11:05:02.242594 <6>[ 0.116491] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
6007 11:05:02.248740 <6>[ 0.116498] arch_timer: Enabling local workaround for ARM erratum 858921
6008 11:05:02.252339 <6>[ 0.116504] arch_timer: CPU7: Trapping CNTVCT access
6009 11:05:02.258632 <6>[ 0.116509] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
6010 11:05:02.262272 <6>[ 0.116557] smp: Brought up 1 node, 8 CPUs
6011 11:05:02.268585 <6>[ 0.355474] SMP: Total of 8 processors activated.
6012 11:05:02.275666 <6>[ 0.360409] CPU features: detected: 32-bit EL0 Support
6013 11:05:02.278856 <6>[ 0.365788] CPU features: detected: 32-bit EL1 Support
6014 11:05:02.285340 <6>[ 0.371157] CPU features: detected: CRC32 instructions
6015 11:05:02.288658 <6>[ 0.376581] CPU: All CPU(s) started at EL2
6016 11:05:02.295442 <6>[ 0.380919] alternatives: applying system-wide alternatives
6017 11:05:02.302303 <6>[ 0.388977] devtmpfs: initialized
6018 11:05:02.314850 <6>[ 0.397918] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
6019 11:05:02.324514 <6>[ 0.407867] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
6020 11:05:02.328421 <6>[ 0.415594] pinctrl core: initialized pinctrl subsystem
6021 11:05:02.336154 <6>[ 0.422710] DMI not present or invalid.
6022 11:05:02.342634 <6>[ 0.427078] NET: Registered PF_NETLINK/PF_ROUTE protocol family
6023 11:05:02.349278 <6>[ 0.433986] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
6024 11:05:02.359054 <6>[ 0.441513] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
6025 11:05:02.365984 <6>[ 0.449763] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
6026 11:05:02.372930 <6>[ 0.457936] audit: initializing netlink subsys (disabled)
6027 11:05:02.379354 <5>[ 0.463641] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
6028 11:05:02.386546 <6>[ 0.464626] thermal_sys: Registered thermal governor 'step_wise'
6029 11:05:02.393005 <6>[ 0.471609] thermal_sys: Registered thermal governor 'power_allocator'
6030 11:05:02.396177 <6>[ 0.477909] cpuidle: using governor menu
6031 11:05:02.402841 <6>[ 0.488871] NET: Registered PF_QIPCRTR protocol family
6032 11:05:02.409638 <6>[ 0.494369] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
6033 11:05:02.416503 <6>[ 0.501469] ASID allocator initialised with 32768 entries
6034 11:05:02.422758 <6>[ 0.508244] Serial: AMBA PL011 UART driver
6035 11:05:02.433254 <4>[ 0.519567] Trying to register duplicate clock ID: 113
6036 11:05:02.493211 <6>[ 0.576218] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6037 11:05:02.507926 <6>[ 0.590607] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6038 11:05:02.511464 <6>[ 0.600385] KASLR enabled
6039 11:05:02.525099 <6>[ 0.608323] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
6040 11:05:02.531865 <6>[ 0.615327] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
6041 11:05:02.538539 <6>[ 0.621804] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
6042 11:05:02.545074 <6>[ 0.628795] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
6043 11:05:02.551739 <6>[ 0.635271] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6044 11:05:02.558292 <6>[ 0.642261] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6045 11:05:02.565144 <6>[ 0.648734] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6046 11:05:02.571578 <6>[ 0.655723] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6047 11:05:02.575064 <6>[ 0.663258] ACPI: Interpreter disabled.
6048 11:05:02.584983 <6>[ 0.671268] iommu: Default domain type: Translated
6049 11:05:02.591461 <6>[ 0.676431] iommu: DMA domain TLB invalidation policy: strict mode
6050 11:05:02.594777 <5>[ 0.683055] SCSI subsystem initialized
6051 11:05:02.601414 <6>[ 0.687499] usbcore: registered new interface driver usbfs
6052 11:05:02.608045 <6>[ 0.693229] usbcore: registered new interface driver hub
6053 11:05:02.611585 <6>[ 0.698771] usbcore: registered new device driver usb
6054 11:05:02.618672 <6>[ 0.705092] pps_core: LinuxPPS API ver. 1 registered
6055 11:05:02.628877 <6>[ 0.710276] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6056 11:05:02.632530 <6>[ 0.719602] PTP clock support registered
6057 11:05:02.635474 <6>[ 0.723855] EDAC MC: Ver: 3.0.0
6058 11:05:02.643211 <6>[ 0.729505] FPGA manager framework
6059 11:05:02.646351 <6>[ 0.733185] Advanced Linux Sound Architecture Driver Initialized.
6060 11:05:02.650190 <6>[ 0.739929] vgaarb: loaded
6061 11:05:02.656795 <6>[ 0.743062] clocksource: Switched to clocksource arch_sys_counter
6062 11:05:02.663312 <5>[ 0.749496] VFS: Disk quotas dquot_6.6.0
6063 11:05:02.669901 <6>[ 0.753670] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6064 11:05:02.673260 <6>[ 0.760846] pnp: PnP ACPI: disabled
6065 11:05:02.680850 <6>[ 0.767716] NET: Registered PF_INET protocol family
6066 11:05:02.687659 <6>[ 0.772939] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6067 11:05:02.699828 <6>[ 0.782850] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6068 11:05:02.709603 <6>[ 0.791606] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6069 11:05:02.716386 <6>[ 0.799556] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6070 11:05:02.722696 <6>[ 0.807788] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6071 11:05:02.729534 <6>[ 0.815883] TCP: Hash tables configured (established 32768 bind 32768)
6072 11:05:02.740042 <6>[ 0.822708] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6073 11:05:02.746526 <6>[ 0.829681] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6074 11:05:02.753379 <6>[ 0.837163] NET: Registered PF_UNIX/PF_LOCAL protocol family
6075 11:05:02.759687 <6>[ 0.843289] RPC: Registered named UNIX socket transport module.
6076 11:05:02.763118 <6>[ 0.849434] RPC: Registered udp transport module.
6077 11:05:02.766551 <6>[ 0.854359] RPC: Registered tcp transport module.
6078 11:05:02.772953 <6>[ 0.859283] RPC: Registered tcp NFSv4.1 backchannel transport module.
6079 11:05:02.779603 <6>[ 0.865935] PCI: CLS 0 bytes, default 64
6080 11:05:02.782661 <6>[ 0.870195] Unpacking initramfs...
6081 11:05:02.800854 <6>[ 0.883684] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6082 11:05:02.810867 <6>[ 0.892316] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6083 11:05:02.814555 <6>[ 0.901163] kvm [1]: IPA Size Limit: 40 bits
6084 11:05:02.821344 <6>[ 0.907494] kvm [1]: vgic-v2@c420000
6085 11:05:02.824848 <6>[ 0.911317] kvm [1]: GIC system register CPU interface enabled
6086 11:05:02.830922 <6>[ 0.917523] kvm [1]: vgic interrupt IRQ18
6087 11:05:02.834518 <6>[ 0.921899] kvm [1]: Hyp mode initialized successfully
6088 11:05:02.841858 <5>[ 0.928250] Initialise system trusted keyrings
6089 11:05:02.848288 <6>[ 0.933104] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6090 11:05:02.856876 <6>[ 0.943077] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6091 11:05:02.863255 <5>[ 0.949503] NFS: Registering the id_resolver key type
6092 11:05:02.866561 <5>[ 0.954814] Key type id_resolver registered
6093 11:05:02.873778 <5>[ 0.959225] Key type id_legacy registered
6094 11:05:02.880649 <6>[ 0.963528] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6095 11:05:02.886662 <6>[ 0.970449] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6096 11:05:02.893260 <6>[ 0.978201] 9p: Installing v9fs 9p2000 file system support
6097 11:05:02.921413 <5>[ 1.007514] Key type asymmetric registered
6098 11:05:02.924203 <5>[ 1.011858] Asymmetric key parser 'x509' registered
6099 11:05:02.934595 <6>[ 1.017008] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6100 11:05:02.937512 <6>[ 1.024628] io scheduler mq-deadline registered
6101 11:05:02.941101 <6>[ 1.029392] io scheduler kyber registered
6102 11:05:02.963900 <6>[ 1.050265] EINJ: ACPI disabled.
6103 11:05:02.970347 <4>[ 1.054043] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6104 11:05:03.008703 <6>[ 1.094967] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6105 11:05:03.016976 <6>[ 1.103497] printk: console [ttyS0] disabled
6106 11:05:03.044948 <6>[ 1.128147] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6107 11:05:03.052487 <6>[ 1.137617] printk: console [ttyS0] enabled
6108 11:05:03.055297 <6>[ 1.137617] printk: console [ttyS0] enabled
6109 11:05:03.062098 <6>[ 1.146537] printk: bootconsole [mtk8250] disabled
6110 11:05:03.065568 <6>[ 1.146537] printk: bootconsole [mtk8250] disabled
6111 11:05:03.074765 <3>[ 1.157063] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6112 11:05:03.081609 <3>[ 1.165447] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6113 11:05:03.110546 <6>[ 1.193859] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6114 11:05:03.117087 <6>[ 1.203519] serial serial0: tty port ttyS1 registered
6115 11:05:03.123594 <6>[ 1.210089] SuperH (H)SCI(F) driver initialized
6116 11:05:03.126896 <6>[ 1.215570] msm_serial: driver initialized
6117 11:05:03.142581 <6>[ 1.225900] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6118 11:05:03.152207 <6>[ 1.234503] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6119 11:05:03.158717 <6>[ 1.243083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6120 11:05:03.169346 <6>[ 1.251650] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6121 11:05:03.178524 <6>[ 1.260306] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6122 11:05:03.185605 <6>[ 1.268965] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6123 11:05:03.195180 <6>[ 1.277705] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6124 11:05:03.202129 <6>[ 1.286443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6125 11:05:03.212143 <6>[ 1.295010] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6126 11:05:03.221867 <6>[ 1.303810] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6127 11:05:03.229423 <4>[ 1.316204] cacheinfo: Unable to detect cache hierarchy for CPU 0
6128 11:05:03.239046 <6>[ 1.325536] loop: module loaded
6129 11:05:03.250806 <6>[ 1.337526] vsim1: Bringing 1800000uV into 2700000-2700000uV
6130 11:05:03.268560 <6>[ 1.355530] megasas: 07.719.03.00-rc1
6131 11:05:03.277865 <6>[ 1.364230] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6132 11:05:03.292445 <6>[ 1.378472] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6133 11:05:03.308878 <6>[ 1.395276] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6134 11:05:03.365518 <6>[ 1.445375] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6135 11:05:03.408480 <6>[ 1.494859] Freeing initrd memory: 18268K
6136 11:05:03.423399 <4>[ 1.506771] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6137 11:05:03.430316 <4>[ 1.516003] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6138 11:05:03.437087 <4>[ 1.522700] Hardware name: Google juniper sku16 board (DT)
6139 11:05:03.439971 <4>[ 1.528440] Call trace:
6140 11:05:03.443513 <4>[ 1.531140] dump_backtrace.part.0+0xe0/0xf0
6141 11:05:03.446505 <4>[ 1.535678] show_stack+0x18/0x30
6142 11:05:03.449922 <4>[ 1.539251] dump_stack_lvl+0x64/0x80
6143 11:05:03.456420 <4>[ 1.543170] dump_stack+0x18/0x34
6144 11:05:03.459881 <4>[ 1.546739] sysfs_warn_dup+0x64/0x80
6145 11:05:03.463648 <4>[ 1.550661] sysfs_do_create_link_sd+0xf0/0x100
6146 11:05:03.466427 <4>[ 1.555449] sysfs_create_link+0x20/0x40
6147 11:05:03.473348 <4>[ 1.559629] bus_add_device+0x64/0x120
6148 11:05:03.476681 <4>[ 1.563633] device_add+0x354/0x7ec
6149 11:05:03.480369 <4>[ 1.567380] of_device_add+0x44/0x60
6150 11:05:03.483129 <4>[ 1.571213] of_platform_device_create_pdata+0x90/0x124
6151 11:05:03.489904 <4>[ 1.576695] of_platform_bus_create+0x154/0x380
6152 11:05:03.493252 <4>[ 1.581481] of_platform_populate+0x50/0xfc
6153 11:05:03.499782 <4>[ 1.585920] parse_mtd_partitions+0x1d8/0x4e0
6154 11:05:03.503310 <4>[ 1.590536] mtd_device_parse_register+0xec/0x2e0
6155 11:05:03.506336 <4>[ 1.595497] spi_nor_probe+0x280/0x2f4
6156 11:05:03.513444 <4>[ 1.599502] spi_mem_probe+0x6c/0xc0
6157 11:05:03.516432 <4>[ 1.603335] spi_probe+0x84/0xe4
6158 11:05:03.519925 <4>[ 1.606820] really_probe+0xbc/0x2dc
6159 11:05:03.523210 <4>[ 1.610650] __driver_probe_device+0x78/0x114
6160 11:05:03.526834 <4>[ 1.615262] driver_probe_device+0xd8/0x15c
6161 11:05:03.533495 <4>[ 1.619700] __device_attach_driver+0xb8/0x134
6162 11:05:03.536238 <4>[ 1.624398] bus_for_each_drv+0x7c/0xd4
6163 11:05:03.540031 <4>[ 1.628491] __device_attach+0x9c/0x1a0
6164 11:05:03.546493 <4>[ 1.632581] device_initial_probe+0x14/0x20
6165 11:05:03.549947 <4>[ 1.637019] bus_probe_device+0x98/0xa0
6166 11:05:03.553317 <4>[ 1.641109] device_add+0x3c0/0x7ec
6167 11:05:03.556766 <4>[ 1.644854] __spi_add_device+0x78/0x120
6168 11:05:03.559879 <4>[ 1.649032] spi_add_device+0x44/0x80
6169 11:05:03.566433 <4>[ 1.652950] spi_register_controller+0x704/0xb20
6170 11:05:03.569455 <4>[ 1.657821] devm_spi_register_controller+0x4c/0xac
6171 11:05:03.576500 <4>[ 1.662953] mtk_spi_probe+0x4f4/0x684
6172 11:05:03.579471 <4>[ 1.666958] platform_probe+0x68/0xc0
6173 11:05:03.583384 <4>[ 1.670876] really_probe+0xbc/0x2dc
6174 11:05:03.586869 <4>[ 1.674706] __driver_probe_device+0x78/0x114
6175 11:05:03.593194 <4>[ 1.679318] driver_probe_device+0xd8/0x15c
6176 11:05:03.596671 <4>[ 1.683755] __driver_attach+0x94/0x19c
6177 11:05:03.600261 <4>[ 1.687846] bus_for_each_dev+0x74/0xd0
6178 11:05:03.603126 <4>[ 1.691939] driver_attach+0x24/0x30
6179 11:05:03.607071 <4>[ 1.695769] bus_add_driver+0x154/0x20c
6180 11:05:03.613229 <4>[ 1.699858] driver_register+0x78/0x130
6181 11:05:03.616533 <4>[ 1.703948] __platform_driver_register+0x28/0x34
6182 11:05:03.623150 <4>[ 1.708909] mtk_spi_driver_init+0x1c/0x28
6183 11:05:03.626767 <4>[ 1.713264] do_one_initcall+0x64/0x1dc
6184 11:05:03.629570 <4>[ 1.717355] kernel_init_freeable+0x218/0x284
6185 11:05:03.633068 <4>[ 1.721969] kernel_init+0x24/0x12c
6186 11:05:03.636636 <4>[ 1.725714] ret_from_fork+0x10/0x20
6187 11:05:03.647680 <6>[ 1.734599] tun: Universal TUN/TAP device driver, 1.6
6188 11:05:03.651066 <6>[ 1.740894] thunder_xcv, ver 1.0
6189 11:05:03.654640 <6>[ 1.744410] thunder_bgx, ver 1.0
6190 11:05:03.657724 <6>[ 1.747916] nicpf, ver 1.0
6191 11:05:03.669006 <6>[ 1.752287] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6192 11:05:03.672321 <6>[ 1.759771] hns3: Copyright (c) 2017 Huawei Corporation.
6193 11:05:03.675633 <6>[ 1.765376] hclge is initializing
6194 11:05:03.682831 <6>[ 1.768970] e1000: Intel(R) PRO/1000 Network Driver
6195 11:05:03.688765 <6>[ 1.774105] e1000: Copyright (c) 1999-2006 Intel Corporation.
6196 11:05:03.692426 <6>[ 1.780127] e1000e: Intel(R) PRO/1000 Network Driver
6197 11:05:03.698577 <6>[ 1.785349] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6198 11:05:03.705254 <6>[ 1.791544] igb: Intel(R) Gigabit Ethernet Network Driver
6199 11:05:03.712742 <6>[ 1.797199] igb: Copyright (c) 2007-2014 Intel Corporation.
6200 11:05:03.718861 <6>[ 1.803043] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6201 11:05:03.725563 <6>[ 1.809567] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6202 11:05:03.729320 <6>[ 1.816124] sky2: driver version 1.30
6203 11:05:03.735447 <6>[ 1.821380] usbcore: registered new device driver r8152-cfgselector
6204 11:05:03.742423 <6>[ 1.827924] usbcore: registered new interface driver r8152
6205 11:05:03.749462 <6>[ 1.833752] VFIO - User Level meta-driver version: 0.3
6206 11:05:03.755519 <6>[ 1.841528] mtu3 11201000.usb: uwk - reg:0x420, version:101
6207 11:05:03.762194 <4>[ 1.847404] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6208 11:05:03.768881 <6>[ 1.854677] mtu3 11201000.usb: dr_mode: 1, drd: auto
6209 11:05:03.775438 <6>[ 1.859903] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6210 11:05:03.778766 <6>[ 1.866084] mtu3 11201000.usb: usb3-drd: 0
6211 11:05:03.785299 <6>[ 1.871642] mtu3 11201000.usb: xHCI platform device register success...
6212 11:05:03.797167 <4>[ 1.880263] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6213 11:05:03.803601 <6>[ 1.888200] xhci-mtk 11200000.usb: xHCI Host Controller
6214 11:05:03.810210 <6>[ 1.893706] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6215 11:05:03.816573 <6>[ 1.901444] xhci-mtk 11200000.usb: USB3 root hub has no ports
6216 11:05:03.826487 <6>[ 1.907453] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6217 11:05:03.830194 <6>[ 1.916878] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6218 11:05:03.837241 <6>[ 1.922955] xhci-mtk 11200000.usb: xHCI Host Controller
6219 11:05:03.843342 <6>[ 1.928445] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6220 11:05:03.850344 <6>[ 1.936102] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6221 11:05:03.856400 <6>[ 1.942918] hub 1-0:1.0: USB hub found
6222 11:05:03.860203 <6>[ 1.946946] hub 1-0:1.0: 1 port detected
6223 11:05:03.870182 <6>[ 1.952297] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6224 11:05:03.873622 <6>[ 1.960922] hub 2-0:1.0: USB hub found
6225 11:05:03.879992 <3>[ 1.964948] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6226 11:05:03.887131 <6>[ 1.972834] usbcore: registered new interface driver usb-storage
6227 11:05:03.893340 <6>[ 1.979428] usbcore: registered new device driver onboard-usb-hub
6228 11:05:03.911599 <4>[ 1.995177] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6229 11:05:03.920810 <6>[ 2.007385] mt6397-rtc mt6358-rtc: registered as rtc0
6230 11:05:03.930802 <6>[ 2.012899] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-10T11:05:03 UTC (1720609503)
6231 11:05:03.934366 <6>[ 2.022782] i2c_dev: i2c /dev entries driver
6232 11:05:03.946179 <6>[ 2.029193] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6233 11:05:03.956015 <6>[ 2.037574] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6234 11:05:03.959324 <6>[ 2.046484] i2c 4-0058: Fixed dependency cycle(s) with /panel
6235 11:05:03.969065 <6>[ 2.052552] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6236 11:05:03.985294 <6>[ 2.072115] cpu cpu0: EM: created perf domain
6237 11:05:03.995424 <6>[ 2.077561] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6238 11:05:04.001929 <6>[ 2.088845] cpu cpu4: EM: created perf domain
6239 11:05:04.009337 <6>[ 2.095860] sdhci: Secure Digital Host Controller Interface driver
6240 11:05:04.015798 <6>[ 2.102315] sdhci: Copyright(c) Pierre Ossman
6241 11:05:04.022533 <6>[ 2.107726] Synopsys Designware Multimedia Card Interface Driver
6242 11:05:04.029319 <6>[ 2.108275] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6243 11:05:04.032482 <6>[ 2.114769] sdhci-pltfm: SDHCI platform and OF driver helper
6244 11:05:04.040358 <6>[ 2.127495] ledtrig-cpu: registered to indicate activity on CPUs
6245 11:05:04.048394 <6>[ 2.135214] usbcore: registered new interface driver usbhid
6246 11:05:04.052051 <6>[ 2.141051] usbhid: USB HID core driver
6247 11:05:04.063199 <6>[ 2.145311] spi_master spi2: will run message pump with realtime priority
6248 11:05:04.066422 <4>[ 2.145318] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6249 11:05:04.076259 <4>[ 2.159581] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6250 11:05:04.089699 <6>[ 2.166076] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6251 11:05:04.103056 <6>[ 2.181965] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6252 11:05:04.109967 <4>[ 2.194152] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6253 11:05:04.116365 <6>[ 2.197108] cros-ec-spi spi2.0: Chrome EC device registered
6254 11:05:04.128871 <4>[ 2.212432] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6255 11:05:04.141301 <4>[ 2.224362] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6256 11:05:04.147750 <6>[ 2.233106] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x12c14
6257 11:05:04.154237 <4>[ 2.233138] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6258 11:05:04.157951 <6>[ 2.240969] mmc0: new HS400 MMC card at address 0001
6259 11:05:04.165023 <6>[ 2.251548] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6260 11:05:04.171629 <6>[ 2.255606] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6261 11:05:04.181581 <6>[ 2.255917] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6262 11:05:04.191319 <6>[ 2.260315] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6263 11:05:04.198116 <6>[ 2.261754] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6264 11:05:04.201523 <6>[ 2.263160] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6265 11:05:04.208339 <6>[ 2.264389] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6266 11:05:04.211631 <6>[ 2.273280] NET: Registered PF_PACKET protocol family
6267 11:05:04.218014 <6>[ 2.283687] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6268 11:05:04.225230 <6>[ 2.288867] 9pnet: Installing 9P2000 support
6269 11:05:04.235198 <6>[ 2.311547] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6270 11:05:04.242051 <5>[ 2.315519] Key type dns_resolver registered
6271 11:05:04.251624 <6>[ 2.328297] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6272 11:05:04.255486 <6>[ 2.332468] registered taskstats version 1
6273 11:05:04.258890 <5>[ 2.346412] Loading compiled-in X.509 certificates
6274 11:05:04.283611 <6>[ 2.367196] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6275 11:05:04.308545 <3>[ 2.391997] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6276 11:05:04.340219 <6>[ 2.420159] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6277 11:05:04.351433 <6>[ 2.434360] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6278 11:05:04.361045 <6>[ 2.442932] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6279 11:05:04.367553 <6>[ 2.451610] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6280 11:05:04.377513 <6>[ 2.460165] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6281 11:05:04.384131 <6>[ 2.468686] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6282 11:05:04.394339 <6>[ 2.477206] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6283 11:05:04.403858 <6>[ 2.485725] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6284 11:05:04.410558 <6>[ 2.494919] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6285 11:05:04.417060 <6>[ 2.502475] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6286 11:05:04.423650 <6>[ 2.509810] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6287 11:05:04.434118 <6>[ 2.517101] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6288 11:05:04.436758 <6>[ 2.522326] hub 1-1:1.0: USB hub found
6289 11:05:04.443674 <6>[ 2.524607] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6290 11:05:04.447022 <6>[ 2.528263] hub 1-1:1.0: 3 ports detected
6291 11:05:04.453994 <6>[ 2.536166] panfrost 13040000.gpu: clock rate = 511999970
6292 11:05:04.463584 <6>[ 2.544457] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6293 11:05:04.469926 <6>[ 2.554370] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6294 11:05:04.480462 <6>[ 2.562376] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6295 11:05:04.490202 <6>[ 2.570813] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6296 11:05:04.496555 <6>[ 2.582891] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6297 11:05:04.510403 <6>[ 2.593202] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6298 11:05:04.519652 <6>[ 2.602024] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6299 11:05:04.529682 <6>[ 2.611172] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6300 11:05:04.536430 <6>[ 2.620302] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6301 11:05:04.546329 <6>[ 2.629431] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6302 11:05:04.556252 <6>[ 2.638732] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6303 11:05:04.565938 <6>[ 2.648033] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6304 11:05:04.575957 <6>[ 2.657507] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6305 11:05:04.585976 <6>[ 2.666983] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6306 11:05:04.592414 <6>[ 2.676111] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6307 11:05:04.665225 <6>[ 2.748259] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6308 11:05:04.674643 <6>[ 2.757145] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6309 11:05:04.685572 <6>[ 2.768950] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6310 11:05:04.743711 <6>[ 2.827115] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
6311 11:05:04.847259 <6>[ 2.933934] hub 1-1.1:1.0: USB hub found
6312 11:05:04.850412 <6>[ 2.938338] hub 1-1.1:1.0: 4 ports detected
6313 11:05:05.393965 <6>[ 3.463792] Console: switching to colour frame buffer device 170x48
6314 11:05:05.403764 <6>[ 3.487018] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6315 11:05:05.429820 <6>[ 3.509719] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6316 11:05:05.449769 <6>[ 3.529875] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6317 11:05:05.456315 <6>[ 3.542278] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6318 11:05:05.467338 <6>[ 3.550690] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6319 11:05:05.477045 <6>[ 3.557572] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6320 11:05:05.498529 <6>[ 3.578755] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6321 11:05:05.505537 <6>[ 3.589884] usb 1-1.2: new high-speed USB device number 4 using xhci-mtk
6322 11:05:05.511731 <6>[ 3.597366] Trying to probe devices needed for running init ...
6323 11:05:05.528327 <3>[ 3.611736] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: could not get audiosys reset:-517
6324 11:05:05.545339 <6>[ 3.625198] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6325 11:05:05.699909 <6>[ 3.783236] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
6326 11:05:05.888278 <6>[ 3.971583] r8152-cfgselector 1-1.2: reset high-speed USB device number 4 using xhci-mtk
6327 11:05:06.014383 <4>[ 4.097130] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6328 11:05:06.023505 <4>[ 4.106383] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6329 11:05:06.075981 <6>[ 4.159415] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
6330 11:05:06.079248 <6>[ 4.165666] r8152 1-1.2:1.0 eth0: v1.12.13
6331 11:05:06.105556 <6>[ 4.185359] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6332 11:05:06.213627 <4>[ 4.296783] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6333 11:05:06.225565 <4>[ 4.308826] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6334 11:05:06.269035 <6>[ 4.355828] r8152 1-1.1.1:1.0 eth1: v1.12.13
6335 11:05:06.284013 <6>[ 4.367114] usb 1-1.3: new high-speed USB device number 6 using xhci-mtk
6336 11:05:06.293956 <6>[ 4.370850] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6337 11:05:06.431486 <6>[ 4.511331] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6338 11:05:07.702088 <6>[ 5.788772] r8152 1-1.2:1.0 eth0: carrier on
6339 11:05:09.952894 <5>[ 5.811080] Sending DHCP requests .., OK
6340 11:05:09.965395 <6>[ 8.048489] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6341 11:05:09.975482 <6>[ 8.061745] IP-Config: Complete:
6342 11:05:09.990240 <6>[ 8.070113] device=eth0, hwaddr=00:e0:4c:72:3d:67, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6343 11:05:10.002749 <6>[ 8.085869] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1, domain=lava-rack, nis-domain=(none)
6344 11:05:10.015764 <6>[ 8.099140] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6345 11:05:10.023160 <6>[ 8.099148] nameserver0=192.168.201.1
6346 11:05:10.046051 <6>[ 8.132568] clk: Disabling unused clocks
6347 11:05:10.051106 <6>[ 8.140586] ALSA device list:
6348 11:05:10.059600 <6>[ 8.145962] No soundcards found.
6349 11:05:10.067592 <6>[ 8.153988] Freeing unused kernel memory: 8512K
6350 11:05:10.074331 <6>[ 8.160907] Run /init as init process
6351 11:05:10.084789 Loading, please wait...
6352 11:05:10.114533 Starting systemd-udevd version 252.22-1~deb12u1
6353 11:05:10.433258 <6>[ 8.516712] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6354 11:05:10.456209 <4>[ 8.539470] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6355 11:05:10.462653 <3>[ 8.544654] mtk-scp 10500000.scp: invalid resource
6356 11:05:10.473045 <6>[ 8.556103] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6357 11:05:10.482748 <6>[ 8.558356] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6358 11:05:10.503009 <6>[ 8.583000] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6359 11:05:10.509765 <4>[ 8.583695] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6360 11:05:10.517666 <6>[ 8.583698] remoteproc remoteproc0: scp is available
6361 11:05:10.526225 <3>[ 8.583723] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6362 11:05:10.533062 <3>[ 8.583727] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6363 11:05:10.547708 <3>[ 8.583731] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6364 11:05:10.557731 <3>[ 8.583735] elan_i2c 2-0015: Error applying setting, reverse things back
6365 11:05:10.564100 <4>[ 8.583790] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6366 11:05:10.570678 <6>[ 8.583797] remoteproc remoteproc0: powering up scp
6367 11:05:10.577490 <4>[ 8.583813] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6368 11:05:10.584398 <3>[ 8.583816] remoteproc remoteproc0: request_firmware failed: -2
6369 11:05:10.587062 <6>[ 8.594378] mc: Linux media interface: v0.10
6370 11:05:10.597761 <4>[ 8.607635] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6371 11:05:10.607751 <3>[ 8.617216] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6372 11:05:10.611009 <6>[ 8.639954] Bluetooth: Core ver 2.22
6373 11:05:10.621471 <3>[ 8.641200] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6374 11:05:10.628029 <6>[ 8.647125] r8152 1-1.1.1:1.0 enx88541f0f729c: renamed from eth1
6375 11:05:10.633939 <6>[ 8.648609] NET: Registered PF_BLUETOOTH protocol family
6376 11:05:10.637467 <6>[ 8.649230] videodev: Linux video capture interface: v2.00
6377 11:05:10.647893 <3>[ 8.656226] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6378 11:05:10.653922 <6>[ 8.656696] cs_system_cfg: CoreSight Configuration manager initialised
6379 11:05:10.660833 <6>[ 8.661243] Bluetooth: HCI device and connection manager initialized
6380 11:05:10.670745 <6>[ 8.662885] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6381 11:05:10.677218 <3>[ 8.669846] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6382 11:05:10.687580 <6>[ 8.670173] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6383 11:05:10.697741 <6>[ 8.670269] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6384 11:05:10.704553 <6>[ 8.670351] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6385 11:05:10.714111 <6>[ 8.670406] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6386 11:05:10.721008 <6>[ 8.675927] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6387 11:05:10.724302 <6>[ 8.676007] Bluetooth: HCI socket layer initialized
6388 11:05:10.730737 <6>[ 8.676013] Bluetooth: L2CAP socket layer initialized
6389 11:05:10.737610 <6>[ 8.676026] Bluetooth: SCO socket layer initialized
6390 11:05:10.743973 <3>[ 8.680669] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6391 11:05:10.753685 <5>[ 8.684688] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6392 11:05:10.760503 <6>[ 8.688141] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6393 11:05:10.766997 <5>[ 8.699688] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6394 11:05:10.777343 <5>[ 8.700123] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6395 11:05:10.783594 <3>[ 8.700173] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6396 11:05:10.793461 <4>[ 8.700192] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6397 11:05:10.796653 <6>[ 8.700198] cfg80211: failed to load regulatory.db
6398 11:05:10.806726 <6>[ 8.704271] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6399 11:05:10.813981 <3>[ 8.712577] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6400 11:05:10.823391 <6>[ 8.719011] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6401 11:05:10.829757 <3>[ 8.724350] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6402 11:05:10.839739 <6>[ 8.751608] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6403 11:05:10.850176 Begin: Loading e<3>[ 8.753644] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6404 11:05:10.856957 ssential drivers<6>[ 8.788463] Bluetooth: HCI UART driver ver 2.3
6405 11:05:10.857054 ... done.
6406 11:05:10.866811 Begi<3>[ 8.796080] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6407 11:05:10.873647 n: Running /scri<6>[ 8.803979] Bluetooth: HCI UART protocol H4 registered
6408 11:05:10.880411 pts/init-premoun<6>[ 8.805392] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6409 11:05:10.883335 t ... done.
6410 11:05:10.889983 Beg<6>[ 8.805424] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6411 11:05:10.896756 in: Mounting roo<6>[ 8.805696] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6412 11:05:10.906318 t file system ..<6>[ 8.805962] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6413 11:05:10.916369 . Begin: Running<6>[ 8.806044] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6414 11:05:10.929531 /scripts/nfs-to<3>[ 8.812297] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6415 11:05:10.929616 p ... done.
6416 11:05:10.936478 Beg<6>[ 8.817060] Bluetooth: HCI UART protocol LL registered
6417 11:05:10.946519 in: Running /scr<3>[ 8.823272] debugfs: File 'Playback' in directory 'dapm' already present!
6418 11:05:10.953306 ipts/nfs-premoun<6>[ 8.827482] Bluetooth: HCI UART protocol Three-wire (H5) registered
6419 11:05:10.959519 t ... Waiting up<6>[ 8.827834] Bluetooth: HCI UART protocol Broadcom registered
6420 11:05:10.972825 to 60 secs for <6>[ 8.833072] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6421 11:05:10.980629 <6>[ 8.833227] usbcore: registered new interface driver uvcvideo
6422 11:05:10.986724 any ethernet to <3>[ 8.836027] debugfs: File 'Capture' in directory 'dapm' already present!
6423 11:05:10.993657 become available<6>[ 8.844047] Bluetooth: HCI UART protocol QCA registered
6424 11:05:10.993766
6425 11:05:11.000052 Device /sys/cl<6>[ 8.844890] Bluetooth: hci0: setting up ROME/QCA6390
6426 11:05:11.013658 ass/net/enx88541<6>[ 8.853110] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6427 11:05:11.013737 f0f729c found
6428 11:05:11.020116 d<6>[ 8.858720] Bluetooth: HCI UART protocol Marvell registered
6429 11:05:11.020193 one.
6430 11:05:11.026461 Begin: Wai<3>[ 8.868839] thermal_sys: Failed to find 'trips' node
6431 11:05:11.039711 ting up to 180 s<6>[ 8.880617] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6432 11:05:11.046370 ecs for any netw<3>[ 8.884468] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6433 11:05:11.056357 ork device to be<6>[ 8.889566] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6434 11:05:11.066440 come available .<3>[ 8.897419] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6435 11:05:11.069551 .. done.
6436 11:05:11.076068 <4>[ 8.897424] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6437 11:05:11.086116 <6>[ 8.906273] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6438 11:05:11.093080 <3>[ 8.915103] thermal_sys: Failed to find 'trips' node
6439 11:05:11.103689 <4>[ 9.061377] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6440 11:05:11.106406 <4>[ 9.061377] Fallback method does not support PEC.
6441 11:05:11.117147 <3>[ 9.065348] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6442 11:05:11.123358 <3>[ 9.071598] Bluetooth: hci0: Frame reassembly failed (-84)
6443 11:05:11.129714 <6>[ 9.076430] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6444 11:05:11.139727 <3>[ 9.079683] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6445 11:05:11.146401 <4>[ 9.079687] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6446 11:05:11.186699 <3>[ 9.270026] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6447 11:05:11.202290 <3>[ 9.285182] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6448 11:05:11.209005 IP-Config: eth0 hardware address 00:e0:4c:72:3d:67 mtu 1500 DHCP
6449 11:05:11.231639 IP-Config: enx88541f0f729c hardware address 88:54:1f:0f:72:9c mtu 1500 DHCP
6450 11:05:11.235292 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6451 11:05:11.244958 address: 192.168.201.13 broadcast: 192.168.201.255 netmask: 255.255.255.0
6452 11:05:11.251986 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6453 11:05:11.258107 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-1
6454 11:05:11.264506 domain : lava-rack
6455 11:05:11.271287 rootserver: 19<6>[ 9.356640] Bluetooth: hci0: QCA Product ID :0x00000008
6456 11:05:11.274763 2.168.201.1 rootpath:
6457 11:05:11.278199 filenam<6>[ 9.364551] Bluetooth: hci0: QCA SOC Version :0x00000044
6458 11:05:11.281478 e :
6459 11:05:11.287702 <6>[ 9.372915] Bluetooth: hci0: QCA ROM Version :0x00000302
6460 11:05:11.287786 done.
6461 11:05:11.294642 <6>[ 9.380383] Bluetooth: hci0: QCA Patch Version:0x00000111
6462 11:05:11.304449 Begin: Running /scripts/nfs-bott<6>[ 9.388433] Bluetooth: hci0: QCA controller version 0x00440302
6463 11:05:11.304527 om ... done.
6464 11:05:11.311127 Be<6>[ 9.396548] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6465 11:05:11.324224 gin: Running /sc<4>[ 9.404989] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6466 11:05:11.334320 ripts/init-botto<3>[ 9.415574] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6467 11:05:11.334425 m ... done.
6468 11:05:11.344015 <6>[ 9.421787] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6469 11:05:11.353973 <3>[ 9.424186] Bluetooth: hci0: QCA Failed to download patch (-2)
6470 11:05:11.440084 <4>[ 9.523316] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6471 11:05:11.458195 <4>[ 9.541784] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6472 11:05:11.473927 <4>[ 9.557157] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6473 11:05:11.481539 <4>[ 9.567986] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6474 11:05:12.686893 <6>[ 10.773472] NET: Registered PF_INET6 protocol family
6475 11:05:12.699136 <6>[ 10.785746] Segment Routing with IPv6
6476 11:05:12.707966 <6>[ 10.794189] In-situ OAM (IOAM) with IPv6
6477 11:05:12.883999 <30>[ 10.944079] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6478 11:05:12.905477 <30>[ 10.991615] systemd[1]: Detected architecture arm64.
6479 11:05:12.915515
6480 11:05:12.919648 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6481 11:05:12.919744
6482 11:05:12.941297 <30>[ 11.027923] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6483 11:05:13.935481 <30>[ 12.018711] systemd[1]: Queued start job for default target graphical.target.
6484 11:05:13.977466 <30>[ 12.060685] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6485 11:05:13.990204 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6486 11:05:14.010769 <30>[ 12.093515] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6487 11:05:14.023459 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6488 11:05:14.042654 <30>[ 12.125691] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6489 11:05:14.056554 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6490 11:05:14.077239 <30>[ 12.160690] systemd[1]: Created slice user.slice - User and Session Slice.
6491 11:05:14.089422 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6492 11:05:14.111501 <30>[ 12.191673] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6493 11:05:14.124563 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6494 11:05:14.147501 <30>[ 12.227517] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6495 11:05:14.159753 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6496 11:05:14.186230 <30>[ 12.259466] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6497 11:05:14.205367 <30>[ 12.288795] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6498 11:05:14.213628 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6499 11:05:14.231920 <30>[ 12.315262] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6500 11:05:14.245021 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6501 11:05:14.264744 <30>[ 12.347319] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6502 11:05:14.279087 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6503 11:05:14.292823 <30>[ 12.379366] systemd[1]: Reached target paths.target - Path Units.
6504 11:05:14.307661 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6505 11:05:14.323929 <30>[ 12.407475] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6506 11:05:14.336618 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6507 11:05:14.352601 <30>[ 12.439247] systemd[1]: Reached target slices.target - Slice Units.
6508 11:05:14.367612 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6509 11:05:14.380441 <30>[ 12.467259] systemd[1]: Reached target swap.target - Swaps.
6510 11:05:14.391300 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6511 11:05:14.412067 <30>[ 12.495322] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6512 11:05:14.425619 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6513 11:05:14.444715 <30>[ 12.527747] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6514 11:05:14.458129 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6515 11:05:14.479168 <30>[ 12.562544] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6516 11:05:14.489998 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6517 11:05:14.510512 <30>[ 12.592822] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6518 11:05:14.523801 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6519 11:05:14.540807 <30>[ 12.624053] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6520 11:05:14.553043 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6521 11:05:14.573614 <30>[ 12.656777] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6522 11:05:14.587369 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6523 11:05:14.606439 <30>[ 12.689958] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6524 11:05:14.620005 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6525 11:05:14.636809 <30>[ 12.719922] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6526 11:05:14.650009 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6527 11:05:14.692037 <30>[ 12.775502] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6528 11:05:14.704563 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6529 11:05:14.718297 <30>[ 12.801278] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6530 11:05:14.731962 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6531 11:05:14.752315 <30>[ 12.835200] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6532 11:05:14.764451 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6533 11:05:14.787517 <30>[ 12.864137] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6534 11:05:14.836983 <30>[ 12.920322] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6535 11:05:14.849882 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6536 11:05:14.874712 <30>[ 12.957896] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6537 11:05:14.886111 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6538 11:05:14.910195 <30>[ 12.993216] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6539 11:05:14.921276 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6540 11:05:14.944565 <30>[ 13.027551] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6541 11:05:14.958069 Startin<6>[ 13.039221] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6542 11:05:14.961981 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6543 11:05:15.001521 <30>[ 13.084499] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6544 11:05:15.013763 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6545 11:05:15.042756 <30>[ 13.125762] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6546 11:05:15.053361 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6547 11:05:15.076628 <30>[ 13.159546] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6548 11:05:15.084299 Startin<6>[ 13.171154] fuse: init (API version 7.37)
6549 11:05:15.091123 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6550 11:05:15.122971 <30>[ 13.206299] systemd[1]: Starting systemd-journald.service - Journal Service...
6551 11:05:15.134837 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6552 11:05:15.176769 <30>[ 13.259936] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6553 11:05:15.188385 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6554 11:05:15.211010 <30>[ 13.291018] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6555 11:05:15.221975 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6556 11:05:15.256220 <30>[ 13.339633] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6557 11:05:15.268311 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6558 11:05:15.289111 <30>[ 13.372025] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6559 11:05:15.302788 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6560 11:05:15.309306 <3>[ 13.392655] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6561 11:05:15.325668 <3>[ 13.408443] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6562 11:05:15.332059 <30>[ 13.408903] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6563 11:05:15.346729 <3>[ 13.426901] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6564 11:05:15.357765 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6565 11:05:15.364471 <3>[ 13.447094] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6566 11:05:15.378289 <30>[ 13.460253] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6567 11:05:15.384481 <3>[ 13.462826] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6568 11:05:15.402743 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 13.484135] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6569 11:05:15.402833 File System.
6570 11:05:15.418446 <3>[ 13.501613] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6571 11:05:15.430013 <30>[ 13.510768] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6572 11:05:15.436482 <3>[ 13.518421] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6573 11:05:15.450534 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6574 11:05:15.464361 <30>[ 13.547702] systemd[1]: Started systemd-journald.service - Journal Service.
6575 11:05:15.474616 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6576 11:05:15.497001 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6577 11:05:15.522192 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6578 11:05:15.542492 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6579 11:05:15.563684 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6580 11:05:15.587384 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6581 11:05:15.611485 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6582 11:05:15.635875 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6583 11:05:15.658111 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6584 11:05:15.677525 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6585 11:05:15.701663 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6586 11:05:15.727043 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6587 11:05:15.769082 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6588 11:05:15.797617 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6589 11:05:15.825818 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6590 11:05:15.846238 <4>[ 13.922402] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6591 11:05:15.857121 <3>[ 13.940204] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6592 11:05:15.863512 <46>[ 13.947494] systemd-journald[315]: Received client request to flush runtime journal.
6593 11:05:15.874681 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6594 11:05:16.365374 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6595 11:05:16.649146 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6596 11:05:16.903148 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6597 11:05:16.922081 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6598 11:05:16.941201 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6599 11:05:16.966476 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6600 11:05:17.013502 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6601 11:05:17.317175 <4>[ 15.403166] power_supply_show_property: 3 callbacks suppressed
6602 11:05:17.330914 <3>[ 15.403183] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6603 11:05:17.360230 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create Syst<3>[ 15.440495] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6604 11:05:17.360341 em Users.
6605 11:05:17.376928 <3>[ 15.459604] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6606 11:05:17.396402 <3>[ 15.479364] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6607 11:05:17.403407 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6608 11:05:17.414889 <3>[ 15.497698] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6609 11:05:17.431600 <3>[ 15.514430] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6610 11:05:17.449997 <3>[ 15.532841] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6611 11:05:17.467978 <3>[ 15.550763] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6612 11:05:17.484250 <3>[ 15.566999] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6613 11:05:17.499813 <3>[ 15.582853] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6614 11:05:17.511119 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6615 11:05:17.530547 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6616 11:05:17.554039 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6617 11:05:17.573658 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6618 11:05:17.621042 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6619 11:05:17.645535 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6620 11:05:17.885068 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6621 11:05:17.932620 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6622 11:05:17.949104 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6623 11:05:17.994033 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6624 11:05:18.168533 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6625 11:05:18.190281 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6626 11:05:18.382453 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6627 11:05:18.404698 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6628 11:05:18.424606 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6629 11:05:18.470557 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6630 11:05:18.562291 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6631 11:05:18.601086 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6632 11:05:18.644501 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6633 11:05:18.722422 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6634 11:05:18.741005 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6635 11:05:18.761082 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6636 11:05:18.784463 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6637 11:05:18.804843 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6638 11:05:18.845626 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6639 11:05:18.868548 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6640 11:05:18.887836 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6641 11:05:18.908015 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6642 11:05:18.927575 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6643 11:05:18.947965 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6644 11:05:18.966537 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6645 11:05:18.990111 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6646 11:05:19.010801 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6647 11:05:19.028991 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6648 11:05:19.046753 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6649 11:05:19.068241 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6650 11:05:19.084736 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6651 11:05:19.100456 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6652 11:05:19.124399 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6653 11:05:19.141319 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6654 11:05:19.158674 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6655 11:05:19.205310 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6656 11:05:19.225586 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6657 11:05:19.256237 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6658 11:05:19.300230 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6659 11:05:19.320362 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6660 11:05:19.339566 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6661 11:05:19.357626 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6662 11:05:19.506941 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6663 11:05:19.549108 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6664 11:05:19.611471 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6665 11:05:19.627246 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6666 11:05:19.646748 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6667 11:05:19.682179 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6668 11:05:19.705016 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6669 11:05:19.727896 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6670 11:05:19.750104 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6671 11:05:19.793264 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6672 11:05:19.844315 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6673 11:05:19.909103
6674 11:05:19.912500 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6675 11:05:19.912596
6676 11:05:19.915816 debian-bookworm-arm64 login: root (automatic login)
6677 11:05:19.915934
6678 11:05:20.185453 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
6679 11:05:20.185572
6680 11:05:20.192351 The programs included with the Debian GNU/Linux system are free software;
6681 11:05:20.198718 the exact distribution terms for each program are described in the
6682 11:05:20.202057 individual files in /usr/share/doc/*/copyright.
6683 11:05:20.202132
6684 11:05:20.208473 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6685 11:05:20.211796 permitted by applicable law.
6686 11:05:21.318484 Matched prompt #10: / #
6688 11:05:21.318741 Setting prompt string to ['/ #']
6689 11:05:21.318833 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6691 11:05:21.319028 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6692 11:05:21.319111 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
6693 11:05:21.319192 Setting prompt string to ['/ #']
6694 11:05:21.319250 Forcing a shell prompt, looking for ['/ #']
6695 11:05:21.319306 Sending line: ''
6697 11:05:21.369689 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6698 11:05:21.369773 Waiting using forced prompt support (timeout 00:02:30)
6699 11:05:21.374752 / #
6700 11:05:21.375030 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6701 11:05:21.375119 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
6702 11:05:21.375204 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786794/extract-nfsrootfs-gd9vxcky'"
6704 11:05:21.480884 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786794/extract-nfsrootfs-gd9vxcky'
6705 11:05:21.481141 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
6707 11:05:21.586960 / # export NFS_SERVER_IP='192.168.201.1'
6708 11:05:21.587245 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6709 11:05:21.587371 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
6710 11:05:21.587455 end: 2 depthcharge-action (duration 00:01:15) [common]
6711 11:05:21.587539 start: 3 lava-test-retry (timeout 00:07:40) [common]
6712 11:05:21.587649 start: 3.1 lava-test-shell (timeout 00:07:40) [common]
6713 11:05:21.587719 Using namespace: common
6714 11:05:21.587783 Sending line: '#'
6716 11:05:21.688302 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6717 11:05:21.693671 / # #
6718 11:05:21.693940 Using /lava-14786794
6719 11:05:21.694004 Sending line: 'export SHELL=/bin/bash'
6721 11:05:21.799874 / # export SHELL=/bin/bash
6722 11:05:21.800141 Sending line: '. /lava-14786794/environment'
6724 11:05:21.906055 / # . /lava-14786794/environment
6725 11:05:21.910216 Sending line: '/lava-14786794/bin/lava-test-runner /lava-14786794/0'
6727 11:05:22.010679 Test shell timeout: 10s (minimum of the action and connection timeout)
6728 11:05:22.015380 / # /lava-14786794/bin/lava-test-runner /lava-14786794/0
6729 11:05:22.231782 + export TESTRUN_ID=0_timesync-off
6730 11:05:22.235400 + TESTRUN_ID=0_timesync-off
6731 11:05:22.238225 + cd /lava-14786794/0/tests/0_timesync-off
6732 11:05:22.241471 ++ cat uuid
6733 11:05:22.241579 + UUID=14786794_1.6.2.3.1
6734 11:05:22.244808 + set +x
6735 11:05:22.247923 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14786794_1.6.2.3.1>
6736 11:05:22.248217 Received signal: <STARTRUN> 0_timesync-off 14786794_1.6.2.3.1
6737 11:05:22.248323 Starting test lava.0_timesync-off (14786794_1.6.2.3.1)
6738 11:05:22.248436 Skipping test definition patterns.
6739 11:05:22.251495 + systemctl stop systemd-timesyncd
6740 11:05:22.318146 + set +x
6741 11:05:22.321413 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14786794_1.6.2.3.1>
6742 11:05:22.321687 Received signal: <ENDRUN> 0_timesync-off 14786794_1.6.2.3.1
6743 11:05:22.321790 Ending use of test pattern.
6744 11:05:22.321872 Ending test lava.0_timesync-off (14786794_1.6.2.3.1), duration 0.07
6746 11:05:22.377838 + export TESTRUN_ID=1_kselftest-arm64
6747 11:05:22.377996 + TESTRUN_ID=1_kselftest-arm64
6748 11:05:22.384739 + cd /lava-14786794/0/tests/1_kselftest-arm64
6749 11:05:22.384851 ++ cat uuid
6750 11:05:22.387556 + UUID=14786794_1.6.2.3.5
6751 11:05:22.387637 + set +x
6752 11:05:22.390949 Received signal: <STARTRUN> 1_kselftest-arm64 14786794_1.6.2.3.5
6753 11:05:22.391031 Starting test lava.1_kselftest-arm64 (14786794_1.6.2.3.5)
6754 11:05:22.391139 Skipping test definition patterns.
6755 11:05:22.394400 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14786794_1.6.2.3.5>
6756 11:05:22.394491 + cd ./automated/linux/kselftest/
6757 11:05:22.421020 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
6758 11:05:22.449087 INFO: install_deps skipped
6759 11:05:22.941564 --2024-07-10 11:05:22-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
6760 11:05:22.953996 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6761 11:05:23.087368 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6762 11:05:23.221605 HTTP request sent, awaiting response... 200 OK
6763 11:05:23.224366 Length: 1919896 (1.8M) [application/octet-stream]
6764 11:05:23.228139 Saving to: 'kselftest_armhf.tar.gz'
6765 11:05:23.228235
6766 11:05:23.228299
6767 11:05:23.486971 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6768 11:05:23.755151 kselftest_armhf.tar 2%[ ] 43.57K 164KB/s
6769 11:05:24.021375 kselftest_armhf.tar 11%[=> ] 217.50K 408KB/s
6770 11:05:24.254658 kselftest_armhf.tar 47%[========> ] 892.00K 1.09MB/s
6771 11:05:24.519977 kselftest_armhf.tar 72%[=============> ] 1.33M 1.29MB/s
6772 11:05:24.559967 kselftest_armhf.tar 91%[=================> ] 1.67M 1.28MB/s
6773 11:05:24.566388 kselftest_armhf.tar 100%[===================>] 1.83M 1.37MB/s in 1.3s
6774 11:05:24.566491
6775 11:05:24.735325 2024-07-10 11:05:24 (1.37 MB/s) - 'kselftest_armhf.tar.gz' saved [1919896/1919896]
6776 11:05:24.735464
6777 11:05:31.166665 skiplist:
6778 11:05:31.170028 ========================================
6779 11:05:31.172934 ========================================
6780 11:05:31.218219 arm64:tags_test
6781 11:05:31.220923 arm64:run_tags_test.sh
6782 11:05:31.221026 arm64:fake_sigreturn_bad_magic
6783 11:05:31.224397 arm64:fake_sigreturn_bad_size
6784 11:05:31.227883 arm64:fake_sigreturn_bad_size_for_magic0
6785 11:05:31.231683 arm64:fake_sigreturn_duplicated_fpsimd
6786 11:05:31.234068 arm64:fake_sigreturn_misaligned_sp
6787 11:05:31.238194 arm64:fake_sigreturn_missing_fpsimd
6788 11:05:31.240933 arm64:fake_sigreturn_sme_change_vl
6789 11:05:31.244482 arm64:fake_sigreturn_sve_change_vl
6790 11:05:31.247560 arm64:mangle_pstate_invalid_compat_toggle
6791 11:05:31.250783 arm64:mangle_pstate_invalid_daif_bits
6792 11:05:31.254189 arm64:mangle_pstate_invalid_mode_el1h
6793 11:05:31.261256 arm64:mangle_pstate_invalid_mode_el1t
6794 11:05:31.264027 arm64:mangle_pstate_invalid_mode_el2h
6795 11:05:31.267648 arm64:mangle_pstate_invalid_mode_el2t
6796 11:05:31.270971 arm64:mangle_pstate_invalid_mode_el3h
6797 11:05:31.274157 arm64:mangle_pstate_invalid_mode_el3t
6798 11:05:31.274270 arm64:sme_trap_no_sm
6799 11:05:31.277477 arm64:sme_trap_non_streaming
6800 11:05:31.277571 arm64:sme_trap_za
6801 11:05:31.280749 arm64:sme_vl
6802 11:05:31.280842 arm64:ssve_regs
6803 11:05:31.284021 arm64:sve_regs
6804 11:05:31.284117 arm64:sve_vl
6805 11:05:31.287476 arm64:za_no_regs
6806 11:05:31.287572 arm64:za_regs
6807 11:05:31.287655 arm64:pac
6808 11:05:31.291262 arm64:fp-stress
6809 11:05:31.291355 arm64:sve-ptrace
6810 11:05:31.294087 arm64:sve-probe-vls
6811 11:05:31.294189 arm64:vec-syscfg
6812 11:05:31.297577 arm64:za-fork
6813 11:05:31.297680 arm64:za-ptrace
6814 11:05:31.300663 arm64:check_buffer_fill
6815 11:05:31.300755 arm64:check_child_memory
6816 11:05:31.304436 arm64:check_gcr_el1_cswitch
6817 11:05:31.307652 arm64:check_ksm_options
6818 11:05:31.307750 arm64:check_mmap_options
6819 11:05:31.310801 arm64:check_prctl
6820 11:05:31.313945 arm64:check_tags_inclusion
6821 11:05:31.314047 arm64:check_user_mem
6822 11:05:31.317260 arm64:btitest
6823 11:05:31.317353 arm64:nobtitest
6824 11:05:31.317441 arm64:hwcap
6825 11:05:31.320642 arm64:ptrace
6826 11:05:31.320736 arm64:syscall-abi
6827 11:05:31.324039 arm64:tpidr2
6828 11:05:31.327518 ============== Tests to run ===============
6829 11:05:31.327626 arm64:tags_test
6830 11:05:31.330639 arm64:run_tags_test.sh
6831 11:05:31.333571 arm64:fake_sigreturn_bad_magic
6832 11:05:31.337275 arm64:fake_sigreturn_bad_size
6833 11:05:31.340608 arm64:fake_sigreturn_bad_size_for_magic0
6834 11:05:31.343724 arm64:fake_sigreturn_duplicated_fpsimd
6835 11:05:31.346891 arm64:fake_sigreturn_misaligned_sp
6836 11:05:31.350361 arm64:fake_sigreturn_missing_fpsimd
6837 11:05:31.353658 arm64:fake_sigreturn_sme_change_vl
6838 11:05:31.356986 arm64:fake_sigreturn_sve_change_vl
6839 11:05:31.360566 arm64:mangle_pstate_invalid_compat_toggle
6840 11:05:31.363598 arm64:mangle_pstate_invalid_daif_bits
6841 11:05:31.366530 arm64:mangle_pstate_invalid_mode_el1h
6842 11:05:31.370091 arm64:mangle_pstate_invalid_mode_el1t
6843 11:05:31.373326 arm64:mangle_pstate_invalid_mode_el2h
6844 11:05:31.376407 arm64:mangle_pstate_invalid_mode_el2t
6845 11:05:31.379998 arm64:mangle_pstate_invalid_mode_el3h
6846 11:05:31.383286 arm64:mangle_pstate_invalid_mode_el3t
6847 11:05:31.383391 arm64:sme_trap_no_sm
6848 11:05:31.386385 arm64:sme_trap_non_streaming
6849 11:05:31.389614 arm64:sme_trap_za
6850 11:05:31.389714 arm64:sme_vl
6851 11:05:31.393061 arm64:ssve_regs
6852 11:05:31.393189 arm64:sve_regs
6853 11:05:31.393278 arm64:sve_vl
6854 11:05:31.396750 arm64:za_no_regs
6855 11:05:31.396851 arm64:za_regs
6856 11:05:31.399698 arm64:pac
6857 11:05:31.399797 arm64:fp-stress
6858 11:05:31.399887 arm64:sve-ptrace
6859 11:05:31.402829 arm64:sve-probe-vls
6860 11:05:31.402931 arm64:vec-syscfg
6861 11:05:31.406444 arm64:za-fork
6862 11:05:31.406543 arm64:za-ptrace
6863 11:05:31.409528 arm64:check_buffer_fill
6864 11:05:31.413102 arm64:check_child_memory
6865 11:05:31.413228 arm64:check_gcr_el1_cswitch
6866 11:05:31.416405 arm64:check_ksm_options
6867 11:05:31.419727 arm64:check_mmap_options
6868 11:05:31.419834 arm64:check_prctl
6869 11:05:31.423390 arm64:check_tags_inclusion
6870 11:05:31.426149 arm64:check_user_mem
6871 11:05:31.426252 arm64:btitest
6872 11:05:31.426336 arm64:nobtitest
6873 11:05:31.429271 arm64:hwcap
6874 11:05:31.429376 arm64:ptrace
6875 11:05:31.432674 arm64:syscall-abi
6876 11:05:31.432777 arm64:tpidr2
6877 11:05:31.436073 ===========End Tests to run ===============
6878 11:05:31.439407 shardfile-arm64 pass
6879 11:05:31.666638 <12>[ 29.752613] kselftest: Running tests in arm64
6880 11:05:31.675559 TAP version 13
6881 11:05:31.688751 1..48
6882 11:05:31.706458 # selftests: arm64: tags_test
6883 11:05:32.156968 ok 1 selftests: arm64: tags_test
6884 11:05:32.170620 # selftests: arm64: run_tags_test.sh
6885 11:05:32.238835 # --------------------
6886 11:05:32.242193 # running tags test
6887 11:05:32.242318 # --------------------
6888 11:05:32.245519 # [PASS]
6889 11:05:32.248603 ok 2 selftests: arm64: run_tags_test.sh
6890 11:05:32.261919 # selftests: arm64: fake_sigreturn_bad_magic
6891 11:05:32.345019 # Registered handlers for all signals.
6892 11:05:32.345177 # Detected MINSTKSIGSZ:4720
6893 11:05:32.348097 # Testcase initialized.
6894 11:05:32.351512 # uc context validated.
6895 11:05:32.355400 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6896 11:05:32.358467 # Handled SIG_COPYCTX
6897 11:05:32.358537 # Available space:3568
6898 11:05:32.364795 # Using badly built context - ERR: BAD MAGIC !
6899 11:05:32.371417 # SIG_OK -- SP:0xFFFFF06E81F0 si_addr@:0xfffff06e81f0 si_code:2 token@:0xfffff06e6f90 offset:-4704
6900 11:05:32.375001 # ==>> completed. PASS(1)
6901 11:05:32.381586 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
6902 11:05:32.388041 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF06E6F90
6903 11:05:32.394600 ok 3 selftests: arm64: fake_sigreturn_bad_magic
6904 11:05:32.397935 # selftests: arm64: fake_sigreturn_bad_size
6905 11:05:32.433288 # Registered handlers for all signals.
6906 11:05:32.433396 # Detected MINSTKSIGSZ:4720
6907 11:05:32.436501 # Testcase initialized.
6908 11:05:32.439828 # uc context validated.
6909 11:05:32.442942 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6910 11:05:32.446585 # Handled SIG_COPYCTX
6911 11:05:32.446661 # Available space:3568
6912 11:05:32.450140 # uc context validated.
6913 11:05:32.456580 # Using badly built context - ERR: Bad size for esr_context
6914 11:05:32.463464 # SIG_OK -- SP:0xFFFFCF92A130 si_addr@:0xffffcf92a130 si_code:2 token@:0xffffcf928ed0 offset:-4704
6915 11:05:32.466642 # ==>> completed. PASS(1)
6916 11:05:32.472884 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
6917 11:05:32.479626 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCF928ED0
6918 11:05:32.482837 ok 4 selftests: arm64: fake_sigreturn_bad_size
6919 11:05:32.489450 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
6920 11:05:32.536444 # Registered handlers for all signals.
6921 11:05:32.536567 # Detected MINSTKSIGSZ:4720
6922 11:05:32.539592 # Testcase initialized.
6923 11:05:32.543004 # uc context validated.
6924 11:05:32.546512 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6925 11:05:32.549770 # Handled SIG_COPYCTX
6926 11:05:32.549865 # Available space:3568
6927 11:05:32.556311 # Using badly built context - ERR: Bad size for terminator
6928 11:05:32.566279 # SIG_OK -- SP:0xFFFFF5F2E290 si_addr@:0xfffff5f2e290 si_code:2 token@:0xfffff5f2d030 offset:-4704
6929 11:05:32.566356 # ==>> completed. PASS(1)
6930 11:05:32.576217 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
6931 11:05:32.583129 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF5F2D030
6932 11:05:32.586171 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
6933 11:05:32.592647 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
6934 11:05:32.610955 # Registered handlers for all signals.
6935 11:05:32.611041 # Detected MINSTKSIGSZ:4720
6936 11:05:32.614287 # Testcase initialized.
6937 11:05:32.617463 # uc context validated.
6938 11:05:32.620788 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6939 11:05:32.624085 # Handled SIG_COPYCTX
6940 11:05:32.624185 # Available space:3568
6941 11:05:32.630559 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
6942 11:05:32.640567 # SIG_OK -- SP:0xFFFFF499F380 si_addr@:0xfffff499f380 si_code:2 token@:0xfffff499e120 offset:-4704
6943 11:05:32.640649 # ==>> completed. PASS(1)
6944 11:05:32.650397 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
6945 11:05:32.657113 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF499E120
6946 11:05:32.660503 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
6947 11:05:32.666681 # selftests: arm64: fake_sigreturn_misaligned_sp
6948 11:05:32.710308 # Registered handlers for all signals.
6949 11:05:32.710445 # Detected MINSTKSIGSZ:4720
6950 11:05:32.714161 # Testcase initialized.
6951 11:05:32.716937 # uc context validated.
6952 11:05:32.719935 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6953 11:05:32.723422 # Handled SIG_COPYCTX
6954 11:05:32.730056 # SIG_OK -- SP:0xFFFFEEB59F53 si_addr@:0xffffeeb59f53 si_code:2 token@:0xffffeeb59f53 offset:0
6955 11:05:32.733352 # ==>> completed. PASS(1)
6956 11:05:32.740195 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
6957 11:05:32.746688 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEEB59F53
6958 11:05:32.753459 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
6959 11:05:32.756399 # selftests: arm64: fake_sigreturn_missing_fpsimd
6960 11:05:32.797886 # Registered handlers for all signals.
6961 11:05:32.798028 # Detected MINSTKSIGSZ:4720
6962 11:05:32.801325 # Testcase initialized.
6963 11:05:32.804496 # uc context validated.
6964 11:05:32.808012 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6965 11:05:32.811050 # Handled SIG_COPYCTX
6966 11:05:32.814370 # Mangling template header. Spare space:4096
6967 11:05:32.817341 # Using badly built context - ERR: Missing FPSIMD
6968 11:05:32.827474 # SIG_OK -- SP:0xFFFFC4F1AFB0 si_addr@:0xffffc4f1afb0 si_code:2 token@:0xffffc4f19d50 offset:-4704
6969 11:05:32.830703 # ==>> completed. PASS(1)
6970 11:05:32.837380 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
6971 11:05:32.844333 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC4F19D50
6972 11:05:32.847833 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
6973 11:05:32.853964 # selftests: arm64: fake_sigreturn_sme_change_vl
6974 11:05:32.904872 # Registered handlers for all signals.
6975 11:05:32.905000 # Detected MINSTKSIGSZ:4720
6976 11:05:32.907892 # ==>> completed. SKIP.
6977 11:05:32.914135 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
6978 11:05:32.917223 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
6979 11:05:32.926099 # selftests: arm64: fake_sigreturn_sve_change_vl
6980 11:05:32.980328 # Registered handlers for all signals.
6981 11:05:32.980442 # Detected MINSTKSIGSZ:4720
6982 11:05:32.983904 # ==>> completed. SKIP.
6983 11:05:32.990127 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
6984 11:05:32.993522 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
6985 11:05:33.001464 # selftests: arm64: mangle_pstate_invalid_compat_toggle
6986 11:05:33.064262 # Registered handlers for all signals.
6987 11:05:33.064372 # Detected MINSTKSIGSZ:4720
6988 11:05:33.067766 # Testcase initialized.
6989 11:05:33.070770 # uc context validated.
6990 11:05:33.070866 # Handled SIG_TRIG
6991 11:05:33.080572 # SIG_OK -- SP:0xFFFFE62A7240 si_addr@:0xffffe62a7240 si_code:2 token@:(nil) offset:-281474543284800
6992 11:05:33.083818 # ==>> completed. PASS(1)
6993 11:05:33.090510 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
6994 11:05:33.097267 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
6995 11:05:33.100507 # selftests: arm64: mangle_pstate_invalid_daif_bits
6996 11:05:33.159288 # Registered handlers for all signals.
6997 11:05:33.159400 # Detected MINSTKSIGSZ:4720
6998 11:05:33.162656 # Testcase initialized.
6999 11:05:33.165378 # uc context validated.
7000 11:05:33.165476 # Handled SIG_TRIG
7001 11:05:33.175368 # SIG_OK -- SP:0xFFFFCD000B60 si_addr@:0xffffcd000b60 si_code:2 token@:(nil) offset:-281474121075552
7002 11:05:33.178698 # ==>> completed. PASS(1)
7003 11:05:33.185348 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
7004 11:05:33.189321 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
7005 11:05:33.195120 # selftests: arm64: mangle_pstate_invalid_mode_el1h
7006 11:05:33.253722 # Registered handlers for all signals.
7007 11:05:33.253854 # Detected MINSTKSIGSZ:4720
7008 11:05:33.257687 # Testcase initialized.
7009 11:05:33.260837 # uc context validated.
7010 11:05:33.260923 # Handled SIG_TRIG
7011 11:05:33.270687 # SIG_OK -- SP:0xFFFFC607FBC0 si_addr@:0xffffc607fbc0 si_code:2 token@:(nil) offset:-281474004155328
7012 11:05:33.274300 # ==>> completed. PASS(1)
7013 11:05:33.280729 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
7014 11:05:33.283700 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
7015 11:05:33.290239 # selftests: arm64: mangle_pstate_invalid_mode_el1t
7016 11:05:33.323342 # Registered handlers for all signals.
7017 11:05:33.323452 # Detected MINSTKSIGSZ:4720
7018 11:05:33.326361 # Testcase initialized.
7019 11:05:33.329587 # uc context validated.
7020 11:05:33.329666 # Handled SIG_TRIG
7021 11:05:33.339759 # SIG_OK -- SP:0xFFFFD03B12A0 si_addr@:0xffffd03b12a0 si_code:2 token@:(nil) offset:-281474175275680
7022 11:05:33.342939 # ==>> completed. PASS(1)
7023 11:05:33.349328 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
7024 11:05:33.352909 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
7025 11:05:33.360752 # selftests: arm64: mangle_pstate_invalid_mode_el2h
7026 11:05:33.426663 # Registered handlers for all signals.
7027 11:05:33.426785 # Detected MINSTKSIGSZ:4720
7028 11:05:33.429876 # Testcase initialized.
7029 11:05:33.433457 # uc context validated.
7030 11:05:33.433533 # Handled SIG_TRIG
7031 11:05:33.443356 # SIG_OK -- SP:0xFFFFE79DC180 si_addr@:0xffffe79dc180 si_code:2 token@:(nil) offset:-281474567618944
7032 11:05:33.446089 # ==>> completed. PASS(1)
7033 11:05:33.452698 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
7034 11:05:33.456018 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
7035 11:05:33.462582 # selftests: arm64: mangle_pstate_invalid_mode_el2t
7036 11:05:33.519506 # Registered handlers for all signals.
7037 11:05:33.519630 # Detected MINSTKSIGSZ:4720
7038 11:05:33.522531 # Testcase initialized.
7039 11:05:33.525933 # uc context validated.
7040 11:05:33.526012 # Handled SIG_TRIG
7041 11:05:33.535865 # SIG_OK -- SP:0xFFFFF0106FE0 si_addr@:0xfffff0106fe0 si_code:2 token@:(nil) offset:-281474709352416
7042 11:05:33.539310 # ==>> completed. PASS(1)
7043 11:05:33.545958 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
7044 11:05:33.548956 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
7045 11:05:33.555476 # selftests: arm64: mangle_pstate_invalid_mode_el3h
7046 11:05:33.633066 # Registered handlers for all signals.
7047 11:05:33.633224 # Detected MINSTKSIGSZ:4720
7048 11:05:33.636352 # Testcase initialized.
7049 11:05:33.639557 # uc context validated.
7050 11:05:33.639657 # Handled SIG_TRIG
7051 11:05:33.649537 # SIG_OK -- SP:0xFFFFF673BFC0 si_addr@:0xfffff673bfc0 si_code:2 token@:(nil) offset:-281474816524224
7052 11:05:33.653019 # ==>> completed. PASS(1)
7053 11:05:33.659570 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
7054 11:05:33.662769 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
7055 11:05:33.669552 # selftests: arm64: mangle_pstate_invalid_mode_el3t
7056 11:05:33.733399 # Registered handlers for all signals.
7057 11:05:33.733526 # Detected MINSTKSIGSZ:4720
7058 11:05:33.736939 # Testcase initialized.
7059 11:05:33.740653 # uc context validated.
7060 11:05:33.740731 # Handled SIG_TRIG
7061 11:05:33.749852 # SIG_OK -- SP:0xFFFFC147B4F0 si_addr@:0xffffc147b4f0 si_code:2 token@:(nil) offset:-281473924445424
7062 11:05:33.753368 # ==>> completed. PASS(1)
7063 11:05:33.760006 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
7064 11:05:33.763163 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
7065 11:05:33.766213 # selftests: arm64: sme_trap_no_sm
7066 11:05:33.829509 # Registered handlers for all signals.
7067 11:05:33.829652 # Detected MINSTKSIGSZ:4720
7068 11:05:33.832804 # ==>> completed. SKIP.
7069 11:05:33.843001 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
7070 11:05:33.846131 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
7071 11:05:33.849338 # selftests: arm64: sme_trap_non_streaming
7072 11:05:33.902008 # Registered handlers for all signals.
7073 11:05:33.902176 # Detected MINSTKSIGSZ:4720
7074 11:05:33.905041 # ==>> completed. SKIP.
7075 11:05:33.915095 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
7076 11:05:33.921469 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
7077 11:05:33.924748 # selftests: arm64: sme_trap_za
7078 11:05:33.985534 # Registered handlers for all signals.
7079 11:05:33.985660 # Detected MINSTKSIGSZ:4720
7080 11:05:33.988734 # Testcase initialized.
7081 11:05:33.998534 # SIG_OK -- SP:0xFFFFCF210280 si_addr@:0xaaaae9de2480 si_code:1 token@:(nil) offset:-187651044811904
7082 11:05:33.998619 # ==>> completed. PASS(1)
7083 11:05:34.008642 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
7084 11:05:34.011837 ok 21 selftests: arm64: sme_trap_za
7085 11:05:34.011919 # selftests: arm64: sme_vl
7086 11:05:34.072909 # Registered handlers for all signals.
7087 11:05:34.073035 # Detected MINSTKSIGSZ:4720
7088 11:05:34.075966 # ==>> completed. SKIP.
7089 11:05:34.083016 # # SME VL :: Check that we get the right SME VL reported
7090 11:05:34.085712 ok 22 selftests: arm64: sme_vl # SKIP
7091 11:05:34.091999 # selftests: arm64: ssve_regs
7092 11:05:34.153459 # Registered handlers for all signals.
7093 11:05:34.153584 # Detected MINSTKSIGSZ:4720
7094 11:05:34.156891 # ==>> completed. SKIP.
7095 11:05:34.163579 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
7096 11:05:34.170262 ok 23 selftests: arm64: ssve_regs # SKIP
7097 11:05:34.173594 # selftests: arm64: sve_regs
7098 11:05:34.239125 # Registered handlers for all signals.
7099 11:05:34.239252 # Detected MINSTKSIGSZ:4720
7100 11:05:34.243177 # ==>> completed. SKIP.
7101 11:05:34.248969 # # SVE registers :: Check that we get the right SVE registers reported
7102 11:05:34.252529 ok 24 selftests: arm64: sve_regs # SKIP
7103 11:05:34.258397 # selftests: arm64: sve_vl
7104 11:05:34.320133 # Registered handlers for all signals.
7105 11:05:34.320252 # Detected MINSTKSIGSZ:4720
7106 11:05:34.323750 # ==>> completed. SKIP.
7107 11:05:34.330515 # # SVE VL :: Check that we get the right SVE VL reported
7108 11:05:34.333049 ok 25 selftests: arm64: sve_vl # SKIP
7109 11:05:34.340753 # selftests: arm64: za_no_regs
7110 11:05:34.430142 # Registered handlers for all signals.
7111 11:05:34.430254 # Detected MINSTKSIGSZ:4720
7112 11:05:34.432679 # ==>> completed. SKIP.
7113 11:05:34.440099 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
7114 11:05:34.443051 ok 26 selftests: arm64: za_no_regs # SKIP
7115 11:05:34.446693 # selftests: arm64: za_regs
7116 11:05:34.530845 # Registered handlers for all signals.
7117 11:05:34.530973 # Detected MINSTKSIGSZ:4720
7118 11:05:34.534323 # ==>> completed. SKIP.
7119 11:05:34.541051 # # ZA register :: Check that we get the right ZA registers reported
7120 11:05:34.544429 ok 27 selftests: arm64: za_regs # SKIP
7121 11:05:34.550134 # selftests: arm64: pac
7122 11:05:34.616982 # TAP version 13
7123 11:05:34.617132 # 1..7
7124 11:05:34.620322 # # Starting 7 tests from 1 test cases.
7125 11:05:34.623650 # # RUN global.corrupt_pac ...
7126 11:05:34.626683 # # SKIP PAUTH not enabled
7127 11:05:34.630107 # # OK global.corrupt_pac
7128 11:05:34.633373 # ok 1 # SKIP PAUTH not enabled
7129 11:05:34.640169 # # RUN global.pac_instructions_not_nop ...
7130 11:05:34.643529 # # SKIP PAUTH not enabled
7131 11:05:34.646627 # # OK global.pac_instructions_not_nop
7132 11:05:34.649782 # ok 2 # SKIP PAUTH not enabled
7133 11:05:34.656625 # # RUN global.pac_instructions_not_nop_generic ...
7134 11:05:34.660450 # # SKIP Generic PAUTH not enabled
7135 11:05:34.666455 # # OK global.pac_instructions_not_nop_generic
7136 11:05:34.669835 # ok 3 # SKIP Generic PAUTH not enabled
7137 11:05:34.672843 # # RUN global.single_thread_different_keys ...
7138 11:05:34.676309 # # SKIP PAUTH not enabled
7139 11:05:34.682880 # # OK global.single_thread_different_keys
7140 11:05:34.686430 # ok 4 # SKIP PAUTH not enabled
7141 11:05:34.689496 # # RUN global.exec_changed_keys ...
7142 11:05:34.692922 # # SKIP PAUTH not enabled
7143 11:05:34.696174 # # OK global.exec_changed_keys
7144 11:05:34.699553 # ok 5 # SKIP PAUTH not enabled
7145 11:05:34.702665 # # RUN global.context_switch_keep_keys ...
7146 11:05:34.706243 # # SKIP PAUTH not enabled
7147 11:05:34.712752 # # OK global.context_switch_keep_keys
7148 11:05:34.716183 # ok 6 # SKIP PAUTH not enabled
7149 11:05:34.719487 # # RUN global.context_switch_keep_keys_generic ...
7150 11:05:34.722973 # # SKIP Generic PAUTH not enabled
7151 11:05:34.729666 # # OK global.context_switch_keep_keys_generic
7152 11:05:34.732945 # ok 7 # SKIP Generic PAUTH not enabled
7153 11:05:34.736279 # # PASSED: 7 / 7 tests passed.
7154 11:05:34.739465 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
7155 11:05:34.742793 ok 28 selftests: arm64: pac
7156 11:05:34.745686 # selftests: arm64: fp-stress
7157 11:05:41.954539 <6>[ 40.043349] vaux18: disabling
7158 11:05:41.957799 <6>[ 40.046722] vio28: disabling
7159 11:05:44.709435 # TAP version 13
7160 11:05:44.709548 # 1..16
7161 11:05:44.712484 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
7162 11:05:44.712560 # # Will run for 10s
7163 11:05:44.716007 # # Started FPSIMD-0-0
7164 11:05:44.719283 # # Started FPSIMD-0-1
7165 11:05:44.719358 # # Started FPSIMD-1-0
7166 11:05:44.722571 # # Started FPSIMD-1-1
7167 11:05:44.725749 # # Started FPSIMD-2-0
7168 11:05:44.725825 # # Started FPSIMD-2-1
7169 11:05:44.728722 # # Started FPSIMD-3-0
7170 11:05:44.732049 # # Started FPSIMD-3-1
7171 11:05:44.732124 # # Started FPSIMD-4-0
7172 11:05:44.735492 # # Started FPSIMD-4-1
7173 11:05:44.735569 # # Started FPSIMD-5-0
7174 11:05:44.739001 # # Started FPSIMD-5-1
7175 11:05:44.742601 # # Started FPSIMD-6-0
7176 11:05:44.742676 # # Started FPSIMD-6-1
7177 11:05:44.745958 # # Started FPSIMD-7-0
7178 11:05:44.748835 # # Started FPSIMD-7-1
7179 11:05:44.752109 # # FPSIMD-1-0: Vector length: 128 bits
7180 11:05:44.752186 # # FPSIMD-1-0: PID: 1187
7181 11:05:44.756202 # # FPSIMD-1-1: Vector length: 128 bits
7182 11:05:44.758823 # # FPSIMD-1-1: PID: 1188
7183 11:05:44.762266 # # FPSIMD-2-1: Vector length: 128 bits
7184 11:05:44.765368 # # FPSIMD-2-1: PID: 1190
7185 11:05:44.768696 # # FPSIMD-2-0: Vector length: 128 bits
7186 11:05:44.772278 # # FPSIMD-2-0: PID: 1189
7187 11:05:44.775607 # # FPSIMD-0-0: Vector length: 128 bits
7188 11:05:44.778879 # # FPSIMD-0-0: PID: 1185
7189 11:05:44.782342 # # FPSIMD-0-1: Vector length: 128 bits
7190 11:05:44.782419 # # FPSIMD-0-1: PID: 1186
7191 11:05:44.785952 # # FPSIMD-3-1: Vector length: 128 bits
7192 11:05:44.789038 # # FPSIMD-3-1: PID: 1192
7193 11:05:44.792109 # # FPSIMD-7-1: Vector length: 128 bits
7194 11:05:44.795442 # # FPSIMD-7-1: PID: 1200
7195 11:05:44.799536 # # FPSIMD-5-0: Vector length: 128 bits
7196 11:05:44.802078 # # FPSIMD-5-0: PID: 1195
7197 11:05:44.805364 # # FPSIMD-7-0: Vector length: 128 bits
7198 11:05:44.809307 # # FPSIMD-7-0: PID: 1199
7199 11:05:44.812269 # # FPSIMD-6-0: Vector length: 128 bits
7200 11:05:44.812357 # # FPSIMD-6-0: PID: 1197
7201 11:05:44.815739 # # FPSIMD-4-1: Vector length: 128 bits
7202 11:05:44.822202 # # FPSIMD-5-1: Vector length: 128 bits
7203 11:05:44.822279 # # FPSIMD-4-1: PID: 1194
7204 11:05:44.825018 # # FPSIMD-5-1: PID: 1196
7205 11:05:44.828482 # # FPSIMD-6-1: Vector length: 128 bits
7206 11:05:44.831787 # # FPSIMD-6-1: PID: 1198
7207 11:05:44.835252 # # FPSIMD-4-0: Vector length: 128 bits
7208 11:05:44.838427 # # FPSIMD-4-0: PID: 1193
7209 11:05:44.841580 # # FPSIMD-3-0: Vector length: 128 bits
7210 11:05:44.841654 # # FPSIMD-3-0: PID: 1191
7211 11:05:44.845308 # # Finishing up...
7212 11:05:44.851479 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=830570, signals=10
7213 11:05:44.858488 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=905624, signals=10
7214 11:05:44.865104 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=712178, signals=10
7215 11:05:44.871658 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=913303, signals=10
7216 11:05:44.881221 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=728044, signals=10
7217 11:05:44.887777 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=709392, signals=10
7218 11:05:44.894656 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=874095, signals=10
7219 11:05:44.897928 # ok 1 FPSIMD-0-0
7220 11:05:44.898006 # ok 2 FPSIMD-0-1
7221 11:05:44.901045 # ok 3 FPSIMD-1-0
7222 11:05:44.901165 # ok 4 FPSIMD-1-1
7223 11:05:44.904859 # ok 5 FPSIMD-2-0
7224 11:05:44.904937 # ok 6 FPSIMD-2-1
7225 11:05:44.908117 # ok 7 FPSIMD-3-0
7226 11:05:44.908217 # ok 8 FPSIMD-3-1
7227 11:05:44.911421 # ok 9 FPSIMD-4-0
7228 11:05:44.911499 # ok 10 FPSIMD-4-1
7229 11:05:44.914475 # ok 11 FPSIMD-5-0
7230 11:05:44.914553 # ok 12 FPSIMD-5-1
7231 11:05:44.918127 # ok 13 FPSIMD-6-0
7232 11:05:44.918204 # ok 14 FPSIMD-6-1
7233 11:05:44.921360 # ok 15 FPSIMD-7-0
7234 11:05:44.921437 # ok 16 FPSIMD-7-1
7235 11:05:44.927857 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=712483, signals=9
7236 11:05:44.937953 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=937095, signals=10
7237 11:05:44.944706 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=983791, signals=10
7238 11:05:44.951218 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=699084, signals=10
7239 11:05:44.957909 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=699300, signals=10
7240 11:05:44.964354 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=734883, signals=10
7241 11:05:44.970918 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=735557, signals=10
7242 11:05:44.977804 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=810616, signals=9
7243 11:05:44.987527 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=784503, signals=10
7244 11:05:44.990760 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
7245 11:05:44.994525 ok 29 selftests: arm64: fp-stress
7246 11:05:44.997683 # selftests: arm64: sve-ptrace
7247 11:05:44.997799 # TAP version 13
7248 11:05:45.000970 # 1..4104
7249 11:05:45.001045 # ok 2 # SKIP SVE not available
7250 11:05:45.007519 # # Planned tests != run tests (4104 != 1)
7251 11:05:45.011071 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7252 11:05:45.014743 ok 30 selftests: arm64: sve-ptrace # SKIP
7253 11:05:45.017891 # selftests: arm64: sve-probe-vls
7254 11:05:45.020925 # TAP version 13
7255 11:05:45.021000 # 1..2
7256 11:05:45.024263 # ok 2 # SKIP SVE not available
7257 11:05:45.027799 # # Planned tests != run tests (2 != 1)
7258 11:05:45.030980 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7259 11:05:45.037602 ok 31 selftests: arm64: sve-probe-vls # SKIP
7260 11:05:45.040813 # selftests: arm64: vec-syscfg
7261 11:05:45.040912 # TAP version 13
7262 11:05:45.041026 # 1..20
7263 11:05:45.043708 # ok 1 # SKIP SVE not supported
7264 11:05:45.047121 # ok 2 # SKIP SVE not supported
7265 11:05:45.050485 # ok 3 # SKIP SVE not supported
7266 11:05:45.054075 # ok 4 # SKIP SVE not supported
7267 11:05:45.057590 # ok 5 # SKIP SVE not supported
7268 11:05:45.057691 # ok 6 # SKIP SVE not supported
7269 11:05:45.060349 # ok 7 # SKIP SVE not supported
7270 11:05:45.063733 # ok 8 # SKIP SVE not supported
7271 11:05:45.066851 # ok 9 # SKIP SVE not supported
7272 11:05:45.070160 # ok 10 # SKIP SVE not supported
7273 11:05:45.073652 # ok 11 # SKIP SME not supported
7274 11:05:45.076899 # ok 12 # SKIP SME not supported
7275 11:05:45.080574 # ok 13 # SKIP SME not supported
7276 11:05:45.083653 # ok 14 # SKIP SME not supported
7277 11:05:45.086721 # ok 15 # SKIP SME not supported
7278 11:05:45.086803 # ok 16 # SKIP SME not supported
7279 11:05:45.090432 # ok 17 # SKIP SME not supported
7280 11:05:45.093801 # ok 18 # SKIP SME not supported
7281 11:05:45.097089 # ok 19 # SKIP SME not supported
7282 11:05:45.100393 # ok 20 # SKIP SME not supported
7283 11:05:45.108072 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
7284 11:05:45.110310 ok 32 selftests: arm64: vec-syscfg
7285 11:05:45.110386 # selftests: arm64: za-fork
7286 11:05:45.113148 # TAP version 13
7287 11:05:45.113236 # 1..1
7288 11:05:45.116811 # # PID: 1277
7289 11:05:45.116886 # # SME support not present
7290 11:05:45.119985 # ok 0 skipped
7291 11:05:45.123192 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7292 11:05:45.126265 ok 33 selftests: arm64: za-fork
7293 11:05:45.129777 # selftests: arm64: za-ptrace
7294 11:05:45.202219 # TAP version 13
7295 11:05:45.202336 # 1..1
7296 11:05:45.205549 # ok 2 # SKIP SME not available
7297 11:05:45.212307 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7298 11:05:45.215197 ok 34 selftests: arm64: za-ptrace # SKIP
7299 11:05:45.236869 # selftests: arm64: check_buffer_fill
7300 11:05:45.317070 # # SKIP: MTE features unavailable
7301 11:05:45.326378 ok 35 selftests: arm64: check_buffer_fill # SKIP
7302 11:05:45.342272 # selftests: arm64: check_child_memory
7303 11:05:45.416408 # # SKIP: MTE features unavailable
7304 11:05:45.425601 ok 36 selftests: arm64: check_child_memory # SKIP
7305 11:05:45.440148 # selftests: arm64: check_gcr_el1_cswitch
7306 11:05:45.511783 # # SKIP: MTE features unavailable
7307 11:05:45.519748 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
7308 11:05:45.535252 # selftests: arm64: check_ksm_options
7309 11:05:45.585708 # # SKIP: MTE features unavailable
7310 11:05:45.592500 ok 38 selftests: arm64: check_ksm_options # SKIP
7311 11:05:45.606532 # selftests: arm64: check_mmap_options
7312 11:05:45.657096 # # SKIP: MTE features unavailable
7313 11:05:45.664874 ok 39 selftests: arm64: check_mmap_options # SKIP
7314 11:05:45.676955 # selftests: arm64: check_prctl
7315 11:05:45.760672 # TAP version 13
7316 11:05:45.760778 # 1..5
7317 11:05:45.763887 # ok 1 check_basic_read
7318 11:05:45.763963 # ok 2 NONE
7319 11:05:45.767341 # ok 3 # SKIP SYNC
7320 11:05:45.767416 # ok 4 # SKIP ASYNC
7321 11:05:45.770884 # ok 5 # SKIP SYNC+ASYNC
7322 11:05:45.774158 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
7323 11:05:45.777288 ok 40 selftests: arm64: check_prctl
7324 11:05:45.788329 # selftests: arm64: check_tags_inclusion
7325 11:05:45.858283 # # SKIP: MTE features unavailable
7326 11:05:45.866190 ok 41 selftests: arm64: check_tags_inclusion # SKIP
7327 11:05:45.881203 # selftests: arm64: check_user_mem
7328 11:05:45.955817 # # SKIP: MTE features unavailable
7329 11:05:45.964037 ok 42 selftests: arm64: check_user_mem # SKIP
7330 11:05:45.975713 # selftests: arm64: btitest
7331 11:05:46.039711 # TAP version 13
7332 11:05:46.039799 # 1..18
7333 11:05:46.043116 # # HWCAP_PACA not present
7334 11:05:46.046130 # # HWCAP2_BTI not present
7335 11:05:46.046208 # # Test binary built for BTI
7336 11:05:46.052589 # ok 1 nohint_func/call_using_br_x0 # SKIP
7337 11:05:46.056521 # ok 1 nohint_func/call_using_br_x16 # SKIP
7338 11:05:46.059527 # ok 1 nohint_func/call_using_blr # SKIP
7339 11:05:46.062934 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7340 11:05:46.066373 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7341 11:05:46.072419 # ok 1 bti_none_func/call_using_blr # SKIP
7342 11:05:46.075944 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7343 11:05:46.079421 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7344 11:05:46.082786 # ok 1 bti_c_func/call_using_blr # SKIP
7345 11:05:46.086216 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7346 11:05:46.089346 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7347 11:05:46.092459 # ok 1 bti_j_func/call_using_blr # SKIP
7348 11:05:46.096336 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7349 11:05:46.102363 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7350 11:05:46.105841 # ok 1 bti_jc_func/call_using_blr # SKIP
7351 11:05:46.108836 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7352 11:05:46.112440 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7353 11:05:46.115595 # ok 1 paciasp_func/call_using_blr # SKIP
7354 11:05:46.122451 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7355 11:05:46.125654 # # WARNING - EXPECTED TEST COUNT WRONG
7356 11:05:46.129154 ok 43 selftests: arm64: btitest
7357 11:05:46.132465 # selftests: arm64: nobtitest
7358 11:05:46.132540 # TAP version 13
7359 11:05:46.132599 # 1..18
7360 11:05:46.135370 # # HWCAP_PACA not present
7361 11:05:46.138535 # # HWCAP2_BTI not present
7362 11:05:46.142026 # # Test binary not built for BTI
7363 11:05:46.145038 # ok 1 nohint_func/call_using_br_x0 # SKIP
7364 11:05:46.148858 # ok 1 nohint_func/call_using_br_x16 # SKIP
7365 11:05:46.152324 # ok 1 nohint_func/call_using_blr # SKIP
7366 11:05:46.155322 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7367 11:05:46.161899 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7368 11:05:46.165288 # ok 1 bti_none_func/call_using_blr # SKIP
7369 11:05:46.168411 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7370 11:05:46.171845 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7371 11:05:46.175244 # ok 1 bti_c_func/call_using_blr # SKIP
7372 11:05:46.178501 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7373 11:05:46.181985 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7374 11:05:46.185543 # ok 1 bti_j_func/call_using_blr # SKIP
7375 11:05:46.191531 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7376 11:05:46.195140 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7377 11:05:46.198551 # ok 1 bti_jc_func/call_using_blr # SKIP
7378 11:05:46.201786 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7379 11:05:46.205158 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7380 11:05:46.208334 # ok 1 paciasp_func/call_using_blr # SKIP
7381 11:05:46.214920 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7382 11:05:46.218167 # # WARNING - EXPECTED TEST COUNT WRONG
7383 11:05:46.221892 ok 44 selftests: arm64: nobtitest
7384 11:05:46.224698 # selftests: arm64: hwcap
7385 11:05:46.228047 # TAP version 13
7386 11:05:46.228122 # 1..28
7387 11:05:46.231713 # ok 1 cpuinfo_match_RNG
7388 11:05:46.231788 # # SIGILL reported for RNG
7389 11:05:46.235705 # ok 2 # SKIP sigill_RNG
7390 11:05:46.238668 # ok 3 cpuinfo_match_SME
7391 11:05:46.238818 # ok 4 sigill_SME
7392 11:05:46.241702 # ok 5 cpuinfo_match_SVE
7393 11:05:46.241778 # ok 6 sigill_SVE
7394 11:05:46.244990 # ok 7 cpuinfo_match_SVE 2
7395 11:05:46.247883 # # SIGILL reported for SVE 2
7396 11:05:46.251319 # ok 8 # SKIP sigill_SVE 2
7397 11:05:46.251396 # ok 9 cpuinfo_match_SVE AES
7398 11:05:46.254989 # # SIGILL reported for SVE AES
7399 11:05:46.258317 # ok 10 # SKIP sigill_SVE AES
7400 11:05:46.260967 # ok 11 cpuinfo_match_SVE2 PMULL
7401 11:05:46.264393 # # SIGILL reported for SVE2 PMULL
7402 11:05:46.268068 # ok 12 # SKIP sigill_SVE2 PMULL
7403 11:05:46.271409 # ok 13 cpuinfo_match_SVE2 BITPERM
7404 11:05:46.274351 # # SIGILL reported for SVE2 BITPERM
7405 11:05:46.278057 # ok 14 # SKIP sigill_SVE2 BITPERM
7406 11:05:46.281381 # ok 15 cpuinfo_match_SVE2 SHA3
7407 11:05:46.281457 # # SIGILL reported for SVE2 SHA3
7408 11:05:46.284372 # ok 16 # SKIP sigill_SVE2 SHA3
7409 11:05:46.287679 # ok 17 cpuinfo_match_SVE2 SM4
7410 11:05:46.291085 # # SIGILL reported for SVE2 SM4
7411 11:05:46.294691 # ok 18 # SKIP sigill_SVE2 SM4
7412 11:05:46.298488 # ok 19 cpuinfo_match_SVE2 I8MM
7413 11:05:46.301017 # # SIGILL reported for SVE2 I8MM
7414 11:05:46.304406 # ok 20 # SKIP sigill_SVE2 I8MM
7415 11:05:46.304482 # ok 21 cpuinfo_match_SVE2 F32MM
7416 11:05:46.307692 # # SIGILL reported for SVE2 F32MM
7417 11:05:46.310809 # ok 22 # SKIP sigill_SVE2 F32MM
7418 11:05:46.314604 # ok 23 cpuinfo_match_SVE2 F64MM
7419 11:05:46.317752 # # SIGILL reported for SVE2 F64MM
7420 11:05:46.320954 # ok 24 # SKIP sigill_SVE2 F64MM
7421 11:05:46.324207 # ok 25 cpuinfo_match_SVE2 BF16
7422 11:05:46.327457 # # SIGILL reported for SVE2 BF16
7423 11:05:46.331221 # ok 26 # SKIP sigill_SVE2 BF16
7424 11:05:46.334255 # ok 27 cpuinfo_match_SVE2 EBF16
7425 11:05:46.334351 # ok 28 # SKIP sigill_SVE2 EBF16
7426 11:05:46.341265 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
7427 11:05:46.344359 ok 45 selftests: arm64: hwcap
7428 11:05:46.347545 # selftests: arm64: ptrace
7429 11:05:46.347638 # TAP version 13
7430 11:05:46.347732 # 1..7
7431 11:05:46.350559 # # Parent is 1519, child is 1520
7432 11:05:46.353953 # ok 1 read_tpidr_one
7433 11:05:46.354019 # ok 2 write_tpidr_one
7434 11:05:46.357570 # ok 3 verify_tpidr_one
7435 11:05:46.360637 # ok 4 count_tpidrs
7436 11:05:46.360757 # ok 5 tpidr2_write
7437 11:05:46.364055 # ok 6 tpidr2_read
7438 11:05:46.364147 # ok 7 write_tpidr_only
7439 11:05:46.370385 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
7440 11:05:46.374395 ok 46 selftests: arm64: ptrace
7441 11:05:46.377071 # selftests: arm64: syscall-abi
7442 11:05:46.402296 # TAP version 13
7443 11:05:46.402367 # 1..2
7444 11:05:46.406007 # ok 1 getpid() FPSIMD
7445 11:05:46.409218 # ok 2 sched_yield() FPSIMD
7446 11:05:46.412566 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
7447 11:05:46.415963 ok 47 selftests: arm64: syscall-abi
7448 11:05:46.422237 # selftests: arm64: tpidr2
7449 11:05:46.475086 # Segmentation fault
7450 11:05:46.483949 not ok 48 selftests: arm64: tpidr2 # exit=139
7451 11:05:48.110333 arm64_tags_test pass
7452 11:05:48.113593 arm64_run_tags_test_sh pass
7453 11:05:48.116705 arm64_fake_sigreturn_bad_magic pass
7454 11:05:48.120175 arm64_fake_sigreturn_bad_size pass
7455 11:05:48.123500 arm64_fake_sigreturn_bad_size_for_magic0 pass
7456 11:05:48.126446 arm64_fake_sigreturn_duplicated_fpsimd pass
7457 11:05:48.129856 arm64_fake_sigreturn_misaligned_sp pass
7458 11:05:48.133151 arm64_fake_sigreturn_missing_fpsimd pass
7459 11:05:48.136700 arm64_fake_sigreturn_sme_change_vl skip
7460 11:05:48.143483 arm64_fake_sigreturn_sve_change_vl skip
7461 11:05:48.146343 arm64_mangle_pstate_invalid_compat_toggle pass
7462 11:05:48.149714 arm64_mangle_pstate_invalid_daif_bits pass
7463 11:05:48.153000 arm64_mangle_pstate_invalid_mode_el1h pass
7464 11:05:48.156521 arm64_mangle_pstate_invalid_mode_el1t pass
7465 11:05:48.162840 arm64_mangle_pstate_invalid_mode_el2h pass
7466 11:05:48.166701 arm64_mangle_pstate_invalid_mode_el2t pass
7467 11:05:48.169824 arm64_mangle_pstate_invalid_mode_el3h pass
7468 11:05:48.172872 arm64_mangle_pstate_invalid_mode_el3t pass
7469 11:05:48.176214 arm64_sme_trap_no_sm skip
7470 11:05:48.179452 arm64_sme_trap_non_streaming skip
7471 11:05:48.179547 arm64_sme_trap_za pass
7472 11:05:48.182725 arm64_sme_vl skip
7473 11:05:48.186534 arm64_ssve_regs skip
7474 11:05:48.186626 arm64_sve_regs skip
7475 11:05:48.189994 arm64_sve_vl skip
7476 11:05:48.190080 arm64_za_no_regs skip
7477 11:05:48.192755 arm64_za_regs skip
7478 11:05:48.196535 arm64_pac_PAUTH_not_enabled skip
7479 11:05:48.199782 arm64_pac_PAUTH_not_enabled_dup2 skip
7480 11:05:48.202904 arm64_pac_Generic_PAUTH_not_enabled skip
7481 11:05:48.206321 arm64_pac_PAUTH_not_enabled_dup3 skip
7482 11:05:48.209734 arm64_pac_PAUTH_not_enabled_dup4 skip
7483 11:05:48.212888 arm64_pac_PAUTH_not_enabled_dup5 skip
7484 11:05:48.216203 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
7485 11:05:48.219544 arm64_pac pass
7486 11:05:48.223467 arm64_fp-stress_FPSIMD-0-0 pass
7487 11:05:48.226048 arm64_fp-stress_FPSIMD-0-1 pass
7488 11:05:48.226137 arm64_fp-stress_FPSIMD-1-0 pass
7489 11:05:48.229537 arm64_fp-stress_FPSIMD-1-1 pass
7490 11:05:48.232878 arm64_fp-stress_FPSIMD-2-0 pass
7491 11:05:48.236694 arm64_fp-stress_FPSIMD-2-1 pass
7492 11:05:48.239442 arm64_fp-stress_FPSIMD-3-0 pass
7493 11:05:48.242947 arm64_fp-stress_FPSIMD-3-1 pass
7494 11:05:48.245862 arm64_fp-stress_FPSIMD-4-0 pass
7495 11:05:48.249574 arm64_fp-stress_FPSIMD-4-1 pass
7496 11:05:48.253101 arm64_fp-stress_FPSIMD-5-0 pass
7497 11:05:48.256171 arm64_fp-stress_FPSIMD-5-1 pass
7498 11:05:48.256246 arm64_fp-stress_FPSIMD-6-0 pass
7499 11:05:48.259646 arm64_fp-stress_FPSIMD-6-1 pass
7500 11:05:48.262963 arm64_fp-stress_FPSIMD-7-0 pass
7501 11:05:48.266188 arm64_fp-stress_FPSIMD-7-1 pass
7502 11:05:48.269608 arm64_fp-stress pass
7503 11:05:48.272655 arm64_sve-ptrace_SVE_not_available skip
7504 11:05:48.272731 arm64_sve-ptrace skip
7505 11:05:48.279908 arm64_sve-probe-vls_SVE_not_available skip
7506 11:05:48.279985 arm64_sve-probe-vls skip
7507 11:05:48.282644 arm64_vec-syscfg_SVE_not_supported skip
7508 11:05:48.289208 arm64_vec-syscfg_SVE_not_supported_dup2 skip
7509 11:05:48.292749 arm64_vec-syscfg_SVE_not_supported_dup3 skip
7510 11:05:48.296469 arm64_vec-syscfg_SVE_not_supported_dup4 skip
7511 11:05:48.299343 arm64_vec-syscfg_SVE_not_supported_dup5 skip
7512 11:05:48.305722 arm64_vec-syscfg_SVE_not_supported_dup6 skip
7513 11:05:48.308997 arm64_vec-syscfg_SVE_not_supported_dup7 skip
7514 11:05:48.312752 arm64_vec-syscfg_SVE_not_supported_dup8 skip
7515 11:05:48.315751 arm64_vec-syscfg_SVE_not_supported_dup9 skip
7516 11:05:48.322672 arm64_vec-syscfg_SVE_not_supported_dup10 skip
7517 11:05:48.325542 arm64_vec-syscfg_SME_not_supported skip
7518 11:05:48.329073 arm64_vec-syscfg_SME_not_supported_dup2 skip
7519 11:05:48.332228 arm64_vec-syscfg_SME_not_supported_dup3 skip
7520 11:05:48.339079 arm64_vec-syscfg_SME_not_supported_dup4 skip
7521 11:05:48.342061 arm64_vec-syscfg_SME_not_supported_dup5 skip
7522 11:05:48.345444 arm64_vec-syscfg_SME_not_supported_dup6 skip
7523 11:05:48.349436 arm64_vec-syscfg_SME_not_supported_dup7 skip
7524 11:05:48.355178 arm64_vec-syscfg_SME_not_supported_dup8 skip
7525 11:05:48.358806 arm64_vec-syscfg_SME_not_supported_dup9 skip
7526 11:05:48.362354 arm64_vec-syscfg_SME_not_supported_dup10 skip
7527 11:05:48.365601 arm64_vec-syscfg pass
7528 11:05:48.365678 arm64_za-fork_skipped pass
7529 11:05:48.368604 arm64_za-fork pass
7530 11:05:48.371999 arm64_za-ptrace_SME_not_available skip
7531 11:05:48.375371 arm64_za-ptrace skip
7532 11:05:48.375470 arm64_check_buffer_fill skip
7533 11:05:48.378856 arm64_check_child_memory skip
7534 11:05:48.381758 arm64_check_gcr_el1_cswitch skip
7535 11:05:48.385334 arm64_check_ksm_options skip
7536 11:05:48.388490 arm64_check_mmap_options skip
7537 11:05:48.392142 arm64_check_prctl_check_basic_read pass
7538 11:05:48.395443 arm64_check_prctl_NONE pass
7539 11:05:48.398279 arm64_check_prctl_SYNC skip
7540 11:05:48.398355 arm64_check_prctl_ASYNC skip
7541 11:05:48.401915 arm64_check_prctl_SYNC_ASYNC skip
7542 11:05:48.405369 arm64_check_prctl pass
7543 11:05:48.408582 arm64_check_tags_inclusion skip
7544 11:05:48.411998 arm64_check_user_mem skip
7545 11:05:48.415203 arm64_btitest_nohint_func_call_using_br_x0 skip
7546 11:05:48.418813 arm64_btitest_nohint_func_call_using_br_x16 skip
7547 11:05:48.425305 arm64_btitest_nohint_func_call_using_blr skip
7548 11:05:48.428701 arm64_btitest_bti_none_func_call_using_br_x0 skip
7549 11:05:48.431570 arm64_btitest_bti_none_func_call_using_br_x16 skip
7550 11:05:48.438413 arm64_btitest_bti_none_func_call_using_blr skip
7551 11:05:48.441614 arm64_btitest_bti_c_func_call_using_br_x0 skip
7552 11:05:48.445207 arm64_btitest_bti_c_func_call_using_br_x16 skip
7553 11:05:48.451497 arm64_btitest_bti_c_func_call_using_blr skip
7554 11:05:48.454772 arm64_btitest_bti_j_func_call_using_br_x0 skip
7555 11:05:48.458235 arm64_btitest_bti_j_func_call_using_br_x16 skip
7556 11:05:48.461280 arm64_btitest_bti_j_func_call_using_blr skip
7557 11:05:48.468414 arm64_btitest_bti_jc_func_call_using_br_x0 skip
7558 11:05:48.471297 arm64_btitest_bti_jc_func_call_using_br_x16 skip
7559 11:05:48.474574 arm64_btitest_bti_jc_func_call_using_blr skip
7560 11:05:48.481360 arm64_btitest_paciasp_func_call_using_br_x0 skip
7561 11:05:48.484682 arm64_btitest_paciasp_func_call_using_br_x16 skip
7562 11:05:48.488047 arm64_btitest_paciasp_func_call_using_blr skip
7563 11:05:48.491462 arm64_btitest pass
7564 11:05:48.494482 arm64_nobtitest_nohint_func_call_using_br_x0 skip
7565 11:05:48.497836 arm64_nobtitest_nohint_func_call_using_br_x16 skip
7566 11:05:48.504666 arm64_nobtitest_nohint_func_call_using_blr skip
7567 11:05:48.508183 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
7568 11:05:48.514829 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
7569 11:05:48.517821 arm64_nobtitest_bti_none_func_call_using_blr skip
7570 11:05:48.521192 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
7571 11:05:48.527790 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
7572 11:05:48.531075 arm64_nobtitest_bti_c_func_call_using_blr skip
7573 11:05:48.534497 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
7574 11:05:48.537885 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
7575 11:05:48.544359 arm64_nobtitest_bti_j_func_call_using_blr skip
7576 11:05:48.547955 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
7577 11:05:48.551041 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
7578 11:05:48.557639 arm64_nobtitest_bti_jc_func_call_using_blr skip
7579 11:05:48.561067 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
7580 11:05:48.567418 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
7581 11:05:48.570511 arm64_nobtitest_paciasp_func_call_using_blr skip
7582 11:05:48.570605 arm64_nobtitest pass
7583 11:05:48.573974 arm64_hwcap_cpuinfo_match_RNG pass
7584 11:05:48.577227 arm64_hwcap_sigill_RNG skip
7585 11:05:48.580924 arm64_hwcap_cpuinfo_match_SME pass
7586 11:05:48.584080 arm64_hwcap_sigill_SME pass
7587 11:05:48.587031 arm64_hwcap_cpuinfo_match_SVE pass
7588 11:05:48.590813 arm64_hwcap_sigill_SVE pass
7589 11:05:48.594002 arm64_hwcap_cpuinfo_match_SVE_2 pass
7590 11:05:48.594078 arm64_hwcap_sigill_SVE_2 skip
7591 11:05:48.596846 arm64_hwcap_cpuinfo_match_SVE_AES pass
7592 11:05:48.600510 arm64_hwcap_sigill_SVE_AES skip
7593 11:05:48.603904 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
7594 11:05:48.607246 arm64_hwcap_sigill_SVE2_PMULL skip
7595 11:05:48.613405 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
7596 11:05:48.617545 arm64_hwcap_sigill_SVE2_BITPERM skip
7597 11:05:48.620393 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
7598 11:05:48.623590 arm64_hwcap_sigill_SVE2_SHA3 skip
7599 11:05:48.627091 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
7600 11:05:48.630152 arm64_hwcap_sigill_SVE2_SM4 skip
7601 11:05:48.633303 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
7602 11:05:48.637456 arm64_hwcap_sigill_SVE2_I8MM skip
7603 11:05:48.639853 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
7604 11:05:48.643307 arm64_hwcap_sigill_SVE2_F32MM skip
7605 11:05:48.646991 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
7606 11:05:48.650345 arm64_hwcap_sigill_SVE2_F64MM skip
7607 11:05:48.653406 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
7608 11:05:48.656687 arm64_hwcap_sigill_SVE2_BF16 skip
7609 11:05:48.660452 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
7610 11:05:48.663508 arm64_hwcap_sigill_SVE2_EBF16 skip
7611 11:05:48.663583 arm64_hwcap pass
7612 11:05:48.666595 arm64_ptrace_read_tpidr_one pass
7613 11:05:48.670327 arm64_ptrace_write_tpidr_one pass
7614 11:05:48.673516 arm64_ptrace_verify_tpidr_one pass
7615 11:05:48.676749 arm64_ptrace_count_tpidrs pass
7616 11:05:48.679898 arm64_ptrace_tpidr2_write pass
7617 11:05:48.683306 arm64_ptrace_tpidr2_read pass
7618 11:05:48.686758 arm64_ptrace_write_tpidr_only pass
7619 11:05:48.686835 arm64_ptrace pass
7620 11:05:48.689878 arm64_syscall-abi_getpid_FPSIMD pass
7621 11:05:48.693069 arm64_syscall-abi_sched_yield_FPSIMD pass
7622 11:05:48.696393 arm64_syscall-abi pass
7623 11:05:48.696492 arm64_tpidr2 fail
7624 11:05:48.703193 + ../../utils/send-to-lava.sh ./output/result.txt
7625 11:05:48.706568 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
7627 11:05:48.709389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
7628 11:05:48.712932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
7629 11:05:48.713197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
7631 11:05:48.719388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
7632 11:05:48.719659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
7634 11:05:48.725995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
7635 11:05:48.726245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
7637 11:05:48.732785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
7638 11:05:48.733027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
7640 11:05:48.742838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
7641 11:05:48.743108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
7643 11:05:48.784151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
7644 11:05:48.784433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
7646 11:05:48.825562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
7647 11:05:48.825820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
7649 11:05:48.869222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
7650 11:05:48.869475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
7652 11:05:48.910654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
7653 11:05:48.910943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
7655 11:05:48.951431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
7656 11:05:48.951728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
7658 11:05:48.992167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
7659 11:05:48.992440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
7661 11:05:49.029557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
7662 11:05:49.029817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
7664 11:05:49.071097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
7665 11:05:49.071354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
7667 11:05:49.114348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
7668 11:05:49.114606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
7670 11:05:49.159106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
7671 11:05:49.159370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
7673 11:05:49.202625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
7674 11:05:49.202882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
7676 11:05:49.241921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
7677 11:05:49.242171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
7679 11:05:49.283383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
7680 11:05:49.283640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
7682 11:05:49.317487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
7683 11:05:49.317742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
7685 11:05:49.356593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
7687 11:05:49.359766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
7688 11:05:49.396909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
7689 11:05:49.397199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
7691 11:05:49.439502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
7692 11:05:49.439782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
7694 11:05:49.480300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
7695 11:05:49.480552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
7697 11:05:49.520854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
7698 11:05:49.521107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
7700 11:05:49.566529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
7701 11:05:49.566780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
7703 11:05:49.613406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
7704 11:05:49.613656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
7706 11:05:49.656326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
7707 11:05:49.656601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
7709 11:05:49.699180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
7711 11:05:49.702662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
7712 11:05:49.745259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
7713 11:05:49.745507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
7715 11:05:49.797290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
7716 11:05:49.797596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
7718 11:05:49.843867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
7719 11:05:49.844120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
7721 11:05:49.889667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
7722 11:05:49.889930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
7724 11:05:49.938148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
7725 11:05:49.938405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
7727 11:05:49.987926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
7728 11:05:49.988184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
7730 11:05:50.025996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
7731 11:05:50.026361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
7733 11:05:50.071651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
7734 11:05:50.071961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
7736 11:05:50.113918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
7737 11:05:50.114280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
7739 11:05:50.154669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
7741 11:05:50.158073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
7742 11:05:50.196707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
7743 11:05:50.197060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
7745 11:05:50.232248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
7746 11:05:50.232543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
7748 11:05:50.272054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
7749 11:05:50.272332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
7751 11:05:50.313382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
7753 11:05:50.316496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
7754 11:05:50.355364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
7755 11:05:50.355653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
7757 11:05:50.397266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
7758 11:05:50.397618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
7760 11:05:50.437198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
7762 11:05:50.440563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
7763 11:05:50.480301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
7764 11:05:50.480558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
7766 11:05:50.517985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
7767 11:05:50.518234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
7769 11:05:50.556733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
7770 11:05:50.557011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
7772 11:05:50.597561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
7773 11:05:50.597840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
7775 11:05:50.636135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
7777 11:05:50.638857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
7778 11:05:50.682639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
7779 11:05:50.682894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
7781 11:05:50.724356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
7782 11:05:50.724604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
7784 11:05:50.767660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
7785 11:05:50.767930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
7787 11:05:50.804894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
7788 11:05:50.805137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
7790 11:05:50.849298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
7791 11:05:50.849543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
7793 11:05:50.888642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
7794 11:05:50.888895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
7796 11:05:50.938199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
7797 11:05:50.938541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
7799 11:05:50.979440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
7800 11:05:50.979777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
7802 11:05:51.020500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
7803 11:05:51.020818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
7805 11:05:51.063938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
7806 11:05:51.064262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
7808 11:05:51.104912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
7809 11:05:51.105152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
7811 11:05:51.147613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
7812 11:05:51.147870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
7814 11:05:51.188659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
7815 11:05:51.188949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
7817 11:05:51.232201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
7818 11:05:51.232467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
7820 11:05:51.273378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
7821 11:05:51.273656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
7823 11:05:51.309524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
7824 11:05:51.309804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
7826 11:05:51.353151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
7827 11:05:51.353422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
7829 11:05:51.391243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
7830 11:05:51.391499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
7832 11:05:51.428287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
7833 11:05:51.428547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
7835 11:05:51.465110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
7836 11:05:51.465448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
7838 11:05:51.499585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
7839 11:05:51.499886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
7841 11:05:51.536450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
7842 11:05:51.536698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
7844 11:05:51.571603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
7845 11:05:51.571887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
7847 11:05:51.604971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
7848 11:05:51.605244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
7850 11:05:51.642554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
7851 11:05:51.642812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
7853 11:05:51.680780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
7854 11:05:51.681087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
7856 11:05:51.716441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
7857 11:05:51.716724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
7859 11:05:51.752635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
7860 11:05:51.752904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
7862 11:05:51.788553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
7863 11:05:51.788826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
7865 11:05:51.826821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
7866 11:05:51.827091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
7868 11:05:51.862028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
7869 11:05:51.862273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
7871 11:05:51.900855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
7872 11:05:51.901138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
7874 11:05:51.938819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
7875 11:05:51.939082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
7877 11:05:51.973990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
7879 11:05:51.977361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
7880 11:05:52.007270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
7881 11:05:52.007560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
7883 11:05:52.041940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
7884 11:05:52.042232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
7886 11:05:52.080520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
7887 11:05:52.080840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
7889 11:05:52.115557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
7890 11:05:52.115827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
7892 11:05:52.156203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
7893 11:05:52.156478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
7895 11:05:52.193450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
7896 11:05:52.193726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
7898 11:05:52.232740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
7900 11:05:52.235627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
7901 11:05:52.270177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
7902 11:05:52.270455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
7904 11:05:52.305599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
7905 11:05:52.305878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
7907 11:05:52.345788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
7908 11:05:52.346044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
7910 11:05:52.386084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
7911 11:05:52.386345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
7913 11:05:52.427789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
7914 11:05:52.428099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
7916 11:05:52.467521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
7917 11:05:52.467781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
7919 11:05:52.504115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
7920 11:05:52.504389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
7922 11:05:52.542084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
7923 11:05:52.542384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
7925 11:05:52.581244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
7926 11:05:52.581510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
7928 11:05:52.617758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
7929 11:05:52.618039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
7931 11:05:52.656775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
7932 11:05:52.657032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
7934 11:05:52.694118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
7935 11:05:52.694370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
7937 11:05:52.729841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
7938 11:05:52.730090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
7940 11:05:52.766952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
7941 11:05:52.767207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
7943 11:05:52.804241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
7944 11:05:52.804507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
7946 11:05:52.842259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7947 11:05:52.842535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
7949 11:05:52.878464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7950 11:05:52.878710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
7952 11:05:52.915726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
7953 11:05:52.915972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
7955 11:05:52.951982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
7956 11:05:52.952229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
7958 11:05:52.988830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
7959 11:05:52.989090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
7961 11:05:53.025424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
7962 11:05:53.025670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
7964 11:05:53.057613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
7965 11:05:53.057878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
7967 11:05:53.104172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
7968 11:05:53.104526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
7970 11:05:53.131342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
7971 11:05:53.131612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
7973 11:05:53.171494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
7974 11:05:53.171739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
7976 11:05:53.207962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
7977 11:05:53.208264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
7979 11:05:53.243972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
7980 11:05:53.244263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
7982 11:05:53.280460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
7983 11:05:53.280739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
7985 11:05:53.320176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
7986 11:05:53.320434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
7988 11:05:53.356061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
7989 11:05:53.356408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
7991 11:05:53.393589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
7992 11:05:53.393875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
7994 11:05:53.432086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
7995 11:05:53.432366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
7997 11:05:53.469145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
7998 11:05:53.469443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
8000 11:05:53.507286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
8001 11:05:53.507547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
8003 11:05:53.545845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
8004 11:05:53.546146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
8006 11:05:53.586976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
8007 11:05:53.587243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
8009 11:05:53.626047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
8010 11:05:53.626299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
8012 11:05:53.662701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
8013 11:05:53.662962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
8015 11:05:53.699848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
8016 11:05:53.700110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
8018 11:05:53.740361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
8019 11:05:53.740614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
8021 11:05:53.773908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
8022 11:05:53.774155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
8024 11:05:53.814685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
8025 11:05:53.814950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
8027 11:05:53.852660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
8028 11:05:53.852939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
8030 11:05:53.893678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
8031 11:05:53.893980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
8033 11:05:53.933412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
8034 11:05:53.933669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
8036 11:05:53.978115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
8037 11:05:53.978367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
8039 11:05:54.016130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
8040 11:05:54.016383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
8042 11:05:54.060797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
8043 11:05:54.061066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
8045 11:05:54.096749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
8046 11:05:54.096998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
8048 11:05:54.142073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
8049 11:05:54.142367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
8051 11:05:54.180118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
8052 11:05:54.180398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
8054 11:05:54.225302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
8055 11:05:54.225557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
8057 11:05:54.261107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
8058 11:05:54.261420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
8060 11:05:54.298279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
8061 11:05:54.298534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
8063 11:05:54.334926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
8064 11:05:54.335178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
8066 11:05:54.373957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
8067 11:05:54.374207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
8069 11:05:54.406680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
8071 11:05:54.409539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
8072 11:05:54.448533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
8073 11:05:54.448789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
8075 11:05:54.483877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
8077 11:05:54.487107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
8078 11:05:54.526222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
8079 11:05:54.526472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
8081 11:05:54.561043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
8083 11:05:54.564840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
8084 11:05:54.604975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
8085 11:05:54.605239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
8087 11:05:54.643387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
8088 11:05:54.643633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
8090 11:05:54.680375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
8091 11:05:54.680618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
8093 11:05:54.716972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
8094 11:05:54.717253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
8096 11:05:54.757381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
8097 11:05:54.757632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
8099 11:05:54.797485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
8101 11:05:54.800639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
8102 11:05:54.841782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
8103 11:05:54.842040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
8105 11:05:54.878132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
8107 11:05:54.880970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
8108 11:05:54.916363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
8109 11:05:54.916654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
8111 11:05:54.956508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
8113 11:05:54.960044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
8114 11:05:54.996104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
8116 11:05:54.999004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
8117 11:05:55.039121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
8118 11:05:55.039402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
8120 11:05:55.075569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
8121 11:05:55.075819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
8123 11:05:55.114537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
8124 11:05:55.114789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
8126 11:05:55.152042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
8127 11:05:55.152288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
8129 11:05:55.195106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
8130 11:05:55.195366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
8132 11:05:55.231765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
8133 11:05:55.232013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
8135 11:05:55.272575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
8136 11:05:55.272825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
8138 11:05:55.311844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
8139 11:05:55.312093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
8141 11:05:55.348271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
8142 11:05:55.348515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
8144 11:05:55.386377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=fail>
8145 11:05:55.386467 + set +x
8146 11:05:55.386693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=fail
8148 11:05:55.393224 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14786794_1.6.2.3.5>
8149 11:05:55.393460 Received signal: <ENDRUN> 1_kselftest-arm64 14786794_1.6.2.3.5
8150 11:05:55.393528 Ending use of test pattern.
8151 11:05:55.393585 Ending test lava.1_kselftest-arm64 (14786794_1.6.2.3.5), duration 33.00
8153 11:05:55.396229 <LAVA_TEST_RUNNER EXIT>
8154 11:05:55.396464 ok: lava_test_shell seems to have completed
8155 11:05:55.397348 shardfile-arm64: pass
arm64_tags_test: pass
arm64_run_tags_test_sh: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_fp-stress: pass
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-probe-vls: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg: pass
arm64_za-fork_skipped: pass
arm64_za-fork: pass
arm64_za-ptrace_SME_not_available: skip
arm64_za-ptrace: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest: pass
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SVE_AES: skip
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_write_tpidr_only: pass
arm64_ptrace: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi: pass
arm64_tpidr2: fail
8156 11:05:55.397515 end: 3.1 lava-test-shell (duration 00:00:34) [common]
8157 11:05:55.397599 end: 3 lava-test-retry (duration 00:00:34) [common]
8158 11:05:55.397678 start: 4 finalize (timeout 00:07:07) [common]
8159 11:05:55.397760 start: 4.1 power-off (timeout 00:00:30) [common]
8160 11:05:55.397890 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1', '--port=1', '--command=off']
8161 11:05:57.462939 >> Command sent successfully.
8162 11:05:57.466257 Returned 0 in 2 seconds
8163 11:05:57.466404 end: 4.1 power-off (duration 00:00:02) [common]
8165 11:05:57.466614 start: 4.2 read-feedback (timeout 00:07:05) [common]
8166 11:05:57.466756 Listened to connection for namespace 'common' for up to 1s
8167 11:05:58.467762 Finalising connection for namespace 'common'
8168 11:05:58.467895 Disconnecting from shell: Finalise
8169 11:05:58.467964 / #
8170 11:05:58.568217 end: 4.2 read-feedback (duration 00:00:01) [common]
8171 11:05:58.568350 end: 4 finalize (duration 00:00:03) [common]
8172 11:05:58.568456 Cleaning after the job
8173 11:05:58.568553 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/ramdisk
8174 11:05:58.571016 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/kernel
8175 11:05:58.583089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/dtb
8176 11:05:58.583294 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/nfsrootfs
8177 11:05:58.651314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786794/tftp-deploy-hhm84oqd/modules
8178 11:05:58.657092 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786794
8179 11:05:59.246681 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786794
8180 11:05:59.246844 Job finished correctly