Boot log: mt8192-asurada-spherion-r0
- Errors: 3
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 6
- Kernel Warnings: 0
1 11:02:00.343324 lava-dispatcher, installed at version: 2024.05
2 11:02:00.343571 start: 0 validate
3 11:02:00.343686 Start time: 2024-07-10 11:02:00.343680+00:00 (UTC)
4 11:02:00.343827 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:00.343970 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:02:00.615100 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:00.615267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:02:00.881089 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:02:00.881837 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:03:01.215391 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:03:01.216030 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:03:01.746656 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:03:01.747283 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:03:02.025708 validate duration: 61.68
16 11:03:02.027364 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:03:02.027880 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:03:02.028316 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:03:02.029016 Not decompressing ramdisk as can be used compressed.
20 11:03:02.029468 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:03:02.029798 saving as /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/ramdisk/initrd.cpio.gz
22 11:03:02.030142 total size: 5628169 (5 MB)
23 11:03:08.965842 progress 0 % (0 MB)
24 11:03:08.975252 progress 5 % (0 MB)
25 11:03:08.983976 progress 10 % (0 MB)
26 11:03:08.991811 progress 15 % (0 MB)
27 11:03:08.998937 progress 20 % (1 MB)
28 11:03:09.003383 progress 25 % (1 MB)
29 11:03:09.007310 progress 30 % (1 MB)
30 11:03:09.010751 progress 35 % (1 MB)
31 11:03:09.013364 progress 40 % (2 MB)
32 11:03:09.016210 progress 45 % (2 MB)
33 11:03:09.018386 progress 50 % (2 MB)
34 11:03:09.020779 progress 55 % (2 MB)
35 11:03:09.022930 progress 60 % (3 MB)
36 11:03:09.024786 progress 65 % (3 MB)
37 11:03:09.026785 progress 70 % (3 MB)
38 11:03:09.028488 progress 75 % (4 MB)
39 11:03:09.030449 progress 80 % (4 MB)
40 11:03:09.031993 progress 85 % (4 MB)
41 11:03:09.033570 progress 90 % (4 MB)
42 11:03:09.035032 progress 95 % (5 MB)
43 11:03:09.036358 progress 100 % (5 MB)
44 11:03:09.036554 5 MB downloaded in 7.01 s (0.77 MB/s)
45 11:03:09.036692 end: 1.1.1 http-download (duration 00:00:07) [common]
47 11:03:09.036933 end: 1.1 download-retry (duration 00:00:07) [common]
48 11:03:09.037010 start: 1.2 download-retry (timeout 00:09:53) [common]
49 11:03:09.037082 start: 1.2.1 http-download (timeout 00:09:53) [common]
50 11:03:09.037209 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:03:09.037268 saving as /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/kernel/Image
52 11:03:09.037319 total size: 54813184 (52 MB)
53 11:03:09.037370 No compression specified
54 11:03:09.038416 progress 0 % (0 MB)
55 11:03:09.051578 progress 5 % (2 MB)
56 11:03:09.065096 progress 10 % (5 MB)
57 11:03:09.077867 progress 15 % (7 MB)
58 11:03:09.091129 progress 20 % (10 MB)
59 11:03:09.104398 progress 25 % (13 MB)
60 11:03:09.117356 progress 30 % (15 MB)
61 11:03:09.130896 progress 35 % (18 MB)
62 11:03:09.144526 progress 40 % (20 MB)
63 11:03:09.158052 progress 45 % (23 MB)
64 11:03:09.171683 progress 50 % (26 MB)
65 11:03:09.186024 progress 55 % (28 MB)
66 11:03:09.199474 progress 60 % (31 MB)
67 11:03:09.213320 progress 65 % (34 MB)
68 11:03:09.227306 progress 70 % (36 MB)
69 11:03:09.241634 progress 75 % (39 MB)
70 11:03:09.255511 progress 80 % (41 MB)
71 11:03:09.269380 progress 85 % (44 MB)
72 11:03:09.283162 progress 90 % (47 MB)
73 11:03:09.297042 progress 95 % (49 MB)
74 11:03:09.310434 progress 100 % (52 MB)
75 11:03:09.310670 52 MB downloaded in 0.27 s (191.24 MB/s)
76 11:03:09.310860 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:03:09.311068 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:03:09.311146 start: 1.3 download-retry (timeout 00:09:53) [common]
80 11:03:09.311221 start: 1.3.1 http-download (timeout 00:09:53) [common]
81 11:03:09.311352 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:03:09.311411 saving as /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/dtb/mt8192-asurada-spherion-r0.dtb
83 11:03:09.311462 total size: 47258 (0 MB)
84 11:03:09.311514 No compression specified
85 11:03:09.312589 progress 69 % (0 MB)
86 11:03:09.312840 progress 100 % (0 MB)
87 11:03:09.312982 0 MB downloaded in 0.00 s (29.70 MB/s)
88 11:03:09.313091 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:03:09.313288 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:03:09.313362 start: 1.4 download-retry (timeout 00:09:53) [common]
92 11:03:09.313436 start: 1.4.1 http-download (timeout 00:09:53) [common]
93 11:03:09.313544 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:03:09.313603 saving as /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/nfsrootfs/full.rootfs.tar
95 11:03:09.313655 total size: 120894716 (115 MB)
96 11:03:09.313708 Using unxz to decompress xz
97 11:03:09.314959 progress 0 % (0 MB)
98 11:03:09.654434 progress 5 % (5 MB)
99 11:03:09.994902 progress 10 % (11 MB)
100 11:03:10.341450 progress 15 % (17 MB)
101 11:03:10.666800 progress 20 % (23 MB)
102 11:03:10.978218 progress 25 % (28 MB)
103 11:03:11.334254 progress 30 % (34 MB)
104 11:03:11.665432 progress 35 % (40 MB)
105 11:03:11.840407 progress 40 % (46 MB)
106 11:03:12.027425 progress 45 % (51 MB)
107 11:03:12.328072 progress 50 % (57 MB)
108 11:03:12.688648 progress 55 % (63 MB)
109 11:03:13.023837 progress 60 % (69 MB)
110 11:03:13.378128 progress 65 % (74 MB)
111 11:03:13.728590 progress 70 % (80 MB)
112 11:03:14.101540 progress 75 % (86 MB)
113 11:03:14.446076 progress 80 % (92 MB)
114 11:03:14.788278 progress 85 % (98 MB)
115 11:03:15.142493 progress 90 % (103 MB)
116 11:03:15.474949 progress 95 % (109 MB)
117 11:03:15.842093 progress 100 % (115 MB)
118 11:03:15.847787 115 MB downloaded in 6.53 s (17.64 MB/s)
119 11:03:15.847987 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:03:15.848282 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:03:15.848362 start: 1.5 download-retry (timeout 00:09:46) [common]
123 11:03:15.848437 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 11:03:15.848579 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:03:15.848640 saving as /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/modules/modules.tar
126 11:03:15.848692 total size: 8607984 (8 MB)
127 11:03:15.848747 Using unxz to decompress xz
128 11:03:15.850047 progress 0 % (0 MB)
129 11:03:15.870251 progress 5 % (0 MB)
130 11:03:15.894633 progress 10 % (0 MB)
131 11:03:15.918693 progress 15 % (1 MB)
132 11:03:15.943172 progress 20 % (1 MB)
133 11:03:15.968239 progress 25 % (2 MB)
134 11:03:15.991970 progress 30 % (2 MB)
135 11:03:16.015091 progress 35 % (2 MB)
136 11:03:16.041534 progress 40 % (3 MB)
137 11:03:16.066020 progress 45 % (3 MB)
138 11:03:16.089963 progress 50 % (4 MB)
139 11:03:16.114483 progress 55 % (4 MB)
140 11:03:16.139419 progress 60 % (4 MB)
141 11:03:16.163194 progress 65 % (5 MB)
142 11:03:16.189253 progress 70 % (5 MB)
143 11:03:16.217585 progress 75 % (6 MB)
144 11:03:16.245918 progress 80 % (6 MB)
145 11:03:16.269709 progress 85 % (7 MB)
146 11:03:16.293730 progress 90 % (7 MB)
147 11:03:16.318406 progress 95 % (7 MB)
148 11:03:16.341877 progress 100 % (8 MB)
149 11:03:16.347313 8 MB downloaded in 0.50 s (16.46 MB/s)
150 11:03:16.347563 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:03:16.347910 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:03:16.348031 start: 1.6 prepare-tftp-overlay (timeout 00:09:46) [common]
154 11:03:16.348152 start: 1.6.1 extract-nfsrootfs (timeout 00:09:46) [common]
155 11:03:20.152606 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786783/extract-nfsrootfs-3uoqcuz9
156 11:03:20.152791 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:03:20.152878 start: 1.6.2 lava-overlay (timeout 00:09:42) [common]
158 11:03:20.153029 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu
159 11:03:20.153148 makedir: /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin
160 11:03:20.153239 makedir: /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/tests
161 11:03:20.153327 makedir: /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/results
162 11:03:20.153407 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-add-keys
163 11:03:20.153528 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-add-sources
164 11:03:20.153643 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-background-process-start
165 11:03:20.153756 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-background-process-stop
166 11:03:20.153878 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-common-functions
167 11:03:20.153992 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-echo-ipv4
168 11:03:20.154112 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-install-packages
169 11:03:20.154258 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-installed-packages
170 11:03:20.154366 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-os-build
171 11:03:20.154474 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-probe-channel
172 11:03:20.154584 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-probe-ip
173 11:03:20.154693 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-target-ip
174 11:03:20.154806 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-target-mac
175 11:03:20.154916 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-target-storage
176 11:03:20.155027 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-test-case
177 11:03:20.155137 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-test-event
178 11:03:20.155245 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-test-feedback
179 11:03:20.155355 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-test-raise
180 11:03:20.155465 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-test-reference
181 11:03:20.155574 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-test-runner
182 11:03:20.155682 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-test-set
183 11:03:20.155791 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-test-shell
184 11:03:20.155907 Updating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-add-keys (debian)
185 11:03:20.156053 Updating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-add-sources (debian)
186 11:03:20.156182 Updating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-install-packages (debian)
187 11:03:20.156309 Updating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-installed-packages (debian)
188 11:03:20.156434 Updating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/bin/lava-os-build (debian)
189 11:03:20.156542 Creating /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/environment
190 11:03:20.156629 LAVA metadata
191 11:03:20.156692 - LAVA_JOB_ID=14786783
192 11:03:20.156748 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:03:20.156849 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:42) [common]
194 11:03:20.156904 skipped lava-vland-overlay
195 11:03:20.156972 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:03:20.157043 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:42) [common]
197 11:03:20.157097 skipped lava-multinode-overlay
198 11:03:20.157161 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:03:20.157229 start: 1.6.2.3 test-definition (timeout 00:09:42) [common]
200 11:03:20.157308 Loading test definitions
201 11:03:20.157383 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:42) [common]
202 11:03:20.157440 Using /lava-14786783 at stage 0
203 11:03:20.157731 uuid=14786783_1.6.2.3.1 testdef=None
204 11:03:20.157811 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:03:20.157885 start: 1.6.2.3.2 test-overlay (timeout 00:09:42) [common]
206 11:03:20.158317 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:03:20.158511 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:42) [common]
209 11:03:20.159016 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:03:20.159221 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:42) [common]
212 11:03:20.159701 runner path: /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/0/tests/0_timesync-off test_uuid 14786783_1.6.2.3.1
213 11:03:20.159840 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:03:20.160041 start: 1.6.2.3.5 git-repo-action (timeout 00:09:42) [common]
216 11:03:20.160104 Using /lava-14786783 at stage 0
217 11:03:20.160191 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:03:20.160301 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/0/tests/1_kselftest-arm64'
219 11:03:22.914973 Running '/usr/bin/git checkout kernelci.org
220 11:03:23.066231 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:03:23.066603 uuid=14786783_1.6.2.3.5 testdef=None
222 11:03:23.066711 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:03:23.066906 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 11:03:23.067638 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:03:23.067841 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 11:03:23.068735 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:03:23.068950 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 11:03:23.069809 runner path: /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/0/tests/1_kselftest-arm64 test_uuid 14786783_1.6.2.3.5
232 11:03:23.069888 BOARD='mt8192-asurada-spherion-r0'
233 11:03:23.069947 BRANCH='cip'
234 11:03:23.070000 SKIPFILE='/dev/null'
235 11:03:23.070051 SKIP_INSTALL='True'
236 11:03:23.070114 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:03:23.070170 TST_CASENAME=''
238 11:03:23.070221 TST_CMDFILES='arm64'
239 11:03:23.070358 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:03:23.070552 Creating lava-test-runner.conf files
242 11:03:23.070608 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786783/lava-overlay-kk44ivbu/lava-14786783/0 for stage 0
243 11:03:23.070691 - 0_timesync-off
244 11:03:23.070750 - 1_kselftest-arm64
245 11:03:23.070837 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:03:23.070913 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 11:03:30.289000 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:03:30.289165 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 11:03:30.289275 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:03:30.289386 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 11:03:30.289495 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 11:03:30.433925 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:03:30.434070 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 11:03:30.434188 extracting modules file /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786783/extract-nfsrootfs-3uoqcuz9
255 11:03:30.651913 extracting modules file /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786783/extract-overlay-ramdisk-vhyu659p/ramdisk
256 11:03:30.873189 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:03:30.873329 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 11:03:30.873408 [common] Applying overlay to NFS
259 11:03:30.873467 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786783/compress-overlay-do2cnlzx/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786783/extract-nfsrootfs-3uoqcuz9
260 11:03:31.730634 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:03:31.730793 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 11:03:31.730881 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:03:31.730959 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 11:03:31.731041 Building ramdisk /var/lib/lava/dispatcher/tmp/14786783/extract-overlay-ramdisk-vhyu659p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786783/extract-overlay-ramdisk-vhyu659p/ramdisk
265 11:03:32.048389 >> 129845 blocks
266 11:03:34.155590 rename /var/lib/lava/dispatcher/tmp/14786783/extract-overlay-ramdisk-vhyu659p/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/ramdisk/ramdisk.cpio.gz
267 11:03:34.155760 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:03:34.155879 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 11:03:34.156008 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 11:03:34.156101 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/kernel/Image']
271 11:03:47.768371 Returned 0 in 13 seconds
272 11:03:47.768533 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/kernel/image.itb
273 11:03:48.108065 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:03:48.108193 output: Created: Wed Jul 10 12:03:48 2024
275 11:03:48.108256 output: Image 0 (kernel-1)
276 11:03:48.108311 output: Description:
277 11:03:48.108363 output: Created: Wed Jul 10 12:03:48 2024
278 11:03:48.108414 output: Type: Kernel Image
279 11:03:48.108464 output: Compression: lzma compressed
280 11:03:48.108516 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
281 11:03:48.108566 output: Architecture: AArch64
282 11:03:48.108613 output: OS: Linux
283 11:03:48.108661 output: Load Address: 0x00000000
284 11:03:48.108709 output: Entry Point: 0x00000000
285 11:03:48.108757 output: Hash algo: crc32
286 11:03:48.108805 output: Hash value: 9bb85fb9
287 11:03:48.108853 output: Image 1 (fdt-1)
288 11:03:48.108900 output: Description: mt8192-asurada-spherion-r0
289 11:03:48.108948 output: Created: Wed Jul 10 12:03:48 2024
290 11:03:48.108995 output: Type: Flat Device Tree
291 11:03:48.109042 output: Compression: uncompressed
292 11:03:48.109089 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:03:48.109137 output: Architecture: AArch64
294 11:03:48.109185 output: Hash algo: crc32
295 11:03:48.109232 output: Hash value: 0f8e4d2e
296 11:03:48.109278 output: Image 2 (ramdisk-1)
297 11:03:48.109325 output: Description: unavailable
298 11:03:48.109372 output: Created: Wed Jul 10 12:03:48 2024
299 11:03:48.109419 output: Type: RAMDisk Image
300 11:03:48.109466 output: Compression: uncompressed
301 11:03:48.109513 output: Data Size: 18710035 Bytes = 18271.52 KiB = 17.84 MiB
302 11:03:48.109560 output: Architecture: AArch64
303 11:03:48.109607 output: OS: Linux
304 11:03:48.109654 output: Load Address: unavailable
305 11:03:48.109700 output: Entry Point: unavailable
306 11:03:48.109748 output: Hash algo: crc32
307 11:03:48.109795 output: Hash value: 77b4ad84
308 11:03:48.109842 output: Default Configuration: 'conf-1'
309 11:03:48.109887 output: Configuration 0 (conf-1)
310 11:03:48.109934 output: Description: mt8192-asurada-spherion-r0
311 11:03:48.109981 output: Kernel: kernel-1
312 11:03:48.110028 output: Init Ramdisk: ramdisk-1
313 11:03:48.110075 output: FDT: fdt-1
314 11:03:48.110167 output: Loadables: kernel-1
315 11:03:48.110215 output:
316 11:03:48.110313 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:03:48.110387 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:03:48.110460 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 11:03:48.110533 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 11:03:48.110590 No LXC device requested
321 11:03:48.110655 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:03:48.110725 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 11:03:48.110792 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:03:48.110846 Checking files for TFTP limit of 4294967296 bytes.
325 11:03:48.111202 end: 1 tftp-deploy (duration 00:00:46) [common]
326 11:03:48.111288 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:03:48.111365 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:03:48.111452 substitutions:
329 11:03:48.111510 - {DTB}: 14786783/tftp-deploy-bq371b8n/dtb/mt8192-asurada-spherion-r0.dtb
330 11:03:48.111564 - {INITRD}: 14786783/tftp-deploy-bq371b8n/ramdisk/ramdisk.cpio.gz
331 11:03:48.111615 - {KERNEL}: 14786783/tftp-deploy-bq371b8n/kernel/Image
332 11:03:48.111665 - {LAVA_MAC}: None
333 11:03:48.111713 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786783/extract-nfsrootfs-3uoqcuz9
334 11:03:48.111762 - {NFS_SERVER_IP}: 192.168.201.1
335 11:03:48.111811 - {PRESEED_CONFIG}: None
336 11:03:48.111867 - {PRESEED_LOCAL}: None
337 11:03:48.111917 - {RAMDISK}: 14786783/tftp-deploy-bq371b8n/ramdisk/ramdisk.cpio.gz
338 11:03:48.111966 - {ROOT_PART}: None
339 11:03:48.112013 - {ROOT}: None
340 11:03:48.112061 - {SERVER_IP}: 192.168.201.1
341 11:03:48.112108 - {TEE}: None
342 11:03:48.112155 Parsed boot commands:
343 11:03:48.112201 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:03:48.112333 Parsed boot commands: tftpboot 192.168.201.1 14786783/tftp-deploy-bq371b8n/kernel/image.itb 14786783/tftp-deploy-bq371b8n/kernel/cmdline
345 11:03:48.112411 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:03:48.112483 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:03:48.112555 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:03:48.112624 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:03:48.112679 Not connected, no need to disconnect.
350 11:03:48.112743 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:03:48.112809 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:03:48.112862 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 11:03:48.115882 Setting prompt string to ['lava-test: # ']
354 11:03:48.116183 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:03:48.116276 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:03:48.116362 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:03:48.116439 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:03:48.116642 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
359 11:03:57.243451 >> Command sent successfully.
360 11:03:57.246705 Returned 0 in 9 seconds
361 11:03:57.246856 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:03:57.247107 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:03:57.247187 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:03:57.247258 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:03:57.247312 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:03:57.247372 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:03:57.247694 [Enter `^Ec?' for help]
369 11:03:58.627610
370 11:03:58.627741
371 11:03:58.627803 F0: 102B 0000
372 11:03:58.627861
373 11:03:58.627914 F3: 1001 0000 [0200]
374 11:03:58.627970
375 11:03:58.631216 F3: 1001 0000
376 11:03:58.631305
377 11:03:58.631385 F7: 102D 0000
378 11:03:58.631443
379 11:03:58.631500 F1: 0000 0000
380 11:03:58.631553
381 11:03:58.635144 V0: 0000 0000 [0001]
382 11:03:58.635255
383 11:03:58.635313 00: 0007 8000
384 11:03:58.635368
385 11:03:58.638611 01: 0000 0000
386 11:03:58.638687
387 11:03:58.638745 BP: 0C00 0209 [0000]
388 11:03:58.638798
389 11:03:58.638847 G0: 1182 0000
390 11:03:58.638896
391 11:03:58.642524 EC: 0000 0021 [4000]
392 11:03:58.642597
393 11:03:58.642654 S7: 0000 0000 [0000]
394 11:03:58.642707
395 11:03:58.646491 CC: 0000 0000 [0001]
396 11:03:58.646564
397 11:03:58.646623 T0: 0000 0040 [010F]
398 11:03:58.646676
399 11:03:58.649982 Jump to BL
400 11:03:58.650056
401 11:03:58.673579
402 11:03:58.673656
403 11:03:58.683817 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:03:58.687363 ARM64: Exception handlers installed.
405 11:03:58.687456 ARM64: Testing exception
406 11:03:58.691131 ARM64: Done test exception
407 11:03:58.698178 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:03:58.708724 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:03:58.715590 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:03:58.726030 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:03:58.732573 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:03:58.739068 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:03:58.750617 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:03:58.757150 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:03:58.776750 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:03:58.779950 WDT: Last reset was cold boot
417 11:03:58.783451 SPI1(PAD0) initialized at 2873684 Hz
418 11:03:58.786803 SPI5(PAD0) initialized at 992727 Hz
419 11:03:58.790494 VBOOT: Loading verstage.
420 11:03:58.796917 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:03:58.800607 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:03:58.803396 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:03:58.806739 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:03:58.814375 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:03:58.820864 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:03:58.831783 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 11:03:58.831861
428 11:03:58.831920
429 11:03:58.842171 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:03:58.844932 ARM64: Exception handlers installed.
431 11:03:58.848350 ARM64: Testing exception
432 11:03:58.848423 ARM64: Done test exception
433 11:03:58.855488 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:03:58.858432 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:03:58.872707 Probing TPM: . done!
436 11:03:58.872800 TPM ready after 0 ms
437 11:03:58.879534 Connected to device vid:did:rid of 1ae0:0028:00
438 11:03:58.886075 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 11:03:58.926209 Initialized TPM device CR50 revision 0
440 11:03:58.937210 tlcl_send_startup: Startup return code is 0
441 11:03:58.937291 TPM: setup succeeded
442 11:03:58.948830 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:03:58.957685 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:03:58.967866 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:03:58.977025 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:03:58.979895 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:03:58.983557 in-header: 03 07 00 00 08 00 00 00
448 11:03:58.986517 in-data: aa e4 47 04 13 02 00 00
449 11:03:58.990123 Chrome EC: UHEPI supported
450 11:03:58.996580 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:03:58.999788 in-header: 03 a9 00 00 08 00 00 00
452 11:03:59.003214 in-data: 84 60 60 08 00 00 00 00
453 11:03:59.003281 Phase 1
454 11:03:59.006782 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:03:59.013512 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:03:59.020296 VB2:vb2_check_recovery() Recovery was requested manually
457 11:03:59.023240 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:03:59.026822 Recovery requested (1009000e)
459 11:03:59.036945 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:03:59.040198 tlcl_extend: response is 0
461 11:03:59.048611 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:03:59.053647 tlcl_extend: response is 0
463 11:03:59.060163 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:03:59.080940 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:03:59.087527 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:03:59.087596
467 11:03:59.087659
468 11:03:59.097711 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:03:59.101401 ARM64: Exception handlers installed.
470 11:03:59.101489 ARM64: Testing exception
471 11:03:59.104997 ARM64: Done test exception
472 11:03:59.127474 pmic_efuse_setting: Set efuses in 11 msecs
473 11:03:59.130198 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:03:59.134445 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:03:59.141158 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:03:59.145385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:03:59.148679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:03:59.156112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:03:59.160038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:03:59.163373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:03:59.170765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:03:59.174900 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:03:59.178050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:03:59.181997 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:03:59.189273 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:03:59.192921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:03:59.200289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:03:59.204144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:03:59.208675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:03:59.215653 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:03:59.223572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:03:59.227102 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:03:59.234546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:03:59.237901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:03:59.245125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:03:59.249282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:03:59.256875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:03:59.260226 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:03:59.267741 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:03:59.271256 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:03:59.274916 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:03:59.282738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:03:59.285765 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:03:59.289905 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:03:59.297262 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:03:59.300619 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:03:59.304648 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:03:59.311509 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:03:59.315242 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:03:59.318961 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:03:59.326650 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:03:59.330327 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:03:59.333744 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:03:59.337420 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:03:59.345111 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:03:59.348391 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:03:59.352322 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:03:59.355958 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:03:59.359701 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:03:59.363184 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:03:59.370794 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:03:59.374570 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:03:59.377879 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:03:59.381933 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:03:59.389375 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:03:59.396786 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:03:59.404094 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:03:59.412129 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:03:59.419230 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:03:59.423363 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:03:59.426998 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:03:59.434242 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:03:59.440719 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x34
534 11:03:59.443766 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:03:59.451136 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:03:59.454609 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:03:59.463729 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 11:03:59.467187 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 11:03:59.473851 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 11:03:59.477404 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
541 11:03:59.480251 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 11:03:59.483790 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
543 11:03:59.487233 ADC[4]: Raw value=896300 ID=7
544 11:03:59.490809 ADC[3]: Raw value=213070 ID=1
545 11:03:59.490910 RAM Code: 0x71
546 11:03:59.497384 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 11:03:59.500443 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 11:03:59.510441 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 11:03:59.517216 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 11:03:59.520581 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 11:03:59.523876 in-header: 03 07 00 00 08 00 00 00
552 11:03:59.527267 in-data: aa e4 47 04 13 02 00 00
553 11:03:59.530744 Chrome EC: UHEPI supported
554 11:03:59.537176 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 11:03:59.540229 in-header: 03 a9 00 00 08 00 00 00
556 11:03:59.543734 in-data: 84 60 60 08 00 00 00 00
557 11:03:59.547189 MRC: failed to locate region type 0.
558 11:03:59.550911 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 11:03:59.554271 DRAM-K: Running full calibration
560 11:03:59.561287 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 11:03:59.564189 header.status = 0x0
562 11:03:59.567285 header.version = 0x6 (expected: 0x6)
563 11:03:59.570745 header.size = 0xd00 (expected: 0xd00)
564 11:03:59.570927 header.flags = 0x0
565 11:03:59.577275 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 11:03:59.596118 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
567 11:03:59.602834 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 11:03:59.605918 dram_init: ddr_geometry: 2
569 11:03:59.606619 [EMI] MDL number = 2
570 11:03:59.609363 [EMI] Get MDL freq = 0
571 11:03:59.612867 dram_init: ddr_type: 0
572 11:03:59.613418 is_discrete_lpddr4: 1
573 11:03:59.615997 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 11:03:59.616536
575 11:03:59.617017
576 11:03:59.619165 [Bian_co] ETT version 0.0.0.1
577 11:03:59.626224 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 11:03:59.626616
579 11:03:59.629122 dramc_set_vcore_voltage set vcore to 650000
580 11:03:59.629530 Read voltage for 800, 4
581 11:03:59.632329 Vio18 = 0
582 11:03:59.632890 Vcore = 650000
583 11:03:59.633209 Vdram = 0
584 11:03:59.635840 Vddq = 0
585 11:03:59.636473 Vmddr = 0
586 11:03:59.639178 dram_init: config_dvfs: 1
587 11:03:59.642780 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 11:03:59.649248 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 11:03:59.652164 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 11:03:59.655327 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 11:03:59.658697 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 11:03:59.662289 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 11:03:59.665429 MEM_TYPE=3, freq_sel=18
594 11:03:59.668854 sv_algorithm_assistance_LP4_1600
595 11:03:59.672349 ============ PULL DRAM RESETB DOWN ============
596 11:03:59.675521 ========== PULL DRAM RESETB DOWN end =========
597 11:03:59.682018 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 11:03:59.685661 ===================================
599 11:03:59.688665 LPDDR4 DRAM CONFIGURATION
600 11:03:59.688740 ===================================
601 11:03:59.691890 EX_ROW_EN[0] = 0x0
602 11:03:59.695637 EX_ROW_EN[1] = 0x0
603 11:03:59.695712 LP4Y_EN = 0x0
604 11:03:59.699080 WORK_FSP = 0x0
605 11:03:59.699155 WL = 0x2
606 11:03:59.701918 RL = 0x2
607 11:03:59.701992 BL = 0x2
608 11:03:59.705445 RPST = 0x0
609 11:03:59.705520 RD_PRE = 0x0
610 11:03:59.708869 WR_PRE = 0x1
611 11:03:59.708944 WR_PST = 0x0
612 11:03:59.711953 DBI_WR = 0x0
613 11:03:59.712028 DBI_RD = 0x0
614 11:03:59.715694 OTF = 0x1
615 11:03:59.719136 ===================================
616 11:03:59.722047 ===================================
617 11:03:59.722164 ANA top config
618 11:03:59.725718 ===================================
619 11:03:59.728746 DLL_ASYNC_EN = 0
620 11:03:59.732539 ALL_SLAVE_EN = 1
621 11:03:59.735432 NEW_RANK_MODE = 1
622 11:03:59.735508 DLL_IDLE_MODE = 1
623 11:03:59.738962 LP45_APHY_COMB_EN = 1
624 11:03:59.742090 TX_ODT_DIS = 1
625 11:03:59.745416 NEW_8X_MODE = 1
626 11:03:59.749154 ===================================
627 11:03:59.752176 ===================================
628 11:03:59.755910 data_rate = 1600
629 11:03:59.755984 CKR = 1
630 11:03:59.759123 DQ_P2S_RATIO = 8
631 11:03:59.762202 ===================================
632 11:03:59.765360 CA_P2S_RATIO = 8
633 11:03:59.768804 DQ_CA_OPEN = 0
634 11:03:59.772115 DQ_SEMI_OPEN = 0
635 11:03:59.772189 CA_SEMI_OPEN = 0
636 11:03:59.775809 CA_FULL_RATE = 0
637 11:03:59.779305 DQ_CKDIV4_EN = 1
638 11:03:59.782288 CA_CKDIV4_EN = 1
639 11:03:59.785420 CA_PREDIV_EN = 0
640 11:03:59.789001 PH8_DLY = 0
641 11:03:59.789077 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 11:03:59.792818 DQ_AAMCK_DIV = 4
643 11:03:59.795514 CA_AAMCK_DIV = 4
644 11:03:59.798955 CA_ADMCK_DIV = 4
645 11:03:59.802710 DQ_TRACK_CA_EN = 0
646 11:03:59.805698 CA_PICK = 800
647 11:03:59.805772 CA_MCKIO = 800
648 11:03:59.809045 MCKIO_SEMI = 0
649 11:03:59.812416 PLL_FREQ = 3068
650 11:03:59.815724 DQ_UI_PI_RATIO = 32
651 11:03:59.819116 CA_UI_PI_RATIO = 0
652 11:03:59.822288 ===================================
653 11:03:59.825525 ===================================
654 11:03:59.829098 memory_type:LPDDR4
655 11:03:59.829197 GP_NUM : 10
656 11:03:59.832177 SRAM_EN : 1
657 11:03:59.832253 MD32_EN : 0
658 11:03:59.835820 ===================================
659 11:03:59.839278 [ANA_INIT] >>>>>>>>>>>>>>
660 11:03:59.842293 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 11:03:59.845724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 11:03:59.848988 ===================================
663 11:03:59.852333 data_rate = 1600,PCW = 0X7600
664 11:03:59.855489 ===================================
665 11:03:59.859082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:03:59.862221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 11:03:59.868710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 11:03:59.875647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 11:03:59.879125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 11:03:59.882316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 11:03:59.882392 [ANA_INIT] flow start
672 11:03:59.885675 [ANA_INIT] PLL >>>>>>>>
673 11:03:59.888812 [ANA_INIT] PLL <<<<<<<<
674 11:03:59.888887 [ANA_INIT] MIDPI >>>>>>>>
675 11:03:59.892330 [ANA_INIT] MIDPI <<<<<<<<
676 11:03:59.896031 [ANA_INIT] DLL >>>>>>>>
677 11:03:59.896113 [ANA_INIT] flow end
678 11:03:59.898882 ============ LP4 DIFF to SE enter ============
679 11:03:59.905975 ============ LP4 DIFF to SE exit ============
680 11:03:59.906069 [ANA_INIT] <<<<<<<<<<<<<
681 11:03:59.908805 [Flow] Enable top DCM control >>>>>
682 11:03:59.912305 [Flow] Enable top DCM control <<<<<
683 11:03:59.915843 Enable DLL master slave shuffle
684 11:03:59.922140 ==============================================================
685 11:03:59.922216 Gating Mode config
686 11:03:59.929519 ==============================================================
687 11:03:59.933335 Config description:
688 11:03:59.940561 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 11:03:59.947945 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 11:03:59.951641 SELPH_MODE 0: By rank 1: By Phase
691 11:03:59.959490 ==============================================================
692 11:03:59.962851 GAT_TRACK_EN = 1
693 11:03:59.962927 RX_GATING_MODE = 2
694 11:03:59.966309 RX_GATING_TRACK_MODE = 2
695 11:03:59.969683 SELPH_MODE = 1
696 11:03:59.972973 PICG_EARLY_EN = 1
697 11:03:59.976414 VALID_LAT_VALUE = 1
698 11:03:59.982805 ==============================================================
699 11:03:59.986445 Enter into Gating configuration >>>>
700 11:03:59.989738 Exit from Gating configuration <<<<
701 11:03:59.992961 Enter into DVFS_PRE_config >>>>>
702 11:04:00.002824 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 11:04:00.006344 Exit from DVFS_PRE_config <<<<<
704 11:04:00.009364 Enter into PICG configuration >>>>
705 11:04:00.012850 Exit from PICG configuration <<<<
706 11:04:00.012926 [RX_INPUT] configuration >>>>>
707 11:04:00.015917 [RX_INPUT] configuration <<<<<
708 11:04:00.022737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 11:04:00.029451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 11:04:00.032478 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 11:04:00.039376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 11:04:00.045927 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 11:04:00.052981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 11:04:00.056125 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 11:04:00.059557 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 11:04:00.065913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 11:04:00.070068 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 11:04:00.072754 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 11:04:00.076340 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 11:04:00.079676 ===================================
721 11:04:00.083190 LPDDR4 DRAM CONFIGURATION
722 11:04:00.086574 ===================================
723 11:04:00.089828 EX_ROW_EN[0] = 0x0
724 11:04:00.089903 EX_ROW_EN[1] = 0x0
725 11:04:00.093098 LP4Y_EN = 0x0
726 11:04:00.093197 WORK_FSP = 0x0
727 11:04:00.096499 WL = 0x2
728 11:04:00.096578 RL = 0x2
729 11:04:00.099515 BL = 0x2
730 11:04:00.099622 RPST = 0x0
731 11:04:00.102713 RD_PRE = 0x0
732 11:04:00.102811 WR_PRE = 0x1
733 11:04:00.106372 WR_PST = 0x0
734 11:04:00.106443 DBI_WR = 0x0
735 11:04:00.109211 DBI_RD = 0x0
736 11:04:00.109302 OTF = 0x1
737 11:04:00.112819 ===================================
738 11:04:00.119448 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 11:04:00.122911 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 11:04:00.126237 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 11:04:00.129167 ===================================
742 11:04:00.132502 LPDDR4 DRAM CONFIGURATION
743 11:04:00.136274 ===================================
744 11:04:00.139396 EX_ROW_EN[0] = 0x10
745 11:04:00.139470 EX_ROW_EN[1] = 0x0
746 11:04:00.143035 LP4Y_EN = 0x0
747 11:04:00.143132 WORK_FSP = 0x0
748 11:04:00.146258 WL = 0x2
749 11:04:00.146347 RL = 0x2
750 11:04:00.149837 BL = 0x2
751 11:04:00.149921 RPST = 0x0
752 11:04:00.153117 RD_PRE = 0x0
753 11:04:00.153221 WR_PRE = 0x1
754 11:04:00.156296 WR_PST = 0x0
755 11:04:00.156388 DBI_WR = 0x0
756 11:04:00.159196 DBI_RD = 0x0
757 11:04:00.159270 OTF = 0x1
758 11:04:00.162691 ===================================
759 11:04:00.169297 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 11:04:00.174016 nWR fixed to 40
761 11:04:00.176962 [ModeRegInit_LP4] CH0 RK0
762 11:04:00.177058 [ModeRegInit_LP4] CH0 RK1
763 11:04:00.180530 [ModeRegInit_LP4] CH1 RK0
764 11:04:00.183529 [ModeRegInit_LP4] CH1 RK1
765 11:04:00.183600 match AC timing 13
766 11:04:00.191010 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 11:04:00.194059 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 11:04:00.196990 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 11:04:00.203817 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 11:04:00.207508 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 11:04:00.207617 [EMI DOE] emi_dcm 0
772 11:04:00.213885 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 11:04:00.213978 ==
774 11:04:00.217262 Dram Type= 6, Freq= 0, CH_0, rank 0
775 11:04:00.220633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 11:04:00.220731 ==
777 11:04:00.227353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 11:04:00.233818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 11:04:00.241330 [CA 0] Center 38 (7~69) winsize 63
780 11:04:00.244552 [CA 1] Center 38 (7~69) winsize 63
781 11:04:00.247850 [CA 2] Center 35 (5~66) winsize 62
782 11:04:00.251568 [CA 3] Center 35 (5~66) winsize 62
783 11:04:00.255065 [CA 4] Center 34 (4~65) winsize 62
784 11:04:00.257932 [CA 5] Center 34 (3~65) winsize 63
785 11:04:00.258034
786 11:04:00.261031 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 11:04:00.261109
788 11:04:00.264351 [CATrainingPosCal] consider 1 rank data
789 11:04:00.268073 u2DelayCellTimex100 = 270/100 ps
790 11:04:00.271768 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 11:04:00.274569 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
792 11:04:00.281218 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 11:04:00.284872 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 11:04:00.287754 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 11:04:00.291422 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
796 11:04:00.291536
797 11:04:00.294669 CA PerBit enable=1, Macro0, CA PI delay=34
798 11:04:00.294757
799 11:04:00.297994 [CBTSetCACLKResult] CA Dly = 34
800 11:04:00.298085 CS Dly: 6 (0~37)
801 11:04:00.298161 ==
802 11:04:00.301184 Dram Type= 6, Freq= 0, CH_0, rank 1
803 11:04:00.307798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 11:04:00.307878 ==
805 11:04:00.311748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 11:04:00.318415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 11:04:00.327418 [CA 0] Center 38 (7~69) winsize 63
808 11:04:00.330636 [CA 1] Center 38 (7~69) winsize 63
809 11:04:00.334110 [CA 2] Center 35 (5~66) winsize 62
810 11:04:00.337667 [CA 3] Center 35 (5~66) winsize 62
811 11:04:00.340964 [CA 4] Center 34 (4~65) winsize 62
812 11:04:00.344740 [CA 5] Center 34 (4~65) winsize 62
813 11:04:00.344819
814 11:04:00.347923 [CmdBusTrainingLP45] Vref(ca) range 1: 30
815 11:04:00.348001
816 11:04:00.351242 [CATrainingPosCal] consider 2 rank data
817 11:04:00.354066 u2DelayCellTimex100 = 270/100 ps
818 11:04:00.358007 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 11:04:00.361256 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
820 11:04:00.367639 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 11:04:00.370597 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 11:04:00.374165 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 11:04:00.377505 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 11:04:00.377580
825 11:04:00.380890 CA PerBit enable=1, Macro0, CA PI delay=34
826 11:04:00.380962
827 11:04:00.383965 [CBTSetCACLKResult] CA Dly = 34
828 11:04:00.384036 CS Dly: 6 (0~38)
829 11:04:00.384093
830 11:04:00.387486 ----->DramcWriteLeveling(PI) begin...
831 11:04:00.391071 ==
832 11:04:00.391140 Dram Type= 6, Freq= 0, CH_0, rank 0
833 11:04:00.397841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 11:04:00.397911 ==
835 11:04:00.401012 Write leveling (Byte 0): 32 => 32
836 11:04:00.404381 Write leveling (Byte 1): 28 => 28
837 11:04:00.404475 DramcWriteLeveling(PI) end<-----
838 11:04:00.407389
839 11:04:00.407466 ==
840 11:04:00.410917 Dram Type= 6, Freq= 0, CH_0, rank 0
841 11:04:00.414047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 11:04:00.414153 ==
843 11:04:00.418073 [Gating] SW mode calibration
844 11:04:00.424117 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 11:04:00.427353 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 11:04:00.434557 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 11:04:00.437888 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 11:04:00.440844 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
849 11:04:00.447735 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 11:04:00.450869 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:04:00.454177 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:04:00.461056 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:04:00.464197 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:04:00.467583 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:04:00.474586 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:04:00.477461 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:04:00.480913 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:04:00.487884 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:04:00.490848 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:04:00.494664 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:04:00.498156 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:04:00.504718 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:04:00.508893 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:04:00.511964 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
865 11:04:00.518535 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:04:00.522089 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:04:00.524920 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:04:00.528297 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:04:00.535258 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:04:00.538429 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:04:00.541884 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:04:00.548448 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:04:00.551644 0 9 12 | B1->B0 | 2828 2f2f | 1 1 | (1 1) (1 1)
874 11:04:00.555427 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 11:04:00.561839 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 11:04:00.564918 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 11:04:00.568346 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 11:04:00.575132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:04:00.578339 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:04:00.581752 0 10 8 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
881 11:04:00.588423 0 10 12 | B1->B0 | 2525 2525 | 0 0 | (1 0) (1 0)
882 11:04:00.591669 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 11:04:00.595142 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 11:04:00.601675 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 11:04:00.604859 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 11:04:00.608431 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:04:00.615131 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:04:00.618434 0 11 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
889 11:04:00.621956 0 11 12 | B1->B0 | 3737 4242 | 1 1 | (0 0) (0 0)
890 11:04:00.625329 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 11:04:00.631610 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 11:04:00.634989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 11:04:00.638803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 11:04:00.645330 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:04:00.648265 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:04:00.651631 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 11:04:00.658227 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 11:04:00.661717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:04:00.665118 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:04:00.671625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:04:00.675018 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:04:00.678686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:04:00.685027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:04:00.688826 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:04:00.692220 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:04:00.699029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:04:00.701810 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:04:00.705822 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:04:00.708527 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:04:00.715211 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:04:00.718539 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
912 11:04:00.721953 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
913 11:04:00.725721 Total UI for P1: 0, mck2ui 16
914 11:04:00.728435 best dqsien dly found for B0: ( 0, 14, 4)
915 11:04:00.735319 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
916 11:04:00.735407 Total UI for P1: 0, mck2ui 16
917 11:04:00.742036 best dqsien dly found for B1: ( 0, 14, 10)
918 11:04:00.745226 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
919 11:04:00.748540 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
920 11:04:00.748614
921 11:04:00.751802 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
922 11:04:00.755121 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
923 11:04:00.758885 [Gating] SW calibration Done
924 11:04:00.758982 ==
925 11:04:00.761870 Dram Type= 6, Freq= 0, CH_0, rank 0
926 11:04:00.765413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 11:04:00.765483 ==
928 11:04:00.768625 RX Vref Scan: 0
929 11:04:00.768695
930 11:04:00.768751 RX Vref 0 -> 0, step: 1
931 11:04:00.768804
932 11:04:00.771750 RX Delay -130 -> 252, step: 16
933 11:04:00.775142 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
934 11:04:00.781675 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 11:04:00.785118 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
936 11:04:00.788897 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
937 11:04:00.792388 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
938 11:04:00.795188 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
939 11:04:00.802131 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
940 11:04:00.805008 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
941 11:04:00.808402 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
942 11:04:00.812170 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
943 11:04:00.815363 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
944 11:04:00.822050 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
945 11:04:00.825053 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 11:04:00.828736 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
947 11:04:00.831943 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
948 11:04:00.835423 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
949 11:04:00.838478 ==
950 11:04:00.838550 Dram Type= 6, Freq= 0, CH_0, rank 0
951 11:04:00.845340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 11:04:00.845411 ==
953 11:04:00.845480 DQS Delay:
954 11:04:00.848581 DQS0 = 0, DQS1 = 0
955 11:04:00.848652 DQM Delay:
956 11:04:00.852487 DQM0 = 79, DQM1 = 70
957 11:04:00.852562 DQ Delay:
958 11:04:00.855568 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
959 11:04:00.858555 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
960 11:04:00.862147 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
961 11:04:00.865643 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 11:04:00.865720
963 11:04:00.865782
964 11:04:00.865836 ==
965 11:04:00.868884 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:04:00.872556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:04:00.872625 ==
968 11:04:00.872680
969 11:04:00.872731
970 11:04:00.875780 TX Vref Scan disable
971 11:04:00.875841 == TX Byte 0 ==
972 11:04:00.882097 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
973 11:04:00.885343 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
974 11:04:00.888971 == TX Byte 1 ==
975 11:04:00.892151 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
976 11:04:00.895278 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
977 11:04:00.895349 ==
978 11:04:00.898843 Dram Type= 6, Freq= 0, CH_0, rank 0
979 11:04:00.901958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 11:04:00.902047 ==
981 11:04:00.916820 TX Vref=22, minBit 0, minWin=27, winSum=437
982 11:04:00.920154 TX Vref=24, minBit 7, minWin=26, winSum=440
983 11:04:00.923297 TX Vref=26, minBit 5, minWin=27, winSum=445
984 11:04:00.927450 TX Vref=28, minBit 10, minWin=27, winSum=446
985 11:04:00.930498 TX Vref=30, minBit 2, minWin=27, winSum=445
986 11:04:00.933353 TX Vref=32, minBit 2, minWin=27, winSum=442
987 11:04:00.940467 [TxChooseVref] Worse bit 10, Min win 27, Win sum 446, Final Vref 28
988 11:04:00.940538
989 11:04:00.943488 Final TX Range 1 Vref 28
990 11:04:00.943552
991 11:04:00.943605 ==
992 11:04:00.947272 Dram Type= 6, Freq= 0, CH_0, rank 0
993 11:04:00.950150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 11:04:00.950228 ==
995 11:04:00.950288
996 11:04:00.953504
997 11:04:00.953569 TX Vref Scan disable
998 11:04:00.956909 == TX Byte 0 ==
999 11:04:00.960437 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1000 11:04:00.963445 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1001 11:04:00.967236 == TX Byte 1 ==
1002 11:04:00.970051 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1003 11:04:00.973711 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1004 11:04:00.977122
1005 11:04:00.977193 [DATLAT]
1006 11:04:00.977252 Freq=800, CH0 RK0
1007 11:04:00.977307
1008 11:04:00.980913 DATLAT Default: 0xa
1009 11:04:00.980980 0, 0xFFFF, sum = 0
1010 11:04:00.983592 1, 0xFFFF, sum = 0
1011 11:04:00.983662 2, 0xFFFF, sum = 0
1012 11:04:00.987070 3, 0xFFFF, sum = 0
1013 11:04:00.987143 4, 0xFFFF, sum = 0
1014 11:04:00.990144 5, 0xFFFF, sum = 0
1015 11:04:00.990207 6, 0xFFFF, sum = 0
1016 11:04:00.994026 7, 0xFFFF, sum = 0
1017 11:04:00.997133 8, 0xFFFF, sum = 0
1018 11:04:00.997200 9, 0x0, sum = 1
1019 11:04:00.997255 10, 0x0, sum = 2
1020 11:04:01.000319 11, 0x0, sum = 3
1021 11:04:01.000388 12, 0x0, sum = 4
1022 11:04:01.003665 best_step = 10
1023 11:04:01.003733
1024 11:04:01.003787 ==
1025 11:04:01.007255 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 11:04:01.010497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 11:04:01.010566 ==
1028 11:04:01.013731 RX Vref Scan: 1
1029 11:04:01.013797
1030 11:04:01.013860 Set Vref Range= 32 -> 127
1031 11:04:01.013913
1032 11:04:01.016893 RX Vref 32 -> 127, step: 1
1033 11:04:01.016959
1034 11:04:01.020572 RX Delay -111 -> 252, step: 8
1035 11:04:01.020637
1036 11:04:01.023586 Set Vref, RX VrefLevel [Byte0]: 32
1037 11:04:01.027040 [Byte1]: 32
1038 11:04:01.027105
1039 11:04:01.030237 Set Vref, RX VrefLevel [Byte0]: 33
1040 11:04:01.033457 [Byte1]: 33
1041 11:04:01.037785
1042 11:04:01.037857 Set Vref, RX VrefLevel [Byte0]: 34
1043 11:04:01.040722 [Byte1]: 34
1044 11:04:01.044826
1045 11:04:01.044903 Set Vref, RX VrefLevel [Byte0]: 35
1046 11:04:01.048286 [Byte1]: 35
1047 11:04:01.052505
1048 11:04:01.052569 Set Vref, RX VrefLevel [Byte0]: 36
1049 11:04:01.056136 [Byte1]: 36
1050 11:04:01.060682
1051 11:04:01.060746 Set Vref, RX VrefLevel [Byte0]: 37
1052 11:04:01.063953 [Byte1]: 37
1053 11:04:01.068040
1054 11:04:01.068109 Set Vref, RX VrefLevel [Byte0]: 38
1055 11:04:01.071148 [Byte1]: 38
1056 11:04:01.075808
1057 11:04:01.075887 Set Vref, RX VrefLevel [Byte0]: 39
1058 11:04:01.078896 [Byte1]: 39
1059 11:04:01.083304
1060 11:04:01.083384 Set Vref, RX VrefLevel [Byte0]: 40
1061 11:04:01.086504 [Byte1]: 40
1062 11:04:01.090907
1063 11:04:01.090978 Set Vref, RX VrefLevel [Byte0]: 41
1064 11:04:01.094042 [Byte1]: 41
1065 11:04:01.098579
1066 11:04:01.098652 Set Vref, RX VrefLevel [Byte0]: 42
1067 11:04:01.101780 [Byte1]: 42
1068 11:04:01.106047
1069 11:04:01.106141 Set Vref, RX VrefLevel [Byte0]: 43
1070 11:04:01.109467 [Byte1]: 43
1071 11:04:01.113725
1072 11:04:01.113818 Set Vref, RX VrefLevel [Byte0]: 44
1073 11:04:01.117255 [Byte1]: 44
1074 11:04:01.121735
1075 11:04:01.121807 Set Vref, RX VrefLevel [Byte0]: 45
1076 11:04:01.124846 [Byte1]: 45
1077 11:04:01.129144
1078 11:04:01.129216 Set Vref, RX VrefLevel [Byte0]: 46
1079 11:04:01.132576 [Byte1]: 46
1080 11:04:01.136722
1081 11:04:01.136792 Set Vref, RX VrefLevel [Byte0]: 47
1082 11:04:01.139845 [Byte1]: 47
1083 11:04:01.144317
1084 11:04:01.144385 Set Vref, RX VrefLevel [Byte0]: 48
1085 11:04:01.147752 [Byte1]: 48
1086 11:04:01.151794
1087 11:04:01.151864 Set Vref, RX VrefLevel [Byte0]: 49
1088 11:04:01.155279 [Byte1]: 49
1089 11:04:01.159983
1090 11:04:01.160053 Set Vref, RX VrefLevel [Byte0]: 50
1091 11:04:01.163072 [Byte1]: 50
1092 11:04:01.167512
1093 11:04:01.167605 Set Vref, RX VrefLevel [Byte0]: 51
1094 11:04:01.170768 [Byte1]: 51
1095 11:04:01.175253
1096 11:04:01.175325 Set Vref, RX VrefLevel [Byte0]: 52
1097 11:04:01.178288 [Byte1]: 52
1098 11:04:01.182554
1099 11:04:01.182624 Set Vref, RX VrefLevel [Byte0]: 53
1100 11:04:01.186095 [Byte1]: 53
1101 11:04:01.190052
1102 11:04:01.190144 Set Vref, RX VrefLevel [Byte0]: 54
1103 11:04:01.193339 [Byte1]: 54
1104 11:04:01.197803
1105 11:04:01.197897 Set Vref, RX VrefLevel [Byte0]: 55
1106 11:04:01.201009 [Byte1]: 55
1107 11:04:01.205574
1108 11:04:01.205647 Set Vref, RX VrefLevel [Byte0]: 56
1109 11:04:01.208750 [Byte1]: 56
1110 11:04:01.213451
1111 11:04:01.213534 Set Vref, RX VrefLevel [Byte0]: 57
1112 11:04:01.216938 [Byte1]: 57
1113 11:04:01.221159
1114 11:04:01.221227 Set Vref, RX VrefLevel [Byte0]: 58
1115 11:04:01.224136 [Byte1]: 58
1116 11:04:01.228233
1117 11:04:01.228302 Set Vref, RX VrefLevel [Byte0]: 59
1118 11:04:01.231623 [Byte1]: 59
1119 11:04:01.236157
1120 11:04:01.236226 Set Vref, RX VrefLevel [Byte0]: 60
1121 11:04:01.239396 [Byte1]: 60
1122 11:04:01.243784
1123 11:04:01.243854 Set Vref, RX VrefLevel [Byte0]: 61
1124 11:04:01.247251 [Byte1]: 61
1125 11:04:01.251380
1126 11:04:01.251457 Set Vref, RX VrefLevel [Byte0]: 62
1127 11:04:01.254490 [Byte1]: 62
1128 11:04:01.259165
1129 11:04:01.259235 Set Vref, RX VrefLevel [Byte0]: 63
1130 11:04:01.262430 [Byte1]: 63
1131 11:04:01.266564
1132 11:04:01.266632 Set Vref, RX VrefLevel [Byte0]: 64
1133 11:04:01.270276 [Byte1]: 64
1134 11:04:01.274603
1135 11:04:01.274700 Set Vref, RX VrefLevel [Byte0]: 65
1136 11:04:01.277844 [Byte1]: 65
1137 11:04:01.282331
1138 11:04:01.282430 Set Vref, RX VrefLevel [Byte0]: 66
1139 11:04:01.285172 [Byte1]: 66
1140 11:04:01.289795
1141 11:04:01.289891 Set Vref, RX VrefLevel [Byte0]: 67
1142 11:04:01.292987 [Byte1]: 67
1143 11:04:01.297058
1144 11:04:01.297150 Set Vref, RX VrefLevel [Byte0]: 68
1145 11:04:01.300481 [Byte1]: 68
1146 11:04:01.305142
1147 11:04:01.305214 Set Vref, RX VrefLevel [Byte0]: 69
1148 11:04:01.311198 [Byte1]: 69
1149 11:04:01.311272
1150 11:04:01.314661 Set Vref, RX VrefLevel [Byte0]: 70
1151 11:04:01.318328 [Byte1]: 70
1152 11:04:01.318425
1153 11:04:01.321551 Set Vref, RX VrefLevel [Byte0]: 71
1154 11:04:01.324907 [Byte1]: 71
1155 11:04:01.325000
1156 11:04:01.328239 Set Vref, RX VrefLevel [Byte0]: 72
1157 11:04:01.331275 [Byte1]: 72
1158 11:04:01.335255
1159 11:04:01.335355 Set Vref, RX VrefLevel [Byte0]: 73
1160 11:04:01.338710 [Byte1]: 73
1161 11:04:01.343633
1162 11:04:01.343724 Set Vref, RX VrefLevel [Byte0]: 74
1163 11:04:01.346557 [Byte1]: 74
1164 11:04:01.350669
1165 11:04:01.350736 Set Vref, RX VrefLevel [Byte0]: 75
1166 11:04:01.353815 [Byte1]: 75
1167 11:04:01.358812
1168 11:04:01.358890 Set Vref, RX VrefLevel [Byte0]: 76
1169 11:04:01.361618 [Byte1]: 76
1170 11:04:01.365939
1171 11:04:01.366032 Set Vref, RX VrefLevel [Byte0]: 77
1172 11:04:01.369397 [Byte1]: 77
1173 11:04:01.374107
1174 11:04:01.374180 Final RX Vref Byte 0 = 57 to rank0
1175 11:04:01.377168 Final RX Vref Byte 1 = 58 to rank0
1176 11:04:01.380764 Final RX Vref Byte 0 = 57 to rank1
1177 11:04:01.384180 Final RX Vref Byte 1 = 58 to rank1==
1178 11:04:01.387225 Dram Type= 6, Freq= 0, CH_0, rank 0
1179 11:04:01.390605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 11:04:01.393652 ==
1181 11:04:01.393746 DQS Delay:
1182 11:04:01.393837 DQS0 = 0, DQS1 = 0
1183 11:04:01.397056 DQM Delay:
1184 11:04:01.397157 DQM0 = 81, DQM1 = 68
1185 11:04:01.400759 DQ Delay:
1186 11:04:01.403773 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1187 11:04:01.403867 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1188 11:04:01.407027 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1189 11:04:01.413567 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1190 11:04:01.413663
1191 11:04:01.413747
1192 11:04:01.420065 [DQSOSCAuto] RK0, (LSB)MR18= 0x302f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1193 11:04:01.423402 CH0 RK0: MR19=606, MR18=302F
1194 11:04:01.430169 CH0_RK0: MR19=0x606, MR18=0x302F, DQSOSC=397, MR23=63, INC=93, DEC=62
1195 11:04:01.430244
1196 11:04:01.433732 ----->DramcWriteLeveling(PI) begin...
1197 11:04:01.433832 ==
1198 11:04:01.437046 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 11:04:01.440123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 11:04:01.440217 ==
1201 11:04:01.443400 Write leveling (Byte 0): 30 => 30
1202 11:04:01.446982 Write leveling (Byte 1): 29 => 29
1203 11:04:01.450143 DramcWriteLeveling(PI) end<-----
1204 11:04:01.450212
1205 11:04:01.450294 ==
1206 11:04:01.453256 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 11:04:01.456970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 11:04:01.457068 ==
1209 11:04:01.460522 [Gating] SW mode calibration
1210 11:04:01.466919 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1211 11:04:01.473376 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1212 11:04:01.477129 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1213 11:04:01.480579 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 11:04:01.486989 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1215 11:04:01.490093 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:04:01.493681 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:04:01.500266 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:04:01.503426 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:04:01.506802 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:04:01.513657 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:04:01.517456 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:04:01.520309 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:04:01.527935 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:04:01.530155 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:04:01.533682 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:04:01.536785 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:04:01.543916 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:04:01.547154 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1229 11:04:01.550389 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1230 11:04:01.597835 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1231 11:04:01.597973 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1232 11:04:01.598254 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:04:01.598356 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:04:01.598457 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:04:01.598563 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:04:01.598658 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:04:01.598762 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1238 11:04:01.598822 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
1239 11:04:01.599377 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1240 11:04:01.639934 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 11:04:01.640066 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 11:04:01.640345 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 11:04:01.640437 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 11:04:01.641174 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:04:01.641536 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1246 11:04:01.641634 0 10 8 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (1 0)
1247 11:04:01.641900 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:04:01.642009 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:04:01.645110 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:04:01.648274 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:04:01.648350 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:04:01.651945 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:04:01.658234 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1254 11:04:01.661753 0 11 8 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
1255 11:04:01.665213 0 11 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1256 11:04:01.671401 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 11:04:01.674811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 11:04:01.678433 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:04:01.684772 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:04:01.688528 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:04:01.691375 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1262 11:04:01.698498 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1263 11:04:01.701854 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:04:01.705152 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:04:01.708289 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:04:01.714904 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:04:01.718556 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:04:01.721720 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:04:01.728280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:04:01.731720 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:04:01.735002 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:04:01.741686 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:04:01.745262 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:04:01.748488 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:04:01.754932 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:04:01.758543 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:04:01.762322 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:04:01.768553 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 11:04:01.771527 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 11:04:01.775462 Total UI for P1: 0, mck2ui 16
1281 11:04:01.778288 best dqsien dly found for B0: ( 0, 14, 8)
1282 11:04:01.781822 Total UI for P1: 0, mck2ui 16
1283 11:04:01.785213 best dqsien dly found for B1: ( 0, 14, 8)
1284 11:04:01.788707 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1285 11:04:01.791944 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1286 11:04:01.792022
1287 11:04:01.795249 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1288 11:04:01.798800 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1289 11:04:01.801716 [Gating] SW calibration Done
1290 11:04:01.801818 ==
1291 11:04:01.805414 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 11:04:01.808197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 11:04:01.808276 ==
1294 11:04:01.812091 RX Vref Scan: 0
1295 11:04:01.812171
1296 11:04:01.815169 RX Vref 0 -> 0, step: 1
1297 11:04:01.815278
1298 11:04:01.815365 RX Delay -130 -> 252, step: 16
1299 11:04:01.821955 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1300 11:04:01.824802 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1301 11:04:01.828326 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1302 11:04:01.831975 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1303 11:04:01.835149 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1304 11:04:01.841602 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1305 11:04:01.844914 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1306 11:04:01.848726 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1307 11:04:01.852071 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1308 11:04:01.855460 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1309 11:04:01.858539 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1310 11:04:01.865107 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1311 11:04:01.868472 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1312 11:04:01.872039 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1313 11:04:01.874878 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1314 11:04:01.881939 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1315 11:04:01.882060 ==
1316 11:04:01.885014 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 11:04:01.888569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 11:04:01.888685 ==
1319 11:04:01.888754 DQS Delay:
1320 11:04:01.891777 DQS0 = 0, DQS1 = 0
1321 11:04:01.891884 DQM Delay:
1322 11:04:01.895264 DQM0 = 75, DQM1 = 69
1323 11:04:01.895348 DQ Delay:
1324 11:04:01.898569 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1325 11:04:01.901687 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1326 11:04:01.905512 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1327 11:04:01.908675 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1328 11:04:01.908781
1329 11:04:01.908875
1330 11:04:01.908957 ==
1331 11:04:01.912060 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 11:04:01.915437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 11:04:01.915549 ==
1334 11:04:01.915644
1335 11:04:01.915725
1336 11:04:01.918438 TX Vref Scan disable
1337 11:04:01.921893 == TX Byte 0 ==
1338 11:04:01.924923 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1339 11:04:01.928416 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1340 11:04:01.932288 == TX Byte 1 ==
1341 11:04:01.935368 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1342 11:04:01.938265 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1343 11:04:01.938351 ==
1344 11:04:01.941873 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 11:04:01.948311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 11:04:01.948395 ==
1347 11:04:01.959746 TX Vref=22, minBit 1, minWin=27, winSum=438
1348 11:04:01.962922 TX Vref=24, minBit 1, minWin=27, winSum=437
1349 11:04:01.966556 TX Vref=26, minBit 2, minWin=27, winSum=442
1350 11:04:01.970005 TX Vref=28, minBit 1, minWin=27, winSum=443
1351 11:04:01.972992 TX Vref=30, minBit 3, minWin=27, winSum=445
1352 11:04:01.976547 TX Vref=32, minBit 3, minWin=27, winSum=444
1353 11:04:01.982903 [TxChooseVref] Worse bit 3, Min win 27, Win sum 445, Final Vref 30
1354 11:04:01.983042
1355 11:04:01.986565 Final TX Range 1 Vref 30
1356 11:04:01.986689
1357 11:04:01.986790 ==
1358 11:04:01.989669 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 11:04:01.992864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 11:04:01.992982 ==
1361 11:04:01.993080
1362 11:04:01.996321
1363 11:04:01.996419 TX Vref Scan disable
1364 11:04:01.999656 == TX Byte 0 ==
1365 11:04:02.002934 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1366 11:04:02.006508 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1367 11:04:02.009456 == TX Byte 1 ==
1368 11:04:02.012961 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1369 11:04:02.016335 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1370 11:04:02.019715
1371 11:04:02.019792 [DATLAT]
1372 11:04:02.019851 Freq=800, CH0 RK1
1373 11:04:02.019906
1374 11:04:02.022916 DATLAT Default: 0xa
1375 11:04:02.022992 0, 0xFFFF, sum = 0
1376 11:04:02.026568 1, 0xFFFF, sum = 0
1377 11:04:02.026645 2, 0xFFFF, sum = 0
1378 11:04:02.029698 3, 0xFFFF, sum = 0
1379 11:04:02.029776 4, 0xFFFF, sum = 0
1380 11:04:02.033218 5, 0xFFFF, sum = 0
1381 11:04:02.033294 6, 0xFFFF, sum = 0
1382 11:04:02.036825 7, 0xFFFF, sum = 0
1383 11:04:02.039766 8, 0xFFFF, sum = 0
1384 11:04:02.039843 9, 0x0, sum = 1
1385 11:04:02.039903 10, 0x0, sum = 2
1386 11:04:02.043552 11, 0x0, sum = 3
1387 11:04:02.043629 12, 0x0, sum = 4
1388 11:04:02.046570 best_step = 10
1389 11:04:02.046646
1390 11:04:02.046704 ==
1391 11:04:02.049816 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 11:04:02.053248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 11:04:02.053326 ==
1394 11:04:02.056339 RX Vref Scan: 0
1395 11:04:02.056415
1396 11:04:02.056473 RX Vref 0 -> 0, step: 1
1397 11:04:02.056527
1398 11:04:02.059615 RX Delay -111 -> 252, step: 8
1399 11:04:02.066484 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1400 11:04:02.069908 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1401 11:04:02.073493 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1402 11:04:02.076505 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1403 11:04:02.079938 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1404 11:04:02.086848 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1405 11:04:02.090263 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1406 11:04:02.093535 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1407 11:04:02.096848 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1408 11:04:02.100096 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1409 11:04:02.103305 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1410 11:04:02.110042 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1411 11:04:02.113749 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1412 11:04:02.116587 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1413 11:04:02.120143 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1414 11:04:02.126710 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1415 11:04:02.126787 ==
1416 11:04:02.130664 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 11:04:02.133724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 11:04:02.133800 ==
1419 11:04:02.133859 DQS Delay:
1420 11:04:02.137303 DQS0 = 0, DQS1 = 0
1421 11:04:02.137382 DQM Delay:
1422 11:04:02.140720 DQM0 = 78, DQM1 = 69
1423 11:04:02.140800 DQ Delay:
1424 11:04:02.143706 DQ0 =80, DQ1 =80, DQ2 =76, DQ3 =72
1425 11:04:02.146834 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1426 11:04:02.150260 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =60
1427 11:04:02.153829 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1428 11:04:02.153896
1429 11:04:02.153957
1430 11:04:02.160412 [DQSOSCAuto] RK1, (LSB)MR18= 0x512c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
1431 11:04:02.163384 CH0 RK1: MR19=606, MR18=512C
1432 11:04:02.170053 CH0_RK1: MR19=0x606, MR18=0x512C, DQSOSC=389, MR23=63, INC=97, DEC=65
1433 11:04:02.173971 [RxdqsGatingPostProcess] freq 800
1434 11:04:02.177291 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 11:04:02.180494 Pre-setting of DQS Precalculation
1436 11:04:02.187094 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 11:04:02.187204 ==
1438 11:04:02.190670 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 11:04:02.193812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 11:04:02.193906 ==
1441 11:04:02.200273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 11:04:02.207335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 11:04:02.214530 [CA 0] Center 36 (6~66) winsize 61
1444 11:04:02.218423 [CA 1] Center 36 (6~67) winsize 62
1445 11:04:02.221477 [CA 2] Center 34 (5~64) winsize 60
1446 11:04:02.224598 [CA 3] Center 34 (4~64) winsize 61
1447 11:04:02.228353 [CA 4] Center 34 (4~64) winsize 61
1448 11:04:02.231242 [CA 5] Center 33 (3~64) winsize 62
1449 11:04:02.231311
1450 11:04:02.234488 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1451 11:04:02.234553
1452 11:04:02.237918 [CATrainingPosCal] consider 1 rank data
1453 11:04:02.241537 u2DelayCellTimex100 = 270/100 ps
1454 11:04:02.244747 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1455 11:04:02.248441 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1456 11:04:02.254861 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1457 11:04:02.257945 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1458 11:04:02.261238 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1459 11:04:02.264945 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1460 11:04:02.265014
1461 11:04:02.268112 CA PerBit enable=1, Macro0, CA PI delay=33
1462 11:04:02.268180
1463 11:04:02.271712 [CBTSetCACLKResult] CA Dly = 33
1464 11:04:02.271782 CS Dly: 5 (0~36)
1465 11:04:02.274603 ==
1466 11:04:02.274671 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 11:04:02.281328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 11:04:02.281439 ==
1469 11:04:02.284765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 11:04:02.291348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 11:04:02.300952 [CA 0] Center 36 (6~66) winsize 61
1472 11:04:02.304443 [CA 1] Center 36 (6~67) winsize 62
1473 11:04:02.307878 [CA 2] Center 35 (5~65) winsize 61
1474 11:04:02.310725 [CA 3] Center 33 (3~64) winsize 62
1475 11:04:02.314069 [CA 4] Center 34 (4~65) winsize 62
1476 11:04:02.317626 [CA 5] Center 33 (3~64) winsize 62
1477 11:04:02.317722
1478 11:04:02.321070 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1479 11:04:02.321135
1480 11:04:02.324135 [CATrainingPosCal] consider 2 rank data
1481 11:04:02.327989 u2DelayCellTimex100 = 270/100 ps
1482 11:04:02.331265 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1483 11:04:02.334363 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1484 11:04:02.341009 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1485 11:04:02.344755 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1486 11:04:02.347722 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1487 11:04:02.351311 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1488 11:04:02.351380
1489 11:04:02.354492 CA PerBit enable=1, Macro0, CA PI delay=33
1490 11:04:02.354581
1491 11:04:02.357507 [CBTSetCACLKResult] CA Dly = 33
1492 11:04:02.357585 CS Dly: 5 (0~37)
1493 11:04:02.357644
1494 11:04:02.360855 ----->DramcWriteLeveling(PI) begin...
1495 11:04:02.360921 ==
1496 11:04:02.364193 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 11:04:02.371016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 11:04:02.371084 ==
1499 11:04:02.374296 Write leveling (Byte 0): 26 => 26
1500 11:04:02.377410 Write leveling (Byte 1): 32 => 32
1501 11:04:02.377506 DramcWriteLeveling(PI) end<-----
1502 11:04:02.381121
1503 11:04:02.381213 ==
1504 11:04:02.384143 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 11:04:02.387671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 11:04:02.387743 ==
1507 11:04:02.390713 [Gating] SW mode calibration
1508 11:04:02.397619 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 11:04:02.401199 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 11:04:02.407586 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1511 11:04:02.411078 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1512 11:04:02.414700 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1513 11:04:02.421246 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:04:02.424875 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:04:02.427928 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:04:02.434403 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:04:02.437838 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:04:02.440961 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:04:02.448056 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:04:02.451122 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:04:02.454859 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:04:02.457746 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:04:02.464341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:04:02.467778 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:04:02.471060 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:04:02.477745 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:04:02.481284 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1528 11:04:02.484573 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:04:02.490844 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:04:02.494232 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:04:02.497650 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:04:02.504615 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:04:02.507400 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:04:02.510867 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:04:02.517666 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:04:02.520859 0 9 8 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
1537 11:04:02.524094 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 11:04:02.531393 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 11:04:02.534135 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 11:04:02.537448 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 11:04:02.544374 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 11:04:02.547309 0 10 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1543 11:04:02.550765 0 10 4 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
1544 11:04:02.557271 0 10 8 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
1545 11:04:02.561003 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:04:02.564525 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:04:02.570816 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:04:02.574610 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:04:02.577703 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:04:02.581084 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:04:02.587833 0 11 4 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
1552 11:04:02.590699 0 11 8 | B1->B0 | 3b3b 4140 | 0 1 | (0 0) (0 0)
1553 11:04:02.594201 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 11:04:02.600596 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:04:02.605084 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 11:04:02.607660 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 11:04:02.614384 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:04:02.617811 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:04:02.621201 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:04:02.627589 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1561 11:04:02.631038 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:04:02.634312 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:04:02.640864 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:04:02.644426 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:04:02.647738 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:04:02.654114 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:04:02.657629 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:04:02.660774 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:04:02.667360 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:04:02.671014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:04:02.674066 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:04:02.677638 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:04:02.684129 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:04:02.687734 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:04:02.690682 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:04:02.698269 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 11:04:02.701024 Total UI for P1: 0, mck2ui 16
1578 11:04:02.704067 best dqsien dly found for B0: ( 0, 14, 6)
1579 11:04:02.704136 Total UI for P1: 0, mck2ui 16
1580 11:04:02.710713 best dqsien dly found for B1: ( 0, 14, 6)
1581 11:04:02.714351 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1582 11:04:02.717632 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1583 11:04:02.717724
1584 11:04:02.720965 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1585 11:04:02.724721 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1586 11:04:02.727545 [Gating] SW calibration Done
1587 11:04:02.727614 ==
1588 11:04:02.731043 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 11:04:02.734386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 11:04:02.734477 ==
1591 11:04:02.737656 RX Vref Scan: 0
1592 11:04:02.737747
1593 11:04:02.737805 RX Vref 0 -> 0, step: 1
1594 11:04:02.737858
1595 11:04:02.740989 RX Delay -130 -> 252, step: 16
1596 11:04:02.744020 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1597 11:04:02.750984 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1598 11:04:02.754404 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1599 11:04:02.757420 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1600 11:04:02.760756 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1601 11:04:02.764230 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1602 11:04:02.771165 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1603 11:04:02.774641 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1604 11:04:02.777588 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1605 11:04:02.781261 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1606 11:04:02.784333 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1607 11:04:02.790970 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1608 11:04:02.794576 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1609 11:04:02.797625 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1610 11:04:02.801045 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1611 11:04:02.804151 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1612 11:04:02.804218 ==
1613 11:04:02.807787 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 11:04:02.814358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 11:04:02.814433 ==
1616 11:04:02.814492 DQS Delay:
1617 11:04:02.817852 DQS0 = 0, DQS1 = 0
1618 11:04:02.817925 DQM Delay:
1619 11:04:02.817983 DQM0 = 81, DQM1 = 71
1620 11:04:02.821201 DQ Delay:
1621 11:04:02.824267 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1622 11:04:02.827467 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1623 11:04:02.831083 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1624 11:04:02.834113 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1625 11:04:02.834210
1626 11:04:02.834271
1627 11:04:02.834326 ==
1628 11:04:02.837758 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 11:04:02.840858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 11:04:02.840929 ==
1631 11:04:02.840985
1632 11:04:02.841036
1633 11:04:02.844349 TX Vref Scan disable
1634 11:04:02.844412 == TX Byte 0 ==
1635 11:04:02.851400 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1636 11:04:02.854463 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1637 11:04:02.854530 == TX Byte 1 ==
1638 11:04:02.861021 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1639 11:04:02.864669 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1640 11:04:02.864737 ==
1641 11:04:02.867444 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 11:04:02.870727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 11:04:02.870794 ==
1644 11:04:02.885813 TX Vref=22, minBit 8, minWin=27, winSum=447
1645 11:04:02.888958 TX Vref=24, minBit 8, minWin=27, winSum=450
1646 11:04:02.892471 TX Vref=26, minBit 11, minWin=27, winSum=455
1647 11:04:02.895819 TX Vref=28, minBit 1, minWin=28, winSum=457
1648 11:04:02.899192 TX Vref=30, minBit 0, minWin=28, winSum=456
1649 11:04:02.902800 TX Vref=32, minBit 9, minWin=27, winSum=457
1650 11:04:02.909216 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 28
1651 11:04:02.909303
1652 11:04:02.912411 Final TX Range 1 Vref 28
1653 11:04:02.912501
1654 11:04:02.912561 ==
1655 11:04:02.916221 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 11:04:02.918961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 11:04:02.919029 ==
1658 11:04:02.919084
1659 11:04:02.922422
1660 11:04:02.922492 TX Vref Scan disable
1661 11:04:02.925557 == TX Byte 0 ==
1662 11:04:02.929346 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1663 11:04:02.932936 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1664 11:04:02.935835 == TX Byte 1 ==
1665 11:04:02.939159 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1666 11:04:02.942431 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1667 11:04:02.945997
1668 11:04:02.946070 [DATLAT]
1669 11:04:02.946172 Freq=800, CH1 RK0
1670 11:04:02.946226
1671 11:04:02.949042 DATLAT Default: 0xa
1672 11:04:02.949110 0, 0xFFFF, sum = 0
1673 11:04:02.952470 1, 0xFFFF, sum = 0
1674 11:04:02.952535 2, 0xFFFF, sum = 0
1675 11:04:02.955904 3, 0xFFFF, sum = 0
1676 11:04:02.955969 4, 0xFFFF, sum = 0
1677 11:04:02.959831 5, 0xFFFF, sum = 0
1678 11:04:02.959894 6, 0xFFFF, sum = 0
1679 11:04:02.962502 7, 0xFFFF, sum = 0
1680 11:04:02.962565 8, 0xFFFF, sum = 0
1681 11:04:02.965811 9, 0x0, sum = 1
1682 11:04:02.965877 10, 0x0, sum = 2
1683 11:04:02.969659 11, 0x0, sum = 3
1684 11:04:02.969728 12, 0x0, sum = 4
1685 11:04:02.972721 best_step = 10
1686 11:04:02.972787
1687 11:04:02.972840 ==
1688 11:04:02.976300 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 11:04:02.979512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 11:04:02.979583 ==
1691 11:04:02.982749 RX Vref Scan: 1
1692 11:04:02.982809
1693 11:04:02.982860 Set Vref Range= 32 -> 127
1694 11:04:02.982910
1695 11:04:02.986444 RX Vref 32 -> 127, step: 1
1696 11:04:02.986507
1697 11:04:02.989356 RX Delay -111 -> 252, step: 8
1698 11:04:02.989420
1699 11:04:02.992930 Set Vref, RX VrefLevel [Byte0]: 32
1700 11:04:02.996038 [Byte1]: 32
1701 11:04:02.996108
1702 11:04:02.999616 Set Vref, RX VrefLevel [Byte0]: 33
1703 11:04:03.003081 [Byte1]: 33
1704 11:04:03.006277
1705 11:04:03.006353 Set Vref, RX VrefLevel [Byte0]: 34
1706 11:04:03.009946 [Byte1]: 34
1707 11:04:03.013791
1708 11:04:03.013861 Set Vref, RX VrefLevel [Byte0]: 35
1709 11:04:03.017581 [Byte1]: 35
1710 11:04:03.021651
1711 11:04:03.021716 Set Vref, RX VrefLevel [Byte0]: 36
1712 11:04:03.025228 [Byte1]: 36
1713 11:04:03.029187
1714 11:04:03.029260 Set Vref, RX VrefLevel [Byte0]: 37
1715 11:04:03.032720 [Byte1]: 37
1716 11:04:03.036720
1717 11:04:03.036790 Set Vref, RX VrefLevel [Byte0]: 38
1718 11:04:03.040308 [Byte1]: 38
1719 11:04:03.044984
1720 11:04:03.045073 Set Vref, RX VrefLevel [Byte0]: 39
1721 11:04:03.047866 [Byte1]: 39
1722 11:04:03.052139
1723 11:04:03.052254 Set Vref, RX VrefLevel [Byte0]: 40
1724 11:04:03.055760 [Byte1]: 40
1725 11:04:03.059914
1726 11:04:03.059982 Set Vref, RX VrefLevel [Byte0]: 41
1727 11:04:03.063337 [Byte1]: 41
1728 11:04:03.067387
1729 11:04:03.067462 Set Vref, RX VrefLevel [Byte0]: 42
1730 11:04:03.070721 [Byte1]: 42
1731 11:04:03.075122
1732 11:04:03.075199 Set Vref, RX VrefLevel [Byte0]: 43
1733 11:04:03.078478 [Byte1]: 43
1734 11:04:03.082581
1735 11:04:03.082650 Set Vref, RX VrefLevel [Byte0]: 44
1736 11:04:03.086126 [Byte1]: 44
1737 11:04:03.090437
1738 11:04:03.090514 Set Vref, RX VrefLevel [Byte0]: 45
1739 11:04:03.093977 [Byte1]: 45
1740 11:04:03.097901
1741 11:04:03.098008 Set Vref, RX VrefLevel [Byte0]: 46
1742 11:04:03.101540 [Byte1]: 46
1743 11:04:03.105813
1744 11:04:03.105881 Set Vref, RX VrefLevel [Byte0]: 47
1745 11:04:03.109343 [Byte1]: 47
1746 11:04:03.113327
1747 11:04:03.113396 Set Vref, RX VrefLevel [Byte0]: 48
1748 11:04:03.116590 [Byte1]: 48
1749 11:04:03.120797
1750 11:04:03.120865 Set Vref, RX VrefLevel [Byte0]: 49
1751 11:04:03.124154 [Byte1]: 49
1752 11:04:03.128714
1753 11:04:03.128788 Set Vref, RX VrefLevel [Byte0]: 50
1754 11:04:03.132017 [Byte1]: 50
1755 11:04:03.135996
1756 11:04:03.136096 Set Vref, RX VrefLevel [Byte0]: 51
1757 11:04:03.139513 [Byte1]: 51
1758 11:04:03.144212
1759 11:04:03.144284 Set Vref, RX VrefLevel [Byte0]: 52
1760 11:04:03.147308 [Byte1]: 52
1761 11:04:03.151905
1762 11:04:03.151976 Set Vref, RX VrefLevel [Byte0]: 53
1763 11:04:03.154879 [Byte1]: 53
1764 11:04:03.159441
1765 11:04:03.159512 Set Vref, RX VrefLevel [Byte0]: 54
1766 11:04:03.162898 [Byte1]: 54
1767 11:04:03.166998
1768 11:04:03.167067 Set Vref, RX VrefLevel [Byte0]: 55
1769 11:04:03.169985 [Byte1]: 55
1770 11:04:03.174649
1771 11:04:03.174745 Set Vref, RX VrefLevel [Byte0]: 56
1772 11:04:03.178070 [Byte1]: 56
1773 11:04:03.182206
1774 11:04:03.182287 Set Vref, RX VrefLevel [Byte0]: 57
1775 11:04:03.185711 [Byte1]: 57
1776 11:04:03.189956
1777 11:04:03.190045 Set Vref, RX VrefLevel [Byte0]: 58
1778 11:04:03.193307 [Byte1]: 58
1779 11:04:03.197606
1780 11:04:03.197677 Set Vref, RX VrefLevel [Byte0]: 59
1781 11:04:03.200759 [Byte1]: 59
1782 11:04:03.205550
1783 11:04:03.205655 Set Vref, RX VrefLevel [Byte0]: 60
1784 11:04:03.208256 [Byte1]: 60
1785 11:04:03.213381
1786 11:04:03.213458 Set Vref, RX VrefLevel [Byte0]: 61
1787 11:04:03.215905 [Byte1]: 61
1788 11:04:03.220148
1789 11:04:03.220213 Set Vref, RX VrefLevel [Byte0]: 62
1790 11:04:03.227124 [Byte1]: 62
1791 11:04:03.227193
1792 11:04:03.230488 Set Vref, RX VrefLevel [Byte0]: 63
1793 11:04:03.233902 [Byte1]: 63
1794 11:04:03.233993
1795 11:04:03.236945 Set Vref, RX VrefLevel [Byte0]: 64
1796 11:04:03.240285 [Byte1]: 64
1797 11:04:03.240352
1798 11:04:03.243457 Set Vref, RX VrefLevel [Byte0]: 65
1799 11:04:03.247161 [Byte1]: 65
1800 11:04:03.251097
1801 11:04:03.251169 Set Vref, RX VrefLevel [Byte0]: 66
1802 11:04:03.254825 [Byte1]: 66
1803 11:04:03.258617
1804 11:04:03.258680 Set Vref, RX VrefLevel [Byte0]: 67
1805 11:04:03.262309 [Byte1]: 67
1806 11:04:03.266583
1807 11:04:03.266682 Set Vref, RX VrefLevel [Byte0]: 68
1808 11:04:03.269565 [Byte1]: 68
1809 11:04:03.274078
1810 11:04:03.274203 Set Vref, RX VrefLevel [Byte0]: 69
1811 11:04:03.277114 [Byte1]: 69
1812 11:04:03.281646
1813 11:04:03.281716 Set Vref, RX VrefLevel [Byte0]: 70
1814 11:04:03.285027 [Byte1]: 70
1815 11:04:03.289390
1816 11:04:03.289482 Set Vref, RX VrefLevel [Byte0]: 71
1817 11:04:03.292728 [Byte1]: 71
1818 11:04:03.296732
1819 11:04:03.296806 Set Vref, RX VrefLevel [Byte0]: 72
1820 11:04:03.300643 [Byte1]: 72
1821 11:04:03.304730
1822 11:04:03.304794 Set Vref, RX VrefLevel [Byte0]: 73
1823 11:04:03.307603 [Byte1]: 73
1824 11:04:03.312487
1825 11:04:03.312574 Set Vref, RX VrefLevel [Byte0]: 74
1826 11:04:03.315356 [Byte1]: 74
1827 11:04:03.319993
1828 11:04:03.320063 Set Vref, RX VrefLevel [Byte0]: 75
1829 11:04:03.323152 [Byte1]: 75
1830 11:04:03.327308
1831 11:04:03.327370 Set Vref, RX VrefLevel [Byte0]: 76
1832 11:04:03.330709 [Byte1]: 76
1833 11:04:03.335397
1834 11:04:03.335481 Set Vref, RX VrefLevel [Byte0]: 77
1835 11:04:03.338605 [Byte1]: 77
1836 11:04:03.342715
1837 11:04:03.342783 Set Vref, RX VrefLevel [Byte0]: 78
1838 11:04:03.346085 [Byte1]: 78
1839 11:04:03.350305
1840 11:04:03.350372 Final RX Vref Byte 0 = 55 to rank0
1841 11:04:03.353753 Final RX Vref Byte 1 = 53 to rank0
1842 11:04:03.357128 Final RX Vref Byte 0 = 55 to rank1
1843 11:04:03.360897 Final RX Vref Byte 1 = 53 to rank1==
1844 11:04:03.363717 Dram Type= 6, Freq= 0, CH_1, rank 0
1845 11:04:03.370390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 11:04:03.370460 ==
1847 11:04:03.370516 DQS Delay:
1848 11:04:03.370574 DQS0 = 0, DQS1 = 0
1849 11:04:03.373606 DQM Delay:
1850 11:04:03.373667 DQM0 = 80, DQM1 = 71
1851 11:04:03.377544 DQ Delay:
1852 11:04:03.380550 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1853 11:04:03.380614 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1854 11:04:03.384078 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1855 11:04:03.387005 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1856 11:04:03.390430
1857 11:04:03.390501
1858 11:04:03.397269 [DQSOSCAuto] RK0, (LSB)MR18= 0x1821, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
1859 11:04:03.400269 CH1 RK0: MR19=606, MR18=1821
1860 11:04:03.407297 CH1_RK0: MR19=0x606, MR18=0x1821, DQSOSC=401, MR23=63, INC=91, DEC=61
1861 11:04:03.407373
1862 11:04:03.410924 ----->DramcWriteLeveling(PI) begin...
1863 11:04:03.411000 ==
1864 11:04:03.413864 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 11:04:03.417414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 11:04:03.417482 ==
1867 11:04:03.420492 Write leveling (Byte 0): 27 => 27
1868 11:04:03.424076 Write leveling (Byte 1): 28 => 28
1869 11:04:03.427218 DramcWriteLeveling(PI) end<-----
1870 11:04:03.427279
1871 11:04:03.427337 ==
1872 11:04:03.430636 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 11:04:03.433823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 11:04:03.433882 ==
1875 11:04:03.436961 [Gating] SW mode calibration
1876 11:04:03.443629 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1877 11:04:03.450276 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1878 11:04:03.453614 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1879 11:04:03.457394 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1880 11:04:03.463965 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1881 11:04:03.467012 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:04:03.470522 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:04:03.477355 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:04:03.480593 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:04:03.483832 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:04:03.490440 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:04:03.494024 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:04:03.497541 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:04:03.500275 0 7 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1890 11:04:03.507175 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:04:03.510347 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:04:03.513871 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:04:03.520354 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:04:03.524159 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:04:03.527030 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1896 11:04:03.533720 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1897 11:04:03.537227 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:04:03.540950 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:04:03.547372 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:04:03.550384 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:04:03.553930 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:04:03.560082 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:04:03.564012 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1904 11:04:03.567065 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
1905 11:04:03.573867 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 11:04:03.577514 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 11:04:03.580163 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 11:04:03.586861 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 11:04:03.590476 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 11:04:03.594014 0 10 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1911 11:04:03.596903 0 10 4 | B1->B0 | 2f2f 2d2d | 0 0 | (1 0) (1 0)
1912 11:04:03.603820 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:04:03.607191 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:04:03.610091 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:04:03.616865 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:04:03.620315 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:04:03.623566 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 11:04:03.630255 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1919 11:04:03.634064 0 11 4 | B1->B0 | 3434 4040 | 0 1 | (0 0) (0 0)
1920 11:04:03.636993 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1921 11:04:03.643589 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 11:04:03.646792 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 11:04:03.650374 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 11:04:03.657288 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 11:04:03.660367 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 11:04:03.663758 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 11:04:03.670066 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1928 11:04:03.673558 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1929 11:04:03.676897 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:04:03.683871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:04:03.687058 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:04:03.690513 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:04:03.696741 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:04:03.700180 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:04:03.703673 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:04:03.710214 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:04:03.713822 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:04:03.716823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:04:03.720172 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:04:03.726690 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:04:03.730452 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:04:03.733762 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:04:03.740236 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1944 11:04:03.743457 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 11:04:03.747139 Total UI for P1: 0, mck2ui 16
1946 11:04:03.750373 best dqsien dly found for B0: ( 0, 14, 4)
1947 11:04:03.753840 Total UI for P1: 0, mck2ui 16
1948 11:04:03.756904 best dqsien dly found for B1: ( 0, 14, 4)
1949 11:04:03.760518 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1950 11:04:03.763379 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1951 11:04:03.763455
1952 11:04:03.766924 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1953 11:04:03.770018 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1954 11:04:03.773303 [Gating] SW calibration Done
1955 11:04:03.773398 ==
1956 11:04:03.776818 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 11:04:03.780448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 11:04:03.783653 ==
1959 11:04:03.783729 RX Vref Scan: 0
1960 11:04:03.783788
1961 11:04:03.786811 RX Vref 0 -> 0, step: 1
1962 11:04:03.786887
1963 11:04:03.790225 RX Delay -130 -> 252, step: 16
1964 11:04:03.793819 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1965 11:04:03.796758 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1966 11:04:03.800586 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1967 11:04:03.803663 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1968 11:04:03.807030 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1969 11:04:03.813478 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1970 11:04:03.817391 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1971 11:04:03.820015 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1972 11:04:03.823427 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1973 11:04:03.826699 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1974 11:04:03.833676 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1975 11:04:03.836728 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1976 11:04:03.840627 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1977 11:04:03.843418 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1978 11:04:03.850537 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1979 11:04:03.853354 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1980 11:04:03.853421 ==
1981 11:04:03.857118 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 11:04:03.860453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 11:04:03.860519 ==
1984 11:04:03.860574 DQS Delay:
1985 11:04:03.863621 DQS0 = 0, DQS1 = 0
1986 11:04:03.863684 DQM Delay:
1987 11:04:03.867203 DQM0 = 79, DQM1 = 74
1988 11:04:03.867287 DQ Delay:
1989 11:04:03.870149 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1990 11:04:03.873514 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1991 11:04:03.877129 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1992 11:04:03.880015 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1993 11:04:03.880087
1994 11:04:03.880142
1995 11:04:03.880192 ==
1996 11:04:03.883576 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 11:04:03.886944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 11:04:03.890571 ==
1999 11:04:03.890641
2000 11:04:03.890698
2001 11:04:03.890750 TX Vref Scan disable
2002 11:04:03.893805 == TX Byte 0 ==
2003 11:04:03.896649 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2004 11:04:03.899917 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2005 11:04:03.903514 == TX Byte 1 ==
2006 11:04:03.907148 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2007 11:04:03.910584 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2008 11:04:03.913677 ==
2009 11:04:03.913745 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 11:04:03.920055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 11:04:03.920128 ==
2012 11:04:03.932281 TX Vref=22, minBit 0, minWin=28, winSum=454
2013 11:04:03.935519 TX Vref=24, minBit 11, minWin=27, winSum=454
2014 11:04:03.938839 TX Vref=26, minBit 4, minWin=28, winSum=461
2015 11:04:03.942013 TX Vref=28, minBit 4, minWin=28, winSum=461
2016 11:04:03.945511 TX Vref=30, minBit 3, minWin=28, winSum=462
2017 11:04:03.952174 TX Vref=32, minBit 2, minWin=28, winSum=456
2018 11:04:03.955385 [TxChooseVref] Worse bit 3, Min win 28, Win sum 462, Final Vref 30
2019 11:04:03.955466
2020 11:04:03.958606 Final TX Range 1 Vref 30
2021 11:04:03.958672
2022 11:04:03.958725 ==
2023 11:04:03.961766 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 11:04:03.965121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 11:04:03.965194 ==
2026 11:04:03.968832
2027 11:04:03.968895
2028 11:04:03.968955 TX Vref Scan disable
2029 11:04:03.972012 == TX Byte 0 ==
2030 11:04:03.975324 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2031 11:04:03.981984 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2032 11:04:03.982076 == TX Byte 1 ==
2033 11:04:03.985207 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2034 11:04:03.992518 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2035 11:04:03.992595
2036 11:04:03.992652 [DATLAT]
2037 11:04:03.992706 Freq=800, CH1 RK1
2038 11:04:03.992757
2039 11:04:03.995627 DATLAT Default: 0xa
2040 11:04:03.995702 0, 0xFFFF, sum = 0
2041 11:04:03.998711 1, 0xFFFF, sum = 0
2042 11:04:03.998778 2, 0xFFFF, sum = 0
2043 11:04:04.002231 3, 0xFFFF, sum = 0
2044 11:04:04.002302 4, 0xFFFF, sum = 0
2045 11:04:04.005321 5, 0xFFFF, sum = 0
2046 11:04:04.008944 6, 0xFFFF, sum = 0
2047 11:04:04.009015 7, 0xFFFF, sum = 0
2048 11:04:04.012081 8, 0xFFFF, sum = 0
2049 11:04:04.012166 9, 0x0, sum = 1
2050 11:04:04.012225 10, 0x0, sum = 2
2051 11:04:04.015673 11, 0x0, sum = 3
2052 11:04:04.015742 12, 0x0, sum = 4
2053 11:04:04.019163 best_step = 10
2054 11:04:04.019229
2055 11:04:04.019283 ==
2056 11:04:04.022028 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 11:04:04.026009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 11:04:04.026075 ==
2059 11:04:04.029211 RX Vref Scan: 0
2060 11:04:04.029274
2061 11:04:04.029327 RX Vref 0 -> 0, step: 1
2062 11:04:04.029377
2063 11:04:04.032037 RX Delay -111 -> 252, step: 8
2064 11:04:04.039310 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2065 11:04:04.042664 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2066 11:04:04.045965 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2067 11:04:04.049164 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2068 11:04:04.052198 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2069 11:04:04.059315 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2070 11:04:04.062550 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2071 11:04:04.066074 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2072 11:04:04.068877 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2073 11:04:04.072251 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2074 11:04:04.079236 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2075 11:04:04.082020 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2076 11:04:04.085550 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2077 11:04:04.088547 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2078 11:04:04.095151 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2079 11:04:04.098910 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2080 11:04:04.098983 ==
2081 11:04:04.102010 Dram Type= 6, Freq= 0, CH_1, rank 1
2082 11:04:04.105432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2083 11:04:04.105503 ==
2084 11:04:04.105560 DQS Delay:
2085 11:04:04.108634 DQS0 = 0, DQS1 = 0
2086 11:04:04.108699 DQM Delay:
2087 11:04:04.112069 DQM0 = 77, DQM1 = 72
2088 11:04:04.112147 DQ Delay:
2089 11:04:04.115430 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2090 11:04:04.118458 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2091 11:04:04.121779 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
2092 11:04:04.125117 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
2093 11:04:04.125185
2094 11:04:04.125240
2095 11:04:04.135478 [DQSOSCAuto] RK1, (LSB)MR18= 0x2740, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2096 11:04:04.135552 CH1 RK1: MR19=606, MR18=2740
2097 11:04:04.142104 CH1_RK1: MR19=0x606, MR18=0x2740, DQSOSC=393, MR23=63, INC=95, DEC=63
2098 11:04:04.144977 [RxdqsGatingPostProcess] freq 800
2099 11:04:04.151828 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2100 11:04:04.155349 Pre-setting of DQS Precalculation
2101 11:04:04.158482 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2102 11:04:04.164878 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2103 11:04:04.171543 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2104 11:04:04.175595
2105 11:04:04.175662
2106 11:04:04.175718 [Calibration Summary] 1600 Mbps
2107 11:04:04.178439 CH 0, Rank 0
2108 11:04:04.178506 SW Impedance : PASS
2109 11:04:04.182055 DUTY Scan : NO K
2110 11:04:04.185354 ZQ Calibration : PASS
2111 11:04:04.185422 Jitter Meter : NO K
2112 11:04:04.189108 CBT Training : PASS
2113 11:04:04.192048 Write leveling : PASS
2114 11:04:04.192117 RX DQS gating : PASS
2115 11:04:04.195354 RX DQ/DQS(RDDQC) : PASS
2116 11:04:04.198315 TX DQ/DQS : PASS
2117 11:04:04.198383 RX DATLAT : PASS
2118 11:04:04.201970 RX DQ/DQS(Engine): PASS
2119 11:04:04.205254 TX OE : NO K
2120 11:04:04.205321 All Pass.
2121 11:04:04.205377
2122 11:04:04.205441 CH 0, Rank 1
2123 11:04:04.208875 SW Impedance : PASS
2124 11:04:04.211904 DUTY Scan : NO K
2125 11:04:04.211995 ZQ Calibration : PASS
2126 11:04:04.215560 Jitter Meter : NO K
2127 11:04:04.215626 CBT Training : PASS
2128 11:04:04.218487 Write leveling : PASS
2129 11:04:04.222284 RX DQS gating : PASS
2130 11:04:04.222348 RX DQ/DQS(RDDQC) : PASS
2131 11:04:04.225402 TX DQ/DQS : PASS
2132 11:04:04.228407 RX DATLAT : PASS
2133 11:04:04.228475 RX DQ/DQS(Engine): PASS
2134 11:04:04.231705 TX OE : NO K
2135 11:04:04.231782 All Pass.
2136 11:04:04.231841
2137 11:04:04.235640 CH 1, Rank 0
2138 11:04:04.235785 SW Impedance : PASS
2139 11:04:04.238648 DUTY Scan : NO K
2140 11:04:04.241841 ZQ Calibration : PASS
2141 11:04:04.241916 Jitter Meter : NO K
2142 11:04:04.245166 CBT Training : PASS
2143 11:04:04.248391 Write leveling : PASS
2144 11:04:04.248502 RX DQS gating : PASS
2145 11:04:04.251817 RX DQ/DQS(RDDQC) : PASS
2146 11:04:04.255167 TX DQ/DQS : PASS
2147 11:04:04.255241 RX DATLAT : PASS
2148 11:04:04.258774 RX DQ/DQS(Engine): PASS
2149 11:04:04.258876 TX OE : NO K
2150 11:04:04.262267 All Pass.
2151 11:04:04.262359
2152 11:04:04.262439 CH 1, Rank 1
2153 11:04:04.265410 SW Impedance : PASS
2154 11:04:04.265505 DUTY Scan : NO K
2155 11:04:04.268685 ZQ Calibration : PASS
2156 11:04:04.272558 Jitter Meter : NO K
2157 11:04:04.272649 CBT Training : PASS
2158 11:04:04.275232 Write leveling : PASS
2159 11:04:04.279010 RX DQS gating : PASS
2160 11:04:04.279130 RX DQ/DQS(RDDQC) : PASS
2161 11:04:04.282262 TX DQ/DQS : PASS
2162 11:04:04.285216 RX DATLAT : PASS
2163 11:04:04.285312 RX DQ/DQS(Engine): PASS
2164 11:04:04.288848 TX OE : NO K
2165 11:04:04.288940 All Pass.
2166 11:04:04.289027
2167 11:04:04.291906 DramC Write-DBI off
2168 11:04:04.295539 PER_BANK_REFRESH: Hybrid Mode
2169 11:04:04.295630 TX_TRACKING: ON
2170 11:04:04.298349 [GetDramInforAfterCalByMRR] Vendor 6.
2171 11:04:04.301809 [GetDramInforAfterCalByMRR] Revision 606.
2172 11:04:04.305389 [GetDramInforAfterCalByMRR] Revision 2 0.
2173 11:04:04.309055 MR0 0x3b3b
2174 11:04:04.309149 MR8 0x5151
2175 11:04:04.312145 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 11:04:04.312238
2177 11:04:04.312370 MR0 0x3b3b
2178 11:04:04.315183 MR8 0x5151
2179 11:04:04.318787 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 11:04:04.318882
2181 11:04:04.325076 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2182 11:04:04.331730 [FAST_K] Save calibration result to emmc
2183 11:04:04.335237 [FAST_K] Save calibration result to emmc
2184 11:04:04.335333 dram_init: config_dvfs: 1
2185 11:04:04.342030 dramc_set_vcore_voltage set vcore to 662500
2186 11:04:04.342168 Read voltage for 1200, 2
2187 11:04:04.342252 Vio18 = 0
2188 11:04:04.345447 Vcore = 662500
2189 11:04:04.345541 Vdram = 0
2190 11:04:04.345621 Vddq = 0
2191 11:04:04.348514 Vmddr = 0
2192 11:04:04.352303 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2193 11:04:04.358511 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2194 11:04:04.358591 MEM_TYPE=3, freq_sel=15
2195 11:04:04.362049 sv_algorithm_assistance_LP4_1600
2196 11:04:04.368861 ============ PULL DRAM RESETB DOWN ============
2197 11:04:04.372047 ========== PULL DRAM RESETB DOWN end =========
2198 11:04:04.375114 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2199 11:04:04.378738 ===================================
2200 11:04:04.382152 LPDDR4 DRAM CONFIGURATION
2201 11:04:04.385078 ===================================
2202 11:04:04.388470 EX_ROW_EN[0] = 0x0
2203 11:04:04.388550 EX_ROW_EN[1] = 0x0
2204 11:04:04.392079 LP4Y_EN = 0x0
2205 11:04:04.392150 WORK_FSP = 0x0
2206 11:04:04.395366 WL = 0x4
2207 11:04:04.395432 RL = 0x4
2208 11:04:04.398642 BL = 0x2
2209 11:04:04.398713 RPST = 0x0
2210 11:04:04.401777 RD_PRE = 0x0
2211 11:04:04.401844 WR_PRE = 0x1
2212 11:04:04.405089 WR_PST = 0x0
2213 11:04:04.405156 DBI_WR = 0x0
2214 11:04:04.408683 DBI_RD = 0x0
2215 11:04:04.408775 OTF = 0x1
2216 11:04:04.411571 ===================================
2217 11:04:04.414966 ===================================
2218 11:04:04.418392 ANA top config
2219 11:04:04.421815 ===================================
2220 11:04:04.421882 DLL_ASYNC_EN = 0
2221 11:04:04.425318 ALL_SLAVE_EN = 0
2222 11:04:04.428383 NEW_RANK_MODE = 1
2223 11:04:04.431749 DLL_IDLE_MODE = 1
2224 11:04:04.435052 LP45_APHY_COMB_EN = 1
2225 11:04:04.435122 TX_ODT_DIS = 1
2226 11:04:04.438195 NEW_8X_MODE = 1
2227 11:04:04.442218 ===================================
2228 11:04:04.445019 ===================================
2229 11:04:04.448286 data_rate = 2400
2230 11:04:04.451821 CKR = 1
2231 11:04:04.454838 DQ_P2S_RATIO = 8
2232 11:04:04.458434 ===================================
2233 11:04:04.458503 CA_P2S_RATIO = 8
2234 11:04:04.461521 DQ_CA_OPEN = 0
2235 11:04:04.464990 DQ_SEMI_OPEN = 0
2236 11:04:04.468743 CA_SEMI_OPEN = 0
2237 11:04:04.471473 CA_FULL_RATE = 0
2238 11:04:04.475199 DQ_CKDIV4_EN = 0
2239 11:04:04.475268 CA_CKDIV4_EN = 0
2240 11:04:04.478677 CA_PREDIV_EN = 0
2241 11:04:04.481755 PH8_DLY = 17
2242 11:04:04.484986 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2243 11:04:04.488692 DQ_AAMCK_DIV = 4
2244 11:04:04.491568 CA_AAMCK_DIV = 4
2245 11:04:04.491635 CA_ADMCK_DIV = 4
2246 11:04:04.495209 DQ_TRACK_CA_EN = 0
2247 11:04:04.498219 CA_PICK = 1200
2248 11:04:04.501617 CA_MCKIO = 1200
2249 11:04:04.505131 MCKIO_SEMI = 0
2250 11:04:04.508554 PLL_FREQ = 2366
2251 11:04:04.511578 DQ_UI_PI_RATIO = 32
2252 11:04:04.511649 CA_UI_PI_RATIO = 0
2253 11:04:04.514974 ===================================
2254 11:04:04.518506 ===================================
2255 11:04:04.521437 memory_type:LPDDR4
2256 11:04:04.524960 GP_NUM : 10
2257 11:04:04.525027 SRAM_EN : 1
2258 11:04:04.528529 MD32_EN : 0
2259 11:04:04.531533 ===================================
2260 11:04:04.534938 [ANA_INIT] >>>>>>>>>>>>>>
2261 11:04:04.538337 <<<<<< [CONFIGURE PHASE]: ANA_TX
2262 11:04:04.541510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2263 11:04:04.545121 ===================================
2264 11:04:04.545193 data_rate = 2400,PCW = 0X5b00
2265 11:04:04.548311 ===================================
2266 11:04:04.551796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2267 11:04:04.558345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 11:04:04.565008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 11:04:04.568528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2270 11:04:04.571705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2271 11:04:04.574750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2272 11:04:04.578341 [ANA_INIT] flow start
2273 11:04:04.578407 [ANA_INIT] PLL >>>>>>>>
2274 11:04:04.581949 [ANA_INIT] PLL <<<<<<<<
2275 11:04:04.584956 [ANA_INIT] MIDPI >>>>>>>>
2276 11:04:04.588604 [ANA_INIT] MIDPI <<<<<<<<
2277 11:04:04.588680 [ANA_INIT] DLL >>>>>>>>
2278 11:04:04.591664 [ANA_INIT] DLL <<<<<<<<
2279 11:04:04.591730 [ANA_INIT] flow end
2280 11:04:04.598290 ============ LP4 DIFF to SE enter ============
2281 11:04:04.601500 ============ LP4 DIFF to SE exit ============
2282 11:04:04.605029 [ANA_INIT] <<<<<<<<<<<<<
2283 11:04:04.608306 [Flow] Enable top DCM control >>>>>
2284 11:04:04.611555 [Flow] Enable top DCM control <<<<<
2285 11:04:04.615068 Enable DLL master slave shuffle
2286 11:04:04.618413 ==============================================================
2287 11:04:04.621549 Gating Mode config
2288 11:04:04.625064 ==============================================================
2289 11:04:04.628598 Config description:
2290 11:04:04.638415 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2291 11:04:04.645175 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2292 11:04:04.648542 SELPH_MODE 0: By rank 1: By Phase
2293 11:04:04.654939 ==============================================================
2294 11:04:04.658088 GAT_TRACK_EN = 1
2295 11:04:04.661803 RX_GATING_MODE = 2
2296 11:04:04.664724 RX_GATING_TRACK_MODE = 2
2297 11:04:04.668283 SELPH_MODE = 1
2298 11:04:04.668351 PICG_EARLY_EN = 1
2299 11:04:04.671968 VALID_LAT_VALUE = 1
2300 11:04:04.678467 ==============================================================
2301 11:04:04.681961 Enter into Gating configuration >>>>
2302 11:04:04.685060 Exit from Gating configuration <<<<
2303 11:04:04.688120 Enter into DVFS_PRE_config >>>>>
2304 11:04:04.698792 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2305 11:04:04.701714 Exit from DVFS_PRE_config <<<<<
2306 11:04:04.704938 Enter into PICG configuration >>>>
2307 11:04:04.708388 Exit from PICG configuration <<<<
2308 11:04:04.711427 [RX_INPUT] configuration >>>>>
2309 11:04:04.714925 [RX_INPUT] configuration <<<<<
2310 11:04:04.718508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2311 11:04:04.725309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2312 11:04:04.731773 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 11:04:04.738199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 11:04:04.744949 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 11:04:04.748533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 11:04:04.755199 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2317 11:04:04.758275 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2318 11:04:04.761447 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2319 11:04:04.764912 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2320 11:04:04.768514 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2321 11:04:04.774897 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 11:04:04.778721 ===================================
2323 11:04:04.781472 LPDDR4 DRAM CONFIGURATION
2324 11:04:04.784956 ===================================
2325 11:04:04.785023 EX_ROW_EN[0] = 0x0
2326 11:04:04.788479 EX_ROW_EN[1] = 0x0
2327 11:04:04.788563 LP4Y_EN = 0x0
2328 11:04:04.791518 WORK_FSP = 0x0
2329 11:04:04.791587 WL = 0x4
2330 11:04:04.794855 RL = 0x4
2331 11:04:04.794923 BL = 0x2
2332 11:04:04.798580 RPST = 0x0
2333 11:04:04.798694 RD_PRE = 0x0
2334 11:04:04.801678 WR_PRE = 0x1
2335 11:04:04.801769 WR_PST = 0x0
2336 11:04:04.804799 DBI_WR = 0x0
2337 11:04:04.804911 DBI_RD = 0x0
2338 11:04:04.807967 OTF = 0x1
2339 11:04:04.811444 ===================================
2340 11:04:04.814931 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2341 11:04:04.818337 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2342 11:04:04.825106 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2343 11:04:04.828080 ===================================
2344 11:04:04.828162 LPDDR4 DRAM CONFIGURATION
2345 11:04:04.831487 ===================================
2346 11:04:04.835223 EX_ROW_EN[0] = 0x10
2347 11:04:04.838318 EX_ROW_EN[1] = 0x0
2348 11:04:04.838396 LP4Y_EN = 0x0
2349 11:04:04.841848 WORK_FSP = 0x0
2350 11:04:04.841926 WL = 0x4
2351 11:04:04.845217 RL = 0x4
2352 11:04:04.845294 BL = 0x2
2353 11:04:04.848749 RPST = 0x0
2354 11:04:04.848827 RD_PRE = 0x0
2355 11:04:04.851721 WR_PRE = 0x1
2356 11:04:04.851799 WR_PST = 0x0
2357 11:04:04.855103 DBI_WR = 0x0
2358 11:04:04.855181 DBI_RD = 0x0
2359 11:04:04.858740 OTF = 0x1
2360 11:04:04.861959 ===================================
2361 11:04:04.869328 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2362 11:04:04.869424 ==
2363 11:04:04.871762 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 11:04:04.875271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 11:04:04.875359 ==
2366 11:04:04.878853 [Duty_Offset_Calibration]
2367 11:04:04.878944 B0:2 B1:0 CA:3
2368 11:04:04.879017
2369 11:04:04.882070 [DutyScan_Calibration_Flow] k_type=0
2370 11:04:04.891755
2371 11:04:04.891886 ==CLK 0==
2372 11:04:04.894594 Final CLK duty delay cell = 0
2373 11:04:04.898468 [0] MAX Duty = 5062%(X100), DQS PI = 12
2374 11:04:04.901449 [0] MIN Duty = 4875%(X100), DQS PI = 58
2375 11:04:04.901529 [0] AVG Duty = 4968%(X100)
2376 11:04:04.905096
2377 11:04:04.905173 CH0 CLK Duty spec in!! Max-Min= 187%
2378 11:04:04.911781 [DutyScan_Calibration_Flow] ====Done====
2379 11:04:04.911862
2380 11:04:04.914991 [DutyScan_Calibration_Flow] k_type=1
2381 11:04:04.929861
2382 11:04:04.929937 ==DQS 0 ==
2383 11:04:04.933425 Final DQS duty delay cell = 0
2384 11:04:04.936515 [0] MAX Duty = 5062%(X100), DQS PI = 16
2385 11:04:04.940078 [0] MIN Duty = 4907%(X100), DQS PI = 2
2386 11:04:04.940155 [0] AVG Duty = 4984%(X100)
2387 11:04:04.943650
2388 11:04:04.943725 ==DQS 1 ==
2389 11:04:04.946683 Final DQS duty delay cell = -4
2390 11:04:04.950150 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2391 11:04:04.953511 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2392 11:04:04.957014 [-4] AVG Duty = 4922%(X100)
2393 11:04:04.957089
2394 11:04:04.960051 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2395 11:04:04.960130
2396 11:04:04.963510 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2397 11:04:04.967054 [DutyScan_Calibration_Flow] ====Done====
2398 11:04:04.967130
2399 11:04:04.970375 [DutyScan_Calibration_Flow] k_type=3
2400 11:04:04.987127
2401 11:04:04.987235 ==DQM 0 ==
2402 11:04:04.991025 Final DQM duty delay cell = 0
2403 11:04:04.994910 [0] MAX Duty = 5124%(X100), DQS PI = 12
2404 11:04:04.997250 [0] MIN Duty = 4876%(X100), DQS PI = 0
2405 11:04:04.997317 [0] AVG Duty = 5000%(X100)
2406 11:04:05.000818
2407 11:04:05.000911 ==DQM 1 ==
2408 11:04:05.004134 Final DQM duty delay cell = 4
2409 11:04:05.007346 [4] MAX Duty = 5124%(X100), DQS PI = 50
2410 11:04:05.010632 [4] MIN Duty = 5000%(X100), DQS PI = 12
2411 11:04:05.010700 [4] AVG Duty = 5062%(X100)
2412 11:04:05.014040
2413 11:04:05.017471 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2414 11:04:05.017550
2415 11:04:05.020516 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2416 11:04:05.024271 [DutyScan_Calibration_Flow] ====Done====
2417 11:04:05.024338
2418 11:04:05.027100 [DutyScan_Calibration_Flow] k_type=2
2419 11:04:05.042506
2420 11:04:05.042589 ==DQ 0 ==
2421 11:04:05.045438 Final DQ duty delay cell = -4
2422 11:04:05.049113 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2423 11:04:05.052243 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2424 11:04:05.055551 [-4] AVG Duty = 4969%(X100)
2425 11:04:05.055648
2426 11:04:05.055728 ==DQ 1 ==
2427 11:04:05.058986 Final DQ duty delay cell = -4
2428 11:04:05.062301 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2429 11:04:05.065644 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2430 11:04:05.069004 [-4] AVG Duty = 4938%(X100)
2431 11:04:05.069071
2432 11:04:05.072316 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2433 11:04:05.072380
2434 11:04:05.075736 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2435 11:04:05.079076 [DutyScan_Calibration_Flow] ====Done====
2436 11:04:05.079141 ==
2437 11:04:05.082303 Dram Type= 6, Freq= 0, CH_1, rank 0
2438 11:04:05.085741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 11:04:05.085807 ==
2440 11:04:05.088773 [Duty_Offset_Calibration]
2441 11:04:05.088841 B0:1 B1:-2 CA:0
2442 11:04:05.088893
2443 11:04:05.092633 [DutyScan_Calibration_Flow] k_type=0
2444 11:04:05.103065
2445 11:04:05.103133 ==CLK 0==
2446 11:04:05.106461 Final CLK duty delay cell = 0
2447 11:04:05.109345 [0] MAX Duty = 5031%(X100), DQS PI = 18
2448 11:04:05.112733 [0] MIN Duty = 4844%(X100), DQS PI = 58
2449 11:04:05.112811 [0] AVG Duty = 4937%(X100)
2450 11:04:05.116261
2451 11:04:05.119584 CH1 CLK Duty spec in!! Max-Min= 187%
2452 11:04:05.122728 [DutyScan_Calibration_Flow] ====Done====
2453 11:04:05.122805
2454 11:04:05.126024 [DutyScan_Calibration_Flow] k_type=1
2455 11:04:05.141228
2456 11:04:05.141306 ==DQS 0 ==
2457 11:04:05.144857 Final DQS duty delay cell = -4
2458 11:04:05.147911 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2459 11:04:05.151614 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2460 11:04:05.154462 [-4] AVG Duty = 4938%(X100)
2461 11:04:05.154537
2462 11:04:05.154594 ==DQS 1 ==
2463 11:04:05.157940 Final DQS duty delay cell = 0
2464 11:04:05.161307 [0] MAX Duty = 5062%(X100), DQS PI = 0
2465 11:04:05.164626 [0] MIN Duty = 4875%(X100), DQS PI = 26
2466 11:04:05.168441 [0] AVG Duty = 4968%(X100)
2467 11:04:05.168517
2468 11:04:05.171614 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2469 11:04:05.171687
2470 11:04:05.174758 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2471 11:04:05.177662 [DutyScan_Calibration_Flow] ====Done====
2472 11:04:05.177730
2473 11:04:05.181343 [DutyScan_Calibration_Flow] k_type=3
2474 11:04:05.197977
2475 11:04:05.198073 ==DQM 0 ==
2476 11:04:05.201583 Final DQM duty delay cell = 0
2477 11:04:05.204960 [0] MAX Duty = 5000%(X100), DQS PI = 22
2478 11:04:05.208040 [0] MIN Duty = 4876%(X100), DQS PI = 2
2479 11:04:05.208115 [0] AVG Duty = 4938%(X100)
2480 11:04:05.211405
2481 11:04:05.211480 ==DQM 1 ==
2482 11:04:05.214468 Final DQM duty delay cell = 0
2483 11:04:05.218247 [0] MAX Duty = 5031%(X100), DQS PI = 36
2484 11:04:05.221140 [0] MIN Duty = 4907%(X100), DQS PI = 0
2485 11:04:05.221230 [0] AVG Duty = 4969%(X100)
2486 11:04:05.224830
2487 11:04:05.228186 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2488 11:04:05.228263
2489 11:04:05.231380 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2490 11:04:05.234835 [DutyScan_Calibration_Flow] ====Done====
2491 11:04:05.234909
2492 11:04:05.238085 [DutyScan_Calibration_Flow] k_type=2
2493 11:04:05.254694
2494 11:04:05.254766 ==DQ 0 ==
2495 11:04:05.257713 Final DQ duty delay cell = 0
2496 11:04:05.260991 [0] MAX Duty = 5093%(X100), DQS PI = 28
2497 11:04:05.264780 [0] MIN Duty = 4938%(X100), DQS PI = 54
2498 11:04:05.264856 [0] AVG Duty = 5015%(X100)
2499 11:04:05.264914
2500 11:04:05.268194 ==DQ 1 ==
2501 11:04:05.271169 Final DQ duty delay cell = 0
2502 11:04:05.274262 [0] MAX Duty = 5125%(X100), DQS PI = 36
2503 11:04:05.277854 [0] MIN Duty = 4969%(X100), DQS PI = 26
2504 11:04:05.277929 [0] AVG Duty = 5047%(X100)
2505 11:04:05.277986
2506 11:04:05.281246 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2507 11:04:05.281320
2508 11:04:05.287819 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2509 11:04:05.291359 [DutyScan_Calibration_Flow] ====Done====
2510 11:04:05.294853 nWR fixed to 30
2511 11:04:05.294929 [ModeRegInit_LP4] CH0 RK0
2512 11:04:05.297963 [ModeRegInit_LP4] CH0 RK1
2513 11:04:05.301227 [ModeRegInit_LP4] CH1 RK0
2514 11:04:05.301302 [ModeRegInit_LP4] CH1 RK1
2515 11:04:05.304807 match AC timing 7
2516 11:04:05.308181 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2517 11:04:05.311208 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2518 11:04:05.317724 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2519 11:04:05.321530 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2520 11:04:05.327931 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2521 11:04:05.328007 ==
2522 11:04:05.331099 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 11:04:05.334427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 11:04:05.334502 ==
2525 11:04:05.340797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 11:04:05.347353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2527 11:04:05.354479 [CA 0] Center 40 (10~71) winsize 62
2528 11:04:05.357937 [CA 1] Center 39 (9~70) winsize 62
2529 11:04:05.361586 [CA 2] Center 36 (6~66) winsize 61
2530 11:04:05.364434 [CA 3] Center 35 (5~66) winsize 62
2531 11:04:05.368167 [CA 4] Center 34 (4~65) winsize 62
2532 11:04:05.371432 [CA 5] Center 33 (3~63) winsize 61
2533 11:04:05.371506
2534 11:04:05.374687 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2535 11:04:05.374762
2536 11:04:05.377850 [CATrainingPosCal] consider 1 rank data
2537 11:04:05.381611 u2DelayCellTimex100 = 270/100 ps
2538 11:04:05.384542 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2539 11:04:05.391210 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2540 11:04:05.394272 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2541 11:04:05.397843 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 11:04:05.401440 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2543 11:04:05.404180 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2544 11:04:05.404251
2545 11:04:05.407719 CA PerBit enable=1, Macro0, CA PI delay=33
2546 11:04:05.407788
2547 11:04:05.411020 [CBTSetCACLKResult] CA Dly = 33
2548 11:04:05.414410 CS Dly: 7 (0~38)
2549 11:04:05.414483 ==
2550 11:04:05.417468 Dram Type= 6, Freq= 0, CH_0, rank 1
2551 11:04:05.420947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 11:04:05.421024 ==
2553 11:04:05.427504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2554 11:04:05.430893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2555 11:04:05.440817 [CA 0] Center 40 (10~70) winsize 61
2556 11:04:05.444238 [CA 1] Center 40 (10~70) winsize 61
2557 11:04:05.447090 [CA 2] Center 35 (5~66) winsize 62
2558 11:04:05.450585 [CA 3] Center 35 (5~66) winsize 62
2559 11:04:05.453982 [CA 4] Center 34 (4~65) winsize 62
2560 11:04:05.457157 [CA 5] Center 33 (3~63) winsize 61
2561 11:04:05.457229
2562 11:04:05.460880 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2563 11:04:05.460952
2564 11:04:05.464279 [CATrainingPosCal] consider 2 rank data
2565 11:04:05.467176 u2DelayCellTimex100 = 270/100 ps
2566 11:04:05.470644 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2567 11:04:05.477490 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2568 11:04:05.480830 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2569 11:04:05.483715 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2570 11:04:05.487433 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2571 11:04:05.490618 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2572 11:04:05.490690
2573 11:04:05.494012 CA PerBit enable=1, Macro0, CA PI delay=33
2574 11:04:05.494115
2575 11:04:05.497201 [CBTSetCACLKResult] CA Dly = 33
2576 11:04:05.500471 CS Dly: 8 (0~40)
2577 11:04:05.500544
2578 11:04:05.503797 ----->DramcWriteLeveling(PI) begin...
2579 11:04:05.503895 ==
2580 11:04:05.507160 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 11:04:05.510836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 11:04:05.510907 ==
2583 11:04:05.514292 Write leveling (Byte 0): 32 => 32
2584 11:04:05.517809 Write leveling (Byte 1): 29 => 29
2585 11:04:05.520853 DramcWriteLeveling(PI) end<-----
2586 11:04:05.520920
2587 11:04:05.520985 ==
2588 11:04:05.523798 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 11:04:05.527354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 11:04:05.527417 ==
2591 11:04:05.530476 [Gating] SW mode calibration
2592 11:04:05.537674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2593 11:04:05.543914 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2594 11:04:05.547338 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2595 11:04:05.550492 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2596 11:04:05.557162 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 11:04:05.560791 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 11:04:05.563666 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 11:04:05.567470 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 11:04:05.573815 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 11:04:05.577461 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2602 11:04:05.581031 1 0 0 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
2603 11:04:05.587362 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2604 11:04:05.590579 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 11:04:05.594039 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 11:04:05.600783 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 11:04:05.604154 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 11:04:05.607647 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 11:04:05.614338 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2610 11:04:05.617495 1 1 0 | B1->B0 | 2c2c 3b3b | 0 1 | (1 1) (0 0)
2611 11:04:05.620626 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 11:04:05.627443 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 11:04:05.630529 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 11:04:05.634083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 11:04:05.640676 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 11:04:05.644218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 11:04:05.647384 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2618 11:04:05.650764 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2619 11:04:05.657383 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2620 11:04:05.660529 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:04:05.664056 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:04:05.670721 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:04:05.674197 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:04:05.677600 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:04:05.684128 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:04:05.687791 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:04:05.690617 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:04:05.697680 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:04:05.701228 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:04:05.704590 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:04:05.711021 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:04:05.714737 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:04:05.717411 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:04:05.724401 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2635 11:04:05.724477 Total UI for P1: 0, mck2ui 16
2636 11:04:05.727430 best dqsien dly found for B0: ( 1, 3, 30)
2637 11:04:05.734111 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 11:04:05.737713 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 11:04:05.741025 Total UI for P1: 0, mck2ui 16
2640 11:04:05.744345 best dqsien dly found for B1: ( 1, 4, 2)
2641 11:04:05.747960 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2642 11:04:05.750974 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2643 11:04:05.751049
2644 11:04:05.754518 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2645 11:04:05.757634 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2646 11:04:05.760803 [Gating] SW calibration Done
2647 11:04:05.760880 ==
2648 11:04:05.764171 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 11:04:05.767474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 11:04:05.770966 ==
2651 11:04:05.771041 RX Vref Scan: 0
2652 11:04:05.771099
2653 11:04:05.774785 RX Vref 0 -> 0, step: 1
2654 11:04:05.774884
2655 11:04:05.777656 RX Delay -40 -> 252, step: 8
2656 11:04:05.780937 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2657 11:04:05.784078 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2658 11:04:05.787514 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2659 11:04:05.790909 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2660 11:04:05.797873 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2661 11:04:05.801312 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2662 11:04:05.804401 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2663 11:04:05.807365 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2664 11:04:05.811205 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2665 11:04:05.814187 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2666 11:04:05.820907 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2667 11:04:05.824396 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2668 11:04:05.827483 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2669 11:04:05.831155 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2670 11:04:05.834651 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2671 11:04:05.841055 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2672 11:04:05.841131 ==
2673 11:04:05.844305 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 11:04:05.847696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 11:04:05.847763 ==
2676 11:04:05.847818 DQS Delay:
2677 11:04:05.851026 DQS0 = 0, DQS1 = 0
2678 11:04:05.851089 DQM Delay:
2679 11:04:05.854208 DQM0 = 112, DQM1 = 102
2680 11:04:05.854299 DQ Delay:
2681 11:04:05.857923 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2682 11:04:05.860922 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2683 11:04:05.864494 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2684 11:04:05.868044 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2685 11:04:05.868120
2686 11:04:05.868179
2687 11:04:05.871102 ==
2688 11:04:05.871178 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 11:04:05.877496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 11:04:05.877572 ==
2691 11:04:05.877631
2692 11:04:05.877685
2693 11:04:05.880935 TX Vref Scan disable
2694 11:04:05.881010 == TX Byte 0 ==
2695 11:04:05.884000 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2696 11:04:05.890580 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2697 11:04:05.890661 == TX Byte 1 ==
2698 11:04:05.893755 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2699 11:04:05.900761 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2700 11:04:05.900837 ==
2701 11:04:05.904037 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 11:04:05.907445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 11:04:05.907545 ==
2704 11:04:05.919436 TX Vref=22, minBit 4, minWin=25, winSum=419
2705 11:04:05.923077 TX Vref=24, minBit 5, minWin=25, winSum=424
2706 11:04:05.926112 TX Vref=26, minBit 7, minWin=26, winSum=429
2707 11:04:05.929398 TX Vref=28, minBit 10, minWin=26, winSum=436
2708 11:04:05.932548 TX Vref=30, minBit 10, minWin=26, winSum=436
2709 11:04:05.939514 TX Vref=32, minBit 0, minWin=26, winSum=432
2710 11:04:05.942987 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 28
2711 11:04:05.943067
2712 11:04:05.946085 Final TX Range 1 Vref 28
2713 11:04:05.946196
2714 11:04:05.946254 ==
2715 11:04:05.949371 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 11:04:05.953120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 11:04:05.956100 ==
2718 11:04:05.956176
2719 11:04:05.956234
2720 11:04:05.956288 TX Vref Scan disable
2721 11:04:05.959185 == TX Byte 0 ==
2722 11:04:05.962843 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2723 11:04:05.969747 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2724 11:04:05.969824 == TX Byte 1 ==
2725 11:04:05.973199 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2726 11:04:05.976061 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2727 11:04:05.979741
2728 11:04:05.979816 [DATLAT]
2729 11:04:05.979875 Freq=1200, CH0 RK0
2730 11:04:05.979929
2731 11:04:05.982607 DATLAT Default: 0xd
2732 11:04:05.982683 0, 0xFFFF, sum = 0
2733 11:04:05.986324 1, 0xFFFF, sum = 0
2734 11:04:05.986401 2, 0xFFFF, sum = 0
2735 11:04:05.989416 3, 0xFFFF, sum = 0
2736 11:04:05.989493 4, 0xFFFF, sum = 0
2737 11:04:05.992793 5, 0xFFFF, sum = 0
2738 11:04:05.992869 6, 0xFFFF, sum = 0
2739 11:04:05.996601 7, 0xFFFF, sum = 0
2740 11:04:05.999324 8, 0xFFFF, sum = 0
2741 11:04:05.999405 9, 0xFFFF, sum = 0
2742 11:04:06.003345 10, 0xFFFF, sum = 0
2743 11:04:06.003422 11, 0xFFFF, sum = 0
2744 11:04:06.006562 12, 0x0, sum = 1
2745 11:04:06.006639 13, 0x0, sum = 2
2746 11:04:06.009562 14, 0x0, sum = 3
2747 11:04:06.009669 15, 0x0, sum = 4
2748 11:04:06.009729 best_step = 13
2749 11:04:06.009784
2750 11:04:06.013183 ==
2751 11:04:06.013258 Dram Type= 6, Freq= 0, CH_0, rank 0
2752 11:04:06.019587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2753 11:04:06.019663 ==
2754 11:04:06.019722 RX Vref Scan: 1
2755 11:04:06.019776
2756 11:04:06.023312 Set Vref Range= 32 -> 127
2757 11:04:06.023387
2758 11:04:06.026484 RX Vref 32 -> 127, step: 1
2759 11:04:06.026560
2760 11:04:06.029920 RX Delay -37 -> 252, step: 4
2761 11:04:06.029995
2762 11:04:06.033061 Set Vref, RX VrefLevel [Byte0]: 32
2763 11:04:06.036059 [Byte1]: 32
2764 11:04:06.036135
2765 11:04:06.039533 Set Vref, RX VrefLevel [Byte0]: 33
2766 11:04:06.043107 [Byte1]: 33
2767 11:04:06.046043
2768 11:04:06.046128 Set Vref, RX VrefLevel [Byte0]: 34
2769 11:04:06.050195 [Byte1]: 34
2770 11:04:06.053834
2771 11:04:06.053909 Set Vref, RX VrefLevel [Byte0]: 35
2772 11:04:06.057347 [Byte1]: 35
2773 11:04:06.062081
2774 11:04:06.062181 Set Vref, RX VrefLevel [Byte0]: 36
2775 11:04:06.065497 [Byte1]: 36
2776 11:04:06.069959
2777 11:04:06.070034 Set Vref, RX VrefLevel [Byte0]: 37
2778 11:04:06.073461 [Byte1]: 37
2779 11:04:06.078134
2780 11:04:06.078222 Set Vref, RX VrefLevel [Byte0]: 38
2781 11:04:06.081239 [Byte1]: 38
2782 11:04:06.086180
2783 11:04:06.086256 Set Vref, RX VrefLevel [Byte0]: 39
2784 11:04:06.089301 [Byte1]: 39
2785 11:04:06.094118
2786 11:04:06.094207 Set Vref, RX VrefLevel [Byte0]: 40
2787 11:04:06.097609 [Byte1]: 40
2788 11:04:06.101828
2789 11:04:06.101904 Set Vref, RX VrefLevel [Byte0]: 41
2790 11:04:06.105087 [Byte1]: 41
2791 11:04:06.109923
2792 11:04:06.109998 Set Vref, RX VrefLevel [Byte0]: 42
2793 11:04:06.113603 [Byte1]: 42
2794 11:04:06.118133
2795 11:04:06.118249 Set Vref, RX VrefLevel [Byte0]: 43
2796 11:04:06.121470 [Byte1]: 43
2797 11:04:06.126489
2798 11:04:06.126564 Set Vref, RX VrefLevel [Byte0]: 44
2799 11:04:06.129337 [Byte1]: 44
2800 11:04:06.134049
2801 11:04:06.134178 Set Vref, RX VrefLevel [Byte0]: 45
2802 11:04:06.137507 [Byte1]: 45
2803 11:04:06.142503
2804 11:04:06.142581 Set Vref, RX VrefLevel [Byte0]: 46
2805 11:04:06.145438 [Byte1]: 46
2806 11:04:06.150054
2807 11:04:06.150180 Set Vref, RX VrefLevel [Byte0]: 47
2808 11:04:06.153369 [Byte1]: 47
2809 11:04:06.158034
2810 11:04:06.158133 Set Vref, RX VrefLevel [Byte0]: 48
2811 11:04:06.161596 [Byte1]: 48
2812 11:04:06.166476
2813 11:04:06.166551 Set Vref, RX VrefLevel [Byte0]: 49
2814 11:04:06.169287 [Byte1]: 49
2815 11:04:06.174042
2816 11:04:06.174152 Set Vref, RX VrefLevel [Byte0]: 50
2817 11:04:06.177562 [Byte1]: 50
2818 11:04:06.181869
2819 11:04:06.181944 Set Vref, RX VrefLevel [Byte0]: 51
2820 11:04:06.185344 [Byte1]: 51
2821 11:04:06.189862
2822 11:04:06.189937 Set Vref, RX VrefLevel [Byte0]: 52
2823 11:04:06.193169 [Byte1]: 52
2824 11:04:06.197921
2825 11:04:06.198001 Set Vref, RX VrefLevel [Byte0]: 53
2826 11:04:06.201609 [Byte1]: 53
2827 11:04:06.206503
2828 11:04:06.206578 Set Vref, RX VrefLevel [Byte0]: 54
2829 11:04:06.209729 [Byte1]: 54
2830 11:04:06.214219
2831 11:04:06.214319 Set Vref, RX VrefLevel [Byte0]: 55
2832 11:04:06.217104 [Byte1]: 55
2833 11:04:06.222188
2834 11:04:06.222263 Set Vref, RX VrefLevel [Byte0]: 56
2835 11:04:06.225786 [Byte1]: 56
2836 11:04:06.229842
2837 11:04:06.229917 Set Vref, RX VrefLevel [Byte0]: 57
2838 11:04:06.233192 [Byte1]: 57
2839 11:04:06.238338
2840 11:04:06.238436 Set Vref, RX VrefLevel [Byte0]: 58
2841 11:04:06.241221 [Byte1]: 58
2842 11:04:06.246036
2843 11:04:06.246117 Set Vref, RX VrefLevel [Byte0]: 59
2844 11:04:06.249553 [Byte1]: 59
2845 11:04:06.254010
2846 11:04:06.254085 Set Vref, RX VrefLevel [Byte0]: 60
2847 11:04:06.257217 [Byte1]: 60
2848 11:04:06.261849
2849 11:04:06.261924 Set Vref, RX VrefLevel [Byte0]: 61
2850 11:04:06.265496 [Byte1]: 61
2851 11:04:06.270250
2852 11:04:06.270325 Set Vref, RX VrefLevel [Byte0]: 62
2853 11:04:06.273215 [Byte1]: 62
2854 11:04:06.278659
2855 11:04:06.278739 Set Vref, RX VrefLevel [Byte0]: 63
2856 11:04:06.281274 [Byte1]: 63
2857 11:04:06.286172
2858 11:04:06.286247 Set Vref, RX VrefLevel [Byte0]: 64
2859 11:04:06.289883 [Byte1]: 64
2860 11:04:06.294027
2861 11:04:06.294112 Set Vref, RX VrefLevel [Byte0]: 65
2862 11:04:06.297334 [Byte1]: 65
2863 11:04:06.302132
2864 11:04:06.302232 Set Vref, RX VrefLevel [Byte0]: 66
2865 11:04:06.305650 [Byte1]: 66
2866 11:04:06.310224
2867 11:04:06.310292 Set Vref, RX VrefLevel [Byte0]: 67
2868 11:04:06.313541 [Byte1]: 67
2869 11:04:06.318097
2870 11:04:06.318202 Set Vref, RX VrefLevel [Byte0]: 68
2871 11:04:06.321874 [Byte1]: 68
2872 11:04:06.326049
2873 11:04:06.326148 Set Vref, RX VrefLevel [Byte0]: 69
2874 11:04:06.329262 [Byte1]: 69
2875 11:04:06.333810
2876 11:04:06.333905 Set Vref, RX VrefLevel [Byte0]: 70
2877 11:04:06.337319 [Byte1]: 70
2878 11:04:06.342130
2879 11:04:06.342220 Set Vref, RX VrefLevel [Byte0]: 71
2880 11:04:06.345103 [Byte1]: 71
2881 11:04:06.349802
2882 11:04:06.349889 Set Vref, RX VrefLevel [Byte0]: 72
2883 11:04:06.353577 [Byte1]: 72
2884 11:04:06.358404
2885 11:04:06.358466 Set Vref, RX VrefLevel [Byte0]: 73
2886 11:04:06.361104 [Byte1]: 73
2887 11:04:06.366105
2888 11:04:06.366197 Final RX Vref Byte 0 = 60 to rank0
2889 11:04:06.369263 Final RX Vref Byte 1 = 49 to rank0
2890 11:04:06.372619 Final RX Vref Byte 0 = 60 to rank1
2891 11:04:06.375884 Final RX Vref Byte 1 = 49 to rank1==
2892 11:04:06.379328 Dram Type= 6, Freq= 0, CH_0, rank 0
2893 11:04:06.386020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 11:04:06.386133 ==
2895 11:04:06.386207 DQS Delay:
2896 11:04:06.386260 DQS0 = 0, DQS1 = 0
2897 11:04:06.389231 DQM Delay:
2898 11:04:06.389306 DQM0 = 112, DQM1 = 100
2899 11:04:06.392770 DQ Delay:
2900 11:04:06.396254 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2901 11:04:06.399213 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2902 11:04:06.403124 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =92
2903 11:04:06.406433 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2904 11:04:06.406509
2905 11:04:06.406566
2906 11:04:06.413041 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2907 11:04:06.416018 CH0 RK0: MR19=403, MR18=FF
2908 11:04:06.423101 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2909 11:04:06.423177
2910 11:04:06.425798 ----->DramcWriteLeveling(PI) begin...
2911 11:04:06.425874 ==
2912 11:04:06.429540 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 11:04:06.432859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 11:04:06.432935 ==
2915 11:04:06.435978 Write leveling (Byte 0): 32 => 32
2916 11:04:06.439745 Write leveling (Byte 1): 28 => 28
2917 11:04:06.443156 DramcWriteLeveling(PI) end<-----
2918 11:04:06.443232
2919 11:04:06.443291 ==
2920 11:04:06.446259 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 11:04:06.449576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 11:04:06.449653 ==
2923 11:04:06.452568 [Gating] SW mode calibration
2924 11:04:06.459433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2925 11:04:06.465928 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2926 11:04:06.469506 0 15 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2927 11:04:06.475946 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 11:04:06.479291 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 11:04:06.482664 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 11:04:06.489549 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 11:04:06.492865 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 11:04:06.496169 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2933 11:04:06.499165 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2934 11:04:06.505992 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
2935 11:04:06.509750 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 11:04:06.512931 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 11:04:06.519777 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 11:04:06.522558 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 11:04:06.526018 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 11:04:06.532574 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
2941 11:04:06.536141 1 0 28 | B1->B0 | 2424 4545 | 0 1 | (0 0) (0 0)
2942 11:04:06.539272 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2943 11:04:06.546327 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:04:06.549101 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:04:06.552383 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:04:06.559275 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:04:06.562746 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:04:06.566206 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2949 11:04:06.572800 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2950 11:04:06.575810 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2951 11:04:06.579399 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:04:06.585729 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:04:06.589120 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:04:06.593011 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:04:06.599390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:04:06.602893 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:04:06.606069 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:04:06.609280 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:04:06.616321 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:04:06.619426 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:04:06.622832 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:04:06.629468 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:04:06.632858 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:04:06.636469 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2965 11:04:06.642586 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2966 11:04:06.646123 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:04:06.649769 Total UI for P1: 0, mck2ui 16
2968 11:04:06.652790 best dqsien dly found for B0: ( 1, 3, 26)
2969 11:04:06.656525 Total UI for P1: 0, mck2ui 16
2970 11:04:06.659170 best dqsien dly found for B1: ( 1, 3, 30)
2971 11:04:06.662465 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2972 11:04:06.665557 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2973 11:04:06.665633
2974 11:04:06.669053 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2975 11:04:06.672676 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2976 11:04:06.675783 [Gating] SW calibration Done
2977 11:04:06.675858 ==
2978 11:04:06.679763 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 11:04:06.682679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 11:04:06.686296 ==
2981 11:04:06.686372 RX Vref Scan: 0
2982 11:04:06.686430
2983 11:04:06.689257 RX Vref 0 -> 0, step: 1
2984 11:04:06.689333
2985 11:04:06.689392 RX Delay -40 -> 252, step: 8
2986 11:04:06.696051 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2987 11:04:06.699402 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2988 11:04:06.702614 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2989 11:04:06.706042 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2990 11:04:06.709131 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2991 11:04:06.715891 iDelay=200, Bit 5, Center 95 (24 ~ 167) 144
2992 11:04:06.719433 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2993 11:04:06.722852 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2994 11:04:06.725922 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2995 11:04:06.729324 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2996 11:04:06.736404 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2997 11:04:06.739189 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2998 11:04:06.742719 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2999 11:04:06.746208 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
3000 11:04:06.749299 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3001 11:04:06.755919 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3002 11:04:06.755995 ==
3003 11:04:06.759152 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 11:04:06.762467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 11:04:06.762606 ==
3006 11:04:06.762718 DQS Delay:
3007 11:04:06.766204 DQS0 = 0, DQS1 = 0
3008 11:04:06.766279 DQM Delay:
3009 11:04:06.769297 DQM0 = 110, DQM1 = 100
3010 11:04:06.769374 DQ Delay:
3011 11:04:06.772890 DQ0 =107, DQ1 =111, DQ2 =107, DQ3 =107
3012 11:04:06.776125 DQ4 =115, DQ5 =95, DQ6 =119, DQ7 =123
3013 11:04:06.779522 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3014 11:04:06.782891 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
3015 11:04:06.782966
3016 11:04:06.783025
3017 11:04:06.783078 ==
3018 11:04:06.786246 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 11:04:06.792765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 11:04:06.792841 ==
3021 11:04:06.792900
3022 11:04:06.792954
3023 11:04:06.793005 TX Vref Scan disable
3024 11:04:06.796550 == TX Byte 0 ==
3025 11:04:06.799431 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3026 11:04:06.803158 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3027 11:04:06.806573 == TX Byte 1 ==
3028 11:04:06.809694 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3029 11:04:06.812969 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3030 11:04:06.816560 ==
3031 11:04:06.819536 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 11:04:06.823292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 11:04:06.823369 ==
3034 11:04:06.834523 TX Vref=22, minBit 1, minWin=25, winSum=422
3035 11:04:06.837904 TX Vref=24, minBit 1, minWin=26, winSum=428
3036 11:04:06.841358 TX Vref=26, minBit 8, minWin=26, winSum=432
3037 11:04:06.844182 TX Vref=28, minBit 8, minWin=25, winSum=434
3038 11:04:06.847902 TX Vref=30, minBit 8, minWin=26, winSum=434
3039 11:04:06.850992 TX Vref=32, minBit 8, minWin=26, winSum=433
3040 11:04:06.857530 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3041 11:04:06.857612
3042 11:04:06.861109 Final TX Range 1 Vref 30
3043 11:04:06.861186
3044 11:04:06.861244 ==
3045 11:04:06.864531 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 11:04:06.867983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 11:04:06.868060 ==
3048 11:04:06.868118
3049 11:04:06.871009
3050 11:04:06.871084 TX Vref Scan disable
3051 11:04:06.874349 == TX Byte 0 ==
3052 11:04:06.877812 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3053 11:04:06.881035 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3054 11:04:06.884324 == TX Byte 1 ==
3055 11:04:06.887481 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3056 11:04:06.891205 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3057 11:04:06.891281
3058 11:04:06.894853 [DATLAT]
3059 11:04:06.894928 Freq=1200, CH0 RK1
3060 11:04:06.894986
3061 11:04:06.897813 DATLAT Default: 0xd
3062 11:04:06.897889 0, 0xFFFF, sum = 0
3063 11:04:06.900741 1, 0xFFFF, sum = 0
3064 11:04:06.900818 2, 0xFFFF, sum = 0
3065 11:04:06.904461 3, 0xFFFF, sum = 0
3066 11:04:06.904554 4, 0xFFFF, sum = 0
3067 11:04:06.907555 5, 0xFFFF, sum = 0
3068 11:04:06.907632 6, 0xFFFF, sum = 0
3069 11:04:06.911107 7, 0xFFFF, sum = 0
3070 11:04:06.914058 8, 0xFFFF, sum = 0
3071 11:04:06.914158 9, 0xFFFF, sum = 0
3072 11:04:06.917727 10, 0xFFFF, sum = 0
3073 11:04:06.917803 11, 0xFFFF, sum = 0
3074 11:04:06.921092 12, 0x0, sum = 1
3075 11:04:06.921169 13, 0x0, sum = 2
3076 11:04:06.923989 14, 0x0, sum = 3
3077 11:04:06.924065 15, 0x0, sum = 4
3078 11:04:06.924125 best_step = 13
3079 11:04:06.924178
3080 11:04:06.927711 ==
3081 11:04:06.931152 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 11:04:06.934225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:04:06.934317 ==
3084 11:04:06.934377 RX Vref Scan: 0
3085 11:04:06.934432
3086 11:04:06.937706 RX Vref 0 -> 0, step: 1
3087 11:04:06.937780
3088 11:04:06.940990 RX Delay -37 -> 252, step: 4
3089 11:04:06.944189 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3090 11:04:06.951133 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3091 11:04:06.954616 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3092 11:04:06.957311 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3093 11:04:06.960991 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3094 11:04:06.963944 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3095 11:04:06.970578 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3096 11:04:06.973911 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3097 11:04:06.977356 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3098 11:04:06.980805 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3099 11:04:06.983675 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3100 11:04:06.990308 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3101 11:04:06.994087 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3102 11:04:06.996926 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3103 11:04:07.000371 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3104 11:04:07.003752 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3105 11:04:07.003843 ==
3106 11:04:07.007356 Dram Type= 6, Freq= 0, CH_0, rank 1
3107 11:04:07.013710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 11:04:07.013802 ==
3109 11:04:07.013878 DQS Delay:
3110 11:04:07.017009 DQS0 = 0, DQS1 = 0
3111 11:04:07.017096 DQM Delay:
3112 11:04:07.020348 DQM0 = 110, DQM1 = 99
3113 11:04:07.020436 DQ Delay:
3114 11:04:07.023646 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3115 11:04:07.026900 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3116 11:04:07.030467 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =90
3117 11:04:07.034045 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3118 11:04:07.034169
3119 11:04:07.034244
3120 11:04:07.043980 [DQSOSCAuto] RK1, (LSB)MR18= 0x17ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3121 11:04:07.044072 CH0 RK1: MR19=403, MR18=17FF
3122 11:04:07.050080 CH0_RK1: MR19=0x403, MR18=0x17FF, DQSOSC=401, MR23=63, INC=40, DEC=27
3123 11:04:07.053430 [RxdqsGatingPostProcess] freq 1200
3124 11:04:07.060127 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3125 11:04:07.063667 best DQS0 dly(2T, 0.5T) = (0, 11)
3126 11:04:07.067107 best DQS1 dly(2T, 0.5T) = (0, 12)
3127 11:04:07.070006 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3128 11:04:07.073557 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3129 11:04:07.077116 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 11:04:07.077215 best DQS1 dly(2T, 0.5T) = (0, 11)
3131 11:04:07.080034 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 11:04:07.083512 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3133 11:04:07.086581 Pre-setting of DQS Precalculation
3134 11:04:07.093185 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3135 11:04:07.093275 ==
3136 11:04:07.096796 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 11:04:07.100191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 11:04:07.100278 ==
3139 11:04:07.106697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 11:04:07.113074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3141 11:04:07.120308 [CA 0] Center 37 (7~67) winsize 61
3142 11:04:07.123933 [CA 1] Center 37 (7~68) winsize 62
3143 11:04:07.126846 [CA 2] Center 34 (4~64) winsize 61
3144 11:04:07.130319 [CA 3] Center 34 (4~64) winsize 61
3145 11:04:07.133481 [CA 4] Center 34 (4~64) winsize 61
3146 11:04:07.136897 [CA 5] Center 33 (3~63) winsize 61
3147 11:04:07.136990
3148 11:04:07.140400 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3149 11:04:07.140490
3150 11:04:07.143417 [CATrainingPosCal] consider 1 rank data
3151 11:04:07.147083 u2DelayCellTimex100 = 270/100 ps
3152 11:04:07.149918 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3153 11:04:07.156622 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 11:04:07.159779 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 11:04:07.163159 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 11:04:07.166840 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 11:04:07.169728 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3158 11:04:07.169814
3159 11:04:07.173150 CA PerBit enable=1, Macro0, CA PI delay=33
3160 11:04:07.173242
3161 11:04:07.176279 [CBTSetCACLKResult] CA Dly = 33
3162 11:04:07.176371 CS Dly: 6 (0~37)
3163 11:04:07.179935 ==
3164 11:04:07.183175 Dram Type= 6, Freq= 0, CH_1, rank 1
3165 11:04:07.186425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 11:04:07.186521 ==
3167 11:04:07.193185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3168 11:04:07.196566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3169 11:04:07.206052 [CA 0] Center 37 (7~67) winsize 61
3170 11:04:07.208966 [CA 1] Center 37 (7~68) winsize 62
3171 11:04:07.212372 [CA 2] Center 34 (4~65) winsize 62
3172 11:04:07.216195 [CA 3] Center 33 (3~64) winsize 62
3173 11:04:07.219114 [CA 4] Center 34 (4~65) winsize 62
3174 11:04:07.222344 [CA 5] Center 32 (2~63) winsize 62
3175 11:04:07.222437
3176 11:04:07.225419 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3177 11:04:07.225511
3178 11:04:07.229019 [CATrainingPosCal] consider 2 rank data
3179 11:04:07.232117 u2DelayCellTimex100 = 270/100 ps
3180 11:04:07.235679 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3181 11:04:07.242068 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3182 11:04:07.245401 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 11:04:07.249019 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3184 11:04:07.251998 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3185 11:04:07.255500 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3186 11:04:07.255589
3187 11:04:07.258991 CA PerBit enable=1, Macro0, CA PI delay=33
3188 11:04:07.259080
3189 11:04:07.262367 [CBTSetCACLKResult] CA Dly = 33
3190 11:04:07.262455 CS Dly: 7 (0~39)
3191 11:04:07.265384
3192 11:04:07.268924 ----->DramcWriteLeveling(PI) begin...
3193 11:04:07.269017 ==
3194 11:04:07.271831 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 11:04:07.275361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 11:04:07.275453 ==
3197 11:04:07.278784 Write leveling (Byte 0): 25 => 25
3198 11:04:07.281992 Write leveling (Byte 1): 28 => 28
3199 11:04:07.285479 DramcWriteLeveling(PI) end<-----
3200 11:04:07.285570
3201 11:04:07.285646 ==
3202 11:04:07.288509 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 11:04:07.292085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 11:04:07.292176 ==
3205 11:04:07.295639 [Gating] SW mode calibration
3206 11:04:07.302016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3207 11:04:07.308711 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3208 11:04:07.312298 0 15 0 | B1->B0 | 3030 2d2d | 1 1 | (1 1) (1 1)
3209 11:04:07.315550 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 11:04:07.321898 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 11:04:07.325190 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 11:04:07.328712 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 11:04:07.334974 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 11:04:07.338459 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3215 11:04:07.341707 0 15 28 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
3216 11:04:07.348279 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 11:04:07.351740 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 11:04:07.355416 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 11:04:07.358436 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 11:04:07.365113 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 11:04:07.368330 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 11:04:07.371534 1 0 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
3223 11:04:07.378252 1 0 28 | B1->B0 | 4242 4040 | 1 1 | (0 0) (0 0)
3224 11:04:07.381776 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:04:07.385041 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:04:07.391809 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:04:07.394868 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:04:07.398074 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:04:07.405170 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 11:04:07.408038 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 11:04:07.411686 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3232 11:04:07.418049 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:04:07.421815 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:04:07.424898 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:04:07.431684 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:04:07.434771 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:04:07.438358 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:04:07.444573 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:04:07.448176 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:04:07.451466 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:04:07.458230 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:04:07.461206 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:04:07.464622 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:04:07.471434 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:04:07.474521 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:04:07.478031 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3247 11:04:07.484265 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3248 11:04:07.487857 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 11:04:07.491505 Total UI for P1: 0, mck2ui 16
3250 11:04:07.494281 best dqsien dly found for B0: ( 1, 3, 28)
3251 11:04:07.497624 Total UI for P1: 0, mck2ui 16
3252 11:04:07.501157 best dqsien dly found for B1: ( 1, 3, 26)
3253 11:04:07.504239 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3254 11:04:07.507549 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3255 11:04:07.507638
3256 11:04:07.511250 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3257 11:04:07.514112 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3258 11:04:07.517741 [Gating] SW calibration Done
3259 11:04:07.517825 ==
3260 11:04:07.520829 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 11:04:07.523809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 11:04:07.527405 ==
3263 11:04:07.527491 RX Vref Scan: 0
3264 11:04:07.527567
3265 11:04:07.530983 RX Vref 0 -> 0, step: 1
3266 11:04:07.531072
3267 11:04:07.531148 RX Delay -40 -> 252, step: 8
3268 11:04:07.537613 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3269 11:04:07.541193 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3270 11:04:07.544169 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3271 11:04:07.547701 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3272 11:04:07.550960 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3273 11:04:07.557653 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3274 11:04:07.560686 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3275 11:04:07.564047 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3276 11:04:07.567203 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3277 11:04:07.570950 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3278 11:04:07.577458 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3279 11:04:07.580505 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3280 11:04:07.584049 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3281 11:04:07.587110 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3282 11:04:07.590422 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3283 11:04:07.597221 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3284 11:04:07.597315 ==
3285 11:04:07.600517 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 11:04:07.603975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 11:04:07.604069 ==
3288 11:04:07.604147 DQS Delay:
3289 11:04:07.607036 DQS0 = 0, DQS1 = 0
3290 11:04:07.607127 DQM Delay:
3291 11:04:07.610281 DQM0 = 113, DQM1 = 106
3292 11:04:07.610376 DQ Delay:
3293 11:04:07.613949 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =111
3294 11:04:07.617184 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3295 11:04:07.620202 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3296 11:04:07.623776 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3297 11:04:07.623865
3298 11:04:07.627428
3299 11:04:07.627515 ==
3300 11:04:07.630113 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 11:04:07.633582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 11:04:07.633668 ==
3303 11:04:07.633742
3304 11:04:07.633813
3305 11:04:07.637214 TX Vref Scan disable
3306 11:04:07.637301 == TX Byte 0 ==
3307 11:04:07.644077 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3308 11:04:07.646853 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3309 11:04:07.646943 == TX Byte 1 ==
3310 11:04:07.653562 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3311 11:04:07.656804 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3312 11:04:07.656906 ==
3313 11:04:07.660007 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 11:04:07.663615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 11:04:07.663709 ==
3316 11:04:07.675703 TX Vref=22, minBit 9, minWin=24, winSum=409
3317 11:04:07.678817 TX Vref=24, minBit 8, minWin=25, winSum=416
3318 11:04:07.682426 TX Vref=26, minBit 8, minWin=25, winSum=417
3319 11:04:07.685647 TX Vref=28, minBit 11, minWin=25, winSum=426
3320 11:04:07.688988 TX Vref=30, minBit 11, minWin=25, winSum=427
3321 11:04:07.695681 TX Vref=32, minBit 9, minWin=25, winSum=421
3322 11:04:07.698654 [TxChooseVref] Worse bit 11, Min win 25, Win sum 427, Final Vref 30
3323 11:04:07.698753
3324 11:04:07.702145 Final TX Range 1 Vref 30
3325 11:04:07.702242
3326 11:04:07.702322 ==
3327 11:04:07.705671 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 11:04:07.709408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 11:04:07.712027 ==
3330 11:04:07.712121
3331 11:04:07.712200
3332 11:04:07.712279 TX Vref Scan disable
3333 11:04:07.715423 == TX Byte 0 ==
3334 11:04:07.718637 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3335 11:04:07.725825 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3336 11:04:07.725934 == TX Byte 1 ==
3337 11:04:07.729194 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3338 11:04:07.735109 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3339 11:04:07.735180
3340 11:04:07.735237 [DATLAT]
3341 11:04:07.735290 Freq=1200, CH1 RK0
3342 11:04:07.735341
3343 11:04:07.738505 DATLAT Default: 0xd
3344 11:04:07.741884 0, 0xFFFF, sum = 0
3345 11:04:07.741977 1, 0xFFFF, sum = 0
3346 11:04:07.745725 2, 0xFFFF, sum = 0
3347 11:04:07.745821 3, 0xFFFF, sum = 0
3348 11:04:07.748835 4, 0xFFFF, sum = 0
3349 11:04:07.748906 5, 0xFFFF, sum = 0
3350 11:04:07.752172 6, 0xFFFF, sum = 0
3351 11:04:07.752274 7, 0xFFFF, sum = 0
3352 11:04:07.755110 8, 0xFFFF, sum = 0
3353 11:04:07.755181 9, 0xFFFF, sum = 0
3354 11:04:07.758166 10, 0xFFFF, sum = 0
3355 11:04:07.758237 11, 0xFFFF, sum = 0
3356 11:04:07.761509 12, 0x0, sum = 1
3357 11:04:07.761633 13, 0x0, sum = 2
3358 11:04:07.764904 14, 0x0, sum = 3
3359 11:04:07.765004 15, 0x0, sum = 4
3360 11:04:07.768069 best_step = 13
3361 11:04:07.768190
3362 11:04:07.768280 ==
3363 11:04:07.771736 Dram Type= 6, Freq= 0, CH_1, rank 0
3364 11:04:07.774853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3365 11:04:07.774926 ==
3366 11:04:07.778590 RX Vref Scan: 1
3367 11:04:07.778663
3368 11:04:07.778753 Set Vref Range= 32 -> 127
3369 11:04:07.778841
3370 11:04:07.781445 RX Vref 32 -> 127, step: 1
3371 11:04:07.781542
3372 11:04:07.785002 RX Delay -21 -> 252, step: 4
3373 11:04:07.785099
3374 11:04:07.788593 Set Vref, RX VrefLevel [Byte0]: 32
3375 11:04:07.791679 [Byte1]: 32
3376 11:04:07.791773
3377 11:04:07.794753 Set Vref, RX VrefLevel [Byte0]: 33
3378 11:04:07.798089 [Byte1]: 33
3379 11:04:07.802431
3380 11:04:07.802522 Set Vref, RX VrefLevel [Byte0]: 34
3381 11:04:07.805645 [Byte1]: 34
3382 11:04:07.810188
3383 11:04:07.810280 Set Vref, RX VrefLevel [Byte0]: 35
3384 11:04:07.813446 [Byte1]: 35
3385 11:04:07.818220
3386 11:04:07.818311 Set Vref, RX VrefLevel [Byte0]: 36
3387 11:04:07.821021 [Byte1]: 36
3388 11:04:07.826109
3389 11:04:07.826199 Set Vref, RX VrefLevel [Byte0]: 37
3390 11:04:07.829127 [Byte1]: 37
3391 11:04:07.833802
3392 11:04:07.833889 Set Vref, RX VrefLevel [Byte0]: 38
3393 11:04:07.837257 [Byte1]: 38
3394 11:04:07.841769
3395 11:04:07.841857 Set Vref, RX VrefLevel [Byte0]: 39
3396 11:04:07.845070 [Byte1]: 39
3397 11:04:07.849585
3398 11:04:07.849675 Set Vref, RX VrefLevel [Byte0]: 40
3399 11:04:07.853362 [Byte1]: 40
3400 11:04:07.857676
3401 11:04:07.857767 Set Vref, RX VrefLevel [Byte0]: 41
3402 11:04:07.861124 [Byte1]: 41
3403 11:04:07.865506
3404 11:04:07.865605 Set Vref, RX VrefLevel [Byte0]: 42
3405 11:04:07.868588 [Byte1]: 42
3406 11:04:07.873230
3407 11:04:07.873328 Set Vref, RX VrefLevel [Byte0]: 43
3408 11:04:07.876991 [Byte1]: 43
3409 11:04:07.881828
3410 11:04:07.881922 Set Vref, RX VrefLevel [Byte0]: 44
3411 11:04:07.884743 [Byte1]: 44
3412 11:04:07.889561
3413 11:04:07.889655 Set Vref, RX VrefLevel [Byte0]: 45
3414 11:04:07.892593 [Byte1]: 45
3415 11:04:07.897186
3416 11:04:07.897277 Set Vref, RX VrefLevel [Byte0]: 46
3417 11:04:07.900750 [Byte1]: 46
3418 11:04:07.905229
3419 11:04:07.905315 Set Vref, RX VrefLevel [Byte0]: 47
3420 11:04:07.908190 [Byte1]: 47
3421 11:04:07.912789
3422 11:04:07.912873 Set Vref, RX VrefLevel [Byte0]: 48
3423 11:04:07.916554 [Byte1]: 48
3424 11:04:07.921174
3425 11:04:07.921263 Set Vref, RX VrefLevel [Byte0]: 49
3426 11:04:07.924479 [Byte1]: 49
3427 11:04:07.928714
3428 11:04:07.928803 Set Vref, RX VrefLevel [Byte0]: 50
3429 11:04:07.931947 [Byte1]: 50
3430 11:04:07.936881
3431 11:04:07.936980 Set Vref, RX VrefLevel [Byte0]: 51
3432 11:04:07.940543 [Byte1]: 51
3433 11:04:07.945019
3434 11:04:07.945108 Set Vref, RX VrefLevel [Byte0]: 52
3435 11:04:07.948056 [Byte1]: 52
3436 11:04:07.952835
3437 11:04:07.952926 Set Vref, RX VrefLevel [Byte0]: 53
3438 11:04:07.955948 [Byte1]: 53
3439 11:04:07.961004
3440 11:04:07.961094 Set Vref, RX VrefLevel [Byte0]: 54
3441 11:04:07.963631 [Byte1]: 54
3442 11:04:07.968523
3443 11:04:07.968634 Set Vref, RX VrefLevel [Byte0]: 55
3444 11:04:07.971932 [Byte1]: 55
3445 11:04:07.976560
3446 11:04:07.976649 Set Vref, RX VrefLevel [Byte0]: 56
3447 11:04:07.983081 [Byte1]: 56
3448 11:04:07.983170
3449 11:04:07.986636 Set Vref, RX VrefLevel [Byte0]: 57
3450 11:04:07.989553 [Byte1]: 57
3451 11:04:07.989639
3452 11:04:07.992779 Set Vref, RX VrefLevel [Byte0]: 58
3453 11:04:07.995872 [Byte1]: 58
3454 11:04:08.000316
3455 11:04:08.000403 Set Vref, RX VrefLevel [Byte0]: 59
3456 11:04:08.003314 [Byte1]: 59
3457 11:04:08.008286
3458 11:04:08.008372 Set Vref, RX VrefLevel [Byte0]: 60
3459 11:04:08.011464 [Byte1]: 60
3460 11:04:08.016100
3461 11:04:08.016186 Set Vref, RX VrefLevel [Byte0]: 61
3462 11:04:08.019500 [Byte1]: 61
3463 11:04:08.023882
3464 11:04:08.023968 Set Vref, RX VrefLevel [Byte0]: 62
3465 11:04:08.027131 [Byte1]: 62
3466 11:04:08.031714
3467 11:04:08.031802 Set Vref, RX VrefLevel [Byte0]: 63
3468 11:04:08.035039 [Byte1]: 63
3469 11:04:08.039805
3470 11:04:08.039891 Set Vref, RX VrefLevel [Byte0]: 64
3471 11:04:08.043035 [Byte1]: 64
3472 11:04:08.047853
3473 11:04:08.047943 Set Vref, RX VrefLevel [Byte0]: 65
3474 11:04:08.050933 [Byte1]: 65
3475 11:04:08.055501
3476 11:04:08.055596 Set Vref, RX VrefLevel [Byte0]: 66
3477 11:04:08.058924 [Byte1]: 66
3478 11:04:08.063625
3479 11:04:08.063737 Set Vref, RX VrefLevel [Byte0]: 67
3480 11:04:08.066864 [Byte1]: 67
3481 11:04:08.071510
3482 11:04:08.071600 Final RX Vref Byte 0 = 55 to rank0
3483 11:04:08.075174 Final RX Vref Byte 1 = 51 to rank0
3484 11:04:08.078116 Final RX Vref Byte 0 = 55 to rank1
3485 11:04:08.081640 Final RX Vref Byte 1 = 51 to rank1==
3486 11:04:08.085049 Dram Type= 6, Freq= 0, CH_1, rank 0
3487 11:04:08.088538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 11:04:08.091388 ==
3489 11:04:08.091478 DQS Delay:
3490 11:04:08.091552 DQS0 = 0, DQS1 = 0
3491 11:04:08.095020 DQM Delay:
3492 11:04:08.095109 DQM0 = 114, DQM1 = 106
3493 11:04:08.098704 DQ Delay:
3494 11:04:08.101446 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3495 11:04:08.104722 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3496 11:04:08.108123 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3497 11:04:08.111619 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =112
3498 11:04:08.111711
3499 11:04:08.111790
3500 11:04:08.118429 [DQSOSCAuto] RK0, (LSB)MR18= 0xf6fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3501 11:04:08.121177 CH1 RK0: MR19=303, MR18=F6FC
3502 11:04:08.128354 CH1_RK0: MR19=0x303, MR18=0xF6FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3503 11:04:08.128454
3504 11:04:08.131172 ----->DramcWriteLeveling(PI) begin...
3505 11:04:08.131262 ==
3506 11:04:08.135096 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 11:04:08.137998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 11:04:08.141581 ==
3509 11:04:08.141669 Write leveling (Byte 0): 23 => 23
3510 11:04:08.144658 Write leveling (Byte 1): 27 => 27
3511 11:04:08.148230 DramcWriteLeveling(PI) end<-----
3512 11:04:08.148318
3513 11:04:08.148392 ==
3514 11:04:08.151359 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 11:04:08.157916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 11:04:08.158008 ==
3517 11:04:08.161406 [Gating] SW mode calibration
3518 11:04:08.168273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3519 11:04:08.170940 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3520 11:04:08.177729 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3521 11:04:08.180856 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 11:04:08.184420 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 11:04:08.190975 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 11:04:08.194024 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 11:04:08.197394 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
3526 11:04:08.203871 0 15 24 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
3527 11:04:08.207718 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3528 11:04:08.210912 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 11:04:08.217331 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 11:04:08.220728 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 11:04:08.224019 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 11:04:08.230602 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 11:04:08.233951 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3534 11:04:08.237083 1 0 24 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
3535 11:04:08.244035 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 11:04:08.247073 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 11:04:08.250760 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 11:04:08.253770 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:04:08.260251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:04:08.263784 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 11:04:08.267263 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3542 11:04:08.273851 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3543 11:04:08.277340 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:04:08.280694 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:04:08.287184 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:04:08.290392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:04:08.293747 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:04:08.300704 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:04:08.303681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:04:08.306851 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:04:08.313920 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:04:08.316837 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:04:08.320247 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:04:08.326675 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:04:08.330278 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 11:04:08.333543 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 11:04:08.340160 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 11:04:08.343574 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3559 11:04:08.346981 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 11:04:08.350087 Total UI for P1: 0, mck2ui 16
3561 11:04:08.353335 best dqsien dly found for B0: ( 1, 3, 24)
3562 11:04:08.356881 Total UI for P1: 0, mck2ui 16
3563 11:04:08.360452 best dqsien dly found for B1: ( 1, 3, 24)
3564 11:04:08.363402 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3565 11:04:08.367018 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3566 11:04:08.367109
3567 11:04:08.369867 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3568 11:04:08.376381 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3569 11:04:08.376471 [Gating] SW calibration Done
3570 11:04:08.379943 ==
3571 11:04:08.380030 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 11:04:08.386820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 11:04:08.386911 ==
3574 11:04:08.386987 RX Vref Scan: 0
3575 11:04:08.387060
3576 11:04:08.389989 RX Vref 0 -> 0, step: 1
3577 11:04:08.390079
3578 11:04:08.393800 RX Delay -40 -> 252, step: 8
3579 11:04:08.396826 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3580 11:04:08.399801 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3581 11:04:08.403349 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3582 11:04:08.409779 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3583 11:04:08.413432 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3584 11:04:08.416293 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3585 11:04:08.419839 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3586 11:04:08.423275 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3587 11:04:08.429802 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3588 11:04:08.433415 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3589 11:04:08.436349 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3590 11:04:08.439495 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3591 11:04:08.442970 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3592 11:04:08.449428 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3593 11:04:08.452805 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3594 11:04:08.456374 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3595 11:04:08.456465 ==
3596 11:04:08.459367 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 11:04:08.462703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 11:04:08.462780 ==
3599 11:04:08.466057 DQS Delay:
3600 11:04:08.466175 DQS0 = 0, DQS1 = 0
3601 11:04:08.469447 DQM Delay:
3602 11:04:08.469516 DQM0 = 110, DQM1 = 107
3603 11:04:08.472833 DQ Delay:
3604 11:04:08.476138 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3605 11:04:08.479241 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3606 11:04:08.482605 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3607 11:04:08.486274 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3608 11:04:08.486340
3609 11:04:08.486401
3610 11:04:08.486453 ==
3611 11:04:08.489411 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:04:08.492663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:04:08.492757 ==
3614 11:04:08.492835
3615 11:04:08.492909
3616 11:04:08.496069 TX Vref Scan disable
3617 11:04:08.499257 == TX Byte 0 ==
3618 11:04:08.502892 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3619 11:04:08.505817 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3620 11:04:08.509346 == TX Byte 1 ==
3621 11:04:08.512514 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 11:04:08.515958 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 11:04:08.516045 ==
3624 11:04:08.519522 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 11:04:08.522353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 11:04:08.526011 ==
3627 11:04:08.535952 TX Vref=22, minBit 0, minWin=25, winSum=418
3628 11:04:08.539684 TX Vref=24, minBit 0, minWin=26, winSum=426
3629 11:04:08.542519 TX Vref=26, minBit 0, minWin=26, winSum=429
3630 11:04:08.545951 TX Vref=28, minBit 0, minWin=26, winSum=433
3631 11:04:08.549201 TX Vref=30, minBit 0, minWin=26, winSum=428
3632 11:04:08.552767 TX Vref=32, minBit 1, minWin=26, winSum=432
3633 11:04:08.559334 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
3634 11:04:08.559436
3635 11:04:08.562695 Final TX Range 1 Vref 28
3636 11:04:08.562802
3637 11:04:08.562862 ==
3638 11:04:08.566288 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 11:04:08.569328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 11:04:08.569453 ==
3641 11:04:08.569524
3642 11:04:08.572681
3643 11:04:08.572771 TX Vref Scan disable
3644 11:04:08.576098 == TX Byte 0 ==
3645 11:04:08.579557 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3646 11:04:08.582373 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3647 11:04:08.585891 == TX Byte 1 ==
3648 11:04:08.589476 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3649 11:04:08.592375 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3650 11:04:08.595911
3651 11:04:08.596001 [DATLAT]
3652 11:04:08.596075 Freq=1200, CH1 RK1
3653 11:04:08.596146
3654 11:04:08.599152 DATLAT Default: 0xd
3655 11:04:08.599235 0, 0xFFFF, sum = 0
3656 11:04:08.602329 1, 0xFFFF, sum = 0
3657 11:04:08.602413 2, 0xFFFF, sum = 0
3658 11:04:08.605889 3, 0xFFFF, sum = 0
3659 11:04:08.605980 4, 0xFFFF, sum = 0
3660 11:04:08.609151 5, 0xFFFF, sum = 0
3661 11:04:08.612461 6, 0xFFFF, sum = 0
3662 11:04:08.612558 7, 0xFFFF, sum = 0
3663 11:04:08.615605 8, 0xFFFF, sum = 0
3664 11:04:08.615708 9, 0xFFFF, sum = 0
3665 11:04:08.618849 10, 0xFFFF, sum = 0
3666 11:04:08.618921 11, 0xFFFF, sum = 0
3667 11:04:08.622502 12, 0x0, sum = 1
3668 11:04:08.622574 13, 0x0, sum = 2
3669 11:04:08.625966 14, 0x0, sum = 3
3670 11:04:08.626035 15, 0x0, sum = 4
3671 11:04:08.626090 best_step = 13
3672 11:04:08.629043
3673 11:04:08.629112 ==
3674 11:04:08.632410 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 11:04:08.635508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 11:04:08.635580 ==
3677 11:04:08.635637 RX Vref Scan: 0
3678 11:04:08.635689
3679 11:04:08.639089 RX Vref 0 -> 0, step: 1
3680 11:04:08.639151
3681 11:04:08.642009 RX Delay -21 -> 252, step: 4
3682 11:04:08.645621 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3683 11:04:08.652220 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3684 11:04:08.655464 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3685 11:04:08.659283 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3686 11:04:08.662023 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3687 11:04:08.665494 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3688 11:04:08.671912 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3689 11:04:08.675273 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3690 11:04:08.678887 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3691 11:04:08.682035 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3692 11:04:08.685247 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3693 11:04:08.692313 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3694 11:04:08.695261 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3695 11:04:08.698888 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3696 11:04:08.701753 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3697 11:04:08.705695 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3698 11:04:08.709092 ==
3699 11:04:08.712117 Dram Type= 6, Freq= 0, CH_1, rank 1
3700 11:04:08.715198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3701 11:04:08.715298 ==
3702 11:04:08.715380 DQS Delay:
3703 11:04:08.718642 DQS0 = 0, DQS1 = 0
3704 11:04:08.718735 DQM Delay:
3705 11:04:08.721990 DQM0 = 111, DQM1 = 108
3706 11:04:08.722136 DQ Delay:
3707 11:04:08.725149 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3708 11:04:08.728411 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3709 11:04:08.731828 DQ8 =94, DQ9 =98, DQ10 =110, DQ11 =102
3710 11:04:08.735171 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3711 11:04:08.735265
3712 11:04:08.735346
3713 11:04:08.745097 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3714 11:04:08.745174 CH1 RK1: MR19=304, MR18=FB0A
3715 11:04:08.751696 CH1_RK1: MR19=0x304, MR18=0xFB0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3716 11:04:08.754857 [RxdqsGatingPostProcess] freq 1200
3717 11:04:08.761749 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3718 11:04:08.765070 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 11:04:08.768255 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 11:04:08.771812 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 11:04:08.774912 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 11:04:08.778671 best DQS0 dly(2T, 0.5T) = (0, 11)
3723 11:04:08.781690 best DQS1 dly(2T, 0.5T) = (0, 11)
3724 11:04:08.784845 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3725 11:04:08.784936 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3726 11:04:08.788329 Pre-setting of DQS Precalculation
3727 11:04:08.794844 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3728 11:04:08.801602 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3729 11:04:08.808829 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3730 11:04:08.808926
3731 11:04:08.809003
3732 11:04:08.811687 [Calibration Summary] 2400 Mbps
3733 11:04:08.814729 CH 0, Rank 0
3734 11:04:08.814826 SW Impedance : PASS
3735 11:04:08.818470 DUTY Scan : NO K
3736 11:04:08.821660 ZQ Calibration : PASS
3737 11:04:08.821756 Jitter Meter : NO K
3738 11:04:08.825259 CBT Training : PASS
3739 11:04:08.825349 Write leveling : PASS
3740 11:04:08.828175 RX DQS gating : PASS
3741 11:04:08.831768 RX DQ/DQS(RDDQC) : PASS
3742 11:04:08.831856 TX DQ/DQS : PASS
3743 11:04:08.834823 RX DATLAT : PASS
3744 11:04:08.837980 RX DQ/DQS(Engine): PASS
3745 11:04:08.838067 TX OE : NO K
3746 11:04:08.841189 All Pass.
3747 11:04:08.841276
3748 11:04:08.841351 CH 0, Rank 1
3749 11:04:08.844367 SW Impedance : PASS
3750 11:04:08.844456 DUTY Scan : NO K
3751 11:04:08.848155 ZQ Calibration : PASS
3752 11:04:08.851259 Jitter Meter : NO K
3753 11:04:08.851351 CBT Training : PASS
3754 11:04:08.854461 Write leveling : PASS
3755 11:04:08.857745 RX DQS gating : PASS
3756 11:04:08.857832 RX DQ/DQS(RDDQC) : PASS
3757 11:04:08.861127 TX DQ/DQS : PASS
3758 11:04:08.864417 RX DATLAT : PASS
3759 11:04:08.864507 RX DQ/DQS(Engine): PASS
3760 11:04:08.868304 TX OE : NO K
3761 11:04:08.868392 All Pass.
3762 11:04:08.868467
3763 11:04:08.870918 CH 1, Rank 0
3764 11:04:08.871005 SW Impedance : PASS
3765 11:04:08.874714 DUTY Scan : NO K
3766 11:04:08.878022 ZQ Calibration : PASS
3767 11:04:08.878152 Jitter Meter : NO K
3768 11:04:08.880864 CBT Training : PASS
3769 11:04:08.884163 Write leveling : PASS
3770 11:04:08.884258 RX DQS gating : PASS
3771 11:04:08.887592 RX DQ/DQS(RDDQC) : PASS
3772 11:04:08.890736 TX DQ/DQS : PASS
3773 11:04:08.890837 RX DATLAT : PASS
3774 11:04:08.894321 RX DQ/DQS(Engine): PASS
3775 11:04:08.894419 TX OE : NO K
3776 11:04:08.898059 All Pass.
3777 11:04:08.898158
3778 11:04:08.898234 CH 1, Rank 1
3779 11:04:08.900824 SW Impedance : PASS
3780 11:04:08.900921 DUTY Scan : NO K
3781 11:04:08.904618 ZQ Calibration : PASS
3782 11:04:08.907453 Jitter Meter : NO K
3783 11:04:08.907549 CBT Training : PASS
3784 11:04:08.911074 Write leveling : PASS
3785 11:04:08.914216 RX DQS gating : PASS
3786 11:04:08.914313 RX DQ/DQS(RDDQC) : PASS
3787 11:04:08.917593 TX DQ/DQS : PASS
3788 11:04:08.920665 RX DATLAT : PASS
3789 11:04:08.920757 RX DQ/DQS(Engine): PASS
3790 11:04:08.924206 TX OE : NO K
3791 11:04:08.924294 All Pass.
3792 11:04:08.924369
3793 11:04:08.927420 DramC Write-DBI off
3794 11:04:08.930437 PER_BANK_REFRESH: Hybrid Mode
3795 11:04:08.930522 TX_TRACKING: ON
3796 11:04:08.940447 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3797 11:04:08.943916 [FAST_K] Save calibration result to emmc
3798 11:04:08.947257 dramc_set_vcore_voltage set vcore to 650000
3799 11:04:08.950769 Read voltage for 600, 5
3800 11:04:08.950856 Vio18 = 0
3801 11:04:08.950930 Vcore = 650000
3802 11:04:08.953688 Vdram = 0
3803 11:04:08.953774 Vddq = 0
3804 11:04:08.953848 Vmddr = 0
3805 11:04:08.960679 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3806 11:04:08.964159 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3807 11:04:08.967029 MEM_TYPE=3, freq_sel=19
3808 11:04:08.970589 sv_algorithm_assistance_LP4_1600
3809 11:04:08.973989 ============ PULL DRAM RESETB DOWN ============
3810 11:04:08.976867 ========== PULL DRAM RESETB DOWN end =========
3811 11:04:08.983780 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3812 11:04:08.987052 ===================================
3813 11:04:08.990554 LPDDR4 DRAM CONFIGURATION
3814 11:04:08.993588 ===================================
3815 11:04:08.993677 EX_ROW_EN[0] = 0x0
3816 11:04:08.996911 EX_ROW_EN[1] = 0x0
3817 11:04:08.996997 LP4Y_EN = 0x0
3818 11:04:09.000207 WORK_FSP = 0x0
3819 11:04:09.000295 WL = 0x2
3820 11:04:09.003615 RL = 0x2
3821 11:04:09.003706 BL = 0x2
3822 11:04:09.006836 RPST = 0x0
3823 11:04:09.006926 RD_PRE = 0x0
3824 11:04:09.010213 WR_PRE = 0x1
3825 11:04:09.010304 WR_PST = 0x0
3826 11:04:09.014010 DBI_WR = 0x0
3827 11:04:09.014116 DBI_RD = 0x0
3828 11:04:09.016816 OTF = 0x1
3829 11:04:09.020325 ===================================
3830 11:04:09.023587 ===================================
3831 11:04:09.023683 ANA top config
3832 11:04:09.027147 ===================================
3833 11:04:09.030034 DLL_ASYNC_EN = 0
3834 11:04:09.033520 ALL_SLAVE_EN = 1
3835 11:04:09.037137 NEW_RANK_MODE = 1
3836 11:04:09.037235 DLL_IDLE_MODE = 1
3837 11:04:09.040078 LP45_APHY_COMB_EN = 1
3838 11:04:09.043846 TX_ODT_DIS = 1
3839 11:04:09.046581 NEW_8X_MODE = 1
3840 11:04:09.050165 ===================================
3841 11:04:09.053157 ===================================
3842 11:04:09.056778 data_rate = 1200
3843 11:04:09.056862 CKR = 1
3844 11:04:09.060075 DQ_P2S_RATIO = 8
3845 11:04:09.063165 ===================================
3846 11:04:09.066612 CA_P2S_RATIO = 8
3847 11:04:09.070053 DQ_CA_OPEN = 0
3848 11:04:09.073484 DQ_SEMI_OPEN = 0
3849 11:04:09.077000 CA_SEMI_OPEN = 0
3850 11:04:09.077091 CA_FULL_RATE = 0
3851 11:04:09.079993 DQ_CKDIV4_EN = 1
3852 11:04:09.083625 CA_CKDIV4_EN = 1
3853 11:04:09.086694 CA_PREDIV_EN = 0
3854 11:04:09.089899 PH8_DLY = 0
3855 11:04:09.093277 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3856 11:04:09.093368 DQ_AAMCK_DIV = 4
3857 11:04:09.096483 CA_AAMCK_DIV = 4
3858 11:04:09.099847 CA_ADMCK_DIV = 4
3859 11:04:09.103269 DQ_TRACK_CA_EN = 0
3860 11:04:09.106465 CA_PICK = 600
3861 11:04:09.110066 CA_MCKIO = 600
3862 11:04:09.110192 MCKIO_SEMI = 0
3863 11:04:09.113148 PLL_FREQ = 2288
3864 11:04:09.116549 DQ_UI_PI_RATIO = 32
3865 11:04:09.120045 CA_UI_PI_RATIO = 0
3866 11:04:09.123374 ===================================
3867 11:04:09.126416 ===================================
3868 11:04:09.129998 memory_type:LPDDR4
3869 11:04:09.130084 GP_NUM : 10
3870 11:04:09.133016 SRAM_EN : 1
3871 11:04:09.136347 MD32_EN : 0
3872 11:04:09.139879 ===================================
3873 11:04:09.139966 [ANA_INIT] >>>>>>>>>>>>>>
3874 11:04:09.143285 <<<<<< [CONFIGURE PHASE]: ANA_TX
3875 11:04:09.146392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3876 11:04:09.149959 ===================================
3877 11:04:09.153385 data_rate = 1200,PCW = 0X5800
3878 11:04:09.156277 ===================================
3879 11:04:09.159447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3880 11:04:09.166477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 11:04:09.169497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3882 11:04:09.176272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3883 11:04:09.179644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3884 11:04:09.183199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3885 11:04:09.183286 [ANA_INIT] flow start
3886 11:04:09.186245 [ANA_INIT] PLL >>>>>>>>
3887 11:04:09.189486 [ANA_INIT] PLL <<<<<<<<
3888 11:04:09.192861 [ANA_INIT] MIDPI >>>>>>>>
3889 11:04:09.192958 [ANA_INIT] MIDPI <<<<<<<<
3890 11:04:09.196007 [ANA_INIT] DLL >>>>>>>>
3891 11:04:09.199534 [ANA_INIT] flow end
3892 11:04:09.202720 ============ LP4 DIFF to SE enter ============
3893 11:04:09.206687 ============ LP4 DIFF to SE exit ============
3894 11:04:09.209585 [ANA_INIT] <<<<<<<<<<<<<
3895 11:04:09.212585 [Flow] Enable top DCM control >>>>>
3896 11:04:09.216087 [Flow] Enable top DCM control <<<<<
3897 11:04:09.219565 Enable DLL master slave shuffle
3898 11:04:09.222556 ==============================================================
3899 11:04:09.226210 Gating Mode config
3900 11:04:09.232671 ==============================================================
3901 11:04:09.232769 Config description:
3902 11:04:09.242335 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3903 11:04:09.249500 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3904 11:04:09.252460 SELPH_MODE 0: By rank 1: By Phase
3905 11:04:09.259307 ==============================================================
3906 11:04:09.262395 GAT_TRACK_EN = 1
3907 11:04:09.266034 RX_GATING_MODE = 2
3908 11:04:09.269197 RX_GATING_TRACK_MODE = 2
3909 11:04:09.272612 SELPH_MODE = 1
3910 11:04:09.275852 PICG_EARLY_EN = 1
3911 11:04:09.279006 VALID_LAT_VALUE = 1
3912 11:04:09.282171 ==============================================================
3913 11:04:09.285761 Enter into Gating configuration >>>>
3914 11:04:09.289197 Exit from Gating configuration <<<<
3915 11:04:09.292202 Enter into DVFS_PRE_config >>>>>
3916 11:04:09.301992 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3917 11:04:09.305621 Exit from DVFS_PRE_config <<<<<
3918 11:04:09.309112 Enter into PICG configuration >>>>
3919 11:04:09.312511 Exit from PICG configuration <<<<
3920 11:04:09.315614 [RX_INPUT] configuration >>>>>
3921 11:04:09.319105 [RX_INPUT] configuration <<<<<
3922 11:04:09.325472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3923 11:04:09.329147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3924 11:04:09.335280 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3925 11:04:09.342167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3926 11:04:09.348939 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 11:04:09.355375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 11:04:09.358861 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3929 11:04:09.362338 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3930 11:04:09.365155 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3931 11:04:09.372260 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3932 11:04:09.375225 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3933 11:04:09.378336 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 11:04:09.381983 ===================================
3935 11:04:09.385766 LPDDR4 DRAM CONFIGURATION
3936 11:04:09.388576 ===================================
3937 11:04:09.388668 EX_ROW_EN[0] = 0x0
3938 11:04:09.391679 EX_ROW_EN[1] = 0x0
3939 11:04:09.395052 LP4Y_EN = 0x0
3940 11:04:09.395142 WORK_FSP = 0x0
3941 11:04:09.398284 WL = 0x2
3942 11:04:09.398372 RL = 0x2
3943 11:04:09.401824 BL = 0x2
3944 11:04:09.401914 RPST = 0x0
3945 11:04:09.404977 RD_PRE = 0x0
3946 11:04:09.405067 WR_PRE = 0x1
3947 11:04:09.408188 WR_PST = 0x0
3948 11:04:09.408279 DBI_WR = 0x0
3949 11:04:09.411497 DBI_RD = 0x0
3950 11:04:09.411590 OTF = 0x1
3951 11:04:09.415227 ===================================
3952 11:04:09.418175 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3953 11:04:09.425367 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3954 11:04:09.428343 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3955 11:04:09.431604 ===================================
3956 11:04:09.435031 LPDDR4 DRAM CONFIGURATION
3957 11:04:09.438365 ===================================
3958 11:04:09.438454 EX_ROW_EN[0] = 0x10
3959 11:04:09.441615 EX_ROW_EN[1] = 0x0
3960 11:04:09.444641 LP4Y_EN = 0x0
3961 11:04:09.444781 WORK_FSP = 0x0
3962 11:04:09.448084 WL = 0x2
3963 11:04:09.448159 RL = 0x2
3964 11:04:09.452015 BL = 0x2
3965 11:04:09.452091 RPST = 0x0
3966 11:04:09.454984 RD_PRE = 0x0
3967 11:04:09.455084 WR_PRE = 0x1
3968 11:04:09.458072 WR_PST = 0x0
3969 11:04:09.458190 DBI_WR = 0x0
3970 11:04:09.461510 DBI_RD = 0x0
3971 11:04:09.461586 OTF = 0x1
3972 11:04:09.464565 ===================================
3973 11:04:09.471034 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3974 11:04:09.475633 nWR fixed to 30
3975 11:04:09.479029 [ModeRegInit_LP4] CH0 RK0
3976 11:04:09.479104 [ModeRegInit_LP4] CH0 RK1
3977 11:04:09.481904 [ModeRegInit_LP4] CH1 RK0
3978 11:04:09.485531 [ModeRegInit_LP4] CH1 RK1
3979 11:04:09.485605 match AC timing 17
3980 11:04:09.492098 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3981 11:04:09.495352 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3982 11:04:09.498616 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3983 11:04:09.505013 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3984 11:04:09.508794 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3985 11:04:09.508869 ==
3986 11:04:09.512324 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 11:04:09.515371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 11:04:09.515446 ==
3989 11:04:09.521974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 11:04:09.528571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3991 11:04:09.531560 [CA 0] Center 37 (7~67) winsize 61
3992 11:04:09.535146 [CA 1] Center 36 (6~67) winsize 62
3993 11:04:09.538410 [CA 2] Center 35 (5~65) winsize 61
3994 11:04:09.541800 [CA 3] Center 35 (5~65) winsize 61
3995 11:04:09.545142 [CA 4] Center 34 (4~65) winsize 62
3996 11:04:09.548765 [CA 5] Center 34 (4~64) winsize 61
3997 11:04:09.548864
3998 11:04:09.551895 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3999 11:04:09.551970
4000 11:04:09.555045 [CATrainingPosCal] consider 1 rank data
4001 11:04:09.558634 u2DelayCellTimex100 = 270/100 ps
4002 11:04:09.561467 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4003 11:04:09.564992 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4004 11:04:09.568530 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4005 11:04:09.571481 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4006 11:04:09.575098 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4007 11:04:09.581766 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4008 11:04:09.581842
4009 11:04:09.584530 CA PerBit enable=1, Macro0, CA PI delay=34
4010 11:04:09.584608
4011 11:04:09.588152 [CBTSetCACLKResult] CA Dly = 34
4012 11:04:09.588228 CS Dly: 5 (0~36)
4013 11:04:09.588286 ==
4014 11:04:09.591238 Dram Type= 6, Freq= 0, CH_0, rank 1
4015 11:04:09.594861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 11:04:09.598095 ==
4017 11:04:09.601606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 11:04:09.608146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4019 11:04:09.611463 [CA 0] Center 37 (7~67) winsize 61
4020 11:04:09.614966 [CA 1] Center 36 (6~67) winsize 62
4021 11:04:09.618521 [CA 2] Center 35 (5~65) winsize 61
4022 11:04:09.621960 [CA 3] Center 35 (5~65) winsize 61
4023 11:04:09.624747 [CA 4] Center 34 (3~65) winsize 63
4024 11:04:09.627879 [CA 5] Center 33 (3~64) winsize 62
4025 11:04:09.627954
4026 11:04:09.631311 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4027 11:04:09.631417
4028 11:04:09.634937 [CATrainingPosCal] consider 2 rank data
4029 11:04:09.638018 u2DelayCellTimex100 = 270/100 ps
4030 11:04:09.641546 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4031 11:04:09.644717 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4032 11:04:09.648181 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4033 11:04:09.651166 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4034 11:04:09.658126 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4035 11:04:09.661044 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4036 11:04:09.661122
4037 11:04:09.664372 CA PerBit enable=1, Macro0, CA PI delay=34
4038 11:04:09.664448
4039 11:04:09.667872 [CBTSetCACLKResult] CA Dly = 34
4040 11:04:09.667947 CS Dly: 6 (0~38)
4041 11:04:09.668007
4042 11:04:09.671010 ----->DramcWriteLeveling(PI) begin...
4043 11:04:09.671087 ==
4044 11:04:09.674739 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 11:04:09.681661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 11:04:09.681741 ==
4047 11:04:09.684355 Write leveling (Byte 0): 33 => 33
4048 11:04:09.688044 Write leveling (Byte 1): 33 => 33
4049 11:04:09.688121 DramcWriteLeveling(PI) end<-----
4050 11:04:09.691465
4051 11:04:09.691541 ==
4052 11:04:09.694404 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 11:04:09.697664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 11:04:09.697741 ==
4055 11:04:09.701213 [Gating] SW mode calibration
4056 11:04:09.707693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4057 11:04:09.711334 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4058 11:04:09.717809 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 11:04:09.721116 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 11:04:09.724222 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 11:04:09.730874 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4062 11:04:09.734000 0 9 16 | B1->B0 | 2f2f 2929 | 1 0 | (1 1) (0 0)
4063 11:04:09.737514 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 11:04:09.744196 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 11:04:09.747839 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 11:04:09.750710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:04:09.757875 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:04:09.760838 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 11:04:09.764050 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4070 11:04:09.770963 0 10 16 | B1->B0 | 3232 3d3d | 0 1 | (1 1) (0 0)
4071 11:04:09.774254 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 11:04:09.777421 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 11:04:09.784272 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 11:04:09.787224 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:04:09.791082 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:04:09.797238 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 11:04:09.800586 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 11:04:09.804150 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4079 11:04:09.810940 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:04:09.813982 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:04:09.817445 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:04:09.820606 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:04:09.827174 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:04:09.830689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:04:09.833737 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:04:09.840468 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:04:09.843458 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:04:09.846881 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:04:09.853275 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:04:09.857172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:04:09.860267 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:04:09.866879 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 11:04:09.870368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4094 11:04:09.873508 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4095 11:04:09.876457 Total UI for P1: 0, mck2ui 16
4096 11:04:09.879927 best dqsien dly found for B0: ( 0, 13, 12)
4097 11:04:09.886498 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 11:04:09.889688 Total UI for P1: 0, mck2ui 16
4099 11:04:09.893277 best dqsien dly found for B1: ( 0, 13, 16)
4100 11:04:09.896489 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4101 11:04:09.899842 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4102 11:04:09.899920
4103 11:04:09.903583 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4104 11:04:09.906854 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4105 11:04:09.909694 [Gating] SW calibration Done
4106 11:04:09.909772 ==
4107 11:04:09.913274 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 11:04:09.916316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 11:04:09.916393 ==
4110 11:04:09.919810 RX Vref Scan: 0
4111 11:04:09.919887
4112 11:04:09.923333 RX Vref 0 -> 0, step: 1
4113 11:04:09.923459
4114 11:04:09.923570 RX Delay -230 -> 252, step: 16
4115 11:04:09.930143 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4116 11:04:09.933103 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4117 11:04:09.936775 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4118 11:04:09.939466 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4119 11:04:09.946198 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4120 11:04:09.949399 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4121 11:04:09.952896 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4122 11:04:09.956566 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4123 11:04:09.959747 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4124 11:04:09.966048 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4125 11:04:09.969605 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4126 11:04:09.973490 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4127 11:04:09.976200 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4128 11:04:09.982748 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4129 11:04:09.986196 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4130 11:04:09.989167 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4131 11:04:09.989276 ==
4132 11:04:09.992826 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 11:04:09.999266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 11:04:09.999376 ==
4135 11:04:09.999472 DQS Delay:
4136 11:04:09.999564 DQS0 = 0, DQS1 = 0
4137 11:04:10.002450 DQM Delay:
4138 11:04:10.002559 DQM0 = 39, DQM1 = 29
4139 11:04:10.005649 DQ Delay:
4140 11:04:10.009518 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =41
4141 11:04:10.012327 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4142 11:04:10.012432 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =25
4143 11:04:10.019086 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4144 11:04:10.019192
4145 11:04:10.019326
4146 11:04:10.019461 ==
4147 11:04:10.022474 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 11:04:10.025552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 11:04:10.025659 ==
4150 11:04:10.025755
4151 11:04:10.025852
4152 11:04:10.028889 TX Vref Scan disable
4153 11:04:10.028992 == TX Byte 0 ==
4154 11:04:10.035578 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4155 11:04:10.039134 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4156 11:04:10.039240 == TX Byte 1 ==
4157 11:04:10.046024 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4158 11:04:10.048773 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4159 11:04:10.048900 ==
4160 11:04:10.051930 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 11:04:10.055533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 11:04:10.055641 ==
4163 11:04:10.055735
4164 11:04:10.059047
4165 11:04:10.059153 TX Vref Scan disable
4166 11:04:10.061901 == TX Byte 0 ==
4167 11:04:10.065342 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4168 11:04:10.072071 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4169 11:04:10.072192 == TX Byte 1 ==
4170 11:04:10.075269 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4171 11:04:10.082051 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4172 11:04:10.082212
4173 11:04:10.082325 [DATLAT]
4174 11:04:10.082429 Freq=600, CH0 RK0
4175 11:04:10.082533
4176 11:04:10.085467 DATLAT Default: 0x9
4177 11:04:10.085587 0, 0xFFFF, sum = 0
4178 11:04:10.088755 1, 0xFFFF, sum = 0
4179 11:04:10.092038 2, 0xFFFF, sum = 0
4180 11:04:10.092170 3, 0xFFFF, sum = 0
4181 11:04:10.095353 4, 0xFFFF, sum = 0
4182 11:04:10.095498 5, 0xFFFF, sum = 0
4183 11:04:10.098930 6, 0xFFFF, sum = 0
4184 11:04:10.099051 7, 0xFFFF, sum = 0
4185 11:04:10.101868 8, 0x0, sum = 1
4186 11:04:10.101989 9, 0x0, sum = 2
4187 11:04:10.102097 10, 0x0, sum = 3
4188 11:04:10.105517 11, 0x0, sum = 4
4189 11:04:10.105638 best_step = 9
4190 11:04:10.105747
4191 11:04:10.105852 ==
4192 11:04:10.108865 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 11:04:10.115095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 11:04:10.115217 ==
4195 11:04:10.115327 RX Vref Scan: 1
4196 11:04:10.115431
4197 11:04:10.118526 RX Vref 0 -> 0, step: 1
4198 11:04:10.118645
4199 11:04:10.121780 RX Delay -195 -> 252, step: 8
4200 11:04:10.121901
4201 11:04:10.124940 Set Vref, RX VrefLevel [Byte0]: 60
4202 11:04:10.128240 [Byte1]: 49
4203 11:04:10.128411
4204 11:04:10.131840 Final RX Vref Byte 0 = 60 to rank0
4205 11:04:10.134810 Final RX Vref Byte 1 = 49 to rank0
4206 11:04:10.138184 Final RX Vref Byte 0 = 60 to rank1
4207 11:04:10.141394 Final RX Vref Byte 1 = 49 to rank1==
4208 11:04:10.144923 Dram Type= 6, Freq= 0, CH_0, rank 0
4209 11:04:10.148590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 11:04:10.148722 ==
4211 11:04:10.151451 DQS Delay:
4212 11:04:10.151573 DQS0 = 0, DQS1 = 0
4213 11:04:10.154693 DQM Delay:
4214 11:04:10.154821 DQM0 = 35, DQM1 = 29
4215 11:04:10.154927 DQ Delay:
4216 11:04:10.158382 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4217 11:04:10.161354 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4218 11:04:10.164893 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4219 11:04:10.168601 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4220 11:04:10.168724
4221 11:04:10.168834
4222 11:04:10.178355 [DQSOSCAuto] RK0, (LSB)MR18= 0x4342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4223 11:04:10.181784 CH0 RK0: MR19=808, MR18=4342
4224 11:04:10.188121 CH0_RK0: MR19=0x808, MR18=0x4342, DQSOSC=397, MR23=63, INC=166, DEC=110
4225 11:04:10.188224
4226 11:04:10.191672 ----->DramcWriteLeveling(PI) begin...
4227 11:04:10.191775 ==
4228 11:04:10.195266 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 11:04:10.198266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 11:04:10.198367 ==
4231 11:04:10.201377 Write leveling (Byte 0): 32 => 32
4232 11:04:10.204816 Write leveling (Byte 1): 32 => 32
4233 11:04:10.208489 DramcWriteLeveling(PI) end<-----
4234 11:04:10.208587
4235 11:04:10.208672 ==
4236 11:04:10.211407 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 11:04:10.214772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 11:04:10.214874 ==
4239 11:04:10.218619 [Gating] SW mode calibration
4240 11:04:10.224405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4241 11:04:10.231173 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4242 11:04:10.234386 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 11:04:10.238138 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 11:04:10.244571 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 11:04:10.248349 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4246 11:04:10.251010 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4247 11:04:10.257770 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 11:04:10.261527 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 11:04:10.264509 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 11:04:10.271212 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:04:10.274152 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 11:04:10.277589 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 11:04:10.284321 0 10 12 | B1->B0 | 2828 3535 | 1 0 | (0 0) (0 0)
4254 11:04:10.287261 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4255 11:04:10.290842 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:04:10.297485 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:04:10.300539 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 11:04:10.304046 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:04:10.310446 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:04:10.313880 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 11:04:10.317541 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4262 11:04:10.323840 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:04:10.327309 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:04:10.330454 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:04:10.336990 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:04:10.340476 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:04:10.343629 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:04:10.350471 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:04:10.353714 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:04:10.357097 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:04:10.363860 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:04:10.366960 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:04:10.370346 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:04:10.373536 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:04:10.379880 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 11:04:10.384182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:04:10.387083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4278 11:04:10.393743 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4279 11:04:10.396719 Total UI for P1: 0, mck2ui 16
4280 11:04:10.400235 best dqsien dly found for B0: ( 0, 13, 12)
4281 11:04:10.403344 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 11:04:10.406924 Total UI for P1: 0, mck2ui 16
4283 11:04:10.409941 best dqsien dly found for B1: ( 0, 13, 18)
4284 11:04:10.413540 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4285 11:04:10.416567 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4286 11:04:10.416642
4287 11:04:10.419592 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4288 11:04:10.426560 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4289 11:04:10.426636 [Gating] SW calibration Done
4290 11:04:10.426694 ==
4291 11:04:10.429995 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 11:04:10.436284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 11:04:10.436360 ==
4294 11:04:10.436417 RX Vref Scan: 0
4295 11:04:10.436471
4296 11:04:10.439908 RX Vref 0 -> 0, step: 1
4297 11:04:10.439983
4298 11:04:10.443165 RX Delay -230 -> 252, step: 16
4299 11:04:10.446324 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4300 11:04:10.449267 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4301 11:04:10.455994 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4302 11:04:10.459488 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4303 11:04:10.462594 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4304 11:04:10.465897 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4305 11:04:10.469338 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4306 11:04:10.475738 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4307 11:04:10.479053 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4308 11:04:10.482400 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4309 11:04:10.485750 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4310 11:04:10.492169 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4311 11:04:10.495884 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4312 11:04:10.499238 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4313 11:04:10.502322 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4314 11:04:10.508878 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4315 11:04:10.508978 ==
4316 11:04:10.512481 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 11:04:10.516227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 11:04:10.516334 ==
4319 11:04:10.516429 DQS Delay:
4320 11:04:10.519095 DQS0 = 0, DQS1 = 0
4321 11:04:10.519200 DQM Delay:
4322 11:04:10.522557 DQM0 = 33, DQM1 = 26
4323 11:04:10.522662 DQ Delay:
4324 11:04:10.525252 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4325 11:04:10.528574 DQ4 =33, DQ5 =17, DQ6 =41, DQ7 =41
4326 11:04:10.532041 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4327 11:04:10.535638 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4328 11:04:10.535744
4329 11:04:10.535838
4330 11:04:10.535926 ==
4331 11:04:10.538774 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 11:04:10.542284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 11:04:10.542390 ==
4334 11:04:10.545174
4335 11:04:10.545276
4336 11:04:10.545370 TX Vref Scan disable
4337 11:04:10.548795 == TX Byte 0 ==
4338 11:04:10.552291 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4339 11:04:10.555183 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4340 11:04:10.558495 == TX Byte 1 ==
4341 11:04:10.561826 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4342 11:04:10.565333 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4343 11:04:10.565438 ==
4344 11:04:10.568508 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 11:04:10.575370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 11:04:10.575476 ==
4347 11:04:10.575571
4348 11:04:10.575663
4349 11:04:10.578705 TX Vref Scan disable
4350 11:04:10.578809 == TX Byte 0 ==
4351 11:04:10.585201 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4352 11:04:10.588380 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4353 11:04:10.588493 == TX Byte 1 ==
4354 11:04:10.594828 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4355 11:04:10.598421 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4356 11:04:10.598542
4357 11:04:10.598645 [DATLAT]
4358 11:04:10.601637 Freq=600, CH0 RK1
4359 11:04:10.601748
4360 11:04:10.601848 DATLAT Default: 0x9
4361 11:04:10.605140 0, 0xFFFF, sum = 0
4362 11:04:10.605251 1, 0xFFFF, sum = 0
4363 11:04:10.608319 2, 0xFFFF, sum = 0
4364 11:04:10.608428 3, 0xFFFF, sum = 0
4365 11:04:10.611653 4, 0xFFFF, sum = 0
4366 11:04:10.611768 5, 0xFFFF, sum = 0
4367 11:04:10.615094 6, 0xFFFF, sum = 0
4368 11:04:10.618044 7, 0xFFFF, sum = 0
4369 11:04:10.618174 8, 0x0, sum = 1
4370 11:04:10.618269 9, 0x0, sum = 2
4371 11:04:10.621747 10, 0x0, sum = 3
4372 11:04:10.621862 11, 0x0, sum = 4
4373 11:04:10.624766 best_step = 9
4374 11:04:10.624879
4375 11:04:10.624968 ==
4376 11:04:10.628404 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 11:04:10.631573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 11:04:10.631673 ==
4379 11:04:10.635204 RX Vref Scan: 0
4380 11:04:10.635303
4381 11:04:10.635389 RX Vref 0 -> 0, step: 1
4382 11:04:10.635481
4383 11:04:10.637992 RX Delay -195 -> 252, step: 8
4384 11:04:10.645152 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4385 11:04:10.648971 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4386 11:04:10.651781 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4387 11:04:10.655648 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4388 11:04:10.662131 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4389 11:04:10.664915 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4390 11:04:10.668879 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4391 11:04:10.671975 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4392 11:04:10.675122 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4393 11:04:10.681578 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4394 11:04:10.685167 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4395 11:04:10.688376 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4396 11:04:10.691522 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4397 11:04:10.698212 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4398 11:04:10.701250 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4399 11:04:10.704991 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4400 11:04:10.705095 ==
4401 11:04:10.707901 Dram Type= 6, Freq= 0, CH_0, rank 1
4402 11:04:10.715081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 11:04:10.715187 ==
4404 11:04:10.715278 DQS Delay:
4405 11:04:10.715366 DQS0 = 0, DQS1 = 0
4406 11:04:10.718059 DQM Delay:
4407 11:04:10.718167 DQM0 = 33, DQM1 = 28
4408 11:04:10.721294 DQ Delay:
4409 11:04:10.725073 DQ0 =32, DQ1 =36, DQ2 =28, DQ3 =28
4410 11:04:10.728000 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4411 11:04:10.728082 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4412 11:04:10.734907 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4413 11:04:10.734982
4414 11:04:10.735040
4415 11:04:10.741420 [DQSOSCAuto] RK1, (LSB)MR18= 0x7443, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4416 11:04:10.744907 CH0 RK1: MR19=808, MR18=7443
4417 11:04:10.751381 CH0_RK1: MR19=0x808, MR18=0x7443, DQSOSC=388, MR23=63, INC=174, DEC=116
4418 11:04:10.754360 [RxdqsGatingPostProcess] freq 600
4419 11:04:10.758015 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4420 11:04:10.761022 Pre-setting of DQS Precalculation
4421 11:04:10.767800 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4422 11:04:10.767875 ==
4423 11:04:10.770917 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 11:04:10.774544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 11:04:10.774620 ==
4426 11:04:10.780798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 11:04:10.787544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4428 11:04:10.790642 [CA 0] Center 35 (5~66) winsize 62
4429 11:04:10.794068 [CA 1] Center 36 (6~66) winsize 61
4430 11:04:10.797525 [CA 2] Center 34 (4~65) winsize 62
4431 11:04:10.801054 [CA 3] Center 34 (4~65) winsize 62
4432 11:04:10.804020 [CA 4] Center 34 (4~65) winsize 62
4433 11:04:10.807487 [CA 5] Center 33 (3~64) winsize 62
4434 11:04:10.807589
4435 11:04:10.810416 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4436 11:04:10.810519
4437 11:04:10.814022 [CATrainingPosCal] consider 1 rank data
4438 11:04:10.817600 u2DelayCellTimex100 = 270/100 ps
4439 11:04:10.820366 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 11:04:10.823839 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4441 11:04:10.827424 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 11:04:10.830775 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 11:04:10.833788 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 11:04:10.837172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 11:04:10.837273
4446 11:04:10.843819 CA PerBit enable=1, Macro0, CA PI delay=33
4447 11:04:10.843920
4448 11:04:10.844014 [CBTSetCACLKResult] CA Dly = 33
4449 11:04:10.846809 CS Dly: 4 (0~35)
4450 11:04:10.846911 ==
4451 11:04:10.850548 Dram Type= 6, Freq= 0, CH_1, rank 1
4452 11:04:10.853450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 11:04:10.853554 ==
4454 11:04:10.860509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4455 11:04:10.866706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4456 11:04:10.870036 [CA 0] Center 35 (5~66) winsize 62
4457 11:04:10.873857 [CA 1] Center 35 (5~66) winsize 62
4458 11:04:10.876635 [CA 2] Center 34 (4~65) winsize 62
4459 11:04:10.879816 [CA 3] Center 34 (3~65) winsize 63
4460 11:04:10.883444 [CA 4] Center 34 (4~65) winsize 62
4461 11:04:10.887138 [CA 5] Center 34 (3~65) winsize 63
4462 11:04:10.887214
4463 11:04:10.889888 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4464 11:04:10.889964
4465 11:04:10.893543 [CATrainingPosCal] consider 2 rank data
4466 11:04:10.896865 u2DelayCellTimex100 = 270/100 ps
4467 11:04:10.899820 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 11:04:10.903534 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4469 11:04:10.907004 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 11:04:10.910347 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 11:04:10.913166 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4472 11:04:10.916660 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4473 11:04:10.919902
4474 11:04:10.922997 CA PerBit enable=1, Macro0, CA PI delay=33
4475 11:04:10.923100
4476 11:04:10.926909 [CBTSetCACLKResult] CA Dly = 33
4477 11:04:10.927010 CS Dly: 4 (0~36)
4478 11:04:10.927099
4479 11:04:10.929786 ----->DramcWriteLeveling(PI) begin...
4480 11:04:10.929899 ==
4481 11:04:10.933121 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 11:04:10.936298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 11:04:10.939523 ==
4484 11:04:10.939627 Write leveling (Byte 0): 29 => 29
4485 11:04:10.943043 Write leveling (Byte 1): 29 => 29
4486 11:04:10.946266 DramcWriteLeveling(PI) end<-----
4487 11:04:10.946369
4488 11:04:10.946458 ==
4489 11:04:10.949690 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 11:04:10.956205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 11:04:10.956325 ==
4492 11:04:10.959819 [Gating] SW mode calibration
4493 11:04:10.966689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4494 11:04:10.969723 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4495 11:04:10.976672 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 11:04:10.979721 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 11:04:10.982659 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4498 11:04:10.989613 0 9 12 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
4499 11:04:10.992571 0 9 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4500 11:04:10.996299 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 11:04:10.999206 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 11:04:11.005862 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 11:04:11.009840 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:04:11.012417 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 11:04:11.019242 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 11:04:11.022871 0 10 12 | B1->B0 | 2d2d 2f2f | 0 0 | (0 0) (0 0)
4507 11:04:11.025792 0 10 16 | B1->B0 | 4242 4444 | 0 0 | (0 0) (1 1)
4508 11:04:11.032197 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 11:04:11.035616 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:04:11.039323 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:04:11.046125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:04:11.048763 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:04:11.052160 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 11:04:11.058716 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4515 11:04:11.062164 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4516 11:04:11.065882 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:04:11.072297 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:04:11.075343 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:04:11.078872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:04:11.085246 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:04:11.088949 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:04:11.092456 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:04:11.099037 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:04:11.102216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:04:11.105313 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:04:11.112237 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:04:11.115646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:04:11.118833 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 11:04:11.125543 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 11:04:11.128790 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4531 11:04:11.132450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4532 11:04:11.135340 Total UI for P1: 0, mck2ui 16
4533 11:04:11.138517 best dqsien dly found for B0: ( 0, 13, 12)
4534 11:04:11.145235 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 11:04:11.145310 Total UI for P1: 0, mck2ui 16
4536 11:04:11.148940 best dqsien dly found for B1: ( 0, 13, 16)
4537 11:04:11.155298 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4538 11:04:11.158706 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4539 11:04:11.158780
4540 11:04:11.162078 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4541 11:04:11.165318 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4542 11:04:11.168731 [Gating] SW calibration Done
4543 11:04:11.168806 ==
4544 11:04:11.171998 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 11:04:11.175454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 11:04:11.175530 ==
4547 11:04:11.178808 RX Vref Scan: 0
4548 11:04:11.178883
4549 11:04:11.178940 RX Vref 0 -> 0, step: 1
4550 11:04:11.178993
4551 11:04:11.181987 RX Delay -230 -> 252, step: 16
4552 11:04:11.185246 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4553 11:04:11.192131 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4554 11:04:11.195135 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4555 11:04:11.198469 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4556 11:04:11.201913 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4557 11:04:11.208772 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4558 11:04:11.212167 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4559 11:04:11.215319 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4560 11:04:11.218628 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4561 11:04:11.221459 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4562 11:04:11.228742 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4563 11:04:11.231930 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4564 11:04:11.235308 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4565 11:04:11.238273 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4566 11:04:11.245286 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4567 11:04:11.248314 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4568 11:04:11.248390 ==
4569 11:04:11.251334 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 11:04:11.255011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 11:04:11.255088 ==
4572 11:04:11.258054 DQS Delay:
4573 11:04:11.258169 DQS0 = 0, DQS1 = 0
4574 11:04:11.258229 DQM Delay:
4575 11:04:11.261775 DQM0 = 36, DQM1 = 28
4576 11:04:11.261855 DQ Delay:
4577 11:04:11.264864 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4578 11:04:11.267811 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4579 11:04:11.271379 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4580 11:04:11.275060 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4581 11:04:11.275136
4582 11:04:11.275194
4583 11:04:11.275247 ==
4584 11:04:11.277963 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 11:04:11.284510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 11:04:11.284588 ==
4587 11:04:11.284647
4588 11:04:11.284701
4589 11:04:11.284752 TX Vref Scan disable
4590 11:04:11.288561 == TX Byte 0 ==
4591 11:04:11.292445 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4592 11:04:11.295343 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4593 11:04:11.299006 == TX Byte 1 ==
4594 11:04:11.301948 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4595 11:04:11.308460 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4596 11:04:11.308537 ==
4597 11:04:11.311649 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 11:04:11.314761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 11:04:11.314862 ==
4600 11:04:11.314946
4601 11:04:11.315026
4602 11:04:11.318184 TX Vref Scan disable
4603 11:04:11.321899 == TX Byte 0 ==
4604 11:04:11.325473 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4605 11:04:11.328278 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4606 11:04:11.331739 == TX Byte 1 ==
4607 11:04:11.334811 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4608 11:04:11.338130 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4609 11:04:11.338220
4610 11:04:11.338279 [DATLAT]
4611 11:04:11.341609 Freq=600, CH1 RK0
4612 11:04:11.341696
4613 11:04:11.344652 DATLAT Default: 0x9
4614 11:04:11.344741 0, 0xFFFF, sum = 0
4615 11:04:11.348181 1, 0xFFFF, sum = 0
4616 11:04:11.348276 2, 0xFFFF, sum = 0
4617 11:04:11.351273 3, 0xFFFF, sum = 0
4618 11:04:11.351342 4, 0xFFFF, sum = 0
4619 11:04:11.354540 5, 0xFFFF, sum = 0
4620 11:04:11.354610 6, 0xFFFF, sum = 0
4621 11:04:11.357882 7, 0xFFFF, sum = 0
4622 11:04:11.357973 8, 0x0, sum = 1
4623 11:04:11.361316 9, 0x0, sum = 2
4624 11:04:11.361394 10, 0x0, sum = 3
4625 11:04:11.364341 11, 0x0, sum = 4
4626 11:04:11.364405 best_step = 9
4627 11:04:11.364458
4628 11:04:11.364529 ==
4629 11:04:11.368063 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 11:04:11.371341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 11:04:11.371402 ==
4632 11:04:11.374748 RX Vref Scan: 1
4633 11:04:11.374807
4634 11:04:11.377740 RX Vref 0 -> 0, step: 1
4635 11:04:11.377805
4636 11:04:11.377856 RX Delay -195 -> 252, step: 8
4637 11:04:11.377906
4638 11:04:11.381367 Set Vref, RX VrefLevel [Byte0]: 55
4639 11:04:11.384683 [Byte1]: 51
4640 11:04:11.388915
4641 11:04:11.388978 Final RX Vref Byte 0 = 55 to rank0
4642 11:04:11.392603 Final RX Vref Byte 1 = 51 to rank0
4643 11:04:11.395672 Final RX Vref Byte 0 = 55 to rank1
4644 11:04:11.398748 Final RX Vref Byte 1 = 51 to rank1==
4645 11:04:11.402253 Dram Type= 6, Freq= 0, CH_1, rank 0
4646 11:04:11.409109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 11:04:11.409176 ==
4648 11:04:11.409232 DQS Delay:
4649 11:04:11.409284 DQS0 = 0, DQS1 = 0
4650 11:04:11.412433 DQM Delay:
4651 11:04:11.412525 DQM0 = 39, DQM1 = 28
4652 11:04:11.415772 DQ Delay:
4653 11:04:11.419110 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4654 11:04:11.422091 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4655 11:04:11.425836 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4656 11:04:11.429235 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4657 11:04:11.429306
4658 11:04:11.429362
4659 11:04:11.435639 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 400 ps
4660 11:04:11.438517 CH1 RK0: MR19=808, MR18=2F3C
4661 11:04:11.445133 CH1_RK0: MR19=0x808, MR18=0x2F3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4662 11:04:11.445204
4663 11:04:11.448617 ----->DramcWriteLeveling(PI) begin...
4664 11:04:11.448681 ==
4665 11:04:11.452364 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 11:04:11.455461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 11:04:11.455582 ==
4668 11:04:11.459201 Write leveling (Byte 0): 33 => 33
4669 11:04:11.461762 Write leveling (Byte 1): 32 => 32
4670 11:04:11.465354 DramcWriteLeveling(PI) end<-----
4671 11:04:11.465425
4672 11:04:11.465482 ==
4673 11:04:11.468406 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 11:04:11.471468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 11:04:11.471536 ==
4676 11:04:11.474951 [Gating] SW mode calibration
4677 11:04:11.481994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4678 11:04:11.488444 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4679 11:04:11.491605 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 11:04:11.498457 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 11:04:11.501349 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
4682 11:04:11.504874 0 9 12 | B1->B0 | 3030 2d2d | 0 0 | (1 1) (1 1)
4683 11:04:11.511307 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4684 11:04:11.515001 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 11:04:11.517984 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 11:04:11.525187 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 11:04:11.528366 0 10 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4688 11:04:11.531256 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 11:04:11.538181 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4690 11:04:11.541185 0 10 12 | B1->B0 | 3131 4040 | 1 0 | (0 0) (0 0)
4691 11:04:11.544824 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4692 11:04:11.548161 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 11:04:11.554826 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 11:04:11.558033 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:04:11.561429 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 11:04:11.568231 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 11:04:11.571218 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 11:04:11.574832 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:04:11.581065 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:04:11.584295 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:04:11.588291 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:04:11.594624 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:04:11.597571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:04:11.601259 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:04:11.607921 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:04:11.611750 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:04:11.614534 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:04:11.621126 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:04:11.624839 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:04:11.627709 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:04:11.634814 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 11:04:11.637866 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 11:04:11.641040 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 11:04:11.647684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4715 11:04:11.647761 Total UI for P1: 0, mck2ui 16
4716 11:04:11.654270 best dqsien dly found for B0: ( 0, 13, 10)
4717 11:04:11.657709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4718 11:04:11.661392 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 11:04:11.664280 Total UI for P1: 0, mck2ui 16
4720 11:04:11.667536 best dqsien dly found for B1: ( 0, 13, 14)
4721 11:04:11.670940 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4722 11:04:11.674363 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4723 11:04:11.674439
4724 11:04:11.677710 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4725 11:04:11.684395 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4726 11:04:11.684472 [Gating] SW calibration Done
4727 11:04:11.687451 ==
4728 11:04:11.687527 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 11:04:11.694410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 11:04:11.694486 ==
4731 11:04:11.694545 RX Vref Scan: 0
4732 11:04:11.694599
4733 11:04:11.697734 RX Vref 0 -> 0, step: 1
4734 11:04:11.697809
4735 11:04:11.701132 RX Delay -230 -> 252, step: 16
4736 11:04:11.704336 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4737 11:04:11.707367 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4738 11:04:11.714073 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4739 11:04:11.717878 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4740 11:04:11.720876 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4741 11:04:11.724543 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4742 11:04:11.727653 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4743 11:04:11.734109 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4744 11:04:11.737853 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4745 11:04:11.740730 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4746 11:04:11.744176 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4747 11:04:11.751052 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4748 11:04:11.753899 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4749 11:04:11.757166 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4750 11:04:11.760482 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4751 11:04:11.767470 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4752 11:04:11.767547 ==
4753 11:04:11.770414 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 11:04:11.773917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 11:04:11.773993 ==
4756 11:04:11.774052 DQS Delay:
4757 11:04:11.777413 DQS0 = 0, DQS1 = 0
4758 11:04:11.777488 DQM Delay:
4759 11:04:11.780464 DQM0 = 35, DQM1 = 30
4760 11:04:11.780540 DQ Delay:
4761 11:04:11.784057 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4762 11:04:11.787120 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4763 11:04:11.790691 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4764 11:04:11.793612 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4765 11:04:11.793687
4766 11:04:11.793744
4767 11:04:11.793797 ==
4768 11:04:11.797121 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 11:04:11.800385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 11:04:11.800461 ==
4771 11:04:11.800519
4772 11:04:11.803564
4773 11:04:11.803640 TX Vref Scan disable
4774 11:04:11.806941 == TX Byte 0 ==
4775 11:04:11.810361 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4776 11:04:11.813620 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4777 11:04:11.816883 == TX Byte 1 ==
4778 11:04:11.820314 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4779 11:04:11.823835 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4780 11:04:11.823910 ==
4781 11:04:11.827285 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 11:04:11.833811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 11:04:11.833888 ==
4784 11:04:11.833947
4785 11:04:11.834000
4786 11:04:11.834050 TX Vref Scan disable
4787 11:04:11.838016 == TX Byte 0 ==
4788 11:04:11.841296 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4789 11:04:11.844626 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4790 11:04:11.847860 == TX Byte 1 ==
4791 11:04:11.851554 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4792 11:04:11.854903 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4793 11:04:11.858003
4794 11:04:11.858125 [DATLAT]
4795 11:04:11.858217 Freq=600, CH1 RK1
4796 11:04:11.858287
4797 11:04:11.861420 DATLAT Default: 0x9
4798 11:04:11.861495 0, 0xFFFF, sum = 0
4799 11:04:11.864944 1, 0xFFFF, sum = 0
4800 11:04:11.865021 2, 0xFFFF, sum = 0
4801 11:04:11.867852 3, 0xFFFF, sum = 0
4802 11:04:11.867929 4, 0xFFFF, sum = 0
4803 11:04:11.871417 5, 0xFFFF, sum = 0
4804 11:04:11.874896 6, 0xFFFF, sum = 0
4805 11:04:11.874973 7, 0xFFFF, sum = 0
4806 11:04:11.877774 8, 0x0, sum = 1
4807 11:04:11.877851 9, 0x0, sum = 2
4808 11:04:11.877909 10, 0x0, sum = 3
4809 11:04:11.881116 11, 0x0, sum = 4
4810 11:04:11.881193 best_step = 9
4811 11:04:11.881251
4812 11:04:11.881304 ==
4813 11:04:11.884272 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 11:04:11.891711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 11:04:11.891788 ==
4816 11:04:11.891846 RX Vref Scan: 0
4817 11:04:11.891900
4818 11:04:11.894567 RX Vref 0 -> 0, step: 1
4819 11:04:11.894642
4820 11:04:11.897721 RX Delay -195 -> 252, step: 8
4821 11:04:11.901007 iDelay=205, Bit 0, Center 36 (-123 ~ 196) 320
4822 11:04:11.907963 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4823 11:04:11.910880 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4824 11:04:11.914353 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4825 11:04:11.917847 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4826 11:04:11.924497 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4827 11:04:11.927747 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4828 11:04:11.930913 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4829 11:04:11.934211 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4830 11:04:11.937562 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4831 11:04:11.944091 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4832 11:04:11.947886 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4833 11:04:11.950983 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4834 11:04:11.954296 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4835 11:04:11.960801 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4836 11:04:11.964555 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4837 11:04:11.964631 ==
4838 11:04:11.967478 Dram Type= 6, Freq= 0, CH_1, rank 1
4839 11:04:11.971076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4840 11:04:11.971153 ==
4841 11:04:11.974497 DQS Delay:
4842 11:04:11.974572 DQS0 = 0, DQS1 = 0
4843 11:04:11.974631 DQM Delay:
4844 11:04:11.977200 DQM0 = 36, DQM1 = 30
4845 11:04:11.977275 DQ Delay:
4846 11:04:11.980694 DQ0 =36, DQ1 =32, DQ2 =24, DQ3 =32
4847 11:04:11.984101 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4848 11:04:11.987276 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4849 11:04:11.990944 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4850 11:04:11.991020
4851 11:04:11.991078
4852 11:04:12.000992 [DQSOSCAuto] RK1, (LSB)MR18= 0x4465, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 396 ps
4853 11:04:12.001069 CH1 RK1: MR19=808, MR18=4465
4854 11:04:12.007602 CH1_RK1: MR19=0x808, MR18=0x4465, DQSOSC=390, MR23=63, INC=172, DEC=114
4855 11:04:12.010748 [RxdqsGatingPostProcess] freq 600
4856 11:04:12.017719 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4857 11:04:12.020425 Pre-setting of DQS Precalculation
4858 11:04:12.024115 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4859 11:04:12.030619 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4860 11:04:12.040704 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4861 11:04:12.040778
4862 11:04:12.040835
4863 11:04:12.043727 [Calibration Summary] 1200 Mbps
4864 11:04:12.043801 CH 0, Rank 0
4865 11:04:12.047087 SW Impedance : PASS
4866 11:04:12.047161 DUTY Scan : NO K
4867 11:04:12.050738 ZQ Calibration : PASS
4868 11:04:12.053667 Jitter Meter : NO K
4869 11:04:12.053742 CBT Training : PASS
4870 11:04:12.057265 Write leveling : PASS
4871 11:04:12.057341 RX DQS gating : PASS
4872 11:04:12.060413 RX DQ/DQS(RDDQC) : PASS
4873 11:04:12.063676 TX DQ/DQS : PASS
4874 11:04:12.063753 RX DATLAT : PASS
4875 11:04:12.067604 RX DQ/DQS(Engine): PASS
4876 11:04:12.070340 TX OE : NO K
4877 11:04:12.070415 All Pass.
4878 11:04:12.070473
4879 11:04:12.070527 CH 0, Rank 1
4880 11:04:12.073562 SW Impedance : PASS
4881 11:04:12.077216 DUTY Scan : NO K
4882 11:04:12.077293 ZQ Calibration : PASS
4883 11:04:12.080956 Jitter Meter : NO K
4884 11:04:12.083536 CBT Training : PASS
4885 11:04:12.083611 Write leveling : PASS
4886 11:04:12.087261 RX DQS gating : PASS
4887 11:04:12.090379 RX DQ/DQS(RDDQC) : PASS
4888 11:04:12.090454 TX DQ/DQS : PASS
4889 11:04:12.094047 RX DATLAT : PASS
4890 11:04:12.096884 RX DQ/DQS(Engine): PASS
4891 11:04:12.096959 TX OE : NO K
4892 11:04:12.097018 All Pass.
4893 11:04:12.100179
4894 11:04:12.100254 CH 1, Rank 0
4895 11:04:12.103686 SW Impedance : PASS
4896 11:04:12.103762 DUTY Scan : NO K
4897 11:04:12.106960 ZQ Calibration : PASS
4898 11:04:12.107036 Jitter Meter : NO K
4899 11:04:12.110222 CBT Training : PASS
4900 11:04:12.113837 Write leveling : PASS
4901 11:04:12.113912 RX DQS gating : PASS
4902 11:04:12.116852 RX DQ/DQS(RDDQC) : PASS
4903 11:04:12.120442 TX DQ/DQS : PASS
4904 11:04:12.120518 RX DATLAT : PASS
4905 11:04:12.124186 RX DQ/DQS(Engine): PASS
4906 11:04:12.126964 TX OE : NO K
4907 11:04:12.127039 All Pass.
4908 11:04:12.127098
4909 11:04:12.127151 CH 1, Rank 1
4910 11:04:12.130037 SW Impedance : PASS
4911 11:04:12.133686 DUTY Scan : NO K
4912 11:04:12.133760 ZQ Calibration : PASS
4913 11:04:12.136863 Jitter Meter : NO K
4914 11:04:12.140327 CBT Training : PASS
4915 11:04:12.140402 Write leveling : PASS
4916 11:04:12.143270 RX DQS gating : PASS
4917 11:04:12.146749 RX DQ/DQS(RDDQC) : PASS
4918 11:04:12.146890 TX DQ/DQS : PASS
4919 11:04:12.150080 RX DATLAT : PASS
4920 11:04:12.153283 RX DQ/DQS(Engine): PASS
4921 11:04:12.153348 TX OE : NO K
4922 11:04:12.153411 All Pass.
4923 11:04:12.156612
4924 11:04:12.156676 DramC Write-DBI off
4925 11:04:12.160014 PER_BANK_REFRESH: Hybrid Mode
4926 11:04:12.160081 TX_TRACKING: ON
4927 11:04:12.170211 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4928 11:04:12.173481 [FAST_K] Save calibration result to emmc
4929 11:04:12.176951 dramc_set_vcore_voltage set vcore to 662500
4930 11:04:12.180172 Read voltage for 933, 3
4931 11:04:12.180239 Vio18 = 0
4932 11:04:12.183070 Vcore = 662500
4933 11:04:12.183156 Vdram = 0
4934 11:04:12.183235 Vddq = 0
4935 11:04:12.183313 Vmddr = 0
4936 11:04:12.190376 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4937 11:04:12.196505 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4938 11:04:12.196583 MEM_TYPE=3, freq_sel=17
4939 11:04:12.199875 sv_algorithm_assistance_LP4_1600
4940 11:04:12.202832 ============ PULL DRAM RESETB DOWN ============
4941 11:04:12.209796 ========== PULL DRAM RESETB DOWN end =========
4942 11:04:12.212872 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4943 11:04:12.216272 ===================================
4944 11:04:12.219611 LPDDR4 DRAM CONFIGURATION
4945 11:04:12.223186 ===================================
4946 11:04:12.223253 EX_ROW_EN[0] = 0x0
4947 11:04:12.226043 EX_ROW_EN[1] = 0x0
4948 11:04:12.226138 LP4Y_EN = 0x0
4949 11:04:12.229558 WORK_FSP = 0x0
4950 11:04:12.229621 WL = 0x3
4951 11:04:12.233061 RL = 0x3
4952 11:04:12.236210 BL = 0x2
4953 11:04:12.236268 RPST = 0x0
4954 11:04:12.239820 RD_PRE = 0x0
4955 11:04:12.239878 WR_PRE = 0x1
4956 11:04:12.242950 WR_PST = 0x0
4957 11:04:12.243009 DBI_WR = 0x0
4958 11:04:12.246126 DBI_RD = 0x0
4959 11:04:12.246185 OTF = 0x1
4960 11:04:12.249168 ===================================
4961 11:04:12.252581 ===================================
4962 11:04:12.255726 ANA top config
4963 11:04:12.259448 ===================================
4964 11:04:12.259513 DLL_ASYNC_EN = 0
4965 11:04:12.262721 ALL_SLAVE_EN = 1
4966 11:04:12.265826 NEW_RANK_MODE = 1
4967 11:04:12.269372 DLL_IDLE_MODE = 1
4968 11:04:12.269436 LP45_APHY_COMB_EN = 1
4969 11:04:12.272437 TX_ODT_DIS = 1
4970 11:04:12.275921 NEW_8X_MODE = 1
4971 11:04:12.279025 ===================================
4972 11:04:12.282425 ===================================
4973 11:04:12.285460 data_rate = 1866
4974 11:04:12.289030 CKR = 1
4975 11:04:12.292233 DQ_P2S_RATIO = 8
4976 11:04:12.295737 ===================================
4977 11:04:12.295803 CA_P2S_RATIO = 8
4978 11:04:12.299303 DQ_CA_OPEN = 0
4979 11:04:12.302307 DQ_SEMI_OPEN = 0
4980 11:04:12.305783 CA_SEMI_OPEN = 0
4981 11:04:12.309155 CA_FULL_RATE = 0
4982 11:04:12.312196 DQ_CKDIV4_EN = 1
4983 11:04:12.312261 CA_CKDIV4_EN = 1
4984 11:04:12.315812 CA_PREDIV_EN = 0
4985 11:04:12.319093 PH8_DLY = 0
4986 11:04:12.322352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4987 11:04:12.325977 DQ_AAMCK_DIV = 4
4988 11:04:12.328876 CA_AAMCK_DIV = 4
4989 11:04:12.328941 CA_ADMCK_DIV = 4
4990 11:04:12.332379 DQ_TRACK_CA_EN = 0
4991 11:04:12.336214 CA_PICK = 933
4992 11:04:12.339091 CA_MCKIO = 933
4993 11:04:12.342593 MCKIO_SEMI = 0
4994 11:04:12.345598 PLL_FREQ = 3732
4995 11:04:12.348774 DQ_UI_PI_RATIO = 32
4996 11:04:12.348843 CA_UI_PI_RATIO = 0
4997 11:04:12.352257 ===================================
4998 11:04:12.356038 ===================================
4999 11:04:12.359189 memory_type:LPDDR4
5000 11:04:12.362604 GP_NUM : 10
5001 11:04:12.362697 SRAM_EN : 1
5002 11:04:12.365422 MD32_EN : 0
5003 11:04:12.368935 ===================================
5004 11:04:12.372256 [ANA_INIT] >>>>>>>>>>>>>>
5005 11:04:12.375501 <<<<<< [CONFIGURE PHASE]: ANA_TX
5006 11:04:12.378542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5007 11:04:12.382031 ===================================
5008 11:04:12.382139 data_rate = 1866,PCW = 0X8f00
5009 11:04:12.385510 ===================================
5010 11:04:12.388717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5011 11:04:12.395300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5012 11:04:12.402277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5013 11:04:12.405525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5014 11:04:12.408727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5015 11:04:12.411810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5016 11:04:12.415484 [ANA_INIT] flow start
5017 11:04:12.415551 [ANA_INIT] PLL >>>>>>>>
5018 11:04:12.418703 [ANA_INIT] PLL <<<<<<<<
5019 11:04:12.421716 [ANA_INIT] MIDPI >>>>>>>>
5020 11:04:12.425543 [ANA_INIT] MIDPI <<<<<<<<
5021 11:04:12.425609 [ANA_INIT] DLL >>>>>>>>
5022 11:04:12.428703 [ANA_INIT] flow end
5023 11:04:12.432047 ============ LP4 DIFF to SE enter ============
5024 11:04:12.435639 ============ LP4 DIFF to SE exit ============
5025 11:04:12.438694 [ANA_INIT] <<<<<<<<<<<<<
5026 11:04:12.441702 [Flow] Enable top DCM control >>>>>
5027 11:04:12.445271 [Flow] Enable top DCM control <<<<<
5028 11:04:12.448868 Enable DLL master slave shuffle
5029 11:04:12.455573 ==============================================================
5030 11:04:12.455647 Gating Mode config
5031 11:04:12.461596 ==============================================================
5032 11:04:12.461665 Config description:
5033 11:04:12.471927 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5034 11:04:12.478105 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5035 11:04:12.484687 SELPH_MODE 0: By rank 1: By Phase
5036 11:04:12.488465 ==============================================================
5037 11:04:12.491475 GAT_TRACK_EN = 1
5038 11:04:12.495187 RX_GATING_MODE = 2
5039 11:04:12.498154 RX_GATING_TRACK_MODE = 2
5040 11:04:12.501343 SELPH_MODE = 1
5041 11:04:12.505056 PICG_EARLY_EN = 1
5042 11:04:12.508007 VALID_LAT_VALUE = 1
5043 11:04:12.514894 ==============================================================
5044 11:04:12.518051 Enter into Gating configuration >>>>
5045 11:04:12.521565 Exit from Gating configuration <<<<
5046 11:04:12.521663 Enter into DVFS_PRE_config >>>>>
5047 11:04:12.534621 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5048 11:04:12.538014 Exit from DVFS_PRE_config <<<<<
5049 11:04:12.541095 Enter into PICG configuration >>>>
5050 11:04:12.544431 Exit from PICG configuration <<<<
5051 11:04:12.544510 [RX_INPUT] configuration >>>>>
5052 11:04:12.547889 [RX_INPUT] configuration <<<<<
5053 11:04:12.554425 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5054 11:04:12.558060 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5055 11:04:12.564633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5056 11:04:12.571245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5057 11:04:12.577802 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5058 11:04:12.584581 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5059 11:04:12.587794 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5060 11:04:12.591044 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5061 11:04:12.597791 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5062 11:04:12.601058 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5063 11:04:12.604620 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5064 11:04:12.607512 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5065 11:04:12.611055 ===================================
5066 11:04:12.614117 LPDDR4 DRAM CONFIGURATION
5067 11:04:12.617673 ===================================
5068 11:04:12.620727 EX_ROW_EN[0] = 0x0
5069 11:04:12.620803 EX_ROW_EN[1] = 0x0
5070 11:04:12.624499 LP4Y_EN = 0x0
5071 11:04:12.624575 WORK_FSP = 0x0
5072 11:04:12.627622 WL = 0x3
5073 11:04:12.627713 RL = 0x3
5074 11:04:12.631170 BL = 0x2
5075 11:04:12.631264 RPST = 0x0
5076 11:04:12.633886 RD_PRE = 0x0
5077 11:04:12.633977 WR_PRE = 0x1
5078 11:04:12.637180 WR_PST = 0x0
5079 11:04:12.640955 DBI_WR = 0x0
5080 11:04:12.641046 DBI_RD = 0x0
5081 11:04:12.643799 OTF = 0x1
5082 11:04:12.647401 ===================================
5083 11:04:12.651025 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5084 11:04:12.654444 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5085 11:04:12.657486 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5086 11:04:12.660520 ===================================
5087 11:04:12.663740 LPDDR4 DRAM CONFIGURATION
5088 11:04:12.667119 ===================================
5089 11:04:12.670608 EX_ROW_EN[0] = 0x10
5090 11:04:12.670676 EX_ROW_EN[1] = 0x0
5091 11:04:12.673823 LP4Y_EN = 0x0
5092 11:04:12.673918 WORK_FSP = 0x0
5093 11:04:12.677050 WL = 0x3
5094 11:04:12.677126 RL = 0x3
5095 11:04:12.680657 BL = 0x2
5096 11:04:12.680732 RPST = 0x0
5097 11:04:12.683677 RD_PRE = 0x0
5098 11:04:12.683752 WR_PRE = 0x1
5099 11:04:12.687645 WR_PST = 0x0
5100 11:04:12.687744 DBI_WR = 0x0
5101 11:04:12.690272 DBI_RD = 0x0
5102 11:04:12.690347 OTF = 0x1
5103 11:04:12.693902 ===================================
5104 11:04:12.700520 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5105 11:04:12.705428 nWR fixed to 30
5106 11:04:12.709173 [ModeRegInit_LP4] CH0 RK0
5107 11:04:12.709248 [ModeRegInit_LP4] CH0 RK1
5108 11:04:12.712103 [ModeRegInit_LP4] CH1 RK0
5109 11:04:12.715344 [ModeRegInit_LP4] CH1 RK1
5110 11:04:12.715435 match AC timing 9
5111 11:04:12.722427 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5112 11:04:12.725280 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5113 11:04:12.728444 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5114 11:04:12.735834 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5115 11:04:12.738985 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5116 11:04:12.739062 ==
5117 11:04:12.741984 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 11:04:12.745075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 11:04:12.745175 ==
5120 11:04:12.752365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5121 11:04:12.758538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5122 11:04:12.761871 [CA 0] Center 38 (8~69) winsize 62
5123 11:04:12.765386 [CA 1] Center 38 (7~69) winsize 63
5124 11:04:12.768823 [CA 2] Center 35 (5~66) winsize 62
5125 11:04:12.771793 [CA 3] Center 35 (5~66) winsize 62
5126 11:04:12.775497 [CA 4] Center 34 (4~65) winsize 62
5127 11:04:12.778871 [CA 5] Center 33 (3~64) winsize 62
5128 11:04:12.778948
5129 11:04:12.781803 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5130 11:04:12.781880
5131 11:04:12.785500 [CATrainingPosCal] consider 1 rank data
5132 11:04:12.788828 u2DelayCellTimex100 = 270/100 ps
5133 11:04:12.791801 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5134 11:04:12.795153 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5135 11:04:12.798673 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5136 11:04:12.801820 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5137 11:04:12.804963 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5138 11:04:12.808741 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5139 11:04:12.811809
5140 11:04:12.815164 CA PerBit enable=1, Macro0, CA PI delay=33
5141 11:04:12.815261
5142 11:04:12.818586 [CBTSetCACLKResult] CA Dly = 33
5143 11:04:12.818684 CS Dly: 7 (0~38)
5144 11:04:12.818768 ==
5145 11:04:12.821839 Dram Type= 6, Freq= 0, CH_0, rank 1
5146 11:04:12.825364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:04:12.825441 ==
5148 11:04:12.832112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5149 11:04:12.838515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5150 11:04:12.841727 [CA 0] Center 38 (8~69) winsize 62
5151 11:04:12.845564 [CA 1] Center 38 (8~69) winsize 62
5152 11:04:12.848528 [CA 2] Center 35 (5~66) winsize 62
5153 11:04:12.851755 [CA 3] Center 35 (5~66) winsize 62
5154 11:04:12.855076 [CA 4] Center 34 (4~65) winsize 62
5155 11:04:12.858266 [CA 5] Center 33 (3~64) winsize 62
5156 11:04:12.858343
5157 11:04:12.862094 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5158 11:04:12.862206
5159 11:04:12.864860 [CATrainingPosCal] consider 2 rank data
5160 11:04:12.868496 u2DelayCellTimex100 = 270/100 ps
5161 11:04:12.871404 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5162 11:04:12.875117 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5163 11:04:12.878028 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5164 11:04:12.881491 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5165 11:04:12.884785 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5166 11:04:12.891539 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5167 11:04:12.891616
5168 11:04:12.894716 CA PerBit enable=1, Macro0, CA PI delay=33
5169 11:04:12.894793
5170 11:04:12.898212 [CBTSetCACLKResult] CA Dly = 33
5171 11:04:12.898321 CS Dly: 7 (0~38)
5172 11:04:12.898423
5173 11:04:12.901717 ----->DramcWriteLeveling(PI) begin...
5174 11:04:12.901796 ==
5175 11:04:12.904625 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 11:04:12.911233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 11:04:12.911311 ==
5178 11:04:12.914878 Write leveling (Byte 0): 30 => 30
5179 11:04:12.914955 Write leveling (Byte 1): 30 => 30
5180 11:04:12.918092 DramcWriteLeveling(PI) end<-----
5181 11:04:12.918192
5182 11:04:12.921391 ==
5183 11:04:12.921469 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 11:04:12.928347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 11:04:12.928425 ==
5186 11:04:12.931254 [Gating] SW mode calibration
5187 11:04:12.937870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5188 11:04:12.941641 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5189 11:04:12.947924 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5190 11:04:12.951154 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5191 11:04:12.955109 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 11:04:12.961296 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 11:04:12.964797 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 11:04:12.967930 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 11:04:12.974535 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 11:04:12.978084 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5197 11:04:12.981179 0 15 0 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5198 11:04:12.988233 0 15 4 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
5199 11:04:12.991091 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 11:04:12.994988 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 11:04:13.000854 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 11:04:13.004290 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 11:04:13.007805 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 11:04:13.014250 0 15 28 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
5205 11:04:13.017478 1 0 0 | B1->B0 | 2d2d 3a3a | 0 0 | (0 0) (0 0)
5206 11:04:13.020957 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5207 11:04:13.024471 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:04:13.031142 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 11:04:13.034298 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 11:04:13.037955 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 11:04:13.044440 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 11:04:13.047533 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 11:04:13.050825 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5214 11:04:13.057388 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5215 11:04:13.060461 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:04:13.064126 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:04:13.070435 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:04:13.074337 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:04:13.077063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:04:13.084064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:04:13.087580 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:04:13.090460 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:04:13.097658 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:04:13.100808 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 11:04:13.103878 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 11:04:13.110589 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 11:04:13.113835 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 11:04:13.117386 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 11:04:13.124017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5230 11:04:13.124094 Total UI for P1: 0, mck2ui 16
5231 11:04:13.130428 best dqsien dly found for B0: ( 1, 2, 30)
5232 11:04:13.133857 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5233 11:04:13.137291 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 11:04:13.140916 Total UI for P1: 0, mck2ui 16
5235 11:04:13.143938 best dqsien dly found for B1: ( 1, 3, 4)
5236 11:04:13.146996 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5237 11:04:13.150449 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5238 11:04:13.150541
5239 11:04:13.154032 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5240 11:04:13.157023 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5241 11:04:13.160674 [Gating] SW calibration Done
5242 11:04:13.160750 ==
5243 11:04:13.164097 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 11:04:13.170671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 11:04:13.170747 ==
5246 11:04:13.170805 RX Vref Scan: 0
5247 11:04:13.170860
5248 11:04:13.173692 RX Vref 0 -> 0, step: 1
5249 11:04:13.173767
5250 11:04:13.177250 RX Delay -80 -> 252, step: 8
5251 11:04:13.180276 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5252 11:04:13.184055 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5253 11:04:13.187335 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5254 11:04:13.190814 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5255 11:04:13.193879 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5256 11:04:13.200472 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5257 11:04:13.204004 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5258 11:04:13.206906 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5259 11:04:13.210363 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5260 11:04:13.213877 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5261 11:04:13.220188 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5262 11:04:13.223569 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5263 11:04:13.226666 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5264 11:04:13.229954 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5265 11:04:13.236371 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5266 11:04:13.239849 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5267 11:04:13.239925 ==
5268 11:04:13.243274 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 11:04:13.246441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 11:04:13.246517 ==
5271 11:04:13.246576 DQS Delay:
5272 11:04:13.250129 DQS0 = 0, DQS1 = 0
5273 11:04:13.250218 DQM Delay:
5274 11:04:13.253462 DQM0 = 94, DQM1 = 83
5275 11:04:13.253537 DQ Delay:
5276 11:04:13.256504 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5277 11:04:13.259829 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5278 11:04:13.263429 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5279 11:04:13.266821 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5280 11:04:13.266896
5281 11:04:13.266954
5282 11:04:13.267006 ==
5283 11:04:13.269686 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 11:04:13.276507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:04:13.276583 ==
5286 11:04:13.276641
5287 11:04:13.276695
5288 11:04:13.276745 TX Vref Scan disable
5289 11:04:13.279875 == TX Byte 0 ==
5290 11:04:13.283284 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5291 11:04:13.290047 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5292 11:04:13.290159 == TX Byte 1 ==
5293 11:04:13.292898 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5294 11:04:13.299555 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5295 11:04:13.299644 ==
5296 11:04:13.303084 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 11:04:13.306455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 11:04:13.306532 ==
5299 11:04:13.306590
5300 11:04:13.306643
5301 11:04:13.309802 TX Vref Scan disable
5302 11:04:13.309878 == TX Byte 0 ==
5303 11:04:13.316369 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5304 11:04:13.319344 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5305 11:04:13.319420 == TX Byte 1 ==
5306 11:04:13.326391 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5307 11:04:13.329517 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5308 11:04:13.329594
5309 11:04:13.329691 [DATLAT]
5310 11:04:13.332854 Freq=933, CH0 RK0
5311 11:04:13.332930
5312 11:04:13.333020 DATLAT Default: 0xd
5313 11:04:13.335931 0, 0xFFFF, sum = 0
5314 11:04:13.336008 1, 0xFFFF, sum = 0
5315 11:04:13.339190 2, 0xFFFF, sum = 0
5316 11:04:13.339297 3, 0xFFFF, sum = 0
5317 11:04:13.342920 4, 0xFFFF, sum = 0
5318 11:04:13.345966 5, 0xFFFF, sum = 0
5319 11:04:13.346065 6, 0xFFFF, sum = 0
5320 11:04:13.349253 7, 0xFFFF, sum = 0
5321 11:04:13.349352 8, 0xFFFF, sum = 0
5322 11:04:13.352960 9, 0xFFFF, sum = 0
5323 11:04:13.353055 10, 0x0, sum = 1
5324 11:04:13.355943 11, 0x0, sum = 2
5325 11:04:13.356023 12, 0x0, sum = 3
5326 11:04:13.356102 13, 0x0, sum = 4
5327 11:04:13.359439 best_step = 11
5328 11:04:13.359518
5329 11:04:13.359594 ==
5330 11:04:13.362666 Dram Type= 6, Freq= 0, CH_0, rank 0
5331 11:04:13.366201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 11:04:13.366290 ==
5333 11:04:13.368951 RX Vref Scan: 1
5334 11:04:13.369047
5335 11:04:13.372558 RX Vref 0 -> 0, step: 1
5336 11:04:13.372658
5337 11:04:13.372757 RX Delay -69 -> 252, step: 4
5338 11:04:13.372849
5339 11:04:13.376095 Set Vref, RX VrefLevel [Byte0]: 60
5340 11:04:13.379438 [Byte1]: 49
5341 11:04:13.383616
5342 11:04:13.383695 Final RX Vref Byte 0 = 60 to rank0
5343 11:04:13.387024 Final RX Vref Byte 1 = 49 to rank0
5344 11:04:13.390721 Final RX Vref Byte 0 = 60 to rank1
5345 11:04:13.393478 Final RX Vref Byte 1 = 49 to rank1==
5346 11:04:13.397283 Dram Type= 6, Freq= 0, CH_0, rank 0
5347 11:04:13.403925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 11:04:13.404024 ==
5349 11:04:13.404107 DQS Delay:
5350 11:04:13.404186 DQS0 = 0, DQS1 = 0
5351 11:04:13.407188 DQM Delay:
5352 11:04:13.407339 DQM0 = 95, DQM1 = 83
5353 11:04:13.410305 DQ Delay:
5354 11:04:13.413281 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5355 11:04:13.416792 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5356 11:04:13.420493 DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =76
5357 11:04:13.423331 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5358 11:04:13.423409
5359 11:04:13.423467
5360 11:04:13.430139 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5361 11:04:13.433467 CH0 RK0: MR19=505, MR18=1414
5362 11:04:13.439820 CH0_RK0: MR19=0x505, MR18=0x1414, DQSOSC=415, MR23=63, INC=62, DEC=41
5363 11:04:13.439929
5364 11:04:13.443300 ----->DramcWriteLeveling(PI) begin...
5365 11:04:13.443405 ==
5366 11:04:13.446517 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 11:04:13.450240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 11:04:13.450345 ==
5369 11:04:13.453090 Write leveling (Byte 0): 31 => 31
5370 11:04:13.456547 Write leveling (Byte 1): 31 => 31
5371 11:04:13.460220 DramcWriteLeveling(PI) end<-----
5372 11:04:13.460369
5373 11:04:13.460502 ==
5374 11:04:13.463202 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 11:04:13.466585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 11:04:13.466663 ==
5377 11:04:13.469992 [Gating] SW mode calibration
5378 11:04:13.476280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5379 11:04:13.483059 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5380 11:04:13.486670 0 14 0 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
5381 11:04:13.493214 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 11:04:13.496437 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 11:04:13.499803 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 11:04:13.506683 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 11:04:13.509616 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 11:04:13.513250 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 11:04:13.519963 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (1 1)
5388 11:04:13.523255 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5389 11:04:13.526093 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 11:04:13.529844 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 11:04:13.536343 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 11:04:13.539424 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 11:04:13.543038 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 11:04:13.549436 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 11:04:13.552663 0 15 28 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
5396 11:04:13.556491 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5397 11:04:13.562806 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 11:04:13.566093 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 11:04:13.569293 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 11:04:13.576042 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 11:04:13.579367 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 11:04:13.583036 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 11:04:13.589146 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5404 11:04:13.592543 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:04:13.595989 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:04:13.602461 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:04:13.606302 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:04:13.609119 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:04:13.615581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:04:13.619852 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:04:13.622662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:04:13.629219 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:04:13.632673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 11:04:13.635897 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 11:04:13.642908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 11:04:13.645733 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 11:04:13.648720 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 11:04:13.655703 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 11:04:13.658926 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5420 11:04:13.662399 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5421 11:04:13.665759 Total UI for P1: 0, mck2ui 16
5422 11:04:13.668996 best dqsien dly found for B0: ( 1, 2, 28)
5423 11:04:13.672275 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 11:04:13.675850 Total UI for P1: 0, mck2ui 16
5425 11:04:13.678906 best dqsien dly found for B1: ( 1, 3, 0)
5426 11:04:13.682295 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5427 11:04:13.688885 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5428 11:04:13.688978
5429 11:04:13.692290 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5430 11:04:13.695282 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5431 11:04:13.698971 [Gating] SW calibration Done
5432 11:04:13.699092 ==
5433 11:04:13.701891 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 11:04:13.705485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 11:04:13.705570 ==
5436 11:04:13.708582 RX Vref Scan: 0
5437 11:04:13.708663
5438 11:04:13.708741 RX Vref 0 -> 0, step: 1
5439 11:04:13.708816
5440 11:04:13.711846 RX Delay -80 -> 252, step: 8
5441 11:04:13.715540 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5442 11:04:13.718979 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5443 11:04:13.724976 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5444 11:04:13.728750 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5445 11:04:13.732085 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5446 11:04:13.735421 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5447 11:04:13.739004 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5448 11:04:13.745447 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5449 11:04:13.748575 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5450 11:04:13.752071 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5451 11:04:13.755110 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5452 11:04:13.758533 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5453 11:04:13.765336 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5454 11:04:13.768231 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5455 11:04:13.771825 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5456 11:04:13.774823 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5457 11:04:13.774908 ==
5458 11:04:13.778472 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 11:04:13.785267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 11:04:13.785356 ==
5461 11:04:13.785442 DQS Delay:
5462 11:04:13.785509 DQS0 = 0, DQS1 = 0
5463 11:04:13.788560 DQM Delay:
5464 11:04:13.788639 DQM0 = 92, DQM1 = 82
5465 11:04:13.791640 DQ Delay:
5466 11:04:13.794792 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5467 11:04:13.797731 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5468 11:04:13.801519 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5469 11:04:13.804919 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5470 11:04:13.805003
5471 11:04:13.805080
5472 11:04:13.805152 ==
5473 11:04:13.808319 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 11:04:13.811072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 11:04:13.811166 ==
5476 11:04:13.811261
5477 11:04:13.811366
5478 11:04:13.814938 TX Vref Scan disable
5479 11:04:13.815056 == TX Byte 0 ==
5480 11:04:13.821318 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5481 11:04:13.824752 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5482 11:04:13.824838 == TX Byte 1 ==
5483 11:04:13.830996 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5484 11:04:13.834548 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5485 11:04:13.834631 ==
5486 11:04:13.838031 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 11:04:13.841016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 11:04:13.841111 ==
5489 11:04:13.844612
5490 11:04:13.844695
5491 11:04:13.844755 TX Vref Scan disable
5492 11:04:13.847555 == TX Byte 0 ==
5493 11:04:13.850829 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5494 11:04:13.854335 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5495 11:04:13.857740 == TX Byte 1 ==
5496 11:04:13.860606 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5497 11:04:13.867408 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5498 11:04:13.867503
5499 11:04:13.867562 [DATLAT]
5500 11:04:13.867616 Freq=933, CH0 RK1
5501 11:04:13.867668
5502 11:04:13.870888 DATLAT Default: 0xb
5503 11:04:13.870965 0, 0xFFFF, sum = 0
5504 11:04:13.873982 1, 0xFFFF, sum = 0
5505 11:04:13.874073 2, 0xFFFF, sum = 0
5506 11:04:13.877570 3, 0xFFFF, sum = 0
5507 11:04:13.880852 4, 0xFFFF, sum = 0
5508 11:04:13.880932 5, 0xFFFF, sum = 0
5509 11:04:13.884403 6, 0xFFFF, sum = 0
5510 11:04:13.884507 7, 0xFFFF, sum = 0
5511 11:04:13.887195 8, 0xFFFF, sum = 0
5512 11:04:13.887289 9, 0xFFFF, sum = 0
5513 11:04:13.890636 10, 0x0, sum = 1
5514 11:04:13.890750 11, 0x0, sum = 2
5515 11:04:13.894026 12, 0x0, sum = 3
5516 11:04:13.894130 13, 0x0, sum = 4
5517 11:04:13.894220 best_step = 11
5518 11:04:13.894301
5519 11:04:13.897207 ==
5520 11:04:13.900794 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 11:04:13.904187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 11:04:13.904271 ==
5523 11:04:13.904350 RX Vref Scan: 0
5524 11:04:13.904423
5525 11:04:13.907539 RX Vref 0 -> 0, step: 1
5526 11:04:13.907642
5527 11:04:13.910455 RX Delay -77 -> 252, step: 4
5528 11:04:13.913864 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5529 11:04:13.920424 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5530 11:04:13.923544 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5531 11:04:13.927149 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5532 11:04:13.930501 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5533 11:04:13.933695 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5534 11:04:13.940136 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5535 11:04:13.943569 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5536 11:04:13.947349 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5537 11:04:13.950336 iDelay=199, Bit 9, Center 70 (-21 ~ 162) 184
5538 11:04:13.953385 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5539 11:04:13.960681 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5540 11:04:13.963991 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5541 11:04:13.967004 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5542 11:04:13.970214 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5543 11:04:13.973331 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5544 11:04:13.973437 ==
5545 11:04:13.976585 Dram Type= 6, Freq= 0, CH_0, rank 1
5546 11:04:13.983242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 11:04:13.983337 ==
5548 11:04:13.983403 DQS Delay:
5549 11:04:13.986533 DQS0 = 0, DQS1 = 0
5550 11:04:13.986612 DQM Delay:
5551 11:04:13.986702 DQM0 = 92, DQM1 = 84
5552 11:04:13.990315 DQ Delay:
5553 11:04:13.993261 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5554 11:04:13.996496 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =102
5555 11:04:13.999997 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =76
5556 11:04:14.003491 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5557 11:04:14.003575
5558 11:04:14.003633
5559 11:04:14.010017 [DQSOSCAuto] RK1, (LSB)MR18= 0x3619, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 404 ps
5560 11:04:14.013293 CH0 RK1: MR19=505, MR18=3619
5561 11:04:14.019617 CH0_RK1: MR19=0x505, MR18=0x3619, DQSOSC=404, MR23=63, INC=66, DEC=44
5562 11:04:14.023079 [RxdqsGatingPostProcess] freq 933
5563 11:04:14.029811 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5564 11:04:14.029907 best DQS0 dly(2T, 0.5T) = (0, 10)
5565 11:04:14.033256 best DQS1 dly(2T, 0.5T) = (0, 11)
5566 11:04:14.036298 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5567 11:04:14.040196 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5568 11:04:14.043095 best DQS0 dly(2T, 0.5T) = (0, 10)
5569 11:04:14.046017 best DQS1 dly(2T, 0.5T) = (0, 11)
5570 11:04:14.049727 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5571 11:04:14.052558 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5572 11:04:14.056449 Pre-setting of DQS Precalculation
5573 11:04:14.062909 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5574 11:04:14.063001 ==
5575 11:04:14.066538 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 11:04:14.069771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 11:04:14.069852 ==
5578 11:04:14.076170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5579 11:04:14.079523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5580 11:04:14.083356 [CA 0] Center 37 (7~67) winsize 61
5581 11:04:14.086476 [CA 1] Center 37 (7~68) winsize 62
5582 11:04:14.089940 [CA 2] Center 34 (5~64) winsize 60
5583 11:04:14.093443 [CA 3] Center 34 (5~64) winsize 60
5584 11:04:14.096216 [CA 4] Center 34 (5~64) winsize 60
5585 11:04:14.099875 [CA 5] Center 34 (4~64) winsize 61
5586 11:04:14.099996
5587 11:04:14.103700 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5588 11:04:14.103825
5589 11:04:14.106747 [CATrainingPosCal] consider 1 rank data
5590 11:04:14.110031 u2DelayCellTimex100 = 270/100 ps
5591 11:04:14.113114 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5592 11:04:14.119708 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5593 11:04:14.123119 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5594 11:04:14.126068 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5595 11:04:14.129772 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5596 11:04:14.133454 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5597 11:04:14.133581
5598 11:04:14.136169 CA PerBit enable=1, Macro0, CA PI delay=34
5599 11:04:14.136245
5600 11:04:14.139612 [CBTSetCACLKResult] CA Dly = 34
5601 11:04:14.139690 CS Dly: 6 (0~37)
5602 11:04:14.142727 ==
5603 11:04:14.146295 Dram Type= 6, Freq= 0, CH_1, rank 1
5604 11:04:14.149390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 11:04:14.149473 ==
5606 11:04:14.153200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5607 11:04:14.159329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5608 11:04:14.163029 [CA 0] Center 37 (7~68) winsize 62
5609 11:04:14.166457 [CA 1] Center 37 (7~68) winsize 62
5610 11:04:14.169845 [CA 2] Center 35 (6~65) winsize 60
5611 11:04:14.173136 [CA 3] Center 34 (4~64) winsize 61
5612 11:04:14.176885 [CA 4] Center 35 (5~65) winsize 61
5613 11:04:14.180325 [CA 5] Center 33 (3~64) winsize 62
5614 11:04:14.180405
5615 11:04:14.183240 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5616 11:04:14.183318
5617 11:04:14.186482 [CATrainingPosCal] consider 2 rank data
5618 11:04:14.189889 u2DelayCellTimex100 = 270/100 ps
5619 11:04:14.192883 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5620 11:04:14.196670 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5621 11:04:14.203135 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5622 11:04:14.206363 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5623 11:04:14.210068 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5624 11:04:14.213067 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5625 11:04:14.213172
5626 11:04:14.216618 CA PerBit enable=1, Macro0, CA PI delay=34
5627 11:04:14.216723
5628 11:04:14.219515 [CBTSetCACLKResult] CA Dly = 34
5629 11:04:14.219593 CS Dly: 7 (0~39)
5630 11:04:14.219652
5631 11:04:14.226617 ----->DramcWriteLeveling(PI) begin...
5632 11:04:14.226707 ==
5633 11:04:14.229370 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 11:04:14.232884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 11:04:14.232967 ==
5636 11:04:14.236235 Write leveling (Byte 0): 24 => 24
5637 11:04:14.239621 Write leveling (Byte 1): 27 => 27
5638 11:04:14.242813 DramcWriteLeveling(PI) end<-----
5639 11:04:14.242895
5640 11:04:14.242972 ==
5641 11:04:14.245893 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 11:04:14.249063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 11:04:14.249175 ==
5644 11:04:14.252483 [Gating] SW mode calibration
5645 11:04:14.259183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5646 11:04:14.266027 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5647 11:04:14.269317 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5648 11:04:14.272516 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 11:04:14.279564 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 11:04:14.282661 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 11:04:14.285635 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 11:04:14.292542 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 11:04:14.296016 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5654 11:04:14.298956 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
5655 11:04:14.306175 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 11:04:14.309284 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 11:04:14.312884 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 11:04:14.316067 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 11:04:14.322479 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 11:04:14.325626 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 11:04:14.329240 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 11:04:14.335614 0 15 28 | B1->B0 | 3232 3232 | 0 0 | (0 0) (0 0)
5663 11:04:14.339021 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:04:14.342417 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 11:04:14.349457 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:04:14.352379 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 11:04:14.355726 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 11:04:14.362234 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 11:04:14.365881 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5670 11:04:14.368760 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5671 11:04:14.375593 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:04:14.379128 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:04:14.382011 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:04:14.388989 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:04:14.391991 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:04:14.395300 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:04:14.401870 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:04:14.405307 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:04:14.408394 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 11:04:14.415835 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 11:04:14.418688 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:04:14.421631 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 11:04:14.428880 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 11:04:14.431742 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 11:04:14.435434 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 11:04:14.441810 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 11:04:14.441906 Total UI for P1: 0, mck2ui 16
5688 11:04:14.448390 best dqsien dly found for B0: ( 1, 2, 26)
5689 11:04:14.448483 Total UI for P1: 0, mck2ui 16
5690 11:04:14.451776 best dqsien dly found for B1: ( 1, 2, 26)
5691 11:04:14.458068 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5692 11:04:14.461941 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5693 11:04:14.462036
5694 11:04:14.465233 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5695 11:04:14.468362 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5696 11:04:14.472079 [Gating] SW calibration Done
5697 11:04:14.472173 ==
5698 11:04:14.475028 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 11:04:14.478295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 11:04:14.478379 ==
5701 11:04:14.481590 RX Vref Scan: 0
5702 11:04:14.481669
5703 11:04:14.481728 RX Vref 0 -> 0, step: 1
5704 11:04:14.481783
5705 11:04:14.485612 RX Delay -80 -> 252, step: 8
5706 11:04:14.488489 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5707 11:04:14.491549 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5708 11:04:14.498503 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5709 11:04:14.501637 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5710 11:04:14.505054 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5711 11:04:14.508630 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5712 11:04:14.511807 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5713 11:04:14.518403 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5714 11:04:14.521426 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5715 11:04:14.525225 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5716 11:04:14.527886 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5717 11:04:14.531452 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5718 11:04:14.538018 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5719 11:04:14.541947 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5720 11:04:14.545021 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5721 11:04:14.548022 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5722 11:04:14.548105 ==
5723 11:04:14.551275 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 11:04:14.554754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 11:04:14.558224 ==
5726 11:04:14.558358 DQS Delay:
5727 11:04:14.558442 DQS0 = 0, DQS1 = 0
5728 11:04:14.561551 DQM Delay:
5729 11:04:14.561629 DQM0 = 93, DQM1 = 85
5730 11:04:14.564431 DQ Delay:
5731 11:04:14.564547 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5732 11:04:14.568054 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5733 11:04:14.570991 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5734 11:04:14.574600 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5735 11:04:14.577675
5736 11:04:14.577785
5737 11:04:14.577869 ==
5738 11:04:14.581314 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 11:04:14.584676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 11:04:14.584760 ==
5741 11:04:14.584820
5742 11:04:14.584874
5743 11:04:14.587884 TX Vref Scan disable
5744 11:04:14.587963 == TX Byte 0 ==
5745 11:04:14.594475 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5746 11:04:14.597617 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5747 11:04:14.597705 == TX Byte 1 ==
5748 11:04:14.604407 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 11:04:14.607901 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 11:04:14.607990 ==
5751 11:04:14.611233 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 11:04:14.614178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 11:04:14.614263 ==
5754 11:04:14.614324
5755 11:04:14.614379
5756 11:04:14.617699 TX Vref Scan disable
5757 11:04:14.621476 == TX Byte 0 ==
5758 11:04:14.624341 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5759 11:04:14.627424 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5760 11:04:14.630684 == TX Byte 1 ==
5761 11:04:14.634256 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5762 11:04:14.637572 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5763 11:04:14.637657
5764 11:04:14.641097 [DATLAT]
5765 11:04:14.641183 Freq=933, CH1 RK0
5766 11:04:14.641245
5767 11:04:14.644045 DATLAT Default: 0xd
5768 11:04:14.644124 0, 0xFFFF, sum = 0
5769 11:04:14.647363 1, 0xFFFF, sum = 0
5770 11:04:14.647447 2, 0xFFFF, sum = 0
5771 11:04:14.650455 3, 0xFFFF, sum = 0
5772 11:04:14.650540 4, 0xFFFF, sum = 0
5773 11:04:14.654292 5, 0xFFFF, sum = 0
5774 11:04:14.654379 6, 0xFFFF, sum = 0
5775 11:04:14.657288 7, 0xFFFF, sum = 0
5776 11:04:14.657373 8, 0xFFFF, sum = 0
5777 11:04:14.660875 9, 0xFFFF, sum = 0
5778 11:04:14.660993 10, 0x0, sum = 1
5779 11:04:14.663864 11, 0x0, sum = 2
5780 11:04:14.663964 12, 0x0, sum = 3
5781 11:04:14.667209 13, 0x0, sum = 4
5782 11:04:14.667293 best_step = 11
5783 11:04:14.667354
5784 11:04:14.667409 ==
5785 11:04:14.670440 Dram Type= 6, Freq= 0, CH_1, rank 0
5786 11:04:14.677621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 11:04:14.677721 ==
5788 11:04:14.677783 RX Vref Scan: 1
5789 11:04:14.677838
5790 11:04:14.680464 RX Vref 0 -> 0, step: 1
5791 11:04:14.680545
5792 11:04:14.683842 RX Delay -69 -> 252, step: 4
5793 11:04:14.683921
5794 11:04:14.687346 Set Vref, RX VrefLevel [Byte0]: 55
5795 11:04:14.690500 [Byte1]: 51
5796 11:04:14.690627
5797 11:04:14.694019 Final RX Vref Byte 0 = 55 to rank0
5798 11:04:14.697285 Final RX Vref Byte 1 = 51 to rank0
5799 11:04:14.700698 Final RX Vref Byte 0 = 55 to rank1
5800 11:04:14.703772 Final RX Vref Byte 1 = 51 to rank1==
5801 11:04:14.707394 Dram Type= 6, Freq= 0, CH_1, rank 0
5802 11:04:14.710753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 11:04:14.710835 ==
5804 11:04:14.713998 DQS Delay:
5805 11:04:14.714076 DQS0 = 0, DQS1 = 0
5806 11:04:14.714163 DQM Delay:
5807 11:04:14.717243 DQM0 = 96, DQM1 = 87
5808 11:04:14.717323 DQ Delay:
5809 11:04:14.721097 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
5810 11:04:14.723851 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =94
5811 11:04:14.727564 DQ8 =76, DQ9 =80, DQ10 =86, DQ11 =80
5812 11:04:14.730446 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5813 11:04:14.730529
5814 11:04:14.730588
5815 11:04:14.740596 [DQSOSCAuto] RK0, (LSB)MR18= 0x810, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
5816 11:04:14.744096 CH1 RK0: MR19=505, MR18=810
5817 11:04:14.747363 CH1_RK0: MR19=0x505, MR18=0x810, DQSOSC=416, MR23=63, INC=62, DEC=41
5818 11:04:14.747450
5819 11:04:14.750297 ----->DramcWriteLeveling(PI) begin...
5820 11:04:14.753909 ==
5821 11:04:14.756916 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 11:04:14.760482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 11:04:14.760606 ==
5824 11:04:14.763497 Write leveling (Byte 0): 25 => 25
5825 11:04:14.767291 Write leveling (Byte 1): 26 => 26
5826 11:04:14.770318 DramcWriteLeveling(PI) end<-----
5827 11:04:14.770539
5828 11:04:14.770645 ==
5829 11:04:14.773493 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 11:04:14.777249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 11:04:14.777356 ==
5832 11:04:14.780039 [Gating] SW mode calibration
5833 11:04:14.787001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5834 11:04:14.793608 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5835 11:04:14.796965 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 11:04:14.800049 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 11:04:14.806890 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 11:04:14.810269 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 11:04:14.813671 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 11:04:14.816872 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5841 11:04:14.823784 0 14 24 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 0)
5842 11:04:14.826698 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5843 11:04:14.830624 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 11:04:14.836914 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 11:04:14.839762 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 11:04:14.843172 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 11:04:14.850028 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 11:04:14.853391 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 11:04:14.856878 0 15 24 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
5850 11:04:14.863395 0 15 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5851 11:04:14.866513 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 11:04:14.870106 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 11:04:14.876442 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 11:04:14.879889 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 11:04:14.882836 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 11:04:14.889976 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 11:04:14.893361 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 11:04:14.895971 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5859 11:04:14.903110 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:04:14.906640 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:04:14.909593 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:04:14.915943 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:04:14.919207 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:04:14.923232 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:04:14.929639 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:04:14.932542 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:04:14.936112 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:04:14.943338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:04:14.946045 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:04:14.949534 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 11:04:14.956014 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 11:04:14.959500 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 11:04:14.962840 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5874 11:04:14.969576 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 11:04:14.969666 Total UI for P1: 0, mck2ui 16
5876 11:04:14.976064 best dqsien dly found for B0: ( 1, 2, 24)
5877 11:04:14.976142 Total UI for P1: 0, mck2ui 16
5878 11:04:14.979004 best dqsien dly found for B1: ( 1, 2, 26)
5879 11:04:14.985939 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5880 11:04:14.989275 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5881 11:04:14.989369
5882 11:04:14.992436 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5883 11:04:14.996109 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5884 11:04:14.998843 [Gating] SW calibration Done
5885 11:04:14.998937 ==
5886 11:04:15.002234 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 11:04:15.005663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 11:04:15.005737 ==
5889 11:04:15.008963 RX Vref Scan: 0
5890 11:04:15.009028
5891 11:04:15.009082 RX Vref 0 -> 0, step: 1
5892 11:04:15.009132
5893 11:04:15.012347 RX Delay -80 -> 252, step: 8
5894 11:04:15.015637 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5895 11:04:15.019126 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5896 11:04:15.025527 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5897 11:04:15.029015 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5898 11:04:15.032619 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5899 11:04:15.035812 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5900 11:04:15.038644 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5901 11:04:15.045664 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5902 11:04:15.048900 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5903 11:04:15.052447 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5904 11:04:15.055863 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5905 11:04:15.058690 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5906 11:04:15.065628 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5907 11:04:15.068993 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5908 11:04:15.072029 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5909 11:04:15.075715 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5910 11:04:15.075834 ==
5911 11:04:15.078811 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 11:04:15.081962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 11:04:15.082075 ==
5914 11:04:15.085477 DQS Delay:
5915 11:04:15.085555 DQS0 = 0, DQS1 = 0
5916 11:04:15.089075 DQM Delay:
5917 11:04:15.089153 DQM0 = 94, DQM1 = 88
5918 11:04:15.089212 DQ Delay:
5919 11:04:15.091978 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5920 11:04:15.095526 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5921 11:04:15.098714 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5922 11:04:15.101706 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5923 11:04:15.101808
5924 11:04:15.105532
5925 11:04:15.105619 ==
5926 11:04:15.108969 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 11:04:15.111880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 11:04:15.111977 ==
5929 11:04:15.112050
5930 11:04:15.112135
5931 11:04:15.115022 TX Vref Scan disable
5932 11:04:15.115096 == TX Byte 0 ==
5933 11:04:15.121669 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5934 11:04:15.125633 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5935 11:04:15.125741 == TX Byte 1 ==
5936 11:04:15.131883 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5937 11:04:15.135073 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5938 11:04:15.135178 ==
5939 11:04:15.138843 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 11:04:15.141612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 11:04:15.141754 ==
5942 11:04:15.141838
5943 11:04:15.141917
5944 11:04:15.145021 TX Vref Scan disable
5945 11:04:15.148613 == TX Byte 0 ==
5946 11:04:15.151385 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5947 11:04:15.155239 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5948 11:04:15.158141 == TX Byte 1 ==
5949 11:04:15.161609 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5950 11:04:15.164714 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5951 11:04:15.164797
5952 11:04:15.168073 [DATLAT]
5953 11:04:15.168174 Freq=933, CH1 RK1
5954 11:04:15.168259
5955 11:04:15.171649 DATLAT Default: 0xb
5956 11:04:15.171745 0, 0xFFFF, sum = 0
5957 11:04:15.175360 1, 0xFFFF, sum = 0
5958 11:04:15.175441 2, 0xFFFF, sum = 0
5959 11:04:15.178275 3, 0xFFFF, sum = 0
5960 11:04:15.178354 4, 0xFFFF, sum = 0
5961 11:04:15.181394 5, 0xFFFF, sum = 0
5962 11:04:15.181478 6, 0xFFFF, sum = 0
5963 11:04:15.184981 7, 0xFFFF, sum = 0
5964 11:04:15.185061 8, 0xFFFF, sum = 0
5965 11:04:15.188082 9, 0xFFFF, sum = 0
5966 11:04:15.188184 10, 0x0, sum = 1
5967 11:04:15.191857 11, 0x0, sum = 2
5968 11:04:15.191941 12, 0x0, sum = 3
5969 11:04:15.194790 13, 0x0, sum = 4
5970 11:04:15.194868 best_step = 11
5971 11:04:15.194927
5972 11:04:15.194981 ==
5973 11:04:15.198017 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 11:04:15.204808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 11:04:15.204897 ==
5976 11:04:15.204957 RX Vref Scan: 0
5977 11:04:15.205027
5978 11:04:15.207849 RX Vref 0 -> 0, step: 1
5979 11:04:15.207929
5980 11:04:15.211038 RX Delay -69 -> 252, step: 4
5981 11:04:15.214556 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5982 11:04:15.217778 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5983 11:04:15.224702 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5984 11:04:15.228059 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5985 11:04:15.231363 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5986 11:04:15.234575 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5987 11:04:15.237754 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5988 11:04:15.240935 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5989 11:04:15.247761 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5990 11:04:15.251182 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5991 11:04:15.253992 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5992 11:04:15.257464 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5993 11:04:15.260673 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5994 11:04:15.267736 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5995 11:04:15.270821 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5996 11:04:15.274605 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5997 11:04:15.274730 ==
5998 11:04:15.277560 Dram Type= 6, Freq= 0, CH_1, rank 1
5999 11:04:15.280575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6000 11:04:15.280658 ==
6001 11:04:15.284264 DQS Delay:
6002 11:04:15.284366 DQS0 = 0, DQS1 = 0
6003 11:04:15.287198 DQM Delay:
6004 11:04:15.287277 DQM0 = 91, DQM1 = 89
6005 11:04:15.287375 DQ Delay:
6006 11:04:15.291026 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6007 11:04:15.294032 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =88
6008 11:04:15.297687 DQ8 =76, DQ9 =80, DQ10 =94, DQ11 =82
6009 11:04:15.300692 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
6010 11:04:15.300792
6011 11:04:15.300883
6012 11:04:15.310423 [DQSOSCAuto] RK1, (LSB)MR18= 0x1528, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
6013 11:04:15.314038 CH1 RK1: MR19=505, MR18=1528
6014 11:04:15.317189 CH1_RK1: MR19=0x505, MR18=0x1528, DQSOSC=409, MR23=63, INC=64, DEC=43
6015 11:04:15.320528 [RxdqsGatingPostProcess] freq 933
6016 11:04:15.327389 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6017 11:04:15.331083 best DQS0 dly(2T, 0.5T) = (0, 10)
6018 11:04:15.334041 best DQS1 dly(2T, 0.5T) = (0, 10)
6019 11:04:15.337173 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6020 11:04:15.340445 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6021 11:04:15.343907 best DQS0 dly(2T, 0.5T) = (0, 10)
6022 11:04:15.347619 best DQS1 dly(2T, 0.5T) = (0, 10)
6023 11:04:15.350494 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6024 11:04:15.353990 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6025 11:04:15.357024 Pre-setting of DQS Precalculation
6026 11:04:15.360366 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6027 11:04:15.367092 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6028 11:04:15.373619 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6029 11:04:15.373738
6030 11:04:15.373831
6031 11:04:15.377056 [Calibration Summary] 1866 Mbps
6032 11:04:15.380716 CH 0, Rank 0
6033 11:04:15.380819 SW Impedance : PASS
6034 11:04:15.383799 DUTY Scan : NO K
6035 11:04:15.386991 ZQ Calibration : PASS
6036 11:04:15.387075 Jitter Meter : NO K
6037 11:04:15.390584 CBT Training : PASS
6038 11:04:15.394054 Write leveling : PASS
6039 11:04:15.394146 RX DQS gating : PASS
6040 11:04:15.397085 RX DQ/DQS(RDDQC) : PASS
6041 11:04:15.400263 TX DQ/DQS : PASS
6042 11:04:15.400345 RX DATLAT : PASS
6043 11:04:15.403895 RX DQ/DQS(Engine): PASS
6044 11:04:15.404002 TX OE : NO K
6045 11:04:15.407447 All Pass.
6046 11:04:15.407548
6047 11:04:15.407640 CH 0, Rank 1
6048 11:04:15.410424 SW Impedance : PASS
6049 11:04:15.410517 DUTY Scan : NO K
6050 11:04:15.414068 ZQ Calibration : PASS
6051 11:04:15.416957 Jitter Meter : NO K
6052 11:04:15.417063 CBT Training : PASS
6053 11:04:15.420641 Write leveling : PASS
6054 11:04:15.423696 RX DQS gating : PASS
6055 11:04:15.423782 RX DQ/DQS(RDDQC) : PASS
6056 11:04:15.427278 TX DQ/DQS : PASS
6057 11:04:15.430025 RX DATLAT : PASS
6058 11:04:15.430112 RX DQ/DQS(Engine): PASS
6059 11:04:15.433534 TX OE : NO K
6060 11:04:15.433615 All Pass.
6061 11:04:15.433675
6062 11:04:15.436678 CH 1, Rank 0
6063 11:04:15.436757 SW Impedance : PASS
6064 11:04:15.440428 DUTY Scan : NO K
6065 11:04:15.444008 ZQ Calibration : PASS
6066 11:04:15.444093 Jitter Meter : NO K
6067 11:04:15.446897 CBT Training : PASS
6068 11:04:15.450358 Write leveling : PASS
6069 11:04:15.450444 RX DQS gating : PASS
6070 11:04:15.453632 RX DQ/DQS(RDDQC) : PASS
6071 11:04:15.456680 TX DQ/DQS : PASS
6072 11:04:15.456756 RX DATLAT : PASS
6073 11:04:15.460067 RX DQ/DQS(Engine): PASS
6074 11:04:15.460171 TX OE : NO K
6075 11:04:15.463717 All Pass.
6076 11:04:15.463820
6077 11:04:15.463911 CH 1, Rank 1
6078 11:04:15.466607 SW Impedance : PASS
6079 11:04:15.466702 DUTY Scan : NO K
6080 11:04:15.470250 ZQ Calibration : PASS
6081 11:04:15.473194 Jitter Meter : NO K
6082 11:04:15.473291 CBT Training : PASS
6083 11:04:15.476777 Write leveling : PASS
6084 11:04:15.480106 RX DQS gating : PASS
6085 11:04:15.480195 RX DQ/DQS(RDDQC) : PASS
6086 11:04:15.483311 TX DQ/DQS : PASS
6087 11:04:15.486238 RX DATLAT : PASS
6088 11:04:15.486347 RX DQ/DQS(Engine): PASS
6089 11:04:15.489547 TX OE : NO K
6090 11:04:15.489647 All Pass.
6091 11:04:15.489731
6092 11:04:15.493023 DramC Write-DBI off
6093 11:04:15.496511 PER_BANK_REFRESH: Hybrid Mode
6094 11:04:15.496615 TX_TRACKING: ON
6095 11:04:15.506989 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6096 11:04:15.510169 [FAST_K] Save calibration result to emmc
6097 11:04:15.513074 dramc_set_vcore_voltage set vcore to 650000
6098 11:04:15.516123 Read voltage for 400, 6
6099 11:04:15.516229 Vio18 = 0
6100 11:04:15.516315 Vcore = 650000
6101 11:04:15.519751 Vdram = 0
6102 11:04:15.519878 Vddq = 0
6103 11:04:15.519979 Vmddr = 0
6104 11:04:15.526319 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6105 11:04:15.529955 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6106 11:04:15.532963 MEM_TYPE=3, freq_sel=20
6107 11:04:15.536084 sv_algorithm_assistance_LP4_800
6108 11:04:15.539956 ============ PULL DRAM RESETB DOWN ============
6109 11:04:15.542842 ========== PULL DRAM RESETB DOWN end =========
6110 11:04:15.549509 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6111 11:04:15.552659 ===================================
6112 11:04:15.556194 LPDDR4 DRAM CONFIGURATION
6113 11:04:15.556304 ===================================
6114 11:04:15.559711 EX_ROW_EN[0] = 0x0
6115 11:04:15.563024 EX_ROW_EN[1] = 0x0
6116 11:04:15.563129 LP4Y_EN = 0x0
6117 11:04:15.566295 WORK_FSP = 0x0
6118 11:04:15.566395 WL = 0x2
6119 11:04:15.569542 RL = 0x2
6120 11:04:15.569616 BL = 0x2
6121 11:04:15.572646 RPST = 0x0
6122 11:04:15.572724 RD_PRE = 0x0
6123 11:04:15.576048 WR_PRE = 0x1
6124 11:04:15.576126 WR_PST = 0x0
6125 11:04:15.579452 DBI_WR = 0x0
6126 11:04:15.579524 DBI_RD = 0x0
6127 11:04:15.582681 OTF = 0x1
6128 11:04:15.586378 ===================================
6129 11:04:15.589295 ===================================
6130 11:04:15.589457 ANA top config
6131 11:04:15.593053 ===================================
6132 11:04:15.596084 DLL_ASYNC_EN = 0
6133 11:04:15.599378 ALL_SLAVE_EN = 1
6134 11:04:15.602402 NEW_RANK_MODE = 1
6135 11:04:15.602508 DLL_IDLE_MODE = 1
6136 11:04:15.606194 LP45_APHY_COMB_EN = 1
6137 11:04:15.609170 TX_ODT_DIS = 1
6138 11:04:15.612422 NEW_8X_MODE = 1
6139 11:04:15.616097 ===================================
6140 11:04:15.619177 ===================================
6141 11:04:15.622692 data_rate = 800
6142 11:04:15.626119 CKR = 1
6143 11:04:15.626211 DQ_P2S_RATIO = 4
6144 11:04:15.629173 ===================================
6145 11:04:15.632674 CA_P2S_RATIO = 4
6146 11:04:15.635666 DQ_CA_OPEN = 0
6147 11:04:15.639314 DQ_SEMI_OPEN = 1
6148 11:04:15.642398 CA_SEMI_OPEN = 1
6149 11:04:15.642496 CA_FULL_RATE = 0
6150 11:04:15.645618 DQ_CKDIV4_EN = 0
6151 11:04:15.648951 CA_CKDIV4_EN = 1
6152 11:04:15.652026 CA_PREDIV_EN = 0
6153 11:04:15.655486 PH8_DLY = 0
6154 11:04:15.659219 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6155 11:04:15.662367 DQ_AAMCK_DIV = 0
6156 11:04:15.662553 CA_AAMCK_DIV = 0
6157 11:04:15.665381 CA_ADMCK_DIV = 4
6158 11:04:15.668767 DQ_TRACK_CA_EN = 0
6159 11:04:15.672145 CA_PICK = 800
6160 11:04:15.675180 CA_MCKIO = 400
6161 11:04:15.678666 MCKIO_SEMI = 400
6162 11:04:15.681741 PLL_FREQ = 3016
6163 11:04:15.681843 DQ_UI_PI_RATIO = 32
6164 11:04:15.684986 CA_UI_PI_RATIO = 32
6165 11:04:15.688351 ===================================
6166 11:04:15.691888 ===================================
6167 11:04:15.695062 memory_type:LPDDR4
6168 11:04:15.698638 GP_NUM : 10
6169 11:04:15.698751 SRAM_EN : 1
6170 11:04:15.701825 MD32_EN : 0
6171 11:04:15.705464 ===================================
6172 11:04:15.708239 [ANA_INIT] >>>>>>>>>>>>>>
6173 11:04:15.708332 <<<<<< [CONFIGURE PHASE]: ANA_TX
6174 11:04:15.711994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6175 11:04:15.715100 ===================================
6176 11:04:15.718027 data_rate = 800,PCW = 0X7400
6177 11:04:15.721670 ===================================
6178 11:04:15.724880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6179 11:04:15.731199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6180 11:04:15.741541 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6181 11:04:15.748267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6182 11:04:15.751398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6183 11:04:15.754376 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6184 11:04:15.758119 [ANA_INIT] flow start
6185 11:04:15.758232 [ANA_INIT] PLL >>>>>>>>
6186 11:04:15.761308 [ANA_INIT] PLL <<<<<<<<
6187 11:04:15.764405 [ANA_INIT] MIDPI >>>>>>>>
6188 11:04:15.764515 [ANA_INIT] MIDPI <<<<<<<<
6189 11:04:15.768185 [ANA_INIT] DLL >>>>>>>>
6190 11:04:15.771137 [ANA_INIT] flow end
6191 11:04:15.774513 ============ LP4 DIFF to SE enter ============
6192 11:04:15.777901 ============ LP4 DIFF to SE exit ============
6193 11:04:15.780916 [ANA_INIT] <<<<<<<<<<<<<
6194 11:04:15.784402 [Flow] Enable top DCM control >>>>>
6195 11:04:15.787585 [Flow] Enable top DCM control <<<<<
6196 11:04:15.791283 Enable DLL master slave shuffle
6197 11:04:15.794699 ==============================================================
6198 11:04:15.797569 Gating Mode config
6199 11:04:15.804586 ==============================================================
6200 11:04:15.804689 Config description:
6201 11:04:15.814229 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6202 11:04:15.821071 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6203 11:04:15.824630 SELPH_MODE 0: By rank 1: By Phase
6204 11:04:15.831329 ==============================================================
6205 11:04:15.834811 GAT_TRACK_EN = 0
6206 11:04:15.838065 RX_GATING_MODE = 2
6207 11:04:15.841161 RX_GATING_TRACK_MODE = 2
6208 11:04:15.844301 SELPH_MODE = 1
6209 11:04:15.847787 PICG_EARLY_EN = 1
6210 11:04:15.851084 VALID_LAT_VALUE = 1
6211 11:04:15.854669 ==============================================================
6212 11:04:15.857985 Enter into Gating configuration >>>>
6213 11:04:15.861269 Exit from Gating configuration <<<<
6214 11:04:15.864292 Enter into DVFS_PRE_config >>>>>
6215 11:04:15.874337 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6216 11:04:15.877931 Exit from DVFS_PRE_config <<<<<
6217 11:04:15.881344 Enter into PICG configuration >>>>
6218 11:04:15.884090 Exit from PICG configuration <<<<
6219 11:04:15.887579 [RX_INPUT] configuration >>>>>
6220 11:04:15.890827 [RX_INPUT] configuration <<<<<
6221 11:04:15.897518 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6222 11:04:15.901191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6223 11:04:15.907642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6224 11:04:15.914189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6225 11:04:15.920769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6226 11:04:15.927248 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6227 11:04:15.930444 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6228 11:04:15.934032 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6229 11:04:15.937606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6230 11:04:15.943792 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6231 11:04:15.947555 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6232 11:04:15.950598 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6233 11:04:15.954091 ===================================
6234 11:04:15.957221 LPDDR4 DRAM CONFIGURATION
6235 11:04:15.960471 ===================================
6236 11:04:15.960558 EX_ROW_EN[0] = 0x0
6237 11:04:15.964069 EX_ROW_EN[1] = 0x0
6238 11:04:15.964139 LP4Y_EN = 0x0
6239 11:04:15.967422 WORK_FSP = 0x0
6240 11:04:15.970470 WL = 0x2
6241 11:04:15.970542 RL = 0x2
6242 11:04:15.973868 BL = 0x2
6243 11:04:15.973964 RPST = 0x0
6244 11:04:15.977263 RD_PRE = 0x0
6245 11:04:15.977337 WR_PRE = 0x1
6246 11:04:15.981220 WR_PST = 0x0
6247 11:04:15.981336 DBI_WR = 0x0
6248 11:04:15.983600 DBI_RD = 0x0
6249 11:04:15.983665 OTF = 0x1
6250 11:04:15.986969 ===================================
6251 11:04:15.990489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6252 11:04:15.997506 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6253 11:04:16.000609 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6254 11:04:16.003867 ===================================
6255 11:04:16.007297 LPDDR4 DRAM CONFIGURATION
6256 11:04:16.010730 ===================================
6257 11:04:16.010816 EX_ROW_EN[0] = 0x10
6258 11:04:16.013967 EX_ROW_EN[1] = 0x0
6259 11:04:16.014049 LP4Y_EN = 0x0
6260 11:04:16.017365 WORK_FSP = 0x0
6261 11:04:16.017455 WL = 0x2
6262 11:04:16.020333 RL = 0x2
6263 11:04:16.020414 BL = 0x2
6264 11:04:16.023959 RPST = 0x0
6265 11:04:16.024042 RD_PRE = 0x0
6266 11:04:16.027531 WR_PRE = 0x1
6267 11:04:16.030295 WR_PST = 0x0
6268 11:04:16.030378 DBI_WR = 0x0
6269 11:04:16.033650 DBI_RD = 0x0
6270 11:04:16.033731 OTF = 0x1
6271 11:04:16.037151 ===================================
6272 11:04:16.043582 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6273 11:04:16.047557 nWR fixed to 30
6274 11:04:16.051153 [ModeRegInit_LP4] CH0 RK0
6275 11:04:16.051241 [ModeRegInit_LP4] CH0 RK1
6276 11:04:16.054012 [ModeRegInit_LP4] CH1 RK0
6277 11:04:16.057239 [ModeRegInit_LP4] CH1 RK1
6278 11:04:16.057321 match AC timing 19
6279 11:04:16.064046 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6280 11:04:16.067070 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6281 11:04:16.070646 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6282 11:04:16.077391 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6283 11:04:16.080485 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6284 11:04:16.080581 ==
6285 11:04:16.084079 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 11:04:16.087731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 11:04:16.087817 ==
6288 11:04:16.093957 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6289 11:04:16.100712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6290 11:04:16.104082 [CA 0] Center 36 (8~64) winsize 57
6291 11:04:16.107193 [CA 1] Center 36 (8~64) winsize 57
6292 11:04:16.110441 [CA 2] Center 36 (8~64) winsize 57
6293 11:04:16.113839 [CA 3] Center 36 (8~64) winsize 57
6294 11:04:16.113944 [CA 4] Center 36 (8~64) winsize 57
6295 11:04:16.117101 [CA 5] Center 36 (8~64) winsize 57
6296 11:04:16.117196
6297 11:04:16.123532 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6298 11:04:16.123619
6299 11:04:16.127195 [CATrainingPosCal] consider 1 rank data
6300 11:04:16.130564 u2DelayCellTimex100 = 270/100 ps
6301 11:04:16.134154 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:04:16.137036 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:04:16.140341 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:04:16.143817 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:04:16.146680 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:04:16.150492 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:04:16.150563
6308 11:04:16.153640 CA PerBit enable=1, Macro0, CA PI delay=36
6309 11:04:16.153712
6310 11:04:16.156824 [CBTSetCACLKResult] CA Dly = 36
6311 11:04:16.160082 CS Dly: 1 (0~32)
6312 11:04:16.160158 ==
6313 11:04:16.163234 Dram Type= 6, Freq= 0, CH_0, rank 1
6314 11:04:16.167120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:04:16.167192 ==
6316 11:04:16.173798 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6317 11:04:16.176828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6318 11:04:16.180457 [CA 0] Center 36 (8~64) winsize 57
6319 11:04:16.183634 [CA 1] Center 36 (8~64) winsize 57
6320 11:04:16.186904 [CA 2] Center 36 (8~64) winsize 57
6321 11:04:16.189840 [CA 3] Center 36 (8~64) winsize 57
6322 11:04:16.193470 [CA 4] Center 36 (8~64) winsize 57
6323 11:04:16.197139 [CA 5] Center 36 (8~64) winsize 57
6324 11:04:16.197238
6325 11:04:16.200537 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6326 11:04:16.200604
6327 11:04:16.203521 [CATrainingPosCal] consider 2 rank data
6328 11:04:16.206720 u2DelayCellTimex100 = 270/100 ps
6329 11:04:16.210075 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 11:04:16.213117 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:04:16.219969 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:04:16.223128 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:04:16.226705 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 11:04:16.229576 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 11:04:16.229662
6336 11:04:16.233239 CA PerBit enable=1, Macro0, CA PI delay=36
6337 11:04:16.233321
6338 11:04:16.236209 [CBTSetCACLKResult] CA Dly = 36
6339 11:04:16.236288 CS Dly: 1 (0~32)
6340 11:04:16.236365
6341 11:04:16.239824 ----->DramcWriteLeveling(PI) begin...
6342 11:04:16.243319 ==
6343 11:04:16.246304 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 11:04:16.249489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 11:04:16.249571 ==
6346 11:04:16.252887 Write leveling (Byte 0): 40 => 8
6347 11:04:16.256792 Write leveling (Byte 1): 40 => 8
6348 11:04:16.259816 DramcWriteLeveling(PI) end<-----
6349 11:04:16.259902
6350 11:04:16.259979 ==
6351 11:04:16.262677 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 11:04:16.266038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 11:04:16.266161 ==
6354 11:04:16.269399 [Gating] SW mode calibration
6355 11:04:16.276616 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6356 11:04:16.283140 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6357 11:04:16.286390 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6358 11:04:16.289542 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6359 11:04:16.295794 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 11:04:16.299296 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 11:04:16.302461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 11:04:16.305972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 11:04:16.312575 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 11:04:16.316247 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 11:04:16.319453 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6366 11:04:16.322491 Total UI for P1: 0, mck2ui 16
6367 11:04:16.326012 best dqsien dly found for B0: ( 0, 14, 24)
6368 11:04:16.329107 Total UI for P1: 0, mck2ui 16
6369 11:04:16.332599 best dqsien dly found for B1: ( 0, 14, 24)
6370 11:04:16.335591 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6371 11:04:16.342628 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6372 11:04:16.342735
6373 11:04:16.345687 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6374 11:04:16.348668 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6375 11:04:16.352302 [Gating] SW calibration Done
6376 11:04:16.352373 ==
6377 11:04:16.355227 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 11:04:16.358724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 11:04:16.358793 ==
6380 11:04:16.362222 RX Vref Scan: 0
6381 11:04:16.362301
6382 11:04:16.362358 RX Vref 0 -> 0, step: 1
6383 11:04:16.362410
6384 11:04:16.365347 RX Delay -410 -> 252, step: 16
6385 11:04:16.371679 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6386 11:04:16.375523 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6387 11:04:16.378340 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6388 11:04:16.381938 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6389 11:04:16.385493 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6390 11:04:16.392258 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6391 11:04:16.395630 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6392 11:04:16.398711 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6393 11:04:16.405330 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6394 11:04:16.408282 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6395 11:04:16.412000 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6396 11:04:16.414944 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6397 11:04:16.421618 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6398 11:04:16.424834 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6399 11:04:16.428128 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6400 11:04:16.431436 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6401 11:04:16.434879 ==
6402 11:04:16.438424 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 11:04:16.441299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 11:04:16.441368 ==
6405 11:04:16.441425 DQS Delay:
6406 11:04:16.445089 DQS0 = 59, DQS1 = 59
6407 11:04:16.445151 DQM Delay:
6408 11:04:16.448131 DQM0 = 18, DQM1 = 10
6409 11:04:16.448192 DQ Delay:
6410 11:04:16.451678 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6411 11:04:16.455024 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6412 11:04:16.458375 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6413 11:04:16.461430 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6414 11:04:16.461531
6415 11:04:16.461619
6416 11:04:16.461701 ==
6417 11:04:16.464714 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 11:04:16.468244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 11:04:16.468316 ==
6420 11:04:16.468371
6421 11:04:16.468422
6422 11:04:16.471405 TX Vref Scan disable
6423 11:04:16.471471 == TX Byte 0 ==
6424 11:04:16.478457 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 11:04:16.481685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 11:04:16.481777 == TX Byte 1 ==
6427 11:04:16.487819 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 11:04:16.491121 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 11:04:16.491196 ==
6430 11:04:16.494774 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 11:04:16.497821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 11:04:16.497890 ==
6433 11:04:16.497947
6434 11:04:16.497998
6435 11:04:16.501286 TX Vref Scan disable
6436 11:04:16.501352 == TX Byte 0 ==
6437 11:04:16.508111 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6438 11:04:16.511045 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6439 11:04:16.511133 == TX Byte 1 ==
6440 11:04:16.517637 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6441 11:04:16.521464 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6442 11:04:16.521553
6443 11:04:16.521632 [DATLAT]
6444 11:04:16.524279 Freq=400, CH0 RK0
6445 11:04:16.524359
6446 11:04:16.524436 DATLAT Default: 0xf
6447 11:04:16.527968 0, 0xFFFF, sum = 0
6448 11:04:16.528075 1, 0xFFFF, sum = 0
6449 11:04:16.530963 2, 0xFFFF, sum = 0
6450 11:04:16.531046 3, 0xFFFF, sum = 0
6451 11:04:16.534257 4, 0xFFFF, sum = 0
6452 11:04:16.534352 5, 0xFFFF, sum = 0
6453 11:04:16.537610 6, 0xFFFF, sum = 0
6454 11:04:16.537691 7, 0xFFFF, sum = 0
6455 11:04:16.541144 8, 0xFFFF, sum = 0
6456 11:04:16.541228 9, 0xFFFF, sum = 0
6457 11:04:16.544041 10, 0xFFFF, sum = 0
6458 11:04:16.547551 11, 0xFFFF, sum = 0
6459 11:04:16.547636 12, 0xFFFF, sum = 0
6460 11:04:16.550727 13, 0x0, sum = 1
6461 11:04:16.550809 14, 0x0, sum = 2
6462 11:04:16.554004 15, 0x0, sum = 3
6463 11:04:16.554138 16, 0x0, sum = 4
6464 11:04:16.554232 best_step = 14
6465 11:04:16.554322
6466 11:04:16.557177 ==
6467 11:04:16.561050 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 11:04:16.564670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 11:04:16.564759 ==
6470 11:04:16.564838 RX Vref Scan: 1
6471 11:04:16.564911
6472 11:04:16.567253 RX Vref 0 -> 0, step: 1
6473 11:04:16.567332
6474 11:04:16.570826 RX Delay -359 -> 252, step: 8
6475 11:04:16.570906
6476 11:04:16.574397 Set Vref, RX VrefLevel [Byte0]: 60
6477 11:04:16.577236 [Byte1]: 49
6478 11:04:16.580989
6479 11:04:16.581073 Final RX Vref Byte 0 = 60 to rank0
6480 11:04:16.584605 Final RX Vref Byte 1 = 49 to rank0
6481 11:04:16.587900 Final RX Vref Byte 0 = 60 to rank1
6482 11:04:16.591025 Final RX Vref Byte 1 = 49 to rank1==
6483 11:04:16.594230 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 11:04:16.600878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 11:04:16.600979 ==
6486 11:04:16.601061 DQS Delay:
6487 11:04:16.604444 DQS0 = 60, DQS1 = 68
6488 11:04:16.604526 DQM Delay:
6489 11:04:16.604603 DQM0 = 14, DQM1 = 13
6490 11:04:16.607696 DQ Delay:
6491 11:04:16.611070 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6492 11:04:16.614492 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6493 11:04:16.614568 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6494 11:04:16.617644 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6495 11:04:16.621075
6496 11:04:16.621146
6497 11:04:16.627494 [DQSOSCAuto] RK0, (LSB)MR18= 0x908e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6498 11:04:16.631172 CH0 RK0: MR19=C0C, MR18=908E
6499 11:04:16.637653 CH0_RK0: MR19=0xC0C, MR18=0x908E, DQSOSC=391, MR23=63, INC=386, DEC=257
6500 11:04:16.637744 ==
6501 11:04:16.640715 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 11:04:16.643993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 11:04:16.644062 ==
6504 11:04:16.647470 [Gating] SW mode calibration
6505 11:04:16.654259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6506 11:04:16.660726 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6507 11:04:16.664266 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 11:04:16.667544 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 11:04:16.674201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 11:04:16.677545 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 11:04:16.680667 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 11:04:16.683969 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 11:04:16.690897 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 11:04:16.694655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 11:04:16.697556 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6516 11:04:16.700616 Total UI for P1: 0, mck2ui 16
6517 11:04:16.704030 best dqsien dly found for B0: ( 0, 14, 24)
6518 11:04:16.707312 Total UI for P1: 0, mck2ui 16
6519 11:04:16.710821 best dqsien dly found for B1: ( 0, 14, 24)
6520 11:04:16.714345 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6521 11:04:16.720695 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6522 11:04:16.720784
6523 11:04:16.724105 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6524 11:04:16.727642 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6525 11:04:16.730572 [Gating] SW calibration Done
6526 11:04:16.730637 ==
6527 11:04:16.734236 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 11:04:16.737143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 11:04:16.737205 ==
6530 11:04:16.740802 RX Vref Scan: 0
6531 11:04:16.740866
6532 11:04:16.740921 RX Vref 0 -> 0, step: 1
6533 11:04:16.740971
6534 11:04:16.743992 RX Delay -410 -> 252, step: 16
6535 11:04:16.747467 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6536 11:04:16.753550 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6537 11:04:16.757070 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6538 11:04:16.760212 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6539 11:04:16.763558 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6540 11:04:16.770918 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6541 11:04:16.773410 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6542 11:04:16.777012 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6543 11:04:16.780720 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6544 11:04:16.787104 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6545 11:04:16.790837 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6546 11:04:16.793530 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6547 11:04:16.797116 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6548 11:04:16.803657 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6549 11:04:16.806972 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6550 11:04:16.810154 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6551 11:04:16.810261 ==
6552 11:04:16.813836 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 11:04:16.820216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 11:04:16.820316 ==
6555 11:04:16.820445 DQS Delay:
6556 11:04:16.823789 DQS0 = 59, DQS1 = 59
6557 11:04:16.823891 DQM Delay:
6558 11:04:16.823975 DQM0 = 15, DQM1 = 10
6559 11:04:16.827073 DQ Delay:
6560 11:04:16.830502 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6561 11:04:16.833521 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6562 11:04:16.833625 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6563 11:04:16.840599 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6564 11:04:16.840689
6565 11:04:16.840751
6566 11:04:16.840805 ==
6567 11:04:16.843329 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 11:04:16.846991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 11:04:16.847070 ==
6570 11:04:16.847129
6571 11:04:16.847182
6572 11:04:16.850289 TX Vref Scan disable
6573 11:04:16.850367 == TX Byte 0 ==
6574 11:04:16.853607 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6575 11:04:16.860441 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6576 11:04:16.860536 == TX Byte 1 ==
6577 11:04:16.863156 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6578 11:04:16.870017 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6579 11:04:16.870171 ==
6580 11:04:16.873091 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 11:04:16.876662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 11:04:16.876742 ==
6583 11:04:16.876801
6584 11:04:16.876854
6585 11:04:16.879666 TX Vref Scan disable
6586 11:04:16.879743 == TX Byte 0 ==
6587 11:04:16.886396 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6588 11:04:16.889805 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6589 11:04:16.889890 == TX Byte 1 ==
6590 11:04:16.893172 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6591 11:04:16.900049 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6592 11:04:16.900144
6593 11:04:16.900223 [DATLAT]
6594 11:04:16.903098 Freq=400, CH0 RK1
6595 11:04:16.903180
6596 11:04:16.903258 DATLAT Default: 0xe
6597 11:04:16.906533 0, 0xFFFF, sum = 0
6598 11:04:16.906615 1, 0xFFFF, sum = 0
6599 11:04:16.909668 2, 0xFFFF, sum = 0
6600 11:04:16.909750 3, 0xFFFF, sum = 0
6601 11:04:16.913158 4, 0xFFFF, sum = 0
6602 11:04:16.913240 5, 0xFFFF, sum = 0
6603 11:04:16.916445 6, 0xFFFF, sum = 0
6604 11:04:16.916525 7, 0xFFFF, sum = 0
6605 11:04:16.919682 8, 0xFFFF, sum = 0
6606 11:04:16.919761 9, 0xFFFF, sum = 0
6607 11:04:16.922936 10, 0xFFFF, sum = 0
6608 11:04:16.923007 11, 0xFFFF, sum = 0
6609 11:04:16.926414 12, 0xFFFF, sum = 0
6610 11:04:16.926489 13, 0x0, sum = 1
6611 11:04:16.929375 14, 0x0, sum = 2
6612 11:04:16.929437 15, 0x0, sum = 3
6613 11:04:16.932937 16, 0x0, sum = 4
6614 11:04:16.933000 best_step = 14
6615 11:04:16.933051
6616 11:04:16.933106 ==
6617 11:04:16.936124 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 11:04:16.942675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 11:04:16.942773 ==
6620 11:04:16.942867 RX Vref Scan: 0
6621 11:04:16.942963
6622 11:04:16.946266 RX Vref 0 -> 0, step: 1
6623 11:04:16.946362
6624 11:04:16.949305 RX Delay -359 -> 252, step: 8
6625 11:04:16.956018 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6626 11:04:16.959436 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6627 11:04:16.962634 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6628 11:04:16.966266 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6629 11:04:16.973066 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6630 11:04:16.976128 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6631 11:04:16.979363 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6632 11:04:16.982983 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6633 11:04:16.989112 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6634 11:04:16.992705 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6635 11:04:16.996198 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6636 11:04:16.999484 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6637 11:04:17.006370 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6638 11:04:17.009284 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6639 11:04:17.012183 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6640 11:04:17.019239 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6641 11:04:17.019347 ==
6642 11:04:17.022138 Dram Type= 6, Freq= 0, CH_0, rank 1
6643 11:04:17.025904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 11:04:17.026014 ==
6645 11:04:17.026115 DQS Delay:
6646 11:04:17.028849 DQS0 = 60, DQS1 = 68
6647 11:04:17.028927 DQM Delay:
6648 11:04:17.032458 DQM0 = 11, DQM1 = 13
6649 11:04:17.032566 DQ Delay:
6650 11:04:17.035726 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6651 11:04:17.039165 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6652 11:04:17.042464 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6653 11:04:17.045778 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6654 11:04:17.045867
6655 11:04:17.045955
6656 11:04:17.052372 [DQSOSCAuto] RK1, (LSB)MR18= 0xd68c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 383 ps
6657 11:04:17.055602 CH0 RK1: MR19=C0C, MR18=D68C
6658 11:04:17.062416 CH0_RK1: MR19=0xC0C, MR18=0xD68C, DQSOSC=383, MR23=63, INC=402, DEC=268
6659 11:04:17.065597 [RxdqsGatingPostProcess] freq 400
6660 11:04:17.068813 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6661 11:04:17.072177 best DQS0 dly(2T, 0.5T) = (0, 10)
6662 11:04:17.075534 best DQS1 dly(2T, 0.5T) = (0, 10)
6663 11:04:17.078873 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6664 11:04:17.082535 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6665 11:04:17.085997 best DQS0 dly(2T, 0.5T) = (0, 10)
6666 11:04:17.088867 best DQS1 dly(2T, 0.5T) = (0, 10)
6667 11:04:17.092468 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6668 11:04:17.095382 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6669 11:04:17.099158 Pre-setting of DQS Precalculation
6670 11:04:17.102607 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6671 11:04:17.105396 ==
6672 11:04:17.109052 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 11:04:17.112079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 11:04:17.112155 ==
6675 11:04:17.115653 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6676 11:04:17.122511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6677 11:04:17.125536 [CA 0] Center 36 (8~64) winsize 57
6678 11:04:17.129042 [CA 1] Center 36 (8~64) winsize 57
6679 11:04:17.131983 [CA 2] Center 36 (8~64) winsize 57
6680 11:04:17.135067 [CA 3] Center 36 (8~64) winsize 57
6681 11:04:17.138572 [CA 4] Center 36 (8~64) winsize 57
6682 11:04:17.142037 [CA 5] Center 36 (8~64) winsize 57
6683 11:04:17.142162
6684 11:04:17.145233 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6685 11:04:17.145370
6686 11:04:17.148753 [CATrainingPosCal] consider 1 rank data
6687 11:04:17.152111 u2DelayCellTimex100 = 270/100 ps
6688 11:04:17.155589 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:04:17.158679 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:04:17.162266 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:04:17.165347 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:04:17.168851 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:04:17.175566 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:04:17.175673
6695 11:04:17.178353 CA PerBit enable=1, Macro0, CA PI delay=36
6696 11:04:17.178433
6697 11:04:17.181879 [CBTSetCACLKResult] CA Dly = 36
6698 11:04:17.181982 CS Dly: 1 (0~32)
6699 11:04:17.182045 ==
6700 11:04:17.185393 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 11:04:17.188595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:04:17.192064 ==
6703 11:04:17.194937 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6704 11:04:17.201473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6705 11:04:17.205032 [CA 0] Center 36 (8~64) winsize 57
6706 11:04:17.208573 [CA 1] Center 36 (8~64) winsize 57
6707 11:04:17.211719 [CA 2] Center 36 (8~64) winsize 57
6708 11:04:17.215013 [CA 3] Center 36 (8~64) winsize 57
6709 11:04:17.218543 [CA 4] Center 36 (8~64) winsize 57
6710 11:04:17.221341 [CA 5] Center 36 (8~64) winsize 57
6711 11:04:17.221426
6712 11:04:17.224902 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6713 11:04:17.224981
6714 11:04:17.228438 [CATrainingPosCal] consider 2 rank data
6715 11:04:17.231667 u2DelayCellTimex100 = 270/100 ps
6716 11:04:17.234659 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 11:04:17.238356 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:04:17.241559 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:04:17.245328 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:04:17.248129 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 11:04:17.251142 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 11:04:17.251226
6723 11:04:17.258292 CA PerBit enable=1, Macro0, CA PI delay=36
6724 11:04:17.258386
6725 11:04:17.258447 [CBTSetCACLKResult] CA Dly = 36
6726 11:04:17.261201 CS Dly: 1 (0~32)
6727 11:04:17.261278
6728 11:04:17.264959 ----->DramcWriteLeveling(PI) begin...
6729 11:04:17.265029 ==
6730 11:04:17.268341 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 11:04:17.271120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 11:04:17.271200 ==
6733 11:04:17.274756 Write leveling (Byte 0): 40 => 8
6734 11:04:17.278136 Write leveling (Byte 1): 40 => 8
6735 11:04:17.281549 DramcWriteLeveling(PI) end<-----
6736 11:04:17.281629
6737 11:04:17.281688 ==
6738 11:04:17.284332 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 11:04:17.287821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 11:04:17.291301 ==
6741 11:04:17.291421 [Gating] SW mode calibration
6742 11:04:17.297743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6743 11:04:17.304289 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6744 11:04:17.307849 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6745 11:04:17.314162 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6746 11:04:17.317495 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 11:04:17.320980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 11:04:17.327703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 11:04:17.330879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 11:04:17.334302 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 11:04:17.340861 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 11:04:17.344574 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6753 11:04:17.347473 Total UI for P1: 0, mck2ui 16
6754 11:04:17.350596 best dqsien dly found for B0: ( 0, 14, 24)
6755 11:04:17.354056 Total UI for P1: 0, mck2ui 16
6756 11:04:17.357380 best dqsien dly found for B1: ( 0, 14, 24)
6757 11:04:17.361081 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6758 11:04:17.364361 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6759 11:04:17.364446
6760 11:04:17.367355 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6761 11:04:17.370844 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6762 11:04:17.374426 [Gating] SW calibration Done
6763 11:04:17.374508 ==
6764 11:04:17.377328 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 11:04:17.380803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 11:04:17.383897 ==
6767 11:04:17.383977 RX Vref Scan: 0
6768 11:04:17.384035
6769 11:04:17.387554 RX Vref 0 -> 0, step: 1
6770 11:04:17.387631
6771 11:04:17.390918 RX Delay -410 -> 252, step: 16
6772 11:04:17.394127 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6773 11:04:17.397832 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6774 11:04:17.400646 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6775 11:04:17.407528 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6776 11:04:17.411000 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6777 11:04:17.413829 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6778 11:04:17.417553 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6779 11:04:17.423796 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6780 11:04:17.427448 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6781 11:04:17.430717 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6782 11:04:17.433816 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6783 11:04:17.440745 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6784 11:04:17.444189 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6785 11:04:17.447142 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6786 11:04:17.450972 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6787 11:04:17.457205 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6788 11:04:17.457299 ==
6789 11:04:17.460603 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 11:04:17.464085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 11:04:17.464170 ==
6792 11:04:17.464229 DQS Delay:
6793 11:04:17.467173 DQS0 = 51, DQS1 = 67
6794 11:04:17.467250 DQM Delay:
6795 11:04:17.470944 DQM0 = 12, DQM1 = 17
6796 11:04:17.471024 DQ Delay:
6797 11:04:17.474096 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6798 11:04:17.477316 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6799 11:04:17.480496 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6800 11:04:17.483760 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6801 11:04:17.483839
6802 11:04:17.483897
6803 11:04:17.483951 ==
6804 11:04:17.487216 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 11:04:17.490892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 11:04:17.490972 ==
6807 11:04:17.491031
6808 11:04:17.493945
6809 11:04:17.494021 TX Vref Scan disable
6810 11:04:17.497533 == TX Byte 0 ==
6811 11:04:17.500374 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 11:04:17.503587 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 11:04:17.507463 == TX Byte 1 ==
6814 11:04:17.510808 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 11:04:17.513994 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 11:04:17.514076 ==
6817 11:04:17.516958 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 11:04:17.520247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 11:04:17.520328 ==
6820 11:04:17.523424
6821 11:04:17.523521
6822 11:04:17.523581 TX Vref Scan disable
6823 11:04:17.527052 == TX Byte 0 ==
6824 11:04:17.530037 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 11:04:17.533609 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 11:04:17.536941 == TX Byte 1 ==
6827 11:04:17.540250 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 11:04:17.543472 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 11:04:17.543551
6830 11:04:17.543609 [DATLAT]
6831 11:04:17.547064 Freq=400, CH1 RK0
6832 11:04:17.547142
6833 11:04:17.550264 DATLAT Default: 0xf
6834 11:04:17.550340 0, 0xFFFF, sum = 0
6835 11:04:17.553663 1, 0xFFFF, sum = 0
6836 11:04:17.553741 2, 0xFFFF, sum = 0
6837 11:04:17.556327 3, 0xFFFF, sum = 0
6838 11:04:17.556404 4, 0xFFFF, sum = 0
6839 11:04:17.560003 5, 0xFFFF, sum = 0
6840 11:04:17.560084 6, 0xFFFF, sum = 0
6841 11:04:17.563437 7, 0xFFFF, sum = 0
6842 11:04:17.563518 8, 0xFFFF, sum = 0
6843 11:04:17.566719 9, 0xFFFF, sum = 0
6844 11:04:17.566798 10, 0xFFFF, sum = 0
6845 11:04:17.570067 11, 0xFFFF, sum = 0
6846 11:04:17.570189 12, 0xFFFF, sum = 0
6847 11:04:17.573505 13, 0x0, sum = 1
6848 11:04:17.573584 14, 0x0, sum = 2
6849 11:04:17.576507 15, 0x0, sum = 3
6850 11:04:17.576590 16, 0x0, sum = 4
6851 11:04:17.580260 best_step = 14
6852 11:04:17.580340
6853 11:04:17.580399 ==
6854 11:04:17.583163 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 11:04:17.586586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 11:04:17.586669 ==
6857 11:04:17.590276 RX Vref Scan: 1
6858 11:04:17.590355
6859 11:04:17.590414 RX Vref 0 -> 0, step: 1
6860 11:04:17.590467
6861 11:04:17.593208 RX Delay -375 -> 252, step: 8
6862 11:04:17.593285
6863 11:04:17.596649 Set Vref, RX VrefLevel [Byte0]: 55
6864 11:04:17.600298 [Byte1]: 51
6865 11:04:17.604352
6866 11:04:17.604438 Final RX Vref Byte 0 = 55 to rank0
6867 11:04:17.607831 Final RX Vref Byte 1 = 51 to rank0
6868 11:04:17.610874 Final RX Vref Byte 0 = 55 to rank1
6869 11:04:17.614345 Final RX Vref Byte 1 = 51 to rank1==
6870 11:04:17.617989 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 11:04:17.624026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 11:04:17.624126 ==
6873 11:04:17.624186 DQS Delay:
6874 11:04:17.627310 DQS0 = 56, DQS1 = 64
6875 11:04:17.627389 DQM Delay:
6876 11:04:17.627448 DQM0 = 12, DQM1 = 11
6877 11:04:17.630976 DQ Delay:
6878 11:04:17.634326 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6879 11:04:17.634409 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6880 11:04:17.637417 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6881 11:04:17.641370 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6882 11:04:17.644333
6883 11:04:17.644414
6884 11:04:17.650517 [DQSOSCAuto] RK0, (LSB)MR18= 0x6678, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 396 ps
6885 11:04:17.653871 CH1 RK0: MR19=C0C, MR18=6678
6886 11:04:17.660519 CH1_RK0: MR19=0xC0C, MR18=0x6678, DQSOSC=394, MR23=63, INC=380, DEC=253
6887 11:04:17.660621 ==
6888 11:04:17.664063 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 11:04:17.667420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 11:04:17.667504 ==
6891 11:04:17.670784 [Gating] SW mode calibration
6892 11:04:17.677602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6893 11:04:17.683763 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6894 11:04:17.687472 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6895 11:04:17.690297 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6896 11:04:17.697261 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 11:04:17.700160 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 11:04:17.703958 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 11:04:17.710377 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 11:04:17.713492 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 11:04:17.716936 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 11:04:17.723601 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6903 11:04:17.723697 Total UI for P1: 0, mck2ui 16
6904 11:04:17.727070 best dqsien dly found for B0: ( 0, 14, 24)
6905 11:04:17.730361 Total UI for P1: 0, mck2ui 16
6906 11:04:17.733655 best dqsien dly found for B1: ( 0, 14, 24)
6907 11:04:17.736837 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6908 11:04:17.744103 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6909 11:04:17.744199
6910 11:04:17.746782 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6911 11:04:17.750072 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6912 11:04:17.753568 [Gating] SW calibration Done
6913 11:04:17.753645 ==
6914 11:04:17.757066 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 11:04:17.760509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 11:04:17.760592 ==
6917 11:04:17.763507 RX Vref Scan: 0
6918 11:04:17.763587
6919 11:04:17.763645 RX Vref 0 -> 0, step: 1
6920 11:04:17.763700
6921 11:04:17.767296 RX Delay -410 -> 252, step: 16
6922 11:04:17.770220 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6923 11:04:17.777122 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6924 11:04:17.780056 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6925 11:04:17.783685 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6926 11:04:17.787408 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6927 11:04:17.793839 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6928 11:04:17.797083 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6929 11:04:17.800414 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6930 11:04:17.803550 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6931 11:04:17.810437 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6932 11:04:17.813311 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6933 11:04:17.817071 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6934 11:04:17.820118 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6935 11:04:17.826874 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6936 11:04:17.830086 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6937 11:04:17.833154 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6938 11:04:17.833237 ==
6939 11:04:17.836406 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 11:04:17.843273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 11:04:17.843369 ==
6942 11:04:17.843428 DQS Delay:
6943 11:04:17.846601 DQS0 = 59, DQS1 = 59
6944 11:04:17.846679 DQM Delay:
6945 11:04:17.850239 DQM0 = 19, DQM1 = 14
6946 11:04:17.850317 DQ Delay:
6947 11:04:17.852842 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6948 11:04:17.856666 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6949 11:04:17.859500 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6950 11:04:17.863190 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6951 11:04:17.863274
6952 11:04:17.863333
6953 11:04:17.863386 ==
6954 11:04:17.866070 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 11:04:17.870142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 11:04:17.870254 ==
6957 11:04:17.870315
6958 11:04:17.870384
6959 11:04:17.873453 TX Vref Scan disable
6960 11:04:17.873532 == TX Byte 0 ==
6961 11:04:17.879873 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6962 11:04:17.882906 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6963 11:04:17.882987 == TX Byte 1 ==
6964 11:04:17.886611 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6965 11:04:17.892926 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6966 11:04:17.893019 ==
6967 11:04:17.896686 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 11:04:17.899573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 11:04:17.899654 ==
6970 11:04:17.899714
6971 11:04:17.899767
6972 11:04:17.903121 TX Vref Scan disable
6973 11:04:17.903199 == TX Byte 0 ==
6974 11:04:17.909380 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6975 11:04:17.912994 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6976 11:04:17.913080 == TX Byte 1 ==
6977 11:04:17.919766 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6978 11:04:17.922632 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6979 11:04:17.922714
6980 11:04:17.922799 [DATLAT]
6981 11:04:17.926135 Freq=400, CH1 RK1
6982 11:04:17.926249
6983 11:04:17.926323 DATLAT Default: 0xe
6984 11:04:17.929737 0, 0xFFFF, sum = 0
6985 11:04:17.929816 1, 0xFFFF, sum = 0
6986 11:04:17.932664 2, 0xFFFF, sum = 0
6987 11:04:17.932743 3, 0xFFFF, sum = 0
6988 11:04:17.936187 4, 0xFFFF, sum = 0
6989 11:04:17.936267 5, 0xFFFF, sum = 0
6990 11:04:17.939799 6, 0xFFFF, sum = 0
6991 11:04:17.939878 7, 0xFFFF, sum = 0
6992 11:04:17.942704 8, 0xFFFF, sum = 0
6993 11:04:17.942781 9, 0xFFFF, sum = 0
6994 11:04:17.946077 10, 0xFFFF, sum = 0
6995 11:04:17.946198 11, 0xFFFF, sum = 0
6996 11:04:17.949269 12, 0xFFFF, sum = 0
6997 11:04:17.949348 13, 0x0, sum = 1
6998 11:04:17.952786 14, 0x0, sum = 2
6999 11:04:17.952891 15, 0x0, sum = 3
7000 11:04:17.956225 16, 0x0, sum = 4
7001 11:04:17.956304 best_step = 14
7002 11:04:17.956363
7003 11:04:17.956417 ==
7004 11:04:17.959696 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 11:04:17.966383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 11:04:17.966482 ==
7007 11:04:17.966542 RX Vref Scan: 0
7008 11:04:17.966595
7009 11:04:17.969287 RX Vref 0 -> 0, step: 1
7010 11:04:17.969364
7011 11:04:17.972815 RX Delay -359 -> 252, step: 8
7012 11:04:17.979094 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7013 11:04:17.982714 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7014 11:04:17.985625 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7015 11:04:17.989266 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7016 11:04:17.995663 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7017 11:04:17.999129 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7018 11:04:18.002398 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7019 11:04:18.005470 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7020 11:04:18.012355 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7021 11:04:18.015750 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7022 11:04:18.019041 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7023 11:04:18.022277 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7024 11:04:18.029281 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7025 11:04:18.032354 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7026 11:04:18.035271 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7027 11:04:18.042351 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7028 11:04:18.042449 ==
7029 11:04:18.045212 Dram Type= 6, Freq= 0, CH_1, rank 1
7030 11:04:18.048892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7031 11:04:18.048974 ==
7032 11:04:18.049033 DQS Delay:
7033 11:04:18.051738 DQS0 = 60, DQS1 = 64
7034 11:04:18.051814 DQM Delay:
7035 11:04:18.055473 DQM0 = 12, DQM1 = 10
7036 11:04:18.055575 DQ Delay:
7037 11:04:18.058681 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7038 11:04:18.061909 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7039 11:04:18.065306 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7040 11:04:18.068749 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7041 11:04:18.068845
7042 11:04:18.068940
7043 11:04:18.074978 [DQSOSCAuto] RK1, (LSB)MR18= 0x88b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 392 ps
7044 11:04:18.078519 CH1 RK1: MR19=C0C, MR18=88B7
7045 11:04:18.085220 CH1_RK1: MR19=0xC0C, MR18=0x88B7, DQSOSC=387, MR23=63, INC=394, DEC=262
7046 11:04:18.088303 [RxdqsGatingPostProcess] freq 400
7047 11:04:18.094632 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7048 11:04:18.098204 best DQS0 dly(2T, 0.5T) = (0, 10)
7049 11:04:18.101680 best DQS1 dly(2T, 0.5T) = (0, 10)
7050 11:04:18.104626 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7051 11:04:18.104707 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7052 11:04:18.108270 best DQS0 dly(2T, 0.5T) = (0, 10)
7053 11:04:18.111556 best DQS1 dly(2T, 0.5T) = (0, 10)
7054 11:04:18.114646 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7055 11:04:18.118252 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7056 11:04:18.121475 Pre-setting of DQS Precalculation
7057 11:04:18.128372 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7058 11:04:18.134278 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7059 11:04:18.140992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7060 11:04:18.141117
7061 11:04:18.141208
7062 11:04:18.144315 [Calibration Summary] 800 Mbps
7063 11:04:18.144408 CH 0, Rank 0
7064 11:04:18.147771 SW Impedance : PASS
7065 11:04:18.150798 DUTY Scan : NO K
7066 11:04:18.150890 ZQ Calibration : PASS
7067 11:04:18.154573 Jitter Meter : NO K
7068 11:04:18.157364 CBT Training : PASS
7069 11:04:18.157454 Write leveling : PASS
7070 11:04:18.160654 RX DQS gating : PASS
7071 11:04:18.164130 RX DQ/DQS(RDDQC) : PASS
7072 11:04:18.164234 TX DQ/DQS : PASS
7073 11:04:18.167358 RX DATLAT : PASS
7074 11:04:18.170634 RX DQ/DQS(Engine): PASS
7075 11:04:18.170715 TX OE : NO K
7076 11:04:18.170774 All Pass.
7077 11:04:18.174160
7078 11:04:18.174254 CH 0, Rank 1
7079 11:04:18.177415 SW Impedance : PASS
7080 11:04:18.177492 DUTY Scan : NO K
7081 11:04:18.180954 ZQ Calibration : PASS
7082 11:04:18.181031 Jitter Meter : NO K
7083 11:04:18.184407 CBT Training : PASS
7084 11:04:18.187930 Write leveling : NO K
7085 11:04:18.188031 RX DQS gating : PASS
7086 11:04:18.191090 RX DQ/DQS(RDDQC) : PASS
7087 11:04:18.193827 TX DQ/DQS : PASS
7088 11:04:18.193922 RX DATLAT : PASS
7089 11:04:18.197420 RX DQ/DQS(Engine): PASS
7090 11:04:18.201193 TX OE : NO K
7091 11:04:18.201279 All Pass.
7092 11:04:18.201338
7093 11:04:18.201392 CH 1, Rank 0
7094 11:04:18.204032 SW Impedance : PASS
7095 11:04:18.207490 DUTY Scan : NO K
7096 11:04:18.207572 ZQ Calibration : PASS
7097 11:04:18.210551 Jitter Meter : NO K
7098 11:04:18.214226 CBT Training : PASS
7099 11:04:18.214308 Write leveling : PASS
7100 11:04:18.216952 RX DQS gating : PASS
7101 11:04:18.220493 RX DQ/DQS(RDDQC) : PASS
7102 11:04:18.220575 TX DQ/DQS : PASS
7103 11:04:18.223501 RX DATLAT : PASS
7104 11:04:18.227148 RX DQ/DQS(Engine): PASS
7105 11:04:18.227228 TX OE : NO K
7106 11:04:18.230473 All Pass.
7107 11:04:18.230549
7108 11:04:18.230607 CH 1, Rank 1
7109 11:04:18.233602 SW Impedance : PASS
7110 11:04:18.233679 DUTY Scan : NO K
7111 11:04:18.237581 ZQ Calibration : PASS
7112 11:04:18.237659 Jitter Meter : NO K
7113 11:04:18.240708 CBT Training : PASS
7114 11:04:18.243956 Write leveling : NO K
7115 11:04:18.244035 RX DQS gating : PASS
7116 11:04:18.246944 RX DQ/DQS(RDDQC) : PASS
7117 11:04:18.250761 TX DQ/DQS : PASS
7118 11:04:18.250840 RX DATLAT : PASS
7119 11:04:18.253912 RX DQ/DQS(Engine): PASS
7120 11:04:18.257181 TX OE : NO K
7121 11:04:18.257261 All Pass.
7122 11:04:18.257319
7123 11:04:18.260530 DramC Write-DBI off
7124 11:04:18.260607 PER_BANK_REFRESH: Hybrid Mode
7125 11:04:18.263568 TX_TRACKING: ON
7126 11:04:18.273709 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7127 11:04:18.277189 [FAST_K] Save calibration result to emmc
7128 11:04:18.280368 dramc_set_vcore_voltage set vcore to 725000
7129 11:04:18.280456 Read voltage for 1600, 0
7130 11:04:18.283710 Vio18 = 0
7131 11:04:18.283815 Vcore = 725000
7132 11:04:18.283942 Vdram = 0
7133 11:04:18.286662 Vddq = 0
7134 11:04:18.286763 Vmddr = 0
7135 11:04:18.293462 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7136 11:04:18.296668 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7137 11:04:18.300254 MEM_TYPE=3, freq_sel=13
7138 11:04:18.303249 sv_algorithm_assistance_LP4_3733
7139 11:04:18.306578 ============ PULL DRAM RESETB DOWN ============
7140 11:04:18.310262 ========== PULL DRAM RESETB DOWN end =========
7141 11:04:18.316773 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7142 11:04:18.320131 ===================================
7143 11:04:18.320239 LPDDR4 DRAM CONFIGURATION
7144 11:04:18.323036 ===================================
7145 11:04:18.326595 EX_ROW_EN[0] = 0x0
7146 11:04:18.329756 EX_ROW_EN[1] = 0x0
7147 11:04:18.329858 LP4Y_EN = 0x0
7148 11:04:18.333243 WORK_FSP = 0x1
7149 11:04:18.333321 WL = 0x5
7150 11:04:18.337091 RL = 0x5
7151 11:04:18.337190 BL = 0x2
7152 11:04:18.339989 RPST = 0x0
7153 11:04:18.340084 RD_PRE = 0x0
7154 11:04:18.343156 WR_PRE = 0x1
7155 11:04:18.343250 WR_PST = 0x1
7156 11:04:18.346697 DBI_WR = 0x0
7157 11:04:18.346769 DBI_RD = 0x0
7158 11:04:18.349304 OTF = 0x1
7159 11:04:18.352885 ===================================
7160 11:04:18.356264 ===================================
7161 11:04:18.356362 ANA top config
7162 11:04:18.359715 ===================================
7163 11:04:18.362789 DLL_ASYNC_EN = 0
7164 11:04:18.366077 ALL_SLAVE_EN = 0
7165 11:04:18.369235 NEW_RANK_MODE = 1
7166 11:04:18.369315 DLL_IDLE_MODE = 1
7167 11:04:18.373035 LP45_APHY_COMB_EN = 1
7168 11:04:18.375894 TX_ODT_DIS = 0
7169 11:04:18.379253 NEW_8X_MODE = 1
7170 11:04:18.382683 ===================================
7171 11:04:18.386022 ===================================
7172 11:04:18.389668 data_rate = 3200
7173 11:04:18.389788 CKR = 1
7174 11:04:18.392388 DQ_P2S_RATIO = 8
7175 11:04:18.395896 ===================================
7176 11:04:18.399044 CA_P2S_RATIO = 8
7177 11:04:18.402612 DQ_CA_OPEN = 0
7178 11:04:18.406070 DQ_SEMI_OPEN = 0
7179 11:04:18.408885 CA_SEMI_OPEN = 0
7180 11:04:18.408983 CA_FULL_RATE = 0
7181 11:04:18.412376 DQ_CKDIV4_EN = 0
7182 11:04:18.415920 CA_CKDIV4_EN = 0
7183 11:04:18.418876 CA_PREDIV_EN = 0
7184 11:04:18.422384 PH8_DLY = 12
7185 11:04:18.425331 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7186 11:04:18.425413 DQ_AAMCK_DIV = 4
7187 11:04:18.428848 CA_AAMCK_DIV = 4
7188 11:04:18.432715 CA_ADMCK_DIV = 4
7189 11:04:18.435701 DQ_TRACK_CA_EN = 0
7190 11:04:18.439125 CA_PICK = 1600
7191 11:04:18.442116 CA_MCKIO = 1600
7192 11:04:18.445723 MCKIO_SEMI = 0
7193 11:04:18.445804 PLL_FREQ = 3068
7194 11:04:18.448485 DQ_UI_PI_RATIO = 32
7195 11:04:18.451996 CA_UI_PI_RATIO = 0
7196 11:04:18.455012 ===================================
7197 11:04:18.458625 ===================================
7198 11:04:18.462227 memory_type:LPDDR4
7199 11:04:18.465428 GP_NUM : 10
7200 11:04:18.465532 SRAM_EN : 1
7201 11:04:18.468891 MD32_EN : 0
7202 11:04:18.471836 ===================================
7203 11:04:18.471933 [ANA_INIT] >>>>>>>>>>>>>>
7204 11:04:18.475470 <<<<<< [CONFIGURE PHASE]: ANA_TX
7205 11:04:18.478716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7206 11:04:18.482016 ===================================
7207 11:04:18.485043 data_rate = 3200,PCW = 0X7600
7208 11:04:18.488868 ===================================
7209 11:04:18.491795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7210 11:04:18.498088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7211 11:04:18.504886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7212 11:04:18.508591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7213 11:04:18.511689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7214 11:04:18.515018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7215 11:04:18.518291 [ANA_INIT] flow start
7216 11:04:18.518372 [ANA_INIT] PLL >>>>>>>>
7217 11:04:18.521870 [ANA_INIT] PLL <<<<<<<<
7218 11:04:18.524999 [ANA_INIT] MIDPI >>>>>>>>
7219 11:04:18.525109 [ANA_INIT] MIDPI <<<<<<<<
7220 11:04:18.528219 [ANA_INIT] DLL >>>>>>>>
7221 11:04:18.531517 [ANA_INIT] DLL <<<<<<<<
7222 11:04:18.531617 [ANA_INIT] flow end
7223 11:04:18.537885 ============ LP4 DIFF to SE enter ============
7224 11:04:18.541607 ============ LP4 DIFF to SE exit ============
7225 11:04:18.544540 [ANA_INIT] <<<<<<<<<<<<<
7226 11:04:18.548381 [Flow] Enable top DCM control >>>>>
7227 11:04:18.551133 [Flow] Enable top DCM control <<<<<
7228 11:04:18.551227 Enable DLL master slave shuffle
7229 11:04:18.557999 ==============================================================
7230 11:04:18.561626 Gating Mode config
7231 11:04:18.564521 ==============================================================
7232 11:04:18.568036 Config description:
7233 11:04:18.577838 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7234 11:04:18.584403 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7235 11:04:18.587917 SELPH_MODE 0: By rank 1: By Phase
7236 11:04:18.594230 ==============================================================
7237 11:04:18.597677 GAT_TRACK_EN = 1
7238 11:04:18.600877 RX_GATING_MODE = 2
7239 11:04:18.604350 RX_GATING_TRACK_MODE = 2
7240 11:04:18.607888 SELPH_MODE = 1
7241 11:04:18.607975 PICG_EARLY_EN = 1
7242 11:04:18.611153 VALID_LAT_VALUE = 1
7243 11:04:18.617408 ==============================================================
7244 11:04:18.620791 Enter into Gating configuration >>>>
7245 11:04:18.624240 Exit from Gating configuration <<<<
7246 11:04:18.627865 Enter into DVFS_PRE_config >>>>>
7247 11:04:18.637434 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7248 11:04:18.640633 Exit from DVFS_PRE_config <<<<<
7249 11:04:18.644287 Enter into PICG configuration >>>>
7250 11:04:18.647281 Exit from PICG configuration <<<<
7251 11:04:18.650624 [RX_INPUT] configuration >>>>>
7252 11:04:18.653957 [RX_INPUT] configuration <<<<<
7253 11:04:18.657657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7254 11:04:18.663747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7255 11:04:18.670752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7256 11:04:18.677428 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7257 11:04:18.683879 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7258 11:04:18.687641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7259 11:04:18.694024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7260 11:04:18.697434 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7261 11:04:18.700462 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7262 11:04:18.703801 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7263 11:04:18.710660 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7264 11:04:18.714036 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7265 11:04:18.717003 ===================================
7266 11:04:18.720664 LPDDR4 DRAM CONFIGURATION
7267 11:04:18.724094 ===================================
7268 11:04:18.724178 EX_ROW_EN[0] = 0x0
7269 11:04:18.727027 EX_ROW_EN[1] = 0x0
7270 11:04:18.727120 LP4Y_EN = 0x0
7271 11:04:18.730500 WORK_FSP = 0x1
7272 11:04:18.730586 WL = 0x5
7273 11:04:18.733981 RL = 0x5
7274 11:04:18.734084 BL = 0x2
7275 11:04:18.737080 RPST = 0x0
7276 11:04:18.737156 RD_PRE = 0x0
7277 11:04:18.740519 WR_PRE = 0x1
7278 11:04:18.743615 WR_PST = 0x1
7279 11:04:18.743693 DBI_WR = 0x0
7280 11:04:18.747064 DBI_RD = 0x0
7281 11:04:18.747143 OTF = 0x1
7282 11:04:18.750215 ===================================
7283 11:04:18.753510 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7284 11:04:18.757216 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7285 11:04:18.763496 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7286 11:04:18.766664 ===================================
7287 11:04:18.770107 LPDDR4 DRAM CONFIGURATION
7288 11:04:18.773478 ===================================
7289 11:04:18.773564 EX_ROW_EN[0] = 0x10
7290 11:04:18.776912 EX_ROW_EN[1] = 0x0
7291 11:04:18.776984 LP4Y_EN = 0x0
7292 11:04:18.780608 WORK_FSP = 0x1
7293 11:04:18.780673 WL = 0x5
7294 11:04:18.784033 RL = 0x5
7295 11:04:18.784097 BL = 0x2
7296 11:04:18.787052 RPST = 0x0
7297 11:04:18.787116 RD_PRE = 0x0
7298 11:04:18.790694 WR_PRE = 0x1
7299 11:04:18.790784 WR_PST = 0x1
7300 11:04:18.793576 DBI_WR = 0x0
7301 11:04:18.793664 DBI_RD = 0x0
7302 11:04:18.797262 OTF = 0x1
7303 11:04:18.800636 ===================================
7304 11:04:18.807033 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7305 11:04:18.807133 ==
7306 11:04:18.810705 Dram Type= 6, Freq= 0, CH_0, rank 0
7307 11:04:18.813310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 11:04:18.813389 ==
7309 11:04:18.816788 [Duty_Offset_Calibration]
7310 11:04:18.816867 B0:2 B1:0 CA:3
7311 11:04:18.816924
7312 11:04:18.820239 [DutyScan_Calibration_Flow] k_type=0
7313 11:04:18.831082
7314 11:04:18.831206 ==CLK 0==
7315 11:04:18.834611 Final CLK duty delay cell = 0
7316 11:04:18.837698 [0] MAX Duty = 5031%(X100), DQS PI = 12
7317 11:04:18.841469 [0] MIN Duty = 4907%(X100), DQS PI = 6
7318 11:04:18.841555 [0] AVG Duty = 4969%(X100)
7319 11:04:18.844587
7320 11:04:18.844655 CH0 CLK Duty spec in!! Max-Min= 124%
7321 11:04:18.851046 [DutyScan_Calibration_Flow] ====Done====
7322 11:04:18.851127
7323 11:04:18.854504 [DutyScan_Calibration_Flow] k_type=1
7324 11:04:18.871457
7325 11:04:18.871581 ==DQS 0 ==
7326 11:04:18.874718 Final DQS duty delay cell = 0
7327 11:04:18.877646 [0] MAX Duty = 5094%(X100), DQS PI = 30
7328 11:04:18.881372 [0] MIN Duty = 4875%(X100), DQS PI = 48
7329 11:04:18.884401 [0] AVG Duty = 4984%(X100)
7330 11:04:18.884489
7331 11:04:18.884547 ==DQS 1 ==
7332 11:04:18.887542 Final DQS duty delay cell = 0
7333 11:04:18.891059 [0] MAX Duty = 5156%(X100), DQS PI = 32
7334 11:04:18.894470 [0] MIN Duty = 5031%(X100), DQS PI = 12
7335 11:04:18.897949 [0] AVG Duty = 5093%(X100)
7336 11:04:18.898054
7337 11:04:18.901004 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7338 11:04:18.901083
7339 11:04:18.904484 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7340 11:04:18.907711 [DutyScan_Calibration_Flow] ====Done====
7341 11:04:18.907795
7342 11:04:18.911051 [DutyScan_Calibration_Flow] k_type=3
7343 11:04:18.929290
7344 11:04:18.929418 ==DQM 0 ==
7345 11:04:18.932323 Final DQM duty delay cell = 0
7346 11:04:18.935817 [0] MAX Duty = 5156%(X100), DQS PI = 14
7347 11:04:18.939676 [0] MIN Duty = 4844%(X100), DQS PI = 50
7348 11:04:18.942904 [0] AVG Duty = 5000%(X100)
7349 11:04:18.943000
7350 11:04:18.943058 ==DQM 1 ==
7351 11:04:18.945742 Final DQM duty delay cell = 4
7352 11:04:18.948902 [4] MAX Duty = 5156%(X100), DQS PI = 0
7353 11:04:18.952550 [4] MIN Duty = 5000%(X100), DQS PI = 28
7354 11:04:18.955599 [4] AVG Duty = 5078%(X100)
7355 11:04:18.955680
7356 11:04:18.959311 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7357 11:04:18.959389
7358 11:04:18.962571 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7359 11:04:18.965533 [DutyScan_Calibration_Flow] ====Done====
7360 11:04:18.965615
7361 11:04:18.969356 [DutyScan_Calibration_Flow] k_type=2
7362 11:04:18.985795
7363 11:04:18.985919 ==DQ 0 ==
7364 11:04:18.988973 Final DQ duty delay cell = -4
7365 11:04:18.992253 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7366 11:04:18.995677 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7367 11:04:18.998602 [-4] AVG Duty = 4938%(X100)
7368 11:04:18.998687
7369 11:04:18.998747 ==DQ 1 ==
7370 11:04:19.002368 Final DQ duty delay cell = 0
7371 11:04:19.005425 [0] MAX Duty = 5156%(X100), DQS PI = 60
7372 11:04:19.008657 [0] MIN Duty = 4969%(X100), DQS PI = 20
7373 11:04:19.012187 [0] AVG Duty = 5062%(X100)
7374 11:04:19.012273
7375 11:04:19.015734 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7376 11:04:19.015840
7377 11:04:19.018809 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7378 11:04:19.022351 [DutyScan_Calibration_Flow] ====Done====
7379 11:04:19.022431 ==
7380 11:04:19.025095 Dram Type= 6, Freq= 0, CH_1, rank 0
7381 11:04:19.028424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7382 11:04:19.028521 ==
7383 11:04:19.032147 [Duty_Offset_Calibration]
7384 11:04:19.032246 B0:1 B1:-2 CA:1
7385 11:04:19.032329
7386 11:04:19.035000 [DutyScan_Calibration_Flow] k_type=0
7387 11:04:19.045985
7388 11:04:19.046112 ==CLK 0==
7389 11:04:19.049308 Final CLK duty delay cell = 0
7390 11:04:19.052429 [0] MAX Duty = 5062%(X100), DQS PI = 20
7391 11:04:19.056172 [0] MIN Duty = 4813%(X100), DQS PI = 60
7392 11:04:19.059054 [0] AVG Duty = 4937%(X100)
7393 11:04:19.059152
7394 11:04:19.062375 CH1 CLK Duty spec in!! Max-Min= 249%
7395 11:04:19.065688 [DutyScan_Calibration_Flow] ====Done====
7396 11:04:19.065769
7397 11:04:19.069131 [DutyScan_Calibration_Flow] k_type=1
7398 11:04:19.085530
7399 11:04:19.085639 ==DQS 0 ==
7400 11:04:19.089095 Final DQS duty delay cell = 0
7401 11:04:19.092367 [0] MAX Duty = 5187%(X100), DQS PI = 24
7402 11:04:19.095945 [0] MIN Duty = 5062%(X100), DQS PI = 48
7403 11:04:19.099180 [0] AVG Duty = 5124%(X100)
7404 11:04:19.099277
7405 11:04:19.099358 ==DQS 1 ==
7406 11:04:19.102546 Final DQS duty delay cell = 0
7407 11:04:19.106201 [0] MAX Duty = 5093%(X100), DQS PI = 60
7408 11:04:19.108975 [0] MIN Duty = 4875%(X100), DQS PI = 24
7409 11:04:19.109045 [0] AVG Duty = 4984%(X100)
7410 11:04:19.112718
7411 11:04:19.116055 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7412 11:04:19.116125
7413 11:04:19.119107 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7414 11:04:19.122382 [DutyScan_Calibration_Flow] ====Done====
7415 11:04:19.122454
7416 11:04:19.125730 [DutyScan_Calibration_Flow] k_type=3
7417 11:04:19.143034
7418 11:04:19.143156 ==DQM 0 ==
7419 11:04:19.146482 Final DQM duty delay cell = 0
7420 11:04:19.149359 [0] MAX Duty = 5031%(X100), DQS PI = 26
7421 11:04:19.153199 [0] MIN Duty = 4813%(X100), DQS PI = 54
7422 11:04:19.155923 [0] AVG Duty = 4922%(X100)
7423 11:04:19.156006
7424 11:04:19.156063 ==DQM 1 ==
7425 11:04:19.159576 Final DQM duty delay cell = 0
7426 11:04:19.163087 [0] MAX Duty = 5062%(X100), DQS PI = 34
7427 11:04:19.166071 [0] MIN Duty = 4875%(X100), DQS PI = 24
7428 11:04:19.169633 [0] AVG Duty = 4968%(X100)
7429 11:04:19.169729
7430 11:04:19.172562 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7431 11:04:19.172652
7432 11:04:19.175839 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7433 11:04:19.179268 [DutyScan_Calibration_Flow] ====Done====
7434 11:04:19.179342
7435 11:04:19.182808 [DutyScan_Calibration_Flow] k_type=2
7436 11:04:19.199681
7437 11:04:19.199799 ==DQ 0 ==
7438 11:04:19.202805 Final DQ duty delay cell = 0
7439 11:04:19.206213 [0] MAX Duty = 5093%(X100), DQS PI = 20
7440 11:04:19.209611 [0] MIN Duty = 4907%(X100), DQS PI = 48
7441 11:04:19.209684 [0] AVG Duty = 5000%(X100)
7442 11:04:19.212923
7443 11:04:19.212994 ==DQ 1 ==
7444 11:04:19.216215 Final DQ duty delay cell = 0
7445 11:04:19.219893 [0] MAX Duty = 5125%(X100), DQS PI = 34
7446 11:04:19.223452 [0] MIN Duty = 4969%(X100), DQS PI = 24
7447 11:04:19.223531 [0] AVG Duty = 5047%(X100)
7448 11:04:19.223589
7449 11:04:19.226477 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7450 11:04:19.229762
7451 11:04:19.232817 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7452 11:04:19.236442 [DutyScan_Calibration_Flow] ====Done====
7453 11:04:19.239508 nWR fixed to 30
7454 11:04:19.239595 [ModeRegInit_LP4] CH0 RK0
7455 11:04:19.242942 [ModeRegInit_LP4] CH0 RK1
7456 11:04:19.246303 [ModeRegInit_LP4] CH1 RK0
7457 11:04:19.246382 [ModeRegInit_LP4] CH1 RK1
7458 11:04:19.249940 match AC timing 5
7459 11:04:19.252844 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7460 11:04:19.259507 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7461 11:04:19.262807 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7462 11:04:19.269941 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7463 11:04:19.273057 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7464 11:04:19.273135 [MiockJmeterHQA]
7465 11:04:19.273191
7466 11:04:19.275982 [DramcMiockJmeter] u1RxGatingPI = 0
7467 11:04:19.279283 0 : 4363, 4137
7468 11:04:19.279359 4 : 4363, 4137
7469 11:04:19.279416 8 : 4255, 4029
7470 11:04:19.282827 12 : 4363, 4137
7471 11:04:19.282894 16 : 4252, 4027
7472 11:04:19.286625 20 : 4255, 4030
7473 11:04:19.286692 24 : 4253, 4026
7474 11:04:19.289412 28 : 4364, 4137
7475 11:04:19.289476 32 : 4363, 4137
7476 11:04:19.293023 36 : 4255, 4030
7477 11:04:19.293090 40 : 4253, 4026
7478 11:04:19.293144 44 : 4252, 4027
7479 11:04:19.295902 48 : 4252, 4027
7480 11:04:19.295974 52 : 4253, 4026
7481 11:04:19.299552 56 : 4363, 4138
7482 11:04:19.299621 60 : 4252, 4026
7483 11:04:19.302569 64 : 4252, 4027
7484 11:04:19.302650 68 : 4253, 4027
7485 11:04:19.306286 72 : 4250, 4026
7486 11:04:19.306363 76 : 4250, 4027
7487 11:04:19.306422 80 : 4360, 4138
7488 11:04:19.309744 84 : 4361, 4137
7489 11:04:19.309811 88 : 4250, 4027
7490 11:04:19.312992 92 : 4249, 4027
7491 11:04:19.313124 96 : 4250, 4027
7492 11:04:19.315947 100 : 4250, 4027
7493 11:04:19.316015 104 : 4252, 3253
7494 11:04:19.316071 108 : 4361, 0
7495 11:04:19.319626 112 : 4249, 0
7496 11:04:19.319695 116 : 4361, 0
7497 11:04:19.322504 120 : 4363, 0
7498 11:04:19.322573 124 : 4250, 0
7499 11:04:19.322628 128 : 4250, 0
7500 11:04:19.326013 132 : 4250, 0
7501 11:04:19.326079 136 : 4250, 0
7502 11:04:19.329404 140 : 4250, 0
7503 11:04:19.329471 144 : 4250, 0
7504 11:04:19.329527 148 : 4253, 0
7505 11:04:19.332427 152 : 4361, 0
7506 11:04:19.332493 156 : 4360, 0
7507 11:04:19.335842 160 : 4248, 0
7508 11:04:19.335913 164 : 4250, 0
7509 11:04:19.335977 168 : 4361, 0
7510 11:04:19.339015 172 : 4360, 0
7511 11:04:19.339082 176 : 4250, 0
7512 11:04:19.342862 180 : 4250, 0
7513 11:04:19.342949 184 : 4250, 0
7514 11:04:19.343005 188 : 4253, 0
7515 11:04:19.345712 192 : 4250, 0
7516 11:04:19.345774 196 : 4250, 0
7517 11:04:19.345833 200 : 4250, 0
7518 11:04:19.349088 204 : 4361, 0
7519 11:04:19.349170 208 : 4249, 0
7520 11:04:19.352415 212 : 4361, 0
7521 11:04:19.352482 216 : 4250, 0
7522 11:04:19.352536 220 : 4250, 0
7523 11:04:19.356101 224 : 4250, 0
7524 11:04:19.356168 228 : 4250, 0
7525 11:04:19.359229 232 : 4250, 1
7526 11:04:19.359295 236 : 4249, 1102
7527 11:04:19.362687 240 : 4250, 4027
7528 11:04:19.362778 244 : 4360, 4138
7529 11:04:19.362858 248 : 4250, 4027
7530 11:04:19.365558 252 : 4360, 4137
7531 11:04:19.365629 256 : 4360, 4138
7532 11:04:19.368911 260 : 4250, 4027
7533 11:04:19.369031 264 : 4250, 4027
7534 11:04:19.372100 268 : 4361, 4137
7535 11:04:19.372172 272 : 4250, 4027
7536 11:04:19.375851 276 : 4250, 4027
7537 11:04:19.375930 280 : 4250, 4027
7538 11:04:19.378976 284 : 4252, 4029
7539 11:04:19.379042 288 : 4250, 4027
7540 11:04:19.382342 292 : 4250, 4027
7541 11:04:19.382442 296 : 4361, 4137
7542 11:04:19.386033 300 : 4250, 4026
7543 11:04:19.386162 304 : 4250, 4027
7544 11:04:19.386218 308 : 4360, 4138
7545 11:04:19.388983 312 : 4250, 4027
7546 11:04:19.389045 316 : 4250, 4027
7547 11:04:19.392047 320 : 4363, 4139
7548 11:04:19.392118 324 : 4250, 4027
7549 11:04:19.395599 328 : 4250, 4027
7550 11:04:19.395666 332 : 4250, 4027
7551 11:04:19.399080 336 : 4250, 4026
7552 11:04:19.399147 340 : 4250, 4027
7553 11:04:19.401952 344 : 4250, 4027
7554 11:04:19.402036 348 : 4361, 4137
7555 11:04:19.405521 352 : 4250, 4019
7556 11:04:19.405625 356 : 4250, 2806
7557 11:04:19.405725 360 : 4360, 0
7558 11:04:19.408668
7559 11:04:19.408734 MIOCK jitter meter ch=0
7560 11:04:19.408787
7561 11:04:19.412148 1T = (360-108) = 252 dly cells
7562 11:04:19.419113 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7563 11:04:19.419248 ==
7564 11:04:19.422162 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 11:04:19.425228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 11:04:19.425338 ==
7567 11:04:19.431865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7568 11:04:19.435587 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7569 11:04:19.438492 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7570 11:04:19.445034 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7571 11:04:19.454994 [CA 0] Center 44 (14~75) winsize 62
7572 11:04:19.458134 [CA 1] Center 43 (13~74) winsize 62
7573 11:04:19.461706 [CA 2] Center 40 (11~69) winsize 59
7574 11:04:19.464670 [CA 3] Center 39 (10~69) winsize 60
7575 11:04:19.468117 [CA 4] Center 37 (8~67) winsize 60
7576 11:04:19.471554 [CA 5] Center 36 (7~66) winsize 60
7577 11:04:19.471661
7578 11:04:19.474813 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7579 11:04:19.474908
7580 11:04:19.481235 [CATrainingPosCal] consider 1 rank data
7581 11:04:19.481348 u2DelayCellTimex100 = 258/100 ps
7582 11:04:19.488226 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7583 11:04:19.491308 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7584 11:04:19.494488 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7585 11:04:19.498025 CA3 delay=39 (10~69),Diff = 3 PI (11 cell)
7586 11:04:19.501071 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7587 11:04:19.504572 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7588 11:04:19.504648
7589 11:04:19.507718 CA PerBit enable=1, Macro0, CA PI delay=36
7590 11:04:19.507793
7591 11:04:19.511242 [CBTSetCACLKResult] CA Dly = 36
7592 11:04:19.514657 CS Dly: 11 (0~42)
7593 11:04:19.517634 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7594 11:04:19.521182 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7595 11:04:19.521267 ==
7596 11:04:19.524482 Dram Type= 6, Freq= 0, CH_0, rank 1
7597 11:04:19.531057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 11:04:19.531159 ==
7599 11:04:19.534240 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7600 11:04:19.540711 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7601 11:04:19.544293 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7602 11:04:19.550697 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7603 11:04:19.558687 [CA 0] Center 43 (13~74) winsize 62
7604 11:04:19.562068 [CA 1] Center 43 (13~74) winsize 62
7605 11:04:19.565496 [CA 2] Center 39 (10~68) winsize 59
7606 11:04:19.568793 [CA 3] Center 39 (10~68) winsize 59
7607 11:04:19.571788 [CA 4] Center 36 (6~66) winsize 61
7608 11:04:19.575229 [CA 5] Center 36 (6~66) winsize 61
7609 11:04:19.575327
7610 11:04:19.578724 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7611 11:04:19.578819
7612 11:04:19.582205 [CATrainingPosCal] consider 2 rank data
7613 11:04:19.585138 u2DelayCellTimex100 = 258/100 ps
7614 11:04:19.591841 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7615 11:04:19.595537 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7616 11:04:19.598695 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7617 11:04:19.601973 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7618 11:04:19.605137 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7619 11:04:19.608483 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7620 11:04:19.608568
7621 11:04:19.612093 CA PerBit enable=1, Macro0, CA PI delay=36
7622 11:04:19.612172
7623 11:04:19.614917 [CBTSetCACLKResult] CA Dly = 36
7624 11:04:19.618578 CS Dly: 11 (0~43)
7625 11:04:19.621526 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7626 11:04:19.625051 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7627 11:04:19.625134
7628 11:04:19.628189 ----->DramcWriteLeveling(PI) begin...
7629 11:04:19.628266 ==
7630 11:04:19.631478 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 11:04:19.638051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 11:04:19.638170 ==
7633 11:04:19.641820 Write leveling (Byte 0): 35 => 35
7634 11:04:19.644930 Write leveling (Byte 1): 28 => 28
7635 11:04:19.645009 DramcWriteLeveling(PI) end<-----
7636 11:04:19.648339
7637 11:04:19.648415 ==
7638 11:04:19.651601 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 11:04:19.655368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 11:04:19.655450 ==
7641 11:04:19.658326 [Gating] SW mode calibration
7642 11:04:19.665084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7643 11:04:19.668380 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7644 11:04:19.675036 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 11:04:19.678257 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 11:04:19.681516 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 11:04:19.688060 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 11:04:19.691629 1 4 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7649 11:04:19.694574 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7650 11:04:19.701478 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7651 11:04:19.704930 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 11:04:19.708006 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 11:04:19.714859 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 11:04:19.718231 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 11:04:19.721621 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7656 11:04:19.727781 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7657 11:04:19.731142 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7658 11:04:19.734543 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7659 11:04:19.741737 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 11:04:19.744769 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 11:04:19.748147 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 11:04:19.754381 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 11:04:19.758160 1 6 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7664 11:04:19.761175 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7665 11:04:19.767791 1 6 20 | B1->B0 | 2c2b 4646 | 1 0 | (0 0) (0 0)
7666 11:04:19.771399 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7667 11:04:19.774224 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 11:04:19.781073 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 11:04:19.784758 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 11:04:19.787610 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 11:04:19.794234 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 11:04:19.797543 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7673 11:04:19.800964 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7674 11:04:19.804163 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7675 11:04:19.810598 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 11:04:19.814166 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 11:04:19.817555 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 11:04:19.824301 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 11:04:19.827627 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 11:04:19.830775 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 11:04:19.837454 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 11:04:19.840878 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 11:04:19.844033 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 11:04:19.851048 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 11:04:19.853997 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 11:04:19.857186 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 11:04:19.864015 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7688 11:04:19.867105 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7689 11:04:19.870644 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7690 11:04:19.873838 Total UI for P1: 0, mck2ui 16
7691 11:04:19.877267 best dqsien dly found for B0: ( 1, 9, 14)
7692 11:04:19.883991 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7693 11:04:19.887310 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7694 11:04:19.890499 Total UI for P1: 0, mck2ui 16
7695 11:04:19.894042 best dqsien dly found for B1: ( 1, 9, 22)
7696 11:04:19.897080 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7697 11:04:19.900842 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7698 11:04:19.900933
7699 11:04:19.903807 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7700 11:04:19.907346 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7701 11:04:19.910505 [Gating] SW calibration Done
7702 11:04:19.910602 ==
7703 11:04:19.914020 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 11:04:19.917013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 11:04:19.920258 ==
7706 11:04:19.920352 RX Vref Scan: 0
7707 11:04:19.920438
7708 11:04:19.923773 RX Vref 0 -> 0, step: 1
7709 11:04:19.923874
7710 11:04:19.923963 RX Delay 0 -> 252, step: 8
7711 11:04:19.930380 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7712 11:04:19.933807 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7713 11:04:19.937128 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7714 11:04:19.940775 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7715 11:04:19.943710 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7716 11:04:19.950800 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7717 11:04:19.953520 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7718 11:04:19.957336 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7719 11:04:19.960463 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7720 11:04:19.963644 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7721 11:04:19.970613 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7722 11:04:19.973710 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7723 11:04:19.976778 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7724 11:04:19.980027 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7725 11:04:19.987196 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7726 11:04:19.990233 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7727 11:04:19.990319 ==
7728 11:04:19.993379 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 11:04:19.996891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 11:04:19.996971 ==
7731 11:04:19.999878 DQS Delay:
7732 11:04:19.999955 DQS0 = 0, DQS1 = 0
7733 11:04:20.000015 DQM Delay:
7734 11:04:20.003172 DQM0 = 127, DQM1 = 124
7735 11:04:20.003249 DQ Delay:
7736 11:04:20.006882 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7737 11:04:20.009903 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =135
7738 11:04:20.013250 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7739 11:04:20.019803 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7740 11:04:20.019915
7741 11:04:20.020002
7742 11:04:20.020083 ==
7743 11:04:20.023339 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 11:04:20.026757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 11:04:20.026839 ==
7746 11:04:20.026898
7747 11:04:20.026952
7748 11:04:20.029768 TX Vref Scan disable
7749 11:04:20.029845 == TX Byte 0 ==
7750 11:04:20.036179 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7751 11:04:20.039896 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7752 11:04:20.043165 == TX Byte 1 ==
7753 11:04:20.046078 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7754 11:04:20.049194 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7755 11:04:20.049292 ==
7756 11:04:20.053039 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 11:04:20.056267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 11:04:20.056373 ==
7759 11:04:20.071104
7760 11:04:20.074460 TX Vref early break, caculate TX vref
7761 11:04:20.077848 TX Vref=16, minBit 8, minWin=21, winSum=354
7762 11:04:20.080965 TX Vref=18, minBit 11, minWin=21, winSum=368
7763 11:04:20.084162 TX Vref=20, minBit 8, minWin=22, winSum=378
7764 11:04:20.087415 TX Vref=22, minBit 8, minWin=23, winSum=388
7765 11:04:20.091037 TX Vref=24, minBit 8, minWin=23, winSum=397
7766 11:04:20.097710 TX Vref=26, minBit 0, minWin=25, winSum=403
7767 11:04:20.100926 TX Vref=28, minBit 9, minWin=24, winSum=406
7768 11:04:20.104328 TX Vref=30, minBit 9, minWin=24, winSum=399
7769 11:04:20.107113 TX Vref=32, minBit 8, minWin=23, winSum=388
7770 11:04:20.110986 TX Vref=34, minBit 8, minWin=22, winSum=377
7771 11:04:20.117088 [TxChooseVref] Worse bit 0, Min win 25, Win sum 403, Final Vref 26
7772 11:04:20.117184
7773 11:04:20.120694 Final TX Range 0 Vref 26
7774 11:04:20.120774
7775 11:04:20.120834 ==
7776 11:04:20.124284 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 11:04:20.127343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 11:04:20.127442 ==
7779 11:04:20.127516
7780 11:04:20.127569
7781 11:04:20.130374 TX Vref Scan disable
7782 11:04:20.137545 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7783 11:04:20.137636 == TX Byte 0 ==
7784 11:04:20.140884 u2DelayCellOfst[0]=15 cells (4 PI)
7785 11:04:20.144036 u2DelayCellOfst[1]=18 cells (5 PI)
7786 11:04:20.147084 u2DelayCellOfst[2]=11 cells (3 PI)
7787 11:04:20.150295 u2DelayCellOfst[3]=11 cells (3 PI)
7788 11:04:20.153925 u2DelayCellOfst[4]=7 cells (2 PI)
7789 11:04:20.157384 u2DelayCellOfst[5]=0 cells (0 PI)
7790 11:04:20.160683 u2DelayCellOfst[6]=18 cells (5 PI)
7791 11:04:20.163569 u2DelayCellOfst[7]=18 cells (5 PI)
7792 11:04:20.167154 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7793 11:04:20.170700 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7794 11:04:20.173915 == TX Byte 1 ==
7795 11:04:20.176839 u2DelayCellOfst[8]=0 cells (0 PI)
7796 11:04:20.176934 u2DelayCellOfst[9]=3 cells (1 PI)
7797 11:04:20.180444 u2DelayCellOfst[10]=7 cells (2 PI)
7798 11:04:20.183993 u2DelayCellOfst[11]=3 cells (1 PI)
7799 11:04:20.187039 u2DelayCellOfst[12]=11 cells (3 PI)
7800 11:04:20.190343 u2DelayCellOfst[13]=11 cells (3 PI)
7801 11:04:20.193595 u2DelayCellOfst[14]=15 cells (4 PI)
7802 11:04:20.197270 u2DelayCellOfst[15]=11 cells (3 PI)
7803 11:04:20.200206 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7804 11:04:20.206885 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7805 11:04:20.206986 DramC Write-DBI on
7806 11:04:20.207046 ==
7807 11:04:20.210339 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 11:04:20.213821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 11:04:20.216840 ==
7810 11:04:20.216920
7811 11:04:20.216979
7812 11:04:20.217032 TX Vref Scan disable
7813 11:04:20.220982 == TX Byte 0 ==
7814 11:04:20.224171 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7815 11:04:20.226917 == TX Byte 1 ==
7816 11:04:20.230762 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7817 11:04:20.234221 DramC Write-DBI off
7818 11:04:20.234303
7819 11:04:20.234362 [DATLAT]
7820 11:04:20.234417 Freq=1600, CH0 RK0
7821 11:04:20.234468
7822 11:04:20.237111 DATLAT Default: 0xf
7823 11:04:20.237188 0, 0xFFFF, sum = 0
7824 11:04:20.240833 1, 0xFFFF, sum = 0
7825 11:04:20.240914 2, 0xFFFF, sum = 0
7826 11:04:20.243614 3, 0xFFFF, sum = 0
7827 11:04:20.247152 4, 0xFFFF, sum = 0
7828 11:04:20.247236 5, 0xFFFF, sum = 0
7829 11:04:20.250744 6, 0xFFFF, sum = 0
7830 11:04:20.250823 7, 0xFFFF, sum = 0
7831 11:04:20.254087 8, 0xFFFF, sum = 0
7832 11:04:20.254211 9, 0xFFFF, sum = 0
7833 11:04:20.257400 10, 0xFFFF, sum = 0
7834 11:04:20.257479 11, 0xFFFF, sum = 0
7835 11:04:20.260278 12, 0xFFFF, sum = 0
7836 11:04:20.260360 13, 0xEFFF, sum = 0
7837 11:04:20.263896 14, 0x0, sum = 1
7838 11:04:20.263974 15, 0x0, sum = 2
7839 11:04:20.266929 16, 0x0, sum = 3
7840 11:04:20.267008 17, 0x0, sum = 4
7841 11:04:20.270283 best_step = 15
7842 11:04:20.270363
7843 11:04:20.270422 ==
7844 11:04:20.273571 Dram Type= 6, Freq= 0, CH_0, rank 0
7845 11:04:20.276839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7846 11:04:20.276919 ==
7847 11:04:20.280263 RX Vref Scan: 1
7848 11:04:20.280339
7849 11:04:20.280402 Set Vref Range= 24 -> 127
7850 11:04:20.280495
7851 11:04:20.283691 RX Vref 24 -> 127, step: 1
7852 11:04:20.283769
7853 11:04:20.286842 RX Delay 11 -> 252, step: 4
7854 11:04:20.286943
7855 11:04:20.290348 Set Vref, RX VrefLevel [Byte0]: 24
7856 11:04:20.293398 [Byte1]: 24
7857 11:04:20.293492
7858 11:04:20.296649 Set Vref, RX VrefLevel [Byte0]: 25
7859 11:04:20.299954 [Byte1]: 25
7860 11:04:20.303366
7861 11:04:20.303466 Set Vref, RX VrefLevel [Byte0]: 26
7862 11:04:20.306462 [Byte1]: 26
7863 11:04:20.311050
7864 11:04:20.311146 Set Vref, RX VrefLevel [Byte0]: 27
7865 11:04:20.314330 [Byte1]: 27
7866 11:04:20.318575
7867 11:04:20.318678 Set Vref, RX VrefLevel [Byte0]: 28
7868 11:04:20.322148 [Byte1]: 28
7869 11:04:20.326597
7870 11:04:20.326684 Set Vref, RX VrefLevel [Byte0]: 29
7871 11:04:20.329886 [Byte1]: 29
7872 11:04:20.333714
7873 11:04:20.333794 Set Vref, RX VrefLevel [Byte0]: 30
7874 11:04:20.337404 [Byte1]: 30
7875 11:04:20.341362
7876 11:04:20.341443 Set Vref, RX VrefLevel [Byte0]: 31
7877 11:04:20.344861 [Byte1]: 31
7878 11:04:20.349010
7879 11:04:20.349093 Set Vref, RX VrefLevel [Byte0]: 32
7880 11:04:20.352410 [Byte1]: 32
7881 11:04:20.356615
7882 11:04:20.356696 Set Vref, RX VrefLevel [Byte0]: 33
7883 11:04:20.360066 [Byte1]: 33
7884 11:04:20.364184
7885 11:04:20.364266 Set Vref, RX VrefLevel [Byte0]: 34
7886 11:04:20.367385 [Byte1]: 34
7887 11:04:20.371940
7888 11:04:20.372024 Set Vref, RX VrefLevel [Byte0]: 35
7889 11:04:20.375501 [Byte1]: 35
7890 11:04:20.379587
7891 11:04:20.379687 Set Vref, RX VrefLevel [Byte0]: 36
7892 11:04:20.382573 [Byte1]: 36
7893 11:04:20.386854
7894 11:04:20.386970 Set Vref, RX VrefLevel [Byte0]: 37
7895 11:04:20.390434 [Byte1]: 37
7896 11:04:20.394438
7897 11:04:20.394522 Set Vref, RX VrefLevel [Byte0]: 38
7898 11:04:20.397813 [Byte1]: 38
7899 11:04:20.402591
7900 11:04:20.402715 Set Vref, RX VrefLevel [Byte0]: 39
7901 11:04:20.405422 [Byte1]: 39
7902 11:04:20.409992
7903 11:04:20.410097 Set Vref, RX VrefLevel [Byte0]: 40
7904 11:04:20.412976 [Byte1]: 40
7905 11:04:20.417748
7906 11:04:20.417831 Set Vref, RX VrefLevel [Byte0]: 41
7907 11:04:20.420846 [Byte1]: 41
7908 11:04:20.425332
7909 11:04:20.425408 Set Vref, RX VrefLevel [Byte0]: 42
7910 11:04:20.428427 [Byte1]: 42
7911 11:04:20.432545
7912 11:04:20.432674 Set Vref, RX VrefLevel [Byte0]: 43
7913 11:04:20.436300 [Byte1]: 43
7914 11:04:20.440678
7915 11:04:20.440755 Set Vref, RX VrefLevel [Byte0]: 44
7916 11:04:20.443618 [Byte1]: 44
7917 11:04:20.447765
7918 11:04:20.447832 Set Vref, RX VrefLevel [Byte0]: 45
7919 11:04:20.451409 [Byte1]: 45
7920 11:04:20.455384
7921 11:04:20.455482 Set Vref, RX VrefLevel [Byte0]: 46
7922 11:04:20.458918 [Byte1]: 46
7923 11:04:20.463311
7924 11:04:20.463403 Set Vref, RX VrefLevel [Byte0]: 47
7925 11:04:20.466723 [Byte1]: 47
7926 11:04:20.470712
7927 11:04:20.470804 Set Vref, RX VrefLevel [Byte0]: 48
7928 11:04:20.474174 [Byte1]: 48
7929 11:04:20.478166
7930 11:04:20.478258 Set Vref, RX VrefLevel [Byte0]: 49
7931 11:04:20.481585 [Byte1]: 49
7932 11:04:20.485933
7933 11:04:20.486008 Set Vref, RX VrefLevel [Byte0]: 50
7934 11:04:20.489425 [Byte1]: 50
7935 11:04:20.494056
7936 11:04:20.494206 Set Vref, RX VrefLevel [Byte0]: 51
7937 11:04:20.497228 [Byte1]: 51
7938 11:04:20.501260
7939 11:04:20.501351 Set Vref, RX VrefLevel [Byte0]: 52
7940 11:04:20.504536 [Byte1]: 52
7941 11:04:20.508872
7942 11:04:20.508964 Set Vref, RX VrefLevel [Byte0]: 53
7943 11:04:20.512200 [Byte1]: 53
7944 11:04:20.516524
7945 11:04:20.516623 Set Vref, RX VrefLevel [Byte0]: 54
7946 11:04:20.519562 [Byte1]: 54
7947 11:04:20.524328
7948 11:04:20.524421 Set Vref, RX VrefLevel [Byte0]: 55
7949 11:04:20.527216 [Byte1]: 55
7950 11:04:20.531445
7951 11:04:20.531538 Set Vref, RX VrefLevel [Byte0]: 56
7952 11:04:20.535080 [Byte1]: 56
7953 11:04:20.539037
7954 11:04:20.539106 Set Vref, RX VrefLevel [Byte0]: 57
7955 11:04:20.542405 [Byte1]: 57
7956 11:04:20.547110
7957 11:04:20.547172 Set Vref, RX VrefLevel [Byte0]: 58
7958 11:04:20.549995 [Byte1]: 58
7959 11:04:20.554645
7960 11:04:20.554744 Set Vref, RX VrefLevel [Byte0]: 59
7961 11:04:20.558040 [Byte1]: 59
7962 11:04:20.561931
7963 11:04:20.562025 Set Vref, RX VrefLevel [Byte0]: 60
7964 11:04:20.565584 [Byte1]: 60
7965 11:04:20.569782
7966 11:04:20.569859 Set Vref, RX VrefLevel [Byte0]: 61
7967 11:04:20.572905 [Byte1]: 61
7968 11:04:20.577372
7969 11:04:20.577441 Set Vref, RX VrefLevel [Byte0]: 62
7970 11:04:20.580402 [Byte1]: 62
7971 11:04:20.584990
7972 11:04:20.585089 Set Vref, RX VrefLevel [Byte0]: 63
7973 11:04:20.588047 [Byte1]: 63
7974 11:04:20.592790
7975 11:04:20.592856 Set Vref, RX VrefLevel [Byte0]: 64
7976 11:04:20.595770 [Byte1]: 64
7977 11:04:20.600770
7978 11:04:20.600845 Set Vref, RX VrefLevel [Byte0]: 65
7979 11:04:20.603505 [Byte1]: 65
7980 11:04:20.607600
7981 11:04:20.607694 Set Vref, RX VrefLevel [Byte0]: 66
7982 11:04:20.611005 [Byte1]: 66
7983 11:04:20.615518
7984 11:04:20.615591 Set Vref, RX VrefLevel [Byte0]: 67
7985 11:04:20.618599 [Byte1]: 67
7986 11:04:20.623203
7987 11:04:20.623299 Set Vref, RX VrefLevel [Byte0]: 68
7988 11:04:20.626573 [Byte1]: 68
7989 11:04:20.631224
7990 11:04:20.631302 Set Vref, RX VrefLevel [Byte0]: 69
7991 11:04:20.633942 [Byte1]: 69
7992 11:04:20.638305
7993 11:04:20.638384 Set Vref, RX VrefLevel [Byte0]: 70
7994 11:04:20.641658 [Byte1]: 70
7995 11:04:20.645884
7996 11:04:20.645962 Set Vref, RX VrefLevel [Byte0]: 71
7997 11:04:20.649285 [Byte1]: 71
7998 11:04:20.653243
7999 11:04:20.653321 Set Vref, RX VrefLevel [Byte0]: 72
8000 11:04:20.657312 [Byte1]: 72
8001 11:04:20.660931
8002 11:04:20.661013 Set Vref, RX VrefLevel [Byte0]: 73
8003 11:04:20.664315 [Byte1]: 73
8004 11:04:20.668504
8005 11:04:20.668589 Final RX Vref Byte 0 = 63 to rank0
8006 11:04:20.671902 Final RX Vref Byte 1 = 60 to rank0
8007 11:04:20.675537 Final RX Vref Byte 0 = 63 to rank1
8008 11:04:20.679032 Final RX Vref Byte 1 = 60 to rank1==
8009 11:04:20.682025 Dram Type= 6, Freq= 0, CH_0, rank 0
8010 11:04:20.688740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 11:04:20.688831 ==
8012 11:04:20.688890 DQS Delay:
8013 11:04:20.688944 DQS0 = 0, DQS1 = 0
8014 11:04:20.692452 DQM Delay:
8015 11:04:20.692527 DQM0 = 126, DQM1 = 119
8016 11:04:20.695688 DQ Delay:
8017 11:04:20.698464 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8018 11:04:20.702196 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8019 11:04:20.705709 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8020 11:04:20.708503 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8021 11:04:20.708647
8022 11:04:20.708728
8023 11:04:20.708785
8024 11:04:20.711634 [DramC_TX_OE_Calibration] TA2
8025 11:04:20.715259 Original DQ_B0 (3 6) =30, OEN = 27
8026 11:04:20.718648 Original DQ_B1 (3 6) =30, OEN = 27
8027 11:04:20.722006 24, 0x0, End_B0=24 End_B1=24
8028 11:04:20.722084 25, 0x0, End_B0=25 End_B1=25
8029 11:04:20.724922 26, 0x0, End_B0=26 End_B1=26
8030 11:04:20.728492 27, 0x0, End_B0=27 End_B1=27
8031 11:04:20.731466 28, 0x0, End_B0=28 End_B1=28
8032 11:04:20.735075 29, 0x0, End_B0=29 End_B1=29
8033 11:04:20.735152 30, 0x0, End_B0=30 End_B1=30
8034 11:04:20.738250 31, 0x4141, End_B0=30 End_B1=30
8035 11:04:20.741613 Byte0 end_step=30 best_step=27
8036 11:04:20.745149 Byte1 end_step=30 best_step=27
8037 11:04:20.748153 Byte0 TX OE(2T, 0.5T) = (3, 3)
8038 11:04:20.751839 Byte1 TX OE(2T, 0.5T) = (3, 3)
8039 11:04:20.751915
8040 11:04:20.751972
8041 11:04:20.758366 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8042 11:04:20.761258 CH0 RK0: MR19=303, MR18=1515
8043 11:04:20.767932 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
8044 11:04:20.768016
8045 11:04:20.771188 ----->DramcWriteLeveling(PI) begin...
8046 11:04:20.771265 ==
8047 11:04:20.774657 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 11:04:20.777856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 11:04:20.777932 ==
8050 11:04:20.781447 Write leveling (Byte 0): 34 => 34
8051 11:04:20.785211 Write leveling (Byte 1): 28 => 28
8052 11:04:20.788273 DramcWriteLeveling(PI) end<-----
8053 11:04:20.788349
8054 11:04:20.788407 ==
8055 11:04:20.791882 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 11:04:20.795323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 11:04:20.795399 ==
8058 11:04:20.798697 [Gating] SW mode calibration
8059 11:04:20.805053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8060 11:04:20.811459 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8061 11:04:20.814538 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 11:04:20.821552 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 11:04:20.824821 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 11:04:20.827587 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8065 11:04:20.834200 1 4 16 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8066 11:04:20.837643 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 11:04:20.841107 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 11:04:20.844364 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 11:04:20.851238 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 11:04:20.854247 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 11:04:20.857942 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8072 11:04:20.864716 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8073 11:04:20.867547 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8074 11:04:20.871026 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8075 11:04:20.877926 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 11:04:20.880645 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 11:04:20.884166 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 11:04:20.890938 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 11:04:20.894031 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8080 11:04:20.897316 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8081 11:04:20.903902 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
8082 11:04:20.907276 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 11:04:20.911072 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 11:04:20.917440 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 11:04:20.920390 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 11:04:20.923813 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 11:04:20.930533 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 11:04:20.933815 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 11:04:20.937179 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 11:04:20.943922 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 11:04:20.947160 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:04:20.950188 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:04:20.956695 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:04:20.960290 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:04:20.964046 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:04:20.970757 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:04:20.973623 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:04:20.977258 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:04:20.983541 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:04:20.986872 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 11:04:20.990216 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:04:20.996444 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:04:20.999771 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 11:04:21.003256 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8105 11:04:21.006349 Total UI for P1: 0, mck2ui 16
8106 11:04:21.010010 best dqsien dly found for B0: ( 1, 9, 8)
8107 11:04:21.016168 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 11:04:21.019800 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 11:04:21.022684 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 11:04:21.026285 Total UI for P1: 0, mck2ui 16
8111 11:04:21.029523 best dqsien dly found for B1: ( 1, 9, 18)
8112 11:04:21.032731 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8113 11:04:21.036203 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8114 11:04:21.036276
8115 11:04:21.042842 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8116 11:04:21.046033 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8117 11:04:21.046139 [Gating] SW calibration Done
8118 11:04:21.049471 ==
8119 11:04:21.052890 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 11:04:21.055982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 11:04:21.056052 ==
8122 11:04:21.056109 RX Vref Scan: 0
8123 11:04:21.056168
8124 11:04:21.059279 RX Vref 0 -> 0, step: 1
8125 11:04:21.059341
8126 11:04:21.062978 RX Delay 0 -> 252, step: 8
8127 11:04:21.065886 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8128 11:04:21.069617 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8129 11:04:21.072604 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8130 11:04:21.079111 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8131 11:04:21.082621 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8132 11:04:21.086201 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8133 11:04:21.089102 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8134 11:04:21.092327 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8135 11:04:21.099204 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8136 11:04:21.102878 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8137 11:04:21.106027 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8138 11:04:21.109265 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8139 11:04:21.112635 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8140 11:04:21.119078 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8141 11:04:21.122392 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8142 11:04:21.125731 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8143 11:04:21.125798 ==
8144 11:04:21.129160 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 11:04:21.132190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 11:04:21.135742 ==
8147 11:04:21.135809 DQS Delay:
8148 11:04:21.135866 DQS0 = 0, DQS1 = 0
8149 11:04:21.139060 DQM Delay:
8150 11:04:21.139127 DQM0 = 128, DQM1 = 120
8151 11:04:21.142467 DQ Delay:
8152 11:04:21.145500 DQ0 =127, DQ1 =127, DQ2 =127, DQ3 =123
8153 11:04:21.148848 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8154 11:04:21.152269 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8155 11:04:21.155536 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8156 11:04:21.155602
8157 11:04:21.155659
8158 11:04:21.155710 ==
8159 11:04:21.158666 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 11:04:21.162031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 11:04:21.162094 ==
8162 11:04:21.162158
8163 11:04:21.165373
8164 11:04:21.165450 TX Vref Scan disable
8165 11:04:21.169188 == TX Byte 0 ==
8166 11:04:21.172296 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8167 11:04:21.175416 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8168 11:04:21.178732 == TX Byte 1 ==
8169 11:04:21.182313 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8170 11:04:21.185489 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8171 11:04:21.185555 ==
8172 11:04:21.188823 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 11:04:21.195281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 11:04:21.195353 ==
8175 11:04:21.208392
8176 11:04:21.211964 TX Vref early break, caculate TX vref
8177 11:04:21.215055 TX Vref=16, minBit 8, minWin=21, winSum=364
8178 11:04:21.218599 TX Vref=18, minBit 8, minWin=22, winSum=376
8179 11:04:21.222001 TX Vref=20, minBit 0, minWin=23, winSum=383
8180 11:04:21.225026 TX Vref=22, minBit 1, minWin=24, winSum=392
8181 11:04:21.228747 TX Vref=24, minBit 1, minWin=24, winSum=397
8182 11:04:21.234959 TX Vref=26, minBit 1, minWin=23, winSum=401
8183 11:04:21.238240 TX Vref=28, minBit 8, minWin=24, winSum=409
8184 11:04:21.241589 TX Vref=30, minBit 8, minWin=24, winSum=401
8185 11:04:21.245382 TX Vref=32, minBit 8, minWin=23, winSum=391
8186 11:04:21.248935 TX Vref=34, minBit 8, minWin=22, winSum=389
8187 11:04:21.251416 TX Vref=36, minBit 8, minWin=22, winSum=377
8188 11:04:21.258536 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
8189 11:04:21.258614
8190 11:04:21.261532 Final TX Range 0 Vref 28
8191 11:04:21.261607
8192 11:04:21.261664 ==
8193 11:04:21.265562 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 11:04:21.268332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 11:04:21.268411 ==
8196 11:04:21.268481
8197 11:04:21.268538
8198 11:04:21.271504 TX Vref Scan disable
8199 11:04:21.278372 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8200 11:04:21.278451 == TX Byte 0 ==
8201 11:04:21.281694 u2DelayCellOfst[0]=15 cells (4 PI)
8202 11:04:21.284777 u2DelayCellOfst[1]=22 cells (6 PI)
8203 11:04:21.288230 u2DelayCellOfst[2]=15 cells (4 PI)
8204 11:04:21.291268 u2DelayCellOfst[3]=15 cells (4 PI)
8205 11:04:21.294851 u2DelayCellOfst[4]=11 cells (3 PI)
8206 11:04:21.298147 u2DelayCellOfst[5]=0 cells (0 PI)
8207 11:04:21.301819 u2DelayCellOfst[6]=22 cells (6 PI)
8208 11:04:21.305056 u2DelayCellOfst[7]=22 cells (6 PI)
8209 11:04:21.307971 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8210 11:04:21.311542 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8211 11:04:21.314596 == TX Byte 1 ==
8212 11:04:21.318159 u2DelayCellOfst[8]=3 cells (1 PI)
8213 11:04:21.321469 u2DelayCellOfst[9]=0 cells (0 PI)
8214 11:04:21.321545 u2DelayCellOfst[10]=7 cells (2 PI)
8215 11:04:21.324952 u2DelayCellOfst[11]=3 cells (1 PI)
8216 11:04:21.327969 u2DelayCellOfst[12]=15 cells (4 PI)
8217 11:04:21.331655 u2DelayCellOfst[13]=11 cells (3 PI)
8218 11:04:21.335000 u2DelayCellOfst[14]=15 cells (4 PI)
8219 11:04:21.337932 u2DelayCellOfst[15]=11 cells (3 PI)
8220 11:04:21.344493 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8221 11:04:21.348411 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8222 11:04:21.348488 DramC Write-DBI on
8223 11:04:21.348547 ==
8224 11:04:21.351076 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 11:04:21.357754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 11:04:21.357833 ==
8227 11:04:21.357891
8228 11:04:21.357944
8229 11:04:21.358011 TX Vref Scan disable
8230 11:04:21.361997 == TX Byte 0 ==
8231 11:04:21.365578 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8232 11:04:21.369158 == TX Byte 1 ==
8233 11:04:21.371915 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8234 11:04:21.375464 DramC Write-DBI off
8235 11:04:21.375540
8236 11:04:21.375596 [DATLAT]
8237 11:04:21.375649 Freq=1600, CH0 RK1
8238 11:04:21.375699
8239 11:04:21.378976 DATLAT Default: 0xf
8240 11:04:21.379051 0, 0xFFFF, sum = 0
8241 11:04:21.381951 1, 0xFFFF, sum = 0
8242 11:04:21.382027 2, 0xFFFF, sum = 0
8243 11:04:21.385117 3, 0xFFFF, sum = 0
8244 11:04:21.389236 4, 0xFFFF, sum = 0
8245 11:04:21.389318 5, 0xFFFF, sum = 0
8246 11:04:21.392023 6, 0xFFFF, sum = 0
8247 11:04:21.392104 7, 0xFFFF, sum = 0
8248 11:04:21.395925 8, 0xFFFF, sum = 0
8249 11:04:21.396017 9, 0xFFFF, sum = 0
8250 11:04:21.398631 10, 0xFFFF, sum = 0
8251 11:04:21.398709 11, 0xFFFF, sum = 0
8252 11:04:21.401878 12, 0xFFFF, sum = 0
8253 11:04:21.401958 13, 0xCFFF, sum = 0
8254 11:04:21.405234 14, 0x0, sum = 1
8255 11:04:21.405316 15, 0x0, sum = 2
8256 11:04:21.408459 16, 0x0, sum = 3
8257 11:04:21.408542 17, 0x0, sum = 4
8258 11:04:21.411768 best_step = 15
8259 11:04:21.411847
8260 11:04:21.411904 ==
8261 11:04:21.415103 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 11:04:21.418373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 11:04:21.418463 ==
8264 11:04:21.421699 RX Vref Scan: 0
8265 11:04:21.421780
8266 11:04:21.421888 RX Vref 0 -> 0, step: 1
8267 11:04:21.421943
8268 11:04:21.425431 RX Delay 3 -> 252, step: 4
8269 11:04:21.428586 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8270 11:04:21.435053 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8271 11:04:21.438170 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8272 11:04:21.441576 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8273 11:04:21.444922 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8274 11:04:21.448588 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8275 11:04:21.455153 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8276 11:04:21.458591 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8277 11:04:21.461744 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8278 11:04:21.465426 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8279 11:04:21.468302 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8280 11:04:21.475161 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8281 11:04:21.478282 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8282 11:04:21.481710 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8283 11:04:21.485382 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8284 11:04:21.491866 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8285 11:04:21.491942 ==
8286 11:04:21.495156 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 11:04:21.498352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 11:04:21.498427 ==
8289 11:04:21.498484 DQS Delay:
8290 11:04:21.501501 DQS0 = 0, DQS1 = 0
8291 11:04:21.501575 DQM Delay:
8292 11:04:21.505028 DQM0 = 124, DQM1 = 117
8293 11:04:21.505103 DQ Delay:
8294 11:04:21.508228 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8295 11:04:21.511427 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8296 11:04:21.514614 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8297 11:04:21.518202 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8298 11:04:21.518277
8299 11:04:21.518335
8300 11:04:21.518387
8301 11:04:21.521437 [DramC_TX_OE_Calibration] TA2
8302 11:04:21.524614 Original DQ_B0 (3 6) =30, OEN = 27
8303 11:04:21.527932 Original DQ_B1 (3 6) =30, OEN = 27
8304 11:04:21.531115 24, 0x0, End_B0=24 End_B1=24
8305 11:04:21.534681 25, 0x0, End_B0=25 End_B1=25
8306 11:04:21.534758 26, 0x0, End_B0=26 End_B1=26
8307 11:04:21.537866 27, 0x0, End_B0=27 End_B1=27
8308 11:04:21.541434 28, 0x0, End_B0=28 End_B1=28
8309 11:04:21.544713 29, 0x0, End_B0=29 End_B1=29
8310 11:04:21.547956 30, 0x0, End_B0=30 End_B1=30
8311 11:04:21.548034 31, 0x4141, End_B0=30 End_B1=30
8312 11:04:21.551170 Byte0 end_step=30 best_step=27
8313 11:04:21.554292 Byte1 end_step=30 best_step=27
8314 11:04:21.558005 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 11:04:21.560875 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 11:04:21.560955
8317 11:04:21.561013
8318 11:04:21.567462 [DQSOSCAuto] RK1, (LSB)MR18= 0x2815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
8319 11:04:21.571045 CH0 RK1: MR19=303, MR18=2815
8320 11:04:21.578054 CH0_RK1: MR19=0x303, MR18=0x2815, DQSOSC=389, MR23=63, INC=24, DEC=16
8321 11:04:21.580900 [RxdqsGatingPostProcess] freq 1600
8322 11:04:21.587878 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 11:04:21.587959 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 11:04:21.591080 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 11:04:21.594056 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 11:04:21.597531 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 11:04:21.601151 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 11:04:21.604352 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 11:04:21.607504 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 11:04:21.611094 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 11:04:21.614001 Pre-setting of DQS Precalculation
8332 11:04:21.617420 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 11:04:21.621118 ==
8334 11:04:21.621207 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 11:04:21.627627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 11:04:21.627729 ==
8337 11:04:21.630445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 11:04:21.637157 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 11:04:21.640424 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 11:04:21.647077 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 11:04:21.655339 [CA 0] Center 41 (12~71) winsize 60
8342 11:04:21.658908 [CA 1] Center 42 (12~72) winsize 61
8343 11:04:21.661635 [CA 2] Center 38 (9~67) winsize 59
8344 11:04:21.665181 [CA 3] Center 36 (7~66) winsize 60
8345 11:04:21.668593 [CA 4] Center 37 (8~67) winsize 60
8346 11:04:21.671636 [CA 5] Center 36 (7~66) winsize 60
8347 11:04:21.671712
8348 11:04:21.675248 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 11:04:21.675325
8350 11:04:21.678277 [CATrainingPosCal] consider 1 rank data
8351 11:04:21.681909 u2DelayCellTimex100 = 258/100 ps
8352 11:04:21.684870 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8353 11:04:21.691839 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8354 11:04:21.695055 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8355 11:04:21.698621 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8356 11:04:21.702046 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8357 11:04:21.704928 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 11:04:21.705003
8359 11:04:21.708443 CA PerBit enable=1, Macro0, CA PI delay=36
8360 11:04:21.708529
8361 11:04:21.711871 [CBTSetCACLKResult] CA Dly = 36
8362 11:04:21.715251 CS Dly: 10 (0~41)
8363 11:04:21.718449 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 11:04:21.721566 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 11:04:21.721642 ==
8366 11:04:21.725534 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 11:04:21.728154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 11:04:21.731617 ==
8369 11:04:21.735129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 11:04:21.738153 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 11:04:21.745313 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 11:04:21.747959 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 11:04:21.758347 [CA 0] Center 41 (12~71) winsize 60
8374 11:04:21.762054 [CA 1] Center 42 (13~72) winsize 60
8375 11:04:21.764931 [CA 2] Center 37 (8~67) winsize 60
8376 11:04:21.768717 [CA 3] Center 36 (7~66) winsize 60
8377 11:04:21.771685 [CA 4] Center 37 (8~67) winsize 60
8378 11:04:21.774813 [CA 5] Center 36 (6~66) winsize 61
8379 11:04:21.774892
8380 11:04:21.778361 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8381 11:04:21.778473
8382 11:04:21.781741 [CATrainingPosCal] consider 2 rank data
8383 11:04:21.785009 u2DelayCellTimex100 = 258/100 ps
8384 11:04:21.788141 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8385 11:04:21.795081 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8386 11:04:21.798404 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8387 11:04:21.801933 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8388 11:04:21.804989 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8389 11:04:21.808528 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 11:04:21.808602
8391 11:04:21.811581 CA PerBit enable=1, Macro0, CA PI delay=36
8392 11:04:21.811648
8393 11:04:21.815109 [CBTSetCACLKResult] CA Dly = 36
8394 11:04:21.818789 CS Dly: 11 (0~43)
8395 11:04:21.821771 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 11:04:21.824706 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 11:04:21.824787
8398 11:04:21.828017 ----->DramcWriteLeveling(PI) begin...
8399 11:04:21.828096 ==
8400 11:04:21.831725 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 11:04:21.834978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 11:04:21.838411 ==
8403 11:04:21.838488 Write leveling (Byte 0): 27 => 27
8404 11:04:21.841349 Write leveling (Byte 1): 29 => 29
8405 11:04:21.845078 DramcWriteLeveling(PI) end<-----
8406 11:04:21.845153
8407 11:04:21.845209 ==
8408 11:04:21.848023 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 11:04:21.854604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 11:04:21.854680 ==
8411 11:04:21.858251 [Gating] SW mode calibration
8412 11:04:21.864902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 11:04:21.867868 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 11:04:21.874428 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 11:04:21.878034 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 11:04:21.881032 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 11:04:21.887811 1 4 12 | B1->B0 | 2525 2322 | 1 1 | (1 1) (1 1)
8418 11:04:21.891666 1 4 16 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8419 11:04:21.894268 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 11:04:21.901695 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 11:04:21.904563 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 11:04:21.908401 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 11:04:21.911440 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 11:04:21.917547 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 11:04:21.920800 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8426 11:04:21.927809 1 5 16 | B1->B0 | 2424 2525 | 0 0 | (1 0) (1 0)
8427 11:04:21.930885 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:04:21.934347 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 11:04:21.937472 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 11:04:21.943936 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 11:04:21.947373 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 11:04:21.954118 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 11:04:21.957072 1 6 12 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
8434 11:04:21.960674 1 6 16 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
8435 11:04:21.963678 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 11:04:21.970649 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 11:04:21.973667 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 11:04:21.977015 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 11:04:21.983978 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 11:04:21.987229 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 11:04:21.991032 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8442 11:04:21.997230 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:04:22.000700 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8444 11:04:22.003755 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:04:22.010484 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:04:22.013915 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:04:22.017028 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:04:22.023898 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:04:22.026862 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:04:22.030215 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:04:22.036850 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:04:22.040341 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:04:22.043471 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:04:22.050263 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 11:04:22.053478 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 11:04:22.056990 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 11:04:22.063575 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8458 11:04:22.066640 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 11:04:22.070385 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8460 11:04:22.073295 Total UI for P1: 0, mck2ui 16
8461 11:04:22.076579 best dqsien dly found for B0: ( 1, 9, 14)
8462 11:04:22.083554 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 11:04:22.083625 Total UI for P1: 0, mck2ui 16
8464 11:04:22.086701 best dqsien dly found for B1: ( 1, 9, 16)
8465 11:04:22.093248 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8466 11:04:22.096920 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8467 11:04:22.097012
8468 11:04:22.099964 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8469 11:04:22.103266 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8470 11:04:22.106449 [Gating] SW calibration Done
8471 11:04:22.106518 ==
8472 11:04:22.110250 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 11:04:22.113180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 11:04:22.113269 ==
8475 11:04:22.116382 RX Vref Scan: 0
8476 11:04:22.116444
8477 11:04:22.116500 RX Vref 0 -> 0, step: 1
8478 11:04:22.116551
8479 11:04:22.120047 RX Delay 0 -> 252, step: 8
8480 11:04:22.123214 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8481 11:04:22.129828 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8482 11:04:22.133267 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8483 11:04:22.137033 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8484 11:04:22.139802 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8485 11:04:22.143574 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8486 11:04:22.146367 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8487 11:04:22.153407 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8488 11:04:22.156770 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8489 11:04:22.159796 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8490 11:04:22.163026 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8491 11:04:22.166489 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8492 11:04:22.173007 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8493 11:04:22.176581 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8494 11:04:22.179838 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8495 11:04:22.182736 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8496 11:04:22.182802 ==
8497 11:04:22.186367 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 11:04:22.192764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 11:04:22.192865 ==
8500 11:04:22.192957 DQS Delay:
8501 11:04:22.196260 DQS0 = 0, DQS1 = 0
8502 11:04:22.196351 DQM Delay:
8503 11:04:22.199871 DQM0 = 132, DQM1 = 126
8504 11:04:22.199935 DQ Delay:
8505 11:04:22.203177 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8506 11:04:22.206206 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8507 11:04:22.209426 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8508 11:04:22.213301 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8509 11:04:22.213370
8510 11:04:22.213431
8511 11:04:22.213486 ==
8512 11:04:22.216404 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 11:04:22.222801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 11:04:22.222882 ==
8515 11:04:22.222941
8516 11:04:22.222994
8517 11:04:22.223043 TX Vref Scan disable
8518 11:04:22.225995 == TX Byte 0 ==
8519 11:04:22.229683 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8520 11:04:22.232997 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8521 11:04:22.236318 == TX Byte 1 ==
8522 11:04:22.239274 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8523 11:04:22.242850 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8524 11:04:22.246358 ==
8525 11:04:22.249627 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 11:04:22.252757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 11:04:22.252823 ==
8528 11:04:22.264833
8529 11:04:22.268232 TX Vref early break, caculate TX vref
8530 11:04:22.271856 TX Vref=16, minBit 8, minWin=21, winSum=363
8531 11:04:22.274864 TX Vref=18, minBit 9, minWin=22, winSum=371
8532 11:04:22.278312 TX Vref=20, minBit 10, minWin=22, winSum=379
8533 11:04:22.281457 TX Vref=22, minBit 8, minWin=23, winSum=388
8534 11:04:22.284622 TX Vref=24, minBit 11, minWin=23, winSum=403
8535 11:04:22.291580 TX Vref=26, minBit 9, minWin=24, winSum=413
8536 11:04:22.294616 TX Vref=28, minBit 12, minWin=25, winSum=417
8537 11:04:22.298035 TX Vref=30, minBit 9, minWin=24, winSum=412
8538 11:04:22.301580 TX Vref=32, minBit 9, minWin=24, winSum=404
8539 11:04:22.304798 TX Vref=34, minBit 1, minWin=23, winSum=392
8540 11:04:22.311341 [TxChooseVref] Worse bit 12, Min win 25, Win sum 417, Final Vref 28
8541 11:04:22.311451
8542 11:04:22.314901 Final TX Range 0 Vref 28
8543 11:04:22.314995
8544 11:04:22.315081 ==
8545 11:04:22.317974 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 11:04:22.321492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 11:04:22.321581 ==
8548 11:04:22.321666
8549 11:04:22.321745
8550 11:04:22.324316 TX Vref Scan disable
8551 11:04:22.330851 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8552 11:04:22.330949 == TX Byte 0 ==
8553 11:04:22.334864 u2DelayCellOfst[0]=18 cells (5 PI)
8554 11:04:22.337625 u2DelayCellOfst[1]=11 cells (3 PI)
8555 11:04:22.341086 u2DelayCellOfst[2]=0 cells (0 PI)
8556 11:04:22.344236 u2DelayCellOfst[3]=3 cells (1 PI)
8557 11:04:22.347545 u2DelayCellOfst[4]=7 cells (2 PI)
8558 11:04:22.350872 u2DelayCellOfst[5]=18 cells (5 PI)
8559 11:04:22.354524 u2DelayCellOfst[6]=18 cells (5 PI)
8560 11:04:22.357738 u2DelayCellOfst[7]=7 cells (2 PI)
8561 11:04:22.361052 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8562 11:04:22.364360 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8563 11:04:22.367772 == TX Byte 1 ==
8564 11:04:22.371165 u2DelayCellOfst[8]=0 cells (0 PI)
8565 11:04:22.371244 u2DelayCellOfst[9]=3 cells (1 PI)
8566 11:04:22.374620 u2DelayCellOfst[10]=11 cells (3 PI)
8567 11:04:22.377574 u2DelayCellOfst[11]=7 cells (2 PI)
8568 11:04:22.380474 u2DelayCellOfst[12]=15 cells (4 PI)
8569 11:04:22.384013 u2DelayCellOfst[13]=18 cells (5 PI)
8570 11:04:22.387146 u2DelayCellOfst[14]=18 cells (5 PI)
8571 11:04:22.390658 u2DelayCellOfst[15]=18 cells (5 PI)
8572 11:04:22.394335 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8573 11:04:22.401115 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8574 11:04:22.401193 DramC Write-DBI on
8575 11:04:22.401270 ==
8576 11:04:22.403818 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 11:04:22.410462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 11:04:22.410542 ==
8579 11:04:22.410618
8580 11:04:22.410688
8581 11:04:22.410757 TX Vref Scan disable
8582 11:04:22.414378 == TX Byte 0 ==
8583 11:04:22.417678 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8584 11:04:22.421552 == TX Byte 1 ==
8585 11:04:22.424277 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8586 11:04:22.427791 DramC Write-DBI off
8587 11:04:22.427868
8588 11:04:22.427944 [DATLAT]
8589 11:04:22.428015 Freq=1600, CH1 RK0
8590 11:04:22.428089
8591 11:04:22.430983 DATLAT Default: 0xf
8592 11:04:22.431082 0, 0xFFFF, sum = 0
8593 11:04:22.434974 1, 0xFFFF, sum = 0
8594 11:04:22.435052 2, 0xFFFF, sum = 0
8595 11:04:22.437410 3, 0xFFFF, sum = 0
8596 11:04:22.440904 4, 0xFFFF, sum = 0
8597 11:04:22.440982 5, 0xFFFF, sum = 0
8598 11:04:22.444473 6, 0xFFFF, sum = 0
8599 11:04:22.444552 7, 0xFFFF, sum = 0
8600 11:04:22.447455 8, 0xFFFF, sum = 0
8601 11:04:22.447534 9, 0xFFFF, sum = 0
8602 11:04:22.450856 10, 0xFFFF, sum = 0
8603 11:04:22.450935 11, 0xFFFF, sum = 0
8604 11:04:22.454255 12, 0xFFFF, sum = 0
8605 11:04:22.454382 13, 0x8FFF, sum = 0
8606 11:04:22.457401 14, 0x0, sum = 1
8607 11:04:22.457474 15, 0x0, sum = 2
8608 11:04:22.461053 16, 0x0, sum = 3
8609 11:04:22.461131 17, 0x0, sum = 4
8610 11:04:22.464124 best_step = 15
8611 11:04:22.464201
8612 11:04:22.464278 ==
8613 11:04:22.467690 Dram Type= 6, Freq= 0, CH_1, rank 0
8614 11:04:22.470663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8615 11:04:22.470742 ==
8616 11:04:22.470819 RX Vref Scan: 1
8617 11:04:22.474319
8618 11:04:22.474397 Set Vref Range= 24 -> 127
8619 11:04:22.474474
8620 11:04:22.477688 RX Vref 24 -> 127, step: 1
8621 11:04:22.477765
8622 11:04:22.480898 RX Delay 11 -> 252, step: 4
8623 11:04:22.480975
8624 11:04:22.483836 Set Vref, RX VrefLevel [Byte0]: 24
8625 11:04:22.487181 [Byte1]: 24
8626 11:04:22.487258
8627 11:04:22.490860 Set Vref, RX VrefLevel [Byte0]: 25
8628 11:04:22.494010 [Byte1]: 25
8629 11:04:22.494088
8630 11:04:22.497522 Set Vref, RX VrefLevel [Byte0]: 26
8631 11:04:22.500673 [Byte1]: 26
8632 11:04:22.504774
8633 11:04:22.504851 Set Vref, RX VrefLevel [Byte0]: 27
8634 11:04:22.508142 [Byte1]: 27
8635 11:04:22.512484
8636 11:04:22.512561 Set Vref, RX VrefLevel [Byte0]: 28
8637 11:04:22.515550 [Byte1]: 28
8638 11:04:22.519721
8639 11:04:22.519798 Set Vref, RX VrefLevel [Byte0]: 29
8640 11:04:22.523431 [Byte1]: 29
8641 11:04:22.527677
8642 11:04:22.527754 Set Vref, RX VrefLevel [Byte0]: 30
8643 11:04:22.531365 [Byte1]: 30
8644 11:04:22.535219
8645 11:04:22.535296 Set Vref, RX VrefLevel [Byte0]: 31
8646 11:04:22.538777 [Byte1]: 31
8647 11:04:22.542636
8648 11:04:22.542714 Set Vref, RX VrefLevel [Byte0]: 32
8649 11:04:22.546262 [Byte1]: 32
8650 11:04:22.550334
8651 11:04:22.550411 Set Vref, RX VrefLevel [Byte0]: 33
8652 11:04:22.553671 [Byte1]: 33
8653 11:04:22.557823
8654 11:04:22.557900 Set Vref, RX VrefLevel [Byte0]: 34
8655 11:04:22.561650 [Byte1]: 34
8656 11:04:22.565769
8657 11:04:22.565846 Set Vref, RX VrefLevel [Byte0]: 35
8658 11:04:22.568736 [Byte1]: 35
8659 11:04:22.573243
8660 11:04:22.573321 Set Vref, RX VrefLevel [Byte0]: 36
8661 11:04:22.576521 [Byte1]: 36
8662 11:04:22.581120
8663 11:04:22.581195 Set Vref, RX VrefLevel [Byte0]: 37
8664 11:04:22.584164 [Byte1]: 37
8665 11:04:22.588507
8666 11:04:22.588581 Set Vref, RX VrefLevel [Byte0]: 38
8667 11:04:22.591870 [Byte1]: 38
8668 11:04:22.596438
8669 11:04:22.596513 Set Vref, RX VrefLevel [Byte0]: 39
8670 11:04:22.599212 [Byte1]: 39
8671 11:04:22.603896
8672 11:04:22.603970 Set Vref, RX VrefLevel [Byte0]: 40
8673 11:04:22.607235 [Byte1]: 40
8674 11:04:22.611329
8675 11:04:22.611406 Set Vref, RX VrefLevel [Byte0]: 41
8676 11:04:22.614691 [Byte1]: 41
8677 11:04:22.618875
8678 11:04:22.618949 Set Vref, RX VrefLevel [Byte0]: 42
8679 11:04:22.622380 [Byte1]: 42
8680 11:04:22.626540
8681 11:04:22.626617 Set Vref, RX VrefLevel [Byte0]: 43
8682 11:04:22.630027 [Byte1]: 43
8683 11:04:22.634085
8684 11:04:22.634172 Set Vref, RX VrefLevel [Byte0]: 44
8685 11:04:22.637613 [Byte1]: 44
8686 11:04:22.641577
8687 11:04:22.641654 Set Vref, RX VrefLevel [Byte0]: 45
8688 11:04:22.644858 [Byte1]: 45
8689 11:04:22.649792
8690 11:04:22.649869 Set Vref, RX VrefLevel [Byte0]: 46
8691 11:04:22.652583 [Byte1]: 46
8692 11:04:22.656851
8693 11:04:22.656927 Set Vref, RX VrefLevel [Byte0]: 47
8694 11:04:22.660068 [Byte1]: 47
8695 11:04:22.664654
8696 11:04:22.664748 Set Vref, RX VrefLevel [Byte0]: 48
8697 11:04:22.667893 [Byte1]: 48
8698 11:04:22.672400
8699 11:04:22.672477 Set Vref, RX VrefLevel [Byte0]: 49
8700 11:04:22.675486 [Byte1]: 49
8701 11:04:22.679765
8702 11:04:22.679848 Set Vref, RX VrefLevel [Byte0]: 50
8703 11:04:22.683063 [Byte1]: 50
8704 11:04:22.687646
8705 11:04:22.687724 Set Vref, RX VrefLevel [Byte0]: 51
8706 11:04:22.691084 [Byte1]: 51
8707 11:04:22.695206
8708 11:04:22.695308 Set Vref, RX VrefLevel [Byte0]: 52
8709 11:04:22.698513 [Byte1]: 52
8710 11:04:22.703155
8711 11:04:22.703232 Set Vref, RX VrefLevel [Byte0]: 53
8712 11:04:22.705852 [Byte1]: 53
8713 11:04:22.710479
8714 11:04:22.710559 Set Vref, RX VrefLevel [Byte0]: 54
8715 11:04:22.713558 [Byte1]: 54
8716 11:04:22.718058
8717 11:04:22.718162 Set Vref, RX VrefLevel [Byte0]: 55
8718 11:04:22.721218 [Byte1]: 55
8719 11:04:22.725640
8720 11:04:22.725718 Set Vref, RX VrefLevel [Byte0]: 56
8721 11:04:22.729206 [Byte1]: 56
8722 11:04:22.733383
8723 11:04:22.733462 Set Vref, RX VrefLevel [Byte0]: 57
8724 11:04:22.736480 [Byte1]: 57
8725 11:04:22.740645
8726 11:04:22.740725 Set Vref, RX VrefLevel [Byte0]: 58
8727 11:04:22.744323 [Byte1]: 58
8728 11:04:22.748394
8729 11:04:22.748472 Set Vref, RX VrefLevel [Byte0]: 59
8730 11:04:22.751841 [Byte1]: 59
8731 11:04:22.756276
8732 11:04:22.756355 Set Vref, RX VrefLevel [Byte0]: 60
8733 11:04:22.759174 [Byte1]: 60
8734 11:04:22.764034
8735 11:04:22.764113 Set Vref, RX VrefLevel [Byte0]: 61
8736 11:04:22.766720 [Byte1]: 61
8737 11:04:22.771048
8738 11:04:22.771146 Set Vref, RX VrefLevel [Byte0]: 62
8739 11:04:22.774335 [Byte1]: 62
8740 11:04:22.778723
8741 11:04:22.778803 Set Vref, RX VrefLevel [Byte0]: 63
8742 11:04:22.782196 [Byte1]: 63
8743 11:04:22.786365
8744 11:04:22.786443 Set Vref, RX VrefLevel [Byte0]: 64
8745 11:04:22.789504 [Byte1]: 64
8746 11:04:22.794377
8747 11:04:22.794460 Set Vref, RX VrefLevel [Byte0]: 65
8748 11:04:22.797422 [Byte1]: 65
8749 11:04:22.801542
8750 11:04:22.801668 Set Vref, RX VrefLevel [Byte0]: 66
8751 11:04:22.805539 [Byte1]: 66
8752 11:04:22.809343
8753 11:04:22.809464 Set Vref, RX VrefLevel [Byte0]: 67
8754 11:04:22.812678 [Byte1]: 67
8755 11:04:22.817148
8756 11:04:22.817218 Set Vref, RX VrefLevel [Byte0]: 68
8757 11:04:22.820374 [Byte1]: 68
8758 11:04:22.824262
8759 11:04:22.824339 Set Vref, RX VrefLevel [Byte0]: 69
8760 11:04:22.827648 [Byte1]: 69
8761 11:04:22.832116
8762 11:04:22.832195 Set Vref, RX VrefLevel [Byte0]: 70
8763 11:04:22.835565 [Byte1]: 70
8764 11:04:22.839792
8765 11:04:22.839872 Final RX Vref Byte 0 = 59 to rank0
8766 11:04:22.843365 Final RX Vref Byte 1 = 53 to rank0
8767 11:04:22.846518 Final RX Vref Byte 0 = 59 to rank1
8768 11:04:22.849995 Final RX Vref Byte 1 = 53 to rank1==
8769 11:04:22.852952 Dram Type= 6, Freq= 0, CH_1, rank 0
8770 11:04:22.859993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 11:04:22.860077 ==
8772 11:04:22.860154 DQS Delay:
8773 11:04:22.860226 DQS0 = 0, DQS1 = 0
8774 11:04:22.863147 DQM Delay:
8775 11:04:22.863225 DQM0 = 130, DQM1 = 123
8776 11:04:22.866656 DQ Delay:
8777 11:04:22.869356 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8778 11:04:22.872981 DQ4 =128, DQ5 =142, DQ6 =140, DQ7 =128
8779 11:04:22.876271 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =116
8780 11:04:22.879629 DQ12 =134, DQ13 =130, DQ14 =132, DQ15 =130
8781 11:04:22.879707
8782 11:04:22.879783
8783 11:04:22.879854
8784 11:04:22.882631 [DramC_TX_OE_Calibration] TA2
8785 11:04:22.886329 Original DQ_B0 (3 6) =30, OEN = 27
8786 11:04:22.889313 Original DQ_B1 (3 6) =30, OEN = 27
8787 11:04:22.893063 24, 0x0, End_B0=24 End_B1=24
8788 11:04:22.893146 25, 0x0, End_B0=25 End_B1=25
8789 11:04:22.896307 26, 0x0, End_B0=26 End_B1=26
8790 11:04:22.899706 27, 0x0, End_B0=27 End_B1=27
8791 11:04:22.903052 28, 0x0, End_B0=28 End_B1=28
8792 11:04:22.903133 29, 0x0, End_B0=29 End_B1=29
8793 11:04:22.905998 30, 0x0, End_B0=30 End_B1=30
8794 11:04:22.909303 31, 0x4141, End_B0=30 End_B1=30
8795 11:04:22.912699 Byte0 end_step=30 best_step=27
8796 11:04:22.916377 Byte1 end_step=30 best_step=27
8797 11:04:22.919696 Byte0 TX OE(2T, 0.5T) = (3, 3)
8798 11:04:22.923111 Byte1 TX OE(2T, 0.5T) = (3, 3)
8799 11:04:22.923190
8800 11:04:22.923265
8801 11:04:22.929315 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8802 11:04:22.932516 CH1 RK0: MR19=303, MR18=A0E
8803 11:04:22.939466 CH1_RK0: MR19=0x303, MR18=0xA0E, DQSOSC=402, MR23=63, INC=22, DEC=15
8804 11:04:22.939578
8805 11:04:22.942352 ----->DramcWriteLeveling(PI) begin...
8806 11:04:22.942426 ==
8807 11:04:22.945897 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 11:04:22.949552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 11:04:22.949635 ==
8810 11:04:22.952773 Write leveling (Byte 0): 22 => 22
8811 11:04:22.956235 Write leveling (Byte 1): 29 => 29
8812 11:04:22.959059 DramcWriteLeveling(PI) end<-----
8813 11:04:22.959137
8814 11:04:22.959194 ==
8815 11:04:22.962797 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 11:04:22.966040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 11:04:22.966177 ==
8818 11:04:22.969132 [Gating] SW mode calibration
8819 11:04:22.976226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8820 11:04:22.982590 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8821 11:04:22.985927 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 11:04:22.988963 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 11:04:22.995846 1 4 8 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
8824 11:04:22.999382 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8825 11:04:23.002765 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 11:04:23.008970 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 11:04:23.012453 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 11:04:23.015760 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 11:04:23.022219 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 11:04:23.025436 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8831 11:04:23.029015 1 5 8 | B1->B0 | 3434 2929 | 0 1 | (0 1) (1 0)
8832 11:04:23.035395 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8833 11:04:23.038858 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:04:23.042031 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:04:23.049833 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:04:23.052216 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 11:04:23.055585 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 11:04:23.062016 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 11:04:23.065418 1 6 8 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
8840 11:04:23.068902 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8841 11:04:23.072002 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:04:23.078842 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:04:23.082622 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 11:04:23.085440 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 11:04:23.092103 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 11:04:23.095897 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 11:04:23.098733 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8848 11:04:23.105748 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8849 11:04:23.108604 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:04:23.111965 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:04:23.118658 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:04:23.122363 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:04:23.125595 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:04:23.132422 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:04:23.135278 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:04:23.138874 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:04:23.145556 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:04:23.148517 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:04:23.151929 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:04:23.158369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:04:23.161908 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:04:23.165472 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:04:23.172318 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8864 11:04:23.175151 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8865 11:04:23.178939 Total UI for P1: 0, mck2ui 16
8866 11:04:23.182423 best dqsien dly found for B0: ( 1, 9, 8)
8867 11:04:23.185435 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 11:04:23.188721 Total UI for P1: 0, mck2ui 16
8869 11:04:23.192097 best dqsien dly found for B1: ( 1, 9, 10)
8870 11:04:23.195101 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8871 11:04:23.198299 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8872 11:04:23.198375
8873 11:04:23.201660 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8874 11:04:23.208437 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8875 11:04:23.208521 [Gating] SW calibration Done
8876 11:04:23.208580 ==
8877 11:04:23.211561 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 11:04:23.218081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 11:04:23.218196 ==
8880 11:04:23.218255 RX Vref Scan: 0
8881 11:04:23.218307
8882 11:04:23.221602 RX Vref 0 -> 0, step: 1
8883 11:04:23.221678
8884 11:04:23.224857 RX Delay 0 -> 252, step: 8
8885 11:04:23.228275 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8886 11:04:23.231727 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8887 11:04:23.235115 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8888 11:04:23.241369 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8889 11:04:23.244811 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8890 11:04:23.247834 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8891 11:04:23.251416 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8892 11:04:23.254432 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8893 11:04:23.261022 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8894 11:04:23.264659 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8895 11:04:23.267880 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8896 11:04:23.271304 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8897 11:04:23.274505 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8898 11:04:23.280896 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8899 11:04:23.284619 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8900 11:04:23.287877 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8901 11:04:23.287955 ==
8902 11:04:23.290828 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 11:04:23.294116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 11:04:23.297934 ==
8905 11:04:23.298040 DQS Delay:
8906 11:04:23.298163 DQS0 = 0, DQS1 = 0
8907 11:04:23.300973 DQM Delay:
8908 11:04:23.301048 DQM0 = 129, DQM1 = 128
8909 11:04:23.304291 DQ Delay:
8910 11:04:23.307853 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =123
8911 11:04:23.310969 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8912 11:04:23.314373 DQ8 =111, DQ9 =115, DQ10 =135, DQ11 =123
8913 11:04:23.317383 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8914 11:04:23.317459
8915 11:04:23.317517
8916 11:04:23.317570 ==
8917 11:04:23.320762 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 11:04:23.324442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 11:04:23.324519 ==
8920 11:04:23.324577
8921 11:04:23.327528
8922 11:04:23.327602 TX Vref Scan disable
8923 11:04:23.330890 == TX Byte 0 ==
8924 11:04:23.334507 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8925 11:04:23.337538 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8926 11:04:23.340471 == TX Byte 1 ==
8927 11:04:23.344065 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8928 11:04:23.347253 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8929 11:04:23.347329 ==
8930 11:04:23.350560 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 11:04:23.357121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 11:04:23.357200 ==
8933 11:04:23.370863
8934 11:04:23.373787 TX Vref early break, caculate TX vref
8935 11:04:23.377659 TX Vref=16, minBit 0, minWin=22, winSum=371
8936 11:04:23.380930 TX Vref=18, minBit 0, minWin=23, winSum=381
8937 11:04:23.383941 TX Vref=20, minBit 0, minWin=24, winSum=395
8938 11:04:23.387438 TX Vref=22, minBit 0, minWin=23, winSum=397
8939 11:04:23.390919 TX Vref=24, minBit 0, minWin=25, winSum=405
8940 11:04:23.397021 TX Vref=26, minBit 0, minWin=25, winSum=410
8941 11:04:23.400810 TX Vref=28, minBit 0, minWin=25, winSum=415
8942 11:04:23.403601 TX Vref=30, minBit 0, minWin=25, winSum=411
8943 11:04:23.407038 TX Vref=32, minBit 5, minWin=23, winSum=402
8944 11:04:23.410353 TX Vref=34, minBit 5, minWin=22, winSum=399
8945 11:04:23.413879 TX Vref=36, minBit 0, minWin=23, winSum=388
8946 11:04:23.420405 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8947 11:04:23.420491
8948 11:04:23.423532 Final TX Range 0 Vref 28
8949 11:04:23.423603
8950 11:04:23.423661 ==
8951 11:04:23.427059 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 11:04:23.429996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 11:04:23.430095 ==
8954 11:04:23.430207
8955 11:04:23.433514
8956 11:04:23.433590 TX Vref Scan disable
8957 11:04:23.440231 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8958 11:04:23.440310 == TX Byte 0 ==
8959 11:04:23.443495 u2DelayCellOfst[0]=18 cells (5 PI)
8960 11:04:23.446571 u2DelayCellOfst[1]=11 cells (3 PI)
8961 11:04:23.450126 u2DelayCellOfst[2]=0 cells (0 PI)
8962 11:04:23.453265 u2DelayCellOfst[3]=7 cells (2 PI)
8963 11:04:23.456496 u2DelayCellOfst[4]=11 cells (3 PI)
8964 11:04:23.459981 u2DelayCellOfst[5]=22 cells (6 PI)
8965 11:04:23.463347 u2DelayCellOfst[6]=18 cells (5 PI)
8966 11:04:23.466391 u2DelayCellOfst[7]=7 cells (2 PI)
8967 11:04:23.469956 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8968 11:04:23.473210 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8969 11:04:23.476843 == TX Byte 1 ==
8970 11:04:23.480211 u2DelayCellOfst[8]=0 cells (0 PI)
8971 11:04:23.483208 u2DelayCellOfst[9]=7 cells (2 PI)
8972 11:04:23.483286 u2DelayCellOfst[10]=15 cells (4 PI)
8973 11:04:23.486984 u2DelayCellOfst[11]=7 cells (2 PI)
8974 11:04:23.489990 u2DelayCellOfst[12]=18 cells (5 PI)
8975 11:04:23.493036 u2DelayCellOfst[13]=18 cells (5 PI)
8976 11:04:23.496457 u2DelayCellOfst[14]=18 cells (5 PI)
8977 11:04:23.499732 u2DelayCellOfst[15]=18 cells (5 PI)
8978 11:04:23.506703 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8979 11:04:23.509977 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8980 11:04:23.510082 DramC Write-DBI on
8981 11:04:23.510186 ==
8982 11:04:23.513246 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 11:04:23.519524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 11:04:23.519605 ==
8985 11:04:23.519664
8986 11:04:23.519717
8987 11:04:23.519768 TX Vref Scan disable
8988 11:04:23.524267 == TX Byte 0 ==
8989 11:04:23.527163 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8990 11:04:23.530709 == TX Byte 1 ==
8991 11:04:23.533829 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8992 11:04:23.537263 DramC Write-DBI off
8993 11:04:23.537339
8994 11:04:23.537397 [DATLAT]
8995 11:04:23.537450 Freq=1600, CH1 RK1
8996 11:04:23.537502
8997 11:04:23.540583 DATLAT Default: 0xf
8998 11:04:23.540659 0, 0xFFFF, sum = 0
8999 11:04:23.543974 1, 0xFFFF, sum = 0
9000 11:04:23.547015 2, 0xFFFF, sum = 0
9001 11:04:23.547092 3, 0xFFFF, sum = 0
9002 11:04:23.550238 4, 0xFFFF, sum = 0
9003 11:04:23.550318 5, 0xFFFF, sum = 0
9004 11:04:23.553502 6, 0xFFFF, sum = 0
9005 11:04:23.553581 7, 0xFFFF, sum = 0
9006 11:04:23.557456 8, 0xFFFF, sum = 0
9007 11:04:23.557535 9, 0xFFFF, sum = 0
9008 11:04:23.560714 10, 0xFFFF, sum = 0
9009 11:04:23.560793 11, 0xFFFF, sum = 0
9010 11:04:23.563827 12, 0xFFFF, sum = 0
9011 11:04:23.563906 13, 0x8FFF, sum = 0
9012 11:04:23.567330 14, 0x0, sum = 1
9013 11:04:23.567408 15, 0x0, sum = 2
9014 11:04:23.570118 16, 0x0, sum = 3
9015 11:04:23.570210 17, 0x0, sum = 4
9016 11:04:23.573700 best_step = 15
9017 11:04:23.573777
9018 11:04:23.573854 ==
9019 11:04:23.576856 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 11:04:23.580452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 11:04:23.580530 ==
9022 11:04:23.583480 RX Vref Scan: 0
9023 11:04:23.583556
9024 11:04:23.583631 RX Vref 0 -> 0, step: 1
9025 11:04:23.583703
9026 11:04:23.587102 RX Delay 3 -> 252, step: 4
9027 11:04:23.590816 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9028 11:04:23.596817 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9029 11:04:23.600281 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9030 11:04:23.603329 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9031 11:04:23.606509 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
9032 11:04:23.610006 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9033 11:04:23.616546 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9034 11:04:23.619998 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9035 11:04:23.623585 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
9036 11:04:23.627080 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9037 11:04:23.630038 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
9038 11:04:23.636225 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9039 11:04:23.639820 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9040 11:04:23.643514 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9041 11:04:23.646195 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9042 11:04:23.653142 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9043 11:04:23.653225 ==
9044 11:04:23.656681 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 11:04:23.660022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 11:04:23.660101 ==
9047 11:04:23.660178 DQS Delay:
9048 11:04:23.662865 DQS0 = 0, DQS1 = 0
9049 11:04:23.662943 DQM Delay:
9050 11:04:23.666256 DQM0 = 127, DQM1 = 124
9051 11:04:23.666334 DQ Delay:
9052 11:04:23.669917 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =124
9053 11:04:23.672827 DQ4 =122, DQ5 =138, DQ6 =138, DQ7 =124
9054 11:04:23.676098 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =120
9055 11:04:23.679597 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9056 11:04:23.679680
9057 11:04:23.679757
9058 11:04:23.682914
9059 11:04:23.682993 [DramC_TX_OE_Calibration] TA2
9060 11:04:23.686130 Original DQ_B0 (3 6) =30, OEN = 27
9061 11:04:23.689425 Original DQ_B1 (3 6) =30, OEN = 27
9062 11:04:23.693153 24, 0x0, End_B0=24 End_B1=24
9063 11:04:23.696052 25, 0x0, End_B0=25 End_B1=25
9064 11:04:23.699611 26, 0x0, End_B0=26 End_B1=26
9065 11:04:23.699692 27, 0x0, End_B0=27 End_B1=27
9066 11:04:23.702646 28, 0x0, End_B0=28 End_B1=28
9067 11:04:23.706282 29, 0x0, End_B0=29 End_B1=29
9068 11:04:23.709986 30, 0x0, End_B0=30 End_B1=30
9069 11:04:23.712921 31, 0x4141, End_B0=30 End_B1=30
9070 11:04:23.713005 Byte0 end_step=30 best_step=27
9071 11:04:23.716222 Byte1 end_step=30 best_step=27
9072 11:04:23.719195 Byte0 TX OE(2T, 0.5T) = (3, 3)
9073 11:04:23.722754 Byte1 TX OE(2T, 0.5T) = (3, 3)
9074 11:04:23.722836
9075 11:04:23.722913
9076 11:04:23.729901 [DQSOSCAuto] RK1, (LSB)MR18= 0x1421, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
9077 11:04:23.732524 CH1 RK1: MR19=303, MR18=1421
9078 11:04:23.739446 CH1_RK1: MR19=0x303, MR18=0x1421, DQSOSC=393, MR23=63, INC=23, DEC=15
9079 11:04:23.742722 [RxdqsGatingPostProcess] freq 1600
9080 11:04:23.749088 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9081 11:04:23.752614 best DQS0 dly(2T, 0.5T) = (1, 1)
9082 11:04:23.752699 best DQS1 dly(2T, 0.5T) = (1, 1)
9083 11:04:23.755708 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9084 11:04:23.759115 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9085 11:04:23.762593 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 11:04:23.766127 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 11:04:23.769233 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 11:04:23.772994 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 11:04:23.775683 Pre-setting of DQS Precalculation
9090 11:04:23.779305 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9091 11:04:23.788975 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9092 11:04:23.795687 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 11:04:23.795782
9094 11:04:23.795860
9095 11:04:23.799228 [Calibration Summary] 3200 Mbps
9096 11:04:23.799307 CH 0, Rank 0
9097 11:04:23.802113 SW Impedance : PASS
9098 11:04:23.802191 DUTY Scan : NO K
9099 11:04:23.805318 ZQ Calibration : PASS
9100 11:04:23.808958 Jitter Meter : NO K
9101 11:04:23.809036 CBT Training : PASS
9102 11:04:23.812075 Write leveling : PASS
9103 11:04:23.815357 RX DQS gating : PASS
9104 11:04:23.815455 RX DQ/DQS(RDDQC) : PASS
9105 11:04:23.819019 TX DQ/DQS : PASS
9106 11:04:23.822034 RX DATLAT : PASS
9107 11:04:23.822169 RX DQ/DQS(Engine): PASS
9108 11:04:23.825531 TX OE : PASS
9109 11:04:23.825622 All Pass.
9110 11:04:23.825680
9111 11:04:23.828681 CH 0, Rank 1
9112 11:04:23.828761 SW Impedance : PASS
9113 11:04:23.832344 DUTY Scan : NO K
9114 11:04:23.835597 ZQ Calibration : PASS
9115 11:04:23.835678 Jitter Meter : NO K
9116 11:04:23.838516 CBT Training : PASS
9117 11:04:23.841879 Write leveling : PASS
9118 11:04:23.841963 RX DQS gating : PASS
9119 11:04:23.845364 RX DQ/DQS(RDDQC) : PASS
9120 11:04:23.849017 TX DQ/DQS : PASS
9121 11:04:23.849095 RX DATLAT : PASS
9122 11:04:23.851893 RX DQ/DQS(Engine): PASS
9123 11:04:23.851971 TX OE : PASS
9124 11:04:23.855412 All Pass.
9125 11:04:23.855489
9126 11:04:23.855547 CH 1, Rank 0
9127 11:04:23.858813 SW Impedance : PASS
9128 11:04:23.858906 DUTY Scan : NO K
9129 11:04:23.861888 ZQ Calibration : PASS
9130 11:04:23.865446 Jitter Meter : NO K
9131 11:04:23.865522 CBT Training : PASS
9132 11:04:23.868337 Write leveling : PASS
9133 11:04:23.871703 RX DQS gating : PASS
9134 11:04:23.871786 RX DQ/DQS(RDDQC) : PASS
9135 11:04:23.875231 TX DQ/DQS : PASS
9136 11:04:23.878704 RX DATLAT : PASS
9137 11:04:23.878781 RX DQ/DQS(Engine): PASS
9138 11:04:23.881786 TX OE : PASS
9139 11:04:23.881864 All Pass.
9140 11:04:23.881921
9141 11:04:23.885310 CH 1, Rank 1
9142 11:04:23.885388 SW Impedance : PASS
9143 11:04:23.888267 DUTY Scan : NO K
9144 11:04:23.892102 ZQ Calibration : PASS
9145 11:04:23.892181 Jitter Meter : NO K
9146 11:04:23.894757 CBT Training : PASS
9147 11:04:23.898891 Write leveling : PASS
9148 11:04:23.898971 RX DQS gating : PASS
9149 11:04:23.901574 RX DQ/DQS(RDDQC) : PASS
9150 11:04:23.905199 TX DQ/DQS : PASS
9151 11:04:23.905276 RX DATLAT : PASS
9152 11:04:23.908142 RX DQ/DQS(Engine): PASS
9153 11:04:23.908217 TX OE : PASS
9154 11:04:23.911913 All Pass.
9155 11:04:23.911990
9156 11:04:23.912048 DramC Write-DBI on
9157 11:04:23.914724 PER_BANK_REFRESH: Hybrid Mode
9158 11:04:23.918335 TX_TRACKING: ON
9159 11:04:23.924846 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9160 11:04:23.934807 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9161 11:04:23.941192 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9162 11:04:23.944635 [FAST_K] Save calibration result to emmc
9163 11:04:23.948248 sync common calibartion params.
9164 11:04:23.948330 sync cbt_mode0:1, 1:1
9165 11:04:23.951010 dram_init: ddr_geometry: 2
9166 11:04:23.954593 dram_init: ddr_geometry: 2
9167 11:04:23.958005 dram_init: ddr_geometry: 2
9168 11:04:23.958138 0:dram_rank_size:100000000
9169 11:04:23.961233 1:dram_rank_size:100000000
9170 11:04:23.968068 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9171 11:04:23.970853 DFS_SHUFFLE_HW_MODE: ON
9172 11:04:23.974333 dramc_set_vcore_voltage set vcore to 725000
9173 11:04:23.974415 Read voltage for 1600, 0
9174 11:04:23.977686 Vio18 = 0
9175 11:04:23.977779 Vcore = 725000
9176 11:04:23.977856 Vdram = 0
9177 11:04:23.980638 Vddq = 0
9178 11:04:23.980741 Vmddr = 0
9179 11:04:23.984220 switch to 3200 Mbps bootup
9180 11:04:23.984298 [DramcRunTimeConfig]
9181 11:04:23.984375 PHYPLL
9182 11:04:23.987742 DPM_CONTROL_AFTERK: ON
9183 11:04:23.990507 PER_BANK_REFRESH: ON
9184 11:04:23.990585 REFRESH_OVERHEAD_REDUCTION: ON
9185 11:04:23.994200 CMD_PICG_NEW_MODE: OFF
9186 11:04:23.997410 XRTWTW_NEW_MODE: ON
9187 11:04:23.997490 XRTRTR_NEW_MODE: ON
9188 11:04:24.000901 TX_TRACKING: ON
9189 11:04:24.000979 RDSEL_TRACKING: OFF
9190 11:04:24.003782 DQS Precalculation for DVFS: ON
9191 11:04:24.003861 RX_TRACKING: OFF
9192 11:04:24.007434 HW_GATING DBG: ON
9193 11:04:24.010733 ZQCS_ENABLE_LP4: ON
9194 11:04:24.010833 RX_PICG_NEW_MODE: ON
9195 11:04:24.014278 TX_PICG_NEW_MODE: ON
9196 11:04:24.014357 ENABLE_RX_DCM_DPHY: ON
9197 11:04:24.017578 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9198 11:04:24.020642 DUMMY_READ_FOR_TRACKING: OFF
9199 11:04:24.023984 !!! SPM_CONTROL_AFTERK: OFF
9200 11:04:24.027682 !!! SPM could not control APHY
9201 11:04:24.027770 IMPEDANCE_TRACKING: ON
9202 11:04:24.030664 TEMP_SENSOR: ON
9203 11:04:24.030739 HW_SAVE_FOR_SR: OFF
9204 11:04:24.034340 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9205 11:04:24.037113 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9206 11:04:24.040685 Read ODT Tracking: ON
9207 11:04:24.040762 Refresh Rate DeBounce: ON
9208 11:04:24.044120 DFS_NO_QUEUE_FLUSH: ON
9209 11:04:24.047751 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9210 11:04:24.050472 ENABLE_DFS_RUNTIME_MRW: OFF
9211 11:04:24.050548 DDR_RESERVE_NEW_MODE: ON
9212 11:04:24.054061 MR_CBT_SWITCH_FREQ: ON
9213 11:04:24.057125 =========================
9214 11:04:24.075434 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9215 11:04:24.078829 dram_init: ddr_geometry: 2
9216 11:04:24.097050 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9217 11:04:24.100544 dram_init: dram init end (result: 0)
9218 11:04:24.106696 DRAM-K: Full calibration passed in 24539 msecs
9219 11:04:24.109967 MRC: failed to locate region type 0.
9220 11:04:24.110045 DRAM rank0 size:0x100000000,
9221 11:04:24.113474 DRAM rank1 size=0x100000000
9222 11:04:24.123298 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9223 11:04:24.129971 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9224 11:04:24.136436 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9225 11:04:24.143095 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9226 11:04:24.146457 DRAM rank0 size:0x100000000,
9227 11:04:24.150265 DRAM rank1 size=0x100000000
9228 11:04:24.150342 CBMEM:
9229 11:04:24.153097 IMD: root @ 0xfffff000 254 entries.
9230 11:04:24.156333 IMD: root @ 0xffffec00 62 entries.
9231 11:04:24.159718 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9232 11:04:24.166421 WARNING: RO_VPD is uninitialized or empty.
9233 11:04:24.170020 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9234 11:04:24.177193 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9235 11:04:24.190059 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9236 11:04:24.200995 BS: romstage times (exec / console): total (unknown) / 24006 ms
9237 11:04:24.201095
9238 11:04:24.201155
9239 11:04:24.210968 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9240 11:04:24.214423 ARM64: Exception handlers installed.
9241 11:04:24.217984 ARM64: Testing exception
9242 11:04:24.221161 ARM64: Done test exception
9243 11:04:24.221239 Enumerating buses...
9244 11:04:24.224680 Show all devs... Before device enumeration.
9245 11:04:24.227706 Root Device: enabled 1
9246 11:04:24.231283 CPU_CLUSTER: 0: enabled 1
9247 11:04:24.231375 CPU: 00: enabled 1
9248 11:04:24.234667 Compare with tree...
9249 11:04:24.234776 Root Device: enabled 1
9250 11:04:24.237777 CPU_CLUSTER: 0: enabled 1
9251 11:04:24.240882 CPU: 00: enabled 1
9252 11:04:24.240958 Root Device scanning...
9253 11:04:24.244353 scan_static_bus for Root Device
9254 11:04:24.247601 CPU_CLUSTER: 0 enabled
9255 11:04:24.250780 scan_static_bus for Root Device done
9256 11:04:24.253986 scan_bus: bus Root Device finished in 8 msecs
9257 11:04:24.254086 done
9258 11:04:24.261002 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9259 11:04:24.264647 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9260 11:04:24.270662 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9261 11:04:24.274443 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9262 11:04:24.277681 Allocating resources...
9263 11:04:24.280984 Reading resources...
9264 11:04:24.284008 Root Device read_resources bus 0 link: 0
9265 11:04:24.284108 DRAM rank0 size:0x100000000,
9266 11:04:24.287858 DRAM rank1 size=0x100000000
9267 11:04:24.290579 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9268 11:04:24.293966 CPU: 00 missing read_resources
9269 11:04:24.297444 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9270 11:04:24.304165 Root Device read_resources bus 0 link: 0 done
9271 11:04:24.304241 Done reading resources.
9272 11:04:24.311139 Show resources in subtree (Root Device)...After reading.
9273 11:04:24.314012 Root Device child on link 0 CPU_CLUSTER: 0
9274 11:04:24.317430 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 11:04:24.327282 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 11:04:24.327366 CPU: 00
9277 11:04:24.330305 Root Device assign_resources, bus 0 link: 0
9278 11:04:24.334060 CPU_CLUSTER: 0 missing set_resources
9279 11:04:24.340508 Root Device assign_resources, bus 0 link: 0 done
9280 11:04:24.340584 Done setting resources.
9281 11:04:24.347159 Show resources in subtree (Root Device)...After assigning values.
9282 11:04:24.350429 Root Device child on link 0 CPU_CLUSTER: 0
9283 11:04:24.353910 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 11:04:24.363557 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 11:04:24.363633 CPU: 00
9286 11:04:24.366945 Done allocating resources.
9287 11:04:24.373539 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9288 11:04:24.373617 Enabling resources...
9289 11:04:24.373676 done.
9290 11:04:24.380093 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9291 11:04:24.380170 Initializing devices...
9292 11:04:24.383715 Root Device init
9293 11:04:24.383791 init hardware done!
9294 11:04:24.386446 0x00000018: ctrlr->caps
9295 11:04:24.389911 52.000 MHz: ctrlr->f_max
9296 11:04:24.389989 0.400 MHz: ctrlr->f_min
9297 11:04:24.393248 0x40ff8080: ctrlr->voltages
9298 11:04:24.396500 sclk: 390625
9299 11:04:24.396577 Bus Width = 1
9300 11:04:24.396635 sclk: 390625
9301 11:04:24.399765 Bus Width = 1
9302 11:04:24.399840 Early init status = 3
9303 11:04:24.406482 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9304 11:04:24.410262 in-header: 03 fc 00 00 01 00 00 00
9305 11:04:24.410362 in-data: 00
9306 11:04:24.416503 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9307 11:04:24.419873 in-header: 03 fd 00 00 00 00 00 00
9308 11:04:24.422846 in-data:
9309 11:04:24.426337 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9310 11:04:24.429793 in-header: 03 fc 00 00 01 00 00 00
9311 11:04:24.433462 in-data: 00
9312 11:04:24.436693 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9313 11:04:24.441311 in-header: 03 fd 00 00 00 00 00 00
9314 11:04:24.444319 in-data:
9315 11:04:24.448002 [SSUSB] Setting up USB HOST controller...
9316 11:04:24.451044 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9317 11:04:24.454661 [SSUSB] phy power-on done.
9318 11:04:24.457672 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9319 11:04:24.464373 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9320 11:04:24.467662 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9321 11:04:24.474296 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9322 11:04:24.481049 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9323 11:04:24.487594 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9324 11:04:24.494574 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9325 11:04:24.501215 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9326 11:04:24.504158 SPM: binary array size = 0x9dc
9327 11:04:24.507328 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9328 11:04:24.514216 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9329 11:04:24.520886 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9330 11:04:24.524051 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9331 11:04:24.530509 configure_display: Starting display init
9332 11:04:24.564853 anx7625_power_on_init: Init interface.
9333 11:04:24.567675 anx7625_disable_pd_protocol: Disabled PD feature.
9334 11:04:24.571236 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9335 11:04:24.598832 anx7625_start_dp_work: Secure OCM version=00
9336 11:04:24.602120 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9337 11:04:24.616972 sp_tx_get_edid_block: EDID Block = 1
9338 11:04:24.719397 Extracted contents:
9339 11:04:24.722730 header: 00 ff ff ff ff ff ff 00
9340 11:04:24.726170 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9341 11:04:24.729593 version: 01 04
9342 11:04:24.732510 basic params: 95 1f 11 78 0a
9343 11:04:24.736017 chroma info: 76 90 94 55 54 90 27 21 50 54
9344 11:04:24.739458 established: 00 00 00
9345 11:04:24.745916 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9346 11:04:24.749047 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9347 11:04:24.755700 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 11:04:24.762499 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9349 11:04:24.769154 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9350 11:04:24.772240 extensions: 00
9351 11:04:24.772317 checksum: fb
9352 11:04:24.772375
9353 11:04:24.775859 Manufacturer: IVO Model 57d Serial Number 0
9354 11:04:24.778809 Made week 0 of 2020
9355 11:04:24.782565 EDID version: 1.4
9356 11:04:24.782640 Digital display
9357 11:04:24.785605 6 bits per primary color channel
9358 11:04:24.785682 DisplayPort interface
9359 11:04:24.788908 Maximum image size: 31 cm x 17 cm
9360 11:04:24.792064 Gamma: 220%
9361 11:04:24.792139 Check DPMS levels
9362 11:04:24.795349 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9363 11:04:24.802341 First detailed timing is preferred timing
9364 11:04:24.802418 Established timings supported:
9365 11:04:24.805462 Standard timings supported:
9366 11:04:24.809086 Detailed timings
9367 11:04:24.812096 Hex of detail: 383680a07038204018303c0035ae10000019
9368 11:04:24.815270 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9369 11:04:24.822056 0780 0798 07c8 0820 hborder 0
9370 11:04:24.825755 0438 043b 0447 0458 vborder 0
9371 11:04:24.828599 -hsync -vsync
9372 11:04:24.828676 Did detailed timing
9373 11:04:24.835529 Hex of detail: 000000000000000000000000000000000000
9374 11:04:24.838684 Manufacturer-specified data, tag 0
9375 11:04:24.842192 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9376 11:04:24.845200 ASCII string: InfoVision
9377 11:04:24.848770 Hex of detail: 000000fe00523134304e574635205248200a
9378 11:04:24.851618 ASCII string: R140NWF5 RH
9379 11:04:24.851692 Checksum
9380 11:04:24.855167 Checksum: 0xfb (valid)
9381 11:04:24.858299 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9382 11:04:24.861399 DSI data_rate: 832800000 bps
9383 11:04:24.868289 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9384 11:04:24.871576 anx7625_parse_edid: pixelclock(138800).
9385 11:04:24.875069 hactive(1920), hsync(48), hfp(24), hbp(88)
9386 11:04:24.878254 vactive(1080), vsync(12), vfp(3), vbp(17)
9387 11:04:24.881631 anx7625_dsi_config: config dsi.
9388 11:04:24.888404 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9389 11:04:24.901991 anx7625_dsi_config: success to config DSI
9390 11:04:24.905132 anx7625_dp_start: MIPI phy setup OK.
9391 11:04:24.908126 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9392 11:04:24.911647 mtk_ddp_mode_set invalid vrefresh 60
9393 11:04:24.914700 main_disp_path_setup
9394 11:04:24.914775 ovl_layer_smi_id_en
9395 11:04:24.918293 ovl_layer_smi_id_en
9396 11:04:24.918368 ccorr_config
9397 11:04:24.918426 aal_config
9398 11:04:24.921426 gamma_config
9399 11:04:24.921500 postmask_config
9400 11:04:24.924668 dither_config
9401 11:04:24.928129 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9402 11:04:24.934869 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9403 11:04:24.938264 Root Device init finished in 551 msecs
9404 11:04:24.938340 CPU_CLUSTER: 0 init
9405 11:04:24.947733 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9406 11:04:24.951317 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9407 11:04:24.954837 APU_MBOX 0x190000b0 = 0x10001
9408 11:04:24.957826 APU_MBOX 0x190001b0 = 0x10001
9409 11:04:24.961101 APU_MBOX 0x190005b0 = 0x10001
9410 11:04:24.964820 APU_MBOX 0x190006b0 = 0x10001
9411 11:04:24.967667 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9412 11:04:24.980424 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9413 11:04:24.992969 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9414 11:04:24.999954 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9415 11:04:25.011097 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9416 11:04:25.020309 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9417 11:04:25.023975 CPU_CLUSTER: 0 init finished in 81 msecs
9418 11:04:25.026786 Devices initialized
9419 11:04:25.030042 Show all devs... After init.
9420 11:04:25.030128 Root Device: enabled 1
9421 11:04:25.033306 CPU_CLUSTER: 0: enabled 1
9422 11:04:25.036948 CPU: 00: enabled 1
9423 11:04:25.040273 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9424 11:04:25.043218 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9425 11:04:25.046673 ELOG: NV offset 0x57f000 size 0x1000
9426 11:04:25.053623 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9427 11:04:25.060207 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9428 11:04:25.063698 ELOG: Event(17) added with size 13 at 2024-07-10 11:04:25 UTC
9429 11:04:25.066681 out: cmd=0x121: 03 db 21 01 00 00 00 00
9430 11:04:25.070449 in-header: 03 d1 00 00 2c 00 00 00
9431 11:04:25.083789 in-data: 6c 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9432 11:04:25.090252 ELOG: Event(A1) added with size 10 at 2024-07-10 11:04:25 UTC
9433 11:04:25.097203 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9434 11:04:25.103814 ELOG: Event(A0) added with size 9 at 2024-07-10 11:04:25 UTC
9435 11:04:25.106927 elog_add_boot_reason: Logged dev mode boot
9436 11:04:25.110307 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9437 11:04:25.113231 Finalize devices...
9438 11:04:25.113309 Devices finalized
9439 11:04:25.120247 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9440 11:04:25.123517 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9441 11:04:25.127036 in-header: 03 07 00 00 08 00 00 00
9442 11:04:25.129846 in-data: aa e4 47 04 13 02 00 00
9443 11:04:25.133284 Chrome EC: UHEPI supported
9444 11:04:25.139879 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9445 11:04:25.143291 in-header: 03 a9 00 00 08 00 00 00
9446 11:04:25.146516 in-data: 84 60 60 08 00 00 00 00
9447 11:04:25.149619 ELOG: Event(91) added with size 10 at 2024-07-10 11:04:25 UTC
9448 11:04:25.156642 Chrome EC: clear events_b mask to 0x0000000020004000
9449 11:04:25.163119 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9450 11:04:25.166311 in-header: 03 fd 00 00 00 00 00 00
9451 11:04:25.166387 in-data:
9452 11:04:25.173056 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9453 11:04:25.176388 Writing coreboot table at 0xffe64000
9454 11:04:25.179565 0. 000000000010a000-0000000000113fff: RAMSTAGE
9455 11:04:25.182824 1. 0000000040000000-00000000400fffff: RAM
9456 11:04:25.189452 2. 0000000040100000-000000004032afff: RAMSTAGE
9457 11:04:25.192793 3. 000000004032b000-00000000545fffff: RAM
9458 11:04:25.196231 4. 0000000054600000-000000005465ffff: BL31
9459 11:04:25.200043 5. 0000000054660000-00000000ffe63fff: RAM
9460 11:04:25.206318 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9461 11:04:25.209760 7. 0000000100000000-000000023fffffff: RAM
9462 11:04:25.209862 Passing 5 GPIOs to payload:
9463 11:04:25.216415 NAME | PORT | POLARITY | VALUE
9464 11:04:25.219561 EC in RW | 0x000000aa | low | undefined
9465 11:04:25.226022 EC interrupt | 0x00000005 | low | undefined
9466 11:04:25.229331 TPM interrupt | 0x000000ab | high | undefined
9467 11:04:25.236196 SD card detect | 0x00000011 | high | undefined
9468 11:04:25.239205 speaker enable | 0x00000093 | high | undefined
9469 11:04:25.242862 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9470 11:04:25.245564 in-header: 03 f9 00 00 02 00 00 00
9471 11:04:25.249259 in-data: 02 00
9472 11:04:25.249336 ADC[4]: Raw value=895930 ID=7
9473 11:04:25.252481 ADC[3]: Raw value=212700 ID=1
9474 11:04:25.256225 RAM Code: 0x71
9475 11:04:25.256301 ADC[6]: Raw value=74722 ID=0
9476 11:04:25.259345 ADC[5]: Raw value=212330 ID=1
9477 11:04:25.262177 SKU Code: 0x1
9478 11:04:25.265470 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2658
9479 11:04:25.269065 coreboot table: 964 bytes.
9480 11:04:25.272323 IMD ROOT 0. 0xfffff000 0x00001000
9481 11:04:25.275650 IMD SMALL 1. 0xffffe000 0x00001000
9482 11:04:25.278895 RO MCACHE 2. 0xffffc000 0x00001104
9483 11:04:25.282220 CONSOLE 3. 0xfff7c000 0x00080000
9484 11:04:25.285888 FMAP 4. 0xfff7b000 0x00000452
9485 11:04:25.288612 TIME STAMP 5. 0xfff7a000 0x00000910
9486 11:04:25.292165 VBOOT WORK 6. 0xfff66000 0x00014000
9487 11:04:25.295304 RAMOOPS 7. 0xffe66000 0x00100000
9488 11:04:25.298770 COREBOOT 8. 0xffe64000 0x00002000
9489 11:04:25.298846 IMD small region:
9490 11:04:25.302030 IMD ROOT 0. 0xffffec00 0x00000400
9491 11:04:25.308755 VPD 1. 0xffffeb80 0x0000006c
9492 11:04:25.312100 MMC STATUS 2. 0xffffeb60 0x00000004
9493 11:04:25.315078 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9494 11:04:25.321779 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9495 11:04:25.361883 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9496 11:04:25.365261 Checking segment from ROM address 0x40100000
9497 11:04:25.368476 Checking segment from ROM address 0x4010001c
9498 11:04:25.375624 Loading segment from ROM address 0x40100000
9499 11:04:25.375712 code (compression=0)
9500 11:04:25.385229 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9501 11:04:25.392294 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9502 11:04:25.392379 it's not compressed!
9503 11:04:25.399141 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9504 11:04:25.401844 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9505 11:04:25.422499 Loading segment from ROM address 0x4010001c
9506 11:04:25.422608 Entry Point 0x80000000
9507 11:04:25.425819 Loaded segments
9508 11:04:25.429058 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9509 11:04:25.436119 Jumping to boot code at 0x80000000(0xffe64000)
9510 11:04:25.442731 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9511 11:04:25.448679 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9512 11:04:25.457014 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9513 11:04:25.460575 Checking segment from ROM address 0x40100000
9514 11:04:25.463592 Checking segment from ROM address 0x4010001c
9515 11:04:25.469974 Loading segment from ROM address 0x40100000
9516 11:04:25.470082 code (compression=1)
9517 11:04:25.476798 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9518 11:04:25.487005 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9519 11:04:25.487095 using LZMA
9520 11:04:25.495214 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9521 11:04:25.502065 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9522 11:04:25.505012 Loading segment from ROM address 0x4010001c
9523 11:04:25.505087 Entry Point 0x54601000
9524 11:04:25.508860 Loaded segments
9525 11:04:25.511575 NOTICE: MT8192 bl31_setup
9526 11:04:25.518912 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9527 11:04:25.522678 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9528 11:04:25.525457 WARNING: region 0:
9529 11:04:25.528768 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 11:04:25.528861 WARNING: region 1:
9531 11:04:25.535220 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9532 11:04:25.538600 WARNING: region 2:
9533 11:04:25.542125 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9534 11:04:25.545279 WARNING: region 3:
9535 11:04:25.548616 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9536 11:04:25.552195 WARNING: region 4:
9537 11:04:25.558635 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 11:04:25.558712 WARNING: region 5:
9539 11:04:25.562538 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 11:04:25.565454 WARNING: region 6:
9541 11:04:25.568561 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 11:04:25.571751 WARNING: region 7:
9543 11:04:25.575761 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 11:04:25.582006 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9545 11:04:25.585003 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9546 11:04:25.588582 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9547 11:04:25.595342 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9548 11:04:25.598213 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9549 11:04:25.604974 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9550 11:04:25.608230 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9551 11:04:25.611770 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9552 11:04:25.618370 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9553 11:04:25.621675 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9554 11:04:25.625382 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9555 11:04:25.631946 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9556 11:04:25.635204 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9557 11:04:25.641424 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9558 11:04:25.644999 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9559 11:04:25.648406 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9560 11:04:25.654893 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9561 11:04:25.658372 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9562 11:04:25.664846 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9563 11:04:25.668063 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9564 11:04:25.671462 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9565 11:04:25.678278 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9566 11:04:25.681365 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9567 11:04:25.684753 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9568 11:04:25.691128 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9569 11:04:25.694897 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9570 11:04:25.701158 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9571 11:04:25.704651 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9572 11:04:25.710794 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9573 11:04:25.714318 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9574 11:04:25.717859 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9575 11:04:25.724476 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9576 11:04:25.727969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9577 11:04:25.730813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9578 11:04:25.734179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9579 11:04:25.740773 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9580 11:04:25.744109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9581 11:04:25.747975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9582 11:04:25.751053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9583 11:04:25.757369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9584 11:04:25.760906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9585 11:04:25.763843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9586 11:04:25.767611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9587 11:04:25.773912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9588 11:04:25.777206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9589 11:04:25.780358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9590 11:04:25.787353 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9591 11:04:25.790288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9592 11:04:25.793678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9593 11:04:25.800292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9594 11:04:25.803833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9595 11:04:25.810907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9596 11:04:25.813905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9597 11:04:25.816807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9598 11:04:25.823763 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9599 11:04:25.827055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9600 11:04:25.833591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9601 11:04:25.837027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9602 11:04:25.843594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9603 11:04:25.847096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9604 11:04:25.850464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9605 11:04:25.856791 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9606 11:04:25.860175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9607 11:04:25.866728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9608 11:04:25.870219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9609 11:04:25.876846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9610 11:04:25.880583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9611 11:04:25.886676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9612 11:04:25.890008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9613 11:04:25.893361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9614 11:04:25.899814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9615 11:04:25.903059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9616 11:04:25.910046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9617 11:04:25.913265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9618 11:04:25.919665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9619 11:04:25.922915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9620 11:04:25.929705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9621 11:04:25.933006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9622 11:04:25.936542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9623 11:04:25.943051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9624 11:04:25.946309 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9625 11:04:25.952868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9626 11:04:25.956265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9627 11:04:25.962784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9628 11:04:25.966056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9629 11:04:25.973294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9630 11:04:25.976034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9631 11:04:25.979655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9632 11:04:25.986250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9633 11:04:25.990168 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9634 11:04:25.996145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9635 11:04:25.999298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9636 11:04:26.005885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9637 11:04:26.009810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9638 11:04:26.012631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9639 11:04:26.019373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9640 11:04:26.022731 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9641 11:04:26.026060 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9642 11:04:26.033064 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9643 11:04:26.036165 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9644 11:04:26.038884 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9645 11:04:26.046116 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9646 11:04:26.048933 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9647 11:04:26.052186 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9648 11:04:26.059082 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9649 11:04:26.062640 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9650 11:04:26.068851 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9651 11:04:26.072209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9652 11:04:26.078895 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9653 11:04:26.082027 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9654 11:04:26.085658 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9655 11:04:26.092277 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9656 11:04:26.095223 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9657 11:04:26.102037 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9658 11:04:26.105279 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9659 11:04:26.108627 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9660 11:04:26.111692 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9661 11:04:26.118477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9662 11:04:26.121538 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9663 11:04:26.124833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9664 11:04:26.132046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9665 11:04:26.135439 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9666 11:04:26.138062 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9667 11:04:26.141387 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9668 11:04:26.148195 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9669 11:04:26.151336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9670 11:04:26.158026 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9671 11:04:26.161260 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9672 11:04:26.167955 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9673 11:04:26.171742 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9674 11:04:26.174888 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9675 11:04:26.181315 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9676 11:04:26.184706 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9677 11:04:26.188332 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9678 11:04:26.194812 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9679 11:04:26.197779 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9680 11:04:26.204451 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9681 11:04:26.207664 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9682 11:04:26.211187 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9683 11:04:26.217846 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9684 11:04:26.221594 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9685 11:04:26.227798 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9686 11:04:26.230864 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9687 11:04:26.234560 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9688 11:04:26.241189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9689 11:04:26.244615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9690 11:04:26.251191 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9691 11:04:26.254254 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9692 11:04:26.257536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9693 11:04:26.264235 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9694 11:04:26.267706 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9695 11:04:26.270688 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9696 11:04:26.277362 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9697 11:04:26.281091 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9698 11:04:26.287533 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9699 11:04:26.290844 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9700 11:04:26.294574 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9701 11:04:26.300418 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9702 11:04:26.303907 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9703 11:04:26.310831 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9704 11:04:26.314448 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9705 11:04:26.317281 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9706 11:04:26.324003 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9707 11:04:26.327476 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9708 11:04:26.333718 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9709 11:04:26.337105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9710 11:04:26.340371 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9711 11:04:26.347421 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9712 11:04:26.350316 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9713 11:04:26.356929 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9714 11:04:26.360600 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9715 11:04:26.364117 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9716 11:04:26.370692 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9717 11:04:26.373326 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9718 11:04:26.380014 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9719 11:04:26.383240 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9720 11:04:26.387120 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9721 11:04:26.393162 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9722 11:04:26.396857 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9723 11:04:26.400030 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9724 11:04:26.407120 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9725 11:04:26.410023 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9726 11:04:26.417053 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9727 11:04:26.420262 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9728 11:04:26.423054 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9729 11:04:26.430128 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9730 11:04:26.433147 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9731 11:04:26.440199 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9732 11:04:26.443368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9733 11:04:26.450037 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9734 11:04:26.453280 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9735 11:04:26.456600 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9736 11:04:26.463046 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9737 11:04:26.466064 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9738 11:04:26.472725 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9739 11:04:26.476345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9740 11:04:26.480067 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9741 11:04:26.486301 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9742 11:04:26.489476 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9743 11:04:26.496069 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9744 11:04:26.499857 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9745 11:04:26.506231 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9746 11:04:26.509460 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9747 11:04:26.512627 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9748 11:04:26.519867 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9749 11:04:26.523138 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9750 11:04:26.529437 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9751 11:04:26.532775 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9752 11:04:26.536190 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9753 11:04:26.542587 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9754 11:04:26.545644 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9755 11:04:26.552557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9756 11:04:26.555825 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9757 11:04:26.562438 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9758 11:04:26.566388 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9759 11:04:26.569016 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9760 11:04:26.575680 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9761 11:04:26.579270 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9762 11:04:26.585633 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9763 11:04:26.588918 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9764 11:04:26.592165 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9765 11:04:26.599124 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9766 11:04:26.601992 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9767 11:04:26.609103 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9768 11:04:26.612007 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9769 11:04:26.618593 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9770 11:04:26.622036 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9771 11:04:26.625463 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9772 11:04:26.631853 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9773 11:04:26.635699 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9774 11:04:26.639052 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9775 11:04:26.642499 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9776 11:04:26.649084 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9777 11:04:26.651987 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9778 11:04:26.655098 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9779 11:04:26.661950 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9780 11:04:26.665251 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9781 11:04:26.672145 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9782 11:04:26.675207 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9783 11:04:26.678559 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9784 11:04:26.685038 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9785 11:04:26.688123 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9786 11:04:26.691928 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9787 11:04:26.698228 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9788 11:04:26.701444 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9789 11:04:26.704767 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9790 11:04:26.711291 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9791 11:04:26.714966 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9792 11:04:26.718305 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9793 11:04:26.725033 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9794 11:04:26.727937 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9795 11:04:26.734884 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9796 11:04:26.738066 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9797 11:04:26.741831 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9798 11:04:26.747842 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9799 11:04:26.751331 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9800 11:04:26.757898 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9801 11:04:26.760938 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9802 11:04:26.764246 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9803 11:04:26.771331 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9804 11:04:26.774215 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9805 11:04:26.777962 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9806 11:04:26.784208 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9807 11:04:26.787573 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9808 11:04:26.790885 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9809 11:04:26.797544 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9810 11:04:26.800963 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9811 11:04:26.807276 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9812 11:04:26.810962 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9813 11:04:26.814216 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9814 11:04:26.817512 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9815 11:04:26.823931 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9816 11:04:26.827562 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9817 11:04:26.830471 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9818 11:04:26.833820 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9819 11:04:26.837235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9820 11:04:26.844303 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9821 11:04:26.847245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9822 11:04:26.850694 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9823 11:04:26.854545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9824 11:04:26.860780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9825 11:04:26.864156 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9826 11:04:26.867440 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9827 11:04:26.873958 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9828 11:04:26.877787 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9829 11:04:26.884195 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9830 11:04:26.887514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9831 11:04:26.894392 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9832 11:04:26.897310 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9833 11:04:26.900459 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9834 11:04:26.907097 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9835 11:04:26.910515 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9836 11:04:26.916824 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9837 11:04:26.920757 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9838 11:04:26.923436 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9839 11:04:26.929976 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9840 11:04:26.933692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9841 11:04:26.940246 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9842 11:04:26.943263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9843 11:04:26.947192 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9844 11:04:26.953463 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9845 11:04:26.956621 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9846 11:04:26.963173 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9847 11:04:26.966577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9848 11:04:26.973252 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9849 11:04:26.976395 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9850 11:04:26.979772 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9851 11:04:26.986738 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9852 11:04:26.990084 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9853 11:04:26.996157 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9854 11:04:26.999684 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9855 11:04:27.006681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9856 11:04:27.009583 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9857 11:04:27.013145 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9858 11:04:27.019250 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9859 11:04:27.022700 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9860 11:04:27.029564 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9861 11:04:27.032730 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9862 11:04:27.036130 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9863 11:04:27.042455 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9864 11:04:27.045773 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9865 11:04:27.052485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9866 11:04:27.055611 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9867 11:04:27.059340 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9868 11:04:27.065783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9869 11:04:27.068959 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9870 11:04:27.075742 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9871 11:04:27.079102 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9872 11:04:27.085616 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9873 11:04:27.088856 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9874 11:04:27.091965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9875 11:04:27.098607 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9876 11:04:27.102464 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9877 11:04:27.108724 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9878 11:04:27.112457 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9879 11:04:27.115487 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9880 11:04:27.121942 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9881 11:04:27.125321 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9882 11:04:27.131933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9883 11:04:27.134932 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9884 11:04:27.138483 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9885 11:04:27.145458 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9886 11:04:27.148758 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9887 11:04:27.154938 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9888 11:04:27.158627 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9889 11:04:27.161602 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9890 11:04:27.168461 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9891 11:04:27.172008 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9892 11:04:27.178252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9893 11:04:27.181972 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9894 11:04:27.188106 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9895 11:04:27.191627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9896 11:04:27.194760 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9897 11:04:27.201466 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9898 11:04:27.204690 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9899 11:04:27.211351 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9900 11:04:27.215016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9901 11:04:27.221516 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9902 11:04:27.224449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9903 11:04:27.230980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9904 11:04:27.234441 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9905 11:04:27.238268 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9906 11:04:27.244532 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9907 11:04:27.247560 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9908 11:04:27.254359 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9909 11:04:27.257434 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9910 11:04:27.264226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9911 11:04:27.267460 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9912 11:04:27.270811 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9913 11:04:27.277347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9914 11:04:27.280880 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9915 11:04:27.287571 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9916 11:04:27.290561 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9917 11:04:27.297415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9918 11:04:27.300868 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9919 11:04:27.307373 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9920 11:04:27.310744 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9921 11:04:27.314117 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9922 11:04:27.320924 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9923 11:04:27.323927 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9924 11:04:27.330517 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9925 11:04:27.333962 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9926 11:04:27.340332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9927 11:04:27.343953 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9928 11:04:27.346947 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9929 11:04:27.354025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9930 11:04:27.356814 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9931 11:04:27.363898 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9932 11:04:27.367106 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9933 11:04:27.373308 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9934 11:04:27.376684 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9935 11:04:27.383580 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9936 11:04:27.387005 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9937 11:04:27.390061 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9938 11:04:27.396519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9939 11:04:27.399813 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9940 11:04:27.406414 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9941 11:04:27.409744 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9942 11:04:27.416546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9943 11:04:27.420028 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9944 11:04:27.423145 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9945 11:04:27.430307 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9946 11:04:27.433345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9947 11:04:27.440167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9948 11:04:27.442991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9949 11:04:27.449521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9950 11:04:27.453101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9951 11:04:27.459635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9952 11:04:27.462543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9953 11:04:27.465964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9954 11:04:27.472662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9955 11:04:27.476111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9956 11:04:27.482787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9957 11:04:27.485824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9958 11:04:27.492547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9959 11:04:27.495875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9960 11:04:27.502426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9961 11:04:27.506277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9962 11:04:27.512314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9963 11:04:27.515617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9964 11:04:27.522368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9965 11:04:27.525618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9966 11:04:27.532448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9967 11:04:27.535602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9968 11:04:27.542364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9969 11:04:27.546077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9970 11:04:27.552662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9971 11:04:27.555797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9972 11:04:27.562348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9973 11:04:27.565219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9974 11:04:27.572260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9975 11:04:27.575733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9976 11:04:27.582209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9977 11:04:27.585678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9978 11:04:27.592277 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9979 11:04:27.592353 INFO: [APUAPC] vio 0
9980 11:04:27.599136 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9981 11:04:27.602338 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9982 11:04:27.605481 INFO: [APUAPC] D0_APC_0: 0x400510
9983 11:04:27.608830 INFO: [APUAPC] D0_APC_1: 0x0
9984 11:04:27.612343 INFO: [APUAPC] D0_APC_2: 0x1540
9985 11:04:27.615518 INFO: [APUAPC] D0_APC_3: 0x0
9986 11:04:27.619088 INFO: [APUAPC] D1_APC_0: 0xffffffff
9987 11:04:27.622681 INFO: [APUAPC] D1_APC_1: 0xffffffff
9988 11:04:27.625602 INFO: [APUAPC] D1_APC_2: 0x3fffff
9989 11:04:27.628832 INFO: [APUAPC] D1_APC_3: 0x0
9990 11:04:27.631842 INFO: [APUAPC] D2_APC_0: 0xffffffff
9991 11:04:27.635619 INFO: [APUAPC] D2_APC_1: 0xffffffff
9992 11:04:27.638609 INFO: [APUAPC] D2_APC_2: 0x3fffff
9993 11:04:27.642242 INFO: [APUAPC] D2_APC_3: 0x0
9994 11:04:27.645457 INFO: [APUAPC] D3_APC_0: 0xffffffff
9995 11:04:27.648583 INFO: [APUAPC] D3_APC_1: 0xffffffff
9996 11:04:27.652063 INFO: [APUAPC] D3_APC_2: 0x3fffff
9997 11:04:27.655477 INFO: [APUAPC] D3_APC_3: 0x0
9998 11:04:27.658537 INFO: [APUAPC] D4_APC_0: 0xffffffff
9999 11:04:27.662237 INFO: [APUAPC] D4_APC_1: 0xffffffff
10000 11:04:27.665339 INFO: [APUAPC] D4_APC_2: 0x3fffff
10001 11:04:27.665693 INFO: [APUAPC] D4_APC_3: 0x0
10002 11:04:27.671946 INFO: [APUAPC] D5_APC_0: 0xffffffff
10003 11:04:27.675375 INFO: [APUAPC] D5_APC_1: 0xffffffff
10004 11:04:27.679224 INFO: [APUAPC] D5_APC_2: 0x3fffff
10005 11:04:27.679768 INFO: [APUAPC] D5_APC_3: 0x0
10006 11:04:27.681859 INFO: [APUAPC] D6_APC_0: 0xffffffff
10007 11:04:27.685474 INFO: [APUAPC] D6_APC_1: 0xffffffff
10008 11:04:27.688911 INFO: [APUAPC] D6_APC_2: 0x3fffff
10009 11:04:27.691976 INFO: [APUAPC] D6_APC_3: 0x0
10010 11:04:27.695027 INFO: [APUAPC] D7_APC_0: 0xffffffff
10011 11:04:27.698581 INFO: [APUAPC] D7_APC_1: 0xffffffff
10012 11:04:27.701670 INFO: [APUAPC] D7_APC_2: 0x3fffff
10013 11:04:27.705063 INFO: [APUAPC] D7_APC_3: 0x0
10014 11:04:27.708877 INFO: [APUAPC] D8_APC_0: 0xffffffff
10015 11:04:27.711628 INFO: [APUAPC] D8_APC_1: 0xffffffff
10016 11:04:27.714666 INFO: [APUAPC] D8_APC_2: 0x3fffff
10017 11:04:27.718041 INFO: [APUAPC] D8_APC_3: 0x0
10018 11:04:27.721467 INFO: [APUAPC] D9_APC_0: 0xffffffff
10019 11:04:27.724819 INFO: [APUAPC] D9_APC_1: 0xffffffff
10020 11:04:27.728144 INFO: [APUAPC] D9_APC_2: 0x3fffff
10021 11:04:27.731574 INFO: [APUAPC] D9_APC_3: 0x0
10022 11:04:27.734502 INFO: [APUAPC] D10_APC_0: 0xffffffff
10023 11:04:27.738418 INFO: [APUAPC] D10_APC_1: 0xffffffff
10024 11:04:27.741363 INFO: [APUAPC] D10_APC_2: 0x3fffff
10025 11:04:27.744491 INFO: [APUAPC] D10_APC_3: 0x0
10026 11:04:27.748032 INFO: [APUAPC] D11_APC_0: 0xffffffff
10027 11:04:27.751143 INFO: [APUAPC] D11_APC_1: 0xffffffff
10028 11:04:27.754601 INFO: [APUAPC] D11_APC_2: 0x3fffff
10029 11:04:27.757885 INFO: [APUAPC] D11_APC_3: 0x0
10030 11:04:27.760882 INFO: [APUAPC] D12_APC_0: 0xffffffff
10031 11:04:27.764321 INFO: [APUAPC] D12_APC_1: 0xffffffff
10032 11:04:27.767634 INFO: [APUAPC] D12_APC_2: 0x3fffff
10033 11:04:27.770773 INFO: [APUAPC] D12_APC_3: 0x0
10034 11:04:27.774511 INFO: [APUAPC] D13_APC_0: 0xffffffff
10035 11:04:27.777436 INFO: [APUAPC] D13_APC_1: 0xffffffff
10036 11:04:27.781071 INFO: [APUAPC] D13_APC_2: 0x3fffff
10037 11:04:27.784641 INFO: [APUAPC] D13_APC_3: 0x0
10038 11:04:27.787986 INFO: [APUAPC] D14_APC_0: 0xffffffff
10039 11:04:27.790687 INFO: [APUAPC] D14_APC_1: 0xffffffff
10040 11:04:27.794805 INFO: [APUAPC] D14_APC_2: 0x3fffff
10041 11:04:27.797828 INFO: [APUAPC] D14_APC_3: 0x0
10042 11:04:27.800888 INFO: [APUAPC] D15_APC_0: 0xffffffff
10043 11:04:27.804763 INFO: [APUAPC] D15_APC_1: 0xffffffff
10044 11:04:27.807750 INFO: [APUAPC] D15_APC_2: 0x3fffff
10045 11:04:27.811577 INFO: [APUAPC] D15_APC_3: 0x0
10046 11:04:27.814306 INFO: [APUAPC] APC_CON: 0x4
10047 11:04:27.817753 INFO: [NOCDAPC] D0_APC_0: 0x0
10048 11:04:27.821282 INFO: [NOCDAPC] D0_APC_1: 0x0
10049 11:04:27.824328 INFO: [NOCDAPC] D1_APC_0: 0x0
10050 11:04:27.827938 INFO: [NOCDAPC] D1_APC_1: 0xfff
10051 11:04:27.831077 INFO: [NOCDAPC] D2_APC_0: 0x0
10052 11:04:27.834521 INFO: [NOCDAPC] D2_APC_1: 0xfff
10053 11:04:27.834879 INFO: [NOCDAPC] D3_APC_0: 0x0
10054 11:04:27.837988 INFO: [NOCDAPC] D3_APC_1: 0xfff
10055 11:04:27.841001 INFO: [NOCDAPC] D4_APC_0: 0x0
10056 11:04:27.844574 INFO: [NOCDAPC] D4_APC_1: 0xfff
10057 11:04:27.847659 INFO: [NOCDAPC] D5_APC_0: 0x0
10058 11:04:27.851304 INFO: [NOCDAPC] D5_APC_1: 0xfff
10059 11:04:27.854224 INFO: [NOCDAPC] D6_APC_0: 0x0
10060 11:04:27.857431 INFO: [NOCDAPC] D6_APC_1: 0xfff
10061 11:04:27.860981 INFO: [NOCDAPC] D7_APC_0: 0x0
10062 11:04:27.864056 INFO: [NOCDAPC] D7_APC_1: 0xfff
10063 11:04:27.867612 INFO: [NOCDAPC] D8_APC_0: 0x0
10064 11:04:27.867971 INFO: [NOCDAPC] D8_APC_1: 0xfff
10065 11:04:27.870662 INFO: [NOCDAPC] D9_APC_0: 0x0
10066 11:04:27.874253 INFO: [NOCDAPC] D9_APC_1: 0xfff
10067 11:04:27.877438 INFO: [NOCDAPC] D10_APC_0: 0x0
10068 11:04:27.881019 INFO: [NOCDAPC] D10_APC_1: 0xfff
10069 11:04:27.884031 INFO: [NOCDAPC] D11_APC_0: 0x0
10070 11:04:27.887578 INFO: [NOCDAPC] D11_APC_1: 0xfff
10071 11:04:27.890910 INFO: [NOCDAPC] D12_APC_0: 0x0
10072 11:04:27.894025 INFO: [NOCDAPC] D12_APC_1: 0xfff
10073 11:04:27.897247 INFO: [NOCDAPC] D13_APC_0: 0x0
10074 11:04:27.900828 INFO: [NOCDAPC] D13_APC_1: 0xfff
10075 11:04:27.903938 INFO: [NOCDAPC] D14_APC_0: 0x0
10076 11:04:27.907505 INFO: [NOCDAPC] D14_APC_1: 0xfff
10077 11:04:27.910512 INFO: [NOCDAPC] D15_APC_0: 0x0
10078 11:04:27.913646 INFO: [NOCDAPC] D15_APC_1: 0xfff
10079 11:04:27.914003 INFO: [NOCDAPC] APC_CON: 0x4
10080 11:04:27.917287 INFO: [APUAPC] set_apusys_apc done
10081 11:04:27.920277 INFO: [DEVAPC] devapc_init done
10082 11:04:27.927423 INFO: GICv3 without legacy support detected.
10083 11:04:27.930412 INFO: ARM GICv3 driver initialized in EL3
10084 11:04:27.933830 INFO: Maximum SPI INTID supported: 639
10085 11:04:27.936924 INFO: BL31: Initializing runtime services
10086 11:04:27.943847 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10087 11:04:27.946997 INFO: SPM: enable CPC mode
10088 11:04:27.950170 INFO: mcdi ready for mcusys-off-idle and system suspend
10089 11:04:27.956686 INFO: BL31: Preparing for EL3 exit to normal world
10090 11:04:27.960260 INFO: Entry point address = 0x80000000
10091 11:04:27.960608 INFO: SPSR = 0x8
10092 11:04:27.967557
10093 11:04:27.967905
10094 11:04:27.968172
10095 11:04:27.970681 Starting depthcharge on Spherion...
10096 11:04:27.971030
10097 11:04:27.971301 Wipe memory regions:
10098 11:04:27.971549
10099 11:04:27.973655 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10100 11:04:27.974061 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10101 11:04:27.974425 Setting prompt string to ['asurada:']
10102 11:04:27.974711 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10103 11:04:27.975249 [0x00000040000000, 0x00000054600000)
10104 11:04:28.096126
10105 11:04:28.096516 [0x00000054660000, 0x00000080000000)
10106 11:04:28.357192
10107 11:04:28.357623 [0x000000821a7280, 0x000000ffe64000)
10108 11:04:29.101998
10109 11:04:29.102557 [0x00000100000000, 0x00000240000000)
10110 11:04:30.991906
10111 11:04:30.994906 Initializing XHCI USB controller at 0x11200000.
10112 11:04:32.033005
10113 11:04:32.036570 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10114 11:04:32.036866
10115 11:04:32.037123
10116 11:04:32.037680 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10117 11:04:32.037975 Sending line: 'tftpboot 192.168.201.1 14786783/tftp-deploy-bq371b8n/kernel/image.itb 14786783/tftp-deploy-bq371b8n/kernel/cmdline '
10119 11:04:32.139058 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 11:04:32.139500 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10121 11:04:32.143686 asurada: tftpboot 192.168.201.1 14786783/tftp-deploy-bq371b8n/kernel/image.itp-deploy-bq371b8n/kernel/cmdline
10122 11:04:32.144083
10123 11:04:32.144390 Waiting for link
10124 11:04:32.302017
10125 11:04:32.302628 R8152: Initializing
10126 11:04:32.302950
10127 11:04:32.305013 Version 6 (ocp_data = 5c30)
10128 11:04:32.305400
10129 11:04:32.308300 R8152: Done initializing
10130 11:04:32.308685
10131 11:04:32.308985 Adding net device
10132 11:04:34.401654
10133 11:04:34.402097 done.
10134 11:04:34.402464
10135 11:04:34.402783 MAC: 00:24:32:30:78:ff
10136 11:04:34.403080
10137 11:04:34.404484 Sending DHCP discover... done.
10138 11:04:34.404926
10139 11:04:38.104918 Waiting for reply... done.
10140 11:04:38.105049
10141 11:04:38.105107 Sending DHCP request... done.
10142 11:04:38.109119
10143 11:04:38.109255 Waiting for reply... done.
10144 11:04:38.109317
10145 11:04:38.112320 My ip is 192.168.201.21
10146 11:04:38.112458
10147 11:04:38.115145 The DHCP server ip is 192.168.201.1
10148 11:04:38.115282
10149 11:04:38.118606 TFTP server IP predefined by user: 192.168.201.1
10150 11:04:38.118761
10151 11:04:38.125132 Bootfile predefined by user: 14786783/tftp-deploy-bq371b8n/kernel/image.itb
10152 11:04:38.125280
10153 11:04:38.128481 Sending tftp read request... done.
10154 11:04:38.128617
10155 11:04:38.131413 Waiting for the transfer...
10156 11:04:38.131541
10157 11:04:38.820772 00000000 ################################################################
10158 11:04:38.821234
10159 11:04:39.448185 00080000 ################################################################
10160 11:04:39.448312
10161 11:04:40.126811 00100000 ################################################################
10162 11:04:40.127285
10163 11:04:40.802478 00180000 ################################################################
10164 11:04:40.802935
10165 11:04:41.423933 00200000 ################################################################
10166 11:04:41.424392
10167 11:04:42.140075 00280000 ################################################################
10168 11:04:42.140628
10169 11:04:42.817362 00300000 ################################################################
10170 11:04:42.817799
10171 11:04:43.485092 00380000 ################################################################
10172 11:04:43.485204
10173 11:04:44.070328 00400000 ################################################################
10174 11:04:44.070456
10175 11:04:44.665489 00480000 ################################################################
10176 11:04:44.666383
10177 11:04:45.336746 00500000 ################################################################
10178 11:04:45.337217
10179 11:04:46.002208 00580000 ################################################################
10180 11:04:46.002350
10181 11:04:46.659199 00600000 ################################################################
10182 11:04:46.659677
10183 11:04:47.216212 00680000 ################################################################
10184 11:04:47.216362
10185 11:04:47.778599 00700000 ################################################################
10186 11:04:47.778728
10187 11:04:48.381220 00780000 ################################################################
10188 11:04:48.381775
10189 11:04:49.099232 00800000 ################################################################
10190 11:04:49.099759
10191 11:04:49.801502 00880000 ################################################################
10192 11:04:49.802012
10193 11:04:50.527719 00900000 ################################################################
10194 11:04:50.528247
10195 11:04:51.211834 00980000 ################################################################
10196 11:04:51.212025
10197 11:04:51.850451 00a00000 ################################################################
10198 11:04:51.850926
10199 11:04:52.519510 00a80000 ################################################################
10200 11:04:52.519997
10201 11:04:53.166467 00b00000 ################################################################
10202 11:04:53.166588
10203 11:04:53.850297 00b80000 ################################################################
10204 11:04:53.850752
10205 11:04:54.494877 00c00000 ################################################################
10206 11:04:54.495008
10207 11:04:55.104843 00c80000 ################################################################
10208 11:04:55.105348
10209 11:04:55.826495 00d00000 ################################################################
10210 11:04:55.827049
10211 11:04:56.448261 00d80000 ################################################################
10212 11:04:56.448392
10213 11:04:56.995015 00e00000 ################################################################
10214 11:04:56.995133
10215 11:04:57.558530 00e80000 ################################################################
10216 11:04:57.558658
10217 11:04:58.117861 00f00000 ################################################################
10218 11:04:58.117988
10219 11:04:58.691380 00f80000 ################################################################
10220 11:04:58.691542
10221 11:04:59.256072 01000000 ################################################################
10222 11:04:59.256187
10223 11:04:59.813956 01080000 ################################################################
10224 11:04:59.814096
10225 11:05:00.367869 01100000 ################################################################
10226 11:05:00.367998
10227 11:05:00.917557 01180000 ################################################################
10228 11:05:00.917681
10229 11:05:01.468124 01200000 ################################################################
10230 11:05:01.468291
10231 11:05:02.016626 01280000 ################################################################
10232 11:05:02.016740
10233 11:05:02.569076 01300000 ################################################################
10234 11:05:02.569191
10235 11:05:03.111362 01380000 ################################################################
10236 11:05:03.111482
10237 11:05:03.661236 01400000 ################################################################
10238 11:05:03.661355
10239 11:05:04.208036 01480000 ################################################################
10240 11:05:04.208157
10241 11:05:04.762846 01500000 ################################################################
10242 11:05:04.762969
10243 11:05:05.300131 01580000 ################################################################
10244 11:05:05.300281
10245 11:05:05.848648 01600000 ################################################################
10246 11:05:05.848766
10247 11:05:06.394737 01680000 ################################################################
10248 11:05:06.394856
10249 11:05:06.941939 01700000 ################################################################
10250 11:05:06.942055
10251 11:05:07.493123 01780000 ################################################################
10252 11:05:07.493246
10253 11:05:08.021491 01800000 ################################################################
10254 11:05:08.021675
10255 11:05:08.556255 01880000 ################################################################
10256 11:05:08.556395
10257 11:05:09.086139 01900000 ################################################################
10258 11:05:09.086277
10259 11:05:09.630021 01980000 ################################################################
10260 11:05:09.630168
10261 11:05:10.202895 01a00000 ################################################################
10262 11:05:10.203021
10263 11:05:10.784770 01a80000 ################################################################
10264 11:05:10.784889
10265 11:05:11.347401 01b00000 ################################################################
10266 11:05:11.347522
10267 11:05:11.910473 01b80000 ################################################################
10268 11:05:11.910671
10269 11:05:12.634502 01c00000 ################################################################
10270 11:05:12.635013
10271 11:05:13.357866 01c80000 ################################################################
10272 11:05:13.358375
10273 11:05:14.076102 01d00000 ################################################################
10274 11:05:14.076628
10275 11:05:14.706875 01d80000 ################################################################
10276 11:05:14.707056
10277 11:05:15.211474 01e00000 #################################################### done.
10278 11:05:15.211748
10279 11:05:15.215118 The bootfile was 31875578 bytes long.
10280 11:05:15.215344
10281 11:05:15.218393 Sending tftp read request... done.
10282 11:05:15.218689
10283 11:05:15.218961 Waiting for the transfer...
10284 11:05:15.219174
10285 11:05:15.222141 00000000 # done.
10286 11:05:15.222419
10287 11:05:15.228530 Command line loaded dynamically from TFTP file: 14786783/tftp-deploy-bq371b8n/kernel/cmdline
10288 11:05:15.228765
10289 11:05:15.251519 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786783/extract-nfsrootfs-3uoqcuz9,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10290 11:05:15.251782
10291 11:05:15.252014 Loading FIT.
10292 11:05:15.252230
10293 11:05:15.254852 Image ramdisk-1 has 18710035 bytes.
10294 11:05:15.255083
10295 11:05:15.258032 Image fdt-1 has 47258 bytes.
10296 11:05:15.258296
10297 11:05:15.261543 Image kernel-1 has 13116259 bytes.
10298 11:05:15.261773
10299 11:05:15.271776 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10300 11:05:15.272010
10301 11:05:15.287817 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10302 11:05:15.288057
10303 11:05:15.294397 Choosing best match conf-1 for compat google,spherion-rev2.
10304 11:05:15.294629
10305 11:05:15.302171 Connected to device vid:did:rid of 1ae0:0028:00
10306 11:05:15.310208
10307 11:05:15.313933 tpm_get_response: command 0x17b, return code 0x0
10308 11:05:15.314193
10309 11:05:15.320365 ec_init: CrosEC protocol v3 supported (256, 248)
10310 11:05:15.320546
10311 11:05:15.323651 tpm_cleanup: add release locality here.
10312 11:05:15.323827
10313 11:05:15.327075 Shutting down all USB controllers.
10314 11:05:15.327252
10315 11:05:15.330711 Removing current net device
10316 11:05:15.330888
10317 11:05:15.333492 Exiting depthcharge with code 4 at timestamp: 76658279
10318 11:05:15.333669
10319 11:05:15.340495 LZMA decompressing kernel-1 to 0x821a6718
10320 11:05:15.340671
10321 11:05:15.343960 LZMA decompressing kernel-1 to 0x40000000
10322 11:05:16.958915
10323 11:05:16.959775 jumping to kernel
10324 11:05:16.961557 end: 2.2.4 bootloader-commands (duration 00:00:49) [common]
10325 11:05:16.962051 start: 2.2.5 auto-login-action (timeout 00:03:31) [common]
10326 11:05:16.962483 Setting prompt string to ['Linux version [0-9]']
10327 11:05:16.962832 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10328 11:05:16.963183 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10329 11:05:17.040741
10330 11:05:17.044009 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10331 11:05:17.048002 start: 2.2.5.1 login-action (timeout 00:03:31) [common]
10332 11:05:17.048275 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10333 11:05:17.048478 Setting prompt string to []
10334 11:05:17.048691 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 11:05:17.048874 Using line separator: #'\n'#
10336 11:05:17.049029 No login prompt set.
10337 11:05:17.049191 Parsing kernel messages
10338 11:05:17.049337 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 11:05:17.049608 [login-action] Waiting for messages, (timeout 00:03:31)
10340 11:05:17.049784 Waiting using forced prompt support (timeout 00:01:46)
10341 11:05:17.066798 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10342 11:05:17.070568 [ 0.000000] random: crng init done
10343 11:05:17.073708 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10344 11:05:17.077337 [ 0.000000] efi: UEFI not found.
10345 11:05:17.086837 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10346 11:05:17.093685 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10347 11:05:17.103328 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10348 11:05:17.113382 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10349 11:05:17.120118 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10350 11:05:17.123313 [ 0.000000] printk: bootconsole [mtk8250] enabled
10351 11:05:17.132236 [ 0.000000] NUMA: No NUMA configuration found
10352 11:05:17.138696 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10353 11:05:17.144779 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10354 11:05:17.145005 [ 0.000000] Zone ranges:
10355 11:05:17.151482 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10356 11:05:17.154888 [ 0.000000] DMA32 empty
10357 11:05:17.161783 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10358 11:05:17.164689 [ 0.000000] Movable zone start for each node
10359 11:05:17.168480 [ 0.000000] Early memory node ranges
10360 11:05:17.174890 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10361 11:05:17.181442 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10362 11:05:17.187908 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10363 11:05:17.194713 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10364 11:05:17.201206 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10365 11:05:17.207943 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10366 11:05:17.265846 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10367 11:05:17.272067 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10368 11:05:17.279253 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10369 11:05:17.282039 [ 0.000000] psci: probing for conduit method from DT.
10370 11:05:17.289064 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10371 11:05:17.292161 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10372 11:05:17.298812 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10373 11:05:17.302452 [ 0.000000] psci: SMC Calling Convention v1.2
10374 11:05:17.308833 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10375 11:05:17.312142 [ 0.000000] Detected VIPT I-cache on CPU0
10376 11:05:17.319036 [ 0.000000] CPU features: detected: GIC system register CPU interface
10377 11:05:17.325452 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10378 11:05:17.332241 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10379 11:05:17.338555 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10380 11:05:17.344998 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10381 11:05:17.351573 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10382 11:05:17.357958 [ 0.000000] alternatives: applying boot alternatives
10383 11:05:17.361493 [ 0.000000] Fallback order for Node 0: 0
10384 11:05:17.371447 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 11:05:17.371572 [ 0.000000] Policy zone: Normal
10386 11:05:17.397586 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786783/extract-nfsrootfs-3uoqcuz9,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10387 11:05:17.407785 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10388 11:05:17.418904 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10389 11:05:17.428373 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10390 11:05:17.435223 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10391 11:05:17.438664 <6>[ 0.000000] software IO TLB: area num 8.
10392 11:05:17.495325 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10393 11:07:02.678796 ShellCommand command timed out.: Sending # in case of corruption. Connection timeout 00:03:31, retry in 00:01:46
10394 11:07:02.679238 pattern: ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10395 11:07:02.679591 Sending line: '#'
10397 11:07:23.907741 ShellCommand command timed out.: Sending # in case of corruption. Connection timeout 00:03:31, retry in 00:00:21
10398 11:07:23.908257 pattern: ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10399 11:07:23.908633 Sending line: '#'
10401 11:07:45.138181 ShellCommand command timed out.: Sending # in case of corruption. Connection timeout 00:03:31, retry in 00:00:21
10402 11:07:45.138838 pattern: ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10403 11:07:45.139386 Sending line: '#'
10405 11:08:06.366282 ShellCommand command timed out.: Sending # in case of corruption. Connection timeout 00:03:31, retry in 00:00:21
10406 11:08:06.366406 pattern: ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10407 11:08:06.366471 Sending line: '#'
10409 11:08:27.594271 ShellCommand command timed out.: Sending # in case of corruption. Connection timeout 00:03:31, retry in 00:00:21
10410 11:08:27.594415 pattern: ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10411 11:08:27.594485 Sending line: '#'
10414 11:08:48.048801 end: 2.2.5.1 login-action (duration 00:03:31) [common]
10416 11:08:48.049653 auto-login-action failed: 1 of 1 attempts. 'login-action timed out after 211 seconds'
10418 11:08:48.050401 end: 2.2.5 auto-login-action (duration 00:03:31) [common]
10420 11:08:48.051178 depthcharge-retry failed: 1 of 1 attempts. 'login-action timed out after 211 seconds'
10422 11:08:48.051877 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10425 11:08:48.053092 end: 2 depthcharge-action (duration 00:05:00) [common]
10427 11:08:48.054054 Cleaning after the job
10428 11:08:48.054523 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/ramdisk
10429 11:08:48.063752 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/kernel
10430 11:08:48.093022 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/dtb
10431 11:08:48.093326 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/nfsrootfs
10432 11:08:48.161001 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786783/tftp-deploy-bq371b8n/modules
10433 11:08:48.166567 start: 4.1 power-off (timeout 00:00:30) [common]
10434 11:08:48.166727 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
10435 11:08:50.264392 >> Command sent successfully.
10436 11:08:50.271561 Returned 0 in 2 seconds
10437 11:08:50.271695 end: 4.1 power-off (duration 00:00:02) [common]
10439 11:08:50.271879 start: 4.2 read-feedback (timeout 00:04:58) [common]
10440 11:08:50.272014 Listened to connection for namespace 'common' for up to 1s
10441 11:08:51.273424 Finalising connection for namespace 'common'
10442 11:08:51.273996 Disconnecting from shell: Finalise
10443 11:08:51.375026 end: 4.2 read-feedback (duration 00:00:01) [common]
10444 11:08:51.375638 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786783
10445 11:08:51.927524 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786783
10446 11:08:51.927691 JobError: Your job cannot terminate cleanly.