Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 25
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:02:10.887670 lava-dispatcher, installed at version: 2024.05
2 11:02:10.887857 start: 0 validate
3 11:02:10.887973 Start time: 2024-07-10 11:02:10.887967+00:00 (UTC)
4 11:02:10.888097 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:10.888238 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:02:10.891028 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:10.891152 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:02:24.898287 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:02:24.899098 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:02:25.169097 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:02:25.169761 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:02:25.698544 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:02:25.699260 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:02:29.208998 validate duration: 18.32
16 11:02:29.209277 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:02:29.209367 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:02:29.209442 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:02:29.209587 Not decompressing ramdisk as can be used compressed.
20 11:02:29.209670 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:02:29.209732 saving as /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/ramdisk/initrd.cpio.gz
22 11:02:29.209788 total size: 5628169 (5 MB)
23 11:02:29.475151 progress 0 % (0 MB)
24 11:02:29.476771 progress 5 % (0 MB)
25 11:02:29.478271 progress 10 % (0 MB)
26 11:02:29.479638 progress 15 % (0 MB)
27 11:02:29.481108 progress 20 % (1 MB)
28 11:02:29.482451 progress 25 % (1 MB)
29 11:02:29.483912 progress 30 % (1 MB)
30 11:02:29.485402 progress 35 % (1 MB)
31 11:02:29.486710 progress 40 % (2 MB)
32 11:02:29.488214 progress 45 % (2 MB)
33 11:02:29.489563 progress 50 % (2 MB)
34 11:02:29.491029 progress 55 % (2 MB)
35 11:02:29.492480 progress 60 % (3 MB)
36 11:02:29.493773 progress 65 % (3 MB)
37 11:02:29.495213 progress 70 % (3 MB)
38 11:02:29.496501 progress 75 % (4 MB)
39 11:02:29.498006 progress 80 % (4 MB)
40 11:02:29.499328 progress 85 % (4 MB)
41 11:02:29.500772 progress 90 % (4 MB)
42 11:02:29.502212 progress 95 % (5 MB)
43 11:02:29.503507 progress 100 % (5 MB)
44 11:02:29.503706 5 MB downloaded in 0.29 s (18.26 MB/s)
45 11:02:29.503851 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:02:29.504066 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:02:29.504143 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:02:29.504217 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:02:29.504352 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:02:29.504413 saving as /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/kernel/Image
52 11:02:29.504465 total size: 54813184 (52 MB)
53 11:02:29.504517 No compression specified
54 11:02:29.505501 progress 0 % (0 MB)
55 11:02:29.518357 progress 5 % (2 MB)
56 11:02:29.531529 progress 10 % (5 MB)
57 11:02:29.544378 progress 15 % (7 MB)
58 11:02:29.557559 progress 20 % (10 MB)
59 11:02:29.570797 progress 25 % (13 MB)
60 11:02:29.584010 progress 30 % (15 MB)
61 11:02:29.597094 progress 35 % (18 MB)
62 11:02:29.610309 progress 40 % (20 MB)
63 11:02:29.623181 progress 45 % (23 MB)
64 11:02:29.636280 progress 50 % (26 MB)
65 11:02:29.649489 progress 55 % (28 MB)
66 11:02:29.662371 progress 60 % (31 MB)
67 11:02:29.675719 progress 65 % (34 MB)
68 11:02:29.688820 progress 70 % (36 MB)
69 11:02:29.701973 progress 75 % (39 MB)
70 11:02:29.715054 progress 80 % (41 MB)
71 11:02:29.728089 progress 85 % (44 MB)
72 11:02:29.741230 progress 90 % (47 MB)
73 11:02:29.754318 progress 95 % (49 MB)
74 11:02:29.767357 progress 100 % (52 MB)
75 11:02:29.767578 52 MB downloaded in 0.26 s (198.68 MB/s)
76 11:02:29.767722 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:02:29.767926 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:02:29.768004 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:02:29.768077 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:02:29.768206 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:02:29.768266 saving as /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/dtb/mt8192-asurada-spherion-r0.dtb
83 11:02:29.768316 total size: 47258 (0 MB)
84 11:02:29.768368 No compression specified
85 11:02:29.769448 progress 69 % (0 MB)
86 11:02:29.769697 progress 100 % (0 MB)
87 11:02:29.769837 0 MB downloaded in 0.00 s (29.70 MB/s)
88 11:02:29.769943 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:02:29.770138 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:02:29.770211 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:02:29.770285 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:02:29.770389 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:02:29.770447 saving as /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/nfsrootfs/full.rootfs.tar
95 11:02:29.770500 total size: 120894716 (115 MB)
96 11:02:29.770554 Using unxz to decompress xz
97 11:02:29.771707 progress 0 % (0 MB)
98 11:02:30.101710 progress 5 % (5 MB)
99 11:02:30.444994 progress 10 % (11 MB)
100 11:02:30.780508 progress 15 % (17 MB)
101 11:02:31.096956 progress 20 % (23 MB)
102 11:02:31.397444 progress 25 % (28 MB)
103 11:02:31.751778 progress 30 % (34 MB)
104 11:02:32.078296 progress 35 % (40 MB)
105 11:02:32.253182 progress 40 % (46 MB)
106 11:02:32.432034 progress 45 % (51 MB)
107 11:02:32.732695 progress 50 % (57 MB)
108 11:02:33.077748 progress 55 % (63 MB)
109 11:02:33.409792 progress 60 % (69 MB)
110 11:02:33.750751 progress 65 % (74 MB)
111 11:02:34.081787 progress 70 % (80 MB)
112 11:02:34.420878 progress 75 % (86 MB)
113 11:02:34.749646 progress 80 % (92 MB)
114 11:02:35.076675 progress 85 % (98 MB)
115 11:02:35.409054 progress 90 % (103 MB)
116 11:02:35.737400 progress 95 % (109 MB)
117 11:02:36.094963 progress 100 % (115 MB)
118 11:02:36.100249 115 MB downloaded in 6.33 s (18.21 MB/s)
119 11:02:36.100406 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:02:36.100616 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:02:36.100692 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:02:36.100766 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:02:36.100897 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:02:36.100960 saving as /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/modules/modules.tar
126 11:02:36.101015 total size: 8607984 (8 MB)
127 11:02:36.101073 Using unxz to decompress xz
128 11:02:36.366281 progress 0 % (0 MB)
129 11:02:36.387306 progress 5 % (0 MB)
130 11:02:36.412222 progress 10 % (0 MB)
131 11:02:36.435842 progress 15 % (1 MB)
132 11:02:36.460511 progress 20 % (1 MB)
133 11:02:36.484958 progress 25 % (2 MB)
134 11:02:36.509221 progress 30 % (2 MB)
135 11:02:36.532246 progress 35 % (2 MB)
136 11:02:36.559749 progress 40 % (3 MB)
137 11:02:36.584935 progress 45 % (3 MB)
138 11:02:36.609751 progress 50 % (4 MB)
139 11:02:36.634826 progress 55 % (4 MB)
140 11:02:36.659565 progress 60 % (4 MB)
141 11:02:36.683909 progress 65 % (5 MB)
142 11:02:36.712745 progress 70 % (5 MB)
143 11:02:36.741890 progress 75 % (6 MB)
144 11:02:36.769148 progress 80 % (6 MB)
145 11:02:36.792536 progress 85 % (7 MB)
146 11:02:36.815668 progress 90 % (7 MB)
147 11:02:36.838873 progress 95 % (7 MB)
148 11:02:36.860972 progress 100 % (8 MB)
149 11:02:36.866165 8 MB downloaded in 0.77 s (10.73 MB/s)
150 11:02:36.866329 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:02:36.866538 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:02:36.866614 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 11:02:36.866688 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 11:02:40.316862 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786811/extract-nfsrootfs-8vk9jkqc
156 11:02:40.317027 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:02:40.317113 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:02:40.317317 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1
159 11:02:40.317434 makedir: /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin
160 11:02:40.317524 makedir: /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/tests
161 11:02:40.317610 makedir: /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/results
162 11:02:40.317688 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-add-keys
163 11:02:40.317807 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-add-sources
164 11:02:40.317919 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-background-process-start
165 11:02:40.318031 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-background-process-stop
166 11:02:40.318151 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-common-functions
167 11:02:40.318263 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-echo-ipv4
168 11:02:40.318372 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-install-packages
169 11:02:40.318479 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-installed-packages
170 11:02:40.318586 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-os-build
171 11:02:40.318693 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-probe-channel
172 11:02:40.318802 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-probe-ip
173 11:02:40.318909 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-target-ip
174 11:02:40.319016 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-target-mac
175 11:02:40.319125 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-target-storage
176 11:02:40.319236 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-test-case
177 11:02:40.319345 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-test-event
178 11:02:40.319451 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-test-feedback
179 11:02:40.319560 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-test-raise
180 11:02:40.319666 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-test-reference
181 11:02:40.319774 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-test-runner
182 11:02:40.319903 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-test-set
183 11:02:40.320010 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-test-shell
184 11:02:40.320119 Updating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-add-keys (debian)
185 11:02:40.320248 Updating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-add-sources (debian)
186 11:02:40.320375 Updating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-install-packages (debian)
187 11:02:40.320499 Updating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-installed-packages (debian)
188 11:02:40.320624 Updating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/bin/lava-os-build (debian)
189 11:02:40.320734 Creating /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/environment
190 11:02:40.320821 LAVA metadata
191 11:02:40.320884 - LAVA_JOB_ID=14786811
192 11:02:40.320939 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:02:40.321026 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 11:02:40.321080 skipped lava-vland-overlay
195 11:02:40.321175 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:02:40.321260 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 11:02:40.321314 skipped lava-multinode-overlay
198 11:02:40.321377 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:02:40.321445 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 11:02:40.321506 Loading test definitions
201 11:02:40.321579 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 11:02:40.321639 Using /lava-14786811 at stage 0
203 11:02:40.321923 uuid=14786811_1.6.2.3.1 testdef=None
204 11:02:40.322002 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:02:40.322075 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 11:02:40.322451 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:02:40.322642 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 11:02:40.323128 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:02:40.323330 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 11:02:40.323824 runner path: /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/0/tests/0_timesync-off test_uuid 14786811_1.6.2.3.1
213 11:02:40.324000 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:02:40.324199 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 11:02:40.324263 Using /lava-14786811 at stage 0
217 11:02:40.324347 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:02:40.324420 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/0/tests/1_kselftest-dt'
219 11:02:44.388902 Running '/usr/bin/git checkout kernelci.org
220 11:02:44.535327 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 11:02:44.535683 uuid=14786811_1.6.2.3.5 testdef=None
222 11:02:44.535783 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 11:02:44.535971 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 11:02:44.536594 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:02:44.536788 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 11:02:44.537925 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:02:44.538269 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 11:02:44.539726 runner path: /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/0/tests/1_kselftest-dt test_uuid 14786811_1.6.2.3.5
232 11:02:44.539829 BOARD='mt8192-asurada-spherion-r0'
233 11:02:44.539911 BRANCH='cip'
234 11:02:44.539989 SKIPFILE='/dev/null'
235 11:02:44.540066 SKIP_INSTALL='True'
236 11:02:44.540141 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:02:44.540218 TST_CASENAME=''
238 11:02:44.540293 TST_CMDFILES='dt'
239 11:02:44.540458 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:02:44.540764 Creating lava-test-runner.conf files
242 11:02:44.540844 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786811/lava-overlay-gjv_rkw1/lava-14786811/0 for stage 0
243 11:02:44.540950 - 0_timesync-off
244 11:02:44.541033 - 1_kselftest-dt
245 11:02:44.541150 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 11:02:44.541251 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 11:02:51.603646 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:02:51.603773 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 11:02:51.603853 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:02:51.603931 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:02:51.604007 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 11:02:51.747570 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:02:51.747712 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 11:02:51.747785 extracting modules file /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786811/extract-nfsrootfs-8vk9jkqc
255 11:02:51.965409 extracting modules file /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786811/extract-overlay-ramdisk-entktavj/ramdisk
256 11:02:52.188627 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:02:52.188765 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 11:02:52.188848 [common] Applying overlay to NFS
259 11:02:52.188907 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786811/compress-overlay-0duywtik/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786811/extract-nfsrootfs-8vk9jkqc
260 11:02:53.049833 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:02:53.049966 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 11:02:53.050051 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:02:53.050129 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 11:02:53.050199 Building ramdisk /var/lib/lava/dispatcher/tmp/14786811/extract-overlay-ramdisk-entktavj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786811/extract-overlay-ramdisk-entktavj/ramdisk
265 11:02:53.328698 >> 129845 blocks
266 11:02:55.398580 rename /var/lib/lava/dispatcher/tmp/14786811/extract-overlay-ramdisk-entktavj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/ramdisk/ramdisk.cpio.gz
267 11:02:55.398746 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:02:55.398834 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 11:02:55.398913 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 11:02:55.398990 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/kernel/Image']
271 11:03:10.094032 Returned 0 in 14 seconds
272 11:03:10.094198 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/kernel/image.itb
273 11:03:14.520344 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:03:14.520460 output: Created: Wed Jul 10 12:03:11 2024
275 11:03:14.520522 output: Image 0 (kernel-1)
276 11:03:14.520576 output: Description:
277 11:03:14.520627 output: Created: Wed Jul 10 12:03:11 2024
278 11:03:14.520678 output: Type: Kernel Image
279 11:03:14.520728 output: Compression: lzma compressed
280 11:03:14.520781 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
281 11:03:14.520831 output: Architecture: AArch64
282 11:03:14.520879 output: OS: Linux
283 11:03:14.520926 output: Load Address: 0x00000000
284 11:03:14.520974 output: Entry Point: 0x00000000
285 11:03:14.521021 output: Hash algo: crc32
286 11:03:14.521069 output: Hash value: 9bb85fb9
287 11:03:14.521116 output: Image 1 (fdt-1)
288 11:03:14.521204 output: Description: mt8192-asurada-spherion-r0
289 11:03:14.521253 output: Created: Wed Jul 10 12:03:11 2024
290 11:03:14.521300 output: Type: Flat Device Tree
291 11:03:14.521348 output: Compression: uncompressed
292 11:03:14.521395 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:03:14.521443 output: Architecture: AArch64
294 11:03:14.521491 output: Hash algo: crc32
295 11:03:14.521537 output: Hash value: 0f8e4d2e
296 11:03:14.521584 output: Image 2 (ramdisk-1)
297 11:03:14.521630 output: Description: unavailable
298 11:03:14.521676 output: Created: Wed Jul 10 12:03:11 2024
299 11:03:14.521723 output: Type: RAMDisk Image
300 11:03:14.521769 output: Compression: uncompressed
301 11:03:14.521816 output: Data Size: 18707718 Bytes = 18269.26 KiB = 17.84 MiB
302 11:03:14.521864 output: Architecture: AArch64
303 11:03:14.521911 output: OS: Linux
304 11:03:14.521958 output: Load Address: unavailable
305 11:03:14.522004 output: Entry Point: unavailable
306 11:03:14.522051 output: Hash algo: crc32
307 11:03:14.522097 output: Hash value: 506a5fb9
308 11:03:14.522143 output: Default Configuration: 'conf-1'
309 11:03:14.522190 output: Configuration 0 (conf-1)
310 11:03:14.522236 output: Description: mt8192-asurada-spherion-r0
311 11:03:14.522283 output: Kernel: kernel-1
312 11:03:14.522329 output: Init Ramdisk: ramdisk-1
313 11:03:14.522375 output: FDT: fdt-1
314 11:03:14.522422 output: Loadables: kernel-1
315 11:03:14.522469 output:
316 11:03:14.522570 end: 1.6.8.1 prepare-fit (duration 00:00:19) [common]
317 11:03:14.522643 end: 1.6.8 prepare-kernel (duration 00:00:19) [common]
318 11:03:14.522719 end: 1.6 prepare-tftp-overlay (duration 00:00:38) [common]
319 11:03:14.522793 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 11:03:14.522849 No LXC device requested
321 11:03:14.522914 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:03:14.523001 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 11:03:14.523081 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:03:14.523135 Checking files for TFTP limit of 4294967296 bytes.
325 11:03:14.523497 end: 1 tftp-deploy (duration 00:00:45) [common]
326 11:03:14.523586 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:03:14.523664 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:03:14.523754 substitutions:
329 11:03:14.523813 - {DTB}: 14786811/tftp-deploy-ta6ugt5m/dtb/mt8192-asurada-spherion-r0.dtb
330 11:03:14.523868 - {INITRD}: 14786811/tftp-deploy-ta6ugt5m/ramdisk/ramdisk.cpio.gz
331 11:03:14.523921 - {KERNEL}: 14786811/tftp-deploy-ta6ugt5m/kernel/Image
332 11:03:14.523970 - {LAVA_MAC}: None
333 11:03:14.524019 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786811/extract-nfsrootfs-8vk9jkqc
334 11:03:14.524069 - {NFS_SERVER_IP}: 192.168.201.1
335 11:03:14.524118 - {PRESEED_CONFIG}: None
336 11:03:14.524174 - {PRESEED_LOCAL}: None
337 11:03:14.524223 - {RAMDISK}: 14786811/tftp-deploy-ta6ugt5m/ramdisk/ramdisk.cpio.gz
338 11:03:14.524272 - {ROOT_PART}: None
339 11:03:14.524320 - {ROOT}: None
340 11:03:14.524368 - {SERVER_IP}: 192.168.201.1
341 11:03:14.524415 - {TEE}: None
342 11:03:14.524463 Parsed boot commands:
343 11:03:14.524509 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:03:14.524649 Parsed boot commands: tftpboot 192.168.201.1 14786811/tftp-deploy-ta6ugt5m/kernel/image.itb 14786811/tftp-deploy-ta6ugt5m/kernel/cmdline
345 11:03:14.524792 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:03:14.524871 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:03:14.524958 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:03:14.525031 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:03:14.525091 Not connected, no need to disconnect.
350 11:03:14.525186 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:03:14.525271 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:03:14.525327 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 11:03:14.528457 Setting prompt string to ['lava-test: # ']
354 11:03:14.528776 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:03:14.528903 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:03:14.529007 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:03:14.529085 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:03:14.529271 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=reboot']
359 11:03:23.679238 >> Command sent successfully.
360 11:03:23.683500 Returned 0 in 9 seconds
361 11:03:23.683680 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:03:23.683917 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:03:23.684023 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:03:23.684104 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:03:23.684174 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:03:23.684259 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:03:23.684769 [Enter `^Ec?' for help]
369 11:03:24.880692
370 11:03:24.881312
371 11:03:24.881760 F0: 102B 0000
372 11:03:24.882170
373 11:03:24.882544 F3: 1001 0000 [0200]
374 11:03:24.882938
375 11:03:24.884185 F3: 1001 0000
376 11:03:24.884593
377 11:03:24.884980 F7: 102D 0000
378 11:03:24.885346
379 11:03:24.885612 F1: 0000 0000
380 11:03:24.887909
381 11:03:24.888335 V0: 0000 0000 [0001]
382 11:03:24.888735
383 11:03:24.889246 00: 0007 8000
384 11:03:24.889735
385 11:03:24.891986 01: 0000 0000
386 11:03:24.892419
387 11:03:24.892834 BP: 0C00 0209 [0000]
388 11:03:24.893283
389 11:03:24.895391 G0: 1182 0000
390 11:03:24.895843
391 11:03:24.896230 EC: 0000 0021 [4000]
392 11:03:24.896598
393 11:03:24.899667 S7: 0000 0000 [0000]
394 11:03:24.900013
395 11:03:24.900281 CC: 0000 0000 [0001]
396 11:03:24.900529
397 11:03:24.900762 T0: 0000 0040 [010F]
398 11:03:24.902935
399 11:03:24.903395 Jump to BL
400 11:03:24.903729
401 11:03:24.927074
402 11:03:24.927513
403 11:03:24.937075 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:03:24.940547 ARM64: Exception handlers installed.
405 11:03:24.940895 ARM64: Testing exception
406 11:03:24.943949 ARM64: Done test exception
407 11:03:24.950506 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:03:24.961024 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:03:24.967759 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:03:24.978521 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:03:24.984981 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:03:24.995223 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:03:25.005311 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:03:25.011882 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:03:25.030579 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:03:25.033655 WDT: Last reset was cold boot
417 11:03:25.037049 SPI1(PAD0) initialized at 2873684 Hz
418 11:03:25.040556 SPI5(PAD0) initialized at 992727 Hz
419 11:03:25.043822 VBOOT: Loading verstage.
420 11:03:25.050317 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:03:25.053658 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:03:25.056953 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:03:25.060246 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:03:25.067612 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:03:25.074624 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:03:25.085471 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 11:03:25.085832
428 11:03:25.086113
429 11:03:25.095550 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:03:25.098759 ARM64: Exception handlers installed.
431 11:03:25.102107 ARM64: Testing exception
432 11:03:25.102459 ARM64: Done test exception
433 11:03:25.108592 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:03:25.111812 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:03:25.126587 Probing TPM: . done!
436 11:03:25.126941 TPM ready after 0 ms
437 11:03:25.133096 Connected to device vid:did:rid of 1ae0:0028:00
438 11:03:25.140004 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 11:03:25.143374 Initialized TPM device CR50 revision 0
440 11:03:25.184695 tlcl_send_startup: Startup return code is 0
441 11:03:25.192608 TPM: setup succeeded
442 11:03:25.208688 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:03:25.216087 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:03:25.224809 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:03:25.233874 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:03:25.237112 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:03:25.240709 in-header: 03 07 00 00 08 00 00 00
448 11:03:25.243917 in-data: aa e4 47 04 13 02 00 00
449 11:03:25.247277 Chrome EC: UHEPI supported
450 11:03:25.253754 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:03:25.257327 in-header: 03 a9 00 00 08 00 00 00
452 11:03:25.260435 in-data: 84 60 60 08 00 00 00 00
453 11:03:25.260819 Phase 1
454 11:03:25.263780 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:03:25.270765 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:03:25.277321 VB2:vb2_check_recovery() Recovery was requested manually
457 11:03:25.280623 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:03:25.284509 Recovery requested (1009000e)
459 11:03:25.292091 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:03:25.297622 tlcl_extend: response is 0
461 11:03:25.305832 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:03:25.310995 tlcl_extend: response is 0
463 11:03:25.317690 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:03:25.338133 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:03:25.345004 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:03:25.345435
467 11:03:25.345783
468 11:03:25.354869 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:03:25.358279 ARM64: Exception handlers installed.
470 11:03:25.361387 ARM64: Testing exception
471 11:03:25.361908 ARM64: Done test exception
472 11:03:25.384223 pmic_efuse_setting: Set efuses in 11 msecs
473 11:03:25.388256 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:03:25.391575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:03:25.399514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:03:25.403034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:03:25.407023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:03:25.414556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:03:25.417785 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:03:25.421533 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:03:25.425232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:03:25.432276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:03:25.436334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:03:25.439557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:03:25.446853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:03:25.450728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:03:25.458391 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:03:25.461711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:03:25.468891 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:03:25.472765 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:03:25.479883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:03:25.483655 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:03:25.491122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:03:25.495125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:03:25.502934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:03:25.506393 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:03:25.513619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:03:25.517838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:03:25.524905 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:03:25.529005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:03:25.532742 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:03:25.539619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:03:25.543435 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:03:25.547132 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:03:25.554778 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:03:25.558154 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:03:25.561912 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:03:25.569007 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:03:25.572663 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:03:25.576896 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:03:25.584352 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:03:25.588133 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:03:25.592069 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:03:25.595643 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:03:25.599498 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:03:25.602959 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:03:25.610632 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:03:25.614605 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:03:25.618209 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:03:25.621977 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:03:25.625662 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:03:25.629076 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:03:25.633005 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:03:25.640548 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:03:25.648130 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:03:25.655522 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:03:25.658738 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:03:25.668778 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:03:25.675683 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:03:25.682453 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:03:25.685679 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:03:25.688778 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:03:25.696839 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x8
534 11:03:25.703167 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:03:25.706672 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:03:25.709772 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:03:25.720937 [RTC]rtc_get_frequency_meter,154: input=15, output=773
538 11:03:25.730786 [RTC]rtc_get_frequency_meter,154: input=23, output=959
539 11:03:25.740125 [RTC]rtc_get_frequency_meter,154: input=19, output=866
540 11:03:25.749859 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 11:03:25.759238 [RTC]rtc_get_frequency_meter,154: input=16, output=796
542 11:03:25.762941 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 11:03:25.770049 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 11:03:25.773528 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
545 11:03:25.777191 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 11:03:25.780971 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
547 11:03:25.784185 ADC[4]: Raw value=902507 ID=7
548 11:03:25.787415 ADC[3]: Raw value=213179 ID=1
549 11:03:25.787921 RAM Code: 0x71
550 11:03:25.791039 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 11:03:25.798388 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 11:03:25.804825 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 11:03:25.811515 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:03:25.814810 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 11:03:25.818323 in-header: 03 07 00 00 08 00 00 00
556 11:03:25.821520 in-data: aa e4 47 04 13 02 00 00
557 11:03:25.824935 Chrome EC: UHEPI supported
558 11:03:25.831664 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 11:03:25.835026 in-header: 03 a9 00 00 08 00 00 00
560 11:03:25.838630 in-data: 84 60 60 08 00 00 00 00
561 11:03:25.841699 MRC: failed to locate region type 0.
562 11:03:25.848484 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 11:03:25.851672 DRAM-K: Running full calibration
564 11:03:25.858236 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 11:03:25.858627 header.status = 0x0
566 11:03:25.861910 header.version = 0x6 (expected: 0x6)
567 11:03:25.865204 header.size = 0xd00 (expected: 0xd00)
568 11:03:25.868387 header.flags = 0x0
569 11:03:25.875349 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 11:03:25.891311 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
571 11:03:25.898399 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 11:03:25.901674 dram_init: ddr_geometry: 2
573 11:03:25.902245 [EMI] MDL number = 2
574 11:03:25.904756 [EMI] Get MDL freq = 0
575 11:03:25.908304 dram_init: ddr_type: 0
576 11:03:25.908711 is_discrete_lpddr4: 1
577 11:03:25.911831 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 11:03:25.912344
579 11:03:25.912739
580 11:03:25.915007 [Bian_co] ETT version 0.0.0.1
581 11:03:25.918447 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 11:03:25.921735
583 11:03:25.925030 dramc_set_vcore_voltage set vcore to 650000
584 11:03:25.925577 Read voltage for 800, 4
585 11:03:25.928390 Vio18 = 0
586 11:03:25.928801 Vcore = 650000
587 11:03:25.929279 Vdram = 0
588 11:03:25.931587 Vddq = 0
589 11:03:25.932148 Vmddr = 0
590 11:03:25.935204 dram_init: config_dvfs: 1
591 11:03:25.938550 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 11:03:25.945076 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 11:03:25.948297 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
594 11:03:25.951719 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
595 11:03:25.954870 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 11:03:25.958262 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 11:03:25.961473 MEM_TYPE=3, freq_sel=18
598 11:03:25.964900 sv_algorithm_assistance_LP4_1600
599 11:03:25.968174 ============ PULL DRAM RESETB DOWN ============
600 11:03:25.971930 ========== PULL DRAM RESETB DOWN end =========
601 11:03:25.978360 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 11:03:25.981613 ===================================
603 11:03:25.982010 LPDDR4 DRAM CONFIGURATION
604 11:03:25.985172 ===================================
605 11:03:25.988565 EX_ROW_EN[0] = 0x0
606 11:03:25.991994 EX_ROW_EN[1] = 0x0
607 11:03:25.992375 LP4Y_EN = 0x0
608 11:03:25.995188 WORK_FSP = 0x0
609 11:03:25.995568 WL = 0x2
610 11:03:25.998205 RL = 0x2
611 11:03:25.998751 BL = 0x2
612 11:03:26.001787 RPST = 0x0
613 11:03:26.002166 RD_PRE = 0x0
614 11:03:26.004953 WR_PRE = 0x1
615 11:03:26.005394 WR_PST = 0x0
616 11:03:26.008478 DBI_WR = 0x0
617 11:03:26.008860 DBI_RD = 0x0
618 11:03:26.011798 OTF = 0x1
619 11:03:26.014947 ===================================
620 11:03:26.018370 ===================================
621 11:03:26.018775 ANA top config
622 11:03:26.021668 ===================================
623 11:03:26.025466 DLL_ASYNC_EN = 0
624 11:03:26.028441 ALL_SLAVE_EN = 1
625 11:03:26.028851 NEW_RANK_MODE = 1
626 11:03:26.031743 DLL_IDLE_MODE = 1
627 11:03:26.035368 LP45_APHY_COMB_EN = 1
628 11:03:26.038319 TX_ODT_DIS = 1
629 11:03:26.041944 NEW_8X_MODE = 1
630 11:03:26.042359 ===================================
631 11:03:26.045290 ===================================
632 11:03:26.048207 data_rate = 1600
633 11:03:26.052082 CKR = 1
634 11:03:26.055430 DQ_P2S_RATIO = 8
635 11:03:26.058654 ===================================
636 11:03:26.061964 CA_P2S_RATIO = 8
637 11:03:26.065315 DQ_CA_OPEN = 0
638 11:03:26.065706 DQ_SEMI_OPEN = 0
639 11:03:26.068593 CA_SEMI_OPEN = 0
640 11:03:26.072318 CA_FULL_RATE = 0
641 11:03:26.075533 DQ_CKDIV4_EN = 1
642 11:03:26.078763 CA_CKDIV4_EN = 1
643 11:03:26.082129 CA_PREDIV_EN = 0
644 11:03:26.082526 PH8_DLY = 0
645 11:03:26.085705 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 11:03:26.088903 DQ_AAMCK_DIV = 4
647 11:03:26.092188 CA_AAMCK_DIV = 4
648 11:03:26.095574 CA_ADMCK_DIV = 4
649 11:03:26.096082 DQ_TRACK_CA_EN = 0
650 11:03:26.098799 CA_PICK = 800
651 11:03:26.102372 CA_MCKIO = 800
652 11:03:26.105379 MCKIO_SEMI = 0
653 11:03:26.108971 PLL_FREQ = 3068
654 11:03:26.112244 DQ_UI_PI_RATIO = 32
655 11:03:26.115452 CA_UI_PI_RATIO = 0
656 11:03:26.119084 ===================================
657 11:03:26.122276 ===================================
658 11:03:26.122674 memory_type:LPDDR4
659 11:03:26.125621 GP_NUM : 10
660 11:03:26.128992 SRAM_EN : 1
661 11:03:26.129530 MD32_EN : 0
662 11:03:26.132237 ===================================
663 11:03:26.135796 [ANA_INIT] >>>>>>>>>>>>>>
664 11:03:26.139319 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 11:03:26.142476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:03:26.145637 ===================================
667 11:03:26.149195 data_rate = 1600,PCW = 0X7600
668 11:03:26.152357 ===================================
669 11:03:26.156051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 11:03:26.159349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 11:03:26.166206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 11:03:26.168957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 11:03:26.172578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 11:03:26.179690 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 11:03:26.180122 [ANA_INIT] flow start
676 11:03:26.180424 [ANA_INIT] PLL >>>>>>>>
677 11:03:26.182565 [ANA_INIT] PLL <<<<<<<<
678 11:03:26.186096 [ANA_INIT] MIDPI >>>>>>>>
679 11:03:26.189342 [ANA_INIT] MIDPI <<<<<<<<
680 11:03:26.189735 [ANA_INIT] DLL >>>>>>>>
681 11:03:26.192429 [ANA_INIT] flow end
682 11:03:26.195967 ============ LP4 DIFF to SE enter ============
683 11:03:26.199500 ============ LP4 DIFF to SE exit ============
684 11:03:26.202756 [ANA_INIT] <<<<<<<<<<<<<
685 11:03:26.205764 [Flow] Enable top DCM control >>>>>
686 11:03:26.209264 [Flow] Enable top DCM control <<<<<
687 11:03:26.212500 Enable DLL master slave shuffle
688 11:03:26.219053 ==============================================================
689 11:03:26.219195 Gating Mode config
690 11:03:26.225604 ==============================================================
691 11:03:26.225711 Config description:
692 11:03:26.235413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 11:03:26.242011 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 11:03:26.249432 SELPH_MODE 0: By rank 1: By Phase
695 11:03:26.252452 ==============================================================
696 11:03:26.255725 GAT_TRACK_EN = 1
697 11:03:26.258861 RX_GATING_MODE = 2
698 11:03:26.262367 RX_GATING_TRACK_MODE = 2
699 11:03:26.265728 SELPH_MODE = 1
700 11:03:26.268997 PICG_EARLY_EN = 1
701 11:03:26.272297 VALID_LAT_VALUE = 1
702 11:03:26.275634 ==============================================================
703 11:03:26.279259 Enter into Gating configuration >>>>
704 11:03:26.282696 Exit from Gating configuration <<<<
705 11:03:26.285939 Enter into DVFS_PRE_config >>>>>
706 11:03:26.299092 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 11:03:26.299239 Exit from DVFS_PRE_config <<<<<
708 11:03:26.302732 Enter into PICG configuration >>>>
709 11:03:26.305739 Exit from PICG configuration <<<<
710 11:03:26.309327 [RX_INPUT] configuration >>>>>
711 11:03:26.312648 [RX_INPUT] configuration <<<<<
712 11:03:26.319403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 11:03:26.322369 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 11:03:26.329668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 11:03:26.335889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 11:03:26.342878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 11:03:26.349435 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 11:03:26.352611 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 11:03:26.355965 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 11:03:26.359874 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 11:03:26.366278 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 11:03:26.369688 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 11:03:26.373215 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 11:03:26.376630 ===================================
725 11:03:26.379787 LPDDR4 DRAM CONFIGURATION
726 11:03:26.383019 ===================================
727 11:03:26.383405 EX_ROW_EN[0] = 0x0
728 11:03:26.386715 EX_ROW_EN[1] = 0x0
729 11:03:26.387099 LP4Y_EN = 0x0
730 11:03:26.389921 WORK_FSP = 0x0
731 11:03:26.390304 WL = 0x2
732 11:03:26.393224 RL = 0x2
733 11:03:26.393609 BL = 0x2
734 11:03:26.396456 RPST = 0x0
735 11:03:26.396843 RD_PRE = 0x0
736 11:03:26.399874 WR_PRE = 0x1
737 11:03:26.403381 WR_PST = 0x0
738 11:03:26.403764 DBI_WR = 0x0
739 11:03:26.406743 DBI_RD = 0x0
740 11:03:26.407127 OTF = 0x1
741 11:03:26.410001 ===================================
742 11:03:26.413749 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 11:03:26.416919 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 11:03:26.423509 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 11:03:26.427051 ===================================
746 11:03:26.427436 LPDDR4 DRAM CONFIGURATION
747 11:03:26.430341 ===================================
748 11:03:26.433760 EX_ROW_EN[0] = 0x10
749 11:03:26.437307 EX_ROW_EN[1] = 0x0
750 11:03:26.437690 LP4Y_EN = 0x0
751 11:03:26.440877 WORK_FSP = 0x0
752 11:03:26.441332 WL = 0x2
753 11:03:26.441650 RL = 0x2
754 11:03:26.444499 BL = 0x2
755 11:03:26.444902 RPST = 0x0
756 11:03:26.448038 RD_PRE = 0x0
757 11:03:26.448425 WR_PRE = 0x1
758 11:03:26.452528 WR_PST = 0x0
759 11:03:26.452920 DBI_WR = 0x0
760 11:03:26.456016 DBI_RD = 0x0
761 11:03:26.456402 OTF = 0x1
762 11:03:26.459659 ===================================
763 11:03:26.466875 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 11:03:26.471051 nWR fixed to 40
765 11:03:26.471447 [ModeRegInit_LP4] CH0 RK0
766 11:03:26.474119 [ModeRegInit_LP4] CH0 RK1
767 11:03:26.477424 [ModeRegInit_LP4] CH1 RK0
768 11:03:26.477877 [ModeRegInit_LP4] CH1 RK1
769 11:03:26.480409 match AC timing 13
770 11:03:26.484251 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 11:03:26.487365 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 11:03:26.494266 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 11:03:26.497510 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 11:03:26.504146 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 11:03:26.504539 [EMI DOE] emi_dcm 0
776 11:03:26.507460 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 11:03:26.510652 ==
778 11:03:26.511037 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:03:26.517247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:03:26.517638 ==
781 11:03:26.520829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 11:03:26.527290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 11:03:26.537167 [CA 0] Center 37 (7~68) winsize 62
784 11:03:26.540497 [CA 1] Center 38 (7~69) winsize 63
785 11:03:26.543842 [CA 2] Center 35 (5~66) winsize 62
786 11:03:26.547066 [CA 3] Center 35 (4~66) winsize 63
787 11:03:26.550657 [CA 4] Center 34 (4~65) winsize 62
788 11:03:26.553821 [CA 5] Center 33 (3~64) winsize 62
789 11:03:26.554212
790 11:03:26.557220 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 11:03:26.557612
792 11:03:26.560905 [CATrainingPosCal] consider 1 rank data
793 11:03:26.563735 u2DelayCellTimex100 = 270/100 ps
794 11:03:26.567461 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 11:03:26.570612 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 11:03:26.577514 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 11:03:26.580806 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
798 11:03:26.584209 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 11:03:26.587845 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 11:03:26.588232
801 11:03:26.591521 CA PerBit enable=1, Macro0, CA PI delay=33
802 11:03:26.591907
803 11:03:26.594880 [CBTSetCACLKResult] CA Dly = 33
804 11:03:26.595266 CS Dly: 6 (0~37)
805 11:03:26.595560 ==
806 11:03:26.598037 Dram Type= 6, Freq= 0, CH_0, rank 1
807 11:03:26.601303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 11:03:26.604471 ==
809 11:03:26.608124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 11:03:26.614577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 11:03:26.623791 [CA 0] Center 38 (7~69) winsize 63
812 11:03:26.626945 [CA 1] Center 38 (7~69) winsize 63
813 11:03:26.630501 [CA 2] Center 36 (6~67) winsize 62
814 11:03:26.633761 [CA 3] Center 35 (5~66) winsize 62
815 11:03:26.637076 [CA 4] Center 35 (4~66) winsize 63
816 11:03:26.640297 [CA 5] Center 34 (4~65) winsize 62
817 11:03:26.640710
818 11:03:26.643556 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 11:03:26.643945
820 11:03:26.646860 [CATrainingPosCal] consider 2 rank data
821 11:03:26.650409 u2DelayCellTimex100 = 270/100 ps
822 11:03:26.653752 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
823 11:03:26.657168 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 11:03:26.663897 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 11:03:26.667269 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 11:03:26.670241 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 11:03:26.673739 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 11:03:26.674127
829 11:03:26.677107 CA PerBit enable=1, Macro0, CA PI delay=34
830 11:03:26.677532
831 11:03:26.680354 [CBTSetCACLKResult] CA Dly = 34
832 11:03:26.680741 CS Dly: 6 (0~38)
833 11:03:26.681187
834 11:03:26.684085 ----->DramcWriteLeveling(PI) begin...
835 11:03:26.684479 ==
836 11:03:26.687379 Dram Type= 6, Freq= 0, CH_0, rank 0
837 11:03:26.694063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 11:03:26.694451 ==
839 11:03:26.697083 Write leveling (Byte 0): 31 => 31
840 11:03:26.700625 Write leveling (Byte 1): 31 => 31
841 11:03:26.701014 DramcWriteLeveling(PI) end<-----
842 11:03:26.701353
843 11:03:26.704060 ==
844 11:03:26.707359 Dram Type= 6, Freq= 0, CH_0, rank 0
845 11:03:26.710699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 11:03:26.711089 ==
847 11:03:26.713954 [Gating] SW mode calibration
848 11:03:26.720905 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 11:03:26.724125 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 11:03:26.731168 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 11:03:26.734382 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 11:03:26.737623 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 11:03:26.744308 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:03:26.747561 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:03:26.750945 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:03:26.754492 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:03:26.760923 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:03:26.764365 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:03:26.767698 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:03:26.774725 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:03:26.778109 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:03:26.781195 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:03:26.787778 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:03:26.791143 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:03:26.794778 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:03:26.801694 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 11:03:26.804948 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
868 11:03:26.808153 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
869 11:03:26.811616 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:03:26.818183 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:03:26.821410 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:03:26.825099 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:03:26.831525 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:03:26.834697 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:03:26.838479 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
876 11:03:26.844896 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
877 11:03:26.847972 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
878 11:03:26.851971 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:03:26.858351 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:03:26.861532 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:03:26.865039 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:03:26.871580 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:03:26.874754 0 10 4 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
884 11:03:26.878504 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
885 11:03:26.881908 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
886 11:03:26.888285 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:03:26.891706 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:03:26.894964 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:03:26.901842 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:03:26.905398 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
891 11:03:26.908560 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
892 11:03:26.915365 0 11 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
893 11:03:26.918436 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
894 11:03:26.921798 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:03:26.928375 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:03:26.931650 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 11:03:26.935430 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:03:26.941815 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:03:26.945037 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 11:03:26.948343 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:03:26.955119 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:03:26.958743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:03:26.961967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:03:26.965163 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:03:26.971989 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:03:26.975252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:03:26.978135 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:03:26.985115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:03:26.988324 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:03:26.991525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:03:26.998589 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:03:27.001695 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:03:27.005071 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:03:27.012112 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:03:27.015058 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 11:03:27.018575 Total UI for P1: 0, mck2ui 16
917 11:03:27.022178 best dqsien dly found for B0: ( 0, 14, 2)
918 11:03:27.026483 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
919 11:03:27.029687 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 11:03:27.033123 Total UI for P1: 0, mck2ui 16
921 11:03:27.036365 best dqsien dly found for B1: ( 0, 14, 10)
922 11:03:27.040024 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
923 11:03:27.043268 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
924 11:03:27.043651
925 11:03:27.046547 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
926 11:03:27.053036 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
927 11:03:27.053531 [Gating] SW calibration Done
928 11:03:27.053847 ==
929 11:03:27.056386 Dram Type= 6, Freq= 0, CH_0, rank 0
930 11:03:27.063083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 11:03:27.063713 ==
932 11:03:27.064115 RX Vref Scan: 0
933 11:03:27.064402
934 11:03:27.066749 RX Vref 0 -> 0, step: 1
935 11:03:27.067128
936 11:03:27.069956 RX Delay -130 -> 252, step: 16
937 11:03:27.073587 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
938 11:03:27.076489 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 11:03:27.079913 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 11:03:27.083510 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 11:03:27.090056 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
942 11:03:27.093209 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 11:03:27.096778 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 11:03:27.100203 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 11:03:27.103574 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 11:03:27.110099 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 11:03:27.113275 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 11:03:27.116644 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 11:03:27.119964 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
950 11:03:27.123622 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
951 11:03:27.130109 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 11:03:27.133539 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 11:03:27.133923 ==
954 11:03:27.137028 Dram Type= 6, Freq= 0, CH_0, rank 0
955 11:03:27.140106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 11:03:27.140548 ==
957 11:03:27.143372 DQS Delay:
958 11:03:27.143901 DQS0 = 0, DQS1 = 0
959 11:03:27.144282 DQM Delay:
960 11:03:27.146699 DQM0 = 89, DQM1 = 78
961 11:03:27.147083 DQ Delay:
962 11:03:27.150043 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
963 11:03:27.153736 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
964 11:03:27.156859 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 11:03:27.160263 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
966 11:03:27.160694
967 11:03:27.160988
968 11:03:27.161339 ==
969 11:03:27.163603 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:03:27.170065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:03:27.170449 ==
972 11:03:27.170770
973 11:03:27.171043
974 11:03:27.171299 TX Vref Scan disable
975 11:03:27.173836 == TX Byte 0 ==
976 11:03:27.177255 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 11:03:27.180420 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 11:03:27.184089 == TX Byte 1 ==
979 11:03:27.187313 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 11:03:27.190360 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 11:03:27.193926 ==
982 11:03:27.197068 Dram Type= 6, Freq= 0, CH_0, rank 0
983 11:03:27.200716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 11:03:27.201097 ==
985 11:03:27.212855 TX Vref=22, minBit 6, minWin=27, winSum=442
986 11:03:27.216018 TX Vref=24, minBit 8, minWin=27, winSum=443
987 11:03:27.219359 TX Vref=26, minBit 6, minWin=27, winSum=447
988 11:03:27.223000 TX Vref=28, minBit 8, minWin=27, winSum=453
989 11:03:27.226298 TX Vref=30, minBit 9, minWin=27, winSum=456
990 11:03:27.229506 TX Vref=32, minBit 8, minWin=28, winSum=459
991 11:03:27.236103 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
992 11:03:27.236487
993 11:03:27.239690 Final TX Range 1 Vref 32
994 11:03:27.240074
995 11:03:27.240368 ==
996 11:03:27.243012 Dram Type= 6, Freq= 0, CH_0, rank 0
997 11:03:27.246440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 11:03:27.246826 ==
999 11:03:27.247125
1000 11:03:27.247397
1001 11:03:27.249790 TX Vref Scan disable
1002 11:03:27.253031 == TX Byte 0 ==
1003 11:03:27.256244 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1004 11:03:27.259451 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1005 11:03:27.263162 == TX Byte 1 ==
1006 11:03:27.266406 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 11:03:27.269557 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 11:03:27.269947
1009 11:03:27.272875 [DATLAT]
1010 11:03:27.273299 Freq=800, CH0 RK0
1011 11:03:27.273630
1012 11:03:27.276215 DATLAT Default: 0xa
1013 11:03:27.276600 0, 0xFFFF, sum = 0
1014 11:03:27.279375 1, 0xFFFF, sum = 0
1015 11:03:27.279452 2, 0xFFFF, sum = 0
1016 11:03:27.282509 3, 0xFFFF, sum = 0
1017 11:03:27.282586 4, 0xFFFF, sum = 0
1018 11:03:27.286057 5, 0xFFFF, sum = 0
1019 11:03:27.286133 6, 0xFFFF, sum = 0
1020 11:03:27.289515 7, 0xFFFF, sum = 0
1021 11:03:27.289618 8, 0xFFFF, sum = 0
1022 11:03:27.292823 9, 0x0, sum = 1
1023 11:03:27.292921 10, 0x0, sum = 2
1024 11:03:27.295758 11, 0x0, sum = 3
1025 11:03:27.295854 12, 0x0, sum = 4
1026 11:03:27.299790 best_step = 10
1027 11:03:27.299878
1028 11:03:27.299963 ==
1029 11:03:27.302980 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 11:03:27.306113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 11:03:27.306203 ==
1032 11:03:27.306288 RX Vref Scan: 1
1033 11:03:27.309348
1034 11:03:27.309437 Set Vref Range= 32 -> 127
1035 11:03:27.309518
1036 11:03:27.312581 RX Vref 32 -> 127, step: 1
1037 11:03:27.312669
1038 11:03:27.316279 RX Delay -95 -> 252, step: 8
1039 11:03:27.316374
1040 11:03:27.319939 Set Vref, RX VrefLevel [Byte0]: 32
1041 11:03:27.322846 [Byte1]: 32
1042 11:03:27.322934
1043 11:03:27.326214 Set Vref, RX VrefLevel [Byte0]: 33
1044 11:03:27.329685 [Byte1]: 33
1045 11:03:27.329779
1046 11:03:27.332899 Set Vref, RX VrefLevel [Byte0]: 34
1047 11:03:27.336214 [Byte1]: 34
1048 11:03:27.340436
1049 11:03:27.340603 Set Vref, RX VrefLevel [Byte0]: 35
1050 11:03:27.343687 [Byte1]: 35
1051 11:03:27.347779
1052 11:03:27.347919 Set Vref, RX VrefLevel [Byte0]: 36
1053 11:03:27.351261 [Byte1]: 36
1054 11:03:27.355496
1055 11:03:27.355746 Set Vref, RX VrefLevel [Byte0]: 37
1056 11:03:27.358835 [Byte1]: 37
1057 11:03:27.363083
1058 11:03:27.363351 Set Vref, RX VrefLevel [Byte0]: 38
1059 11:03:27.369788 [Byte1]: 38
1060 11:03:27.370140
1061 11:03:27.372969 Set Vref, RX VrefLevel [Byte0]: 39
1062 11:03:27.376339 [Byte1]: 39
1063 11:03:27.376815
1064 11:03:27.379519 Set Vref, RX VrefLevel [Byte0]: 40
1065 11:03:27.382789 [Byte1]: 40
1066 11:03:27.383267
1067 11:03:27.386640 Set Vref, RX VrefLevel [Byte0]: 41
1068 11:03:27.389607 [Byte1]: 41
1069 11:03:27.393500
1070 11:03:27.393995 Set Vref, RX VrefLevel [Byte0]: 42
1071 11:03:27.396853 [Byte1]: 42
1072 11:03:27.401295
1073 11:03:27.401787 Set Vref, RX VrefLevel [Byte0]: 43
1074 11:03:27.404739 [Byte1]: 43
1075 11:03:27.408759
1076 11:03:27.409302 Set Vref, RX VrefLevel [Byte0]: 44
1077 11:03:27.412138 [Byte1]: 44
1078 11:03:27.416290
1079 11:03:27.416781 Set Vref, RX VrefLevel [Byte0]: 45
1080 11:03:27.419537 [Byte1]: 45
1081 11:03:27.424073
1082 11:03:27.424581 Set Vref, RX VrefLevel [Byte0]: 46
1083 11:03:27.427181 [Byte1]: 46
1084 11:03:27.431793
1085 11:03:27.432179 Set Vref, RX VrefLevel [Byte0]: 47
1086 11:03:27.434789 [Byte1]: 47
1087 11:03:27.439471
1088 11:03:27.439857 Set Vref, RX VrefLevel [Byte0]: 48
1089 11:03:27.442562 [Byte1]: 48
1090 11:03:27.446769
1091 11:03:27.447153 Set Vref, RX VrefLevel [Byte0]: 49
1092 11:03:27.449903 [Byte1]: 49
1093 11:03:27.454643
1094 11:03:27.455030 Set Vref, RX VrefLevel [Byte0]: 50
1095 11:03:27.457627 [Byte1]: 50
1096 11:03:27.462010
1097 11:03:27.462477 Set Vref, RX VrefLevel [Byte0]: 51
1098 11:03:27.465248 [Byte1]: 51
1099 11:03:27.469586
1100 11:03:27.470055 Set Vref, RX VrefLevel [Byte0]: 52
1101 11:03:27.472997 [Byte1]: 52
1102 11:03:27.477545
1103 11:03:27.477930 Set Vref, RX VrefLevel [Byte0]: 53
1104 11:03:27.480290 [Byte1]: 53
1105 11:03:27.485047
1106 11:03:27.485485 Set Vref, RX VrefLevel [Byte0]: 54
1107 11:03:27.488224 [Byte1]: 54
1108 11:03:27.492472
1109 11:03:27.492877 Set Vref, RX VrefLevel [Byte0]: 55
1110 11:03:27.495800 [Byte1]: 55
1111 11:03:27.499922
1112 11:03:27.500342 Set Vref, RX VrefLevel [Byte0]: 56
1113 11:03:27.503409 [Byte1]: 56
1114 11:03:27.507458
1115 11:03:27.507874 Set Vref, RX VrefLevel [Byte0]: 57
1116 11:03:27.510958 [Byte1]: 57
1117 11:03:27.515277
1118 11:03:27.515672 Set Vref, RX VrefLevel [Byte0]: 58
1119 11:03:27.518423 [Byte1]: 58
1120 11:03:27.522773
1121 11:03:27.523160 Set Vref, RX VrefLevel [Byte0]: 59
1122 11:03:27.526035 [Byte1]: 59
1123 11:03:27.530450
1124 11:03:27.530837 Set Vref, RX VrefLevel [Byte0]: 60
1125 11:03:27.533626 [Byte1]: 60
1126 11:03:27.538124
1127 11:03:27.538509 Set Vref, RX VrefLevel [Byte0]: 61
1128 11:03:27.541503 [Byte1]: 61
1129 11:03:27.545954
1130 11:03:27.546412 Set Vref, RX VrefLevel [Byte0]: 62
1131 11:03:27.548776 [Byte1]: 62
1132 11:03:27.553447
1133 11:03:27.553834 Set Vref, RX VrefLevel [Byte0]: 63
1134 11:03:27.556671 [Byte1]: 63
1135 11:03:27.560864
1136 11:03:27.561312 Set Vref, RX VrefLevel [Byte0]: 64
1137 11:03:27.564135 [Byte1]: 64
1138 11:03:27.568416
1139 11:03:27.568813 Set Vref, RX VrefLevel [Byte0]: 65
1140 11:03:27.571517 [Byte1]: 65
1141 11:03:27.576153
1142 11:03:27.576554 Set Vref, RX VrefLevel [Byte0]: 66
1143 11:03:27.579281 [Byte1]: 66
1144 11:03:27.583319
1145 11:03:27.583720 Set Vref, RX VrefLevel [Byte0]: 67
1146 11:03:27.587054 [Byte1]: 67
1147 11:03:27.591065
1148 11:03:27.591465 Set Vref, RX VrefLevel [Byte0]: 68
1149 11:03:27.594703 [Byte1]: 68
1150 11:03:27.599025
1151 11:03:27.599426 Set Vref, RX VrefLevel [Byte0]: 69
1152 11:03:27.602271 [Byte1]: 69
1153 11:03:27.606370
1154 11:03:27.606770 Set Vref, RX VrefLevel [Byte0]: 70
1155 11:03:27.609499 [Byte1]: 70
1156 11:03:27.613770
1157 11:03:27.614166 Set Vref, RX VrefLevel [Byte0]: 71
1158 11:03:27.617465 [Byte1]: 71
1159 11:03:27.621798
1160 11:03:27.622196 Set Vref, RX VrefLevel [Byte0]: 72
1161 11:03:27.624889 [Byte1]: 72
1162 11:03:27.629283
1163 11:03:27.629683 Set Vref, RX VrefLevel [Byte0]: 73
1164 11:03:27.632342 [Byte1]: 73
1165 11:03:27.636589
1166 11:03:27.636987 Set Vref, RX VrefLevel [Byte0]: 74
1167 11:03:27.639899 [Byte1]: 74
1168 11:03:27.644426
1169 11:03:27.644822 Set Vref, RX VrefLevel [Byte0]: 75
1170 11:03:27.647943 [Byte1]: 75
1171 11:03:27.651988
1172 11:03:27.652390 Set Vref, RX VrefLevel [Byte0]: 76
1173 11:03:27.655183 [Byte1]: 76
1174 11:03:27.659485
1175 11:03:27.659883 Final RX Vref Byte 0 = 62 to rank0
1176 11:03:27.663186 Final RX Vref Byte 1 = 55 to rank0
1177 11:03:27.666364 Final RX Vref Byte 0 = 62 to rank1
1178 11:03:27.669655 Final RX Vref Byte 1 = 55 to rank1==
1179 11:03:27.673219 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 11:03:27.679714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 11:03:27.680129 ==
1182 11:03:27.680531 DQS Delay:
1183 11:03:27.680963 DQS0 = 0, DQS1 = 0
1184 11:03:27.683153 DQM Delay:
1185 11:03:27.683551 DQM0 = 93, DQM1 = 81
1186 11:03:27.686444 DQ Delay:
1187 11:03:27.690006 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1188 11:03:27.690407 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1189 11:03:27.693252 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1190 11:03:27.696593 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1191 11:03:27.699942
1192 11:03:27.700355
1193 11:03:27.706770 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1194 11:03:27.709862 CH0 RK0: MR19=606, MR18=3D38
1195 11:03:27.716775 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1196 11:03:27.717204
1197 11:03:27.719760 ----->DramcWriteLeveling(PI) begin...
1198 11:03:27.720183 ==
1199 11:03:27.723221 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 11:03:27.726607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 11:03:27.727037 ==
1202 11:03:27.729829 Write leveling (Byte 0): 31 => 31
1203 11:03:27.733324 Write leveling (Byte 1): 30 => 30
1204 11:03:27.736519 DramcWriteLeveling(PI) end<-----
1205 11:03:27.736910
1206 11:03:27.737276 ==
1207 11:03:27.739811 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 11:03:27.743474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 11:03:27.743862 ==
1210 11:03:27.746956 [Gating] SW mode calibration
1211 11:03:27.753206 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 11:03:27.759886 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 11:03:27.763414 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 11:03:27.766699 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1215 11:03:27.773718 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1216 11:03:27.776919 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:03:27.780187 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:03:27.783574 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:03:27.790107 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:03:27.793616 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:03:27.796787 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:03:27.803364 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:03:27.806850 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:03:27.810593 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:03:27.854379 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:03:27.854794 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:03:27.855423 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:03:27.855737 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:03:27.856035 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:03:27.856312 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1231 11:03:27.856573 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:03:27.856893 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:03:27.857205 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:03:27.857503 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:03:27.877595 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:03:27.878038 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:03:27.878887 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:03:27.879255 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1239 11:03:27.879558 0 9 8 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
1240 11:03:27.881286 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 11:03:27.884483 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 11:03:27.891015 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 11:03:27.894622 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 11:03:27.898038 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:03:27.904691 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:03:27.907865 0 10 4 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
1247 11:03:27.911127 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1248 11:03:27.918061 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:03:27.921418 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:03:27.924665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:03:27.931602 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:03:27.934775 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:03:27.938284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:03:27.944795 0 11 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1255 11:03:27.948153 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
1256 11:03:27.951522 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 11:03:27.954917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 11:03:27.961652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:03:27.964768 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:03:27.968082 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:03:27.974978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:03:27.978345 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1263 11:03:27.981778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:03:27.988270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:03:27.991723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:03:27.994709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:03:28.001726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:03:28.004854 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:03:28.008152 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:03:28.015040 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:03:28.018235 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:03:28.021663 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:03:28.028102 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:03:28.031457 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:03:28.035149 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:03:28.038381 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:03:28.044937 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:03:28.048434 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 11:03:28.051835 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 11:03:28.054922 Total UI for P1: 0, mck2ui 16
1281 11:03:28.058731 best dqsien dly found for B0: ( 0, 14, 4)
1282 11:03:28.062072 Total UI for P1: 0, mck2ui 16
1283 11:03:28.065505 best dqsien dly found for B1: ( 0, 14, 4)
1284 11:03:28.068889 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1285 11:03:28.072106 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1286 11:03:28.072494
1287 11:03:28.078655 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1288 11:03:28.081812 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1289 11:03:28.082202 [Gating] SW calibration Done
1290 11:03:28.085337 ==
1291 11:03:28.088251 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 11:03:28.091771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 11:03:28.092165 ==
1294 11:03:28.092465 RX Vref Scan: 0
1295 11:03:28.092744
1296 11:03:28.095016 RX Vref 0 -> 0, step: 1
1297 11:03:28.095399
1298 11:03:28.098382 RX Delay -130 -> 252, step: 16
1299 11:03:28.102143 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1300 11:03:28.105383 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1301 11:03:28.108629 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1302 11:03:28.115030 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1303 11:03:28.118312 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1304 11:03:28.121981 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1305 11:03:28.125069 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1306 11:03:28.128364 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1307 11:03:28.135295 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1308 11:03:28.138498 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1309 11:03:28.141677 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1310 11:03:28.145218 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1311 11:03:28.148687 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1312 11:03:28.155212 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1313 11:03:28.158739 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1314 11:03:28.161975 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1315 11:03:28.162363 ==
1316 11:03:28.165177 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 11:03:28.168392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 11:03:28.168786 ==
1319 11:03:28.172147 DQS Delay:
1320 11:03:28.172550 DQS0 = 0, DQS1 = 0
1321 11:03:28.175471 DQM Delay:
1322 11:03:28.175886 DQM0 = 90, DQM1 = 79
1323 11:03:28.176187 DQ Delay:
1324 11:03:28.178817 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1325 11:03:28.182158 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1326 11:03:28.185318 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1327 11:03:28.188877 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1328 11:03:28.189339
1329 11:03:28.189644
1330 11:03:28.191890 ==
1331 11:03:28.192281 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 11:03:28.198784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 11:03:28.199170 ==
1334 11:03:28.199515
1335 11:03:28.199795
1336 11:03:28.201862 TX Vref Scan disable
1337 11:03:28.202281 == TX Byte 0 ==
1338 11:03:28.205777 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1339 11:03:28.212345 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1340 11:03:28.212735 == TX Byte 1 ==
1341 11:03:28.215314 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1342 11:03:28.222127 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1343 11:03:28.222546 ==
1344 11:03:28.225426 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 11:03:28.228878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 11:03:28.229321 ==
1347 11:03:28.242154 TX Vref=22, minBit 8, minWin=27, winSum=447
1348 11:03:28.245433 TX Vref=24, minBit 8, minWin=27, winSum=452
1349 11:03:28.248687 TX Vref=26, minBit 8, minWin=27, winSum=451
1350 11:03:28.251868 TX Vref=28, minBit 8, minWin=27, winSum=453
1351 11:03:28.255383 TX Vref=30, minBit 10, minWin=27, winSum=456
1352 11:03:28.258706 TX Vref=32, minBit 8, minWin=27, winSum=455
1353 11:03:28.265477 [TxChooseVref] Worse bit 10, Min win 27, Win sum 456, Final Vref 30
1354 11:03:28.265872
1355 11:03:28.268905 Final TX Range 1 Vref 30
1356 11:03:28.269350
1357 11:03:28.269681 ==
1358 11:03:28.272130 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 11:03:28.275370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 11:03:28.275796 ==
1361 11:03:28.276103
1362 11:03:28.278457
1363 11:03:28.278971 TX Vref Scan disable
1364 11:03:28.282295 == TX Byte 0 ==
1365 11:03:28.285556 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1366 11:03:28.288863 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1367 11:03:28.292089 == TX Byte 1 ==
1368 11:03:28.295355 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1369 11:03:28.298850 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1370 11:03:28.302055
1371 11:03:28.302464 [DATLAT]
1372 11:03:28.302763 Freq=800, CH0 RK1
1373 11:03:28.303074
1374 11:03:28.305418 DATLAT Default: 0xa
1375 11:03:28.305830 0, 0xFFFF, sum = 0
1376 11:03:28.308862 1, 0xFFFF, sum = 0
1377 11:03:28.309376 2, 0xFFFF, sum = 0
1378 11:03:28.311912 3, 0xFFFF, sum = 0
1379 11:03:28.312303 4, 0xFFFF, sum = 0
1380 11:03:28.315338 5, 0xFFFF, sum = 0
1381 11:03:28.315761 6, 0xFFFF, sum = 0
1382 11:03:28.318886 7, 0xFFFF, sum = 0
1383 11:03:28.319273 8, 0xFFFF, sum = 0
1384 11:03:28.322166 9, 0x0, sum = 1
1385 11:03:28.322557 10, 0x0, sum = 2
1386 11:03:28.325425 11, 0x0, sum = 3
1387 11:03:28.325702 12, 0x0, sum = 4
1388 11:03:28.328455 best_step = 10
1389 11:03:28.328726
1390 11:03:28.328934 ==
1391 11:03:28.331900 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 11:03:28.335555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 11:03:28.335769 ==
1394 11:03:28.338557 RX Vref Scan: 0
1395 11:03:28.338761
1396 11:03:28.338920 RX Vref 0 -> 0, step: 1
1397 11:03:28.339065
1398 11:03:28.342126 RX Delay -95 -> 252, step: 8
1399 11:03:28.348712 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1400 11:03:28.352064 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1401 11:03:28.355743 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1402 11:03:28.358965 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1403 11:03:28.362056 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1404 11:03:28.365513 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1405 11:03:28.372253 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1406 11:03:28.375622 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1407 11:03:28.379426 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1408 11:03:28.382621 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1409 11:03:28.385715 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1410 11:03:28.392605 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1411 11:03:28.395877 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1412 11:03:28.399603 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1413 11:03:28.402602 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1414 11:03:28.406185 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1415 11:03:28.409281 ==
1416 11:03:28.409703 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 11:03:28.416444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 11:03:28.416834 ==
1419 11:03:28.417209 DQS Delay:
1420 11:03:28.419556 DQS0 = 0, DQS1 = 0
1421 11:03:28.419958 DQM Delay:
1422 11:03:28.422675 DQM0 = 91, DQM1 = 81
1423 11:03:28.423064 DQ Delay:
1424 11:03:28.426141 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1425 11:03:28.429237 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1426 11:03:28.433067 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1427 11:03:28.436213 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1428 11:03:28.436617
1429 11:03:28.436928
1430 11:03:28.442535 [DQSOSCAuto] RK1, (LSB)MR18= 0x4720, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1431 11:03:28.446208 CH0 RK1: MR19=606, MR18=4720
1432 11:03:28.452830 CH0_RK1: MR19=0x606, MR18=0x4720, DQSOSC=392, MR23=63, INC=96, DEC=64
1433 11:03:28.455985 [RxdqsGatingPostProcess] freq 800
1434 11:03:28.459234 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 11:03:28.462977 Pre-setting of DQS Precalculation
1436 11:03:28.469356 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 11:03:28.469889 ==
1438 11:03:28.472984 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 11:03:28.476089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 11:03:28.476477 ==
1441 11:03:28.483064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 11:03:28.489621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 11:03:28.496998 [CA 0] Center 36 (6~67) winsize 62
1444 11:03:28.500301 [CA 1] Center 36 (6~67) winsize 62
1445 11:03:28.503551 [CA 2] Center 34 (4~65) winsize 62
1446 11:03:28.507053 [CA 3] Center 34 (3~65) winsize 63
1447 11:03:28.510400 [CA 4] Center 34 (3~65) winsize 63
1448 11:03:28.513591 [CA 5] Center 33 (3~64) winsize 62
1449 11:03:28.513982
1450 11:03:28.517249 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1451 11:03:28.517642
1452 11:03:28.520456 [CATrainingPosCal] consider 1 rank data
1453 11:03:28.523731 u2DelayCellTimex100 = 270/100 ps
1454 11:03:28.527420 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1455 11:03:28.530428 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1456 11:03:28.533790 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1457 11:03:28.540381 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1458 11:03:28.543737 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1459 11:03:28.547050 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1460 11:03:28.547441
1461 11:03:28.550645 CA PerBit enable=1, Macro0, CA PI delay=33
1462 11:03:28.551037
1463 11:03:28.553930 [CBTSetCACLKResult] CA Dly = 33
1464 11:03:28.554324 CS Dly: 5 (0~36)
1465 11:03:28.554621 ==
1466 11:03:28.557283 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 11:03:28.564052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 11:03:28.564449 ==
1469 11:03:28.567271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 11:03:28.574371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 11:03:28.583172 [CA 0] Center 36 (6~67) winsize 62
1472 11:03:28.586550 [CA 1] Center 36 (6~67) winsize 62
1473 11:03:28.589966 [CA 2] Center 35 (5~66) winsize 62
1474 11:03:28.593195 [CA 3] Center 34 (4~65) winsize 62
1475 11:03:28.596498 [CA 4] Center 34 (4~65) winsize 62
1476 11:03:28.599742 [CA 5] Center 34 (3~65) winsize 63
1477 11:03:28.600134
1478 11:03:28.603049 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1479 11:03:28.603440
1480 11:03:28.606177 [CATrainingPosCal] consider 2 rank data
1481 11:03:28.609950 u2DelayCellTimex100 = 270/100 ps
1482 11:03:28.613228 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1483 11:03:28.616696 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1484 11:03:28.623396 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1485 11:03:28.626660 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1486 11:03:28.629920 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1487 11:03:28.633394 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1488 11:03:28.633814
1489 11:03:28.636601 CA PerBit enable=1, Macro0, CA PI delay=33
1490 11:03:28.637010
1491 11:03:28.640054 [CBTSetCACLKResult] CA Dly = 33
1492 11:03:28.640520 CS Dly: 6 (0~38)
1493 11:03:28.640989
1494 11:03:28.643311 ----->DramcWriteLeveling(PI) begin...
1495 11:03:28.646514 ==
1496 11:03:28.646925 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 11:03:28.653476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 11:03:28.653898 ==
1499 11:03:28.656478 Write leveling (Byte 0): 26 => 26
1500 11:03:28.660026 Write leveling (Byte 1): 30 => 30
1501 11:03:28.663212 DramcWriteLeveling(PI) end<-----
1502 11:03:28.663731
1503 11:03:28.664194 ==
1504 11:03:28.666552 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 11:03:28.669811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 11:03:28.670221 ==
1507 11:03:28.673253 [Gating] SW mode calibration
1508 11:03:28.680104 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 11:03:28.683247 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 11:03:28.690098 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1511 11:03:28.693539 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1512 11:03:28.696617 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:03:28.703518 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:03:28.706917 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:03:28.709856 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:03:28.716886 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:03:28.720378 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:03:28.723586 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:03:28.730006 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:03:28.733187 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:03:28.737018 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:03:28.743354 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:03:28.746577 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:03:28.749939 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:03:28.753267 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:03:28.759970 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1527 11:03:28.763311 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1528 11:03:28.767045 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:03:28.773550 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:03:28.776760 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:03:28.779968 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:03:28.786647 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:03:28.790075 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:03:28.793558 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:03:28.800076 0 9 4 | B1->B0 | 2626 2d2d | 1 0 | (1 1) (0 0)
1536 11:03:28.803298 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 11:03:28.806641 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 11:03:28.813235 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 11:03:28.816939 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 11:03:28.820217 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 11:03:28.826900 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 11:03:28.830311 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1543 11:03:28.833614 0 10 4 | B1->B0 | 2f2f 2929 | 0 0 | (0 1) (0 0)
1544 11:03:28.837231 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:03:28.843765 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:03:28.846843 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:03:28.850315 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:03:28.856781 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:03:28.860470 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:03:28.863274 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1551 11:03:28.870180 0 11 4 | B1->B0 | 3232 3d3c | 0 1 | (0 0) (0 0)
1552 11:03:28.873312 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 11:03:28.876482 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 11:03:28.883587 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:03:28.886714 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 11:03:28.889983 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 11:03:28.893361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:03:28.900184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:03:28.903337 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1560 11:03:28.906686 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:03:28.913639 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:03:28.916645 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:03:28.920509 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:03:28.926935 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:03:28.930009 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:03:28.933384 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:03:28.939979 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:03:28.943524 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:03:28.946886 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:03:28.953596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:03:28.956853 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:03:28.960496 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:03:28.967084 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:03:28.970212 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:03:28.973560 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1576 11:03:28.976846 Total UI for P1: 0, mck2ui 16
1577 11:03:28.980537 best dqsien dly found for B1: ( 0, 14, 2)
1578 11:03:28.983631 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 11:03:28.987227 Total UI for P1: 0, mck2ui 16
1580 11:03:28.990339 best dqsien dly found for B0: ( 0, 14, 4)
1581 11:03:28.993541 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1582 11:03:28.997205 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1583 11:03:28.997291
1584 11:03:29.003781 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1585 11:03:29.007378 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1586 11:03:29.007465 [Gating] SW calibration Done
1587 11:03:29.010419 ==
1588 11:03:29.014089 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 11:03:29.017080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 11:03:29.017192 ==
1591 11:03:29.017274 RX Vref Scan: 0
1592 11:03:29.017354
1593 11:03:29.020766 RX Vref 0 -> 0, step: 1
1594 11:03:29.020841
1595 11:03:29.023836 RX Delay -130 -> 252, step: 16
1596 11:03:29.027067 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1597 11:03:29.030735 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1598 11:03:29.037140 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1599 11:03:29.040359 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1600 11:03:29.044018 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1601 11:03:29.047272 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1602 11:03:29.050678 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1603 11:03:29.054212 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1604 11:03:29.060457 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1605 11:03:29.063982 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1606 11:03:29.067336 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1607 11:03:29.070442 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1608 11:03:29.074120 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1609 11:03:29.080541 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1610 11:03:29.084337 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1611 11:03:29.087394 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1612 11:03:29.087526 ==
1613 11:03:29.090687 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 11:03:29.094158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 11:03:29.094239 ==
1616 11:03:29.097193 DQS Delay:
1617 11:03:29.097306 DQS0 = 0, DQS1 = 0
1618 11:03:29.100534 DQM Delay:
1619 11:03:29.100641 DQM0 = 87, DQM1 = 80
1620 11:03:29.100746 DQ Delay:
1621 11:03:29.104052 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1622 11:03:29.107301 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1623 11:03:29.110913 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1624 11:03:29.113986 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1625 11:03:29.114098
1626 11:03:29.114184
1627 11:03:29.117716 ==
1628 11:03:29.117839 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 11:03:29.124204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 11:03:29.124342 ==
1631 11:03:29.124449
1632 11:03:29.124546
1633 11:03:29.127556 TX Vref Scan disable
1634 11:03:29.127727 == TX Byte 0 ==
1635 11:03:29.131162 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1636 11:03:29.137634 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1637 11:03:29.137927 == TX Byte 1 ==
1638 11:03:29.141014 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1639 11:03:29.148162 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1640 11:03:29.148513 ==
1641 11:03:29.151482 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 11:03:29.154886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 11:03:29.155285 ==
1644 11:03:29.167708 TX Vref=22, minBit 8, minWin=27, winSum=448
1645 11:03:29.171406 TX Vref=24, minBit 8, minWin=27, winSum=451
1646 11:03:29.174807 TX Vref=26, minBit 15, minWin=27, winSum=455
1647 11:03:29.177979 TX Vref=28, minBit 15, minWin=27, winSum=455
1648 11:03:29.181035 TX Vref=30, minBit 15, minWin=27, winSum=457
1649 11:03:29.188076 TX Vref=32, minBit 12, minWin=27, winSum=457
1650 11:03:29.191396 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 30
1651 11:03:29.191788
1652 11:03:29.194599 Final TX Range 1 Vref 30
1653 11:03:29.194986
1654 11:03:29.195284 ==
1655 11:03:29.198119 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 11:03:29.201277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 11:03:29.204707 ==
1658 11:03:29.205092
1659 11:03:29.205433
1660 11:03:29.205711 TX Vref Scan disable
1661 11:03:29.208341 == TX Byte 0 ==
1662 11:03:29.211511 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1663 11:03:29.214765 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1664 11:03:29.218330 == TX Byte 1 ==
1665 11:03:29.221408 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1666 11:03:29.224882 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1667 11:03:29.228095
1668 11:03:29.228484 [DATLAT]
1669 11:03:29.228784 Freq=800, CH1 RK0
1670 11:03:29.229066
1671 11:03:29.231504 DATLAT Default: 0xa
1672 11:03:29.231890 0, 0xFFFF, sum = 0
1673 11:03:29.234845 1, 0xFFFF, sum = 0
1674 11:03:29.235470 2, 0xFFFF, sum = 0
1675 11:03:29.238144 3, 0xFFFF, sum = 0
1676 11:03:29.238515 4, 0xFFFF, sum = 0
1677 11:03:29.241746 5, 0xFFFF, sum = 0
1678 11:03:29.242176 6, 0xFFFF, sum = 0
1679 11:03:29.245219 7, 0xFFFF, sum = 0
1680 11:03:29.245724 8, 0xFFFF, sum = 0
1681 11:03:29.248335 9, 0x0, sum = 1
1682 11:03:29.248739 10, 0x0, sum = 2
1683 11:03:29.251848 11, 0x0, sum = 3
1684 11:03:29.252305 12, 0x0, sum = 4
1685 11:03:29.254953 best_step = 10
1686 11:03:29.255426
1687 11:03:29.255733 ==
1688 11:03:29.258204 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 11:03:29.262136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 11:03:29.262564 ==
1691 11:03:29.265000 RX Vref Scan: 1
1692 11:03:29.265443
1693 11:03:29.265751 Set Vref Range= 32 -> 127
1694 11:03:29.266024
1695 11:03:29.268218 RX Vref 32 -> 127, step: 1
1696 11:03:29.268639
1697 11:03:29.271681 RX Delay -95 -> 252, step: 8
1698 11:03:29.272226
1699 11:03:29.274881 Set Vref, RX VrefLevel [Byte0]: 32
1700 11:03:29.278288 [Byte1]: 32
1701 11:03:29.278694
1702 11:03:29.282099 Set Vref, RX VrefLevel [Byte0]: 33
1703 11:03:29.285052 [Byte1]: 33
1704 11:03:29.288250
1705 11:03:29.288644 Set Vref, RX VrefLevel [Byte0]: 34
1706 11:03:29.292021 [Byte1]: 34
1707 11:03:29.296285
1708 11:03:29.296685 Set Vref, RX VrefLevel [Byte0]: 35
1709 11:03:29.299520 [Byte1]: 35
1710 11:03:29.303662
1711 11:03:29.304103 Set Vref, RX VrefLevel [Byte0]: 36
1712 11:03:29.306830 [Byte1]: 36
1713 11:03:29.311414
1714 11:03:29.311820 Set Vref, RX VrefLevel [Byte0]: 37
1715 11:03:29.314653 [Byte1]: 37
1716 11:03:29.318730
1717 11:03:29.319110 Set Vref, RX VrefLevel [Byte0]: 38
1718 11:03:29.322414 [Byte1]: 38
1719 11:03:29.326456
1720 11:03:29.326836 Set Vref, RX VrefLevel [Byte0]: 39
1721 11:03:29.329682 [Byte1]: 39
1722 11:03:29.334102
1723 11:03:29.334481 Set Vref, RX VrefLevel [Byte0]: 40
1724 11:03:29.337326 [Byte1]: 40
1725 11:03:29.341814
1726 11:03:29.342197 Set Vref, RX VrefLevel [Byte0]: 41
1727 11:03:29.344940 [Byte1]: 41
1728 11:03:29.349231
1729 11:03:29.349628 Set Vref, RX VrefLevel [Byte0]: 42
1730 11:03:29.352658 [Byte1]: 42
1731 11:03:29.356950
1732 11:03:29.357469 Set Vref, RX VrefLevel [Byte0]: 43
1733 11:03:29.360145 [Byte1]: 43
1734 11:03:29.364439
1735 11:03:29.364830 Set Vref, RX VrefLevel [Byte0]: 44
1736 11:03:29.367827 [Byte1]: 44
1737 11:03:29.372248
1738 11:03:29.372675 Set Vref, RX VrefLevel [Byte0]: 45
1739 11:03:29.375164 [Byte1]: 45
1740 11:03:29.379578
1741 11:03:29.379958 Set Vref, RX VrefLevel [Byte0]: 46
1742 11:03:29.383091 [Byte1]: 46
1743 11:03:29.387252
1744 11:03:29.387664 Set Vref, RX VrefLevel [Byte0]: 47
1745 11:03:29.390582 [Byte1]: 47
1746 11:03:29.394973
1747 11:03:29.395369 Set Vref, RX VrefLevel [Byte0]: 48
1748 11:03:29.398098 [Byte1]: 48
1749 11:03:29.402691
1750 11:03:29.403070 Set Vref, RX VrefLevel [Byte0]: 49
1751 11:03:29.405905 [Byte1]: 49
1752 11:03:29.410069
1753 11:03:29.410560 Set Vref, RX VrefLevel [Byte0]: 50
1754 11:03:29.413425 [Byte1]: 50
1755 11:03:29.417659
1756 11:03:29.418038 Set Vref, RX VrefLevel [Byte0]: 51
1757 11:03:29.420827 [Byte1]: 51
1758 11:03:29.425232
1759 11:03:29.425632 Set Vref, RX VrefLevel [Byte0]: 52
1760 11:03:29.428458 [Byte1]: 52
1761 11:03:29.432681
1762 11:03:29.433080 Set Vref, RX VrefLevel [Byte0]: 53
1763 11:03:29.435964 [Byte1]: 53
1764 11:03:29.440495
1765 11:03:29.440896 Set Vref, RX VrefLevel [Byte0]: 54
1766 11:03:29.443780 [Byte1]: 54
1767 11:03:29.448024
1768 11:03:29.448406 Set Vref, RX VrefLevel [Byte0]: 55
1769 11:03:29.451413 [Byte1]: 55
1770 11:03:29.455744
1771 11:03:29.456143 Set Vref, RX VrefLevel [Byte0]: 56
1772 11:03:29.459068 [Byte1]: 56
1773 11:03:29.463293
1774 11:03:29.463674 Set Vref, RX VrefLevel [Byte0]: 57
1775 11:03:29.466435 [Byte1]: 57
1776 11:03:29.470876
1777 11:03:29.471445 Set Vref, RX VrefLevel [Byte0]: 58
1778 11:03:29.473834 [Byte1]: 58
1779 11:03:29.478444
1780 11:03:29.478869 Set Vref, RX VrefLevel [Byte0]: 59
1781 11:03:29.481706 [Byte1]: 59
1782 11:03:29.486132
1783 11:03:29.486542 Set Vref, RX VrefLevel [Byte0]: 60
1784 11:03:29.489293 [Byte1]: 60
1785 11:03:29.493515
1786 11:03:29.493947 Set Vref, RX VrefLevel [Byte0]: 61
1787 11:03:29.497066 [Byte1]: 61
1788 11:03:29.501391
1789 11:03:29.501815 Set Vref, RX VrefLevel [Byte0]: 62
1790 11:03:29.504391 [Byte1]: 62
1791 11:03:29.509079
1792 11:03:29.509522 Set Vref, RX VrefLevel [Byte0]: 63
1793 11:03:29.512228 [Byte1]: 63
1794 11:03:29.516234
1795 11:03:29.516646 Set Vref, RX VrefLevel [Byte0]: 64
1796 11:03:29.519655 [Byte1]: 64
1797 11:03:29.524007
1798 11:03:29.524417 Set Vref, RX VrefLevel [Byte0]: 65
1799 11:03:29.527301 [Byte1]: 65
1800 11:03:29.531760
1801 11:03:29.532173 Set Vref, RX VrefLevel [Byte0]: 66
1802 11:03:29.535016 [Byte1]: 66
1803 11:03:29.539070
1804 11:03:29.539461 Set Vref, RX VrefLevel [Byte0]: 67
1805 11:03:29.542749 [Byte1]: 67
1806 11:03:29.546923
1807 11:03:29.547312 Set Vref, RX VrefLevel [Byte0]: 68
1808 11:03:29.549963 [Byte1]: 68
1809 11:03:29.554527
1810 11:03:29.554890 Set Vref, RX VrefLevel [Byte0]: 69
1811 11:03:29.557669 [Byte1]: 69
1812 11:03:29.562011
1813 11:03:29.562495 Set Vref, RX VrefLevel [Byte0]: 70
1814 11:03:29.565192 [Byte1]: 70
1815 11:03:29.569445
1816 11:03:29.569872 Set Vref, RX VrefLevel [Byte0]: 71
1817 11:03:29.572751 [Byte1]: 71
1818 11:03:29.577252
1819 11:03:29.577660 Set Vref, RX VrefLevel [Byte0]: 72
1820 11:03:29.580686 [Byte1]: 72
1821 11:03:29.584579
1822 11:03:29.584985 Set Vref, RX VrefLevel [Byte0]: 73
1823 11:03:29.587858 [Byte1]: 73
1824 11:03:29.592449
1825 11:03:29.592837 Set Vref, RX VrefLevel [Byte0]: 74
1826 11:03:29.595634 [Byte1]: 74
1827 11:03:29.599970
1828 11:03:29.600357 Set Vref, RX VrefLevel [Byte0]: 75
1829 11:03:29.603142 [Byte1]: 75
1830 11:03:29.607750
1831 11:03:29.608176 Set Vref, RX VrefLevel [Byte0]: 76
1832 11:03:29.610678 [Byte1]: 76
1833 11:03:29.615328
1834 11:03:29.615725 Set Vref, RX VrefLevel [Byte0]: 77
1835 11:03:29.618267 [Byte1]: 77
1836 11:03:29.622712
1837 11:03:29.623109 Set Vref, RX VrefLevel [Byte0]: 78
1838 11:03:29.625959 [Byte1]: 78
1839 11:03:29.630277
1840 11:03:29.630658 Set Vref, RX VrefLevel [Byte0]: 79
1841 11:03:29.633675 [Byte1]: 79
1842 11:03:29.637930
1843 11:03:29.638353 Final RX Vref Byte 0 = 51 to rank0
1844 11:03:29.641673 Final RX Vref Byte 1 = 63 to rank0
1845 11:03:29.644866 Final RX Vref Byte 0 = 51 to rank1
1846 11:03:29.647700 Final RX Vref Byte 1 = 63 to rank1==
1847 11:03:29.651411 Dram Type= 6, Freq= 0, CH_1, rank 0
1848 11:03:29.654702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 11:03:29.657939 ==
1850 11:03:29.658330 DQS Delay:
1851 11:03:29.658656 DQS0 = 0, DQS1 = 0
1852 11:03:29.661380 DQM Delay:
1853 11:03:29.661780 DQM0 = 92, DQM1 = 81
1854 11:03:29.664597 DQ Delay:
1855 11:03:29.667867 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1856 11:03:29.668264 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1857 11:03:29.671626 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =72
1858 11:03:29.678152 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1859 11:03:29.678558
1860 11:03:29.678865
1861 11:03:29.684815 [DQSOSCAuto] RK0, (LSB)MR18= 0x3855, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
1862 11:03:29.688199 CH1 RK0: MR19=606, MR18=3855
1863 11:03:29.694917 CH1_RK0: MR19=0x606, MR18=0x3855, DQSOSC=388, MR23=63, INC=98, DEC=65
1864 11:03:29.695322
1865 11:03:29.698210 ----->DramcWriteLeveling(PI) begin...
1866 11:03:29.698618 ==
1867 11:03:29.701411 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 11:03:29.705054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 11:03:29.705506 ==
1870 11:03:29.708177 Write leveling (Byte 0): 28 => 28
1871 11:03:29.711708 Write leveling (Byte 1): 30 => 30
1872 11:03:29.715433 DramcWriteLeveling(PI) end<-----
1873 11:03:29.715851
1874 11:03:29.716165 ==
1875 11:03:29.718171 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 11:03:29.721530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 11:03:29.721986 ==
1878 11:03:29.725182 [Gating] SW mode calibration
1879 11:03:29.731662 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1880 11:03:29.738368 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1881 11:03:29.741760 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1882 11:03:29.745510 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1883 11:03:29.748711 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1884 11:03:29.755251 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:03:29.760336 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:03:29.761809 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:03:29.768484 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:03:29.771553 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:03:29.775193 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:03:29.781775 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:03:29.785163 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:03:29.788598 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:03:29.795077 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:03:29.798826 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:03:29.802117 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:03:29.808579 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:03:29.812304 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:03:29.815579 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1899 11:03:29.819056 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:03:29.825747 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:03:29.828950 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:03:29.832213 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:03:29.838938 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:03:29.842366 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:03:29.845912 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:03:29.852483 0 9 4 | B1->B0 | 2323 2424 | 1 0 | (0 0) (1 1)
1907 11:03:29.855689 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1908 11:03:29.858976 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 11:03:29.865657 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 11:03:29.868869 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 11:03:29.872543 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 11:03:29.879140 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 11:03:29.882259 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (0 0) (0 1)
1914 11:03:29.885530 0 10 4 | B1->B0 | 2a2a 2f2f | 0 1 | (0 0) (1 1)
1915 11:03:29.892353 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:03:29.895983 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:03:29.899199 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 11:03:29.902600 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 11:03:29.909206 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:03:29.912432 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:03:29.916118 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1922 11:03:29.922740 0 11 4 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
1923 11:03:29.925885 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 11:03:29.929561 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 11:03:29.936128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 11:03:29.939695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 11:03:29.942586 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 11:03:29.949564 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 11:03:29.952799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 11:03:29.956095 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1931 11:03:29.962750 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1932 11:03:29.965979 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:03:29.969749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:03:29.972846 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:03:29.979493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:03:29.982734 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:03:29.986056 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:03:29.993045 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:03:29.996116 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:03:29.999326 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:03:30.006397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:03:30.009532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:03:30.013205 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:03:30.019396 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:03:30.023095 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:03:30.026450 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1947 11:03:30.029524 Total UI for P1: 0, mck2ui 16
1948 11:03:30.033112 best dqsien dly found for B1: ( 0, 14, 2)
1949 11:03:30.036841 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1950 11:03:30.040028 Total UI for P1: 0, mck2ui 16
1951 11:03:30.043415 best dqsien dly found for B0: ( 0, 14, 4)
1952 11:03:30.046506 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1953 11:03:30.049971 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1954 11:03:30.050356
1955 11:03:30.056553 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 11:03:30.060062 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1957 11:03:30.060457 [Gating] SW calibration Done
1958 11:03:30.063274 ==
1959 11:03:30.066809 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 11:03:30.069959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 11:03:30.070394 ==
1962 11:03:30.070709 RX Vref Scan: 0
1963 11:03:30.071040
1964 11:03:30.073754 RX Vref 0 -> 0, step: 1
1965 11:03:30.074142
1966 11:03:30.077003 RX Delay -130 -> 252, step: 16
1967 11:03:30.080170 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1968 11:03:30.083373 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1969 11:03:30.086759 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1970 11:03:30.093475 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1971 11:03:30.096738 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1972 11:03:30.100406 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1973 11:03:30.103802 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1974 11:03:30.106978 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1975 11:03:30.113487 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1976 11:03:30.116998 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1977 11:03:30.120335 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1978 11:03:30.123790 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1979 11:03:30.126987 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1980 11:03:30.133833 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1981 11:03:30.137219 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1982 11:03:30.140377 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1983 11:03:30.140923 ==
1984 11:03:30.143634 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 11:03:30.147157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 11:03:30.147788 ==
1987 11:03:30.150604 DQS Delay:
1988 11:03:30.150993 DQS0 = 0, DQS1 = 0
1989 11:03:30.151472 DQM Delay:
1990 11:03:30.153875 DQM0 = 89, DQM1 = 79
1991 11:03:30.154433 DQ Delay:
1992 11:03:30.157049 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1993 11:03:30.160421 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1994 11:03:30.163954 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =77
1995 11:03:30.167250 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1996 11:03:30.167648
1997 11:03:30.167995
1998 11:03:30.168290 ==
1999 11:03:30.170763 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 11:03:30.177242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 11:03:30.177708 ==
2002 11:03:30.178018
2003 11:03:30.178386
2004 11:03:30.178659 TX Vref Scan disable
2005 11:03:30.180726 == TX Byte 0 ==
2006 11:03:30.183900 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2007 11:03:30.187659 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2008 11:03:30.190952 == TX Byte 1 ==
2009 11:03:30.194207 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2010 11:03:30.200789 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2011 11:03:30.201237 ==
2012 11:03:30.203973 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 11:03:30.207041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 11:03:30.207475 ==
2015 11:03:30.219764 TX Vref=22, minBit 9, minWin=27, winSum=447
2016 11:03:30.223236 TX Vref=24, minBit 13, minWin=27, winSum=451
2017 11:03:30.226281 TX Vref=26, minBit 13, minWin=27, winSum=456
2018 11:03:30.230100 TX Vref=28, minBit 12, minWin=27, winSum=456
2019 11:03:30.233410 TX Vref=30, minBit 15, minWin=27, winSum=460
2020 11:03:30.240267 TX Vref=32, minBit 13, minWin=27, winSum=455
2021 11:03:30.243386 [TxChooseVref] Worse bit 15, Min win 27, Win sum 460, Final Vref 30
2022 11:03:30.243879
2023 11:03:30.246486 Final TX Range 1 Vref 30
2024 11:03:30.246826
2025 11:03:30.247189 ==
2026 11:03:30.250253 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 11:03:30.253564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 11:03:30.254113 ==
2029 11:03:30.256794
2030 11:03:30.257232
2031 11:03:30.257561 TX Vref Scan disable
2032 11:03:30.260294 == TX Byte 0 ==
2033 11:03:30.263875 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2034 11:03:30.266993 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2035 11:03:30.270406 == TX Byte 1 ==
2036 11:03:30.273616 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2037 11:03:30.277098 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2038 11:03:30.280336
2039 11:03:30.280730 [DATLAT]
2040 11:03:30.281177 Freq=800, CH1 RK1
2041 11:03:30.281485
2042 11:03:30.283931 DATLAT Default: 0xa
2043 11:03:30.284390 0, 0xFFFF, sum = 0
2044 11:03:30.287419 1, 0xFFFF, sum = 0
2045 11:03:30.287888 2, 0xFFFF, sum = 0
2046 11:03:30.290204 3, 0xFFFF, sum = 0
2047 11:03:30.290640 4, 0xFFFF, sum = 0
2048 11:03:30.293706 5, 0xFFFF, sum = 0
2049 11:03:30.294110 6, 0xFFFF, sum = 0
2050 11:03:30.297173 7, 0xFFFF, sum = 0
2051 11:03:30.297570 8, 0xFFFF, sum = 0
2052 11:03:30.300339 9, 0x0, sum = 1
2053 11:03:30.300729 10, 0x0, sum = 2
2054 11:03:30.303561 11, 0x0, sum = 3
2055 11:03:30.303927 12, 0x0, sum = 4
2056 11:03:30.307185 best_step = 10
2057 11:03:30.307566
2058 11:03:30.307861 ==
2059 11:03:30.310182 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 11:03:30.313656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 11:03:30.314044 ==
2062 11:03:30.316894 RX Vref Scan: 0
2063 11:03:30.317324
2064 11:03:30.317624 RX Vref 0 -> 0, step: 1
2065 11:03:30.317898
2066 11:03:30.320453 RX Delay -95 -> 252, step: 8
2067 11:03:30.327133 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2068 11:03:30.330355 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2069 11:03:30.333673 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2070 11:03:30.337017 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2071 11:03:30.340217 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2072 11:03:30.343794 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2073 11:03:30.350545 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2074 11:03:30.353769 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2075 11:03:30.357063 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2076 11:03:30.360263 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2077 11:03:30.364033 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2078 11:03:30.370401 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2079 11:03:30.373400 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2080 11:03:30.377038 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2081 11:03:30.380164 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2082 11:03:30.383499 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2083 11:03:30.387166 ==
2084 11:03:30.390617 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 11:03:30.393774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 11:03:30.394011 ==
2087 11:03:30.394196 DQS Delay:
2088 11:03:30.397290 DQS0 = 0, DQS1 = 0
2089 11:03:30.397585 DQM Delay:
2090 11:03:30.400536 DQM0 = 91, DQM1 = 83
2091 11:03:30.400999 DQ Delay:
2092 11:03:30.404019 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2093 11:03:30.407234 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2094 11:03:30.410846 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2095 11:03:30.414026 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2096 11:03:30.414411
2097 11:03:30.414704
2098 11:03:30.420863 [DQSOSCAuto] RK1, (LSB)MR18= 0x4016, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
2099 11:03:30.424052 CH1 RK1: MR19=606, MR18=4016
2100 11:03:30.430776 CH1_RK1: MR19=0x606, MR18=0x4016, DQSOSC=393, MR23=63, INC=95, DEC=63
2101 11:03:30.433903 [RxdqsGatingPostProcess] freq 800
2102 11:03:30.437449 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 11:03:30.440609 Pre-setting of DQS Precalculation
2104 11:03:30.447305 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 11:03:30.453918 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 11:03:30.460728 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 11:03:30.461121
2108 11:03:30.461444
2109 11:03:30.463590 [Calibration Summary] 1600 Mbps
2110 11:03:30.463665 CH 0, Rank 0
2111 11:03:30.466912 SW Impedance : PASS
2112 11:03:30.470400 DUTY Scan : NO K
2113 11:03:30.470476 ZQ Calibration : PASS
2114 11:03:30.473609 Jitter Meter : NO K
2115 11:03:30.477253 CBT Training : PASS
2116 11:03:30.477353 Write leveling : PASS
2117 11:03:30.480717 RX DQS gating : PASS
2118 11:03:30.483886 RX DQ/DQS(RDDQC) : PASS
2119 11:03:30.483970 TX DQ/DQS : PASS
2120 11:03:30.486939 RX DATLAT : PASS
2121 11:03:30.490374 RX DQ/DQS(Engine): PASS
2122 11:03:30.490468 TX OE : NO K
2123 11:03:30.490552 All Pass.
2124 11:03:30.493718
2125 11:03:30.493793 CH 0, Rank 1
2126 11:03:30.496978 SW Impedance : PASS
2127 11:03:30.497068 DUTY Scan : NO K
2128 11:03:30.500221 ZQ Calibration : PASS
2129 11:03:30.500296 Jitter Meter : NO K
2130 11:03:30.503760 CBT Training : PASS
2131 11:03:30.507094 Write leveling : PASS
2132 11:03:30.507170 RX DQS gating : PASS
2133 11:03:30.510241 RX DQ/DQS(RDDQC) : PASS
2134 11:03:30.513919 TX DQ/DQS : PASS
2135 11:03:30.513995 RX DATLAT : PASS
2136 11:03:30.517304 RX DQ/DQS(Engine): PASS
2137 11:03:30.520818 TX OE : NO K
2138 11:03:30.520894 All Pass.
2139 11:03:30.520952
2140 11:03:30.521006 CH 1, Rank 0
2141 11:03:30.524098 SW Impedance : PASS
2142 11:03:30.527286 DUTY Scan : NO K
2143 11:03:30.527363 ZQ Calibration : PASS
2144 11:03:30.530763 Jitter Meter : NO K
2145 11:03:30.530839 CBT Training : PASS
2146 11:03:30.533968 Write leveling : PASS
2147 11:03:30.537306 RX DQS gating : PASS
2148 11:03:30.537382 RX DQ/DQS(RDDQC) : PASS
2149 11:03:30.540842 TX DQ/DQS : PASS
2150 11:03:30.543976 RX DATLAT : PASS
2151 11:03:30.544051 RX DQ/DQS(Engine): PASS
2152 11:03:30.547376 TX OE : NO K
2153 11:03:30.547452 All Pass.
2154 11:03:30.547510
2155 11:03:30.550578 CH 1, Rank 1
2156 11:03:30.550654 SW Impedance : PASS
2157 11:03:30.554048 DUTY Scan : NO K
2158 11:03:30.557180 ZQ Calibration : PASS
2159 11:03:30.557256 Jitter Meter : NO K
2160 11:03:30.560498 CBT Training : PASS
2161 11:03:30.564161 Write leveling : PASS
2162 11:03:30.564236 RX DQS gating : PASS
2163 11:03:30.567349 RX DQ/DQS(RDDQC) : PASS
2164 11:03:30.570698 TX DQ/DQS : PASS
2165 11:03:30.570770 RX DATLAT : PASS
2166 11:03:30.573936 RX DQ/DQS(Engine): PASS
2167 11:03:30.574030 TX OE : NO K
2168 11:03:30.577323 All Pass.
2169 11:03:30.577416
2170 11:03:30.577498 DramC Write-DBI off
2171 11:03:30.580528 PER_BANK_REFRESH: Hybrid Mode
2172 11:03:30.583864 TX_TRACKING: ON
2173 11:03:30.587180 [GetDramInforAfterCalByMRR] Vendor 6.
2174 11:03:30.590857 [GetDramInforAfterCalByMRR] Revision 606.
2175 11:03:30.594075 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 11:03:30.594144 MR0 0x3b3b
2177 11:03:30.594201 MR8 0x5151
2178 11:03:30.600616 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 11:03:30.600686
2180 11:03:30.600741 MR0 0x3b3b
2181 11:03:30.600813 MR8 0x5151
2182 11:03:30.603855 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 11:03:30.603920
2184 11:03:30.614176 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 11:03:30.617180 [FAST_K] Save calibration result to emmc
2186 11:03:30.620782 [FAST_K] Save calibration result to emmc
2187 11:03:30.624189 dram_init: config_dvfs: 1
2188 11:03:30.627664 dramc_set_vcore_voltage set vcore to 662500
2189 11:03:30.631060 Read voltage for 1200, 2
2190 11:03:30.631135 Vio18 = 0
2191 11:03:30.631194 Vcore = 662500
2192 11:03:30.634160 Vdram = 0
2193 11:03:30.634235 Vddq = 0
2194 11:03:30.634293 Vmddr = 0
2195 11:03:30.641247 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 11:03:30.644244 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 11:03:30.647719 MEM_TYPE=3, freq_sel=15
2198 11:03:30.651138 sv_algorithm_assistance_LP4_1600
2199 11:03:30.654691 ============ PULL DRAM RESETB DOWN ============
2200 11:03:30.657715 ========== PULL DRAM RESETB DOWN end =========
2201 11:03:30.664708 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 11:03:30.667781 ===================================
2203 11:03:30.667857 LPDDR4 DRAM CONFIGURATION
2204 11:03:30.671177 ===================================
2205 11:03:30.674393 EX_ROW_EN[0] = 0x0
2206 11:03:30.678042 EX_ROW_EN[1] = 0x0
2207 11:03:30.678118 LP4Y_EN = 0x0
2208 11:03:30.681273 WORK_FSP = 0x0
2209 11:03:30.681348 WL = 0x4
2210 11:03:30.684768 RL = 0x4
2211 11:03:30.684844 BL = 0x2
2212 11:03:30.688004 RPST = 0x0
2213 11:03:30.688080 RD_PRE = 0x0
2214 11:03:30.691285 WR_PRE = 0x1
2215 11:03:30.691355 WR_PST = 0x0
2216 11:03:30.694701 DBI_WR = 0x0
2217 11:03:30.694777 DBI_RD = 0x0
2218 11:03:30.697933 OTF = 0x1
2219 11:03:30.701201 ===================================
2220 11:03:30.704563 ===================================
2221 11:03:30.704639 ANA top config
2222 11:03:30.707884 ===================================
2223 11:03:30.711083 DLL_ASYNC_EN = 0
2224 11:03:30.714728 ALL_SLAVE_EN = 0
2225 11:03:30.714804 NEW_RANK_MODE = 1
2226 11:03:30.718055 DLL_IDLE_MODE = 1
2227 11:03:30.721310 LP45_APHY_COMB_EN = 1
2228 11:03:30.724804 TX_ODT_DIS = 1
2229 11:03:30.727845 NEW_8X_MODE = 1
2230 11:03:30.727921 ===================================
2231 11:03:30.731195 ===================================
2232 11:03:30.734655 data_rate = 2400
2233 11:03:30.738073 CKR = 1
2234 11:03:30.741023 DQ_P2S_RATIO = 8
2235 11:03:30.744506 ===================================
2236 11:03:30.747899 CA_P2S_RATIO = 8
2237 11:03:30.751370 DQ_CA_OPEN = 0
2238 11:03:30.754461 DQ_SEMI_OPEN = 0
2239 11:03:30.754537 CA_SEMI_OPEN = 0
2240 11:03:30.758009 CA_FULL_RATE = 0
2241 11:03:30.761283 DQ_CKDIV4_EN = 0
2242 11:03:30.764445 CA_CKDIV4_EN = 0
2243 11:03:30.767888 CA_PREDIV_EN = 0
2244 11:03:30.767964 PH8_DLY = 17
2245 11:03:30.771617 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 11:03:30.774923 DQ_AAMCK_DIV = 4
2247 11:03:30.778170 CA_AAMCK_DIV = 4
2248 11:03:30.781306 CA_ADMCK_DIV = 4
2249 11:03:30.784915 DQ_TRACK_CA_EN = 0
2250 11:03:30.784991 CA_PICK = 1200
2251 11:03:30.788255 CA_MCKIO = 1200
2252 11:03:30.791438 MCKIO_SEMI = 0
2253 11:03:30.794746 PLL_FREQ = 2366
2254 11:03:30.798101 DQ_UI_PI_RATIO = 32
2255 11:03:30.801574 CA_UI_PI_RATIO = 0
2256 11:03:30.804828 ===================================
2257 11:03:30.808042 ===================================
2258 11:03:30.808118 memory_type:LPDDR4
2259 11:03:30.811763 GP_NUM : 10
2260 11:03:30.815052 SRAM_EN : 1
2261 11:03:30.815128 MD32_EN : 0
2262 11:03:30.818218 ===================================
2263 11:03:30.821466 [ANA_INIT] >>>>>>>>>>>>>>
2264 11:03:30.824643 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 11:03:30.827858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 11:03:30.831461 ===================================
2267 11:03:30.834745 data_rate = 2400,PCW = 0X5b00
2268 11:03:30.838336 ===================================
2269 11:03:30.841535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 11:03:30.844748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 11:03:30.851414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 11:03:30.854959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 11:03:30.857907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 11:03:30.864768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 11:03:30.864897 [ANA_INIT] flow start
2276 11:03:30.867809 [ANA_INIT] PLL >>>>>>>>
2277 11:03:30.867885 [ANA_INIT] PLL <<<<<<<<
2278 11:03:30.871288 [ANA_INIT] MIDPI >>>>>>>>
2279 11:03:30.874517 [ANA_INIT] MIDPI <<<<<<<<
2280 11:03:30.877771 [ANA_INIT] DLL >>>>>>>>
2281 11:03:30.877846 [ANA_INIT] DLL <<<<<<<<
2282 11:03:30.881375 [ANA_INIT] flow end
2283 11:03:30.884634 ============ LP4 DIFF to SE enter ============
2284 11:03:30.887761 ============ LP4 DIFF to SE exit ============
2285 11:03:30.891079 [ANA_INIT] <<<<<<<<<<<<<
2286 11:03:30.894422 [Flow] Enable top DCM control >>>>>
2287 11:03:30.897781 [Flow] Enable top DCM control <<<<<
2288 11:03:30.901293 Enable DLL master slave shuffle
2289 11:03:30.907913 ==============================================================
2290 11:03:30.907984 Gating Mode config
2291 11:03:30.914312 ==============================================================
2292 11:03:30.914384 Config description:
2293 11:03:30.924529 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 11:03:30.931316 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 11:03:30.937706 SELPH_MODE 0: By rank 1: By Phase
2296 11:03:30.941042 ==============================================================
2297 11:03:30.944182 GAT_TRACK_EN = 1
2298 11:03:30.947681 RX_GATING_MODE = 2
2299 11:03:30.951017 RX_GATING_TRACK_MODE = 2
2300 11:03:30.954396 SELPH_MODE = 1
2301 11:03:30.957765 PICG_EARLY_EN = 1
2302 11:03:30.961288 VALID_LAT_VALUE = 1
2303 11:03:30.964520 ==============================================================
2304 11:03:30.967689 Enter into Gating configuration >>>>
2305 11:03:30.971266 Exit from Gating configuration <<<<
2306 11:03:30.974682 Enter into DVFS_PRE_config >>>>>
2307 11:03:30.987717 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 11:03:30.991506 Exit from DVFS_PRE_config <<<<<
2309 11:03:30.991583 Enter into PICG configuration >>>>
2310 11:03:30.994926 Exit from PICG configuration <<<<
2311 11:03:30.998094 [RX_INPUT] configuration >>>>>
2312 11:03:31.001279 [RX_INPUT] configuration <<<<<
2313 11:03:31.008271 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 11:03:31.011596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 11:03:31.018176 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 11:03:31.024689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 11:03:31.031302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 11:03:31.038051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 11:03:31.041293 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 11:03:31.044568 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 11:03:31.047964 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 11:03:31.054901 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 11:03:31.058018 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 11:03:31.061308 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 11:03:31.064925 ===================================
2326 11:03:31.068270 LPDDR4 DRAM CONFIGURATION
2327 11:03:31.071458 ===================================
2328 11:03:31.071533 EX_ROW_EN[0] = 0x0
2329 11:03:31.074650 EX_ROW_EN[1] = 0x0
2330 11:03:31.074726 LP4Y_EN = 0x0
2331 11:03:31.078279 WORK_FSP = 0x0
2332 11:03:31.082061 WL = 0x4
2333 11:03:31.082156 RL = 0x4
2334 11:03:31.084984 BL = 0x2
2335 11:03:31.085099 RPST = 0x0
2336 11:03:31.088243 RD_PRE = 0x0
2337 11:03:31.088333 WR_PRE = 0x1
2338 11:03:31.091472 WR_PST = 0x0
2339 11:03:31.091560 DBI_WR = 0x0
2340 11:03:31.095165 DBI_RD = 0x0
2341 11:03:31.095268 OTF = 0x1
2342 11:03:31.098267 ===================================
2343 11:03:31.101512 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 11:03:31.105271 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 11:03:31.111862 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 11:03:31.115102 ===================================
2347 11:03:31.118164 LPDDR4 DRAM CONFIGURATION
2348 11:03:31.121905 ===================================
2349 11:03:31.122011 EX_ROW_EN[0] = 0x10
2350 11:03:31.125177 EX_ROW_EN[1] = 0x0
2351 11:03:31.125247 LP4Y_EN = 0x0
2352 11:03:31.128194 WORK_FSP = 0x0
2353 11:03:31.128282 WL = 0x4
2354 11:03:31.131805 RL = 0x4
2355 11:03:31.131896 BL = 0x2
2356 11:03:31.135668 RPST = 0x0
2357 11:03:31.135763 RD_PRE = 0x0
2358 11:03:31.138368 WR_PRE = 0x1
2359 11:03:31.138470 WR_PST = 0x0
2360 11:03:31.141735 DBI_WR = 0x0
2361 11:03:31.141827 DBI_RD = 0x0
2362 11:03:31.144947 OTF = 0x1
2363 11:03:31.148712 ===================================
2364 11:03:31.155575 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 11:03:31.155707 ==
2366 11:03:31.158745 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 11:03:31.162062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 11:03:31.162164 ==
2369 11:03:31.165317 [Duty_Offset_Calibration]
2370 11:03:31.165394 B0:2 B1:0 CA:1
2371 11:03:31.165453
2372 11:03:31.168731 [DutyScan_Calibration_Flow] k_type=0
2373 11:03:31.178148
2374 11:03:31.178233 ==CLK 0==
2375 11:03:31.181772 Final CLK duty delay cell = -4
2376 11:03:31.184966 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2377 11:03:31.188408 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2378 11:03:31.191583 [-4] AVG Duty = 4953%(X100)
2379 11:03:31.191659
2380 11:03:31.195346 CH0 CLK Duty spec in!! Max-Min= 156%
2381 11:03:31.198077 [DutyScan_Calibration_Flow] ====Done====
2382 11:03:31.198153
2383 11:03:31.201397 [DutyScan_Calibration_Flow] k_type=1
2384 11:03:31.217356
2385 11:03:31.217434 ==DQS 0 ==
2386 11:03:31.220604 Final DQS duty delay cell = 0
2387 11:03:31.223855 [0] MAX Duty = 5187%(X100), DQS PI = 30
2388 11:03:31.227128 [0] MIN Duty = 4938%(X100), DQS PI = 0
2389 11:03:31.227205 [0] AVG Duty = 5062%(X100)
2390 11:03:31.230443
2391 11:03:31.230519 ==DQS 1 ==
2392 11:03:31.233582 Final DQS duty delay cell = -4
2393 11:03:31.236923 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2394 11:03:31.240712 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2395 11:03:31.243747 [-4] AVG Duty = 5015%(X100)
2396 11:03:31.243823
2397 11:03:31.247270 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2398 11:03:31.247347
2399 11:03:31.250526 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2400 11:03:31.253854 [DutyScan_Calibration_Flow] ====Done====
2401 11:03:31.253985
2402 11:03:31.257056 [DutyScan_Calibration_Flow] k_type=3
2403 11:03:31.273803
2404 11:03:31.273957 ==DQM 0 ==
2405 11:03:31.276877 Final DQM duty delay cell = 0
2406 11:03:31.280417 [0] MAX Duty = 5062%(X100), DQS PI = 24
2407 11:03:31.283607 [0] MIN Duty = 4813%(X100), DQS PI = 0
2408 11:03:31.283711 [0] AVG Duty = 4937%(X100)
2409 11:03:31.287189
2410 11:03:31.287297 ==DQM 1 ==
2411 11:03:31.290453 Final DQM duty delay cell = 0
2412 11:03:31.293925 [0] MAX Duty = 5187%(X100), DQS PI = 48
2413 11:03:31.297475 [0] MIN Duty = 5000%(X100), DQS PI = 12
2414 11:03:31.297576 [0] AVG Duty = 5093%(X100)
2415 11:03:31.300704
2416 11:03:31.303677 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2417 11:03:31.303790
2418 11:03:31.307218 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2419 11:03:31.310328 [DutyScan_Calibration_Flow] ====Done====
2420 11:03:31.310427
2421 11:03:31.313841 [DutyScan_Calibration_Flow] k_type=2
2422 11:03:31.330380
2423 11:03:31.330511 ==DQ 0 ==
2424 11:03:31.333522 Final DQ duty delay cell = -4
2425 11:03:31.336904 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2426 11:03:31.340087 [-4] MIN Duty = 4844%(X100), DQS PI = 16
2427 11:03:31.343346 [-4] AVG Duty = 4937%(X100)
2428 11:03:31.343480
2429 11:03:31.343584 ==DQ 1 ==
2430 11:03:31.347063 Final DQ duty delay cell = 4
2431 11:03:31.350324 [4] MAX Duty = 5093%(X100), DQS PI = 6
2432 11:03:31.353616 [4] MIN Duty = 5031%(X100), DQS PI = 0
2433 11:03:31.353731 [4] AVG Duty = 5062%(X100)
2434 11:03:31.357007
2435 11:03:31.360289 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2436 11:03:31.360435
2437 11:03:31.363921 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2438 11:03:31.367054 [DutyScan_Calibration_Flow] ====Done====
2439 11:03:31.367174 ==
2440 11:03:31.370375 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 11:03:31.373641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 11:03:31.373750 ==
2443 11:03:31.377262 [Duty_Offset_Calibration]
2444 11:03:31.377406 B0:0 B1:-1 CA:2
2445 11:03:31.377510
2446 11:03:31.380020 [DutyScan_Calibration_Flow] k_type=0
2447 11:03:31.390475
2448 11:03:31.390651 ==CLK 0==
2449 11:03:31.393593 Final CLK duty delay cell = 0
2450 11:03:31.396921 [0] MAX Duty = 5156%(X100), DQS PI = 16
2451 11:03:31.400489 [0] MIN Duty = 4938%(X100), DQS PI = 44
2452 11:03:31.400579 [0] AVG Duty = 5047%(X100)
2453 11:03:31.400656
2454 11:03:31.404079 CH1 CLK Duty spec in!! Max-Min= 218%
2455 11:03:31.410648 [DutyScan_Calibration_Flow] ====Done====
2456 11:03:31.410782
2457 11:03:31.413448 [DutyScan_Calibration_Flow] k_type=1
2458 11:03:31.429731
2459 11:03:31.429905 ==DQS 0 ==
2460 11:03:31.433466 Final DQS duty delay cell = 0
2461 11:03:31.436334 [0] MAX Duty = 5093%(X100), DQS PI = 24
2462 11:03:31.440009 [0] MIN Duty = 4969%(X100), DQS PI = 0
2463 11:03:31.440086 [0] AVG Duty = 5031%(X100)
2464 11:03:31.443281
2465 11:03:31.443357 ==DQS 1 ==
2466 11:03:31.446496 Final DQS duty delay cell = 0
2467 11:03:31.449667 [0] MAX Duty = 5156%(X100), DQS PI = 0
2468 11:03:31.452999 [0] MIN Duty = 4875%(X100), DQS PI = 34
2469 11:03:31.456147 [0] AVG Duty = 5015%(X100)
2470 11:03:31.456229
2471 11:03:31.459513 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2472 11:03:31.459653
2473 11:03:31.462744 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2474 11:03:31.466440 [DutyScan_Calibration_Flow] ====Done====
2475 11:03:31.466516
2476 11:03:31.469549 [DutyScan_Calibration_Flow] k_type=3
2477 11:03:31.486241
2478 11:03:31.486346 ==DQM 0 ==
2479 11:03:31.489486 Final DQM duty delay cell = 4
2480 11:03:31.492997 [4] MAX Duty = 5093%(X100), DQS PI = 20
2481 11:03:31.496514 [4] MIN Duty = 4938%(X100), DQS PI = 44
2482 11:03:31.496606 [4] AVG Duty = 5015%(X100)
2483 11:03:31.499511
2484 11:03:31.499586 ==DQM 1 ==
2485 11:03:31.502915 Final DQM duty delay cell = -4
2486 11:03:31.506452 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2487 11:03:31.509692 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2488 11:03:31.512982 [-4] AVG Duty = 4891%(X100)
2489 11:03:31.513058
2490 11:03:31.516355 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2491 11:03:31.516430
2492 11:03:31.519635 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2493 11:03:31.522916 [DutyScan_Calibration_Flow] ====Done====
2494 11:03:31.523006
2495 11:03:31.526185 [DutyScan_Calibration_Flow] k_type=2
2496 11:03:31.543303
2497 11:03:31.543380 ==DQ 0 ==
2498 11:03:31.546845 Final DQ duty delay cell = 0
2499 11:03:31.550198 [0] MAX Duty = 5062%(X100), DQS PI = 20
2500 11:03:31.552984 [0] MIN Duty = 4938%(X100), DQS PI = 0
2501 11:03:31.553060 [0] AVG Duty = 5000%(X100)
2502 11:03:31.553119
2503 11:03:31.556744 ==DQ 1 ==
2504 11:03:31.559963 Final DQ duty delay cell = 0
2505 11:03:31.563216 [0] MAX Duty = 5031%(X100), DQS PI = 2
2506 11:03:31.566488 [0] MIN Duty = 4813%(X100), DQS PI = 34
2507 11:03:31.566564 [0] AVG Duty = 4922%(X100)
2508 11:03:31.566624
2509 11:03:31.569889 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2510 11:03:31.569965
2511 11:03:31.573234 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2512 11:03:31.580022 [DutyScan_Calibration_Flow] ====Done====
2513 11:03:31.583280 nWR fixed to 30
2514 11:03:31.583357 [ModeRegInit_LP4] CH0 RK0
2515 11:03:31.586531 [ModeRegInit_LP4] CH0 RK1
2516 11:03:31.590100 [ModeRegInit_LP4] CH1 RK0
2517 11:03:31.590191 [ModeRegInit_LP4] CH1 RK1
2518 11:03:31.593354 match AC timing 7
2519 11:03:31.596583 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 11:03:31.600178 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 11:03:31.606531 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 11:03:31.609917 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 11:03:31.616689 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 11:03:31.616784 ==
2525 11:03:31.619875 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 11:03:31.623118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 11:03:31.623214 ==
2528 11:03:31.630050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 11:03:31.633431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 11:03:31.642982 [CA 0] Center 38 (7~69) winsize 63
2531 11:03:31.646172 [CA 1] Center 38 (7~69) winsize 63
2532 11:03:31.649611 [CA 2] Center 34 (4~65) winsize 62
2533 11:03:31.652859 [CA 3] Center 34 (4~65) winsize 62
2534 11:03:31.656273 [CA 4] Center 33 (3~64) winsize 62
2535 11:03:31.660061 [CA 5] Center 33 (3~63) winsize 61
2536 11:03:31.660160
2537 11:03:31.663247 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2538 11:03:31.663325
2539 11:03:31.666521 [CATrainingPosCal] consider 1 rank data
2540 11:03:31.669760 u2DelayCellTimex100 = 270/100 ps
2541 11:03:31.673454 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2542 11:03:31.676699 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2543 11:03:31.679963 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
2544 11:03:31.686482 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2545 11:03:31.690263 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2546 11:03:31.693164 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 11:03:31.693242
2548 11:03:31.696440 CA PerBit enable=1, Macro0, CA PI delay=33
2549 11:03:31.696517
2550 11:03:31.699856 [CBTSetCACLKResult] CA Dly = 33
2551 11:03:31.699934 CS Dly: 5 (0~36)
2552 11:03:31.699993 ==
2553 11:03:31.703364 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 11:03:31.710209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 11:03:31.710288 ==
2556 11:03:31.713595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 11:03:31.720056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2558 11:03:31.728442 [CA 0] Center 38 (7~69) winsize 63
2559 11:03:31.732126 [CA 1] Center 38 (8~69) winsize 62
2560 11:03:31.735492 [CA 2] Center 35 (5~66) winsize 62
2561 11:03:31.738453 [CA 3] Center 35 (4~66) winsize 63
2562 11:03:31.742155 [CA 4] Center 34 (3~65) winsize 63
2563 11:03:31.745441 [CA 5] Center 33 (3~64) winsize 62
2564 11:03:31.745518
2565 11:03:31.748654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2566 11:03:31.748742
2567 11:03:31.751919 [CATrainingPosCal] consider 2 rank data
2568 11:03:31.755218 u2DelayCellTimex100 = 270/100 ps
2569 11:03:31.758887 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2570 11:03:31.761964 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2571 11:03:31.768961 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2572 11:03:31.772030 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2573 11:03:31.775199 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2574 11:03:31.778836 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2575 11:03:31.778912
2576 11:03:31.782104 CA PerBit enable=1, Macro0, CA PI delay=33
2577 11:03:31.782180
2578 11:03:31.785491 [CBTSetCACLKResult] CA Dly = 33
2579 11:03:31.785568 CS Dly: 6 (0~39)
2580 11:03:31.785626
2581 11:03:31.788655 ----->DramcWriteLeveling(PI) begin...
2582 11:03:31.788731 ==
2583 11:03:31.792041 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 11:03:31.798924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 11:03:31.799000 ==
2586 11:03:31.802041 Write leveling (Byte 0): 31 => 31
2587 11:03:31.805369 Write leveling (Byte 1): 31 => 31
2588 11:03:31.805445 DramcWriteLeveling(PI) end<-----
2589 11:03:31.805504
2590 11:03:31.808820 ==
2591 11:03:31.812157 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 11:03:31.815705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 11:03:31.815783 ==
2594 11:03:31.818967 [Gating] SW mode calibration
2595 11:03:31.825716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 11:03:31.829028 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 11:03:31.835669 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2598 11:03:31.838972 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2599 11:03:31.842207 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 11:03:31.849051 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 11:03:31.852348 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 11:03:31.855605 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 11:03:31.862633 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2604 11:03:31.866008 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2605 11:03:31.869293 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2606 11:03:31.872514 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 11:03:31.879127 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 11:03:31.882446 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 11:03:31.885624 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 11:03:31.892266 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 11:03:31.895536 1 0 24 | B1->B0 | 2323 3736 | 0 1 | (0 0) (0 0)
2612 11:03:31.899149 1 0 28 | B1->B0 | 2b2a 4646 | 1 0 | (0 0) (0 0)
2613 11:03:31.905763 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2614 11:03:31.909502 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 11:03:31.912473 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 11:03:31.919365 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 11:03:31.922637 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 11:03:31.925628 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 11:03:31.932869 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 11:03:31.935912 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2621 11:03:31.939426 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 11:03:31.945896 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2623 11:03:31.949249 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:03:31.952532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:03:31.955835 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:03:31.962550 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:03:31.965691 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:03:31.969357 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:03:31.975999 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:03:31.979335 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:03:31.982607 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:03:31.989328 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:03:31.992834 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:03:31.995903 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:03:32.002979 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:03:32.006130 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 11:03:32.009421 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 11:03:32.012770 Total UI for P1: 0, mck2ui 16
2639 11:03:32.016358 best dqsien dly found for B0: ( 1, 3, 28)
2640 11:03:32.019838 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 11:03:32.022993 Total UI for P1: 0, mck2ui 16
2642 11:03:32.026287 best dqsien dly found for B1: ( 1, 4, 0)
2643 11:03:32.029485 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2644 11:03:32.036105 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2645 11:03:32.036214
2646 11:03:32.039610 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2647 11:03:32.042973 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2648 11:03:32.046022 [Gating] SW calibration Done
2649 11:03:32.046116 ==
2650 11:03:32.049495 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 11:03:32.052841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 11:03:32.052948 ==
2653 11:03:32.053046 RX Vref Scan: 0
2654 11:03:32.053145
2655 11:03:32.056314 RX Vref 0 -> 0, step: 1
2656 11:03:32.056400
2657 11:03:32.059610 RX Delay -40 -> 252, step: 8
2658 11:03:32.062988 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2659 11:03:32.066390 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2660 11:03:32.073203 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2661 11:03:32.076419 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2662 11:03:32.079665 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2663 11:03:32.082930 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2664 11:03:32.086222 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2665 11:03:32.089926 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2666 11:03:32.096459 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2667 11:03:32.099610 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2668 11:03:32.103117 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2669 11:03:32.106209 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2670 11:03:32.109628 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2671 11:03:32.116267 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2672 11:03:32.119829 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2673 11:03:32.123057 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2674 11:03:32.123149 ==
2675 11:03:32.126472 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 11:03:32.129702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 11:03:32.129799 ==
2678 11:03:32.133337 DQS Delay:
2679 11:03:32.133431 DQS0 = 0, DQS1 = 0
2680 11:03:32.136526 DQM Delay:
2681 11:03:32.136620 DQM0 = 122, DQM1 = 110
2682 11:03:32.139588 DQ Delay:
2683 11:03:32.142938 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2684 11:03:32.146543 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2685 11:03:32.149610 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2686 11:03:32.152881 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2687 11:03:32.152973
2688 11:03:32.153058
2689 11:03:32.153165 ==
2690 11:03:32.156313 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 11:03:32.159863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 11:03:32.159961 ==
2693 11:03:32.160049
2694 11:03:32.160133
2695 11:03:32.162992 TX Vref Scan disable
2696 11:03:32.166423 == TX Byte 0 ==
2697 11:03:32.170042 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2698 11:03:32.173044 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2699 11:03:32.176666 == TX Byte 1 ==
2700 11:03:32.179829 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2701 11:03:32.183209 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2702 11:03:32.183302 ==
2703 11:03:32.186480 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 11:03:32.189804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 11:03:32.189874 ==
2706 11:03:32.202470 TX Vref=22, minBit 1, minWin=24, winSum=401
2707 11:03:32.205694 TX Vref=24, minBit 0, minWin=24, winSum=408
2708 11:03:32.209491 TX Vref=26, minBit 4, minWin=24, winSum=416
2709 11:03:32.212552 TX Vref=28, minBit 0, minWin=25, winSum=417
2710 11:03:32.215975 TX Vref=30, minBit 0, minWin=26, winSum=421
2711 11:03:32.219096 TX Vref=32, minBit 0, minWin=25, winSum=414
2712 11:03:32.226548 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 30
2713 11:03:32.226629
2714 11:03:32.229121 Final TX Range 1 Vref 30
2715 11:03:32.229226
2716 11:03:32.229286 ==
2717 11:03:32.232910 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 11:03:32.236254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 11:03:32.236463 ==
2720 11:03:32.236572
2721 11:03:32.239294
2722 11:03:32.239425 TX Vref Scan disable
2723 11:03:32.242531 == TX Byte 0 ==
2724 11:03:32.245776 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2725 11:03:32.249100 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2726 11:03:32.252445 == TX Byte 1 ==
2727 11:03:32.256160 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2728 11:03:32.259406 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2729 11:03:32.259503
2730 11:03:32.262548 [DATLAT]
2731 11:03:32.262641 Freq=1200, CH0 RK0
2732 11:03:32.262730
2733 11:03:32.266163 DATLAT Default: 0xd
2734 11:03:32.266255 0, 0xFFFF, sum = 0
2735 11:03:32.269267 1, 0xFFFF, sum = 0
2736 11:03:32.269367 2, 0xFFFF, sum = 0
2737 11:03:32.272834 3, 0xFFFF, sum = 0
2738 11:03:32.272929 4, 0xFFFF, sum = 0
2739 11:03:32.276274 5, 0xFFFF, sum = 0
2740 11:03:32.276358 6, 0xFFFF, sum = 0
2741 11:03:32.279440 7, 0xFFFF, sum = 0
2742 11:03:32.279553 8, 0xFFFF, sum = 0
2743 11:03:32.282946 9, 0xFFFF, sum = 0
2744 11:03:32.283043 10, 0xFFFF, sum = 0
2745 11:03:32.286343 11, 0xFFFF, sum = 0
2746 11:03:32.286448 12, 0x0, sum = 1
2747 11:03:32.289760 13, 0x0, sum = 2
2748 11:03:32.289853 14, 0x0, sum = 3
2749 11:03:32.292965 15, 0x0, sum = 4
2750 11:03:32.293058 best_step = 13
2751 11:03:32.293164
2752 11:03:32.293261 ==
2753 11:03:32.296239 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 11:03:32.302836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 11:03:32.302914 ==
2756 11:03:32.303003 RX Vref Scan: 1
2757 11:03:32.303084
2758 11:03:32.306093 Set Vref Range= 32 -> 127
2759 11:03:32.306161
2760 11:03:32.310028 RX Vref 32 -> 127, step: 1
2761 11:03:32.310098
2762 11:03:32.310154 RX Delay -13 -> 252, step: 4
2763 11:03:32.313516
2764 11:03:32.313611 Set Vref, RX VrefLevel [Byte0]: 32
2765 11:03:32.316323 [Byte1]: 32
2766 11:03:32.320973
2767 11:03:32.321070 Set Vref, RX VrefLevel [Byte0]: 33
2768 11:03:32.324135 [Byte1]: 33
2769 11:03:32.328849
2770 11:03:32.328943 Set Vref, RX VrefLevel [Byte0]: 34
2771 11:03:32.332089 [Byte1]: 34
2772 11:03:32.336628
2773 11:03:32.336730 Set Vref, RX VrefLevel [Byte0]: 35
2774 11:03:32.339745 [Byte1]: 35
2775 11:03:32.344429
2776 11:03:32.344524 Set Vref, RX VrefLevel [Byte0]: 36
2777 11:03:32.347660 [Byte1]: 36
2778 11:03:32.352476
2779 11:03:32.352576 Set Vref, RX VrefLevel [Byte0]: 37
2780 11:03:32.355658 [Byte1]: 37
2781 11:03:32.360250
2782 11:03:32.360351 Set Vref, RX VrefLevel [Byte0]: 38
2783 11:03:32.363556 [Byte1]: 38
2784 11:03:32.367990
2785 11:03:32.368084 Set Vref, RX VrefLevel [Byte0]: 39
2786 11:03:32.374645 [Byte1]: 39
2787 11:03:32.374734
2788 11:03:32.377710 Set Vref, RX VrefLevel [Byte0]: 40
2789 11:03:32.381310 [Byte1]: 40
2790 11:03:32.381410
2791 11:03:32.384738 Set Vref, RX VrefLevel [Byte0]: 41
2792 11:03:32.387979 [Byte1]: 41
2793 11:03:32.391759
2794 11:03:32.391854 Set Vref, RX VrefLevel [Byte0]: 42
2795 11:03:32.394996 [Byte1]: 42
2796 11:03:32.399724
2797 11:03:32.399817 Set Vref, RX VrefLevel [Byte0]: 43
2798 11:03:32.402941 [Byte1]: 43
2799 11:03:32.407635
2800 11:03:32.407713 Set Vref, RX VrefLevel [Byte0]: 44
2801 11:03:32.411036 [Byte1]: 44
2802 11:03:32.415617
2803 11:03:32.415719 Set Vref, RX VrefLevel [Byte0]: 45
2804 11:03:32.418934 [Byte1]: 45
2805 11:03:32.423564
2806 11:03:32.423631 Set Vref, RX VrefLevel [Byte0]: 46
2807 11:03:32.426767 [Byte1]: 46
2808 11:03:32.431487
2809 11:03:32.431577 Set Vref, RX VrefLevel [Byte0]: 47
2810 11:03:32.434660 [Byte1]: 47
2811 11:03:32.439157
2812 11:03:32.439251 Set Vref, RX VrefLevel [Byte0]: 48
2813 11:03:32.442628 [Byte1]: 48
2814 11:03:32.447153
2815 11:03:32.447231 Set Vref, RX VrefLevel [Byte0]: 49
2816 11:03:32.450205 [Byte1]: 49
2817 11:03:32.455238
2818 11:03:32.455313 Set Vref, RX VrefLevel [Byte0]: 50
2819 11:03:32.458468 [Byte1]: 50
2820 11:03:32.463000
2821 11:03:32.463076 Set Vref, RX VrefLevel [Byte0]: 51
2822 11:03:32.466267 [Byte1]: 51
2823 11:03:32.470802
2824 11:03:32.470896 Set Vref, RX VrefLevel [Byte0]: 52
2825 11:03:32.474111 [Byte1]: 52
2826 11:03:32.478445
2827 11:03:32.478544 Set Vref, RX VrefLevel [Byte0]: 53
2828 11:03:32.481795 [Byte1]: 53
2829 11:03:32.486415
2830 11:03:32.486517 Set Vref, RX VrefLevel [Byte0]: 54
2831 11:03:32.489934 [Byte1]: 54
2832 11:03:32.494391
2833 11:03:32.494494 Set Vref, RX VrefLevel [Byte0]: 55
2834 11:03:32.497672 [Byte1]: 55
2835 11:03:32.502241
2836 11:03:32.502338 Set Vref, RX VrefLevel [Byte0]: 56
2837 11:03:32.505623 [Byte1]: 56
2838 11:03:32.510388
2839 11:03:32.510489 Set Vref, RX VrefLevel [Byte0]: 57
2840 11:03:32.513702 [Byte1]: 57
2841 11:03:32.518242
2842 11:03:32.518336 Set Vref, RX VrefLevel [Byte0]: 58
2843 11:03:32.521560 [Byte1]: 58
2844 11:03:32.526158
2845 11:03:32.526247 Set Vref, RX VrefLevel [Byte0]: 59
2846 11:03:32.529454 [Byte1]: 59
2847 11:03:32.534052
2848 11:03:32.534141 Set Vref, RX VrefLevel [Byte0]: 60
2849 11:03:32.536958 [Byte1]: 60
2850 11:03:32.541546
2851 11:03:32.541636 Set Vref, RX VrefLevel [Byte0]: 61
2852 11:03:32.545111 [Byte1]: 61
2853 11:03:32.549748
2854 11:03:32.549837 Set Vref, RX VrefLevel [Byte0]: 62
2855 11:03:32.552926 [Byte1]: 62
2856 11:03:32.557557
2857 11:03:32.557640 Set Vref, RX VrefLevel [Byte0]: 63
2858 11:03:32.560724 [Byte1]: 63
2859 11:03:32.565435
2860 11:03:32.565509 Set Vref, RX VrefLevel [Byte0]: 64
2861 11:03:32.568669 [Byte1]: 64
2862 11:03:32.573097
2863 11:03:32.573200 Set Vref, RX VrefLevel [Byte0]: 65
2864 11:03:32.576343 [Byte1]: 65
2865 11:03:32.581390
2866 11:03:32.581492 Set Vref, RX VrefLevel [Byte0]: 66
2867 11:03:32.584533 [Byte1]: 66
2868 11:03:32.588978
2869 11:03:32.589071 Set Vref, RX VrefLevel [Byte0]: 67
2870 11:03:32.592219 [Byte1]: 67
2871 11:03:32.597053
2872 11:03:32.597168 Set Vref, RX VrefLevel [Byte0]: 68
2873 11:03:32.600424 [Byte1]: 68
2874 11:03:32.604996
2875 11:03:32.605096 Set Vref, RX VrefLevel [Byte0]: 69
2876 11:03:32.608324 [Byte1]: 69
2877 11:03:32.612901
2878 11:03:32.612976 Set Vref, RX VrefLevel [Byte0]: 70
2879 11:03:32.616065 [Byte1]: 70
2880 11:03:32.620503
2881 11:03:32.620578 Final RX Vref Byte 0 = 58 to rank0
2882 11:03:32.624094 Final RX Vref Byte 1 = 49 to rank0
2883 11:03:32.627301 Final RX Vref Byte 0 = 58 to rank1
2884 11:03:32.630556 Final RX Vref Byte 1 = 49 to rank1==
2885 11:03:32.634138 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 11:03:32.640959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 11:03:32.641049 ==
2888 11:03:32.641108 DQS Delay:
2889 11:03:32.641218 DQS0 = 0, DQS1 = 0
2890 11:03:32.644069 DQM Delay:
2891 11:03:32.644144 DQM0 = 122, DQM1 = 109
2892 11:03:32.647272 DQ Delay:
2893 11:03:32.651000 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2894 11:03:32.654178 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2895 11:03:32.657704 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2896 11:03:32.661002 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2897 11:03:32.661077
2898 11:03:32.661174
2899 11:03:32.667321 [DQSOSCAuto] RK0, (LSB)MR18= 0xd09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2900 11:03:32.670680 CH0 RK0: MR19=404, MR18=D09
2901 11:03:32.677660 CH0_RK0: MR19=0x404, MR18=0xD09, DQSOSC=405, MR23=63, INC=39, DEC=26
2902 11:03:32.677735
2903 11:03:32.680785 ----->DramcWriteLeveling(PI) begin...
2904 11:03:32.680902 ==
2905 11:03:32.683973 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 11:03:32.687227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 11:03:32.687322 ==
2908 11:03:32.691044 Write leveling (Byte 0): 36 => 36
2909 11:03:32.694662 Write leveling (Byte 1): 30 => 30
2910 11:03:32.697825 DramcWriteLeveling(PI) end<-----
2911 11:03:32.697915
2912 11:03:32.697998 ==
2913 11:03:32.700994 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 11:03:32.704229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 11:03:32.707699 ==
2916 11:03:32.707794 [Gating] SW mode calibration
2917 11:03:32.714210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 11:03:32.721036 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 11:03:32.724340 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2920 11:03:32.730825 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 11:03:32.734605 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 11:03:32.737714 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 11:03:32.741363 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 11:03:32.747776 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 11:03:32.751517 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2926 11:03:32.754538 0 15 28 | B1->B0 | 2e2e 2b2b | 1 0 | (1 0) (0 0)
2927 11:03:32.761055 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 11:03:32.764917 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 11:03:32.768172 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 11:03:32.774585 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 11:03:32.778042 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 11:03:32.781339 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 11:03:32.788114 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2934 11:03:32.791470 1 0 28 | B1->B0 | 3e3e 4141 | 0 1 | (0 0) (0 0)
2935 11:03:32.794667 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 11:03:32.801509 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 11:03:32.804844 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 11:03:32.807929 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 11:03:32.814795 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 11:03:32.818083 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 11:03:32.821302 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 11:03:32.824987 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2943 11:03:32.831319 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 11:03:32.834914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 11:03:32.838263 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 11:03:32.845008 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 11:03:32.848297 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 11:03:32.851542 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 11:03:32.858217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 11:03:32.861748 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:03:32.865025 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:03:32.871651 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:03:32.875011 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:03:32.878268 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:03:32.884747 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:03:32.888041 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:03:32.891388 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:03:32.895154 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2959 11:03:32.901783 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 11:03:32.905142 Total UI for P1: 0, mck2ui 16
2961 11:03:32.908371 best dqsien dly found for B0: ( 1, 3, 28)
2962 11:03:32.911552 Total UI for P1: 0, mck2ui 16
2963 11:03:32.915003 best dqsien dly found for B1: ( 1, 3, 28)
2964 11:03:32.918340 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2965 11:03:32.921885 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2966 11:03:32.921973
2967 11:03:32.924934 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2968 11:03:32.928542 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2969 11:03:32.931730 [Gating] SW calibration Done
2970 11:03:32.931833 ==
2971 11:03:32.934956 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 11:03:32.938199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 11:03:32.938309 ==
2974 11:03:32.941706 RX Vref Scan: 0
2975 11:03:32.941799
2976 11:03:32.941885 RX Vref 0 -> 0, step: 1
2977 11:03:32.941967
2978 11:03:32.945021 RX Delay -40 -> 252, step: 8
2979 11:03:32.948644 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2980 11:03:32.955070 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2981 11:03:32.958574 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2982 11:03:32.961934 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2983 11:03:32.965206 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2984 11:03:32.968505 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2985 11:03:32.974978 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2986 11:03:32.978641 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2987 11:03:32.981884 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2988 11:03:32.985012 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2989 11:03:32.988505 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2990 11:03:32.995303 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2991 11:03:32.998585 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2992 11:03:33.002132 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2993 11:03:33.005534 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2994 11:03:33.008483 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2995 11:03:33.011928 ==
2996 11:03:33.012018 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 11:03:33.018322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 11:03:33.018416 ==
2999 11:03:33.018502 DQS Delay:
3000 11:03:33.021974 DQS0 = 0, DQS1 = 0
3001 11:03:33.022062 DQM Delay:
3002 11:03:33.025243 DQM0 = 120, DQM1 = 108
3003 11:03:33.025332 DQ Delay:
3004 11:03:33.028429 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3005 11:03:33.031939 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3006 11:03:33.035154 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3007 11:03:33.038816 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3008 11:03:33.038896
3009 11:03:33.038955
3010 11:03:33.039008 ==
3011 11:03:33.041766 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 11:03:33.045572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 11:03:33.048653 ==
3014 11:03:33.048730
3015 11:03:33.048788
3016 11:03:33.048842 TX Vref Scan disable
3017 11:03:33.052001 == TX Byte 0 ==
3018 11:03:33.055252 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3019 11:03:33.058708 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3020 11:03:33.062146 == TX Byte 1 ==
3021 11:03:33.065381 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3022 11:03:33.068759 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3023 11:03:33.072046 ==
3024 11:03:33.072121 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 11:03:33.078756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 11:03:33.078832 ==
3027 11:03:33.090287 TX Vref=22, minBit 1, minWin=24, winSum=407
3028 11:03:33.093568 TX Vref=24, minBit 3, minWin=24, winSum=410
3029 11:03:33.096857 TX Vref=26, minBit 4, minWin=25, winSum=419
3030 11:03:33.100040 TX Vref=28, minBit 2, minWin=25, winSum=421
3031 11:03:33.103416 TX Vref=30, minBit 5, minWin=25, winSum=430
3032 11:03:33.106958 TX Vref=32, minBit 4, minWin=25, winSum=425
3033 11:03:33.113618 [TxChooseVref] Worse bit 5, Min win 25, Win sum 430, Final Vref 30
3034 11:03:33.113694
3035 11:03:33.116795 Final TX Range 1 Vref 30
3036 11:03:33.116870
3037 11:03:33.116927 ==
3038 11:03:33.120241 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 11:03:33.123347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 11:03:33.123437 ==
3041 11:03:33.123496
3042 11:03:33.123549
3043 11:03:33.127001 TX Vref Scan disable
3044 11:03:33.130140 == TX Byte 0 ==
3045 11:03:33.133738 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3046 11:03:33.137011 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3047 11:03:33.140510 == TX Byte 1 ==
3048 11:03:33.143915 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3049 11:03:33.147236 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3050 11:03:33.147311
3051 11:03:33.150356 [DATLAT]
3052 11:03:33.150431 Freq=1200, CH0 RK1
3053 11:03:33.150489
3054 11:03:33.153981 DATLAT Default: 0xd
3055 11:03:33.154060 0, 0xFFFF, sum = 0
3056 11:03:33.156967 1, 0xFFFF, sum = 0
3057 11:03:33.157043 2, 0xFFFF, sum = 0
3058 11:03:33.160581 3, 0xFFFF, sum = 0
3059 11:03:33.160659 4, 0xFFFF, sum = 0
3060 11:03:33.164031 5, 0xFFFF, sum = 0
3061 11:03:33.164107 6, 0xFFFF, sum = 0
3062 11:03:33.167718 7, 0xFFFF, sum = 0
3063 11:03:33.167799 8, 0xFFFF, sum = 0
3064 11:03:33.170812 9, 0xFFFF, sum = 0
3065 11:03:33.170887 10, 0xFFFF, sum = 0
3066 11:03:33.174036 11, 0xFFFF, sum = 0
3067 11:03:33.174112 12, 0x0, sum = 1
3068 11:03:33.177400 13, 0x0, sum = 2
3069 11:03:33.177477 14, 0x0, sum = 3
3070 11:03:33.180578 15, 0x0, sum = 4
3071 11:03:33.180654 best_step = 13
3072 11:03:33.180712
3073 11:03:33.180765 ==
3074 11:03:33.183848 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 11:03:33.190912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 11:03:33.190990 ==
3077 11:03:33.191048 RX Vref Scan: 0
3078 11:03:33.191101
3079 11:03:33.194055 RX Vref 0 -> 0, step: 1
3080 11:03:33.194131
3081 11:03:33.197333 RX Delay -21 -> 252, step: 4
3082 11:03:33.200702 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3083 11:03:33.203875 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3084 11:03:33.207232 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3085 11:03:33.214077 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3086 11:03:33.217281 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3087 11:03:33.220958 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3088 11:03:33.224051 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3089 11:03:33.227651 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3090 11:03:33.233819 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3091 11:03:33.237494 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3092 11:03:33.240660 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3093 11:03:33.243967 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3094 11:03:33.247512 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3095 11:03:33.253900 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3096 11:03:33.257508 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3097 11:03:33.260550 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3098 11:03:33.260670 ==
3099 11:03:33.263836 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 11:03:33.267634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 11:03:33.267734 ==
3102 11:03:33.270459 DQS Delay:
3103 11:03:33.270558 DQS0 = 0, DQS1 = 0
3104 11:03:33.273723 DQM Delay:
3105 11:03:33.273869 DQM0 = 119, DQM1 = 107
3106 11:03:33.273952 DQ Delay:
3107 11:03:33.280778 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3108 11:03:33.284007 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3109 11:03:33.287250 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3110 11:03:33.290575 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3111 11:03:33.290675
3112 11:03:33.290760
3113 11:03:33.297720 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3114 11:03:33.300754 CH0 RK1: MR19=403, MR18=11F8
3115 11:03:33.307384 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3116 11:03:33.310940 [RxdqsGatingPostProcess] freq 1200
3117 11:03:33.314142 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3118 11:03:33.317303 best DQS0 dly(2T, 0.5T) = (0, 11)
3119 11:03:33.320677 best DQS1 dly(2T, 0.5T) = (0, 12)
3120 11:03:33.323980 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3121 11:03:33.327626 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3122 11:03:33.330862 best DQS0 dly(2T, 0.5T) = (0, 11)
3123 11:03:33.334256 best DQS1 dly(2T, 0.5T) = (0, 11)
3124 11:03:33.337316 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3125 11:03:33.340809 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3126 11:03:33.343985 Pre-setting of DQS Precalculation
3127 11:03:33.347278 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3128 11:03:33.347370 ==
3129 11:03:33.350805 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 11:03:33.357513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:03:33.357591 ==
3132 11:03:33.360747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 11:03:33.367527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3134 11:03:33.375948 [CA 0] Center 37 (7~67) winsize 61
3135 11:03:33.379545 [CA 1] Center 37 (7~68) winsize 62
3136 11:03:33.382651 [CA 2] Center 35 (5~65) winsize 61
3137 11:03:33.386220 [CA 3] Center 33 (3~64) winsize 62
3138 11:03:33.389281 [CA 4] Center 33 (3~64) winsize 62
3139 11:03:33.392883 [CA 5] Center 33 (3~64) winsize 62
3140 11:03:33.392987
3141 11:03:33.396115 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3142 11:03:33.396203
3143 11:03:33.399332 [CATrainingPosCal] consider 1 rank data
3144 11:03:33.402618 u2DelayCellTimex100 = 270/100 ps
3145 11:03:33.405854 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3146 11:03:33.409597 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 11:03:33.416041 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3148 11:03:33.419253 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3149 11:03:33.422541 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 11:03:33.425911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3151 11:03:33.425992
3152 11:03:33.429002 CA PerBit enable=1, Macro0, CA PI delay=33
3153 11:03:33.429101
3154 11:03:33.432904 [CBTSetCACLKResult] CA Dly = 33
3155 11:03:33.432981 CS Dly: 5 (0~36)
3156 11:03:33.435894 ==
3157 11:03:33.436002 Dram Type= 6, Freq= 0, CH_1, rank 1
3158 11:03:33.442608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 11:03:33.442684 ==
3160 11:03:33.445822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3161 11:03:33.452414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3162 11:03:33.461665 [CA 0] Center 38 (8~68) winsize 61
3163 11:03:33.465032 [CA 1] Center 37 (7~68) winsize 62
3164 11:03:33.468311 [CA 2] Center 35 (5~66) winsize 62
3165 11:03:33.471860 [CA 3] Center 34 (4~65) winsize 62
3166 11:03:33.475021 [CA 4] Center 34 (4~64) winsize 61
3167 11:03:33.478440 [CA 5] Center 33 (3~63) winsize 61
3168 11:03:33.478502
3169 11:03:33.482016 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3170 11:03:33.482115
3171 11:03:33.485456 [CATrainingPosCal] consider 2 rank data
3172 11:03:33.488370 u2DelayCellTimex100 = 270/100 ps
3173 11:03:33.491736 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3174 11:03:33.495267 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3175 11:03:33.501534 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3176 11:03:33.505195 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3177 11:03:33.508225 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 11:03:33.511489 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3179 11:03:33.511567
3180 11:03:33.514789 CA PerBit enable=1, Macro0, CA PI delay=33
3181 11:03:33.514866
3182 11:03:33.518105 [CBTSetCACLKResult] CA Dly = 33
3183 11:03:33.518183 CS Dly: 6 (0~38)
3184 11:03:33.518241
3185 11:03:33.521717 ----->DramcWriteLeveling(PI) begin...
3186 11:03:33.524928 ==
3187 11:03:33.528336 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 11:03:33.531841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 11:03:33.531918 ==
3190 11:03:33.535041 Write leveling (Byte 0): 23 => 23
3191 11:03:33.538390 Write leveling (Byte 1): 29 => 29
3192 11:03:33.541877 DramcWriteLeveling(PI) end<-----
3193 11:03:33.541953
3194 11:03:33.542011 ==
3195 11:03:33.544948 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 11:03:33.548233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 11:03:33.548308 ==
3198 11:03:33.551885 [Gating] SW mode calibration
3199 11:03:33.558507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3200 11:03:33.561637 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3201 11:03:33.568425 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 11:03:33.571713 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 11:03:33.574896 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 11:03:33.581762 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 11:03:33.585058 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 11:03:33.588315 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3207 11:03:33.594606 0 15 24 | B1->B0 | 2a2a 2424 | 0 0 | (1 0) (0 0)
3208 11:03:33.598007 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 11:03:33.601413 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 11:03:33.607904 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 11:03:33.611211 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 11:03:33.614606 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 11:03:33.621212 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 11:03:33.624767 1 0 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3215 11:03:33.628238 1 0 24 | B1->B0 | 4343 4545 | 1 1 | (0 0) (0 0)
3216 11:03:33.634586 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 11:03:33.638329 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 11:03:33.641573 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 11:03:33.648202 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 11:03:33.651439 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 11:03:33.654563 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 11:03:33.661631 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3223 11:03:33.664617 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3224 11:03:33.667778 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3225 11:03:33.674452 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 11:03:33.678025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 11:03:33.681026 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 11:03:33.687914 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 11:03:33.691298 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 11:03:33.694468 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 11:03:33.697930 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 11:03:33.704646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:03:33.707813 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:03:33.711122 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:03:33.717781 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:03:33.720981 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:03:33.724376 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:03:33.731238 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3239 11:03:33.734445 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3240 11:03:33.737561 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3241 11:03:33.740969 Total UI for P1: 0, mck2ui 16
3242 11:03:33.744138 best dqsien dly found for B0: ( 1, 3, 22)
3243 11:03:33.750915 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 11:03:33.750991 Total UI for P1: 0, mck2ui 16
3245 11:03:33.757609 best dqsien dly found for B1: ( 1, 3, 26)
3246 11:03:33.760945 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3247 11:03:33.764185 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3248 11:03:33.764260
3249 11:03:33.767876 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3250 11:03:33.770960 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3251 11:03:33.774089 [Gating] SW calibration Done
3252 11:03:33.774164 ==
3253 11:03:33.777859 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 11:03:33.781266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 11:03:33.781343 ==
3256 11:03:33.784169 RX Vref Scan: 0
3257 11:03:33.784243
3258 11:03:33.784301 RX Vref 0 -> 0, step: 1
3259 11:03:33.784354
3260 11:03:33.787643 RX Delay -40 -> 252, step: 8
3261 11:03:33.790873 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3262 11:03:33.797693 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3263 11:03:33.801227 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3264 11:03:33.804272 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3265 11:03:33.807752 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3266 11:03:33.810773 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3267 11:03:33.817439 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3268 11:03:33.820825 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3269 11:03:33.824461 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3270 11:03:33.827783 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3271 11:03:33.831053 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3272 11:03:33.837459 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3273 11:03:33.841056 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3274 11:03:33.844353 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3275 11:03:33.847586 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3276 11:03:33.851032 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3277 11:03:33.851097 ==
3278 11:03:33.854180 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 11:03:33.861053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 11:03:33.861155 ==
3281 11:03:33.861245 DQS Delay:
3282 11:03:33.864516 DQS0 = 0, DQS1 = 0
3283 11:03:33.864581 DQM Delay:
3284 11:03:33.867840 DQM0 = 119, DQM1 = 112
3285 11:03:33.867917 DQ Delay:
3286 11:03:33.870957 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3287 11:03:33.874487 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3288 11:03:33.877497 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3289 11:03:33.880706 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3290 11:03:33.880784
3291 11:03:33.880841
3292 11:03:33.880894 ==
3293 11:03:33.884342 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 11:03:33.887479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 11:03:33.890720 ==
3296 11:03:33.890795
3297 11:03:33.890853
3298 11:03:33.890906 TX Vref Scan disable
3299 11:03:33.894372 == TX Byte 0 ==
3300 11:03:33.897720 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3301 11:03:33.900951 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3302 11:03:33.904199 == TX Byte 1 ==
3303 11:03:33.907630 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3304 11:03:33.910722 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3305 11:03:33.914381 ==
3306 11:03:33.914497 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 11:03:33.920722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 11:03:33.920798 ==
3309 11:03:33.931911 TX Vref=22, minBit 1, minWin=24, winSum=400
3310 11:03:33.935227 TX Vref=24, minBit 10, minWin=24, winSum=404
3311 11:03:33.938743 TX Vref=26, minBit 10, minWin=24, winSum=408
3312 11:03:33.941845 TX Vref=28, minBit 11, minWin=24, winSum=415
3313 11:03:33.945065 TX Vref=30, minBit 8, minWin=25, winSum=417
3314 11:03:33.952028 TX Vref=32, minBit 9, minWin=24, winSum=416
3315 11:03:33.955326 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 30
3316 11:03:33.955402
3317 11:03:33.958570 Final TX Range 1 Vref 30
3318 11:03:33.958645
3319 11:03:33.958703 ==
3320 11:03:33.961895 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 11:03:33.965167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 11:03:33.965271 ==
3323 11:03:33.968692
3324 11:03:33.968766
3325 11:03:33.968823 TX Vref Scan disable
3326 11:03:33.971719 == TX Byte 0 ==
3327 11:03:33.975199 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3328 11:03:33.982013 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3329 11:03:33.982088 == TX Byte 1 ==
3330 11:03:33.985283 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3331 11:03:33.992100 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3332 11:03:33.992176
3333 11:03:33.992234 [DATLAT]
3334 11:03:33.992288 Freq=1200, CH1 RK0
3335 11:03:33.992339
3336 11:03:33.995229 DATLAT Default: 0xd
3337 11:03:33.995303 0, 0xFFFF, sum = 0
3338 11:03:33.998472 1, 0xFFFF, sum = 0
3339 11:03:34.001760 2, 0xFFFF, sum = 0
3340 11:03:34.001836 3, 0xFFFF, sum = 0
3341 11:03:34.005040 4, 0xFFFF, sum = 0
3342 11:03:34.005117 5, 0xFFFF, sum = 0
3343 11:03:34.008414 6, 0xFFFF, sum = 0
3344 11:03:34.008490 7, 0xFFFF, sum = 0
3345 11:03:34.011658 8, 0xFFFF, sum = 0
3346 11:03:34.011734 9, 0xFFFF, sum = 0
3347 11:03:34.015117 10, 0xFFFF, sum = 0
3348 11:03:34.015193 11, 0xFFFF, sum = 0
3349 11:03:34.018373 12, 0x0, sum = 1
3350 11:03:34.018449 13, 0x0, sum = 2
3351 11:03:34.021505 14, 0x0, sum = 3
3352 11:03:34.021581 15, 0x0, sum = 4
3353 11:03:34.025104 best_step = 13
3354 11:03:34.025214
3355 11:03:34.025273 ==
3356 11:03:34.028473 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 11:03:34.031469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 11:03:34.031545 ==
3359 11:03:34.031604 RX Vref Scan: 1
3360 11:03:34.031658
3361 11:03:34.035068 Set Vref Range= 32 -> 127
3362 11:03:34.035143
3363 11:03:34.038365 RX Vref 32 -> 127, step: 1
3364 11:03:34.038440
3365 11:03:34.041553 RX Delay -13 -> 252, step: 4
3366 11:03:34.041628
3367 11:03:34.045167 Set Vref, RX VrefLevel [Byte0]: 32
3368 11:03:34.048242 [Byte1]: 32
3369 11:03:34.048317
3370 11:03:34.051562 Set Vref, RX VrefLevel [Byte0]: 33
3371 11:03:34.054865 [Byte1]: 33
3372 11:03:34.058532
3373 11:03:34.058606 Set Vref, RX VrefLevel [Byte0]: 34
3374 11:03:34.061861 [Byte1]: 34
3375 11:03:34.066116
3376 11:03:34.066190 Set Vref, RX VrefLevel [Byte0]: 35
3377 11:03:34.069819 [Byte1]: 35
3378 11:03:34.073970
3379 11:03:34.074044 Set Vref, RX VrefLevel [Byte0]: 36
3380 11:03:34.077711 [Byte1]: 36
3381 11:03:34.082185
3382 11:03:34.082261 Set Vref, RX VrefLevel [Byte0]: 37
3383 11:03:34.085611 [Byte1]: 37
3384 11:03:34.090179
3385 11:03:34.090253 Set Vref, RX VrefLevel [Byte0]: 38
3386 11:03:34.093205 [Byte1]: 38
3387 11:03:34.098002
3388 11:03:34.098076 Set Vref, RX VrefLevel [Byte0]: 39
3389 11:03:34.100974 [Byte1]: 39
3390 11:03:34.105861
3391 11:03:34.105934 Set Vref, RX VrefLevel [Byte0]: 40
3392 11:03:34.109232 [Byte1]: 40
3393 11:03:34.113678
3394 11:03:34.113752 Set Vref, RX VrefLevel [Byte0]: 41
3395 11:03:34.116842 [Byte1]: 41
3396 11:03:34.121503
3397 11:03:34.121576 Set Vref, RX VrefLevel [Byte0]: 42
3398 11:03:34.124799 [Byte1]: 42
3399 11:03:34.129261
3400 11:03:34.129334 Set Vref, RX VrefLevel [Byte0]: 43
3401 11:03:34.132936 [Byte1]: 43
3402 11:03:34.137383
3403 11:03:34.137457 Set Vref, RX VrefLevel [Byte0]: 44
3404 11:03:34.140831 [Byte1]: 44
3405 11:03:34.145060
3406 11:03:34.145157 Set Vref, RX VrefLevel [Byte0]: 45
3407 11:03:34.148575 [Byte1]: 45
3408 11:03:34.153060
3409 11:03:34.153160 Set Vref, RX VrefLevel [Byte0]: 46
3410 11:03:34.156360 [Byte1]: 46
3411 11:03:34.161002
3412 11:03:34.161076 Set Vref, RX VrefLevel [Byte0]: 47
3413 11:03:34.164158 [Byte1]: 47
3414 11:03:34.168834
3415 11:03:34.168908 Set Vref, RX VrefLevel [Byte0]: 48
3416 11:03:34.172091 [Byte1]: 48
3417 11:03:34.176895
3418 11:03:34.176969 Set Vref, RX VrefLevel [Byte0]: 49
3419 11:03:34.180245 [Byte1]: 49
3420 11:03:34.184455
3421 11:03:34.184529 Set Vref, RX VrefLevel [Byte0]: 50
3422 11:03:34.187981 [Byte1]: 50
3423 11:03:34.192552
3424 11:03:34.192626 Set Vref, RX VrefLevel [Byte0]: 51
3425 11:03:34.195804 [Byte1]: 51
3426 11:03:34.200238
3427 11:03:34.200312 Set Vref, RX VrefLevel [Byte0]: 52
3428 11:03:34.203577 [Byte1]: 52
3429 11:03:34.208172
3430 11:03:34.208247 Set Vref, RX VrefLevel [Byte0]: 53
3431 11:03:34.211726 [Byte1]: 53
3432 11:03:34.216039
3433 11:03:34.216114 Set Vref, RX VrefLevel [Byte0]: 54
3434 11:03:34.219549 [Byte1]: 54
3435 11:03:34.223882
3436 11:03:34.223957 Set Vref, RX VrefLevel [Byte0]: 55
3437 11:03:34.227673 [Byte1]: 55
3438 11:03:34.231863
3439 11:03:34.231938 Set Vref, RX VrefLevel [Byte0]: 56
3440 11:03:34.235109 [Byte1]: 56
3441 11:03:34.239848
3442 11:03:34.239923 Set Vref, RX VrefLevel [Byte0]: 57
3443 11:03:34.243267 [Byte1]: 57
3444 11:03:34.247753
3445 11:03:34.247828 Set Vref, RX VrefLevel [Byte0]: 58
3446 11:03:34.250990 [Byte1]: 58
3447 11:03:34.255704
3448 11:03:34.259063 Set Vref, RX VrefLevel [Byte0]: 59
3449 11:03:34.259139 [Byte1]: 59
3450 11:03:34.263583
3451 11:03:34.263658 Set Vref, RX VrefLevel [Byte0]: 60
3452 11:03:34.266819 [Byte1]: 60
3453 11:03:34.271425
3454 11:03:34.271500 Set Vref, RX VrefLevel [Byte0]: 61
3455 11:03:34.274740 [Byte1]: 61
3456 11:03:34.279254
3457 11:03:34.279328 Set Vref, RX VrefLevel [Byte0]: 62
3458 11:03:34.282481 [Byte1]: 62
3459 11:03:34.287218
3460 11:03:34.287294 Set Vref, RX VrefLevel [Byte0]: 63
3461 11:03:34.290803 [Byte1]: 63
3462 11:03:34.295101
3463 11:03:34.295176 Set Vref, RX VrefLevel [Byte0]: 64
3464 11:03:34.298234 [Byte1]: 64
3465 11:03:34.302988
3466 11:03:34.303065 Set Vref, RX VrefLevel [Byte0]: 65
3467 11:03:34.306256 [Byte1]: 65
3468 11:03:34.310705
3469 11:03:34.310877 Set Vref, RX VrefLevel [Byte0]: 66
3470 11:03:34.314020 [Byte1]: 66
3471 11:03:34.318618
3472 11:03:34.318733 Set Vref, RX VrefLevel [Byte0]: 67
3473 11:03:34.321886 [Byte1]: 67
3474 11:03:34.326488
3475 11:03:34.326587 Final RX Vref Byte 0 = 54 to rank0
3476 11:03:34.329933 Final RX Vref Byte 1 = 53 to rank0
3477 11:03:34.333162 Final RX Vref Byte 0 = 54 to rank1
3478 11:03:34.336799 Final RX Vref Byte 1 = 53 to rank1==
3479 11:03:34.340036 Dram Type= 6, Freq= 0, CH_1, rank 0
3480 11:03:34.346658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 11:03:34.346774 ==
3482 11:03:34.346859 DQS Delay:
3483 11:03:34.346941 DQS0 = 0, DQS1 = 0
3484 11:03:34.349626 DQM Delay:
3485 11:03:34.349712 DQM0 = 119, DQM1 = 112
3486 11:03:34.353254 DQ Delay:
3487 11:03:34.356601 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =120
3488 11:03:34.359915 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3489 11:03:34.363121 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3490 11:03:34.366430 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3491 11:03:34.366507
3492 11:03:34.366565
3493 11:03:34.373424 [DQSOSCAuto] RK0, (LSB)MR18= 0x61a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3494 11:03:34.376722 CH1 RK0: MR19=404, MR18=61A
3495 11:03:34.383268 CH1_RK0: MR19=0x404, MR18=0x61A, DQSOSC=400, MR23=63, INC=40, DEC=27
3496 11:03:34.383346
3497 11:03:34.386623 ----->DramcWriteLeveling(PI) begin...
3498 11:03:34.386700 ==
3499 11:03:34.389789 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 11:03:34.392982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 11:03:34.396217 ==
3502 11:03:34.396293 Write leveling (Byte 0): 24 => 24
3503 11:03:34.399933 Write leveling (Byte 1): 28 => 28
3504 11:03:34.403303 DramcWriteLeveling(PI) end<-----
3505 11:03:34.403378
3506 11:03:34.403436 ==
3507 11:03:34.406527 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 11:03:34.413020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 11:03:34.413099 ==
3510 11:03:34.413180 [Gating] SW mode calibration
3511 11:03:34.423166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3512 11:03:34.426529 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3513 11:03:34.429772 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 11:03:34.436302 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 11:03:34.439635 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 11:03:34.442860 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 11:03:34.449506 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 11:03:34.452700 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3519 11:03:34.456121 0 15 24 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
3520 11:03:34.462769 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 0)
3521 11:03:34.466103 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 11:03:34.469439 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 11:03:34.476108 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 11:03:34.479287 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 11:03:34.482964 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 11:03:34.489546 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3527 11:03:34.493097 1 0 24 | B1->B0 | 3a3a 2929 | 0 0 | (0 0) (0 0)
3528 11:03:34.496395 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 11:03:34.503090 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 11:03:34.506418 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 11:03:34.509709 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 11:03:34.516258 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 11:03:34.519520 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 11:03:34.522855 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3535 11:03:34.529436 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3536 11:03:34.532539 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3537 11:03:34.535779 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:03:34.542881 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:03:34.546059 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:03:34.549451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:03:34.555681 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:03:34.559526 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:03:34.562702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:03:34.566038 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:03:34.572696 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:03:34.575707 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:03:34.579171 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:03:34.585725 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:03:34.588871 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:03:34.592203 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:03:34.599070 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3552 11:03:34.602328 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3553 11:03:34.605870 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 11:03:34.609066 Total UI for P1: 0, mck2ui 16
3555 11:03:34.612486 best dqsien dly found for B0: ( 1, 3, 26)
3556 11:03:34.615824 Total UI for P1: 0, mck2ui 16
3557 11:03:34.619089 best dqsien dly found for B1: ( 1, 3, 26)
3558 11:03:34.622372 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3559 11:03:34.625627 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3560 11:03:34.625703
3561 11:03:34.632479 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3562 11:03:34.635716 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3563 11:03:34.638986 [Gating] SW calibration Done
3564 11:03:34.639062 ==
3565 11:03:34.642250 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 11:03:34.645490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 11:03:34.645566 ==
3568 11:03:34.645625 RX Vref Scan: 0
3569 11:03:34.645678
3570 11:03:34.648799 RX Vref 0 -> 0, step: 1
3571 11:03:34.648874
3572 11:03:34.652339 RX Delay -40 -> 252, step: 8
3573 11:03:34.655550 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3574 11:03:34.658798 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3575 11:03:34.665596 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3576 11:03:34.668943 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3577 11:03:34.672373 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3578 11:03:34.675749 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3579 11:03:34.679075 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3580 11:03:34.682122 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3581 11:03:34.689101 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3582 11:03:34.692478 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3583 11:03:34.695540 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3584 11:03:34.698869 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3585 11:03:34.702245 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3586 11:03:34.709077 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3587 11:03:34.712658 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3588 11:03:34.715495 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3589 11:03:34.715583 ==
3590 11:03:34.718794 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 11:03:34.722166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 11:03:34.722229 ==
3593 11:03:34.725602 DQS Delay:
3594 11:03:34.725691 DQS0 = 0, DQS1 = 0
3595 11:03:34.729078 DQM Delay:
3596 11:03:34.729165 DQM0 = 120, DQM1 = 113
3597 11:03:34.732412 DQ Delay:
3598 11:03:34.735962 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3599 11:03:34.738896 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3600 11:03:34.742163 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3601 11:03:34.745588 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3602 11:03:34.745652
3603 11:03:34.745707
3604 11:03:34.745759 ==
3605 11:03:34.748865 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 11:03:34.752028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 11:03:34.752093 ==
3608 11:03:34.752147
3609 11:03:34.752216
3610 11:03:34.755662 TX Vref Scan disable
3611 11:03:34.758989 == TX Byte 0 ==
3612 11:03:34.762288 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3613 11:03:34.765590 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3614 11:03:34.768784 == TX Byte 1 ==
3615 11:03:34.772224 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3616 11:03:34.775498 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3617 11:03:34.775619 ==
3618 11:03:34.779064 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 11:03:34.782304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 11:03:34.782371 ==
3621 11:03:34.795743 TX Vref=22, minBit 1, minWin=25, winSum=412
3622 11:03:34.798940 TX Vref=24, minBit 1, minWin=25, winSum=411
3623 11:03:34.802772 TX Vref=26, minBit 1, minWin=25, winSum=418
3624 11:03:34.805876 TX Vref=28, minBit 1, minWin=25, winSum=424
3625 11:03:34.809091 TX Vref=30, minBit 0, minWin=26, winSum=423
3626 11:03:34.812650 TX Vref=32, minBit 10, minWin=25, winSum=424
3627 11:03:34.819334 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
3628 11:03:34.819461
3629 11:03:34.822533 Final TX Range 1 Vref 30
3630 11:03:34.822640
3631 11:03:34.822699 ==
3632 11:03:34.826079 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 11:03:34.829574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 11:03:34.829736 ==
3635 11:03:34.829843
3636 11:03:34.829921
3637 11:03:34.832712 TX Vref Scan disable
3638 11:03:34.835955 == TX Byte 0 ==
3639 11:03:34.839529 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3640 11:03:34.842606 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3641 11:03:34.845962 == TX Byte 1 ==
3642 11:03:34.849302 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3643 11:03:34.852958 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3644 11:03:34.853034
3645 11:03:34.856154 [DATLAT]
3646 11:03:34.856229 Freq=1200, CH1 RK1
3647 11:03:34.856288
3648 11:03:34.859144 DATLAT Default: 0xd
3649 11:03:34.859219 0, 0xFFFF, sum = 0
3650 11:03:34.862836 1, 0xFFFF, sum = 0
3651 11:03:34.862913 2, 0xFFFF, sum = 0
3652 11:03:34.866122 3, 0xFFFF, sum = 0
3653 11:03:34.866198 4, 0xFFFF, sum = 0
3654 11:03:34.869430 5, 0xFFFF, sum = 0
3655 11:03:34.869521 6, 0xFFFF, sum = 0
3656 11:03:34.872507 7, 0xFFFF, sum = 0
3657 11:03:34.872582 8, 0xFFFF, sum = 0
3658 11:03:34.875825 9, 0xFFFF, sum = 0
3659 11:03:34.879309 10, 0xFFFF, sum = 0
3660 11:03:34.879385 11, 0xFFFF, sum = 0
3661 11:03:34.882645 12, 0x0, sum = 1
3662 11:03:34.882753 13, 0x0, sum = 2
3663 11:03:34.882813 14, 0x0, sum = 3
3664 11:03:34.886312 15, 0x0, sum = 4
3665 11:03:34.886388 best_step = 13
3666 11:03:34.886446
3667 11:03:34.886500 ==
3668 11:03:34.889470 Dram Type= 6, Freq= 0, CH_1, rank 1
3669 11:03:34.896302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3670 11:03:34.896379 ==
3671 11:03:34.896437 RX Vref Scan: 0
3672 11:03:34.896491
3673 11:03:34.899645 RX Vref 0 -> 0, step: 1
3674 11:03:34.899720
3675 11:03:34.902716 RX Delay -13 -> 252, step: 4
3676 11:03:34.905949 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3677 11:03:34.909526 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3678 11:03:34.915802 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3679 11:03:34.919499 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3680 11:03:34.922584 iDelay=191, Bit 4, Center 120 (59 ~ 182) 124
3681 11:03:34.925821 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3682 11:03:34.929212 iDelay=191, Bit 6, Center 128 (67 ~ 190) 124
3683 11:03:34.936076 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3684 11:03:34.939445 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3685 11:03:34.942503 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3686 11:03:34.946101 iDelay=191, Bit 10, Center 112 (47 ~ 178) 132
3687 11:03:34.949193 iDelay=191, Bit 11, Center 108 (43 ~ 174) 132
3688 11:03:34.955756 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3689 11:03:34.958956 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3690 11:03:34.962134 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3691 11:03:34.965579 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3692 11:03:34.965668 ==
3693 11:03:34.969071 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 11:03:34.975603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 11:03:34.975679 ==
3696 11:03:34.975738 DQS Delay:
3697 11:03:34.978895 DQS0 = 0, DQS1 = 0
3698 11:03:34.978971 DQM Delay:
3699 11:03:34.979029 DQM0 = 119, DQM1 = 113
3700 11:03:34.981972 DQ Delay:
3701 11:03:34.985300 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3702 11:03:34.988902 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =116
3703 11:03:34.991993 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3704 11:03:34.995448 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3705 11:03:34.995523
3706 11:03:34.995581
3707 11:03:35.005323 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3708 11:03:35.005399 CH1 RK1: MR19=403, MR18=9EF
3709 11:03:35.012016 CH1_RK1: MR19=0x403, MR18=0x9EF, DQSOSC=406, MR23=63, INC=39, DEC=26
3710 11:03:35.015023 [RxdqsGatingPostProcess] freq 1200
3711 11:03:35.021946 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3712 11:03:35.025239 best DQS0 dly(2T, 0.5T) = (0, 11)
3713 11:03:35.028371 best DQS1 dly(2T, 0.5T) = (0, 11)
3714 11:03:35.031797 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3715 11:03:35.035165 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3716 11:03:35.035242 best DQS0 dly(2T, 0.5T) = (0, 11)
3717 11:03:35.038566 best DQS1 dly(2T, 0.5T) = (0, 11)
3718 11:03:35.041832 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3719 11:03:35.045058 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3720 11:03:35.048427 Pre-setting of DQS Precalculation
3721 11:03:35.055006 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3722 11:03:35.061762 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3723 11:03:35.068243 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3724 11:03:35.068319
3725 11:03:35.068377
3726 11:03:35.071776 [Calibration Summary] 2400 Mbps
3727 11:03:35.071851 CH 0, Rank 0
3728 11:03:35.074993 SW Impedance : PASS
3729 11:03:35.078294 DUTY Scan : NO K
3730 11:03:35.078369 ZQ Calibration : PASS
3731 11:03:35.081578 Jitter Meter : NO K
3732 11:03:35.084801 CBT Training : PASS
3733 11:03:35.084876 Write leveling : PASS
3734 11:03:35.088104 RX DQS gating : PASS
3735 11:03:35.091329 RX DQ/DQS(RDDQC) : PASS
3736 11:03:35.091404 TX DQ/DQS : PASS
3737 11:03:35.094554 RX DATLAT : PASS
3738 11:03:35.098234 RX DQ/DQS(Engine): PASS
3739 11:03:35.098310 TX OE : NO K
3740 11:03:35.101299 All Pass.
3741 11:03:35.101374
3742 11:03:35.101432 CH 0, Rank 1
3743 11:03:35.104903 SW Impedance : PASS
3744 11:03:35.104978 DUTY Scan : NO K
3745 11:03:35.108095 ZQ Calibration : PASS
3746 11:03:35.111278 Jitter Meter : NO K
3747 11:03:35.111370 CBT Training : PASS
3748 11:03:35.114621 Write leveling : PASS
3749 11:03:35.118285 RX DQS gating : PASS
3750 11:03:35.118352 RX DQ/DQS(RDDQC) : PASS
3751 11:03:35.121291 TX DQ/DQS : PASS
3752 11:03:35.121353 RX DATLAT : PASS
3753 11:03:35.124939 RX DQ/DQS(Engine): PASS
3754 11:03:35.128212 TX OE : NO K
3755 11:03:35.128280 All Pass.
3756 11:03:35.128361
3757 11:03:35.128439 CH 1, Rank 0
3758 11:03:35.131488 SW Impedance : PASS
3759 11:03:35.134677 DUTY Scan : NO K
3760 11:03:35.134741 ZQ Calibration : PASS
3761 11:03:35.138007 Jitter Meter : NO K
3762 11:03:35.141582 CBT Training : PASS
3763 11:03:35.141650 Write leveling : PASS
3764 11:03:35.144653 RX DQS gating : PASS
3765 11:03:35.148030 RX DQ/DQS(RDDQC) : PASS
3766 11:03:35.148151 TX DQ/DQS : PASS
3767 11:03:35.151404 RX DATLAT : PASS
3768 11:03:35.154610 RX DQ/DQS(Engine): PASS
3769 11:03:35.154673 TX OE : NO K
3770 11:03:35.154727 All Pass.
3771 11:03:35.158277
3772 11:03:35.158366 CH 1, Rank 1
3773 11:03:35.161269 SW Impedance : PASS
3774 11:03:35.161336 DUTY Scan : NO K
3775 11:03:35.164759 ZQ Calibration : PASS
3776 11:03:35.164846 Jitter Meter : NO K
3777 11:03:35.168184 CBT Training : PASS
3778 11:03:35.171392 Write leveling : PASS
3779 11:03:35.171460 RX DQS gating : PASS
3780 11:03:35.174955 RX DQ/DQS(RDDQC) : PASS
3781 11:03:35.178098 TX DQ/DQS : PASS
3782 11:03:35.178174 RX DATLAT : PASS
3783 11:03:35.181372 RX DQ/DQS(Engine): PASS
3784 11:03:35.184658 TX OE : NO K
3785 11:03:35.184725 All Pass.
3786 11:03:35.184779
3787 11:03:35.188113 DramC Write-DBI off
3788 11:03:35.188191 PER_BANK_REFRESH: Hybrid Mode
3789 11:03:35.191342 TX_TRACKING: ON
3790 11:03:35.198173 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3791 11:03:35.204663 [FAST_K] Save calibration result to emmc
3792 11:03:35.208219 dramc_set_vcore_voltage set vcore to 650000
3793 11:03:35.208288 Read voltage for 600, 5
3794 11:03:35.211200 Vio18 = 0
3795 11:03:35.211263 Vcore = 650000
3796 11:03:35.211317 Vdram = 0
3797 11:03:35.214865 Vddq = 0
3798 11:03:35.214934 Vmddr = 0
3799 11:03:35.218139 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3800 11:03:35.224949 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3801 11:03:35.228141 MEM_TYPE=3, freq_sel=19
3802 11:03:35.231539 sv_algorithm_assistance_LP4_1600
3803 11:03:35.234708 ============ PULL DRAM RESETB DOWN ============
3804 11:03:35.237944 ========== PULL DRAM RESETB DOWN end =========
3805 11:03:35.241278 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3806 11:03:35.244674 ===================================
3807 11:03:35.247996 LPDDR4 DRAM CONFIGURATION
3808 11:03:35.251139 ===================================
3809 11:03:35.254711 EX_ROW_EN[0] = 0x0
3810 11:03:35.254787 EX_ROW_EN[1] = 0x0
3811 11:03:35.257775 LP4Y_EN = 0x0
3812 11:03:35.257851 WORK_FSP = 0x0
3813 11:03:35.261234 WL = 0x2
3814 11:03:35.261310 RL = 0x2
3815 11:03:35.264551 BL = 0x2
3816 11:03:35.264626 RPST = 0x0
3817 11:03:35.268057 RD_PRE = 0x0
3818 11:03:35.271035 WR_PRE = 0x1
3819 11:03:35.271110 WR_PST = 0x0
3820 11:03:35.274302 DBI_WR = 0x0
3821 11:03:35.274377 DBI_RD = 0x0
3822 11:03:35.277841 OTF = 0x1
3823 11:03:35.280988 ===================================
3824 11:03:35.284298 ===================================
3825 11:03:35.284374 ANA top config
3826 11:03:35.287590 ===================================
3827 11:03:35.291068 DLL_ASYNC_EN = 0
3828 11:03:35.294372 ALL_SLAVE_EN = 1
3829 11:03:35.294447 NEW_RANK_MODE = 1
3830 11:03:35.297909 DLL_IDLE_MODE = 1
3831 11:03:35.301070 LP45_APHY_COMB_EN = 1
3832 11:03:35.304342 TX_ODT_DIS = 1
3833 11:03:35.304417 NEW_8X_MODE = 1
3834 11:03:35.308000 ===================================
3835 11:03:35.311301 ===================================
3836 11:03:35.314359 data_rate = 1200
3837 11:03:35.317623 CKR = 1
3838 11:03:35.321063 DQ_P2S_RATIO = 8
3839 11:03:35.324666 ===================================
3840 11:03:35.327835 CA_P2S_RATIO = 8
3841 11:03:35.330957 DQ_CA_OPEN = 0
3842 11:03:35.331032 DQ_SEMI_OPEN = 0
3843 11:03:35.334745 CA_SEMI_OPEN = 0
3844 11:03:35.337929 CA_FULL_RATE = 0
3845 11:03:35.341079 DQ_CKDIV4_EN = 1
3846 11:03:35.344442 CA_CKDIV4_EN = 1
3847 11:03:35.344517 CA_PREDIV_EN = 0
3848 11:03:35.347916 PH8_DLY = 0
3849 11:03:35.350985 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3850 11:03:35.354325 DQ_AAMCK_DIV = 4
3851 11:03:35.357565 CA_AAMCK_DIV = 4
3852 11:03:35.360904 CA_ADMCK_DIV = 4
3853 11:03:35.361012 DQ_TRACK_CA_EN = 0
3854 11:03:35.364564 CA_PICK = 600
3855 11:03:35.367660 CA_MCKIO = 600
3856 11:03:35.371222 MCKIO_SEMI = 0
3857 11:03:35.374378 PLL_FREQ = 2288
3858 11:03:35.377804 DQ_UI_PI_RATIO = 32
3859 11:03:35.381002 CA_UI_PI_RATIO = 0
3860 11:03:35.384268 ===================================
3861 11:03:35.387579 ===================================
3862 11:03:35.387674 memory_type:LPDDR4
3863 11:03:35.391197 GP_NUM : 10
3864 11:03:35.394443 SRAM_EN : 1
3865 11:03:35.394544 MD32_EN : 0
3866 11:03:35.397742 ===================================
3867 11:03:35.400970 [ANA_INIT] >>>>>>>>>>>>>>
3868 11:03:35.404235 <<<<<< [CONFIGURE PHASE]: ANA_TX
3869 11:03:35.407867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3870 11:03:35.411059 ===================================
3871 11:03:35.414208 data_rate = 1200,PCW = 0X5800
3872 11:03:35.417814 ===================================
3873 11:03:35.420956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3874 11:03:35.424294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3875 11:03:35.430611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3876 11:03:35.434149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3877 11:03:35.437539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3878 11:03:35.440759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3879 11:03:35.444083 [ANA_INIT] flow start
3880 11:03:35.447213 [ANA_INIT] PLL >>>>>>>>
3881 11:03:35.447291 [ANA_INIT] PLL <<<<<<<<
3882 11:03:35.450770 [ANA_INIT] MIDPI >>>>>>>>
3883 11:03:35.453893 [ANA_INIT] MIDPI <<<<<<<<
3884 11:03:35.457610 [ANA_INIT] DLL >>>>>>>>
3885 11:03:35.457687 [ANA_INIT] flow end
3886 11:03:35.460551 ============ LP4 DIFF to SE enter ============
3887 11:03:35.467598 ============ LP4 DIFF to SE exit ============
3888 11:03:35.467677 [ANA_INIT] <<<<<<<<<<<<<
3889 11:03:35.470502 [Flow] Enable top DCM control >>>>>
3890 11:03:35.473895 [Flow] Enable top DCM control <<<<<
3891 11:03:35.477468 Enable DLL master slave shuffle
3892 11:03:35.484037 ==============================================================
3893 11:03:35.484115 Gating Mode config
3894 11:03:35.490860 ==============================================================
3895 11:03:35.494123 Config description:
3896 11:03:35.500986 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3897 11:03:35.507430 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3898 11:03:35.514009 SELPH_MODE 0: By rank 1: By Phase
3899 11:03:35.520820 ==============================================================
3900 11:03:35.520896 GAT_TRACK_EN = 1
3901 11:03:35.524126 RX_GATING_MODE = 2
3902 11:03:35.527379 RX_GATING_TRACK_MODE = 2
3903 11:03:35.530624 SELPH_MODE = 1
3904 11:03:35.533892 PICG_EARLY_EN = 1
3905 11:03:35.537335 VALID_LAT_VALUE = 1
3906 11:03:35.543532 ==============================================================
3907 11:03:35.546955 Enter into Gating configuration >>>>
3908 11:03:35.550306 Exit from Gating configuration <<<<
3909 11:03:35.554078 Enter into DVFS_PRE_config >>>>>
3910 11:03:35.563902 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3911 11:03:35.567173 Exit from DVFS_PRE_config <<<<<
3912 11:03:35.570527 Enter into PICG configuration >>>>
3913 11:03:35.573673 Exit from PICG configuration <<<<
3914 11:03:35.577115 [RX_INPUT] configuration >>>>>
3915 11:03:35.577251 [RX_INPUT] configuration <<<<<
3916 11:03:35.583862 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3917 11:03:35.590467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3918 11:03:35.593790 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 11:03:35.600133 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 11:03:35.606896 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3921 11:03:35.613878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3922 11:03:35.617132 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3923 11:03:35.620400 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3924 11:03:35.627188 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3925 11:03:35.630560 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3926 11:03:35.633889 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3927 11:03:35.640399 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 11:03:35.640475 ===================================
3929 11:03:35.643564 LPDDR4 DRAM CONFIGURATION
3930 11:03:35.647149 ===================================
3931 11:03:35.650273 EX_ROW_EN[0] = 0x0
3932 11:03:35.650351 EX_ROW_EN[1] = 0x0
3933 11:03:35.653712 LP4Y_EN = 0x0
3934 11:03:35.653787 WORK_FSP = 0x0
3935 11:03:35.656790 WL = 0x2
3936 11:03:35.656866 RL = 0x2
3937 11:03:35.660293 BL = 0x2
3938 11:03:35.660368 RPST = 0x0
3939 11:03:35.663492 RD_PRE = 0x0
3940 11:03:35.667113 WR_PRE = 0x1
3941 11:03:35.667188 WR_PST = 0x0
3942 11:03:35.670481 DBI_WR = 0x0
3943 11:03:35.670557 DBI_RD = 0x0
3944 11:03:35.673800 OTF = 0x1
3945 11:03:35.677099 ===================================
3946 11:03:35.680374 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3947 11:03:35.683495 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3948 11:03:35.686776 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3949 11:03:35.690206 ===================================
3950 11:03:35.693669 LPDDR4 DRAM CONFIGURATION
3951 11:03:35.697231 ===================================
3952 11:03:35.700084 EX_ROW_EN[0] = 0x10
3953 11:03:35.700159 EX_ROW_EN[1] = 0x0
3954 11:03:35.703607 LP4Y_EN = 0x0
3955 11:03:35.703682 WORK_FSP = 0x0
3956 11:03:35.706895 WL = 0x2
3957 11:03:35.706970 RL = 0x2
3958 11:03:35.710295 BL = 0x2
3959 11:03:35.710370 RPST = 0x0
3960 11:03:35.713636 RD_PRE = 0x0
3961 11:03:35.713711 WR_PRE = 0x1
3962 11:03:35.716616 WR_PST = 0x0
3963 11:03:35.716692 DBI_WR = 0x0
3964 11:03:35.720365 DBI_RD = 0x0
3965 11:03:35.720467 OTF = 0x1
3966 11:03:35.723709 ===================================
3967 11:03:35.730147 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3968 11:03:35.734972 nWR fixed to 30
3969 11:03:35.738275 [ModeRegInit_LP4] CH0 RK0
3970 11:03:35.738350 [ModeRegInit_LP4] CH0 RK1
3971 11:03:35.741882 [ModeRegInit_LP4] CH1 RK0
3972 11:03:35.745468 [ModeRegInit_LP4] CH1 RK1
3973 11:03:35.745543 match AC timing 17
3974 11:03:35.751964 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3975 11:03:35.755111 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3976 11:03:35.758463 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3977 11:03:35.765309 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3978 11:03:35.768837 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3979 11:03:35.768912 ==
3980 11:03:35.771984 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 11:03:35.775279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 11:03:35.775356 ==
3983 11:03:35.781988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3984 11:03:35.788383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3985 11:03:35.792207 [CA 0] Center 36 (5~67) winsize 63
3986 11:03:35.795476 [CA 1] Center 36 (6~67) winsize 62
3987 11:03:35.798800 [CA 2] Center 34 (4~65) winsize 62
3988 11:03:35.801923 [CA 3] Center 34 (3~65) winsize 63
3989 11:03:35.805029 [CA 4] Center 34 (3~65) winsize 63
3990 11:03:35.808639 [CA 5] Center 33 (2~64) winsize 63
3991 11:03:35.808731
3992 11:03:35.812081 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3993 11:03:35.812157
3994 11:03:35.815431 [CATrainingPosCal] consider 1 rank data
3995 11:03:35.818674 u2DelayCellTimex100 = 270/100 ps
3996 11:03:35.821893 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3997 11:03:35.825406 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 11:03:35.828448 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 11:03:35.831773 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4000 11:03:35.834993 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4001 11:03:35.838285 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4002 11:03:35.838387
4003 11:03:35.845013 CA PerBit enable=1, Macro0, CA PI delay=33
4004 11:03:35.845103
4005 11:03:35.848154 [CBTSetCACLKResult] CA Dly = 33
4006 11:03:35.848229 CS Dly: 5 (0~36)
4007 11:03:35.848287 ==
4008 11:03:35.851334 Dram Type= 6, Freq= 0, CH_0, rank 1
4009 11:03:35.854576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 11:03:35.854674 ==
4011 11:03:35.861699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4012 11:03:35.867934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4013 11:03:35.871398 [CA 0] Center 36 (6~67) winsize 62
4014 11:03:35.874741 [CA 1] Center 36 (6~67) winsize 62
4015 11:03:35.878129 [CA 2] Center 35 (5~66) winsize 62
4016 11:03:35.881190 [CA 3] Center 34 (4~65) winsize 62
4017 11:03:35.884494 [CA 4] Center 34 (3~65) winsize 63
4018 11:03:35.887760 [CA 5] Center 34 (3~65) winsize 63
4019 11:03:35.887835
4020 11:03:35.891330 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4021 11:03:35.891405
4022 11:03:35.894576 [CATrainingPosCal] consider 2 rank data
4023 11:03:35.897879 u2DelayCellTimex100 = 270/100 ps
4024 11:03:35.901314 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4025 11:03:35.904618 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4026 11:03:35.907546 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4027 11:03:35.911302 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4028 11:03:35.917557 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4029 11:03:35.921355 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4030 11:03:35.921430
4031 11:03:35.924259 CA PerBit enable=1, Macro0, CA PI delay=33
4032 11:03:35.924334
4033 11:03:35.927871 [CBTSetCACLKResult] CA Dly = 33
4034 11:03:35.927946 CS Dly: 5 (0~37)
4035 11:03:35.928004
4036 11:03:35.930946 ----->DramcWriteLeveling(PI) begin...
4037 11:03:35.931056 ==
4038 11:03:35.934211 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 11:03:35.940898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 11:03:35.940974 ==
4041 11:03:35.944410 Write leveling (Byte 0): 32 => 32
4042 11:03:35.947324 Write leveling (Byte 1): 31 => 31
4043 11:03:35.947416 DramcWriteLeveling(PI) end<-----
4044 11:03:35.947488
4045 11:03:35.951029 ==
4046 11:03:35.954344 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 11:03:35.957634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 11:03:35.957710 ==
4049 11:03:35.960946 [Gating] SW mode calibration
4050 11:03:35.967376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4051 11:03:35.970802 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4052 11:03:35.977683 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 11:03:35.980905 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 11:03:35.984411 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 11:03:35.990857 0 9 12 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 0)
4056 11:03:35.994292 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4057 11:03:35.997560 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 11:03:36.004238 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 11:03:36.007542 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 11:03:36.011077 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 11:03:36.017402 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 11:03:36.021092 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 11:03:36.024354 0 10 12 | B1->B0 | 2424 3636 | 1 1 | (0 0) (0 0)
4064 11:03:36.027722 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
4065 11:03:36.034106 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 11:03:36.037754 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 11:03:36.040916 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 11:03:36.047644 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 11:03:36.051048 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 11:03:36.054230 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4071 11:03:36.060706 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4072 11:03:36.064427 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4073 11:03:36.067713 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:03:36.074157 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:03:36.077358 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:03:36.080956 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:03:36.087536 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:03:36.090627 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:03:36.094006 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:03:36.100640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:03:36.104274 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:03:36.107553 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:03:36.114113 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:03:36.117355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:03:36.120790 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:03:36.127279 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:03:36.130617 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4088 11:03:36.133870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4089 11:03:36.137158 Total UI for P1: 0, mck2ui 16
4090 11:03:36.140742 best dqsien dly found for B0: ( 0, 13, 12)
4091 11:03:36.144051 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 11:03:36.147243 Total UI for P1: 0, mck2ui 16
4093 11:03:36.150502 best dqsien dly found for B1: ( 0, 13, 14)
4094 11:03:36.153987 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4095 11:03:36.160652 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4096 11:03:36.160727
4097 11:03:36.163724 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4098 11:03:36.167212 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4099 11:03:36.170548 [Gating] SW calibration Done
4100 11:03:36.170623 ==
4101 11:03:36.173896 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 11:03:36.177160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 11:03:36.177265 ==
4104 11:03:36.177337 RX Vref Scan: 0
4105 11:03:36.180499
4106 11:03:36.180589 RX Vref 0 -> 0, step: 1
4107 11:03:36.180662
4108 11:03:36.183866 RX Delay -230 -> 252, step: 16
4109 11:03:36.187149 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4110 11:03:36.193925 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4111 11:03:36.197149 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4112 11:03:36.200780 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4113 11:03:36.203779 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4114 11:03:36.207214 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4115 11:03:36.213908 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4116 11:03:36.217017 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4117 11:03:36.220827 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4118 11:03:36.224009 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4119 11:03:36.230721 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4120 11:03:36.233904 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4121 11:03:36.237101 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4122 11:03:36.240304 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4123 11:03:36.247241 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4124 11:03:36.250495 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4125 11:03:36.250571 ==
4126 11:03:36.253918 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 11:03:36.257198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 11:03:36.257274 ==
4129 11:03:36.257331 DQS Delay:
4130 11:03:36.260240 DQS0 = 0, DQS1 = 0
4131 11:03:36.260314 DQM Delay:
4132 11:03:36.263693 DQM0 = 49, DQM1 = 41
4133 11:03:36.263768 DQ Delay:
4134 11:03:36.267007 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4135 11:03:36.270507 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4136 11:03:36.273659 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4137 11:03:36.277300 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4138 11:03:36.277376
4139 11:03:36.277434
4140 11:03:36.277488 ==
4141 11:03:36.280441 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 11:03:36.283465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 11:03:36.286699 ==
4144 11:03:36.286774
4145 11:03:36.286831
4146 11:03:36.286884 TX Vref Scan disable
4147 11:03:36.290028 == TX Byte 0 ==
4148 11:03:36.293320 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4149 11:03:36.299958 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4150 11:03:36.300033 == TX Byte 1 ==
4151 11:03:36.303197 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4152 11:03:36.310058 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4153 11:03:36.310134 ==
4154 11:03:36.313641 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 11:03:36.316683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 11:03:36.316758 ==
4157 11:03:36.316834
4158 11:03:36.316918
4159 11:03:36.319876 TX Vref Scan disable
4160 11:03:36.323588 == TX Byte 0 ==
4161 11:03:36.326615 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4162 11:03:36.330216 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4163 11:03:36.330292 == TX Byte 1 ==
4164 11:03:36.336829 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4165 11:03:36.340013 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4166 11:03:36.340111
4167 11:03:36.340198 [DATLAT]
4168 11:03:36.343313 Freq=600, CH0 RK0
4169 11:03:36.343387
4170 11:03:36.343445 DATLAT Default: 0x9
4171 11:03:36.347092 0, 0xFFFF, sum = 0
4172 11:03:36.347169 1, 0xFFFF, sum = 0
4173 11:03:36.350296 2, 0xFFFF, sum = 0
4174 11:03:36.350372 3, 0xFFFF, sum = 0
4175 11:03:36.353570 4, 0xFFFF, sum = 0
4176 11:03:36.353647 5, 0xFFFF, sum = 0
4177 11:03:36.356745 6, 0xFFFF, sum = 0
4178 11:03:36.360341 7, 0xFFFF, sum = 0
4179 11:03:36.360417 8, 0x0, sum = 1
4180 11:03:36.360475 9, 0x0, sum = 2
4181 11:03:36.363653 10, 0x0, sum = 3
4182 11:03:36.363768 11, 0x0, sum = 4
4183 11:03:36.366819 best_step = 9
4184 11:03:36.366894
4185 11:03:36.366988 ==
4186 11:03:36.370216 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 11:03:36.373231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 11:03:36.373307 ==
4189 11:03:36.376861 RX Vref Scan: 1
4190 11:03:36.376936
4191 11:03:36.376994 RX Vref 0 -> 0, step: 1
4192 11:03:36.377047
4193 11:03:36.379936 RX Delay -179 -> 252, step: 8
4194 11:03:36.380010
4195 11:03:36.383245 Set Vref, RX VrefLevel [Byte0]: 58
4196 11:03:36.386466 [Byte1]: 49
4197 11:03:36.390529
4198 11:03:36.390604 Final RX Vref Byte 0 = 58 to rank0
4199 11:03:36.393791 Final RX Vref Byte 1 = 49 to rank0
4200 11:03:36.397107 Final RX Vref Byte 0 = 58 to rank1
4201 11:03:36.400813 Final RX Vref Byte 1 = 49 to rank1==
4202 11:03:36.404013 Dram Type= 6, Freq= 0, CH_0, rank 0
4203 11:03:36.410678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 11:03:36.410794 ==
4205 11:03:36.410882 DQS Delay:
4206 11:03:36.410963 DQS0 = 0, DQS1 = 0
4207 11:03:36.413991 DQM Delay:
4208 11:03:36.414065 DQM0 = 48, DQM1 = 39
4209 11:03:36.417464 DQ Delay:
4210 11:03:36.420625 DQ0 =44, DQ1 =52, DQ2 =44, DQ3 =44
4211 11:03:36.420700 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4212 11:03:36.424067 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4213 11:03:36.427211 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4214 11:03:36.430655
4215 11:03:36.430757
4216 11:03:36.437625 [DQSOSCAuto] RK0, (LSB)MR18= 0x635d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4217 11:03:36.440871 CH0 RK0: MR19=808, MR18=635D
4218 11:03:36.447187 CH0_RK0: MR19=0x808, MR18=0x635D, DQSOSC=391, MR23=63, INC=171, DEC=114
4219 11:03:36.447265
4220 11:03:36.450650 ----->DramcWriteLeveling(PI) begin...
4221 11:03:36.450727 ==
4222 11:03:36.453845 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 11:03:36.457522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 11:03:36.457658 ==
4225 11:03:36.460902 Write leveling (Byte 0): 35 => 35
4226 11:03:36.464090 Write leveling (Byte 1): 32 => 32
4227 11:03:36.467363 DramcWriteLeveling(PI) end<-----
4228 11:03:36.467528
4229 11:03:36.467627 ==
4230 11:03:36.470512 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 11:03:36.473868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 11:03:36.474004 ==
4233 11:03:36.477035 [Gating] SW mode calibration
4234 11:03:36.483739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4235 11:03:36.490525 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4236 11:03:36.493652 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 11:03:36.497480 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 11:03:36.504046 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 11:03:36.507247 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
4240 11:03:36.510524 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4241 11:03:36.517055 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 11:03:36.520878 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 11:03:36.523870 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 11:03:36.530505 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 11:03:36.534000 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 11:03:36.537084 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 11:03:36.543950 0 10 12 | B1->B0 | 3131 3333 | 0 0 | (0 0) (1 1)
4248 11:03:36.547209 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 11:03:36.550368 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 11:03:36.556953 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 11:03:36.560621 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:03:36.563908 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 11:03:36.570391 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 11:03:36.573684 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 11:03:36.576855 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:03:36.580401 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:03:36.587084 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:03:36.590346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:03:36.593528 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:03:36.600338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:03:36.603516 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:03:36.606783 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:03:36.613855 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:03:36.616905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:03:36.620090 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:03:36.627108 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:03:36.630707 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:03:36.633671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:03:36.640220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:03:36.643285 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:03:36.646901 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4272 11:03:36.653376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 11:03:36.653451 Total UI for P1: 0, mck2ui 16
4274 11:03:36.660196 best dqsien dly found for B0: ( 0, 13, 12)
4275 11:03:36.660272 Total UI for P1: 0, mck2ui 16
4276 11:03:36.666707 best dqsien dly found for B1: ( 0, 13, 14)
4277 11:03:36.669997 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4278 11:03:36.673373 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4279 11:03:36.673449
4280 11:03:36.677029 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4281 11:03:36.680010 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4282 11:03:36.683585 [Gating] SW calibration Done
4283 11:03:36.683660 ==
4284 11:03:36.686822 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 11:03:36.690147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 11:03:36.690223 ==
4287 11:03:36.693497 RX Vref Scan: 0
4288 11:03:36.693572
4289 11:03:36.693630 RX Vref 0 -> 0, step: 1
4290 11:03:36.693685
4291 11:03:36.696850 RX Delay -230 -> 252, step: 16
4292 11:03:36.700557 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4293 11:03:36.706855 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4294 11:03:36.710368 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4295 11:03:36.713723 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4296 11:03:36.716968 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4297 11:03:36.720285 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4298 11:03:36.726976 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4299 11:03:36.730651 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4300 11:03:36.733800 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4301 11:03:36.737012 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4302 11:03:36.743645 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4303 11:03:36.746889 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4304 11:03:36.750465 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4305 11:03:36.753846 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4306 11:03:36.760256 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4307 11:03:36.763519 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4308 11:03:36.763595 ==
4309 11:03:36.766864 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 11:03:36.770116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 11:03:36.770192 ==
4312 11:03:36.773440 DQS Delay:
4313 11:03:36.773515 DQS0 = 0, DQS1 = 0
4314 11:03:36.773573 DQM Delay:
4315 11:03:36.777167 DQM0 = 47, DQM1 = 42
4316 11:03:36.777242 DQ Delay:
4317 11:03:36.780447 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4318 11:03:36.783750 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4319 11:03:36.786987 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4320 11:03:36.790325 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4321 11:03:36.790401
4322 11:03:36.790460
4323 11:03:36.790514 ==
4324 11:03:36.793526 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 11:03:36.800189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 11:03:36.800265 ==
4327 11:03:36.800323
4328 11:03:36.800377
4329 11:03:36.800427 TX Vref Scan disable
4330 11:03:36.803716 == TX Byte 0 ==
4331 11:03:36.807056 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4332 11:03:36.813744 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4333 11:03:36.813823 == TX Byte 1 ==
4334 11:03:36.817040 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4335 11:03:36.823415 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4336 11:03:36.823491 ==
4337 11:03:36.827054 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 11:03:36.830455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 11:03:36.830531 ==
4340 11:03:36.830589
4341 11:03:36.830642
4342 11:03:36.833582 TX Vref Scan disable
4343 11:03:36.836844 == TX Byte 0 ==
4344 11:03:36.840030 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4345 11:03:36.843788 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4346 11:03:36.843863 == TX Byte 1 ==
4347 11:03:36.850068 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4348 11:03:36.853587 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4349 11:03:36.853662
4350 11:03:36.853720 [DATLAT]
4351 11:03:36.856927 Freq=600, CH0 RK1
4352 11:03:36.857001
4353 11:03:36.857059 DATLAT Default: 0x9
4354 11:03:36.860132 0, 0xFFFF, sum = 0
4355 11:03:36.860208 1, 0xFFFF, sum = 0
4356 11:03:36.863398 2, 0xFFFF, sum = 0
4357 11:03:36.866933 3, 0xFFFF, sum = 0
4358 11:03:36.867009 4, 0xFFFF, sum = 0
4359 11:03:36.870234 5, 0xFFFF, sum = 0
4360 11:03:36.870310 6, 0xFFFF, sum = 0
4361 11:03:36.873544 7, 0xFFFF, sum = 0
4362 11:03:36.873634 8, 0x0, sum = 1
4363 11:03:36.873694 9, 0x0, sum = 2
4364 11:03:36.876983 10, 0x0, sum = 3
4365 11:03:36.877060 11, 0x0, sum = 4
4366 11:03:36.880206 best_step = 9
4367 11:03:36.880281
4368 11:03:36.880339 ==
4369 11:03:36.883427 Dram Type= 6, Freq= 0, CH_0, rank 1
4370 11:03:36.886809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 11:03:36.886884 ==
4372 11:03:36.890432 RX Vref Scan: 0
4373 11:03:36.890506
4374 11:03:36.890563 RX Vref 0 -> 0, step: 1
4375 11:03:36.890615
4376 11:03:36.893644 RX Delay -179 -> 252, step: 8
4377 11:03:36.900653 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4378 11:03:36.904194 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4379 11:03:36.907535 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4380 11:03:36.911139 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4381 11:03:36.914133 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4382 11:03:36.920975 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4383 11:03:36.923916 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4384 11:03:36.927671 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4385 11:03:36.930731 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4386 11:03:36.934013 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4387 11:03:36.940938 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4388 11:03:36.944160 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4389 11:03:36.947548 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4390 11:03:36.951122 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4391 11:03:36.957431 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4392 11:03:36.960878 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4393 11:03:36.960972 ==
4394 11:03:36.964198 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 11:03:36.967541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 11:03:36.967606 ==
4397 11:03:36.967663 DQS Delay:
4398 11:03:36.971160 DQS0 = 0, DQS1 = 0
4399 11:03:36.971226 DQM Delay:
4400 11:03:36.974102 DQM0 = 48, DQM1 = 40
4401 11:03:36.974162 DQ Delay:
4402 11:03:36.977433 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4403 11:03:36.980793 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4404 11:03:36.984020 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4405 11:03:36.987713 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4406 11:03:36.987789
4407 11:03:36.987846
4408 11:03:36.997336 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4409 11:03:36.997440 CH0 RK1: MR19=808, MR18=6F3C
4410 11:03:37.004260 CH0_RK1: MR19=0x808, MR18=0x6F3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4411 11:03:37.007517 [RxdqsGatingPostProcess] freq 600
4412 11:03:37.014039 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4413 11:03:37.017253 Pre-setting of DQS Precalculation
4414 11:03:37.020852 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4415 11:03:37.020945 ==
4416 11:03:37.024041 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 11:03:37.027375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 11:03:37.030824 ==
4419 11:03:37.034043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 11:03:37.040702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4421 11:03:37.044276 [CA 0] Center 35 (5~66) winsize 62
4422 11:03:37.047417 [CA 1] Center 35 (5~66) winsize 62
4423 11:03:37.050639 [CA 2] Center 34 (4~65) winsize 62
4424 11:03:37.054006 [CA 3] Center 33 (3~64) winsize 62
4425 11:03:37.057578 [CA 4] Center 34 (3~65) winsize 63
4426 11:03:37.060740 [CA 5] Center 33 (3~64) winsize 62
4427 11:03:37.060834
4428 11:03:37.064213 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4429 11:03:37.064278
4430 11:03:37.067531 [CATrainingPosCal] consider 1 rank data
4431 11:03:37.071334 u2DelayCellTimex100 = 270/100 ps
4432 11:03:37.074223 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 11:03:37.077434 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4434 11:03:37.081066 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 11:03:37.083884 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 11:03:37.090554 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4437 11:03:37.094156 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 11:03:37.094247
4439 11:03:37.097454 CA PerBit enable=1, Macro0, CA PI delay=33
4440 11:03:37.097549
4441 11:03:37.100769 [CBTSetCACLKResult] CA Dly = 33
4442 11:03:37.100862 CS Dly: 5 (0~36)
4443 11:03:37.100943 ==
4444 11:03:37.104076 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 11:03:37.110391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 11:03:37.110479 ==
4447 11:03:37.113747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4448 11:03:37.120486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4449 11:03:37.123949 [CA 0] Center 35 (5~66) winsize 62
4450 11:03:37.127395 [CA 1] Center 35 (5~66) winsize 62
4451 11:03:37.130205 [CA 2] Center 34 (3~65) winsize 63
4452 11:03:37.133575 [CA 3] Center 34 (3~65) winsize 63
4453 11:03:37.137175 [CA 4] Center 34 (4~64) winsize 61
4454 11:03:37.140465 [CA 5] Center 33 (3~64) winsize 62
4455 11:03:37.140557
4456 11:03:37.143753 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4457 11:03:37.143846
4458 11:03:37.146825 [CATrainingPosCal] consider 2 rank data
4459 11:03:37.150532 u2DelayCellTimex100 = 270/100 ps
4460 11:03:37.153757 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4461 11:03:37.157006 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4462 11:03:37.160570 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 11:03:37.166898 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 11:03:37.170484 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4465 11:03:37.173775 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4466 11:03:37.173869
4467 11:03:37.177053 CA PerBit enable=1, Macro0, CA PI delay=33
4468 11:03:37.177159
4469 11:03:37.180170 [CBTSetCACLKResult] CA Dly = 33
4470 11:03:37.180256 CS Dly: 6 (0~38)
4471 11:03:37.180344
4472 11:03:37.183680 ----->DramcWriteLeveling(PI) begin...
4473 11:03:37.186956 ==
4474 11:03:37.187026 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 11:03:37.193447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 11:03:37.193541 ==
4477 11:03:37.196702 Write leveling (Byte 0): 29 => 29
4478 11:03:37.199968 Write leveling (Byte 1): 32 => 32
4479 11:03:37.203227 DramcWriteLeveling(PI) end<-----
4480 11:03:37.203320
4481 11:03:37.203401 ==
4482 11:03:37.206542 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 11:03:37.209803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 11:03:37.209890 ==
4485 11:03:37.213070 [Gating] SW mode calibration
4486 11:03:37.220162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4487 11:03:37.223356 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4488 11:03:37.230198 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 11:03:37.233346 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4490 11:03:37.236751 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4491 11:03:37.243155 0 9 12 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4492 11:03:37.246431 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 11:03:37.249799 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 11:03:37.256554 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 11:03:37.259706 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 11:03:37.262919 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 11:03:37.269616 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 11:03:37.273325 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4499 11:03:37.276406 0 10 12 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
4500 11:03:37.282939 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 11:03:37.286574 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 11:03:37.289861 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 11:03:37.296214 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:03:37.299556 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 11:03:37.303360 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 11:03:37.309954 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4507 11:03:37.313257 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4508 11:03:37.316492 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:03:37.323194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:03:37.326512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:03:37.329633 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:03:37.336312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:03:37.339568 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:03:37.343071 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:03:37.349383 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:03:37.352868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:03:37.356357 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:03:37.359390 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:03:37.366033 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:03:37.369662 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:03:37.372772 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:03:37.379450 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:03:37.383263 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4524 11:03:37.386549 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 11:03:37.389766 Total UI for P1: 0, mck2ui 16
4526 11:03:37.393150 best dqsien dly found for B0: ( 0, 13, 12)
4527 11:03:37.396437 Total UI for P1: 0, mck2ui 16
4528 11:03:37.399757 best dqsien dly found for B1: ( 0, 13, 12)
4529 11:03:37.403259 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4530 11:03:37.406200 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4531 11:03:37.406268
4532 11:03:37.413199 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4533 11:03:37.416508 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4534 11:03:37.416599 [Gating] SW calibration Done
4535 11:03:37.419702 ==
4536 11:03:37.422992 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 11:03:37.426333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 11:03:37.426426 ==
4539 11:03:37.426509 RX Vref Scan: 0
4540 11:03:37.426588
4541 11:03:37.429610 RX Vref 0 -> 0, step: 1
4542 11:03:37.429681
4543 11:03:37.432927 RX Delay -230 -> 252, step: 16
4544 11:03:37.436201 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4545 11:03:37.439599 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4546 11:03:37.446301 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4547 11:03:37.449438 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4548 11:03:37.453284 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4549 11:03:37.456438 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4550 11:03:37.459568 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4551 11:03:37.466297 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4552 11:03:37.469809 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4553 11:03:37.473053 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4554 11:03:37.476257 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4555 11:03:37.482870 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4556 11:03:37.486140 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4557 11:03:37.489396 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4558 11:03:37.492766 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4559 11:03:37.496525 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4560 11:03:37.499590 ==
4561 11:03:37.502947 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 11:03:37.506119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 11:03:37.506214 ==
4564 11:03:37.506297 DQS Delay:
4565 11:03:37.509690 DQS0 = 0, DQS1 = 0
4566 11:03:37.509817 DQM Delay:
4567 11:03:37.512802 DQM0 = 54, DQM1 = 46
4568 11:03:37.512915 DQ Delay:
4569 11:03:37.516523 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4570 11:03:37.519303 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4571 11:03:37.522859 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4572 11:03:37.526364 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4573 11:03:37.526439
4574 11:03:37.526496
4575 11:03:37.526550 ==
4576 11:03:37.529571 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 11:03:37.532929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 11:03:37.533029 ==
4579 11:03:37.533114
4580 11:03:37.533214
4581 11:03:37.536556 TX Vref Scan disable
4582 11:03:37.539800 == TX Byte 0 ==
4583 11:03:37.543024 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4584 11:03:37.546231 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4585 11:03:37.549649 == TX Byte 1 ==
4586 11:03:37.552714 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4587 11:03:37.556024 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4588 11:03:37.556099 ==
4589 11:03:37.559400 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 11:03:37.566143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 11:03:37.566219 ==
4592 11:03:37.566277
4593 11:03:37.566353
4594 11:03:37.566418 TX Vref Scan disable
4595 11:03:37.570032 == TX Byte 0 ==
4596 11:03:37.573432 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4597 11:03:37.579980 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4598 11:03:37.580056 == TX Byte 1 ==
4599 11:03:37.583261 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4600 11:03:37.589928 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4601 11:03:37.590004
4602 11:03:37.590064 [DATLAT]
4603 11:03:37.590128 Freq=600, CH1 RK0
4604 11:03:37.590211
4605 11:03:37.593375 DATLAT Default: 0x9
4606 11:03:37.593450 0, 0xFFFF, sum = 0
4607 11:03:37.596754 1, 0xFFFF, sum = 0
4608 11:03:37.600007 2, 0xFFFF, sum = 0
4609 11:03:37.600083 3, 0xFFFF, sum = 0
4610 11:03:37.603331 4, 0xFFFF, sum = 0
4611 11:03:37.603408 5, 0xFFFF, sum = 0
4612 11:03:37.606669 6, 0xFFFF, sum = 0
4613 11:03:37.606745 7, 0xFFFF, sum = 0
4614 11:03:37.609888 8, 0x0, sum = 1
4615 11:03:37.609965 9, 0x0, sum = 2
4616 11:03:37.610024 10, 0x0, sum = 3
4617 11:03:37.612997 11, 0x0, sum = 4
4618 11:03:37.613073 best_step = 9
4619 11:03:37.613157
4620 11:03:37.613226 ==
4621 11:03:37.616599 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 11:03:37.623394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 11:03:37.623471 ==
4624 11:03:37.623530 RX Vref Scan: 1
4625 11:03:37.623584
4626 11:03:37.626310 RX Vref 0 -> 0, step: 1
4627 11:03:37.626408
4628 11:03:37.630112 RX Delay -163 -> 252, step: 8
4629 11:03:37.630211
4630 11:03:37.633370 Set Vref, RX VrefLevel [Byte0]: 54
4631 11:03:37.636629 [Byte1]: 53
4632 11:03:37.636703
4633 11:03:37.639867 Final RX Vref Byte 0 = 54 to rank0
4634 11:03:37.643212 Final RX Vref Byte 1 = 53 to rank0
4635 11:03:37.646423 Final RX Vref Byte 0 = 54 to rank1
4636 11:03:37.649968 Final RX Vref Byte 1 = 53 to rank1==
4637 11:03:37.653455 Dram Type= 6, Freq= 0, CH_1, rank 0
4638 11:03:37.656611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 11:03:37.656686 ==
4640 11:03:37.660006 DQS Delay:
4641 11:03:37.660081 DQS0 = 0, DQS1 = 0
4642 11:03:37.660138 DQM Delay:
4643 11:03:37.663239 DQM0 = 48, DQM1 = 42
4644 11:03:37.663314 DQ Delay:
4645 11:03:37.666552 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4646 11:03:37.670056 DQ4 =48, DQ5 =56, DQ6 =60, DQ7 =44
4647 11:03:37.673218 DQ8 =32, DQ9 =28, DQ10 =44, DQ11 =36
4648 11:03:37.676559 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4649 11:03:37.676634
4650 11:03:37.676692
4651 11:03:37.686875 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f77, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4652 11:03:37.686960 CH1 RK0: MR19=808, MR18=4F77
4653 11:03:37.693248 CH1_RK0: MR19=0x808, MR18=0x4F77, DQSOSC=387, MR23=63, INC=175, DEC=116
4654 11:03:37.693325
4655 11:03:37.696550 ----->DramcWriteLeveling(PI) begin...
4656 11:03:37.699877 ==
4657 11:03:37.703281 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 11:03:37.706458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 11:03:37.706538 ==
4660 11:03:37.709997 Write leveling (Byte 0): 30 => 30
4661 11:03:37.713268 Write leveling (Byte 1): 30 => 30
4662 11:03:37.716521 DramcWriteLeveling(PI) end<-----
4663 11:03:37.716645
4664 11:03:37.716719 ==
4665 11:03:37.719789 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 11:03:37.723226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 11:03:37.723302 ==
4668 11:03:37.726674 [Gating] SW mode calibration
4669 11:03:37.732965 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4670 11:03:37.736395 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4671 11:03:37.743035 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 11:03:37.746459 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 11:03:37.749654 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4674 11:03:37.756518 0 9 12 | B1->B0 | 2525 3131 | 0 1 | (0 0) (1 0)
4675 11:03:37.759477 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 11:03:37.763218 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 11:03:37.769899 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 11:03:37.773039 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 11:03:37.776475 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 11:03:37.783082 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 11:03:37.786073 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4682 11:03:37.789461 0 10 12 | B1->B0 | 3939 3131 | 0 0 | (0 0) (0 0)
4683 11:03:37.796223 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 11:03:37.799282 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 11:03:37.802818 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 11:03:37.809320 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 11:03:37.813092 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 11:03:37.816307 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 11:03:37.823036 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:03:37.826140 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4691 11:03:37.829332 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:03:37.835921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:03:37.839668 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:03:37.842586 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:03:37.849561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:03:37.852969 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:03:37.856197 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:03:37.859580 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:03:37.866478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:03:37.869947 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:03:37.872772 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:03:37.879405 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:03:37.882884 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:03:37.886187 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:03:37.892719 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:03:37.896244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 11:03:37.899338 Total UI for P1: 0, mck2ui 16
4708 11:03:37.902874 best dqsien dly found for B0: ( 0, 13, 10)
4709 11:03:37.906000 Total UI for P1: 0, mck2ui 16
4710 11:03:37.909807 best dqsien dly found for B1: ( 0, 13, 10)
4711 11:03:37.912901 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4712 11:03:37.916069 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4713 11:03:37.916147
4714 11:03:37.919687 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4715 11:03:37.922960 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4716 11:03:37.926136 [Gating] SW calibration Done
4717 11:03:37.926212 ==
4718 11:03:37.929252 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 11:03:37.932982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 11:03:37.936274 ==
4721 11:03:37.936351 RX Vref Scan: 0
4722 11:03:37.936410
4723 11:03:37.939474 RX Vref 0 -> 0, step: 1
4724 11:03:37.939551
4725 11:03:37.942471 RX Delay -230 -> 252, step: 16
4726 11:03:37.946119 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4727 11:03:37.949270 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4728 11:03:37.952595 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4729 11:03:37.959414 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4730 11:03:37.962523 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4731 11:03:37.965856 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4732 11:03:37.969342 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4733 11:03:37.972607 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4734 11:03:37.979148 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4735 11:03:37.982379 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4736 11:03:37.985598 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4737 11:03:37.989272 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4738 11:03:37.995740 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4739 11:03:37.999138 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4740 11:03:38.002498 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4741 11:03:38.005491 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4742 11:03:38.005569 ==
4743 11:03:38.009270 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 11:03:38.015587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 11:03:38.015663 ==
4746 11:03:38.015721 DQS Delay:
4747 11:03:38.018996 DQS0 = 0, DQS1 = 0
4748 11:03:38.019085 DQM Delay:
4749 11:03:38.019142 DQM0 = 51, DQM1 = 43
4750 11:03:38.022192 DQ Delay:
4751 11:03:38.025889 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4752 11:03:38.029158 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4753 11:03:38.032706 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4754 11:03:38.035742 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4755 11:03:38.035817
4756 11:03:38.035875
4757 11:03:38.035928 ==
4758 11:03:38.039113 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 11:03:38.042419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 11:03:38.042494 ==
4761 11:03:38.042552
4762 11:03:38.042604
4763 11:03:38.045739 TX Vref Scan disable
4764 11:03:38.045813 == TX Byte 0 ==
4765 11:03:38.052106 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4766 11:03:38.055445 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4767 11:03:38.055537 == TX Byte 1 ==
4768 11:03:38.062329 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4769 11:03:38.065546 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4770 11:03:38.065621 ==
4771 11:03:38.068953 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 11:03:38.072569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 11:03:38.072644 ==
4774 11:03:38.072703
4775 11:03:38.072756
4776 11:03:38.075443 TX Vref Scan disable
4777 11:03:38.078936 == TX Byte 0 ==
4778 11:03:38.082103 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4779 11:03:38.089154 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4780 11:03:38.089243 == TX Byte 1 ==
4781 11:03:38.092507 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4782 11:03:38.095791 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4783 11:03:38.095867
4784 11:03:38.099052 [DATLAT]
4785 11:03:38.099128 Freq=600, CH1 RK1
4786 11:03:38.099186
4787 11:03:38.102361 DATLAT Default: 0x9
4788 11:03:38.102435 0, 0xFFFF, sum = 0
4789 11:03:38.106145 1, 0xFFFF, sum = 0
4790 11:03:38.106222 2, 0xFFFF, sum = 0
4791 11:03:38.109135 3, 0xFFFF, sum = 0
4792 11:03:38.109226 4, 0xFFFF, sum = 0
4793 11:03:38.112501 5, 0xFFFF, sum = 0
4794 11:03:38.112577 6, 0xFFFF, sum = 0
4795 11:03:38.115661 7, 0xFFFF, sum = 0
4796 11:03:38.115737 8, 0x0, sum = 1
4797 11:03:38.118897 9, 0x0, sum = 2
4798 11:03:38.118973 10, 0x0, sum = 3
4799 11:03:38.122427 11, 0x0, sum = 4
4800 11:03:38.122504 best_step = 9
4801 11:03:38.122562
4802 11:03:38.122615 ==
4803 11:03:38.125695 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 11:03:38.132428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 11:03:38.132504 ==
4806 11:03:38.132562 RX Vref Scan: 0
4807 11:03:38.132617
4808 11:03:38.135550 RX Vref 0 -> 0, step: 1
4809 11:03:38.135625
4810 11:03:38.138844 RX Delay -179 -> 252, step: 8
4811 11:03:38.142162 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4812 11:03:38.145670 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4813 11:03:38.152181 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4814 11:03:38.155568 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4815 11:03:38.158583 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4816 11:03:38.162122 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4817 11:03:38.168594 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4818 11:03:38.171990 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4819 11:03:38.175133 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4820 11:03:38.178374 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4821 11:03:38.182104 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4822 11:03:38.188306 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4823 11:03:38.191863 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4824 11:03:38.195152 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4825 11:03:38.198416 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4826 11:03:38.204955 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4827 11:03:38.205031 ==
4828 11:03:38.208229 Dram Type= 6, Freq= 0, CH_1, rank 1
4829 11:03:38.211916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4830 11:03:38.211992 ==
4831 11:03:38.212050 DQS Delay:
4832 11:03:38.215344 DQS0 = 0, DQS1 = 0
4833 11:03:38.215419 DQM Delay:
4834 11:03:38.218148 DQM0 = 49, DQM1 = 43
4835 11:03:38.218224 DQ Delay:
4836 11:03:38.221564 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4837 11:03:38.224847 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4838 11:03:38.228148 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4839 11:03:38.231443 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4840 11:03:38.231519
4841 11:03:38.231576
4842 11:03:38.238476 [DQSOSCAuto] RK1, (LSB)MR18= 0x6229, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4843 11:03:38.241596 CH1 RK1: MR19=808, MR18=6229
4844 11:03:38.247975 CH1_RK1: MR19=0x808, MR18=0x6229, DQSOSC=391, MR23=63, INC=171, DEC=114
4845 11:03:38.251402 [RxdqsGatingPostProcess] freq 600
4846 11:03:38.258064 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4847 11:03:38.261294 Pre-setting of DQS Precalculation
4848 11:03:38.264609 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4849 11:03:38.271302 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4850 11:03:38.278019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4851 11:03:38.278094
4852 11:03:38.278154
4853 11:03:38.281343 [Calibration Summary] 1200 Mbps
4854 11:03:38.284600 CH 0, Rank 0
4855 11:03:38.284674 SW Impedance : PASS
4856 11:03:38.287757 DUTY Scan : NO K
4857 11:03:38.290927 ZQ Calibration : PASS
4858 11:03:38.291002 Jitter Meter : NO K
4859 11:03:38.294184 CBT Training : PASS
4860 11:03:38.297826 Write leveling : PASS
4861 11:03:38.297901 RX DQS gating : PASS
4862 11:03:38.300943 RX DQ/DQS(RDDQC) : PASS
4863 11:03:38.304242 TX DQ/DQS : PASS
4864 11:03:38.304318 RX DATLAT : PASS
4865 11:03:38.307553 RX DQ/DQS(Engine): PASS
4866 11:03:38.307629 TX OE : NO K
4867 11:03:38.311245 All Pass.
4868 11:03:38.311321
4869 11:03:38.311378 CH 0, Rank 1
4870 11:03:38.314363 SW Impedance : PASS
4871 11:03:38.314439 DUTY Scan : NO K
4872 11:03:38.317937 ZQ Calibration : PASS
4873 11:03:38.320951 Jitter Meter : NO K
4874 11:03:38.321026 CBT Training : PASS
4875 11:03:38.324296 Write leveling : PASS
4876 11:03:38.327527 RX DQS gating : PASS
4877 11:03:38.327602 RX DQ/DQS(RDDQC) : PASS
4878 11:03:38.330848 TX DQ/DQS : PASS
4879 11:03:38.334586 RX DATLAT : PASS
4880 11:03:38.334661 RX DQ/DQS(Engine): PASS
4881 11:03:38.337803 TX OE : NO K
4882 11:03:38.337878 All Pass.
4883 11:03:38.337937
4884 11:03:38.341004 CH 1, Rank 0
4885 11:03:38.341079 SW Impedance : PASS
4886 11:03:38.344152 DUTY Scan : NO K
4887 11:03:38.347719 ZQ Calibration : PASS
4888 11:03:38.347794 Jitter Meter : NO K
4889 11:03:38.350802 CBT Training : PASS
4890 11:03:38.353977 Write leveling : PASS
4891 11:03:38.354071 RX DQS gating : PASS
4892 11:03:38.357516 RX DQ/DQS(RDDQC) : PASS
4893 11:03:38.357638 TX DQ/DQS : PASS
4894 11:03:38.360651 RX DATLAT : PASS
4895 11:03:38.363966 RX DQ/DQS(Engine): PASS
4896 11:03:38.364093 TX OE : NO K
4897 11:03:38.367415 All Pass.
4898 11:03:38.367490
4899 11:03:38.367548 CH 1, Rank 1
4900 11:03:38.370726 SW Impedance : PASS
4901 11:03:38.370801 DUTY Scan : NO K
4902 11:03:38.373938 ZQ Calibration : PASS
4903 11:03:38.377332 Jitter Meter : NO K
4904 11:03:38.377408 CBT Training : PASS
4905 11:03:38.380682 Write leveling : PASS
4906 11:03:38.384049 RX DQS gating : PASS
4907 11:03:38.384124 RX DQ/DQS(RDDQC) : PASS
4908 11:03:38.387108 TX DQ/DQS : PASS
4909 11:03:38.390816 RX DATLAT : PASS
4910 11:03:38.390892 RX DQ/DQS(Engine): PASS
4911 11:03:38.393892 TX OE : NO K
4912 11:03:38.393968 All Pass.
4913 11:03:38.394026
4914 11:03:38.397261 DramC Write-DBI off
4915 11:03:38.400935 PER_BANK_REFRESH: Hybrid Mode
4916 11:03:38.401010 TX_TRACKING: ON
4917 11:03:38.410535 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4918 11:03:38.414181 [FAST_K] Save calibration result to emmc
4919 11:03:38.417401 dramc_set_vcore_voltage set vcore to 662500
4920 11:03:38.420858 Read voltage for 933, 3
4921 11:03:38.420932 Vio18 = 0
4922 11:03:38.420990 Vcore = 662500
4923 11:03:38.424254 Vdram = 0
4924 11:03:38.424328 Vddq = 0
4925 11:03:38.424387 Vmddr = 0
4926 11:03:38.430787 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4927 11:03:38.434151 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4928 11:03:38.437506 MEM_TYPE=3, freq_sel=17
4929 11:03:38.440679 sv_algorithm_assistance_LP4_1600
4930 11:03:38.443892 ============ PULL DRAM RESETB DOWN ============
4931 11:03:38.447510 ========== PULL DRAM RESETB DOWN end =========
4932 11:03:38.453978 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4933 11:03:38.457131 ===================================
4934 11:03:38.457220 LPDDR4 DRAM CONFIGURATION
4935 11:03:38.460832 ===================================
4936 11:03:38.464026 EX_ROW_EN[0] = 0x0
4937 11:03:38.467264 EX_ROW_EN[1] = 0x0
4938 11:03:38.467338 LP4Y_EN = 0x0
4939 11:03:38.470781 WORK_FSP = 0x0
4940 11:03:38.470856 WL = 0x3
4941 11:03:38.473992 RL = 0x3
4942 11:03:38.474067 BL = 0x2
4943 11:03:38.477251 RPST = 0x0
4944 11:03:38.477326 RD_PRE = 0x0
4945 11:03:38.480789 WR_PRE = 0x1
4946 11:03:38.480863 WR_PST = 0x0
4947 11:03:38.483795 DBI_WR = 0x0
4948 11:03:38.483870 DBI_RD = 0x0
4949 11:03:38.487131 OTF = 0x1
4950 11:03:38.490666 ===================================
4951 11:03:38.493927 ===================================
4952 11:03:38.494003 ANA top config
4953 11:03:38.497132 ===================================
4954 11:03:38.500429 DLL_ASYNC_EN = 0
4955 11:03:38.504001 ALL_SLAVE_EN = 1
4956 11:03:38.504077 NEW_RANK_MODE = 1
4957 11:03:38.507061 DLL_IDLE_MODE = 1
4958 11:03:38.510732 LP45_APHY_COMB_EN = 1
4959 11:03:38.513885 TX_ODT_DIS = 1
4960 11:03:38.517176 NEW_8X_MODE = 1
4961 11:03:38.520424 ===================================
4962 11:03:38.523974 ===================================
4963 11:03:38.524050 data_rate = 1866
4964 11:03:38.526949 CKR = 1
4965 11:03:38.530263 DQ_P2S_RATIO = 8
4966 11:03:38.533896 ===================================
4967 11:03:38.537169 CA_P2S_RATIO = 8
4968 11:03:38.540541 DQ_CA_OPEN = 0
4969 11:03:38.543659 DQ_SEMI_OPEN = 0
4970 11:03:38.543755 CA_SEMI_OPEN = 0
4971 11:03:38.547050 CA_FULL_RATE = 0
4972 11:03:38.550233 DQ_CKDIV4_EN = 1
4973 11:03:38.553854 CA_CKDIV4_EN = 1
4974 11:03:38.557091 CA_PREDIV_EN = 0
4975 11:03:38.560187 PH8_DLY = 0
4976 11:03:38.560327 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4977 11:03:38.563489 DQ_AAMCK_DIV = 4
4978 11:03:38.567250 CA_AAMCK_DIV = 4
4979 11:03:38.570600 CA_ADMCK_DIV = 4
4980 11:03:38.573951 DQ_TRACK_CA_EN = 0
4981 11:03:38.577017 CA_PICK = 933
4982 11:03:38.577120 CA_MCKIO = 933
4983 11:03:38.580720 MCKIO_SEMI = 0
4984 11:03:38.583552 PLL_FREQ = 3732
4985 11:03:38.586843 DQ_UI_PI_RATIO = 32
4986 11:03:38.590424 CA_UI_PI_RATIO = 0
4987 11:03:38.593425 ===================================
4988 11:03:38.597028 ===================================
4989 11:03:38.600143 memory_type:LPDDR4
4990 11:03:38.600212 GP_NUM : 10
4991 11:03:38.603548 SRAM_EN : 1
4992 11:03:38.603615 MD32_EN : 0
4993 11:03:38.606846 ===================================
4994 11:03:38.610410 [ANA_INIT] >>>>>>>>>>>>>>
4995 11:03:38.613675 <<<<<< [CONFIGURE PHASE]: ANA_TX
4996 11:03:38.616854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4997 11:03:38.620372 ===================================
4998 11:03:38.623741 data_rate = 1866,PCW = 0X8f00
4999 11:03:38.627020 ===================================
5000 11:03:38.629923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5001 11:03:38.636775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 11:03:38.639996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5003 11:03:38.646732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5004 11:03:38.649965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5005 11:03:38.653784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5006 11:03:38.653862 [ANA_INIT] flow start
5007 11:03:38.656601 [ANA_INIT] PLL >>>>>>>>
5008 11:03:38.660315 [ANA_INIT] PLL <<<<<<<<
5009 11:03:38.660392 [ANA_INIT] MIDPI >>>>>>>>
5010 11:03:38.663341 [ANA_INIT] MIDPI <<<<<<<<
5011 11:03:38.666883 [ANA_INIT] DLL >>>>>>>>
5012 11:03:38.666960 [ANA_INIT] flow end
5013 11:03:38.673441 ============ LP4 DIFF to SE enter ============
5014 11:03:38.676677 ============ LP4 DIFF to SE exit ============
5015 11:03:38.676754 [ANA_INIT] <<<<<<<<<<<<<
5016 11:03:38.680039 [Flow] Enable top DCM control >>>>>
5017 11:03:38.683307 [Flow] Enable top DCM control <<<<<
5018 11:03:38.686566 Enable DLL master slave shuffle
5019 11:03:38.693350 ==============================================================
5020 11:03:38.696569 Gating Mode config
5021 11:03:38.699927 ==============================================================
5022 11:03:38.703230 Config description:
5023 11:03:38.713097 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5024 11:03:38.720061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5025 11:03:38.723265 SELPH_MODE 0: By rank 1: By Phase
5026 11:03:38.730203 ==============================================================
5027 11:03:38.733187 GAT_TRACK_EN = 1
5028 11:03:38.736927 RX_GATING_MODE = 2
5029 11:03:38.737003 RX_GATING_TRACK_MODE = 2
5030 11:03:38.740024 SELPH_MODE = 1
5031 11:03:38.743324 PICG_EARLY_EN = 1
5032 11:03:38.746462 VALID_LAT_VALUE = 1
5033 11:03:38.753456 ==============================================================
5034 11:03:38.756953 Enter into Gating configuration >>>>
5035 11:03:38.760276 Exit from Gating configuration <<<<
5036 11:03:38.763500 Enter into DVFS_PRE_config >>>>>
5037 11:03:38.773605 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5038 11:03:38.776808 Exit from DVFS_PRE_config <<<<<
5039 11:03:38.779890 Enter into PICG configuration >>>>
5040 11:03:38.783110 Exit from PICG configuration <<<<
5041 11:03:38.786750 [RX_INPUT] configuration >>>>>
5042 11:03:38.789951 [RX_INPUT] configuration <<<<<
5043 11:03:38.793260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5044 11:03:38.799864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5045 11:03:38.806598 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 11:03:38.809785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 11:03:38.816506 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 11:03:38.823255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 11:03:38.826780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5050 11:03:38.833122 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5051 11:03:38.836765 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5052 11:03:38.839771 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5053 11:03:38.843488 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5054 11:03:38.849990 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 11:03:38.853277 ===================================
5056 11:03:38.853353 LPDDR4 DRAM CONFIGURATION
5057 11:03:38.856433 ===================================
5058 11:03:38.859731 EX_ROW_EN[0] = 0x0
5059 11:03:38.862949 EX_ROW_EN[1] = 0x0
5060 11:03:38.863024 LP4Y_EN = 0x0
5061 11:03:38.866734 WORK_FSP = 0x0
5062 11:03:38.866808 WL = 0x3
5063 11:03:38.870053 RL = 0x3
5064 11:03:38.870128 BL = 0x2
5065 11:03:38.873148 RPST = 0x0
5066 11:03:38.873259 RD_PRE = 0x0
5067 11:03:38.876315 WR_PRE = 0x1
5068 11:03:38.876390 WR_PST = 0x0
5069 11:03:38.879677 DBI_WR = 0x0
5070 11:03:38.879751 DBI_RD = 0x0
5071 11:03:38.882999 OTF = 0x1
5072 11:03:38.886450 ===================================
5073 11:03:38.889735 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5074 11:03:38.892946 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5075 11:03:38.900037 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5076 11:03:38.903267 ===================================
5077 11:03:38.903342 LPDDR4 DRAM CONFIGURATION
5078 11:03:38.906445 ===================================
5079 11:03:38.909914 EX_ROW_EN[0] = 0x10
5080 11:03:38.909989 EX_ROW_EN[1] = 0x0
5081 11:03:38.913143 LP4Y_EN = 0x0
5082 11:03:38.916277 WORK_FSP = 0x0
5083 11:03:38.916352 WL = 0x3
5084 11:03:38.919717 RL = 0x3
5085 11:03:38.919792 BL = 0x2
5086 11:03:38.922943 RPST = 0x0
5087 11:03:38.923017 RD_PRE = 0x0
5088 11:03:38.926340 WR_PRE = 0x1
5089 11:03:38.926415 WR_PST = 0x0
5090 11:03:38.929590 DBI_WR = 0x0
5091 11:03:38.929689 DBI_RD = 0x0
5092 11:03:38.932938 OTF = 0x1
5093 11:03:38.936240 ===================================
5094 11:03:38.939776 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5095 11:03:38.945331 nWR fixed to 30
5096 11:03:38.948542 [ModeRegInit_LP4] CH0 RK0
5097 11:03:38.948617 [ModeRegInit_LP4] CH0 RK1
5098 11:03:38.952033 [ModeRegInit_LP4] CH1 RK0
5099 11:03:38.955351 [ModeRegInit_LP4] CH1 RK1
5100 11:03:38.955464 match AC timing 9
5101 11:03:38.961811 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5102 11:03:38.965155 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5103 11:03:38.968594 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5104 11:03:38.975216 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5105 11:03:38.978654 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5106 11:03:38.978730 ==
5107 11:03:38.981937 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 11:03:38.985018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 11:03:38.985122 ==
5110 11:03:38.992107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 11:03:38.998231 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5112 11:03:39.001541 [CA 0] Center 38 (7~69) winsize 63
5113 11:03:39.004763 [CA 1] Center 38 (7~69) winsize 63
5114 11:03:39.008362 [CA 2] Center 35 (5~65) winsize 61
5115 11:03:39.011777 [CA 3] Center 35 (5~65) winsize 61
5116 11:03:39.015066 [CA 4] Center 34 (4~64) winsize 61
5117 11:03:39.017997 [CA 5] Center 33 (3~63) winsize 61
5118 11:03:39.018073
5119 11:03:39.021700 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5120 11:03:39.021800
5121 11:03:39.024884 [CATrainingPosCal] consider 1 rank data
5122 11:03:39.028201 u2DelayCellTimex100 = 270/100 ps
5123 11:03:39.031271 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5124 11:03:39.034699 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5125 11:03:39.037873 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 11:03:39.041189 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5127 11:03:39.044721 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5128 11:03:39.051002 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5129 11:03:39.051147
5130 11:03:39.054684 CA PerBit enable=1, Macro0, CA PI delay=33
5131 11:03:39.054761
5132 11:03:39.057866 [CBTSetCACLKResult] CA Dly = 33
5133 11:03:39.057941 CS Dly: 6 (0~37)
5134 11:03:39.057999 ==
5135 11:03:39.061048 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 11:03:39.064560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 11:03:39.067736 ==
5138 11:03:39.071067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 11:03:39.077568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5140 11:03:39.081263 [CA 0] Center 38 (8~69) winsize 62
5141 11:03:39.084388 [CA 1] Center 38 (8~69) winsize 62
5142 11:03:39.087556 [CA 2] Center 36 (6~66) winsize 61
5143 11:03:39.090830 [CA 3] Center 35 (5~66) winsize 62
5144 11:03:39.094681 [CA 4] Center 34 (4~65) winsize 62
5145 11:03:39.097960 [CA 5] Center 34 (4~64) winsize 61
5146 11:03:39.098035
5147 11:03:39.101085 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5148 11:03:39.101196
5149 11:03:39.104516 [CATrainingPosCal] consider 2 rank data
5150 11:03:39.107769 u2DelayCellTimex100 = 270/100 ps
5151 11:03:39.110972 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5152 11:03:39.114419 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5153 11:03:39.117291 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5154 11:03:39.123955 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5155 11:03:39.127796 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5156 11:03:39.130980 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5157 11:03:39.131056
5158 11:03:39.134346 CA PerBit enable=1, Macro0, CA PI delay=33
5159 11:03:39.134421
5160 11:03:39.137282 [CBTSetCACLKResult] CA Dly = 33
5161 11:03:39.137357 CS Dly: 7 (0~39)
5162 11:03:39.137416
5163 11:03:39.140632 ----->DramcWriteLeveling(PI) begin...
5164 11:03:39.140730 ==
5165 11:03:39.144144 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 11:03:39.150885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 11:03:39.150961 ==
5168 11:03:39.153925 Write leveling (Byte 0): 33 => 33
5169 11:03:39.157649 Write leveling (Byte 1): 30 => 30
5170 11:03:39.157724 DramcWriteLeveling(PI) end<-----
5171 11:03:39.160596
5172 11:03:39.160679 ==
5173 11:03:39.163855 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 11:03:39.167498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 11:03:39.167574 ==
5176 11:03:39.170859 [Gating] SW mode calibration
5177 11:03:39.177442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5178 11:03:39.180630 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5179 11:03:39.187167 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5180 11:03:39.190700 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 11:03:39.193926 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 11:03:39.200757 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 11:03:39.204095 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 11:03:39.207400 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 11:03:39.213773 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5186 11:03:39.217454 0 14 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
5187 11:03:39.220410 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5188 11:03:39.227026 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:03:39.230584 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 11:03:39.233680 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 11:03:39.240748 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 11:03:39.244036 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 11:03:39.247172 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5194 11:03:39.253608 0 15 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
5195 11:03:39.257077 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5196 11:03:39.260325 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:03:39.267017 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:03:39.270026 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 11:03:39.273454 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 11:03:39.279996 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 11:03:39.283430 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 11:03:39.287193 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5203 11:03:39.293599 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5204 11:03:39.296736 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:03:39.299853 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:03:39.303282 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:03:39.310209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:03:39.313620 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:03:39.316880 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:03:39.323763 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:03:39.327024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:03:39.330374 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:03:39.336931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:03:39.340096 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:03:39.343409 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:03:39.350371 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5217 11:03:39.353552 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 11:03:39.356698 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5219 11:03:39.360065 Total UI for P1: 0, mck2ui 16
5220 11:03:39.363650 best dqsien dly found for B0: ( 1, 2, 22)
5221 11:03:39.370179 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5222 11:03:39.373581 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 11:03:39.376725 Total UI for P1: 0, mck2ui 16
5224 11:03:39.380287 best dqsien dly found for B1: ( 1, 2, 30)
5225 11:03:39.383540 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5226 11:03:39.386979 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5227 11:03:39.387055
5228 11:03:39.390379 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5229 11:03:39.393617 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5230 11:03:39.397141 [Gating] SW calibration Done
5231 11:03:39.397232 ==
5232 11:03:39.400245 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 11:03:39.403487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 11:03:39.403563 ==
5235 11:03:39.407052 RX Vref Scan: 0
5236 11:03:39.407127
5237 11:03:39.410460 RX Vref 0 -> 0, step: 1
5238 11:03:39.410536
5239 11:03:39.410594 RX Delay -80 -> 252, step: 8
5240 11:03:39.416734 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5241 11:03:39.420275 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5242 11:03:39.423499 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5243 11:03:39.426997 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5244 11:03:39.430554 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5245 11:03:39.433475 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5246 11:03:39.440271 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5247 11:03:39.443552 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5248 11:03:39.446868 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5249 11:03:39.450159 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5250 11:03:39.453523 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5251 11:03:39.456653 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5252 11:03:39.463284 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5253 11:03:39.466903 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5254 11:03:39.469965 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5255 11:03:39.473459 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5256 11:03:39.473534 ==
5257 11:03:39.476637 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:03:39.480187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:03:39.483482 ==
5260 11:03:39.483556 DQS Delay:
5261 11:03:39.483615 DQS0 = 0, DQS1 = 0
5262 11:03:39.486571 DQM Delay:
5263 11:03:39.486645 DQM0 = 105, DQM1 = 90
5264 11:03:39.489958 DQ Delay:
5265 11:03:39.493392 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5266 11:03:39.496775 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5267 11:03:39.499978 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5268 11:03:39.503287 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5269 11:03:39.503361
5270 11:03:39.503418
5271 11:03:39.503472 ==
5272 11:03:39.506864 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 11:03:39.510052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 11:03:39.510127 ==
5275 11:03:39.510185
5276 11:03:39.510237
5277 11:03:39.513304 TX Vref Scan disable
5278 11:03:39.513378 == TX Byte 0 ==
5279 11:03:39.520095 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5280 11:03:39.523158 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5281 11:03:39.523233 == TX Byte 1 ==
5282 11:03:39.529949 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5283 11:03:39.533252 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5284 11:03:39.533326 ==
5285 11:03:39.536820 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 11:03:39.539679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:03:39.539756 ==
5288 11:03:39.539814
5289 11:03:39.539867
5290 11:03:39.542965 TX Vref Scan disable
5291 11:03:39.546697 == TX Byte 0 ==
5292 11:03:39.549969 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5293 11:03:39.553341 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5294 11:03:39.556573 == TX Byte 1 ==
5295 11:03:39.559678 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5296 11:03:39.563112 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5297 11:03:39.563187
5298 11:03:39.566704 [DATLAT]
5299 11:03:39.566778 Freq=933, CH0 RK0
5300 11:03:39.566836
5301 11:03:39.569891 DATLAT Default: 0xd
5302 11:03:39.569965 0, 0xFFFF, sum = 0
5303 11:03:39.573046 1, 0xFFFF, sum = 0
5304 11:03:39.573183 2, 0xFFFF, sum = 0
5305 11:03:39.576346 3, 0xFFFF, sum = 0
5306 11:03:39.576445 4, 0xFFFF, sum = 0
5307 11:03:39.579786 5, 0xFFFF, sum = 0
5308 11:03:39.579889 6, 0xFFFF, sum = 0
5309 11:03:39.583086 7, 0xFFFF, sum = 0
5310 11:03:39.583188 8, 0xFFFF, sum = 0
5311 11:03:39.586253 9, 0xFFFF, sum = 0
5312 11:03:39.586332 10, 0x0, sum = 1
5313 11:03:39.589635 11, 0x0, sum = 2
5314 11:03:39.589748 12, 0x0, sum = 3
5315 11:03:39.593222 13, 0x0, sum = 4
5316 11:03:39.593309 best_step = 11
5317 11:03:39.593380
5318 11:03:39.593436 ==
5319 11:03:39.596479 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 11:03:39.602747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 11:03:39.602878 ==
5322 11:03:39.602982 RX Vref Scan: 1
5323 11:03:39.603065
5324 11:03:39.606166 RX Vref 0 -> 0, step: 1
5325 11:03:39.606264
5326 11:03:39.609617 RX Delay -53 -> 252, step: 4
5327 11:03:39.609716
5328 11:03:39.612938 Set Vref, RX VrefLevel [Byte0]: 58
5329 11:03:39.616209 [Byte1]: 49
5330 11:03:39.616280
5331 11:03:39.619550 Final RX Vref Byte 0 = 58 to rank0
5332 11:03:39.623031 Final RX Vref Byte 1 = 49 to rank0
5333 11:03:39.626283 Final RX Vref Byte 0 = 58 to rank1
5334 11:03:39.629538 Final RX Vref Byte 1 = 49 to rank1==
5335 11:03:39.632797 Dram Type= 6, Freq= 0, CH_0, rank 0
5336 11:03:39.636024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 11:03:39.636121 ==
5338 11:03:39.639459 DQS Delay:
5339 11:03:39.639552 DQS0 = 0, DQS1 = 0
5340 11:03:39.643077 DQM Delay:
5341 11:03:39.643169 DQM0 = 108, DQM1 = 92
5342 11:03:39.643255 DQ Delay:
5343 11:03:39.645977 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5344 11:03:39.649275 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =116
5345 11:03:39.652715 DQ8 =88, DQ9 =78, DQ10 =92, DQ11 =90
5346 11:03:39.659314 DQ12 =96, DQ13 =92, DQ14 =104, DQ15 =100
5347 11:03:39.659396
5348 11:03:39.659456
5349 11:03:39.666237 [DQSOSCAuto] RK0, (LSB)MR18= 0x2925, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
5350 11:03:39.669339 CH0 RK0: MR19=505, MR18=2925
5351 11:03:39.675975 CH0_RK0: MR19=0x505, MR18=0x2925, DQSOSC=408, MR23=63, INC=65, DEC=43
5352 11:03:39.676056
5353 11:03:39.679389 ----->DramcWriteLeveling(PI) begin...
5354 11:03:39.679467 ==
5355 11:03:39.682807 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 11:03:39.685835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 11:03:39.685914 ==
5358 11:03:39.689474 Write leveling (Byte 0): 32 => 32
5359 11:03:39.692666 Write leveling (Byte 1): 28 => 28
5360 11:03:39.695969 DramcWriteLeveling(PI) end<-----
5361 11:03:39.696047
5362 11:03:39.696106 ==
5363 11:03:39.699199 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 11:03:39.702518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 11:03:39.702596 ==
5366 11:03:39.706185 [Gating] SW mode calibration
5367 11:03:39.712808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5368 11:03:39.719144 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5369 11:03:39.722317 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:03:39.725907 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:03:39.732384 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 11:03:39.735989 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 11:03:39.739176 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 11:03:39.745979 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 11:03:39.749331 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
5376 11:03:39.752450 0 14 28 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
5377 11:03:39.759147 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:03:39.762560 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:03:39.765810 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 11:03:39.772540 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 11:03:39.775777 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 11:03:39.779400 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 11:03:39.786111 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5384 11:03:39.789206 0 15 28 | B1->B0 | 3b3b 4545 | 0 0 | (1 1) (0 0)
5385 11:03:39.792476 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:03:39.799082 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:03:39.802341 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:03:39.806015 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 11:03:39.812676 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 11:03:39.815855 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 11:03:39.819286 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 11:03:39.822578 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5393 11:03:39.829060 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:03:39.832331 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:03:39.835886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:03:39.842422 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:03:39.845738 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:03:39.849029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:03:39.856197 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:03:39.859040 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:03:39.862298 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:03:39.868912 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:03:39.872286 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:03:39.875583 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:03:39.882332 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:03:39.885913 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:03:39.889171 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5408 11:03:39.895810 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5409 11:03:39.899017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 11:03:39.902721 Total UI for P1: 0, mck2ui 16
5411 11:03:39.905955 best dqsien dly found for B0: ( 1, 2, 26)
5412 11:03:39.909181 Total UI for P1: 0, mck2ui 16
5413 11:03:39.912159 best dqsien dly found for B1: ( 1, 2, 28)
5414 11:03:39.915970 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5415 11:03:39.919112 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5416 11:03:39.919207
5417 11:03:39.922506 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5418 11:03:39.925608 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5419 11:03:39.929409 [Gating] SW calibration Done
5420 11:03:39.929487 ==
5421 11:03:39.932753 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 11:03:39.935836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 11:03:39.935939 ==
5424 11:03:39.939114 RX Vref Scan: 0
5425 11:03:39.939189
5426 11:03:39.942738 RX Vref 0 -> 0, step: 1
5427 11:03:39.942813
5428 11:03:39.942871 RX Delay -80 -> 252, step: 8
5429 11:03:39.949472 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5430 11:03:39.952711 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5431 11:03:39.955834 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5432 11:03:39.959204 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5433 11:03:39.962448 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5434 11:03:39.965645 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5435 11:03:39.972454 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5436 11:03:39.975881 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5437 11:03:39.979028 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5438 11:03:39.982532 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5439 11:03:39.985631 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5440 11:03:39.989003 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5441 11:03:39.995718 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5442 11:03:39.998889 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5443 11:03:40.002609 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5444 11:03:40.005742 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5445 11:03:40.005817 ==
5446 11:03:40.008908 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 11:03:40.012322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 11:03:40.012398 ==
5449 11:03:40.015736 DQS Delay:
5450 11:03:40.015811 DQS0 = 0, DQS1 = 0
5451 11:03:40.018961 DQM Delay:
5452 11:03:40.019036 DQM0 = 104, DQM1 = 89
5453 11:03:40.019094 DQ Delay:
5454 11:03:40.022611 DQ0 =99, DQ1 =103, DQ2 =99, DQ3 =99
5455 11:03:40.025947 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5456 11:03:40.028784 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5457 11:03:40.032244 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5458 11:03:40.035472
5459 11:03:40.035546
5460 11:03:40.035602 ==
5461 11:03:40.039057 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 11:03:40.042187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 11:03:40.042262 ==
5464 11:03:40.042320
5465 11:03:40.042373
5466 11:03:40.045550 TX Vref Scan disable
5467 11:03:40.045648 == TX Byte 0 ==
5468 11:03:40.052041 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5469 11:03:40.055550 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5470 11:03:40.055625 == TX Byte 1 ==
5471 11:03:40.062377 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5472 11:03:40.065724 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5473 11:03:40.065798 ==
5474 11:03:40.068877 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 11:03:40.072071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 11:03:40.072146 ==
5477 11:03:40.072214
5478 11:03:40.072300
5479 11:03:40.075865 TX Vref Scan disable
5480 11:03:40.078976 == TX Byte 0 ==
5481 11:03:40.082226 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5482 11:03:40.085399 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5483 11:03:40.088805 == TX Byte 1 ==
5484 11:03:40.092367 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5485 11:03:40.095372 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5486 11:03:40.095447
5487 11:03:40.098703 [DATLAT]
5488 11:03:40.098777 Freq=933, CH0 RK1
5489 11:03:40.098835
5490 11:03:40.102361 DATLAT Default: 0xb
5491 11:03:40.102435 0, 0xFFFF, sum = 0
5492 11:03:40.105587 1, 0xFFFF, sum = 0
5493 11:03:40.105662 2, 0xFFFF, sum = 0
5494 11:03:40.108779 3, 0xFFFF, sum = 0
5495 11:03:40.108854 4, 0xFFFF, sum = 0
5496 11:03:40.112070 5, 0xFFFF, sum = 0
5497 11:03:40.112186 6, 0xFFFF, sum = 0
5498 11:03:40.115642 7, 0xFFFF, sum = 0
5499 11:03:40.115719 8, 0xFFFF, sum = 0
5500 11:03:40.118823 9, 0xFFFF, sum = 0
5501 11:03:40.118898 10, 0x0, sum = 1
5502 11:03:40.121985 11, 0x0, sum = 2
5503 11:03:40.122061 12, 0x0, sum = 3
5504 11:03:40.125352 13, 0x0, sum = 4
5505 11:03:40.125428 best_step = 11
5506 11:03:40.125487
5507 11:03:40.125540 ==
5508 11:03:40.128762 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 11:03:40.132446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 11:03:40.135709 ==
5511 11:03:40.135783 RX Vref Scan: 0
5512 11:03:40.135841
5513 11:03:40.138963 RX Vref 0 -> 0, step: 1
5514 11:03:40.139037
5515 11:03:40.142061 RX Delay -53 -> 252, step: 4
5516 11:03:40.145780 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5517 11:03:40.149015 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5518 11:03:40.155865 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5519 11:03:40.158869 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5520 11:03:40.162318 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5521 11:03:40.165689 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5522 11:03:40.168805 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5523 11:03:40.172380 iDelay=199, Bit 7, Center 108 (23 ~ 194) 172
5524 11:03:40.178903 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5525 11:03:40.182179 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5526 11:03:40.185423 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5527 11:03:40.189032 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5528 11:03:40.192373 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5529 11:03:40.198843 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5530 11:03:40.202065 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5531 11:03:40.205469 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5532 11:03:40.205544 ==
5533 11:03:40.208754 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 11:03:40.212318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 11:03:40.212395 ==
5536 11:03:40.215420 DQS Delay:
5537 11:03:40.215494 DQS0 = 0, DQS1 = 0
5538 11:03:40.218876 DQM Delay:
5539 11:03:40.218951 DQM0 = 103, DQM1 = 93
5540 11:03:40.219010 DQ Delay:
5541 11:03:40.222082 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5542 11:03:40.225621 DQ4 =104, DQ5 =98, DQ6 =110, DQ7 =108
5543 11:03:40.228569 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5544 11:03:40.235256 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =100
5545 11:03:40.235331
5546 11:03:40.235388
5547 11:03:40.242143 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5548 11:03:40.245389 CH0 RK1: MR19=505, MR18=2D0E
5549 11:03:40.251789 CH0_RK1: MR19=0x505, MR18=0x2D0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5550 11:03:40.255547 [RxdqsGatingPostProcess] freq 933
5551 11:03:40.258341 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 11:03:40.262231 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 11:03:40.265448 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 11:03:40.268657 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 11:03:40.271859 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 11:03:40.275527 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 11:03:40.278653 best DQS1 dly(2T, 0.5T) = (0, 10)
5558 11:03:40.281935 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 11:03:40.285241 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5560 11:03:40.288675 Pre-setting of DQS Precalculation
5561 11:03:40.292003 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 11:03:40.292079 ==
5563 11:03:40.295163 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 11:03:40.302356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 11:03:40.302432 ==
5566 11:03:40.305353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 11:03:40.312113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5568 11:03:40.315423 [CA 0] Center 37 (7~68) winsize 62
5569 11:03:40.318643 [CA 1] Center 37 (7~68) winsize 62
5570 11:03:40.321978 [CA 2] Center 36 (6~66) winsize 61
5571 11:03:40.325448 [CA 3] Center 34 (4~65) winsize 62
5572 11:03:40.328401 [CA 4] Center 35 (4~66) winsize 63
5573 11:03:40.331816 [CA 5] Center 34 (4~65) winsize 62
5574 11:03:40.331891
5575 11:03:40.335211 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5576 11:03:40.335287
5577 11:03:40.338682 [CATrainingPosCal] consider 1 rank data
5578 11:03:40.341887 u2DelayCellTimex100 = 270/100 ps
5579 11:03:40.345487 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5580 11:03:40.348710 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5581 11:03:40.352075 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5582 11:03:40.358454 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5583 11:03:40.362141 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5584 11:03:40.365361 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5585 11:03:40.365436
5586 11:03:40.368627 CA PerBit enable=1, Macro0, CA PI delay=34
5587 11:03:40.368701
5588 11:03:40.372377 [CBTSetCACLKResult] CA Dly = 34
5589 11:03:40.372479 CS Dly: 6 (0~37)
5590 11:03:40.372568 ==
5591 11:03:40.375290 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 11:03:40.381960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 11:03:40.382039 ==
5594 11:03:40.385276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 11:03:40.391762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5596 11:03:40.395321 [CA 0] Center 37 (7~68) winsize 62
5597 11:03:40.398371 [CA 1] Center 38 (8~68) winsize 61
5598 11:03:40.402012 [CA 2] Center 36 (6~66) winsize 61
5599 11:03:40.404935 [CA 3] Center 35 (5~65) winsize 61
5600 11:03:40.408668 [CA 4] Center 35 (5~65) winsize 61
5601 11:03:40.411887 [CA 5] Center 34 (4~65) winsize 62
5602 11:03:40.411964
5603 11:03:40.415050 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5604 11:03:40.415128
5605 11:03:40.418498 [CATrainingPosCal] consider 2 rank data
5606 11:03:40.421970 u2DelayCellTimex100 = 270/100 ps
5607 11:03:40.425010 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5608 11:03:40.428203 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5609 11:03:40.431692 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5610 11:03:40.438348 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5611 11:03:40.441840 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5612 11:03:40.445007 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5613 11:03:40.445107
5614 11:03:40.448238 CA PerBit enable=1, Macro0, CA PI delay=34
5615 11:03:40.448315
5616 11:03:40.451510 [CBTSetCACLKResult] CA Dly = 34
5617 11:03:40.451587 CS Dly: 7 (0~39)
5618 11:03:40.451669
5619 11:03:40.455195 ----->DramcWriteLeveling(PI) begin...
5620 11:03:40.455273 ==
5621 11:03:40.458315 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 11:03:40.464850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 11:03:40.464928 ==
5624 11:03:40.468267 Write leveling (Byte 0): 28 => 28
5625 11:03:40.471567 Write leveling (Byte 1): 28 => 28
5626 11:03:40.471644 DramcWriteLeveling(PI) end<-----
5627 11:03:40.474970
5628 11:03:40.475047 ==
5629 11:03:40.478206 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 11:03:40.481899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 11:03:40.481977 ==
5632 11:03:40.485056 [Gating] SW mode calibration
5633 11:03:40.491522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 11:03:40.495253 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 11:03:40.501424 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 11:03:40.504798 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 11:03:40.508522 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 11:03:40.514649 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 11:03:40.518036 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 11:03:40.521513 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5641 11:03:40.528384 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5642 11:03:40.531356 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5643 11:03:40.534603 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 11:03:40.541494 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 11:03:40.544899 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 11:03:40.547984 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 11:03:40.555198 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 11:03:40.558416 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 11:03:40.561461 0 15 24 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 0)
5650 11:03:40.568261 0 15 28 | B1->B0 | 4343 4545 | 1 1 | (0 0) (0 0)
5651 11:03:40.571451 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:03:40.574619 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:03:40.581315 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 11:03:40.584438 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 11:03:40.588166 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 11:03:40.594793 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5657 11:03:40.598053 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5658 11:03:40.601336 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5659 11:03:40.604511 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:03:40.611379 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:03:40.614590 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:03:40.617778 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:03:40.624265 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:03:40.627703 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:03:40.631034 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:03:40.637613 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:03:40.640955 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:03:40.644469 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:03:40.651250 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:03:40.654659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:03:40.657533 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:03:40.664392 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5673 11:03:40.667635 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5674 11:03:40.670845 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 11:03:40.674107 Total UI for P1: 0, mck2ui 16
5676 11:03:40.677433 best dqsien dly found for B0: ( 1, 2, 22)
5677 11:03:40.681034 Total UI for P1: 0, mck2ui 16
5678 11:03:40.684417 best dqsien dly found for B1: ( 1, 2, 24)
5679 11:03:40.687663 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5680 11:03:40.690970 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5681 11:03:40.691060
5682 11:03:40.697517 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5683 11:03:40.701142 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5684 11:03:40.701245 [Gating] SW calibration Done
5685 11:03:40.704363 ==
5686 11:03:40.704449 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 11:03:40.710690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 11:03:40.710783 ==
5689 11:03:40.710865 RX Vref Scan: 0
5690 11:03:40.710947
5691 11:03:40.714446 RX Vref 0 -> 0, step: 1
5692 11:03:40.714510
5693 11:03:40.717863 RX Delay -80 -> 252, step: 8
5694 11:03:40.721016 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5695 11:03:40.724320 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5696 11:03:40.727557 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5697 11:03:40.734303 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5698 11:03:40.737543 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5699 11:03:40.740958 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5700 11:03:40.744115 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5701 11:03:40.747392 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5702 11:03:40.750772 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5703 11:03:40.757614 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5704 11:03:40.760749 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5705 11:03:40.763994 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5706 11:03:40.767421 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5707 11:03:40.770860 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5708 11:03:40.774126 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5709 11:03:40.780865 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5710 11:03:40.780943 ==
5711 11:03:40.784154 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 11:03:40.787456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 11:03:40.787535 ==
5714 11:03:40.787595 DQS Delay:
5715 11:03:40.790808 DQS0 = 0, DQS1 = 0
5716 11:03:40.790886 DQM Delay:
5717 11:03:40.794270 DQM0 = 102, DQM1 = 95
5718 11:03:40.794348 DQ Delay:
5719 11:03:40.797570 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =99
5720 11:03:40.800845 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5721 11:03:40.804075 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =95
5722 11:03:40.807313 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5723 11:03:40.807392
5724 11:03:40.807451
5725 11:03:40.807506 ==
5726 11:03:40.810733 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 11:03:40.814425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 11:03:40.817732 ==
5729 11:03:40.817808
5730 11:03:40.817867
5731 11:03:40.817921 TX Vref Scan disable
5732 11:03:40.820970 == TX Byte 0 ==
5733 11:03:40.824026 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5734 11:03:40.827469 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5735 11:03:40.830759 == TX Byte 1 ==
5736 11:03:40.834357 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5737 11:03:40.837529 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5738 11:03:40.837641 ==
5739 11:03:40.840772 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 11:03:40.847354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:03:40.847431 ==
5742 11:03:40.847490
5743 11:03:40.847545
5744 11:03:40.847598 TX Vref Scan disable
5745 11:03:40.851633 == TX Byte 0 ==
5746 11:03:40.854965 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5747 11:03:40.861725 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5748 11:03:40.861802 == TX Byte 1 ==
5749 11:03:40.864858 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5750 11:03:40.868271 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5751 11:03:40.871443
5752 11:03:40.871518 [DATLAT]
5753 11:03:40.871577 Freq=933, CH1 RK0
5754 11:03:40.871632
5755 11:03:40.874794 DATLAT Default: 0xd
5756 11:03:40.874893 0, 0xFFFF, sum = 0
5757 11:03:40.878230 1, 0xFFFF, sum = 0
5758 11:03:40.878307 2, 0xFFFF, sum = 0
5759 11:03:40.881743 3, 0xFFFF, sum = 0
5760 11:03:40.881820 4, 0xFFFF, sum = 0
5761 11:03:40.884838 5, 0xFFFF, sum = 0
5762 11:03:40.888487 6, 0xFFFF, sum = 0
5763 11:03:40.888565 7, 0xFFFF, sum = 0
5764 11:03:40.891744 8, 0xFFFF, sum = 0
5765 11:03:40.891821 9, 0xFFFF, sum = 0
5766 11:03:40.895200 10, 0x0, sum = 1
5767 11:03:40.895276 11, 0x0, sum = 2
5768 11:03:40.895335 12, 0x0, sum = 3
5769 11:03:40.898573 13, 0x0, sum = 4
5770 11:03:40.898650 best_step = 11
5771 11:03:40.898709
5772 11:03:40.898762 ==
5773 11:03:40.901770 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 11:03:40.908459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 11:03:40.908534 ==
5776 11:03:40.908593 RX Vref Scan: 1
5777 11:03:40.908647
5778 11:03:40.911678 RX Vref 0 -> 0, step: 1
5779 11:03:40.911753
5780 11:03:40.915002 RX Delay -53 -> 252, step: 4
5781 11:03:40.915077
5782 11:03:40.918258 Set Vref, RX VrefLevel [Byte0]: 54
5783 11:03:40.921498 [Byte1]: 53
5784 11:03:40.921574
5785 11:03:40.924768 Final RX Vref Byte 0 = 54 to rank0
5786 11:03:40.928248 Final RX Vref Byte 1 = 53 to rank0
5787 11:03:40.931580 Final RX Vref Byte 0 = 54 to rank1
5788 11:03:40.934795 Final RX Vref Byte 1 = 53 to rank1==
5789 11:03:40.938361 Dram Type= 6, Freq= 0, CH_1, rank 0
5790 11:03:40.941551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 11:03:40.941619 ==
5792 11:03:40.944941 DQS Delay:
5793 11:03:40.945031 DQS0 = 0, DQS1 = 0
5794 11:03:40.948148 DQM Delay:
5795 11:03:40.948232 DQM0 = 104, DQM1 = 98
5796 11:03:40.948291 DQ Delay:
5797 11:03:40.951499 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5798 11:03:40.954853 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5799 11:03:40.958106 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =90
5800 11:03:40.964658 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =104
5801 11:03:40.964747
5802 11:03:40.964828
5803 11:03:40.971476 [DQSOSCAuto] RK0, (LSB)MR18= 0x213a, (MSB)MR19= 0x505, tDQSOscB0 = 403 ps tDQSOscB1 = 411 ps
5804 11:03:40.974711 CH1 RK0: MR19=505, MR18=213A
5805 11:03:40.981260 CH1_RK0: MR19=0x505, MR18=0x213A, DQSOSC=403, MR23=63, INC=66, DEC=44
5806 11:03:40.981340
5807 11:03:40.984549 ----->DramcWriteLeveling(PI) begin...
5808 11:03:40.984626 ==
5809 11:03:40.988070 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 11:03:40.991290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 11:03:40.991368 ==
5812 11:03:40.994572 Write leveling (Byte 0): 27 => 27
5813 11:03:40.998110 Write leveling (Byte 1): 29 => 29
5814 11:03:41.001280 DramcWriteLeveling(PI) end<-----
5815 11:03:41.001386
5816 11:03:41.001447 ==
5817 11:03:41.004847 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 11:03:41.008180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 11:03:41.008256 ==
5820 11:03:41.011553 [Gating] SW mode calibration
5821 11:03:41.018087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5822 11:03:41.024698 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5823 11:03:41.027989 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5824 11:03:41.034331 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:03:41.037661 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 11:03:41.041113 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 11:03:41.047790 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 11:03:41.051084 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 11:03:41.054488 0 14 24 | B1->B0 | 2e2e 3333 | 1 1 | (1 1) (1 1)
5830 11:03:41.061092 0 14 28 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 0)
5831 11:03:41.064107 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5832 11:03:41.067725 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:03:41.071008 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 11:03:41.077900 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 11:03:41.080814 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 11:03:41.084321 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 11:03:41.091071 0 15 24 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
5838 11:03:41.094239 0 15 28 | B1->B0 | 3f3f 3939 | 1 1 | (0 0) (0 0)
5839 11:03:41.097432 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5840 11:03:41.104329 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:03:41.107924 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:03:41.110831 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 11:03:41.117311 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 11:03:41.121240 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 11:03:41.124386 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5846 11:03:41.130971 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5847 11:03:41.134183 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:03:41.137447 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:03:41.143957 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:03:41.147449 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:03:41.150784 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:03:41.157385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:03:41.161075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:03:41.164304 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:03:41.167494 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:03:41.174359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:03:41.177523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:03:41.181056 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:03:41.187319 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:03:41.190948 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:03:41.193986 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5862 11:03:41.197384 Total UI for P1: 0, mck2ui 16
5863 11:03:41.201009 best dqsien dly found for B1: ( 1, 2, 22)
5864 11:03:41.207375 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5865 11:03:41.210873 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 11:03:41.213939 Total UI for P1: 0, mck2ui 16
5867 11:03:41.217609 best dqsien dly found for B0: ( 1, 2, 26)
5868 11:03:41.220977 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5869 11:03:41.224202 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5870 11:03:41.224278
5871 11:03:41.227512 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5872 11:03:41.230770 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5873 11:03:41.234004 [Gating] SW calibration Done
5874 11:03:41.234079 ==
5875 11:03:41.237310 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 11:03:41.240918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 11:03:41.244297 ==
5878 11:03:41.244372 RX Vref Scan: 0
5879 11:03:41.244431
5880 11:03:41.247536 RX Vref 0 -> 0, step: 1
5881 11:03:41.247612
5882 11:03:41.250715 RX Delay -80 -> 252, step: 8
5883 11:03:41.253906 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5884 11:03:41.257107 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5885 11:03:41.260795 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5886 11:03:41.264160 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5887 11:03:41.267449 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5888 11:03:41.273853 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5889 11:03:41.277003 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5890 11:03:41.280755 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5891 11:03:41.283969 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5892 11:03:41.287211 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5893 11:03:41.290670 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5894 11:03:41.297016 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5895 11:03:41.300681 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5896 11:03:41.304064 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5897 11:03:41.307150 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5898 11:03:41.310598 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5899 11:03:41.313905 ==
5900 11:03:41.313981 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 11:03:41.320790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 11:03:41.320867 ==
5903 11:03:41.320926 DQS Delay:
5904 11:03:41.323854 DQS0 = 0, DQS1 = 0
5905 11:03:41.323929 DQM Delay:
5906 11:03:41.327088 DQM0 = 100, DQM1 = 95
5907 11:03:41.327164 DQ Delay:
5908 11:03:41.330476 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5909 11:03:41.333748 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =99
5910 11:03:41.337381 DQ8 =79, DQ9 =87, DQ10 =99, DQ11 =87
5911 11:03:41.340761 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5912 11:03:41.340837
5913 11:03:41.340894
5914 11:03:41.340947 ==
5915 11:03:41.344031 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 11:03:41.347253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 11:03:41.347329 ==
5918 11:03:41.347388
5919 11:03:41.350605
5920 11:03:41.350680 TX Vref Scan disable
5921 11:03:41.353792 == TX Byte 0 ==
5922 11:03:41.356966 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5923 11:03:41.360595 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5924 11:03:41.363827 == TX Byte 1 ==
5925 11:03:41.367084 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5926 11:03:41.370353 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5927 11:03:41.370429 ==
5928 11:03:41.374074 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 11:03:41.380441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 11:03:41.380517 ==
5931 11:03:41.380578
5932 11:03:41.380631
5933 11:03:41.380681 TX Vref Scan disable
5934 11:03:41.384556 == TX Byte 0 ==
5935 11:03:41.387861 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5936 11:03:41.394538 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5937 11:03:41.394618 == TX Byte 1 ==
5938 11:03:41.397715 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5939 11:03:41.401372 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5940 11:03:41.404352
5941 11:03:41.404427 [DATLAT]
5942 11:03:41.404486 Freq=933, CH1 RK1
5943 11:03:41.404541
5944 11:03:41.408153 DATLAT Default: 0xb
5945 11:03:41.408229 0, 0xFFFF, sum = 0
5946 11:03:41.411319 1, 0xFFFF, sum = 0
5947 11:03:41.411396 2, 0xFFFF, sum = 0
5948 11:03:41.414553 3, 0xFFFF, sum = 0
5949 11:03:41.414630 4, 0xFFFF, sum = 0
5950 11:03:41.418037 5, 0xFFFF, sum = 0
5951 11:03:41.421157 6, 0xFFFF, sum = 0
5952 11:03:41.421234 7, 0xFFFF, sum = 0
5953 11:03:41.424622 8, 0xFFFF, sum = 0
5954 11:03:41.424699 9, 0xFFFF, sum = 0
5955 11:03:41.427824 10, 0x0, sum = 1
5956 11:03:41.427900 11, 0x0, sum = 2
5957 11:03:41.427960 12, 0x0, sum = 3
5958 11:03:41.431254 13, 0x0, sum = 4
5959 11:03:41.431331 best_step = 11
5960 11:03:41.431390
5961 11:03:41.431444 ==
5962 11:03:41.434692 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 11:03:41.441241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 11:03:41.441317 ==
5965 11:03:41.441376 RX Vref Scan: 0
5966 11:03:41.441430
5967 11:03:41.444430 RX Vref 0 -> 0, step: 1
5968 11:03:41.444505
5969 11:03:41.447820 RX Delay -61 -> 252, step: 4
5970 11:03:41.450924 iDelay=199, Bit 0, Center 110 (31 ~ 190) 160
5971 11:03:41.457498 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5972 11:03:41.461011 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5973 11:03:41.464387 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5974 11:03:41.467412 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5975 11:03:41.470699 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5976 11:03:41.477659 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5977 11:03:41.481237 iDelay=199, Bit 7, Center 104 (23 ~ 186) 164
5978 11:03:41.484306 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5979 11:03:41.487558 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5980 11:03:41.490811 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5981 11:03:41.493939 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5982 11:03:41.500758 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5983 11:03:41.503900 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5984 11:03:41.507500 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5985 11:03:41.510601 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5986 11:03:41.510693 ==
5987 11:03:41.513953 Dram Type= 6, Freq= 0, CH_1, rank 1
5988 11:03:41.520738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5989 11:03:41.520802 ==
5990 11:03:41.520856 DQS Delay:
5991 11:03:41.523945 DQS0 = 0, DQS1 = 0
5992 11:03:41.524028 DQM Delay:
5993 11:03:41.524107 DQM0 = 105, DQM1 = 98
5994 11:03:41.527133 DQ Delay:
5995 11:03:41.530729 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5996 11:03:41.533886 DQ4 =108, DQ5 =116, DQ6 =112, DQ7 =104
5997 11:03:41.537150 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5998 11:03:41.540457 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5999 11:03:41.540543
6000 11:03:41.540621
6001 11:03:41.547237 [DQSOSCAuto] RK1, (LSB)MR18= 0x2906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
6002 11:03:41.550549 CH1 RK1: MR19=505, MR18=2906
6003 11:03:41.557486 CH1_RK1: MR19=0x505, MR18=0x2906, DQSOSC=408, MR23=63, INC=65, DEC=43
6004 11:03:41.560796 [RxdqsGatingPostProcess] freq 933
6005 11:03:41.567383 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6006 11:03:41.567451 best DQS0 dly(2T, 0.5T) = (0, 10)
6007 11:03:41.570621 best DQS1 dly(2T, 0.5T) = (0, 10)
6008 11:03:41.573882 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6009 11:03:41.577095 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6010 11:03:41.580766 best DQS0 dly(2T, 0.5T) = (0, 10)
6011 11:03:41.584168 best DQS1 dly(2T, 0.5T) = (0, 10)
6012 11:03:41.587362 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6013 11:03:41.590627 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6014 11:03:41.593888 Pre-setting of DQS Precalculation
6015 11:03:41.597557 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6016 11:03:41.607241 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6017 11:03:41.614158 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6018 11:03:41.614255
6019 11:03:41.614339
6020 11:03:41.617396 [Calibration Summary] 1866 Mbps
6021 11:03:41.617460 CH 0, Rank 0
6022 11:03:41.620725 SW Impedance : PASS
6023 11:03:41.620814 DUTY Scan : NO K
6024 11:03:41.623943 ZQ Calibration : PASS
6025 11:03:41.627542 Jitter Meter : NO K
6026 11:03:41.627631 CBT Training : PASS
6027 11:03:41.630907 Write leveling : PASS
6028 11:03:41.633903 RX DQS gating : PASS
6029 11:03:41.633964 RX DQ/DQS(RDDQC) : PASS
6030 11:03:41.637522 TX DQ/DQS : PASS
6031 11:03:41.640681 RX DATLAT : PASS
6032 11:03:41.640769 RX DQ/DQS(Engine): PASS
6033 11:03:41.644282 TX OE : NO K
6034 11:03:41.644371 All Pass.
6035 11:03:41.644451
6036 11:03:41.647387 CH 0, Rank 1
6037 11:03:41.647473 SW Impedance : PASS
6038 11:03:41.650620 DUTY Scan : NO K
6039 11:03:41.653793 ZQ Calibration : PASS
6040 11:03:41.653858 Jitter Meter : NO K
6041 11:03:41.657264 CBT Training : PASS
6042 11:03:41.657354 Write leveling : PASS
6043 11:03:41.660758 RX DQS gating : PASS
6044 11:03:41.664053 RX DQ/DQS(RDDQC) : PASS
6045 11:03:41.664154 TX DQ/DQS : PASS
6046 11:03:41.667143 RX DATLAT : PASS
6047 11:03:41.670600 RX DQ/DQS(Engine): PASS
6048 11:03:41.670687 TX OE : NO K
6049 11:03:41.673924 All Pass.
6050 11:03:41.674038
6051 11:03:41.674146 CH 1, Rank 0
6052 11:03:41.677269 SW Impedance : PASS
6053 11:03:41.677400 DUTY Scan : NO K
6054 11:03:41.680510 ZQ Calibration : PASS
6055 11:03:41.684350 Jitter Meter : NO K
6056 11:03:41.684449 CBT Training : PASS
6057 11:03:41.687615 Write leveling : PASS
6058 11:03:41.690676 RX DQS gating : PASS
6059 11:03:41.690792 RX DQ/DQS(RDDQC) : PASS
6060 11:03:41.694386 TX DQ/DQS : PASS
6061 11:03:41.697520 RX DATLAT : PASS
6062 11:03:41.697733 RX DQ/DQS(Engine): PASS
6063 11:03:41.700768 TX OE : NO K
6064 11:03:41.700874 All Pass.
6065 11:03:41.700958
6066 11:03:41.704052 CH 1, Rank 1
6067 11:03:41.704126 SW Impedance : PASS
6068 11:03:41.707207 DUTY Scan : NO K
6069 11:03:41.707283 ZQ Calibration : PASS
6070 11:03:41.710588 Jitter Meter : NO K
6071 11:03:41.713952 CBT Training : PASS
6072 11:03:41.714030 Write leveling : PASS
6073 11:03:41.717278 RX DQS gating : PASS
6074 11:03:41.720624 RX DQ/DQS(RDDQC) : PASS
6075 11:03:41.720725 TX DQ/DQS : PASS
6076 11:03:41.723986 RX DATLAT : PASS
6077 11:03:41.727212 RX DQ/DQS(Engine): PASS
6078 11:03:41.727290 TX OE : NO K
6079 11:03:41.730604 All Pass.
6080 11:03:41.730681
6081 11:03:41.730740 DramC Write-DBI off
6082 11:03:41.733889 PER_BANK_REFRESH: Hybrid Mode
6083 11:03:41.733967 TX_TRACKING: ON
6084 11:03:41.744105 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6085 11:03:41.747350 [FAST_K] Save calibration result to emmc
6086 11:03:41.750660 dramc_set_vcore_voltage set vcore to 650000
6087 11:03:41.754095 Read voltage for 400, 6
6088 11:03:41.754172 Vio18 = 0
6089 11:03:41.757310 Vcore = 650000
6090 11:03:41.757387 Vdram = 0
6091 11:03:41.757446 Vddq = 0
6092 11:03:41.757500 Vmddr = 0
6093 11:03:41.763980 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6094 11:03:41.770955 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6095 11:03:41.771033 MEM_TYPE=3, freq_sel=20
6096 11:03:41.773849 sv_algorithm_assistance_LP4_800
6097 11:03:41.777302 ============ PULL DRAM RESETB DOWN ============
6098 11:03:41.784210 ========== PULL DRAM RESETB DOWN end =========
6099 11:03:41.787596 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6100 11:03:41.791140 ===================================
6101 11:03:41.794469 LPDDR4 DRAM CONFIGURATION
6102 11:03:41.797685 ===================================
6103 11:03:41.797762 EX_ROW_EN[0] = 0x0
6104 11:03:41.800901 EX_ROW_EN[1] = 0x0
6105 11:03:41.800978 LP4Y_EN = 0x0
6106 11:03:41.804232 WORK_FSP = 0x0
6107 11:03:41.804308 WL = 0x2
6108 11:03:41.807561 RL = 0x2
6109 11:03:41.807637 BL = 0x2
6110 11:03:41.810872 RPST = 0x0
6111 11:03:41.810948 RD_PRE = 0x0
6112 11:03:41.814110 WR_PRE = 0x1
6113 11:03:41.817567 WR_PST = 0x0
6114 11:03:41.817642 DBI_WR = 0x0
6115 11:03:41.820867 DBI_RD = 0x0
6116 11:03:41.820941 OTF = 0x1
6117 11:03:41.824096 ===================================
6118 11:03:41.827541 ===================================
6119 11:03:41.827616 ANA top config
6120 11:03:41.830535 ===================================
6121 11:03:41.833985 DLL_ASYNC_EN = 0
6122 11:03:41.837239 ALL_SLAVE_EN = 1
6123 11:03:41.840541 NEW_RANK_MODE = 1
6124 11:03:41.843867 DLL_IDLE_MODE = 1
6125 11:03:41.843942 LP45_APHY_COMB_EN = 1
6126 11:03:41.847152 TX_ODT_DIS = 1
6127 11:03:41.850337 NEW_8X_MODE = 1
6128 11:03:41.853710 ===================================
6129 11:03:41.857452 ===================================
6130 11:03:41.860631 data_rate = 800
6131 11:03:41.863990 CKR = 1
6132 11:03:41.864066 DQ_P2S_RATIO = 4
6133 11:03:41.867734 ===================================
6134 11:03:41.870471 CA_P2S_RATIO = 4
6135 11:03:41.874272 DQ_CA_OPEN = 0
6136 11:03:41.877314 DQ_SEMI_OPEN = 1
6137 11:03:41.880549 CA_SEMI_OPEN = 1
6138 11:03:41.880624 CA_FULL_RATE = 0
6139 11:03:41.883996 DQ_CKDIV4_EN = 0
6140 11:03:41.887248 CA_CKDIV4_EN = 1
6141 11:03:41.890460 CA_PREDIV_EN = 0
6142 11:03:41.893717 PH8_DLY = 0
6143 11:03:41.897363 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6144 11:03:41.897438 DQ_AAMCK_DIV = 0
6145 11:03:41.900458 CA_AAMCK_DIV = 0
6146 11:03:41.904042 CA_ADMCK_DIV = 4
6147 11:03:41.907399 DQ_TRACK_CA_EN = 0
6148 11:03:41.910597 CA_PICK = 800
6149 11:03:41.913776 CA_MCKIO = 400
6150 11:03:41.916972 MCKIO_SEMI = 400
6151 11:03:41.920543 PLL_FREQ = 3016
6152 11:03:41.920648 DQ_UI_PI_RATIO = 32
6153 11:03:41.923672 CA_UI_PI_RATIO = 32
6154 11:03:41.927044 ===================================
6155 11:03:41.930399 ===================================
6156 11:03:41.933748 memory_type:LPDDR4
6157 11:03:41.937182 GP_NUM : 10
6158 11:03:41.937257 SRAM_EN : 1
6159 11:03:41.940315 MD32_EN : 0
6160 11:03:41.943772 ===================================
6161 11:03:41.946887 [ANA_INIT] >>>>>>>>>>>>>>
6162 11:03:41.946963 <<<<<< [CONFIGURE PHASE]: ANA_TX
6163 11:03:41.950203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6164 11:03:41.953591 ===================================
6165 11:03:41.956602 data_rate = 800,PCW = 0X7400
6166 11:03:41.960317 ===================================
6167 11:03:41.963652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6168 11:03:41.970071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6169 11:03:41.980150 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 11:03:41.986735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6171 11:03:41.990501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6172 11:03:41.993339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6173 11:03:41.993415 [ANA_INIT] flow start
6174 11:03:41.996950 [ANA_INIT] PLL >>>>>>>>
6175 11:03:42.000297 [ANA_INIT] PLL <<<<<<<<
6176 11:03:42.000372 [ANA_INIT] MIDPI >>>>>>>>
6177 11:03:42.003773 [ANA_INIT] MIDPI <<<<<<<<
6178 11:03:42.007017 [ANA_INIT] DLL >>>>>>>>
6179 11:03:42.007092 [ANA_INIT] flow end
6180 11:03:42.013608 ============ LP4 DIFF to SE enter ============
6181 11:03:42.016885 ============ LP4 DIFF to SE exit ============
6182 11:03:42.020121 [ANA_INIT] <<<<<<<<<<<<<
6183 11:03:42.023410 [Flow] Enable top DCM control >>>>>
6184 11:03:42.026723 [Flow] Enable top DCM control <<<<<
6185 11:03:42.026799 Enable DLL master slave shuffle
6186 11:03:42.033517 ==============================================================
6187 11:03:42.036741 Gating Mode config
6188 11:03:42.039927 ==============================================================
6189 11:03:42.043387 Config description:
6190 11:03:42.053496 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6191 11:03:42.060020 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6192 11:03:42.063386 SELPH_MODE 0: By rank 1: By Phase
6193 11:03:42.069814 ==============================================================
6194 11:03:42.073138 GAT_TRACK_EN = 0
6195 11:03:42.076663 RX_GATING_MODE = 2
6196 11:03:42.080084 RX_GATING_TRACK_MODE = 2
6197 11:03:42.083127 SELPH_MODE = 1
6198 11:03:42.083203 PICG_EARLY_EN = 1
6199 11:03:42.086521 VALID_LAT_VALUE = 1
6200 11:03:42.093228 ==============================================================
6201 11:03:42.096705 Enter into Gating configuration >>>>
6202 11:03:42.099942 Exit from Gating configuration <<<<
6203 11:03:42.103519 Enter into DVFS_PRE_config >>>>>
6204 11:03:42.113361 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6205 11:03:42.116821 Exit from DVFS_PRE_config <<<<<
6206 11:03:42.120011 Enter into PICG configuration >>>>
6207 11:03:42.123319 Exit from PICG configuration <<<<
6208 11:03:42.126614 [RX_INPUT] configuration >>>>>
6209 11:03:42.129956 [RX_INPUT] configuration <<<<<
6210 11:03:42.133190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6211 11:03:42.140288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6212 11:03:42.146554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 11:03:42.153383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 11:03:42.156613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 11:03:42.163496 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 11:03:42.166747 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6217 11:03:42.173224 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6218 11:03:42.176586 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6219 11:03:42.179886 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6220 11:03:42.183154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6221 11:03:42.190023 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6222 11:03:42.193392 ===================================
6223 11:03:42.193467 LPDDR4 DRAM CONFIGURATION
6224 11:03:42.196556 ===================================
6225 11:03:42.199954 EX_ROW_EN[0] = 0x0
6226 11:03:42.203436 EX_ROW_EN[1] = 0x0
6227 11:03:42.203510 LP4Y_EN = 0x0
6228 11:03:42.206829 WORK_FSP = 0x0
6229 11:03:42.206903 WL = 0x2
6230 11:03:42.210185 RL = 0x2
6231 11:03:42.210259 BL = 0x2
6232 11:03:42.213091 RPST = 0x0
6233 11:03:42.213187 RD_PRE = 0x0
6234 11:03:42.216736 WR_PRE = 0x1
6235 11:03:42.216810 WR_PST = 0x0
6236 11:03:42.220001 DBI_WR = 0x0
6237 11:03:42.220076 DBI_RD = 0x0
6238 11:03:42.223193 OTF = 0x1
6239 11:03:42.226662 ===================================
6240 11:03:42.229752 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6241 11:03:42.233010 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6242 11:03:42.240036 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6243 11:03:42.243333 ===================================
6244 11:03:42.243408 LPDDR4 DRAM CONFIGURATION
6245 11:03:42.246576 ===================================
6246 11:03:42.249755 EX_ROW_EN[0] = 0x10
6247 11:03:42.253488 EX_ROW_EN[1] = 0x0
6248 11:03:42.253563 LP4Y_EN = 0x0
6249 11:03:42.256486 WORK_FSP = 0x0
6250 11:03:42.256560 WL = 0x2
6251 11:03:42.259806 RL = 0x2
6252 11:03:42.259881 BL = 0x2
6253 11:03:42.262973 RPST = 0x0
6254 11:03:42.263047 RD_PRE = 0x0
6255 11:03:42.266568 WR_PRE = 0x1
6256 11:03:42.266642 WR_PST = 0x0
6257 11:03:42.269804 DBI_WR = 0x0
6258 11:03:42.269891 DBI_RD = 0x0
6259 11:03:42.273018 OTF = 0x1
6260 11:03:42.276272 ===================================
6261 11:03:42.283267 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6262 11:03:42.286602 nWR fixed to 30
6263 11:03:42.286679 [ModeRegInit_LP4] CH0 RK0
6264 11:03:42.290013 [ModeRegInit_LP4] CH0 RK1
6265 11:03:42.293204 [ModeRegInit_LP4] CH1 RK0
6266 11:03:42.296604 [ModeRegInit_LP4] CH1 RK1
6267 11:03:42.296678 match AC timing 19
6268 11:03:42.299745 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6269 11:03:42.306405 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6270 11:03:42.309631 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6271 11:03:42.313182 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6272 11:03:42.319592 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6273 11:03:42.319667 ==
6274 11:03:42.322969 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 11:03:42.326228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 11:03:42.326303 ==
6277 11:03:42.332854 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 11:03:42.339396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6279 11:03:42.339472 [CA 0] Center 36 (8~64) winsize 57
6280 11:03:42.342916 [CA 1] Center 36 (8~64) winsize 57
6281 11:03:42.346296 [CA 2] Center 36 (8~64) winsize 57
6282 11:03:42.349495 [CA 3] Center 36 (8~64) winsize 57
6283 11:03:42.352823 [CA 4] Center 36 (8~64) winsize 57
6284 11:03:42.356276 [CA 5] Center 36 (8~64) winsize 57
6285 11:03:42.356351
6286 11:03:42.359501 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6287 11:03:42.359576
6288 11:03:42.362859 [CATrainingPosCal] consider 1 rank data
6289 11:03:42.365995 u2DelayCellTimex100 = 270/100 ps
6290 11:03:42.369289 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:03:42.376123 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:03:42.379414 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:03:42.382586 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 11:03:42.385933 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 11:03:42.389169 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 11:03:42.389244
6297 11:03:42.392397 CA PerBit enable=1, Macro0, CA PI delay=36
6298 11:03:42.392472
6299 11:03:42.396087 [CBTSetCACLKResult] CA Dly = 36
6300 11:03:42.396162 CS Dly: 1 (0~32)
6301 11:03:42.399396 ==
6302 11:03:42.399471 Dram Type= 6, Freq= 0, CH_0, rank 1
6303 11:03:42.405924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 11:03:42.405999 ==
6305 11:03:42.409012 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6306 11:03:42.415724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6307 11:03:42.419116 [CA 0] Center 36 (8~64) winsize 57
6308 11:03:42.422717 [CA 1] Center 36 (8~64) winsize 57
6309 11:03:42.426098 [CA 2] Center 36 (8~64) winsize 57
6310 11:03:42.429366 [CA 3] Center 36 (8~64) winsize 57
6311 11:03:42.432544 [CA 4] Center 36 (8~64) winsize 57
6312 11:03:42.436021 [CA 5] Center 36 (8~64) winsize 57
6313 11:03:42.436096
6314 11:03:42.439256 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6315 11:03:42.439331
6316 11:03:42.442848 [CATrainingPosCal] consider 2 rank data
6317 11:03:42.446274 u2DelayCellTimex100 = 270/100 ps
6318 11:03:42.449557 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:03:42.452771 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:03:42.456147 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:03:42.459187 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:03:42.462879 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 11:03:42.466072 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 11:03:42.469347
6325 11:03:42.472761 CA PerBit enable=1, Macro0, CA PI delay=36
6326 11:03:42.472835
6327 11:03:42.475944 [CBTSetCACLKResult] CA Dly = 36
6328 11:03:42.476019 CS Dly: 1 (0~32)
6329 11:03:42.476076
6330 11:03:42.479016 ----->DramcWriteLeveling(PI) begin...
6331 11:03:42.479092 ==
6332 11:03:42.482768 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 11:03:42.485884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 11:03:42.489283 ==
6335 11:03:42.489358 Write leveling (Byte 0): 40 => 8
6336 11:03:42.492683 Write leveling (Byte 1): 32 => 0
6337 11:03:42.495851 DramcWriteLeveling(PI) end<-----
6338 11:03:42.495925
6339 11:03:42.495983 ==
6340 11:03:42.499541 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 11:03:42.505662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 11:03:42.505762 ==
6343 11:03:42.505850 [Gating] SW mode calibration
6344 11:03:42.516045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6345 11:03:42.519389 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6346 11:03:42.522559 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6347 11:03:42.529076 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 11:03:42.532462 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 11:03:42.535894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 11:03:42.542219 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 11:03:42.545660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 11:03:42.549066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 11:03:42.555716 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 11:03:42.558932 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 11:03:42.562524 Total UI for P1: 0, mck2ui 16
6356 11:03:42.565590 best dqsien dly found for B0: ( 0, 14, 24)
6357 11:03:42.569338 Total UI for P1: 0, mck2ui 16
6358 11:03:42.572214 best dqsien dly found for B1: ( 0, 14, 24)
6359 11:03:42.575590 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6360 11:03:42.579327 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6361 11:03:42.579402
6362 11:03:42.582481 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6363 11:03:42.585807 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 11:03:42.588988 [Gating] SW calibration Done
6365 11:03:42.589062 ==
6366 11:03:42.592263 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 11:03:42.595643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 11:03:42.599036 ==
6369 11:03:42.599111 RX Vref Scan: 0
6370 11:03:42.599169
6371 11:03:42.602112 RX Vref 0 -> 0, step: 1
6372 11:03:42.602186
6373 11:03:42.605500 RX Delay -410 -> 252, step: 16
6374 11:03:42.608818 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6375 11:03:42.612554 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6376 11:03:42.615873 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6377 11:03:42.622295 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6378 11:03:42.625571 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6379 11:03:42.629157 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6380 11:03:42.632238 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6381 11:03:42.638922 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6382 11:03:42.642185 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6383 11:03:42.645631 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6384 11:03:42.649035 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6385 11:03:42.655487 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6386 11:03:42.658771 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6387 11:03:42.662023 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6388 11:03:42.665530 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6389 11:03:42.672229 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6390 11:03:42.672304 ==
6391 11:03:42.675665 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 11:03:42.678786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 11:03:42.678861 ==
6394 11:03:42.678923 DQS Delay:
6395 11:03:42.682202 DQS0 = 27, DQS1 = 43
6396 11:03:42.682277 DQM Delay:
6397 11:03:42.685450 DQM0 = 11, DQM1 = 12
6398 11:03:42.685525 DQ Delay:
6399 11:03:42.689062 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6400 11:03:42.692353 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6401 11:03:42.695700 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6402 11:03:42.698707 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6403 11:03:42.698818
6404 11:03:42.698906
6405 11:03:42.698967 ==
6406 11:03:42.702473 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 11:03:42.705478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 11:03:42.705557 ==
6409 11:03:42.705624
6410 11:03:42.705678
6411 11:03:42.708870 TX Vref Scan disable
6412 11:03:42.711940 == TX Byte 0 ==
6413 11:03:42.715468 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 11:03:42.718787 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 11:03:42.721971 == TX Byte 1 ==
6416 11:03:42.725350 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6417 11:03:42.728653 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6418 11:03:42.728743 ==
6419 11:03:42.731927 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 11:03:42.735011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:03:42.738791 ==
6422 11:03:42.738866
6423 11:03:42.738923
6424 11:03:42.738976 TX Vref Scan disable
6425 11:03:42.741912 == TX Byte 0 ==
6426 11:03:42.744951 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 11:03:42.748498 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 11:03:42.751913 == TX Byte 1 ==
6429 11:03:42.755201 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6430 11:03:42.758558 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6431 11:03:42.758633
6432 11:03:42.761940 [DATLAT]
6433 11:03:42.762043 Freq=400, CH0 RK0
6434 11:03:42.762101
6435 11:03:42.764895 DATLAT Default: 0xf
6436 11:03:42.764969 0, 0xFFFF, sum = 0
6437 11:03:42.768416 1, 0xFFFF, sum = 0
6438 11:03:42.768492 2, 0xFFFF, sum = 0
6439 11:03:42.771888 3, 0xFFFF, sum = 0
6440 11:03:42.771963 4, 0xFFFF, sum = 0
6441 11:03:42.775045 5, 0xFFFF, sum = 0
6442 11:03:42.775121 6, 0xFFFF, sum = 0
6443 11:03:42.778548 7, 0xFFFF, sum = 0
6444 11:03:42.778624 8, 0xFFFF, sum = 0
6445 11:03:42.781954 9, 0xFFFF, sum = 0
6446 11:03:42.782031 10, 0xFFFF, sum = 0
6447 11:03:42.785050 11, 0xFFFF, sum = 0
6448 11:03:42.785189 12, 0xFFFF, sum = 0
6449 11:03:42.788446 13, 0x0, sum = 1
6450 11:03:42.788522 14, 0x0, sum = 2
6451 11:03:42.791892 15, 0x0, sum = 3
6452 11:03:42.791968 16, 0x0, sum = 4
6453 11:03:42.795229 best_step = 14
6454 11:03:42.795328
6455 11:03:42.795445 ==
6456 11:03:42.798625 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 11:03:42.801742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 11:03:42.801811 ==
6459 11:03:42.805009 RX Vref Scan: 1
6460 11:03:42.805109
6461 11:03:42.805197 RX Vref 0 -> 0, step: 1
6462 11:03:42.805252
6463 11:03:42.808342 RX Delay -327 -> 252, step: 8
6464 11:03:42.808432
6465 11:03:42.811843 Set Vref, RX VrefLevel [Byte0]: 58
6466 11:03:42.814976 [Byte1]: 49
6467 11:03:42.819209
6468 11:03:42.819280 Final RX Vref Byte 0 = 58 to rank0
6469 11:03:42.822521 Final RX Vref Byte 1 = 49 to rank0
6470 11:03:42.826277 Final RX Vref Byte 0 = 58 to rank1
6471 11:03:42.829603 Final RX Vref Byte 1 = 49 to rank1==
6472 11:03:42.832494 Dram Type= 6, Freq= 0, CH_0, rank 0
6473 11:03:42.839660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 11:03:42.839733 ==
6475 11:03:42.839814 DQS Delay:
6476 11:03:42.842745 DQS0 = 28, DQS1 = 48
6477 11:03:42.842817 DQM Delay:
6478 11:03:42.842888 DQM0 = 12, DQM1 = 15
6479 11:03:42.846036 DQ Delay:
6480 11:03:42.849077 DQ0 =8, DQ1 =12, DQ2 =12, DQ3 =8
6481 11:03:42.852700 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6482 11:03:42.852767 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6483 11:03:42.856220 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6484 11:03:42.856287
6485 11:03:42.859402
6486 11:03:42.866140 [DQSOSCAuto] RK0, (LSB)MR18= 0xbbb2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 386 ps
6487 11:03:42.869573 CH0 RK0: MR19=C0C, MR18=BBB2
6488 11:03:42.876115 CH0_RK0: MR19=0xC0C, MR18=0xBBB2, DQSOSC=386, MR23=63, INC=396, DEC=264
6489 11:03:42.876191 ==
6490 11:03:42.879501 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 11:03:42.882720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 11:03:42.882790 ==
6493 11:03:42.886108 [Gating] SW mode calibration
6494 11:03:42.892438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6495 11:03:42.899194 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6496 11:03:42.902723 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6497 11:03:42.906164 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 11:03:42.909353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 11:03:42.916002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 11:03:42.919431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 11:03:42.922678 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 11:03:42.929344 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 11:03:42.932342 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 11:03:42.936141 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 11:03:42.939365 Total UI for P1: 0, mck2ui 16
6506 11:03:42.942612 best dqsien dly found for B0: ( 0, 14, 24)
6507 11:03:42.945915 Total UI for P1: 0, mck2ui 16
6508 11:03:42.949111 best dqsien dly found for B1: ( 0, 14, 24)
6509 11:03:42.952422 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6510 11:03:42.955679 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6511 11:03:42.958879
6512 11:03:42.962623 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6513 11:03:42.965917 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 11:03:42.969131 [Gating] SW calibration Done
6515 11:03:42.969200 ==
6516 11:03:42.972360 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 11:03:42.975640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 11:03:42.975711 ==
6519 11:03:42.975786 RX Vref Scan: 0
6520 11:03:42.975860
6521 11:03:42.979179 RX Vref 0 -> 0, step: 1
6522 11:03:42.979250
6523 11:03:42.982394 RX Delay -410 -> 252, step: 16
6524 11:03:42.986093 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6525 11:03:42.992363 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6526 11:03:42.995616 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6527 11:03:42.998788 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6528 11:03:43.002165 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6529 11:03:43.008920 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6530 11:03:43.012226 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6531 11:03:43.015493 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6532 11:03:43.018839 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6533 11:03:43.025425 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6534 11:03:43.029012 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6535 11:03:43.032327 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6536 11:03:43.035694 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6537 11:03:43.041989 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6538 11:03:43.045547 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6539 11:03:43.048549 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6540 11:03:43.048615 ==
6541 11:03:43.052199 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 11:03:43.058539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 11:03:43.058613 ==
6544 11:03:43.058685 DQS Delay:
6545 11:03:43.061778 DQS0 = 27, DQS1 = 43
6546 11:03:43.061850 DQM Delay:
6547 11:03:43.061921 DQM0 = 9, DQM1 = 15
6548 11:03:43.065095 DQ Delay:
6549 11:03:43.065205 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6550 11:03:43.068490 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6551 11:03:43.071740 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6552 11:03:43.075498 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6553 11:03:43.075570
6554 11:03:43.075641
6555 11:03:43.075709 ==
6556 11:03:43.078823 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 11:03:43.085336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 11:03:43.085407 ==
6559 11:03:43.085481
6560 11:03:43.085574
6561 11:03:43.088537 TX Vref Scan disable
6562 11:03:43.088630 == TX Byte 0 ==
6563 11:03:43.091881 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6564 11:03:43.095080 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6565 11:03:43.098805 == TX Byte 1 ==
6566 11:03:43.102019 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6567 11:03:43.105270 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6568 11:03:43.108485 ==
6569 11:03:43.108559 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 11:03:43.115009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 11:03:43.115098 ==
6572 11:03:43.115155
6573 11:03:43.115208
6574 11:03:43.118634 TX Vref Scan disable
6575 11:03:43.118708 == TX Byte 0 ==
6576 11:03:43.121678 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6577 11:03:43.125050 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6578 11:03:43.128440 == TX Byte 1 ==
6579 11:03:43.131818 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6580 11:03:43.135040 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6581 11:03:43.138549
6582 11:03:43.138623 [DATLAT]
6583 11:03:43.138681 Freq=400, CH0 RK1
6584 11:03:43.138734
6585 11:03:43.141883 DATLAT Default: 0xe
6586 11:03:43.141958 0, 0xFFFF, sum = 0
6587 11:03:43.145369 1, 0xFFFF, sum = 0
6588 11:03:43.145444 2, 0xFFFF, sum = 0
6589 11:03:43.148618 3, 0xFFFF, sum = 0
6590 11:03:43.148694 4, 0xFFFF, sum = 0
6591 11:03:43.151983 5, 0xFFFF, sum = 0
6592 11:03:43.152058 6, 0xFFFF, sum = 0
6593 11:03:43.154994 7, 0xFFFF, sum = 0
6594 11:03:43.158604 8, 0xFFFF, sum = 0
6595 11:03:43.158686 9, 0xFFFF, sum = 0
6596 11:03:43.161604 10, 0xFFFF, sum = 0
6597 11:03:43.161680 11, 0xFFFF, sum = 0
6598 11:03:43.165346 12, 0xFFFF, sum = 0
6599 11:03:43.165425 13, 0x0, sum = 1
6600 11:03:43.168716 14, 0x0, sum = 2
6601 11:03:43.168791 15, 0x0, sum = 3
6602 11:03:43.172035 16, 0x0, sum = 4
6603 11:03:43.172111 best_step = 14
6604 11:03:43.172168
6605 11:03:43.172221 ==
6606 11:03:43.175263 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 11:03:43.178509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 11:03:43.178584 ==
6609 11:03:43.181681 RX Vref Scan: 0
6610 11:03:43.181754
6611 11:03:43.181812 RX Vref 0 -> 0, step: 1
6612 11:03:43.185345
6613 11:03:43.185421 RX Delay -327 -> 252, step: 8
6614 11:03:43.193724 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6615 11:03:43.196990 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6616 11:03:43.200249 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6617 11:03:43.203772 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6618 11:03:43.210322 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6619 11:03:43.213513 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6620 11:03:43.216910 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6621 11:03:43.220299 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6622 11:03:43.226806 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6623 11:03:43.230440 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6624 11:03:43.233771 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6625 11:03:43.237050 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6626 11:03:43.243751 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6627 11:03:43.247042 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6628 11:03:43.250065 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6629 11:03:43.256493 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6630 11:03:43.256581 ==
6631 11:03:43.260169 Dram Type= 6, Freq= 0, CH_0, rank 1
6632 11:03:43.263292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 11:03:43.263387 ==
6634 11:03:43.263470 DQS Delay:
6635 11:03:43.266721 DQS0 = 28, DQS1 = 40
6636 11:03:43.266789 DQM Delay:
6637 11:03:43.270208 DQM0 = 9, DQM1 = 11
6638 11:03:43.270301 DQ Delay:
6639 11:03:43.273351 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6640 11:03:43.276797 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6641 11:03:43.280027 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6642 11:03:43.283332 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6643 11:03:43.283398
6644 11:03:43.283493
6645 11:03:43.289966 [DQSOSCAuto] RK1, (LSB)MR18= 0xc97b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 384 ps
6646 11:03:43.293310 CH0 RK1: MR19=C0C, MR18=C97B
6647 11:03:43.299934 CH0_RK1: MR19=0xC0C, MR18=0xC97B, DQSOSC=384, MR23=63, INC=400, DEC=267
6648 11:03:43.303257 [RxdqsGatingPostProcess] freq 400
6649 11:03:43.306738 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6650 11:03:43.310117 best DQS0 dly(2T, 0.5T) = (0, 10)
6651 11:03:43.313333 best DQS1 dly(2T, 0.5T) = (0, 10)
6652 11:03:43.316549 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6653 11:03:43.319877 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6654 11:03:43.323139 best DQS0 dly(2T, 0.5T) = (0, 10)
6655 11:03:43.326374 best DQS1 dly(2T, 0.5T) = (0, 10)
6656 11:03:43.330046 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6657 11:03:43.333257 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6658 11:03:43.336699 Pre-setting of DQS Precalculation
6659 11:03:43.339996 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6660 11:03:43.343342 ==
6661 11:03:43.343408 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 11:03:43.349886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 11:03:43.349962 ==
6664 11:03:43.353616 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 11:03:43.360042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6666 11:03:43.363193 [CA 0] Center 36 (8~64) winsize 57
6667 11:03:43.366580 [CA 1] Center 36 (8~64) winsize 57
6668 11:03:43.369769 [CA 2] Center 36 (8~64) winsize 57
6669 11:03:43.373228 [CA 3] Center 36 (8~64) winsize 57
6670 11:03:43.376549 [CA 4] Center 36 (8~64) winsize 57
6671 11:03:43.380261 [CA 5] Center 36 (8~64) winsize 57
6672 11:03:43.380335
6673 11:03:43.383479 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6674 11:03:43.383554
6675 11:03:43.386810 [CATrainingPosCal] consider 1 rank data
6676 11:03:43.390012 u2DelayCellTimex100 = 270/100 ps
6677 11:03:43.393234 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:03:43.396695 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:03:43.400002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:03:43.403339 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 11:03:43.406646 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 11:03:43.409934 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 11:03:43.410009
6684 11:03:43.416745 CA PerBit enable=1, Macro0, CA PI delay=36
6685 11:03:43.416819
6686 11:03:43.420201 [CBTSetCACLKResult] CA Dly = 36
6687 11:03:43.420279 CS Dly: 1 (0~32)
6688 11:03:43.420337 ==
6689 11:03:43.423338 Dram Type= 6, Freq= 0, CH_1, rank 1
6690 11:03:43.426781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 11:03:43.426853 ==
6692 11:03:43.433376 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6693 11:03:43.440071 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6694 11:03:43.443166 [CA 0] Center 36 (8~64) winsize 57
6695 11:03:43.446486 [CA 1] Center 36 (8~64) winsize 57
6696 11:03:43.449643 [CA 2] Center 36 (8~64) winsize 57
6697 11:03:43.453371 [CA 3] Center 36 (8~64) winsize 57
6698 11:03:43.456504 [CA 4] Center 36 (8~64) winsize 57
6699 11:03:43.456576 [CA 5] Center 36 (8~64) winsize 57
6700 11:03:43.459957
6701 11:03:43.463167 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6702 11:03:43.463237
6703 11:03:43.466525 [CATrainingPosCal] consider 2 rank data
6704 11:03:43.470052 u2DelayCellTimex100 = 270/100 ps
6705 11:03:43.472944 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:03:43.476784 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:03:43.479842 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:03:43.483292 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:03:43.486459 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 11:03:43.489684 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 11:03:43.489754
6712 11:03:43.492809 CA PerBit enable=1, Macro0, CA PI delay=36
6713 11:03:43.492874
6714 11:03:43.496553 [CBTSetCACLKResult] CA Dly = 36
6715 11:03:43.499798 CS Dly: 1 (0~32)
6716 11:03:43.499863
6717 11:03:43.503019 ----->DramcWriteLeveling(PI) begin...
6718 11:03:43.503096 ==
6719 11:03:43.506515 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 11:03:43.509851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 11:03:43.509927 ==
6722 11:03:43.513089 Write leveling (Byte 0): 40 => 8
6723 11:03:43.516324 Write leveling (Byte 1): 32 => 0
6724 11:03:43.519480 DramcWriteLeveling(PI) end<-----
6725 11:03:43.519555
6726 11:03:43.519612 ==
6727 11:03:43.523085 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 11:03:43.526370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 11:03:43.526445 ==
6730 11:03:43.529571 [Gating] SW mode calibration
6731 11:03:43.536128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6732 11:03:43.543025 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6733 11:03:43.546277 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6734 11:03:43.549573 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6735 11:03:43.556152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 11:03:43.559646 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 11:03:43.562844 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 11:03:43.569702 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 11:03:43.572978 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 11:03:43.576122 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 11:03:43.583009 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 11:03:43.583084 Total UI for P1: 0, mck2ui 16
6743 11:03:43.589470 best dqsien dly found for B0: ( 0, 14, 24)
6744 11:03:43.589577 Total UI for P1: 0, mck2ui 16
6745 11:03:43.596107 best dqsien dly found for B1: ( 0, 14, 24)
6746 11:03:43.599762 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6747 11:03:43.603042 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6748 11:03:43.603117
6749 11:03:43.606293 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6750 11:03:43.609692 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 11:03:43.612820 [Gating] SW calibration Done
6752 11:03:43.612917 ==
6753 11:03:43.616417 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 11:03:43.619443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 11:03:43.619518 ==
6756 11:03:43.623054 RX Vref Scan: 0
6757 11:03:43.623128
6758 11:03:43.623185 RX Vref 0 -> 0, step: 1
6759 11:03:43.623239
6760 11:03:43.626381 RX Delay -410 -> 252, step: 16
6761 11:03:43.632868 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6762 11:03:43.636028 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6763 11:03:43.639675 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6764 11:03:43.642870 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6765 11:03:43.649513 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6766 11:03:43.652950 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6767 11:03:43.656198 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6768 11:03:43.659512 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6769 11:03:43.663094 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6770 11:03:43.669644 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6771 11:03:43.672750 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6772 11:03:43.676100 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6773 11:03:43.682706 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6774 11:03:43.686294 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6775 11:03:43.689323 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6776 11:03:43.692712 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6777 11:03:43.692788 ==
6778 11:03:43.696452 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 11:03:43.702723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 11:03:43.702822 ==
6781 11:03:43.702898 DQS Delay:
6782 11:03:43.706138 DQS0 = 27, DQS1 = 35
6783 11:03:43.706214 DQM Delay:
6784 11:03:43.706290 DQM0 = 6, DQM1 = 10
6785 11:03:43.709527 DQ Delay:
6786 11:03:43.712857 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6787 11:03:43.712934 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6788 11:03:43.716106 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6789 11:03:43.719517 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =16
6790 11:03:43.719594
6791 11:03:43.719669
6792 11:03:43.722933 ==
6793 11:03:43.723010 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 11:03:43.729532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 11:03:43.729610 ==
6796 11:03:43.729686
6797 11:03:43.729758
6798 11:03:43.732801 TX Vref Scan disable
6799 11:03:43.732878 == TX Byte 0 ==
6800 11:03:43.736489 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 11:03:43.739788 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 11:03:43.743030 == TX Byte 1 ==
6803 11:03:43.746177 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6804 11:03:43.749937 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6805 11:03:43.752868 ==
6806 11:03:43.756341 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 11:03:43.759724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:03:43.759835 ==
6809 11:03:43.759980
6810 11:03:43.760070
6811 11:03:43.762881 TX Vref Scan disable
6812 11:03:43.762969 == TX Byte 0 ==
6813 11:03:43.766351 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 11:03:43.773090 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 11:03:43.773208 == TX Byte 1 ==
6816 11:03:43.776721 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6817 11:03:43.783234 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6818 11:03:43.783308
6819 11:03:43.783367 [DATLAT]
6820 11:03:43.783427 Freq=400, CH1 RK0
6821 11:03:43.783482
6822 11:03:43.786470 DATLAT Default: 0xf
6823 11:03:43.786556 0, 0xFFFF, sum = 0
6824 11:03:43.789745 1, 0xFFFF, sum = 0
6825 11:03:43.793016 2, 0xFFFF, sum = 0
6826 11:03:43.793081 3, 0xFFFF, sum = 0
6827 11:03:43.796428 4, 0xFFFF, sum = 0
6828 11:03:43.796497 5, 0xFFFF, sum = 0
6829 11:03:43.799528 6, 0xFFFF, sum = 0
6830 11:03:43.799595 7, 0xFFFF, sum = 0
6831 11:03:43.803184 8, 0xFFFF, sum = 0
6832 11:03:43.803245 9, 0xFFFF, sum = 0
6833 11:03:43.806285 10, 0xFFFF, sum = 0
6834 11:03:43.806350 11, 0xFFFF, sum = 0
6835 11:03:43.809750 12, 0xFFFF, sum = 0
6836 11:03:43.809811 13, 0x0, sum = 1
6837 11:03:43.813229 14, 0x0, sum = 2
6838 11:03:43.813290 15, 0x0, sum = 3
6839 11:03:43.816335 16, 0x0, sum = 4
6840 11:03:43.816400 best_step = 14
6841 11:03:43.816459
6842 11:03:43.816509 ==
6843 11:03:43.819712 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 11:03:43.823315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 11:03:43.826344 ==
6846 11:03:43.826408 RX Vref Scan: 1
6847 11:03:43.826469
6848 11:03:43.829718 RX Vref 0 -> 0, step: 1
6849 11:03:43.829779
6850 11:03:43.832789 RX Delay -311 -> 252, step: 8
6851 11:03:43.832853
6852 11:03:43.832905 Set Vref, RX VrefLevel [Byte0]: 54
6853 11:03:43.836424 [Byte1]: 53
6854 11:03:43.841913
6855 11:03:43.841975 Final RX Vref Byte 0 = 54 to rank0
6856 11:03:43.845111 Final RX Vref Byte 1 = 53 to rank0
6857 11:03:43.848375 Final RX Vref Byte 0 = 54 to rank1
6858 11:03:43.852029 Final RX Vref Byte 1 = 53 to rank1==
6859 11:03:43.855273 Dram Type= 6, Freq= 0, CH_1, rank 0
6860 11:03:43.861888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 11:03:43.861957 ==
6862 11:03:43.862011 DQS Delay:
6863 11:03:43.862061 DQS0 = 28, DQS1 = 40
6864 11:03:43.865317 DQM Delay:
6865 11:03:43.865372 DQM0 = 8, DQM1 = 13
6866 11:03:43.868740 DQ Delay:
6867 11:03:43.868797 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6868 11:03:43.871874 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6869 11:03:43.875108 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6870 11:03:43.878400 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6871 11:03:43.878467
6872 11:03:43.878520
6873 11:03:43.888585 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ed8, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6874 11:03:43.891793 CH1 RK0: MR19=C0C, MR18=9ED8
6875 11:03:43.898287 CH1_RK0: MR19=0xC0C, MR18=0x9ED8, DQSOSC=383, MR23=63, INC=402, DEC=268
6876 11:03:43.898356 ==
6877 11:03:43.901847 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 11:03:43.905004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 11:03:43.905065 ==
6880 11:03:43.908539 [Gating] SW mode calibration
6881 11:03:43.914870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6882 11:03:43.918398 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6883 11:03:43.925040 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6884 11:03:43.928140 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 11:03:43.931791 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 11:03:43.938274 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 11:03:43.941593 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 11:03:43.944821 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 11:03:43.951787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 11:03:43.955025 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 11:03:43.958291 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 11:03:43.961367 Total UI for P1: 0, mck2ui 16
6893 11:03:43.964992 best dqsien dly found for B0: ( 0, 14, 24)
6894 11:03:43.968166 Total UI for P1: 0, mck2ui 16
6895 11:03:43.971728 best dqsien dly found for B1: ( 0, 14, 24)
6896 11:03:43.975018 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6897 11:03:43.978394 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6898 11:03:43.978471
6899 11:03:43.984911 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6900 11:03:43.988137 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 11:03:43.988236 [Gating] SW calibration Done
6902 11:03:43.991707 ==
6903 11:03:43.994886 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 11:03:43.998292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 11:03:43.998370 ==
6906 11:03:43.998448 RX Vref Scan: 0
6907 11:03:43.998520
6908 11:03:44.001624 RX Vref 0 -> 0, step: 1
6909 11:03:44.001701
6910 11:03:44.004856 RX Delay -410 -> 252, step: 16
6911 11:03:44.008590 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6912 11:03:44.011513 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6913 11:03:44.018099 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6914 11:03:44.021547 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6915 11:03:44.025072 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6916 11:03:44.028213 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6917 11:03:44.034786 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6918 11:03:44.037990 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6919 11:03:44.041382 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6920 11:03:44.044829 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6921 11:03:44.051650 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6922 11:03:44.054977 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6923 11:03:44.058329 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6924 11:03:44.061630 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6925 11:03:44.068438 iDelay=230, Bit 14, Center -19 (-266 ~ 229) 496
6926 11:03:44.071548 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6927 11:03:44.071625 ==
6928 11:03:44.074678 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 11:03:44.077984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 11:03:44.078061 ==
6931 11:03:44.081605 DQS Delay:
6932 11:03:44.081682 DQS0 = 35, DQS1 = 35
6933 11:03:44.084825 DQM Delay:
6934 11:03:44.084901 DQM0 = 17, DQM1 = 12
6935 11:03:44.084993 DQ Delay:
6936 11:03:44.087957 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6937 11:03:44.091654 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6938 11:03:44.094976 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6939 11:03:44.098385 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6940 11:03:44.098461
6941 11:03:44.098546
6942 11:03:44.098617 ==
6943 11:03:44.101510 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 11:03:44.107940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 11:03:44.108017 ==
6946 11:03:44.108094
6947 11:03:44.108166
6948 11:03:44.108235 TX Vref Scan disable
6949 11:03:44.111159 == TX Byte 0 ==
6950 11:03:44.114819 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6951 11:03:44.118093 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6952 11:03:44.121322 == TX Byte 1 ==
6953 11:03:44.124709 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6954 11:03:44.127717 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6955 11:03:44.127798 ==
6956 11:03:44.131428 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 11:03:44.137689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 11:03:44.137767 ==
6959 11:03:44.137859
6960 11:03:44.137948
6961 11:03:44.138035 TX Vref Scan disable
6962 11:03:44.140925 == TX Byte 0 ==
6963 11:03:44.144340 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6964 11:03:44.147856 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6965 11:03:44.151178 == TX Byte 1 ==
6966 11:03:44.154367 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6967 11:03:44.157661 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6968 11:03:44.157737
6969 11:03:44.161306 [DATLAT]
6970 11:03:44.161383 Freq=400, CH1 RK1
6971 11:03:44.161458
6972 11:03:44.164515 DATLAT Default: 0xe
6973 11:03:44.164591 0, 0xFFFF, sum = 0
6974 11:03:44.167588 1, 0xFFFF, sum = 0
6975 11:03:44.167666 2, 0xFFFF, sum = 0
6976 11:03:44.171168 3, 0xFFFF, sum = 0
6977 11:03:44.171269 4, 0xFFFF, sum = 0
6978 11:03:44.174341 5, 0xFFFF, sum = 0
6979 11:03:44.174420 6, 0xFFFF, sum = 0
6980 11:03:44.178044 7, 0xFFFF, sum = 0
6981 11:03:44.178122 8, 0xFFFF, sum = 0
6982 11:03:44.180973 9, 0xFFFF, sum = 0
6983 11:03:44.184589 10, 0xFFFF, sum = 0
6984 11:03:44.184681 11, 0xFFFF, sum = 0
6985 11:03:44.187776 12, 0xFFFF, sum = 0
6986 11:03:44.187876 13, 0x0, sum = 1
6987 11:03:44.190847 14, 0x0, sum = 2
6988 11:03:44.190925 15, 0x0, sum = 3
6989 11:03:44.190984 16, 0x0, sum = 4
6990 11:03:44.194529 best_step = 14
6991 11:03:44.194603
6992 11:03:44.194660 ==
6993 11:03:44.197781 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 11:03:44.201092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 11:03:44.201185 ==
6996 11:03:44.204432 RX Vref Scan: 0
6997 11:03:44.204506
6998 11:03:44.204563 RX Vref 0 -> 0, step: 1
6999 11:03:44.207601
7000 11:03:44.207674 RX Delay -311 -> 252, step: 8
7001 11:03:44.215984 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
7002 11:03:44.219306 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7003 11:03:44.222547 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7004 11:03:44.226075 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
7005 11:03:44.232538 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7006 11:03:44.236003 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7007 11:03:44.239811 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
7008 11:03:44.243104 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7009 11:03:44.249364 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7010 11:03:44.252821 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7011 11:03:44.255866 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7012 11:03:44.259115 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7013 11:03:44.265920 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7014 11:03:44.269118 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7015 11:03:44.272305 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7016 11:03:44.278869 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7017 11:03:44.278949 ==
7018 11:03:44.282206 Dram Type= 6, Freq= 0, CH_1, rank 1
7019 11:03:44.285893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7020 11:03:44.285965 ==
7021 11:03:44.286037 DQS Delay:
7022 11:03:44.288930 DQS0 = 32, DQS1 = 36
7023 11:03:44.289016 DQM Delay:
7024 11:03:44.292452 DQM0 = 14, DQM1 = 12
7025 11:03:44.292545 DQ Delay:
7026 11:03:44.295567 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
7027 11:03:44.298696 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7028 11:03:44.301970 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7029 11:03:44.305365 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7030 11:03:44.305436
7031 11:03:44.305525
7032 11:03:44.311940 [DQSOSCAuto] RK1, (LSB)MR18= 0xb15a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
7033 11:03:44.315582 CH1 RK1: MR19=C0C, MR18=B15A
7034 11:03:44.321841 CH1_RK1: MR19=0xC0C, MR18=0xB15A, DQSOSC=387, MR23=63, INC=394, DEC=262
7035 11:03:44.325403 [RxdqsGatingPostProcess] freq 400
7036 11:03:44.331686 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7037 11:03:44.335461 best DQS0 dly(2T, 0.5T) = (0, 10)
7038 11:03:44.335527 best DQS1 dly(2T, 0.5T) = (0, 10)
7039 11:03:44.338500 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7040 11:03:44.341796 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7041 11:03:44.344991 best DQS0 dly(2T, 0.5T) = (0, 10)
7042 11:03:44.348571 best DQS1 dly(2T, 0.5T) = (0, 10)
7043 11:03:44.351522 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7044 11:03:44.355530 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7045 11:03:44.358245 Pre-setting of DQS Precalculation
7046 11:03:44.365334 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7047 11:03:44.371861 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7048 11:03:44.378263 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7049 11:03:44.378333
7050 11:03:44.378407
7051 11:03:44.381843 [Calibration Summary] 800 Mbps
7052 11:03:44.381908 CH 0, Rank 0
7053 11:03:44.384840 SW Impedance : PASS
7054 11:03:44.388572 DUTY Scan : NO K
7055 11:03:44.388637 ZQ Calibration : PASS
7056 11:03:44.391712 Jitter Meter : NO K
7057 11:03:44.394796 CBT Training : PASS
7058 11:03:44.394860 Write leveling : PASS
7059 11:03:44.398165 RX DQS gating : PASS
7060 11:03:44.398239 RX DQ/DQS(RDDQC) : PASS
7061 11:03:44.401610 TX DQ/DQS : PASS
7062 11:03:44.404886 RX DATLAT : PASS
7063 11:03:44.404956 RX DQ/DQS(Engine): PASS
7064 11:03:44.408145 TX OE : NO K
7065 11:03:44.408218 All Pass.
7066 11:03:44.408288
7067 11:03:44.411368 CH 0, Rank 1
7068 11:03:44.411437 SW Impedance : PASS
7069 11:03:44.415017 DUTY Scan : NO K
7070 11:03:44.417972 ZQ Calibration : PASS
7071 11:03:44.418036 Jitter Meter : NO K
7072 11:03:44.421356 CBT Training : PASS
7073 11:03:44.424612 Write leveling : NO K
7074 11:03:44.424706 RX DQS gating : PASS
7075 11:03:44.428397 RX DQ/DQS(RDDQC) : PASS
7076 11:03:44.431464 TX DQ/DQS : PASS
7077 11:03:44.431528 RX DATLAT : PASS
7078 11:03:44.435005 RX DQ/DQS(Engine): PASS
7079 11:03:44.437966 TX OE : NO K
7080 11:03:44.438030 All Pass.
7081 11:03:44.438099
7082 11:03:44.438165 CH 1, Rank 0
7083 11:03:44.441258 SW Impedance : PASS
7084 11:03:44.444585 DUTY Scan : NO K
7085 11:03:44.444648 ZQ Calibration : PASS
7086 11:03:44.448161 Jitter Meter : NO K
7087 11:03:44.451379 CBT Training : PASS
7088 11:03:44.451451 Write leveling : PASS
7089 11:03:44.454800 RX DQS gating : PASS
7090 11:03:44.454868 RX DQ/DQS(RDDQC) : PASS
7091 11:03:44.458255 TX DQ/DQS : PASS
7092 11:03:44.461279 RX DATLAT : PASS
7093 11:03:44.461352 RX DQ/DQS(Engine): PASS
7094 11:03:44.464697 TX OE : NO K
7095 11:03:44.464788 All Pass.
7096 11:03:44.464883
7097 11:03:44.467968 CH 1, Rank 1
7098 11:03:44.468033 SW Impedance : PASS
7099 11:03:44.471001 DUTY Scan : NO K
7100 11:03:44.474385 ZQ Calibration : PASS
7101 11:03:44.474452 Jitter Meter : NO K
7102 11:03:44.477994 CBT Training : PASS
7103 11:03:44.481171 Write leveling : NO K
7104 11:03:44.481238 RX DQS gating : PASS
7105 11:03:44.484311 RX DQ/DQS(RDDQC) : PASS
7106 11:03:44.487729 TX DQ/DQS : PASS
7107 11:03:44.487794 RX DATLAT : PASS
7108 11:03:44.490972 RX DQ/DQS(Engine): PASS
7109 11:03:44.494570 TX OE : NO K
7110 11:03:44.494634 All Pass.
7111 11:03:44.494703
7112 11:03:44.494770 DramC Write-DBI off
7113 11:03:44.497678 PER_BANK_REFRESH: Hybrid Mode
7114 11:03:44.501361 TX_TRACKING: ON
7115 11:03:44.507778 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7116 11:03:44.511504 [FAST_K] Save calibration result to emmc
7117 11:03:44.517973 dramc_set_vcore_voltage set vcore to 725000
7118 11:03:44.518042 Read voltage for 1600, 0
7119 11:03:44.521240 Vio18 = 0
7120 11:03:44.521312 Vcore = 725000
7121 11:03:44.521401 Vdram = 0
7122 11:03:44.524505 Vddq = 0
7123 11:03:44.524597 Vmddr = 0
7124 11:03:44.527883 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7125 11:03:44.534501 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7126 11:03:44.537970 MEM_TYPE=3, freq_sel=13
7127 11:03:44.538037 sv_algorithm_assistance_LP4_3733
7128 11:03:44.544568 ============ PULL DRAM RESETB DOWN ============
7129 11:03:44.547534 ========== PULL DRAM RESETB DOWN end =========
7130 11:03:44.551145 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7131 11:03:44.554378 ===================================
7132 11:03:44.557623 LPDDR4 DRAM CONFIGURATION
7133 11:03:44.560862 ===================================
7134 11:03:44.564424 EX_ROW_EN[0] = 0x0
7135 11:03:44.564510 EX_ROW_EN[1] = 0x0
7136 11:03:44.567657 LP4Y_EN = 0x0
7137 11:03:44.567723 WORK_FSP = 0x1
7138 11:03:44.571077 WL = 0x5
7139 11:03:44.571166 RL = 0x5
7140 11:03:44.574561 BL = 0x2
7141 11:03:44.574631 RPST = 0x0
7142 11:03:44.577538 RD_PRE = 0x0
7143 11:03:44.577610 WR_PRE = 0x1
7144 11:03:44.581135 WR_PST = 0x1
7145 11:03:44.581214 DBI_WR = 0x0
7146 11:03:44.584519 DBI_RD = 0x0
7147 11:03:44.584588 OTF = 0x1
7148 11:03:44.587754 ===================================
7149 11:03:44.590877 ===================================
7150 11:03:44.594271 ANA top config
7151 11:03:44.597478 ===================================
7152 11:03:44.601100 DLL_ASYNC_EN = 0
7153 11:03:44.601183 ALL_SLAVE_EN = 0
7154 11:03:44.604240 NEW_RANK_MODE = 1
7155 11:03:44.607733 DLL_IDLE_MODE = 1
7156 11:03:44.610888 LP45_APHY_COMB_EN = 1
7157 11:03:44.610964 TX_ODT_DIS = 0
7158 11:03:44.614118 NEW_8X_MODE = 1
7159 11:03:44.617771 ===================================
7160 11:03:44.621122 ===================================
7161 11:03:44.624426 data_rate = 3200
7162 11:03:44.627704 CKR = 1
7163 11:03:44.630936 DQ_P2S_RATIO = 8
7164 11:03:44.634250 ===================================
7165 11:03:44.637769 CA_P2S_RATIO = 8
7166 11:03:44.637843 DQ_CA_OPEN = 0
7167 11:03:44.640673 DQ_SEMI_OPEN = 0
7168 11:03:44.644352 CA_SEMI_OPEN = 0
7169 11:03:44.647627 CA_FULL_RATE = 0
7170 11:03:44.651279 DQ_CKDIV4_EN = 0
7171 11:03:44.654364 CA_CKDIV4_EN = 0
7172 11:03:44.654438 CA_PREDIV_EN = 0
7173 11:03:44.657473 PH8_DLY = 12
7174 11:03:44.660859 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7175 11:03:44.664479 DQ_AAMCK_DIV = 4
7176 11:03:44.667390 CA_AAMCK_DIV = 4
7177 11:03:44.670961 CA_ADMCK_DIV = 4
7178 11:03:44.671035 DQ_TRACK_CA_EN = 0
7179 11:03:44.674273 CA_PICK = 1600
7180 11:03:44.678015 CA_MCKIO = 1600
7181 11:03:44.680900 MCKIO_SEMI = 0
7182 11:03:44.684460 PLL_FREQ = 3068
7183 11:03:44.687523 DQ_UI_PI_RATIO = 32
7184 11:03:44.691050 CA_UI_PI_RATIO = 0
7185 11:03:44.694110 ===================================
7186 11:03:44.697315 ===================================
7187 11:03:44.697387 memory_type:LPDDR4
7188 11:03:44.701002 GP_NUM : 10
7189 11:03:44.704239 SRAM_EN : 1
7190 11:03:44.704311 MD32_EN : 0
7191 11:03:44.707567 ===================================
7192 11:03:44.710669 [ANA_INIT] >>>>>>>>>>>>>>
7193 11:03:44.714233 <<<<<< [CONFIGURE PHASE]: ANA_TX
7194 11:03:44.717641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7195 11:03:44.720871 ===================================
7196 11:03:44.724061 data_rate = 3200,PCW = 0X7600
7197 11:03:44.727392 ===================================
7198 11:03:44.730642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7199 11:03:44.733920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7200 11:03:44.740574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 11:03:44.743764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7202 11:03:44.747484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7203 11:03:44.750742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7204 11:03:44.754009 [ANA_INIT] flow start
7205 11:03:44.757394 [ANA_INIT] PLL >>>>>>>>
7206 11:03:44.757461 [ANA_INIT] PLL <<<<<<<<
7207 11:03:44.760590 [ANA_INIT] MIDPI >>>>>>>>
7208 11:03:44.763814 [ANA_INIT] MIDPI <<<<<<<<
7209 11:03:44.763880 [ANA_INIT] DLL >>>>>>>>
7210 11:03:44.767070 [ANA_INIT] DLL <<<<<<<<
7211 11:03:44.770555 [ANA_INIT] flow end
7212 11:03:44.773902 ============ LP4 DIFF to SE enter ============
7213 11:03:44.777245 ============ LP4 DIFF to SE exit ============
7214 11:03:44.780490 [ANA_INIT] <<<<<<<<<<<<<
7215 11:03:44.783804 [Flow] Enable top DCM control >>>>>
7216 11:03:44.787197 [Flow] Enable top DCM control <<<<<
7217 11:03:44.790381 Enable DLL master slave shuffle
7218 11:03:44.793718 ==============================================================
7219 11:03:44.797366 Gating Mode config
7220 11:03:44.803943 ==============================================================
7221 11:03:44.804056 Config description:
7222 11:03:44.813793 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7223 11:03:44.820577 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7224 11:03:44.823659 SELPH_MODE 0: By rank 1: By Phase
7225 11:03:44.830432 ==============================================================
7226 11:03:44.834157 GAT_TRACK_EN = 1
7227 11:03:44.837457 RX_GATING_MODE = 2
7228 11:03:44.840327 RX_GATING_TRACK_MODE = 2
7229 11:03:44.844029 SELPH_MODE = 1
7230 11:03:44.847227 PICG_EARLY_EN = 1
7231 11:03:44.850353 VALID_LAT_VALUE = 1
7232 11:03:44.853941 ==============================================================
7233 11:03:44.857105 Enter into Gating configuration >>>>
7234 11:03:44.860258 Exit from Gating configuration <<<<
7235 11:03:44.863603 Enter into DVFS_PRE_config >>>>>
7236 11:03:44.876878 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7237 11:03:44.876955 Exit from DVFS_PRE_config <<<<<
7238 11:03:44.880161 Enter into PICG configuration >>>>
7239 11:03:44.883438 Exit from PICG configuration <<<<
7240 11:03:44.886857 [RX_INPUT] configuration >>>>>
7241 11:03:44.890552 [RX_INPUT] configuration <<<<<
7242 11:03:44.897212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7243 11:03:44.900305 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7244 11:03:44.907066 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 11:03:44.913651 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 11:03:44.920268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 11:03:44.926837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 11:03:44.930100 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7249 11:03:44.933665 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7250 11:03:44.936998 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7251 11:03:44.943512 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7252 11:03:44.946827 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7253 11:03:44.950098 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7254 11:03:44.953716 ===================================
7255 11:03:44.956991 LPDDR4 DRAM CONFIGURATION
7256 11:03:44.960171 ===================================
7257 11:03:44.960237 EX_ROW_EN[0] = 0x0
7258 11:03:44.963441 EX_ROW_EN[1] = 0x0
7259 11:03:44.966609 LP4Y_EN = 0x0
7260 11:03:44.966674 WORK_FSP = 0x1
7261 11:03:44.970330 WL = 0x5
7262 11:03:44.970394 RL = 0x5
7263 11:03:44.973471 BL = 0x2
7264 11:03:44.973560 RPST = 0x0
7265 11:03:44.976767 RD_PRE = 0x0
7266 11:03:44.976840 WR_PRE = 0x1
7267 11:03:44.979925 WR_PST = 0x1
7268 11:03:44.979991 DBI_WR = 0x0
7269 11:03:44.983565 DBI_RD = 0x0
7270 11:03:44.983633 OTF = 0x1
7271 11:03:44.986902 ===================================
7272 11:03:44.990113 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7273 11:03:44.996608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7274 11:03:45.000033 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7275 11:03:45.003239 ===================================
7276 11:03:45.006523 LPDDR4 DRAM CONFIGURATION
7277 11:03:45.009745 ===================================
7278 11:03:45.009818 EX_ROW_EN[0] = 0x10
7279 11:03:45.013160 EX_ROW_EN[1] = 0x0
7280 11:03:45.016645 LP4Y_EN = 0x0
7281 11:03:45.016734 WORK_FSP = 0x1
7282 11:03:45.019716 WL = 0x5
7283 11:03:45.019785 RL = 0x5
7284 11:03:45.023024 BL = 0x2
7285 11:03:45.023099 RPST = 0x0
7286 11:03:45.026305 RD_PRE = 0x0
7287 11:03:45.026372 WR_PRE = 0x1
7288 11:03:45.029759 WR_PST = 0x1
7289 11:03:45.029853 DBI_WR = 0x0
7290 11:03:45.033211 DBI_RD = 0x0
7291 11:03:45.033276 OTF = 0x1
7292 11:03:45.036211 ===================================
7293 11:03:45.042925 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7294 11:03:45.042993 ==
7295 11:03:45.046561 Dram Type= 6, Freq= 0, CH_0, rank 0
7296 11:03:45.049768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 11:03:45.049839 ==
7298 11:03:45.053068 [Duty_Offset_Calibration]
7299 11:03:45.056145 B0:2 B1:0 CA:1
7300 11:03:45.056209
7301 11:03:45.059757 [DutyScan_Calibration_Flow] k_type=0
7302 11:03:45.067618
7303 11:03:45.067685 ==CLK 0==
7304 11:03:45.070799 Final CLK duty delay cell = -4
7305 11:03:45.074183 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7306 11:03:45.077374 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7307 11:03:45.080794 [-4] AVG Duty = 4922%(X100)
7308 11:03:45.080863
7309 11:03:45.083993 CH0 CLK Duty spec in!! Max-Min= 218%
7310 11:03:45.087203 [DutyScan_Calibration_Flow] ====Done====
7311 11:03:45.087272
7312 11:03:45.090863 [DutyScan_Calibration_Flow] k_type=1
7313 11:03:45.106807
7314 11:03:45.106878 ==DQS 0 ==
7315 11:03:45.109975 Final DQS duty delay cell = 0
7316 11:03:45.113218 [0] MAX Duty = 5218%(X100), DQS PI = 34
7317 11:03:45.116801 [0] MIN Duty = 4938%(X100), DQS PI = 62
7318 11:03:45.120343 [0] AVG Duty = 5078%(X100)
7319 11:03:45.120419
7320 11:03:45.120477 ==DQS 1 ==
7321 11:03:45.123380 Final DQS duty delay cell = -4
7322 11:03:45.126659 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7323 11:03:45.129998 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7324 11:03:45.133375 [-4] AVG Duty = 4984%(X100)
7325 11:03:45.133472
7326 11:03:45.136990 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7327 11:03:45.137064
7328 11:03:45.140238 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7329 11:03:45.143397 [DutyScan_Calibration_Flow] ====Done====
7330 11:03:45.143473
7331 11:03:45.146662 [DutyScan_Calibration_Flow] k_type=3
7332 11:03:45.164460
7333 11:03:45.164554 ==DQM 0 ==
7334 11:03:45.167699 Final DQM duty delay cell = 0
7335 11:03:45.170900 [0] MAX Duty = 5062%(X100), DQS PI = 12
7336 11:03:45.174294 [0] MIN Duty = 4813%(X100), DQS PI = 50
7337 11:03:45.177623 [0] AVG Duty = 4937%(X100)
7338 11:03:45.177697
7339 11:03:45.177754 ==DQM 1 ==
7340 11:03:45.181012 Final DQM duty delay cell = 0
7341 11:03:45.184166 [0] MAX Duty = 5249%(X100), DQS PI = 30
7342 11:03:45.187421 [0] MIN Duty = 5000%(X100), DQS PI = 18
7343 11:03:45.191158 [0] AVG Duty = 5124%(X100)
7344 11:03:45.191232
7345 11:03:45.194552 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7346 11:03:45.194627
7347 11:03:45.197804 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7348 11:03:45.201083 [DutyScan_Calibration_Flow] ====Done====
7349 11:03:45.201176
7350 11:03:45.204308 [DutyScan_Calibration_Flow] k_type=2
7351 11:03:45.221641
7352 11:03:45.221715 ==DQ 0 ==
7353 11:03:45.224760 Final DQ duty delay cell = 0
7354 11:03:45.228116 [0] MAX Duty = 5124%(X100), DQS PI = 34
7355 11:03:45.231777 [0] MIN Duty = 5000%(X100), DQS PI = 0
7356 11:03:45.231852 [0] AVG Duty = 5062%(X100)
7357 11:03:45.231909
7358 11:03:45.234910 ==DQ 1 ==
7359 11:03:45.238244 Final DQ duty delay cell = 0
7360 11:03:45.241649 [0] MAX Duty = 4969%(X100), DQS PI = 44
7361 11:03:45.244855 [0] MIN Duty = 4875%(X100), DQS PI = 10
7362 11:03:45.244932 [0] AVG Duty = 4922%(X100)
7363 11:03:45.245024
7364 11:03:45.248524 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7365 11:03:45.248601
7366 11:03:45.251790 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7367 11:03:45.258374 [DutyScan_Calibration_Flow] ====Done====
7368 11:03:45.258451 ==
7369 11:03:45.261589 Dram Type= 6, Freq= 0, CH_1, rank 0
7370 11:03:45.264727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7371 11:03:45.264826 ==
7372 11:03:45.268228 [Duty_Offset_Calibration]
7373 11:03:45.268301 B0:0 B1:-1 CA:2
7374 11:03:45.268358
7375 11:03:45.271556 [DutyScan_Calibration_Flow] k_type=0
7376 11:03:45.281578
7377 11:03:45.281651 ==CLK 0==
7378 11:03:45.285612 Final CLK duty delay cell = 0
7379 11:03:45.288576 [0] MAX Duty = 5156%(X100), DQS PI = 10
7380 11:03:45.291798 [0] MIN Duty = 4906%(X100), DQS PI = 46
7381 11:03:45.291872 [0] AVG Duty = 5031%(X100)
7382 11:03:45.294973
7383 11:03:45.295047 CH1 CLK Duty spec in!! Max-Min= 250%
7384 11:03:45.301986 [DutyScan_Calibration_Flow] ====Done====
7385 11:03:45.302060
7386 11:03:45.304734 [DutyScan_Calibration_Flow] k_type=1
7387 11:03:45.321700
7388 11:03:45.321773 ==DQS 0 ==
7389 11:03:45.324812 Final DQS duty delay cell = 0
7390 11:03:45.328236 [0] MAX Duty = 5093%(X100), DQS PI = 24
7391 11:03:45.331512 [0] MIN Duty = 5000%(X100), DQS PI = 0
7392 11:03:45.331586 [0] AVG Duty = 5046%(X100)
7393 11:03:45.334629
7394 11:03:45.334703 ==DQS 1 ==
7395 11:03:45.338321 Final DQS duty delay cell = 0
7396 11:03:45.341386 [0] MAX Duty = 5187%(X100), DQS PI = 0
7397 11:03:45.344876 [0] MIN Duty = 4844%(X100), DQS PI = 32
7398 11:03:45.344943 [0] AVG Duty = 5015%(X100)
7399 11:03:45.348193
7400 11:03:45.348259 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7401 11:03:45.351565
7402 11:03:45.354802 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7403 11:03:45.358024 [DutyScan_Calibration_Flow] ====Done====
7404 11:03:45.358090
7405 11:03:45.361354 [DutyScan_Calibration_Flow] k_type=3
7406 11:03:45.378955
7407 11:03:45.379023 ==DQM 0 ==
7408 11:03:45.382169 Final DQM duty delay cell = 4
7409 11:03:45.385629 [4] MAX Duty = 5125%(X100), DQS PI = 8
7410 11:03:45.388849 [4] MIN Duty = 4969%(X100), DQS PI = 46
7411 11:03:45.388907 [4] AVG Duty = 5047%(X100)
7412 11:03:45.392202
7413 11:03:45.392265 ==DQM 1 ==
7414 11:03:45.395660 Final DQM duty delay cell = 0
7415 11:03:45.398767 [0] MAX Duty = 5281%(X100), DQS PI = 58
7416 11:03:45.402020 [0] MIN Duty = 4876%(X100), DQS PI = 34
7417 11:03:45.402091 [0] AVG Duty = 5078%(X100)
7418 11:03:45.405328
7419 11:03:45.409046 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7420 11:03:45.409139
7421 11:03:45.412309 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7422 11:03:45.415374 [DutyScan_Calibration_Flow] ====Done====
7423 11:03:45.415433
7424 11:03:45.418527 [DutyScan_Calibration_Flow] k_type=2
7425 11:03:45.435664
7426 11:03:45.435733 ==DQ 0 ==
7427 11:03:45.439080 Final DQ duty delay cell = 0
7428 11:03:45.442301 [0] MAX Duty = 5062%(X100), DQS PI = 18
7429 11:03:45.445968 [0] MIN Duty = 4969%(X100), DQS PI = 0
7430 11:03:45.446029 [0] AVG Duty = 5015%(X100)
7431 11:03:45.446088
7432 11:03:45.449121 ==DQ 1 ==
7433 11:03:45.452342 Final DQ duty delay cell = 0
7434 11:03:45.455928 [0] MAX Duty = 5062%(X100), DQS PI = 2
7435 11:03:45.459072 [0] MIN Duty = 4813%(X100), DQS PI = 34
7436 11:03:45.459132 [0] AVG Duty = 4937%(X100)
7437 11:03:45.459183
7438 11:03:45.462583 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7439 11:03:45.462667
7440 11:03:45.466102 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7441 11:03:45.469360 [DutyScan_Calibration_Flow] ====Done====
7442 11:03:45.474677 nWR fixed to 30
7443 11:03:45.477947 [ModeRegInit_LP4] CH0 RK0
7444 11:03:45.478024 [ModeRegInit_LP4] CH0 RK1
7445 11:03:45.481258 [ModeRegInit_LP4] CH1 RK0
7446 11:03:45.484515 [ModeRegInit_LP4] CH1 RK1
7447 11:03:45.484591 match AC timing 5
7448 11:03:45.491499 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7449 11:03:45.494786 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7450 11:03:45.497954 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7451 11:03:45.504500 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7452 11:03:45.507900 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7453 11:03:45.507977 [MiockJmeterHQA]
7454 11:03:45.508053
7455 11:03:45.511232 [DramcMiockJmeter] u1RxGatingPI = 0
7456 11:03:45.514838 0 : 4252, 4027
7457 11:03:45.514916 4 : 4252, 4026
7458 11:03:45.517812 8 : 4255, 4029
7459 11:03:45.517890 12 : 4252, 4027
7460 11:03:45.521431 16 : 4252, 4027
7461 11:03:45.521509 20 : 4255, 4030
7462 11:03:45.521587 24 : 4253, 4026
7463 11:03:45.524651 28 : 4363, 4137
7464 11:03:45.524728 32 : 4252, 4027
7465 11:03:45.528324 36 : 4253, 4027
7466 11:03:45.528402 40 : 4252, 4026
7467 11:03:45.531604 44 : 4363, 4138
7468 11:03:45.531682 48 : 4255, 4030
7469 11:03:45.531760 52 : 4361, 4138
7470 11:03:45.534752 56 : 4250, 4027
7471 11:03:45.534831 60 : 4250, 4027
7472 11:03:45.538083 64 : 4250, 4027
7473 11:03:45.538161 68 : 4250, 4027
7474 11:03:45.541364 72 : 4361, 4138
7475 11:03:45.541442 76 : 4250, 4026
7476 11:03:45.545014 80 : 4361, 4137
7477 11:03:45.545116 84 : 4250, 4027
7478 11:03:45.545204 88 : 4250, 3743
7479 11:03:45.548182 92 : 4250, 0
7480 11:03:45.548260 96 : 4361, 0
7481 11:03:45.551271 100 : 4250, 0
7482 11:03:45.551349 104 : 4363, 0
7483 11:03:45.551426 108 : 4250, 0
7484 11:03:45.554934 112 : 4249, 0
7485 11:03:45.555013 116 : 4363, 0
7486 11:03:45.555090 120 : 4361, 0
7487 11:03:45.558303 124 : 4363, 0
7488 11:03:45.558380 128 : 4250, 0
7489 11:03:45.561114 132 : 4250, 0
7490 11:03:45.561201 136 : 4250, 0
7491 11:03:45.561278 140 : 4250, 0
7492 11:03:45.564589 144 : 4250, 0
7493 11:03:45.564667 148 : 4250, 0
7494 11:03:45.567959 152 : 4250, 0
7495 11:03:45.568037 156 : 4250, 0
7496 11:03:45.568115 160 : 4361, 0
7497 11:03:45.571580 164 : 4250, 0
7498 11:03:45.571657 168 : 4250, 0
7499 11:03:45.574710 172 : 4361, 0
7500 11:03:45.574788 176 : 4361, 0
7501 11:03:45.574866 180 : 4250, 0
7502 11:03:45.577918 184 : 4250, 0
7503 11:03:45.577996 188 : 4250, 0
7504 11:03:45.578074 192 : 4249, 0
7505 11:03:45.581132 196 : 4250, 0
7506 11:03:45.581240 200 : 4252, 7
7507 11:03:45.584760 204 : 4250, 2791
7508 11:03:45.584838 208 : 4250, 4027
7509 11:03:45.588011 212 : 4361, 4138
7510 11:03:45.588089 216 : 4361, 4138
7511 11:03:45.591368 220 : 4248, 4024
7512 11:03:45.591446 224 : 4361, 4137
7513 11:03:45.594512 228 : 4361, 4138
7514 11:03:45.594590 232 : 4250, 4027
7515 11:03:45.594668 236 : 4250, 4027
7516 11:03:45.597630 240 : 4250, 4027
7517 11:03:45.597732 244 : 4250, 4027
7518 11:03:45.601016 248 : 4252, 4027
7519 11:03:45.601117 252 : 4250, 4026
7520 11:03:45.604480 256 : 4250, 4027
7521 11:03:45.604582 260 : 4250, 4027
7522 11:03:45.607558 264 : 4361, 4138
7523 11:03:45.607636 268 : 4360, 4137
7524 11:03:45.610943 272 : 4248, 4024
7525 11:03:45.611021 276 : 4361, 4137
7526 11:03:45.614215 280 : 4361, 4138
7527 11:03:45.614293 284 : 4250, 4027
7528 11:03:45.617712 288 : 4250, 4027
7529 11:03:45.617790 292 : 4250, 4027
7530 11:03:45.621134 296 : 4250, 4026
7531 11:03:45.621211 300 : 4252, 4027
7532 11:03:45.621288 304 : 4250, 4027
7533 11:03:45.624164 308 : 4250, 4027
7534 11:03:45.624243 312 : 4250, 3904
7535 11:03:45.627316 316 : 4361, 1945
7536 11:03:45.627394
7537 11:03:45.630862 MIOCK jitter meter ch=0
7538 11:03:45.630939
7539 11:03:45.631014 1T = (316-92) = 224 dly cells
7540 11:03:45.637709 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7541 11:03:45.637787 ==
7542 11:03:45.640739 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 11:03:45.644132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 11:03:45.647334 ==
7545 11:03:45.651006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 11:03:45.654229 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 11:03:45.660509 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 11:03:45.667023 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 11:03:45.674742 [CA 0] Center 42 (12~72) winsize 61
7550 11:03:45.677791 [CA 1] Center 42 (12~72) winsize 61
7551 11:03:45.680924 [CA 2] Center 37 (7~67) winsize 61
7552 11:03:45.684281 [CA 3] Center 37 (7~67) winsize 61
7553 11:03:45.688077 [CA 4] Center 36 (6~66) winsize 61
7554 11:03:45.691223 [CA 5] Center 35 (5~65) winsize 61
7555 11:03:45.691323
7556 11:03:45.694509 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 11:03:45.694586
7558 11:03:45.697826 [CATrainingPosCal] consider 1 rank data
7559 11:03:45.700928 u2DelayCellTimex100 = 290/100 ps
7560 11:03:45.704302 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7561 11:03:45.711337 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7562 11:03:45.714430 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7563 11:03:45.717543 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7564 11:03:45.720819 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7565 11:03:45.724497 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7566 11:03:45.724574
7567 11:03:45.727832 CA PerBit enable=1, Macro0, CA PI delay=35
7568 11:03:45.727908
7569 11:03:45.730944 [CBTSetCACLKResult] CA Dly = 35
7570 11:03:45.731021 CS Dly: 9 (0~40)
7571 11:03:45.737710 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 11:03:45.740841 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 11:03:45.740939 ==
7574 11:03:45.744314 Dram Type= 6, Freq= 0, CH_0, rank 1
7575 11:03:45.747412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 11:03:45.747489 ==
7577 11:03:45.754204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7578 11:03:45.757518 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7579 11:03:45.764505 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7580 11:03:45.767305 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7581 11:03:45.777715 [CA 0] Center 43 (13~74) winsize 62
7582 11:03:45.780833 [CA 1] Center 43 (13~73) winsize 61
7583 11:03:45.784219 [CA 2] Center 38 (9~68) winsize 60
7584 11:03:45.787841 [CA 3] Center 38 (9~68) winsize 60
7585 11:03:45.791071 [CA 4] Center 37 (7~67) winsize 61
7586 11:03:45.794426 [CA 5] Center 36 (6~66) winsize 61
7587 11:03:45.794508
7588 11:03:45.797725 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7589 11:03:45.797824
7590 11:03:45.800798 [CATrainingPosCal] consider 2 rank data
7591 11:03:45.804101 u2DelayCellTimex100 = 290/100 ps
7592 11:03:45.807553 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7593 11:03:45.814373 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7594 11:03:45.817479 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7595 11:03:45.821069 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7596 11:03:45.824370 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7597 11:03:45.827733 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7598 11:03:45.827810
7599 11:03:45.831035 CA PerBit enable=1, Macro0, CA PI delay=35
7600 11:03:45.831120
7601 11:03:45.834205 [CBTSetCACLKResult] CA Dly = 35
7602 11:03:45.837584 CS Dly: 10 (0~43)
7603 11:03:45.840774 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7604 11:03:45.844121 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7605 11:03:45.844190
7606 11:03:45.847309 ----->DramcWriteLeveling(PI) begin...
7607 11:03:45.847382 ==
7608 11:03:45.850944 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 11:03:45.857383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 11:03:45.857461 ==
7611 11:03:45.861031 Write leveling (Byte 0): 37 => 37
7612 11:03:45.861160 Write leveling (Byte 1): 31 => 31
7613 11:03:45.863931 DramcWriteLeveling(PI) end<-----
7614 11:03:45.864090
7615 11:03:45.864280 ==
7616 11:03:45.867720 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 11:03:45.873838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 11:03:45.873917 ==
7619 11:03:45.877519 [Gating] SW mode calibration
7620 11:03:45.883961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7621 11:03:45.887367 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7622 11:03:45.894046 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 11:03:45.897301 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 11:03:45.900522 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
7625 11:03:45.907081 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7626 11:03:45.910624 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7627 11:03:45.913967 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 11:03:45.920526 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 11:03:45.924085 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 11:03:45.927290 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 11:03:45.930539 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 11:03:45.937397 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
7633 11:03:45.940560 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7634 11:03:45.943891 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7635 11:03:45.950716 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
7636 11:03:45.953990 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 11:03:45.956917 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 11:03:45.963881 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 11:03:45.967295 1 6 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7640 11:03:45.970330 1 6 8 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
7641 11:03:45.977095 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7642 11:03:45.980251 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7643 11:03:45.983903 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7644 11:03:45.990402 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 11:03:45.993662 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 11:03:45.997347 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 11:03:46.003692 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 11:03:46.007173 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7649 11:03:46.010759 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7650 11:03:46.017372 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7651 11:03:46.020360 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7652 11:03:46.023819 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:03:46.030470 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:03:46.033876 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:03:46.037028 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:03:46.043655 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:03:46.046883 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:03:46.050987 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:03:46.054013 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:03:46.060531 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:03:46.063766 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:03:46.067160 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:03:46.073603 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:03:46.077198 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7665 11:03:46.080362 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7666 11:03:46.086750 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7667 11:03:46.090192 Total UI for P1: 0, mck2ui 16
7668 11:03:46.093394 best dqsien dly found for B0: ( 1, 9, 10)
7669 11:03:46.096675 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7670 11:03:46.099940 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 11:03:46.103265 Total UI for P1: 0, mck2ui 16
7672 11:03:46.106439 best dqsien dly found for B1: ( 1, 9, 20)
7673 11:03:46.110211 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7674 11:03:46.113453 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7675 11:03:46.113528
7676 11:03:46.119909 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7677 11:03:46.123292 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7678 11:03:46.126305 [Gating] SW calibration Done
7679 11:03:46.126380 ==
7680 11:03:46.129677 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 11:03:46.133078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 11:03:46.133209 ==
7683 11:03:46.133270 RX Vref Scan: 0
7684 11:03:46.136321
7685 11:03:46.136395 RX Vref 0 -> 0, step: 1
7686 11:03:46.136463
7687 11:03:46.139650 RX Delay 0 -> 252, step: 8
7688 11:03:46.142995 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7689 11:03:46.146418 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7690 11:03:46.153061 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7691 11:03:46.156385 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7692 11:03:46.159676 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7693 11:03:46.162906 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7694 11:03:46.166142 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7695 11:03:46.169891 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7696 11:03:46.176574 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7697 11:03:46.179700 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7698 11:03:46.182943 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7699 11:03:46.186443 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7700 11:03:46.192798 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7701 11:03:46.196437 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7702 11:03:46.199771 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7703 11:03:46.203077 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7704 11:03:46.203152 ==
7705 11:03:46.206269 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 11:03:46.209543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 11:03:46.212740 ==
7708 11:03:46.212823 DQS Delay:
7709 11:03:46.212883 DQS0 = 0, DQS1 = 0
7710 11:03:46.215877 DQM Delay:
7711 11:03:46.215944 DQM0 = 137, DQM1 = 126
7712 11:03:46.219245 DQ Delay:
7713 11:03:46.222552 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7714 11:03:46.225827 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7715 11:03:46.229058 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7716 11:03:46.232850 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7717 11:03:46.232911
7718 11:03:46.232972
7719 11:03:46.233024 ==
7720 11:03:46.235999 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 11:03:46.239272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 11:03:46.239340 ==
7723 11:03:46.239393
7724 11:03:46.242701
7725 11:03:46.242809 TX Vref Scan disable
7726 11:03:46.245917 == TX Byte 0 ==
7727 11:03:46.249439 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7728 11:03:46.252483 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7729 11:03:46.255798 == TX Byte 1 ==
7730 11:03:46.259206 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7731 11:03:46.262449 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7732 11:03:46.262510 ==
7733 11:03:46.265903 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 11:03:46.272501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 11:03:46.272572 ==
7736 11:03:46.284200
7737 11:03:46.287821 TX Vref early break, caculate TX vref
7738 11:03:46.290992 TX Vref=16, minBit 11, minWin=22, winSum=374
7739 11:03:46.294551 TX Vref=18, minBit 7, minWin=23, winSum=387
7740 11:03:46.297796 TX Vref=20, minBit 7, minWin=23, winSum=398
7741 11:03:46.301092 TX Vref=22, minBit 7, minWin=24, winSum=404
7742 11:03:46.304307 TX Vref=24, minBit 7, minWin=25, winSum=418
7743 11:03:46.310926 TX Vref=26, minBit 4, minWin=25, winSum=422
7744 11:03:46.314559 TX Vref=28, minBit 0, minWin=25, winSum=426
7745 11:03:46.317816 TX Vref=30, minBit 1, minWin=25, winSum=418
7746 11:03:46.321080 TX Vref=32, minBit 7, minWin=24, winSum=410
7747 11:03:46.324329 TX Vref=34, minBit 0, minWin=24, winSum=398
7748 11:03:46.330871 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
7749 11:03:46.330941
7750 11:03:46.334184 Final TX Range 0 Vref 28
7751 11:03:46.334252
7752 11:03:46.334306 ==
7753 11:03:46.337978 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 11:03:46.340825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 11:03:46.340887 ==
7756 11:03:46.340938
7757 11:03:46.340987
7758 11:03:46.344304 TX Vref Scan disable
7759 11:03:46.351046 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7760 11:03:46.351117 == TX Byte 0 ==
7761 11:03:46.354555 u2DelayCellOfst[0]=13 cells (4 PI)
7762 11:03:46.358060 u2DelayCellOfst[1]=20 cells (6 PI)
7763 11:03:46.361337 u2DelayCellOfst[2]=13 cells (4 PI)
7764 11:03:46.364430 u2DelayCellOfst[3]=13 cells (4 PI)
7765 11:03:46.367798 u2DelayCellOfst[4]=10 cells (3 PI)
7766 11:03:46.371288 u2DelayCellOfst[5]=0 cells (0 PI)
7767 11:03:46.374367 u2DelayCellOfst[6]=20 cells (6 PI)
7768 11:03:46.374437 u2DelayCellOfst[7]=16 cells (5 PI)
7769 11:03:46.380860 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7770 11:03:46.384180 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7771 11:03:46.387545 == TX Byte 1 ==
7772 11:03:46.387611 u2DelayCellOfst[8]=0 cells (0 PI)
7773 11:03:46.390978 u2DelayCellOfst[9]=0 cells (0 PI)
7774 11:03:46.394534 u2DelayCellOfst[10]=6 cells (2 PI)
7775 11:03:46.397928 u2DelayCellOfst[11]=3 cells (1 PI)
7776 11:03:46.400956 u2DelayCellOfst[12]=13 cells (4 PI)
7777 11:03:46.404224 u2DelayCellOfst[13]=10 cells (3 PI)
7778 11:03:46.407587 u2DelayCellOfst[14]=13 cells (4 PI)
7779 11:03:46.410892 u2DelayCellOfst[15]=10 cells (3 PI)
7780 11:03:46.414163 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7781 11:03:46.420745 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7782 11:03:46.420849 DramC Write-DBI on
7783 11:03:46.420926 ==
7784 11:03:46.424043 Dram Type= 6, Freq= 0, CH_0, rank 0
7785 11:03:46.427332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7786 11:03:46.430555 ==
7787 11:03:46.430632
7788 11:03:46.430707
7789 11:03:46.430779 TX Vref Scan disable
7790 11:03:46.434272 == TX Byte 0 ==
7791 11:03:46.437604 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7792 11:03:46.440462 == TX Byte 1 ==
7793 11:03:46.443822 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7794 11:03:46.447296 DramC Write-DBI off
7795 11:03:46.447372
7796 11:03:46.447447 [DATLAT]
7797 11:03:46.447518 Freq=1600, CH0 RK0
7798 11:03:46.447588
7799 11:03:46.450599 DATLAT Default: 0xf
7800 11:03:46.450675 0, 0xFFFF, sum = 0
7801 11:03:46.453986 1, 0xFFFF, sum = 0
7802 11:03:46.457173 2, 0xFFFF, sum = 0
7803 11:03:46.457252 3, 0xFFFF, sum = 0
7804 11:03:46.460493 4, 0xFFFF, sum = 0
7805 11:03:46.460571 5, 0xFFFF, sum = 0
7806 11:03:46.463817 6, 0xFFFF, sum = 0
7807 11:03:46.463896 7, 0xFFFF, sum = 0
7808 11:03:46.467057 8, 0xFFFF, sum = 0
7809 11:03:46.467132 9, 0xFFFF, sum = 0
7810 11:03:46.470703 10, 0xFFFF, sum = 0
7811 11:03:46.470772 11, 0xFFFF, sum = 0
7812 11:03:46.473841 12, 0xFFFF, sum = 0
7813 11:03:46.473912 13, 0xFFFF, sum = 0
7814 11:03:46.477012 14, 0x0, sum = 1
7815 11:03:46.477079 15, 0x0, sum = 2
7816 11:03:46.480733 16, 0x0, sum = 3
7817 11:03:46.480793 17, 0x0, sum = 4
7818 11:03:46.483534 best_step = 15
7819 11:03:46.483600
7820 11:03:46.483651 ==
7821 11:03:46.486907 Dram Type= 6, Freq= 0, CH_0, rank 0
7822 11:03:46.490524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7823 11:03:46.490589 ==
7824 11:03:46.494013 RX Vref Scan: 1
7825 11:03:46.494071
7826 11:03:46.494121 Set Vref Range= 24 -> 127
7827 11:03:46.494169
7828 11:03:46.497532 RX Vref 24 -> 127, step: 1
7829 11:03:46.497594
7830 11:03:46.500508 RX Delay 19 -> 252, step: 4
7831 11:03:46.500573
7832 11:03:46.503652 Set Vref, RX VrefLevel [Byte0]: 24
7833 11:03:46.507007 [Byte1]: 24
7834 11:03:46.507084
7835 11:03:46.510317 Set Vref, RX VrefLevel [Byte0]: 25
7836 11:03:46.513634 [Byte1]: 25
7837 11:03:46.513697
7838 11:03:46.517114 Set Vref, RX VrefLevel [Byte0]: 26
7839 11:03:46.520220 [Byte1]: 26
7840 11:03:46.524374
7841 11:03:46.524443 Set Vref, RX VrefLevel [Byte0]: 27
7842 11:03:46.527572 [Byte1]: 27
7843 11:03:46.531707
7844 11:03:46.531769 Set Vref, RX VrefLevel [Byte0]: 28
7845 11:03:46.534970 [Byte1]: 28
7846 11:03:46.539607
7847 11:03:46.539667 Set Vref, RX VrefLevel [Byte0]: 29
7848 11:03:46.542536 [Byte1]: 29
7849 11:03:46.547170
7850 11:03:46.547229 Set Vref, RX VrefLevel [Byte0]: 30
7851 11:03:46.550354 [Byte1]: 30
7852 11:03:46.554491
7853 11:03:46.554552 Set Vref, RX VrefLevel [Byte0]: 31
7854 11:03:46.558157 [Byte1]: 31
7855 11:03:46.562122
7856 11:03:46.562189 Set Vref, RX VrefLevel [Byte0]: 32
7857 11:03:46.565529 [Byte1]: 32
7858 11:03:46.569673
7859 11:03:46.569736 Set Vref, RX VrefLevel [Byte0]: 33
7860 11:03:46.572976 [Byte1]: 33
7861 11:03:46.577074
7862 11:03:46.577163 Set Vref, RX VrefLevel [Byte0]: 34
7863 11:03:46.580518 [Byte1]: 34
7864 11:03:46.584996
7865 11:03:46.585055 Set Vref, RX VrefLevel [Byte0]: 35
7866 11:03:46.588157 [Byte1]: 35
7867 11:03:46.592350
7868 11:03:46.592410 Set Vref, RX VrefLevel [Byte0]: 36
7869 11:03:46.595931 [Byte1]: 36
7870 11:03:46.600071
7871 11:03:46.600144 Set Vref, RX VrefLevel [Byte0]: 37
7872 11:03:46.603387 [Byte1]: 37
7873 11:03:46.607559
7874 11:03:46.607618 Set Vref, RX VrefLevel [Byte0]: 38
7875 11:03:46.611030 [Byte1]: 38
7876 11:03:46.615447
7877 11:03:46.615529 Set Vref, RX VrefLevel [Byte0]: 39
7878 11:03:46.618737 [Byte1]: 39
7879 11:03:46.622516
7880 11:03:46.622574 Set Vref, RX VrefLevel [Byte0]: 40
7881 11:03:46.626033 [Byte1]: 40
7882 11:03:46.630501
7883 11:03:46.630565 Set Vref, RX VrefLevel [Byte0]: 41
7884 11:03:46.633413 [Byte1]: 41
7885 11:03:46.637831
7886 11:03:46.637891 Set Vref, RX VrefLevel [Byte0]: 42
7887 11:03:46.641012 [Byte1]: 42
7888 11:03:46.645911
7889 11:03:46.646330 Set Vref, RX VrefLevel [Byte0]: 43
7890 11:03:46.649376 [Byte1]: 43
7891 11:03:46.653988
7892 11:03:46.654487 Set Vref, RX VrefLevel [Byte0]: 44
7893 11:03:46.656819 [Byte1]: 44
7894 11:03:46.661025
7895 11:03:46.661498 Set Vref, RX VrefLevel [Byte0]: 45
7896 11:03:46.664550 [Byte1]: 45
7897 11:03:46.668714
7898 11:03:46.669258 Set Vref, RX VrefLevel [Byte0]: 46
7899 11:03:46.672185 [Byte1]: 46
7900 11:03:46.676162
7901 11:03:46.676617 Set Vref, RX VrefLevel [Byte0]: 47
7902 11:03:46.679603 [Byte1]: 47
7903 11:03:46.684079
7904 11:03:46.684663 Set Vref, RX VrefLevel [Byte0]: 48
7905 11:03:46.687286 [Byte1]: 48
7906 11:03:46.691249
7907 11:03:46.691734 Set Vref, RX VrefLevel [Byte0]: 49
7908 11:03:46.694813 [Byte1]: 49
7909 11:03:46.698972
7910 11:03:46.699413 Set Vref, RX VrefLevel [Byte0]: 50
7911 11:03:46.702230 [Byte1]: 50
7912 11:03:46.706387
7913 11:03:46.706815 Set Vref, RX VrefLevel [Byte0]: 51
7914 11:03:46.709744 [Byte1]: 51
7915 11:03:46.713923
7916 11:03:46.714355 Set Vref, RX VrefLevel [Byte0]: 52
7917 11:03:46.717703 [Byte1]: 52
7918 11:03:46.721876
7919 11:03:46.722296 Set Vref, RX VrefLevel [Byte0]: 53
7920 11:03:46.724728 [Byte1]: 53
7921 11:03:46.729192
7922 11:03:46.729635 Set Vref, RX VrefLevel [Byte0]: 54
7923 11:03:46.732213 [Byte1]: 54
7924 11:03:46.736633
7925 11:03:46.737055 Set Vref, RX VrefLevel [Byte0]: 55
7926 11:03:46.739878 [Byte1]: 55
7927 11:03:46.744340
7928 11:03:46.744760 Set Vref, RX VrefLevel [Byte0]: 56
7929 11:03:46.747589 [Byte1]: 56
7930 11:03:46.752106
7931 11:03:46.752523 Set Vref, RX VrefLevel [Byte0]: 57
7932 11:03:46.755104 [Byte1]: 57
7933 11:03:46.759514
7934 11:03:46.759932 Set Vref, RX VrefLevel [Byte0]: 58
7935 11:03:46.762888 [Byte1]: 58
7936 11:03:46.767012
7937 11:03:46.767430 Set Vref, RX VrefLevel [Byte0]: 59
7938 11:03:46.770191 [Byte1]: 59
7939 11:03:46.774616
7940 11:03:46.774995 Set Vref, RX VrefLevel [Byte0]: 60
7941 11:03:46.777922 [Byte1]: 60
7942 11:03:46.782154
7943 11:03:46.782535 Set Vref, RX VrefLevel [Byte0]: 61
7944 11:03:46.785499 [Byte1]: 61
7945 11:03:46.789621
7946 11:03:46.789997 Set Vref, RX VrefLevel [Byte0]: 62
7947 11:03:46.792896 [Byte1]: 62
7948 11:03:46.797258
7949 11:03:46.797637 Set Vref, RX VrefLevel [Byte0]: 63
7950 11:03:46.800433 [Byte1]: 63
7951 11:03:46.804907
7952 11:03:46.805460 Set Vref, RX VrefLevel [Byte0]: 64
7953 11:03:46.808139 [Byte1]: 64
7954 11:03:46.812373
7955 11:03:46.812759 Set Vref, RX VrefLevel [Byte0]: 65
7956 11:03:46.815705 [Byte1]: 65
7957 11:03:46.819923
7958 11:03:46.820273 Set Vref, RX VrefLevel [Byte0]: 66
7959 11:03:46.823220 [Byte1]: 66
7960 11:03:46.827793
7961 11:03:46.828178 Set Vref, RX VrefLevel [Byte0]: 67
7962 11:03:46.830999 [Byte1]: 67
7963 11:03:46.835275
7964 11:03:46.835674 Set Vref, RX VrefLevel [Byte0]: 68
7965 11:03:46.838275 [Byte1]: 68
7966 11:03:46.842518
7967 11:03:46.842879 Set Vref, RX VrefLevel [Byte0]: 69
7968 11:03:46.846011 [Byte1]: 69
7969 11:03:46.850020
7970 11:03:46.850404 Set Vref, RX VrefLevel [Byte0]: 70
7971 11:03:46.853513 [Byte1]: 70
7972 11:03:46.857722
7973 11:03:46.858095 Set Vref, RX VrefLevel [Byte0]: 71
7974 11:03:46.861314 [Byte1]: 71
7975 11:03:46.865580
7976 11:03:46.866020 Set Vref, RX VrefLevel [Byte0]: 72
7977 11:03:46.868827 [Byte1]: 72
7978 11:03:46.873091
7979 11:03:46.873501 Set Vref, RX VrefLevel [Byte0]: 73
7980 11:03:46.876502 [Byte1]: 73
7981 11:03:46.880500
7982 11:03:46.881003 Set Vref, RX VrefLevel [Byte0]: 74
7983 11:03:46.884033 [Byte1]: 74
7984 11:03:46.888141
7985 11:03:46.888555 Set Vref, RX VrefLevel [Byte0]: 75
7986 11:03:46.891381 [Byte1]: 75
7987 11:03:46.895887
7988 11:03:46.896328 Set Vref, RX VrefLevel [Byte0]: 76
7989 11:03:46.899048 [Byte1]: 76
7990 11:03:46.903272
7991 11:03:46.903837 Set Vref, RX VrefLevel [Byte0]: 77
7992 11:03:46.906767 [Byte1]: 77
7993 11:03:46.910945
7994 11:03:46.911421 Set Vref, RX VrefLevel [Byte0]: 78
7995 11:03:46.914259 [Byte1]: 78
7996 11:03:46.918407
7997 11:03:46.919187 Set Vref, RX VrefLevel [Byte0]: 79
7998 11:03:46.921446 [Byte1]: 79
7999 11:03:46.925737
8000 11:03:46.926011 Final RX Vref Byte 0 = 59 to rank0
8001 11:03:46.928873 Final RX Vref Byte 1 = 64 to rank0
8002 11:03:46.932537 Final RX Vref Byte 0 = 59 to rank1
8003 11:03:46.935835 Final RX Vref Byte 1 = 64 to rank1==
8004 11:03:46.939091 Dram Type= 6, Freq= 0, CH_0, rank 0
8005 11:03:46.945840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 11:03:46.946131 ==
8007 11:03:46.946349 DQS Delay:
8008 11:03:46.946546 DQS0 = 0, DQS1 = 0
8009 11:03:46.949031 DQM Delay:
8010 11:03:46.949368 DQM0 = 136, DQM1 = 124
8011 11:03:46.952598 DQ Delay:
8012 11:03:46.955818 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
8013 11:03:46.959378 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
8014 11:03:46.962658 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8015 11:03:46.965937 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
8016 11:03:46.966364
8017 11:03:46.966693
8018 11:03:46.966995
8019 11:03:46.969251 [DramC_TX_OE_Calibration] TA2
8020 11:03:46.972639 Original DQ_B0 (3 6) =30, OEN = 27
8021 11:03:46.975888 Original DQ_B1 (3 6) =30, OEN = 27
8022 11:03:46.979516 24, 0x0, End_B0=24 End_B1=24
8023 11:03:46.979950 25, 0x0, End_B0=25 End_B1=25
8024 11:03:46.982794 26, 0x0, End_B0=26 End_B1=26
8025 11:03:46.986012 27, 0x0, End_B0=27 End_B1=27
8026 11:03:46.989467 28, 0x0, End_B0=28 End_B1=28
8027 11:03:46.989901 29, 0x0, End_B0=29 End_B1=29
8028 11:03:46.992868 30, 0x0, End_B0=30 End_B1=30
8029 11:03:46.996146 31, 0x4141, End_B0=30 End_B1=30
8030 11:03:46.999764 Byte0 end_step=30 best_step=27
8031 11:03:47.002898 Byte1 end_step=30 best_step=27
8032 11:03:47.006160 Byte0 TX OE(2T, 0.5T) = (3, 3)
8033 11:03:47.006609 Byte1 TX OE(2T, 0.5T) = (3, 3)
8034 11:03:47.006972
8035 11:03:47.009330
8036 11:03:47.015867 [DQSOSCAuto] RK0, (LSB)MR18= 0x2220, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
8037 11:03:47.019202 CH0 RK0: MR19=303, MR18=2220
8038 11:03:47.025939 CH0_RK0: MR19=0x303, MR18=0x2220, DQSOSC=392, MR23=63, INC=24, DEC=16
8039 11:03:47.026488
8040 11:03:47.029191 ----->DramcWriteLeveling(PI) begin...
8041 11:03:47.029674 ==
8042 11:03:47.032400 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 11:03:47.035833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 11:03:47.036249 ==
8045 11:03:47.039453 Write leveling (Byte 0): 36 => 36
8046 11:03:47.042401 Write leveling (Byte 1): 28 => 28
8047 11:03:47.045583 DramcWriteLeveling(PI) end<-----
8048 11:03:47.045971
8049 11:03:47.046267 ==
8050 11:03:47.048940 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 11:03:47.052071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 11:03:47.052464 ==
8053 11:03:47.055526 [Gating] SW mode calibration
8054 11:03:47.062241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8055 11:03:47.069001 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8056 11:03:47.072140 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 11:03:47.075597 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 11:03:47.081962 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8059 11:03:47.085350 1 4 12 | B1->B0 | 2424 3131 | 1 0 | (1 1) (1 1)
8060 11:03:47.088820 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:03:47.095591 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:03:47.098985 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:03:47.102125 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 11:03:47.108519 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 11:03:47.112106 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8066 11:03:47.115651 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 11:03:47.121858 1 5 12 | B1->B0 | 3333 2929 | 1 0 | (1 0) (1 0)
8068 11:03:47.125276 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
8069 11:03:47.128764 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:03:47.135660 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:03:47.138846 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:03:47.142142 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:03:47.149018 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:03:47.152019 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8075 11:03:47.155236 1 6 12 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8076 11:03:47.162037 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8077 11:03:47.165469 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:03:47.168703 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:03:47.172008 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 11:03:47.178712 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 11:03:47.181961 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 11:03:47.185420 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 11:03:47.192208 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8084 11:03:47.195405 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8085 11:03:47.198471 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:03:47.205021 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:03:47.208470 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:03:47.211611 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:03:47.218277 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:03:47.221781 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:03:47.224983 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:03:47.231600 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:03:47.235180 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:03:47.238330 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:03:47.244749 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:03:47.248093 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:03:47.251663 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:03:47.258280 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8099 11:03:47.261402 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8100 11:03:47.265080 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8101 11:03:47.268202 Total UI for P1: 0, mck2ui 16
8102 11:03:47.271679 best dqsien dly found for B0: ( 1, 9, 10)
8103 11:03:47.278392 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 11:03:47.278858 Total UI for P1: 0, mck2ui 16
8105 11:03:47.284879 best dqsien dly found for B1: ( 1, 9, 14)
8106 11:03:47.288036 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8107 11:03:47.291345 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8108 11:03:47.291731
8109 11:03:47.294865 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8110 11:03:47.298382 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8111 11:03:47.301631 [Gating] SW calibration Done
8112 11:03:47.302015 ==
8113 11:03:47.304756 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 11:03:47.308014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 11:03:47.308400 ==
8116 11:03:47.311341 RX Vref Scan: 0
8117 11:03:47.311721
8118 11:03:47.312014 RX Vref 0 -> 0, step: 1
8119 11:03:47.312289
8120 11:03:47.314630 RX Delay 0 -> 252, step: 8
8121 11:03:47.317771 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8122 11:03:47.324926 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8123 11:03:47.327981 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8124 11:03:47.331594 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8125 11:03:47.335174 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8126 11:03:47.338014 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8127 11:03:47.344909 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8128 11:03:47.348244 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8129 11:03:47.351558 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8130 11:03:47.354924 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8131 11:03:47.357995 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8132 11:03:47.361323 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8133 11:03:47.368024 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8134 11:03:47.371263 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8135 11:03:47.374854 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8136 11:03:47.377912 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8137 11:03:47.378352 ==
8138 11:03:47.381528 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 11:03:47.388026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 11:03:47.388478 ==
8141 11:03:47.388809 DQS Delay:
8142 11:03:47.391176 DQS0 = 0, DQS1 = 0
8143 11:03:47.391606 DQM Delay:
8144 11:03:47.391958 DQM0 = 136, DQM1 = 126
8145 11:03:47.394697 DQ Delay:
8146 11:03:47.398304 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8147 11:03:47.401495 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8148 11:03:47.405019 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8149 11:03:47.407961 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8150 11:03:47.408354
8151 11:03:47.408686
8152 11:03:47.408957 ==
8153 11:03:47.411605 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 11:03:47.414737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 11:03:47.418052 ==
8156 11:03:47.418438
8157 11:03:47.418737
8158 11:03:47.419014 TX Vref Scan disable
8159 11:03:47.421238 == TX Byte 0 ==
8160 11:03:47.425055 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8161 11:03:47.428076 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8162 11:03:47.431535 == TX Byte 1 ==
8163 11:03:47.434906 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8164 11:03:47.438005 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8165 11:03:47.441370 ==
8166 11:03:47.441780 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 11:03:47.447935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 11:03:47.448342 ==
8169 11:03:47.460910
8170 11:03:47.464199 TX Vref early break, caculate TX vref
8171 11:03:47.467489 TX Vref=16, minBit 8, minWin=23, winSum=389
8172 11:03:47.470934 TX Vref=18, minBit 0, minWin=24, winSum=399
8173 11:03:47.474093 TX Vref=20, minBit 8, minWin=24, winSum=405
8174 11:03:47.477280 TX Vref=22, minBit 0, minWin=25, winSum=415
8175 11:03:47.480747 TX Vref=24, minBit 7, minWin=25, winSum=419
8176 11:03:47.487564 TX Vref=26, minBit 0, minWin=26, winSum=429
8177 11:03:47.490840 TX Vref=28, minBit 2, minWin=25, winSum=425
8178 11:03:47.494099 TX Vref=30, minBit 0, minWin=25, winSum=421
8179 11:03:47.497553 TX Vref=32, minBit 0, minWin=25, winSum=412
8180 11:03:47.500572 TX Vref=34, minBit 1, minWin=24, winSum=401
8181 11:03:47.507324 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8182 11:03:47.507757
8183 11:03:47.510762 Final TX Range 0 Vref 26
8184 11:03:47.511165
8185 11:03:47.511497 ==
8186 11:03:47.514340 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 11:03:47.517541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 11:03:47.517928 ==
8189 11:03:47.518226
8190 11:03:47.518549
8191 11:03:47.520742 TX Vref Scan disable
8192 11:03:47.527571 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8193 11:03:47.527996 == TX Byte 0 ==
8194 11:03:47.530882 u2DelayCellOfst[0]=13 cells (4 PI)
8195 11:03:47.534201 u2DelayCellOfst[1]=20 cells (6 PI)
8196 11:03:47.537451 u2DelayCellOfst[2]=13 cells (4 PI)
8197 11:03:47.540490 u2DelayCellOfst[3]=13 cells (4 PI)
8198 11:03:47.544132 u2DelayCellOfst[4]=10 cells (3 PI)
8199 11:03:47.547396 u2DelayCellOfst[5]=0 cells (0 PI)
8200 11:03:47.550597 u2DelayCellOfst[6]=20 cells (6 PI)
8201 11:03:47.553907 u2DelayCellOfst[7]=20 cells (6 PI)
8202 11:03:47.557199 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8203 11:03:47.560366 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8204 11:03:47.563754 == TX Byte 1 ==
8205 11:03:47.564210 u2DelayCellOfst[8]=0 cells (0 PI)
8206 11:03:47.567311 u2DelayCellOfst[9]=0 cells (0 PI)
8207 11:03:47.570550 u2DelayCellOfst[10]=6 cells (2 PI)
8208 11:03:47.573917 u2DelayCellOfst[11]=3 cells (1 PI)
8209 11:03:47.576984 u2DelayCellOfst[12]=13 cells (4 PI)
8210 11:03:47.580317 u2DelayCellOfst[13]=13 cells (4 PI)
8211 11:03:47.584077 u2DelayCellOfst[14]=13 cells (4 PI)
8212 11:03:47.587263 u2DelayCellOfst[15]=10 cells (3 PI)
8213 11:03:47.590671 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8214 11:03:47.597392 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8215 11:03:47.597781 DramC Write-DBI on
8216 11:03:47.598069 ==
8217 11:03:47.600454 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 11:03:47.603978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 11:03:47.606863 ==
8220 11:03:47.607227
8221 11:03:47.607515
8222 11:03:47.607801 TX Vref Scan disable
8223 11:03:47.610468 == TX Byte 0 ==
8224 11:03:47.613814 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8225 11:03:47.616906 == TX Byte 1 ==
8226 11:03:47.620481 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8227 11:03:47.623526 DramC Write-DBI off
8228 11:03:47.623866
8229 11:03:47.624146 [DATLAT]
8230 11:03:47.624409 Freq=1600, CH0 RK1
8231 11:03:47.624687
8232 11:03:47.627210 DATLAT Default: 0xf
8233 11:03:47.627541 0, 0xFFFF, sum = 0
8234 11:03:47.630162 1, 0xFFFF, sum = 0
8235 11:03:47.633525 2, 0xFFFF, sum = 0
8236 11:03:47.633850 3, 0xFFFF, sum = 0
8237 11:03:47.637116 4, 0xFFFF, sum = 0
8238 11:03:47.637455 5, 0xFFFF, sum = 0
8239 11:03:47.640351 6, 0xFFFF, sum = 0
8240 11:03:47.640684 7, 0xFFFF, sum = 0
8241 11:03:47.643643 8, 0xFFFF, sum = 0
8242 11:03:47.643987 9, 0xFFFF, sum = 0
8243 11:03:47.646926 10, 0xFFFF, sum = 0
8244 11:03:47.647313 11, 0xFFFF, sum = 0
8245 11:03:47.650046 12, 0xFFFF, sum = 0
8246 11:03:47.650432 13, 0xFFFF, sum = 0
8247 11:03:47.653243 14, 0x0, sum = 1
8248 11:03:47.653631 15, 0x0, sum = 2
8249 11:03:47.656995 16, 0x0, sum = 3
8250 11:03:47.657453 17, 0x0, sum = 4
8251 11:03:47.660242 best_step = 15
8252 11:03:47.660619
8253 11:03:47.660909 ==
8254 11:03:47.663503 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 11:03:47.666885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 11:03:47.667240 ==
8257 11:03:47.669926 RX Vref Scan: 0
8258 11:03:47.670263
8259 11:03:47.670567 RX Vref 0 -> 0, step: 1
8260 11:03:47.670831
8261 11:03:47.673543 RX Delay 19 -> 252, step: 4
8262 11:03:47.676810 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8263 11:03:47.683370 iDelay=191, Bit 1, Center 134 (87 ~ 182) 96
8264 11:03:47.686513 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8265 11:03:47.690018 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8266 11:03:47.693529 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8267 11:03:47.696413 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8268 11:03:47.703360 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8269 11:03:47.706383 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8270 11:03:47.709981 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8271 11:03:47.713123 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8272 11:03:47.716392 iDelay=191, Bit 10, Center 122 (75 ~ 170) 96
8273 11:03:47.723297 iDelay=191, Bit 11, Center 118 (71 ~ 166) 96
8274 11:03:47.726560 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8275 11:03:47.729801 iDelay=191, Bit 13, Center 126 (75 ~ 178) 104
8276 11:03:47.733369 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8277 11:03:47.736461 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8278 11:03:47.739601 ==
8279 11:03:47.742968 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 11:03:47.746732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 11:03:47.747160 ==
8282 11:03:47.747486 DQS Delay:
8283 11:03:47.749628 DQS0 = 0, DQS1 = 0
8284 11:03:47.750051 DQM Delay:
8285 11:03:47.752967 DQM0 = 132, DQM1 = 122
8286 11:03:47.753437 DQ Delay:
8287 11:03:47.756444 DQ0 =132, DQ1 =134, DQ2 =128, DQ3 =130
8288 11:03:47.760110 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8289 11:03:47.763149 DQ8 =116, DQ9 =110, DQ10 =122, DQ11 =118
8290 11:03:47.766422 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =128
8291 11:03:47.766968
8292 11:03:47.767482
8293 11:03:47.768005
8294 11:03:47.769721 [DramC_TX_OE_Calibration] TA2
8295 11:03:47.772842 Original DQ_B0 (3 6) =30, OEN = 27
8296 11:03:47.776313 Original DQ_B1 (3 6) =30, OEN = 27
8297 11:03:47.779506 24, 0x0, End_B0=24 End_B1=24
8298 11:03:47.782818 25, 0x0, End_B0=25 End_B1=25
8299 11:03:47.783250 26, 0x0, End_B0=26 End_B1=26
8300 11:03:47.786729 27, 0x0, End_B0=27 End_B1=27
8301 11:03:47.790000 28, 0x0, End_B0=28 End_B1=28
8302 11:03:47.792851 29, 0x0, End_B0=29 End_B1=29
8303 11:03:47.793419 30, 0x0, End_B0=30 End_B1=30
8304 11:03:47.796026 31, 0x4141, End_B0=30 End_B1=30
8305 11:03:47.799861 Byte0 end_step=30 best_step=27
8306 11:03:47.803194 Byte1 end_step=30 best_step=27
8307 11:03:47.806205 Byte0 TX OE(2T, 0.5T) = (3, 3)
8308 11:03:47.809834 Byte1 TX OE(2T, 0.5T) = (3, 3)
8309 11:03:47.810359
8310 11:03:47.810800
8311 11:03:47.816581 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8312 11:03:47.819628 CH0 RK1: MR19=303, MR18=220F
8313 11:03:47.826020 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8314 11:03:47.829633 [RxdqsGatingPostProcess] freq 1600
8315 11:03:47.832972 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8316 11:03:47.836542 best DQS0 dly(2T, 0.5T) = (1, 1)
8317 11:03:47.839792 best DQS1 dly(2T, 0.5T) = (1, 1)
8318 11:03:47.843035 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8319 11:03:47.846243 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8320 11:03:47.849430 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 11:03:47.853423 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 11:03:47.856362 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 11:03:47.859965 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 11:03:47.862917 Pre-setting of DQS Precalculation
8325 11:03:47.866031 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8326 11:03:47.866473 ==
8327 11:03:47.869784 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 11:03:47.872915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 11:03:47.876117 ==
8330 11:03:47.879463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 11:03:47.883013 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 11:03:47.889837 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 11:03:47.895745 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 11:03:47.903082 [CA 0] Center 42 (12~72) winsize 61
8335 11:03:47.906334 [CA 1] Center 41 (11~72) winsize 62
8336 11:03:47.909730 [CA 2] Center 38 (9~67) winsize 59
8337 11:03:47.913173 [CA 3] Center 37 (8~67) winsize 60
8338 11:03:47.916668 [CA 4] Center 37 (7~67) winsize 61
8339 11:03:47.919807 [CA 5] Center 37 (7~67) winsize 61
8340 11:03:47.920272
8341 11:03:47.923191 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8342 11:03:47.923643
8343 11:03:47.926397 [CATrainingPosCal] consider 1 rank data
8344 11:03:47.929772 u2DelayCellTimex100 = 290/100 ps
8345 11:03:47.932988 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8346 11:03:47.939933 CA1 delay=41 (11~72),Diff = 4 PI (13 cell)
8347 11:03:47.942944 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8348 11:03:47.946331 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8349 11:03:47.950055 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
8350 11:03:47.952800 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8351 11:03:47.953399
8352 11:03:47.956305 CA PerBit enable=1, Macro0, CA PI delay=37
8353 11:03:47.956706
8354 11:03:47.959557 [CBTSetCACLKResult] CA Dly = 37
8355 11:03:47.960080 CS Dly: 9 (0~40)
8356 11:03:47.966287 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 11:03:47.969446 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 11:03:47.969989 ==
8359 11:03:47.973170 Dram Type= 6, Freq= 0, CH_1, rank 1
8360 11:03:47.976037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 11:03:47.976466 ==
8362 11:03:47.982808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8363 11:03:47.986406 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8364 11:03:47.993049 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8365 11:03:47.996305 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8366 11:03:48.006080 [CA 0] Center 42 (13~72) winsize 60
8367 11:03:48.009872 [CA 1] Center 42 (13~72) winsize 60
8368 11:03:48.012950 [CA 2] Center 38 (9~68) winsize 60
8369 11:03:48.016407 [CA 3] Center 37 (8~67) winsize 60
8370 11:03:48.018999 [CA 4] Center 38 (9~68) winsize 60
8371 11:03:48.022372 [CA 5] Center 37 (8~67) winsize 60
8372 11:03:48.022447
8373 11:03:48.025896 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8374 11:03:48.026001
8375 11:03:48.029331 [CATrainingPosCal] consider 2 rank data
8376 11:03:48.032439 u2DelayCellTimex100 = 290/100 ps
8377 11:03:48.035666 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8378 11:03:48.042563 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8379 11:03:48.045704 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8380 11:03:48.049491 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8381 11:03:48.052269 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8382 11:03:48.055899 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8383 11:03:48.055992
8384 11:03:48.059056 CA PerBit enable=1, Macro0, CA PI delay=37
8385 11:03:48.059150
8386 11:03:48.062584 [CBTSetCACLKResult] CA Dly = 37
8387 11:03:48.065539 CS Dly: 10 (0~42)
8388 11:03:48.069184 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8389 11:03:48.072390 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8390 11:03:48.072513
8391 11:03:48.075634 ----->DramcWriteLeveling(PI) begin...
8392 11:03:48.075775 ==
8393 11:03:48.079244 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 11:03:48.082464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 11:03:48.085721 ==
8396 11:03:48.085906 Write leveling (Byte 0): 24 => 24
8397 11:03:48.089087 Write leveling (Byte 1): 30 => 30
8398 11:03:48.092345 DramcWriteLeveling(PI) end<-----
8399 11:03:48.092419
8400 11:03:48.092476 ==
8401 11:03:48.095357 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 11:03:48.102371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 11:03:48.102446 ==
8404 11:03:48.105687 [Gating] SW mode calibration
8405 11:03:48.112223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8406 11:03:48.115664 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8407 11:03:48.119144 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 11:03:48.125414 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 11:03:48.128998 1 4 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8410 11:03:48.132284 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 11:03:48.139268 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 11:03:48.142595 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 11:03:48.146025 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 11:03:48.152582 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 11:03:48.156084 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 11:03:48.159097 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8417 11:03:48.165909 1 5 8 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 1)
8418 11:03:48.169419 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8419 11:03:48.172515 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:03:48.179224 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:03:48.182413 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:03:48.185848 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 11:03:48.192608 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 11:03:48.195547 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 11:03:48.198981 1 6 8 | B1->B0 | 3736 4545 | 1 0 | (0 0) (0 0)
8426 11:03:48.205580 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 11:03:48.209255 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 11:03:48.212566 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 11:03:48.219172 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:03:48.222360 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:03:48.225361 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 11:03:48.232128 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8433 11:03:48.235573 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8434 11:03:48.238980 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8435 11:03:48.242491 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:03:48.249195 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:03:48.252429 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:03:48.255705 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:03:48.262173 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:03:48.265984 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:03:48.268740 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:03:48.275497 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:03:48.278998 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:03:48.282461 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:03:48.289042 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:03:48.292274 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:03:48.295970 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:03:48.302091 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8449 11:03:48.305955 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8450 11:03:48.309097 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 11:03:48.312390 Total UI for P1: 0, mck2ui 16
8452 11:03:48.315650 best dqsien dly found for B0: ( 1, 9, 6)
8453 11:03:48.318822 Total UI for P1: 0, mck2ui 16
8454 11:03:48.322430 best dqsien dly found for B1: ( 1, 9, 10)
8455 11:03:48.325478 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8456 11:03:48.328996 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8457 11:03:48.329461
8458 11:03:48.332195 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8459 11:03:48.339319 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8460 11:03:48.339838 [Gating] SW calibration Done
8461 11:03:48.340176 ==
8462 11:03:48.342376 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 11:03:48.349179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 11:03:48.349670 ==
8465 11:03:48.350004 RX Vref Scan: 0
8466 11:03:48.350309
8467 11:03:48.352398 RX Vref 0 -> 0, step: 1
8468 11:03:48.352817
8469 11:03:48.355736 RX Delay 0 -> 252, step: 8
8470 11:03:48.359119 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8471 11:03:48.362327 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8472 11:03:48.365668 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8473 11:03:48.368791 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8474 11:03:48.375747 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8475 11:03:48.378950 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8476 11:03:48.382325 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8477 11:03:48.385741 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8478 11:03:48.389120 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8479 11:03:48.395552 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8480 11:03:48.398922 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8481 11:03:48.402206 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8482 11:03:48.405601 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8483 11:03:48.408786 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8484 11:03:48.415313 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8485 11:03:48.419038 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8486 11:03:48.419476 ==
8487 11:03:48.422259 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 11:03:48.425408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 11:03:48.425838 ==
8490 11:03:48.428909 DQS Delay:
8491 11:03:48.429441 DQS0 = 0, DQS1 = 0
8492 11:03:48.429782 DQM Delay:
8493 11:03:48.432116 DQM0 = 139, DQM1 = 130
8494 11:03:48.432538 DQ Delay:
8495 11:03:48.435292 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8496 11:03:48.438555 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8497 11:03:48.442309 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8498 11:03:48.448885 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8499 11:03:48.449363
8500 11:03:48.449698
8501 11:03:48.450002 ==
8502 11:03:48.451964 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 11:03:48.455292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 11:03:48.455682 ==
8505 11:03:48.455979
8506 11:03:48.456250
8507 11:03:48.458702 TX Vref Scan disable
8508 11:03:48.459087 == TX Byte 0 ==
8509 11:03:48.465177 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8510 11:03:48.468681 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8511 11:03:48.469241 == TX Byte 1 ==
8512 11:03:48.475345 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8513 11:03:48.478583 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8514 11:03:48.478988 ==
8515 11:03:48.481907 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 11:03:48.485719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 11:03:48.486106 ==
8518 11:03:48.498944
8519 11:03:48.502552 TX Vref early break, caculate TX vref
8520 11:03:48.505579 TX Vref=16, minBit 15, minWin=20, winSum=366
8521 11:03:48.508921 TX Vref=18, minBit 15, minWin=21, winSum=381
8522 11:03:48.512478 TX Vref=20, minBit 15, minWin=21, winSum=386
8523 11:03:48.515590 TX Vref=22, minBit 9, minWin=23, winSum=401
8524 11:03:48.519238 TX Vref=24, minBit 15, minWin=23, winSum=412
8525 11:03:48.525582 TX Vref=26, minBit 9, minWin=25, winSum=416
8526 11:03:48.528825 TX Vref=28, minBit 10, minWin=24, winSum=417
8527 11:03:48.532151 TX Vref=30, minBit 10, minWin=23, winSum=404
8528 11:03:48.535481 TX Vref=32, minBit 10, minWin=23, winSum=398
8529 11:03:48.539130 TX Vref=34, minBit 10, minWin=22, winSum=384
8530 11:03:48.545583 [TxChooseVref] Worse bit 9, Min win 25, Win sum 416, Final Vref 26
8531 11:03:48.546012
8532 11:03:48.548772 Final TX Range 0 Vref 26
8533 11:03:48.549268
8534 11:03:48.549572 ==
8535 11:03:48.551935 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 11:03:48.555307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 11:03:48.555693 ==
8538 11:03:48.555989
8539 11:03:48.558449
8540 11:03:48.558830 TX Vref Scan disable
8541 11:03:48.565513 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8542 11:03:48.565920 == TX Byte 0 ==
8543 11:03:48.569069 u2DelayCellOfst[0]=16 cells (5 PI)
8544 11:03:48.572118 u2DelayCellOfst[1]=10 cells (3 PI)
8545 11:03:48.575277 u2DelayCellOfst[2]=0 cells (0 PI)
8546 11:03:48.579021 u2DelayCellOfst[3]=3 cells (1 PI)
8547 11:03:48.582294 u2DelayCellOfst[4]=6 cells (2 PI)
8548 11:03:48.585584 u2DelayCellOfst[5]=16 cells (5 PI)
8549 11:03:48.588820 u2DelayCellOfst[6]=16 cells (5 PI)
8550 11:03:48.591970 u2DelayCellOfst[7]=3 cells (1 PI)
8551 11:03:48.595718 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8552 11:03:48.598441 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8553 11:03:48.602011 == TX Byte 1 ==
8554 11:03:48.605205 u2DelayCellOfst[8]=0 cells (0 PI)
8555 11:03:48.605595 u2DelayCellOfst[9]=3 cells (1 PI)
8556 11:03:48.608690 u2DelayCellOfst[10]=13 cells (4 PI)
8557 11:03:48.611986 u2DelayCellOfst[11]=3 cells (1 PI)
8558 11:03:48.615043 u2DelayCellOfst[12]=16 cells (5 PI)
8559 11:03:48.618659 u2DelayCellOfst[13]=16 cells (5 PI)
8560 11:03:48.622006 u2DelayCellOfst[14]=16 cells (5 PI)
8561 11:03:48.625015 u2DelayCellOfst[15]=16 cells (5 PI)
8562 11:03:48.631801 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8563 11:03:48.635014 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8564 11:03:48.635399 DramC Write-DBI on
8565 11:03:48.635695 ==
8566 11:03:48.638074 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 11:03:48.644531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 11:03:48.644607 ==
8569 11:03:48.644665
8570 11:03:48.644719
8571 11:03:48.644770 TX Vref Scan disable
8572 11:03:48.648678 == TX Byte 0 ==
8573 11:03:48.652055 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8574 11:03:48.655270 == TX Byte 1 ==
8575 11:03:48.658569 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8576 11:03:48.661904 DramC Write-DBI off
8577 11:03:48.661981
8578 11:03:48.662039 [DATLAT]
8579 11:03:48.662093 Freq=1600, CH1 RK0
8580 11:03:48.662144
8581 11:03:48.665162 DATLAT Default: 0xf
8582 11:03:48.665274 0, 0xFFFF, sum = 0
8583 11:03:48.668662 1, 0xFFFF, sum = 0
8584 11:03:48.671661 2, 0xFFFF, sum = 0
8585 11:03:48.671738 3, 0xFFFF, sum = 0
8586 11:03:48.675000 4, 0xFFFF, sum = 0
8587 11:03:48.675076 5, 0xFFFF, sum = 0
8588 11:03:48.678404 6, 0xFFFF, sum = 0
8589 11:03:48.678480 7, 0xFFFF, sum = 0
8590 11:03:48.681924 8, 0xFFFF, sum = 0
8591 11:03:48.682000 9, 0xFFFF, sum = 0
8592 11:03:48.685249 10, 0xFFFF, sum = 0
8593 11:03:48.685325 11, 0xFFFF, sum = 0
8594 11:03:48.688426 12, 0xFFFF, sum = 0
8595 11:03:48.688503 13, 0xFFFF, sum = 0
8596 11:03:48.691760 14, 0x0, sum = 1
8597 11:03:48.691836 15, 0x0, sum = 2
8598 11:03:48.695015 16, 0x0, sum = 3
8599 11:03:48.695091 17, 0x0, sum = 4
8600 11:03:48.698396 best_step = 15
8601 11:03:48.698471
8602 11:03:48.698528 ==
8603 11:03:48.701647 Dram Type= 6, Freq= 0, CH_1, rank 0
8604 11:03:48.704871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8605 11:03:48.704947 ==
8606 11:03:48.708389 RX Vref Scan: 1
8607 11:03:48.708464
8608 11:03:48.708524 Set Vref Range= 24 -> 127
8609 11:03:48.708578
8610 11:03:48.712067 RX Vref 24 -> 127, step: 1
8611 11:03:48.712142
8612 11:03:48.714860 RX Delay 19 -> 252, step: 4
8613 11:03:48.714935
8614 11:03:48.718360 Set Vref, RX VrefLevel [Byte0]: 24
8615 11:03:48.721597 [Byte1]: 24
8616 11:03:48.721672
8617 11:03:48.725297 Set Vref, RX VrefLevel [Byte0]: 25
8618 11:03:48.728283 [Byte1]: 25
8619 11:03:48.728358
8620 11:03:48.731639 Set Vref, RX VrefLevel [Byte0]: 26
8621 11:03:48.735250 [Byte1]: 26
8622 11:03:48.738724
8623 11:03:48.738799 Set Vref, RX VrefLevel [Byte0]: 27
8624 11:03:48.742098 [Byte1]: 27
8625 11:03:48.746378
8626 11:03:48.746453 Set Vref, RX VrefLevel [Byte0]: 28
8627 11:03:48.749553 [Byte1]: 28
8628 11:03:48.753848
8629 11:03:48.753923 Set Vref, RX VrefLevel [Byte0]: 29
8630 11:03:48.757466 [Byte1]: 29
8631 11:03:48.761706
8632 11:03:48.761780 Set Vref, RX VrefLevel [Byte0]: 30
8633 11:03:48.764923 [Byte1]: 30
8634 11:03:48.769073
8635 11:03:48.769192 Set Vref, RX VrefLevel [Byte0]: 31
8636 11:03:48.772660 [Byte1]: 31
8637 11:03:48.776566
8638 11:03:48.776640 Set Vref, RX VrefLevel [Byte0]: 32
8639 11:03:48.779995 [Byte1]: 32
8640 11:03:48.784360
8641 11:03:48.784434 Set Vref, RX VrefLevel [Byte0]: 33
8642 11:03:48.787859 [Byte1]: 33
8643 11:03:48.791944
8644 11:03:48.792023 Set Vref, RX VrefLevel [Byte0]: 34
8645 11:03:48.795185 [Byte1]: 34
8646 11:03:48.799400
8647 11:03:48.799475 Set Vref, RX VrefLevel [Byte0]: 35
8648 11:03:48.802634 [Byte1]: 35
8649 11:03:48.806868
8650 11:03:48.806943 Set Vref, RX VrefLevel [Byte0]: 36
8651 11:03:48.810570 [Byte1]: 36
8652 11:03:48.814776
8653 11:03:48.814851 Set Vref, RX VrefLevel [Byte0]: 37
8654 11:03:48.818006 [Byte1]: 37
8655 11:03:48.822387
8656 11:03:48.822462 Set Vref, RX VrefLevel [Byte0]: 38
8657 11:03:48.825463 [Byte1]: 38
8658 11:03:48.829335
8659 11:03:48.832802 Set Vref, RX VrefLevel [Byte0]: 39
8660 11:03:48.835954 [Byte1]: 39
8661 11:03:48.836029
8662 11:03:48.839612 Set Vref, RX VrefLevel [Byte0]: 40
8663 11:03:48.842742 [Byte1]: 40
8664 11:03:48.842817
8665 11:03:48.846211 Set Vref, RX VrefLevel [Byte0]: 41
8666 11:03:48.849348 [Byte1]: 41
8667 11:03:48.849423
8668 11:03:48.852845 Set Vref, RX VrefLevel [Byte0]: 42
8669 11:03:48.855810 [Byte1]: 42
8670 11:03:48.859870
8671 11:03:48.859945 Set Vref, RX VrefLevel [Byte0]: 43
8672 11:03:48.863338 [Byte1]: 43
8673 11:03:48.867363
8674 11:03:48.867437 Set Vref, RX VrefLevel [Byte0]: 44
8675 11:03:48.870702 [Byte1]: 44
8676 11:03:48.875309
8677 11:03:48.875384 Set Vref, RX VrefLevel [Byte0]: 45
8678 11:03:48.878604 [Byte1]: 45
8679 11:03:48.882828
8680 11:03:48.882903 Set Vref, RX VrefLevel [Byte0]: 46
8681 11:03:48.885986 [Byte1]: 46
8682 11:03:48.890353
8683 11:03:48.890428 Set Vref, RX VrefLevel [Byte0]: 47
8684 11:03:48.893733 [Byte1]: 47
8685 11:03:48.897898
8686 11:03:48.897973 Set Vref, RX VrefLevel [Byte0]: 48
8687 11:03:48.901106 [Byte1]: 48
8688 11:03:48.905321
8689 11:03:48.905396 Set Vref, RX VrefLevel [Byte0]: 49
8690 11:03:48.908489 [Byte1]: 49
8691 11:03:48.913116
8692 11:03:48.913225 Set Vref, RX VrefLevel [Byte0]: 50
8693 11:03:48.916380 [Byte1]: 50
8694 11:03:48.920705
8695 11:03:48.920807 Set Vref, RX VrefLevel [Byte0]: 51
8696 11:03:48.923923 [Byte1]: 51
8697 11:03:48.928067
8698 11:03:48.928142 Set Vref, RX VrefLevel [Byte0]: 52
8699 11:03:48.931419 [Byte1]: 52
8700 11:03:48.935866
8701 11:03:48.935941 Set Vref, RX VrefLevel [Byte0]: 53
8702 11:03:48.939212 [Byte1]: 53
8703 11:03:48.943232
8704 11:03:48.943307 Set Vref, RX VrefLevel [Byte0]: 54
8705 11:03:48.946481 [Byte1]: 54
8706 11:03:48.950894
8707 11:03:48.951022 Set Vref, RX VrefLevel [Byte0]: 55
8708 11:03:48.954379 [Byte1]: 55
8709 11:03:48.958431
8710 11:03:48.958501 Set Vref, RX VrefLevel [Byte0]: 56
8711 11:03:48.961697 [Byte1]: 56
8712 11:03:48.965821
8713 11:03:48.965895 Set Vref, RX VrefLevel [Byte0]: 57
8714 11:03:48.969069 [Byte1]: 57
8715 11:03:48.973552
8716 11:03:48.973627 Set Vref, RX VrefLevel [Byte0]: 58
8717 11:03:48.976708 [Byte1]: 58
8718 11:03:48.981036
8719 11:03:48.981113 Set Vref, RX VrefLevel [Byte0]: 59
8720 11:03:48.984393 [Byte1]: 59
8721 11:03:48.988816
8722 11:03:48.988891 Set Vref, RX VrefLevel [Byte0]: 60
8723 11:03:48.992125 [Byte1]: 60
8724 11:03:48.996429
8725 11:03:48.996503 Set Vref, RX VrefLevel [Byte0]: 61
8726 11:03:48.999544 [Byte1]: 61
8727 11:03:49.003824
8728 11:03:49.003899 Set Vref, RX VrefLevel [Byte0]: 62
8729 11:03:49.007163 [Byte1]: 62
8730 11:03:49.011374
8731 11:03:49.011451 Set Vref, RX VrefLevel [Byte0]: 63
8732 11:03:49.014699 [Byte1]: 63
8733 11:03:49.018918
8734 11:03:49.018996 Set Vref, RX VrefLevel [Byte0]: 64
8735 11:03:49.022193 [Byte1]: 64
8736 11:03:49.026853
8737 11:03:49.026929 Set Vref, RX VrefLevel [Byte0]: 65
8738 11:03:49.030131 [Byte1]: 65
8739 11:03:49.034086
8740 11:03:49.034162 Set Vref, RX VrefLevel [Byte0]: 66
8741 11:03:49.037265 [Byte1]: 66
8742 11:03:49.041710
8743 11:03:49.041788 Set Vref, RX VrefLevel [Byte0]: 67
8744 11:03:49.045113 [Byte1]: 67
8745 11:03:49.049439
8746 11:03:49.049509 Set Vref, RX VrefLevel [Byte0]: 68
8747 11:03:49.052554 [Byte1]: 68
8748 11:03:49.056965
8749 11:03:49.057064 Set Vref, RX VrefLevel [Byte0]: 69
8750 11:03:49.059902 [Byte1]: 69
8751 11:03:49.064291
8752 11:03:49.064362 Set Vref, RX VrefLevel [Byte0]: 70
8753 11:03:49.067686 [Byte1]: 70
8754 11:03:49.072075
8755 11:03:49.072147 Set Vref, RX VrefLevel [Byte0]: 71
8756 11:03:49.075068 [Byte1]: 71
8757 11:03:49.079496
8758 11:03:49.079590 Set Vref, RX VrefLevel [Byte0]: 72
8759 11:03:49.082961 [Byte1]: 72
8760 11:03:49.087249
8761 11:03:49.087313 Set Vref, RX VrefLevel [Byte0]: 73
8762 11:03:49.090450 [Byte1]: 73
8763 11:03:49.094617
8764 11:03:49.094676 Set Vref, RX VrefLevel [Byte0]: 74
8765 11:03:49.098094 [Byte1]: 74
8766 11:03:49.102407
8767 11:03:49.102475 Set Vref, RX VrefLevel [Byte0]: 75
8768 11:03:49.105709 [Byte1]: 75
8769 11:03:49.110057
8770 11:03:49.110153 Set Vref, RX VrefLevel [Byte0]: 76
8771 11:03:49.113354 [Byte1]: 76
8772 11:03:49.117417
8773 11:03:49.117487 Final RX Vref Byte 0 = 58 to rank0
8774 11:03:49.121025 Final RX Vref Byte 1 = 64 to rank0
8775 11:03:49.124350 Final RX Vref Byte 0 = 58 to rank1
8776 11:03:49.127498 Final RX Vref Byte 1 = 64 to rank1==
8777 11:03:49.130839 Dram Type= 6, Freq= 0, CH_1, rank 0
8778 11:03:49.137313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 11:03:49.137422 ==
8780 11:03:49.137481 DQS Delay:
8781 11:03:49.137535 DQS0 = 0, DQS1 = 0
8782 11:03:49.140660 DQM Delay:
8783 11:03:49.140735 DQM0 = 135, DQM1 = 128
8784 11:03:49.144086 DQ Delay:
8785 11:03:49.147386 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8786 11:03:49.150770 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
8787 11:03:49.153816 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8788 11:03:49.157032 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8789 11:03:49.157153
8790 11:03:49.157227
8791 11:03:49.157280
8792 11:03:49.160373 [DramC_TX_OE_Calibration] TA2
8793 11:03:49.164083 Original DQ_B0 (3 6) =30, OEN = 27
8794 11:03:49.167385 Original DQ_B1 (3 6) =30, OEN = 27
8795 11:03:49.170999 24, 0x0, End_B0=24 End_B1=24
8796 11:03:49.171076 25, 0x0, End_B0=25 End_B1=25
8797 11:03:49.174077 26, 0x0, End_B0=26 End_B1=26
8798 11:03:49.177408 27, 0x0, End_B0=27 End_B1=27
8799 11:03:49.180702 28, 0x0, End_B0=28 End_B1=28
8800 11:03:49.183825 29, 0x0, End_B0=29 End_B1=29
8801 11:03:49.183902 30, 0x0, End_B0=30 End_B1=30
8802 11:03:49.187217 31, 0x4141, End_B0=30 End_B1=30
8803 11:03:49.190680 Byte0 end_step=30 best_step=27
8804 11:03:49.193882 Byte1 end_step=30 best_step=27
8805 11:03:49.197376 Byte0 TX OE(2T, 0.5T) = (3, 3)
8806 11:03:49.200624 Byte1 TX OE(2T, 0.5T) = (3, 3)
8807 11:03:49.200726
8808 11:03:49.200833
8809 11:03:49.207134 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b29, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8810 11:03:49.210298 CH1 RK0: MR19=303, MR18=1B29
8811 11:03:49.216857 CH1_RK0: MR19=0x303, MR18=0x1B29, DQSOSC=389, MR23=63, INC=24, DEC=16
8812 11:03:49.216933
8813 11:03:49.220259 ----->DramcWriteLeveling(PI) begin...
8814 11:03:49.220336 ==
8815 11:03:49.223686 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 11:03:49.226967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 11:03:49.227043 ==
8818 11:03:49.230167 Write leveling (Byte 0): 24 => 24
8819 11:03:49.234011 Write leveling (Byte 1): 31 => 31
8820 11:03:49.237292 DramcWriteLeveling(PI) end<-----
8821 11:03:49.237367
8822 11:03:49.237425 ==
8823 11:03:49.240542 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 11:03:49.243854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 11:03:49.243930 ==
8826 11:03:49.247073 [Gating] SW mode calibration
8827 11:03:49.254133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8828 11:03:49.260339 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8829 11:03:49.264028 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 11:03:49.267225 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 11:03:49.273642 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
8832 11:03:49.277007 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8833 11:03:49.280265 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 11:03:49.286951 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 11:03:49.290620 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 11:03:49.293896 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 11:03:49.300025 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 11:03:49.303506 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 11:03:49.306867 1 5 8 | B1->B0 | 2626 3434 | 1 1 | (1 0) (1 0)
8840 11:03:49.313504 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8841 11:03:49.317071 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 11:03:49.320051 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 11:03:49.326717 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 11:03:49.329924 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 11:03:49.333370 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 11:03:49.340389 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8847 11:03:49.343587 1 6 8 | B1->B0 | 3c3c 2424 | 0 0 | (0 0) (0 0)
8848 11:03:49.346956 1 6 12 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (0 0)
8849 11:03:49.353474 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 11:03:49.357068 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 11:03:49.360347 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 11:03:49.363515 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 11:03:49.370445 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 11:03:49.373373 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:03:49.376703 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8856 11:03:49.383508 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8857 11:03:49.387040 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:03:49.390397 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:03:49.396647 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:03:49.400298 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:03:49.403439 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:03:49.410048 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:03:49.413551 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:03:49.416777 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:03:49.423749 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:03:49.426768 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:03:49.430451 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:03:49.437250 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:03:49.440154 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:03:49.443597 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:03:49.450192 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8872 11:03:49.453563 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8873 11:03:49.456772 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 11:03:49.460168 Total UI for P1: 0, mck2ui 16
8875 11:03:49.463785 best dqsien dly found for B0: ( 1, 9, 10)
8876 11:03:49.466630 Total UI for P1: 0, mck2ui 16
8877 11:03:49.470138 best dqsien dly found for B1: ( 1, 9, 10)
8878 11:03:49.473281 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8879 11:03:49.476479 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8880 11:03:49.476540
8881 11:03:49.480111 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8882 11:03:49.486571 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8883 11:03:49.486689 [Gating] SW calibration Done
8884 11:03:49.486760 ==
8885 11:03:49.489983 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 11:03:49.496595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 11:03:49.496660 ==
8888 11:03:49.496741 RX Vref Scan: 0
8889 11:03:49.496819
8890 11:03:49.500281 RX Vref 0 -> 0, step: 1
8891 11:03:49.500339
8892 11:03:49.503473 RX Delay 0 -> 252, step: 8
8893 11:03:49.506756 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8894 11:03:49.510110 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8895 11:03:49.513202 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8896 11:03:49.516784 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8897 11:03:49.523443 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8898 11:03:49.526782 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8899 11:03:49.529943 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8900 11:03:49.533272 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8901 11:03:49.536792 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8902 11:03:49.543242 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8903 11:03:49.546574 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8904 11:03:49.549848 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8905 11:03:49.553056 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8906 11:03:49.556530 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8907 11:03:49.563248 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8908 11:03:49.566308 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8909 11:03:49.566399 ==
8910 11:03:49.569564 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 11:03:49.572918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 11:03:49.573009 ==
8913 11:03:49.576249 DQS Delay:
8914 11:03:49.576312 DQS0 = 0, DQS1 = 0
8915 11:03:49.576365 DQM Delay:
8916 11:03:49.579651 DQM0 = 138, DQM1 = 131
8917 11:03:49.579736 DQ Delay:
8918 11:03:49.582974 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =139
8919 11:03:49.586204 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =139
8920 11:03:49.592764 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8921 11:03:49.596106 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8922 11:03:49.596194
8923 11:03:49.596264
8924 11:03:49.596316 ==
8925 11:03:49.599384 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 11:03:49.602908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 11:03:49.602994 ==
8928 11:03:49.603072
8929 11:03:49.603150
8930 11:03:49.606386 TX Vref Scan disable
8931 11:03:49.609516 == TX Byte 0 ==
8932 11:03:49.612881 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8933 11:03:49.616011 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8934 11:03:49.619364 == TX Byte 1 ==
8935 11:03:49.622648 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8936 11:03:49.625993 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8937 11:03:49.626083 ==
8938 11:03:49.629588 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 11:03:49.632817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 11:03:49.635609 ==
8941 11:03:49.647562
8942 11:03:49.650736 TX Vref early break, caculate TX vref
8943 11:03:49.653928 TX Vref=16, minBit 9, minWin=22, winSum=380
8944 11:03:49.657446 TX Vref=18, minBit 9, minWin=22, winSum=391
8945 11:03:49.660769 TX Vref=20, minBit 9, minWin=23, winSum=403
8946 11:03:49.663974 TX Vref=22, minBit 9, minWin=23, winSum=407
8947 11:03:49.667378 TX Vref=24, minBit 13, minWin=24, winSum=417
8948 11:03:49.673890 TX Vref=26, minBit 13, minWin=25, winSum=422
8949 11:03:49.677241 TX Vref=28, minBit 10, minWin=24, winSum=419
8950 11:03:49.680565 TX Vref=30, minBit 9, minWin=24, winSum=408
8951 11:03:49.683708 TX Vref=32, minBit 15, minWin=23, winSum=400
8952 11:03:49.687276 TX Vref=34, minBit 10, minWin=23, winSum=390
8953 11:03:49.694068 [TxChooseVref] Worse bit 13, Min win 25, Win sum 422, Final Vref 26
8954 11:03:49.694161
8955 11:03:49.697250 Final TX Range 0 Vref 26
8956 11:03:49.697331
8957 11:03:49.697402 ==
8958 11:03:49.700539 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 11:03:49.703775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 11:03:49.703868 ==
8961 11:03:49.703952
8962 11:03:49.704031
8963 11:03:49.707259 TX Vref Scan disable
8964 11:03:49.713982 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8965 11:03:49.714078 == TX Byte 0 ==
8966 11:03:49.717247 u2DelayCellOfst[0]=13 cells (4 PI)
8967 11:03:49.720645 u2DelayCellOfst[1]=10 cells (3 PI)
8968 11:03:49.723690 u2DelayCellOfst[2]=0 cells (0 PI)
8969 11:03:49.726996 u2DelayCellOfst[3]=3 cells (1 PI)
8970 11:03:49.730251 u2DelayCellOfst[4]=6 cells (2 PI)
8971 11:03:49.733640 u2DelayCellOfst[5]=16 cells (5 PI)
8972 11:03:49.736998 u2DelayCellOfst[6]=13 cells (4 PI)
8973 11:03:49.740449 u2DelayCellOfst[7]=3 cells (1 PI)
8974 11:03:49.743702 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8975 11:03:49.746983 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8976 11:03:49.750406 == TX Byte 1 ==
8977 11:03:49.753546 u2DelayCellOfst[8]=0 cells (0 PI)
8978 11:03:49.753615 u2DelayCellOfst[9]=3 cells (1 PI)
8979 11:03:49.756836 u2DelayCellOfst[10]=10 cells (3 PI)
8980 11:03:49.760115 u2DelayCellOfst[11]=3 cells (1 PI)
8981 11:03:49.763530 u2DelayCellOfst[12]=13 cells (4 PI)
8982 11:03:49.766718 u2DelayCellOfst[13]=13 cells (4 PI)
8983 11:03:49.769971 u2DelayCellOfst[14]=16 cells (5 PI)
8984 11:03:49.773484 u2DelayCellOfst[15]=16 cells (5 PI)
8985 11:03:49.776752 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8986 11:03:49.783630 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8987 11:03:49.783725 DramC Write-DBI on
8988 11:03:49.783808 ==
8989 11:03:49.786655 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 11:03:49.793285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 11:03:49.793386 ==
8992 11:03:49.793472
8993 11:03:49.793551
8994 11:03:49.793629 TX Vref Scan disable
8995 11:03:49.797315 == TX Byte 0 ==
8996 11:03:49.800448 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8997 11:03:49.804089 == TX Byte 1 ==
8998 11:03:49.807243 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8999 11:03:49.810449 DramC Write-DBI off
9000 11:03:49.810526
9001 11:03:49.810584 [DATLAT]
9002 11:03:49.810638 Freq=1600, CH1 RK1
9003 11:03:49.810705
9004 11:03:49.813744 DATLAT Default: 0xf
9005 11:03:49.813865 0, 0xFFFF, sum = 0
9006 11:03:49.817335 1, 0xFFFF, sum = 0
9007 11:03:49.817412 2, 0xFFFF, sum = 0
9008 11:03:49.820750 3, 0xFFFF, sum = 0
9009 11:03:49.820841 4, 0xFFFF, sum = 0
9010 11:03:49.824150 5, 0xFFFF, sum = 0
9011 11:03:49.827403 6, 0xFFFF, sum = 0
9012 11:03:49.827481 7, 0xFFFF, sum = 0
9013 11:03:49.830795 8, 0xFFFF, sum = 0
9014 11:03:49.830872 9, 0xFFFF, sum = 0
9015 11:03:49.833689 10, 0xFFFF, sum = 0
9016 11:03:49.833766 11, 0xFFFF, sum = 0
9017 11:03:49.836980 12, 0xFFFF, sum = 0
9018 11:03:49.837083 13, 0xFFFF, sum = 0
9019 11:03:49.840444 14, 0x0, sum = 1
9020 11:03:49.840520 15, 0x0, sum = 2
9021 11:03:49.843812 16, 0x0, sum = 3
9022 11:03:49.843888 17, 0x0, sum = 4
9023 11:03:49.847146 best_step = 15
9024 11:03:49.847224
9025 11:03:49.847283 ==
9026 11:03:49.850352 Dram Type= 6, Freq= 0, CH_1, rank 1
9027 11:03:49.854147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9028 11:03:49.854222 ==
9029 11:03:49.854280 RX Vref Scan: 0
9030 11:03:49.854333
9031 11:03:49.857433 RX Vref 0 -> 0, step: 1
9032 11:03:49.857508
9033 11:03:49.860821 RX Delay 19 -> 252, step: 4
9034 11:03:49.864159 iDelay=191, Bit 0, Center 138 (95 ~ 182) 88
9035 11:03:49.867547 iDelay=191, Bit 1, Center 132 (87 ~ 178) 92
9036 11:03:49.873932 iDelay=191, Bit 2, Center 120 (71 ~ 170) 100
9037 11:03:49.877391 iDelay=191, Bit 3, Center 132 (83 ~ 182) 100
9038 11:03:49.880545 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
9039 11:03:49.883942 iDelay=191, Bit 5, Center 144 (99 ~ 190) 92
9040 11:03:49.887081 iDelay=191, Bit 6, Center 144 (99 ~ 190) 92
9041 11:03:49.893897 iDelay=191, Bit 7, Center 132 (83 ~ 182) 100
9042 11:03:49.897095 iDelay=191, Bit 8, Center 112 (63 ~ 162) 100
9043 11:03:49.900488 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
9044 11:03:49.903639 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
9045 11:03:49.907026 iDelay=191, Bit 11, Center 124 (71 ~ 178) 108
9046 11:03:49.913683 iDelay=191, Bit 12, Center 138 (87 ~ 190) 104
9047 11:03:49.917307 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9048 11:03:49.920196 iDelay=191, Bit 14, Center 138 (91 ~ 186) 96
9049 11:03:49.923851 iDelay=191, Bit 15, Center 138 (87 ~ 190) 104
9050 11:03:49.923949 ==
9051 11:03:49.927359 Dram Type= 6, Freq= 0, CH_1, rank 1
9052 11:03:49.930401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9053 11:03:49.933772 ==
9054 11:03:49.933864 DQS Delay:
9055 11:03:49.933939 DQS0 = 0, DQS1 = 0
9056 11:03:49.937088 DQM Delay:
9057 11:03:49.937205 DQM0 = 134, DQM1 = 129
9058 11:03:49.940446 DQ Delay:
9059 11:03:49.943920 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
9060 11:03:49.947352 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
9061 11:03:49.950364 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9062 11:03:49.954123 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
9063 11:03:49.954199
9064 11:03:49.954256
9065 11:03:49.954309
9066 11:03:49.957555 [DramC_TX_OE_Calibration] TA2
9067 11:03:49.960960 Original DQ_B0 (3 6) =30, OEN = 27
9068 11:03:49.964167 Original DQ_B1 (3 6) =30, OEN = 27
9069 11:03:49.964243 24, 0x0, End_B0=24 End_B1=24
9070 11:03:49.967382 25, 0x0, End_B0=25 End_B1=25
9071 11:03:49.970673 26, 0x0, End_B0=26 End_B1=26
9072 11:03:49.974053 27, 0x0, End_B0=27 End_B1=27
9073 11:03:49.977578 28, 0x0, End_B0=28 End_B1=28
9074 11:03:49.977687 29, 0x0, End_B0=29 End_B1=29
9075 11:03:49.980584 30, 0x0, End_B0=30 End_B1=30
9076 11:03:49.984095 31, 0x4141, End_B0=30 End_B1=30
9077 11:03:49.987284 Byte0 end_step=30 best_step=27
9078 11:03:49.990673 Byte1 end_step=30 best_step=27
9079 11:03:49.993994 Byte0 TX OE(2T, 0.5T) = (3, 3)
9080 11:03:49.994069 Byte1 TX OE(2T, 0.5T) = (3, 3)
9081 11:03:49.994127
9082 11:03:49.994180
9083 11:03:50.003959 [DQSOSCAuto] RK1, (LSB)MR18= 0x210c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
9084 11:03:50.007086 CH1 RK1: MR19=303, MR18=210C
9085 11:03:50.013973 CH1_RK1: MR19=0x303, MR18=0x210C, DQSOSC=393, MR23=63, INC=23, DEC=15
9086 11:03:50.014052 [RxdqsGatingPostProcess] freq 1600
9087 11:03:50.020244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9088 11:03:50.024150 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 11:03:50.026942 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 11:03:50.030242 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 11:03:50.033955 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 11:03:50.036945 best DQS0 dly(2T, 0.5T) = (1, 1)
9093 11:03:50.040649 best DQS1 dly(2T, 0.5T) = (1, 1)
9094 11:03:50.043787 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9095 11:03:50.043888 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9096 11:03:50.047225 Pre-setting of DQS Precalculation
9097 11:03:50.053643 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9098 11:03:50.060421 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9099 11:03:50.067199 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 11:03:50.067275
9101 11:03:50.067334
9102 11:03:50.070420 [Calibration Summary] 3200 Mbps
9103 11:03:50.073781 CH 0, Rank 0
9104 11:03:50.073856 SW Impedance : PASS
9105 11:03:50.077123 DUTY Scan : NO K
9106 11:03:50.080423 ZQ Calibration : PASS
9107 11:03:50.080521 Jitter Meter : NO K
9108 11:03:50.083746 CBT Training : PASS
9109 11:03:50.083839 Write leveling : PASS
9110 11:03:50.086932 RX DQS gating : PASS
9111 11:03:50.090286 RX DQ/DQS(RDDQC) : PASS
9112 11:03:50.090388 TX DQ/DQS : PASS
9113 11:03:50.093616 RX DATLAT : PASS
9114 11:03:50.096917 RX DQ/DQS(Engine): PASS
9115 11:03:50.097011 TX OE : PASS
9116 11:03:50.100118 All Pass.
9117 11:03:50.100211
9118 11:03:50.100293 CH 0, Rank 1
9119 11:03:50.103806 SW Impedance : PASS
9120 11:03:50.103881 DUTY Scan : NO K
9121 11:03:50.107073 ZQ Calibration : PASS
9122 11:03:50.110485 Jitter Meter : NO K
9123 11:03:50.110580 CBT Training : PASS
9124 11:03:50.113797 Write leveling : PASS
9125 11:03:50.116760 RX DQS gating : PASS
9126 11:03:50.116856 RX DQ/DQS(RDDQC) : PASS
9127 11:03:50.120045 TX DQ/DQS : PASS
9128 11:03:50.123451 RX DATLAT : PASS
9129 11:03:50.123545 RX DQ/DQS(Engine): PASS
9130 11:03:50.126634 TX OE : PASS
9131 11:03:50.126728 All Pass.
9132 11:03:50.126811
9133 11:03:50.130122 CH 1, Rank 0
9134 11:03:50.130214 SW Impedance : PASS
9135 11:03:50.133348 DUTY Scan : NO K
9136 11:03:50.133439 ZQ Calibration : PASS
9137 11:03:50.137034 Jitter Meter : NO K
9138 11:03:50.140282 CBT Training : PASS
9139 11:03:50.140365 Write leveling : PASS
9140 11:03:50.143398 RX DQS gating : PASS
9141 11:03:50.146699 RX DQ/DQS(RDDQC) : PASS
9142 11:03:50.146797 TX DQ/DQS : PASS
9143 11:03:50.150129 RX DATLAT : PASS
9144 11:03:50.153391 RX DQ/DQS(Engine): PASS
9145 11:03:50.153487 TX OE : PASS
9146 11:03:50.156611 All Pass.
9147 11:03:50.156711
9148 11:03:50.156797 CH 1, Rank 1
9149 11:03:50.160039 SW Impedance : PASS
9150 11:03:50.160133 DUTY Scan : NO K
9151 11:03:50.163254 ZQ Calibration : PASS
9152 11:03:50.166578 Jitter Meter : NO K
9153 11:03:50.166676 CBT Training : PASS
9154 11:03:50.170114 Write leveling : PASS
9155 11:03:50.173310 RX DQS gating : PASS
9156 11:03:50.173379 RX DQ/DQS(RDDQC) : PASS
9157 11:03:50.176556 TX DQ/DQS : PASS
9158 11:03:50.176649 RX DATLAT : PASS
9159 11:03:50.180130 RX DQ/DQS(Engine): PASS
9160 11:03:50.183488 TX OE : PASS
9161 11:03:50.183582 All Pass.
9162 11:03:50.183675
9163 11:03:50.186836 DramC Write-DBI on
9164 11:03:50.186930 PER_BANK_REFRESH: Hybrid Mode
9165 11:03:50.189918 TX_TRACKING: ON
9166 11:03:50.199921 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9167 11:03:50.206846 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9168 11:03:50.213444 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9169 11:03:50.216659 [FAST_K] Save calibration result to emmc
9170 11:03:50.220216 sync common calibartion params.
9171 11:03:50.223589 sync cbt_mode0:1, 1:1
9172 11:03:50.223681 dram_init: ddr_geometry: 2
9173 11:03:50.226849 dram_init: ddr_geometry: 2
9174 11:03:50.230204 dram_init: ddr_geometry: 2
9175 11:03:50.233516 0:dram_rank_size:100000000
9176 11:03:50.233593 1:dram_rank_size:100000000
9177 11:03:50.240017 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9178 11:03:50.243321 DFS_SHUFFLE_HW_MODE: ON
9179 11:03:50.247058 dramc_set_vcore_voltage set vcore to 725000
9180 11:03:50.247134 Read voltage for 1600, 0
9181 11:03:50.250092 Vio18 = 0
9182 11:03:50.250167 Vcore = 725000
9183 11:03:50.250225 Vdram = 0
9184 11:03:50.253705 Vddq = 0
9185 11:03:50.253780 Vmddr = 0
9186 11:03:50.256924 switch to 3200 Mbps bootup
9187 11:03:50.256999 [DramcRunTimeConfig]
9188 11:03:50.257056 PHYPLL
9189 11:03:50.260061 DPM_CONTROL_AFTERK: ON
9190 11:03:50.263352 PER_BANK_REFRESH: ON
9191 11:03:50.263430 REFRESH_OVERHEAD_REDUCTION: ON
9192 11:03:50.266578 CMD_PICG_NEW_MODE: OFF
9193 11:03:50.270072 XRTWTW_NEW_MODE: ON
9194 11:03:50.270162 XRTRTR_NEW_MODE: ON
9195 11:03:50.273448 TX_TRACKING: ON
9196 11:03:50.273523 RDSEL_TRACKING: OFF
9197 11:03:50.276754 DQS Precalculation for DVFS: ON
9198 11:03:50.276829 RX_TRACKING: OFF
9199 11:03:50.280267 HW_GATING DBG: ON
9200 11:03:50.283645 ZQCS_ENABLE_LP4: ON
9201 11:03:50.283719 RX_PICG_NEW_MODE: ON
9202 11:03:50.286929 TX_PICG_NEW_MODE: ON
9203 11:03:50.287020 ENABLE_RX_DCM_DPHY: ON
9204 11:03:50.290229 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9205 11:03:50.293661 DUMMY_READ_FOR_TRACKING: OFF
9206 11:03:50.296744 !!! SPM_CONTROL_AFTERK: OFF
9207 11:03:50.299989 !!! SPM could not control APHY
9208 11:03:50.300066 IMPEDANCE_TRACKING: ON
9209 11:03:50.303418 TEMP_SENSOR: ON
9210 11:03:50.303492 HW_SAVE_FOR_SR: OFF
9211 11:03:50.306758 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9212 11:03:50.310098 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9213 11:03:50.313418 Read ODT Tracking: ON
9214 11:03:50.313494 Refresh Rate DeBounce: ON
9215 11:03:50.316900 DFS_NO_QUEUE_FLUSH: ON
9216 11:03:50.320185 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9217 11:03:50.323531 ENABLE_DFS_RUNTIME_MRW: OFF
9218 11:03:50.323607 DDR_RESERVE_NEW_MODE: ON
9219 11:03:50.326566 MR_CBT_SWITCH_FREQ: ON
9220 11:03:50.330086 =========================
9221 11:03:50.347996 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9222 11:03:50.351605 dram_init: ddr_geometry: 2
9223 11:03:50.369601 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9224 11:03:50.373258 dram_init: dram init end (result: 0)
9225 11:03:50.379543 DRAM-K: Full calibration passed in 24517 msecs
9226 11:03:50.382857 MRC: failed to locate region type 0.
9227 11:03:50.382933 DRAM rank0 size:0x100000000,
9228 11:03:50.386107 DRAM rank1 size=0x100000000
9229 11:03:50.396441 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9230 11:03:50.402983 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9231 11:03:50.409465 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9232 11:03:50.416172 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9233 11:03:50.419284 DRAM rank0 size:0x100000000,
9234 11:03:50.422881 DRAM rank1 size=0x100000000
9235 11:03:50.422950 CBMEM:
9236 11:03:50.426120 IMD: root @ 0xfffff000 254 entries.
9237 11:03:50.429202 IMD: root @ 0xffffec00 62 entries.
9238 11:03:50.432715 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9239 11:03:50.436225 WARNING: RO_VPD is uninitialized or empty.
9240 11:03:50.442607 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9241 11:03:50.449902 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9242 11:03:50.462358 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9243 11:03:50.473781 BS: romstage times (exec / console): total (unknown) / 24013 ms
9244 11:03:50.473858
9245 11:03:50.473917
9246 11:03:50.483883 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9247 11:03:50.487302 ARM64: Exception handlers installed.
9248 11:03:50.490710 ARM64: Testing exception
9249 11:03:50.493974 ARM64: Done test exception
9250 11:03:50.494087 Enumerating buses...
9251 11:03:50.497255 Show all devs... Before device enumeration.
9252 11:03:50.500353 Root Device: enabled 1
9253 11:03:50.504137 CPU_CLUSTER: 0: enabled 1
9254 11:03:50.504212 CPU: 00: enabled 1
9255 11:03:50.507230 Compare with tree...
9256 11:03:50.507329 Root Device: enabled 1
9257 11:03:50.510568 CPU_CLUSTER: 0: enabled 1
9258 11:03:50.514145 CPU: 00: enabled 1
9259 11:03:50.514223 Root Device scanning...
9260 11:03:50.517455 scan_static_bus for Root Device
9261 11:03:50.520896 CPU_CLUSTER: 0 enabled
9262 11:03:50.523948 scan_static_bus for Root Device done
9263 11:03:50.527203 scan_bus: bus Root Device finished in 8 msecs
9264 11:03:50.527281 done
9265 11:03:50.534007 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9266 11:03:50.537414 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9267 11:03:50.543765 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9268 11:03:50.547127 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9269 11:03:50.550557 Allocating resources...
9270 11:03:50.550635 Reading resources...
9271 11:03:50.557297 Root Device read_resources bus 0 link: 0
9272 11:03:50.557375 DRAM rank0 size:0x100000000,
9273 11:03:50.560539 DRAM rank1 size=0x100000000
9274 11:03:50.563743 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9275 11:03:50.567210 CPU: 00 missing read_resources
9276 11:03:50.570566 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9277 11:03:50.577020 Root Device read_resources bus 0 link: 0 done
9278 11:03:50.577122 Done reading resources.
9279 11:03:50.583906 Show resources in subtree (Root Device)...After reading.
9280 11:03:50.587230 Root Device child on link 0 CPU_CLUSTER: 0
9281 11:03:50.590446 CPU_CLUSTER: 0 child on link 0 CPU: 00
9282 11:03:50.600241 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9283 11:03:50.600346 CPU: 00
9284 11:03:50.604020 Root Device assign_resources, bus 0 link: 0
9285 11:03:50.606955 CPU_CLUSTER: 0 missing set_resources
9286 11:03:50.610314 Root Device assign_resources, bus 0 link: 0 done
9287 11:03:50.613485 Done setting resources.
9288 11:03:50.620335 Show resources in subtree (Root Device)...After assigning values.
9289 11:03:50.623661 Root Device child on link 0 CPU_CLUSTER: 0
9290 11:03:50.626917 CPU_CLUSTER: 0 child on link 0 CPU: 00
9291 11:03:50.636843 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9292 11:03:50.636920 CPU: 00
9293 11:03:50.640383 Done allocating resources.
9294 11:03:50.643358 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9295 11:03:50.646810 Enabling resources...
9296 11:03:50.646885 done.
9297 11:03:50.650121 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9298 11:03:50.653845 Initializing devices...
9299 11:03:50.657403 Root Device init
9300 11:03:50.657491 init hardware done!
9301 11:03:50.660157 0x00000018: ctrlr->caps
9302 11:03:50.660259 52.000 MHz: ctrlr->f_max
9303 11:03:50.663424 0.400 MHz: ctrlr->f_min
9304 11:03:50.667005 0x40ff8080: ctrlr->voltages
9305 11:03:50.667082 sclk: 390625
9306 11:03:50.670262 Bus Width = 1
9307 11:03:50.670360 sclk: 390625
9308 11:03:50.670490 Bus Width = 1
9309 11:03:50.674036 Early init status = 3
9310 11:03:50.676991 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9311 11:03:50.681145 in-header: 03 fc 00 00 01 00 00 00
9312 11:03:50.684549 in-data: 00
9313 11:03:50.687729 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9314 11:03:50.692464 in-header: 03 fd 00 00 00 00 00 00
9315 11:03:50.695932 in-data:
9316 11:03:50.699172 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9317 11:03:50.702703 in-header: 03 fc 00 00 01 00 00 00
9318 11:03:50.706035 in-data: 00
9319 11:03:50.709306 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9320 11:03:50.713746 in-header: 03 fd 00 00 00 00 00 00
9321 11:03:50.717553 in-data:
9322 11:03:50.720900 [SSUSB] Setting up USB HOST controller...
9323 11:03:50.723969 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9324 11:03:50.727408 [SSUSB] phy power-on done.
9325 11:03:50.730611 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9326 11:03:50.737085 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9327 11:03:50.740412 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9328 11:03:50.747016 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9329 11:03:50.755074 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9330 11:03:50.760172 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9331 11:03:50.767218 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9332 11:03:50.773851 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9333 11:03:50.777112 SPM: binary array size = 0x9dc
9334 11:03:50.780468 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9335 11:03:50.786867 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9336 11:03:50.793478 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9337 11:03:50.796805 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9338 11:03:50.803114 configure_display: Starting display init
9339 11:03:50.837206 anx7625_power_on_init: Init interface.
9340 11:03:50.840749 anx7625_disable_pd_protocol: Disabled PD feature.
9341 11:03:50.843575 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9342 11:03:50.871500 anx7625_start_dp_work: Secure OCM version=00
9343 11:03:50.874861 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9344 11:03:50.889654 sp_tx_get_edid_block: EDID Block = 1
9345 11:03:50.992125 Extracted contents:
9346 11:03:50.995602 header: 00 ff ff ff ff ff ff 00
9347 11:03:50.998773 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9348 11:03:51.002303 version: 01 04
9349 11:03:51.005452 basic params: 95 1f 11 78 0a
9350 11:03:51.008788 chroma info: 76 90 94 55 54 90 27 21 50 54
9351 11:03:51.012179 established: 00 00 00
9352 11:03:51.019017 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9353 11:03:51.022046 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9354 11:03:51.028593 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9355 11:03:51.035430 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9356 11:03:51.041860 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9357 11:03:51.045066 extensions: 00
9358 11:03:51.045196 checksum: fb
9359 11:03:51.045280
9360 11:03:51.048813 Manufacturer: IVO Model 57d Serial Number 0
9361 11:03:51.052202 Made week 0 of 2020
9362 11:03:51.052277 EDID version: 1.4
9363 11:03:51.055326 Digital display
9364 11:03:51.058819 6 bits per primary color channel
9365 11:03:51.058949 DisplayPort interface
9366 11:03:51.061957 Maximum image size: 31 cm x 17 cm
9367 11:03:51.065067 Gamma: 220%
9368 11:03:51.065198 Check DPMS levels
9369 11:03:51.068486 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9370 11:03:51.071857 First detailed timing is preferred timing
9371 11:03:51.075459 Established timings supported:
9372 11:03:51.078318 Standard timings supported:
9373 11:03:51.081807 Detailed timings
9374 11:03:51.085007 Hex of detail: 383680a07038204018303c0035ae10000019
9375 11:03:51.088807 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9376 11:03:51.095316 0780 0798 07c8 0820 hborder 0
9377 11:03:51.098547 0438 043b 0447 0458 vborder 0
9378 11:03:51.101727 -hsync -vsync
9379 11:03:51.101804 Did detailed timing
9380 11:03:51.105078 Hex of detail: 000000000000000000000000000000000000
9381 11:03:51.108365 Manufacturer-specified data, tag 0
9382 11:03:51.114958 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9383 11:03:51.115036 ASCII string: InfoVision
9384 11:03:51.121803 Hex of detail: 000000fe00523134304e574635205248200a
9385 11:03:51.125097 ASCII string: R140NWF5 RH
9386 11:03:51.125210 Checksum
9387 11:03:51.125269 Checksum: 0xfb (valid)
9388 11:03:51.132147 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9389 11:03:51.134971 DSI data_rate: 832800000 bps
9390 11:03:51.138568 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9391 11:03:51.145043 anx7625_parse_edid: pixelclock(138800).
9392 11:03:51.148285 hactive(1920), hsync(48), hfp(24), hbp(88)
9393 11:03:51.151632 vactive(1080), vsync(12), vfp(3), vbp(17)
9394 11:03:51.155446 anx7625_dsi_config: config dsi.
9395 11:03:51.161606 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9396 11:03:51.174125 anx7625_dsi_config: success to config DSI
9397 11:03:51.177728 anx7625_dp_start: MIPI phy setup OK.
9398 11:03:51.180998 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9399 11:03:51.184418 mtk_ddp_mode_set invalid vrefresh 60
9400 11:03:51.187712 main_disp_path_setup
9401 11:03:51.187787 ovl_layer_smi_id_en
9402 11:03:51.190892 ovl_layer_smi_id_en
9403 11:03:51.190969 ccorr_config
9404 11:03:51.191028 aal_config
9405 11:03:51.194171 gamma_config
9406 11:03:51.194246 postmask_config
9407 11:03:51.197768 dither_config
9408 11:03:51.201263 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9409 11:03:51.207755 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9410 11:03:51.211062 Root Device init finished in 551 msecs
9411 11:03:51.211138 CPU_CLUSTER: 0 init
9412 11:03:51.220930 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9413 11:03:51.224222 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9414 11:03:51.227483 APU_MBOX 0x190000b0 = 0x10001
9415 11:03:51.230757 APU_MBOX 0x190001b0 = 0x10001
9416 11:03:51.233969 APU_MBOX 0x190005b0 = 0x10001
9417 11:03:51.237602 APU_MBOX 0x190006b0 = 0x10001
9418 11:03:51.240813 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9419 11:03:51.253376 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9420 11:03:51.265743 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9421 11:03:51.272190 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9422 11:03:51.284176 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9423 11:03:51.293325 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9424 11:03:51.296332 CPU_CLUSTER: 0 init finished in 81 msecs
9425 11:03:51.299778 Devices initialized
9426 11:03:51.303065 Show all devs... After init.
9427 11:03:51.303141 Root Device: enabled 1
9428 11:03:51.306191 CPU_CLUSTER: 0: enabled 1
9429 11:03:51.309655 CPU: 00: enabled 1
9430 11:03:51.312970 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9431 11:03:51.316076 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9432 11:03:51.319527 ELOG: NV offset 0x57f000 size 0x1000
9433 11:03:51.326367 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9434 11:03:51.332747 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9435 11:03:51.335989 ELOG: Event(17) added with size 13 at 2024-07-10 11:03:44 UTC
9436 11:03:51.339714 out: cmd=0x121: 03 db 21 01 00 00 00 00
9437 11:03:51.343374 in-header: 03 68 00 00 2c 00 00 00
9438 11:03:51.356670 in-data: d7 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9439 11:03:51.363345 ELOG: Event(A1) added with size 10 at 2024-07-10 11:03:44 UTC
9440 11:03:51.369984 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9441 11:03:51.376790 ELOG: Event(A0) added with size 9 at 2024-07-10 11:03:44 UTC
9442 11:03:51.379907 elog_add_boot_reason: Logged dev mode boot
9443 11:03:51.383101 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9444 11:03:51.386874 Finalize devices...
9445 11:03:51.386951 Devices finalized
9446 11:03:51.393213 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9447 11:03:51.396350 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9448 11:03:51.400147 in-header: 03 07 00 00 08 00 00 00
9449 11:03:51.403344 in-data: aa e4 47 04 13 02 00 00
9450 11:03:51.406548 Chrome EC: UHEPI supported
9451 11:03:51.413104 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9452 11:03:51.416346 in-header: 03 a9 00 00 08 00 00 00
9453 11:03:51.419683 in-data: 84 60 60 08 00 00 00 00
9454 11:03:51.423197 ELOG: Event(91) added with size 10 at 2024-07-10 11:03:44 UTC
9455 11:03:51.429749 Chrome EC: clear events_b mask to 0x0000000020004000
9456 11:03:51.436875 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9457 11:03:51.440246 in-header: 03 fd 00 00 00 00 00 00
9458 11:03:51.440322 in-data:
9459 11:03:51.446635 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9460 11:03:51.450107 Writing coreboot table at 0xffe64000
9461 11:03:51.453248 0. 000000000010a000-0000000000113fff: RAMSTAGE
9462 11:03:51.456541 1. 0000000040000000-00000000400fffff: RAM
9463 11:03:51.459861 2. 0000000040100000-000000004032afff: RAMSTAGE
9464 11:03:51.463186 3. 000000004032b000-00000000545fffff: RAM
9465 11:03:51.469878 4. 0000000054600000-000000005465ffff: BL31
9466 11:03:51.473058 5. 0000000054660000-00000000ffe63fff: RAM
9467 11:03:51.476395 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9468 11:03:51.483058 7. 0000000100000000-000000023fffffff: RAM
9469 11:03:51.483126 Passing 5 GPIOs to payload:
9470 11:03:51.489561 NAME | PORT | POLARITY | VALUE
9471 11:03:51.493248 EC in RW | 0x000000aa | low | undefined
9472 11:03:51.499813 EC interrupt | 0x00000005 | low | undefined
9473 11:03:51.503382 TPM interrupt | 0x000000ab | high | undefined
9474 11:03:51.506549 SD card detect | 0x00000011 | high | undefined
9475 11:03:51.512974 speaker enable | 0x00000093 | high | undefined
9476 11:03:51.516143 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9477 11:03:51.519486 in-header: 03 f9 00 00 02 00 00 00
9478 11:03:51.519554 in-data: 02 00
9479 11:03:51.523260 ADC[4]: Raw value=900663 ID=7
9480 11:03:51.526515 ADC[3]: Raw value=213179 ID=1
9481 11:03:51.526581 RAM Code: 0x71
9482 11:03:51.529740 ADC[6]: Raw value=74502 ID=0
9483 11:03:51.532832 ADC[5]: Raw value=211703 ID=1
9484 11:03:51.532894 SKU Code: 0x1
9485 11:03:51.539417 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1e5a
9486 11:03:51.542966 coreboot table: 964 bytes.
9487 11:03:51.546518 IMD ROOT 0. 0xfffff000 0x00001000
9488 11:03:51.549683 IMD SMALL 1. 0xffffe000 0x00001000
9489 11:03:51.553328 RO MCACHE 2. 0xffffc000 0x00001104
9490 11:03:51.556183 CONSOLE 3. 0xfff7c000 0x00080000
9491 11:03:51.559728 FMAP 4. 0xfff7b000 0x00000452
9492 11:03:51.562997 TIME STAMP 5. 0xfff7a000 0x00000910
9493 11:03:51.566318 VBOOT WORK 6. 0xfff66000 0x00014000
9494 11:03:51.569558 RAMOOPS 7. 0xffe66000 0x00100000
9495 11:03:51.572781 COREBOOT 8. 0xffe64000 0x00002000
9496 11:03:51.572857 IMD small region:
9497 11:03:51.576079 IMD ROOT 0. 0xffffec00 0x00000400
9498 11:03:51.579876 VPD 1. 0xffffeb80 0x0000006c
9499 11:03:51.582933 MMC STATUS 2. 0xffffeb60 0x00000004
9500 11:03:51.589611 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9501 11:03:51.596076 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9502 11:03:51.635068 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9503 11:03:51.638225 Checking segment from ROM address 0x40100000
9504 11:03:51.641828 Checking segment from ROM address 0x4010001c
9505 11:03:51.648337 Loading segment from ROM address 0x40100000
9506 11:03:51.648414 code (compression=0)
9507 11:03:51.658554 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9508 11:03:51.665001 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9509 11:03:51.665102 it's not compressed!
9510 11:03:51.671579 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9511 11:03:51.674834 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9512 11:03:51.695546 Loading segment from ROM address 0x4010001c
9513 11:03:51.695623 Entry Point 0x80000000
9514 11:03:51.698790 Loaded segments
9515 11:03:51.702192 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9516 11:03:51.709134 Jumping to boot code at 0x80000000(0xffe64000)
9517 11:03:51.715707 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9518 11:03:51.722383 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9519 11:03:51.729772 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9520 11:03:51.733171 Checking segment from ROM address 0x40100000
9521 11:03:51.736762 Checking segment from ROM address 0x4010001c
9522 11:03:51.743278 Loading segment from ROM address 0x40100000
9523 11:03:51.743458 code (compression=1)
9524 11:03:51.750078 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9525 11:03:51.760213 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9526 11:03:51.760435 using LZMA
9527 11:03:51.768341 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9528 11:03:51.775232 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9529 11:03:51.778383 Loading segment from ROM address 0x4010001c
9530 11:03:51.778628 Entry Point 0x54601000
9531 11:03:51.781767 Loaded segments
9532 11:03:51.784851 NOTICE: MT8192 bl31_setup
9533 11:03:51.792227 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9534 11:03:51.795868 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9535 11:03:51.799158 WARNING: region 0:
9536 11:03:51.802390 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 11:03:51.802821 WARNING: region 1:
9538 11:03:51.808883 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9539 11:03:51.812141 WARNING: region 2:
9540 11:03:51.815415 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9541 11:03:51.818966 WARNING: region 3:
9542 11:03:51.822434 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 11:03:51.825570 WARNING: region 4:
9544 11:03:51.832372 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9545 11:03:51.832859 WARNING: region 5:
9546 11:03:51.835510 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 11:03:51.839140 WARNING: region 6:
9548 11:03:51.842338 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 11:03:51.845568 WARNING: region 7:
9550 11:03:51.849057 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 11:03:51.855751 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9552 11:03:51.858909 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9553 11:03:51.862241 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9554 11:03:51.869179 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9555 11:03:51.872202 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9556 11:03:51.875789 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9557 11:03:51.882558 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9558 11:03:51.885360 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9559 11:03:51.892122 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9560 11:03:51.895663 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9561 11:03:51.898861 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9562 11:03:51.905493 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9563 11:03:51.908694 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9564 11:03:51.912370 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9565 11:03:51.918402 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9566 11:03:51.921930 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9567 11:03:51.928478 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9568 11:03:51.931535 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9569 11:03:51.935352 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9570 11:03:51.942221 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9571 11:03:51.945484 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9572 11:03:51.948499 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9573 11:03:51.955605 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9574 11:03:51.959850 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9575 11:03:51.965696 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9576 11:03:51.969376 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9577 11:03:51.972537 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9578 11:03:51.979253 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9579 11:03:51.982474 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9580 11:03:51.989073 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9581 11:03:51.992453 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9582 11:03:51.995938 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9583 11:03:52.002602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9584 11:03:52.006080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9585 11:03:52.008890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9586 11:03:52.012404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9587 11:03:52.019071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9588 11:03:52.022006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9589 11:03:52.025483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9590 11:03:52.028864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9591 11:03:52.035153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9592 11:03:52.038419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9593 11:03:52.041828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9594 11:03:52.045257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9595 11:03:52.052189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9596 11:03:52.055388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9597 11:03:52.058644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9598 11:03:52.062115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9599 11:03:52.068332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9600 11:03:52.071484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9601 11:03:52.078439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9602 11:03:52.081556 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9603 11:03:52.088555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9604 11:03:52.091508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9605 11:03:52.098083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9606 11:03:52.101528 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9607 11:03:52.104838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9608 11:03:52.111535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9609 11:03:52.114860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9610 11:03:52.121419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9611 11:03:52.124668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9612 11:03:52.130976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9613 11:03:52.134374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9614 11:03:52.141234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9615 11:03:52.144374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9616 11:03:52.147611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9617 11:03:52.154831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9618 11:03:52.157870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9619 11:03:52.164812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9620 11:03:52.167504 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9621 11:03:52.174261 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9622 11:03:52.177485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9623 11:03:52.180683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9624 11:03:52.187541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9625 11:03:52.190636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9626 11:03:52.197649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9627 11:03:52.200837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9628 11:03:52.207284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9629 11:03:52.210708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9630 11:03:52.217200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9631 11:03:52.220700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9632 11:03:52.224242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9633 11:03:52.230771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9634 11:03:52.234154 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9635 11:03:52.240725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9636 11:03:52.243929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9637 11:03:52.250571 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9638 11:03:52.253782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9639 11:03:52.257305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9640 11:03:52.264404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9641 11:03:52.267606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9642 11:03:52.273717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9643 11:03:52.277517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9644 11:03:52.284343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9645 11:03:52.287423 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9646 11:03:52.294035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9647 11:03:52.297266 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9648 11:03:52.300597 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9649 11:03:52.304232 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9650 11:03:52.307103 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9651 11:03:52.314150 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9652 11:03:52.317225 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9653 11:03:52.324130 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9654 11:03:52.327339 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9655 11:03:52.330408 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9656 11:03:52.337668 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9657 11:03:52.340864 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9658 11:03:52.347239 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9659 11:03:52.350998 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9660 11:03:52.354038 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9661 11:03:52.360677 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9662 11:03:52.364391 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9663 11:03:52.370912 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9664 11:03:52.373854 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9665 11:03:52.377051 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9666 11:03:52.383994 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9667 11:03:52.386983 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9668 11:03:52.390297 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9669 11:03:52.397193 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9670 11:03:52.400594 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9671 11:03:52.404076 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9672 11:03:52.407237 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9673 11:03:52.410884 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9674 11:03:52.417346 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9675 11:03:52.420751 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9676 11:03:52.427196 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9677 11:03:52.430579 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9678 11:03:52.434281 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9679 11:03:52.440788 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9680 11:03:52.443831 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9681 11:03:52.447868 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9682 11:03:52.454387 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9683 11:03:52.457600 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9684 11:03:52.464095 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9685 11:03:52.467878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9686 11:03:52.471195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9687 11:03:52.477705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9688 11:03:52.480809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9689 11:03:52.487500 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9690 11:03:52.491341 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9691 11:03:52.494458 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9692 11:03:52.501081 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9693 11:03:52.504519 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9694 11:03:52.507685 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9695 11:03:52.514337 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9696 11:03:52.517434 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9697 11:03:52.524612 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9698 11:03:52.527807 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9699 11:03:52.530780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9700 11:03:52.537573 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9701 11:03:52.541224 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9702 11:03:52.547359 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9703 11:03:52.551040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9704 11:03:52.554189 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9705 11:03:52.561103 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9706 11:03:52.564382 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9707 11:03:52.567612 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9708 11:03:52.574224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9709 11:03:52.577740 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9710 11:03:52.583985 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9711 11:03:52.587302 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9712 11:03:52.591355 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9713 11:03:52.597192 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9714 11:03:52.600511 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9715 11:03:52.607773 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9716 11:03:52.611233 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9717 11:03:52.614057 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9718 11:03:52.620912 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9719 11:03:52.624247 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9720 11:03:52.630487 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9721 11:03:52.634137 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9722 11:03:52.637183 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9723 11:03:52.643760 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9724 11:03:52.647561 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9725 11:03:52.650928 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9726 11:03:52.657221 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9727 11:03:52.660531 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9728 11:03:52.667362 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9729 11:03:52.670744 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9730 11:03:52.673819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9731 11:03:52.680695 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9732 11:03:52.684116 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9733 11:03:52.690942 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9734 11:03:52.693874 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9735 11:03:52.697076 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9736 11:03:52.704094 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9737 11:03:52.707268 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9738 11:03:52.713631 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9739 11:03:52.717368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9740 11:03:52.720759 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9741 11:03:52.727254 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9742 11:03:52.730578 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9743 11:03:52.737229 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9744 11:03:52.740236 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9745 11:03:52.743524 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9746 11:03:52.750349 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9747 11:03:52.753869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9748 11:03:52.760517 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9749 11:03:52.763885 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9750 11:03:52.770499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9751 11:03:52.773795 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9752 11:03:52.776967 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9753 11:03:52.784176 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9754 11:03:52.786672 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9755 11:03:52.793493 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9756 11:03:52.796940 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9757 11:03:52.800295 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9758 11:03:52.807139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9759 11:03:52.810354 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9760 11:03:52.817254 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9761 11:03:52.820277 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9762 11:03:52.823585 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9763 11:03:52.830343 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9764 11:03:52.833692 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9765 11:03:52.840093 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9766 11:03:52.843629 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9767 11:03:52.850289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9768 11:03:52.853539 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9769 11:03:52.856822 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9770 11:03:52.863533 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9771 11:03:52.866819 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9772 11:03:52.873114 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9773 11:03:52.876513 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9774 11:03:52.879884 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9775 11:03:52.886440 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9776 11:03:52.889906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9777 11:03:52.896713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9778 11:03:52.899707 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9779 11:03:52.906831 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9780 11:03:52.910078 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9781 11:03:52.913344 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9782 11:03:52.916776 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9783 11:03:52.919758 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9784 11:03:52.926836 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9785 11:03:52.930054 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9786 11:03:52.932942 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9787 11:03:52.940186 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9788 11:03:52.943350 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9789 11:03:52.946398 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9790 11:03:52.953226 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9791 11:03:52.956688 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9792 11:03:52.962980 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9793 11:03:52.966722 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9794 11:03:52.969687 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9795 11:03:52.976234 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9796 11:03:52.979584 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9797 11:03:52.982734 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9798 11:03:52.989114 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9799 11:03:52.992567 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9800 11:03:52.996123 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9801 11:03:53.002708 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9802 11:03:53.005816 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9803 11:03:53.012887 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9804 11:03:53.016054 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9805 11:03:53.019221 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9806 11:03:53.025875 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9807 11:03:53.029708 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9808 11:03:53.032824 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9809 11:03:53.039259 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9810 11:03:53.042512 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9811 11:03:53.045782 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9812 11:03:53.052656 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9813 11:03:53.055823 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9814 11:03:53.058960 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9815 11:03:53.065841 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9816 11:03:53.069178 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9817 11:03:53.075797 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9818 11:03:53.079053 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9819 11:03:53.082139 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9820 11:03:53.085529 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9821 11:03:53.092297 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9822 11:03:53.095646 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9823 11:03:53.098972 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9824 11:03:53.102371 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9825 11:03:53.108965 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9826 11:03:53.112210 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9827 11:03:53.115954 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9828 11:03:53.119257 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9829 11:03:53.125742 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9830 11:03:53.129341 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9831 11:03:53.132724 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9832 11:03:53.136025 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9833 11:03:53.142853 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9834 11:03:53.146069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9835 11:03:53.152676 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9836 11:03:53.155937 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9837 11:03:53.159012 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9838 11:03:53.166119 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9839 11:03:53.169230 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9840 11:03:53.175779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9841 11:03:53.178960 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9842 11:03:53.182357 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9843 11:03:53.189038 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9844 11:03:53.192440 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9845 11:03:53.198886 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9846 11:03:53.202392 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9847 11:03:53.209064 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9848 11:03:53.212073 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9849 11:03:53.215417 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9850 11:03:53.222134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9851 11:03:53.225389 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9852 11:03:53.231990 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9853 11:03:53.235294 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9854 11:03:53.238897 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9855 11:03:53.245503 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9856 11:03:53.248910 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9857 11:03:53.255301 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9858 11:03:53.258642 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9859 11:03:53.261990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9860 11:03:53.268574 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9861 11:03:53.271844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9862 11:03:53.278889 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9863 11:03:53.282119 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9864 11:03:53.285491 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9865 11:03:53.292292 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9866 11:03:53.295460 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9867 11:03:53.301780 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9868 11:03:53.305173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9869 11:03:53.311810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9870 11:03:53.315154 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9871 11:03:53.318468 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9872 11:03:53.325143 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9873 11:03:53.328377 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9874 11:03:53.331773 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9875 11:03:53.338714 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9876 11:03:53.341955 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9877 11:03:53.348351 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9878 11:03:53.352134 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9879 11:03:53.358814 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9880 11:03:53.361655 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9881 11:03:53.365068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9882 11:03:53.371849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9883 11:03:53.375106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9884 11:03:53.381583 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9885 11:03:53.385357 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9886 11:03:53.388565 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9887 11:03:53.394974 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9888 11:03:53.398401 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9889 11:03:53.405097 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9890 11:03:53.408505 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9891 11:03:53.411853 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9892 11:03:53.418595 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9893 11:03:53.421871 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9894 11:03:53.428213 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9895 11:03:53.431713 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9896 11:03:53.434966 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9897 11:03:53.441872 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9898 11:03:53.444951 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9899 11:03:53.451822 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9900 11:03:53.455174 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9901 11:03:53.458288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9902 11:03:53.465367 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9903 11:03:53.468452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9904 11:03:53.475092 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9905 11:03:53.478783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9906 11:03:53.481813 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9907 11:03:53.488267 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9908 11:03:53.491539 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9909 11:03:53.498357 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9910 11:03:53.501647 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9911 11:03:53.508338 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9912 11:03:53.511507 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9913 11:03:53.514807 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9914 11:03:53.521593 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9915 11:03:53.525096 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9916 11:03:53.531533 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9917 11:03:53.534913 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9918 11:03:53.541683 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9919 11:03:53.544930 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9920 11:03:53.548056 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9921 11:03:53.554706 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9922 11:03:53.558061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9923 11:03:53.564959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9924 11:03:53.568374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9925 11:03:53.574739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9926 11:03:53.578638 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9927 11:03:53.585262 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9928 11:03:53.588281 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9929 11:03:53.591667 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9930 11:03:53.598394 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9931 11:03:53.601690 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9932 11:03:53.608596 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9933 11:03:53.611777 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9934 11:03:53.618581 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9935 11:03:53.621917 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9936 11:03:53.624983 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9937 11:03:53.631646 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9938 11:03:53.635073 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9939 11:03:53.641584 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9940 11:03:53.644960 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9941 11:03:53.648261 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9942 11:03:53.655116 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9943 11:03:53.658135 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9944 11:03:53.664733 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9945 11:03:53.668398 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9946 11:03:53.674730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9947 11:03:53.678069 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9948 11:03:53.684978 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9949 11:03:53.688255 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9950 11:03:53.691888 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9951 11:03:53.698090 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9952 11:03:53.701397 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9953 11:03:53.705114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9954 11:03:53.711763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9955 11:03:53.715126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9956 11:03:53.721348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9957 11:03:53.724670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9958 11:03:53.731558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9959 11:03:53.734659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9960 11:03:53.741488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9961 11:03:53.744735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9962 11:03:53.751458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9963 11:03:53.754242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9964 11:03:53.761216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9965 11:03:53.764245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9966 11:03:53.771004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9967 11:03:53.774403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9968 11:03:53.781197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9969 11:03:53.784445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9970 11:03:53.791190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9971 11:03:53.794434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9972 11:03:53.800872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9973 11:03:53.804324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9974 11:03:53.811075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9975 11:03:53.814271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9976 11:03:53.821157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9977 11:03:53.824280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9978 11:03:53.831203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9979 11:03:53.834501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9980 11:03:53.840978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9981 11:03:53.844616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9982 11:03:53.851228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9983 11:03:53.854462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9984 11:03:53.857730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9985 11:03:53.864450 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9986 11:03:53.864547 INFO: [APUAPC] vio 0
9987 11:03:53.871865 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9988 11:03:53.875207 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9989 11:03:53.878257 INFO: [APUAPC] D0_APC_0: 0x400510
9990 11:03:53.881530 INFO: [APUAPC] D0_APC_1: 0x0
9991 11:03:53.884899 INFO: [APUAPC] D0_APC_2: 0x1540
9992 11:03:53.888277 INFO: [APUAPC] D0_APC_3: 0x0
9993 11:03:53.891529 INFO: [APUAPC] D1_APC_0: 0xffffffff
9994 11:03:53.894858 INFO: [APUAPC] D1_APC_1: 0xffffffff
9995 11:03:53.898108 INFO: [APUAPC] D1_APC_2: 0x3fffff
9996 11:03:53.901375 INFO: [APUAPC] D1_APC_3: 0x0
9997 11:03:53.905048 INFO: [APUAPC] D2_APC_0: 0xffffffff
9998 11:03:53.908254 INFO: [APUAPC] D2_APC_1: 0xffffffff
9999 11:03:53.911569 INFO: [APUAPC] D2_APC_2: 0x3fffff
10000 11:03:53.914669 INFO: [APUAPC] D2_APC_3: 0x0
10001 11:03:53.918251 INFO: [APUAPC] D3_APC_0: 0xffffffff
10002 11:03:53.921421 INFO: [APUAPC] D3_APC_1: 0xffffffff
10003 11:03:53.925074 INFO: [APUAPC] D3_APC_2: 0x3fffff
10004 11:03:53.925204 INFO: [APUAPC] D3_APC_3: 0x0
10005 11:03:53.931304 INFO: [APUAPC] D4_APC_0: 0xffffffff
10006 11:03:53.934955 INFO: [APUAPC] D4_APC_1: 0xffffffff
10007 11:03:53.938220 INFO: [APUAPC] D4_APC_2: 0x3fffff
10008 11:03:53.938316 INFO: [APUAPC] D4_APC_3: 0x0
10009 11:03:53.941735 INFO: [APUAPC] D5_APC_0: 0xffffffff
10010 11:03:53.945029 INFO: [APUAPC] D5_APC_1: 0xffffffff
10011 11:03:53.948278 INFO: [APUAPC] D5_APC_2: 0x3fffff
10012 11:03:53.951533 INFO: [APUAPC] D5_APC_3: 0x0
10013 11:03:53.954777 INFO: [APUAPC] D6_APC_0: 0xffffffff
10014 11:03:53.958118 INFO: [APUAPC] D6_APC_1: 0xffffffff
10015 11:03:53.961572 INFO: [APUAPC] D6_APC_2: 0x3fffff
10016 11:03:53.965033 INFO: [APUAPC] D6_APC_3: 0x0
10017 11:03:53.968189 INFO: [APUAPC] D7_APC_0: 0xffffffff
10018 11:03:53.971440 INFO: [APUAPC] D7_APC_1: 0xffffffff
10019 11:03:53.974860 INFO: [APUAPC] D7_APC_2: 0x3fffff
10020 11:03:53.978086 INFO: [APUAPC] D7_APC_3: 0x0
10021 11:03:53.981673 INFO: [APUAPC] D8_APC_0: 0xffffffff
10022 11:03:53.984748 INFO: [APUAPC] D8_APC_1: 0xffffffff
10023 11:03:53.988305 INFO: [APUAPC] D8_APC_2: 0x3fffff
10024 11:03:53.991535 INFO: [APUAPC] D8_APC_3: 0x0
10025 11:03:53.994990 INFO: [APUAPC] D9_APC_0: 0xffffffff
10026 11:03:53.998248 INFO: [APUAPC] D9_APC_1: 0xffffffff
10027 11:03:54.001706 INFO: [APUAPC] D9_APC_2: 0x3fffff
10028 11:03:54.004951 INFO: [APUAPC] D9_APC_3: 0x0
10029 11:03:54.008347 INFO: [APUAPC] D10_APC_0: 0xffffffff
10030 11:03:54.011570 INFO: [APUAPC] D10_APC_1: 0xffffffff
10031 11:03:54.014737 INFO: [APUAPC] D10_APC_2: 0x3fffff
10032 11:03:54.018010 INFO: [APUAPC] D10_APC_3: 0x0
10033 11:03:54.021639 INFO: [APUAPC] D11_APC_0: 0xffffffff
10034 11:03:54.024827 INFO: [APUAPC] D11_APC_1: 0xffffffff
10035 11:03:54.027858 INFO: [APUAPC] D11_APC_2: 0x3fffff
10036 11:03:54.031294 INFO: [APUAPC] D11_APC_3: 0x0
10037 11:03:54.034744 INFO: [APUAPC] D12_APC_0: 0xffffffff
10038 11:03:54.037975 INFO: [APUAPC] D12_APC_1: 0xffffffff
10039 11:03:54.041269 INFO: [APUAPC] D12_APC_2: 0x3fffff
10040 11:03:54.044992 INFO: [APUAPC] D12_APC_3: 0x0
10041 11:03:54.048230 INFO: [APUAPC] D13_APC_0: 0xffffffff
10042 11:03:54.051524 INFO: [APUAPC] D13_APC_1: 0xffffffff
10043 11:03:54.054689 INFO: [APUAPC] D13_APC_2: 0x3fffff
10044 11:03:54.057950 INFO: [APUAPC] D13_APC_3: 0x0
10045 11:03:54.061581 INFO: [APUAPC] D14_APC_0: 0xffffffff
10046 11:03:54.064780 INFO: [APUAPC] D14_APC_1: 0xffffffff
10047 11:03:54.068026 INFO: [APUAPC] D14_APC_2: 0x3fffff
10048 11:03:54.071309 INFO: [APUAPC] D14_APC_3: 0x0
10049 11:03:54.074863 INFO: [APUAPC] D15_APC_0: 0xffffffff
10050 11:03:54.077914 INFO: [APUAPC] D15_APC_1: 0xffffffff
10051 11:03:54.081353 INFO: [APUAPC] D15_APC_2: 0x3fffff
10052 11:03:54.085034 INFO: [APUAPC] D15_APC_3: 0x0
10053 11:03:54.088133 INFO: [APUAPC] APC_CON: 0x4
10054 11:03:54.091671 INFO: [NOCDAPC] D0_APC_0: 0x0
10055 11:03:54.094686 INFO: [NOCDAPC] D0_APC_1: 0x0
10056 11:03:54.094775 INFO: [NOCDAPC] D1_APC_0: 0x0
10057 11:03:54.098275 INFO: [NOCDAPC] D1_APC_1: 0xfff
10058 11:03:54.101395 INFO: [NOCDAPC] D2_APC_0: 0x0
10059 11:03:54.104945 INFO: [NOCDAPC] D2_APC_1: 0xfff
10060 11:03:54.108316 INFO: [NOCDAPC] D3_APC_0: 0x0
10061 11:03:54.111482 INFO: [NOCDAPC] D3_APC_1: 0xfff
10062 11:03:54.114822 INFO: [NOCDAPC] D4_APC_0: 0x0
10063 11:03:54.118126 INFO: [NOCDAPC] D4_APC_1: 0xfff
10064 11:03:54.121737 INFO: [NOCDAPC] D5_APC_0: 0x0
10065 11:03:54.125054 INFO: [NOCDAPC] D5_APC_1: 0xfff
10066 11:03:54.125195 INFO: [NOCDAPC] D6_APC_0: 0x0
10067 11:03:54.128284 INFO: [NOCDAPC] D6_APC_1: 0xfff
10068 11:03:54.131927 INFO: [NOCDAPC] D7_APC_0: 0x0
10069 11:03:54.135162 INFO: [NOCDAPC] D7_APC_1: 0xfff
10070 11:03:54.138281 INFO: [NOCDAPC] D8_APC_0: 0x0
10071 11:03:54.141528 INFO: [NOCDAPC] D8_APC_1: 0xfff
10072 11:03:54.145201 INFO: [NOCDAPC] D9_APC_0: 0x0
10073 11:03:54.148104 INFO: [NOCDAPC] D9_APC_1: 0xfff
10074 11:03:54.151562 INFO: [NOCDAPC] D10_APC_0: 0x0
10075 11:03:54.154901 INFO: [NOCDAPC] D10_APC_1: 0xfff
10076 11:03:54.158191 INFO: [NOCDAPC] D11_APC_0: 0x0
10077 11:03:54.161746 INFO: [NOCDAPC] D11_APC_1: 0xfff
10078 11:03:54.161836 INFO: [NOCDAPC] D12_APC_0: 0x0
10079 11:03:54.165007 INFO: [NOCDAPC] D12_APC_1: 0xfff
10080 11:03:54.168258 INFO: [NOCDAPC] D13_APC_0: 0x0
10081 11:03:54.171754 INFO: [NOCDAPC] D13_APC_1: 0xfff
10082 11:03:54.174890 INFO: [NOCDAPC] D14_APC_0: 0x0
10083 11:03:54.178156 INFO: [NOCDAPC] D14_APC_1: 0xfff
10084 11:03:54.181567 INFO: [NOCDAPC] D15_APC_0: 0x0
10085 11:03:54.185240 INFO: [NOCDAPC] D15_APC_1: 0xfff
10086 11:03:54.188063 INFO: [NOCDAPC] APC_CON: 0x4
10087 11:03:54.191690 INFO: [APUAPC] set_apusys_apc done
10088 11:03:54.194796 INFO: [DEVAPC] devapc_init done
10089 11:03:54.198242 INFO: GICv3 without legacy support detected.
10090 11:03:54.201573 INFO: ARM GICv3 driver initialized in EL3
10091 11:03:54.204723 INFO: Maximum SPI INTID supported: 639
10092 11:03:54.211629 INFO: BL31: Initializing runtime services
10093 11:03:54.214949 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10094 11:03:54.218260 INFO: SPM: enable CPC mode
10095 11:03:54.224650 INFO: mcdi ready for mcusys-off-idle and system suspend
10096 11:03:54.227965 INFO: BL31: Preparing for EL3 exit to normal world
10097 11:03:54.231325 INFO: Entry point address = 0x80000000
10098 11:03:54.234759 INFO: SPSR = 0x8
10099 11:03:54.239878
10100 11:03:54.239973
10101 11:03:54.240062
10102 11:03:54.243183 Starting depthcharge on Spherion...
10103 11:03:54.243271
10104 11:03:54.243356 Wipe memory regions:
10105 11:03:54.243434
10106 11:03:54.244254 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10107 11:03:54.244348 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10108 11:03:54.244421 Setting prompt string to ['asurada:']
10109 11:03:54.244491 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10110 11:03:54.246528 [0x00000040000000, 0x00000054600000)
10111 11:03:54.368506
10112 11:03:54.368632 [0x00000054660000, 0x00000080000000)
10113 11:03:54.629385
10114 11:03:54.629522 [0x000000821a7280, 0x000000ffe64000)
10115 11:03:55.373972
10116 11:03:55.374088 [0x00000100000000, 0x00000240000000)
10117 11:03:57.263836
10118 11:03:57.267178 Initializing XHCI USB controller at 0x11200000.
10119 11:03:58.305262
10120 11:03:58.308574 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10121 11:03:58.308652
10122 11:03:58.308711
10123 11:03:58.308971 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 11:03:58.309042 Sending line: 'tftpboot 192.168.201.1 14786811/tftp-deploy-ta6ugt5m/kernel/image.itb 14786811/tftp-deploy-ta6ugt5m/kernel/cmdline '
10126 11:03:58.409460 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 11:03:58.409552 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10128 11:03:58.413451 asurada: tftpboot 192.168.201.1 14786811/tftp-deploy-ta6ugt5m/kernel/image.itp-deploy-ta6ugt5m/kernel/cmdline
10129 11:03:58.413531
10130 11:03:58.413593 Waiting for link
10131 11:03:58.572167
10132 11:03:58.572283 R8152: Initializing
10133 11:03:58.572366
10134 11:03:58.575033 Version 9 (ocp_data = 6010)
10135 11:03:58.575124
10136 11:03:58.578370 R8152: Done initializing
10137 11:03:58.578456
10138 11:03:58.578537 Adding net device
10139 11:04:00.453404
10140 11:04:00.453519 done.
10141 11:04:00.453580
10142 11:04:00.453637 MAC: 00:e0:4c:72:2d:d6
10143 11:04:00.453690
10144 11:04:00.456561 Sending DHCP discover... done.
10145 11:04:00.456650
10146 11:04:00.460047 Waiting for reply... done.
10147 11:04:00.460133
10148 11:04:00.463247 Sending DHCP request... done.
10149 11:04:00.463336
10150 11:04:00.463418 Waiting for reply... done.
10151 11:04:00.463496
10152 11:04:00.466512 My ip is 192.168.201.21
10153 11:04:00.466608
10154 11:04:00.469635 The DHCP server ip is 192.168.201.1
10155 11:04:00.469726
10156 11:04:00.473117 TFTP server IP predefined by user: 192.168.201.1
10157 11:04:00.473240
10158 11:04:00.479621 Bootfile predefined by user: 14786811/tftp-deploy-ta6ugt5m/kernel/image.itb
10159 11:04:00.479734
10160 11:04:00.483146 Sending tftp read request... done.
10161 11:04:00.483251
10162 11:04:00.486461 Waiting for the transfer...
10163 11:04:00.486574
10164 11:04:00.755706 00000000 ################################################################
10165 11:04:00.755846
10166 11:04:01.007413 00080000 ################################################################
10167 11:04:01.007549
10168 11:04:01.264840 00100000 ################################################################
10169 11:04:01.264965
10170 11:04:01.523461 00180000 ################################################################
10171 11:04:01.523664
10172 11:04:01.776520 00200000 ################################################################
10173 11:04:01.776662
10174 11:04:02.029640 00280000 ################################################################
10175 11:04:02.029789
10176 11:04:02.282341 00300000 ################################################################
10177 11:04:02.282467
10178 11:04:02.544901 00380000 ################################################################
10179 11:04:02.545023
10180 11:04:02.796587 00400000 ################################################################
10181 11:04:02.796717
10182 11:04:03.056848 00480000 ################################################################
10183 11:04:03.056990
10184 11:04:03.309448 00500000 ################################################################
10185 11:04:03.309570
10186 11:04:03.560689 00580000 ################################################################
10187 11:04:03.560811
10188 11:04:03.818270 00600000 ################################################################
10189 11:04:03.818393
10190 11:04:04.089671 00680000 ################################################################
10191 11:04:04.089791
10192 11:04:04.355669 00700000 ################################################################
10193 11:04:04.355786
10194 11:04:04.621267 00780000 ################################################################
10195 11:04:04.621371
10196 11:04:04.902933 00800000 ################################################################
10197 11:04:04.903047
10198 11:04:05.197429 00880000 ################################################################
10199 11:04:05.197545
10200 11:04:05.488954 00900000 ################################################################
10201 11:04:05.489095
10202 11:04:05.765543 00980000 ################################################################
10203 11:04:05.765677
10204 11:04:06.034075 00a00000 ################################################################
10205 11:04:06.034185
10206 11:04:06.290230 00a80000 ################################################################
10207 11:04:06.290353
10208 11:04:06.562753 00b00000 ################################################################
10209 11:04:06.562861
10210 11:04:06.830067 00b80000 ################################################################
10211 11:04:06.830183
10212 11:04:07.083224 00c00000 ################################################################
10213 11:04:07.083332
10214 11:04:07.331712 00c80000 ################################################################
10215 11:04:07.331825
10216 11:04:07.587921 00d00000 ################################################################
10217 11:04:07.588027
10218 11:04:07.848297 00d80000 ################################################################
10219 11:04:07.848412
10220 11:04:08.106959 00e00000 ################################################################
10221 11:04:08.107068
10222 11:04:08.358381 00e80000 ################################################################
10223 11:04:08.358515
10224 11:04:08.610297 00f00000 ################################################################
10225 11:04:08.610428
10226 11:04:08.861609 00f80000 ################################################################
10227 11:04:08.861720
10228 11:04:09.126784 01000000 ################################################################
10229 11:04:09.126934
10230 11:04:09.382143 01080000 ################################################################
10231 11:04:09.382290
10232 11:04:09.651505 01100000 ################################################################
10233 11:04:09.651657
10234 11:04:09.920635 01180000 ################################################################
10235 11:04:09.920767
10236 11:04:10.222707 01200000 ################################################################
10237 11:04:10.222853
10238 11:04:10.535762 01280000 ################################################################
10239 11:04:10.535874
10240 11:04:10.836167 01300000 ################################################################
10241 11:04:10.836319
10242 11:04:11.127131 01380000 ################################################################
10243 11:04:11.127258
10244 11:04:11.395086 01400000 ################################################################
10245 11:04:11.395227
10246 11:04:11.658674 01480000 ################################################################
10247 11:04:11.658797
10248 11:04:11.919117 01500000 ################################################################
10249 11:04:11.919224
10250 11:04:12.177447 01580000 ################################################################
10251 11:04:12.177563
10252 11:04:12.434882 01600000 ################################################################
10253 11:04:12.434995
10254 11:04:12.689820 01680000 ################################################################
10255 11:04:12.689937
10256 11:04:12.948566 01700000 ################################################################
10257 11:04:12.948674
10258 11:04:13.219229 01780000 ################################################################
10259 11:04:13.219345
10260 11:04:13.481359 01800000 ################################################################
10261 11:04:13.481470
10262 11:04:13.734103 01880000 ################################################################
10263 11:04:13.734217
10264 11:04:13.988973 01900000 ################################################################
10265 11:04:13.989090
10266 11:04:14.239289 01980000 ################################################################
10267 11:04:14.239422
10268 11:04:14.510911 01a00000 ################################################################
10269 11:04:14.511024
10270 11:04:14.764180 01a80000 ################################################################
10271 11:04:14.764301
10272 11:04:15.030540 01b00000 ################################################################
10273 11:04:15.030658
10274 11:04:15.290720 01b80000 ################################################################
10275 11:04:15.290835
10276 11:04:15.561420 01c00000 ################################################################
10277 11:04:15.561537
10278 11:04:15.819903 01c80000 ################################################################
10279 11:04:15.820036
10280 11:04:16.093577 01d00000 ################################################################
10281 11:04:16.093693
10282 11:04:16.357531 01d80000 ################################################################
10283 11:04:16.357647
10284 11:04:16.578882 01e00000 ################################################### done.
10285 11:04:16.579323
10286 11:04:16.582327 The bootfile was 31873262 bytes long.
10287 11:04:16.582762
10288 11:04:16.585474 Sending tftp read request... done.
10289 11:04:16.585905
10290 11:04:16.590126 Waiting for the transfer...
10291 11:04:16.590711
10292 11:04:16.591056 00000000 # done.
10293 11:04:16.591383
10294 11:04:16.596767 Command line loaded dynamically from TFTP file: 14786811/tftp-deploy-ta6ugt5m/kernel/cmdline
10295 11:04:16.599734
10296 11:04:16.619815 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786811/extract-nfsrootfs-8vk9jkqc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10297 11:04:16.619917
10298 11:04:16.619988 Loading FIT.
10299 11:04:16.622819
10300 11:04:16.622908 Image ramdisk-1 has 18707718 bytes.
10301 11:04:16.622978
10302 11:04:16.626380 Image fdt-1 has 47258 bytes.
10303 11:04:16.626539
10304 11:04:16.629890 Image kernel-1 has 13116259 bytes.
10305 11:04:16.630059
10306 11:04:16.639526 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10307 11:04:16.639719
10308 11:04:16.656069 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10309 11:04:16.656431
10310 11:04:16.662500 Choosing best match conf-1 for compat google,spherion-rev2.
10311 11:04:16.666281
10312 11:04:16.670819 Connected to device vid:did:rid of 1ae0:0028:00
10313 11:04:16.677890
10314 11:04:16.681013 tpm_get_response: command 0x17b, return code 0x0
10315 11:04:16.681496
10316 11:04:16.687717 ec_init: CrosEC protocol v3 supported (256, 248)
10317 11:04:16.688277
10318 11:04:16.691044 tpm_cleanup: add release locality here.
10319 11:04:16.691593
10320 11:04:16.694559 Shutting down all USB controllers.
10321 11:04:16.694986
10322 11:04:16.697901 Removing current net device
10323 11:04:16.698334
10324 11:04:16.704462 Exiting depthcharge with code 4 at timestamp: 51772604
10325 11:04:16.704895
10326 11:04:16.707916 LZMA decompressing kernel-1 to 0x821a6718
10327 11:04:16.708347
10328 11:04:16.710890 LZMA decompressing kernel-1 to 0x40000000
10329 11:04:18.326839
10330 11:04:18.327317 jumping to kernel
10331 11:04:18.329076 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10332 11:04:18.329602 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10333 11:04:18.329967 Setting prompt string to ['Linux version [0-9]']
10334 11:04:18.330318 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10335 11:04:18.330667 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10336 11:04:18.407736
10337 11:04:18.411073 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10338 11:04:18.414551 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10339 11:04:18.415001 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10340 11:04:18.415339 Setting prompt string to []
10341 11:04:18.415698 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10342 11:04:18.416198 Using line separator: #'\n'#
10343 11:04:18.416676 No login prompt set.
10344 11:04:18.417107 Parsing kernel messages
10345 11:04:18.417516 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10346 11:04:18.418027 [login-action] Waiting for messages, (timeout 00:03:56)
10347 11:04:18.418366 Waiting using forced prompt support (timeout 00:01:58)
10348 11:04:18.434094 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10349 11:04:18.437251 [ 0.000000] random: crng init done
10350 11:04:18.440986 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10351 11:04:18.444045 [ 0.000000] efi: UEFI not found.
10352 11:04:18.453362 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10353 11:04:18.460261 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10354 11:04:18.470114 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10355 11:04:18.480038 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10356 11:04:18.486611 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10357 11:04:18.489909 [ 0.000000] printk: bootconsole [mtk8250] enabled
10358 11:04:18.498365 [ 0.000000] NUMA: No NUMA configuration found
10359 11:04:18.504903 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10360 11:04:18.511157 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10361 11:04:18.511234 [ 0.000000] Zone ranges:
10362 11:04:18.517934 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10363 11:04:18.521042 [ 0.000000] DMA32 empty
10364 11:04:18.527815 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10365 11:04:18.530973 [ 0.000000] Movable zone start for each node
10366 11:04:18.534370 [ 0.000000] Early memory node ranges
10367 11:04:18.540885 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10368 11:04:18.547777 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10369 11:04:18.553991 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10370 11:04:18.560772 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10371 11:04:18.567232 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10372 11:04:18.573640 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10373 11:04:18.631899 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10374 11:04:18.638640 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10375 11:04:18.645167 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10376 11:04:18.648397 [ 0.000000] psci: probing for conduit method from DT.
10377 11:04:18.654792 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10378 11:04:18.658022 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10379 11:04:18.664792 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10380 11:04:18.668111 [ 0.000000] psci: SMC Calling Convention v1.2
10381 11:04:18.674821 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10382 11:04:18.678422 [ 0.000000] Detected VIPT I-cache on CPU0
10383 11:04:18.684728 [ 0.000000] CPU features: detected: GIC system register CPU interface
10384 11:04:18.691486 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10385 11:04:18.698143 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10386 11:04:18.704554 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10387 11:04:18.714632 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10388 11:04:18.721568 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10389 11:04:18.724696 [ 0.000000] alternatives: applying boot alternatives
10390 11:04:18.731224 [ 0.000000] Fallback order for Node 0: 0
10391 11:04:18.737862 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10392 11:04:18.741050 [ 0.000000] Policy zone: Normal
10393 11:04:18.764215 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786811/extract-nfsrootfs-8vk9jkqc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10394 11:04:18.774031 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10395 11:04:18.785328 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10396 11:04:18.795543 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10397 11:04:18.802154 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10398 11:04:18.804865 <6>[ 0.000000] software IO TLB: area num 8.
10399 11:04:18.862031 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10400 11:04:19.011932 <6>[ 0.000000] Memory: 7945788K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406980K reserved, 32768K cma-reserved)
10401 11:04:19.018530 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10402 11:04:19.024817 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10403 11:04:19.028137 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10404 11:04:19.035021 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10405 11:04:19.041190 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10406 11:04:19.047764 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10407 11:04:19.054594 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10408 11:04:19.060929 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10409 11:04:19.067761 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10410 11:04:19.074184 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10411 11:04:19.077240 <6>[ 0.000000] GICv3: 608 SPIs implemented
10412 11:04:19.080521 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10413 11:04:19.087362 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10414 11:04:19.090774 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10415 11:04:19.097498 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10416 11:04:19.110327 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10417 11:04:19.123325 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10418 11:04:19.130276 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10419 11:04:19.138544 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10420 11:04:19.151813 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10421 11:04:19.158073 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10422 11:04:19.165079 <6>[ 0.009179] Console: colour dummy device 80x25
10423 11:04:19.174662 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10424 11:04:19.181629 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10425 11:04:19.184742 <6>[ 0.029224] LSM: Security Framework initializing
10426 11:04:19.191534 <6>[ 0.034161] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 11:04:19.201345 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10428 11:04:19.208033 <6>[ 0.051396] cblist_init_generic: Setting adjustable number of callback queues.
10429 11:04:19.214244 <6>[ 0.058884] cblist_init_generic: Setting shift to 3 and lim to 1.
10430 11:04:19.224182 <6>[ 0.065224] cblist_init_generic: Setting adjustable number of callback queues.
10431 11:04:19.230978 <6>[ 0.072650] cblist_init_generic: Setting shift to 3 and lim to 1.
10432 11:04:19.234409 <6>[ 0.079051] rcu: Hierarchical SRCU implementation.
10433 11:04:19.240940 <6>[ 0.084066] rcu: Max phase no-delay instances is 1000.
10434 11:04:19.247558 <6>[ 0.091094] EFI services will not be available.
10435 11:04:19.251194 <6>[ 0.096052] smp: Bringing up secondary CPUs ...
10436 11:04:19.259146 <6>[ 0.101137] Detected VIPT I-cache on CPU1
10437 11:04:19.265867 <6>[ 0.101207] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10438 11:04:19.272432 <6>[ 0.101237] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10439 11:04:19.275885 <6>[ 0.101581] Detected VIPT I-cache on CPU2
10440 11:04:19.282306 <6>[ 0.101636] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10441 11:04:19.291837 <6>[ 0.101656] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10442 11:04:19.295253 <6>[ 0.101921] Detected VIPT I-cache on CPU3
10443 11:04:19.301921 <6>[ 0.101970] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10444 11:04:19.308437 <6>[ 0.101984] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10445 11:04:19.311864 <6>[ 0.102293] CPU features: detected: Spectre-v4
10446 11:04:19.318547 <6>[ 0.102298] CPU features: detected: Spectre-BHB
10447 11:04:19.322073 <6>[ 0.102304] Detected PIPT I-cache on CPU4
10448 11:04:19.328410 <6>[ 0.102367] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10449 11:04:19.334781 <6>[ 0.102384] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10450 11:04:19.341844 <6>[ 0.102680] Detected PIPT I-cache on CPU5
10451 11:04:19.348283 <6>[ 0.102736] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10452 11:04:19.354798 <6>[ 0.102752] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10453 11:04:19.358121 <6>[ 0.103021] Detected PIPT I-cache on CPU6
10454 11:04:19.365044 <6>[ 0.103080] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10455 11:04:19.371484 <6>[ 0.103095] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10456 11:04:19.378376 <6>[ 0.103394] Detected PIPT I-cache on CPU7
10457 11:04:19.384520 <6>[ 0.103463] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10458 11:04:19.391329 <6>[ 0.103479] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10459 11:04:19.394528 <6>[ 0.103527] smp: Brought up 1 node, 8 CPUs
10460 11:04:19.401281 <6>[ 0.244822] SMP: Total of 8 processors activated.
10461 11:04:19.404572 <6>[ 0.249743] CPU features: detected: 32-bit EL0 Support
10462 11:04:19.414840 <6>[ 0.255106] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10463 11:04:19.421021 <6>[ 0.263906] CPU features: detected: Common not Private translations
10464 11:04:19.427546 <6>[ 0.270422] CPU features: detected: CRC32 instructions
10465 11:04:19.430827 <6>[ 0.275807] CPU features: detected: RCpc load-acquire (LDAPR)
10466 11:04:19.437580 <6>[ 0.281767] CPU features: detected: LSE atomic instructions
10467 11:04:19.444041 <6>[ 0.287549] CPU features: detected: Privileged Access Never
10468 11:04:19.450441 <6>[ 0.293364] CPU features: detected: RAS Extension Support
10469 11:04:19.456998 <6>[ 0.298972] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10470 11:04:19.460359 <6>[ 0.306194] CPU: All CPU(s) started at EL2
10471 11:04:19.466935 <6>[ 0.310511] alternatives: applying system-wide alternatives
10472 11:04:19.476737 <6>[ 0.321397] devtmpfs: initialized
10473 11:04:19.492297 <6>[ 0.330298] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10474 11:04:19.498887 <6>[ 0.340261] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10475 11:04:19.505474 <6>[ 0.348500] pinctrl core: initialized pinctrl subsystem
10476 11:04:19.508888 <6>[ 0.355169] DMI not present or invalid.
10477 11:04:19.515258 <6>[ 0.359581] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10478 11:04:19.525387 <6>[ 0.366478] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10479 11:04:19.532089 <6>[ 0.374065] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10480 11:04:19.541884 <6>[ 0.382296] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10481 11:04:19.545044 <6>[ 0.390538] audit: initializing netlink subsys (disabled)
10482 11:04:19.555146 <5>[ 0.396229] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10483 11:04:19.561970 <6>[ 0.396938] thermal_sys: Registered thermal governor 'step_wise'
10484 11:04:19.568220 <6>[ 0.404197] thermal_sys: Registered thermal governor 'power_allocator'
10485 11:04:19.571534 <6>[ 0.410451] cpuidle: using governor menu
10486 11:04:19.578289 <6>[ 0.421406] NET: Registered PF_QIPCRTR protocol family
10487 11:04:19.584672 <6>[ 0.426916] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10488 11:04:19.591416 <6>[ 0.434021] ASID allocator initialised with 32768 entries
10489 11:04:19.594612 <6>[ 0.440608] Serial: AMBA PL011 UART driver
10490 11:04:19.605540 <4>[ 0.449960] Trying to register duplicate clock ID: 134
10491 11:04:19.663774 <6>[ 0.511442] KASLR enabled
10492 11:04:19.678223 <6>[ 0.519144] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10493 11:04:19.684637 <6>[ 0.526157] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10494 11:04:19.691146 <6>[ 0.532646] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10495 11:04:19.697913 <6>[ 0.539652] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10496 11:04:19.704739 <6>[ 0.546138] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10497 11:04:19.710936 <6>[ 0.553141] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10498 11:04:19.717461 <6>[ 0.559625] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10499 11:04:19.724168 <6>[ 0.566628] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10500 11:04:19.727365 <6>[ 0.574159] ACPI: Interpreter disabled.
10501 11:04:19.736097 <6>[ 0.580610] iommu: Default domain type: Translated
10502 11:04:19.742753 <6>[ 0.585719] iommu: DMA domain TLB invalidation policy: strict mode
10503 11:04:19.746408 <5>[ 0.592369] SCSI subsystem initialized
10504 11:04:19.752729 <6>[ 0.596535] usbcore: registered new interface driver usbfs
10505 11:04:19.759401 <6>[ 0.602264] usbcore: registered new interface driver hub
10506 11:04:19.762468 <6>[ 0.607815] usbcore: registered new device driver usb
10507 11:04:19.769981 <6>[ 0.613922] pps_core: LinuxPPS API ver. 1 registered
10508 11:04:19.779470 <6>[ 0.619114] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10509 11:04:19.782755 <6>[ 0.628455] PTP clock support registered
10510 11:04:19.785946 <6>[ 0.632697] EDAC MC: Ver: 3.0.0
10511 11:04:19.793619 <6>[ 0.637859] FPGA manager framework
10512 11:04:19.800654 <6>[ 0.641544] Advanced Linux Sound Architecture Driver Initialized.
10513 11:04:19.803672 <6>[ 0.648340] vgaarb: loaded
10514 11:04:19.809762 <6>[ 0.651514] clocksource: Switched to clocksource arch_sys_counter
10515 11:04:19.813178 <5>[ 0.657958] VFS: Disk quotas dquot_6.6.0
10516 11:04:19.819847 <6>[ 0.662144] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10517 11:04:19.823020 <6>[ 0.669332] pnp: PnP ACPI: disabled
10518 11:04:19.831605 <6>[ 0.676047] NET: Registered PF_INET protocol family
10519 11:04:19.841522 <6>[ 0.681634] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10520 11:04:19.852816 <6>[ 0.693942] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10521 11:04:19.862870 <6>[ 0.702757] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10522 11:04:19.869569 <6>[ 0.710730] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10523 11:04:19.876203 <6>[ 0.719430] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10524 11:04:19.888294 <6>[ 0.729187] TCP: Hash tables configured (established 65536 bind 65536)
10525 11:04:19.895115 <6>[ 0.736053] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 11:04:19.901697 <6>[ 0.743250] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10527 11:04:19.908084 <6>[ 0.750954] NET: Registered PF_UNIX/PF_LOCAL protocol family
10528 11:04:19.914800 <6>[ 0.757106] RPC: Registered named UNIX socket transport module.
10529 11:04:19.917871 <6>[ 0.763256] RPC: Registered udp transport module.
10530 11:04:19.924792 <6>[ 0.768189] RPC: Registered tcp transport module.
10531 11:04:19.930930 <6>[ 0.773121] RPC: Registered tcp NFSv4.1 backchannel transport module.
10532 11:04:19.934651 <6>[ 0.779790] PCI: CLS 0 bytes, default 64
10533 11:04:19.937763 <6>[ 0.784159] Unpacking initramfs...
10534 11:04:19.947658 <6>[ 0.788287] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10535 11:04:19.954481 <6>[ 0.796918] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10536 11:04:19.961321 <6>[ 0.805731] kvm [1]: IPA Size Limit: 40 bits
10537 11:04:19.964446 <6>[ 0.810256] kvm [1]: GICv3: no GICV resource entry
10538 11:04:19.971153 <6>[ 0.815275] kvm [1]: disabling GICv2 emulation
10539 11:04:19.977846 <6>[ 0.819956] kvm [1]: GIC system register CPU interface enabled
10540 11:04:19.981330 <6>[ 0.826122] kvm [1]: vgic interrupt IRQ18
10541 11:04:19.987954 <6>[ 0.831553] kvm [1]: VHE mode initialized successfully
10542 11:04:19.994534 <5>[ 0.837927] Initialise system trusted keyrings
10543 11:04:20.000708 <6>[ 0.842736] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10544 11:04:20.008485 <6>[ 0.852740] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10545 11:04:20.015208 <5>[ 0.859131] NFS: Registering the id_resolver key type
10546 11:04:20.018401 <5>[ 0.864428] Key type id_resolver registered
10547 11:04:20.025169 <5>[ 0.868840] Key type id_legacy registered
10548 11:04:20.031982 <6>[ 0.873115] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10549 11:04:20.038203 <6>[ 0.880038] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10550 11:04:20.045098 <6>[ 0.887739] 9p: Installing v9fs 9p2000 file system support
10551 11:04:20.082133 <5>[ 0.926295] Key type asymmetric registered
10552 11:04:20.085726 <5>[ 0.930626] Asymmetric key parser 'x509' registered
10553 11:04:20.095163 <6>[ 0.935766] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10554 11:04:20.098550 <6>[ 0.943384] io scheduler mq-deadline registered
10555 11:04:20.101801 <6>[ 0.948170] io scheduler kyber registered
10556 11:04:20.121021 <6>[ 0.965374] EINJ: ACPI disabled.
10557 11:04:20.153542 <4>[ 0.991318] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 11:04:20.163665 <4>[ 1.001941] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 11:04:20.178847 <6>[ 1.023092] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10560 11:04:20.186710 <6>[ 1.031076] printk: console [ttyS0] disabled
10561 11:04:20.214372 <6>[ 1.055721] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10562 11:04:20.220992 <6>[ 1.065195] printk: console [ttyS0] enabled
10563 11:04:20.224502 <6>[ 1.065195] printk: console [ttyS0] enabled
10564 11:04:20.231201 <6>[ 1.074094] printk: bootconsole [mtk8250] disabled
10565 11:04:20.234613 <6>[ 1.074094] printk: bootconsole [mtk8250] disabled
10566 11:04:20.240903 <6>[ 1.085464] SuperH (H)SCI(F) driver initialized
10567 11:04:20.244113 <6>[ 1.090754] msm_serial: driver initialized
10568 11:04:20.258576 <6>[ 1.099827] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10569 11:04:20.268714 <6>[ 1.108373] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10570 11:04:20.275674 <6>[ 1.116917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10571 11:04:20.285051 <6>[ 1.125548] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10572 11:04:20.291952 <6>[ 1.134255] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10573 11:04:20.301742 <6>[ 1.142970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10574 11:04:20.311437 <6>[ 1.151515] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10575 11:04:20.318476 <6>[ 1.160322] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10576 11:04:20.328118 <6>[ 1.168866] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10577 11:04:20.339782 <6>[ 1.184633] loop: module loaded
10578 11:04:20.346858 <6>[ 1.190578] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10579 11:04:20.369522 <4>[ 1.214130] mtk-pmic-keys: Failed to locate of_node [id: -1]
10580 11:04:20.377173 <6>[ 1.221228] megasas: 07.719.03.00-rc1
10581 11:04:20.386656 <6>[ 1.230996] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10582 11:04:20.394414 <6>[ 1.238893] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10583 11:04:20.410984 <6>[ 1.255586] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10584 11:04:20.468079 <6>[ 1.306063] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10585 11:04:20.730838 <6>[ 1.575481] Freeing initrd memory: 18268K
10586 11:04:20.742317 <6>[ 1.587121] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10587 11:04:20.753458 <6>[ 1.598243] tun: Universal TUN/TAP device driver, 1.6
10588 11:04:20.757205 <6>[ 1.604338] thunder_xcv, ver 1.0
10589 11:04:20.760490 <6>[ 1.607845] thunder_bgx, ver 1.0
10590 11:04:20.763815 <6>[ 1.611336] nicpf, ver 1.0
10591 11:04:20.774396 <6>[ 1.615380] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10592 11:04:20.777651 <6>[ 1.622855] hns3: Copyright (c) 2017 Huawei Corporation.
10593 11:04:20.781020 <6>[ 1.628442] hclge is initializing
10594 11:04:20.787437 <6>[ 1.632025] e1000: Intel(R) PRO/1000 Network Driver
10595 11:04:20.794828 <6>[ 1.637154] e1000: Copyright (c) 1999-2006 Intel Corporation.
10596 11:04:20.797251 <6>[ 1.643171] e1000e: Intel(R) PRO/1000 Network Driver
10597 11:04:20.804612 <6>[ 1.648388] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10598 11:04:20.810571 <6>[ 1.654574] igb: Intel(R) Gigabit Ethernet Network Driver
10599 11:04:20.817047 <6>[ 1.660223] igb: Copyright (c) 2007-2014 Intel Corporation.
10600 11:04:20.823967 <6>[ 1.666059] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10601 11:04:20.830513 <6>[ 1.672579] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10602 11:04:20.834009 <6>[ 1.679042] sky2: driver version 1.30
10603 11:04:20.840559 <6>[ 1.683974] usbcore: registered new device driver r8152-cfgselector
10604 11:04:20.847825 <6>[ 1.690513] usbcore: registered new interface driver r8152
10605 11:04:20.850693 <6>[ 1.696334] VFIO - User Level meta-driver version: 0.3
10606 11:04:20.860389 <6>[ 1.704587] usbcore: registered new interface driver usb-storage
10607 11:04:20.866626 <6>[ 1.711034] usbcore: registered new device driver onboard-usb-hub
10608 11:04:20.875697 <6>[ 1.720247] mt6397-rtc mt6359-rtc: registered as rtc0
10609 11:04:20.885707 <6>[ 1.725713] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:04:14 UTC (1720609454)
10610 11:04:20.888862 <6>[ 1.735282] i2c_dev: i2c /dev entries driver
10611 11:04:20.902702 <4>[ 1.747422] cpu cpu0: supply cpu not found, using dummy regulator
10612 11:04:20.909380 <4>[ 1.753846] cpu cpu1: supply cpu not found, using dummy regulator
10613 11:04:20.916294 <4>[ 1.760249] cpu cpu2: supply cpu not found, using dummy regulator
10614 11:04:20.922788 <4>[ 1.766650] cpu cpu3: supply cpu not found, using dummy regulator
10615 11:04:20.929646 <4>[ 1.773064] cpu cpu4: supply cpu not found, using dummy regulator
10616 11:04:20.936376 <4>[ 1.779462] cpu cpu5: supply cpu not found, using dummy regulator
10617 11:04:20.942932 <4>[ 1.785862] cpu cpu6: supply cpu not found, using dummy regulator
10618 11:04:20.949486 <4>[ 1.792256] cpu cpu7: supply cpu not found, using dummy regulator
10619 11:04:20.969588 <6>[ 1.813923] cpu cpu0: EM: created perf domain
10620 11:04:20.972507 <6>[ 1.818851] cpu cpu4: EM: created perf domain
10621 11:04:20.979791 <6>[ 1.824481] sdhci: Secure Digital Host Controller Interface driver
10622 11:04:20.986515 <6>[ 1.830912] sdhci: Copyright(c) Pierre Ossman
10623 11:04:20.992985 <6>[ 1.835874] Synopsys Designware Multimedia Card Interface Driver
10624 11:04:20.999655 <6>[ 1.842505] sdhci-pltfm: SDHCI platform and OF driver helper
10625 11:04:21.003291 <6>[ 1.842621] mmc0: CQHCI version 5.10
10626 11:04:21.009809 <6>[ 1.852498] ledtrig-cpu: registered to indicate activity on CPUs
10627 11:04:21.016534 <6>[ 1.859498] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10628 11:04:21.023293 <6>[ 1.866568] usbcore: registered new interface driver usbhid
10629 11:04:21.026365 <6>[ 1.872403] usbhid: USB HID core driver
10630 11:04:21.033551 <6>[ 1.876598] spi_master spi0: will run message pump with realtime priority
10631 11:04:21.076886 <6>[ 1.914694] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10632 11:04:21.095203 <6>[ 1.929722] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10633 11:04:21.098895 <3>[ 1.935613] mtk-msdc 11f60000.mmc: phase error: [map:0]
10634 11:04:21.105864 <3>[ 1.948616] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10635 11:04:21.112222 <3>[ 1.954551] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10636 11:04:21.115981 <3>[ 1.960911] mmc0: error -5 whilst initialising MMC card
10637 11:04:21.122129 <6>[ 1.961040] cros-ec-spi spi0.0: Chrome EC device registered
10638 11:04:21.144130 <6>[ 1.985315] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10639 11:04:21.151460 <6>[ 1.995944] NET: Registered PF_PACKET protocol family
10640 11:04:21.154694 <6>[ 2.001350] 9pnet: Installing 9P2000 support
10641 11:04:21.161680 <5>[ 2.005913] Key type dns_resolver registered
10642 11:04:21.164796 <6>[ 2.010933] registered taskstats version 1
10643 11:04:21.171367 <5>[ 2.015311] Loading compiled-in X.509 certificates
10644 11:04:21.200647 <4>[ 2.038437] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 11:04:21.210569 <4>[ 2.049170] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 11:04:21.227391 <6>[ 2.071849] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17814
10647 11:04:21.233990 <6>[ 2.072364] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10648 11:04:21.240852 <6>[ 2.084291] mmc0: Command Queue Engine enabled
10649 11:04:21.244091 <6>[ 2.084748] xhci-mtk 11200000.usb: xHCI Host Controller
10650 11:04:21.251029 <6>[ 2.089032] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10651 11:04:21.260732 <6>[ 2.094518] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10652 11:04:21.264104 <6>[ 2.101691] mmcblk0: mmc0:0001 DA4128 116 GiB
10653 11:04:21.274014 <6>[ 2.108940] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10654 11:04:21.280733 <6>[ 2.119981] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10655 11:04:21.283763 <6>[ 2.122887] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10656 11:04:21.290213 <6>[ 2.130310] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10657 11:04:21.297768 <6>[ 2.134829] xhci-mtk 11200000.usb: xHCI Host Controller
10658 11:04:21.300487 <6>[ 2.140639] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10659 11:04:21.307738 <6>[ 2.145466] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10660 11:04:21.317383 <6>[ 2.145477] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10661 11:04:21.324545 <6>[ 2.151381] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10662 11:04:21.327187 <6>[ 2.158634] hub 1-0:1.0: USB hub found
10663 11:04:21.330939 <6>[ 2.176179] hub 1-0:1.0: 1 port detected
10664 11:04:21.340373 <6>[ 2.180487] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10665 11:04:21.344264 <6>[ 2.189024] hub 2-0:1.0: USB hub found
10666 11:04:21.347535 <6>[ 2.193039] hub 2-0:1.0: 1 port detected
10667 11:04:21.354719 <6>[ 2.199479] mtk-msdc 11f70000.mmc: Got CD GPIO
10668 11:04:21.368162 <6>[ 2.209415] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10669 11:04:21.378092 <6>[ 2.217804] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10670 11:04:21.384601 <6>[ 2.226144] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10671 11:04:21.394412 <6>[ 2.234484] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10672 11:04:21.401086 <6>[ 2.242823] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10673 11:04:21.410950 <6>[ 2.251161] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10674 11:04:21.417763 <6>[ 2.259502] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10675 11:04:21.427911 <6>[ 2.267841] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10676 11:04:21.434285 <6>[ 2.276181] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10677 11:04:21.444318 <6>[ 2.284524] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10678 11:04:21.450895 <6>[ 2.292863] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10679 11:04:21.460879 <6>[ 2.301211] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10680 11:04:21.467739 <6>[ 2.309549] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10681 11:04:21.477283 <6>[ 2.317887] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10682 11:04:21.484457 <6>[ 2.326227] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10683 11:04:21.490955 <6>[ 2.334908] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10684 11:04:21.497586 <6>[ 2.342069] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10685 11:04:21.504308 <6>[ 2.348826] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10686 11:04:21.511145 <6>[ 2.355596] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10687 11:04:21.521183 <6>[ 2.362518] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10688 11:04:21.527734 <6>[ 2.369394] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10689 11:04:21.537924 <6>[ 2.378528] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10690 11:04:21.548403 <6>[ 2.387648] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10691 11:04:21.558379 <6>[ 2.396943] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10692 11:04:21.567433 <6>[ 2.406409] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10693 11:04:21.574014 <6>[ 2.415876] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10694 11:04:21.583986 <6>[ 2.424997] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10695 11:04:21.593966 <6>[ 2.434464] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10696 11:04:21.604037 <6>[ 2.443586] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10697 11:04:21.614495 <6>[ 2.452884] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10698 11:04:21.623819 <6>[ 2.463045] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10699 11:04:21.633720 <6>[ 2.474933] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10700 11:04:21.641680 <6>[ 2.486168] Trying to probe devices needed for running init ...
10701 11:04:21.651967 <3>[ 2.493442] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10702 11:04:21.758127 <6>[ 2.599771] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10703 11:04:21.913041 <6>[ 2.757689] hub 1-1:1.0: USB hub found
10704 11:04:21.916030 <6>[ 2.762201] hub 1-1:1.0: 4 ports detected
10705 11:04:21.928087 <6>[ 2.773058] hub 1-1:1.0: USB hub found
10706 11:04:21.931146 <6>[ 2.777514] hub 1-1:1.0: 4 ports detected
10707 11:04:22.038510 <6>[ 2.879988] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10708 11:04:22.065509 <6>[ 2.910008] hub 2-1:1.0: USB hub found
10709 11:04:22.068303 <6>[ 2.914508] hub 2-1:1.0: 3 ports detected
10710 11:04:22.079065 <6>[ 2.923807] hub 2-1:1.0: USB hub found
10711 11:04:22.082316 <6>[ 2.928251] hub 2-1:1.0: 3 ports detected
10712 11:04:22.254089 <6>[ 3.095669] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10713 11:04:22.386358 <6>[ 3.231493] hub 1-1.4:1.0: USB hub found
10714 11:04:22.389667 <6>[ 3.236089] hub 1-1.4:1.0: 2 ports detected
10715 11:04:22.401789 <6>[ 3.247064] hub 1-1.4:1.0: USB hub found
10716 11:04:22.405320 <6>[ 3.251650] hub 1-1.4:1.0: 2 ports detected
10717 11:04:22.465907 <6>[ 3.308051] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10718 11:04:22.574700 <6>[ 3.416468] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10719 11:04:22.610602 <4>[ 3.452061] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10720 11:04:22.620433 <4>[ 3.461159] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10721 11:04:22.664344 <6>[ 3.509465] r8152 2-1.3:1.0 eth0: v1.12.13
10722 11:04:22.705922 <6>[ 3.547545] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10723 11:04:22.898061 <6>[ 3.739796] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10724 11:04:24.358210 <6>[ 5.203294] r8152 2-1.3:1.0 eth0: carrier on
10725 11:04:27.006017 <5>[ 5.227632] Sending DHCP requests .., OK
10726 11:04:27.012840 <6>[ 7.856070] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10727 11:04:27.016228 <6>[ 7.864365] IP-Config: Complete:
10728 11:04:27.029338 <6>[ 7.867866] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10729 11:04:27.036145 <6>[ 7.878572] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10730 11:04:27.042667 <6>[ 7.887187] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10731 11:04:27.049543 <6>[ 7.887195] nameserver0=192.168.201.1
10732 11:04:27.052721 <6>[ 7.899353] clk: Disabling unused clocks
10733 11:04:27.059041 <6>[ 7.904895] ALSA device list:
10734 11:04:27.062368 <6>[ 7.908188] No soundcards found.
10735 11:04:27.070367 <6>[ 7.915969] Freeing unused kernel memory: 8512K
10736 11:04:27.073630 <6>[ 7.920881] Run /init as init process
10737 11:04:27.083034 Loading, please wait...
10738 11:04:27.110006 Starting systemd-udevd version 252.22-1~deb12u1
10739 11:04:27.357825 <6>[ 8.200267] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10740 11:04:27.368029 <6>[ 8.208289] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10741 11:04:27.374653 <6>[ 8.215019] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10742 11:04:27.384498 <6>[ 8.217066] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10743 11:04:27.391387 <6>[ 8.227287] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10744 11:04:27.397920 <6>[ 8.240296] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10745 11:04:27.407839 <3>[ 8.243587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:04:27.414362 <6>[ 8.249290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10747 11:04:27.417424 <6>[ 8.254926] mc: Linux media interface: v0.10
10748 11:04:27.427584 <4>[ 8.258204] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10749 11:04:27.434171 <6>[ 8.260297] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10750 11:04:27.440641 <3>[ 8.261523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:04:27.450958 <3>[ 8.261532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 11:04:27.457508 <3>[ 8.261622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 11:04:27.467237 <3>[ 8.261627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 11:04:27.474067 <3>[ 8.261634] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 11:04:27.483978 <3>[ 8.261639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 11:04:27.490417 <3>[ 8.261642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 11:04:27.500582 <3>[ 8.261672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 11:04:27.507225 <3>[ 8.261703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 11:04:27.513660 <3>[ 8.261707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 11:04:27.523266 <3>[ 8.261710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 11:04:27.530126 <3>[ 8.261734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 11:04:27.539901 <3>[ 8.261740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 11:04:27.546506 <3>[ 8.261746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 11:04:27.556506 <3>[ 8.261752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 11:04:27.563237 <3>[ 8.263060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 11:04:27.573088 <3>[ 8.263099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 11:04:27.576508 <6>[ 8.265381] remoteproc remoteproc0: scp is available
10768 11:04:27.586197 <4>[ 8.265413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10769 11:04:27.592768 <6>[ 8.266042] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10770 11:04:27.602618 <6>[ 8.266046] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10771 11:04:27.609320 <6>[ 8.266230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10772 11:04:27.619150 <6>[ 8.266242] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10773 11:04:27.625865 <6>[ 8.266247] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10774 11:04:27.635990 <6>[ 8.266252] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10775 11:04:27.642709 <4>[ 8.270141] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10776 11:04:27.649163 <6>[ 8.270556] videodev: Linux video capture interface: v2.00
10777 11:04:27.652598 <6>[ 8.277422] remoteproc remoteproc0: powering up scp
10778 11:04:27.662424 <4>[ 8.297936] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10779 11:04:27.665838 <4>[ 8.297936] Fallback method does not support PEC.
10780 11:04:27.675910 <6>[ 8.301054] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10781 11:04:27.682533 <6>[ 8.336863] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10782 11:04:27.689001 <6>[ 8.341681] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10783 11:04:27.692461 <6>[ 8.349763] pci_bus 0000:00: root bus resource [bus 00-ff]
10784 11:04:27.702141 <6>[ 8.453199] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10785 11:04:27.712145 <6>[ 8.461683] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10786 11:04:27.719072 <6>[ 8.468742] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10787 11:04:27.728916 <6>[ 8.476827] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10788 11:04:27.735552 <6>[ 8.483414] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10789 11:04:27.745396 <6>[ 8.485649] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10790 11:04:27.755017 <6>[ 8.492955] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10791 11:04:27.761816 <6>[ 8.498759] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10792 11:04:27.768218 <6>[ 8.503915] remoteproc remoteproc0: remote processor scp is now up
10793 11:04:27.774873 <6>[ 8.517546] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10794 11:04:27.778455 <6>[ 8.526590] Bluetooth: Core ver 2.22
10795 11:04:27.788392 <6>[ 8.527992] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10796 11:04:27.795189 <6>[ 8.530574] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10797 11:04:27.798341 <6>[ 8.532904] pci 0000:00:00.0: supports D1 D2
10798 11:04:27.804887 <6>[ 8.538766] NET: Registered PF_BLUETOOTH protocol family
10799 11:04:27.811297 <6>[ 8.544214] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10800 11:04:27.821139 <6>[ 8.545412] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10801 11:04:27.827845 <6>[ 8.553511] Bluetooth: HCI device and connection manager initialized
10802 11:04:27.831376 <6>[ 8.553543] Bluetooth: HCI socket layer initialized
10803 11:04:27.838033 <6>[ 8.563716] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10804 11:04:27.844464 <6>[ 8.570718] Bluetooth: L2CAP socket layer initialized
10805 11:04:27.851245 <6>[ 8.571554] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10806 11:04:27.864417 <6>[ 8.572694] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10807 11:04:27.867577 <6>[ 8.572830] usbcore: registered new interface driver uvcvideo
10808 11:04:27.877654 <6>[ 8.579782] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10809 11:04:27.881056 <6>[ 8.586793] Bluetooth: SCO socket layer initialized
10810 11:04:27.887853 <6>[ 8.587268] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10811 11:04:27.894289 <6>[ 8.596696] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10812 11:04:27.900989 <6>[ 8.650623] usbcore: registered new interface driver btusb
10813 11:04:27.910955 <4>[ 8.651211] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10814 11:04:27.917499 <3>[ 8.651224] Bluetooth: hci0: Failed to load firmware file (-2)
10815 11:04:27.923896 <3>[ 8.651229] Bluetooth: hci0: Failed to set up firmware (-2)
10816 11:04:27.934080 <4>[ 8.651234] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10817 11:04:27.940707 <6>[ 8.655767] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10818 11:04:27.947447 <6>[ 8.792294] pci 0000:01:00.0: supports D1 D2
10819 11:04:27.953904 <6>[ 8.796814] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10820 11:04:27.973245 <6>[ 8.815656] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10821 11:04:27.979833 <6>[ 8.822570] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10822 11:04:27.986444 <6>[ 8.830653] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10823 11:04:27.996357 <6>[ 8.838652] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10824 11:04:28.003038 <6>[ 8.846653] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10825 11:04:28.012987 <6>[ 8.854654] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10826 11:04:28.016293 <6>[ 8.862654] pci 0000:00:00.0: PCI bridge to [bus 01]
10827 11:04:28.026315 <6>[ 8.867870] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10828 11:04:28.032455 <6>[ 8.875999] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10829 11:04:28.039416 <6>[ 8.882815] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10830 11:04:28.045538 <6>[ 8.889557] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10831 11:04:28.066477 <5>[ 8.909114] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10832 11:04:28.088505 <5>[ 8.931081] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10833 11:04:28.095223 <5>[ 8.939051] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10834 11:04:28.105167 <4>[ 8.947597] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10835 11:04:28.111452 <6>[ 8.956500] cfg80211: failed to load regulatory.db
10836 11:04:28.171771 <6>[ 9.014210] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10837 11:04:28.178486 <6>[ 9.021765] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10838 11:04:28.202677 <6>[ 9.048491] mt7921e 0000:01:00.0: ASIC revision: 79610010
10839 11:04:28.305635 <6>[ 9.148418] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10840 11:04:28.308761 <6>[ 9.148418]
10841 11:04:28.319049 Begin: Loading essential drivers ... done.
10842 11:04:28.322154 Begin: Running /scripts/init-premount ... done.
10843 11:04:28.328777 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10844 11:04:28.339068 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10845 11:04:28.341688 Device /sys/class/net/eth0 found
10846 11:04:28.341778 done.
10847 11:04:28.361743 Begin: Waiting up to 180 secs for any network device to become available ... done.
10848 11:04:28.406116 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10849 11:04:28.413025 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10850 11:04:28.419642 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10851 11:04:28.425911 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10852 11:04:28.432956 host : mt8192-asurada-spherion-r0-cbg-1
10853 11:04:28.439481 domain : lava-rack
10854 11:04:28.442777 rootserver: 192.168.201.1 rootpath:
10855 11:04:28.443205 filename :
10856 11:04:28.462644 done.
10857 11:04:28.469547 Begin: Running /scripts/nfs-bottom ... done.
10858 11:04:28.491302 Begin: Running /scripts/init-bottom ... done.
10859 11:04:28.574429 <6>[ 9.416416] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10860 11:04:29.807729 <6>[ 10.653313] NET: Registered PF_INET6 protocol family
10861 11:04:29.814586 <6>[ 10.660593] Segment Routing with IPv6
10862 11:04:29.817705 <6>[ 10.664587] In-situ OAM (IOAM) with IPv6
10863 11:04:29.979823 <30>[ 10.799346] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10864 11:04:29.986465 <30>[ 10.832521] systemd[1]: Detected architecture arm64.
10865 11:04:29.994706
10866 11:04:29.997664 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10867 11:04:29.997745
10868 11:04:30.027057 <30>[ 10.872936] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10869 11:04:31.030895 <30>[ 11.873357] systemd[1]: Queued start job for default target graphical.target.
10870 11:04:31.066655 <30>[ 11.908941] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10871 11:04:31.072859 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10872 11:04:31.095478 <30>[ 11.937712] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10873 11:04:31.104954 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10874 11:04:31.123196 <30>[ 11.965582] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10875 11:04:31.133157 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10876 11:04:31.150693 <30>[ 11.993230] systemd[1]: Created slice user.slice - User and Session Slice.
10877 11:04:31.157198 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10878 11:04:31.180747 <30>[ 12.020110] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10879 11:04:31.190741 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10880 11:04:31.208551 <30>[ 12.048066] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10881 11:04:31.215250 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10882 11:04:31.243896 <30>[ 12.076496] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10883 11:04:31.254034 <30>[ 12.096396] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10884 11:04:31.260186 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10885 11:04:31.277430 <30>[ 12.119703] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10886 11:04:31.283624 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10887 11:04:31.301556 <30>[ 12.143861] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10888 11:04:31.311321 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10889 11:04:31.326445 <30>[ 12.171914] systemd[1]: Reached target paths.target - Path Units.
10890 11:04:31.335836 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10891 11:04:31.353638 <30>[ 12.196247] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10892 11:04:31.360314 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10893 11:04:31.373845 <30>[ 12.219797] systemd[1]: Reached target slices.target - Slice Units.
10894 11:04:31.383888 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10895 11:04:31.398176 <30>[ 12.243871] systemd[1]: Reached target swap.target - Swaps.
10896 11:04:31.404662 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10897 11:04:31.425987 <30>[ 12.268342] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10898 11:04:31.435662 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10899 11:04:31.454141 <30>[ 12.296794] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10900 11:04:31.464067 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10901 11:04:31.483951 <30>[ 12.325998] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10902 11:04:31.493483 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10903 11:04:31.511840 <30>[ 12.353939] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10904 11:04:31.521417 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10905 11:04:31.538334 <30>[ 12.380524] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10906 11:04:31.544652 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10907 11:04:31.562673 <30>[ 12.405238] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10908 11:04:31.572398 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10909 11:04:31.592529 <30>[ 12.434699] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10910 11:04:31.601932 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10911 11:04:31.617677 <30>[ 12.460309] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10912 11:04:31.627844 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10913 11:04:31.681515 <30>[ 12.524060] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10914 11:04:31.688446 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10915 11:04:31.709684 <30>[ 12.552364] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10916 11:04:31.716370 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10917 11:04:31.777760 <30>[ 12.620261] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10918 11:04:31.784281 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10919 11:04:31.812167 <30>[ 12.648408] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10920 11:04:31.827583 <30>[ 12.669940] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10921 11:04:31.836989 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10922 11:04:31.858591 <30>[ 12.701039] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10923 11:04:31.864812 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10924 11:04:31.889070 <30>[ 12.731912] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10925 11:04:31.895669 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10926 11:04:31.922574 <30>[ 12.765226] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10927 11:04:31.932281 Startin<6>[ 12.774412] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10928 11:04:31.938998 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10929 11:04:31.993763 <30>[ 12.836249] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10930 11:04:32.000244 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10931 11:04:32.026718 <30>[ 12.869457] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10932 11:04:32.033732 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10933 11:04:32.065303 <6>[ 12.911716] fuse: init (API version 7.37)
10934 11:04:32.077815 <30>[ 12.920489] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10935 11:04:32.084380 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10936 11:04:32.114873 <30>[ 12.957452] systemd[1]: Starting systemd-journald.service - Journal Service...
10937 11:04:32.121592 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10938 11:04:32.144516 <30>[ 12.987024] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10939 11:04:32.151286 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10940 11:04:32.177923 <30>[ 13.017177] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10941 11:04:32.184442 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10942 11:04:32.210501 <30>[ 13.053329] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10943 11:04:32.220436 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10944 11:04:32.242289 <30>[ 13.085064] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10945 11:04:32.249066 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10946 11:04:32.277547 <30>[ 13.120111] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10947 11:04:32.283997 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10948 11:04:32.302046 <30>[ 13.144523] systemd[1]: Started systemd-journald.service - Journal Service.
10949 11:04:32.308213 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10950 11:04:32.329551 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10951 11:04:32.346051 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10952 11:04:32.366289 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10953 11:04:32.387866 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10954 11:04:32.408088 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10955 11:04:32.426722 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10956 11:04:32.446278 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10957 11:04:32.466682 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10958 11:04:32.487418 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10959 11:04:32.506338 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10960 11:04:32.526185 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10961 11:04:32.546825 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10962 11:04:32.566310 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10963 11:04:32.609992 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10964 11:04:32.634807 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10965 11:04:32.663495 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10966 11:04:32.689076 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10967 11:04:32.714026 <46>[ 13.556914] systemd-journald[312]: Received client request to flush runtime journal.
10968 11:04:32.720350 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10969 11:04:32.748513 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10970 11:04:33.038066 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10971 11:04:33.058050 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10972 11:04:33.077191 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10973 11:04:33.094515 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10974 11:04:33.305724 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10975 11:04:34.117005 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10976 11:04:34.135723 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10977 11:04:34.193943 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10978 11:04:34.334028 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10979 11:04:34.357953 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10980 11:04:34.381408 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10981 11:04:34.425028 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10982 11:04:34.451403 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10983 11:04:34.651942 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10984 11:04:34.710662 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10985 11:04:34.762071 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10986 11:04:34.956668 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10987 11:04:35.074860 Starting [0;1;39msystemd-timesyncd… - Network Time S<6>[ 15.920029] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10988 11:04:35.074972 ynchronization...
10989 11:04:35.112721 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10990 11:04:35.203421 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10991 11:04:35.225808 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10992 11:04:35.272316 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10993 11:04:35.314327 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10994 11:04:35.334529 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10995 11:04:35.358380 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10996 11:04:35.381087 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10997 11:04:35.405888 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10998 11:04:35.426519 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10999 11:04:35.445373 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11000 11:04:35.461774 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11001 11:04:35.477680 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11002 11:04:35.502271 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11003 11:04:35.524944 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11004 11:04:35.541624 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11005 11:04:35.561099 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11006 11:04:35.581240 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11007 11:04:35.597218 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11008 11:04:35.615216 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11009 11:04:35.633269 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11010 11:04:35.639726 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11011 11:04:35.694930 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11012 11:04:35.801891 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11013 11:04:35.876013 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11014 11:04:35.898806 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11015 11:04:35.922505 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11016 11:04:35.987886 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11017 11:04:36.022241 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11018 11:04:36.044630 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11019 11:04:36.061525 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11020 11:04:36.081624 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11021 11:04:36.110364 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11022 11:04:36.135587 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11023 11:04:36.251299 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11024 11:04:36.273687 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11025 11:04:36.295277 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11026 11:04:36.340272 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11027 11:04:36.394497 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11028 11:04:36.456807
11029 11:04:36.460081 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11030 11:04:36.460511
11031 11:04:36.463507 debian-bookworm-arm64 login: root (automatic login)
11032 11:04:36.463936
11033 11:04:36.784941 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11034 11:04:36.785460
11035 11:04:36.791687 The programs included with the Debian GNU/Linux system are free software;
11036 11:04:36.798074 the exact distribution terms for each program are described in the
11037 11:04:36.801581 individual files in /usr/share/doc/*/copyright.
11038 11:04:36.802009
11039 11:04:36.808039 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11040 11:04:36.811494 permitted by applicable law.
11041 11:04:37.881945 Matched prompt #10: / #
11043 11:04:37.883069 Setting prompt string to ['/ #']
11044 11:04:37.883517 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11046 11:04:37.884497 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11047 11:04:37.884938 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11048 11:04:37.885319 Setting prompt string to ['/ #']
11049 11:04:37.885662 Forcing a shell prompt, looking for ['/ #']
11050 11:04:37.885966 Sending line: ''
11052 11:04:37.936758 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11053 11:04:37.936972 Waiting using forced prompt support (timeout 00:02:30)
11054 11:04:37.942162 / #
11055 11:04:37.942782 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11056 11:04:37.943093 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11057 11:04:37.943352 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786811/extract-nfsrootfs-8vk9jkqc'"
11059 11:04:38.050119 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786811/extract-nfsrootfs-8vk9jkqc'
11060 11:04:38.050599 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11062 11:04:38.156569 / # export NFS_SERVER_IP='192.168.201.1'
11063 11:04:38.156932 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11064 11:04:38.157067 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11065 11:04:38.157203 end: 2 depthcharge-action (duration 00:01:24) [common]
11066 11:04:38.157319 start: 3 lava-test-retry (timeout 00:07:51) [common]
11067 11:04:38.157417 start: 3.1 lava-test-shell (timeout 00:07:51) [common]
11068 11:04:38.157507 Using namespace: common
11069 11:04:38.157587 Sending line: '#'
11071 11:04:38.258952 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11072 11:04:38.265392 / # #
11073 11:04:38.266192 Using /lava-14786811
11074 11:04:38.266558 Sending line: 'export SHELL=/bin/bash'
11076 11:04:38.373692 / # export SHELL=/bin/bash
11077 11:04:38.374430 Sending line: '. /lava-14786811/environment'
11079 11:04:38.481339 / # . /lava-14786811/environment
11080 11:04:38.487323 Sending line: '/lava-14786811/bin/lava-test-runner /lava-14786811/0'
11082 11:04:38.588695 Test shell timeout: 10s (minimum of the action and connection timeout)
11083 11:04:38.594244 / # /lava-14786811/bin/lava-test-runner /lava-14786811/0
11084 11:04:38.873516 + export TESTRUN_ID=0_timesync-off
11085 11:04:38.876791 + TESTRUN_ID=0_timesync-off
11086 11:04:38.880085 + cd /lava-14786811/0/tests/0_timesync-off
11087 11:04:38.883392 ++ cat uuid
11088 11:04:38.888412 + UUID=14786811_1.6.2.3.1
11089 11:04:38.888482 + set +x
11090 11:04:38.895116 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14786811_1.6.2.3.1>
11091 11:04:38.895389 Received signal: <STARTRUN> 0_timesync-off 14786811_1.6.2.3.1
11092 11:04:38.895477 Starting test lava.0_timesync-off (14786811_1.6.2.3.1)
11093 11:04:38.895582 Skipping test definition patterns.
11094 11:04:38.898195 + systemctl stop systemd-timesyncd
11095 11:04:38.956204 + set +x
11096 11:04:38.959006 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14786811_1.6.2.3.1>
11097 11:04:38.959835 Received signal: <ENDRUN> 0_timesync-off 14786811_1.6.2.3.1
11098 11:04:38.960250 Ending use of test pattern.
11099 11:04:38.960697 Ending test lava.0_timesync-off (14786811_1.6.2.3.1), duration 0.07
11101 11:04:39.033352 + export TESTRUN_ID=1_kselftest-dt
11102 11:04:39.036566 + TESTRUN_ID=1_kselftest-dt
11103 11:04:39.039976 + cd /lava-14786811/0/tests/1_kselftest-dt
11104 11:04:39.043160 ++ cat uuid
11105 11:04:39.046720 + UUID=14786811_1.6.2.3.5
11106 11:04:39.046835 + set +x
11107 11:04:39.050100 Received signal: <STARTRUN> 1_kselftest-dt 14786811_1.6.2.3.5
11108 11:04:39.050251 Starting test lava.1_kselftest-dt (14786811_1.6.2.3.5)
11109 11:04:39.050386 Skipping test definition patterns.
11110 11:04:39.053270 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14786811_1.6.2.3.5>
11111 11:04:39.053455 + cd ./automated/linux/kselftest/
11112 11:04:39.080167 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11113 11:04:39.127298 INFO: install_deps skipped
11114 11:04:39.644921 --2024-07-10 11:04:33-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11115 11:04:39.830443 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11116 11:04:39.963543 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11117 11:04:40.096260 HTTP request sent, awaiting response... 200 OK
11118 11:04:40.099643 Length: 1919896 (1.8M) [application/octet-stream]
11119 11:04:40.102779 Saving to: 'kselftest_armhf.tar.gz'
11120 11:04:40.103336
11121 11:04:40.103679
11122 11:04:40.361544 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11123 11:04:40.626636 kselftest_armhf.tar 2%[ ] 47.81K 184KB/s
11124 11:04:40.940369 kselftest_armhf.tar 11%[=> ] 218.91K 421KB/s
11125 11:04:41.077836 kselftest_armhf.tar 43%[=======> ] 821.30K 991KB/s
11126 11:04:41.084353 kselftest_armhf.tar 100%[===================>] 1.83M 1.90MB/s in 1.0s
11127 11:04:41.084943
11128 11:04:41.251975 2024-07-10 11:04:34 (1.90 MB/s) - 'kselftest_armhf.tar.gz' saved [1919896/1919896]
11129 11:04:41.252102
11130 11:04:47.957424 skiplist:
11131 11:04:47.960636 ========================================
11132 11:04:47.963942 ========================================
11133 11:04:48.036704 ============== Tests to run ===============
11134 11:04:48.039802 ===========End Tests to run ===============
11135 11:04:48.046038 shardfile-dt fail
11136 11:04:48.070499 ./kselftest.sh: 139: cannot open /lava-14786811/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11137 11:04:48.073706 + ../../utils/send-to-lava.sh ./output/result.txt
11138 11:04:48.145264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11139 11:04:48.145766 + set +x
11140 11:04:48.146373 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11142 11:04:48.152242 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14786811_1.6.2.3.5>
11143 11:04:48.152916 Received signal: <ENDRUN> 1_kselftest-dt 14786811_1.6.2.3.5
11144 11:04:48.153334 Ending use of test pattern.
11145 11:04:48.153661 Ending test lava.1_kselftest-dt (14786811_1.6.2.3.5), duration 9.10
11147 11:04:48.154791 ok: lava_test_shell seems to have completed
11148 11:04:48.155256 shardfile-dt: fail
11149 11:04:48.155669 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11150 11:04:48.156076 end: 3 lava-test-retry (duration 00:00:10) [common]
11151 11:04:48.156514 start: 4 finalize (timeout 00:07:41) [common]
11152 11:04:48.156949 start: 4.1 power-off (timeout 00:00:30) [common]
11153 11:04:48.157660 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11154 11:04:50.284274 >> Command sent successfully.
11155 11:04:50.288478 Returned 0 in 2 seconds
11156 11:04:50.288608 end: 4.1 power-off (duration 00:00:02) [common]
11158 11:04:50.288794 start: 4.2 read-feedback (timeout 00:07:39) [common]
11160 11:04:50.289163 Listened to connection for namespace 'common' for up to 1s
11161 11:04:51.289431 Finalising connection for namespace 'common'
11162 11:04:51.290007 Disconnecting from shell: Finalise
11163 11:04:51.290365 / #
11164 11:04:51.391029 end: 4.2 read-feedback (duration 00:00:01) [common]
11165 11:04:51.391191 end: 4 finalize (duration 00:00:03) [common]
11166 11:04:51.391339 Cleaning after the job
11167 11:04:51.391474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/ramdisk
11168 11:04:51.393767 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/kernel
11169 11:04:51.404601 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/dtb
11170 11:04:51.404798 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/nfsrootfs
11171 11:04:51.470400 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786811/tftp-deploy-ta6ugt5m/modules
11172 11:04:51.476065 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786811
11173 11:04:52.062852 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786811
11174 11:04:52.063031 Job finished correctly