Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:05:50.283165 lava-dispatcher, installed at version: 2024.05
2 11:05:50.283369 start: 0 validate
3 11:05:50.283487 Start time: 2024-07-10 11:05:50.283482+00:00 (UTC)
4 11:05:50.283620 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:05:50.283765 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:05:50.559190 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:05:50.559960 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:05:50.829096 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:05:50.830056 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:05:51.099787 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:05:51.100343 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:05:51.367279 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:05:51.367465 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:05:51.634472 validate duration: 1.35
16 11:05:51.634712 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:05:51.634802 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:05:51.634878 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:05:51.635036 Not decompressing ramdisk as can be used compressed.
20 11:05:51.635124 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:05:51.635190 saving as /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/ramdisk/initrd.cpio.gz
22 11:05:51.635245 total size: 5628169 (5 MB)
23 11:05:51.636173 progress 0 % (0 MB)
24 11:05:51.637747 progress 5 % (0 MB)
25 11:05:51.639197 progress 10 % (0 MB)
26 11:05:51.640513 progress 15 % (0 MB)
27 11:05:51.642022 progress 20 % (1 MB)
28 11:05:51.643322 progress 25 % (1 MB)
29 11:05:51.644789 progress 30 % (1 MB)
30 11:05:51.646280 progress 35 % (1 MB)
31 11:05:51.647580 progress 40 % (2 MB)
32 11:05:51.648999 progress 45 % (2 MB)
33 11:05:51.650439 progress 50 % (2 MB)
34 11:05:51.651942 progress 55 % (2 MB)
35 11:05:51.653481 progress 60 % (3 MB)
36 11:05:51.654742 progress 65 % (3 MB)
37 11:05:51.656171 progress 70 % (3 MB)
38 11:05:51.657492 progress 75 % (4 MB)
39 11:05:51.658933 progress 80 % (4 MB)
40 11:05:51.660190 progress 85 % (4 MB)
41 11:05:51.661731 progress 90 % (4 MB)
42 11:05:51.663174 progress 95 % (5 MB)
43 11:05:51.664490 progress 100 % (5 MB)
44 11:05:51.664683 5 MB downloaded in 0.03 s (182.37 MB/s)
45 11:05:51.664814 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:05:51.665024 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:05:51.665105 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:05:51.665233 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:05:51.665358 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:05:51.665417 saving as /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/kernel/Image
52 11:05:51.665483 total size: 54813184 (52 MB)
53 11:05:51.665547 No compression specified
54 11:05:51.666563 progress 0 % (0 MB)
55 11:05:51.679806 progress 5 % (2 MB)
56 11:05:51.693118 progress 10 % (5 MB)
57 11:05:51.706251 progress 15 % (7 MB)
58 11:05:51.719307 progress 20 % (10 MB)
59 11:05:51.732539 progress 25 % (13 MB)
60 11:05:51.745360 progress 30 % (15 MB)
61 11:05:51.758454 progress 35 % (18 MB)
62 11:05:51.771567 progress 40 % (20 MB)
63 11:05:51.784573 progress 45 % (23 MB)
64 11:05:51.797852 progress 50 % (26 MB)
65 11:05:51.811175 progress 55 % (28 MB)
66 11:05:51.824070 progress 60 % (31 MB)
67 11:05:51.837205 progress 65 % (34 MB)
68 11:05:51.850218 progress 70 % (36 MB)
69 11:05:51.863300 progress 75 % (39 MB)
70 11:05:51.876756 progress 80 % (41 MB)
71 11:05:51.890218 progress 85 % (44 MB)
72 11:05:51.903697 progress 90 % (47 MB)
73 11:05:51.917503 progress 95 % (49 MB)
74 11:05:51.931092 progress 100 % (52 MB)
75 11:05:51.931312 52 MB downloaded in 0.27 s (196.65 MB/s)
76 11:05:51.931455 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:05:51.931663 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:05:51.931742 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:05:51.931817 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:05:51.931943 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:05:51.932004 saving as /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/dtb/mt8192-asurada-spherion-r0.dtb
83 11:05:51.932056 total size: 47258 (0 MB)
84 11:05:51.932108 No compression specified
85 11:05:51.933280 progress 69 % (0 MB)
86 11:05:51.933532 progress 100 % (0 MB)
87 11:05:51.933674 0 MB downloaded in 0.00 s (27.89 MB/s)
88 11:05:51.933783 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:05:51.933979 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:05:51.934054 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:05:51.934128 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:05:51.934228 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:05:51.934288 saving as /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/nfsrootfs/full.rootfs.tar
95 11:05:51.934340 total size: 120894716 (115 MB)
96 11:05:51.934393 Using unxz to decompress xz
97 11:05:51.935513 progress 0 % (0 MB)
98 11:05:52.271831 progress 5 % (5 MB)
99 11:05:52.600191 progress 10 % (11 MB)
100 11:05:52.932987 progress 15 % (17 MB)
101 11:05:53.250893 progress 20 % (23 MB)
102 11:05:53.548361 progress 25 % (28 MB)
103 11:05:53.881181 progress 30 % (34 MB)
104 11:05:54.193451 progress 35 % (40 MB)
105 11:05:54.362429 progress 40 % (46 MB)
106 11:05:54.539491 progress 45 % (51 MB)
107 11:05:54.826784 progress 50 % (57 MB)
108 11:05:55.166833 progress 55 % (63 MB)
109 11:05:55.497044 progress 60 % (69 MB)
110 11:05:55.828036 progress 65 % (74 MB)
111 11:05:56.158718 progress 70 % (80 MB)
112 11:05:56.497251 progress 75 % (86 MB)
113 11:05:56.816776 progress 80 % (92 MB)
114 11:05:57.142106 progress 85 % (98 MB)
115 11:05:57.469859 progress 90 % (103 MB)
116 11:05:57.780342 progress 95 % (109 MB)
117 11:05:58.126477 progress 100 % (115 MB)
118 11:05:58.131764 115 MB downloaded in 6.20 s (18.60 MB/s)
119 11:05:58.131950 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:05:58.132184 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:05:58.132265 start: 1.5 download-retry (timeout 00:09:54) [common]
123 11:05:58.132341 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 11:05:58.132466 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:05:58.132527 saving as /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/modules/modules.tar
126 11:05:58.132602 total size: 8607984 (8 MB)
127 11:05:58.132659 Using unxz to decompress xz
128 11:05:58.134117 progress 0 % (0 MB)
129 11:05:58.154139 progress 5 % (0 MB)
130 11:05:58.178003 progress 10 % (0 MB)
131 11:05:58.201338 progress 15 % (1 MB)
132 11:05:58.224663 progress 20 % (1 MB)
133 11:05:58.247239 progress 25 % (2 MB)
134 11:05:58.270150 progress 30 % (2 MB)
135 11:05:58.291894 progress 35 % (2 MB)
136 11:05:58.318075 progress 40 % (3 MB)
137 11:05:58.341517 progress 45 % (3 MB)
138 11:05:58.365728 progress 50 % (4 MB)
139 11:05:58.390704 progress 55 % (4 MB)
140 11:05:58.414103 progress 60 % (4 MB)
141 11:05:58.436886 progress 65 % (5 MB)
142 11:05:58.461393 progress 70 % (5 MB)
143 11:05:58.487552 progress 75 % (6 MB)
144 11:05:58.514382 progress 80 % (6 MB)
145 11:05:58.537358 progress 85 % (7 MB)
146 11:05:58.559716 progress 90 % (7 MB)
147 11:05:58.582244 progress 95 % (7 MB)
148 11:05:58.604276 progress 100 % (8 MB)
149 11:05:58.609799 8 MB downloaded in 0.48 s (17.20 MB/s)
150 11:05:58.610009 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:05:58.610355 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:05:58.610437 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 11:05:58.610513 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 11:06:02.121657 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786841/extract-nfsrootfs-36yjr3fx
156 11:06:02.121831 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:06:02.121918 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 11:06:02.122071 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h
159 11:06:02.122188 makedir: /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin
160 11:06:02.122278 makedir: /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/tests
161 11:06:02.122368 makedir: /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/results
162 11:06:02.122448 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-add-keys
163 11:06:02.122571 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-add-sources
164 11:06:02.122685 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-background-process-start
165 11:06:02.122798 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-background-process-stop
166 11:06:02.122918 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-common-functions
167 11:06:02.123029 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-echo-ipv4
168 11:06:02.123140 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-install-packages
169 11:06:02.123247 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-installed-packages
170 11:06:02.123355 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-os-build
171 11:06:02.123464 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-probe-channel
172 11:06:02.123572 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-probe-ip
173 11:06:02.123682 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-target-ip
174 11:06:02.123790 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-target-mac
175 11:06:02.123897 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-target-storage
176 11:06:02.124009 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-test-case
177 11:06:02.124118 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-test-event
178 11:06:02.124223 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-test-feedback
179 11:06:02.124335 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-test-raise
180 11:06:02.124442 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-test-reference
181 11:06:02.124550 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-test-runner
182 11:06:02.124659 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-test-set
183 11:06:02.124766 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-test-shell
184 11:06:02.124875 Updating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-add-keys (debian)
185 11:06:02.125009 Updating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-add-sources (debian)
186 11:06:02.125134 Updating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-install-packages (debian)
187 11:06:02.125255 Updating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-installed-packages (debian)
188 11:06:02.125375 Updating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/bin/lava-os-build (debian)
189 11:06:02.125480 Creating /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/environment
190 11:06:02.125562 LAVA metadata
191 11:06:02.125622 - LAVA_JOB_ID=14786841
192 11:06:02.125676 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:06:02.125763 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
194 11:06:02.125817 skipped lava-vland-overlay
195 11:06:02.125893 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:06:02.125963 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
197 11:06:02.126016 skipped lava-multinode-overlay
198 11:06:02.126078 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:06:02.126145 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
200 11:06:02.126206 Loading test definitions
201 11:06:02.126278 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
202 11:06:02.126338 Using /lava-14786841 at stage 0
203 11:06:02.126605 uuid=14786841_1.6.2.3.1 testdef=None
204 11:06:02.126682 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:06:02.126754 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
206 11:06:02.127136 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:06:02.127328 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
209 11:06:02.127817 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:06:02.128020 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
212 11:06:02.128493 runner path: /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/0/tests/0_timesync-off test_uuid 14786841_1.6.2.3.1
213 11:06:02.128632 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:06:02.128828 start: 1.6.2.3.5 git-repo-action (timeout 00:09:50) [common]
216 11:06:02.128891 Using /lava-14786841 at stage 0
217 11:06:02.128975 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:06:02.129046 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/0/tests/1_kselftest-tpm2'
219 11:06:04.078415 Running '/usr/bin/git checkout kernelci.org
220 11:06:04.152431 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 11:06:04.152796 uuid=14786841_1.6.2.3.5 testdef=None
222 11:06:04.152896 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 11:06:04.153090 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 11:06:04.153723 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:06:04.153922 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 11:06:04.154786 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:06:04.155004 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 11:06:04.155841 runner path: /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/0/tests/1_kselftest-tpm2 test_uuid 14786841_1.6.2.3.5
232 11:06:04.155920 BOARD='mt8192-asurada-spherion-r0'
233 11:06:04.155978 BRANCH='cip'
234 11:06:04.156031 SKIPFILE='/dev/null'
235 11:06:04.156082 SKIP_INSTALL='True'
236 11:06:04.156132 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:06:04.156183 TST_CASENAME=''
238 11:06:04.156233 TST_CMDFILES='tpm2'
239 11:06:04.156360 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:06:04.156541 Creating lava-test-runner.conf files
242 11:06:04.156595 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786841/lava-overlay-0s7bk86h/lava-14786841/0 for stage 0
243 11:06:04.156675 - 0_timesync-off
244 11:06:04.156733 - 1_kselftest-tpm2
245 11:06:04.156817 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 11:06:04.156890 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 11:06:11.106070 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:06:11.106203 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:41) [common]
249 11:06:11.106285 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:06:11.106365 end: 1.6.2 lava-overlay (duration 00:00:09) [common]
251 11:06:11.106443 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:41) [common]
252 11:06:11.245950 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:06:11.246094 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 11:06:11.246166 extracting modules file /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786841/extract-nfsrootfs-36yjr3fx
255 11:06:11.457063 extracting modules file /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786841/extract-overlay-ramdisk-336fhno9/ramdisk
256 11:06:11.672333 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:06:11.672471 start: 1.6.5 apply-overlay-tftp (timeout 00:09:40) [common]
258 11:06:11.672554 [common] Applying overlay to NFS
259 11:06:11.672613 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786841/compress-overlay-ltbqi1xv/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786841/extract-nfsrootfs-36yjr3fx
260 11:06:12.483692 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:06:12.483830 start: 1.6.6 configure-preseed-file (timeout 00:09:39) [common]
262 11:06:12.483916 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:06:12.483993 start: 1.6.7 compress-ramdisk (timeout 00:09:39) [common]
264 11:06:12.484062 Building ramdisk /var/lib/lava/dispatcher/tmp/14786841/extract-overlay-ramdisk-336fhno9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786841/extract-overlay-ramdisk-336fhno9/ramdisk
265 11:06:12.763977 >> 129845 blocks
266 11:06:14.816865 rename /var/lib/lava/dispatcher/tmp/14786841/extract-overlay-ramdisk-336fhno9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/ramdisk/ramdisk.cpio.gz
267 11:06:14.817030 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:06:14.817174 start: 1.6.8 prepare-kernel (timeout 00:09:37) [common]
269 11:06:14.817267 start: 1.6.8.1 prepare-fit (timeout 00:09:37) [common]
270 11:06:14.817344 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/kernel/Image']
271 11:06:28.037561 Returned 0 in 13 seconds
272 11:06:28.037733 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/kernel/image.itb
273 11:06:28.390693 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:06:28.390825 output: Created: Wed Jul 10 12:06:28 2024
275 11:06:28.390885 output: Image 0 (kernel-1)
276 11:06:28.390938 output: Description:
277 11:06:28.390989 output: Created: Wed Jul 10 12:06:28 2024
278 11:06:28.391038 output: Type: Kernel Image
279 11:06:28.391087 output: Compression: lzma compressed
280 11:06:28.391137 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
281 11:06:28.391186 output: Architecture: AArch64
282 11:06:28.391233 output: OS: Linux
283 11:06:28.391279 output: Load Address: 0x00000000
284 11:06:28.391325 output: Entry Point: 0x00000000
285 11:06:28.391371 output: Hash algo: crc32
286 11:06:28.391418 output: Hash value: 9bb85fb9
287 11:06:28.391464 output: Image 1 (fdt-1)
288 11:06:28.391510 output: Description: mt8192-asurada-spherion-r0
289 11:06:28.391557 output: Created: Wed Jul 10 12:06:28 2024
290 11:06:28.391603 output: Type: Flat Device Tree
291 11:06:28.391650 output: Compression: uncompressed
292 11:06:28.391696 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:06:28.391743 output: Architecture: AArch64
294 11:06:28.391789 output: Hash algo: crc32
295 11:06:28.391835 output: Hash value: 0f8e4d2e
296 11:06:28.391880 output: Image 2 (ramdisk-1)
297 11:06:28.391925 output: Description: unavailable
298 11:06:28.391970 output: Created: Wed Jul 10 12:06:28 2024
299 11:06:28.392016 output: Type: RAMDisk Image
300 11:06:28.392062 output: Compression: uncompressed
301 11:06:28.392108 output: Data Size: 18708495 Bytes = 18270.01 KiB = 17.84 MiB
302 11:06:28.392154 output: Architecture: AArch64
303 11:06:28.392199 output: OS: Linux
304 11:06:28.392244 output: Load Address: unavailable
305 11:06:28.392289 output: Entry Point: unavailable
306 11:06:28.392334 output: Hash algo: crc32
307 11:06:28.392380 output: Hash value: 67faaab9
308 11:06:28.392425 output: Default Configuration: 'conf-1'
309 11:06:28.392470 output: Configuration 0 (conf-1)
310 11:06:28.392515 output: Description: mt8192-asurada-spherion-r0
311 11:06:28.392560 output: Kernel: kernel-1
312 11:06:28.392605 output: Init Ramdisk: ramdisk-1
313 11:06:28.392650 output: FDT: fdt-1
314 11:06:28.392696 output: Loadables: kernel-1
315 11:06:28.392741 output:
316 11:06:28.392839 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:06:28.392910 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:06:28.392980 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 11:06:28.393052 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:23) [common]
320 11:06:28.393106 No LXC device requested
321 11:06:28.393210 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:06:28.393277 start: 1.8 deploy-device-env (timeout 00:09:23) [common]
323 11:06:28.393342 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:06:28.393394 Checking files for TFTP limit of 4294967296 bytes.
325 11:06:28.393749 end: 1 tftp-deploy (duration 00:00:37) [common]
326 11:06:28.393835 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:06:28.393912 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:06:28.394001 substitutions:
329 11:06:28.394059 - {DTB}: 14786841/tftp-deploy-2dy1oftf/dtb/mt8192-asurada-spherion-r0.dtb
330 11:06:28.394111 - {INITRD}: 14786841/tftp-deploy-2dy1oftf/ramdisk/ramdisk.cpio.gz
331 11:06:28.394162 - {KERNEL}: 14786841/tftp-deploy-2dy1oftf/kernel/Image
332 11:06:28.394210 - {LAVA_MAC}: None
333 11:06:28.394259 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786841/extract-nfsrootfs-36yjr3fx
334 11:06:28.394308 - {NFS_SERVER_IP}: 192.168.201.1
335 11:06:28.394357 - {PRESEED_CONFIG}: None
336 11:06:28.394411 - {PRESEED_LOCAL}: None
337 11:06:28.394460 - {RAMDISK}: 14786841/tftp-deploy-2dy1oftf/ramdisk/ramdisk.cpio.gz
338 11:06:28.394508 - {ROOT_PART}: None
339 11:06:28.394555 - {ROOT}: None
340 11:06:28.394602 - {SERVER_IP}: 192.168.201.1
341 11:06:28.394649 - {TEE}: None
342 11:06:28.394696 Parsed boot commands:
343 11:06:28.394742 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:06:28.394873 Parsed boot commands: tftpboot 192.168.201.1 14786841/tftp-deploy-2dy1oftf/kernel/image.itb 14786841/tftp-deploy-2dy1oftf/kernel/cmdline
345 11:06:28.394950 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:06:28.395022 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:06:28.395092 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:06:28.395162 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:06:28.395215 Not connected, no need to disconnect.
350 11:06:28.395278 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:06:28.395344 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:06:28.395396 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 11:06:28.398416 Setting prompt string to ['lava-test: # ']
354 11:06:28.398703 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:06:28.398794 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:06:28.398879 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:06:28.399001 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:06:28.399207 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=reboot']
359 11:06:37.536886 >> Command sent successfully.
360 11:06:37.551708 Returned 0 in 9 seconds
361 11:06:37.552287 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:06:37.553698 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:06:37.554243 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:06:37.554615 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:06:37.554904 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:06:37.555207 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:06:37.556723 [Enter `^Ec?' for help]
369 11:06:38.806331
370 11:06:38.806862
371 11:06:38.807195 F0: 102B 0000
372 11:06:38.807518
373 11:06:38.807816 F3: 1001 0000 [0200]
374 11:06:38.809713
375 11:06:38.810140 F3: 1001 0000
376 11:06:38.810503
377 11:06:38.810823 F7: 102D 0000
378 11:06:38.811112
379 11:06:38.813325 F1: 0000 0000
380 11:06:38.813832
381 11:06:38.814161 V0: 0000 0000 [0001]
382 11:06:38.814462
383 11:06:38.816499 00: 0007 8000
384 11:06:38.816928
385 11:06:38.817293 01: 0000 0000
386 11:06:38.817609
387 11:06:38.819695 BP: 0C00 0209 [0000]
388 11:06:38.820208
389 11:06:38.820538 G0: 1182 0000
390 11:06:38.820834
391 11:06:38.823015 EC: 0000 0021 [4000]
392 11:06:38.823481
393 11:06:38.823809 S7: 0000 0000 [0000]
394 11:06:38.824148
395 11:06:38.826787 CC: 0000 0000 [0001]
396 11:06:38.827291
397 11:06:38.827621 T0: 0000 0040 [010F]
398 11:06:38.827924
399 11:06:38.829679 Jump to BL
400 11:06:38.830099
401 11:06:38.853468
402 11:06:38.853970
403 11:06:38.863290 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:06:38.866779 ARM64: Exception handlers installed.
405 11:06:38.867209 ARM64: Testing exception
406 11:06:38.869821 ARM64: Done test exception
407 11:06:38.876788 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:06:38.886967 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:06:38.893824 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:06:38.904272 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:06:38.910730 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:06:38.920958 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:06:38.931488 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:06:38.937690 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:06:38.956384 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:06:38.959794 WDT: Last reset was cold boot
417 11:06:38.962730 SPI1(PAD0) initialized at 2873684 Hz
418 11:06:38.966171 SPI5(PAD0) initialized at 992727 Hz
419 11:06:38.969855 VBOOT: Loading verstage.
420 11:06:38.976408 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:06:38.979772 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:06:38.983174 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:06:38.986445 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:06:38.993791 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:06:39.000676 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:06:39.011643 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 11:06:39.012175
428 11:06:39.012508
429 11:06:39.022335 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:06:39.026006 ARM64: Exception handlers installed.
431 11:06:39.026441 ARM64: Testing exception
432 11:06:39.029272 ARM64: Done test exception
433 11:06:39.033122 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:06:39.039762 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:06:39.052663 Probing TPM: . done!
436 11:06:39.053196 TPM ready after 0 ms
437 11:06:39.059871 Connected to device vid:did:rid of 1ae0:0028:00
438 11:06:39.067508 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 11:06:39.128197 Initialized TPM device CR50 revision 0
440 11:06:39.142017 tlcl_send_startup: Startup return code is 0
441 11:06:39.142531 TPM: setup succeeded
442 11:06:39.157984 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:06:39.165679 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:06:39.176419 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:06:39.186328 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:06:39.190093 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:06:39.193943 in-header: 03 07 00 00 08 00 00 00
448 11:06:39.197615 in-data: aa e4 47 04 13 02 00 00
449 11:06:39.198051 Chrome EC: UHEPI supported
450 11:06:39.205023 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:06:39.208832 in-header: 03 a9 00 00 08 00 00 00
452 11:06:39.212974 in-data: 84 60 60 08 00 00 00 00
453 11:06:39.213568 Phase 1
454 11:06:39.216431 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:06:39.224190 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:06:39.227680 VB2:vb2_check_recovery() Recovery was requested manually
457 11:06:39.235342 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:06:39.239381 Recovery requested (1009000e)
459 11:06:39.249003 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:06:39.252017 tlcl_extend: response is 0
461 11:06:39.263832 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:06:39.267075 tlcl_extend: response is 0
463 11:06:39.274184 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:06:39.294660 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:06:39.302157 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:06:39.302727
467 11:06:39.303246
468 11:06:39.309943 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:06:39.313379 ARM64: Exception handlers installed.
470 11:06:39.316883 ARM64: Testing exception
471 11:06:39.317471 ARM64: Done test exception
472 11:06:39.339280 pmic_efuse_setting: Set efuses in 11 msecs
473 11:06:39.342606 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:06:39.349821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:06:39.352894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:06:39.359333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:06:39.362847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:06:39.365946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:06:39.372776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:06:39.376111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:06:39.383277 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:06:39.386455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:06:39.393356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:06:39.396495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:06:39.399355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:06:39.406213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:06:39.412798 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:06:39.416088 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:06:39.423010 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:06:39.429438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:06:39.432809 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:06:39.439936 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:06:39.446339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:06:39.449410 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:06:39.456212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:06:39.463128 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:06:39.466512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:06:39.472970 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:06:39.479475 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:06:39.482905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:06:39.489988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:06:39.492897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:06:39.496352 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:06:39.503047 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:06:39.507355 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:06:39.514005 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:06:39.517409 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:06:39.524248 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:06:39.527867 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:06:39.534441 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:06:39.537899 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:06:39.544074 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:06:39.547698 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:06:39.551176 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:06:39.554165 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:06:39.561122 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:06:39.564501 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:06:39.567761 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:06:39.574456 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:06:39.577755 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:06:39.580863 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:06:39.587897 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:06:39.591117 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:06:39.594635 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:06:39.601365 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:06:39.611187 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:06:39.614401 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:06:39.624802 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:06:39.631158 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:06:39.638196 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:06:39.641212 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:06:39.644289 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:06:39.652324 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x8
534 11:06:39.658819 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:06:39.662326 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:06:39.665636 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:06:39.676733 [RTC]rtc_get_frequency_meter,154: input=15, output=771
538 11:06:39.686818 [RTC]rtc_get_frequency_meter,154: input=23, output=959
539 11:06:39.695613 [RTC]rtc_get_frequency_meter,154: input=19, output=865
540 11:06:39.705355 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 11:06:39.715013 [RTC]rtc_get_frequency_meter,154: input=16, output=797
542 11:06:39.724067 [RTC]rtc_get_frequency_meter,154: input=15, output=773
543 11:06:39.733930 [RTC]rtc_get_frequency_meter,154: input=16, output=796
544 11:06:39.737380 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 11:06:39.743938 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 11:06:39.747716 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:06:39.751133 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 11:06:39.757683 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:06:39.761252 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 11:06:39.764032 ADC[4]: Raw value=902876 ID=7
551 11:06:39.764462 ADC[3]: Raw value=212810 ID=1
552 11:06:39.767685 RAM Code: 0x71
553 11:06:39.771090 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:06:39.777440 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:06:39.784822 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:06:39.791195 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:06:39.794422 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:06:39.797663 in-header: 03 07 00 00 08 00 00 00
559 11:06:39.801204 in-data: aa e4 47 04 13 02 00 00
560 11:06:39.804611 Chrome EC: UHEPI supported
561 11:06:39.811391 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:06:39.814633 in-header: 03 a9 00 00 08 00 00 00
563 11:06:39.818579 in-data: 84 60 60 08 00 00 00 00
564 11:06:39.821593 MRC: failed to locate region type 0.
565 11:06:39.828148 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:06:39.831685 DRAM-K: Running full calibration
567 11:06:39.834527 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:06:39.838135 header.status = 0x0
569 11:06:39.841679 header.version = 0x6 (expected: 0x6)
570 11:06:39.844724 header.size = 0xd00 (expected: 0xd00)
571 11:06:39.848233 header.flags = 0x0
572 11:06:39.851573 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:06:39.870135 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 11:06:39.876903 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:06:39.880103 dram_init: ddr_geometry: 2
576 11:06:39.883577 [EMI] MDL number = 2
577 11:06:39.884082 [EMI] Get MDL freq = 0
578 11:06:39.886836 dram_init: ddr_type: 0
579 11:06:39.887263 is_discrete_lpddr4: 1
580 11:06:39.890312 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:06:39.890813
582 11:06:39.891141
583 11:06:39.894091 [Bian_co] ETT version 0.0.0.1
584 11:06:39.900130 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:06:39.900589
586 11:06:39.903815 dramc_set_vcore_voltage set vcore to 650000
587 11:06:39.904323 Read voltage for 800, 4
588 11:06:39.907158 Vio18 = 0
589 11:06:39.907586 Vcore = 650000
590 11:06:39.907915 Vdram = 0
591 11:06:39.910139 Vddq = 0
592 11:06:39.910567 Vmddr = 0
593 11:06:39.913667 dram_init: config_dvfs: 1
594 11:06:39.916957 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:06:39.923999 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:06:39.926992 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
597 11:06:39.930547 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
598 11:06:39.933920 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 11:06:39.937545 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 11:06:39.940539 MEM_TYPE=3, freq_sel=18
601 11:06:39.943876 sv_algorithm_assistance_LP4_1600
602 11:06:39.947477 ============ PULL DRAM RESETB DOWN ============
603 11:06:39.950448 ========== PULL DRAM RESETB DOWN end =========
604 11:06:39.957299 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:06:39.960764 ===================================
606 11:06:39.961313 LPDDR4 DRAM CONFIGURATION
607 11:06:39.963954 ===================================
608 11:06:39.967099 EX_ROW_EN[0] = 0x0
609 11:06:39.970578 EX_ROW_EN[1] = 0x0
610 11:06:39.971080 LP4Y_EN = 0x0
611 11:06:39.974069 WORK_FSP = 0x0
612 11:06:39.974576 WL = 0x2
613 11:06:39.977617 RL = 0x2
614 11:06:39.978125 BL = 0x2
615 11:06:39.980880 RPST = 0x0
616 11:06:39.981451 RD_PRE = 0x0
617 11:06:39.984362 WR_PRE = 0x1
618 11:06:39.984901 WR_PST = 0x0
619 11:06:39.987226 DBI_WR = 0x0
620 11:06:39.987653 DBI_RD = 0x0
621 11:06:39.990766 OTF = 0x1
622 11:06:39.994023 ===================================
623 11:06:39.997589 ===================================
624 11:06:39.998096 ANA top config
625 11:06:40.000835 ===================================
626 11:06:40.004215 DLL_ASYNC_EN = 0
627 11:06:40.007494 ALL_SLAVE_EN = 1
628 11:06:40.008001 NEW_RANK_MODE = 1
629 11:06:40.010916 DLL_IDLE_MODE = 1
630 11:06:40.014252 LP45_APHY_COMB_EN = 1
631 11:06:40.017523 TX_ODT_DIS = 1
632 11:06:40.021038 NEW_8X_MODE = 1
633 11:06:40.023961 ===================================
634 11:06:40.027465 ===================================
635 11:06:40.027981 data_rate = 1600
636 11:06:40.030846 CKR = 1
637 11:06:40.034351 DQ_P2S_RATIO = 8
638 11:06:40.037465 ===================================
639 11:06:40.040936 CA_P2S_RATIO = 8
640 11:06:40.044283 DQ_CA_OPEN = 0
641 11:06:40.044714 DQ_SEMI_OPEN = 0
642 11:06:40.047733 CA_SEMI_OPEN = 0
643 11:06:40.050892 CA_FULL_RATE = 0
644 11:06:40.054242 DQ_CKDIV4_EN = 1
645 11:06:40.057817 CA_CKDIV4_EN = 1
646 11:06:40.061380 CA_PREDIV_EN = 0
647 11:06:40.061885 PH8_DLY = 0
648 11:06:40.064354 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:06:40.067631 DQ_AAMCK_DIV = 4
650 11:06:40.070898 CA_AAMCK_DIV = 4
651 11:06:40.074715 CA_ADMCK_DIV = 4
652 11:06:40.077790 DQ_TRACK_CA_EN = 0
653 11:06:40.078222 CA_PICK = 800
654 11:06:40.081317 CA_MCKIO = 800
655 11:06:40.084427 MCKIO_SEMI = 0
656 11:06:40.088180 PLL_FREQ = 3068
657 11:06:40.090872 DQ_UI_PI_RATIO = 32
658 11:06:40.094025 CA_UI_PI_RATIO = 0
659 11:06:40.097734 ===================================
660 11:06:40.100738 ===================================
661 11:06:40.101190 memory_type:LPDDR4
662 11:06:40.104472 GP_NUM : 10
663 11:06:40.107507 SRAM_EN : 1
664 11:06:40.107935 MD32_EN : 0
665 11:06:40.111315 ===================================
666 11:06:40.114305 [ANA_INIT] >>>>>>>>>>>>>>
667 11:06:40.117507 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:06:40.121549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:06:40.124142 ===================================
670 11:06:40.127602 data_rate = 1600,PCW = 0X7600
671 11:06:40.131232 ===================================
672 11:06:40.134264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:06:40.137566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:06:40.144174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:06:40.147663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:06:40.151269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:06:40.154356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:06:40.157804 [ANA_INIT] flow start
679 11:06:40.161545 [ANA_INIT] PLL >>>>>>>>
680 11:06:40.162050 [ANA_INIT] PLL <<<<<<<<
681 11:06:40.164502 [ANA_INIT] MIDPI >>>>>>>>
682 11:06:40.168426 [ANA_INIT] MIDPI <<<<<<<<
683 11:06:40.169040 [ANA_INIT] DLL >>>>>>>>
684 11:06:40.171291 [ANA_INIT] flow end
685 11:06:40.174370 ============ LP4 DIFF to SE enter ============
686 11:06:40.178284 ============ LP4 DIFF to SE exit ============
687 11:06:40.181416 [ANA_INIT] <<<<<<<<<<<<<
688 11:06:40.184803 [Flow] Enable top DCM control >>>>>
689 11:06:40.187895 [Flow] Enable top DCM control <<<<<
690 11:06:40.191436 Enable DLL master slave shuffle
691 11:06:40.198204 ==============================================================
692 11:06:40.198707 Gating Mode config
693 11:06:40.204945 ==============================================================
694 11:06:40.205497 Config description:
695 11:06:40.214747 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:06:40.221544 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:06:40.228376 SELPH_MODE 0: By rank 1: By Phase
698 11:06:40.231488 ==============================================================
699 11:06:40.234849 GAT_TRACK_EN = 1
700 11:06:40.238410 RX_GATING_MODE = 2
701 11:06:40.241819 RX_GATING_TRACK_MODE = 2
702 11:06:40.245164 SELPH_MODE = 1
703 11:06:40.248202 PICG_EARLY_EN = 1
704 11:06:40.251876 VALID_LAT_VALUE = 1
705 11:06:40.254950 ==============================================================
706 11:06:40.258503 Enter into Gating configuration >>>>
707 11:06:40.261895 Exit from Gating configuration <<<<
708 11:06:40.265248 Enter into DVFS_PRE_config >>>>>
709 11:06:40.278289 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:06:40.281912 Exit from DVFS_PRE_config <<<<<
711 11:06:40.282421 Enter into PICG configuration >>>>
712 11:06:40.285084 Exit from PICG configuration <<<<
713 11:06:40.288415 [RX_INPUT] configuration >>>>>
714 11:06:40.292188 [RX_INPUT] configuration <<<<<
715 11:06:40.298789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:06:40.301505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:06:40.308350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:06:40.315264 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:06:40.322315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:06:40.328732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:06:40.332360 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:06:40.335721 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:06:40.339025 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:06:40.345770 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:06:40.349371 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:06:40.352860 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:06:40.356789 ===================================
728 11:06:40.357248 LPDDR4 DRAM CONFIGURATION
729 11:06:40.360521 ===================================
730 11:06:40.364112 EX_ROW_EN[0] = 0x0
731 11:06:40.364540 EX_ROW_EN[1] = 0x0
732 11:06:40.367826 LP4Y_EN = 0x0
733 11:06:40.368257 WORK_FSP = 0x0
734 11:06:40.371436 WL = 0x2
735 11:06:40.371864 RL = 0x2
736 11:06:40.375602 BL = 0x2
737 11:06:40.376028 RPST = 0x0
738 11:06:40.379384 RD_PRE = 0x0
739 11:06:40.379811 WR_PRE = 0x1
740 11:06:40.380140 WR_PST = 0x0
741 11:06:40.382694 DBI_WR = 0x0
742 11:06:40.383121 DBI_RD = 0x0
743 11:06:40.386339 OTF = 0x1
744 11:06:40.389278 ===================================
745 11:06:40.393199 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:06:40.395919 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:06:40.403321 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:06:40.406199 ===================================
749 11:06:40.406714 LPDDR4 DRAM CONFIGURATION
750 11:06:40.409553 ===================================
751 11:06:40.413256 EX_ROW_EN[0] = 0x10
752 11:06:40.416580 EX_ROW_EN[1] = 0x0
753 11:06:40.417091 LP4Y_EN = 0x0
754 11:06:40.419679 WORK_FSP = 0x0
755 11:06:40.420192 WL = 0x2
756 11:06:40.422795 RL = 0x2
757 11:06:40.423225 BL = 0x2
758 11:06:40.426410 RPST = 0x0
759 11:06:40.426920 RD_PRE = 0x0
760 11:06:40.429848 WR_PRE = 0x1
761 11:06:40.430358 WR_PST = 0x0
762 11:06:40.433170 DBI_WR = 0x0
763 11:06:40.433704 DBI_RD = 0x0
764 11:06:40.436567 OTF = 0x1
765 11:06:40.439736 ===================================
766 11:06:40.446141 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:06:40.449416 nWR fixed to 40
768 11:06:40.449851 [ModeRegInit_LP4] CH0 RK0
769 11:06:40.452796 [ModeRegInit_LP4] CH0 RK1
770 11:06:40.456346 [ModeRegInit_LP4] CH1 RK0
771 11:06:40.456815 [ModeRegInit_LP4] CH1 RK1
772 11:06:40.459751 match AC timing 13
773 11:06:40.463279 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:06:40.466617 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:06:40.472913 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:06:40.476705 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:06:40.482969 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:06:40.483141 [EMI DOE] emi_dcm 0
779 11:06:40.486035 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:06:40.489584 ==
781 11:06:40.489846 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:06:40.496656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:06:40.497216 ==
784 11:06:40.499985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:06:40.506323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:06:40.516210 [CA 0] Center 38 (7~69) winsize 63
787 11:06:40.519625 [CA 1] Center 38 (7~69) winsize 63
788 11:06:40.523660 [CA 2] Center 35 (5~66) winsize 62
789 11:06:40.527280 [CA 3] Center 35 (4~66) winsize 63
790 11:06:40.530412 [CA 4] Center 34 (4~65) winsize 62
791 11:06:40.533806 [CA 5] Center 33 (3~64) winsize 62
792 11:06:40.534254
793 11:06:40.537347 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:06:40.537807
795 11:06:40.540639 [CATrainingPosCal] consider 1 rank data
796 11:06:40.543929 u2DelayCellTimex100 = 270/100 ps
797 11:06:40.547024 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
798 11:06:40.550392 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
799 11:06:40.554107 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 11:06:40.557299 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 11:06:40.561216 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 11:06:40.564366 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:06:40.567971
804 11:06:40.570859 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:06:40.571384
806 11:06:40.573995 [CBTSetCACLKResult] CA Dly = 33
807 11:06:40.574426 CS Dly: 6 (0~37)
808 11:06:40.574755 ==
809 11:06:40.577451 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:06:40.580151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:06:40.580228 ==
812 11:06:40.587280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:06:40.593567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:06:40.602944 [CA 0] Center 38 (7~69) winsize 63
815 11:06:40.606025 [CA 1] Center 38 (7~69) winsize 63
816 11:06:40.609581 [CA 2] Center 36 (6~67) winsize 62
817 11:06:40.613052 [CA 3] Center 36 (5~67) winsize 63
818 11:06:40.616038 [CA 4] Center 35 (4~66) winsize 63
819 11:06:40.619660 [CA 5] Center 34 (4~65) winsize 62
820 11:06:40.619836
821 11:06:40.622763 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:06:40.622953
823 11:06:40.626142 [CATrainingPosCal] consider 2 rank data
824 11:06:40.629575 u2DelayCellTimex100 = 270/100 ps
825 11:06:40.632696 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
826 11:06:40.636444 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
827 11:06:40.642890 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
828 11:06:40.646515 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
829 11:06:40.649557 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
830 11:06:40.653312 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 11:06:40.653665
832 11:06:40.656902 CA PerBit enable=1, Macro0, CA PI delay=34
833 11:06:40.657379
834 11:06:40.659748 [CBTSetCACLKResult] CA Dly = 34
835 11:06:40.660104 CS Dly: 6 (0~38)
836 11:06:40.660378
837 11:06:40.663199 ----->DramcWriteLeveling(PI) begin...
838 11:06:40.663631 ==
839 11:06:40.666446 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:06:40.673424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:06:40.673955 ==
842 11:06:40.676724 Write leveling (Byte 0): 31 => 31
843 11:06:40.680365 Write leveling (Byte 1): 31 => 31
844 11:06:40.680874 DramcWriteLeveling(PI) end<-----
845 11:06:40.681246
846 11:06:40.683589 ==
847 11:06:40.684094 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:06:40.689929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:06:40.690441 ==
850 11:06:40.693868 [Gating] SW mode calibration
851 11:06:40.700101 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:06:40.703667 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:06:40.710047 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:06:40.713813 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:06:40.716570 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 11:06:40.723566 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:06:40.727260 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:06:40.730418 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:06:40.733869 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:06:40.739915 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:06:40.743658 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:06:40.746836 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:06:40.753882 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:06:40.757015 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:06:40.760664 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:06:40.767082 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:06:40.770391 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:06:40.773684 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:06:40.780040 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 11:06:40.783747 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 11:06:40.787436 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 11:06:40.793934 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:06:40.797055 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:06:40.800485 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:06:40.804456 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:06:40.810377 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:06:40.813829 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:06:40.817510 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
879 11:06:40.823867 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
880 11:06:40.827455 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
881 11:06:40.830318 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:06:40.837278 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:06:40.840623 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:06:40.844256 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:06:40.850661 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:06:40.854698 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
887 11:06:40.857774 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 1) (1 0)
888 11:06:40.864214 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 11:06:40.867489 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:06:40.870724 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:06:40.874284 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:06:40.880796 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:06:40.884383 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:06:40.887663 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
895 11:06:40.894340 0 11 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
896 11:06:40.897807 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
897 11:06:40.900728 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:06:40.907891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:06:40.911137 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:06:40.914543 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:06:40.921205 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 11:06:40.924723 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:06:40.928068 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 11:06:40.931132 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:06:40.939176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:06:40.941989 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:06:40.945596 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:06:40.948920 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:06:40.955372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:06:40.959144 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:06:40.962357 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:06:40.969085 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:06:40.972235 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:06:40.975532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:06:40.982449 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:06:40.985867 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:06:40.988956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:06:40.996102 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 11:06:40.998850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 11:06:41.002445 Total UI for P1: 0, mck2ui 16
921 11:06:41.006035 best dqsien dly found for B0: ( 0, 14, 4)
922 11:06:41.008953 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 11:06:41.012573 Total UI for P1: 0, mck2ui 16
924 11:06:41.016004 best dqsien dly found for B1: ( 0, 14, 8)
925 11:06:41.019080 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 11:06:41.022872 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 11:06:41.023389
928 11:06:41.026169 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 11:06:41.029274 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 11:06:41.032645 [Gating] SW calibration Done
931 11:06:41.033196 ==
932 11:06:41.036028 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:06:41.039549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:06:41.042474 ==
935 11:06:41.042916 RX Vref Scan: 0
936 11:06:41.043248
937 11:06:41.046203 RX Vref 0 -> 0, step: 1
938 11:06:41.046717
939 11:06:41.049148 RX Delay -130 -> 252, step: 16
940 11:06:41.052617 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 11:06:41.055946 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 11:06:41.059137 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 11:06:41.062359 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 11:06:41.069440 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 11:06:41.072672 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 11:06:41.076233 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 11:06:41.079509 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 11:06:41.082915 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 11:06:41.089399 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
950 11:06:41.092847 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 11:06:41.096192 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 11:06:41.099423 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 11:06:41.102747 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
954 11:06:41.109587 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 11:06:41.113045 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
956 11:06:41.113613 ==
957 11:06:41.116104 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:06:41.119401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:06:41.119838 ==
960 11:06:41.123326 DQS Delay:
961 11:06:41.123846 DQS0 = 0, DQS1 = 0
962 11:06:41.124188 DQM Delay:
963 11:06:41.126187 DQM0 = 89, DQM1 = 80
964 11:06:41.126619 DQ Delay:
965 11:06:41.129251 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 11:06:41.133098 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
967 11:06:41.136322 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
968 11:06:41.140343 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
969 11:06:41.140843
970 11:06:41.141221
971 11:06:41.141538 ==
972 11:06:41.143067 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:06:41.146211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:06:41.149825 ==
975 11:06:41.150334
976 11:06:41.150668
977 11:06:41.150973 TX Vref Scan disable
978 11:06:41.153272 == TX Byte 0 ==
979 11:06:41.156362 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 11:06:41.159531 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 11:06:41.163228 == TX Byte 1 ==
982 11:06:41.166474 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 11:06:41.170063 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 11:06:41.170573 ==
985 11:06:41.173053 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:06:41.179769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:06:41.180292 ==
988 11:06:41.192327 TX Vref=22, minBit 6, minWin=27, winSum=442
989 11:06:41.195218 TX Vref=24, minBit 6, minWin=27, winSum=446
990 11:06:41.198460 TX Vref=26, minBit 6, minWin=27, winSum=448
991 11:06:41.201862 TX Vref=28, minBit 6, minWin=28, winSum=457
992 11:06:41.205258 TX Vref=30, minBit 8, minWin=27, winSum=458
993 11:06:41.208363 TX Vref=32, minBit 8, minWin=28, winSum=458
994 11:06:41.215393 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
995 11:06:41.215908
996 11:06:41.218423 Final TX Range 1 Vref 32
997 11:06:41.218850
998 11:06:41.219179 ==
999 11:06:41.221841 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:06:41.225327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:06:41.225842 ==
1002 11:06:41.226182
1003 11:06:41.226491
1004 11:06:41.228671 TX Vref Scan disable
1005 11:06:41.232110 == TX Byte 0 ==
1006 11:06:41.235420 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 11:06:41.238609 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 11:06:41.241957 == TX Byte 1 ==
1009 11:06:41.245586 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 11:06:41.248483 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 11:06:41.248912
1012 11:06:41.251864 [DATLAT]
1013 11:06:41.252363 Freq=800, CH0 RK0
1014 11:06:41.252694
1015 11:06:41.255273 DATLAT Default: 0xa
1016 11:06:41.255778 0, 0xFFFF, sum = 0
1017 11:06:41.258519 1, 0xFFFF, sum = 0
1018 11:06:41.259032 2, 0xFFFF, sum = 0
1019 11:06:41.262129 3, 0xFFFF, sum = 0
1020 11:06:41.262567 4, 0xFFFF, sum = 0
1021 11:06:41.265236 5, 0xFFFF, sum = 0
1022 11:06:41.265752 6, 0xFFFF, sum = 0
1023 11:06:41.268587 7, 0xFFFF, sum = 0
1024 11:06:41.269099 8, 0xFFFF, sum = 0
1025 11:06:41.272091 9, 0x0, sum = 1
1026 11:06:41.272607 10, 0x0, sum = 2
1027 11:06:41.275005 11, 0x0, sum = 3
1028 11:06:41.275479 12, 0x0, sum = 4
1029 11:06:41.278959 best_step = 10
1030 11:06:41.279471
1031 11:06:41.279898 ==
1032 11:06:41.281840 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:06:41.285265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:06:41.285809 ==
1035 11:06:41.288653 RX Vref Scan: 1
1036 11:06:41.289210
1037 11:06:41.289563 Set Vref Range= 32 -> 127
1038 11:06:41.289878
1039 11:06:41.292340 RX Vref 32 -> 127, step: 1
1040 11:06:41.292854
1041 11:06:41.295357 RX Delay -79 -> 252, step: 8
1042 11:06:41.295868
1043 11:06:41.298850 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:06:41.301860 [Byte1]: 32
1045 11:06:41.302295
1046 11:06:41.305579 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:06:41.308474 [Byte1]: 33
1048 11:06:41.308904
1049 11:06:41.312115 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:06:41.315333 [Byte1]: 34
1051 11:06:41.319338
1052 11:06:41.319856 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:06:41.322842 [Byte1]: 35
1054 11:06:41.326747
1055 11:06:41.327263 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:06:41.330186 [Byte1]: 36
1057 11:06:41.334369
1058 11:06:41.334892 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:06:41.337619 [Byte1]: 37
1060 11:06:41.342013
1061 11:06:41.342446 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:06:41.345462 [Byte1]: 38
1063 11:06:41.349662
1064 11:06:41.350179 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:06:41.353186 [Byte1]: 39
1066 11:06:41.357026
1067 11:06:41.357570 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:06:41.360611 [Byte1]: 40
1069 11:06:41.365006
1070 11:06:41.365542 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:06:41.368036 [Byte1]: 41
1072 11:06:41.372227
1073 11:06:41.372746 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:06:41.375458 [Byte1]: 42
1075 11:06:41.379907
1076 11:06:41.380424 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:06:41.383288 [Byte1]: 43
1078 11:06:41.387135
1079 11:06:41.387650 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:06:41.390564 [Byte1]: 44
1081 11:06:41.395074
1082 11:06:41.395601 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:06:41.398363 [Byte1]: 45
1084 11:06:41.402598
1085 11:06:41.403033 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:06:41.405964 [Byte1]: 46
1087 11:06:41.409833
1088 11:06:41.410318 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:06:41.413393 [Byte1]: 47
1090 11:06:41.417371
1091 11:06:41.417883 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:06:41.420865 [Byte1]: 48
1093 11:06:41.425081
1094 11:06:41.425638 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:06:41.428601 [Byte1]: 49
1096 11:06:41.433005
1097 11:06:41.433550 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:06:41.436109 [Byte1]: 50
1099 11:06:41.440268
1100 11:06:41.440815 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:06:41.443238 [Byte1]: 51
1102 11:06:41.447655
1103 11:06:41.448171 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:06:41.450997 [Byte1]: 52
1105 11:06:41.455104
1106 11:06:41.455615 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:06:41.458447 [Byte1]: 53
1108 11:06:41.463181
1109 11:06:41.463692 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:06:41.465906 [Byte1]: 54
1111 11:06:41.470316
1112 11:06:41.470827 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:06:41.473344 [Byte1]: 55
1114 11:06:41.477874
1115 11:06:41.478610 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:06:41.481500 [Byte1]: 56
1117 11:06:41.485521
1118 11:06:41.486074 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:06:41.488925 [Byte1]: 57
1120 11:06:41.493099
1121 11:06:41.493652 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:06:41.496423 [Byte1]: 58
1123 11:06:41.500794
1124 11:06:41.501359 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:06:41.503714 [Byte1]: 59
1126 11:06:41.508049
1127 11:06:41.508583 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:06:41.511770 [Byte1]: 60
1129 11:06:41.515479
1130 11:06:41.515913 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:06:41.519196 [Byte1]: 61
1132 11:06:41.523306
1133 11:06:41.523818 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:06:41.526480 [Byte1]: 62
1135 11:06:41.531126
1136 11:06:41.531644 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:06:41.534053 [Byte1]: 63
1138 11:06:41.538434
1139 11:06:41.538942 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:06:41.542084 [Byte1]: 64
1141 11:06:41.545465
1142 11:06:41.545918 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:06:41.548882 [Byte1]: 65
1144 11:06:41.553426
1145 11:06:41.553929 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:06:41.556551 [Byte1]: 66
1147 11:06:41.560855
1148 11:06:41.561622 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:06:41.563585 [Byte1]: 67
1150 11:06:41.567770
1151 11:06:41.567852 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:06:41.571436 [Byte1]: 68
1153 11:06:41.575471
1154 11:06:41.575578 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:06:41.578914 [Byte1]: 69
1156 11:06:41.583228
1157 11:06:41.583328 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:06:41.586425 [Byte1]: 70
1159 11:06:41.590735
1160 11:06:41.590855 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:06:41.594023 [Byte1]: 71
1162 11:06:41.597980
1163 11:06:41.598133 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:06:41.601885 [Byte1]: 72
1165 11:06:41.605863
1166 11:06:41.606248 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:06:41.609493 [Byte1]: 73
1168 11:06:41.613502
1169 11:06:41.613887 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:06:41.617240 [Byte1]: 74
1171 11:06:41.621513
1172 11:06:41.621897 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:06:41.624476 [Byte1]: 75
1174 11:06:41.629056
1175 11:06:41.629593 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:06:41.632262 [Byte1]: 76
1177 11:06:41.636613
1178 11:06:41.637120 Set Vref, RX VrefLevel [Byte0]: 77
1179 11:06:41.640003 [Byte1]: 77
1180 11:06:41.643765
1181 11:06:41.644190 Set Vref, RX VrefLevel [Byte0]: 78
1182 11:06:41.647413 [Byte1]: 78
1183 11:06:41.651916
1184 11:06:41.652424 Set Vref, RX VrefLevel [Byte0]: 79
1185 11:06:41.655105 [Byte1]: 79
1186 11:06:41.659250
1187 11:06:41.659754 Final RX Vref Byte 0 = 62 to rank0
1188 11:06:41.662584 Final RX Vref Byte 1 = 63 to rank0
1189 11:06:41.665913 Final RX Vref Byte 0 = 62 to rank1
1190 11:06:41.669272 Final RX Vref Byte 1 = 63 to rank1==
1191 11:06:41.672598 Dram Type= 6, Freq= 0, CH_0, rank 0
1192 11:06:41.678811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 11:06:41.679283 ==
1194 11:06:41.679631 DQS Delay:
1195 11:06:41.679943 DQS0 = 0, DQS1 = 0
1196 11:06:41.682441 DQM Delay:
1197 11:06:41.682943 DQM0 = 93, DQM1 = 82
1198 11:06:41.685619 DQ Delay:
1199 11:06:41.689270 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1200 11:06:41.692707 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1201 11:06:41.693265 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1202 11:06:41.699239 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =92
1203 11:06:41.699745
1204 11:06:41.700077
1205 11:06:41.705797 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1206 11:06:41.709171 CH0 RK0: MR19=606, MR18=3C37
1207 11:06:41.715878 CH0_RK0: MR19=0x606, MR18=0x3C37, DQSOSC=394, MR23=63, INC=95, DEC=63
1208 11:06:41.716405
1209 11:06:41.718925 ----->DramcWriteLeveling(PI) begin...
1210 11:06:41.719366 ==
1211 11:06:41.722747 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 11:06:41.725739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1213 11:06:41.726176 ==
1214 11:06:41.729192 Write leveling (Byte 0): 31 => 31
1215 11:06:41.732585 Write leveling (Byte 1): 28 => 28
1216 11:06:41.735517 DramcWriteLeveling(PI) end<-----
1217 11:06:41.735954
1218 11:06:41.736299 ==
1219 11:06:41.780068 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 11:06:41.780959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 11:06:41.781393 ==
1222 11:06:41.781723 [Gating] SW mode calibration
1223 11:06:41.782033 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1224 11:06:41.782337 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1225 11:06:41.782630 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1226 11:06:41.782920 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1227 11:06:41.783269 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1228 11:06:41.783562 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:06:41.783867 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:06:41.805571 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:06:41.806084 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:06:41.806518 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:06:41.807022 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:06:41.807706 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:06:41.808955 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:06:41.812402 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:06:41.815941 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:06:41.819588 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:06:41.822610 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:06:41.829011 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:06:41.832340 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:06:41.835749 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1243 11:06:41.842381 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:06:41.845628 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:06:41.849497 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:06:41.856076 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:06:41.859342 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:06:41.862332 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:06:41.869359 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:06:41.872714 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1251 11:06:41.875928 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (0 0)
1252 11:06:41.882723 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 11:06:41.885975 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 11:06:41.889352 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 11:06:41.896100 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 11:06:41.899474 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 11:06:41.902520 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 11:06:41.905903 0 10 4 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
1259 11:06:41.912791 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1260 11:06:41.916324 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:06:41.919310 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 11:06:41.925879 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 11:06:41.929546 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 11:06:41.933002 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 11:06:41.939613 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 11:06:41.942942 0 11 4 | B1->B0 | 2929 3333 | 0 1 | (1 1) (0 0)
1267 11:06:41.946665 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1268 11:06:41.952904 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:06:41.956348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 11:06:41.959822 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 11:06:41.962819 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 11:06:41.970057 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 11:06:41.973273 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 11:06:41.976528 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1275 11:06:41.983215 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1276 11:06:41.986109 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:06:41.989806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:06:41.996714 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:06:42.000113 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:06:42.003561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:06:42.009919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:06:42.013276 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:06:42.016707 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:06:42.023223 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:06:42.026315 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:06:42.029968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:06:42.036556 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:06:42.040116 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 11:06:42.043385 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 11:06:42.046654 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1291 11:06:42.053236 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1292 11:06:42.056450 Total UI for P1: 0, mck2ui 16
1293 11:06:42.060263 best dqsien dly found for B0: ( 0, 14, 4)
1294 11:06:42.063063 Total UI for P1: 0, mck2ui 16
1295 11:06:42.066951 best dqsien dly found for B1: ( 0, 14, 4)
1296 11:06:42.069996 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1297 11:06:42.073651 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1298 11:06:42.074161
1299 11:06:42.076709 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1300 11:06:42.080329 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1301 11:06:42.083681 [Gating] SW calibration Done
1302 11:06:42.084183 ==
1303 11:06:42.087089 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 11:06:42.090156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 11:06:42.090667 ==
1306 11:06:42.093644 RX Vref Scan: 0
1307 11:06:42.094150
1308 11:06:42.094489 RX Vref 0 -> 0, step: 1
1309 11:06:42.094796
1310 11:06:42.097100 RX Delay -130 -> 252, step: 16
1311 11:06:42.100110 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1312 11:06:42.106970 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1313 11:06:42.110347 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1314 11:06:42.113646 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1315 11:06:42.116942 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1316 11:06:42.120681 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1317 11:06:42.126951 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1318 11:06:42.130757 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1319 11:06:42.133535 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1320 11:06:42.136985 iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208
1321 11:06:42.140411 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
1322 11:06:42.147218 iDelay=206, Bit 11, Center 85 (-18 ~ 189) 208
1323 11:06:42.150116 iDelay=206, Bit 12, Center 85 (-18 ~ 189) 208
1324 11:06:42.153529 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1325 11:06:42.157225 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1326 11:06:42.160472 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1327 11:06:42.160977 ==
1328 11:06:42.163366 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 11:06:42.170873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 11:06:42.171443 ==
1331 11:06:42.171792 DQS Delay:
1332 11:06:42.173529 DQS0 = 0, DQS1 = 0
1333 11:06:42.173963 DQM Delay:
1334 11:06:42.174299 DQM0 = 90, DQM1 = 83
1335 11:06:42.177023 DQ Delay:
1336 11:06:42.180078 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1337 11:06:42.183718 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1338 11:06:42.186829 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =85
1339 11:06:42.190376 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1340 11:06:42.190810
1341 11:06:42.191142
1342 11:06:42.191448 ==
1343 11:06:42.193569 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 11:06:42.197320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 11:06:42.197839 ==
1346 11:06:42.198181
1347 11:06:42.198524
1348 11:06:42.200372 TX Vref Scan disable
1349 11:06:42.200833 == TX Byte 0 ==
1350 11:06:42.207071 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1351 11:06:42.210425 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1352 11:06:42.210945 == TX Byte 1 ==
1353 11:06:42.217470 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1354 11:06:42.220718 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1355 11:06:42.221281 ==
1356 11:06:42.223888 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 11:06:42.227151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 11:06:42.227670 ==
1359 11:06:42.241567 TX Vref=22, minBit 8, minWin=27, winSum=450
1360 11:06:42.244767 TX Vref=24, minBit 8, minWin=27, winSum=453
1361 11:06:42.248244 TX Vref=26, minBit 8, minWin=27, winSum=456
1362 11:06:42.251649 TX Vref=28, minBit 8, minWin=27, winSum=456
1363 11:06:42.255225 TX Vref=30, minBit 8, minWin=27, winSum=456
1364 11:06:42.258504 TX Vref=32, minBit 8, minWin=27, winSum=458
1365 11:06:42.264665 [TxChooseVref] Worse bit 8, Min win 27, Win sum 458, Final Vref 32
1366 11:06:42.265204
1367 11:06:42.268088 Final TX Range 1 Vref 32
1368 11:06:42.268602
1369 11:06:42.268939 ==
1370 11:06:42.271443 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 11:06:42.274767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 11:06:42.275201 ==
1373 11:06:42.275601
1374 11:06:42.275915
1375 11:06:42.278212 TX Vref Scan disable
1376 11:06:42.281680 == TX Byte 0 ==
1377 11:06:42.284928 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1378 11:06:42.288112 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1379 11:06:42.291711 == TX Byte 1 ==
1380 11:06:42.294862 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1381 11:06:42.298272 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1382 11:06:42.298696
1383 11:06:42.301568 [DATLAT]
1384 11:06:42.301861 Freq=800, CH0 RK1
1385 11:06:42.302088
1386 11:06:42.304959 DATLAT Default: 0xa
1387 11:06:42.305278 0, 0xFFFF, sum = 0
1388 11:06:42.308295 1, 0xFFFF, sum = 0
1389 11:06:42.308664 2, 0xFFFF, sum = 0
1390 11:06:42.311598 3, 0xFFFF, sum = 0
1391 11:06:42.311904 4, 0xFFFF, sum = 0
1392 11:06:42.315469 5, 0xFFFF, sum = 0
1393 11:06:42.315840 6, 0xFFFF, sum = 0
1394 11:06:42.318201 7, 0xFFFF, sum = 0
1395 11:06:42.318498 8, 0xFFFF, sum = 0
1396 11:06:42.321758 9, 0x0, sum = 1
1397 11:06:42.322053 10, 0x0, sum = 2
1398 11:06:42.325320 11, 0x0, sum = 3
1399 11:06:42.325695 12, 0x0, sum = 4
1400 11:06:42.328304 best_step = 10
1401 11:06:42.328669
1402 11:06:42.328896 ==
1403 11:06:42.331830 Dram Type= 6, Freq= 0, CH_0, rank 1
1404 11:06:42.335364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 11:06:42.335842 ==
1406 11:06:42.336142 RX Vref Scan: 0
1407 11:06:42.338557
1408 11:06:42.339011 RX Vref 0 -> 0, step: 1
1409 11:06:42.339307
1410 11:06:42.342003 RX Delay -79 -> 252, step: 8
1411 11:06:42.345162 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1412 11:06:42.352088 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1413 11:06:42.355354 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1414 11:06:42.358902 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1415 11:06:42.362059 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1416 11:06:42.365679 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1417 11:06:42.371932 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1418 11:06:42.375343 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1419 11:06:42.378613 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1420 11:06:42.382121 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1421 11:06:42.385424 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1422 11:06:42.392231 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1423 11:06:42.395327 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1424 11:06:42.399039 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1425 11:06:42.401896 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1426 11:06:42.405844 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1427 11:06:42.408890 ==
1428 11:06:42.409445 Dram Type= 6, Freq= 0, CH_0, rank 1
1429 11:06:42.415538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 11:06:42.416049 ==
1431 11:06:42.416389 DQS Delay:
1432 11:06:42.418824 DQS0 = 0, DQS1 = 0
1433 11:06:42.419329 DQM Delay:
1434 11:06:42.422435 DQM0 = 90, DQM1 = 80
1435 11:06:42.422937 DQ Delay:
1436 11:06:42.425908 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1437 11:06:42.428825 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1438 11:06:42.432559 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1439 11:06:42.435448 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =84
1440 11:06:42.435830
1441 11:06:42.436145
1442 11:06:42.442428 [DQSOSCAuto] RK1, (LSB)MR18= 0x4822, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1443 11:06:42.445778 CH0 RK1: MR19=606, MR18=4822
1444 11:06:42.452514 CH0_RK1: MR19=0x606, MR18=0x4822, DQSOSC=391, MR23=63, INC=96, DEC=64
1445 11:06:42.455800 [RxdqsGatingPostProcess] freq 800
1446 11:06:42.459298 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1447 11:06:42.462380 Pre-setting of DQS Precalculation
1448 11:06:42.469496 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1449 11:06:42.470006 ==
1450 11:06:42.472652 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 11:06:42.476131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 11:06:42.476644 ==
1453 11:06:42.482770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1454 11:06:42.485742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1455 11:06:42.496430 [CA 0] Center 36 (6~67) winsize 62
1456 11:06:42.499931 [CA 1] Center 37 (6~68) winsize 63
1457 11:06:42.503382 [CA 2] Center 35 (5~65) winsize 61
1458 11:06:42.506528 [CA 3] Center 34 (4~65) winsize 62
1459 11:06:42.510154 [CA 4] Center 34 (4~64) winsize 61
1460 11:06:42.513352 [CA 5] Center 33 (3~64) winsize 62
1461 11:06:42.513871
1462 11:06:42.516310 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1463 11:06:42.516820
1464 11:06:42.519929 [CATrainingPosCal] consider 1 rank data
1465 11:06:42.523420 u2DelayCellTimex100 = 270/100 ps
1466 11:06:42.526781 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1467 11:06:42.530029 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1468 11:06:42.536628 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1469 11:06:42.540090 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1470 11:06:42.543361 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1471 11:06:42.546734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1472 11:06:42.547314
1473 11:06:42.549994 CA PerBit enable=1, Macro0, CA PI delay=33
1474 11:06:42.550422
1475 11:06:42.553302 [CBTSetCACLKResult] CA Dly = 33
1476 11:06:42.553728 CS Dly: 5 (0~36)
1477 11:06:42.554056 ==
1478 11:06:42.556590 Dram Type= 6, Freq= 0, CH_1, rank 1
1479 11:06:42.563262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1480 11:06:42.563771 ==
1481 11:06:42.566474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1482 11:06:42.573324 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1483 11:06:42.582969 [CA 0] Center 37 (7~68) winsize 62
1484 11:06:42.585841 [CA 1] Center 37 (6~68) winsize 63
1485 11:06:42.589284 [CA 2] Center 35 (5~66) winsize 62
1486 11:06:42.592693 [CA 3] Center 34 (4~65) winsize 62
1487 11:06:42.596555 [CA 4] Center 34 (4~65) winsize 62
1488 11:06:42.599646 [CA 5] Center 34 (4~65) winsize 62
1489 11:06:42.600186
1490 11:06:42.602836 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1491 11:06:42.603358
1492 11:06:42.605993 [CATrainingPosCal] consider 2 rank data
1493 11:06:42.609269 u2DelayCellTimex100 = 270/100 ps
1494 11:06:42.612795 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1495 11:06:42.615940 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1496 11:06:42.622640 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1497 11:06:42.626071 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 11:06:42.629374 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1499 11:06:42.632708 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1500 11:06:42.633356
1501 11:06:42.636063 CA PerBit enable=1, Macro0, CA PI delay=34
1502 11:06:42.636564
1503 11:06:42.639580 [CBTSetCACLKResult] CA Dly = 34
1504 11:06:42.640010 CS Dly: 6 (0~38)
1505 11:06:42.640342
1506 11:06:42.642825 ----->DramcWriteLeveling(PI) begin...
1507 11:06:42.643310 ==
1508 11:06:42.646032 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 11:06:42.652735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 11:06:42.653213 ==
1511 11:06:42.656004 Write leveling (Byte 0): 25 => 25
1512 11:06:42.659427 Write leveling (Byte 1): 30 => 30
1513 11:06:42.659839 DramcWriteLeveling(PI) end<-----
1514 11:06:42.660151
1515 11:06:42.662986 ==
1516 11:06:42.666154 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 11:06:42.669654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1518 11:06:42.670042 ==
1519 11:06:42.673101 [Gating] SW mode calibration
1520 11:06:42.679934 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1521 11:06:42.682920 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1522 11:06:42.689598 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1523 11:06:42.693191 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1524 11:06:42.696684 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1525 11:06:42.703441 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:06:42.706471 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:06:42.709926 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:06:42.713563 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:06:42.720156 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:06:42.724023 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:06:42.726866 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:06:42.733616 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:06:42.736667 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:06:42.740118 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:06:42.746970 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:06:42.750605 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:06:42.753594 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:06:42.760245 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1539 11:06:42.763815 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1540 11:06:42.767087 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:06:42.774013 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:06:42.777009 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:06:42.780374 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:06:42.783451 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:06:42.790463 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:06:42.793762 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:06:42.797332 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1548 11:06:42.803965 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:06:42.807412 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:06:42.810959 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 11:06:42.817642 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 11:06:42.820720 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 11:06:42.824000 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 11:06:42.830605 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 11:06:42.833954 0 10 4 | B1->B0 | 3030 2c2c | 0 0 | (1 0) (0 0)
1556 11:06:42.837597 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:06:42.840974 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:06:42.847433 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:06:42.850665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 11:06:42.853974 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 11:06:42.860741 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 11:06:42.863877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 11:06:42.867368 0 11 4 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (0 0)
1564 11:06:42.874038 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1565 11:06:42.877636 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:06:42.880722 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 11:06:42.886908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 11:06:42.890178 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 11:06:42.893418 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 11:06:42.900180 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 11:06:42.903604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1572 11:06:42.906743 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1573 11:06:42.913559 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:06:42.916920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:06:42.920092 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:06:42.923706 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:06:42.930223 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:06:42.933732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:06:42.936928 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:06:42.943725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:06:42.946921 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:06:42.950152 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 11:06:42.957067 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 11:06:42.960575 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 11:06:42.963625 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 11:06:42.970393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 11:06:42.973920 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1588 11:06:42.976938 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1589 11:06:42.980602 Total UI for P1: 0, mck2ui 16
1590 11:06:42.983871 best dqsien dly found for B0: ( 0, 14, 4)
1591 11:06:42.987418 Total UI for P1: 0, mck2ui 16
1592 11:06:42.990425 best dqsien dly found for B1: ( 0, 14, 4)
1593 11:06:42.994227 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1594 11:06:42.997263 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1595 11:06:42.997340
1596 11:06:43.000984 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1597 11:06:43.003900 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1598 11:06:43.007726 [Gating] SW calibration Done
1599 11:06:43.007803 ==
1600 11:06:43.010788 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 11:06:43.017449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 11:06:43.017529 ==
1603 11:06:43.017589 RX Vref Scan: 0
1604 11:06:43.017644
1605 11:06:43.020682 RX Vref 0 -> 0, step: 1
1606 11:06:43.020758
1607 11:06:43.024324 RX Delay -130 -> 252, step: 16
1608 11:06:43.027265 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1609 11:06:43.030725 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1610 11:06:43.034055 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1611 11:06:43.037497 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1612 11:06:43.043928 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1613 11:06:43.047402 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1614 11:06:43.050697 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1615 11:06:43.053877 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1616 11:06:43.057392 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1617 11:06:43.064033 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1618 11:06:43.067395 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1619 11:06:43.070688 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1620 11:06:43.074216 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1621 11:06:43.077280 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1622 11:06:43.084099 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1623 11:06:43.087778 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1624 11:06:43.087920 ==
1625 11:06:43.091268 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 11:06:43.094294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 11:06:43.094461 ==
1628 11:06:43.097722 DQS Delay:
1629 11:06:43.097896 DQS0 = 0, DQS1 = 0
1630 11:06:43.097990 DQM Delay:
1631 11:06:43.101230 DQM0 = 93, DQM1 = 82
1632 11:06:43.101415 DQ Delay:
1633 11:06:43.104315 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1634 11:06:43.108062 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1635 11:06:43.111557 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1636 11:06:43.114534 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1637 11:06:43.114760
1638 11:06:43.114890
1639 11:06:43.115009 ==
1640 11:06:43.118035 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 11:06:43.124748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 11:06:43.125042 ==
1643 11:06:43.125247
1644 11:06:43.125414
1645 11:06:43.125605 TX Vref Scan disable
1646 11:06:43.128182 == TX Byte 0 ==
1647 11:06:43.131746 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1648 11:06:43.134686 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1649 11:06:43.138087 == TX Byte 1 ==
1650 11:06:43.141697 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1651 11:06:43.145238 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1652 11:06:43.148519 ==
1653 11:06:43.151526 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 11:06:43.155188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 11:06:43.155697 ==
1656 11:06:43.167499 TX Vref=22, minBit 15, minWin=26, winSum=446
1657 11:06:43.170961 TX Vref=24, minBit 10, minWin=27, winSum=451
1658 11:06:43.174460 TX Vref=26, minBit 10, minWin=27, winSum=452
1659 11:06:43.177667 TX Vref=28, minBit 15, minWin=27, winSum=455
1660 11:06:43.181249 TX Vref=30, minBit 8, minWin=27, winSum=456
1661 11:06:43.187568 TX Vref=32, minBit 8, minWin=27, winSum=453
1662 11:06:43.191251 [TxChooseVref] Worse bit 8, Min win 27, Win sum 456, Final Vref 30
1663 11:06:43.191756
1664 11:06:43.194288 Final TX Range 1 Vref 30
1665 11:06:43.194721
1666 11:06:43.195051 ==
1667 11:06:43.197514 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 11:06:43.201077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 11:06:43.204595 ==
1670 11:06:43.205098
1671 11:06:43.205487
1672 11:06:43.205800 TX Vref Scan disable
1673 11:06:43.207958 == TX Byte 0 ==
1674 11:06:43.211738 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1675 11:06:43.214824 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1676 11:06:43.218285 == TX Byte 1 ==
1677 11:06:43.221872 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1678 11:06:43.224807 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1679 11:06:43.228324
1680 11:06:43.228827 [DATLAT]
1681 11:06:43.229205 Freq=800, CH1 RK0
1682 11:06:43.229534
1683 11:06:43.231465 DATLAT Default: 0xa
1684 11:06:43.231966 0, 0xFFFF, sum = 0
1685 11:06:43.234849 1, 0xFFFF, sum = 0
1686 11:06:43.235364 2, 0xFFFF, sum = 0
1687 11:06:43.238020 3, 0xFFFF, sum = 0
1688 11:06:43.238534 4, 0xFFFF, sum = 0
1689 11:06:43.241601 5, 0xFFFF, sum = 0
1690 11:06:43.242111 6, 0xFFFF, sum = 0
1691 11:06:43.245056 7, 0xFFFF, sum = 0
1692 11:06:43.245655 8, 0xFFFF, sum = 0
1693 11:06:43.247927 9, 0x0, sum = 1
1694 11:06:43.248366 10, 0x0, sum = 2
1695 11:06:43.251412 11, 0x0, sum = 3
1696 11:06:43.251968 12, 0x0, sum = 4
1697 11:06:43.254994 best_step = 10
1698 11:06:43.255496
1699 11:06:43.255834 ==
1700 11:06:43.258013 Dram Type= 6, Freq= 0, CH_1, rank 0
1701 11:06:43.261728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1702 11:06:43.262248 ==
1703 11:06:43.264999 RX Vref Scan: 1
1704 11:06:43.265467
1705 11:06:43.265804 Set Vref Range= 32 -> 127
1706 11:06:43.266119
1707 11:06:43.267903 RX Vref 32 -> 127, step: 1
1708 11:06:43.268038
1709 11:06:43.271274 RX Delay -95 -> 252, step: 8
1710 11:06:43.271412
1711 11:06:43.274948 Set Vref, RX VrefLevel [Byte0]: 32
1712 11:06:43.278119 [Byte1]: 32
1713 11:06:43.278242
1714 11:06:43.281496 Set Vref, RX VrefLevel [Byte0]: 33
1715 11:06:43.284756 [Byte1]: 33
1716 11:06:43.288000
1717 11:06:43.288139 Set Vref, RX VrefLevel [Byte0]: 34
1718 11:06:43.291289 [Byte1]: 34
1719 11:06:43.295828
1720 11:06:43.295980 Set Vref, RX VrefLevel [Byte0]: 35
1721 11:06:43.299025 [Byte1]: 35
1722 11:06:43.303216
1723 11:06:43.303377 Set Vref, RX VrefLevel [Byte0]: 36
1724 11:06:43.306300 [Byte1]: 36
1725 11:06:43.311120
1726 11:06:43.311593 Set Vref, RX VrefLevel [Byte0]: 37
1727 11:06:43.314393 [Byte1]: 37
1728 11:06:43.318697
1729 11:06:43.319207 Set Vref, RX VrefLevel [Byte0]: 38
1730 11:06:43.322063 [Byte1]: 38
1731 11:06:43.326106
1732 11:06:43.326617 Set Vref, RX VrefLevel [Byte0]: 39
1733 11:06:43.329901 [Byte1]: 39
1734 11:06:43.333977
1735 11:06:43.334487 Set Vref, RX VrefLevel [Byte0]: 40
1736 11:06:43.337355 [Byte1]: 40
1737 11:06:43.341700
1738 11:06:43.342209 Set Vref, RX VrefLevel [Byte0]: 41
1739 11:06:43.345067 [Byte1]: 41
1740 11:06:43.349301
1741 11:06:43.350022 Set Vref, RX VrefLevel [Byte0]: 42
1742 11:06:43.352289 [Byte1]: 42
1743 11:06:43.356889
1744 11:06:43.357448 Set Vref, RX VrefLevel [Byte0]: 43
1745 11:06:43.359999 [Byte1]: 43
1746 11:06:43.364215
1747 11:06:43.364657 Set Vref, RX VrefLevel [Byte0]: 44
1748 11:06:43.367576 [Byte1]: 44
1749 11:06:43.371868
1750 11:06:43.372375 Set Vref, RX VrefLevel [Byte0]: 45
1751 11:06:43.375258 [Byte1]: 45
1752 11:06:43.379496
1753 11:06:43.380053 Set Vref, RX VrefLevel [Byte0]: 46
1754 11:06:43.382577 [Byte1]: 46
1755 11:06:43.386901
1756 11:06:43.387338 Set Vref, RX VrefLevel [Byte0]: 47
1757 11:06:43.390461 [Byte1]: 47
1758 11:06:43.394515
1759 11:06:43.395021 Set Vref, RX VrefLevel [Byte0]: 48
1760 11:06:43.398107 [Byte1]: 48
1761 11:06:43.402463
1762 11:06:43.402979 Set Vref, RX VrefLevel [Byte0]: 49
1763 11:06:43.405398 [Byte1]: 49
1764 11:06:43.409922
1765 11:06:43.410435 Set Vref, RX VrefLevel [Byte0]: 50
1766 11:06:43.413099 [Byte1]: 50
1767 11:06:43.417633
1768 11:06:43.418155 Set Vref, RX VrefLevel [Byte0]: 51
1769 11:06:43.421146 [Byte1]: 51
1770 11:06:43.424795
1771 11:06:43.425260 Set Vref, RX VrefLevel [Byte0]: 52
1772 11:06:43.428351 [Byte1]: 52
1773 11:06:43.432493
1774 11:06:43.432930 Set Vref, RX VrefLevel [Byte0]: 53
1775 11:06:43.435956 [Byte1]: 53
1776 11:06:43.440437
1777 11:06:43.440943 Set Vref, RX VrefLevel [Byte0]: 54
1778 11:06:43.443817 [Byte1]: 54
1779 11:06:43.448010
1780 11:06:43.448446 Set Vref, RX VrefLevel [Byte0]: 55
1781 11:06:43.451114 [Byte1]: 55
1782 11:06:43.455293
1783 11:06:43.455793 Set Vref, RX VrefLevel [Byte0]: 56
1784 11:06:43.458589 [Byte1]: 56
1785 11:06:43.462736
1786 11:06:43.463168 Set Vref, RX VrefLevel [Byte0]: 57
1787 11:06:43.466263 [Byte1]: 57
1788 11:06:43.470621
1789 11:06:43.471123 Set Vref, RX VrefLevel [Byte0]: 58
1790 11:06:43.474006 [Byte1]: 58
1791 11:06:43.478104
1792 11:06:43.478608 Set Vref, RX VrefLevel [Byte0]: 59
1793 11:06:43.481858 [Byte1]: 59
1794 11:06:43.485513
1795 11:06:43.486073 Set Vref, RX VrefLevel [Byte0]: 60
1796 11:06:43.489463 [Byte1]: 60
1797 11:06:43.493316
1798 11:06:43.493816 Set Vref, RX VrefLevel [Byte0]: 61
1799 11:06:43.496674 [Byte1]: 61
1800 11:06:43.501091
1801 11:06:43.501639 Set Vref, RX VrefLevel [Byte0]: 62
1802 11:06:43.504391 [Byte1]: 62
1803 11:06:43.508682
1804 11:06:43.509241 Set Vref, RX VrefLevel [Byte0]: 63
1805 11:06:43.511902 [Byte1]: 63
1806 11:06:43.516519
1807 11:06:43.517032 Set Vref, RX VrefLevel [Byte0]: 64
1808 11:06:43.519777 [Byte1]: 64
1809 11:06:43.523666
1810 11:06:43.527329 Set Vref, RX VrefLevel [Byte0]: 65
1811 11:06:43.527838 [Byte1]: 65
1812 11:06:43.531167
1813 11:06:43.531595 Set Vref, RX VrefLevel [Byte0]: 66
1814 11:06:43.534845 [Byte1]: 66
1815 11:06:43.539055
1816 11:06:43.539556 Set Vref, RX VrefLevel [Byte0]: 67
1817 11:06:43.542816 [Byte1]: 67
1818 11:06:43.546990
1819 11:06:43.547491 Set Vref, RX VrefLevel [Byte0]: 68
1820 11:06:43.549857 [Byte1]: 68
1821 11:06:43.554088
1822 11:06:43.554596 Set Vref, RX VrefLevel [Byte0]: 69
1823 11:06:43.557405 [Byte1]: 69
1824 11:06:43.562333
1825 11:06:43.562834 Set Vref, RX VrefLevel [Byte0]: 70
1826 11:06:43.565272 [Byte1]: 70
1827 11:06:43.569588
1828 11:06:43.570103 Set Vref, RX VrefLevel [Byte0]: 71
1829 11:06:43.572949 [Byte1]: 71
1830 11:06:43.577008
1831 11:06:43.577488 Set Vref, RX VrefLevel [Byte0]: 72
1832 11:06:43.580585 [Byte1]: 72
1833 11:06:43.584601
1834 11:06:43.585104 Set Vref, RX VrefLevel [Byte0]: 73
1835 11:06:43.587669 [Byte1]: 73
1836 11:06:43.592505
1837 11:06:43.593012 Set Vref, RX VrefLevel [Byte0]: 74
1838 11:06:43.595824 [Byte1]: 74
1839 11:06:43.599560
1840 11:06:43.600070 Set Vref, RX VrefLevel [Byte0]: 75
1841 11:06:43.603324 [Byte1]: 75
1842 11:06:43.607500
1843 11:06:43.608010 Final RX Vref Byte 0 = 52 to rank0
1844 11:06:43.610572 Final RX Vref Byte 1 = 63 to rank0
1845 11:06:43.614107 Final RX Vref Byte 0 = 52 to rank1
1846 11:06:43.617471 Final RX Vref Byte 1 = 63 to rank1==
1847 11:06:43.620665 Dram Type= 6, Freq= 0, CH_1, rank 0
1848 11:06:43.624346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 11:06:43.627605 ==
1850 11:06:43.628156 DQS Delay:
1851 11:06:43.628498 DQS0 = 0, DQS1 = 0
1852 11:06:43.630469 DQM Delay:
1853 11:06:43.630904 DQM0 = 92, DQM1 = 83
1854 11:06:43.634370 DQ Delay:
1855 11:06:43.637181 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1856 11:06:43.637619 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1857 11:06:43.640925 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1858 11:06:43.644338 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1859 11:06:43.647464
1860 11:06:43.647969
1861 11:06:43.654198 [DQSOSCAuto] RK0, (LSB)MR18= 0x3351, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1862 11:06:43.657232 CH1 RK0: MR19=606, MR18=3351
1863 11:06:43.664182 CH1_RK0: MR19=0x606, MR18=0x3351, DQSOSC=389, MR23=63, INC=97, DEC=65
1864 11:06:43.664729
1865 11:06:43.667283 ----->DramcWriteLeveling(PI) begin...
1866 11:06:43.667841 ==
1867 11:06:43.671074 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 11:06:43.673914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 11:06:43.674467 ==
1870 11:06:43.677572 Write leveling (Byte 0): 26 => 26
1871 11:06:43.680475 Write leveling (Byte 1): 27 => 27
1872 11:06:43.683875 DramcWriteLeveling(PI) end<-----
1873 11:06:43.684337
1874 11:06:43.684775 ==
1875 11:06:43.687335 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 11:06:43.691200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 11:06:43.691707 ==
1878 11:06:43.694210 [Gating] SW mode calibration
1879 11:06:43.700953 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1880 11:06:43.707634 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1881 11:06:43.710737 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1882 11:06:43.714271 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1883 11:06:43.720949 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:06:43.724787 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:06:43.727747 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:06:43.734429 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:06:43.737936 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:06:43.741048 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:06:43.744261 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:06:43.750946 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:06:43.754800 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:06:43.757879 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:06:43.764835 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:06:43.768290 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:06:43.771363 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:06:43.777944 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:06:43.781391 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1898 11:06:43.784917 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1899 11:06:43.791715 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:06:43.794856 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:06:43.798417 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:06:43.801766 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:06:43.808156 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:06:43.811788 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:06:43.815263 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:06:43.821194 0 9 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1907 11:06:43.824711 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1908 11:06:43.828269 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 11:06:43.834741 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 11:06:43.838175 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 11:06:43.841439 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 11:06:43.848260 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 11:06:43.851792 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 11:06:43.854829 0 10 4 | B1->B0 | 2d2d 3131 | 1 1 | (1 0) (0 1)
1915 11:06:43.861760 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1916 11:06:43.865019 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:06:43.868409 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 11:06:43.874880 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 11:06:43.878129 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:06:43.881531 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:06:43.884866 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:06:43.891778 0 11 4 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
1923 11:06:43.894756 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 11:06:43.898477 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 11:06:43.905029 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 11:06:43.908535 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 11:06:43.911742 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 11:06:43.918728 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 11:06:43.921556 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 11:06:43.925056 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1931 11:06:43.931843 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:06:43.935491 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:06:43.938409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:06:43.945114 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:06:43.948774 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:06:43.951789 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:06:43.955578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:06:43.962384 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:06:43.965740 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:06:43.968639 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:06:43.975586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:06:43.978737 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:06:43.982104 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:06:43.989340 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:06:43.992605 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1946 11:06:43.995803 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1947 11:06:44.002576 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 11:06:44.003106 Total UI for P1: 0, mck2ui 16
1949 11:06:44.008943 best dqsien dly found for B0: ( 0, 14, 4)
1950 11:06:44.009547 Total UI for P1: 0, mck2ui 16
1951 11:06:44.012508 best dqsien dly found for B1: ( 0, 14, 2)
1952 11:06:44.015905 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1953 11:06:44.022521 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1954 11:06:44.023045
1955 11:06:44.025918 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 11:06:44.029320 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1957 11:06:44.032638 [Gating] SW calibration Done
1958 11:06:44.033197 ==
1959 11:06:44.035827 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 11:06:44.039162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 11:06:44.039613 ==
1962 11:06:44.040203 RX Vref Scan: 0
1963 11:06:44.040625
1964 11:06:44.042227 RX Vref 0 -> 0, step: 1
1965 11:06:44.042669
1966 11:06:44.045698 RX Delay -130 -> 252, step: 16
1967 11:06:44.049595 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1968 11:06:44.052319 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1969 11:06:44.058985 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1970 11:06:44.062441 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1971 11:06:44.065975 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1972 11:06:44.069115 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1973 11:06:44.072522 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1974 11:06:44.079170 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1975 11:06:44.082764 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1976 11:06:44.085896 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1977 11:06:44.088818 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1978 11:06:44.092371 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1979 11:06:44.099569 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1980 11:06:44.102831 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1981 11:06:44.106140 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1982 11:06:44.109559 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1983 11:06:44.110258 ==
1984 11:06:44.113204 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 11:06:44.115720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 11:06:44.119509 ==
1987 11:06:44.120017 DQS Delay:
1988 11:06:44.120354 DQS0 = 0, DQS1 = 0
1989 11:06:44.122678 DQM Delay:
1990 11:06:44.123191 DQM0 = 92, DQM1 = 84
1991 11:06:44.125868 DQ Delay:
1992 11:06:44.126300 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1993 11:06:44.129362 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1994 11:06:44.133069 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1995 11:06:44.136294 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1996 11:06:44.139814
1997 11:06:44.140341
1998 11:06:44.140787 ==
1999 11:06:44.143362 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 11:06:44.145732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 11:06:44.146183 ==
2002 11:06:44.146625
2003 11:06:44.147040
2004 11:06:44.149781 TX Vref Scan disable
2005 11:06:44.150314 == TX Byte 0 ==
2006 11:06:44.155777 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2007 11:06:44.159408 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2008 11:06:44.159940 == TX Byte 1 ==
2009 11:06:44.165808 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2010 11:06:44.169102 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2011 11:06:44.169595 ==
2012 11:06:44.173028 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 11:06:44.176074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 11:06:44.176608 ==
2015 11:06:44.189486 TX Vref=22, minBit 8, minWin=27, winSum=452
2016 11:06:44.192746 TX Vref=24, minBit 1, minWin=28, winSum=454
2017 11:06:44.195937 TX Vref=26, minBit 1, minWin=28, winSum=456
2018 11:06:44.199748 TX Vref=28, minBit 8, minWin=28, winSum=459
2019 11:06:44.203276 TX Vref=30, minBit 8, minWin=28, winSum=461
2020 11:06:44.206273 TX Vref=32, minBit 8, minWin=28, winSum=458
2021 11:06:44.213082 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
2022 11:06:44.213643
2023 11:06:44.216628 Final TX Range 1 Vref 30
2024 11:06:44.217180
2025 11:06:44.217530 ==
2026 11:06:44.219466 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 11:06:44.223092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 11:06:44.223604 ==
2029 11:06:44.223943
2030 11:06:44.224251
2031 11:06:44.226715 TX Vref Scan disable
2032 11:06:44.229622 == TX Byte 0 ==
2033 11:06:44.233102 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2034 11:06:44.236408 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2035 11:06:44.239855 == TX Byte 1 ==
2036 11:06:44.243382 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2037 11:06:44.246264 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2038 11:06:44.246797
2039 11:06:44.249535 [DATLAT]
2040 11:06:44.250071 Freq=800, CH1 RK1
2041 11:06:44.250518
2042 11:06:44.252845 DATLAT Default: 0xa
2043 11:06:44.253321 0, 0xFFFF, sum = 0
2044 11:06:44.256544 1, 0xFFFF, sum = 0
2045 11:06:44.257085 2, 0xFFFF, sum = 0
2046 11:06:44.259801 3, 0xFFFF, sum = 0
2047 11:06:44.260341 4, 0xFFFF, sum = 0
2048 11:06:44.262933 5, 0xFFFF, sum = 0
2049 11:06:44.263391 6, 0xFFFF, sum = 0
2050 11:06:44.266020 7, 0xFFFF, sum = 0
2051 11:06:44.266475 8, 0xFFFF, sum = 0
2052 11:06:44.269623 9, 0x0, sum = 1
2053 11:06:44.270163 10, 0x0, sum = 2
2054 11:06:44.273034 11, 0x0, sum = 3
2055 11:06:44.273597 12, 0x0, sum = 4
2056 11:06:44.276491 best_step = 10
2057 11:06:44.277008
2058 11:06:44.277411 ==
2059 11:06:44.279542 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 11:06:44.282789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 11:06:44.283244 ==
2062 11:06:44.286235 RX Vref Scan: 0
2063 11:06:44.286679
2064 11:06:44.287115 RX Vref 0 -> 0, step: 1
2065 11:06:44.287528
2066 11:06:44.289648 RX Delay -95 -> 252, step: 8
2067 11:06:44.296389 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2068 11:06:44.299638 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2069 11:06:44.303063 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2070 11:06:44.306158 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2071 11:06:44.309818 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2072 11:06:44.313198 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2073 11:06:44.319622 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2074 11:06:44.323253 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2075 11:06:44.326032 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2076 11:06:44.329365 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2077 11:06:44.332934 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2078 11:06:44.339318 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2079 11:06:44.342787 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2080 11:06:44.346317 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2081 11:06:44.349417 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2082 11:06:44.352876 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2083 11:06:44.356084 ==
2084 11:06:44.359518 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 11:06:44.362813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 11:06:44.363023 ==
2087 11:06:44.363141 DQS Delay:
2088 11:06:44.366116 DQS0 = 0, DQS1 = 0
2089 11:06:44.366322 DQM Delay:
2090 11:06:44.369598 DQM0 = 91, DQM1 = 84
2091 11:06:44.369831 DQ Delay:
2092 11:06:44.373073 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2093 11:06:44.376557 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2094 11:06:44.379781 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2095 11:06:44.383624 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92
2096 11:06:44.383979
2097 11:06:44.384201
2098 11:06:44.389859 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2099 11:06:44.393191 CH1 RK1: MR19=606, MR18=3E13
2100 11:06:44.400540 CH1_RK1: MR19=0x606, MR18=0x3E13, DQSOSC=394, MR23=63, INC=95, DEC=63
2101 11:06:44.403318 [RxdqsGatingPostProcess] freq 800
2102 11:06:44.406682 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 11:06:44.409809 Pre-setting of DQS Precalculation
2104 11:06:44.417121 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 11:06:44.423964 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 11:06:44.430144 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 11:06:44.430662
2108 11:06:44.430997
2109 11:06:44.433564 [Calibration Summary] 1600 Mbps
2110 11:06:44.434092 CH 0, Rank 0
2111 11:06:44.436619 SW Impedance : PASS
2112 11:06:44.440143 DUTY Scan : NO K
2113 11:06:44.440656 ZQ Calibration : PASS
2114 11:06:44.443648 Jitter Meter : NO K
2115 11:06:44.447093 CBT Training : PASS
2116 11:06:44.447610 Write leveling : PASS
2117 11:06:44.450043 RX DQS gating : PASS
2118 11:06:44.453433 RX DQ/DQS(RDDQC) : PASS
2119 11:06:44.453866 TX DQ/DQS : PASS
2120 11:06:44.456836 RX DATLAT : PASS
2121 11:06:44.460197 RX DQ/DQS(Engine): PASS
2122 11:06:44.460714 TX OE : NO K
2123 11:06:44.461057 All Pass.
2124 11:06:44.461431
2125 11:06:44.463443 CH 0, Rank 1
2126 11:06:44.463963 SW Impedance : PASS
2127 11:06:44.466851 DUTY Scan : NO K
2128 11:06:44.470262 ZQ Calibration : PASS
2129 11:06:44.470858 Jitter Meter : NO K
2130 11:06:44.473742 CBT Training : PASS
2131 11:06:44.476948 Write leveling : PASS
2132 11:06:44.477522 RX DQS gating : PASS
2133 11:06:44.480503 RX DQ/DQS(RDDQC) : PASS
2134 11:06:44.483337 TX DQ/DQS : PASS
2135 11:06:44.483910 RX DATLAT : PASS
2136 11:06:44.486771 RX DQ/DQS(Engine): PASS
2137 11:06:44.489844 TX OE : NO K
2138 11:06:44.490285 All Pass.
2139 11:06:44.490620
2140 11:06:44.490930 CH 1, Rank 0
2141 11:06:44.493419 SW Impedance : PASS
2142 11:06:44.496974 DUTY Scan : NO K
2143 11:06:44.497558 ZQ Calibration : PASS
2144 11:06:44.500343 Jitter Meter : NO K
2145 11:06:44.503537 CBT Training : PASS
2146 11:06:44.504065 Write leveling : PASS
2147 11:06:44.506788 RX DQS gating : PASS
2148 11:06:44.507307 RX DQ/DQS(RDDQC) : PASS
2149 11:06:44.510175 TX DQ/DQS : PASS
2150 11:06:44.513267 RX DATLAT : PASS
2151 11:06:44.513800 RX DQ/DQS(Engine): PASS
2152 11:06:44.516962 TX OE : NO K
2153 11:06:44.517520 All Pass.
2154 11:06:44.517854
2155 11:06:44.520063 CH 1, Rank 1
2156 11:06:44.520585 SW Impedance : PASS
2157 11:06:44.523466 DUTY Scan : NO K
2158 11:06:44.526847 ZQ Calibration : PASS
2159 11:06:44.527283 Jitter Meter : NO K
2160 11:06:44.529779 CBT Training : PASS
2161 11:06:44.533197 Write leveling : PASS
2162 11:06:44.533635 RX DQS gating : PASS
2163 11:06:44.536804 RX DQ/DQS(RDDQC) : PASS
2164 11:06:44.540299 TX DQ/DQS : PASS
2165 11:06:44.540817 RX DATLAT : PASS
2166 11:06:44.543735 RX DQ/DQS(Engine): PASS
2167 11:06:44.544253 TX OE : NO K
2168 11:06:44.546812 All Pass.
2169 11:06:44.547324
2170 11:06:44.547657 DramC Write-DBI off
2171 11:06:44.550409 PER_BANK_REFRESH: Hybrid Mode
2172 11:06:44.553532 TX_TRACKING: ON
2173 11:06:44.557113 [GetDramInforAfterCalByMRR] Vendor 6.
2174 11:06:44.560043 [GetDramInforAfterCalByMRR] Revision 606.
2175 11:06:44.563626 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 11:06:44.564143 MR0 0x3b3b
2177 11:06:44.564483 MR8 0x5151
2178 11:06:44.570329 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 11:06:44.570899
2180 11:06:44.571254 MR0 0x3b3b
2181 11:06:44.571568 MR8 0x5151
2182 11:06:44.573921 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 11:06:44.574440
2184 11:06:44.583919 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 11:06:44.587346 [FAST_K] Save calibration result to emmc
2186 11:06:44.590245 [FAST_K] Save calibration result to emmc
2187 11:06:44.593690 dram_init: config_dvfs: 1
2188 11:06:44.597152 dramc_set_vcore_voltage set vcore to 662500
2189 11:06:44.600605 Read voltage for 1200, 2
2190 11:06:44.601115 Vio18 = 0
2191 11:06:44.601494 Vcore = 662500
2192 11:06:44.604218 Vdram = 0
2193 11:06:44.604732 Vddq = 0
2194 11:06:44.605072 Vmddr = 0
2195 11:06:44.610656 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 11:06:44.614085 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 11:06:44.617534 MEM_TYPE=3, freq_sel=15
2198 11:06:44.620903 sv_algorithm_assistance_LP4_1600
2199 11:06:44.624207 ============ PULL DRAM RESETB DOWN ============
2200 11:06:44.627403 ========== PULL DRAM RESETB DOWN end =========
2201 11:06:44.633795 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 11:06:44.637525 ===================================
2203 11:06:44.638040 LPDDR4 DRAM CONFIGURATION
2204 11:06:44.640940 ===================================
2205 11:06:44.644329 EX_ROW_EN[0] = 0x0
2206 11:06:44.647693 EX_ROW_EN[1] = 0x0
2207 11:06:44.648204 LP4Y_EN = 0x0
2208 11:06:44.650712 WORK_FSP = 0x0
2209 11:06:44.651145 WL = 0x4
2210 11:06:44.654093 RL = 0x4
2211 11:06:44.654525 BL = 0x2
2212 11:06:44.657771 RPST = 0x0
2213 11:06:44.658283 RD_PRE = 0x0
2214 11:06:44.660859 WR_PRE = 0x1
2215 11:06:44.661413 WR_PST = 0x0
2216 11:06:44.664110 DBI_WR = 0x0
2217 11:06:44.664617 DBI_RD = 0x0
2218 11:06:44.667369 OTF = 0x1
2219 11:06:44.670681 ===================================
2220 11:06:44.674419 ===================================
2221 11:06:44.674932 ANA top config
2222 11:06:44.677715 ===================================
2223 11:06:44.680960 DLL_ASYNC_EN = 0
2224 11:06:44.684260 ALL_SLAVE_EN = 0
2225 11:06:44.684770 NEW_RANK_MODE = 1
2226 11:06:44.687222 DLL_IDLE_MODE = 1
2227 11:06:44.690572 LP45_APHY_COMB_EN = 1
2228 11:06:44.694235 TX_ODT_DIS = 1
2229 11:06:44.695026 NEW_8X_MODE = 1
2230 11:06:44.697584 ===================================
2231 11:06:44.701035 ===================================
2232 11:06:44.703980 data_rate = 2400
2233 11:06:44.707199 CKR = 1
2234 11:06:44.710688 DQ_P2S_RATIO = 8
2235 11:06:44.714345 ===================================
2236 11:06:44.717557 CA_P2S_RATIO = 8
2237 11:06:44.721059 DQ_CA_OPEN = 0
2238 11:06:44.722054 DQ_SEMI_OPEN = 0
2239 11:06:44.724211 CA_SEMI_OPEN = 0
2240 11:06:44.727861 CA_FULL_RATE = 0
2241 11:06:44.731263 DQ_CKDIV4_EN = 0
2242 11:06:44.734243 CA_CKDIV4_EN = 0
2243 11:06:44.737856 CA_PREDIV_EN = 0
2244 11:06:44.738667 PH8_DLY = 17
2245 11:06:44.741350 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 11:06:44.744527 DQ_AAMCK_DIV = 4
2247 11:06:44.747607 CA_AAMCK_DIV = 4
2248 11:06:44.751232 CA_ADMCK_DIV = 4
2249 11:06:44.751620 DQ_TRACK_CA_EN = 0
2250 11:06:44.754390 CA_PICK = 1200
2251 11:06:44.758559 CA_MCKIO = 1200
2252 11:06:44.761336 MCKIO_SEMI = 0
2253 11:06:44.764895 PLL_FREQ = 2366
2254 11:06:44.767949 DQ_UI_PI_RATIO = 32
2255 11:06:44.771511 CA_UI_PI_RATIO = 0
2256 11:06:44.775043 ===================================
2257 11:06:44.777847 ===================================
2258 11:06:44.778240 memory_type:LPDDR4
2259 11:06:44.781529 GP_NUM : 10
2260 11:06:44.784930 SRAM_EN : 1
2261 11:06:44.785503 MD32_EN : 0
2262 11:06:44.788045 ===================================
2263 11:06:44.791361 [ANA_INIT] >>>>>>>>>>>>>>
2264 11:06:44.794819 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 11:06:44.798272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 11:06:44.801516 ===================================
2267 11:06:44.804930 data_rate = 2400,PCW = 0X5b00
2268 11:06:44.808369 ===================================
2269 11:06:44.811201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 11:06:44.815289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 11:06:44.821356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 11:06:44.824702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 11:06:44.828480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 11:06:44.831601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 11:06:44.834621 [ANA_INIT] flow start
2276 11:06:44.838007 [ANA_INIT] PLL >>>>>>>>
2277 11:06:44.838442 [ANA_INIT] PLL <<<<<<<<
2278 11:06:44.841732 [ANA_INIT] MIDPI >>>>>>>>
2279 11:06:44.844890 [ANA_INIT] MIDPI <<<<<<<<
2280 11:06:44.845359 [ANA_INIT] DLL >>>>>>>>
2281 11:06:44.848193 [ANA_INIT] DLL <<<<<<<<
2282 11:06:44.851396 [ANA_INIT] flow end
2283 11:06:44.854867 ============ LP4 DIFF to SE enter ============
2284 11:06:44.858596 ============ LP4 DIFF to SE exit ============
2285 11:06:44.861834 [ANA_INIT] <<<<<<<<<<<<<
2286 11:06:44.864855 [Flow] Enable top DCM control >>>>>
2287 11:06:44.868117 [Flow] Enable top DCM control <<<<<
2288 11:06:44.871967 Enable DLL master slave shuffle
2289 11:06:44.874784 ==============================================================
2290 11:06:44.878234 Gating Mode config
2291 11:06:44.881659 ==============================================================
2292 11:06:44.885284 Config description:
2293 11:06:44.895160 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 11:06:44.902027 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 11:06:44.905511 SELPH_MODE 0: By rank 1: By Phase
2296 11:06:44.911812 ==============================================================
2297 11:06:44.915086 GAT_TRACK_EN = 1
2298 11:06:44.918403 RX_GATING_MODE = 2
2299 11:06:44.922092 RX_GATING_TRACK_MODE = 2
2300 11:06:44.925480 SELPH_MODE = 1
2301 11:06:44.926002 PICG_EARLY_EN = 1
2302 11:06:44.928611 VALID_LAT_VALUE = 1
2303 11:06:44.935044 ==============================================================
2304 11:06:44.938454 Enter into Gating configuration >>>>
2305 11:06:44.942515 Exit from Gating configuration <<<<
2306 11:06:44.945219 Enter into DVFS_PRE_config >>>>>
2307 11:06:44.955388 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 11:06:44.958815 Exit from DVFS_PRE_config <<<<<
2309 11:06:44.962054 Enter into PICG configuration >>>>
2310 11:06:44.965329 Exit from PICG configuration <<<<
2311 11:06:44.968769 [RX_INPUT] configuration >>>>>
2312 11:06:44.972328 [RX_INPUT] configuration <<<<<
2313 11:06:44.975494 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 11:06:44.982583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 11:06:44.989216 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 11:06:44.992384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 11:06:44.999255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 11:06:45.006113 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 11:06:45.009353 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 11:06:45.012756 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 11:06:45.019408 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 11:06:45.022599 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 11:06:45.026100 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 11:06:45.032631 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 11:06:45.036099 ===================================
2326 11:06:45.036614 LPDDR4 DRAM CONFIGURATION
2327 11:06:45.039209 ===================================
2328 11:06:45.042523 EX_ROW_EN[0] = 0x0
2329 11:06:45.043054 EX_ROW_EN[1] = 0x0
2330 11:06:45.046102 LP4Y_EN = 0x0
2331 11:06:45.049351 WORK_FSP = 0x0
2332 11:06:45.049862 WL = 0x4
2333 11:06:45.052754 RL = 0x4
2334 11:06:45.053313 BL = 0x2
2335 11:06:45.056041 RPST = 0x0
2336 11:06:45.056581 RD_PRE = 0x0
2337 11:06:45.059197 WR_PRE = 0x1
2338 11:06:45.059706 WR_PST = 0x0
2339 11:06:45.062632 DBI_WR = 0x0
2340 11:06:45.063142 DBI_RD = 0x0
2341 11:06:45.065956 OTF = 0x1
2342 11:06:45.069675 ===================================
2343 11:06:45.072618 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 11:06:45.075976 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 11:06:45.079701 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 11:06:45.083004 ===================================
2347 11:06:45.086057 LPDDR4 DRAM CONFIGURATION
2348 11:06:45.089247 ===================================
2349 11:06:45.092613 EX_ROW_EN[0] = 0x10
2350 11:06:45.093040 EX_ROW_EN[1] = 0x0
2351 11:06:45.096291 LP4Y_EN = 0x0
2352 11:06:45.096803 WORK_FSP = 0x0
2353 11:06:45.099926 WL = 0x4
2354 11:06:45.100436 RL = 0x4
2355 11:06:45.103134 BL = 0x2
2356 11:06:45.103637 RPST = 0x0
2357 11:06:45.106407 RD_PRE = 0x0
2358 11:06:45.106914 WR_PRE = 0x1
2359 11:06:45.109660 WR_PST = 0x0
2360 11:06:45.110174 DBI_WR = 0x0
2361 11:06:45.112592 DBI_RD = 0x0
2362 11:06:45.113022 OTF = 0x1
2363 11:06:45.116496 ===================================
2364 11:06:45.123013 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 11:06:45.123526 ==
2366 11:06:45.126552 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 11:06:45.133267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 11:06:45.133786 ==
2369 11:06:45.134126 [Duty_Offset_Calibration]
2370 11:06:45.136271 B0:2 B1:0 CA:1
2371 11:06:45.136691
2372 11:06:45.139655 [DutyScan_Calibration_Flow] k_type=0
2373 11:06:45.147454
2374 11:06:45.147888 ==CLK 0==
2375 11:06:45.150797 Final CLK duty delay cell = -4
2376 11:06:45.154330 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2377 11:06:45.157678 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2378 11:06:45.160913 [-4] AVG Duty = 4953%(X100)
2379 11:06:45.161380
2380 11:06:45.164895 CH0 CLK Duty spec in!! Max-Min= 156%
2381 11:06:45.167857 [DutyScan_Calibration_Flow] ====Done====
2382 11:06:45.168155
2383 11:06:45.170935 [DutyScan_Calibration_Flow] k_type=1
2384 11:06:45.186493
2385 11:06:45.186873 ==DQS 0 ==
2386 11:06:45.189615 Final DQS duty delay cell = 0
2387 11:06:45.193151 [0] MAX Duty = 5187%(X100), DQS PI = 30
2388 11:06:45.196403 [0] MIN Duty = 4938%(X100), DQS PI = 0
2389 11:06:45.196833 [0] AVG Duty = 5062%(X100)
2390 11:06:45.199683
2391 11:06:45.200105 ==DQS 1 ==
2392 11:06:45.203480 Final DQS duty delay cell = -4
2393 11:06:45.206703 [-4] MAX Duty = 5124%(X100), DQS PI = 34
2394 11:06:45.209815 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2395 11:06:45.213036 [-4] AVG Duty = 5015%(X100)
2396 11:06:45.213486
2397 11:06:45.216591 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2398 11:06:45.217100
2399 11:06:45.220205 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2400 11:06:45.223322 [DutyScan_Calibration_Flow] ====Done====
2401 11:06:45.223835
2402 11:06:45.226961 [DutyScan_Calibration_Flow] k_type=3
2403 11:06:45.243660
2404 11:06:45.244164 ==DQM 0 ==
2405 11:06:45.246801 Final DQM duty delay cell = 0
2406 11:06:45.249989 [0] MAX Duty = 5062%(X100), DQS PI = 24
2407 11:06:45.253624 [0] MIN Duty = 4813%(X100), DQS PI = 0
2408 11:06:45.254136 [0] AVG Duty = 4937%(X100)
2409 11:06:45.254471
2410 11:06:45.256797 ==DQM 1 ==
2411 11:06:45.260124 Final DQM duty delay cell = 0
2412 11:06:45.263982 [0] MAX Duty = 5187%(X100), DQS PI = 48
2413 11:06:45.266539 [0] MIN Duty = 5000%(X100), DQS PI = 12
2414 11:06:45.266974 [0] AVG Duty = 5093%(X100)
2415 11:06:45.267310
2416 11:06:45.273350 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2417 11:06:45.273864
2418 11:06:45.276793 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2419 11:06:45.279747 [DutyScan_Calibration_Flow] ====Done====
2420 11:06:45.280175
2421 11:06:45.283134 [DutyScan_Calibration_Flow] k_type=2
2422 11:06:45.299905
2423 11:06:45.300418 ==DQ 0 ==
2424 11:06:45.303287 Final DQ duty delay cell = -4
2425 11:06:45.306262 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2426 11:06:45.309748 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2427 11:06:45.313202 [-4] AVG Duty = 4953%(X100)
2428 11:06:45.313632
2429 11:06:45.313961 ==DQ 1 ==
2430 11:06:45.316735 Final DQ duty delay cell = 4
2431 11:06:45.320039 [4] MAX Duty = 5093%(X100), DQS PI = 6
2432 11:06:45.323195 [4] MIN Duty = 5031%(X100), DQS PI = 0
2433 11:06:45.323711 [4] AVG Duty = 5062%(X100)
2434 11:06:45.327030
2435 11:06:45.330102 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2436 11:06:45.330729
2437 11:06:45.333399 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2438 11:06:45.336748 [DutyScan_Calibration_Flow] ====Done====
2439 11:06:45.337285 ==
2440 11:06:45.340063 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 11:06:45.343127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 11:06:45.343560 ==
2443 11:06:45.346702 [Duty_Offset_Calibration]
2444 11:06:45.347210 B0:0 B1:-1 CA:2
2445 11:06:45.347547
2446 11:06:45.349709 [DutyScan_Calibration_Flow] k_type=0
2447 11:06:45.360305
2448 11:06:45.360816 ==CLK 0==
2449 11:06:45.363157 Final CLK duty delay cell = 0
2450 11:06:45.366661 [0] MAX Duty = 5156%(X100), DQS PI = 16
2451 11:06:45.369702 [0] MIN Duty = 4938%(X100), DQS PI = 44
2452 11:06:45.370138 [0] AVG Duty = 5047%(X100)
2453 11:06:45.373041
2454 11:06:45.376674 CH1 CLK Duty spec in!! Max-Min= 218%
2455 11:06:45.380371 [DutyScan_Calibration_Flow] ====Done====
2456 11:06:45.380882
2457 11:06:45.383511 [DutyScan_Calibration_Flow] k_type=1
2458 11:06:45.399449
2459 11:06:45.399958 ==DQS 0 ==
2460 11:06:45.402646 Final DQS duty delay cell = 0
2461 11:06:45.406255 [0] MAX Duty = 5093%(X100), DQS PI = 24
2462 11:06:45.409099 [0] MIN Duty = 4969%(X100), DQS PI = 0
2463 11:06:45.409564 [0] AVG Duty = 5031%(X100)
2464 11:06:45.412828
2465 11:06:45.413436 ==DQS 1 ==
2466 11:06:45.415950 Final DQS duty delay cell = 0
2467 11:06:45.419603 [0] MAX Duty = 5156%(X100), DQS PI = 0
2468 11:06:45.422955 [0] MIN Duty = 4875%(X100), DQS PI = 34
2469 11:06:45.423585 [0] AVG Duty = 5015%(X100)
2470 11:06:45.424056
2471 11:06:45.429544 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2472 11:06:45.430057
2473 11:06:45.432921 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2474 11:06:45.436325 [DutyScan_Calibration_Flow] ====Done====
2475 11:06:45.436837
2476 11:06:45.439479 [DutyScan_Calibration_Flow] k_type=3
2477 11:06:45.455749
2478 11:06:45.456256 ==DQM 0 ==
2479 11:06:45.459311 Final DQM duty delay cell = 4
2480 11:06:45.462319 [4] MAX Duty = 5093%(X100), DQS PI = 6
2481 11:06:45.466087 [4] MIN Duty = 4938%(X100), DQS PI = 44
2482 11:06:45.466601 [4] AVG Duty = 5015%(X100)
2483 11:06:45.468869
2484 11:06:45.469345 ==DQM 1 ==
2485 11:06:45.472516 Final DQM duty delay cell = -4
2486 11:06:45.475778 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2487 11:06:45.479000 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2488 11:06:45.482204 [-4] AVG Duty = 4875%(X100)
2489 11:06:45.482636
2490 11:06:45.485188 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2491 11:06:45.485357
2492 11:06:45.488760 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2493 11:06:45.492245 [DutyScan_Calibration_Flow] ====Done====
2494 11:06:45.492537
2495 11:06:45.495434 [DutyScan_Calibration_Flow] k_type=2
2496 11:06:45.512507
2497 11:06:45.513039 ==DQ 0 ==
2498 11:06:45.516077 Final DQ duty delay cell = 0
2499 11:06:45.519333 [0] MAX Duty = 5062%(X100), DQS PI = 20
2500 11:06:45.522795 [0] MIN Duty = 4938%(X100), DQS PI = 0
2501 11:06:45.523311 [0] AVG Duty = 5000%(X100)
2502 11:06:45.523647
2503 11:06:45.526329 ==DQ 1 ==
2504 11:06:45.529551 Final DQ duty delay cell = 0
2505 11:06:45.532603 [0] MAX Duty = 5031%(X100), DQS PI = 2
2506 11:06:45.536386 [0] MIN Duty = 4813%(X100), DQS PI = 34
2507 11:06:45.536990 [0] AVG Duty = 4922%(X100)
2508 11:06:45.537393
2509 11:06:45.539635 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2510 11:06:45.540146
2511 11:06:45.543166 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2512 11:06:45.549515 [DutyScan_Calibration_Flow] ====Done====
2513 11:06:45.553151 nWR fixed to 30
2514 11:06:45.553667 [ModeRegInit_LP4] CH0 RK0
2515 11:06:45.556108 [ModeRegInit_LP4] CH0 RK1
2516 11:06:45.559730 [ModeRegInit_LP4] CH1 RK0
2517 11:06:45.560240 [ModeRegInit_LP4] CH1 RK1
2518 11:06:45.562720 match AC timing 7
2519 11:06:45.566251 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 11:06:45.569731 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 11:06:45.576222 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 11:06:45.580012 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 11:06:45.586405 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 11:06:45.586921 ==
2525 11:06:45.589353 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 11:06:45.592982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 11:06:45.593563 ==
2528 11:06:45.599327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 11:06:45.602799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 11:06:45.612418 [CA 0] Center 38 (7~69) winsize 63
2531 11:06:45.616071 [CA 1] Center 38 (8~69) winsize 62
2532 11:06:45.619491 [CA 2] Center 35 (5~66) winsize 62
2533 11:06:45.622643 [CA 3] Center 35 (4~66) winsize 63
2534 11:06:45.626056 [CA 4] Center 34 (4~65) winsize 62
2535 11:06:45.629419 [CA 5] Center 33 (3~63) winsize 61
2536 11:06:45.629931
2537 11:06:45.632669 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2538 11:06:45.633230
2539 11:06:45.635537 [CATrainingPosCal] consider 1 rank data
2540 11:06:45.639122 u2DelayCellTimex100 = 270/100 ps
2541 11:06:45.642447 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2542 11:06:45.645948 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2543 11:06:45.652661 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2544 11:06:45.655767 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2545 11:06:45.659482 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2546 11:06:45.662513 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 11:06:45.662947
2548 11:06:45.666087 CA PerBit enable=1, Macro0, CA PI delay=33
2549 11:06:45.666610
2550 11:06:45.669371 [CBTSetCACLKResult] CA Dly = 33
2551 11:06:45.669888 CS Dly: 6 (0~37)
2552 11:06:45.670228 ==
2553 11:06:45.672794 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 11:06:45.679436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 11:06:45.679955 ==
2556 11:06:45.682849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 11:06:45.689496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2558 11:06:45.698136 [CA 0] Center 39 (8~70) winsize 63
2559 11:06:45.701440 [CA 1] Center 38 (8~69) winsize 62
2560 11:06:45.704909 [CA 2] Center 35 (5~66) winsize 62
2561 11:06:45.707928 [CA 3] Center 35 (5~66) winsize 62
2562 11:06:45.711401 [CA 4] Center 34 (4~65) winsize 62
2563 11:06:45.714915 [CA 5] Center 34 (4~64) winsize 61
2564 11:06:45.715443
2565 11:06:45.718423 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2566 11:06:45.718937
2567 11:06:45.721820 [CATrainingPosCal] consider 2 rank data
2568 11:06:45.724735 u2DelayCellTimex100 = 270/100 ps
2569 11:06:45.728191 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2570 11:06:45.731644 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2571 11:06:45.738413 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2572 11:06:45.741740 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2573 11:06:45.745030 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2574 11:06:45.748193 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2575 11:06:45.748624
2576 11:06:45.751335 CA PerBit enable=1, Macro0, CA PI delay=33
2577 11:06:45.751774
2578 11:06:45.755004 [CBTSetCACLKResult] CA Dly = 33
2579 11:06:45.755480 CS Dly: 7 (0~39)
2580 11:06:45.755829
2581 11:06:45.758049 ----->DramcWriteLeveling(PI) begin...
2582 11:06:45.758483 ==
2583 11:06:45.761458 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 11:06:45.768256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 11:06:45.768767 ==
2586 11:06:45.771553 Write leveling (Byte 0): 33 => 33
2587 11:06:45.774793 Write leveling (Byte 1): 29 => 29
2588 11:06:45.775225 DramcWriteLeveling(PI) end<-----
2589 11:06:45.775559
2590 11:06:45.778423 ==
2591 11:06:45.781614 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 11:06:45.785169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 11:06:45.785690 ==
2594 11:06:45.788364 [Gating] SW mode calibration
2595 11:06:45.795084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 11:06:45.798315 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 11:06:45.805020 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2598 11:06:45.808300 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2599 11:06:45.811525 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 11:06:45.818404 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 11:06:45.821599 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 11:06:45.825005 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 11:06:45.832031 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2604 11:06:45.835295 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2605 11:06:45.838208 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2606 11:06:45.845249 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 11:06:45.848501 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 11:06:45.851846 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 11:06:45.854880 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 11:06:45.862131 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 11:06:45.865117 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2612 11:06:45.868473 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (1 1) (0 0)
2613 11:06:45.875160 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2614 11:06:45.878562 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 11:06:45.881767 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 11:06:45.888627 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 11:06:45.892241 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 11:06:45.895459 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 11:06:45.902321 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 11:06:45.905789 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2621 11:06:45.908694 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 11:06:45.915153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:06:45.918742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:06:45.922096 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:06:45.925220 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:06:45.932324 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:06:45.935807 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:06:45.938986 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:06:45.945707 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:06:45.948618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:06:45.952150 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:06:45.958640 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:06:45.961936 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:06:45.965700 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:06:45.972167 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2636 11:06:45.975650 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 11:06:45.978917 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 11:06:45.982391 Total UI for P1: 0, mck2ui 16
2639 11:06:45.985310 best dqsien dly found for B0: ( 1, 3, 26)
2640 11:06:45.992262 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 11:06:45.992771 Total UI for P1: 0, mck2ui 16
2642 11:06:45.995755 best dqsien dly found for B1: ( 1, 4, 0)
2643 11:06:46.002063 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2644 11:06:46.005927 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2645 11:06:46.006439
2646 11:06:46.009279 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2647 11:06:46.012330 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2648 11:06:46.015415 [Gating] SW calibration Done
2649 11:06:46.015842 ==
2650 11:06:46.019138 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 11:06:46.022646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 11:06:46.023159 ==
2653 11:06:46.023496 RX Vref Scan: 0
2654 11:06:46.023807
2655 11:06:46.025937 RX Vref 0 -> 0, step: 1
2656 11:06:46.026449
2657 11:06:46.029505 RX Delay -40 -> 252, step: 8
2658 11:06:46.032778 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2659 11:06:46.035678 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2660 11:06:46.042678 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2661 11:06:46.045882 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2662 11:06:46.049425 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2663 11:06:46.052680 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2664 11:06:46.055857 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2665 11:06:46.059545 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2666 11:06:46.066061 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2667 11:06:46.069179 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2668 11:06:46.072576 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2669 11:06:46.076131 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2670 11:06:46.079306 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2671 11:06:46.086132 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2672 11:06:46.089533 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2673 11:06:46.092915 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2674 11:06:46.093384 ==
2675 11:06:46.096432 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 11:06:46.099654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 11:06:46.100110 ==
2678 11:06:46.103027 DQS Delay:
2679 11:06:46.103544 DQS0 = 0, DQS1 = 0
2680 11:06:46.106639 DQM Delay:
2681 11:06:46.107153 DQM0 = 123, DQM1 = 110
2682 11:06:46.107489 DQ Delay:
2683 11:06:46.112885 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2684 11:06:46.116059 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2685 11:06:46.119536 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2686 11:06:46.123226 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2687 11:06:46.123739
2688 11:06:46.124075
2689 11:06:46.124380 ==
2690 11:06:46.125920 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 11:06:46.129411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 11:06:46.129849 ==
2693 11:06:46.130185
2694 11:06:46.130493
2695 11:06:46.132886 TX Vref Scan disable
2696 11:06:46.136128 == TX Byte 0 ==
2697 11:06:46.139528 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2698 11:06:46.143120 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2699 11:06:46.146119 == TX Byte 1 ==
2700 11:06:46.149483 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2701 11:06:46.152952 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2702 11:06:46.153530 ==
2703 11:06:46.156473 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 11:06:46.159960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 11:06:46.160477 ==
2706 11:06:46.172452 TX Vref=22, minBit 3, minWin=24, winSum=409
2707 11:06:46.175863 TX Vref=24, minBit 4, minWin=24, winSum=414
2708 11:06:46.179817 TX Vref=26, minBit 0, minWin=25, winSum=420
2709 11:06:46.183086 TX Vref=28, minBit 1, minWin=25, winSum=419
2710 11:06:46.186109 TX Vref=30, minBit 5, minWin=25, winSum=423
2711 11:06:46.189663 TX Vref=32, minBit 1, minWin=25, winSum=423
2712 11:06:46.196480 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 30
2713 11:06:46.196997
2714 11:06:46.199636 Final TX Range 1 Vref 30
2715 11:06:46.200161
2716 11:06:46.200500 ==
2717 11:06:46.202749 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 11:06:46.206189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 11:06:46.206706 ==
2720 11:06:46.207049
2721 11:06:46.207358
2722 11:06:46.209309 TX Vref Scan disable
2723 11:06:46.213042 == TX Byte 0 ==
2724 11:06:46.216225 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2725 11:06:46.219782 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2726 11:06:46.222856 == TX Byte 1 ==
2727 11:06:46.226346 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2728 11:06:46.229807 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2729 11:06:46.230324
2730 11:06:46.233296 [DATLAT]
2731 11:06:46.233809 Freq=1200, CH0 RK0
2732 11:06:46.234149
2733 11:06:46.236467 DATLAT Default: 0xd
2734 11:06:46.236980 0, 0xFFFF, sum = 0
2735 11:06:46.239528 1, 0xFFFF, sum = 0
2736 11:06:46.239967 2, 0xFFFF, sum = 0
2737 11:06:46.243346 3, 0xFFFF, sum = 0
2738 11:06:46.243869 4, 0xFFFF, sum = 0
2739 11:06:46.246469 5, 0xFFFF, sum = 0
2740 11:06:46.246992 6, 0xFFFF, sum = 0
2741 11:06:46.249647 7, 0xFFFF, sum = 0
2742 11:06:46.250173 8, 0xFFFF, sum = 0
2743 11:06:46.252978 9, 0xFFFF, sum = 0
2744 11:06:46.253550 10, 0xFFFF, sum = 0
2745 11:06:46.256411 11, 0xFFFF, sum = 0
2746 11:06:46.256851 12, 0x0, sum = 1
2747 11:06:46.259819 13, 0x0, sum = 2
2748 11:06:46.260335 14, 0x0, sum = 3
2749 11:06:46.263011 15, 0x0, sum = 4
2750 11:06:46.263529 best_step = 13
2751 11:06:46.263867
2752 11:06:46.264169 ==
2753 11:06:46.266458 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 11:06:46.273298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 11:06:46.273817 ==
2756 11:06:46.274160 RX Vref Scan: 1
2757 11:06:46.274468
2758 11:06:46.276668 Set Vref Range= 32 -> 127
2759 11:06:46.277232
2760 11:06:46.279860 RX Vref 32 -> 127, step: 1
2761 11:06:46.280374
2762 11:06:46.280707 RX Delay -13 -> 252, step: 4
2763 11:06:46.283218
2764 11:06:46.283736 Set Vref, RX VrefLevel [Byte0]: 32
2765 11:06:46.286707 [Byte1]: 32
2766 11:06:46.291059
2767 11:06:46.291492 Set Vref, RX VrefLevel [Byte0]: 33
2768 11:06:46.294591 [Byte1]: 33
2769 11:06:46.298952
2770 11:06:46.299460 Set Vref, RX VrefLevel [Byte0]: 34
2771 11:06:46.301923 [Byte1]: 34
2772 11:06:46.306572
2773 11:06:46.307004 Set Vref, RX VrefLevel [Byte0]: 35
2774 11:06:46.309913 [Byte1]: 35
2775 11:06:46.314711
2776 11:06:46.315290 Set Vref, RX VrefLevel [Byte0]: 36
2777 11:06:46.317924 [Byte1]: 36
2778 11:06:46.322654
2779 11:06:46.323176 Set Vref, RX VrefLevel [Byte0]: 37
2780 11:06:46.325695 [Byte1]: 37
2781 11:06:46.330439
2782 11:06:46.330947 Set Vref, RX VrefLevel [Byte0]: 38
2783 11:06:46.334048 [Byte1]: 38
2784 11:06:46.338653
2785 11:06:46.339165 Set Vref, RX VrefLevel [Byte0]: 39
2786 11:06:46.341398 [Byte1]: 39
2787 11:06:46.346464
2788 11:06:46.346974 Set Vref, RX VrefLevel [Byte0]: 40
2789 11:06:46.349769 [Byte1]: 40
2790 11:06:46.354080
2791 11:06:46.354584 Set Vref, RX VrefLevel [Byte0]: 41
2792 11:06:46.357436 [Byte1]: 41
2793 11:06:46.362165
2794 11:06:46.362672 Set Vref, RX VrefLevel [Byte0]: 42
2795 11:06:46.365562 [Byte1]: 42
2796 11:06:46.369852
2797 11:06:46.370279 Set Vref, RX VrefLevel [Byte0]: 43
2798 11:06:46.373250 [Byte1]: 43
2799 11:06:46.377932
2800 11:06:46.378444 Set Vref, RX VrefLevel [Byte0]: 44
2801 11:06:46.381764 [Byte1]: 44
2802 11:06:46.386020
2803 11:06:46.386536 Set Vref, RX VrefLevel [Byte0]: 45
2804 11:06:46.389491 [Byte1]: 45
2805 11:06:46.393481
2806 11:06:46.393977 Set Vref, RX VrefLevel [Byte0]: 46
2807 11:06:46.397319 [Byte1]: 46
2808 11:06:46.401658
2809 11:06:46.402189 Set Vref, RX VrefLevel [Byte0]: 47
2810 11:06:46.405121 [Byte1]: 47
2811 11:06:46.409528
2812 11:06:46.410051 Set Vref, RX VrefLevel [Byte0]: 48
2813 11:06:46.412528 [Byte1]: 48
2814 11:06:46.417583
2815 11:06:46.418105 Set Vref, RX VrefLevel [Byte0]: 49
2816 11:06:46.420271 [Byte1]: 49
2817 11:06:46.425208
2818 11:06:46.425716 Set Vref, RX VrefLevel [Byte0]: 50
2819 11:06:46.428911 [Byte1]: 50
2820 11:06:46.433083
2821 11:06:46.433571 Set Vref, RX VrefLevel [Byte0]: 51
2822 11:06:46.436313 [Byte1]: 51
2823 11:06:46.440936
2824 11:06:46.441532 Set Vref, RX VrefLevel [Byte0]: 52
2825 11:06:46.444349 [Byte1]: 52
2826 11:06:46.449072
2827 11:06:46.449614 Set Vref, RX VrefLevel [Byte0]: 53
2828 11:06:46.452176 [Byte1]: 53
2829 11:06:46.456831
2830 11:06:46.457295 Set Vref, RX VrefLevel [Byte0]: 54
2831 11:06:46.459831 [Byte1]: 54
2832 11:06:46.464525
2833 11:06:46.465046 Set Vref, RX VrefLevel [Byte0]: 55
2834 11:06:46.467988 [Byte1]: 55
2835 11:06:46.472657
2836 11:06:46.473206 Set Vref, RX VrefLevel [Byte0]: 56
2837 11:06:46.475871 [Byte1]: 56
2838 11:06:46.480361
2839 11:06:46.480873 Set Vref, RX VrefLevel [Byte0]: 57
2840 11:06:46.483979 [Byte1]: 57
2841 11:06:46.488713
2842 11:06:46.489271 Set Vref, RX VrefLevel [Byte0]: 58
2843 11:06:46.491765 [Byte1]: 58
2844 11:06:46.496389
2845 11:06:46.496899 Set Vref, RX VrefLevel [Byte0]: 59
2846 11:06:46.499265 [Byte1]: 59
2847 11:06:46.504205
2848 11:06:46.504731 Set Vref, RX VrefLevel [Byte0]: 60
2849 11:06:46.507511 [Byte1]: 60
2850 11:06:46.512370
2851 11:06:46.512886 Set Vref, RX VrefLevel [Byte0]: 61
2852 11:06:46.515274 [Byte1]: 61
2853 11:06:46.520154
2854 11:06:46.520669 Set Vref, RX VrefLevel [Byte0]: 62
2855 11:06:46.523284 [Byte1]: 62
2856 11:06:46.527745
2857 11:06:46.528261 Set Vref, RX VrefLevel [Byte0]: 63
2858 11:06:46.531075 [Byte1]: 63
2859 11:06:46.535849
2860 11:06:46.536365 Set Vref, RX VrefLevel [Byte0]: 64
2861 11:06:46.538821 [Byte1]: 64
2862 11:06:46.543398
2863 11:06:46.543916 Set Vref, RX VrefLevel [Byte0]: 65
2864 11:06:46.546579 [Byte1]: 65
2865 11:06:46.551306
2866 11:06:46.551836 Set Vref, RX VrefLevel [Byte0]: 66
2867 11:06:46.554532 [Byte1]: 66
2868 11:06:46.559480
2869 11:06:46.560004 Set Vref, RX VrefLevel [Byte0]: 67
2870 11:06:46.562476 [Byte1]: 67
2871 11:06:46.566882
2872 11:06:46.567314 Set Vref, RX VrefLevel [Byte0]: 68
2873 11:06:46.570418 [Byte1]: 68
2874 11:06:46.575182
2875 11:06:46.575694 Set Vref, RX VrefLevel [Byte0]: 69
2876 11:06:46.578438 [Byte1]: 69
2877 11:06:46.582925
2878 11:06:46.583442 Final RX Vref Byte 0 = 60 to rank0
2879 11:06:46.586288 Final RX Vref Byte 1 = 54 to rank0
2880 11:06:46.590029 Final RX Vref Byte 0 = 60 to rank1
2881 11:06:46.593385 Final RX Vref Byte 1 = 54 to rank1==
2882 11:06:46.596500 Dram Type= 6, Freq= 0, CH_0, rank 0
2883 11:06:46.602659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 11:06:46.603163 ==
2885 11:06:46.603499 DQS Delay:
2886 11:06:46.603806 DQS0 = 0, DQS1 = 0
2887 11:06:46.606404 DQM Delay:
2888 11:06:46.606931 DQM0 = 123, DQM1 = 109
2889 11:06:46.609497 DQ Delay:
2890 11:06:46.613231 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2891 11:06:46.616471 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2892 11:06:46.619937 DQ8 =102, DQ9 =96, DQ10 =110, DQ11 =106
2893 11:06:46.623581 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2894 11:06:46.624095
2895 11:06:46.624427
2896 11:06:46.629921 [DQSOSCAuto] RK0, (LSB)MR18= 0x100c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2897 11:06:46.632913 CH0 RK0: MR19=404, MR18=100C
2898 11:06:46.639663 CH0_RK0: MR19=0x404, MR18=0x100C, DQSOSC=403, MR23=63, INC=40, DEC=26
2899 11:06:46.640167
2900 11:06:46.643612 ----->DramcWriteLeveling(PI) begin...
2901 11:06:46.644133 ==
2902 11:06:46.646565 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 11:06:46.650356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 11:06:46.650872 ==
2905 11:06:46.653500 Write leveling (Byte 0): 35 => 35
2906 11:06:46.656372 Write leveling (Byte 1): 30 => 30
2907 11:06:46.660025 DramcWriteLeveling(PI) end<-----
2908 11:06:46.660564
2909 11:06:46.660910 ==
2910 11:06:46.663370 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 11:06:46.666873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 11:06:46.670119 ==
2913 11:06:46.670636 [Gating] SW mode calibration
2914 11:06:46.679850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2915 11:06:46.683187 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2916 11:06:46.686806 0 15 0 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
2917 11:06:46.693583 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 11:06:46.696655 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 11:06:46.700193 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 11:06:46.706943 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 11:06:46.710051 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 11:06:46.713588 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2923 11:06:46.720214 0 15 28 | B1->B0 | 3131 2c2c | 0 0 | (1 0) (0 0)
2924 11:06:46.724161 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 11:06:46.727076 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 11:06:46.730098 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 11:06:46.736963 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 11:06:46.740315 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 11:06:46.743817 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 11:06:46.750221 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 11:06:46.753829 1 0 28 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
2932 11:06:46.756825 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 11:06:46.764210 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 11:06:46.766720 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 11:06:46.770397 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 11:06:46.777069 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 11:06:46.780566 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 11:06:46.783503 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 11:06:46.790471 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2940 11:06:46.793635 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:06:46.797042 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 11:06:46.803565 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 11:06:46.807256 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 11:06:46.810191 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 11:06:46.813550 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 11:06:46.820117 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 11:06:46.823653 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 11:06:46.827187 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 11:06:46.833386 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 11:06:46.837194 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:06:46.840166 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:06:46.847112 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:06:46.850439 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:06:46.853689 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:06:46.860475 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2956 11:06:46.863642 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2957 11:06:46.867098 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 11:06:46.870321 Total UI for P1: 0, mck2ui 16
2959 11:06:46.873815 best dqsien dly found for B0: ( 1, 3, 30)
2960 11:06:46.877036 Total UI for P1: 0, mck2ui 16
2961 11:06:46.880672 best dqsien dly found for B1: ( 1, 3, 30)
2962 11:06:46.883895 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2963 11:06:46.887410 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2964 11:06:46.887843
2965 11:06:46.890743 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2966 11:06:46.893814 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2967 11:06:46.897193 [Gating] SW calibration Done
2968 11:06:46.897627 ==
2969 11:06:46.900650 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 11:06:46.907378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 11:06:46.907889 ==
2972 11:06:46.908259 RX Vref Scan: 0
2973 11:06:46.908566
2974 11:06:46.910773 RX Vref 0 -> 0, step: 1
2975 11:06:46.911348
2976 11:06:46.914168 RX Delay -40 -> 252, step: 8
2977 11:06:46.917696 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2978 11:06:46.920777 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2979 11:06:46.924503 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2980 11:06:46.927573 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2981 11:06:46.934063 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2982 11:06:46.937615 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2983 11:06:46.940854 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2984 11:06:46.944243 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2985 11:06:46.947765 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2986 11:06:46.954199 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2987 11:06:46.957375 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2988 11:06:46.960869 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2989 11:06:46.964505 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2990 11:06:46.967796 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2991 11:06:46.974332 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2992 11:06:46.977795 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2993 11:06:46.978305 ==
2994 11:06:46.981443 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 11:06:46.984318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 11:06:46.984824 ==
2997 11:06:46.985219 DQS Delay:
2998 11:06:46.987648 DQS0 = 0, DQS1 = 0
2999 11:06:46.988079 DQM Delay:
3000 11:06:46.990908 DQM0 = 120, DQM1 = 108
3001 11:06:46.991460 DQ Delay:
3002 11:06:46.994421 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3003 11:06:46.997776 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3004 11:06:47.001211 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
3005 11:06:47.004620 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
3006 11:06:47.005173
3007 11:06:47.008095
3008 11:06:47.008625 ==
3009 11:06:47.011071 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 11:06:47.014212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 11:06:47.014697 ==
3012 11:06:47.015033
3013 11:06:47.015329
3014 11:06:47.017643 TX Vref Scan disable
3015 11:06:47.018070 == TX Byte 0 ==
3016 11:06:47.021296 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3017 11:06:47.027787 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3018 11:06:47.028298 == TX Byte 1 ==
3019 11:06:47.030995 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3020 11:06:47.037649 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3021 11:06:47.038150 ==
3022 11:06:47.041009 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 11:06:47.044365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 11:06:47.044873 ==
3025 11:06:47.057241 TX Vref=22, minBit 0, minWin=25, winSum=414
3026 11:06:47.060447 TX Vref=24, minBit 5, minWin=24, winSum=415
3027 11:06:47.063817 TX Vref=26, minBit 1, minWin=25, winSum=419
3028 11:06:47.067073 TX Vref=28, minBit 3, minWin=25, winSum=423
3029 11:06:47.070367 TX Vref=30, minBit 1, minWin=25, winSum=424
3030 11:06:47.073723 TX Vref=32, minBit 2, minWin=25, winSum=424
3031 11:06:47.080812 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 30
3032 11:06:47.081366
3033 11:06:47.083562 Final TX Range 1 Vref 30
3034 11:06:47.083990
3035 11:06:47.084315 ==
3036 11:06:47.087087 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 11:06:47.090905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 11:06:47.091417 ==
3039 11:06:47.091752
3040 11:06:47.092058
3041 11:06:47.093598 TX Vref Scan disable
3042 11:06:47.097301 == TX Byte 0 ==
3043 11:06:47.100424 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3044 11:06:47.103782 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3045 11:06:47.107598 == TX Byte 1 ==
3046 11:06:47.110773 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3047 11:06:47.113946 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3048 11:06:47.114461
3049 11:06:47.117091 [DATLAT]
3050 11:06:47.117594 Freq=1200, CH0 RK1
3051 11:06:47.117931
3052 11:06:47.120605 DATLAT Default: 0xd
3053 11:06:47.121123 0, 0xFFFF, sum = 0
3054 11:06:47.123880 1, 0xFFFF, sum = 0
3055 11:06:47.124310 2, 0xFFFF, sum = 0
3056 11:06:47.127672 3, 0xFFFF, sum = 0
3057 11:06:47.128186 4, 0xFFFF, sum = 0
3058 11:06:47.130808 5, 0xFFFF, sum = 0
3059 11:06:47.131245 6, 0xFFFF, sum = 0
3060 11:06:47.133913 7, 0xFFFF, sum = 0
3061 11:06:47.134346 8, 0xFFFF, sum = 0
3062 11:06:47.137663 9, 0xFFFF, sum = 0
3063 11:06:47.138176 10, 0xFFFF, sum = 0
3064 11:06:47.140803 11, 0xFFFF, sum = 0
3065 11:06:47.141355 12, 0x0, sum = 1
3066 11:06:47.144015 13, 0x0, sum = 2
3067 11:06:47.144451 14, 0x0, sum = 3
3068 11:06:47.147251 15, 0x0, sum = 4
3069 11:06:47.147684 best_step = 13
3070 11:06:47.148011
3071 11:06:47.148314 ==
3072 11:06:47.150629 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 11:06:47.157464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 11:06:47.157966 ==
3075 11:06:47.158304 RX Vref Scan: 0
3076 11:06:47.158665
3077 11:06:47.160588 RX Vref 0 -> 0, step: 1
3078 11:06:47.161016
3079 11:06:47.164235 RX Delay -21 -> 252, step: 4
3080 11:06:47.167914 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3081 11:06:47.170750 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3082 11:06:47.177683 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3083 11:06:47.181114 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3084 11:06:47.184055 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3085 11:06:47.187936 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3086 11:06:47.190866 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3087 11:06:47.194580 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3088 11:06:47.200667 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3089 11:06:47.204151 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3090 11:06:47.207739 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3091 11:06:47.210915 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3092 11:06:47.214346 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3093 11:06:47.220978 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3094 11:06:47.224068 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3095 11:06:47.227698 iDelay=195, Bit 15, Center 116 (55 ~ 178) 124
3096 11:06:47.228206 ==
3097 11:06:47.230806 Dram Type= 6, Freq= 0, CH_0, rank 1
3098 11:06:47.234119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 11:06:47.234642 ==
3100 11:06:47.237708 DQS Delay:
3101 11:06:47.238227 DQS0 = 0, DQS1 = 0
3102 11:06:47.240906 DQM Delay:
3103 11:06:47.241442 DQM0 = 119, DQM1 = 108
3104 11:06:47.241785 DQ Delay:
3105 11:06:47.247715 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3106 11:06:47.250867 DQ4 =118, DQ5 =114, DQ6 =126, DQ7 =126
3107 11:06:47.254349 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3108 11:06:47.257625 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =116
3109 11:06:47.258105
3110 11:06:47.258457
3111 11:06:47.264666 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3112 11:06:47.267730 CH0 RK1: MR19=403, MR18=15FC
3113 11:06:47.274444 CH0_RK1: MR19=0x403, MR18=0x15FC, DQSOSC=401, MR23=63, INC=40, DEC=27
3114 11:06:47.277801 [RxdqsGatingPostProcess] freq 1200
3115 11:06:47.281365 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3116 11:06:47.284647 best DQS0 dly(2T, 0.5T) = (0, 11)
3117 11:06:47.287784 best DQS1 dly(2T, 0.5T) = (0, 12)
3118 11:06:47.291125 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3119 11:06:47.294369 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3120 11:06:47.297728 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 11:06:47.301101 best DQS1 dly(2T, 0.5T) = (0, 11)
3122 11:06:47.304342 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 11:06:47.307763 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3124 11:06:47.311138 Pre-setting of DQS Precalculation
3125 11:06:47.314410 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3126 11:06:47.314916 ==
3127 11:06:47.317451 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 11:06:47.324210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 11:06:47.324719 ==
3130 11:06:47.327858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 11:06:47.334009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3132 11:06:47.343048 [CA 0] Center 37 (7~68) winsize 62
3133 11:06:47.346293 [CA 1] Center 37 (7~68) winsize 62
3134 11:06:47.349786 [CA 2] Center 35 (5~65) winsize 61
3135 11:06:47.353013 [CA 3] Center 34 (4~65) winsize 62
3136 11:06:47.356407 [CA 4] Center 34 (4~65) winsize 62
3137 11:06:47.359541 [CA 5] Center 33 (3~64) winsize 62
3138 11:06:47.359978
3139 11:06:47.363051 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3140 11:06:47.363555
3141 11:06:47.366473 [CATrainingPosCal] consider 1 rank data
3142 11:06:47.369908 u2DelayCellTimex100 = 270/100 ps
3143 11:06:47.373047 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3144 11:06:47.376477 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3145 11:06:47.383419 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3146 11:06:47.386353 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3147 11:06:47.389649 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3148 11:06:47.393090 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3149 11:06:47.393657
3150 11:06:47.396222 CA PerBit enable=1, Macro0, CA PI delay=33
3151 11:06:47.396724
3152 11:06:47.399803 [CBTSetCACLKResult] CA Dly = 33
3153 11:06:47.400313 CS Dly: 5 (0~36)
3154 11:06:47.402576 ==
3155 11:06:47.405997 Dram Type= 6, Freq= 0, CH_1, rank 1
3156 11:06:47.409781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 11:06:47.410288 ==
3158 11:06:47.412844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3159 11:06:47.419544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3160 11:06:47.428730 [CA 0] Center 38 (8~68) winsize 61
3161 11:06:47.432099 [CA 1] Center 38 (7~69) winsize 63
3162 11:06:47.435505 [CA 2] Center 35 (5~66) winsize 62
3163 11:06:47.438935 [CA 3] Center 35 (5~65) winsize 61
3164 11:06:47.442085 [CA 4] Center 34 (4~64) winsize 61
3165 11:06:47.445615 [CA 5] Center 34 (4~64) winsize 61
3166 11:06:47.446121
3167 11:06:47.448827 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3168 11:06:47.449371
3169 11:06:47.451944 [CATrainingPosCal] consider 2 rank data
3170 11:06:47.455480 u2DelayCellTimex100 = 270/100 ps
3171 11:06:47.458374 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3172 11:06:47.465494 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3173 11:06:47.468554 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3174 11:06:47.471629 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3175 11:06:47.475196 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3176 11:06:47.478593 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3177 11:06:47.479108
3178 11:06:47.482096 CA PerBit enable=1, Macro0, CA PI delay=34
3179 11:06:47.482609
3180 11:06:47.485119 [CBTSetCACLKResult] CA Dly = 34
3181 11:06:47.485593 CS Dly: 6 (0~39)
3182 11:06:47.485923
3183 11:06:47.488295 ----->DramcWriteLeveling(PI) begin...
3184 11:06:47.491855 ==
3185 11:06:47.495127 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 11:06:47.498857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 11:06:47.499369 ==
3188 11:06:47.501952 Write leveling (Byte 0): 25 => 25
3189 11:06:47.505055 Write leveling (Byte 1): 28 => 28
3190 11:06:47.508400 DramcWriteLeveling(PI) end<-----
3191 11:06:47.508901
3192 11:06:47.509286 ==
3193 11:06:47.511872 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 11:06:47.515046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 11:06:47.515477 ==
3196 11:06:47.518406 [Gating] SW mode calibration
3197 11:06:47.525922 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3198 11:06:47.528494 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3199 11:06:47.535343 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 11:06:47.538395 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 11:06:47.541797 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 11:06:47.548399 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 11:06:47.551958 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 11:06:47.555102 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3205 11:06:47.562007 0 15 24 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
3206 11:06:47.565340 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3207 11:06:47.568548 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 11:06:47.575206 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 11:06:47.578334 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 11:06:47.581822 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 11:06:47.588676 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 11:06:47.591677 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3213 11:06:47.595554 1 0 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3214 11:06:47.601866 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 11:06:47.604845 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 11:06:47.608120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 11:06:47.614699 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 11:06:47.618277 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 11:06:47.621672 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 11:06:47.628760 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 11:06:47.631853 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3222 11:06:47.635217 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3223 11:06:47.641678 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:06:47.645283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 11:06:47.648307 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 11:06:47.651902 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 11:06:47.658065 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 11:06:47.661769 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 11:06:47.665195 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 11:06:47.672022 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 11:06:47.675342 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 11:06:47.678263 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:06:47.685040 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:06:47.688397 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:06:47.691655 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:06:47.698460 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3237 11:06:47.701763 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3238 11:06:47.705278 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3239 11:06:47.708282 Total UI for P1: 0, mck2ui 16
3240 11:06:47.711980 best dqsien dly found for B0: ( 1, 3, 22)
3241 11:06:47.718256 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 11:06:47.718816 Total UI for P1: 0, mck2ui 16
3243 11:06:47.721776 best dqsien dly found for B1: ( 1, 3, 26)
3244 11:06:47.724816 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3245 11:06:47.731907 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3246 11:06:47.732426
3247 11:06:47.735459 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3248 11:06:47.738600 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3249 11:06:47.742031 [Gating] SW calibration Done
3250 11:06:47.742544 ==
3251 11:06:47.745227 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 11:06:47.748561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 11:06:47.749071 ==
3254 11:06:47.749447 RX Vref Scan: 0
3255 11:06:47.751804
3256 11:06:47.752325 RX Vref 0 -> 0, step: 1
3257 11:06:47.752663
3258 11:06:47.755123 RX Delay -40 -> 252, step: 8
3259 11:06:47.758422 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3260 11:06:47.761989 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3261 11:06:47.768624 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3262 11:06:47.771906 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3263 11:06:47.775092 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3264 11:06:47.778310 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3265 11:06:47.781856 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3266 11:06:47.788358 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3267 11:06:47.792502 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3268 11:06:47.794954 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3269 11:06:47.798587 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3270 11:06:47.801762 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3271 11:06:47.808124 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3272 11:06:47.811719 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3273 11:06:47.815073 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3274 11:06:47.818539 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3275 11:06:47.819122 ==
3276 11:06:47.821758 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 11:06:47.828590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 11:06:47.829119 ==
3279 11:06:47.829503 DQS Delay:
3280 11:06:47.829815 DQS0 = 0, DQS1 = 0
3281 11:06:47.831901 DQM Delay:
3282 11:06:47.832416 DQM0 = 118, DQM1 = 113
3283 11:06:47.835267 DQ Delay:
3284 11:06:47.838632 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3285 11:06:47.841643 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3286 11:06:47.845538 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3287 11:06:47.848486 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3288 11:06:47.849037
3289 11:06:47.849452
3290 11:06:47.849859 ==
3291 11:06:47.851698 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 11:06:47.854934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 11:06:47.855370 ==
3294 11:06:47.855780
3295 11:06:47.856091
3296 11:06:47.858565 TX Vref Scan disable
3297 11:06:47.861804 == TX Byte 0 ==
3298 11:06:47.864915 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3299 11:06:47.868485 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3300 11:06:47.871971 == TX Byte 1 ==
3301 11:06:47.875487 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3302 11:06:47.878606 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3303 11:06:47.879320 ==
3304 11:06:47.881955 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 11:06:47.888360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 11:06:47.888846 ==
3307 11:06:47.898717 TX Vref=22, minBit 10, minWin=24, winSum=406
3308 11:06:47.901767 TX Vref=24, minBit 10, minWin=24, winSum=409
3309 11:06:47.905059 TX Vref=26, minBit 3, minWin=25, winSum=414
3310 11:06:47.908462 TX Vref=28, minBit 8, minWin=25, winSum=423
3311 11:06:47.912005 TX Vref=30, minBit 10, minWin=25, winSum=419
3312 11:06:47.918413 TX Vref=32, minBit 10, minWin=25, winSum=422
3313 11:06:47.921722 [TxChooseVref] Worse bit 8, Min win 25, Win sum 423, Final Vref 28
3314 11:06:47.922226
3315 11:06:47.925790 Final TX Range 1 Vref 28
3316 11:06:47.926299
3317 11:06:47.926631 ==
3318 11:06:47.928827 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 11:06:47.932192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 11:06:47.935485 ==
3321 11:06:47.935996
3322 11:06:47.936324
3323 11:06:47.936629 TX Vref Scan disable
3324 11:06:47.938576 == TX Byte 0 ==
3325 11:06:47.941904 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3326 11:06:47.948666 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3327 11:06:47.949212 == TX Byte 1 ==
3328 11:06:47.952259 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3329 11:06:47.955261 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3330 11:06:47.958584
3331 11:06:47.959095 [DATLAT]
3332 11:06:47.959449 Freq=1200, CH1 RK0
3333 11:06:47.959835
3334 11:06:47.962063 DATLAT Default: 0xd
3335 11:06:47.962491 0, 0xFFFF, sum = 0
3336 11:06:47.965634 1, 0xFFFF, sum = 0
3337 11:06:47.966151 2, 0xFFFF, sum = 0
3338 11:06:47.968733 3, 0xFFFF, sum = 0
3339 11:06:47.972073 4, 0xFFFF, sum = 0
3340 11:06:47.972622 5, 0xFFFF, sum = 0
3341 11:06:47.975420 6, 0xFFFF, sum = 0
3342 11:06:47.975937 7, 0xFFFF, sum = 0
3343 11:06:47.978572 8, 0xFFFF, sum = 0
3344 11:06:47.979023 9, 0xFFFF, sum = 0
3345 11:06:47.982140 10, 0xFFFF, sum = 0
3346 11:06:47.982663 11, 0xFFFF, sum = 0
3347 11:06:47.985300 12, 0x0, sum = 1
3348 11:06:47.985740 13, 0x0, sum = 2
3349 11:06:47.988614 14, 0x0, sum = 3
3350 11:06:47.989159 15, 0x0, sum = 4
3351 11:06:47.989510 best_step = 13
3352 11:06:47.992063
3353 11:06:47.992574 ==
3354 11:06:47.995491 Dram Type= 6, Freq= 0, CH_1, rank 0
3355 11:06:47.998812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3356 11:06:47.999328 ==
3357 11:06:47.999666 RX Vref Scan: 1
3358 11:06:47.999972
3359 11:06:48.001700 Set Vref Range= 32 -> 127
3360 11:06:48.002127
3361 11:06:48.005425 RX Vref 32 -> 127, step: 1
3362 11:06:48.005989
3363 11:06:48.008531 RX Delay -13 -> 252, step: 4
3364 11:06:48.008960
3365 11:06:48.011675 Set Vref, RX VrefLevel [Byte0]: 32
3366 11:06:48.015283 [Byte1]: 32
3367 11:06:48.015712
3368 11:06:48.018218 Set Vref, RX VrefLevel [Byte0]: 33
3369 11:06:48.022079 [Byte1]: 33
3370 11:06:48.024834
3371 11:06:48.025293 Set Vref, RX VrefLevel [Byte0]: 34
3372 11:06:48.028657 [Byte1]: 34
3373 11:06:48.032699
3374 11:06:48.033122 Set Vref, RX VrefLevel [Byte0]: 35
3375 11:06:48.035907 [Byte1]: 35
3376 11:06:48.040774
3377 11:06:48.041225 Set Vref, RX VrefLevel [Byte0]: 36
3378 11:06:48.044103 [Byte1]: 36
3379 11:06:48.048537
3380 11:06:48.048962 Set Vref, RX VrefLevel [Byte0]: 37
3381 11:06:48.051808 [Byte1]: 37
3382 11:06:48.056538
3383 11:06:48.056921 Set Vref, RX VrefLevel [Byte0]: 38
3384 11:06:48.059635 [Byte1]: 38
3385 11:06:48.064534
3386 11:06:48.064913 Set Vref, RX VrefLevel [Byte0]: 39
3387 11:06:48.068069 [Byte1]: 39
3388 11:06:48.072352
3389 11:06:48.072733 Set Vref, RX VrefLevel [Byte0]: 40
3390 11:06:48.075600 [Byte1]: 40
3391 11:06:48.080231
3392 11:06:48.080608 Set Vref, RX VrefLevel [Byte0]: 41
3393 11:06:48.084013 [Byte1]: 41
3394 11:06:48.088297
3395 11:06:48.088802 Set Vref, RX VrefLevel [Byte0]: 42
3396 11:06:48.091548 [Byte1]: 42
3397 11:06:48.096386
3398 11:06:48.096893 Set Vref, RX VrefLevel [Byte0]: 43
3399 11:06:48.099899 [Byte1]: 43
3400 11:06:48.103983
3401 11:06:48.104488 Set Vref, RX VrefLevel [Byte0]: 44
3402 11:06:48.107120 [Byte1]: 44
3403 11:06:48.111567
3404 11:06:48.111993 Set Vref, RX VrefLevel [Byte0]: 45
3405 11:06:48.114852 [Byte1]: 45
3406 11:06:48.119591
3407 11:06:48.120109 Set Vref, RX VrefLevel [Byte0]: 46
3408 11:06:48.122968 [Byte1]: 46
3409 11:06:48.127586
3410 11:06:48.128087 Set Vref, RX VrefLevel [Byte0]: 47
3411 11:06:48.131149 [Byte1]: 47
3412 11:06:48.135602
3413 11:06:48.136106 Set Vref, RX VrefLevel [Byte0]: 48
3414 11:06:48.138852 [Byte1]: 48
3415 11:06:48.143489
3416 11:06:48.144000 Set Vref, RX VrefLevel [Byte0]: 49
3417 11:06:48.146623 [Byte1]: 49
3418 11:06:48.151434
3419 11:06:48.151949 Set Vref, RX VrefLevel [Byte0]: 50
3420 11:06:48.154594 [Byte1]: 50
3421 11:06:48.159185
3422 11:06:48.159692 Set Vref, RX VrefLevel [Byte0]: 51
3423 11:06:48.162119 [Byte1]: 51
3424 11:06:48.167158
3425 11:06:48.167665 Set Vref, RX VrefLevel [Byte0]: 52
3426 11:06:48.170668 [Byte1]: 52
3427 11:06:48.174958
3428 11:06:48.175464 Set Vref, RX VrefLevel [Byte0]: 53
3429 11:06:48.178148 [Byte1]: 53
3430 11:06:48.183096
3431 11:06:48.183749 Set Vref, RX VrefLevel [Byte0]: 54
3432 11:06:48.185867 [Byte1]: 54
3433 11:06:48.190728
3434 11:06:48.191151 Set Vref, RX VrefLevel [Byte0]: 55
3435 11:06:48.194019 [Byte1]: 55
3436 11:06:48.198595
3437 11:06:48.199103 Set Vref, RX VrefLevel [Byte0]: 56
3438 11:06:48.202081 [Byte1]: 56
3439 11:06:48.206539
3440 11:06:48.206967 Set Vref, RX VrefLevel [Byte0]: 57
3441 11:06:48.209631 [Byte1]: 57
3442 11:06:48.214611
3443 11:06:48.215116 Set Vref, RX VrefLevel [Byte0]: 58
3444 11:06:48.217782 [Byte1]: 58
3445 11:06:48.222422
3446 11:06:48.222939 Set Vref, RX VrefLevel [Byte0]: 59
3447 11:06:48.225625 [Byte1]: 59
3448 11:06:48.229939
3449 11:06:48.230463 Set Vref, RX VrefLevel [Byte0]: 60
3450 11:06:48.233589 [Byte1]: 60
3451 11:06:48.237977
3452 11:06:48.238483 Set Vref, RX VrefLevel [Byte0]: 61
3453 11:06:48.241559 [Byte1]: 61
3454 11:06:48.246082
3455 11:06:48.246585 Set Vref, RX VrefLevel [Byte0]: 62
3456 11:06:48.249505 [Byte1]: 62
3457 11:06:48.253696
3458 11:06:48.254124 Set Vref, RX VrefLevel [Byte0]: 63
3459 11:06:48.257035 [Byte1]: 63
3460 11:06:48.261352
3461 11:06:48.261519 Set Vref, RX VrefLevel [Byte0]: 64
3462 11:06:48.264424 [Byte1]: 64
3463 11:06:48.269459
3464 11:06:48.269576 Set Vref, RX VrefLevel [Byte0]: 65
3465 11:06:48.272551 [Byte1]: 65
3466 11:06:48.277327
3467 11:06:48.277489 Set Vref, RX VrefLevel [Byte0]: 66
3468 11:06:48.280765 [Byte1]: 66
3469 11:06:48.285268
3470 11:06:48.285432 Set Vref, RX VrefLevel [Byte0]: 67
3471 11:06:48.288352 [Byte1]: 67
3472 11:06:48.293112
3473 11:06:48.293312 Set Vref, RX VrefLevel [Byte0]: 68
3474 11:06:48.296532 [Byte1]: 68
3475 11:06:48.300962
3476 11:06:48.301179 Final RX Vref Byte 0 = 53 to rank0
3477 11:06:48.304312 Final RX Vref Byte 1 = 52 to rank0
3478 11:06:48.307516 Final RX Vref Byte 0 = 53 to rank1
3479 11:06:48.310832 Final RX Vref Byte 1 = 52 to rank1==
3480 11:06:48.314398 Dram Type= 6, Freq= 0, CH_1, rank 0
3481 11:06:48.320741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 11:06:48.321066 ==
3483 11:06:48.321321 DQS Delay:
3484 11:06:48.321514 DQS0 = 0, DQS1 = 0
3485 11:06:48.324490 DQM Delay:
3486 11:06:48.324903 DQM0 = 119, DQM1 = 112
3487 11:06:48.327632 DQ Delay:
3488 11:06:48.331256 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3489 11:06:48.334700 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3490 11:06:48.337886 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3491 11:06:48.340855 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3492 11:06:48.341307
3493 11:06:48.341641
3494 11:06:48.351031 [DQSOSCAuto] RK0, (LSB)MR18= 0x81b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 406 ps
3495 11:06:48.351534 CH1 RK0: MR19=404, MR18=81B
3496 11:06:48.357301 CH1_RK0: MR19=0x404, MR18=0x81B, DQSOSC=399, MR23=63, INC=41, DEC=27
3497 11:06:48.357735
3498 11:06:48.360808 ----->DramcWriteLeveling(PI) begin...
3499 11:06:48.361401 ==
3500 11:06:48.364644 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 11:06:48.367935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 11:06:48.371178 ==
3503 11:06:48.371692 Write leveling (Byte 0): 26 => 26
3504 11:06:48.374178 Write leveling (Byte 1): 29 => 29
3505 11:06:48.377534 DramcWriteLeveling(PI) end<-----
3506 11:06:48.377964
3507 11:06:48.378293 ==
3508 11:06:48.381288 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 11:06:48.387818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 11:06:48.388333 ==
3511 11:06:48.388686 [Gating] SW mode calibration
3512 11:06:48.397891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3513 11:06:48.401498 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3514 11:06:48.404425 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 11:06:48.411004 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 11:06:48.414381 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 11:06:48.417731 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 11:06:48.424448 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 11:06:48.427694 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 11:06:48.431207 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 1) (1 0)
3521 11:06:48.437487 0 15 28 | B1->B0 | 2323 2b2b | 0 1 | (1 0) (1 0)
3522 11:06:48.441338 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 11:06:48.444471 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 11:06:48.451100 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 11:06:48.454180 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 11:06:48.458091 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 11:06:48.464433 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 11:06:48.467743 1 0 24 | B1->B0 | 3a3a 2929 | 0 0 | (0 0) (0 0)
3529 11:06:48.470891 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3530 11:06:48.478015 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 11:06:48.481018 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 11:06:48.483983 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 11:06:48.490698 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 11:06:48.494156 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:06:48.497348 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3536 11:06:48.504250 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3537 11:06:48.507186 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3538 11:06:48.510446 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:06:48.517338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:06:48.520951 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:06:48.524092 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:06:48.530827 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:06:48.534083 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:06:48.537205 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:06:48.540546 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:06:48.547254 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:06:48.550248 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:06:48.553820 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:06:48.560679 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:06:48.563608 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:06:48.566919 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:06:48.573689 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3553 11:06:48.576888 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 11:06:48.580576 Total UI for P1: 0, mck2ui 16
3555 11:06:48.583772 best dqsien dly found for B0: ( 1, 3, 24)
3556 11:06:48.586851 Total UI for P1: 0, mck2ui 16
3557 11:06:48.590356 best dqsien dly found for B1: ( 1, 3, 24)
3558 11:06:48.593762 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3559 11:06:48.597497 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3560 11:06:48.598000
3561 11:06:48.600361 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3562 11:06:48.603478 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3563 11:06:48.606943 [Gating] SW calibration Done
3564 11:06:48.607378 ==
3565 11:06:48.610481 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 11:06:48.613909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 11:06:48.616926 ==
3568 11:06:48.617416 RX Vref Scan: 0
3569 11:06:48.617757
3570 11:06:48.620410 RX Vref 0 -> 0, step: 1
3571 11:06:48.620983
3572 11:06:48.623976 RX Delay -40 -> 252, step: 8
3573 11:06:48.627135 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3574 11:06:48.630295 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3575 11:06:48.633602 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3576 11:06:48.637050 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3577 11:06:48.644099 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3578 11:06:48.647205 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3579 11:06:48.650436 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3580 11:06:48.654114 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3581 11:06:48.657269 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3582 11:06:48.660307 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3583 11:06:48.667120 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3584 11:06:48.670535 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3585 11:06:48.673919 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3586 11:06:48.676699 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3587 11:06:48.683745 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3588 11:06:48.686630 iDelay=200, Bit 15, Center 127 (56 ~ 199) 144
3589 11:06:48.687061 ==
3590 11:06:48.690543 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 11:06:48.693326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 11:06:48.693764 ==
3593 11:06:48.696790 DQS Delay:
3594 11:06:48.697331 DQS0 = 0, DQS1 = 0
3595 11:06:48.697673 DQM Delay:
3596 11:06:48.699904 DQM0 = 119, DQM1 = 114
3597 11:06:48.700332 DQ Delay:
3598 11:06:48.703188 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3599 11:06:48.707313 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3600 11:06:48.710310 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3601 11:06:48.713992 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =127
3602 11:06:48.714506
3603 11:06:48.717105
3604 11:06:48.717659 ==
3605 11:06:48.720214 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 11:06:48.723904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 11:06:48.724364 ==
3608 11:06:48.724698
3609 11:06:48.725000
3610 11:06:48.726932 TX Vref Scan disable
3611 11:06:48.727415 == TX Byte 0 ==
3612 11:06:48.731042 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3613 11:06:48.737370 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3614 11:06:48.737809 == TX Byte 1 ==
3615 11:06:48.741023 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3616 11:06:48.747573 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3617 11:06:48.748021 ==
3618 11:06:48.751069 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 11:06:48.754150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 11:06:48.754592 ==
3621 11:06:48.765710 TX Vref=22, minBit 1, minWin=25, winSum=419
3622 11:06:48.769205 TX Vref=24, minBit 9, minWin=25, winSum=419
3623 11:06:48.772122 TX Vref=26, minBit 1, minWin=26, winSum=428
3624 11:06:48.775469 TX Vref=28, minBit 9, minWin=25, winSum=428
3625 11:06:48.778572 TX Vref=30, minBit 8, minWin=26, winSum=429
3626 11:06:48.782372 TX Vref=32, minBit 8, minWin=26, winSum=428
3627 11:06:48.788729 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3628 11:06:48.788885
3629 11:06:48.792099 Final TX Range 1 Vref 30
3630 11:06:48.792259
3631 11:06:48.792347 ==
3632 11:06:48.795284 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 11:06:48.798566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 11:06:48.798655 ==
3635 11:06:48.798723
3636 11:06:48.802256
3637 11:06:48.802344 TX Vref Scan disable
3638 11:06:48.805486 == TX Byte 0 ==
3639 11:06:48.808699 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3640 11:06:48.811819 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3641 11:06:48.815617 == TX Byte 1 ==
3642 11:06:48.818723 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3643 11:06:48.822331 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3644 11:06:48.822479
3645 11:06:48.825478 [DATLAT]
3646 11:06:48.825627 Freq=1200, CH1 RK1
3647 11:06:48.825703
3648 11:06:48.829179 DATLAT Default: 0xd
3649 11:06:48.829335 0, 0xFFFF, sum = 0
3650 11:06:48.832395 1, 0xFFFF, sum = 0
3651 11:06:48.832570 2, 0xFFFF, sum = 0
3652 11:06:48.835427 3, 0xFFFF, sum = 0
3653 11:06:48.835593 4, 0xFFFF, sum = 0
3654 11:06:48.838685 5, 0xFFFF, sum = 0
3655 11:06:48.838861 6, 0xFFFF, sum = 0
3656 11:06:48.841790 7, 0xFFFF, sum = 0
3657 11:06:48.845650 8, 0xFFFF, sum = 0
3658 11:06:48.845843 9, 0xFFFF, sum = 0
3659 11:06:48.848866 10, 0xFFFF, sum = 0
3660 11:06:48.849071 11, 0xFFFF, sum = 0
3661 11:06:48.852359 12, 0x0, sum = 1
3662 11:06:48.852591 13, 0x0, sum = 2
3663 11:06:48.855568 14, 0x0, sum = 3
3664 11:06:48.855797 15, 0x0, sum = 4
3665 11:06:48.855936 best_step = 13
3666 11:06:48.856055
3667 11:06:48.858710 ==
3668 11:06:48.861959 Dram Type= 6, Freq= 0, CH_1, rank 1
3669 11:06:48.865536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3670 11:06:48.865831 ==
3671 11:06:48.866013 RX Vref Scan: 0
3672 11:06:48.866176
3673 11:06:48.868819 RX Vref 0 -> 0, step: 1
3674 11:06:48.869096
3675 11:06:48.872301 RX Delay -13 -> 252, step: 4
3676 11:06:48.875579 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3677 11:06:48.882246 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3678 11:06:48.885484 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3679 11:06:48.889297 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3680 11:06:48.891942 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3681 11:06:48.895446 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3682 11:06:48.902197 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3683 11:06:48.905512 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3684 11:06:48.908735 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3685 11:06:48.912069 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3686 11:06:48.915406 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3687 11:06:48.922254 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3688 11:06:48.925358 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3689 11:06:48.928542 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3690 11:06:48.931837 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3691 11:06:48.935331 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3692 11:06:48.935894 ==
3693 11:06:48.938643 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 11:06:48.945100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 11:06:48.945582 ==
3696 11:06:48.945946 DQS Delay:
3697 11:06:48.948632 DQS0 = 0, DQS1 = 0
3698 11:06:48.949064 DQM Delay:
3699 11:06:48.952387 DQM0 = 119, DQM1 = 113
3700 11:06:48.953189 DQ Delay:
3701 11:06:48.955210 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3702 11:06:48.958489 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3703 11:06:48.961598 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =108
3704 11:06:48.965282 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3705 11:06:48.965711
3706 11:06:48.966040
3707 11:06:48.975384 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3708 11:06:48.975889 CH1 RK1: MR19=403, MR18=9EE
3709 11:06:48.982104 CH1_RK1: MR19=0x403, MR18=0x9EE, DQSOSC=406, MR23=63, INC=39, DEC=26
3710 11:06:48.985303 [RxdqsGatingPostProcess] freq 1200
3711 11:06:48.991803 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3712 11:06:48.994900 best DQS0 dly(2T, 0.5T) = (0, 11)
3713 11:06:48.998447 best DQS1 dly(2T, 0.5T) = (0, 11)
3714 11:06:49.002047 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3715 11:06:49.005239 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3716 11:06:49.005736 best DQS0 dly(2T, 0.5T) = (0, 11)
3717 11:06:49.008398 best DQS1 dly(2T, 0.5T) = (0, 11)
3718 11:06:49.011924 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3719 11:06:49.015034 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3720 11:06:49.018572 Pre-setting of DQS Precalculation
3721 11:06:49.025659 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3722 11:06:49.032194 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3723 11:06:49.038731 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3724 11:06:49.039235
3725 11:06:49.039569
3726 11:06:49.042298 [Calibration Summary] 2400 Mbps
3727 11:06:49.042975 CH 0, Rank 0
3728 11:06:49.045659 SW Impedance : PASS
3729 11:06:49.048393 DUTY Scan : NO K
3730 11:06:49.048820 ZQ Calibration : PASS
3731 11:06:49.052008 Jitter Meter : NO K
3732 11:06:49.055179 CBT Training : PASS
3733 11:06:49.055682 Write leveling : PASS
3734 11:06:49.058456 RX DQS gating : PASS
3735 11:06:49.062017 RX DQ/DQS(RDDQC) : PASS
3736 11:06:49.062520 TX DQ/DQS : PASS
3737 11:06:49.065237 RX DATLAT : PASS
3738 11:06:49.068694 RX DQ/DQS(Engine): PASS
3739 11:06:49.069236 TX OE : NO K
3740 11:06:49.069580 All Pass.
3741 11:06:49.072225
3742 11:06:49.072724 CH 0, Rank 1
3743 11:06:49.075049 SW Impedance : PASS
3744 11:06:49.075481 DUTY Scan : NO K
3745 11:06:49.078895 ZQ Calibration : PASS
3746 11:06:49.079395 Jitter Meter : NO K
3747 11:06:49.082106 CBT Training : PASS
3748 11:06:49.085361 Write leveling : PASS
3749 11:06:49.085867 RX DQS gating : PASS
3750 11:06:49.088776 RX DQ/DQS(RDDQC) : PASS
3751 11:06:49.091795 TX DQ/DQS : PASS
3752 11:06:49.092304 RX DATLAT : PASS
3753 11:06:49.095266 RX DQ/DQS(Engine): PASS
3754 11:06:49.098547 TX OE : NO K
3755 11:06:49.099054 All Pass.
3756 11:06:49.099384
3757 11:06:49.099691 CH 1, Rank 0
3758 11:06:49.101463 SW Impedance : PASS
3759 11:06:49.104781 DUTY Scan : NO K
3760 11:06:49.105233 ZQ Calibration : PASS
3761 11:06:49.108452 Jitter Meter : NO K
3762 11:06:49.111676 CBT Training : PASS
3763 11:06:49.112186 Write leveling : PASS
3764 11:06:49.115103 RX DQS gating : PASS
3765 11:06:49.118424 RX DQ/DQS(RDDQC) : PASS
3766 11:06:49.118932 TX DQ/DQS : PASS
3767 11:06:49.121535 RX DATLAT : PASS
3768 11:06:49.124970 RX DQ/DQS(Engine): PASS
3769 11:06:49.125543 TX OE : NO K
3770 11:06:49.125886 All Pass.
3771 11:06:49.128665
3772 11:06:49.129208 CH 1, Rank 1
3773 11:06:49.129554 SW Impedance : PASS
3774 11:06:49.131898 DUTY Scan : NO K
3775 11:06:49.135016 ZQ Calibration : PASS
3776 11:06:49.135525 Jitter Meter : NO K
3777 11:06:49.138347 CBT Training : PASS
3778 11:06:49.142034 Write leveling : PASS
3779 11:06:49.142545 RX DQS gating : PASS
3780 11:06:49.145050 RX DQ/DQS(RDDQC) : PASS
3781 11:06:49.148508 TX DQ/DQS : PASS
3782 11:06:49.149016 RX DATLAT : PASS
3783 11:06:49.151802 RX DQ/DQS(Engine): PASS
3784 11:06:49.155106 TX OE : NO K
3785 11:06:49.155618 All Pass.
3786 11:06:49.155951
3787 11:06:49.156258 DramC Write-DBI off
3788 11:06:49.158003 PER_BANK_REFRESH: Hybrid Mode
3789 11:06:49.161392 TX_TRACKING: ON
3790 11:06:49.167987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3791 11:06:49.174794 [FAST_K] Save calibration result to emmc
3792 11:06:49.178311 dramc_set_vcore_voltage set vcore to 650000
3793 11:06:49.178819 Read voltage for 600, 5
3794 11:06:49.181709 Vio18 = 0
3795 11:06:49.182217 Vcore = 650000
3796 11:06:49.182553 Vdram = 0
3797 11:06:49.184923 Vddq = 0
3798 11:06:49.185453 Vmddr = 0
3799 11:06:49.188460 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3800 11:06:49.194952 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3801 11:06:49.197982 MEM_TYPE=3, freq_sel=19
3802 11:06:49.201310 sv_algorithm_assistance_LP4_1600
3803 11:06:49.204790 ============ PULL DRAM RESETB DOWN ============
3804 11:06:49.208384 ========== PULL DRAM RESETB DOWN end =========
3805 11:06:49.211396 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3806 11:06:49.214605 ===================================
3807 11:06:49.217839 LPDDR4 DRAM CONFIGURATION
3808 11:06:49.221857 ===================================
3809 11:06:49.224759 EX_ROW_EN[0] = 0x0
3810 11:06:49.225310 EX_ROW_EN[1] = 0x0
3811 11:06:49.228078 LP4Y_EN = 0x0
3812 11:06:49.228608 WORK_FSP = 0x0
3813 11:06:49.231478 WL = 0x2
3814 11:06:49.231986 RL = 0x2
3815 11:06:49.234946 BL = 0x2
3816 11:06:49.235454 RPST = 0x0
3817 11:06:49.238196 RD_PRE = 0x0
3818 11:06:49.238702 WR_PRE = 0x1
3819 11:06:49.241545 WR_PST = 0x0
3820 11:06:49.244695 DBI_WR = 0x0
3821 11:06:49.245252 DBI_RD = 0x0
3822 11:06:49.247682 OTF = 0x1
3823 11:06:49.251291 ===================================
3824 11:06:49.254786 ===================================
3825 11:06:49.255295 ANA top config
3826 11:06:49.258000 ===================================
3827 11:06:49.261251 DLL_ASYNC_EN = 0
3828 11:06:49.261754 ALL_SLAVE_EN = 1
3829 11:06:49.264323 NEW_RANK_MODE = 1
3830 11:06:49.268119 DLL_IDLE_MODE = 1
3831 11:06:49.271151 LP45_APHY_COMB_EN = 1
3832 11:06:49.274357 TX_ODT_DIS = 1
3833 11:06:49.274783 NEW_8X_MODE = 1
3834 11:06:49.277635 ===================================
3835 11:06:49.281371 ===================================
3836 11:06:49.284577 data_rate = 1200
3837 11:06:49.288076 CKR = 1
3838 11:06:49.291470 DQ_P2S_RATIO = 8
3839 11:06:49.294814 ===================================
3840 11:06:49.297947 CA_P2S_RATIO = 8
3841 11:06:49.300991 DQ_CA_OPEN = 0
3842 11:06:49.301467 DQ_SEMI_OPEN = 0
3843 11:06:49.304562 CA_SEMI_OPEN = 0
3844 11:06:49.307872 CA_FULL_RATE = 0
3845 11:06:49.310990 DQ_CKDIV4_EN = 1
3846 11:06:49.314446 CA_CKDIV4_EN = 1
3847 11:06:49.317785 CA_PREDIV_EN = 0
3848 11:06:49.318214 PH8_DLY = 0
3849 11:06:49.321303 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3850 11:06:49.324353 DQ_AAMCK_DIV = 4
3851 11:06:49.328371 CA_AAMCK_DIV = 4
3852 11:06:49.331583 CA_ADMCK_DIV = 4
3853 11:06:49.332085 DQ_TRACK_CA_EN = 0
3854 11:06:49.334920 CA_PICK = 600
3855 11:06:49.338002 CA_MCKIO = 600
3856 11:06:49.341545 MCKIO_SEMI = 0
3857 11:06:49.344876 PLL_FREQ = 2288
3858 11:06:49.348385 DQ_UI_PI_RATIO = 32
3859 11:06:49.351194 CA_UI_PI_RATIO = 0
3860 11:06:49.354735 ===================================
3861 11:06:49.358093 ===================================
3862 11:06:49.358603 memory_type:LPDDR4
3863 11:06:49.361303 GP_NUM : 10
3864 11:06:49.364573 SRAM_EN : 1
3865 11:06:49.365080 MD32_EN : 0
3866 11:06:49.368405 ===================================
3867 11:06:49.371584 [ANA_INIT] >>>>>>>>>>>>>>
3868 11:06:49.374397 <<<<<< [CONFIGURE PHASE]: ANA_TX
3869 11:06:49.377941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3870 11:06:49.381517 ===================================
3871 11:06:49.382020 data_rate = 1200,PCW = 0X5800
3872 11:06:49.384562 ===================================
3873 11:06:49.391323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3874 11:06:49.394819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3875 11:06:49.401434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3876 11:06:49.404888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3877 11:06:49.408348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3878 11:06:49.411571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3879 11:06:49.414649 [ANA_INIT] flow start
3880 11:06:49.417818 [ANA_INIT] PLL >>>>>>>>
3881 11:06:49.418246 [ANA_INIT] PLL <<<<<<<<
3882 11:06:49.421394 [ANA_INIT] MIDPI >>>>>>>>
3883 11:06:49.424909 [ANA_INIT] MIDPI <<<<<<<<
3884 11:06:49.425461 [ANA_INIT] DLL >>>>>>>>
3885 11:06:49.427999 [ANA_INIT] flow end
3886 11:06:49.431521 ============ LP4 DIFF to SE enter ============
3887 11:06:49.434774 ============ LP4 DIFF to SE exit ============
3888 11:06:49.438078 [ANA_INIT] <<<<<<<<<<<<<
3889 11:06:49.441566 [Flow] Enable top DCM control >>>>>
3890 11:06:49.444945 [Flow] Enable top DCM control <<<<<
3891 11:06:49.448257 Enable DLL master slave shuffle
3892 11:06:49.454921 ==============================================================
3893 11:06:49.455424 Gating Mode config
3894 11:06:49.461629 ==============================================================
3895 11:06:49.462139 Config description:
3896 11:06:49.471308 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3897 11:06:49.478534 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3898 11:06:49.484815 SELPH_MODE 0: By rank 1: By Phase
3899 11:06:49.488218 ==============================================================
3900 11:06:49.491185 GAT_TRACK_EN = 1
3901 11:06:49.494762 RX_GATING_MODE = 2
3902 11:06:49.497981 RX_GATING_TRACK_MODE = 2
3903 11:06:49.501301 SELPH_MODE = 1
3904 11:06:49.504987 PICG_EARLY_EN = 1
3905 11:06:49.507838 VALID_LAT_VALUE = 1
3906 11:06:49.511264 ==============================================================
3907 11:06:49.514939 Enter into Gating configuration >>>>
3908 11:06:49.517837 Exit from Gating configuration <<<<
3909 11:06:49.521333 Enter into DVFS_PRE_config >>>>>
3910 11:06:49.534586 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3911 11:06:49.537994 Exit from DVFS_PRE_config <<<<<
3912 11:06:49.541504 Enter into PICG configuration >>>>
3913 11:06:49.544385 Exit from PICG configuration <<<<
3914 11:06:49.544814 [RX_INPUT] configuration >>>>>
3915 11:06:49.547619 [RX_INPUT] configuration <<<<<
3916 11:06:49.554852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3917 11:06:49.558029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3918 11:06:49.564552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 11:06:49.570827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 11:06:49.577625 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3921 11:06:49.584414 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3922 11:06:49.587614 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3923 11:06:49.590946 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3924 11:06:49.597581 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3925 11:06:49.600605 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3926 11:06:49.604094 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3927 11:06:49.607181 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 11:06:49.610343 ===================================
3929 11:06:49.613500 LPDDR4 DRAM CONFIGURATION
3930 11:06:49.616928 ===================================
3931 11:06:49.620263 EX_ROW_EN[0] = 0x0
3932 11:06:49.620404 EX_ROW_EN[1] = 0x0
3933 11:06:49.623205 LP4Y_EN = 0x0
3934 11:06:49.623356 WORK_FSP = 0x0
3935 11:06:49.627010 WL = 0x2
3936 11:06:49.627152 RL = 0x2
3937 11:06:49.630160 BL = 0x2
3938 11:06:49.630296 RPST = 0x0
3939 11:06:49.633662 RD_PRE = 0x0
3940 11:06:49.633828 WR_PRE = 0x1
3941 11:06:49.636974 WR_PST = 0x0
3942 11:06:49.640301 DBI_WR = 0x0
3943 11:06:49.640477 DBI_RD = 0x0
3944 11:06:49.643635 OTF = 0x1
3945 11:06:49.646700 ===================================
3946 11:06:49.650052 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3947 11:06:49.653541 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3948 11:06:49.657199 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3949 11:06:49.660358 ===================================
3950 11:06:49.663687 LPDDR4 DRAM CONFIGURATION
3951 11:06:49.667046 ===================================
3952 11:06:49.670172 EX_ROW_EN[0] = 0x10
3953 11:06:49.670524 EX_ROW_EN[1] = 0x0
3954 11:06:49.673849 LP4Y_EN = 0x0
3955 11:06:49.674287 WORK_FSP = 0x0
3956 11:06:49.677103 WL = 0x2
3957 11:06:49.677751 RL = 0x2
3958 11:06:49.680625 BL = 0x2
3959 11:06:49.681160 RPST = 0x0
3960 11:06:49.683523 RD_PRE = 0x0
3961 11:06:49.683947 WR_PRE = 0x1
3962 11:06:49.687220 WR_PST = 0x0
3963 11:06:49.687729 DBI_WR = 0x0
3964 11:06:49.690568 DBI_RD = 0x0
3965 11:06:49.691075 OTF = 0x1
3966 11:06:49.693491 ===================================
3967 11:06:49.700333 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3968 11:06:49.705166 nWR fixed to 30
3969 11:06:49.708218 [ModeRegInit_LP4] CH0 RK0
3970 11:06:49.708730 [ModeRegInit_LP4] CH0 RK1
3971 11:06:49.711816 [ModeRegInit_LP4] CH1 RK0
3972 11:06:49.714978 [ModeRegInit_LP4] CH1 RK1
3973 11:06:49.715477 match AC timing 17
3974 11:06:49.722076 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3975 11:06:49.724902 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3976 11:06:49.728450 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3977 11:06:49.734839 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3978 11:06:49.738615 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3979 11:06:49.739121 ==
3980 11:06:49.741733 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 11:06:49.745255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 11:06:49.745758 ==
3983 11:06:49.751573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3984 11:06:49.758212 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3985 11:06:49.761457 [CA 0] Center 36 (6~67) winsize 62
3986 11:06:49.765422 [CA 1] Center 36 (6~67) winsize 62
3987 11:06:49.768639 [CA 2] Center 34 (4~65) winsize 62
3988 11:06:49.771387 [CA 3] Center 34 (3~65) winsize 63
3989 11:06:49.775215 [CA 4] Center 33 (3~64) winsize 62
3990 11:06:49.778554 [CA 5] Center 33 (2~64) winsize 63
3991 11:06:49.779060
3992 11:06:49.781734 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3993 11:06:49.782237
3994 11:06:49.784998 [CATrainingPosCal] consider 1 rank data
3995 11:06:49.788386 u2DelayCellTimex100 = 270/100 ps
3996 11:06:49.791572 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3997 11:06:49.794850 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 11:06:49.798296 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 11:06:49.801822 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4000 11:06:49.804969 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 11:06:49.808050 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4002 11:06:49.811371
4003 11:06:49.815065 CA PerBit enable=1, Macro0, CA PI delay=33
4004 11:06:49.815629
4005 11:06:49.818322 [CBTSetCACLKResult] CA Dly = 33
4006 11:06:49.818747 CS Dly: 7 (0~38)
4007 11:06:49.819293 ==
4008 11:06:49.821593 Dram Type= 6, Freq= 0, CH_0, rank 1
4009 11:06:49.825070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 11:06:49.825618 ==
4011 11:06:49.831398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4012 11:06:49.838547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4013 11:06:49.841656 [CA 0] Center 36 (6~67) winsize 62
4014 11:06:49.844933 [CA 1] Center 36 (6~67) winsize 62
4015 11:06:49.848311 [CA 2] Center 35 (4~66) winsize 63
4016 11:06:49.851690 [CA 3] Center 34 (4~65) winsize 62
4017 11:06:49.855514 [CA 4] Center 34 (3~65) winsize 63
4018 11:06:49.858562 [CA 5] Center 33 (3~64) winsize 62
4019 11:06:49.858991
4020 11:06:49.861876 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4021 11:06:49.862299
4022 11:06:49.865497 [CATrainingPosCal] consider 2 rank data
4023 11:06:49.868530 u2DelayCellTimex100 = 270/100 ps
4024 11:06:49.871973 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4025 11:06:49.875457 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4026 11:06:49.878638 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4027 11:06:49.882079 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4028 11:06:49.885444 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4029 11:06:49.889260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4030 11:06:49.889759
4031 11:06:49.895297 CA PerBit enable=1, Macro0, CA PI delay=33
4032 11:06:49.895801
4033 11:06:49.896134 [CBTSetCACLKResult] CA Dly = 33
4034 11:06:49.898707 CS Dly: 7 (0~38)
4035 11:06:49.899209
4036 11:06:49.902105 ----->DramcWriteLeveling(PI) begin...
4037 11:06:49.902626 ==
4038 11:06:49.905309 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 11:06:49.908338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 11:06:49.908767 ==
4041 11:06:49.912013 Write leveling (Byte 0): 35 => 35
4042 11:06:49.915578 Write leveling (Byte 1): 32 => 32
4043 11:06:49.918511 DramcWriteLeveling(PI) end<-----
4044 11:06:49.918942
4045 11:06:49.919283 ==
4046 11:06:49.921814 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 11:06:49.925523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 11:06:49.928391 ==
4049 11:06:49.928820 [Gating] SW mode calibration
4050 11:06:49.938807 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4051 11:06:49.941927 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4052 11:06:49.945209 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 11:06:49.951857 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 11:06:49.955227 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 11:06:49.958485 0 9 12 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
4056 11:06:49.965242 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4057 11:06:49.968544 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 11:06:49.971632 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 11:06:49.978466 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 11:06:49.981575 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 11:06:49.985188 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 11:06:49.991905 0 10 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
4063 11:06:49.995049 0 10 12 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
4064 11:06:49.998259 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4065 11:06:50.001650 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 11:06:50.008479 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 11:06:50.011958 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 11:06:50.015490 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 11:06:50.022015 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 11:06:50.025168 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:06:50.028688 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4072 11:06:50.035485 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:06:50.038895 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:06:50.041947 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:06:50.048365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:06:50.052057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:06:50.055267 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:06:50.061923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:06:50.065091 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:06:50.068834 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:06:50.074999 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:06:50.078436 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:06:50.081810 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:06:50.088528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:06:50.091713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:06:50.095173 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4087 11:06:50.101408 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4088 11:06:50.105229 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 11:06:50.108424 Total UI for P1: 0, mck2ui 16
4090 11:06:50.111790 best dqsien dly found for B0: ( 0, 13, 10)
4091 11:06:50.115132 Total UI for P1: 0, mck2ui 16
4092 11:06:50.118572 best dqsien dly found for B1: ( 0, 13, 14)
4093 11:06:50.121497 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4094 11:06:50.124870 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4095 11:06:50.125348
4096 11:06:50.128371 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4097 11:06:50.131886 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4098 11:06:50.135135 [Gating] SW calibration Done
4099 11:06:50.135641 ==
4100 11:06:50.138385 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 11:06:50.141672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 11:06:50.142199 ==
4103 11:06:50.145341 RX Vref Scan: 0
4104 11:06:50.145867
4105 11:06:50.148356 RX Vref 0 -> 0, step: 1
4106 11:06:50.148785
4107 11:06:50.149155 RX Delay -230 -> 252, step: 16
4108 11:06:50.155247 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4109 11:06:50.158087 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4110 11:06:50.162123 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4111 11:06:50.164751 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4112 11:06:50.171866 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4113 11:06:50.175101 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4114 11:06:50.178216 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4115 11:06:50.181719 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4116 11:06:50.184974 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4117 11:06:50.191879 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4118 11:06:50.195119 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4119 11:06:50.198352 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4120 11:06:50.201774 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4121 11:06:50.208546 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4122 11:06:50.212051 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4123 11:06:50.215242 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4124 11:06:50.215763 ==
4125 11:06:50.218281 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 11:06:50.221678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 11:06:50.222112 ==
4128 11:06:50.224787 DQS Delay:
4129 11:06:50.225247 DQS0 = 0, DQS1 = 0
4130 11:06:50.228400 DQM Delay:
4131 11:06:50.228912 DQM0 = 53, DQM1 = 43
4132 11:06:50.229304 DQ Delay:
4133 11:06:50.231858 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4134 11:06:50.234941 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4135 11:06:50.238071 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4136 11:06:50.241732 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4137 11:06:50.242242
4138 11:06:50.242574
4139 11:06:50.244567 ==
4140 11:06:50.248385 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 11:06:50.251686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 11:06:50.252212 ==
4143 11:06:50.252555
4144 11:06:50.252860
4145 11:06:50.254869 TX Vref Scan disable
4146 11:06:50.255300 == TX Byte 0 ==
4147 11:06:50.261568 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4148 11:06:50.264792 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4149 11:06:50.265268 == TX Byte 1 ==
4150 11:06:50.268624 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4151 11:06:50.274920 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4152 11:06:50.275355 ==
4153 11:06:50.278259 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 11:06:50.281424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 11:06:50.281858 ==
4156 11:06:50.282189
4157 11:06:50.282491
4158 11:06:50.284573 TX Vref Scan disable
4159 11:06:50.288157 == TX Byte 0 ==
4160 11:06:50.291860 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4161 11:06:50.295394 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4162 11:06:50.298147 == TX Byte 1 ==
4163 11:06:50.301571 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4164 11:06:50.305047 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4165 11:06:50.305600
4166 11:06:50.308069 [DATLAT]
4167 11:06:50.308495 Freq=600, CH0 RK0
4168 11:06:50.308831
4169 11:06:50.311670 DATLAT Default: 0x9
4170 11:06:50.312102 0, 0xFFFF, sum = 0
4171 11:06:50.315007 1, 0xFFFF, sum = 0
4172 11:06:50.315528 2, 0xFFFF, sum = 0
4173 11:06:50.318207 3, 0xFFFF, sum = 0
4174 11:06:50.318732 4, 0xFFFF, sum = 0
4175 11:06:50.321354 5, 0xFFFF, sum = 0
4176 11:06:50.321795 6, 0xFFFF, sum = 0
4177 11:06:50.325012 7, 0xFFFF, sum = 0
4178 11:06:50.325500 8, 0x0, sum = 1
4179 11:06:50.328287 9, 0x0, sum = 2
4180 11:06:50.328722 10, 0x0, sum = 3
4181 11:06:50.331962 11, 0x0, sum = 4
4182 11:06:50.332493 best_step = 9
4183 11:06:50.332834
4184 11:06:50.333184 ==
4185 11:06:50.334922 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 11:06:50.338344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 11:06:50.338867 ==
4188 11:06:50.341849 RX Vref Scan: 1
4189 11:06:50.342359
4190 11:06:50.344902 RX Vref 0 -> 0, step: 1
4191 11:06:50.345475
4192 11:06:50.345819 RX Delay -179 -> 252, step: 8
4193 11:06:50.348489
4194 11:06:50.348999 Set Vref, RX VrefLevel [Byte0]: 60
4195 11:06:50.351329 [Byte1]: 54
4196 11:06:50.356209
4197 11:06:50.356728 Final RX Vref Byte 0 = 60 to rank0
4198 11:06:50.359598 Final RX Vref Byte 1 = 54 to rank0
4199 11:06:50.362742 Final RX Vref Byte 0 = 60 to rank1
4200 11:06:50.366034 Final RX Vref Byte 1 = 54 to rank1==
4201 11:06:50.369764 Dram Type= 6, Freq= 0, CH_0, rank 0
4202 11:06:50.376414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 11:06:50.376936 ==
4204 11:06:50.377390 DQS Delay:
4205 11:06:50.377751 DQS0 = 0, DQS1 = 0
4206 11:06:50.379205 DQM Delay:
4207 11:06:50.379641 DQM0 = 50, DQM1 = 38
4208 11:06:50.382789 DQ Delay:
4209 11:06:50.386333 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4210 11:06:50.389814 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4211 11:06:50.392810 DQ8 =32, DQ9 =24, DQ10 =40, DQ11 =32
4212 11:06:50.396147 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =48
4213 11:06:50.396662
4214 11:06:50.396999
4215 11:06:50.402494 [DQSOSCAuto] RK0, (LSB)MR18= 0x615b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4216 11:06:50.406065 CH0 RK0: MR19=808, MR18=615B
4217 11:06:50.412628 CH0_RK0: MR19=0x808, MR18=0x615B, DQSOSC=391, MR23=63, INC=171, DEC=114
4218 11:06:50.413185
4219 11:06:50.416530 ----->DramcWriteLeveling(PI) begin...
4220 11:06:50.417053 ==
4221 11:06:50.419341 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 11:06:50.422580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 11:06:50.423015 ==
4224 11:06:50.425960 Write leveling (Byte 0): 32 => 32
4225 11:06:50.429400 Write leveling (Byte 1): 31 => 31
4226 11:06:50.432714 DramcWriteLeveling(PI) end<-----
4227 11:06:50.433286
4228 11:06:50.433635 ==
4229 11:06:50.436136 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 11:06:50.439607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 11:06:50.440125 ==
4232 11:06:50.442835 [Gating] SW mode calibration
4233 11:06:50.449624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4234 11:06:50.456231 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4235 11:06:50.459582 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 11:06:50.462705 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 11:06:50.469382 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 11:06:50.472903 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (0 1) (0 1)
4239 11:06:50.475862 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4240 11:06:50.483203 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 11:06:50.485917 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 11:06:50.489560 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 11:06:50.495871 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 11:06:50.499263 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 11:06:50.502367 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 11:06:50.509456 0 10 12 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (1 1)
4247 11:06:50.512710 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 11:06:50.516482 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 11:06:50.522785 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 11:06:50.526306 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 11:06:50.529702 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:06:50.533184 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 11:06:50.539900 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 11:06:50.543002 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4255 11:06:50.545969 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:06:50.553228 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:06:50.556302 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:06:50.559508 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:06:50.565971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:06:50.569587 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:06:50.572709 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:06:50.579326 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:06:50.582931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:06:50.585920 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:06:50.592680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:06:50.596080 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:06:50.599410 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:06:50.605789 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:06:50.609171 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:06:50.612670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4271 11:06:50.619237 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4272 11:06:50.619749 Total UI for P1: 0, mck2ui 16
4273 11:06:50.625827 best dqsien dly found for B1: ( 0, 13, 14)
4274 11:06:50.629063 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 11:06:50.632214 Total UI for P1: 0, mck2ui 16
4276 11:06:50.635445 best dqsien dly found for B0: ( 0, 13, 14)
4277 11:06:50.638694 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4278 11:06:50.642209 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4279 11:06:50.642727
4280 11:06:50.645637 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4281 11:06:50.648766 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4282 11:06:50.652338 [Gating] SW calibration Done
4283 11:06:50.652847 ==
4284 11:06:50.655595 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 11:06:50.659050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 11:06:50.662304 ==
4287 11:06:50.662811 RX Vref Scan: 0
4288 11:06:50.663146
4289 11:06:50.665581 RX Vref 0 -> 0, step: 1
4290 11:06:50.666015
4291 11:06:50.669036 RX Delay -230 -> 252, step: 16
4292 11:06:50.672451 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4293 11:06:50.675910 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4294 11:06:50.678819 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4295 11:06:50.685876 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4296 11:06:50.688871 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4297 11:06:50.692399 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4298 11:06:50.695342 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4299 11:06:50.699229 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4300 11:06:50.705594 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4301 11:06:50.709190 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4302 11:06:50.712389 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4303 11:06:50.715691 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4304 11:06:50.719464 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4305 11:06:50.725450 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4306 11:06:50.729285 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4307 11:06:50.732326 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4308 11:06:50.732839 ==
4309 11:06:50.735441 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 11:06:50.742398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 11:06:50.742912 ==
4312 11:06:50.743251 DQS Delay:
4313 11:06:50.743565 DQS0 = 0, DQS1 = 0
4314 11:06:50.745675 DQM Delay:
4315 11:06:50.746104 DQM0 = 50, DQM1 = 39
4316 11:06:50.748633 DQ Delay:
4317 11:06:50.752499 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4318 11:06:50.753005 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4319 11:06:50.755646 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4320 11:06:50.759393 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4321 11:06:50.762297
4322 11:06:50.762806
4323 11:06:50.763141 ==
4324 11:06:50.765313 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 11:06:50.769115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 11:06:50.769672 ==
4327 11:06:50.770017
4328 11:06:50.770329
4329 11:06:50.771841 TX Vref Scan disable
4330 11:06:50.772274 == TX Byte 0 ==
4331 11:06:50.778877 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4332 11:06:50.782225 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4333 11:06:50.782740 == TX Byte 1 ==
4334 11:06:50.789006 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4335 11:06:50.791943 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4336 11:06:50.792377 ==
4337 11:06:50.795595 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 11:06:50.798988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 11:06:50.799506 ==
4340 11:06:50.799841
4341 11:06:50.800149
4342 11:06:50.802436 TX Vref Scan disable
4343 11:06:50.805732 == TX Byte 0 ==
4344 11:06:50.809040 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4345 11:06:50.812216 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4346 11:06:50.815467 == TX Byte 1 ==
4347 11:06:50.818686 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4348 11:06:50.822047 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4349 11:06:50.822591
4350 11:06:50.825342 [DATLAT]
4351 11:06:50.825773 Freq=600, CH0 RK1
4352 11:06:50.826204
4353 11:06:50.828877 DATLAT Default: 0x9
4354 11:06:50.829441 0, 0xFFFF, sum = 0
4355 11:06:50.832141 1, 0xFFFF, sum = 0
4356 11:06:50.832656 2, 0xFFFF, sum = 0
4357 11:06:50.835787 3, 0xFFFF, sum = 0
4358 11:06:50.836302 4, 0xFFFF, sum = 0
4359 11:06:50.838573 5, 0xFFFF, sum = 0
4360 11:06:50.839012 6, 0xFFFF, sum = 0
4361 11:06:50.842099 7, 0xFFFF, sum = 0
4362 11:06:50.842612 8, 0x0, sum = 1
4363 11:06:50.845400 9, 0x0, sum = 2
4364 11:06:50.845915 10, 0x0, sum = 3
4365 11:06:50.848692 11, 0x0, sum = 4
4366 11:06:50.849305 best_step = 9
4367 11:06:50.849650
4368 11:06:50.849958 ==
4369 11:06:50.852118 Dram Type= 6, Freq= 0, CH_0, rank 1
4370 11:06:50.858194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 11:06:50.858275 ==
4372 11:06:50.858334 RX Vref Scan: 0
4373 11:06:50.858388
4374 11:06:50.861804 RX Vref 0 -> 0, step: 1
4375 11:06:50.861881
4376 11:06:50.864993 RX Delay -179 -> 252, step: 8
4377 11:06:50.868226 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4378 11:06:50.871666 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4379 11:06:50.878135 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4380 11:06:50.881639 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4381 11:06:50.884992 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4382 11:06:50.888473 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4383 11:06:50.891501 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4384 11:06:50.898113 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4385 11:06:50.901489 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4386 11:06:50.904609 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4387 11:06:50.908255 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4388 11:06:50.915096 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4389 11:06:50.918602 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4390 11:06:50.922045 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4391 11:06:50.925029 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4392 11:06:50.928392 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4393 11:06:50.931891 ==
4394 11:06:50.935150 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 11:06:50.938313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 11:06:50.938740 ==
4397 11:06:50.939065 DQS Delay:
4398 11:06:50.941760 DQS0 = 0, DQS1 = 0
4399 11:06:50.942255 DQM Delay:
4400 11:06:50.945259 DQM0 = 48, DQM1 = 40
4401 11:06:50.945755 DQ Delay:
4402 11:06:50.948794 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4403 11:06:50.951681 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4404 11:06:50.955193 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4405 11:06:50.958111 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =52
4406 11:06:50.958605
4407 11:06:50.958934
4408 11:06:50.965108 [DQSOSCAuto] RK1, (LSB)MR18= 0x6633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4409 11:06:50.967875 CH0 RK1: MR19=808, MR18=6633
4410 11:06:50.974788 CH0_RK1: MR19=0x808, MR18=0x6633, DQSOSC=390, MR23=63, INC=172, DEC=114
4411 11:06:50.978346 [RxdqsGatingPostProcess] freq 600
4412 11:06:50.985002 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4413 11:06:50.985545 Pre-setting of DQS Precalculation
4414 11:06:50.991699 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4415 11:06:50.992199 ==
4416 11:06:50.995109 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 11:06:50.998352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 11:06:50.998848 ==
4419 11:06:51.004909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 11:06:51.011524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4421 11:06:51.014939 [CA 0] Center 35 (5~66) winsize 62
4422 11:06:51.018099 [CA 1] Center 35 (4~66) winsize 63
4423 11:06:51.021564 [CA 2] Center 34 (4~64) winsize 61
4424 11:06:51.025027 [CA 3] Center 33 (3~64) winsize 62
4425 11:06:51.028275 [CA 4] Center 33 (3~64) winsize 62
4426 11:06:51.031304 [CA 5] Center 33 (3~64) winsize 62
4427 11:06:51.031882
4428 11:06:51.034991 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4429 11:06:51.035408
4430 11:06:51.037947 [CATrainingPosCal] consider 1 rank data
4431 11:06:51.041219 u2DelayCellTimex100 = 270/100 ps
4432 11:06:51.044404 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 11:06:51.047883 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4434 11:06:51.051399 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4435 11:06:51.054456 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 11:06:51.057814 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 11:06:51.061376 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 11:06:51.061877
4439 11:06:51.067852 CA PerBit enable=1, Macro0, CA PI delay=33
4440 11:06:51.068460
4441 11:06:51.068994 [CBTSetCACLKResult] CA Dly = 33
4442 11:06:51.071307 CS Dly: 4 (0~35)
4443 11:06:51.071803 ==
4444 11:06:51.074710 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 11:06:51.077921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 11:06:51.078356 ==
4447 11:06:51.084714 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4448 11:06:51.091753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4449 11:06:51.094562 [CA 0] Center 36 (6~66) winsize 61
4450 11:06:51.098400 [CA 1] Center 36 (6~66) winsize 61
4451 11:06:51.101263 [CA 2] Center 34 (4~65) winsize 62
4452 11:06:51.104885 [CA 3] Center 34 (4~65) winsize 62
4453 11:06:51.108433 [CA 4] Center 34 (4~65) winsize 62
4454 11:06:51.111846 [CA 5] Center 34 (4~64) winsize 61
4455 11:06:51.112348
4456 11:06:51.114650 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4457 11:06:51.115088
4458 11:06:51.117792 [CATrainingPosCal] consider 2 rank data
4459 11:06:51.122041 u2DelayCellTimex100 = 270/100 ps
4460 11:06:51.124502 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4461 11:06:51.128344 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4462 11:06:51.131488 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
4463 11:06:51.134539 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4464 11:06:51.137764 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4465 11:06:51.141692 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4466 11:06:51.142223
4467 11:06:51.148156 CA PerBit enable=1, Macro0, CA PI delay=34
4468 11:06:51.148668
4469 11:06:51.149007 [CBTSetCACLKResult] CA Dly = 34
4470 11:06:51.151622 CS Dly: 4 (0~36)
4471 11:06:51.152050
4472 11:06:51.154677 ----->DramcWriteLeveling(PI) begin...
4473 11:06:51.155297 ==
4474 11:06:51.158160 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 11:06:51.161316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 11:06:51.161753 ==
4477 11:06:51.164811 Write leveling (Byte 0): 30 => 30
4478 11:06:51.167909 Write leveling (Byte 1): 30 => 30
4479 11:06:51.171272 DramcWriteLeveling(PI) end<-----
4480 11:06:51.171789
4481 11:06:51.172125 ==
4482 11:06:51.174550 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 11:06:51.177930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 11:06:51.181514 ==
4485 11:06:51.182041 [Gating] SW mode calibration
4486 11:06:51.191189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4487 11:06:51.194425 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4488 11:06:51.198051 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 11:06:51.204584 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4490 11:06:51.207704 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4491 11:06:51.211085 0 9 12 | B1->B0 | 2a2a 2c2c | 0 1 | (0 0) (1 0)
4492 11:06:51.217823 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 11:06:51.221262 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 11:06:51.224041 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 11:06:51.230985 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 11:06:51.234316 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 11:06:51.237277 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 11:06:51.244231 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4499 11:06:51.247550 0 10 12 | B1->B0 | 3a3a 4141 | 0 0 | (1 1) (0 0)
4500 11:06:51.250645 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 11:06:51.257810 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 11:06:51.260811 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 11:06:51.264072 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:06:51.270660 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 11:06:51.274295 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 11:06:51.277436 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4507 11:06:51.284092 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:06:51.287421 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:06:51.290528 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:06:51.297463 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:06:51.300772 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:06:51.304213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:06:51.307330 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:06:51.314247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:06:51.317272 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:06:51.320752 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:06:51.327257 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:06:51.330665 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:06:51.334248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:06:51.340658 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:06:51.344454 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:06:51.347334 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:06:51.354057 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 11:06:51.357566 Total UI for P1: 0, mck2ui 16
4525 11:06:51.360367 best dqsien dly found for B0: ( 0, 13, 10)
4526 11:06:51.360799 Total UI for P1: 0, mck2ui 16
4527 11:06:51.367154 best dqsien dly found for B1: ( 0, 13, 10)
4528 11:06:51.370410 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4529 11:06:51.373730 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4530 11:06:51.374213
4531 11:06:51.377252 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4532 11:06:51.380619 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4533 11:06:51.383493 [Gating] SW calibration Done
4534 11:06:51.383922 ==
4535 11:06:51.387104 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 11:06:51.390471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 11:06:51.390991 ==
4538 11:06:51.394109 RX Vref Scan: 0
4539 11:06:51.394612
4540 11:06:51.394946 RX Vref 0 -> 0, step: 1
4541 11:06:51.395251
4542 11:06:51.396938 RX Delay -230 -> 252, step: 16
4543 11:06:51.404133 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4544 11:06:51.407088 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4545 11:06:51.410382 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4546 11:06:51.414051 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4547 11:06:51.417365 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4548 11:06:51.423910 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4549 11:06:51.427266 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4550 11:06:51.430664 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4551 11:06:51.434022 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4552 11:06:51.440507 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4553 11:06:51.443798 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4554 11:06:51.446958 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4555 11:06:51.450469 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4556 11:06:51.453892 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4557 11:06:51.460491 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4558 11:06:51.463578 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4559 11:06:51.464083 ==
4560 11:06:51.466955 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 11:06:51.470316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 11:06:51.470821 ==
4563 11:06:51.473830 DQS Delay:
4564 11:06:51.474345 DQS0 = 0, DQS1 = 0
4565 11:06:51.474684 DQM Delay:
4566 11:06:51.477270 DQM0 = 49, DQM1 = 39
4567 11:06:51.477775 DQ Delay:
4568 11:06:51.480251 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4569 11:06:51.483611 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4570 11:06:51.487319 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4571 11:06:51.490410 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4572 11:06:51.491061
4573 11:06:51.491531
4574 11:06:51.491859 ==
4575 11:06:51.493727 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 11:06:51.500595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 11:06:51.501099 ==
4578 11:06:51.501478
4579 11:06:51.501794
4580 11:06:51.502094 TX Vref Scan disable
4581 11:06:51.504212 == TX Byte 0 ==
4582 11:06:51.507346 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4583 11:06:51.514105 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4584 11:06:51.514619 == TX Byte 1 ==
4585 11:06:51.517422 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4586 11:06:51.523846 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4587 11:06:51.524341 ==
4588 11:06:51.527159 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 11:06:51.530791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 11:06:51.531299 ==
4591 11:06:51.531633
4592 11:06:51.531936
4593 11:06:51.534209 TX Vref Scan disable
4594 11:06:51.534641 == TX Byte 0 ==
4595 11:06:51.540669 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4596 11:06:51.544312 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4597 11:06:51.547038 == TX Byte 1 ==
4598 11:06:51.550376 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4599 11:06:51.553643 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4600 11:06:51.554149
4601 11:06:51.554485 [DATLAT]
4602 11:06:51.557402 Freq=600, CH1 RK0
4603 11:06:51.557908
4604 11:06:51.558240 DATLAT Default: 0x9
4605 11:06:51.560649 0, 0xFFFF, sum = 0
4606 11:06:51.561182 1, 0xFFFF, sum = 0
4607 11:06:51.563984 2, 0xFFFF, sum = 0
4608 11:06:51.567167 3, 0xFFFF, sum = 0
4609 11:06:51.567604 4, 0xFFFF, sum = 0
4610 11:06:51.570532 5, 0xFFFF, sum = 0
4611 11:06:51.571064 6, 0xFFFF, sum = 0
4612 11:06:51.573917 7, 0xFFFF, sum = 0
4613 11:06:51.574444 8, 0x0, sum = 1
4614 11:06:51.574792 9, 0x0, sum = 2
4615 11:06:51.576996 10, 0x0, sum = 3
4616 11:06:51.577572 11, 0x0, sum = 4
4617 11:06:51.580165 best_step = 9
4618 11:06:51.580594
4619 11:06:51.580931 ==
4620 11:06:51.583589 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 11:06:51.587153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 11:06:51.587672 ==
4623 11:06:51.590061 RX Vref Scan: 1
4624 11:06:51.590493
4625 11:06:51.590827 RX Vref 0 -> 0, step: 1
4626 11:06:51.591219
4627 11:06:51.593867 RX Delay -179 -> 252, step: 8
4628 11:06:51.594373
4629 11:06:51.596802 Set Vref, RX VrefLevel [Byte0]: 53
4630 11:06:51.599894 [Byte1]: 52
4631 11:06:51.604337
4632 11:06:51.604843 Final RX Vref Byte 0 = 53 to rank0
4633 11:06:51.607883 Final RX Vref Byte 1 = 52 to rank0
4634 11:06:51.611024 Final RX Vref Byte 0 = 53 to rank1
4635 11:06:51.614463 Final RX Vref Byte 1 = 52 to rank1==
4636 11:06:51.617767 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 11:06:51.624771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 11:06:51.625318 ==
4639 11:06:51.625657 DQS Delay:
4640 11:06:51.626077 DQS0 = 0, DQS1 = 0
4641 11:06:51.627805 DQM Delay:
4642 11:06:51.628276 DQM0 = 47, DQM1 = 40
4643 11:06:51.631284 DQ Delay:
4644 11:06:51.634628 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4645 11:06:51.635148 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4646 11:06:51.637994 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4647 11:06:51.641264 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4648 11:06:51.644531
4649 11:06:51.644958
4650 11:06:51.651325 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4651 11:06:51.654788 CH1 RK0: MR19=808, MR18=4C73
4652 11:06:51.661061 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4653 11:06:51.661596
4654 11:06:51.664357 ----->DramcWriteLeveling(PI) begin...
4655 11:06:51.664795 ==
4656 11:06:51.667671 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 11:06:51.670963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 11:06:51.671395 ==
4659 11:06:51.674496 Write leveling (Byte 0): 29 => 29
4660 11:06:51.678082 Write leveling (Byte 1): 29 => 29
4661 11:06:51.680848 DramcWriteLeveling(PI) end<-----
4662 11:06:51.681321
4663 11:06:51.681659 ==
4664 11:06:51.684334 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 11:06:51.688203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 11:06:51.688724 ==
4667 11:06:51.691287 [Gating] SW mode calibration
4668 11:06:51.697736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4669 11:06:51.704832 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4670 11:06:51.708045 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 11:06:51.711302 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 11:06:51.717737 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 11:06:51.720783 0 9 12 | B1->B0 | 2525 2f2f | 0 1 | (1 1) (1 0)
4674 11:06:51.724294 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 11:06:51.730886 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 11:06:51.734464 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 11:06:51.737869 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 11:06:51.744473 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 11:06:51.748250 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 11:06:51.751235 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 11:06:51.757793 0 10 12 | B1->B0 | 3a3a 3030 | 0 0 | (0 0) (0 0)
4682 11:06:51.761253 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:06:51.764438 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 11:06:51.771219 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 11:06:51.774460 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 11:06:51.778120 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 11:06:51.781258 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 11:06:51.787989 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 11:06:51.791464 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4690 11:06:51.794412 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:06:51.801248 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:06:51.804684 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:06:51.807949 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:06:51.814455 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:06:51.817682 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:06:51.820905 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:06:51.827588 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:06:51.831010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:06:51.834219 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:06:51.841331 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:06:51.844185 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:06:51.847858 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:06:51.854341 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:06:51.857691 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:06:51.861269 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4706 11:06:51.867945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 11:06:51.868450 Total UI for P1: 0, mck2ui 16
4708 11:06:51.870873 best dqsien dly found for B0: ( 0, 13, 12)
4709 11:06:51.874096 Total UI for P1: 0, mck2ui 16
4710 11:06:51.877868 best dqsien dly found for B1: ( 0, 13, 12)
4711 11:06:51.881263 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4712 11:06:51.887909 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4713 11:06:51.888411
4714 11:06:51.891316 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4715 11:06:51.894383 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4716 11:06:51.897810 [Gating] SW calibration Done
4717 11:06:51.898241 ==
4718 11:06:51.901303 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 11:06:51.904095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 11:06:51.904490 ==
4721 11:06:51.908097 RX Vref Scan: 0
4722 11:06:51.908604
4723 11:06:51.908938 RX Vref 0 -> 0, step: 1
4724 11:06:51.909289
4725 11:06:51.911324 RX Delay -230 -> 252, step: 16
4726 11:06:51.914368 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4727 11:06:51.921252 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4728 11:06:51.924449 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4729 11:06:51.927661 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4730 11:06:51.930744 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4731 11:06:51.934285 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4732 11:06:51.940606 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4733 11:06:51.944300 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4734 11:06:51.947269 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4735 11:06:51.950571 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4736 11:06:51.957708 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4737 11:06:51.960737 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4738 11:06:51.964156 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4739 11:06:51.967400 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4740 11:06:51.974463 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4741 11:06:51.977254 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4742 11:06:51.977685 ==
4743 11:06:51.980787 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 11:06:51.984033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 11:06:51.984465 ==
4746 11:06:51.984802 DQS Delay:
4747 11:06:51.987939 DQS0 = 0, DQS1 = 0
4748 11:06:51.988605 DQM Delay:
4749 11:06:51.990901 DQM0 = 52, DQM1 = 47
4750 11:06:51.991329 DQ Delay:
4751 11:06:51.993917 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4752 11:06:51.997584 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4753 11:06:52.001177 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4754 11:06:52.004224 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4755 11:06:52.004728
4756 11:06:52.005059
4757 11:06:52.005402 ==
4758 11:06:52.007235 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 11:06:52.011108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 11:06:52.014087 ==
4761 11:06:52.014596
4762 11:06:52.014931
4763 11:06:52.015236 TX Vref Scan disable
4764 11:06:52.017686 == TX Byte 0 ==
4765 11:06:52.020373 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4766 11:06:52.024048 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4767 11:06:52.027351 == TX Byte 1 ==
4768 11:06:52.030836 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4769 11:06:52.034400 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4770 11:06:52.037559 ==
4771 11:06:52.038063 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 11:06:52.044261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 11:06:52.044787 ==
4774 11:06:52.045226
4775 11:06:52.045548
4776 11:06:52.046919 TX Vref Scan disable
4777 11:06:52.047348 == TX Byte 0 ==
4778 11:06:52.053763 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4779 11:06:52.057200 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4780 11:06:52.057637 == TX Byte 1 ==
4781 11:06:52.063624 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4782 11:06:52.067213 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4783 11:06:52.067657
4784 11:06:52.068052 [DATLAT]
4785 11:06:52.070304 Freq=600, CH1 RK1
4786 11:06:52.070818
4787 11:06:52.071154 DATLAT Default: 0x9
4788 11:06:52.073656 0, 0xFFFF, sum = 0
4789 11:06:52.074097 1, 0xFFFF, sum = 0
4790 11:06:52.076870 2, 0xFFFF, sum = 0
4791 11:06:52.077383 3, 0xFFFF, sum = 0
4792 11:06:52.080447 4, 0xFFFF, sum = 0
4793 11:06:52.080885 5, 0xFFFF, sum = 0
4794 11:06:52.083615 6, 0xFFFF, sum = 0
4795 11:06:52.086741 7, 0xFFFF, sum = 0
4796 11:06:52.087317 8, 0x0, sum = 1
4797 11:06:52.087826 9, 0x0, sum = 2
4798 11:06:52.090455 10, 0x0, sum = 3
4799 11:06:52.091097 11, 0x0, sum = 4
4800 11:06:52.093610 best_step = 9
4801 11:06:52.094034
4802 11:06:52.094361 ==
4803 11:06:52.096977 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 11:06:52.099793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 11:06:52.099867 ==
4806 11:06:52.103675 RX Vref Scan: 0
4807 11:06:52.103812
4808 11:06:52.103876 RX Vref 0 -> 0, step: 1
4809 11:06:52.103933
4810 11:06:52.106995 RX Delay -163 -> 252, step: 8
4811 11:06:52.114099 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4812 11:06:52.117058 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4813 11:06:52.120759 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4814 11:06:52.123785 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4815 11:06:52.127136 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4816 11:06:52.133786 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4817 11:06:52.137020 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4818 11:06:52.140777 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4819 11:06:52.143810 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4820 11:06:52.147412 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4821 11:06:52.153469 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4822 11:06:52.157186 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4823 11:06:52.160157 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4824 11:06:52.163885 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4825 11:06:52.170581 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4826 11:06:52.173760 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4827 11:06:52.174110 ==
4828 11:06:52.177531 Dram Type= 6, Freq= 0, CH_1, rank 1
4829 11:06:52.180931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4830 11:06:52.181504 ==
4831 11:06:52.183651 DQS Delay:
4832 11:06:52.184072 DQS0 = 0, DQS1 = 0
4833 11:06:52.184397 DQM Delay:
4834 11:06:52.187060 DQM0 = 48, DQM1 = 43
4835 11:06:52.187484 DQ Delay:
4836 11:06:52.190560 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4837 11:06:52.193823 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =44
4838 11:06:52.196925 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4839 11:06:52.200992 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4840 11:06:52.201553
4841 11:06:52.201885
4842 11:06:52.210642 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4843 11:06:52.211190 CH1 RK1: MR19=808, MR18=5A22
4844 11:06:52.217225 CH1_RK1: MR19=0x808, MR18=0x5A22, DQSOSC=392, MR23=63, INC=170, DEC=113
4845 11:06:52.220800 [RxdqsGatingPostProcess] freq 600
4846 11:06:52.227169 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4847 11:06:52.230226 Pre-setting of DQS Precalculation
4848 11:06:52.234105 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4849 11:06:52.240381 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4850 11:06:52.250592 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4851 11:06:52.251108
4852 11:06:52.251439
4853 11:06:52.251748 [Calibration Summary] 1200 Mbps
4854 11:06:52.253921 CH 0, Rank 0
4855 11:06:52.254431 SW Impedance : PASS
4856 11:06:52.257328 DUTY Scan : NO K
4857 11:06:52.260558 ZQ Calibration : PASS
4858 11:06:52.261065 Jitter Meter : NO K
4859 11:06:52.264028 CBT Training : PASS
4860 11:06:52.266993 Write leveling : PASS
4861 11:06:52.267422 RX DQS gating : PASS
4862 11:06:52.270071 RX DQ/DQS(RDDQC) : PASS
4863 11:06:52.273670 TX DQ/DQS : PASS
4864 11:06:52.274252 RX DATLAT : PASS
4865 11:06:52.277050 RX DQ/DQS(Engine): PASS
4866 11:06:52.280568 TX OE : NO K
4867 11:06:52.281082 All Pass.
4868 11:06:52.281459
4869 11:06:52.281767 CH 0, Rank 1
4870 11:06:52.284105 SW Impedance : PASS
4871 11:06:52.287138 DUTY Scan : NO K
4872 11:06:52.287673 ZQ Calibration : PASS
4873 11:06:52.290449 Jitter Meter : NO K
4874 11:06:52.293732 CBT Training : PASS
4875 11:06:52.294366 Write leveling : PASS
4876 11:06:52.296884 RX DQS gating : PASS
4877 11:06:52.297455 RX DQ/DQS(RDDQC) : PASS
4878 11:06:52.300488 TX DQ/DQS : PASS
4879 11:06:52.303738 RX DATLAT : PASS
4880 11:06:52.304257 RX DQ/DQS(Engine): PASS
4881 11:06:52.307056 TX OE : NO K
4882 11:06:52.307572 All Pass.
4883 11:06:52.307909
4884 11:06:52.310263 CH 1, Rank 0
4885 11:06:52.310777 SW Impedance : PASS
4886 11:06:52.313610 DUTY Scan : NO K
4887 11:06:52.316817 ZQ Calibration : PASS
4888 11:06:52.317393 Jitter Meter : NO K
4889 11:06:52.320394 CBT Training : PASS
4890 11:06:52.323703 Write leveling : PASS
4891 11:06:52.324351 RX DQS gating : PASS
4892 11:06:52.327050 RX DQ/DQS(RDDQC) : PASS
4893 11:06:52.330325 TX DQ/DQS : PASS
4894 11:06:52.330756 RX DATLAT : PASS
4895 11:06:52.333559 RX DQ/DQS(Engine): PASS
4896 11:06:52.337323 TX OE : NO K
4897 11:06:52.337832 All Pass.
4898 11:06:52.338171
4899 11:06:52.338480 CH 1, Rank 1
4900 11:06:52.340665 SW Impedance : PASS
4901 11:06:52.343413 DUTY Scan : NO K
4902 11:06:52.343844 ZQ Calibration : PASS
4903 11:06:52.346998 Jitter Meter : NO K
4904 11:06:52.347507 CBT Training : PASS
4905 11:06:52.350405 Write leveling : PASS
4906 11:06:52.353578 RX DQS gating : PASS
4907 11:06:52.354085 RX DQ/DQS(RDDQC) : PASS
4908 11:06:52.356773 TX DQ/DQS : PASS
4909 11:06:52.360138 RX DATLAT : PASS
4910 11:06:52.360656 RX DQ/DQS(Engine): PASS
4911 11:06:52.363380 TX OE : NO K
4912 11:06:52.363893 All Pass.
4913 11:06:52.364278
4914 11:06:52.366758 DramC Write-DBI off
4915 11:06:52.370034 PER_BANK_REFRESH: Hybrid Mode
4916 11:06:52.370637 TX_TRACKING: ON
4917 11:06:52.380567 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4918 11:06:52.383901 [FAST_K] Save calibration result to emmc
4919 11:06:52.386875 dramc_set_vcore_voltage set vcore to 662500
4920 11:06:52.390189 Read voltage for 933, 3
4921 11:06:52.390717 Vio18 = 0
4922 11:06:52.391059 Vcore = 662500
4923 11:06:52.393755 Vdram = 0
4924 11:06:52.394334 Vddq = 0
4925 11:06:52.394677 Vmddr = 0
4926 11:06:52.400200 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4927 11:06:52.403417 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4928 11:06:52.407142 MEM_TYPE=3, freq_sel=17
4929 11:06:52.410418 sv_algorithm_assistance_LP4_1600
4930 11:06:52.413521 ============ PULL DRAM RESETB DOWN ============
4931 11:06:52.416869 ========== PULL DRAM RESETB DOWN end =========
4932 11:06:52.424048 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4933 11:06:52.426882 ===================================
4934 11:06:52.427398 LPDDR4 DRAM CONFIGURATION
4935 11:06:52.430191 ===================================
4936 11:06:52.433297 EX_ROW_EN[0] = 0x0
4937 11:06:52.437244 EX_ROW_EN[1] = 0x0
4938 11:06:52.437765 LP4Y_EN = 0x0
4939 11:06:52.440426 WORK_FSP = 0x0
4940 11:06:52.440935 WL = 0x3
4941 11:06:52.443553 RL = 0x3
4942 11:06:52.444064 BL = 0x2
4943 11:06:52.447259 RPST = 0x0
4944 11:06:52.447784 RD_PRE = 0x0
4945 11:06:52.450061 WR_PRE = 0x1
4946 11:06:52.450486 WR_PST = 0x0
4947 11:06:52.453753 DBI_WR = 0x0
4948 11:06:52.454260 DBI_RD = 0x0
4949 11:06:52.456769 OTF = 0x1
4950 11:06:52.460296 ===================================
4951 11:06:52.463807 ===================================
4952 11:06:52.464316 ANA top config
4953 11:06:52.467170 ===================================
4954 11:06:52.470727 DLL_ASYNC_EN = 0
4955 11:06:52.473817 ALL_SLAVE_EN = 1
4956 11:06:52.474316 NEW_RANK_MODE = 1
4957 11:06:52.476798 DLL_IDLE_MODE = 1
4958 11:06:52.480275 LP45_APHY_COMB_EN = 1
4959 11:06:52.483544 TX_ODT_DIS = 1
4960 11:06:52.487439 NEW_8X_MODE = 1
4961 11:06:52.490044 ===================================
4962 11:06:52.493824 ===================================
4963 11:06:52.494333 data_rate = 1866
4964 11:06:52.496985 CKR = 1
4965 11:06:52.500455 DQ_P2S_RATIO = 8
4966 11:06:52.503748 ===================================
4967 11:06:52.507144 CA_P2S_RATIO = 8
4968 11:06:52.510276 DQ_CA_OPEN = 0
4969 11:06:52.513866 DQ_SEMI_OPEN = 0
4970 11:06:52.514371 CA_SEMI_OPEN = 0
4971 11:06:52.517178 CA_FULL_RATE = 0
4972 11:06:52.520468 DQ_CKDIV4_EN = 1
4973 11:06:52.523554 CA_CKDIV4_EN = 1
4974 11:06:52.527044 CA_PREDIV_EN = 0
4975 11:06:52.529877 PH8_DLY = 0
4976 11:06:52.530328 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4977 11:06:52.533436 DQ_AAMCK_DIV = 4
4978 11:06:52.537019 CA_AAMCK_DIV = 4
4979 11:06:52.540069 CA_ADMCK_DIV = 4
4980 11:06:52.543684 DQ_TRACK_CA_EN = 0
4981 11:06:52.547195 CA_PICK = 933
4982 11:06:52.547704 CA_MCKIO = 933
4983 11:06:52.550107 MCKIO_SEMI = 0
4984 11:06:52.553320 PLL_FREQ = 3732
4985 11:06:52.557033 DQ_UI_PI_RATIO = 32
4986 11:06:52.560221 CA_UI_PI_RATIO = 0
4987 11:06:52.563602 ===================================
4988 11:06:52.566757 ===================================
4989 11:06:52.569825 memory_type:LPDDR4
4990 11:06:52.570255 GP_NUM : 10
4991 11:06:52.573474 SRAM_EN : 1
4992 11:06:52.573959 MD32_EN : 0
4993 11:06:52.576640 ===================================
4994 11:06:52.580228 [ANA_INIT] >>>>>>>>>>>>>>
4995 11:06:52.583643 <<<<<< [CONFIGURE PHASE]: ANA_TX
4996 11:06:52.586622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4997 11:06:52.590136 ===================================
4998 11:06:52.593532 data_rate = 1866,PCW = 0X8f00
4999 11:06:52.597372 ===================================
5000 11:06:52.600567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5001 11:06:52.603748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 11:06:52.610313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5003 11:06:52.613313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5004 11:06:52.620018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5005 11:06:52.623744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5006 11:06:52.624261 [ANA_INIT] flow start
5007 11:06:52.627112 [ANA_INIT] PLL >>>>>>>>
5008 11:06:52.629808 [ANA_INIT] PLL <<<<<<<<
5009 11:06:52.630338 [ANA_INIT] MIDPI >>>>>>>>
5010 11:06:52.633189 [ANA_INIT] MIDPI <<<<<<<<
5011 11:06:52.636647 [ANA_INIT] DLL >>>>>>>>
5012 11:06:52.637074 [ANA_INIT] flow end
5013 11:06:52.639992 ============ LP4 DIFF to SE enter ============
5014 11:06:52.646801 ============ LP4 DIFF to SE exit ============
5015 11:06:52.647318 [ANA_INIT] <<<<<<<<<<<<<
5016 11:06:52.650127 [Flow] Enable top DCM control >>>>>
5017 11:06:52.653719 [Flow] Enable top DCM control <<<<<
5018 11:06:52.656533 Enable DLL master slave shuffle
5019 11:06:52.663315 ==============================================================
5020 11:06:52.663862 Gating Mode config
5021 11:06:52.670244 ==============================================================
5022 11:06:52.673398 Config description:
5023 11:06:52.683474 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5024 11:06:52.690100 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5025 11:06:52.693409 SELPH_MODE 0: By rank 1: By Phase
5026 11:06:52.700021 ==============================================================
5027 11:06:52.703582 GAT_TRACK_EN = 1
5028 11:06:52.704089 RX_GATING_MODE = 2
5029 11:06:52.706467 RX_GATING_TRACK_MODE = 2
5030 11:06:52.710080 SELPH_MODE = 1
5031 11:06:52.713754 PICG_EARLY_EN = 1
5032 11:06:52.716818 VALID_LAT_VALUE = 1
5033 11:06:52.723301 ==============================================================
5034 11:06:52.726381 Enter into Gating configuration >>>>
5035 11:06:52.729942 Exit from Gating configuration <<<<
5036 11:06:52.733341 Enter into DVFS_PRE_config >>>>>
5037 11:06:52.743669 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5038 11:06:52.746574 Exit from DVFS_PRE_config <<<<<
5039 11:06:52.750013 Enter into PICG configuration >>>>
5040 11:06:52.753766 Exit from PICG configuration <<<<
5041 11:06:52.756624 [RX_INPUT] configuration >>>>>
5042 11:06:52.760199 [RX_INPUT] configuration <<<<<
5043 11:06:52.763106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5044 11:06:52.769774 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5045 11:06:52.776603 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 11:06:52.779989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 11:06:52.786342 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 11:06:52.792809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 11:06:52.796623 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5050 11:06:52.803366 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5051 11:06:52.806862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5052 11:06:52.809941 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5053 11:06:52.813553 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5054 11:06:52.819844 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 11:06:52.823015 ===================================
5056 11:06:52.823514 LPDDR4 DRAM CONFIGURATION
5057 11:06:52.826391 ===================================
5058 11:06:52.829956 EX_ROW_EN[0] = 0x0
5059 11:06:52.832895 EX_ROW_EN[1] = 0x0
5060 11:06:52.833373 LP4Y_EN = 0x0
5061 11:06:52.836606 WORK_FSP = 0x0
5062 11:06:52.837166 WL = 0x3
5063 11:06:52.840149 RL = 0x3
5064 11:06:52.840656 BL = 0x2
5065 11:06:52.843240 RPST = 0x0
5066 11:06:52.843745 RD_PRE = 0x0
5067 11:06:52.846225 WR_PRE = 0x1
5068 11:06:52.846654 WR_PST = 0x0
5069 11:06:52.850038 DBI_WR = 0x0
5070 11:06:52.850546 DBI_RD = 0x0
5071 11:06:52.853055 OTF = 0x1
5072 11:06:52.856524 ===================================
5073 11:06:52.860006 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5074 11:06:52.863246 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5075 11:06:52.870034 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5076 11:06:52.872776 ===================================
5077 11:06:52.873368 LPDDR4 DRAM CONFIGURATION
5078 11:06:52.876203 ===================================
5079 11:06:52.879745 EX_ROW_EN[0] = 0x10
5080 11:06:52.880255 EX_ROW_EN[1] = 0x0
5081 11:06:52.882934 LP4Y_EN = 0x0
5082 11:06:52.883491 WORK_FSP = 0x0
5083 11:06:52.886092 WL = 0x3
5084 11:06:52.886518 RL = 0x3
5085 11:06:52.889331 BL = 0x2
5086 11:06:52.892983 RPST = 0x0
5087 11:06:52.893637 RD_PRE = 0x0
5088 11:06:52.896412 WR_PRE = 0x1
5089 11:06:52.896909 WR_PST = 0x0
5090 11:06:52.899373 DBI_WR = 0x0
5091 11:06:52.899796 DBI_RD = 0x0
5092 11:06:52.903093 OTF = 0x1
5093 11:06:52.906081 ===================================
5094 11:06:52.910115 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5095 11:06:52.914957 nWR fixed to 30
5096 11:06:52.918336 [ModeRegInit_LP4] CH0 RK0
5097 11:06:52.918840 [ModeRegInit_LP4] CH0 RK1
5098 11:06:52.921666 [ModeRegInit_LP4] CH1 RK0
5099 11:06:52.925159 [ModeRegInit_LP4] CH1 RK1
5100 11:06:52.925695 match AC timing 9
5101 11:06:52.931545 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5102 11:06:52.934864 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5103 11:06:52.938082 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5104 11:06:52.944744 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5105 11:06:52.948251 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5106 11:06:52.948752 ==
5107 11:06:52.951838 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 11:06:52.954812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 11:06:52.955315 ==
5110 11:06:52.961565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 11:06:52.968508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5112 11:06:52.971230 [CA 0] Center 37 (7~68) winsize 62
5113 11:06:52.974931 [CA 1] Center 38 (8~69) winsize 62
5114 11:06:52.978283 [CA 2] Center 35 (5~66) winsize 62
5115 11:06:52.981449 [CA 3] Center 34 (4~65) winsize 62
5116 11:06:52.984818 [CA 4] Center 34 (4~65) winsize 62
5117 11:06:52.988346 [CA 5] Center 33 (3~64) winsize 62
5118 11:06:52.988851
5119 11:06:52.991814 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5120 11:06:52.992325
5121 11:06:52.994705 [CATrainingPosCal] consider 1 rank data
5122 11:06:52.998102 u2DelayCellTimex100 = 270/100 ps
5123 11:06:53.001366 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5124 11:06:53.004824 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5125 11:06:53.008260 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5126 11:06:53.011520 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 11:06:53.014790 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5128 11:06:53.017953 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5129 11:06:53.018602
5130 11:06:53.025084 CA PerBit enable=1, Macro0, CA PI delay=33
5131 11:06:53.025638
5132 11:06:53.028360 [CBTSetCACLKResult] CA Dly = 33
5133 11:06:53.028865 CS Dly: 7 (0~38)
5134 11:06:53.029327 ==
5135 11:06:53.031229 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 11:06:53.034666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 11:06:53.035095 ==
5138 11:06:53.041578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 11:06:53.048165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5140 11:06:53.051646 [CA 0] Center 38 (8~69) winsize 62
5141 11:06:53.054821 [CA 1] Center 38 (8~69) winsize 62
5142 11:06:53.057987 [CA 2] Center 35 (5~66) winsize 62
5143 11:06:53.061686 [CA 3] Center 35 (5~66) winsize 62
5144 11:06:53.064523 [CA 4] Center 34 (4~65) winsize 62
5145 11:06:53.068082 [CA 5] Center 34 (4~64) winsize 61
5146 11:06:53.068590
5147 11:06:53.071043 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5148 11:06:53.071468
5149 11:06:53.074825 [CATrainingPosCal] consider 2 rank data
5150 11:06:53.078075 u2DelayCellTimex100 = 270/100 ps
5151 11:06:53.081372 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5152 11:06:53.084581 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5153 11:06:53.088203 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5154 11:06:53.090990 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5155 11:06:53.094850 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5156 11:06:53.097867 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5157 11:06:53.101065
5158 11:06:53.104996 CA PerBit enable=1, Macro0, CA PI delay=34
5159 11:06:53.105807
5160 11:06:53.107739 [CBTSetCACLKResult] CA Dly = 34
5161 11:06:53.108167 CS Dly: 7 (0~39)
5162 11:06:53.108880
5163 11:06:53.111117 ----->DramcWriteLeveling(PI) begin...
5164 11:06:53.111568 ==
5165 11:06:53.114562 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 11:06:53.117910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 11:06:53.118871 ==
5168 11:06:53.121381 Write leveling (Byte 0): 35 => 35
5169 11:06:53.124741 Write leveling (Byte 1): 31 => 31
5170 11:06:53.127857 DramcWriteLeveling(PI) end<-----
5171 11:06:53.128284
5172 11:06:53.128610 ==
5173 11:06:53.131346 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 11:06:53.134697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 11:06:53.137778 ==
5176 11:06:53.138340 [Gating] SW mode calibration
5177 11:06:53.148051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5178 11:06:53.151154 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5179 11:06:53.154475 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5180 11:06:53.161172 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 11:06:53.164312 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 11:06:53.167676 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 11:06:53.174478 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 11:06:53.177982 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 11:06:53.181115 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
5186 11:06:53.187691 0 14 28 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
5187 11:06:53.191129 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5188 11:06:53.194209 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:06:53.200994 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 11:06:53.204307 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 11:06:53.207541 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 11:06:53.214186 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 11:06:53.217414 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
5194 11:06:53.220798 0 15 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
5195 11:06:53.227734 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5196 11:06:53.230898 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:06:53.233908 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:06:53.240616 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 11:06:53.244175 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 11:06:53.247344 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 11:06:53.254482 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 11:06:53.257909 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5203 11:06:53.260938 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5204 11:06:53.267697 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:06:53.270689 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:06:53.274187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:06:53.277303 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:06:53.284286 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:06:53.287730 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:06:53.291262 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:06:53.297346 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:06:53.300761 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:06:53.304764 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:06:53.311028 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:06:53.313905 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:06:53.317831 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:06:53.324415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 11:06:53.327471 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5219 11:06:53.330650 Total UI for P1: 0, mck2ui 16
5220 11:06:53.333977 best dqsien dly found for B0: ( 1, 2, 24)
5221 11:06:53.337319 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 11:06:53.340512 Total UI for P1: 0, mck2ui 16
5223 11:06:53.344083 best dqsien dly found for B1: ( 1, 2, 28)
5224 11:06:53.347475 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5225 11:06:53.350970 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5226 11:06:53.351475
5227 11:06:53.353798 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5228 11:06:53.360631 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5229 11:06:53.361337 [Gating] SW calibration Done
5230 11:06:53.361764 ==
5231 11:06:53.364256 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 11:06:53.370757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 11:06:53.371263 ==
5234 11:06:53.371613 RX Vref Scan: 0
5235 11:06:53.372002
5236 11:06:53.374512 RX Vref 0 -> 0, step: 1
5237 11:06:53.375016
5238 11:06:53.377631 RX Delay -80 -> 252, step: 8
5239 11:06:53.381051 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5240 11:06:53.384233 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5241 11:06:53.387375 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5242 11:06:53.394187 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5243 11:06:53.397874 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5244 11:06:53.401032 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5245 11:06:53.404007 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5246 11:06:53.407434 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5247 11:06:53.410702 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5248 11:06:53.417772 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5249 11:06:53.421075 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5250 11:06:53.424314 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5251 11:06:53.427846 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5252 11:06:53.430654 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5253 11:06:53.433948 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5254 11:06:53.440813 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5255 11:06:53.441358 ==
5256 11:06:53.444035 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 11:06:53.447811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 11:06:53.448314 ==
5259 11:06:53.448646 DQS Delay:
5260 11:06:53.450873 DQS0 = 0, DQS1 = 0
5261 11:06:53.451378 DQM Delay:
5262 11:06:53.453964 DQM0 = 105, DQM1 = 90
5263 11:06:53.454478 DQ Delay:
5264 11:06:53.457316 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5265 11:06:53.461259 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5266 11:06:53.463899 DQ8 =87, DQ9 =75, DQ10 =91, DQ11 =87
5267 11:06:53.467762 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5268 11:06:53.468265
5269 11:06:53.468595
5270 11:06:53.468899 ==
5271 11:06:53.470488 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 11:06:53.473893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 11:06:53.477794 ==
5274 11:06:53.478300
5275 11:06:53.478635
5276 11:06:53.478945 TX Vref Scan disable
5277 11:06:53.480994 == TX Byte 0 ==
5278 11:06:53.484240 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5279 11:06:53.487409 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5280 11:06:53.490992 == TX Byte 1 ==
5281 11:06:53.494300 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5282 11:06:53.497761 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5283 11:06:53.498268 ==
5284 11:06:53.500591 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 11:06:53.507568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 11:06:53.508132 ==
5287 11:06:53.508643
5288 11:06:53.508993
5289 11:06:53.509342 TX Vref Scan disable
5290 11:06:53.512268 == TX Byte 0 ==
5291 11:06:53.514969 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5292 11:06:53.522112 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5293 11:06:53.522624 == TX Byte 1 ==
5294 11:06:53.524948 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5295 11:06:53.531601 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5296 11:06:53.532106
5297 11:06:53.532462 [DATLAT]
5298 11:06:53.532773 Freq=933, CH0 RK0
5299 11:06:53.533071
5300 11:06:53.534849 DATLAT Default: 0xd
5301 11:06:53.535278 0, 0xFFFF, sum = 0
5302 11:06:53.538272 1, 0xFFFF, sum = 0
5303 11:06:53.538710 2, 0xFFFF, sum = 0
5304 11:06:53.542065 3, 0xFFFF, sum = 0
5305 11:06:53.542576 4, 0xFFFF, sum = 0
5306 11:06:53.545519 5, 0xFFFF, sum = 0
5307 11:06:53.546056 6, 0xFFFF, sum = 0
5308 11:06:53.548585 7, 0xFFFF, sum = 0
5309 11:06:53.551848 8, 0xFFFF, sum = 0
5310 11:06:53.552362 9, 0xFFFF, sum = 0
5311 11:06:53.555513 10, 0x0, sum = 1
5312 11:06:53.556028 11, 0x0, sum = 2
5313 11:06:53.556374 12, 0x0, sum = 3
5314 11:06:53.558478 13, 0x0, sum = 4
5315 11:06:53.558918 best_step = 11
5316 11:06:53.559252
5317 11:06:53.559657 ==
5318 11:06:53.561776 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 11:06:53.568657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 11:06:53.569206 ==
5321 11:06:53.569555 RX Vref Scan: 1
5322 11:06:53.569869
5323 11:06:53.571499 RX Vref 0 -> 0, step: 1
5324 11:06:53.571931
5325 11:06:53.575220 RX Delay -61 -> 252, step: 4
5326 11:06:53.575728
5327 11:06:53.578287 Set Vref, RX VrefLevel [Byte0]: 60
5328 11:06:53.581968 [Byte1]: 54
5329 11:06:53.582476
5330 11:06:53.585097 Final RX Vref Byte 0 = 60 to rank0
5331 11:06:53.588133 Final RX Vref Byte 1 = 54 to rank0
5332 11:06:53.591921 Final RX Vref Byte 0 = 60 to rank1
5333 11:06:53.595035 Final RX Vref Byte 1 = 54 to rank1==
5334 11:06:53.598550 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 11:06:53.601776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 11:06:53.602288 ==
5337 11:06:53.604872 DQS Delay:
5338 11:06:53.605349 DQS0 = 0, DQS1 = 0
5339 11:06:53.608869 DQM Delay:
5340 11:06:53.609415 DQM0 = 107, DQM1 = 93
5341 11:06:53.609749 DQ Delay:
5342 11:06:53.611365 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5343 11:06:53.618186 DQ4 =108, DQ5 =100, DQ6 =116, DQ7 =116
5344 11:06:53.621303 DQ8 =88, DQ9 =80, DQ10 =94, DQ11 =92
5345 11:06:53.624876 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5346 11:06:53.625423
5347 11:06:53.625756
5348 11:06:53.631410 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 408 ps
5349 11:06:53.634506 CH0 RK0: MR19=505, MR18=2A26
5350 11:06:53.641431 CH0_RK0: MR19=0x505, MR18=0x2A26, DQSOSC=408, MR23=63, INC=65, DEC=43
5351 11:06:53.641992
5352 11:06:53.645102 ----->DramcWriteLeveling(PI) begin...
5353 11:06:53.645662 ==
5354 11:06:53.648154 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 11:06:53.651311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 11:06:53.651739 ==
5357 11:06:53.654807 Write leveling (Byte 0): 34 => 34
5358 11:06:53.657968 Write leveling (Byte 1): 30 => 30
5359 11:06:53.661540 DramcWriteLeveling(PI) end<-----
5360 11:06:53.662066
5361 11:06:53.662422 ==
5362 11:06:53.664899 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 11:06:53.668153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 11:06:53.668661 ==
5365 11:06:53.671285 [Gating] SW mode calibration
5366 11:06:53.678064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 11:06:53.684996 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5368 11:06:53.688017 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5369 11:06:53.691658 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:06:53.697989 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:06:53.701238 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 11:06:53.704498 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 11:06:53.711345 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 11:06:53.714606 0 14 24 | B1->B0 | 3333 3131 | 1 0 | (0 0) (0 0)
5375 11:06:53.718022 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
5376 11:06:53.725027 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 11:06:53.728059 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:06:53.731568 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:06:53.738158 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 11:06:53.741779 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 11:06:53.744810 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 11:06:53.751189 0 15 24 | B1->B0 | 2c2c 3131 | 0 0 | (1 1) (0 0)
5383 11:06:53.754815 0 15 28 | B1->B0 | 3939 3e3e | 0 0 | (0 0) (0 0)
5384 11:06:53.758078 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:06:53.764713 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:06:53.767965 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:06:53.771242 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:06:53.778211 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 11:06:53.781854 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 11:06:53.784894 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 11:06:53.787994 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5392 11:06:53.794563 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5393 11:06:53.798071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:06:53.801290 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:06:53.808403 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:06:53.810924 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:06:53.814596 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:06:53.821326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:06:53.824719 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:06:53.828305 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:06:53.834359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:06:53.838099 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:06:53.841279 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:06:53.847915 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:06:53.850957 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:06:53.854406 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5407 11:06:53.861343 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5408 11:06:53.864858 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 11:06:53.868234 Total UI for P1: 0, mck2ui 16
5410 11:06:53.870956 best dqsien dly found for B0: ( 1, 2, 28)
5411 11:06:53.874351 Total UI for P1: 0, mck2ui 16
5412 11:06:53.877846 best dqsien dly found for B1: ( 1, 2, 26)
5413 11:06:53.881093 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5414 11:06:53.884282 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5415 11:06:53.884861
5416 11:06:53.887704 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5417 11:06:53.891309 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5418 11:06:53.894515 [Gating] SW calibration Done
5419 11:06:53.894947 ==
5420 11:06:53.897865 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 11:06:53.901180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 11:06:53.901689 ==
5423 11:06:53.904501 RX Vref Scan: 0
5424 11:06:53.905005
5425 11:06:53.907663 RX Vref 0 -> 0, step: 1
5426 11:06:53.908163
5427 11:06:53.908494 RX Delay -80 -> 252, step: 8
5428 11:06:53.914736 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5429 11:06:53.917933 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5430 11:06:53.921387 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5431 11:06:53.925052 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5432 11:06:53.927966 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5433 11:06:53.931208 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5434 11:06:53.938095 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5435 11:06:53.941795 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5436 11:06:53.945225 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5437 11:06:53.948289 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5438 11:06:53.951825 iDelay=208, Bit 10, Center 87 (0 ~ 175) 176
5439 11:06:53.954922 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5440 11:06:53.961565 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5441 11:06:53.964649 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5442 11:06:53.968246 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5443 11:06:53.971751 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5444 11:06:53.972182 ==
5445 11:06:53.974777 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 11:06:53.978051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 11:06:53.981157 ==
5448 11:06:53.981670 DQS Delay:
5449 11:06:53.981999 DQS0 = 0, DQS1 = 0
5450 11:06:53.984632 DQM Delay:
5451 11:06:53.985060 DQM0 = 104, DQM1 = 90
5452 11:06:53.987864 DQ Delay:
5453 11:06:53.988362 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5454 11:06:53.994965 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5455 11:06:53.997667 DQ8 =83, DQ9 =83, DQ10 =87, DQ11 =87
5456 11:06:54.001232 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5457 11:06:54.001664
5458 11:06:54.001996
5459 11:06:54.002299 ==
5460 11:06:54.004693 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 11:06:54.008147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 11:06:54.008663 ==
5463 11:06:54.008999
5464 11:06:54.009355
5465 11:06:54.011142 TX Vref Scan disable
5466 11:06:54.011664 == TX Byte 0 ==
5467 11:06:54.017796 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5468 11:06:54.020992 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5469 11:06:54.021562 == TX Byte 1 ==
5470 11:06:54.027795 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5471 11:06:54.031313 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5472 11:06:54.031820 ==
5473 11:06:54.034155 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 11:06:54.037763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 11:06:54.038280 ==
5476 11:06:54.038799
5477 11:06:54.039227
5478 11:06:54.040845 TX Vref Scan disable
5479 11:06:54.044498 == TX Byte 0 ==
5480 11:06:54.047709 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5481 11:06:54.051215 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5482 11:06:54.054478 == TX Byte 1 ==
5483 11:06:54.057542 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5484 11:06:54.061273 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5485 11:06:54.061949
5486 11:06:54.064413 [DATLAT]
5487 11:06:54.064912 Freq=933, CH0 RK1
5488 11:06:54.065290
5489 11:06:54.067787 DATLAT Default: 0xb
5490 11:06:54.068284 0, 0xFFFF, sum = 0
5491 11:06:54.070738 1, 0xFFFF, sum = 0
5492 11:06:54.071176 2, 0xFFFF, sum = 0
5493 11:06:54.074093 3, 0xFFFF, sum = 0
5494 11:06:54.074529 4, 0xFFFF, sum = 0
5495 11:06:54.077557 5, 0xFFFF, sum = 0
5496 11:06:54.077993 6, 0xFFFF, sum = 0
5497 11:06:54.080771 7, 0xFFFF, sum = 0
5498 11:06:54.084129 8, 0xFFFF, sum = 0
5499 11:06:54.084656 9, 0xFFFF, sum = 0
5500 11:06:54.087181 10, 0x0, sum = 1
5501 11:06:54.087616 11, 0x0, sum = 2
5502 11:06:54.087952 12, 0x0, sum = 3
5503 11:06:54.090694 13, 0x0, sum = 4
5504 11:06:54.091200 best_step = 11
5505 11:06:54.091535
5506 11:06:54.091842 ==
5507 11:06:54.094311 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 11:06:54.100371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 11:06:54.100804 ==
5510 11:06:54.101247 RX Vref Scan: 0
5511 11:06:54.101572
5512 11:06:54.104008 RX Vref 0 -> 0, step: 1
5513 11:06:54.104503
5514 11:06:54.106877 RX Delay -53 -> 252, step: 4
5515 11:06:54.110447 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5516 11:06:54.117216 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5517 11:06:54.120641 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5518 11:06:54.123516 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5519 11:06:54.127134 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5520 11:06:54.130503 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5521 11:06:54.136904 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5522 11:06:54.140234 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5523 11:06:54.143434 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5524 11:06:54.147046 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5525 11:06:54.149929 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5526 11:06:54.153292 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5527 11:06:54.160023 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5528 11:06:54.163547 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5529 11:06:54.166536 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5530 11:06:54.169806 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5531 11:06:54.170483 ==
5532 11:06:54.173709 Dram Type= 6, Freq= 0, CH_0, rank 1
5533 11:06:54.180086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 11:06:54.180814 ==
5535 11:06:54.181439 DQS Delay:
5536 11:06:54.181828 DQS0 = 0, DQS1 = 0
5537 11:06:54.183287 DQM Delay:
5538 11:06:54.183718 DQM0 = 103, DQM1 = 93
5539 11:06:54.186741 DQ Delay:
5540 11:06:54.189961 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =98
5541 11:06:54.193704 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5542 11:06:54.196848 DQ8 =86, DQ9 =82, DQ10 =96, DQ11 =90
5543 11:06:54.200025 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5544 11:06:54.200424
5545 11:06:54.200723
5546 11:06:54.207213 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
5547 11:06:54.210428 CH0 RK1: MR19=505, MR18=2D0C
5548 11:06:54.217085 CH0_RK1: MR19=0x505, MR18=0x2D0C, DQSOSC=407, MR23=63, INC=65, DEC=43
5549 11:06:54.220646 [RxdqsGatingPostProcess] freq 933
5550 11:06:54.223759 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5551 11:06:54.227200 best DQS0 dly(2T, 0.5T) = (0, 10)
5552 11:06:54.230350 best DQS1 dly(2T, 0.5T) = (0, 10)
5553 11:06:54.233781 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5554 11:06:54.237115 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5555 11:06:54.240164 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 11:06:54.243855 best DQS1 dly(2T, 0.5T) = (0, 10)
5557 11:06:54.247012 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 11:06:54.250436 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5559 11:06:54.254051 Pre-setting of DQS Precalculation
5560 11:06:54.257201 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5561 11:06:54.257739 ==
5562 11:06:54.260691 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 11:06:54.267431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 11:06:54.267943 ==
5565 11:06:54.270687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 11:06:54.277084 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5567 11:06:54.280635 [CA 0] Center 38 (8~68) winsize 61
5568 11:06:54.283941 [CA 1] Center 37 (7~68) winsize 62
5569 11:06:54.287172 [CA 2] Center 36 (6~66) winsize 61
5570 11:06:54.290978 [CA 3] Center 35 (5~65) winsize 61
5571 11:06:54.293535 [CA 4] Center 35 (5~66) winsize 62
5572 11:06:54.297503 [CA 5] Center 35 (5~65) winsize 61
5573 11:06:54.298008
5574 11:06:54.300460 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5575 11:06:54.300885
5576 11:06:54.303691 [CATrainingPosCal] consider 1 rank data
5577 11:06:54.306983 u2DelayCellTimex100 = 270/100 ps
5578 11:06:54.310474 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5579 11:06:54.313880 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5580 11:06:54.316804 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5581 11:06:54.324356 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5582 11:06:54.327415 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
5583 11:06:54.331009 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5584 11:06:54.331519
5585 11:06:54.333998 CA PerBit enable=1, Macro0, CA PI delay=35
5586 11:06:54.334426
5587 11:06:54.337531 [CBTSetCACLKResult] CA Dly = 35
5588 11:06:54.337961 CS Dly: 7 (0~38)
5589 11:06:54.338290 ==
5590 11:06:54.340707 Dram Type= 6, Freq= 0, CH_1, rank 1
5591 11:06:54.344269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 11:06:54.347263 ==
5593 11:06:54.350581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 11:06:54.357076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5595 11:06:54.360540 [CA 0] Center 38 (8~68) winsize 61
5596 11:06:54.363903 [CA 1] Center 38 (8~69) winsize 62
5597 11:06:54.367335 [CA 2] Center 36 (6~66) winsize 61
5598 11:06:54.370855 [CA 3] Center 35 (5~65) winsize 61
5599 11:06:54.373990 [CA 4] Center 35 (5~65) winsize 61
5600 11:06:54.377280 [CA 5] Center 35 (5~65) winsize 61
5601 11:06:54.377788
5602 11:06:54.380320 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5603 11:06:54.380746
5604 11:06:54.384173 [CATrainingPosCal] consider 2 rank data
5605 11:06:54.387350 u2DelayCellTimex100 = 270/100 ps
5606 11:06:54.390839 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5607 11:06:54.394053 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5608 11:06:54.397285 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5609 11:06:54.403984 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5610 11:06:54.407281 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5611 11:06:54.410684 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5612 11:06:54.411192
5613 11:06:54.413656 CA PerBit enable=1, Macro0, CA PI delay=35
5614 11:06:54.414083
5615 11:06:54.417237 [CBTSetCACLKResult] CA Dly = 35
5616 11:06:54.417779 CS Dly: 7 (0~39)
5617 11:06:54.418123
5618 11:06:54.420849 ----->DramcWriteLeveling(PI) begin...
5619 11:06:54.421329 ==
5620 11:06:54.423931 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 11:06:54.430392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 11:06:54.430905 ==
5623 11:06:54.433838 Write leveling (Byte 0): 28 => 28
5624 11:06:54.437100 Write leveling (Byte 1): 28 => 28
5625 11:06:54.437585 DramcWriteLeveling(PI) end<-----
5626 11:06:54.438016
5627 11:06:54.440472 ==
5628 11:06:54.443601 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 11:06:54.446991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 11:06:54.447432 ==
5631 11:06:54.450652 [Gating] SW mode calibration
5632 11:06:54.457337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5633 11:06:54.460270 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5634 11:06:54.467046 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 11:06:54.470225 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 11:06:54.473737 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 11:06:54.480417 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 11:06:54.483644 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 11:06:54.486556 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 11:06:54.493539 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 1)
5641 11:06:54.496949 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5642 11:06:54.500587 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 11:06:54.507156 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 11:06:54.510172 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 11:06:54.514126 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 11:06:54.520381 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 11:06:54.523813 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 11:06:54.526851 0 15 24 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
5649 11:06:54.530549 0 15 28 | B1->B0 | 3b3b 4545 | 1 0 | (0 0) (0 0)
5650 11:06:54.536711 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 11:06:54.540510 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:06:54.543574 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:06:54.550198 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 11:06:54.553754 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 11:06:54.557006 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5656 11:06:54.563867 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5657 11:06:54.566979 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5658 11:06:54.570002 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:06:54.577178 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:06:54.579994 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:06:54.583675 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:06:54.590006 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:06:54.593497 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:06:54.597095 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:06:54.603558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:06:54.607213 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:06:54.610825 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:06:54.613862 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:06:54.620777 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:06:54.623976 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:06:54.626742 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5672 11:06:54.633315 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5673 11:06:54.636979 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 11:06:54.640190 Total UI for P1: 0, mck2ui 16
5675 11:06:54.643751 best dqsien dly found for B0: ( 1, 2, 22)
5676 11:06:54.646849 Total UI for P1: 0, mck2ui 16
5677 11:06:54.650409 best dqsien dly found for B1: ( 1, 2, 24)
5678 11:06:54.653708 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5679 11:06:54.656900 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5680 11:06:54.657465
5681 11:06:54.660371 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5682 11:06:54.663792 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5683 11:06:54.666604 [Gating] SW calibration Done
5684 11:06:54.667036 ==
5685 11:06:54.670103 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 11:06:54.676807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 11:06:54.677401 ==
5688 11:06:54.677756 RX Vref Scan: 0
5689 11:06:54.678069
5690 11:06:54.680196 RX Vref 0 -> 0, step: 1
5691 11:06:54.680711
5692 11:06:54.683422 RX Delay -80 -> 252, step: 8
5693 11:06:54.686638 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5694 11:06:54.689969 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5695 11:06:54.693772 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5696 11:06:54.696722 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5697 11:06:54.703426 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5698 11:06:54.706743 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5699 11:06:54.710152 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5700 11:06:54.713620 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5701 11:06:54.716505 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5702 11:06:54.720363 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5703 11:06:54.726944 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5704 11:06:54.730480 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5705 11:06:54.733768 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5706 11:06:54.737203 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5707 11:06:54.740012 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5708 11:06:54.743116 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5709 11:06:54.746801 ==
5710 11:06:54.749925 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 11:06:54.753692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 11:06:54.754234 ==
5713 11:06:54.754677 DQS Delay:
5714 11:06:54.756443 DQS0 = 0, DQS1 = 0
5715 11:06:54.756883 DQM Delay:
5716 11:06:54.760073 DQM0 = 103, DQM1 = 94
5717 11:06:54.760594 DQ Delay:
5718 11:06:54.763337 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =103
5719 11:06:54.766661 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5720 11:06:54.770520 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5721 11:06:54.773036 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5722 11:06:54.773626
5723 11:06:54.774064
5724 11:06:54.774479 ==
5725 11:06:54.776675 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 11:06:54.780406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 11:06:54.780935 ==
5728 11:06:54.783419
5729 11:06:54.783939
5730 11:06:54.784378 TX Vref Scan disable
5731 11:06:54.786600 == TX Byte 0 ==
5732 11:06:54.789566 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5733 11:06:54.793276 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5734 11:06:54.796348 == TX Byte 1 ==
5735 11:06:54.799989 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5736 11:06:54.802978 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5737 11:06:54.803410 ==
5738 11:06:54.806397 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 11:06:54.813091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 11:06:54.813651 ==
5741 11:06:54.813989
5742 11:06:54.814299
5743 11:06:54.814592 TX Vref Scan disable
5744 11:06:54.817078 == TX Byte 0 ==
5745 11:06:54.820445 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5746 11:06:54.827634 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5747 11:06:54.828156 == TX Byte 1 ==
5748 11:06:54.831102 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 11:06:54.834130 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 11:06:54.837568
5751 11:06:54.838085 [DATLAT]
5752 11:06:54.838420 Freq=933, CH1 RK0
5753 11:06:54.838734
5754 11:06:54.841029 DATLAT Default: 0xd
5755 11:06:54.841595 0, 0xFFFF, sum = 0
5756 11:06:54.844259 1, 0xFFFF, sum = 0
5757 11:06:54.844772 2, 0xFFFF, sum = 0
5758 11:06:54.847752 3, 0xFFFF, sum = 0
5759 11:06:54.848280 4, 0xFFFF, sum = 0
5760 11:06:54.850964 5, 0xFFFF, sum = 0
5761 11:06:54.851483 6, 0xFFFF, sum = 0
5762 11:06:54.853843 7, 0xFFFF, sum = 0
5763 11:06:54.857412 8, 0xFFFF, sum = 0
5764 11:06:54.857930 9, 0xFFFF, sum = 0
5765 11:06:54.861070 10, 0x0, sum = 1
5766 11:06:54.861637 11, 0x0, sum = 2
5767 11:06:54.861982 12, 0x0, sum = 3
5768 11:06:54.864028 13, 0x0, sum = 4
5769 11:06:54.864464 best_step = 11
5770 11:06:54.864793
5771 11:06:54.867135 ==
5772 11:06:54.867564 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 11:06:54.874217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 11:06:54.874760 ==
5775 11:06:54.875096 RX Vref Scan: 1
5776 11:06:54.875403
5777 11:06:54.876955 RX Vref 0 -> 0, step: 1
5778 11:06:54.877433
5779 11:06:54.880842 RX Delay -53 -> 252, step: 4
5780 11:06:54.881435
5781 11:06:54.884189 Set Vref, RX VrefLevel [Byte0]: 53
5782 11:06:54.887312 [Byte1]: 52
5783 11:06:54.887819
5784 11:06:54.890562 Final RX Vref Byte 0 = 53 to rank0
5785 11:06:54.893981 Final RX Vref Byte 1 = 52 to rank0
5786 11:06:54.897313 Final RX Vref Byte 0 = 53 to rank1
5787 11:06:54.900623 Final RX Vref Byte 1 = 52 to rank1==
5788 11:06:54.903547 Dram Type= 6, Freq= 0, CH_1, rank 0
5789 11:06:54.907081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 11:06:54.907511 ==
5791 11:06:54.910004 DQS Delay:
5792 11:06:54.910080 DQS0 = 0, DQS1 = 0
5793 11:06:54.913317 DQM Delay:
5794 11:06:54.913456 DQM0 = 104, DQM1 = 98
5795 11:06:54.913521 DQ Delay:
5796 11:06:54.916801 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5797 11:06:54.920058 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5798 11:06:54.923215 DQ8 =86, DQ9 =84, DQ10 =102, DQ11 =92
5799 11:06:54.930049 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =104
5800 11:06:54.930198
5801 11:06:54.930271
5802 11:06:54.936710 [DQSOSCAuto] RK0, (LSB)MR18= 0x2039, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
5803 11:06:54.940062 CH1 RK0: MR19=505, MR18=2039
5804 11:06:54.946673 CH1_RK0: MR19=0x505, MR18=0x2039, DQSOSC=404, MR23=63, INC=66, DEC=44
5805 11:06:54.946842
5806 11:06:54.949896 ----->DramcWriteLeveling(PI) begin...
5807 11:06:54.950088 ==
5808 11:06:54.953519 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 11:06:54.956789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 11:06:54.957002 ==
5811 11:06:54.960108 Write leveling (Byte 0): 26 => 26
5812 11:06:54.963394 Write leveling (Byte 1): 29 => 29
5813 11:06:54.966728 DramcWriteLeveling(PI) end<-----
5814 11:06:54.966993
5815 11:06:54.967154 ==
5816 11:06:54.970450 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 11:06:54.973597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 11:06:54.973979 ==
5819 11:06:54.976808 [Gating] SW mode calibration
5820 11:06:54.983738 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5821 11:06:54.990269 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5822 11:06:54.993548 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5823 11:06:55.000560 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 11:06:55.003810 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:06:55.006871 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 11:06:55.013633 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 11:06:55.016630 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 11:06:55.019976 0 14 24 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
5829 11:06:55.023276 0 14 28 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 1)
5830 11:06:55.030053 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 11:06:55.033364 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 11:06:55.036647 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:06:55.043594 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 11:06:55.047075 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 11:06:55.050095 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 11:06:55.056917 0 15 24 | B1->B0 | 2f2f 2424 | 1 0 | (0 0) (1 1)
5837 11:06:55.060213 0 15 28 | B1->B0 | 4040 3a3a | 0 0 | (0 0) (0 0)
5838 11:06:55.063520 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 11:06:55.070157 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:06:55.073675 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:06:55.076931 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:06:55.083672 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 11:06:55.087025 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 11:06:55.090110 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 11:06:55.096960 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5846 11:06:55.100318 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:06:55.103749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:06:55.110137 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:06:55.113558 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:06:55.116493 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:06:55.123722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:06:55.126539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:06:55.130132 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:06:55.133633 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:06:55.140241 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:06:55.143240 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:06:55.146460 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:06:55.153342 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:06:55.156631 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:06:55.159436 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5861 11:06:55.166317 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 11:06:55.170014 Total UI for P1: 0, mck2ui 16
5863 11:06:55.173042 best dqsien dly found for B0: ( 1, 2, 24)
5864 11:06:55.176514 Total UI for P1: 0, mck2ui 16
5865 11:06:55.179822 best dqsien dly found for B1: ( 1, 2, 26)
5866 11:06:55.182875 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5867 11:06:55.186660 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5868 11:06:55.187166
5869 11:06:55.189519 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5870 11:06:55.193204 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5871 11:06:55.196392 [Gating] SW calibration Done
5872 11:06:55.196909 ==
5873 11:06:55.200091 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 11:06:55.202951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 11:06:55.203391 ==
5876 11:06:55.206136 RX Vref Scan: 0
5877 11:06:55.206789
5878 11:06:55.207150 RX Vref 0 -> 0, step: 1
5879 11:06:55.207470
5880 11:06:55.209739 RX Delay -80 -> 252, step: 8
5881 11:06:55.216309 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5882 11:06:55.219758 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5883 11:06:55.222779 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5884 11:06:55.226068 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5885 11:06:55.229592 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5886 11:06:55.233066 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5887 11:06:55.239612 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5888 11:06:55.242716 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5889 11:06:55.246523 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5890 11:06:55.249479 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5891 11:06:55.252973 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5892 11:06:55.256134 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5893 11:06:55.262909 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5894 11:06:55.266672 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5895 11:06:55.269513 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5896 11:06:55.273101 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5897 11:06:55.273667 ==
5898 11:06:55.276450 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 11:06:55.283025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 11:06:55.283522 ==
5901 11:06:55.283859 DQS Delay:
5902 11:06:55.284167 DQS0 = 0, DQS1 = 0
5903 11:06:55.286313 DQM Delay:
5904 11:06:55.286741 DQM0 = 103, DQM1 = 96
5905 11:06:55.289451 DQ Delay:
5906 11:06:55.293239 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5907 11:06:55.296480 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5908 11:06:55.299600 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5909 11:06:55.302912 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5910 11:06:55.303344
5911 11:06:55.303674
5912 11:06:55.303974 ==
5913 11:06:55.306494 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 11:06:55.309678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 11:06:55.310192 ==
5916 11:06:55.310525
5917 11:06:55.310825
5918 11:06:55.313122 TX Vref Scan disable
5919 11:06:55.316403 == TX Byte 0 ==
5920 11:06:55.319549 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5921 11:06:55.323125 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5922 11:06:55.326019 == TX Byte 1 ==
5923 11:06:55.329224 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5924 11:06:55.332699 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5925 11:06:55.333161 ==
5926 11:06:55.336101 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 11:06:55.339514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 11:06:55.342744 ==
5929 11:06:55.343253
5930 11:06:55.343582
5931 11:06:55.343886 TX Vref Scan disable
5932 11:06:55.346522 == TX Byte 0 ==
5933 11:06:55.349936 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5934 11:06:55.356638 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5935 11:06:55.357217 == TX Byte 1 ==
5936 11:06:55.359767 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 11:06:55.362906 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 11:06:55.366134
5939 11:06:55.366561 [DATLAT]
5940 11:06:55.366892 Freq=933, CH1 RK1
5941 11:06:55.367262
5942 11:06:55.369971 DATLAT Default: 0xb
5943 11:06:55.370485 0, 0xFFFF, sum = 0
5944 11:06:55.373096 1, 0xFFFF, sum = 0
5945 11:06:55.373567 2, 0xFFFF, sum = 0
5946 11:06:55.376578 3, 0xFFFF, sum = 0
5947 11:06:55.377093 4, 0xFFFF, sum = 0
5948 11:06:55.379841 5, 0xFFFF, sum = 0
5949 11:06:55.383333 6, 0xFFFF, sum = 0
5950 11:06:55.383851 7, 0xFFFF, sum = 0
5951 11:06:55.386514 8, 0xFFFF, sum = 0
5952 11:06:55.386952 9, 0xFFFF, sum = 0
5953 11:06:55.389621 10, 0x0, sum = 1
5954 11:06:55.390059 11, 0x0, sum = 2
5955 11:06:55.390402 12, 0x0, sum = 3
5956 11:06:55.393194 13, 0x0, sum = 4
5957 11:06:55.393728 best_step = 11
5958 11:06:55.394069
5959 11:06:55.396288 ==
5960 11:06:55.396807 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 11:06:55.403056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 11:06:55.403575 ==
5963 11:06:55.403916 RX Vref Scan: 0
5964 11:06:55.404234
5965 11:06:55.406355 RX Vref 0 -> 0, step: 1
5966 11:06:55.406875
5967 11:06:55.409518 RX Delay -53 -> 252, step: 4
5968 11:06:55.412976 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5969 11:06:55.419725 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5970 11:06:55.423140 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5971 11:06:55.426088 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5972 11:06:55.429764 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5973 11:06:55.432714 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5974 11:06:55.439487 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5975 11:06:55.442540 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5976 11:06:55.446135 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5977 11:06:55.449440 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5978 11:06:55.452947 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5979 11:06:55.456393 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5980 11:06:55.462996 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5981 11:06:55.466129 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5982 11:06:55.469502 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5983 11:06:55.472613 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5984 11:06:55.473159 ==
5985 11:06:55.476074 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 11:06:55.483172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 11:06:55.483811 ==
5988 11:06:55.484162 DQS Delay:
5989 11:06:55.484473 DQS0 = 0, DQS1 = 0
5990 11:06:55.486216 DQM Delay:
5991 11:06:55.486654 DQM0 = 105, DQM1 = 98
5992 11:06:55.489505 DQ Delay:
5993 11:06:55.492448 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5994 11:06:55.496135 DQ4 =108, DQ5 =116, DQ6 =110, DQ7 =102
5995 11:06:55.499527 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =92
5996 11:06:55.502521 DQ12 =108, DQ13 =106, DQ14 =106, DQ15 =108
5997 11:06:55.502756
5998 11:06:55.502895
5999 11:06:55.509333 [DQSOSCAuto] RK1, (LSB)MR18= 0x2806, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
6000 11:06:55.512767 CH1 RK1: MR19=505, MR18=2806
6001 11:06:55.519075 CH1_RK1: MR19=0x505, MR18=0x2806, DQSOSC=409, MR23=63, INC=64, DEC=43
6002 11:06:55.522749 [RxdqsGatingPostProcess] freq 933
6003 11:06:55.529523 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6004 11:06:55.529915 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 11:06:55.532710 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 11:06:55.536204 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 11:06:55.539410 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 11:06:55.542990 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 11:06:55.545971 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 11:06:55.549025 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 11:06:55.552907 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 11:06:55.556092 Pre-setting of DQS Precalculation
6013 11:06:55.562831 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6014 11:06:55.569586 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6015 11:06:55.575855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6016 11:06:55.576352
6017 11:06:55.576690
6018 11:06:55.579200 [Calibration Summary] 1866 Mbps
6019 11:06:55.579631 CH 0, Rank 0
6020 11:06:55.582721 SW Impedance : PASS
6021 11:06:55.583267 DUTY Scan : NO K
6022 11:06:55.585877 ZQ Calibration : PASS
6023 11:06:55.589272 Jitter Meter : NO K
6024 11:06:55.589789 CBT Training : PASS
6025 11:06:55.592572 Write leveling : PASS
6026 11:06:55.596379 RX DQS gating : PASS
6027 11:06:55.596887 RX DQ/DQS(RDDQC) : PASS
6028 11:06:55.599236 TX DQ/DQS : PASS
6029 11:06:55.602665 RX DATLAT : PASS
6030 11:06:55.603168 RX DQ/DQS(Engine): PASS
6031 11:06:55.606035 TX OE : NO K
6032 11:06:55.606542 All Pass.
6033 11:06:55.606878
6034 11:06:55.609520 CH 0, Rank 1
6035 11:06:55.610025 SW Impedance : PASS
6036 11:06:55.612582 DUTY Scan : NO K
6037 11:06:55.616188 ZQ Calibration : PASS
6038 11:06:55.616689 Jitter Meter : NO K
6039 11:06:55.618966 CBT Training : PASS
6040 11:06:55.622483 Write leveling : PASS
6041 11:06:55.622981 RX DQS gating : PASS
6042 11:06:55.626036 RX DQ/DQS(RDDQC) : PASS
6043 11:06:55.626540 TX DQ/DQS : PASS
6044 11:06:55.629228 RX DATLAT : PASS
6045 11:06:55.632195 RX DQ/DQS(Engine): PASS
6046 11:06:55.632628 TX OE : NO K
6047 11:06:55.635810 All Pass.
6048 11:06:55.636312
6049 11:06:55.636647 CH 1, Rank 0
6050 11:06:55.639217 SW Impedance : PASS
6051 11:06:55.639725 DUTY Scan : NO K
6052 11:06:55.642307 ZQ Calibration : PASS
6053 11:06:55.646000 Jitter Meter : NO K
6054 11:06:55.646508 CBT Training : PASS
6055 11:06:55.648955 Write leveling : PASS
6056 11:06:55.652646 RX DQS gating : PASS
6057 11:06:55.653229 RX DQ/DQS(RDDQC) : PASS
6058 11:06:55.656050 TX DQ/DQS : PASS
6059 11:06:55.658999 RX DATLAT : PASS
6060 11:06:55.659438 RX DQ/DQS(Engine): PASS
6061 11:06:55.662522 TX OE : NO K
6062 11:06:55.663028 All Pass.
6063 11:06:55.663362
6064 11:06:55.666129 CH 1, Rank 1
6065 11:06:55.666563 SW Impedance : PASS
6066 11:06:55.669300 DUTY Scan : NO K
6067 11:06:55.669800 ZQ Calibration : PASS
6068 11:06:55.672414 Jitter Meter : NO K
6069 11:06:55.675801 CBT Training : PASS
6070 11:06:55.676232 Write leveling : PASS
6071 11:06:55.679018 RX DQS gating : PASS
6072 11:06:55.682839 RX DQ/DQS(RDDQC) : PASS
6073 11:06:55.683359 TX DQ/DQS : PASS
6074 11:06:55.686080 RX DATLAT : PASS
6075 11:06:55.689231 RX DQ/DQS(Engine): PASS
6076 11:06:55.689744 TX OE : NO K
6077 11:06:55.692535 All Pass.
6078 11:06:55.693198
6079 11:06:55.693559 DramC Write-DBI off
6080 11:06:55.696000 PER_BANK_REFRESH: Hybrid Mode
6081 11:06:55.696504 TX_TRACKING: ON
6082 11:06:55.706186 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6083 11:06:55.709415 [FAST_K] Save calibration result to emmc
6084 11:06:55.712782 dramc_set_vcore_voltage set vcore to 650000
6085 11:06:55.715975 Read voltage for 400, 6
6086 11:06:55.716410 Vio18 = 0
6087 11:06:55.719744 Vcore = 650000
6088 11:06:55.720247 Vdram = 0
6089 11:06:55.720583 Vddq = 0
6090 11:06:55.720891 Vmddr = 0
6091 11:06:55.726072 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6092 11:06:55.732671 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6093 11:06:55.733222 MEM_TYPE=3, freq_sel=20
6094 11:06:55.735787 sv_algorithm_assistance_LP4_800
6095 11:06:55.739506 ============ PULL DRAM RESETB DOWN ============
6096 11:06:55.746037 ========== PULL DRAM RESETB DOWN end =========
6097 11:06:55.749203 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6098 11:06:55.752906 ===================================
6099 11:06:55.756278 LPDDR4 DRAM CONFIGURATION
6100 11:06:55.759917 ===================================
6101 11:06:55.760429 EX_ROW_EN[0] = 0x0
6102 11:06:55.763188 EX_ROW_EN[1] = 0x0
6103 11:06:55.763697 LP4Y_EN = 0x0
6104 11:06:55.766439 WORK_FSP = 0x0
6105 11:06:55.766951 WL = 0x2
6106 11:06:55.769541 RL = 0x2
6107 11:06:55.770049 BL = 0x2
6108 11:06:55.772963 RPST = 0x0
6109 11:06:55.773554 RD_PRE = 0x0
6110 11:06:55.776133 WR_PRE = 0x1
6111 11:06:55.776562 WR_PST = 0x0
6112 11:06:55.779603 DBI_WR = 0x0
6113 11:06:55.783127 DBI_RD = 0x0
6114 11:06:55.783657 OTF = 0x1
6115 11:06:55.786476 ===================================
6116 11:06:55.789102 ===================================
6117 11:06:55.789619 ANA top config
6118 11:06:55.792852 ===================================
6119 11:06:55.795984 DLL_ASYNC_EN = 0
6120 11:06:55.799246 ALL_SLAVE_EN = 1
6121 11:06:55.802614 NEW_RANK_MODE = 1
6122 11:06:55.805876 DLL_IDLE_MODE = 1
6123 11:06:55.806387 LP45_APHY_COMB_EN = 1
6124 11:06:55.809121 TX_ODT_DIS = 1
6125 11:06:55.812607 NEW_8X_MODE = 1
6126 11:06:55.816286 ===================================
6127 11:06:55.819167 ===================================
6128 11:06:55.822379 data_rate = 800
6129 11:06:55.825980 CKR = 1
6130 11:06:55.826485 DQ_P2S_RATIO = 4
6131 11:06:55.829178 ===================================
6132 11:06:55.832371 CA_P2S_RATIO = 4
6133 11:06:55.836089 DQ_CA_OPEN = 0
6134 11:06:55.838750 DQ_SEMI_OPEN = 1
6135 11:06:55.842163 CA_SEMI_OPEN = 1
6136 11:06:55.845795 CA_FULL_RATE = 0
6137 11:06:55.846303 DQ_CKDIV4_EN = 0
6138 11:06:55.848821 CA_CKDIV4_EN = 1
6139 11:06:55.852375 CA_PREDIV_EN = 0
6140 11:06:55.855360 PH8_DLY = 0
6141 11:06:55.859049 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6142 11:06:55.862340 DQ_AAMCK_DIV = 0
6143 11:06:55.862854 CA_AAMCK_DIV = 0
6144 11:06:55.865435 CA_ADMCK_DIV = 4
6145 11:06:55.869101 DQ_TRACK_CA_EN = 0
6146 11:06:55.872343 CA_PICK = 800
6147 11:06:55.875596 CA_MCKIO = 400
6148 11:06:55.878664 MCKIO_SEMI = 400
6149 11:06:55.882137 PLL_FREQ = 3016
6150 11:06:55.882646 DQ_UI_PI_RATIO = 32
6151 11:06:55.885509 CA_UI_PI_RATIO = 32
6152 11:06:55.888699 ===================================
6153 11:06:55.891869 ===================================
6154 11:06:55.895216 memory_type:LPDDR4
6155 11:06:55.898746 GP_NUM : 10
6156 11:06:55.899253 SRAM_EN : 1
6157 11:06:55.902495 MD32_EN : 0
6158 11:06:55.905519 ===================================
6159 11:06:55.909231 [ANA_INIT] >>>>>>>>>>>>>>
6160 11:06:55.909733 <<<<<< [CONFIGURE PHASE]: ANA_TX
6161 11:06:55.915255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6162 11:06:55.918593 ===================================
6163 11:06:55.919028 data_rate = 800,PCW = 0X7400
6164 11:06:55.921630 ===================================
6165 11:06:55.925306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6166 11:06:55.932241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 11:06:55.941905 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 11:06:55.948318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6169 11:06:55.951986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6170 11:06:55.955096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6171 11:06:55.958413 [ANA_INIT] flow start
6172 11:06:55.958922 [ANA_INIT] PLL >>>>>>>>
6173 11:06:55.961515 [ANA_INIT] PLL <<<<<<<<
6174 11:06:55.965082 [ANA_INIT] MIDPI >>>>>>>>
6175 11:06:55.965662 [ANA_INIT] MIDPI <<<<<<<<
6176 11:06:55.968096 [ANA_INIT] DLL >>>>>>>>
6177 11:06:55.971584 [ANA_INIT] flow end
6178 11:06:55.974963 ============ LP4 DIFF to SE enter ============
6179 11:06:55.978533 ============ LP4 DIFF to SE exit ============
6180 11:06:55.982039 [ANA_INIT] <<<<<<<<<<<<<
6181 11:06:55.984946 [Flow] Enable top DCM control >>>>>
6182 11:06:55.988154 [Flow] Enable top DCM control <<<<<
6183 11:06:55.991239 Enable DLL master slave shuffle
6184 11:06:55.994627 ==============================================================
6185 11:06:55.998056 Gating Mode config
6186 11:06:56.005032 ==============================================================
6187 11:06:56.005584 Config description:
6188 11:06:56.015124 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6189 11:06:56.021539 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6190 11:06:56.025209 SELPH_MODE 0: By rank 1: By Phase
6191 11:06:56.031809 ==============================================================
6192 11:06:56.034686 GAT_TRACK_EN = 0
6193 11:06:56.038177 RX_GATING_MODE = 2
6194 11:06:56.041829 RX_GATING_TRACK_MODE = 2
6195 11:06:56.044834 SELPH_MODE = 1
6196 11:06:56.048539 PICG_EARLY_EN = 1
6197 11:06:56.049302 VALID_LAT_VALUE = 1
6198 11:06:56.054799 ==============================================================
6199 11:06:56.057993 Enter into Gating configuration >>>>
6200 11:06:56.061493 Exit from Gating configuration <<<<
6201 11:06:56.064911 Enter into DVFS_PRE_config >>>>>
6202 11:06:56.074970 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6203 11:06:56.078162 Exit from DVFS_PRE_config <<<<<
6204 11:06:56.081715 Enter into PICG configuration >>>>
6205 11:06:56.085050 Exit from PICG configuration <<<<
6206 11:06:56.088366 [RX_INPUT] configuration >>>>>
6207 11:06:56.091886 [RX_INPUT] configuration <<<<<
6208 11:06:56.094898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6209 11:06:56.101686 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6210 11:06:56.108390 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6211 11:06:56.115032 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6212 11:06:56.121530 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 11:06:56.128090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 11:06:56.131708 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6215 11:06:56.134609 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6216 11:06:56.138177 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6217 11:06:56.141600 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6218 11:06:56.148203 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6219 11:06:56.151344 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 11:06:56.154648 ===================================
6221 11:06:56.157835 LPDDR4 DRAM CONFIGURATION
6222 11:06:56.161066 ===================================
6223 11:06:56.161522 EX_ROW_EN[0] = 0x0
6224 11:06:56.164619 EX_ROW_EN[1] = 0x0
6225 11:06:56.165158 LP4Y_EN = 0x0
6226 11:06:56.168211 WORK_FSP = 0x0
6227 11:06:56.168717 WL = 0x2
6228 11:06:56.171573 RL = 0x2
6229 11:06:56.172084 BL = 0x2
6230 11:06:56.174536 RPST = 0x0
6231 11:06:56.177767 RD_PRE = 0x0
6232 11:06:56.178194 WR_PRE = 0x1
6233 11:06:56.181661 WR_PST = 0x0
6234 11:06:56.182172 DBI_WR = 0x0
6235 11:06:56.184675 DBI_RD = 0x0
6236 11:06:56.185251 OTF = 0x1
6237 11:06:56.188136 ===================================
6238 11:06:56.191325 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6239 11:06:56.194653 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6240 11:06:56.201236 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 11:06:56.204602 ===================================
6242 11:06:56.208141 LPDDR4 DRAM CONFIGURATION
6243 11:06:56.211379 ===================================
6244 11:06:56.211884 EX_ROW_EN[0] = 0x10
6245 11:06:56.214917 EX_ROW_EN[1] = 0x0
6246 11:06:56.215427 LP4Y_EN = 0x0
6247 11:06:56.218009 WORK_FSP = 0x0
6248 11:06:56.218515 WL = 0x2
6249 11:06:56.221414 RL = 0x2
6250 11:06:56.221926 BL = 0x2
6251 11:06:56.224600 RPST = 0x0
6252 11:06:56.225106 RD_PRE = 0x0
6253 11:06:56.228417 WR_PRE = 0x1
6254 11:06:56.228921 WR_PST = 0x0
6255 11:06:56.231607 DBI_WR = 0x0
6256 11:06:56.232114 DBI_RD = 0x0
6257 11:06:56.234319 OTF = 0x1
6258 11:06:56.238056 ===================================
6259 11:06:56.244394 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6260 11:06:56.247960 nWR fixed to 30
6261 11:06:56.251091 [ModeRegInit_LP4] CH0 RK0
6262 11:06:56.251774 [ModeRegInit_LP4] CH0 RK1
6263 11:06:56.254338 [ModeRegInit_LP4] CH1 RK0
6264 11:06:56.257800 [ModeRegInit_LP4] CH1 RK1
6265 11:06:56.258382 match AC timing 19
6266 11:06:56.264415 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6267 11:06:56.267836 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6268 11:06:56.271020 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6269 11:06:56.277628 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6270 11:06:56.280990 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6271 11:06:56.281691 ==
6272 11:06:56.284458 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 11:06:56.287667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 11:06:56.288170 ==
6275 11:06:56.294175 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 11:06:56.301064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6277 11:06:56.304419 [CA 0] Center 36 (8~64) winsize 57
6278 11:06:56.307737 [CA 1] Center 36 (8~64) winsize 57
6279 11:06:56.308137 [CA 2] Center 36 (8~64) winsize 57
6280 11:06:56.310989 [CA 3] Center 36 (8~64) winsize 57
6281 11:06:56.314452 [CA 4] Center 36 (8~64) winsize 57
6282 11:06:56.317491 [CA 5] Center 36 (8~64) winsize 57
6283 11:06:56.318005
6284 11:06:56.321008 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6285 11:06:56.321607
6286 11:06:56.327756 [CATrainingPosCal] consider 1 rank data
6287 11:06:56.328237 u2DelayCellTimex100 = 270/100 ps
6288 11:06:56.334599 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:06:56.337603 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 11:06:56.341265 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:06:56.344607 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:06:56.347952 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:06:56.350841 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 11:06:56.351234
6295 11:06:56.354329 CA PerBit enable=1, Macro0, CA PI delay=36
6296 11:06:56.354798
6297 11:06:56.357812 [CBTSetCACLKResult] CA Dly = 36
6298 11:06:56.361167 CS Dly: 1 (0~32)
6299 11:06:56.361642 ==
6300 11:06:56.364582 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 11:06:56.367488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 11:06:56.367921 ==
6303 11:06:56.374395 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 11:06:56.377642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6305 11:06:56.380805 [CA 0] Center 36 (8~64) winsize 57
6306 11:06:56.384692 [CA 1] Center 36 (8~64) winsize 57
6307 11:06:56.387832 [CA 2] Center 36 (8~64) winsize 57
6308 11:06:56.391033 [CA 3] Center 36 (8~64) winsize 57
6309 11:06:56.394608 [CA 4] Center 36 (8~64) winsize 57
6310 11:06:56.398054 [CA 5] Center 36 (8~64) winsize 57
6311 11:06:56.398559
6312 11:06:56.401165 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6313 11:06:56.401590
6314 11:06:56.404658 [CATrainingPosCal] consider 2 rank data
6315 11:06:56.408055 u2DelayCellTimex100 = 270/100 ps
6316 11:06:56.411297 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:06:56.414669 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:06:56.418056 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:06:56.421228 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:06:56.424929 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:06:56.431452 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:06:56.431953
6323 11:06:56.434679 CA PerBit enable=1, Macro0, CA PI delay=36
6324 11:06:56.435182
6325 11:06:56.438082 [CBTSetCACLKResult] CA Dly = 36
6326 11:06:56.438592 CS Dly: 1 (0~32)
6327 11:06:56.438922
6328 11:06:56.441408 ----->DramcWriteLeveling(PI) begin...
6329 11:06:56.441920 ==
6330 11:06:56.444621 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 11:06:56.448215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 11:06:56.451361 ==
6333 11:06:56.451789 Write leveling (Byte 0): 40 => 8
6334 11:06:56.454716 Write leveling (Byte 1): 32 => 0
6335 11:06:56.458034 DramcWriteLeveling(PI) end<-----
6336 11:06:56.458536
6337 11:06:56.458864 ==
6338 11:06:56.461071 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 11:06:56.467565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 11:06:56.468059 ==
6341 11:06:56.468392 [Gating] SW mode calibration
6342 11:06:56.477653 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6343 11:06:56.481192 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6344 11:06:56.484401 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 11:06:56.491092 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 11:06:56.494387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 11:06:56.497785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 11:06:56.504898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 11:06:56.507937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 11:06:56.510798 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 11:06:56.517970 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 11:06:56.520628 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 11:06:56.524462 Total UI for P1: 0, mck2ui 16
6354 11:06:56.527792 best dqsien dly found for B0: ( 0, 14, 24)
6355 11:06:56.530859 Total UI for P1: 0, mck2ui 16
6356 11:06:56.534276 best dqsien dly found for B1: ( 0, 14, 24)
6357 11:06:56.537602 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6358 11:06:56.540656 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6359 11:06:56.541080
6360 11:06:56.544159 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 11:06:56.547770 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 11:06:56.550612 [Gating] SW calibration Done
6363 11:06:56.551038 ==
6364 11:06:56.554493 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 11:06:56.561012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 11:06:56.561554 ==
6367 11:06:56.561896 RX Vref Scan: 0
6368 11:06:56.562201
6369 11:06:56.564484 RX Vref 0 -> 0, step: 1
6370 11:06:56.564983
6371 11:06:56.567356 RX Delay -410 -> 252, step: 16
6372 11:06:56.570921 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6373 11:06:56.574164 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6374 11:06:56.577700 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6375 11:06:56.584329 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6376 11:06:56.587556 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6377 11:06:56.590838 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6378 11:06:56.594539 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6379 11:06:56.601310 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6380 11:06:56.604322 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6381 11:06:56.607556 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6382 11:06:56.611127 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6383 11:06:56.618080 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6384 11:06:56.620947 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6385 11:06:56.624382 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6386 11:06:56.628010 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6387 11:06:56.634244 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6388 11:06:56.634669 ==
6389 11:06:56.637982 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 11:06:56.640866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 11:06:56.641342 ==
6392 11:06:56.641677 DQS Delay:
6393 11:06:56.644526 DQS0 = 19, DQS1 = 43
6394 11:06:56.645122 DQM Delay:
6395 11:06:56.647661 DQM0 = 5, DQM1 = 15
6396 11:06:56.648169 DQ Delay:
6397 11:06:56.651062 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6398 11:06:56.654365 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6399 11:06:56.658086 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6400 11:06:56.661261 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6401 11:06:56.661766
6402 11:06:56.662089
6403 11:06:56.662385 ==
6404 11:06:56.664774 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 11:06:56.667821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 11:06:56.668248 ==
6407 11:06:56.668573
6408 11:06:56.668874
6409 11:06:56.671398 TX Vref Scan disable
6410 11:06:56.671896 == TX Byte 0 ==
6411 11:06:56.677896 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 11:06:56.681061 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 11:06:56.681613 == TX Byte 1 ==
6414 11:06:56.687945 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6415 11:06:56.690922 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6416 11:06:56.691349 ==
6417 11:06:56.694173 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 11:06:56.697995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 11:06:56.698502 ==
6420 11:06:56.698832
6421 11:06:56.699130
6422 11:06:56.701058 TX Vref Scan disable
6423 11:06:56.701620 == TX Byte 0 ==
6424 11:06:56.707850 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 11:06:56.711172 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 11:06:56.711745 == TX Byte 1 ==
6427 11:06:56.717842 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6428 11:06:56.720998 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6429 11:06:56.721579
6430 11:06:56.721915 [DATLAT]
6431 11:06:56.724275 Freq=400, CH0 RK0
6432 11:06:56.724792
6433 11:06:56.725123 DATLAT Default: 0xf
6434 11:06:56.727597 0, 0xFFFF, sum = 0
6435 11:06:56.728116 1, 0xFFFF, sum = 0
6436 11:06:56.731246 2, 0xFFFF, sum = 0
6437 11:06:56.731757 3, 0xFFFF, sum = 0
6438 11:06:56.734798 4, 0xFFFF, sum = 0
6439 11:06:56.735310 5, 0xFFFF, sum = 0
6440 11:06:56.737713 6, 0xFFFF, sum = 0
6441 11:06:56.740885 7, 0xFFFF, sum = 0
6442 11:06:56.741368 8, 0xFFFF, sum = 0
6443 11:06:56.744356 9, 0xFFFF, sum = 0
6444 11:06:56.744870 10, 0xFFFF, sum = 0
6445 11:06:56.747969 11, 0xFFFF, sum = 0
6446 11:06:56.748478 12, 0xFFFF, sum = 0
6447 11:06:56.751343 13, 0x0, sum = 1
6448 11:06:56.751857 14, 0x0, sum = 2
6449 11:06:56.754324 15, 0x0, sum = 3
6450 11:06:56.754753 16, 0x0, sum = 4
6451 11:06:56.755085 best_step = 14
6452 11:06:56.755383
6453 11:06:56.757657 ==
6454 11:06:56.761242 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 11:06:56.764471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 11:06:56.764975 ==
6457 11:06:56.765356 RX Vref Scan: 1
6458 11:06:56.765657
6459 11:06:56.767644 RX Vref 0 -> 0, step: 1
6460 11:06:56.768064
6461 11:06:56.771068 RX Delay -327 -> 252, step: 8
6462 11:06:56.771574
6463 11:06:56.774636 Set Vref, RX VrefLevel [Byte0]: 60
6464 11:06:56.777972 [Byte1]: 54
6465 11:06:56.781489
6466 11:06:56.781993 Final RX Vref Byte 0 = 60 to rank0
6467 11:06:56.784473 Final RX Vref Byte 1 = 54 to rank0
6468 11:06:56.788124 Final RX Vref Byte 0 = 60 to rank1
6469 11:06:56.790946 Final RX Vref Byte 1 = 54 to rank1==
6470 11:06:56.794462 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 11:06:56.801530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 11:06:56.802039 ==
6473 11:06:56.802367 DQS Delay:
6474 11:06:56.804685 DQS0 = 28, DQS1 = 44
6475 11:06:56.805232 DQM Delay:
6476 11:06:56.805562 DQM0 = 10, DQM1 = 10
6477 11:06:56.808274 DQ Delay:
6478 11:06:56.811401 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6479 11:06:56.811904 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6480 11:06:56.814264 DQ8 =4, DQ9 =0, DQ10 =8, DQ11 =4
6481 11:06:56.817624 DQ12 =16, DQ13 =12, DQ14 =24, DQ15 =16
6482 11:06:56.818128
6483 11:06:56.818458
6484 11:06:56.827605 [DQSOSCAuto] RK0, (LSB)MR18= 0xb7ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6485 11:06:56.831143 CH0 RK0: MR19=C0C, MR18=B7AE
6486 11:06:56.837913 CH0_RK0: MR19=0xC0C, MR18=0xB7AE, DQSOSC=387, MR23=63, INC=394, DEC=262
6487 11:06:56.838423 ==
6488 11:06:56.840762 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 11:06:56.844330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 11:06:56.844842 ==
6491 11:06:56.847833 [Gating] SW mode calibration
6492 11:06:56.854343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6493 11:06:56.857554 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6494 11:06:56.864565 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 11:06:56.867530 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 11:06:56.870664 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 11:06:56.877564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 11:06:56.880492 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 11:06:56.884009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 11:06:56.890589 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 11:06:56.893986 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 11:06:56.897305 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 11:06:56.900564 Total UI for P1: 0, mck2ui 16
6504 11:06:56.903610 best dqsien dly found for B0: ( 0, 14, 24)
6505 11:06:56.907290 Total UI for P1: 0, mck2ui 16
6506 11:06:56.910619 best dqsien dly found for B1: ( 0, 14, 24)
6507 11:06:56.913866 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6508 11:06:56.920704 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6509 11:06:56.921269
6510 11:06:56.923671 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 11:06:56.927201 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 11:06:56.930293 [Gating] SW calibration Done
6513 11:06:56.930720 ==
6514 11:06:56.933699 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 11:06:56.936758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 11:06:56.937344 ==
6517 11:06:56.940293 RX Vref Scan: 0
6518 11:06:56.940893
6519 11:06:56.941281 RX Vref 0 -> 0, step: 1
6520 11:06:56.941592
6521 11:06:56.943696 RX Delay -410 -> 252, step: 16
6522 11:06:56.947107 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6523 11:06:56.953681 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6524 11:06:56.956980 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6525 11:06:56.960687 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6526 11:06:56.963833 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6527 11:06:56.970540 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6528 11:06:56.974057 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6529 11:06:56.977246 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6530 11:06:56.980460 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6531 11:06:56.986859 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6532 11:06:56.990207 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6533 11:06:56.993877 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6534 11:06:56.996775 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6535 11:06:57.003822 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6536 11:06:57.007117 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6537 11:06:57.010127 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6538 11:06:57.010552 ==
6539 11:06:57.013386 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 11:06:57.017205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 11:06:57.020514 ==
6542 11:06:57.021044 DQS Delay:
6543 11:06:57.021434 DQS0 = 27, DQS1 = 35
6544 11:06:57.023491 DQM Delay:
6545 11:06:57.024000 DQM0 = 14, DQM1 = 7
6546 11:06:57.026938 DQ Delay:
6547 11:06:57.027450 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =16
6548 11:06:57.030382 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6549 11:06:57.033562 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6550 11:06:57.036909 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =8
6551 11:06:57.037377
6552 11:06:57.037707
6553 11:06:57.038012 ==
6554 11:06:57.040331 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 11:06:57.046964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 11:06:57.047499 ==
6557 11:06:57.047840
6558 11:06:57.048147
6559 11:06:57.048441 TX Vref Scan disable
6560 11:06:57.050109 == TX Byte 0 ==
6561 11:06:57.053314 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6562 11:06:57.057198 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6563 11:06:57.060622 == TX Byte 1 ==
6564 11:06:57.063945 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6565 11:06:57.067373 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6566 11:06:57.067897 ==
6567 11:06:57.070021 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 11:06:57.077028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 11:06:57.077603 ==
6570 11:06:57.078040
6571 11:06:57.078455
6572 11:06:57.078862 TX Vref Scan disable
6573 11:06:57.080076 == TX Byte 0 ==
6574 11:06:57.083611 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6575 11:06:57.086552 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6576 11:06:57.089990 == TX Byte 1 ==
6577 11:06:57.093610 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6578 11:06:57.097111 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6579 11:06:57.097673
6580 11:06:57.100159 [DATLAT]
6581 11:06:57.100677 Freq=400, CH0 RK1
6582 11:06:57.101032
6583 11:06:57.103317 DATLAT Default: 0xe
6584 11:06:57.103740 0, 0xFFFF, sum = 0
6585 11:06:57.106491 1, 0xFFFF, sum = 0
6586 11:06:57.106923 2, 0xFFFF, sum = 0
6587 11:06:57.110008 3, 0xFFFF, sum = 0
6588 11:06:57.110475 4, 0xFFFF, sum = 0
6589 11:06:57.113746 5, 0xFFFF, sum = 0
6590 11:06:57.114261 6, 0xFFFF, sum = 0
6591 11:06:57.116392 7, 0xFFFF, sum = 0
6592 11:06:57.116826 8, 0xFFFF, sum = 0
6593 11:06:57.119935 9, 0xFFFF, sum = 0
6594 11:06:57.120364 10, 0xFFFF, sum = 0
6595 11:06:57.123463 11, 0xFFFF, sum = 0
6596 11:06:57.126759 12, 0xFFFF, sum = 0
6597 11:06:57.127277 13, 0x0, sum = 1
6598 11:06:57.127614 14, 0x0, sum = 2
6599 11:06:57.129992 15, 0x0, sum = 3
6600 11:06:57.130500 16, 0x0, sum = 4
6601 11:06:57.133560 best_step = 14
6602 11:06:57.134059
6603 11:06:57.134389 ==
6604 11:06:57.136680 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 11:06:57.139813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 11:06:57.140257 ==
6607 11:06:57.143509 RX Vref Scan: 0
6608 11:06:57.144011
6609 11:06:57.144339 RX Vref 0 -> 0, step: 1
6610 11:06:57.144641
6611 11:06:57.146492 RX Delay -311 -> 252, step: 8
6612 11:06:57.154772 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6613 11:06:57.158140 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6614 11:06:57.161831 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6615 11:06:57.164922 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6616 11:06:57.171809 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6617 11:06:57.174967 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6618 11:06:57.178119 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6619 11:06:57.181624 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6620 11:06:57.188028 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6621 11:06:57.191307 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6622 11:06:57.194696 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6623 11:06:57.197990 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6624 11:06:57.204575 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6625 11:06:57.207899 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6626 11:06:57.210999 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6627 11:06:57.217724 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6628 11:06:57.218227 ==
6629 11:06:57.220909 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 11:06:57.224581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 11:06:57.225085 ==
6632 11:06:57.225477 DQS Delay:
6633 11:06:57.228013 DQS0 = 28, DQS1 = 44
6634 11:06:57.228519 DQM Delay:
6635 11:06:57.231011 DQM0 = 9, DQM1 = 15
6636 11:06:57.231444 DQ Delay:
6637 11:06:57.234880 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6638 11:06:57.237775 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6639 11:06:57.241219 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6640 11:06:57.244293 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =28
6641 11:06:57.244797
6642 11:06:57.245162
6643 11:06:57.250836 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6644 11:06:57.254235 CH0 RK1: MR19=C0C, MR18=BF71
6645 11:06:57.261027 CH0_RK1: MR19=0xC0C, MR18=0xBF71, DQSOSC=386, MR23=63, INC=396, DEC=264
6646 11:06:57.264298 [RxdqsGatingPostProcess] freq 400
6647 11:06:57.271595 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6648 11:06:57.272104 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 11:06:57.274751 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 11:06:57.278283 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 11:06:57.280847 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 11:06:57.284535 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 11:06:57.287956 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 11:06:57.291339 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 11:06:57.294836 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 11:06:57.298065 Pre-setting of DQS Precalculation
6657 11:06:57.301617 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6658 11:06:57.304312 ==
6659 11:06:57.304743 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 11:06:57.311330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 11:06:57.311821 ==
6662 11:06:57.314630 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 11:06:57.321013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6664 11:06:57.324324 [CA 0] Center 36 (8~64) winsize 57
6665 11:06:57.327855 [CA 1] Center 36 (8~64) winsize 57
6666 11:06:57.331084 [CA 2] Center 36 (8~64) winsize 57
6667 11:06:57.334476 [CA 3] Center 36 (8~64) winsize 57
6668 11:06:57.337985 [CA 4] Center 36 (8~64) winsize 57
6669 11:06:57.340996 [CA 5] Center 36 (8~64) winsize 57
6670 11:06:57.341514
6671 11:06:57.344347 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6672 11:06:57.345057
6673 11:06:57.347843 [CATrainingPosCal] consider 1 rank data
6674 11:06:57.351073 u2DelayCellTimex100 = 270/100 ps
6675 11:06:57.354588 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:06:57.357809 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 11:06:57.361241 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:06:57.364467 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:06:57.367850 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:06:57.371573 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 11:06:57.372080
6682 11:06:57.377863 CA PerBit enable=1, Macro0, CA PI delay=36
6683 11:06:57.378368
6684 11:06:57.381612 [CBTSetCACLKResult] CA Dly = 36
6685 11:06:57.382117 CS Dly: 1 (0~32)
6686 11:06:57.382451 ==
6687 11:06:57.384804 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 11:06:57.388161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 11:06:57.388672 ==
6690 11:06:57.394953 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 11:06:57.401718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6692 11:06:57.404635 [CA 0] Center 36 (8~64) winsize 57
6693 11:06:57.408009 [CA 1] Center 36 (8~64) winsize 57
6694 11:06:57.411810 [CA 2] Center 36 (8~64) winsize 57
6695 11:06:57.414897 [CA 3] Center 36 (8~64) winsize 57
6696 11:06:57.418033 [CA 4] Center 36 (8~64) winsize 57
6697 11:06:57.418538 [CA 5] Center 36 (8~64) winsize 57
6698 11:06:57.418871
6699 11:06:57.424353 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6700 11:06:57.424779
6701 11:06:57.427848 [CATrainingPosCal] consider 2 rank data
6702 11:06:57.431531 u2DelayCellTimex100 = 270/100 ps
6703 11:06:57.434944 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:06:57.437829 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:06:57.441468 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:06:57.444829 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:06:57.448253 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:06:57.451394 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:06:57.451819
6710 11:06:57.455053 CA PerBit enable=1, Macro0, CA PI delay=36
6711 11:06:57.455559
6712 11:06:57.457715 [CBTSetCACLKResult] CA Dly = 36
6713 11:06:57.461309 CS Dly: 1 (0~32)
6714 11:06:57.461807
6715 11:06:57.464479 ----->DramcWriteLeveling(PI) begin...
6716 11:06:57.464925 ==
6717 11:06:57.467853 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 11:06:57.471160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 11:06:57.471589 ==
6720 11:06:57.474701 Write leveling (Byte 0): 40 => 8
6721 11:06:57.477772 Write leveling (Byte 1): 32 => 0
6722 11:06:57.481288 DramcWriteLeveling(PI) end<-----
6723 11:06:57.481792
6724 11:06:57.482123 ==
6725 11:06:57.484595 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 11:06:57.487962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 11:06:57.488473 ==
6728 11:06:57.491125 [Gating] SW mode calibration
6729 11:06:57.497706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6730 11:06:57.504684 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6731 11:06:57.507929 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 11:06:57.511234 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 11:06:57.517670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 11:06:57.521274 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 11:06:57.524703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 11:06:57.531523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 11:06:57.534680 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 11:06:57.538039 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 11:06:57.545010 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 11:06:57.545577 Total UI for P1: 0, mck2ui 16
6741 11:06:57.548369 best dqsien dly found for B0: ( 0, 14, 24)
6742 11:06:57.551439 Total UI for P1: 0, mck2ui 16
6743 11:06:57.554643 best dqsien dly found for B1: ( 0, 14, 24)
6744 11:06:57.561371 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6745 11:06:57.564782 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6746 11:06:57.565332
6747 11:06:57.568236 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 11:06:57.571442 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 11:06:57.574840 [Gating] SW calibration Done
6750 11:06:57.575266 ==
6751 11:06:57.578092 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 11:06:57.581086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 11:06:57.581598 ==
6754 11:06:57.584585 RX Vref Scan: 0
6755 11:06:57.585091
6756 11:06:57.585480 RX Vref 0 -> 0, step: 1
6757 11:06:57.585784
6758 11:06:57.587821 RX Delay -410 -> 252, step: 16
6759 11:06:57.591418 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6760 11:06:57.598121 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6761 11:06:57.601251 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6762 11:06:57.604315 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6763 11:06:57.608008 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6764 11:06:57.614258 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6765 11:06:57.617769 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6766 11:06:57.620974 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6767 11:06:57.624364 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6768 11:06:57.631329 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6769 11:06:57.634678 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6770 11:06:57.637802 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6771 11:06:57.644365 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6772 11:06:57.647687 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6773 11:06:57.651126 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6774 11:06:57.653856 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6775 11:06:57.654347 ==
6776 11:06:57.657863 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 11:06:57.664250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 11:06:57.664762 ==
6779 11:06:57.665098 DQS Delay:
6780 11:06:57.667697 DQS0 = 27, DQS1 = 35
6781 11:06:57.668209 DQM Delay:
6782 11:06:57.668539 DQM0 = 4, DQM1 = 7
6783 11:06:57.671402 DQ Delay:
6784 11:06:57.674156 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6785 11:06:57.674667 DQ4 =0, DQ5 =8, DQ6 =16, DQ7 =0
6786 11:06:57.677491 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6787 11:06:57.680467 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =8
6788 11:06:57.680891
6789 11:06:57.681253
6790 11:06:57.681561 ==
6791 11:06:57.684468 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 11:06:57.690714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 11:06:57.691227 ==
6794 11:06:57.691561
6795 11:06:57.691863
6796 11:06:57.693854 TX Vref Scan disable
6797 11:06:57.694280 == TX Byte 0 ==
6798 11:06:57.697274 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 11:06:57.700928 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 11:06:57.703850 == TX Byte 1 ==
6801 11:06:57.707526 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6802 11:06:57.714103 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6803 11:06:57.714612 ==
6804 11:06:57.717582 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 11:06:57.720967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 11:06:57.721540 ==
6807 11:06:57.721877
6808 11:06:57.722181
6809 11:06:57.723718 TX Vref Scan disable
6810 11:06:57.724160 == TX Byte 0 ==
6811 11:06:57.727348 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 11:06:57.733862 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 11:06:57.734373 == TX Byte 1 ==
6814 11:06:57.737185 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6815 11:06:57.743822 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6816 11:06:57.744248
6817 11:06:57.744577 [DATLAT]
6818 11:06:57.744879 Freq=400, CH1 RK0
6819 11:06:57.745225
6820 11:06:57.747371 DATLAT Default: 0xf
6821 11:06:57.747799 0, 0xFFFF, sum = 0
6822 11:06:57.750580 1, 0xFFFF, sum = 0
6823 11:06:57.753705 2, 0xFFFF, sum = 0
6824 11:06:57.754148 3, 0xFFFF, sum = 0
6825 11:06:57.757475 4, 0xFFFF, sum = 0
6826 11:06:57.758068 5, 0xFFFF, sum = 0
6827 11:06:57.760556 6, 0xFFFF, sum = 0
6828 11:06:57.760984 7, 0xFFFF, sum = 0
6829 11:06:57.764203 8, 0xFFFF, sum = 0
6830 11:06:57.764716 9, 0xFFFF, sum = 0
6831 11:06:57.767601 10, 0xFFFF, sum = 0
6832 11:06:57.768114 11, 0xFFFF, sum = 0
6833 11:06:57.770442 12, 0xFFFF, sum = 0
6834 11:06:57.770876 13, 0x0, sum = 1
6835 11:06:57.774053 14, 0x0, sum = 2
6836 11:06:57.774567 15, 0x0, sum = 3
6837 11:06:57.777588 16, 0x0, sum = 4
6838 11:06:57.778103 best_step = 14
6839 11:06:57.778434
6840 11:06:57.778735 ==
6841 11:06:57.780501 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 11:06:57.784559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 11:06:57.787429 ==
6844 11:06:57.787932 RX Vref Scan: 1
6845 11:06:57.788263
6846 11:06:57.790312 RX Vref 0 -> 0, step: 1
6847 11:06:57.790738
6848 11:06:57.794074 RX Delay -311 -> 252, step: 8
6849 11:06:57.794577
6850 11:06:57.797274 Set Vref, RX VrefLevel [Byte0]: 53
6851 11:06:57.797786 [Byte1]: 52
6852 11:06:57.802686
6853 11:06:57.803186 Final RX Vref Byte 0 = 53 to rank0
6854 11:06:57.805944 Final RX Vref Byte 1 = 52 to rank0
6855 11:06:57.809578 Final RX Vref Byte 0 = 53 to rank1
6856 11:06:57.812711 Final RX Vref Byte 1 = 52 to rank1==
6857 11:06:57.816165 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 11:06:57.822478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 11:06:57.822977 ==
6860 11:06:57.823320 DQS Delay:
6861 11:06:57.825949 DQS0 = 28, DQS1 = 40
6862 11:06:57.826374 DQM Delay:
6863 11:06:57.826705 DQM0 = 8, DQM1 = 13
6864 11:06:57.829561 DQ Delay:
6865 11:06:57.832529 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6866 11:06:57.833026 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6867 11:06:57.836304 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6868 11:06:57.839021 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6869 11:06:57.839445
6870 11:06:57.839767
6871 11:06:57.849170 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1db, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 389 ps
6872 11:06:57.852809 CH1 RK0: MR19=C0C, MR18=A1DB
6873 11:06:57.859175 CH1_RK0: MR19=0xC0C, MR18=0xA1DB, DQSOSC=382, MR23=63, INC=404, DEC=269
6874 11:06:57.859707 ==
6875 11:06:57.862345 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 11:06:57.865575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 11:06:57.866001 ==
6878 11:06:57.869040 [Gating] SW mode calibration
6879 11:06:57.875797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6880 11:06:57.882190 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6881 11:06:57.886162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 11:06:57.889090 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 11:06:57.892045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 11:06:57.898852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 11:06:57.902221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 11:06:57.905522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 11:06:57.912212 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 11:06:57.915528 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 11:06:57.918679 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 11:06:57.922175 Total UI for P1: 0, mck2ui 16
6891 11:06:57.925499 best dqsien dly found for B0: ( 0, 14, 24)
6892 11:06:57.928744 Total UI for P1: 0, mck2ui 16
6893 11:06:57.932371 best dqsien dly found for B1: ( 0, 14, 24)
6894 11:06:57.935507 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6895 11:06:57.938853 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6896 11:06:57.942166
6897 11:06:57.945215 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 11:06:57.949039 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 11:06:57.952257 [Gating] SW calibration Done
6900 11:06:57.952767 ==
6901 11:06:57.955569 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 11:06:57.958799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 11:06:57.959240 ==
6904 11:06:57.959579 RX Vref Scan: 0
6905 11:06:57.959882
6906 11:06:57.961803 RX Vref 0 -> 0, step: 1
6907 11:06:57.962226
6908 11:06:57.965394 RX Delay -410 -> 252, step: 16
6909 11:06:57.968812 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6910 11:06:57.975520 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6911 11:06:57.978638 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6912 11:06:57.981931 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6913 11:06:57.985213 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6914 11:06:57.992174 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6915 11:06:57.995470 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6916 11:06:57.998889 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6917 11:06:58.002334 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6918 11:06:58.008682 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6919 11:06:58.011703 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6920 11:06:58.015479 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6921 11:06:58.018603 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6922 11:06:58.025034 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6923 11:06:58.028949 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6924 11:06:58.031771 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6925 11:06:58.032208 ==
6926 11:06:58.035409 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 11:06:58.038739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 11:06:58.042094 ==
6929 11:06:58.042609 DQS Delay:
6930 11:06:58.042944 DQS0 = 35, DQS1 = 43
6931 11:06:58.045412 DQM Delay:
6932 11:06:58.045926 DQM0 = 17, DQM1 = 19
6933 11:06:58.048557 DQ Delay:
6934 11:06:58.049063 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6935 11:06:58.051888 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6936 11:06:58.055555 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6937 11:06:58.058542 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6938 11:06:58.059049
6939 11:06:58.059388
6940 11:06:58.061811 ==
6941 11:06:58.065429 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 11:06:58.068824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 11:06:58.069376 ==
6944 11:06:58.069716
6945 11:06:58.070033
6946 11:06:58.072063 TX Vref Scan disable
6947 11:06:58.072575 == TX Byte 0 ==
6948 11:06:58.075101 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6949 11:06:58.082007 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6950 11:06:58.082439 == TX Byte 1 ==
6951 11:06:58.085082 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6952 11:06:58.088476 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6953 11:06:58.092267 ==
6954 11:06:58.095488 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 11:06:58.098793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 11:06:58.099308 ==
6957 11:06:58.099639
6958 11:06:58.099943
6959 11:06:58.101971 TX Vref Scan disable
6960 11:06:58.102527 == TX Byte 0 ==
6961 11:06:58.105388 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6962 11:06:58.111924 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6963 11:06:58.112435 == TX Byte 1 ==
6964 11:06:58.115692 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6965 11:06:58.118914 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6966 11:06:58.121775
6967 11:06:58.122205 [DATLAT]
6968 11:06:58.122537 Freq=400, CH1 RK1
6969 11:06:58.122845
6970 11:06:58.125394 DATLAT Default: 0xe
6971 11:06:58.125901 0, 0xFFFF, sum = 0
6972 11:06:58.128543 1, 0xFFFF, sum = 0
6973 11:06:58.128979 2, 0xFFFF, sum = 0
6974 11:06:58.132055 3, 0xFFFF, sum = 0
6975 11:06:58.132569 4, 0xFFFF, sum = 0
6976 11:06:58.135256 5, 0xFFFF, sum = 0
6977 11:06:58.135773 6, 0xFFFF, sum = 0
6978 11:06:58.138546 7, 0xFFFF, sum = 0
6979 11:06:58.142280 8, 0xFFFF, sum = 0
6980 11:06:58.142800 9, 0xFFFF, sum = 0
6981 11:06:58.145235 10, 0xFFFF, sum = 0
6982 11:06:58.145762 11, 0xFFFF, sum = 0
6983 11:06:58.148527 12, 0xFFFF, sum = 0
6984 11:06:58.148957 13, 0x0, sum = 1
6985 11:06:58.152186 14, 0x0, sum = 2
6986 11:06:58.152744 15, 0x0, sum = 3
6987 11:06:58.155443 16, 0x0, sum = 4
6988 11:06:58.155969 best_step = 14
6989 11:06:58.156306
6990 11:06:58.156610 ==
6991 11:06:58.158643 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 11:06:58.161716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 11:06:58.162148 ==
6994 11:06:58.165517 RX Vref Scan: 0
6995 11:06:58.166026
6996 11:06:58.168844 RX Vref 0 -> 0, step: 1
6997 11:06:58.169385
6998 11:06:58.169716 RX Delay -327 -> 252, step: 8
6999 11:06:58.177521 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7000 11:06:58.180313 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7001 11:06:58.183633 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7002 11:06:58.187364 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
7003 11:06:58.194048 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7004 11:06:58.197181 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7005 11:06:58.200564 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7006 11:06:58.203605 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7007 11:06:58.210884 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7008 11:06:58.213770 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7009 11:06:58.217437 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7010 11:06:58.220476 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7011 11:06:58.227239 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7012 11:06:58.230644 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7013 11:06:58.233864 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7014 11:06:58.240844 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7015 11:06:58.241403 ==
7016 11:06:58.243817 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 11:06:58.247220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 11:06:58.247735 ==
7019 11:06:58.248076 DQS Delay:
7020 11:06:58.250523 DQS0 = 32, DQS1 = 36
7021 11:06:58.251029 DQM Delay:
7022 11:06:58.254025 DQM0 = 12, DQM1 = 11
7023 11:06:58.254537 DQ Delay:
7024 11:06:58.257104 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
7025 11:06:58.260488 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
7026 11:06:58.263793 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7027 11:06:58.267005 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7028 11:06:58.267518
7029 11:06:58.267852
7030 11:06:58.273683 [DQSOSCAuto] RK1, (LSB)MR18= 0xae57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
7031 11:06:58.277194 CH1 RK1: MR19=C0C, MR18=AE57
7032 11:06:58.283737 CH1_RK1: MR19=0xC0C, MR18=0xAE57, DQSOSC=388, MR23=63, INC=392, DEC=261
7033 11:06:58.287278 [RxdqsGatingPostProcess] freq 400
7034 11:06:58.293385 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7035 11:06:58.293896 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 11:06:58.296734 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 11:06:58.300841 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 11:06:58.303758 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 11:06:58.306973 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 11:06:58.310577 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 11:06:58.313742 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 11:06:58.317045 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 11:06:58.320271 Pre-setting of DQS Precalculation
7044 11:06:58.323760 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7045 11:06:58.333555 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7046 11:06:58.340497 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7047 11:06:58.341009
7048 11:06:58.341386
7049 11:06:58.343324 [Calibration Summary] 800 Mbps
7050 11:06:58.343754 CH 0, Rank 0
7051 11:06:58.346656 SW Impedance : PASS
7052 11:06:58.347086 DUTY Scan : NO K
7053 11:06:58.349999 ZQ Calibration : PASS
7054 11:06:58.353578 Jitter Meter : NO K
7055 11:06:58.354087 CBT Training : PASS
7056 11:06:58.356513 Write leveling : PASS
7057 11:06:58.359918 RX DQS gating : PASS
7058 11:06:58.360348 RX DQ/DQS(RDDQC) : PASS
7059 11:06:58.363549 TX DQ/DQS : PASS
7060 11:06:58.366928 RX DATLAT : PASS
7061 11:06:58.367361 RX DQ/DQS(Engine): PASS
7062 11:06:58.369990 TX OE : NO K
7063 11:06:58.370421 All Pass.
7064 11:06:58.370832
7065 11:06:58.373454 CH 0, Rank 1
7066 11:06:58.373885 SW Impedance : PASS
7067 11:06:58.376594 DUTY Scan : NO K
7068 11:06:58.377025 ZQ Calibration : PASS
7069 11:06:58.379993 Jitter Meter : NO K
7070 11:06:58.383270 CBT Training : PASS
7071 11:06:58.383870 Write leveling : NO K
7072 11:06:58.386632 RX DQS gating : PASS
7073 11:06:58.390057 RX DQ/DQS(RDDQC) : PASS
7074 11:06:58.390459 TX DQ/DQS : PASS
7075 11:06:58.393555 RX DATLAT : PASS
7076 11:06:58.396582 RX DQ/DQS(Engine): PASS
7077 11:06:58.397000 TX OE : NO K
7078 11:06:58.399966 All Pass.
7079 11:06:58.400368
7080 11:06:58.400766 CH 1, Rank 0
7081 11:06:58.403712 SW Impedance : PASS
7082 11:06:58.404114 DUTY Scan : NO K
7083 11:06:58.406474 ZQ Calibration : PASS
7084 11:06:58.409775 Jitter Meter : NO K
7085 11:06:58.410184 CBT Training : PASS
7086 11:06:58.413161 Write leveling : PASS
7087 11:06:58.416918 RX DQS gating : PASS
7088 11:06:58.417531 RX DQ/DQS(RDDQC) : PASS
7089 11:06:58.419991 TX DQ/DQS : PASS
7090 11:06:58.423061 RX DATLAT : PASS
7091 11:06:58.423619 RX DQ/DQS(Engine): PASS
7092 11:06:58.426971 TX OE : NO K
7093 11:06:58.427611 All Pass.
7094 11:06:58.428528
7095 11:06:58.430022 CH 1, Rank 1
7096 11:06:58.430411 SW Impedance : PASS
7097 11:06:58.433050 DUTY Scan : NO K
7098 11:06:58.433473 ZQ Calibration : PASS
7099 11:06:58.436532 Jitter Meter : NO K
7100 11:06:58.439931 CBT Training : PASS
7101 11:06:58.440331 Write leveling : NO K
7102 11:06:58.443352 RX DQS gating : PASS
7103 11:06:58.446451 RX DQ/DQS(RDDQC) : PASS
7104 11:06:58.447094 TX DQ/DQS : PASS
7105 11:06:58.449902 RX DATLAT : PASS
7106 11:06:58.453051 RX DQ/DQS(Engine): PASS
7107 11:06:58.453504 TX OE : NO K
7108 11:06:58.456700 All Pass.
7109 11:06:58.457086
7110 11:06:58.457428 DramC Write-DBI off
7111 11:06:58.459903 PER_BANK_REFRESH: Hybrid Mode
7112 11:06:58.460291 TX_TRACKING: ON
7113 11:06:58.470015 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7114 11:06:58.472966 [FAST_K] Save calibration result to emmc
7115 11:06:58.476573 dramc_set_vcore_voltage set vcore to 725000
7116 11:06:58.480189 Read voltage for 1600, 0
7117 11:06:58.480687 Vio18 = 0
7118 11:06:58.483503 Vcore = 725000
7119 11:06:58.484005 Vdram = 0
7120 11:06:58.484335 Vddq = 0
7121 11:06:58.486562 Vmddr = 0
7122 11:06:58.489715 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7123 11:06:58.496439 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7124 11:06:58.496933 MEM_TYPE=3, freq_sel=13
7125 11:06:58.499662 sv_algorithm_assistance_LP4_3733
7126 11:06:58.506279 ============ PULL DRAM RESETB DOWN ============
7127 11:06:58.509614 ========== PULL DRAM RESETB DOWN end =========
7128 11:06:58.512592 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7129 11:06:58.516248 ===================================
7130 11:06:58.519474 LPDDR4 DRAM CONFIGURATION
7131 11:06:58.523149 ===================================
7132 11:06:58.523574 EX_ROW_EN[0] = 0x0
7133 11:06:58.525957 EX_ROW_EN[1] = 0x0
7134 11:06:58.529284 LP4Y_EN = 0x0
7135 11:06:58.529712 WORK_FSP = 0x1
7136 11:06:58.532319 WL = 0x5
7137 11:06:58.532619 RL = 0x5
7138 11:06:58.535897 BL = 0x2
7139 11:06:58.536272 RPST = 0x0
7140 11:06:58.539476 RD_PRE = 0x0
7141 11:06:58.539857 WR_PRE = 0x1
7142 11:06:58.542716 WR_PST = 0x1
7143 11:06:58.543017 DBI_WR = 0x0
7144 11:06:58.545712 DBI_RD = 0x0
7145 11:06:58.546015 OTF = 0x1
7146 11:06:58.549463 ===================================
7147 11:06:58.552651 ===================================
7148 11:06:58.556378 ANA top config
7149 11:06:58.559347 ===================================
7150 11:06:58.559719 DLL_ASYNC_EN = 0
7151 11:06:58.562667 ALL_SLAVE_EN = 0
7152 11:06:58.566129 NEW_RANK_MODE = 1
7153 11:06:58.569616 DLL_IDLE_MODE = 1
7154 11:06:58.572502 LP45_APHY_COMB_EN = 1
7155 11:06:58.572933 TX_ODT_DIS = 0
7156 11:06:58.576585 NEW_8X_MODE = 1
7157 11:06:58.579446 ===================================
7158 11:06:58.582227 ===================================
7159 11:06:58.586047 data_rate = 3200
7160 11:06:58.588960 CKR = 1
7161 11:06:58.592720 DQ_P2S_RATIO = 8
7162 11:06:58.595710 ===================================
7163 11:06:58.599221 CA_P2S_RATIO = 8
7164 11:06:58.599720 DQ_CA_OPEN = 0
7165 11:06:58.602277 DQ_SEMI_OPEN = 0
7166 11:06:58.605782 CA_SEMI_OPEN = 0
7167 11:06:58.608919 CA_FULL_RATE = 0
7168 11:06:58.612332 DQ_CKDIV4_EN = 0
7169 11:06:58.615639 CA_CKDIV4_EN = 0
7170 11:06:58.616143 CA_PREDIV_EN = 0
7171 11:06:58.619312 PH8_DLY = 12
7172 11:06:58.622615 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7173 11:06:58.625392 DQ_AAMCK_DIV = 4
7174 11:06:58.629238 CA_AAMCK_DIV = 4
7175 11:06:58.632125 CA_ADMCK_DIV = 4
7176 11:06:58.632629 DQ_TRACK_CA_EN = 0
7177 11:06:58.635665 CA_PICK = 1600
7178 11:06:58.638964 CA_MCKIO = 1600
7179 11:06:58.642211 MCKIO_SEMI = 0
7180 11:06:58.645115 PLL_FREQ = 3068
7181 11:06:58.648783 DQ_UI_PI_RATIO = 32
7182 11:06:58.652413 CA_UI_PI_RATIO = 0
7183 11:06:58.655721 ===================================
7184 11:06:58.659028 ===================================
7185 11:06:58.659536 memory_type:LPDDR4
7186 11:06:58.661909 GP_NUM : 10
7187 11:06:58.665453 SRAM_EN : 1
7188 11:06:58.665879 MD32_EN : 0
7189 11:06:58.668962 ===================================
7190 11:06:58.672110 [ANA_INIT] >>>>>>>>>>>>>>
7191 11:06:58.675479 <<<<<< [CONFIGURE PHASE]: ANA_TX
7192 11:06:58.678728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7193 11:06:58.681882 ===================================
7194 11:06:58.686274 data_rate = 3200,PCW = 0X7600
7195 11:06:58.686771 ===================================
7196 11:06:58.691929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7197 11:06:58.695509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 11:06:58.701973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 11:06:58.705469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7200 11:06:58.708624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7201 11:06:58.712462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7202 11:06:58.715920 [ANA_INIT] flow start
7203 11:06:58.719293 [ANA_INIT] PLL >>>>>>>>
7204 11:06:58.719794 [ANA_INIT] PLL <<<<<<<<
7205 11:06:58.721982 [ANA_INIT] MIDPI >>>>>>>>
7206 11:06:58.725616 [ANA_INIT] MIDPI <<<<<<<<
7207 11:06:58.726135 [ANA_INIT] DLL >>>>>>>>
7208 11:06:58.729073 [ANA_INIT] DLL <<<<<<<<
7209 11:06:58.732243 [ANA_INIT] flow end
7210 11:06:58.735500 ============ LP4 DIFF to SE enter ============
7211 11:06:58.738851 ============ LP4 DIFF to SE exit ============
7212 11:06:58.742119 [ANA_INIT] <<<<<<<<<<<<<
7213 11:06:58.745337 [Flow] Enable top DCM control >>>>>
7214 11:06:58.748696 [Flow] Enable top DCM control <<<<<
7215 11:06:58.752283 Enable DLL master slave shuffle
7216 11:06:58.755192 ==============================================================
7217 11:06:58.759277 Gating Mode config
7218 11:06:58.765295 ==============================================================
7219 11:06:58.765866 Config description:
7220 11:06:58.775576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7221 11:06:58.782300 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7222 11:06:58.785688 SELPH_MODE 0: By rank 1: By Phase
7223 11:06:58.792610 ==============================================================
7224 11:06:58.795426 GAT_TRACK_EN = 1
7225 11:06:58.798904 RX_GATING_MODE = 2
7226 11:06:58.802528 RX_GATING_TRACK_MODE = 2
7227 11:06:58.805327 SELPH_MODE = 1
7228 11:06:58.808908 PICG_EARLY_EN = 1
7229 11:06:58.809467 VALID_LAT_VALUE = 1
7230 11:06:58.815957 ==============================================================
7231 11:06:58.818998 Enter into Gating configuration >>>>
7232 11:06:58.821992 Exit from Gating configuration <<<<
7233 11:06:58.825559 Enter into DVFS_PRE_config >>>>>
7234 11:06:58.835835 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7235 11:06:58.839439 Exit from DVFS_PRE_config <<<<<
7236 11:06:58.842740 Enter into PICG configuration >>>>
7237 11:06:58.845576 Exit from PICG configuration <<<<
7238 11:06:58.849067 [RX_INPUT] configuration >>>>>
7239 11:06:58.852531 [RX_INPUT] configuration <<<<<
7240 11:06:58.855124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7241 11:06:58.862218 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7242 11:06:58.868883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7243 11:06:58.875745 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7244 11:06:58.882102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 11:06:58.888632 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 11:06:58.892374 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7247 11:06:58.895832 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7248 11:06:58.899126 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7249 11:06:58.902054 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7250 11:06:58.908568 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7251 11:06:58.912217 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 11:06:58.915634 ===================================
7253 11:06:58.918940 LPDDR4 DRAM CONFIGURATION
7254 11:06:58.922193 ===================================
7255 11:06:58.922701 EX_ROW_EN[0] = 0x0
7256 11:06:58.925751 EX_ROW_EN[1] = 0x0
7257 11:06:58.926321 LP4Y_EN = 0x0
7258 11:06:58.929285 WORK_FSP = 0x1
7259 11:06:58.929793 WL = 0x5
7260 11:06:58.932587 RL = 0x5
7261 11:06:58.933092 BL = 0x2
7262 11:06:58.935573 RPST = 0x0
7263 11:06:58.936078 RD_PRE = 0x0
7264 11:06:58.938943 WR_PRE = 0x1
7265 11:06:58.939451 WR_PST = 0x1
7266 11:06:58.942100 DBI_WR = 0x0
7267 11:06:58.945615 DBI_RD = 0x0
7268 11:06:58.946133 OTF = 0x1
7269 11:06:58.948921 ===================================
7270 11:06:58.952310 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7271 11:06:58.955353 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7272 11:06:58.962316 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 11:06:58.965337 ===================================
7274 11:06:58.965762 LPDDR4 DRAM CONFIGURATION
7275 11:06:58.968599 ===================================
7276 11:06:58.972213 EX_ROW_EN[0] = 0x10
7277 11:06:58.975548 EX_ROW_EN[1] = 0x0
7278 11:06:58.976077 LP4Y_EN = 0x0
7279 11:06:58.979049 WORK_FSP = 0x1
7280 11:06:58.979472 WL = 0x5
7281 11:06:58.982077 RL = 0x5
7282 11:06:58.982780 BL = 0x2
7283 11:06:58.985197 RPST = 0x0
7284 11:06:58.985620 RD_PRE = 0x0
7285 11:06:58.988768 WR_PRE = 0x1
7286 11:06:58.989313 WR_PST = 0x1
7287 11:06:58.991912 DBI_WR = 0x0
7288 11:06:58.992406 DBI_RD = 0x0
7289 11:06:58.995511 OTF = 0x1
7290 11:06:58.998392 ===================================
7291 11:06:59.005366 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7292 11:06:59.005871 ==
7293 11:06:59.008346 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 11:06:59.011888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 11:06:59.012322 ==
7296 11:06:59.015410 [Duty_Offset_Calibration]
7297 11:06:59.015913 B0:2 B1:0 CA:1
7298 11:06:59.016245
7299 11:06:59.018736 [DutyScan_Calibration_Flow] k_type=0
7300 11:06:59.029720
7301 11:06:59.030223 ==CLK 0==
7302 11:06:59.033090 Final CLK duty delay cell = 0
7303 11:06:59.036301 [0] MAX Duty = 5187%(X100), DQS PI = 20
7304 11:06:59.039620 [0] MIN Duty = 5031%(X100), DQS PI = 0
7305 11:06:59.040128 [0] AVG Duty = 5109%(X100)
7306 11:06:59.042773
7307 11:06:59.045756 CH0 CLK Duty spec in!! Max-Min= 156%
7308 11:06:59.049826 [DutyScan_Calibration_Flow] ====Done====
7309 11:06:59.050362
7310 11:06:59.052470 [DutyScan_Calibration_Flow] k_type=1
7311 11:06:59.068573
7312 11:06:59.069076 ==DQS 0 ==
7313 11:06:59.072030 Final DQS duty delay cell = 0
7314 11:06:59.075505 [0] MAX Duty = 5218%(X100), DQS PI = 32
7315 11:06:59.078156 [0] MIN Duty = 4969%(X100), DQS PI = 0
7316 11:06:59.078592 [0] AVG Duty = 5093%(X100)
7317 11:06:59.082010
7318 11:06:59.082546 ==DQS 1 ==
7319 11:06:59.084863 Final DQS duty delay cell = -4
7320 11:06:59.088477 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7321 11:06:59.091740 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7322 11:06:59.094912 [-4] AVG Duty = 4969%(X100)
7323 11:06:59.095349
7324 11:06:59.098384 CH0 DQS 0 Duty spec in!! Max-Min= 249%
7325 11:06:59.098890
7326 11:06:59.101731 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7327 11:06:59.104829 [DutyScan_Calibration_Flow] ====Done====
7328 11:06:59.105291
7329 11:06:59.108204 [DutyScan_Calibration_Flow] k_type=3
7330 11:06:59.126038
7331 11:06:59.126593 ==DQM 0 ==
7332 11:06:59.128963 Final DQM duty delay cell = 0
7333 11:06:59.132580 [0] MAX Duty = 5062%(X100), DQS PI = 26
7334 11:06:59.135677 [0] MIN Duty = 4813%(X100), DQS PI = 2
7335 11:06:59.136112 [0] AVG Duty = 4937%(X100)
7336 11:06:59.139225
7337 11:06:59.139736 ==DQM 1 ==
7338 11:06:59.142448 Final DQM duty delay cell = 0
7339 11:06:59.145945 [0] MAX Duty = 5249%(X100), DQS PI = 30
7340 11:06:59.149308 [0] MIN Duty = 5000%(X100), DQS PI = 20
7341 11:06:59.149813 [0] AVG Duty = 5124%(X100)
7342 11:06:59.152650
7343 11:06:59.156233 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7344 11:06:59.156744
7345 11:06:59.159109 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7346 11:06:59.162599 [DutyScan_Calibration_Flow] ====Done====
7347 11:06:59.163112
7348 11:06:59.165810 [DutyScan_Calibration_Flow] k_type=2
7349 11:06:59.182991
7350 11:06:59.183497 ==DQ 0 ==
7351 11:06:59.186540 Final DQ duty delay cell = 0
7352 11:06:59.189678 [0] MAX Duty = 5156%(X100), DQS PI = 36
7353 11:06:59.192800 [0] MIN Duty = 4969%(X100), DQS PI = 18
7354 11:06:59.193272 [0] AVG Duty = 5062%(X100)
7355 11:06:59.196342
7356 11:06:59.196988 ==DQ 1 ==
7357 11:06:59.199426 Final DQ duty delay cell = 0
7358 11:06:59.203128 [0] MAX Duty = 4969%(X100), DQS PI = 44
7359 11:06:59.206276 [0] MIN Duty = 4875%(X100), DQS PI = 10
7360 11:06:59.206783 [0] AVG Duty = 4922%(X100)
7361 11:06:59.207117
7362 11:06:59.209459 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7363 11:06:59.212887
7364 11:06:59.216421 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7365 11:06:59.219742 [DutyScan_Calibration_Flow] ====Done====
7366 11:06:59.220249 ==
7367 11:06:59.222792 Dram Type= 6, Freq= 0, CH_1, rank 0
7368 11:06:59.226107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7369 11:06:59.226618 ==
7370 11:06:59.229205 [Duty_Offset_Calibration]
7371 11:06:59.229640 B0:0 B1:-1 CA:2
7372 11:06:59.230060
7373 11:06:59.232697 [DutyScan_Calibration_Flow] k_type=0
7374 11:06:59.243139
7375 11:06:59.243567 ==CLK 0==
7376 11:06:59.246345 Final CLK duty delay cell = 0
7377 11:06:59.249971 [0] MAX Duty = 5156%(X100), DQS PI = 42
7378 11:06:59.253037 [0] MIN Duty = 4906%(X100), DQS PI = 12
7379 11:06:59.253476 [0] AVG Duty = 5031%(X100)
7380 11:06:59.256590
7381 11:06:59.259979 CH1 CLK Duty spec in!! Max-Min= 250%
7382 11:06:59.262798 [DutyScan_Calibration_Flow] ====Done====
7383 11:06:59.263189
7384 11:06:59.266540 [DutyScan_Calibration_Flow] k_type=1
7385 11:06:59.282850
7386 11:06:59.283401 ==DQS 0 ==
7387 11:06:59.286284 Final DQS duty delay cell = 0
7388 11:06:59.289668 [0] MAX Duty = 5062%(X100), DQS PI = 8
7389 11:06:59.292946 [0] MIN Duty = 4969%(X100), DQS PI = 50
7390 11:06:59.293489 [0] AVG Duty = 5015%(X100)
7391 11:06:59.296275
7392 11:06:59.296694 ==DQS 1 ==
7393 11:06:59.299925 Final DQS duty delay cell = 0
7394 11:06:59.302734 [0] MAX Duty = 5187%(X100), DQS PI = 26
7395 11:06:59.306104 [0] MIN Duty = 4844%(X100), DQS PI = 0
7396 11:06:59.306544 [0] AVG Duty = 5015%(X100)
7397 11:06:59.309807
7398 11:06:59.312744 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7399 11:06:59.313283
7400 11:06:59.316075 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7401 11:06:59.319893 [DutyScan_Calibration_Flow] ====Done====
7402 11:06:59.320400
7403 11:06:59.322576 [DutyScan_Calibration_Flow] k_type=3
7404 11:06:59.339695
7405 11:06:59.340225 ==DQM 0 ==
7406 11:06:59.342973 Final DQM duty delay cell = 4
7407 11:06:59.346275 [4] MAX Duty = 5125%(X100), DQS PI = 24
7408 11:06:59.349755 [4] MIN Duty = 4969%(X100), DQS PI = 0
7409 11:06:59.350250 [4] AVG Duty = 5047%(X100)
7410 11:06:59.353339
7411 11:06:59.353832 ==DQM 1 ==
7412 11:06:59.356510 Final DQM duty delay cell = -4
7413 11:06:59.359975 [-4] MAX Duty = 4938%(X100), DQS PI = 26
7414 11:06:59.362658 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7415 11:06:59.366579 [-4] AVG Duty = 4813%(X100)
7416 11:06:59.367284
7417 11:06:59.369623 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7418 11:06:59.370044
7419 11:06:59.373319 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7420 11:06:59.376039 [DutyScan_Calibration_Flow] ====Done====
7421 11:06:59.376460
7422 11:06:59.379510 [DutyScan_Calibration_Flow] k_type=2
7423 11:06:59.396836
7424 11:06:59.397385 ==DQ 0 ==
7425 11:06:59.400202 Final DQ duty delay cell = 0
7426 11:06:59.403808 [0] MAX Duty = 5093%(X100), DQS PI = 24
7427 11:06:59.406768 [0] MIN Duty = 4938%(X100), DQS PI = 0
7428 11:06:59.407272 [0] AVG Duty = 5015%(X100)
7429 11:06:59.407603
7430 11:06:59.410088 ==DQ 1 ==
7431 11:06:59.413302 Final DQ duty delay cell = 0
7432 11:06:59.416626 [0] MAX Duty = 5094%(X100), DQS PI = 34
7433 11:06:59.420044 [0] MIN Duty = 4813%(X100), DQS PI = 2
7434 11:06:59.420708 [0] AVG Duty = 4953%(X100)
7435 11:06:59.421059
7436 11:06:59.423682 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7437 11:06:59.424201
7438 11:06:59.429937 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7439 11:06:59.433212 [DutyScan_Calibration_Flow] ====Done====
7440 11:06:59.436643 nWR fixed to 30
7441 11:06:59.437195 [ModeRegInit_LP4] CH0 RK0
7442 11:06:59.440337 [ModeRegInit_LP4] CH0 RK1
7443 11:06:59.443375 [ModeRegInit_LP4] CH1 RK0
7444 11:06:59.443877 [ModeRegInit_LP4] CH1 RK1
7445 11:06:59.446296 match AC timing 5
7446 11:06:59.449893 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7447 11:06:59.453438 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7448 11:06:59.459534 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7449 11:06:59.462852 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7450 11:06:59.470054 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7451 11:06:59.470518 [MiockJmeterHQA]
7452 11:06:59.470850
7453 11:06:59.472857 [DramcMiockJmeter] u1RxGatingPI = 0
7454 11:06:59.476515 0 : 4257, 4029
7455 11:06:59.477291 4 : 4258, 4030
7456 11:06:59.477827 8 : 4252, 4027
7457 11:06:59.479653 12 : 4365, 4140
7458 11:06:59.480319 16 : 4363, 4138
7459 11:06:59.482897 20 : 4363, 4138
7460 11:06:59.483368 24 : 4253, 4026
7461 11:06:59.486447 28 : 4363, 4138
7462 11:06:59.486852 32 : 4363, 4137
7463 11:06:59.489746 36 : 4363, 4138
7464 11:06:59.490164 40 : 4252, 4027
7465 11:06:59.490555 44 : 4250, 4026
7466 11:06:59.492615 48 : 4250, 4027
7467 11:06:59.493030 52 : 4249, 4027
7468 11:06:59.496231 56 : 4250, 4027
7469 11:06:59.496629 60 : 4252, 4027
7470 11:06:59.499208 64 : 4250, 4026
7471 11:06:59.499612 68 : 4253, 4029
7472 11:06:59.502852 72 : 4252, 4029
7473 11:06:59.503337 76 : 4252, 4027
7474 11:06:59.503654 80 : 4360, 4138
7475 11:06:59.506345 84 : 4360, 4137
7476 11:06:59.506743 88 : 4250, 3785
7477 11:06:59.509390 92 : 4249, 0
7478 11:06:59.509807 96 : 4252, 0
7479 11:06:59.510117 100 : 4255, 0
7480 11:06:59.512960 104 : 4361, 0
7481 11:06:59.513412 108 : 4363, 0
7482 11:06:59.516209 112 : 4250, 0
7483 11:06:59.516603 116 : 4250, 0
7484 11:06:59.516913 120 : 4255, 0
7485 11:06:59.519992 124 : 4255, 0
7486 11:06:59.520485 128 : 4250, 0
7487 11:06:59.520799 132 : 4360, 0
7488 11:06:59.523137 136 : 4250, 0
7489 11:06:59.523617 140 : 4361, 0
7490 11:06:59.526437 144 : 4250, 0
7491 11:06:59.526920 148 : 4255, 0
7492 11:06:59.527236 152 : 4250, 0
7493 11:06:59.529850 156 : 4250, 0
7494 11:06:59.530249 160 : 4363, 0
7495 11:06:59.532922 164 : 4249, 0
7496 11:06:59.533470 168 : 4250, 0
7497 11:06:59.533790 172 : 4250, 0
7498 11:06:59.536090 176 : 4253, 0
7499 11:06:59.536486 180 : 4252, 0
7500 11:06:59.536808 184 : 4250, 0
7501 11:06:59.539803 188 : 4250, 0
7502 11:06:59.540284 192 : 4361, 0
7503 11:06:59.543143 196 : 4250, 0
7504 11:06:59.543643 200 : 4250, 2
7505 11:06:59.546070 204 : 4250, 2338
7506 11:06:59.546475 208 : 4255, 4032
7507 11:06:59.546833 212 : 4249, 4027
7508 11:06:59.549618 216 : 4250, 4027
7509 11:06:59.550019 220 : 4361, 4138
7510 11:06:59.553173 224 : 4250, 4027
7511 11:06:59.553669 228 : 4360, 4138
7512 11:06:59.556665 232 : 4250, 4027
7513 11:06:59.557186 236 : 4250, 4027
7514 11:06:59.559609 240 : 4250, 4027
7515 11:06:59.560008 244 : 4250, 4027
7516 11:06:59.562938 248 : 4250, 4027
7517 11:06:59.563420 252 : 4250, 4026
7518 11:06:59.566293 256 : 4250, 4027
7519 11:06:59.566779 260 : 4252, 4029
7520 11:06:59.567091 264 : 4250, 4027
7521 11:06:59.569502 268 : 4250, 4027
7522 11:06:59.569902 272 : 4361, 4137
7523 11:06:59.573056 276 : 4250, 4027
7524 11:06:59.573587 280 : 4361, 4137
7525 11:06:59.576113 284 : 4250, 4027
7526 11:06:59.576514 288 : 4250, 4027
7527 11:06:59.579231 292 : 4250, 4027
7528 11:06:59.579627 296 : 4250, 4027
7529 11:06:59.582511 300 : 4250, 4027
7530 11:06:59.582912 304 : 4255, 4029
7531 11:06:59.586300 308 : 4250, 4027
7532 11:06:59.586809 312 : 4252, 3954
7533 11:06:59.589633 316 : 4250, 1709
7534 11:06:59.590031
7535 11:06:59.590336 MIOCK jitter meter ch=0
7536 11:06:59.590618
7537 11:06:59.593080 1T = (316-92) = 224 dly cells
7538 11:06:59.599541 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7539 11:06:59.599937 ==
7540 11:06:59.603282 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 11:06:59.606600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 11:06:59.607076 ==
7543 11:06:59.612989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 11:06:59.616309 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 11:06:59.619888 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 11:06:59.626420 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 11:06:59.635648 [CA 0] Center 43 (13~73) winsize 61
7548 11:06:59.638923 [CA 1] Center 43 (13~73) winsize 61
7549 11:06:59.642185 [CA 2] Center 38 (8~68) winsize 61
7550 11:06:59.645613 [CA 3] Center 37 (8~67) winsize 60
7551 11:06:59.648939 [CA 4] Center 37 (7~67) winsize 61
7552 11:06:59.652564 [CA 5] Center 35 (5~66) winsize 62
7553 11:06:59.653078
7554 11:06:59.655511 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 11:06:59.656026
7556 11:06:59.658655 [CATrainingPosCal] consider 1 rank data
7557 11:06:59.662110 u2DelayCellTimex100 = 290/100 ps
7558 11:06:59.665679 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7559 11:06:59.672354 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7560 11:06:59.675549 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7561 11:06:59.678764 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7562 11:06:59.682162 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7563 11:06:59.685230 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7564 11:06:59.685663
7565 11:06:59.689082 CA PerBit enable=1, Macro0, CA PI delay=35
7566 11:06:59.689636
7567 11:06:59.692207 [CBTSetCACLKResult] CA Dly = 35
7568 11:06:59.695517 CS Dly: 10 (0~41)
7569 11:06:59.698768 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 11:06:59.701878 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 11:06:59.702311 ==
7572 11:06:59.705336 Dram Type= 6, Freq= 0, CH_0, rank 1
7573 11:06:59.708751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 11:06:59.712158 ==
7575 11:06:59.715439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7576 11:06:59.719029 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7577 11:06:59.725303 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7578 11:06:59.728767 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7579 11:06:59.739107 [CA 0] Center 44 (14~74) winsize 61
7580 11:06:59.742459 [CA 1] Center 43 (14~73) winsize 60
7581 11:06:59.745611 [CA 2] Center 38 (9~68) winsize 60
7582 11:06:59.748933 [CA 3] Center 38 (9~68) winsize 60
7583 11:06:59.752031 [CA 4] Center 37 (7~67) winsize 61
7584 11:06:59.755551 [CA 5] Center 36 (7~66) winsize 60
7585 11:06:59.756057
7586 11:06:59.759062 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7587 11:06:59.759571
7588 11:06:59.762248 [CATrainingPosCal] consider 2 rank data
7589 11:06:59.765249 u2DelayCellTimex100 = 290/100 ps
7590 11:06:59.768911 CA0 delay=43 (14~73),Diff = 7 PI (23 cell)
7591 11:06:59.775602 CA1 delay=43 (14~73),Diff = 7 PI (23 cell)
7592 11:06:59.779006 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7593 11:06:59.781868 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7594 11:06:59.785516 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7595 11:06:59.788747 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7596 11:06:59.789376
7597 11:06:59.791965 CA PerBit enable=1, Macro0, CA PI delay=36
7598 11:06:59.792480
7599 11:06:59.795579 [CBTSetCACLKResult] CA Dly = 36
7600 11:06:59.798414 CS Dly: 11 (0~43)
7601 11:06:59.801879 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7602 11:06:59.805250 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7603 11:06:59.805786
7604 11:06:59.808554 ----->DramcWriteLeveling(PI) begin...
7605 11:06:59.809070 ==
7606 11:06:59.811972 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 11:06:59.818716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 11:06:59.819231 ==
7609 11:06:59.821706 Write leveling (Byte 0): 34 => 34
7610 11:06:59.822224 Write leveling (Byte 1): 28 => 28
7611 11:06:59.825261 DramcWriteLeveling(PI) end<-----
7612 11:06:59.825861
7613 11:06:59.828152 ==
7614 11:06:59.828580 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 11:06:59.835086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 11:06:59.835592 ==
7617 11:06:59.838533 [Gating] SW mode calibration
7618 11:06:59.845022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7619 11:06:59.848161 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7620 11:06:59.854956 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 11:06:59.857861 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 11:06:59.861539 1 4 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7623 11:06:59.868255 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7624 11:06:59.871565 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7625 11:06:59.874726 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7626 11:06:59.881777 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 11:06:59.884557 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 11:06:59.888179 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 11:06:59.894849 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 11:06:59.897989 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7631 11:06:59.901287 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7632 11:06:59.908228 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7633 11:06:59.911347 1 5 20 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
7634 11:06:59.914782 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 11:06:59.918000 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 11:06:59.924590 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 11:06:59.927862 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7638 11:06:59.931681 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7639 11:06:59.937877 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7640 11:06:59.941603 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7641 11:06:59.944735 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7642 11:06:59.951419 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 11:06:59.954648 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 11:06:59.957891 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 11:06:59.964936 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 11:06:59.968033 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7647 11:06:59.971048 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7648 11:06:59.977628 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7649 11:06:59.981446 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7650 11:06:59.984741 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:06:59.991580 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:06:59.995006 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:06:59.998155 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:07:00.005053 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:07:00.008155 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:07:00.011682 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:07:00.017879 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:07:00.021453 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:07:00.024382 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:07:00.027757 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:07:00.034405 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:07:00.038023 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 11:07:00.040937 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7664 11:07:00.047916 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7665 11:07:00.051196 Total UI for P1: 0, mck2ui 16
7666 11:07:00.054264 best dqsien dly found for B0: ( 1, 9, 10)
7667 11:07:00.057499 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7668 11:07:00.061167 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 11:07:00.064158 Total UI for P1: 0, mck2ui 16
7670 11:07:00.067842 best dqsien dly found for B1: ( 1, 9, 20)
7671 11:07:00.070739 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7672 11:07:00.074427 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7673 11:07:00.077716
7674 11:07:00.080877 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7675 11:07:00.083971 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7676 11:07:00.087794 [Gating] SW calibration Done
7677 11:07:00.088325 ==
7678 11:07:00.091035 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 11:07:00.093998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 11:07:00.094431 ==
7681 11:07:00.094764 RX Vref Scan: 0
7682 11:07:00.097731
7683 11:07:00.098244 RX Vref 0 -> 0, step: 1
7684 11:07:00.098583
7685 11:07:00.101229 RX Delay 0 -> 252, step: 8
7686 11:07:00.104276 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7687 11:07:00.107500 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7688 11:07:00.114482 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7689 11:07:00.117494 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7690 11:07:00.120999 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7691 11:07:00.124211 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7692 11:07:00.127695 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7693 11:07:00.130868 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7694 11:07:00.137912 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
7695 11:07:00.140984 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
7696 11:07:00.144153 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
7697 11:07:00.147513 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7698 11:07:00.151106 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7699 11:07:00.157681 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7700 11:07:00.160665 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7701 11:07:00.164189 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7702 11:07:00.164705 ==
7703 11:07:00.167455 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 11:07:00.170581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 11:07:00.171033 ==
7706 11:07:00.174317 DQS Delay:
7707 11:07:00.174826 DQS0 = 0, DQS1 = 0
7708 11:07:00.177218 DQM Delay:
7709 11:07:00.177653 DQM0 = 137, DQM1 = 129
7710 11:07:00.180805 DQ Delay:
7711 11:07:00.183743 DQ0 =139, DQ1 =139, DQ2 =131, DQ3 =135
7712 11:07:00.187114 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7713 11:07:00.190600 DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =127
7714 11:07:00.193705 DQ12 =131, DQ13 =131, DQ14 =143, DQ15 =135
7715 11:07:00.194137
7716 11:07:00.194468
7717 11:07:00.194770 ==
7718 11:07:00.196965 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 11:07:00.200840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 11:07:00.201413 ==
7721 11:07:00.201751
7722 11:07:00.202053
7723 11:07:00.204187 TX Vref Scan disable
7724 11:07:00.207474 == TX Byte 0 ==
7725 11:07:00.211001 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7726 11:07:00.214111 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7727 11:07:00.217100 == TX Byte 1 ==
7728 11:07:00.220637 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7729 11:07:00.224010 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7730 11:07:00.224528 ==
7731 11:07:00.227178 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 11:07:00.230728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 11:07:00.233739 ==
7734 11:07:00.245509
7735 11:07:00.248709 TX Vref early break, caculate TX vref
7736 11:07:00.252305 TX Vref=16, minBit 12, minWin=22, winSum=378
7737 11:07:00.255147 TX Vref=18, minBit 12, minWin=22, winSum=390
7738 11:07:00.258608 TX Vref=20, minBit 4, minWin=24, winSum=399
7739 11:07:00.262335 TX Vref=22, minBit 1, minWin=25, winSum=408
7740 11:07:00.265579 TX Vref=24, minBit 7, minWin=25, winSum=420
7741 11:07:00.271918 TX Vref=26, minBit 1, minWin=26, winSum=425
7742 11:07:00.275600 TX Vref=28, minBit 0, minWin=26, winSum=430
7743 11:07:00.278788 TX Vref=30, minBit 0, minWin=26, winSum=424
7744 11:07:00.282034 TX Vref=32, minBit 1, minWin=25, winSum=413
7745 11:07:00.285369 TX Vref=34, minBit 13, minWin=24, winSum=402
7746 11:07:00.292446 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
7747 11:07:00.292965
7748 11:07:00.295654 Final TX Range 0 Vref 28
7749 11:07:00.296165
7750 11:07:00.296499 ==
7751 11:07:00.298628 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 11:07:00.302297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 11:07:00.302816 ==
7754 11:07:00.303159
7755 11:07:00.303465
7756 11:07:00.305088 TX Vref Scan disable
7757 11:07:00.312163 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7758 11:07:00.312682 == TX Byte 0 ==
7759 11:07:00.315204 u2DelayCellOfst[0]=16 cells (5 PI)
7760 11:07:00.318692 u2DelayCellOfst[1]=20 cells (6 PI)
7761 11:07:00.322309 u2DelayCellOfst[2]=16 cells (5 PI)
7762 11:07:00.325433 u2DelayCellOfst[3]=16 cells (5 PI)
7763 11:07:00.328674 u2DelayCellOfst[4]=13 cells (4 PI)
7764 11:07:00.332005 u2DelayCellOfst[5]=0 cells (0 PI)
7765 11:07:00.335727 u2DelayCellOfst[6]=20 cells (6 PI)
7766 11:07:00.339029 u2DelayCellOfst[7]=20 cells (6 PI)
7767 11:07:00.341843 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7768 11:07:00.345281 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7769 11:07:00.348556 == TX Byte 1 ==
7770 11:07:00.349037 u2DelayCellOfst[8]=0 cells (0 PI)
7771 11:07:00.352143 u2DelayCellOfst[9]=0 cells (0 PI)
7772 11:07:00.355298 u2DelayCellOfst[10]=6 cells (2 PI)
7773 11:07:00.359126 u2DelayCellOfst[11]=3 cells (1 PI)
7774 11:07:00.361736 u2DelayCellOfst[12]=10 cells (3 PI)
7775 11:07:00.365154 u2DelayCellOfst[13]=10 cells (3 PI)
7776 11:07:00.369060 u2DelayCellOfst[14]=13 cells (4 PI)
7777 11:07:00.371862 u2DelayCellOfst[15]=10 cells (3 PI)
7778 11:07:00.375451 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7779 11:07:00.382111 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7780 11:07:00.382626 DramC Write-DBI on
7781 11:07:00.382961 ==
7782 11:07:00.385341 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 11:07:00.388926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 11:07:00.389474 ==
7785 11:07:00.392452
7786 11:07:00.392957
7787 11:07:00.393414 TX Vref Scan disable
7788 11:07:00.395402 == TX Byte 0 ==
7789 11:07:00.398741 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7790 11:07:00.402001 == TX Byte 1 ==
7791 11:07:00.405955 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7792 11:07:00.406468 DramC Write-DBI off
7793 11:07:00.408625
7794 11:07:00.409158 [DATLAT]
7795 11:07:00.409539 Freq=1600, CH0 RK0
7796 11:07:00.409854
7797 11:07:00.412235 DATLAT Default: 0xf
7798 11:07:00.412663 0, 0xFFFF, sum = 0
7799 11:07:00.415795 1, 0xFFFF, sum = 0
7800 11:07:00.416309 2, 0xFFFF, sum = 0
7801 11:07:00.418800 3, 0xFFFF, sum = 0
7802 11:07:00.419239 4, 0xFFFF, sum = 0
7803 11:07:00.421876 5, 0xFFFF, sum = 0
7804 11:07:00.425487 6, 0xFFFF, sum = 0
7805 11:07:00.426010 7, 0xFFFF, sum = 0
7806 11:07:00.428466 8, 0xFFFF, sum = 0
7807 11:07:00.428910 9, 0xFFFF, sum = 0
7808 11:07:00.432008 10, 0xFFFF, sum = 0
7809 11:07:00.432530 11, 0xFFFF, sum = 0
7810 11:07:00.435351 12, 0xFFFF, sum = 0
7811 11:07:00.435796 13, 0xFFFF, sum = 0
7812 11:07:00.438766 14, 0x0, sum = 1
7813 11:07:00.439296 15, 0x0, sum = 2
7814 11:07:00.442110 16, 0x0, sum = 3
7815 11:07:00.442629 17, 0x0, sum = 4
7816 11:07:00.445428 best_step = 15
7817 11:07:00.445927
7818 11:07:00.446255 ==
7819 11:07:00.448669 Dram Type= 6, Freq= 0, CH_0, rank 0
7820 11:07:00.451734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7821 11:07:00.452170 ==
7822 11:07:00.452507 RX Vref Scan: 1
7823 11:07:00.452816
7824 11:07:00.455278 Set Vref Range= 24 -> 127
7825 11:07:00.455788
7826 11:07:00.458584 RX Vref 24 -> 127, step: 1
7827 11:07:00.459100
7828 11:07:00.462083 RX Delay 27 -> 252, step: 4
7829 11:07:00.462594
7830 11:07:00.465007 Set Vref, RX VrefLevel [Byte0]: 24
7831 11:07:00.468369 [Byte1]: 24
7832 11:07:00.468798
7833 11:07:00.472040 Set Vref, RX VrefLevel [Byte0]: 25
7834 11:07:00.475250 [Byte1]: 25
7835 11:07:00.475766
7836 11:07:00.478379 Set Vref, RX VrefLevel [Byte0]: 26
7837 11:07:00.482032 [Byte1]: 26
7838 11:07:00.485250
7839 11:07:00.485681 Set Vref, RX VrefLevel [Byte0]: 27
7840 11:07:00.488844 [Byte1]: 27
7841 11:07:00.492756
7842 11:07:00.493323 Set Vref, RX VrefLevel [Byte0]: 28
7843 11:07:00.496348 [Byte1]: 28
7844 11:07:00.500137
7845 11:07:00.500376 Set Vref, RX VrefLevel [Byte0]: 29
7846 11:07:00.503422 [Byte1]: 29
7847 11:07:00.507938
7848 11:07:00.508250 Set Vref, RX VrefLevel [Byte0]: 30
7849 11:07:00.510969 [Byte1]: 30
7850 11:07:00.515316
7851 11:07:00.515630 Set Vref, RX VrefLevel [Byte0]: 31
7852 11:07:00.518749 [Byte1]: 31
7853 11:07:00.522773
7854 11:07:00.523200 Set Vref, RX VrefLevel [Byte0]: 32
7855 11:07:00.526160 [Byte1]: 32
7856 11:07:00.530442
7857 11:07:00.530978 Set Vref, RX VrefLevel [Byte0]: 33
7858 11:07:00.533677 [Byte1]: 33
7859 11:07:00.538027
7860 11:07:00.538470 Set Vref, RX VrefLevel [Byte0]: 34
7861 11:07:00.541205 [Byte1]: 34
7862 11:07:00.545270
7863 11:07:00.545768 Set Vref, RX VrefLevel [Byte0]: 35
7864 11:07:00.549058 [Byte1]: 35
7865 11:07:00.552948
7866 11:07:00.553410 Set Vref, RX VrefLevel [Byte0]: 36
7867 11:07:00.556207 [Byte1]: 36
7868 11:07:00.560694
7869 11:07:00.561079 Set Vref, RX VrefLevel [Byte0]: 37
7870 11:07:00.563790 [Byte1]: 37
7871 11:07:00.568409
7872 11:07:00.568890 Set Vref, RX VrefLevel [Byte0]: 38
7873 11:07:00.571765 [Byte1]: 38
7874 11:07:00.575736
7875 11:07:00.576249 Set Vref, RX VrefLevel [Byte0]: 39
7876 11:07:00.579039 [Byte1]: 39
7877 11:07:00.583232
7878 11:07:00.583732 Set Vref, RX VrefLevel [Byte0]: 40
7879 11:07:00.586386 [Byte1]: 40
7880 11:07:00.590902
7881 11:07:00.591407 Set Vref, RX VrefLevel [Byte0]: 41
7882 11:07:00.594097 [Byte1]: 41
7883 11:07:00.598375
7884 11:07:00.598879 Set Vref, RX VrefLevel [Byte0]: 42
7885 11:07:00.602037 [Byte1]: 42
7886 11:07:00.606215
7887 11:07:00.606717 Set Vref, RX VrefLevel [Byte0]: 43
7888 11:07:00.609271 [Byte1]: 43
7889 11:07:00.613599
7890 11:07:00.614102 Set Vref, RX VrefLevel [Byte0]: 44
7891 11:07:00.616970 [Byte1]: 44
7892 11:07:00.621072
7893 11:07:00.621625 Set Vref, RX VrefLevel [Byte0]: 45
7894 11:07:00.624434 [Byte1]: 45
7895 11:07:00.628721
7896 11:07:00.629268 Set Vref, RX VrefLevel [Byte0]: 46
7897 11:07:00.631850 [Byte1]: 46
7898 11:07:00.636272
7899 11:07:00.636780 Set Vref, RX VrefLevel [Byte0]: 47
7900 11:07:00.639769 [Byte1]: 47
7901 11:07:00.643543
7902 11:07:00.643970 Set Vref, RX VrefLevel [Byte0]: 48
7903 11:07:00.646973 [Byte1]: 48
7904 11:07:00.651802
7905 11:07:00.652311 Set Vref, RX VrefLevel [Byte0]: 49
7906 11:07:00.654261 [Byte1]: 49
7907 11:07:00.658533
7908 11:07:00.659036 Set Vref, RX VrefLevel [Byte0]: 50
7909 11:07:00.662163 [Byte1]: 50
7910 11:07:00.666103
7911 11:07:00.666608 Set Vref, RX VrefLevel [Byte0]: 51
7912 11:07:00.669239 [Byte1]: 51
7913 11:07:00.674011
7914 11:07:00.674677 Set Vref, RX VrefLevel [Byte0]: 52
7915 11:07:00.677076 [Byte1]: 52
7916 11:07:00.681265
7917 11:07:00.681771 Set Vref, RX VrefLevel [Byte0]: 53
7918 11:07:00.684538 [Byte1]: 53
7919 11:07:00.688695
7920 11:07:00.689238 Set Vref, RX VrefLevel [Byte0]: 54
7921 11:07:00.692212 [Byte1]: 54
7922 11:07:00.696316
7923 11:07:00.696825 Set Vref, RX VrefLevel [Byte0]: 55
7924 11:07:00.699860 [Byte1]: 55
7925 11:07:00.703793
7926 11:07:00.704470 Set Vref, RX VrefLevel [Byte0]: 56
7927 11:07:00.707253 [Byte1]: 56
7928 11:07:00.711447
7929 11:07:00.711967 Set Vref, RX VrefLevel [Byte0]: 57
7930 11:07:00.714957 [Byte1]: 57
7931 11:07:00.718998
7932 11:07:00.719502 Set Vref, RX VrefLevel [Byte0]: 58
7933 11:07:00.722443 [Byte1]: 58
7934 11:07:00.726637
7935 11:07:00.727145 Set Vref, RX VrefLevel [Byte0]: 59
7936 11:07:00.729800 [Byte1]: 59
7937 11:07:00.734087
7938 11:07:00.734590 Set Vref, RX VrefLevel [Byte0]: 60
7939 11:07:00.737293 [Byte1]: 60
7940 11:07:00.741803
7941 11:07:00.742314 Set Vref, RX VrefLevel [Byte0]: 61
7942 11:07:00.744888 [Byte1]: 61
7943 11:07:00.749249
7944 11:07:00.749763 Set Vref, RX VrefLevel [Byte0]: 62
7945 11:07:00.752276 [Byte1]: 62
7946 11:07:00.756667
7947 11:07:00.757223 Set Vref, RX VrefLevel [Byte0]: 63
7948 11:07:00.760099 [Byte1]: 63
7949 11:07:00.764114
7950 11:07:00.764618 Set Vref, RX VrefLevel [Byte0]: 64
7951 11:07:00.767272 [Byte1]: 64
7952 11:07:00.771440
7953 11:07:00.771877 Set Vref, RX VrefLevel [Byte0]: 65
7954 11:07:00.774679 [Byte1]: 65
7955 11:07:00.779030
7956 11:07:00.779533 Set Vref, RX VrefLevel [Byte0]: 66
7957 11:07:00.782427 [Byte1]: 66
7958 11:07:00.786672
7959 11:07:00.787175 Set Vref, RX VrefLevel [Byte0]: 67
7960 11:07:00.789886 [Byte1]: 67
7961 11:07:00.794273
7962 11:07:00.794800 Set Vref, RX VrefLevel [Byte0]: 68
7963 11:07:00.797838 [Byte1]: 68
7964 11:07:00.802142
7965 11:07:00.802647 Set Vref, RX VrefLevel [Byte0]: 69
7966 11:07:00.805083 [Byte1]: 69
7967 11:07:00.809343
7968 11:07:00.809844 Set Vref, RX VrefLevel [Byte0]: 70
7969 11:07:00.812638 [Byte1]: 70
7970 11:07:00.817045
7971 11:07:00.817609 Set Vref, RX VrefLevel [Byte0]: 71
7972 11:07:00.820208 [Byte1]: 71
7973 11:07:00.824292
7974 11:07:00.824799 Set Vref, RX VrefLevel [Byte0]: 72
7975 11:07:00.827851 [Byte1]: 72
7976 11:07:00.831899
7977 11:07:00.832417 Set Vref, RX VrefLevel [Byte0]: 73
7978 11:07:00.835236 [Byte1]: 73
7979 11:07:00.839279
7980 11:07:00.839719 Set Vref, RX VrefLevel [Byte0]: 74
7981 11:07:00.842706 [Byte1]: 74
7982 11:07:00.846975
7983 11:07:00.847491 Set Vref, RX VrefLevel [Byte0]: 75
7984 11:07:00.850588 [Byte1]: 75
7985 11:07:00.854252
7986 11:07:00.854690 Set Vref, RX VrefLevel [Byte0]: 76
7987 11:07:00.857743 [Byte1]: 76
7988 11:07:00.861979
7989 11:07:00.862418 Set Vref, RX VrefLevel [Byte0]: 77
7990 11:07:00.865304 [Byte1]: 77
7991 11:07:00.869227
7992 11:07:00.869666 Set Vref, RX VrefLevel [Byte0]: 78
7993 11:07:00.872814 [Byte1]: 78
7994 11:07:00.876933
7995 11:07:00.877482 Set Vref, RX VrefLevel [Byte0]: 79
7996 11:07:00.880233 [Byte1]: 79
7997 11:07:00.884498
7998 11:07:00.884926 Final RX Vref Byte 0 = 65 to rank0
7999 11:07:00.888038 Final RX Vref Byte 1 = 63 to rank0
8000 11:07:00.891689 Final RX Vref Byte 0 = 65 to rank1
8001 11:07:00.894548 Final RX Vref Byte 1 = 63 to rank1==
8002 11:07:00.897842 Dram Type= 6, Freq= 0, CH_0, rank 0
8003 11:07:00.905040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 11:07:00.905595 ==
8005 11:07:00.905937 DQS Delay:
8006 11:07:00.906244 DQS0 = 0, DQS1 = 0
8007 11:07:00.907843 DQM Delay:
8008 11:07:00.908343 DQM0 = 134, DQM1 = 127
8009 11:07:00.911348 DQ Delay:
8010 11:07:00.914472 DQ0 =134, DQ1 =134, DQ2 =130, DQ3 =132
8011 11:07:00.917659 DQ4 =136, DQ5 =124, DQ6 =144, DQ7 =140
8012 11:07:00.921038 DQ8 =118, DQ9 =114, DQ10 =130, DQ11 =122
8013 11:07:00.924607 DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =134
8014 11:07:00.925116
8015 11:07:00.925512
8016 11:07:00.925819
8017 11:07:00.927858 [DramC_TX_OE_Calibration] TA2
8018 11:07:00.931092 Original DQ_B0 (3 6) =30, OEN = 27
8019 11:07:00.934495 Original DQ_B1 (3 6) =30, OEN = 27
8020 11:07:00.937985 24, 0x0, End_B0=24 End_B1=24
8021 11:07:00.938513 25, 0x0, End_B0=25 End_B1=25
8022 11:07:00.941291 26, 0x0, End_B0=26 End_B1=26
8023 11:07:00.944708 27, 0x0, End_B0=27 End_B1=27
8024 11:07:00.948386 28, 0x0, End_B0=28 End_B1=28
8025 11:07:00.948915 29, 0x0, End_B0=29 End_B1=29
8026 11:07:00.950716 30, 0x0, End_B0=30 End_B1=30
8027 11:07:00.954529 31, 0x4141, End_B0=30 End_B1=30
8028 11:07:00.958078 Byte0 end_step=30 best_step=27
8029 11:07:00.961345 Byte1 end_step=30 best_step=27
8030 11:07:00.964684 Byte0 TX OE(2T, 0.5T) = (3, 3)
8031 11:07:00.965258 Byte1 TX OE(2T, 0.5T) = (3, 3)
8032 11:07:00.967602
8033 11:07:00.968038
8034 11:07:00.974427 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8035 11:07:00.977497 CH0 RK0: MR19=303, MR18=1D1B
8036 11:07:00.984349 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8037 11:07:00.984858
8038 11:07:00.987433 ----->DramcWriteLeveling(PI) begin...
8039 11:07:00.987866 ==
8040 11:07:00.990888 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 11:07:00.994306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 11:07:00.994812 ==
8043 11:07:00.998023 Write leveling (Byte 0): 36 => 36
8044 11:07:01.000790 Write leveling (Byte 1): 28 => 28
8045 11:07:01.004403 DramcWriteLeveling(PI) end<-----
8046 11:07:01.004909
8047 11:07:01.005286 ==
8048 11:07:01.007821 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 11:07:01.011442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 11:07:01.011951 ==
8051 11:07:01.014290 [Gating] SW mode calibration
8052 11:07:01.020990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8053 11:07:01.027610 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8054 11:07:01.031034 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 11:07:01.034521 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 11:07:01.041013 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 11:07:01.044258 1 4 12 | B1->B0 | 2929 3433 | 0 1 | (0 0) (1 1)
8058 11:07:01.047787 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 11:07:01.053911 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 11:07:01.057787 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:07:01.061235 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:07:01.067435 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:07:01.070872 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 11:07:01.074136 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8065 11:07:01.081165 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
8066 11:07:01.084004 1 5 16 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8067 11:07:01.087436 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 11:07:01.094217 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 11:07:01.097333 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:07:01.100791 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:07:01.107340 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:07:01.110929 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8073 11:07:01.114033 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
8074 11:07:01.117750 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8075 11:07:01.124448 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:07:01.127881 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:07:01.131475 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:07:01.137772 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:07:01.141063 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 11:07:01.144155 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8081 11:07:01.150724 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8082 11:07:01.154236 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:07:01.157684 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:07:01.164189 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:07:01.167797 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:07:01.170942 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:07:01.177708 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:07:01.181006 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:07:01.184136 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:07:01.190378 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:07:01.194007 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:07:01.197588 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:07:01.203735 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:07:01.207166 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:07:01.210148 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:07:01.216954 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8097 11:07:01.220466 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8098 11:07:01.223422 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8099 11:07:01.230331 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 11:07:01.230843 Total UI for P1: 0, mck2ui 16
8101 11:07:01.237176 best dqsien dly found for B0: ( 1, 9, 12)
8102 11:07:01.237836 Total UI for P1: 0, mck2ui 16
8103 11:07:01.240004 best dqsien dly found for B1: ( 1, 9, 14)
8104 11:07:01.247008 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8105 11:07:01.250385 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8106 11:07:01.250811
8107 11:07:01.253510 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8108 11:07:01.256836 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8109 11:07:01.260333 [Gating] SW calibration Done
8110 11:07:01.260835 ==
8111 11:07:01.263476 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 11:07:01.266591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 11:07:01.267086 ==
8114 11:07:01.269929 RX Vref Scan: 0
8115 11:07:01.270354
8116 11:07:01.270684 RX Vref 0 -> 0, step: 1
8117 11:07:01.270990
8118 11:07:01.273586 RX Delay 0 -> 252, step: 8
8119 11:07:01.276828 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8120 11:07:01.280243 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8121 11:07:01.286680 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8122 11:07:01.290020 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8123 11:07:01.293795 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8124 11:07:01.296905 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8125 11:07:01.299896 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8126 11:07:01.307199 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8127 11:07:01.310213 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8128 11:07:01.313400 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8129 11:07:01.316690 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8130 11:07:01.319872 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8131 11:07:01.326943 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8132 11:07:01.329863 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8133 11:07:01.333327 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8134 11:07:01.336728 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8135 11:07:01.337281 ==
8136 11:07:01.340063 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 11:07:01.346442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 11:07:01.346948 ==
8139 11:07:01.347288 DQS Delay:
8140 11:07:01.349755 DQS0 = 0, DQS1 = 0
8141 11:07:01.350184 DQM Delay:
8142 11:07:01.350513 DQM0 = 135, DQM1 = 126
8143 11:07:01.353550 DQ Delay:
8144 11:07:01.356559 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
8145 11:07:01.359908 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8146 11:07:01.363466 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8147 11:07:01.366602 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8148 11:07:01.367107
8149 11:07:01.367441
8150 11:07:01.367747 ==
8151 11:07:01.369849 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 11:07:01.373595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 11:07:01.376823 ==
8154 11:07:01.377378
8155 11:07:01.377717
8156 11:07:01.378028 TX Vref Scan disable
8157 11:07:01.379739 == TX Byte 0 ==
8158 11:07:01.383307 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8159 11:07:01.386558 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8160 11:07:01.389906 == TX Byte 1 ==
8161 11:07:01.393154 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8162 11:07:01.396606 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8163 11:07:01.400369 ==
8164 11:07:01.400885 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 11:07:01.406829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 11:07:01.407341 ==
8167 11:07:01.420755
8168 11:07:01.424138 TX Vref early break, caculate TX vref
8169 11:07:01.427459 TX Vref=16, minBit 1, minWin=23, winSum=386
8170 11:07:01.431230 TX Vref=18, minBit 0, minWin=24, winSum=396
8171 11:07:01.433730 TX Vref=20, minBit 0, minWin=24, winSum=402
8172 11:07:01.437337 TX Vref=22, minBit 8, minWin=24, winSum=413
8173 11:07:01.440406 TX Vref=24, minBit 0, minWin=25, winSum=417
8174 11:07:01.447675 TX Vref=26, minBit 0, minWin=25, winSum=428
8175 11:07:01.450324 TX Vref=28, minBit 1, minWin=26, winSum=429
8176 11:07:01.453705 TX Vref=30, minBit 0, minWin=25, winSum=426
8177 11:07:01.457406 TX Vref=32, minBit 1, minWin=24, winSum=417
8178 11:07:01.460638 TX Vref=34, minBit 0, minWin=25, winSum=408
8179 11:07:01.463793 TX Vref=36, minBit 0, minWin=24, winSum=398
8180 11:07:01.470766 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
8181 11:07:01.471279
8182 11:07:01.473844 Final TX Range 0 Vref 28
8183 11:07:01.474276
8184 11:07:01.474609 ==
8185 11:07:01.477401 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 11:07:01.480779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 11:07:01.481337 ==
8188 11:07:01.481683
8189 11:07:01.481991
8190 11:07:01.483885 TX Vref Scan disable
8191 11:07:01.490745 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8192 11:07:01.491256 == TX Byte 0 ==
8193 11:07:01.493942 u2DelayCellOfst[0]=13 cells (4 PI)
8194 11:07:01.496856 u2DelayCellOfst[1]=20 cells (6 PI)
8195 11:07:01.500614 u2DelayCellOfst[2]=13 cells (4 PI)
8196 11:07:01.503726 u2DelayCellOfst[3]=13 cells (4 PI)
8197 11:07:01.507576 u2DelayCellOfst[4]=10 cells (3 PI)
8198 11:07:01.510641 u2DelayCellOfst[5]=0 cells (0 PI)
8199 11:07:01.513850 u2DelayCellOfst[6]=20 cells (6 PI)
8200 11:07:01.517196 u2DelayCellOfst[7]=20 cells (6 PI)
8201 11:07:01.520737 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8202 11:07:01.524199 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8203 11:07:01.527299 == TX Byte 1 ==
8204 11:07:01.530456 u2DelayCellOfst[8]=0 cells (0 PI)
8205 11:07:01.530967 u2DelayCellOfst[9]=0 cells (0 PI)
8206 11:07:01.533712 u2DelayCellOfst[10]=6 cells (2 PI)
8207 11:07:01.537072 u2DelayCellOfst[11]=3 cells (1 PI)
8208 11:07:01.540785 u2DelayCellOfst[12]=13 cells (4 PI)
8209 11:07:01.544175 u2DelayCellOfst[13]=10 cells (3 PI)
8210 11:07:01.547202 u2DelayCellOfst[14]=13 cells (4 PI)
8211 11:07:01.550622 u2DelayCellOfst[15]=10 cells (3 PI)
8212 11:07:01.553532 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8213 11:07:01.560326 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8214 11:07:01.560762 DramC Write-DBI on
8215 11:07:01.561095 ==
8216 11:07:01.563643 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 11:07:01.570099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 11:07:01.570594 ==
8219 11:07:01.571218
8220 11:07:01.571844
8221 11:07:01.572324 TX Vref Scan disable
8222 11:07:01.573788 == TX Byte 0 ==
8223 11:07:01.577185 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8224 11:07:01.580654 == TX Byte 1 ==
8225 11:07:01.583995 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8226 11:07:01.587080 DramC Write-DBI off
8227 11:07:01.587546
8228 11:07:01.587852 [DATLAT]
8229 11:07:01.588134 Freq=1600, CH0 RK1
8230 11:07:01.588470
8231 11:07:01.590863 DATLAT Default: 0xf
8232 11:07:01.591299 0, 0xFFFF, sum = 0
8233 11:07:01.594082 1, 0xFFFF, sum = 0
8234 11:07:01.594481 2, 0xFFFF, sum = 0
8235 11:07:01.597288 3, 0xFFFF, sum = 0
8236 11:07:01.600524 4, 0xFFFF, sum = 0
8237 11:07:01.600973 5, 0xFFFF, sum = 0
8238 11:07:01.603919 6, 0xFFFF, sum = 0
8239 11:07:01.604317 7, 0xFFFF, sum = 0
8240 11:07:01.607437 8, 0xFFFF, sum = 0
8241 11:07:01.607903 9, 0xFFFF, sum = 0
8242 11:07:01.610531 10, 0xFFFF, sum = 0
8243 11:07:01.610923 11, 0xFFFF, sum = 0
8244 11:07:01.614179 12, 0xFFFF, sum = 0
8245 11:07:01.614575 13, 0xFFFF, sum = 0
8246 11:07:01.617449 14, 0x0, sum = 1
8247 11:07:01.617847 15, 0x0, sum = 2
8248 11:07:01.620688 16, 0x0, sum = 3
8249 11:07:01.621082 17, 0x0, sum = 4
8250 11:07:01.624452 best_step = 15
8251 11:07:01.624953
8252 11:07:01.625385 ==
8253 11:07:01.627725 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 11:07:01.631188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 11:07:01.631671 ==
8256 11:07:01.632002 RX Vref Scan: 0
8257 11:07:01.633822
8258 11:07:01.634248 RX Vref 0 -> 0, step: 1
8259 11:07:01.634583
8260 11:07:01.637370 RX Delay 19 -> 252, step: 4
8261 11:07:01.640872 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8262 11:07:01.647328 iDelay=191, Bit 1, Center 134 (83 ~ 186) 104
8263 11:07:01.650821 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8264 11:07:01.653927 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8265 11:07:01.657596 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8266 11:07:01.660811 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8267 11:07:01.667708 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8268 11:07:01.670793 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8269 11:07:01.673916 iDelay=191, Bit 8, Center 118 (71 ~ 166) 96
8270 11:07:01.677248 iDelay=191, Bit 9, Center 112 (63 ~ 162) 100
8271 11:07:01.680687 iDelay=191, Bit 10, Center 126 (83 ~ 170) 88
8272 11:07:01.684124 iDelay=191, Bit 11, Center 122 (75 ~ 170) 96
8273 11:07:01.690736 iDelay=191, Bit 12, Center 130 (83 ~ 178) 96
8274 11:07:01.693846 iDelay=191, Bit 13, Center 130 (83 ~ 178) 96
8275 11:07:01.697559 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8276 11:07:01.700720 iDelay=191, Bit 15, Center 132 (83 ~ 182) 100
8277 11:07:01.701181 ==
8278 11:07:01.703859 Dram Type= 6, Freq= 0, CH_0, rank 1
8279 11:07:01.710591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 11:07:01.711107 ==
8281 11:07:01.711445 DQS Delay:
8282 11:07:01.711755 DQS0 = 0, DQS1 = 0
8283 11:07:01.714198 DQM Delay:
8284 11:07:01.714715 DQM0 = 132, DQM1 = 125
8285 11:07:01.717163 DQ Delay:
8286 11:07:01.720784 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =130
8287 11:07:01.724160 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8288 11:07:01.727143 DQ8 =118, DQ9 =112, DQ10 =126, DQ11 =122
8289 11:07:01.730747 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
8290 11:07:01.731264
8291 11:07:01.731601
8292 11:07:01.731906
8293 11:07:01.733758 [DramC_TX_OE_Calibration] TA2
8294 11:07:01.737256 Original DQ_B0 (3 6) =30, OEN = 27
8295 11:07:01.740504 Original DQ_B1 (3 6) =30, OEN = 27
8296 11:07:01.743991 24, 0x0, End_B0=24 End_B1=24
8297 11:07:01.744518 25, 0x0, End_B0=25 End_B1=25
8298 11:07:01.746926 26, 0x0, End_B0=26 End_B1=26
8299 11:07:01.750833 27, 0x0, End_B0=27 End_B1=27
8300 11:07:01.753692 28, 0x0, End_B0=28 End_B1=28
8301 11:07:01.754134 29, 0x0, End_B0=29 End_B1=29
8302 11:07:01.757034 30, 0x0, End_B0=30 End_B1=30
8303 11:07:01.760763 31, 0x4141, End_B0=30 End_B1=30
8304 11:07:01.763862 Byte0 end_step=30 best_step=27
8305 11:07:01.767449 Byte1 end_step=30 best_step=27
8306 11:07:01.770491 Byte0 TX OE(2T, 0.5T) = (3, 3)
8307 11:07:01.771009 Byte1 TX OE(2T, 0.5T) = (3, 3)
8308 11:07:01.773718
8309 11:07:01.774144
8310 11:07:01.780265 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8311 11:07:01.783697 CH0 RK1: MR19=303, MR18=2411
8312 11:07:01.790588 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8313 11:07:01.793688 [RxdqsGatingPostProcess] freq 1600
8314 11:07:01.796806 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8315 11:07:01.800221 best DQS0 dly(2T, 0.5T) = (1, 1)
8316 11:07:01.803970 best DQS1 dly(2T, 0.5T) = (1, 1)
8317 11:07:01.807250 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8318 11:07:01.810612 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8319 11:07:01.813726 best DQS0 dly(2T, 0.5T) = (1, 1)
8320 11:07:01.817023 best DQS1 dly(2T, 0.5T) = (1, 1)
8321 11:07:01.820728 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8322 11:07:01.823725 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8323 11:07:01.824242 Pre-setting of DQS Precalculation
8324 11:07:01.830472 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8325 11:07:01.830982 ==
8326 11:07:01.833784 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 11:07:01.837271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 11:07:01.837777 ==
8329 11:07:01.843842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8330 11:07:01.847187 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8331 11:07:01.853421 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8332 11:07:01.856835 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8333 11:07:01.867079 [CA 0] Center 42 (12~72) winsize 61
8334 11:07:01.870300 [CA 1] Center 42 (12~72) winsize 61
8335 11:07:01.873551 [CA 2] Center 38 (9~68) winsize 60
8336 11:07:01.877046 [CA 3] Center 37 (8~67) winsize 60
8337 11:07:01.880359 [CA 4] Center 37 (7~67) winsize 61
8338 11:07:01.883711 [CA 5] Center 37 (7~67) winsize 61
8339 11:07:01.884217
8340 11:07:01.886760 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8341 11:07:01.887263
8342 11:07:01.890234 [CATrainingPosCal] consider 1 rank data
8343 11:07:01.893531 u2DelayCellTimex100 = 290/100 ps
8344 11:07:01.896991 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8345 11:07:01.903238 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8346 11:07:01.906736 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8347 11:07:01.910048 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8348 11:07:01.913677 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
8349 11:07:01.916656 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8350 11:07:01.917202
8351 11:07:01.919859 CA PerBit enable=1, Macro0, CA PI delay=37
8352 11:07:01.920365
8353 11:07:01.923028 [CBTSetCACLKResult] CA Dly = 37
8354 11:07:01.926605 CS Dly: 8 (0~39)
8355 11:07:01.929605 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8356 11:07:01.933030 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8357 11:07:01.933606 ==
8358 11:07:01.936576 Dram Type= 6, Freq= 0, CH_1, rank 1
8359 11:07:01.939709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 11:07:01.940141 ==
8361 11:07:01.947023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8362 11:07:01.949671 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8363 11:07:01.956613 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8364 11:07:01.959803 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8365 11:07:01.969958 [CA 0] Center 42 (13~72) winsize 60
8366 11:07:01.973461 [CA 1] Center 42 (12~72) winsize 61
8367 11:07:01.976792 [CA 2] Center 38 (9~68) winsize 60
8368 11:07:01.979920 [CA 3] Center 37 (8~67) winsize 60
8369 11:07:01.983220 [CA 4] Center 37 (8~67) winsize 60
8370 11:07:01.986471 [CA 5] Center 37 (8~67) winsize 60
8371 11:07:01.986891
8372 11:07:01.989712 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8373 11:07:01.990134
8374 11:07:01.992944 [CATrainingPosCal] consider 2 rank data
8375 11:07:01.996476 u2DelayCellTimex100 = 290/100 ps
8376 11:07:01.999576 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8377 11:07:02.006194 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8378 11:07:02.009975 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8379 11:07:02.013299 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8380 11:07:02.016407 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8381 11:07:02.019822 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8382 11:07:02.020194
8383 11:07:02.022810 CA PerBit enable=1, Macro0, CA PI delay=37
8384 11:07:02.023102
8385 11:07:02.026297 [CBTSetCACLKResult] CA Dly = 37
8386 11:07:02.026666 CS Dly: 9 (0~42)
8387 11:07:02.033071 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8388 11:07:02.036685 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8389 11:07:02.037098
8390 11:07:02.039625 ----->DramcWriteLeveling(PI) begin...
8391 11:07:02.039923 ==
8392 11:07:02.043140 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 11:07:02.046425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 11:07:02.046825 ==
8395 11:07:02.049471 Write leveling (Byte 0): 23 => 23
8396 11:07:02.052969 Write leveling (Byte 1): 30 => 30
8397 11:07:02.056292 DramcWriteLeveling(PI) end<-----
8398 11:07:02.056707
8399 11:07:02.057027 ==
8400 11:07:02.059297 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 11:07:02.066251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 11:07:02.066674 ==
8403 11:07:02.067000 [Gating] SW mode calibration
8404 11:07:02.076231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8405 11:07:02.079531 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8406 11:07:02.082695 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:07:02.089467 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 11:07:02.092749 1 4 8 | B1->B0 | 3030 3333 | 1 1 | (1 1) (0 0)
8409 11:07:02.096460 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 11:07:02.102964 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 11:07:02.105874 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 11:07:02.109765 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 11:07:02.116352 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 11:07:02.119778 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 11:07:02.122943 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8416 11:07:02.129658 1 5 8 | B1->B0 | 2d2d 2929 | 0 0 | (0 1) (1 0)
8417 11:07:02.133013 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8418 11:07:02.136233 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 11:07:02.142805 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:07:02.146284 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:07:02.149301 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:07:02.155913 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 11:07:02.159661 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8424 11:07:02.162718 1 6 8 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
8425 11:07:02.169363 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 11:07:02.172908 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 11:07:02.176429 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 11:07:02.182499 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 11:07:02.185909 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:07:02.188942 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:07:02.196007 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8432 11:07:02.199426 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8433 11:07:02.202765 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8434 11:07:02.205916 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 11:07:02.212874 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:07:02.215884 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:07:02.219646 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:07:02.226525 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:07:02.229330 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:07:02.233076 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:07:02.239595 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:07:02.242780 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:07:02.246347 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:07:02.252743 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:07:02.256273 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:07:02.259316 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:07:02.266127 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8448 11:07:02.269822 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8449 11:07:02.273051 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8450 11:07:02.276400 Total UI for P1: 0, mck2ui 16
8451 11:07:02.279918 best dqsien dly found for B0: ( 1, 9, 6)
8452 11:07:02.282761 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 11:07:02.285938 Total UI for P1: 0, mck2ui 16
8454 11:07:02.289259 best dqsien dly found for B1: ( 1, 9, 10)
8455 11:07:02.292740 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8456 11:07:02.296099 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8457 11:07:02.296527
8458 11:07:02.303082 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8459 11:07:02.306020 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8460 11:07:02.309805 [Gating] SW calibration Done
8461 11:07:02.310310 ==
8462 11:07:02.313355 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 11:07:02.316354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 11:07:02.316877 ==
8465 11:07:02.317402 RX Vref Scan: 0
8466 11:07:02.317816
8467 11:07:02.319236 RX Vref 0 -> 0, step: 1
8468 11:07:02.319685
8469 11:07:02.323039 RX Delay 0 -> 252, step: 8
8470 11:07:02.326466 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8471 11:07:02.329848 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8472 11:07:02.332952 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8473 11:07:02.339489 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8474 11:07:02.342989 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8475 11:07:02.346571 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8476 11:07:02.349490 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8477 11:07:02.353428 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8478 11:07:02.359416 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8479 11:07:02.362994 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8480 11:07:02.366307 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8481 11:07:02.369821 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8482 11:07:02.373106 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8483 11:07:02.379701 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8484 11:07:02.382721 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8485 11:07:02.386070 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8486 11:07:02.386567 ==
8487 11:07:02.389534 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 11:07:02.393104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 11:07:02.393675 ==
8490 11:07:02.396359 DQS Delay:
8491 11:07:02.396862 DQS0 = 0, DQS1 = 0
8492 11:07:02.397235 DQM Delay:
8493 11:07:02.399435 DQM0 = 138, DQM1 = 130
8494 11:07:02.399863 DQ Delay:
8495 11:07:02.402846 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8496 11:07:02.406434 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8497 11:07:02.412904 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8498 11:07:02.416192 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8499 11:07:02.416622
8500 11:07:02.416953
8501 11:07:02.417300 ==
8502 11:07:02.419443 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 11:07:02.422837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 11:07:02.423344 ==
8505 11:07:02.423674
8506 11:07:02.423973
8507 11:07:02.425968 TX Vref Scan disable
8508 11:07:02.429950 == TX Byte 0 ==
8509 11:07:02.433159 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8510 11:07:02.436525 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8511 11:07:02.439978 == TX Byte 1 ==
8512 11:07:02.442668 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8513 11:07:02.446368 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8514 11:07:02.446874 ==
8515 11:07:02.449740 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 11:07:02.453436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 11:07:02.453985 ==
8518 11:07:02.467427
8519 11:07:02.470868 TX Vref early break, caculate TX vref
8520 11:07:02.474074 TX Vref=16, minBit 10, minWin=21, winSum=368
8521 11:07:02.477371 TX Vref=18, minBit 8, minWin=22, winSum=376
8522 11:07:02.480610 TX Vref=20, minBit 10, minWin=22, winSum=381
8523 11:07:02.483915 TX Vref=22, minBit 8, minWin=23, winSum=396
8524 11:07:02.486983 TX Vref=24, minBit 0, minWin=25, winSum=409
8525 11:07:02.494043 TX Vref=26, minBit 10, minWin=24, winSum=410
8526 11:07:02.497358 TX Vref=28, minBit 8, minWin=25, winSum=414
8527 11:07:02.500518 TX Vref=30, minBit 9, minWin=24, winSum=408
8528 11:07:02.503749 TX Vref=32, minBit 9, minWin=23, winSum=401
8529 11:07:02.507445 TX Vref=34, minBit 11, minWin=22, winSum=391
8530 11:07:02.514063 [TxChooseVref] Worse bit 8, Min win 25, Win sum 414, Final Vref 28
8531 11:07:02.514569
8532 11:07:02.517417 Final TX Range 0 Vref 28
8533 11:07:02.517927
8534 11:07:02.518254 ==
8535 11:07:02.520636 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 11:07:02.523857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 11:07:02.524368 ==
8538 11:07:02.524699
8539 11:07:02.524999
8540 11:07:02.526915 TX Vref Scan disable
8541 11:07:02.533705 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8542 11:07:02.534213 == TX Byte 0 ==
8543 11:07:02.537502 u2DelayCellOfst[0]=13 cells (4 PI)
8544 11:07:02.540471 u2DelayCellOfst[1]=10 cells (3 PI)
8545 11:07:02.544034 u2DelayCellOfst[2]=0 cells (0 PI)
8546 11:07:02.547473 u2DelayCellOfst[3]=3 cells (1 PI)
8547 11:07:02.550852 u2DelayCellOfst[4]=6 cells (2 PI)
8548 11:07:02.553952 u2DelayCellOfst[5]=16 cells (5 PI)
8549 11:07:02.557364 u2DelayCellOfst[6]=16 cells (5 PI)
8550 11:07:02.560231 u2DelayCellOfst[7]=3 cells (1 PI)
8551 11:07:02.563657 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8552 11:07:02.567221 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8553 11:07:02.570428 == TX Byte 1 ==
8554 11:07:02.570937 u2DelayCellOfst[8]=0 cells (0 PI)
8555 11:07:02.573715 u2DelayCellOfst[9]=3 cells (1 PI)
8556 11:07:02.577005 u2DelayCellOfst[10]=10 cells (3 PI)
8557 11:07:02.580705 u2DelayCellOfst[11]=3 cells (1 PI)
8558 11:07:02.583537 u2DelayCellOfst[12]=13 cells (4 PI)
8559 11:07:02.587250 u2DelayCellOfst[13]=16 cells (5 PI)
8560 11:07:02.590647 u2DelayCellOfst[14]=16 cells (5 PI)
8561 11:07:02.593798 u2DelayCellOfst[15]=13 cells (4 PI)
8562 11:07:02.596975 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8563 11:07:02.603786 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8564 11:07:02.604217 DramC Write-DBI on
8565 11:07:02.604544 ==
8566 11:07:02.607080 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 11:07:02.610634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 11:07:02.613587 ==
8569 11:07:02.614158
8570 11:07:02.614496
8571 11:07:02.614932 TX Vref Scan disable
8572 11:07:02.616885 == TX Byte 0 ==
8573 11:07:02.620268 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8574 11:07:02.623563 == TX Byte 1 ==
8575 11:07:02.626715 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8576 11:07:02.630322 DramC Write-DBI off
8577 11:07:02.631091
8578 11:07:02.631985 [DATLAT]
8579 11:07:02.632336 Freq=1600, CH1 RK0
8580 11:07:02.632670
8581 11:07:02.633527 DATLAT Default: 0xf
8582 11:07:02.633890 0, 0xFFFF, sum = 0
8583 11:07:02.637006 1, 0xFFFF, sum = 0
8584 11:07:02.637506 2, 0xFFFF, sum = 0
8585 11:07:02.640226 3, 0xFFFF, sum = 0
8586 11:07:02.643562 4, 0xFFFF, sum = 0
8587 11:07:02.644004 5, 0xFFFF, sum = 0
8588 11:07:02.646888 6, 0xFFFF, sum = 0
8589 11:07:02.647561 7, 0xFFFF, sum = 0
8590 11:07:02.650268 8, 0xFFFF, sum = 0
8591 11:07:02.651008 9, 0xFFFF, sum = 0
8592 11:07:02.653652 10, 0xFFFF, sum = 0
8593 11:07:02.654096 11, 0xFFFF, sum = 0
8594 11:07:02.656898 12, 0xFFFF, sum = 0
8595 11:07:02.657547 13, 0xFFFF, sum = 0
8596 11:07:02.660003 14, 0x0, sum = 1
8597 11:07:02.660722 15, 0x0, sum = 2
8598 11:07:02.663428 16, 0x0, sum = 3
8599 11:07:02.663861 17, 0x0, sum = 4
8600 11:07:02.666710 best_step = 15
8601 11:07:02.667099
8602 11:07:02.667396 ==
8603 11:07:02.670458 Dram Type= 6, Freq= 0, CH_1, rank 0
8604 11:07:02.673294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8605 11:07:02.673688 ==
8606 11:07:02.673992 RX Vref Scan: 1
8607 11:07:02.676624
8608 11:07:02.677009 Set Vref Range= 24 -> 127
8609 11:07:02.677352
8610 11:07:02.680284 RX Vref 24 -> 127, step: 1
8611 11:07:02.680751
8612 11:07:02.683532 RX Delay 19 -> 252, step: 4
8613 11:07:02.684003
8614 11:07:02.686664 Set Vref, RX VrefLevel [Byte0]: 24
8615 11:07:02.689941 [Byte1]: 24
8616 11:07:02.690331
8617 11:07:02.693639 Set Vref, RX VrefLevel [Byte0]: 25
8618 11:07:02.697231 [Byte1]: 25
8619 11:07:02.697696
8620 11:07:02.700249 Set Vref, RX VrefLevel [Byte0]: 26
8621 11:07:02.703595 [Byte1]: 26
8622 11:07:02.707018
8623 11:07:02.707404 Set Vref, RX VrefLevel [Byte0]: 27
8624 11:07:02.710891 [Byte1]: 27
8625 11:07:02.714889
8626 11:07:02.715353 Set Vref, RX VrefLevel [Byte0]: 28
8627 11:07:02.717938 [Byte1]: 28
8628 11:07:02.722266
8629 11:07:02.722722 Set Vref, RX VrefLevel [Byte0]: 29
8630 11:07:02.725750 [Byte1]: 29
8631 11:07:02.729779
8632 11:07:02.730273 Set Vref, RX VrefLevel [Byte0]: 30
8633 11:07:02.733256 [Byte1]: 30
8634 11:07:02.737389
8635 11:07:02.737854 Set Vref, RX VrefLevel [Byte0]: 31
8636 11:07:02.741238 [Byte1]: 31
8637 11:07:02.745346
8638 11:07:02.745844 Set Vref, RX VrefLevel [Byte0]: 32
8639 11:07:02.748589 [Byte1]: 32
8640 11:07:02.752888
8641 11:07:02.753440 Set Vref, RX VrefLevel [Byte0]: 33
8642 11:07:02.755934 [Byte1]: 33
8643 11:07:02.760315
8644 11:07:02.760817 Set Vref, RX VrefLevel [Byte0]: 34
8645 11:07:02.763536 [Byte1]: 34
8646 11:07:02.767669
8647 11:07:02.768095 Set Vref, RX VrefLevel [Byte0]: 35
8648 11:07:02.771511 [Byte1]: 35
8649 11:07:02.775415
8650 11:07:02.775912 Set Vref, RX VrefLevel [Byte0]: 36
8651 11:07:02.778789 [Byte1]: 36
8652 11:07:02.783130
8653 11:07:02.783640 Set Vref, RX VrefLevel [Byte0]: 37
8654 11:07:02.786206 [Byte1]: 37
8655 11:07:02.790572
8656 11:07:02.790996 Set Vref, RX VrefLevel [Byte0]: 38
8657 11:07:02.794045 [Byte1]: 38
8658 11:07:02.798478
8659 11:07:02.798986 Set Vref, RX VrefLevel [Byte0]: 39
8660 11:07:02.801754 [Byte1]: 39
8661 11:07:02.806005
8662 11:07:02.806530 Set Vref, RX VrefLevel [Byte0]: 40
8663 11:07:02.809490 [Byte1]: 40
8664 11:07:02.813524
8665 11:07:02.814033 Set Vref, RX VrefLevel [Byte0]: 41
8666 11:07:02.816858 [Byte1]: 41
8667 11:07:02.821213
8668 11:07:02.821717 Set Vref, RX VrefLevel [Byte0]: 42
8669 11:07:02.824132 [Byte1]: 42
8670 11:07:02.828442
8671 11:07:02.828945 Set Vref, RX VrefLevel [Byte0]: 43
8672 11:07:02.832047 [Byte1]: 43
8673 11:07:02.835824
8674 11:07:02.836252 Set Vref, RX VrefLevel [Byte0]: 44
8675 11:07:02.839093 [Byte1]: 44
8676 11:07:02.843614
8677 11:07:02.844117 Set Vref, RX VrefLevel [Byte0]: 45
8678 11:07:02.847060 [Byte1]: 45
8679 11:07:02.851156
8680 11:07:02.851672 Set Vref, RX VrefLevel [Byte0]: 46
8681 11:07:02.854463 [Byte1]: 46
8682 11:07:02.858920
8683 11:07:02.859443 Set Vref, RX VrefLevel [Byte0]: 47
8684 11:07:02.862617 [Byte1]: 47
8685 11:07:02.866312
8686 11:07:02.866736 Set Vref, RX VrefLevel [Byte0]: 48
8687 11:07:02.869923 [Byte1]: 48
8688 11:07:02.874057
8689 11:07:02.874563 Set Vref, RX VrefLevel [Byte0]: 49
8690 11:07:02.877174 [Byte1]: 49
8691 11:07:02.881849
8692 11:07:02.882359 Set Vref, RX VrefLevel [Byte0]: 50
8693 11:07:02.885044 [Byte1]: 50
8694 11:07:02.889082
8695 11:07:02.889631 Set Vref, RX VrefLevel [Byte0]: 51
8696 11:07:02.892171 [Byte1]: 51
8697 11:07:02.896572
8698 11:07:02.897083 Set Vref, RX VrefLevel [Byte0]: 52
8699 11:07:02.899963 [Byte1]: 52
8700 11:07:02.903970
8701 11:07:02.904396 Set Vref, RX VrefLevel [Byte0]: 53
8702 11:07:02.907577 [Byte1]: 53
8703 11:07:02.911872
8704 11:07:02.912380 Set Vref, RX VrefLevel [Byte0]: 54
8705 11:07:02.915068 [Byte1]: 54
8706 11:07:02.919195
8707 11:07:02.919704 Set Vref, RX VrefLevel [Byte0]: 55
8708 11:07:02.922610 [Byte1]: 55
8709 11:07:02.926929
8710 11:07:02.927544 Set Vref, RX VrefLevel [Byte0]: 56
8711 11:07:02.930144 [Byte1]: 56
8712 11:07:02.934361
8713 11:07:02.934788 Set Vref, RX VrefLevel [Byte0]: 57
8714 11:07:02.937762 [Byte1]: 57
8715 11:07:02.941762
8716 11:07:02.942213 Set Vref, RX VrefLevel [Byte0]: 58
8717 11:07:02.945262 [Byte1]: 58
8718 11:07:02.949843
8719 11:07:02.950355 Set Vref, RX VrefLevel [Byte0]: 59
8720 11:07:02.952925 [Byte1]: 59
8721 11:07:02.957275
8722 11:07:02.957779 Set Vref, RX VrefLevel [Byte0]: 60
8723 11:07:02.960576 [Byte1]: 60
8724 11:07:02.964915
8725 11:07:02.965464 Set Vref, RX VrefLevel [Byte0]: 61
8726 11:07:02.967998 [Byte1]: 61
8727 11:07:02.972249
8728 11:07:02.972756 Set Vref, RX VrefLevel [Byte0]: 62
8729 11:07:02.975827 [Byte1]: 62
8730 11:07:02.979910
8731 11:07:02.980422 Set Vref, RX VrefLevel [Byte0]: 63
8732 11:07:02.983130 [Byte1]: 63
8733 11:07:02.987360
8734 11:07:02.987983 Set Vref, RX VrefLevel [Byte0]: 64
8735 11:07:02.990888 [Byte1]: 64
8736 11:07:02.995229
8737 11:07:02.995742 Set Vref, RX VrefLevel [Byte0]: 65
8738 11:07:02.998235 [Byte1]: 65
8739 11:07:03.002583
8740 11:07:03.003095 Set Vref, RX VrefLevel [Byte0]: 66
8741 11:07:03.006042 [Byte1]: 66
8742 11:07:03.010098
8743 11:07:03.010607 Set Vref, RX VrefLevel [Byte0]: 67
8744 11:07:03.014024 [Byte1]: 67
8745 11:07:03.018008
8746 11:07:03.018521 Set Vref, RX VrefLevel [Byte0]: 68
8747 11:07:03.021209 [Byte1]: 68
8748 11:07:03.025536
8749 11:07:03.026043 Set Vref, RX VrefLevel [Byte0]: 69
8750 11:07:03.028470 [Byte1]: 69
8751 11:07:03.032933
8752 11:07:03.033490 Set Vref, RX VrefLevel [Byte0]: 70
8753 11:07:03.035884 [Byte1]: 70
8754 11:07:03.040343
8755 11:07:03.040856 Set Vref, RX VrefLevel [Byte0]: 71
8756 11:07:03.043472 [Byte1]: 71
8757 11:07:03.048093
8758 11:07:03.048602 Set Vref, RX VrefLevel [Byte0]: 72
8759 11:07:03.051565 [Byte1]: 72
8760 11:07:03.055323
8761 11:07:03.055808 Set Vref, RX VrefLevel [Byte0]: 73
8762 11:07:03.058837 [Byte1]: 73
8763 11:07:03.063439
8764 11:07:03.063950 Set Vref, RX VrefLevel [Byte0]: 74
8765 11:07:03.066204 [Byte1]: 74
8766 11:07:03.070818
8767 11:07:03.071325 Final RX Vref Byte 0 = 54 to rank0
8768 11:07:03.073946 Final RX Vref Byte 1 = 64 to rank0
8769 11:07:03.077347 Final RX Vref Byte 0 = 54 to rank1
8770 11:07:03.080639 Final RX Vref Byte 1 = 64 to rank1==
8771 11:07:03.085297 Dram Type= 6, Freq= 0, CH_1, rank 0
8772 11:07:03.090413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 11:07:03.090919 ==
8774 11:07:03.091354 DQS Delay:
8775 11:07:03.091760 DQS0 = 0, DQS1 = 0
8776 11:07:03.093848 DQM Delay:
8777 11:07:03.094282 DQM0 = 133, DQM1 = 129
8778 11:07:03.097506 DQ Delay:
8779 11:07:03.100602 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8780 11:07:03.104334 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8781 11:07:03.107468 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8782 11:07:03.110992 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8783 11:07:03.111509
8784 11:07:03.111950
8785 11:07:03.112357
8786 11:07:03.114366 [DramC_TX_OE_Calibration] TA2
8787 11:07:03.117673 Original DQ_B0 (3 6) =30, OEN = 27
8788 11:07:03.121099 Original DQ_B1 (3 6) =30, OEN = 27
8789 11:07:03.123945 24, 0x0, End_B0=24 End_B1=24
8790 11:07:03.124404 25, 0x0, End_B0=25 End_B1=25
8791 11:07:03.127456 26, 0x0, End_B0=26 End_B1=26
8792 11:07:03.130709 27, 0x0, End_B0=27 End_B1=27
8793 11:07:03.134223 28, 0x0, End_B0=28 End_B1=28
8794 11:07:03.134695 29, 0x0, End_B0=29 End_B1=29
8795 11:07:03.137820 30, 0x0, End_B0=30 End_B1=30
8796 11:07:03.140656 31, 0x4141, End_B0=30 End_B1=30
8797 11:07:03.144391 Byte0 end_step=30 best_step=27
8798 11:07:03.147438 Byte1 end_step=30 best_step=27
8799 11:07:03.150780 Byte0 TX OE(2T, 0.5T) = (3, 3)
8800 11:07:03.151295 Byte1 TX OE(2T, 0.5T) = (3, 3)
8801 11:07:03.151729
8802 11:07:03.153915
8803 11:07:03.160536 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8804 11:07:03.163868 CH1 RK0: MR19=303, MR18=1927
8805 11:07:03.170752 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8806 11:07:03.171407
8807 11:07:03.174075 ----->DramcWriteLeveling(PI) begin...
8808 11:07:03.174600 ==
8809 11:07:03.177188 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 11:07:03.180669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 11:07:03.181111 ==
8812 11:07:03.184017 Write leveling (Byte 0): 23 => 23
8813 11:07:03.187260 Write leveling (Byte 1): 29 => 29
8814 11:07:03.190459 DramcWriteLeveling(PI) end<-----
8815 11:07:03.190900
8816 11:07:03.191333 ==
8817 11:07:03.194413 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 11:07:03.197117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 11:07:03.197665 ==
8820 11:07:03.200639 [Gating] SW mode calibration
8821 11:07:03.207254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8822 11:07:03.214084 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8823 11:07:03.217168 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 11:07:03.220627 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 11:07:03.227691 1 4 8 | B1->B0 | 2f2f 2323 | 0 1 | (0 0) (1 1)
8826 11:07:03.230978 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8827 11:07:03.233962 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 11:07:03.240753 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 11:07:03.244062 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 11:07:03.247256 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 11:07:03.253911 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 11:07:03.257539 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 11:07:03.260622 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)
8834 11:07:03.264187 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 0)
8835 11:07:03.270664 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:07:03.274119 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 11:07:03.277455 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 11:07:03.284353 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 11:07:03.287329 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 11:07:03.290402 1 6 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8841 11:07:03.297419 1 6 8 | B1->B0 | 4545 2d2d | 0 0 | (0 0) (0 0)
8842 11:07:03.300553 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
8843 11:07:03.303665 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 11:07:03.310466 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 11:07:03.313989 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 11:07:03.317493 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 11:07:03.324004 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 11:07:03.327280 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 11:07:03.330605 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8850 11:07:03.337089 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8851 11:07:03.341225 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:07:03.344146 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:07:03.350793 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:07:03.354211 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:07:03.357609 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:07:03.360267 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:07:03.367649 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:07:03.370722 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:07:03.373684 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:07:03.380423 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:07:03.384338 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:07:03.387220 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:07:03.393610 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:07:03.397543 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:07:03.400421 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8866 11:07:03.406871 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 11:07:03.407093 Total UI for P1: 0, mck2ui 16
8868 11:07:03.413785 best dqsien dly found for B0: ( 1, 9, 8)
8869 11:07:03.414068 Total UI for P1: 0, mck2ui 16
8870 11:07:03.420560 best dqsien dly found for B1: ( 1, 9, 8)
8871 11:07:03.423937 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8872 11:07:03.427248 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8873 11:07:03.427657
8874 11:07:03.430839 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8875 11:07:03.433701 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8876 11:07:03.436894 [Gating] SW calibration Done
8877 11:07:03.437359 ==
8878 11:07:03.440426 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 11:07:03.443562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 11:07:03.443993 ==
8881 11:07:03.447369 RX Vref Scan: 0
8882 11:07:03.447870
8883 11:07:03.448201 RX Vref 0 -> 0, step: 1
8884 11:07:03.448508
8885 11:07:03.450345 RX Delay 0 -> 252, step: 8
8886 11:07:03.453806 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8887 11:07:03.460645 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8888 11:07:03.463611 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8889 11:07:03.466884 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8890 11:07:03.470652 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8891 11:07:03.473350 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8892 11:07:03.476971 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8893 11:07:03.483793 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8894 11:07:03.487034 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8895 11:07:03.489779 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8896 11:07:03.493257 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8897 11:07:03.500056 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8898 11:07:03.503127 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8899 11:07:03.506388 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8900 11:07:03.510182 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8901 11:07:03.513498 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8902 11:07:03.514004 ==
8903 11:07:03.516790 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 11:07:03.523128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 11:07:03.523652 ==
8906 11:07:03.523990 DQS Delay:
8907 11:07:03.526706 DQS0 = 0, DQS1 = 0
8908 11:07:03.527212 DQM Delay:
8909 11:07:03.529674 DQM0 = 137, DQM1 = 132
8910 11:07:03.530180 DQ Delay:
8911 11:07:03.533167 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8912 11:07:03.536341 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8913 11:07:03.540232 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8914 11:07:03.542836 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8915 11:07:03.543264
8916 11:07:03.543591
8917 11:07:03.543886 ==
8918 11:07:03.546902 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 11:07:03.553277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 11:07:03.553791 ==
8921 11:07:03.554127
8922 11:07:03.554429
8923 11:07:03.554721 TX Vref Scan disable
8924 11:07:03.556243 == TX Byte 0 ==
8925 11:07:03.559843 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8926 11:07:03.562950 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8927 11:07:03.566359 == TX Byte 1 ==
8928 11:07:03.569571 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8929 11:07:03.573099 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8930 11:07:03.576234 ==
8931 11:07:03.579599 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 11:07:03.582809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 11:07:03.583238 ==
8934 11:07:03.595864
8935 11:07:03.598873 TX Vref early break, caculate TX vref
8936 11:07:03.602545 TX Vref=16, minBit 8, minWin=22, winSum=379
8937 11:07:03.605702 TX Vref=18, minBit 8, minWin=23, winSum=390
8938 11:07:03.608758 TX Vref=20, minBit 9, minWin=23, winSum=394
8939 11:07:03.612302 TX Vref=22, minBit 8, minWin=24, winSum=407
8940 11:07:03.615405 TX Vref=24, minBit 9, minWin=24, winSum=418
8941 11:07:03.621896 TX Vref=26, minBit 11, minWin=24, winSum=420
8942 11:07:03.625225 TX Vref=28, minBit 8, minWin=25, winSum=416
8943 11:07:03.628625 TX Vref=30, minBit 0, minWin=25, winSum=413
8944 11:07:03.631756 TX Vref=32, minBit 8, minWin=24, winSum=403
8945 11:07:03.635128 TX Vref=34, minBit 8, minWin=24, winSum=396
8946 11:07:03.642067 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
8947 11:07:03.642509
8948 11:07:03.645309 Final TX Range 0 Vref 28
8949 11:07:03.645735
8950 11:07:03.646063 ==
8951 11:07:03.648818 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 11:07:03.651730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 11:07:03.652157 ==
8954 11:07:03.652485
8955 11:07:03.652786
8956 11:07:03.655277 TX Vref Scan disable
8957 11:07:03.661723 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8958 11:07:03.662151 == TX Byte 0 ==
8959 11:07:03.665295 u2DelayCellOfst[0]=20 cells (6 PI)
8960 11:07:03.668300 u2DelayCellOfst[1]=13 cells (4 PI)
8961 11:07:03.671746 u2DelayCellOfst[2]=0 cells (0 PI)
8962 11:07:03.675155 u2DelayCellOfst[3]=10 cells (3 PI)
8963 11:07:03.678417 u2DelayCellOfst[4]=10 cells (3 PI)
8964 11:07:03.681841 u2DelayCellOfst[5]=20 cells (6 PI)
8965 11:07:03.684871 u2DelayCellOfst[6]=20 cells (6 PI)
8966 11:07:03.688295 u2DelayCellOfst[7]=6 cells (2 PI)
8967 11:07:03.691777 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8968 11:07:03.694820 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8969 11:07:03.698391 == TX Byte 1 ==
8970 11:07:03.701640 u2DelayCellOfst[8]=0 cells (0 PI)
8971 11:07:03.702027 u2DelayCellOfst[9]=3 cells (1 PI)
8972 11:07:03.704855 u2DelayCellOfst[10]=10 cells (3 PI)
8973 11:07:03.708107 u2DelayCellOfst[11]=0 cells (0 PI)
8974 11:07:03.711717 u2DelayCellOfst[12]=10 cells (3 PI)
8975 11:07:03.714854 u2DelayCellOfst[13]=16 cells (5 PI)
8976 11:07:03.718452 u2DelayCellOfst[14]=16 cells (5 PI)
8977 11:07:03.721419 u2DelayCellOfst[15]=16 cells (5 PI)
8978 11:07:03.725079 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8979 11:07:03.731984 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8980 11:07:03.732454 DramC Write-DBI on
8981 11:07:03.732754 ==
8982 11:07:03.734681 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 11:07:03.738254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 11:07:03.741507 ==
8985 11:07:03.741894
8986 11:07:03.742190
8987 11:07:03.742468 TX Vref Scan disable
8988 11:07:03.745119 == TX Byte 0 ==
8989 11:07:03.748541 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8990 11:07:03.751887 == TX Byte 1 ==
8991 11:07:03.755127 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8992 11:07:03.755572 DramC Write-DBI off
8993 11:07:03.758348
8994 11:07:03.758780 [DATLAT]
8995 11:07:03.759115 Freq=1600, CH1 RK1
8996 11:07:03.759429
8997 11:07:03.761693 DATLAT Default: 0xf
8998 11:07:03.762124 0, 0xFFFF, sum = 0
8999 11:07:03.765317 1, 0xFFFF, sum = 0
9000 11:07:03.765848 2, 0xFFFF, sum = 0
9001 11:07:03.768345 3, 0xFFFF, sum = 0
9002 11:07:03.768783 4, 0xFFFF, sum = 0
9003 11:07:03.772391 5, 0xFFFF, sum = 0
9004 11:07:03.775257 6, 0xFFFF, sum = 0
9005 11:07:03.775783 7, 0xFFFF, sum = 0
9006 11:07:03.778925 8, 0xFFFF, sum = 0
9007 11:07:03.779448 9, 0xFFFF, sum = 0
9008 11:07:03.782068 10, 0xFFFF, sum = 0
9009 11:07:03.782597 11, 0xFFFF, sum = 0
9010 11:07:03.785179 12, 0xFFFF, sum = 0
9011 11:07:03.785714 13, 0xFFFF, sum = 0
9012 11:07:03.788636 14, 0x0, sum = 1
9013 11:07:03.789203 15, 0x0, sum = 2
9014 11:07:03.791664 16, 0x0, sum = 3
9015 11:07:03.792135 17, 0x0, sum = 4
9016 11:07:03.795325 best_step = 15
9017 11:07:03.795831
9018 11:07:03.796165 ==
9019 11:07:03.798331 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 11:07:03.801977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 11:07:03.802509 ==
9022 11:07:03.802869 RX Vref Scan: 0
9023 11:07:03.803182
9024 11:07:03.805281 RX Vref 0 -> 0, step: 1
9025 11:07:03.805710
9026 11:07:03.808490 RX Delay 19 -> 252, step: 4
9027 11:07:03.812195 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9028 11:07:03.815202 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
9029 11:07:03.822156 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9030 11:07:03.825030 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9031 11:07:03.828832 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9032 11:07:03.832254 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9033 11:07:03.835091 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9034 11:07:03.842360 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9035 11:07:03.845106 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9036 11:07:03.848634 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9037 11:07:03.852050 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9038 11:07:03.855425 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9039 11:07:03.861719 iDelay=195, Bit 12, Center 140 (91 ~ 190) 100
9040 11:07:03.864678 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9041 11:07:03.868133 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9042 11:07:03.871826 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9043 11:07:03.872353 ==
9044 11:07:03.874812 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 11:07:03.881783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 11:07:03.882284 ==
9047 11:07:03.882625 DQS Delay:
9048 11:07:03.882939 DQS0 = 0, DQS1 = 0
9049 11:07:03.885036 DQM Delay:
9050 11:07:03.885498 DQM0 = 134, DQM1 = 130
9051 11:07:03.888481 DQ Delay:
9052 11:07:03.891674 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
9053 11:07:03.895619 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9054 11:07:03.898521 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9055 11:07:03.901933 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =138
9056 11:07:03.902444
9057 11:07:03.902775
9058 11:07:03.903079
9059 11:07:03.904793 [DramC_TX_OE_Calibration] TA2
9060 11:07:03.908209 Original DQ_B0 (3 6) =30, OEN = 27
9061 11:07:03.911790 Original DQ_B1 (3 6) =30, OEN = 27
9062 11:07:03.915114 24, 0x0, End_B0=24 End_B1=24
9063 11:07:03.915651 25, 0x0, End_B0=25 End_B1=25
9064 11:07:03.918701 26, 0x0, End_B0=26 End_B1=26
9065 11:07:03.922057 27, 0x0, End_B0=27 End_B1=27
9066 11:07:03.925260 28, 0x0, End_B0=28 End_B1=28
9067 11:07:03.925782 29, 0x0, End_B0=29 End_B1=29
9068 11:07:03.928424 30, 0x0, End_B0=30 End_B1=30
9069 11:07:03.931704 31, 0x4141, End_B0=30 End_B1=30
9070 11:07:03.935205 Byte0 end_step=30 best_step=27
9071 11:07:03.938437 Byte1 end_step=30 best_step=27
9072 11:07:03.941627 Byte0 TX OE(2T, 0.5T) = (3, 3)
9073 11:07:03.942133 Byte1 TX OE(2T, 0.5T) = (3, 3)
9074 11:07:03.942471
9075 11:07:03.945228
9076 11:07:03.951763 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9077 11:07:03.955123 CH1 RK1: MR19=303, MR18=1D07
9078 11:07:03.961938 CH1_RK1: MR19=0x303, MR18=0x1D07, DQSOSC=395, MR23=63, INC=23, DEC=15
9079 11:07:03.962448 [RxdqsGatingPostProcess] freq 1600
9080 11:07:03.968789 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9081 11:07:03.971829 best DQS0 dly(2T, 0.5T) = (1, 1)
9082 11:07:03.975048 best DQS1 dly(2T, 0.5T) = (1, 1)
9083 11:07:03.978567 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9084 11:07:03.981962 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9085 11:07:03.985694 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 11:07:03.988389 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 11:07:03.988819 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 11:07:03.991774 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 11:07:03.995498 Pre-setting of DQS Precalculation
9090 11:07:04.002108 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9091 11:07:04.008805 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9092 11:07:04.015338 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 11:07:04.015842
9094 11:07:04.016176
9095 11:07:04.018707 [Calibration Summary] 3200 Mbps
9096 11:07:04.022001 CH 0, Rank 0
9097 11:07:04.022562 SW Impedance : PASS
9098 11:07:04.024972 DUTY Scan : NO K
9099 11:07:04.028371 ZQ Calibration : PASS
9100 11:07:04.028800 Jitter Meter : NO K
9101 11:07:04.031883 CBT Training : PASS
9102 11:07:04.032391 Write leveling : PASS
9103 11:07:04.034911 RX DQS gating : PASS
9104 11:07:04.038774 RX DQ/DQS(RDDQC) : PASS
9105 11:07:04.039293 TX DQ/DQS : PASS
9106 11:07:04.041899 RX DATLAT : PASS
9107 11:07:04.045065 RX DQ/DQS(Engine): PASS
9108 11:07:04.045606 TX OE : PASS
9109 11:07:04.048390 All Pass.
9110 11:07:04.048893
9111 11:07:04.049263 CH 0, Rank 1
9112 11:07:04.051685 SW Impedance : PASS
9113 11:07:04.052190 DUTY Scan : NO K
9114 11:07:04.055302 ZQ Calibration : PASS
9115 11:07:04.058315 Jitter Meter : NO K
9116 11:07:04.058751 CBT Training : PASS
9117 11:07:04.061768 Write leveling : PASS
9118 11:07:04.064950 RX DQS gating : PASS
9119 11:07:04.065506 RX DQ/DQS(RDDQC) : PASS
9120 11:07:04.068570 TX DQ/DQS : PASS
9121 11:07:04.071682 RX DATLAT : PASS
9122 11:07:04.072187 RX DQ/DQS(Engine): PASS
9123 11:07:04.074793 TX OE : PASS
9124 11:07:04.075223 All Pass.
9125 11:07:04.075554
9126 11:07:04.078128 CH 1, Rank 0
9127 11:07:04.078634 SW Impedance : PASS
9128 11:07:04.081786 DUTY Scan : NO K
9129 11:07:04.082290 ZQ Calibration : PASS
9130 11:07:04.085372 Jitter Meter : NO K
9131 11:07:04.088403 CBT Training : PASS
9132 11:07:04.088909 Write leveling : PASS
9133 11:07:04.091471 RX DQS gating : PASS
9134 11:07:04.095098 RX DQ/DQS(RDDQC) : PASS
9135 11:07:04.095616 TX DQ/DQS : PASS
9136 11:07:04.098121 RX DATLAT : PASS
9137 11:07:04.102071 RX DQ/DQS(Engine): PASS
9138 11:07:04.102580 TX OE : PASS
9139 11:07:04.105173 All Pass.
9140 11:07:04.105712
9141 11:07:04.106049 CH 1, Rank 1
9142 11:07:04.107864 SW Impedance : PASS
9143 11:07:04.108294 DUTY Scan : NO K
9144 11:07:04.111810 ZQ Calibration : PASS
9145 11:07:04.114926 Jitter Meter : NO K
9146 11:07:04.115434 CBT Training : PASS
9147 11:07:04.118523 Write leveling : PASS
9148 11:07:04.121820 RX DQS gating : PASS
9149 11:07:04.122344 RX DQ/DQS(RDDQC) : PASS
9150 11:07:04.125186 TX DQ/DQS : PASS
9151 11:07:04.125705 RX DATLAT : PASS
9152 11:07:04.128314 RX DQ/DQS(Engine): PASS
9153 11:07:04.131489 TX OE : PASS
9154 11:07:04.131995 All Pass.
9155 11:07:04.132328
9156 11:07:04.135046 DramC Write-DBI on
9157 11:07:04.135729 PER_BANK_REFRESH: Hybrid Mode
9158 11:07:04.138072 TX_TRACKING: ON
9159 11:07:04.148477 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9160 11:07:04.155151 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9161 11:07:04.161792 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9162 11:07:04.164962 [FAST_K] Save calibration result to emmc
9163 11:07:04.167753 sync common calibartion params.
9164 11:07:04.171618 sync cbt_mode0:1, 1:1
9165 11:07:04.172126 dram_init: ddr_geometry: 2
9166 11:07:04.175131 dram_init: ddr_geometry: 2
9167 11:07:04.178149 dram_init: ddr_geometry: 2
9168 11:07:04.181617 0:dram_rank_size:100000000
9169 11:07:04.182133 1:dram_rank_size:100000000
9170 11:07:04.188281 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9171 11:07:04.191256 DFS_SHUFFLE_HW_MODE: ON
9172 11:07:04.194457 dramc_set_vcore_voltage set vcore to 725000
9173 11:07:04.194894 Read voltage for 1600, 0
9174 11:07:04.197867 Vio18 = 0
9175 11:07:04.198369 Vcore = 725000
9176 11:07:04.198704 Vdram = 0
9177 11:07:04.201219 Vddq = 0
9178 11:07:04.201719 Vmddr = 0
9179 11:07:04.205196 switch to 3200 Mbps bootup
9180 11:07:04.205705 [DramcRunTimeConfig]
9181 11:07:04.208417 PHYPLL
9182 11:07:04.208921 DPM_CONTROL_AFTERK: ON
9183 11:07:04.211423 PER_BANK_REFRESH: ON
9184 11:07:04.214604 REFRESH_OVERHEAD_REDUCTION: ON
9185 11:07:04.215109 CMD_PICG_NEW_MODE: OFF
9186 11:07:04.218035 XRTWTW_NEW_MODE: ON
9187 11:07:04.218532 XRTRTR_NEW_MODE: ON
9188 11:07:04.221172 TX_TRACKING: ON
9189 11:07:04.221675 RDSEL_TRACKING: OFF
9190 11:07:04.224525 DQS Precalculation for DVFS: ON
9191 11:07:04.227588 RX_TRACKING: OFF
9192 11:07:04.228014 HW_GATING DBG: ON
9193 11:07:04.230933 ZQCS_ENABLE_LP4: ON
9194 11:07:04.231363 RX_PICG_NEW_MODE: ON
9195 11:07:04.234312 TX_PICG_NEW_MODE: ON
9196 11:07:04.234816 ENABLE_RX_DCM_DPHY: ON
9197 11:07:04.237786 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9198 11:07:04.241100 DUMMY_READ_FOR_TRACKING: OFF
9199 11:07:04.244412 !!! SPM_CONTROL_AFTERK: OFF
9200 11:07:04.247567 !!! SPM could not control APHY
9201 11:07:04.248004 IMPEDANCE_TRACKING: ON
9202 11:07:04.251074 TEMP_SENSOR: ON
9203 11:07:04.251573 HW_SAVE_FOR_SR: OFF
9204 11:07:04.254578 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9205 11:07:04.257585 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9206 11:07:04.261033 Read ODT Tracking: ON
9207 11:07:04.264244 Refresh Rate DeBounce: ON
9208 11:07:04.264745 DFS_NO_QUEUE_FLUSH: ON
9209 11:07:04.267426 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9210 11:07:04.271041 ENABLE_DFS_RUNTIME_MRW: OFF
9211 11:07:04.274288 DDR_RESERVE_NEW_MODE: ON
9212 11:07:04.274792 MR_CBT_SWITCH_FREQ: ON
9213 11:07:04.277505 =========================
9214 11:07:04.296002 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9215 11:07:04.299649 dram_init: ddr_geometry: 2
9216 11:07:04.317692 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9217 11:07:04.321183 dram_init: dram init end (result: 0)
9218 11:07:04.327727 DRAM-K: Full calibration passed in 24485 msecs
9219 11:07:04.330897 MRC: failed to locate region type 0.
9220 11:07:04.331322 DRAM rank0 size:0x100000000,
9221 11:07:04.334293 DRAM rank1 size=0x100000000
9222 11:07:04.344354 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9223 11:07:04.350922 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9224 11:07:04.357510 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9225 11:07:04.364086 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9226 11:07:04.367623 DRAM rank0 size:0x100000000,
9227 11:07:04.371100 DRAM rank1 size=0x100000000
9228 11:07:04.371602 CBMEM:
9229 11:07:04.374409 IMD: root @ 0xfffff000 254 entries.
9230 11:07:04.377482 IMD: root @ 0xffffec00 62 entries.
9231 11:07:04.381087 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9232 11:07:04.384210 WARNING: RO_VPD is uninitialized or empty.
9233 11:07:04.390894 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9234 11:07:04.397780 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9235 11:07:04.410291 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9236 11:07:04.421990 BS: romstage times (exec / console): total (unknown) / 24002 ms
9237 11:07:04.422638
9238 11:07:04.422990
9239 11:07:04.432100 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9240 11:07:04.435277 ARM64: Exception handlers installed.
9241 11:07:04.438996 ARM64: Testing exception
9242 11:07:04.441771 ARM64: Done test exception
9243 11:07:04.442200 Enumerating buses...
9244 11:07:04.445171 Show all devs... Before device enumeration.
9245 11:07:04.448849 Root Device: enabled 1
9246 11:07:04.452236 CPU_CLUSTER: 0: enabled 1
9247 11:07:04.452741 CPU: 00: enabled 1
9248 11:07:04.455394 Compare with tree...
9249 11:07:04.455956 Root Device: enabled 1
9250 11:07:04.458645 CPU_CLUSTER: 0: enabled 1
9251 11:07:04.462145 CPU: 00: enabled 1
9252 11:07:04.462663 Root Device scanning...
9253 11:07:04.465121 scan_static_bus for Root Device
9254 11:07:04.468671 CPU_CLUSTER: 0 enabled
9255 11:07:04.472160 scan_static_bus for Root Device done
9256 11:07:04.475250 scan_bus: bus Root Device finished in 8 msecs
9257 11:07:04.475890 done
9258 11:07:04.481735 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9259 11:07:04.485313 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9260 11:07:04.492029 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9261 11:07:04.495101 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9262 11:07:04.498767 Allocating resources...
9263 11:07:04.499286 Reading resources...
9264 11:07:04.505552 Root Device read_resources bus 0 link: 0
9265 11:07:04.506058 DRAM rank0 size:0x100000000,
9266 11:07:04.508290 DRAM rank1 size=0x100000000
9267 11:07:04.512079 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9268 11:07:04.515140 CPU: 00 missing read_resources
9269 11:07:04.518321 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9270 11:07:04.525248 Root Device read_resources bus 0 link: 0 done
9271 11:07:04.525752 Done reading resources.
9272 11:07:04.531733 Show resources in subtree (Root Device)...After reading.
9273 11:07:04.535277 Root Device child on link 0 CPU_CLUSTER: 0
9274 11:07:04.538265 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 11:07:04.548377 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 11:07:04.548888 CPU: 00
9277 11:07:04.551641 Root Device assign_resources, bus 0 link: 0
9278 11:07:04.554779 CPU_CLUSTER: 0 missing set_resources
9279 11:07:04.558128 Root Device assign_resources, bus 0 link: 0 done
9280 11:07:04.561502 Done setting resources.
9281 11:07:04.568107 Show resources in subtree (Root Device)...After assigning values.
9282 11:07:04.571664 Root Device child on link 0 CPU_CLUSTER: 0
9283 11:07:04.575025 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 11:07:04.584964 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 11:07:04.585500 CPU: 00
9286 11:07:04.588239 Done allocating resources.
9287 11:07:04.591359 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9288 11:07:04.594631 Enabling resources...
9289 11:07:04.595063 done.
9290 11:07:04.601323 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9291 11:07:04.601835 Initializing devices...
9292 11:07:04.604542 Root Device init
9293 11:07:04.605046 init hardware done!
9294 11:07:04.607793 0x00000018: ctrlr->caps
9295 11:07:04.611432 52.000 MHz: ctrlr->f_max
9296 11:07:04.611951 0.400 MHz: ctrlr->f_min
9297 11:07:04.614626 0x40ff8080: ctrlr->voltages
9298 11:07:04.615066 sclk: 390625
9299 11:07:04.617924 Bus Width = 1
9300 11:07:04.618428 sclk: 390625
9301 11:07:04.618760 Bus Width = 1
9302 11:07:04.621762 Early init status = 3
9303 11:07:04.624856 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9304 11:07:04.630073 in-header: 03 fc 00 00 01 00 00 00
9305 11:07:04.633226 in-data: 00
9306 11:07:04.636413 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9307 11:07:04.642029 in-header: 03 fd 00 00 00 00 00 00
9308 11:07:04.645489 in-data:
9309 11:07:04.648838 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9310 11:07:04.653339 in-header: 03 fc 00 00 01 00 00 00
9311 11:07:04.656933 in-data: 00
9312 11:07:04.659825 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9313 11:07:04.665446 in-header: 03 fd 00 00 00 00 00 00
9314 11:07:04.669080 in-data:
9315 11:07:04.672396 [SSUSB] Setting up USB HOST controller...
9316 11:07:04.675553 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9317 11:07:04.678855 [SSUSB] phy power-on done.
9318 11:07:04.682100 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9319 11:07:04.689024 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9320 11:07:04.692304 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9321 11:07:04.698869 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9322 11:07:04.705599 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9323 11:07:04.712400 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9324 11:07:04.718564 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9325 11:07:04.725293 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9326 11:07:04.728425 SPM: binary array size = 0x9dc
9327 11:07:04.731835 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9328 11:07:04.738519 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9329 11:07:04.745015 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9330 11:07:04.748477 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9331 11:07:04.754831 configure_display: Starting display init
9332 11:07:04.788722 anx7625_power_on_init: Init interface.
9333 11:07:04.792077 anx7625_disable_pd_protocol: Disabled PD feature.
9334 11:07:04.795260 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9335 11:07:04.823482 anx7625_start_dp_work: Secure OCM version=00
9336 11:07:04.826759 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9337 11:07:04.841377 sp_tx_get_edid_block: EDID Block = 1
9338 11:07:04.944389 Extracted contents:
9339 11:07:04.947712 header: 00 ff ff ff ff ff ff 00
9340 11:07:04.950704 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9341 11:07:04.953839 version: 01 04
9342 11:07:04.957233 basic params: 95 1f 11 78 0a
9343 11:07:04.960375 chroma info: 76 90 94 55 54 90 27 21 50 54
9344 11:07:04.963574 established: 00 00 00
9345 11:07:04.970485 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9346 11:07:04.973574 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9347 11:07:04.980545 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 11:07:04.987325 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9349 11:07:04.993719 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9350 11:07:04.997257 extensions: 00
9351 11:07:04.997955 checksum: fb
9352 11:07:04.998432
9353 11:07:05.000647 Manufacturer: IVO Model 57d Serial Number 0
9354 11:07:05.003950 Made week 0 of 2020
9355 11:07:05.004459 EDID version: 1.4
9356 11:07:05.007522 Digital display
9357 11:07:05.010560 6 bits per primary color channel
9358 11:07:05.011080 DisplayPort interface
9359 11:07:05.013897 Maximum image size: 31 cm x 17 cm
9360 11:07:05.017274 Gamma: 220%
9361 11:07:05.017778 Check DPMS levels
9362 11:07:05.020572 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9363 11:07:05.024202 First detailed timing is preferred timing
9364 11:07:05.027311 Established timings supported:
9365 11:07:05.030520 Standard timings supported:
9366 11:07:05.031029 Detailed timings
9367 11:07:05.037401 Hex of detail: 383680a07038204018303c0035ae10000019
9368 11:07:05.040644 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9369 11:07:05.044224 0780 0798 07c8 0820 hborder 0
9370 11:07:05.050465 0438 043b 0447 0458 vborder 0
9371 11:07:05.050891 -hsync -vsync
9372 11:07:05.053769 Did detailed timing
9373 11:07:05.057241 Hex of detail: 000000000000000000000000000000000000
9374 11:07:05.060146 Manufacturer-specified data, tag 0
9375 11:07:05.067179 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9376 11:07:05.067605 ASCII string: InfoVision
9377 11:07:05.073775 Hex of detail: 000000fe00523134304e574635205248200a
9378 11:07:05.074284 ASCII string: R140NWF5 RH
9379 11:07:05.077693 Checksum
9380 11:07:05.078199 Checksum: 0xfb (valid)
9381 11:07:05.083688 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9382 11:07:05.084131 DSI data_rate: 832800000 bps
9383 11:07:05.091367 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9384 11:07:05.094927 anx7625_parse_edid: pixelclock(138800).
9385 11:07:05.098293 hactive(1920), hsync(48), hfp(24), hbp(88)
9386 11:07:05.101427 vactive(1080), vsync(12), vfp(3), vbp(17)
9387 11:07:05.104923 anx7625_dsi_config: config dsi.
9388 11:07:05.111716 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9389 11:07:05.125953 anx7625_dsi_config: success to config DSI
9390 11:07:05.129500 anx7625_dp_start: MIPI phy setup OK.
9391 11:07:05.132960 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9392 11:07:05.135916 mtk_ddp_mode_set invalid vrefresh 60
9393 11:07:05.139422 main_disp_path_setup
9394 11:07:05.139922 ovl_layer_smi_id_en
9395 11:07:05.142875 ovl_layer_smi_id_en
9396 11:07:05.143384 ccorr_config
9397 11:07:05.143714 aal_config
9398 11:07:05.146011 gamma_config
9399 11:07:05.146436 postmask_config
9400 11:07:05.149182 dither_config
9401 11:07:05.152708 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9402 11:07:05.159375 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9403 11:07:05.162673 Root Device init finished in 555 msecs
9404 11:07:05.163173 CPU_CLUSTER: 0 init
9405 11:07:05.172649 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9406 11:07:05.176105 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9407 11:07:05.179812 APU_MBOX 0x190000b0 = 0x10001
9408 11:07:05.182797 APU_MBOX 0x190001b0 = 0x10001
9409 11:07:05.186087 APU_MBOX 0x190005b0 = 0x10001
9410 11:07:05.189596 APU_MBOX 0x190006b0 = 0x10001
9411 11:07:05.192537 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9412 11:07:05.204897 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9413 11:07:05.217360 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9414 11:07:05.223982 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9415 11:07:05.235848 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9416 11:07:05.245106 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9417 11:07:05.248215 CPU_CLUSTER: 0 init finished in 81 msecs
9418 11:07:05.251639 Devices initialized
9419 11:07:05.255211 Show all devs... After init.
9420 11:07:05.255720 Root Device: enabled 1
9421 11:07:05.258004 CPU_CLUSTER: 0: enabled 1
9422 11:07:05.261337 CPU: 00: enabled 1
9423 11:07:05.265007 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9424 11:07:05.267774 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9425 11:07:05.271457 ELOG: NV offset 0x57f000 size 0x1000
9426 11:07:05.277946 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9427 11:07:05.285204 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9428 11:07:05.288516 ELOG: Event(17) added with size 13 at 2024-07-10 11:06:58 UTC
9429 11:07:05.291711 out: cmd=0x121: 03 db 21 01 00 00 00 00
9430 11:07:05.294764 in-header: 03 36 00 00 2c 00 00 00
9431 11:07:05.308180 in-data: 08 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9432 11:07:05.315261 ELOG: Event(A1) added with size 10 at 2024-07-10 11:06:58 UTC
9433 11:07:05.321645 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9434 11:07:05.328288 ELOG: Event(A0) added with size 9 at 2024-07-10 11:06:58 UTC
9435 11:07:05.331918 elog_add_boot_reason: Logged dev mode boot
9436 11:07:05.335317 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9437 11:07:05.338430 Finalize devices...
9438 11:07:05.338941 Devices finalized
9439 11:07:05.344971 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9440 11:07:05.348320 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9441 11:07:05.351760 in-header: 03 07 00 00 08 00 00 00
9442 11:07:05.355058 in-data: aa e4 47 04 13 02 00 00
9443 11:07:05.355568 Chrome EC: UHEPI supported
9444 11:07:05.361773 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9445 11:07:05.365503 in-header: 03 a9 00 00 08 00 00 00
9446 11:07:05.368676 in-data: 84 60 60 08 00 00 00 00
9447 11:07:05.375064 ELOG: Event(91) added with size 10 at 2024-07-10 11:06:58 UTC
9448 11:07:05.378793 Chrome EC: clear events_b mask to 0x0000000020004000
9449 11:07:05.385890 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9450 11:07:05.390281 in-header: 03 fd 00 00 00 00 00 00
9451 11:07:05.393468 in-data:
9452 11:07:05.397060 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9453 11:07:05.400071 Writing coreboot table at 0xffe64000
9454 11:07:05.403886 0. 000000000010a000-0000000000113fff: RAMSTAGE
9455 11:07:05.407345 1. 0000000040000000-00000000400fffff: RAM
9456 11:07:05.413840 2. 0000000040100000-000000004032afff: RAMSTAGE
9457 11:07:05.417492 3. 000000004032b000-00000000545fffff: RAM
9458 11:07:05.420584 4. 0000000054600000-000000005465ffff: BL31
9459 11:07:05.423629 5. 0000000054660000-00000000ffe63fff: RAM
9460 11:07:05.430387 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9461 11:07:05.433823 7. 0000000100000000-000000023fffffff: RAM
9462 11:07:05.436747 Passing 5 GPIOs to payload:
9463 11:07:05.440328 NAME | PORT | POLARITY | VALUE
9464 11:07:05.443997 EC in RW | 0x000000aa | low | undefined
9465 11:07:05.450458 EC interrupt | 0x00000005 | low | undefined
9466 11:07:05.453385 TPM interrupt | 0x000000ab | high | undefined
9467 11:07:05.460475 SD card detect | 0x00000011 | high | undefined
9468 11:07:05.463912 speaker enable | 0x00000093 | high | undefined
9469 11:07:05.467045 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9470 11:07:05.470376 in-header: 03 f9 00 00 02 00 00 00
9471 11:07:05.473409 in-data: 02 00
9472 11:07:05.473919 ADC[4]: Raw value=900663 ID=7
9473 11:07:05.477045 ADC[3]: Raw value=213179 ID=1
9474 11:07:05.480187 RAM Code: 0x71
9475 11:07:05.480691 ADC[6]: Raw value=74502 ID=0
9476 11:07:05.483818 ADC[5]: Raw value=212072 ID=1
9477 11:07:05.486613 SKU Code: 0x1
9478 11:07:05.489915 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 746d
9479 11:07:05.493698 coreboot table: 964 bytes.
9480 11:07:05.496791 IMD ROOT 0. 0xfffff000 0x00001000
9481 11:07:05.500731 IMD SMALL 1. 0xffffe000 0x00001000
9482 11:07:05.503715 RO MCACHE 2. 0xffffc000 0x00001104
9483 11:07:05.506857 CONSOLE 3. 0xfff7c000 0x00080000
9484 11:07:05.510221 FMAP 4. 0xfff7b000 0x00000452
9485 11:07:05.513669 TIME STAMP 5. 0xfff7a000 0x00000910
9486 11:07:05.516855 VBOOT WORK 6. 0xfff66000 0x00014000
9487 11:07:05.520333 RAMOOPS 7. 0xffe66000 0x00100000
9488 11:07:05.523507 COREBOOT 8. 0xffe64000 0x00002000
9489 11:07:05.524019 IMD small region:
9490 11:07:05.526923 IMD ROOT 0. 0xffffec00 0x00000400
9491 11:07:05.533812 VPD 1. 0xffffeb80 0x0000006c
9492 11:07:05.536921 MMC STATUS 2. 0xffffeb60 0x00000004
9493 11:07:05.540055 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9494 11:07:05.546519 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9495 11:07:05.587044 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9496 11:07:05.590227 Checking segment from ROM address 0x40100000
9497 11:07:05.593781 Checking segment from ROM address 0x4010001c
9498 11:07:05.600075 Loading segment from ROM address 0x40100000
9499 11:07:05.600582 code (compression=0)
9500 11:07:05.610021 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9501 11:07:05.616752 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9502 11:07:05.617325 it's not compressed!
9503 11:07:05.623904 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9504 11:07:05.630058 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9505 11:07:05.647567 Loading segment from ROM address 0x4010001c
9506 11:07:05.648100 Entry Point 0x80000000
9507 11:07:05.650490 Loaded segments
9508 11:07:05.653856 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9509 11:07:05.660565 Jumping to boot code at 0x80000000(0xffe64000)
9510 11:07:05.667240 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9511 11:07:05.673691 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9512 11:07:05.682039 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9513 11:07:05.685109 Checking segment from ROM address 0x40100000
9514 11:07:05.688504 Checking segment from ROM address 0x4010001c
9515 11:07:05.694935 Loading segment from ROM address 0x40100000
9516 11:07:05.695432 code (compression=1)
9517 11:07:05.702033 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9518 11:07:05.711552 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9519 11:07:05.712062 using LZMA
9520 11:07:05.720327 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9521 11:07:05.727130 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9522 11:07:05.730027 Loading segment from ROM address 0x4010001c
9523 11:07:05.730546 Entry Point 0x54601000
9524 11:07:05.733360 Loaded segments
9525 11:07:05.737048 NOTICE: MT8192 bl31_setup
9526 11:07:05.743821 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9527 11:07:05.747205 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9528 11:07:05.750376 WARNING: region 0:
9529 11:07:05.753392 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 11:07:05.753902 WARNING: region 1:
9531 11:07:05.760514 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9532 11:07:05.763293 WARNING: region 2:
9533 11:07:05.767306 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9534 11:07:05.770360 WARNING: region 3:
9535 11:07:05.773836 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9536 11:07:05.777040 WARNING: region 4:
9537 11:07:05.783763 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 11:07:05.784274 WARNING: region 5:
9539 11:07:05.787320 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 11:07:05.790139 WARNING: region 6:
9541 11:07:05.793622 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 11:07:05.794055 WARNING: region 7:
9543 11:07:05.800269 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 11:07:05.806924 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9545 11:07:05.809951 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9546 11:07:05.813184 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9547 11:07:05.819931 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9548 11:07:05.823318 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9549 11:07:05.826747 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9550 11:07:05.833544 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9551 11:07:05.836518 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9552 11:07:05.843149 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9553 11:07:05.846499 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9554 11:07:05.850058 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9555 11:07:05.856160 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9556 11:07:05.859846 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9557 11:07:05.863043 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9558 11:07:05.869592 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9559 11:07:05.873024 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9560 11:07:05.880110 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9561 11:07:05.883224 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9562 11:07:05.886695 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9563 11:07:05.893183 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9564 11:07:05.896631 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9565 11:07:05.899964 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9566 11:07:05.906699 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9567 11:07:05.909791 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9568 11:07:05.916535 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9569 11:07:05.920038 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9570 11:07:05.926532 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9571 11:07:05.929870 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9572 11:07:05.933348 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9573 11:07:05.939990 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9574 11:07:05.943212 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9575 11:07:05.946749 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9576 11:07:05.953066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9577 11:07:05.956529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9578 11:07:05.959956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9579 11:07:05.963231 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9580 11:07:05.969681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9581 11:07:05.973285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9582 11:07:05.976411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9583 11:07:05.980200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9584 11:07:05.986655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9585 11:07:05.989879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9586 11:07:05.993208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9587 11:07:05.996192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9588 11:07:06.003113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9589 11:07:06.006395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9590 11:07:06.010226 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9591 11:07:06.013278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9592 11:07:06.019843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9593 11:07:06.022862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9594 11:07:06.029840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9595 11:07:06.033211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9596 11:07:06.039662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9597 11:07:06.043196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9598 11:07:06.046189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9599 11:07:06.053010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9600 11:07:06.056296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9601 11:07:06.062745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9602 11:07:06.066399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9603 11:07:06.073051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9604 11:07:06.076236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9605 11:07:06.082864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9606 11:07:06.086616 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9607 11:07:06.090110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9608 11:07:06.096235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9609 11:07:06.099480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9610 11:07:06.106044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9611 11:07:06.109609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9612 11:07:06.116163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9613 11:07:06.119685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9614 11:07:06.123190 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9615 11:07:06.129630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9616 11:07:06.133184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9617 11:07:06.139717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9618 11:07:06.142497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9619 11:07:06.149563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9620 11:07:06.152631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9621 11:07:06.156261 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9622 11:07:06.162773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9623 11:07:06.166182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9624 11:07:06.173294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9625 11:07:06.176172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9626 11:07:06.182824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9627 11:07:06.186125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9628 11:07:06.189376 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9629 11:07:06.196235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9630 11:07:06.199694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9631 11:07:06.205985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9632 11:07:06.209845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9633 11:07:06.216740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9634 11:07:06.219782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9635 11:07:06.223172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9636 11:07:06.229846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9637 11:07:06.233375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9638 11:07:06.239865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9639 11:07:06.243375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9640 11:07:06.246068 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9641 11:07:06.252904 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9642 11:07:06.256702 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9643 11:07:06.259749 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9644 11:07:06.262818 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9645 11:07:06.269517 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9646 11:07:06.272875 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9647 11:07:06.279603 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9648 11:07:06.282890 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9649 11:07:06.286212 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9650 11:07:06.293155 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9651 11:07:06.296352 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9652 11:07:06.302949 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9653 11:07:06.306373 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9654 11:07:06.309874 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9655 11:07:06.316321 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9656 11:07:06.319612 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9657 11:07:06.326185 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9658 11:07:06.329777 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9659 11:07:06.333190 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9660 11:07:06.339570 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9661 11:07:06.342597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9662 11:07:06.346304 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9663 11:07:06.352713 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9664 11:07:06.356418 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9665 11:07:06.359915 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9666 11:07:06.362920 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9667 11:07:06.369331 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9668 11:07:06.372810 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9669 11:07:06.376418 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9670 11:07:06.382478 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9671 11:07:06.386019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9672 11:07:06.392589 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9673 11:07:06.395963 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9674 11:07:06.399185 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9675 11:07:06.405831 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9676 11:07:06.409173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9677 11:07:06.415886 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9678 11:07:06.418802 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9679 11:07:06.422759 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9680 11:07:06.429535 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9681 11:07:06.432443 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9682 11:07:06.435975 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9683 11:07:06.442347 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9684 11:07:06.446018 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9685 11:07:06.452142 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9686 11:07:06.455821 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9687 11:07:06.458937 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9688 11:07:06.465992 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9689 11:07:06.469044 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9690 11:07:06.475299 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9691 11:07:06.479123 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9692 11:07:06.482325 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9693 11:07:06.488737 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9694 11:07:06.492155 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9695 11:07:06.495882 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9696 11:07:06.502541 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9697 11:07:06.505949 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9698 11:07:06.512349 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9699 11:07:06.515411 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9700 11:07:06.518981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9701 11:07:06.525260 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9702 11:07:06.528951 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9703 11:07:06.535663 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9704 11:07:06.538823 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9705 11:07:06.542095 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9706 11:07:06.548863 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9707 11:07:06.552032 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9708 11:07:06.559156 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9709 11:07:06.562299 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9710 11:07:06.565433 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9711 11:07:06.572188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9712 11:07:06.575536 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9713 11:07:06.579265 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9714 11:07:06.585722 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9715 11:07:06.588653 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9716 11:07:06.595412 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9717 11:07:06.598374 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9718 11:07:06.602109 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9719 11:07:06.608456 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9720 11:07:06.611655 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9721 11:07:06.618778 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9722 11:07:06.622105 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9723 11:07:06.625606 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9724 11:07:06.632180 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9725 11:07:06.635296 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9726 11:07:06.641873 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9727 11:07:06.645555 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9728 11:07:06.648514 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9729 11:07:06.655461 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9730 11:07:06.658658 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9731 11:07:06.662059 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9732 11:07:06.669118 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9733 11:07:06.672402 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9734 11:07:06.678741 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9735 11:07:06.681824 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9736 11:07:06.688481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9737 11:07:06.691663 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9738 11:07:06.695501 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9739 11:07:06.701881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9740 11:07:06.705177 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9741 11:07:06.711652 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9742 11:07:06.714835 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9743 11:07:06.721374 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9744 11:07:06.725074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9745 11:07:06.728194 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9746 11:07:06.735125 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9747 11:07:06.737950 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9748 11:07:06.745333 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9749 11:07:06.748101 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9750 11:07:06.751780 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9751 11:07:06.758137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9752 11:07:06.761545 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9753 11:07:06.768049 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9754 11:07:06.771470 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9755 11:07:06.778015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9756 11:07:06.781532 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9757 11:07:06.784757 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9758 11:07:06.791553 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9759 11:07:06.794578 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9760 11:07:06.801689 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9761 11:07:06.804925 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9762 11:07:06.807800 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9763 11:07:06.814857 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9764 11:07:06.818112 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9765 11:07:06.824896 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9766 11:07:06.828057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9767 11:07:06.831646 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9768 11:07:06.837825 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9769 11:07:06.841465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9770 11:07:06.847879 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9771 11:07:06.851346 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9772 11:07:06.854383 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9773 11:07:06.861483 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9774 11:07:06.864893 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9775 11:07:06.868009 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9776 11:07:06.871397 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9777 11:07:06.878100 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9778 11:07:06.881713 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9779 11:07:06.884535 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9780 11:07:06.891226 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9781 11:07:06.894360 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9782 11:07:06.897735 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9783 11:07:06.904189 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9784 11:07:06.907909 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9785 11:07:06.914454 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9786 11:07:06.917784 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9787 11:07:06.921192 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9788 11:07:06.928425 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9789 11:07:06.931431 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9790 11:07:06.934849 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9791 11:07:06.941638 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9792 11:07:06.944739 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9793 11:07:06.948203 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9794 11:07:06.954761 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9795 11:07:06.958321 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9796 11:07:06.964454 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9797 11:07:06.967826 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9798 11:07:06.971458 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9799 11:07:06.977652 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9800 11:07:06.981295 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9801 11:07:06.984461 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9802 11:07:06.991261 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9803 11:07:06.994188 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9804 11:07:06.997974 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9805 11:07:07.004956 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9806 11:07:07.007671 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9807 11:07:07.011030 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9808 11:07:07.017746 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9809 11:07:07.021413 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9810 11:07:07.027986 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9811 11:07:07.031115 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9812 11:07:07.034495 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9813 11:07:07.037829 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9814 11:07:07.044425 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9815 11:07:07.047889 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9816 11:07:07.051053 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9817 11:07:07.054357 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9818 11:07:07.061221 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9819 11:07:07.064364 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9820 11:07:07.067515 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9821 11:07:07.071312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9822 11:07:07.077791 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9823 11:07:07.081356 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9824 11:07:07.084119 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9825 11:07:07.087616 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9826 11:07:07.094553 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9827 11:07:07.097384 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9828 11:07:07.104285 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9829 11:07:07.107511 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9830 11:07:07.111096 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9831 11:07:07.118080 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9832 11:07:07.120958 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9833 11:07:07.127850 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9834 11:07:07.131399 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9835 11:07:07.134357 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9836 11:07:07.141037 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9837 11:07:07.144228 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9838 11:07:07.151295 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9839 11:07:07.154372 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9840 11:07:07.160912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9841 11:07:07.164620 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9842 11:07:07.167551 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9843 11:07:07.174166 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9844 11:07:07.177732 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9845 11:07:07.184424 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9846 11:07:07.187775 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9847 11:07:07.191204 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9848 11:07:07.197372 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9849 11:07:07.200745 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9850 11:07:07.204152 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9851 11:07:07.210537 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9852 11:07:07.214012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9853 11:07:07.220982 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9854 11:07:07.224470 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9855 11:07:07.231077 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9856 11:07:07.234228 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9857 11:07:07.237740 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9858 11:07:07.244182 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9859 11:07:07.247877 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9860 11:07:07.254042 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9861 11:07:07.257515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9862 11:07:07.260979 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9863 11:07:07.267828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9864 11:07:07.270999 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9865 11:07:07.278011 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9866 11:07:07.280880 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9867 11:07:07.284146 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9868 11:07:07.291056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9869 11:07:07.294494 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9870 11:07:07.300965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9871 11:07:07.304153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9872 11:07:07.307369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9873 11:07:07.314227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9874 11:07:07.317322 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9875 11:07:07.324008 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9876 11:07:07.327935 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9877 11:07:07.330906 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9878 11:07:07.337822 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9879 11:07:07.341047 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9880 11:07:07.347588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9881 11:07:07.351042 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9882 11:07:07.354154 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9883 11:07:07.360810 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9884 11:07:07.364353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9885 11:07:07.370671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9886 11:07:07.374043 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9887 11:07:07.377676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9888 11:07:07.384577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9889 11:07:07.387401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9890 11:07:07.394048 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9891 11:07:07.397388 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9892 11:07:07.400634 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9893 11:07:07.407528 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9894 11:07:07.410500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9895 11:07:07.417444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9896 11:07:07.421296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9897 11:07:07.424016 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9898 11:07:07.430663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9899 11:07:07.434579 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9900 11:07:07.440834 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9901 11:07:07.443941 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9902 11:07:07.451001 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9903 11:07:07.454199 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9904 11:07:07.461085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9905 11:07:07.463898 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9906 11:07:07.467271 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9907 11:07:07.474021 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9908 11:07:07.477238 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9909 11:07:07.484050 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9910 11:07:07.487712 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9911 11:07:07.494019 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9912 11:07:07.496743 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9913 11:07:07.500779 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9914 11:07:07.507135 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9915 11:07:07.510399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9916 11:07:07.517237 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9917 11:07:07.520374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9918 11:07:07.527045 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9919 11:07:07.530057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9920 11:07:07.536966 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9921 11:07:07.540213 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9922 11:07:07.543728 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9923 11:07:07.550136 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9924 11:07:07.553804 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9925 11:07:07.560409 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9926 11:07:07.564122 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9927 11:07:07.570290 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9928 11:07:07.573510 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9929 11:07:07.577087 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9930 11:07:07.583473 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9931 11:07:07.586526 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9932 11:07:07.593509 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9933 11:07:07.596415 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9934 11:07:07.603382 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9935 11:07:07.606879 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9936 11:07:07.609980 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9937 11:07:07.616679 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9938 11:07:07.619676 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9939 11:07:07.626429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9940 11:07:07.629828 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9941 11:07:07.636478 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9942 11:07:07.639745 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9943 11:07:07.643180 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9944 11:07:07.649926 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9945 11:07:07.653357 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9946 11:07:07.656489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9947 11:07:07.663137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9948 11:07:07.666825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9949 11:07:07.673370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9950 11:07:07.676831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9951 11:07:07.683563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9952 11:07:07.687001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9953 11:07:07.693929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9954 11:07:07.696964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9955 11:07:07.703664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9956 11:07:07.707168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9957 11:07:07.713497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9958 11:07:07.717317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9959 11:07:07.723887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9960 11:07:07.726997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9961 11:07:07.733834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9962 11:07:07.736487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9963 11:07:07.740087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9964 11:07:07.746871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9965 11:07:07.750098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9966 11:07:07.757229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9967 11:07:07.760027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9968 11:07:07.766638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9969 11:07:07.770243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9970 11:07:07.776799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9971 11:07:07.780517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9972 11:07:07.786594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9973 11:07:07.790275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9974 11:07:07.796646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9975 11:07:07.799831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9976 11:07:07.807062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9977 11:07:07.809935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9978 11:07:07.816824 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9979 11:07:07.817382 INFO: [APUAPC] vio 0
9980 11:07:07.823809 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9981 11:07:07.827086 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9982 11:07:07.830223 INFO: [APUAPC] D0_APC_0: 0x400510
9983 11:07:07.833823 INFO: [APUAPC] D0_APC_1: 0x0
9984 11:07:07.836917 INFO: [APUAPC] D0_APC_2: 0x1540
9985 11:07:07.840257 INFO: [APUAPC] D0_APC_3: 0x0
9986 11:07:07.843698 INFO: [APUAPC] D1_APC_0: 0xffffffff
9987 11:07:07.847058 INFO: [APUAPC] D1_APC_1: 0xffffffff
9988 11:07:07.850283 INFO: [APUAPC] D1_APC_2: 0x3fffff
9989 11:07:07.853448 INFO: [APUAPC] D1_APC_3: 0x0
9990 11:07:07.857083 INFO: [APUAPC] D2_APC_0: 0xffffffff
9991 11:07:07.860201 INFO: [APUAPC] D2_APC_1: 0xffffffff
9992 11:07:07.863303 INFO: [APUAPC] D2_APC_2: 0x3fffff
9993 11:07:07.866855 INFO: [APUAPC] D2_APC_3: 0x0
9994 11:07:07.869973 INFO: [APUAPC] D3_APC_0: 0xffffffff
9995 11:07:07.873437 INFO: [APUAPC] D3_APC_1: 0xffffffff
9996 11:07:07.876897 INFO: [APUAPC] D3_APC_2: 0x3fffff
9997 11:07:07.877458 INFO: [APUAPC] D3_APC_3: 0x0
9998 11:07:07.883690 INFO: [APUAPC] D4_APC_0: 0xffffffff
9999 11:07:07.886636 INFO: [APUAPC] D4_APC_1: 0xffffffff
10000 11:07:07.890304 INFO: [APUAPC] D4_APC_2: 0x3fffff
10001 11:07:07.890811 INFO: [APUAPC] D4_APC_3: 0x0
10002 11:07:07.893502 INFO: [APUAPC] D5_APC_0: 0xffffffff
10003 11:07:07.897228 INFO: [APUAPC] D5_APC_1: 0xffffffff
10004 11:07:07.900287 INFO: [APUAPC] D5_APC_2: 0x3fffff
10005 11:07:07.903669 INFO: [APUAPC] D5_APC_3: 0x0
10006 11:07:07.907024 INFO: [APUAPC] D6_APC_0: 0xffffffff
10007 11:07:07.909901 INFO: [APUAPC] D6_APC_1: 0xffffffff
10008 11:07:07.913462 INFO: [APUAPC] D6_APC_2: 0x3fffff
10009 11:07:07.917084 INFO: [APUAPC] D6_APC_3: 0x0
10010 11:07:07.920167 INFO: [APUAPC] D7_APC_0: 0xffffffff
10011 11:07:07.923500 INFO: [APUAPC] D7_APC_1: 0xffffffff
10012 11:07:07.926811 INFO: [APUAPC] D7_APC_2: 0x3fffff
10013 11:07:07.930486 INFO: [APUAPC] D7_APC_3: 0x0
10014 11:07:07.933586 INFO: [APUAPC] D8_APC_0: 0xffffffff
10015 11:07:07.936587 INFO: [APUAPC] D8_APC_1: 0xffffffff
10016 11:07:07.940117 INFO: [APUAPC] D8_APC_2: 0x3fffff
10017 11:07:07.943701 INFO: [APUAPC] D8_APC_3: 0x0
10018 11:07:07.946766 INFO: [APUAPC] D9_APC_0: 0xffffffff
10019 11:07:07.950261 INFO: [APUAPC] D9_APC_1: 0xffffffff
10020 11:07:07.953412 INFO: [APUAPC] D9_APC_2: 0x3fffff
10021 11:07:07.956575 INFO: [APUAPC] D9_APC_3: 0x0
10022 11:07:07.960121 INFO: [APUAPC] D10_APC_0: 0xffffffff
10023 11:07:07.963560 INFO: [APUAPC] D10_APC_1: 0xffffffff
10024 11:07:07.966844 INFO: [APUAPC] D10_APC_2: 0x3fffff
10025 11:07:07.970140 INFO: [APUAPC] D10_APC_3: 0x0
10026 11:07:07.973294 INFO: [APUAPC] D11_APC_0: 0xffffffff
10027 11:07:07.976842 INFO: [APUAPC] D11_APC_1: 0xffffffff
10028 11:07:07.979967 INFO: [APUAPC] D11_APC_2: 0x3fffff
10029 11:07:07.983577 INFO: [APUAPC] D11_APC_3: 0x0
10030 11:07:07.986946 INFO: [APUAPC] D12_APC_0: 0xffffffff
10031 11:07:07.989870 INFO: [APUAPC] D12_APC_1: 0xffffffff
10032 11:07:07.993458 INFO: [APUAPC] D12_APC_2: 0x3fffff
10033 11:07:07.996833 INFO: [APUAPC] D12_APC_3: 0x0
10034 11:07:08.000259 INFO: [APUAPC] D13_APC_0: 0xffffffff
10035 11:07:08.003766 INFO: [APUAPC] D13_APC_1: 0xffffffff
10036 11:07:08.006880 INFO: [APUAPC] D13_APC_2: 0x3fffff
10037 11:07:08.010166 INFO: [APUAPC] D13_APC_3: 0x0
10038 11:07:08.013610 INFO: [APUAPC] D14_APC_0: 0xffffffff
10039 11:07:08.016743 INFO: [APUAPC] D14_APC_1: 0xffffffff
10040 11:07:08.020310 INFO: [APUAPC] D14_APC_2: 0x3fffff
10041 11:07:08.023465 INFO: [APUAPC] D14_APC_3: 0x0
10042 11:07:08.027173 INFO: [APUAPC] D15_APC_0: 0xffffffff
10043 11:07:08.030077 INFO: [APUAPC] D15_APC_1: 0xffffffff
10044 11:07:08.033650 INFO: [APUAPC] D15_APC_2: 0x3fffff
10045 11:07:08.036996 INFO: [APUAPC] D15_APC_3: 0x0
10046 11:07:08.040194 INFO: [APUAPC] APC_CON: 0x4
10047 11:07:08.043901 INFO: [NOCDAPC] D0_APC_0: 0x0
10048 11:07:08.046460 INFO: [NOCDAPC] D0_APC_1: 0x0
10049 11:07:08.046890 INFO: [NOCDAPC] D1_APC_0: 0x0
10050 11:07:08.050088 INFO: [NOCDAPC] D1_APC_1: 0xfff
10051 11:07:08.053593 INFO: [NOCDAPC] D2_APC_0: 0x0
10052 11:07:08.056529 INFO: [NOCDAPC] D2_APC_1: 0xfff
10053 11:07:08.059819 INFO: [NOCDAPC] D3_APC_0: 0x0
10054 11:07:08.063276 INFO: [NOCDAPC] D3_APC_1: 0xfff
10055 11:07:08.066475 INFO: [NOCDAPC] D4_APC_0: 0x0
10056 11:07:08.069473 INFO: [NOCDAPC] D4_APC_1: 0xfff
10057 11:07:08.072914 INFO: [NOCDAPC] D5_APC_0: 0x0
10058 11:07:08.076612 INFO: [NOCDAPC] D5_APC_1: 0xfff
10059 11:07:08.080072 INFO: [NOCDAPC] D6_APC_0: 0x0
10060 11:07:08.080609 INFO: [NOCDAPC] D6_APC_1: 0xfff
10061 11:07:08.082990 INFO: [NOCDAPC] D7_APC_0: 0x0
10062 11:07:08.086724 INFO: [NOCDAPC] D7_APC_1: 0xfff
10063 11:07:08.090081 INFO: [NOCDAPC] D8_APC_0: 0x0
10064 11:07:08.093023 INFO: [NOCDAPC] D8_APC_1: 0xfff
10065 11:07:08.096570 INFO: [NOCDAPC] D9_APC_0: 0x0
10066 11:07:08.099459 INFO: [NOCDAPC] D9_APC_1: 0xfff
10067 11:07:08.103231 INFO: [NOCDAPC] D10_APC_0: 0x0
10068 11:07:08.106504 INFO: [NOCDAPC] D10_APC_1: 0xfff
10069 11:07:08.109706 INFO: [NOCDAPC] D11_APC_0: 0x0
10070 11:07:08.113238 INFO: [NOCDAPC] D11_APC_1: 0xfff
10071 11:07:08.116134 INFO: [NOCDAPC] D12_APC_0: 0x0
10072 11:07:08.119937 INFO: [NOCDAPC] D12_APC_1: 0xfff
10073 11:07:08.120450 INFO: [NOCDAPC] D13_APC_0: 0x0
10074 11:07:08.123112 INFO: [NOCDAPC] D13_APC_1: 0xfff
10075 11:07:08.126722 INFO: [NOCDAPC] D14_APC_0: 0x0
10076 11:07:08.129825 INFO: [NOCDAPC] D14_APC_1: 0xfff
10077 11:07:08.132959 INFO: [NOCDAPC] D15_APC_0: 0x0
10078 11:07:08.136605 INFO: [NOCDAPC] D15_APC_1: 0xfff
10079 11:07:08.140050 INFO: [NOCDAPC] APC_CON: 0x4
10080 11:07:08.143191 INFO: [APUAPC] set_apusys_apc done
10081 11:07:08.146376 INFO: [DEVAPC] devapc_init done
10082 11:07:08.150047 INFO: GICv3 without legacy support detected.
10083 11:07:08.153093 INFO: ARM GICv3 driver initialized in EL3
10084 11:07:08.156705 INFO: Maximum SPI INTID supported: 639
10085 11:07:08.163323 INFO: BL31: Initializing runtime services
10086 11:07:08.166859 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10087 11:07:08.169625 INFO: SPM: enable CPC mode
10088 11:07:08.176395 INFO: mcdi ready for mcusys-off-idle and system suspend
10089 11:07:08.179697 INFO: BL31: Preparing for EL3 exit to normal world
10090 11:07:08.183067 INFO: Entry point address = 0x80000000
10091 11:07:08.186427 INFO: SPSR = 0x8
10092 11:07:08.192237
10093 11:07:08.192737
10094 11:07:08.193070
10095 11:07:08.195562 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10096 11:07:08.196051 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10097 11:07:08.196444 Setting prompt string to ['asurada:']
10098 11:07:08.196790 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10099 11:07:08.197469 Starting depthcharge on Spherion...
10100 11:07:08.197817
10101 11:07:08.198121 Wipe memory regions:
10102 11:07:08.198411
10103 11:07:08.198751 [0x00000040000000, 0x00000054600000)
10104 11:07:08.320692
10105 11:07:08.321242 [0x00000054660000, 0x00000080000000)
10106 11:07:08.581279
10107 11:07:08.581792 [0x000000821a7280, 0x000000ffe64000)
10108 11:07:09.326045
10109 11:07:09.326557 [0x00000100000000, 0x00000240000000)
10110 11:07:11.216312
10111 11:07:11.219296 Initializing XHCI USB controller at 0x11200000.
10112 11:07:12.258083
10113 11:07:12.261021 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10114 11:07:12.261571
10115 11:07:12.261915
10116 11:07:12.262611 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10117 11:07:12.263004 Sending line: 'tftpboot 192.168.201.1 14786841/tftp-deploy-2dy1oftf/kernel/image.itb 14786841/tftp-deploy-2dy1oftf/kernel/cmdline '
10119 11:07:12.364466 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 11:07:12.364912 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10121 11:07:12.369565 asurada: tftpboot 192.168.201.1 14786841/tftp-deploy-2dy1oftf/kernel/image.ittp-deploy-2dy1oftf/kernel/cmdline
10122 11:07:12.370106
10123 11:07:12.370454 Waiting for link
10124 11:07:12.528060
10125 11:07:12.528569 R8152: Initializing
10126 11:07:12.528910
10127 11:07:12.531210 Version 9 (ocp_data = 6010)
10128 11:07:12.531718
10129 11:07:12.534300 R8152: Done initializing
10130 11:07:12.534808
10131 11:07:12.535146 Adding net device
10132 11:07:14.668123
10133 11:07:14.668628 done.
10134 11:07:14.668964
10135 11:07:14.669416 MAC: 00:e0:4c:72:2d:d6
10136 11:07:14.669798
10137 11:07:14.671751 Sending DHCP discover... done.
10138 11:07:14.672257
10139 11:07:14.674665 Waiting for reply... done.
10140 11:07:14.675179
10141 11:07:14.677822 Sending DHCP request... done.
10142 11:07:14.678255
10143 11:07:14.684079 Waiting for reply... done.
10144 11:07:14.684312
10145 11:07:14.684444 My ip is 192.168.201.21
10146 11:07:14.684565
10147 11:07:14.688094 The DHCP server ip is 192.168.201.1
10148 11:07:14.688599
10149 11:07:14.695015 TFTP server IP predefined by user: 192.168.201.1
10150 11:07:14.695526
10151 11:07:14.700852 Bootfile predefined by user: 14786841/tftp-deploy-2dy1oftf/kernel/image.itb
10152 11:07:14.701404
10153 11:07:14.701749 Sending tftp read request... done.
10154 11:07:14.704457
10155 11:07:14.711544 Waiting for the transfer...
10156 11:07:14.712066
10157 11:07:15.112768 00000000 ################################################################
10158 11:07:15.113342
10159 11:07:15.511310 00080000 ################################################################
10160 11:07:15.511792
10161 11:07:15.910578 00100000 ################################################################
10162 11:07:15.910700
10163 11:07:16.206665 00180000 ################################################################
10164 11:07:16.206784
10165 11:07:16.510293 00200000 ################################################################
10166 11:07:16.510652
10167 11:07:16.889538 00280000 ################################################################
10168 11:07:16.890162
10169 11:07:17.271633 00300000 ################################################################
10170 11:07:17.272153
10171 11:07:17.655082 00380000 ################################################################
10172 11:07:17.655211
10173 11:07:17.956251 00400000 ################################################################
10174 11:07:17.956366
10175 11:07:18.258770 00480000 ################################################################
10176 11:07:18.258880
10177 11:07:18.552046 00500000 ################################################################
10178 11:07:18.552207
10179 11:07:18.812788 00580000 ################################################################
10180 11:07:18.812911
10181 11:07:19.109299 00600000 ################################################################
10182 11:07:19.109415
10183 11:07:19.406663 00680000 ################################################################
10184 11:07:19.406782
10185 11:07:19.677958 00700000 ################################################################
10186 11:07:19.678083
10187 11:07:19.973392 00780000 ################################################################
10188 11:07:19.973514
10189 11:07:20.336140 00800000 ################################################################
10190 11:07:20.336634
10191 11:07:20.711120 00880000 ################################################################
10192 11:07:20.711620
10193 11:07:21.144325 00900000 ################################################################
10194 11:07:21.144809
10195 11:07:21.549764 00980000 ################################################################
10196 11:07:21.550305
10197 11:07:21.940031 00a00000 ################################################################
10198 11:07:21.940629
10199 11:07:22.333818 00a80000 ################################################################
10200 11:07:22.334317
10201 11:07:22.660216 00b00000 ################################################################
10202 11:07:22.660366
10203 11:07:23.053260 00b80000 ################################################################
10204 11:07:23.053894
10205 11:07:23.431150 00c00000 ################################################################
10206 11:07:23.431623
10207 11:07:23.811214 00c80000 ################################################################
10208 11:07:23.811920
10209 11:07:24.125010 00d00000 ################################################################
10210 11:07:24.125141
10211 11:07:24.407068 00d80000 ################################################################
10212 11:07:24.407183
10213 11:07:24.689279 00e00000 ################################################################
10214 11:07:24.689399
10215 11:07:24.967647 00e80000 ################################################################
10216 11:07:24.967770
10217 11:07:25.250337 00f00000 ################################################################
10218 11:07:25.250451
10219 11:07:25.607967 00f80000 ################################################################
10220 11:07:25.608407
10221 11:07:25.900620 01000000 ################################################################
10222 11:07:25.900745
10223 11:07:26.156552 01080000 ################################################################
10224 11:07:26.156670
10225 11:07:26.426865 01100000 ################################################################
10226 11:07:26.426999
10227 11:07:26.728800 01180000 ################################################################
10228 11:07:26.728914
10229 11:07:27.024593 01200000 ################################################################
10230 11:07:27.024717
10231 11:07:27.326502 01280000 ################################################################
10232 11:07:27.326628
10233 11:07:27.630515 01300000 ################################################################
10234 11:07:27.630632
10235 11:07:27.934178 01380000 ################################################################
10236 11:07:27.934303
10237 11:07:28.206168 01400000 ################################################################
10238 11:07:28.206317
10239 11:07:28.466153 01480000 ################################################################
10240 11:07:28.466267
10241 11:07:28.719095 01500000 ################################################################
10242 11:07:28.719208
10243 11:07:28.979818 01580000 ################################################################
10244 11:07:28.979940
10245 11:07:29.258002 01600000 ################################################################
10246 11:07:29.258135
10247 11:07:29.543297 01680000 ################################################################
10248 11:07:29.543417
10249 11:07:29.832827 01700000 ################################################################
10250 11:07:29.832943
10251 11:07:30.096832 01780000 ################################################################
10252 11:07:30.096987
10253 11:07:30.348551 01800000 ################################################################
10254 11:07:30.348684
10255 11:07:30.617645 01880000 ################################################################
10256 11:07:30.617762
10257 11:07:30.913281 01900000 ################################################################
10258 11:07:30.913399
10259 11:07:31.191812 01980000 ################################################################
10260 11:07:31.191975
10261 11:07:31.494156 01a00000 ################################################################
10262 11:07:31.494285
10263 11:07:31.793663 01a80000 ################################################################
10264 11:07:31.793779
10265 11:07:32.132361 01b00000 ################################################################
10266 11:07:32.132487
10267 11:07:32.462669 01b80000 ################################################################
10268 11:07:32.462792
10269 11:07:32.751311 01c00000 ################################################################
10270 11:07:32.751423
10271 11:07:33.053418 01c80000 ################################################################
10272 11:07:33.053537
10273 11:07:33.345774 01d00000 ################################################################
10274 11:07:33.345899
10275 11:07:33.735472 01d80000 ################################################################
10276 11:07:33.735936
10277 11:07:34.045702 01e00000 ################################################### done.
10278 11:07:34.046191
10279 11:07:34.048926 The bootfile was 31874038 bytes long.
10280 11:07:34.049410
10281 11:07:34.052312 Sending tftp read request... done.
10282 11:07:34.052744
10283 11:07:34.056770 Waiting for the transfer...
10284 11:07:34.057235
10285 11:07:34.057572 00000000 # done.
10286 11:07:34.057893
10287 11:07:34.063438 Command line loaded dynamically from TFTP file: 14786841/tftp-deploy-2dy1oftf/kernel/cmdline
10288 11:07:34.063951
10289 11:07:34.086551 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786841/extract-nfsrootfs-36yjr3fx,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10290 11:07:34.086697
10291 11:07:34.089562 Loading FIT.
10292 11:07:34.089696
10293 11:07:34.089761 Image ramdisk-1 has 18708495 bytes.
10294 11:07:34.092855
10295 11:07:34.092994 Image fdt-1 has 47258 bytes.
10296 11:07:34.093059
10297 11:07:34.096057 Image kernel-1 has 13116259 bytes.
10298 11:07:34.096172
10299 11:07:34.105914 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10300 11:07:34.106059
10301 11:07:34.122853 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10302 11:07:34.123030
10303 11:07:34.129224 Choosing best match conf-1 for compat google,spherion-rev2.
10304 11:07:34.132786
10305 11:07:34.137669 Connected to device vid:did:rid of 1ae0:0028:00
10306 11:07:34.145515
10307 11:07:34.149019 tpm_get_response: command 0x17b, return code 0x0
10308 11:07:34.149496
10309 11:07:34.152896 ec_init: CrosEC protocol v3 supported (256, 248)
10310 11:07:34.156654
10311 11:07:34.159695 tpm_cleanup: add release locality here.
10312 11:07:34.160145
10313 11:07:34.160479 Shutting down all USB controllers.
10314 11:07:34.163750
10315 11:07:34.164255 Removing current net device
10316 11:07:34.164591
10317 11:07:34.170313 Exiting depthcharge with code 4 at timestamp: 55312659
10318 11:07:34.170824
10319 11:07:34.173249 LZMA decompressing kernel-1 to 0x821a6718
10320 11:07:34.173684
10321 11:07:34.176156 LZMA decompressing kernel-1 to 0x40000000
10322 11:07:35.792154
10323 11:07:35.792658 jumping to kernel
10324 11:07:35.794174 end: 2.2.4 bootloader-commands (duration 00:00:28) [common]
10325 11:07:35.794373 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10326 11:07:35.794523 Setting prompt string to ['Linux version [0-9]']
10327 11:07:35.794664 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10328 11:07:35.794805 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10329 11:07:35.873038
10330 11:07:35.876233 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10331 11:07:35.879841 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10332 11:07:35.880396 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10333 11:07:35.880777 Setting prompt string to []
10334 11:07:35.881203 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 11:07:35.881577 Using line separator: #'\n'#
10336 11:07:35.881897 No login prompt set.
10337 11:07:35.882389 Parsing kernel messages
10338 11:07:35.882693 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 11:07:35.883243 [login-action] Waiting for messages, (timeout 00:03:53)
10340 11:07:35.883569 Waiting using forced prompt support (timeout 00:01:56)
10341 11:07:35.898777 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10342 11:07:35.902043 [ 0.000000] random: crng init done
10343 11:07:35.906012 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10344 11:07:35.909073 [ 0.000000] efi: UEFI not found.
10345 11:07:35.919012 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10346 11:07:35.925437 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10347 11:07:35.935694 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10348 11:07:35.945740 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10349 11:07:35.952134 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10350 11:07:35.955021 [ 0.000000] printk: bootconsole [mtk8250] enabled
10351 11:07:35.963709 [ 0.000000] NUMA: No NUMA configuration found
10352 11:07:35.970583 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10353 11:07:35.976825 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10354 11:07:35.977397 [ 0.000000] Zone ranges:
10355 11:07:35.983520 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10356 11:07:35.986904 [ 0.000000] DMA32 empty
10357 11:07:35.993295 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10358 11:07:35.996767 [ 0.000000] Movable zone start for each node
10359 11:07:35.999996 [ 0.000000] Early memory node ranges
10360 11:07:36.007092 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10361 11:07:36.013104 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10362 11:07:36.019907 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10363 11:07:36.026051 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10364 11:07:36.032995 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10365 11:07:36.039629 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10366 11:07:36.097225 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10367 11:07:36.103957 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10368 11:07:36.110537 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10369 11:07:36.113823 [ 0.000000] psci: probing for conduit method from DT.
10370 11:07:36.120611 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10371 11:07:36.123341 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10372 11:07:36.130135 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10373 11:07:36.133898 [ 0.000000] psci: SMC Calling Convention v1.2
10374 11:07:36.140295 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10375 11:07:36.143657 [ 0.000000] Detected VIPT I-cache on CPU0
10376 11:07:36.150065 [ 0.000000] CPU features: detected: GIC system register CPU interface
10377 11:07:36.156796 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10378 11:07:36.163324 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10379 11:07:36.170069 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10380 11:07:36.176544 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10381 11:07:36.186330 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10382 11:07:36.189637 [ 0.000000] alternatives: applying boot alternatives
10383 11:07:36.196297 [ 0.000000] Fallback order for Node 0: 0
10384 11:07:36.203048 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 11:07:36.206298 [ 0.000000] Policy zone: Normal
10386 11:07:36.229455 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786841/extract-nfsrootfs-36yjr3fx,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10387 11:07:36.238942 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10388 11:07:36.250515 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10389 11:07:36.260644 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10390 11:07:36.267045 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10391 11:07:36.270350 <6>[ 0.000000] software IO TLB: area num 8.
10392 11:07:36.327437 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10393 11:07:36.476695 <6>[ 0.000000] Memory: 7945788K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406980K reserved, 32768K cma-reserved)
10394 11:07:36.483150 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10395 11:07:36.489747 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10396 11:07:36.492734 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10397 11:07:36.499690 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10398 11:07:36.505918 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10399 11:07:36.509715 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10400 11:07:36.519539 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10401 11:07:36.526108 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10402 11:07:36.532761 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10403 11:07:36.539445 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10404 11:07:36.542571 <6>[ 0.000000] GICv3: 608 SPIs implemented
10405 11:07:36.545902 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10406 11:07:36.553104 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10407 11:07:36.555944 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10408 11:07:36.562336 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10409 11:07:36.576003 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10410 11:07:36.588927 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10411 11:07:36.595350 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10412 11:07:36.603083 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10413 11:07:36.616132 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10414 11:07:36.622811 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10415 11:07:36.629751 <6>[ 0.009182] Console: colour dummy device 80x25
10416 11:07:36.639505 <6>[ 0.013914] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10417 11:07:36.646107 <6>[ 0.024419] pid_max: default: 32768 minimum: 301
10418 11:07:36.649394 <6>[ 0.029322] LSM: Security Framework initializing
10419 11:07:36.655861 <6>[ 0.034259] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 11:07:36.665793 <6>[ 0.042121] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 11:07:36.676019 <6>[ 0.051546] cblist_init_generic: Setting adjustable number of callback queues.
10422 11:07:36.679395 <6>[ 0.058986] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 11:07:36.689564 <6>[ 0.065326] cblist_init_generic: Setting adjustable number of callback queues.
10424 11:07:36.695895 <6>[ 0.072752] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 11:07:36.698795 <6>[ 0.079154] rcu: Hierarchical SRCU implementation.
10426 11:07:36.706089 <6>[ 0.084169] rcu: Max phase no-delay instances is 1000.
10427 11:07:36.712124 <6>[ 0.091204] EFI services will not be available.
10428 11:07:36.715530 <6>[ 0.096160] smp: Bringing up secondary CPUs ...
10429 11:07:36.724263 <6>[ 0.101215] Detected VIPT I-cache on CPU1
10430 11:07:36.730696 <6>[ 0.101286] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10431 11:07:36.737216 <6>[ 0.101318] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10432 11:07:36.740517 <6>[ 0.101665] Detected VIPT I-cache on CPU2
10433 11:07:36.750484 <6>[ 0.101718] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10434 11:07:36.757174 <6>[ 0.101736] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10435 11:07:36.760458 <6>[ 0.102000] Detected VIPT I-cache on CPU3
10436 11:07:36.766719 <6>[ 0.102049] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10437 11:07:36.773365 <6>[ 0.102064] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10438 11:07:36.776727 <6>[ 0.102371] CPU features: detected: Spectre-v4
10439 11:07:36.783545 <6>[ 0.102377] CPU features: detected: Spectre-BHB
10440 11:07:36.786819 <6>[ 0.102383] Detected PIPT I-cache on CPU4
10441 11:07:36.793344 <6>[ 0.102445] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10442 11:07:36.799769 <6>[ 0.102463] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10443 11:07:36.806709 <6>[ 0.102758] Detected PIPT I-cache on CPU5
10444 11:07:36.812925 <6>[ 0.102822] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10445 11:07:36.819861 <6>[ 0.102837] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10446 11:07:36.823124 <6>[ 0.103122] Detected PIPT I-cache on CPU6
10447 11:07:36.829831 <6>[ 0.103187] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10448 11:07:36.836638 <6>[ 0.103202] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10449 11:07:36.842947 <6>[ 0.103500] Detected PIPT I-cache on CPU7
10450 11:07:36.849696 <6>[ 0.103564] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10451 11:07:36.856580 <6>[ 0.103580] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10452 11:07:36.859885 <6>[ 0.103627] smp: Brought up 1 node, 8 CPUs
10453 11:07:36.866337 <6>[ 0.244992] SMP: Total of 8 processors activated.
10454 11:07:36.869542 <6>[ 0.249913] CPU features: detected: 32-bit EL0 Support
10455 11:07:36.879272 <6>[ 0.255310] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10456 11:07:36.885616 <6>[ 0.264111] CPU features: detected: Common not Private translations
10457 11:07:36.892371 <6>[ 0.270627] CPU features: detected: CRC32 instructions
10458 11:07:36.895786 <6>[ 0.275978] CPU features: detected: RCpc load-acquire (LDAPR)
10459 11:07:36.902466 <6>[ 0.281939] CPU features: detected: LSE atomic instructions
10460 11:07:36.909375 <6>[ 0.287720] CPU features: detected: Privileged Access Never
10461 11:07:36.915569 <6>[ 0.293500] CPU features: detected: RAS Extension Support
10462 11:07:36.922157 <6>[ 0.299108] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10463 11:07:36.925675 <6>[ 0.306331] CPU: All CPU(s) started at EL2
10464 11:07:36.932117 <6>[ 0.310648] alternatives: applying system-wide alternatives
10465 11:07:36.941894 <6>[ 0.321562] devtmpfs: initialized
10466 11:07:36.954115 <6>[ 0.330359] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10467 11:07:36.963758 <6>[ 0.340320] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10468 11:07:36.970681 <6>[ 0.348572] pinctrl core: initialized pinctrl subsystem
10469 11:07:36.974280 <6>[ 0.355253] DMI not present or invalid.
10470 11:07:36.980846 <6>[ 0.359609] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10471 11:07:36.990655 <6>[ 0.366509] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10472 11:07:36.997320 <6>[ 0.374094] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10473 11:07:37.006828 <6>[ 0.382327] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10474 11:07:37.010088 <6>[ 0.390575] audit: initializing netlink subsys (disabled)
10475 11:07:37.019990 <5>[ 0.396278] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10476 11:07:37.026809 <6>[ 0.397012] thermal_sys: Registered thermal governor 'step_wise'
10477 11:07:37.033641 <6>[ 0.404243] thermal_sys: Registered thermal governor 'power_allocator'
10478 11:07:37.036381 <6>[ 0.410498] cpuidle: using governor menu
10479 11:07:37.043198 <6>[ 0.421457] NET: Registered PF_QIPCRTR protocol family
10480 11:07:37.049812 <6>[ 0.426935] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10481 11:07:37.056645 <6>[ 0.434038] ASID allocator initialised with 32768 entries
10482 11:07:37.059786 <6>[ 0.440624] Serial: AMBA PL011 UART driver
10483 11:07:37.070291 <4>[ 0.449996] Trying to register duplicate clock ID: 134
10484 11:07:37.128013 <6>[ 0.511240] KASLR enabled
10485 11:07:37.142659 <6>[ 0.518869] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10486 11:07:37.149014 <6>[ 0.525880] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10487 11:07:37.155532 <6>[ 0.532369] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10488 11:07:37.162324 <6>[ 0.539373] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10489 11:07:37.168816 <6>[ 0.545858] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10490 11:07:37.175690 <6>[ 0.552863] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10491 11:07:37.182032 <6>[ 0.559350] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10492 11:07:37.189038 <6>[ 0.566354] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10493 11:07:37.192183 <6>[ 0.573822] ACPI: Interpreter disabled.
10494 11:07:37.200810 <6>[ 0.580266] iommu: Default domain type: Translated
10495 11:07:37.207014 <6>[ 0.585419] iommu: DMA domain TLB invalidation policy: strict mode
10496 11:07:37.211028 <5>[ 0.592071] SCSI subsystem initialized
10497 11:07:37.217600 <6>[ 0.596324] usbcore: registered new interface driver usbfs
10498 11:07:37.223446 <6>[ 0.602054] usbcore: registered new interface driver hub
10499 11:07:37.226997 <6>[ 0.607604] usbcore: registered new device driver usb
10500 11:07:37.233793 <6>[ 0.613730] pps_core: LinuxPPS API ver. 1 registered
10501 11:07:37.243806 <6>[ 0.618923] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10502 11:07:37.247217 <6>[ 0.628264] PTP clock support registered
10503 11:07:37.250102 <6>[ 0.632505] EDAC MC: Ver: 3.0.0
10504 11:07:37.258118 <6>[ 0.637705] FPGA manager framework
10505 11:07:37.261462 <6>[ 0.641383] Advanced Linux Sound Architecture Driver Initialized.
10506 11:07:37.265154 <6>[ 0.648171] vgaarb: loaded
10507 11:07:37.271956 <6>[ 0.651336] clocksource: Switched to clocksource arch_sys_counter
10508 11:07:37.278379 <5>[ 0.657780] VFS: Disk quotas dquot_6.6.0
10509 11:07:37.285104 <6>[ 0.661963] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10510 11:07:37.288339 <6>[ 0.669157] pnp: PnP ACPI: disabled
10511 11:07:37.296456 <6>[ 0.675860] NET: Registered PF_INET protocol family
10512 11:07:37.306091 <6>[ 0.681450] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10513 11:07:37.317321 <6>[ 0.693779] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10514 11:07:37.327433 <6>[ 0.702594] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10515 11:07:37.334034 <6>[ 0.710565] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10516 11:07:37.340562 <6>[ 0.719266] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10517 11:07:37.352991 <6>[ 0.728984] TCP: Hash tables configured (established 65536 bind 65536)
10518 11:07:37.359079 <6>[ 0.735853] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 11:07:37.365713 <6>[ 0.743048] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 11:07:37.372726 <6>[ 0.750752] NET: Registered PF_UNIX/PF_LOCAL protocol family
10521 11:07:37.379040 <6>[ 0.756896] RPC: Registered named UNIX socket transport module.
10522 11:07:37.382166 <6>[ 0.763051] RPC: Registered udp transport module.
10523 11:07:37.388971 <6>[ 0.767985] RPC: Registered tcp transport module.
10524 11:07:37.395881 <6>[ 0.772916] RPC: Registered tcp NFSv4.1 backchannel transport module.
10525 11:07:37.399043 <6>[ 0.779585] PCI: CLS 0 bytes, default 64
10526 11:07:37.402307 <6>[ 0.783939] Unpacking initramfs...
10527 11:07:37.427092 <6>[ 0.803434] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10528 11:07:37.437213 <6>[ 0.812078] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10529 11:07:37.440358 <6>[ 0.820934] kvm [1]: IPA Size Limit: 40 bits
10530 11:07:37.446945 <6>[ 0.825460] kvm [1]: GICv3: no GICV resource entry
10531 11:07:37.450074 <6>[ 0.830480] kvm [1]: disabling GICv2 emulation
10532 11:07:37.456661 <6>[ 0.835171] kvm [1]: GIC system register CPU interface enabled
10533 11:07:37.460136 <6>[ 0.841335] kvm [1]: vgic interrupt IRQ18
10534 11:07:37.466971 <6>[ 0.845681] kvm [1]: VHE mode initialized successfully
10535 11:07:37.473281 <5>[ 0.852211] Initialise system trusted keyrings
10536 11:07:37.479709 <6>[ 0.857013] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10537 11:07:37.487116 <6>[ 0.866967] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10538 11:07:37.493748 <5>[ 0.873335] NFS: Registering the id_resolver key type
10539 11:07:37.497222 <5>[ 0.878637] Key type id_resolver registered
10540 11:07:37.504046 <5>[ 0.883050] Key type id_legacy registered
10541 11:07:37.510417 <6>[ 0.887333] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10542 11:07:37.517044 <6>[ 0.894253] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10543 11:07:37.523590 <6>[ 0.901948] 9p: Installing v9fs 9p2000 file system support
10544 11:07:37.560027 <5>[ 0.939976] Key type asymmetric registered
10545 11:07:37.563688 <5>[ 0.944305] Asymmetric key parser 'x509' registered
10546 11:07:37.573270 <6>[ 0.949442] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10547 11:07:37.576597 <6>[ 0.957076] io scheduler mq-deadline registered
10548 11:07:37.579960 <6>[ 0.961835] io scheduler kyber registered
10549 11:07:37.599224 <6>[ 0.978943] EINJ: ACPI disabled.
10550 11:07:37.631953 <4>[ 1.004897] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 11:07:37.641729 <4>[ 1.015543] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 11:07:37.656963 <6>[ 1.036657] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10553 11:07:37.665246 <6>[ 1.044766] printk: console [ttyS0] disabled
10554 11:07:37.693010 <6>[ 1.069393] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10555 11:07:37.699729 <6>[ 1.078873] printk: console [ttyS0] enabled
10556 11:07:37.702966 <6>[ 1.078873] printk: console [ttyS0] enabled
10557 11:07:37.709592 <6>[ 1.087768] printk: bootconsole [mtk8250] disabled
10558 11:07:37.712823 <6>[ 1.087768] printk: bootconsole [mtk8250] disabled
10559 11:07:37.719548 <6>[ 1.099064] SuperH (H)SCI(F) driver initialized
10560 11:07:37.722461 <6>[ 1.104339] msm_serial: driver initialized
10561 11:07:37.737050 <6>[ 1.113323] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10562 11:07:37.747065 <6>[ 1.121871] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10563 11:07:37.753189 <6>[ 1.130412] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10564 11:07:37.763568 <6>[ 1.139039] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10565 11:07:37.770198 <6>[ 1.147746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10566 11:07:37.780058 <6>[ 1.156460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10567 11:07:37.790128 <6>[ 1.165006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10568 11:07:37.796928 <6>[ 1.173815] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10569 11:07:37.806440 <6>[ 1.182357] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10570 11:07:37.818084 <6>[ 1.197795] loop: module loaded
10571 11:07:37.824423 <6>[ 1.203847] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10572 11:07:37.847536 <4>[ 1.227262] mtk-pmic-keys: Failed to locate of_node [id: -1]
10573 11:07:37.854420 <6>[ 1.234391] megasas: 07.719.03.00-rc1
10574 11:07:37.864229 <6>[ 1.244165] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10575 11:07:37.870905 <6>[ 1.250728] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10576 11:07:37.888118 <6>[ 1.267586] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10577 11:07:37.945054 <6>[ 1.317821] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10578 11:07:38.198928 <6>[ 1.578953] Freeing initrd memory: 18268K
10579 11:07:38.210854 <6>[ 1.590580] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10580 11:07:38.222203 <6>[ 1.601648] tun: Universal TUN/TAP device driver, 1.6
10581 11:07:38.225346 <6>[ 1.607742] thunder_xcv, ver 1.0
10582 11:07:38.228776 <6>[ 1.611239] thunder_bgx, ver 1.0
10583 11:07:38.231850 <6>[ 1.614740] nicpf, ver 1.0
10584 11:07:38.242531 <6>[ 1.618773] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10585 11:07:38.246032 <6>[ 1.626250] hns3: Copyright (c) 2017 Huawei Corporation.
10586 11:07:38.249216 <6>[ 1.631838] hclge is initializing
10587 11:07:38.255505 <6>[ 1.635418] e1000: Intel(R) PRO/1000 Network Driver
10588 11:07:38.262733 <6>[ 1.640548] e1000: Copyright (c) 1999-2006 Intel Corporation.
10589 11:07:38.266053 <6>[ 1.646565] e1000e: Intel(R) PRO/1000 Network Driver
10590 11:07:38.272233 <6>[ 1.651780] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10591 11:07:38.279047 <6>[ 1.657965] igb: Intel(R) Gigabit Ethernet Network Driver
10592 11:07:38.285759 <6>[ 1.663615] igb: Copyright (c) 2007-2014 Intel Corporation.
10593 11:07:38.292387 <6>[ 1.669451] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10594 11:07:38.298843 <6>[ 1.675968] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10595 11:07:38.302042 <6>[ 1.682433] sky2: driver version 1.30
10596 11:07:38.309002 <6>[ 1.687376] usbcore: registered new device driver r8152-cfgselector
10597 11:07:38.315784 <6>[ 1.693913] usbcore: registered new interface driver r8152
10598 11:07:38.318958 <6>[ 1.699731] VFIO - User Level meta-driver version: 0.3
10599 11:07:38.328100 <6>[ 1.707999] usbcore: registered new interface driver usb-storage
10600 11:07:38.334826 <6>[ 1.714444] usbcore: registered new device driver onboard-usb-hub
10601 11:07:38.343874 <6>[ 1.723615] mt6397-rtc mt6359-rtc: registered as rtc0
10602 11:07:38.353576 <6>[ 1.729082] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:07:31 UTC (1720609651)
10603 11:07:38.357075 <6>[ 1.738648] i2c_dev: i2c /dev entries driver
10604 11:07:38.371042 <4>[ 1.750806] cpu cpu0: supply cpu not found, using dummy regulator
10605 11:07:38.377855 <4>[ 1.757228] cpu cpu1: supply cpu not found, using dummy regulator
10606 11:07:38.384538 <4>[ 1.763629] cpu cpu2: supply cpu not found, using dummy regulator
10607 11:07:38.391279 <4>[ 1.770035] cpu cpu3: supply cpu not found, using dummy regulator
10608 11:07:38.397532 <4>[ 1.776437] cpu cpu4: supply cpu not found, using dummy regulator
10609 11:07:38.404257 <4>[ 1.782847] cpu cpu5: supply cpu not found, using dummy regulator
10610 11:07:38.411286 <4>[ 1.789247] cpu cpu6: supply cpu not found, using dummy regulator
10611 11:07:38.417711 <4>[ 1.795640] cpu cpu7: supply cpu not found, using dummy regulator
10612 11:07:38.437269 <6>[ 1.817280] cpu cpu0: EM: created perf domain
10613 11:07:38.440655 <6>[ 1.822223] cpu cpu4: EM: created perf domain
10614 11:07:38.448293 <6>[ 1.827829] sdhci: Secure Digital Host Controller Interface driver
10615 11:07:38.454575 <6>[ 1.834259] sdhci: Copyright(c) Pierre Ossman
10616 11:07:38.461485 <6>[ 1.839218] Synopsys Designware Multimedia Card Interface Driver
10617 11:07:38.468034 <6>[ 1.845856] sdhci-pltfm: SDHCI platform and OF driver helper
10618 11:07:38.471592 <6>[ 1.845974] mmc0: CQHCI version 5.10
10619 11:07:38.478100 <6>[ 1.855932] ledtrig-cpu: registered to indicate activity on CPUs
10620 11:07:38.484831 <6>[ 1.862976] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10621 11:07:38.491219 <6>[ 1.870026] usbcore: registered new interface driver usbhid
10622 11:07:38.494421 <6>[ 1.875848] usbhid: USB HID core driver
10623 11:07:38.501071 <6>[ 1.880052] spi_master spi0: will run message pump with realtime priority
10624 11:07:38.545763 <6>[ 1.918914] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10625 11:07:38.564236 <6>[ 1.933980] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10626 11:07:38.567434 <6>[ 1.940626] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10627 11:07:38.575964 <6>[ 1.955679] cros-ec-spi spi0.0: Chrome EC device registered
10628 11:07:38.582651 <6>[ 1.961703] mmc0: Command Queue Engine enabled
10629 11:07:38.589495 <6>[ 1.966437] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10630 11:07:38.592299 <6>[ 1.974014] mmcblk0: mmc0:0001 DA4128 116 GiB
10631 11:07:38.603372 <6>[ 1.983201] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10632 11:07:38.610528 <6>[ 1.990644] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10633 11:07:38.620732 <6>[ 1.994793] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10634 11:07:38.623840 <6>[ 1.996560] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10635 11:07:38.630722 <6>[ 2.006516] NET: Registered PF_PACKET protocol family
10636 11:07:38.637101 <6>[ 2.011050] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10637 11:07:38.640511 <6>[ 2.015805] 9pnet: Installing 9P2000 support
10638 11:07:38.647531 <5>[ 2.026789] Key type dns_resolver registered
10639 11:07:38.650968 <6>[ 2.031805] registered taskstats version 1
10640 11:07:38.657241 <5>[ 2.036186] Loading compiled-in X.509 certificates
10641 11:07:38.687853 <4>[ 2.060441] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 11:07:38.697208 <4>[ 2.071175] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 11:07:38.711868 <6>[ 2.091762] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10644 11:07:38.718999 <6>[ 2.098616] xhci-mtk 11200000.usb: xHCI Host Controller
10645 11:07:38.725350 <6>[ 2.104137] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10646 11:07:38.735483 <6>[ 2.111989] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10647 11:07:38.742076 <6>[ 2.121419] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10648 11:07:38.748644 <6>[ 2.127541] xhci-mtk 11200000.usb: xHCI Host Controller
10649 11:07:38.755368 <6>[ 2.133123] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10650 11:07:38.762023 <6>[ 2.140822] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10651 11:07:38.769193 <6>[ 2.148662] hub 1-0:1.0: USB hub found
10652 11:07:38.772067 <6>[ 2.152692] hub 1-0:1.0: 1 port detected
10653 11:07:38.782054 <6>[ 2.157005] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10654 11:07:38.785735 <6>[ 2.165754] hub 2-0:1.0: USB hub found
10655 11:07:38.789042 <6>[ 2.169774] hub 2-0:1.0: 1 port detected
10656 11:07:38.796865 <6>[ 2.176742] mtk-msdc 11f70000.mmc: Got CD GPIO
10657 11:07:38.810082 <6>[ 2.186595] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10658 11:07:38.820370 <6>[ 2.194965] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10659 11:07:38.826648 <6>[ 2.203307] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10660 11:07:38.837016 <6>[ 2.211654] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10661 11:07:38.843435 <6>[ 2.219995] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10662 11:07:38.853502 <6>[ 2.228336] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10663 11:07:38.860090 <6>[ 2.236676] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10664 11:07:38.869863 <6>[ 2.245014] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10665 11:07:38.876275 <6>[ 2.253353] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10666 11:07:38.886608 <6>[ 2.261702] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10667 11:07:38.893520 <6>[ 2.270041] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10668 11:07:38.903399 <6>[ 2.278388] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10669 11:07:38.910076 <6>[ 2.286727] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10670 11:07:38.920170 <6>[ 2.295066] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10671 11:07:38.926541 <6>[ 2.303404] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10672 11:07:38.933091 <6>[ 2.312116] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10673 11:07:38.939749 <6>[ 2.319269] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10674 11:07:38.946345 <6>[ 2.326026] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10675 11:07:38.953039 <6>[ 2.332826] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10676 11:07:38.963177 <6>[ 2.339759] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10677 11:07:38.969813 <6>[ 2.346633] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10678 11:07:38.979860 <6>[ 2.355771] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10679 11:07:38.989787 <6>[ 2.364893] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10680 11:07:38.999689 <6>[ 2.374188] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10681 11:07:39.009473 <6>[ 2.383656] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10682 11:07:39.016394 <6>[ 2.393125] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10683 11:07:39.026441 <6>[ 2.402244] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10684 11:07:39.036437 <6>[ 2.411712] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10685 11:07:39.046277 <6>[ 2.420831] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10686 11:07:39.056362 <6>[ 2.430126] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10687 11:07:39.066369 <6>[ 2.440287] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10688 11:07:39.076343 <6>[ 2.452398] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10689 11:07:39.083843 <6>[ 2.463541] Trying to probe devices needed for running init ...
10690 11:07:39.094144 <3>[ 2.470782] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10691 11:07:39.202746 <6>[ 2.579482] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10692 11:07:39.357541 <6>[ 2.737497] hub 1-1:1.0: USB hub found
10693 11:07:39.360834 <6>[ 2.742041] hub 1-1:1.0: 4 ports detected
10694 11:07:39.372946 <6>[ 2.752497] hub 1-1:1.0: USB hub found
10695 11:07:39.376211 <6>[ 2.756942] hub 1-1:1.0: 4 ports detected
10696 11:07:39.483353 <6>[ 2.859831] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10697 11:07:39.509713 <6>[ 2.889416] hub 2-1:1.0: USB hub found
10698 11:07:39.512591 <6>[ 2.893913] hub 2-1:1.0: 3 ports detected
10699 11:07:39.524181 <6>[ 2.903945] hub 2-1:1.0: USB hub found
10700 11:07:39.527424 <6>[ 2.908307] hub 2-1:1.0: 3 ports detected
10701 11:07:39.694980 <6>[ 3.071652] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10702 11:07:39.827807 <6>[ 3.207514] hub 1-1.4:1.0: USB hub found
10703 11:07:39.830527 <6>[ 3.212176] hub 1-1.4:1.0: 2 ports detected
10704 11:07:39.843900 <6>[ 3.223683] hub 1-1.4:1.0: USB hub found
10705 11:07:39.846737 <6>[ 3.228262] hub 1-1.4:1.0: 2 ports detected
10706 11:07:39.907216 <6>[ 3.283778] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10707 11:07:40.015836 <6>[ 3.392297] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10708 11:07:40.051722 <4>[ 3.428215] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10709 11:07:40.061610 <4>[ 3.437307] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10710 11:07:40.101034 <6>[ 3.481186] r8152 2-1.3:1.0 eth0: v1.12.13
10711 11:07:40.142560 <6>[ 3.519416] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10712 11:07:40.330731 <6>[ 3.707485] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10713 11:07:41.700710 <6>[ 5.081172] r8152 2-1.3:1.0 eth0: carrier on
10714 11:07:43.970890 <5>[ 5.103454] Sending DHCP requests .., OK
10715 11:07:43.977424 <6>[ 7.355790] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10716 11:07:43.981045 <6>[ 7.364088] IP-Config: Complete:
10717 11:07:43.994281 <6>[ 7.367581] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10718 11:07:44.000825 <6>[ 7.378301] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10719 11:07:44.007618 <6>[ 7.386920] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10720 11:07:44.013873 <6>[ 7.386929] nameserver0=192.168.201.1
10721 11:07:44.017199 <6>[ 7.399053] clk: Disabling unused clocks
10722 11:07:44.020590 <6>[ 7.404590] ALSA device list:
10723 11:07:44.027463 <6>[ 7.407856] No soundcards found.
10724 11:07:44.034883 <6>[ 7.415124] Freeing unused kernel memory: 8512K
10725 11:07:44.038185 <6>[ 7.420087] Run /init as init process
10726 11:07:44.047321 Loading, please wait...
10727 11:07:44.077034 Starting systemd-udevd version 252.22-1~deb12u1
10728 11:07:44.361736 <6>[ 7.738500] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10729 11:07:44.367872 <6>[ 7.739479] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10730 11:07:44.377805 <6>[ 7.753690] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10731 11:07:44.384784 <6>[ 7.758161] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10732 11:07:44.394418 <6>[ 7.762497] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10733 11:07:44.401349 <6>[ 7.780475] remoteproc remoteproc0: scp is available
10734 11:07:44.408080 <6>[ 7.781740] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10735 11:07:44.414652 <6>[ 7.785787] remoteproc remoteproc0: powering up scp
10736 11:07:44.421322 <6>[ 7.793756] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10737 11:07:44.431015 <6>[ 7.798869] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10738 11:07:44.434596 <6>[ 7.798891] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10739 11:07:44.444590 <3>[ 7.803713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 11:07:44.450736 <3>[ 7.803733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 11:07:44.460948 <3>[ 7.803743] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 11:07:44.467305 <4>[ 7.806976] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10743 11:07:44.477697 <3>[ 7.808166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 11:07:44.484172 <3>[ 7.808179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 11:07:44.494023 <3>[ 7.808183] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:07:44.500838 <3>[ 7.808187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 11:07:44.510513 <3>[ 7.808190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 11:07:44.517720 <4>[ 7.808520] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10749 11:07:44.524025 <4>[ 7.823199] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10750 11:07:44.530772 <6>[ 7.829510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10751 11:07:44.540504 <3>[ 7.839984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 11:07:44.546996 <6>[ 7.845084] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10753 11:07:44.553543 <6>[ 7.859396] mc: Linux media interface: v0.10
10754 11:07:44.560207 <6>[ 7.870882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10755 11:07:44.567169 <3>[ 7.872081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 11:07:44.577242 <3>[ 7.872099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 11:07:44.583791 <3>[ 7.872109] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 11:07:44.593859 <3>[ 7.873601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 11:07:44.600324 <3>[ 7.873613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 11:07:44.609920 <3>[ 7.873617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 11:07:44.616777 <3>[ 7.873621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 11:07:44.623482 <3>[ 7.873624] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 11:07:44.633746 <3>[ 7.884299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 11:07:44.640076 <6>[ 7.886494] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10765 11:07:44.646389 <6>[ 7.909046] videodev: Linux video capture interface: v2.00
10766 11:07:44.653791 <6>[ 7.909148] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10767 11:07:44.663113 <6>[ 7.909151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10768 11:07:44.669637 <6>[ 7.927637] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10769 11:07:44.679757 <6>[ 7.940473] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10770 11:07:44.686084 <6>[ 7.940473] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10771 11:07:44.692887 <6>[ 7.945804] pci_bus 0000:00: root bus resource [bus 00-ff]
10772 11:07:44.699607 <6>[ 7.953806] remoteproc remoteproc0: remote processor scp is now up
10773 11:07:44.705971 <6>[ 7.962147] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10774 11:07:44.716094 <6>[ 7.962177] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10775 11:07:44.722492 <6>[ 7.970148] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10776 11:07:44.729371 <6>[ 7.971446] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10777 11:07:44.739236 <6>[ 7.979036] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10778 11:07:44.748972 <6>[ 7.980445] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10779 11:07:44.759487 <6>[ 7.986385] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10780 11:07:44.769497 <6>[ 7.994765] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10781 11:07:44.772401 <6>[ 8.002611] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10782 11:07:44.782480 <4>[ 8.026393] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10783 11:07:44.789289 <4>[ 8.026393] Fallback method does not support PEC.
10784 11:07:44.795899 <6>[ 8.032136] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10785 11:07:44.798755 <6>[ 8.049750] Bluetooth: Core ver 2.22
10786 11:07:44.802230 <6>[ 8.056028] pci 0000:00:00.0: supports D1 D2
10787 11:07:44.809176 <6>[ 8.064532] NET: Registered PF_BLUETOOTH protocol family
10788 11:07:44.815439 <6>[ 8.071502] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10789 11:07:44.822360 <6>[ 8.072694] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10790 11:07:44.835560 <6>[ 8.073992] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10791 11:07:44.841869 <6>[ 8.074189] usbcore: registered new interface driver uvcvideo
10792 11:07:44.848654 <6>[ 8.077236] Bluetooth: HCI device and connection manager initialized
10793 11:07:44.855600 <6>[ 8.084869] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10794 11:07:44.861860 <6>[ 8.091322] Bluetooth: HCI socket layer initialized
10795 11:07:44.868563 <6>[ 8.100735] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10796 11:07:44.871814 <6>[ 8.107729] Bluetooth: L2CAP socket layer initialized
10797 11:07:44.878613 <6>[ 8.108120] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10798 11:07:44.885084 <6>[ 8.115999] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10799 11:07:44.891821 <6>[ 8.126054] Bluetooth: SCO socket layer initialized
10800 11:07:44.898169 <6>[ 8.134316] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10801 11:07:44.904910 <6>[ 8.194990] usbcore: registered new interface driver btusb
10802 11:07:44.914847 <4>[ 8.195543] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10803 11:07:44.921388 <3>[ 8.195551] Bluetooth: hci0: Failed to load firmware file (-2)
10804 11:07:44.927898 <3>[ 8.195554] Bluetooth: hci0: Failed to set up firmware (-2)
10805 11:07:44.937939 <4>[ 8.195557] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10806 11:07:44.944526 <6>[ 8.201378] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10807 11:07:44.951377 <6>[ 8.331028] pci 0000:01:00.0: supports D1 D2
10808 11:07:44.958105 <6>[ 8.335548] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10809 11:07:44.974080 <6>[ 8.351508] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10810 11:07:44.981072 <6>[ 8.358415] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10811 11:07:44.987378 <6>[ 8.366496] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10812 11:07:44.997575 <6>[ 8.374493] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10813 11:07:45.004125 <6>[ 8.382495] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10814 11:07:45.014258 <6>[ 8.390495] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10815 11:07:45.017504 <6>[ 8.398496] pci 0000:00:00.0: PCI bridge to [bus 01]
10816 11:07:45.027120 <6>[ 8.403712] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10817 11:07:45.033913 <6>[ 8.411830] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10818 11:07:45.040814 <6>[ 8.418661] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10819 11:07:45.046794 <6>[ 8.425412] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10820 11:07:45.062042 <5>[ 8.439202] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10821 11:07:45.081211 <5>[ 8.458241] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10822 11:07:45.087516 <5>[ 8.465656] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10823 11:07:45.097796 <4>[ 8.474114] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10824 11:07:45.101268 <6>[ 8.482999] cfg80211: failed to load regulatory.db
10825 11:07:45.151234 <6>[ 8.528441] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10826 11:07:45.157528 <6>[ 8.535959] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10827 11:07:45.182047 <6>[ 8.562775] mt7921e 0000:01:00.0: ASIC revision: 79610010
10828 11:07:45.286073 <6>[ 8.663375] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10829 11:07:45.289219 <6>[ 8.663375]
10830 11:07:45.296650 Begin: Loading essential drivers ... done.
10831 11:07:45.300395 Begin: Running /scripts/init-premount ... done.
10832 11:07:45.307158 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10833 11:07:45.316894 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10834 11:07:45.317428 Device /sys/class/net/eth0 found
10835 11:07:45.320420 done.
10836 11:07:45.326771 Begin: Waiting up to 180 secs for any network device to become available ... done.
10837 11:07:45.354804 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10838 11:07:45.361507 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10839 11:07:45.368654 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10840 11:07:45.374972 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10841 11:07:45.381237 host : mt8192-asurada-spherion-r0-cbg-1
10842 11:07:45.388182 domain : lava-rack
10843 11:07:45.391248 rootserver: 192.168.201.1 rootpath:
10844 11:07:45.391698 filename :
10845 11:07:45.439772 done.
10846 11:07:45.447010 Begin: Running /scripts/nfs-bottom ... done.
10847 11:07:45.462721 Begin: Running /scripts/init-bottom ... done.
10848 11:07:45.554497 <6>[ 8.931692] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10849 11:07:46.811600 <6>[ 10.192463] NET: Registered PF_INET6 protocol family
10850 11:07:46.818297 <6>[ 10.199524] Segment Routing with IPv6
10851 11:07:46.821458 <6>[ 10.203501] In-situ OAM (IOAM) with IPv6
10852 11:07:46.996136 <30>[ 10.350430] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10853 11:07:47.002618 <30>[ 10.383618] systemd[1]: Detected architecture arm64.
10854 11:07:47.011533
10855 11:07:47.015011 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10856 11:07:47.015515
10857 11:07:47.040278 <30>[ 10.421390] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10858 11:07:48.130563 <30>[ 11.508492] systemd[1]: Queued start job for default target graphical.target.
10859 11:07:48.171512 <30>[ 11.548912] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10860 11:07:48.177950 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10861 11:07:48.199776 <30>[ 11.577463] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10862 11:07:48.209563 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10863 11:07:48.227652 <30>[ 11.605373] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10864 11:07:48.237884 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10865 11:07:48.255766 <30>[ 11.633017] systemd[1]: Created slice user.slice - User and Session Slice.
10866 11:07:48.261954 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10867 11:07:48.285802 <30>[ 11.660074] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10868 11:07:48.295585 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10869 11:07:48.313698 <30>[ 11.687893] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10870 11:07:48.320428 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10871 11:07:48.348580 <30>[ 11.716245] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10872 11:07:48.358672 <30>[ 11.736157] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10873 11:07:48.365101 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10874 11:07:48.382425 <30>[ 11.760012] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10875 11:07:48.392501 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10876 11:07:48.410239 <30>[ 11.787732] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10877 11:07:48.420027 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10878 11:07:48.435225 <30>[ 11.816148] systemd[1]: Reached target paths.target - Path Units.
10879 11:07:48.445547 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10880 11:07:48.462363 <30>[ 11.840101] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10881 11:07:48.469405 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10882 11:07:48.482602 <30>[ 11.863632] systemd[1]: Reached target slices.target - Slice Units.
10883 11:07:48.492637 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10884 11:07:48.507386 <30>[ 11.888101] systemd[1]: Reached target swap.target - Swaps.
10885 11:07:48.513816 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10886 11:07:48.534403 <30>[ 11.912140] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10887 11:07:48.544515 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10888 11:07:48.563077 <30>[ 11.940623] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10889 11:07:48.572922 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10890 11:07:48.592895 <30>[ 11.970331] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10891 11:07:48.602605 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10892 11:07:48.619715 <30>[ 11.997213] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10893 11:07:48.629318 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10894 11:07:48.646430 <30>[ 12.024258] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10895 11:07:48.653352 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10896 11:07:48.671971 <30>[ 12.049328] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10897 11:07:48.681546 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10898 11:07:48.701892 <30>[ 12.079773] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10899 11:07:48.711826 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10900 11:07:48.731173 <30>[ 12.108854] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10901 11:07:48.741163 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10902 11:07:48.781996 <30>[ 12.159736] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10903 11:07:48.788771 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10904 11:07:48.811299 <30>[ 12.188957] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10905 11:07:48.817666 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10906 11:07:48.843506 <30>[ 12.221242] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10907 11:07:48.849963 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10908 11:07:48.876598 <30>[ 12.248142] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10909 11:07:48.930574 <30>[ 12.308511] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10910 11:07:48.940487 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10911 11:07:48.963587 <30>[ 12.341300] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10912 11:07:48.970161 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10913 11:07:48.995459 <30>[ 12.373383] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10914 11:07:49.002161 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10915 11:07:49.037530 <6>[ 12.414872] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10916 11:07:49.058742 <30>[ 12.436446] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10917 11:07:49.065172 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10918 11:07:49.091971 <30>[ 12.469622] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10919 11:07:49.101466 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10920 11:07:49.123489 <30>[ 12.501303] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10921 11:07:49.130125 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10922 11:07:49.155548 <30>[ 12.533358] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10923 11:07:49.165326 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.545762] fuse: init (API version 7.37)
10924 11:07:49.165774 el Module loop...
10925 11:07:49.195456 <30>[ 12.573129] systemd[1]: Starting systemd-journald.service - Journal Service...
10926 11:07:49.201662 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10927 11:07:49.233756 <30>[ 12.611620] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10928 11:07:49.240032 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10929 11:07:49.269486 <30>[ 12.643903] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10930 11:07:49.275781 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10931 11:07:49.300097 <30>[ 12.677889] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10932 11:07:49.310218 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10933 11:07:49.333017 <30>[ 12.710570] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10934 11:07:49.339423 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10935 11:07:49.368698 <30>[ 12.746649] systemd[1]: Started systemd-journald.service - Journal Service.
10936 11:07:49.375262 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10937 11:07:49.402078 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10938 11:07:49.418686 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10939 11:07:49.438563 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10940 11:07:49.462837 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10941 11:07:49.492335 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10942 11:07:49.504530 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10943 11:07:49.527406 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10944 11:07:49.547695 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10945 11:07:49.569066 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10946 11:07:49.592382 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10947 11:07:49.615945 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10948 11:07:49.636133 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10949 11:07:49.660481 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10950 11:07:49.685040 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10951 11:07:49.766624 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10952 11:07:49.785515 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10953 11:07:49.808913 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10954 11:07:49.833918 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10955 11:07:49.861446 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10956 11:07:49.884815 <46>[ 13.262822] systemd-journald[315]: Received client request to flush runtime journal.
10957 11:07:49.903250 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10958 11:07:49.937548 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10959 11:07:49.958801 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10960 11:07:49.982308 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10961 11:07:50.003368 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10962 11:07:50.023829 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10963 11:07:51.273971 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10964 11:07:51.299574 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10965 11:07:51.355086 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10966 11:07:51.453871 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10967 11:07:51.470506 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10968 11:07:51.486060 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10969 11:07:51.526234 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10970 11:07:51.549269 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10971 11:07:51.778721 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10972 11:07:51.846887 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10973 11:07:51.931861 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10974 11:07:52.071163 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10975 11:07:52.143499 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10976 11:07:52.177179 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10977 11:07:52.216232 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/system<6>[ 15.597348] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10978 11:07:52.219536 d-backlight.
10979 11:07:52.280139 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10980 11:07:52.343820 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10981 11:07:52.393977 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10982 11:07:52.415663 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10983 11:07:52.434109 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10984 11:07:52.458255 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10985 11:07:52.491498 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10986 11:07:52.550647 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10987 11:07:52.574379 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10988 11:07:52.595014 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10989 11:07:52.618224 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10990 11:07:52.632983 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10991 11:07:52.684787 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10992 11:07:52.709679 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10993 11:07:52.725836 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10994 11:07:52.745826 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10995 11:07:52.765983 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10996 11:07:52.781838 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10997 11:07:52.800394 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10998 11:07:52.817953 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10999 11:07:52.833612 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11000 11:07:52.894247 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11001 11:07:52.927983 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11002 11:07:53.022761 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11003 11:07:53.047069 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11004 11:07:53.064546 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11005 11:07:53.099135 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11006 11:07:53.157918 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11007 11:07:53.208884 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11008 11:07:53.226937 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11009 11:07:53.244213 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11010 11:07:53.287882 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11011 11:07:53.407671 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11012 11:07:53.431321 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11013 11:07:53.450656 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11014 11:07:53.499096 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11015 11:07:53.564194 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11016 11:07:53.651465
11017 11:07:53.654868 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11018 11:07:53.655340
11019 11:07:53.658099 debian-bookworm-arm64 login: root (automatic login)
11020 11:07:53.658570
11021 11:07:53.980294 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11022 11:07:53.980848
11023 11:07:53.987173 The programs included with the Debian GNU/Linux system are free software;
11024 11:07:53.993669 the exact distribution terms for each program are described in the
11025 11:07:53.996927 individual files in /usr/share/doc/*/copyright.
11026 11:07:53.997395
11027 11:07:54.003386 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11028 11:07:54.007116 permitted by applicable law.
11029 11:07:55.071816 Matched prompt #10: / #
11031 11:07:55.072068 Setting prompt string to ['/ #']
11032 11:07:55.072177 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11034 11:07:55.072435 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11035 11:07:55.072517 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
11036 11:07:55.072580 Setting prompt string to ['/ #']
11037 11:07:55.072662 Forcing a shell prompt, looking for ['/ #']
11038 11:07:55.072718 Sending line: ''
11040 11:07:55.123877 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11041 11:07:55.124354 Waiting using forced prompt support (timeout 00:02:30)
11042 11:07:55.130065 / #
11043 11:07:55.130925 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11044 11:07:55.131395 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
11045 11:07:55.131796 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786841/extract-nfsrootfs-36yjr3fx'"
11047 11:07:55.239302 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786841/extract-nfsrootfs-36yjr3fx'
11048 11:07:55.240055 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11050 11:07:55.347332 / # export NFS_SERVER_IP='192.168.201.1'
11051 11:07:55.348197 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11052 11:07:55.348689 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
11053 11:07:55.349200 end: 2 depthcharge-action (duration 00:01:27) [common]
11054 11:07:55.349679 start: 3 lava-test-retry (timeout 00:07:56) [common]
11055 11:07:55.350140 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11056 11:07:55.350529 Using namespace: common
11057 11:07:55.351041 Sending line: '#'
11059 11:07:55.452381 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11060 11:07:55.457490 / # #
11061 11:07:55.457934 Using /lava-14786841
11062 11:07:55.458080 Sending line: 'export SHELL=/bin/bash'
11064 11:07:55.565567 / # export SHELL=/bin/bash
11065 11:07:55.566316 Sending line: '. /lava-14786841/environment'
11067 11:07:55.673320 / # . /lava-14786841/environment
11068 11:07:55.679753 Sending line: '/lava-14786841/bin/lava-test-runner /lava-14786841/0'
11070 11:07:55.781577 Test shell timeout: 10s (minimum of the action and connection timeout)
11071 11:07:55.787359 / # /lava-14786841/bin/lava-test-runner /lava-14786841/0
11072 11:07:56.030064 + export TESTRUN_ID=0_timesync-off
11073 11:07:56.033351 + TESTRUN_ID=0_timesync-off
11074 11:07:56.036637 + cd /lava-14786841/0/tests/0_timesync-off
11075 11:07:56.039570 ++ cat uuid
11076 11:07:56.043563 + UUID=14786841_1.6.2.3.1
11077 11:07:56.044176 + set +x
11078 11:07:56.050414 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14786841_1.6.2.3.1>
11079 11:07:56.051160 Received signal: <STARTRUN> 0_timesync-off 14786841_1.6.2.3.1
11080 11:07:56.051813 Starting test lava.0_timesync-off (14786841_1.6.2.3.1)
11081 11:07:56.052492 Skipping test definition patterns.
11082 11:07:56.053571 + systemctl stop systemd-timesyncd
11083 11:07:56.139886 + set +x
11084 11:07:56.142988 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14786841_1.6.2.3.1>
11085 11:07:56.143761 Received signal: <ENDRUN> 0_timesync-off 14786841_1.6.2.3.1
11086 11:07:56.144172 Ending use of test pattern.
11087 11:07:56.144495 Ending test lava.0_timesync-off (14786841_1.6.2.3.1), duration 0.09
11089 11:07:56.220186 + export TESTRUN_ID=1_kselftest-tpm2
11090 11:07:56.223821 + TESTRUN_ID=1_kselftest-tpm2
11091 11:07:56.227013 + cd /lava-14786841/0/tests/1_kselftest-tpm2
11092 11:07:56.230013 ++ cat uuid
11093 11:07:56.233531 + UUID=14786841_1.6.2.3.5
11094 11:07:56.234042 + set +x
11095 11:07:56.240220 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14786841_1.6.2.3.5>
11096 11:07:56.241156 Received signal: <STARTRUN> 1_kselftest-tpm2 14786841_1.6.2.3.5
11097 11:07:56.241544 Starting test lava.1_kselftest-tpm2 (14786841_1.6.2.3.5)
11098 11:07:56.242015 Skipping test definition patterns.
11099 11:07:56.243456 + cd ./automated/linux/kselftest/
11100 11:07:56.269566 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11101 11:07:56.309974 INFO: install_deps skipped
11102 11:07:56.815151 --2024-07-10 11:07:50-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11103 11:07:56.821983 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11104 11:07:56.958017 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11105 11:07:57.090666 HTTP request sent, awaiting response... 200 OK
11106 11:07:57.093903 Length: 1919896 (1.8M) [application/octet-stream]
11107 11:07:57.097494 Saving to: 'kselftest_armhf.tar.gz'
11108 11:07:57.098000
11109 11:07:57.098338
11110 11:07:57.356830 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11111 11:07:57.622591 kselftest_armhf.tar 2%[ ] 47.81K 177KB/s
11112 11:07:57.938857 kselftest_armhf.tar 11%[=> ] 217.50K 402KB/s
11113 11:07:58.075489 kselftest_armhf.tar 44%[=======> ] 841.10K 975KB/s
11114 11:07:58.081537 kselftest_armhf.tar 100%[===================>] 1.83M 1.83MB/s in 1.0s
11115 11:07:58.081614
11116 11:07:58.249478 2024-07-10 11:07:51 (1.83 MB/s) - 'kselftest_armhf.tar.gz' saved [1919896/1919896]
11117 11:07:58.249594
11118 11:08:04.993391 skiplist:
11119 11:08:04.996603 ========================================
11120 11:08:04.999819 ========================================
11121 11:08:05.048840 tpm2:test_smoke.sh
11122 11:08:05.051995 tpm2:test_space.sh
11123 11:08:05.069720 ============== Tests to run ===============
11124 11:08:05.073080 tpm2:test_smoke.sh
11125 11:08:05.073615 tpm2:test_space.sh
11126 11:08:05.076634 ===========End Tests to run ===============
11127 11:08:05.079382 shardfile-tpm2 pass
11128 11:08:05.192108 <12>[ 28.575213] kselftest: Running tests in tpm2
11129 11:08:05.202225 TAP version 13
11130 11:08:05.217330 1..2
11131 11:08:05.250657 # selftests: tpm2: test_smoke.sh
11132 11:08:07.102161 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11133 11:08:07.108530 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11134 11:08:07.115524 # Exception ignored in: <function Client.__del__ at 0xffff986fccc0>
11135 11:08:07.119186 # Traceback (most recent call last):
11136 11:08:07.129163 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11137 11:08:07.129683 # if self.tpm:
11138 11:08:07.132173 # ^^^^^^^^
11139 11:08:07.135424 # AttributeError: 'Client' object has no attribute 'tpm'
11140 11:08:07.141731 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11141 11:08:07.148762 # Exception ignored in: <function Client.__del__ at 0xffff986fccc0>
11142 11:08:07.152116 # Traceback (most recent call last):
11143 11:08:07.162291 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11144 11:08:07.162809 # if self.tpm:
11145 11:08:07.165641 # ^^^^^^^^
11146 11:08:07.168686 # AttributeError: 'Client' object has no attribute 'tpm'
11147 11:08:07.175251 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11148 11:08:07.182050 # Exception ignored in: <function Client.__del__ at 0xffff986fccc0>
11149 11:08:07.185257 # Traceback (most recent call last):
11150 11:08:07.195374 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11151 11:08:07.198893 # if self.tpm:
11152 11:08:07.199397 # ^^^^^^^^
11153 11:08:07.205492 # AttributeError: 'Client' object has no attribute 'tpm'
11154 11:08:07.211888 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11155 11:08:07.218455 # Exception ignored in: <function Client.__del__ at 0xffff986fccc0>
11156 11:08:07.221954 # Traceback (most recent call last):
11157 11:08:07.232085 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11158 11:08:07.232604 # if self.tpm:
11159 11:08:07.235134 # ^^^^^^^^
11160 11:08:07.239027 # AttributeError: 'Client' object has no attribute 'tpm'
11161 11:08:07.245391 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11162 11:08:07.251914 # Exception ignored in: <function Client.__del__ at 0xffff986fccc0>
11163 11:08:07.255278 # Traceback (most recent call last):
11164 11:08:07.265312 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11165 11:08:07.268665 # if self.tpm:
11166 11:08:07.269100 # ^^^^^^^^
11167 11:08:07.275226 # AttributeError: 'Client' object has no attribute 'tpm'
11168 11:08:07.281970 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11169 11:08:07.284915 # Exception ignored in: <function Client.__del__ at 0xffff986fccc0>
11170 11:08:07.288297 # Traceback (most recent call last):
11171 11:08:07.298714 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11172 11:08:07.301697 # if self.tpm:
11173 11:08:07.302132 # ^^^^^^^^
11174 11:08:07.308133 # AttributeError: 'Client' object has no attribute 'tpm'
11175 11:08:07.314884 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11176 11:08:07.321960 # Exception ignored in: <function Client.__del__ at 0xffff986fccc0>
11177 11:08:07.325372 # Traceback (most recent call last):
11178 11:08:07.335547 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11179 11:08:07.338267 # if self.tpm:
11180 11:08:07.338707 # ^^^^^^^^
11181 11:08:07.344908 # AttributeError: 'Client' object has no attribute 'tpm'
11182 11:08:07.352091 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11183 11:08:07.358487 # Exception ignored in: <function Client.__del__ at 0xffff986fccc0>
11184 11:08:07.361662 # Traceback (most recent call last):
11185 11:08:07.371853 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11186 11:08:07.372363 # if self.tpm:
11187 11:08:07.375275 # ^^^^^^^^
11188 11:08:07.378316 # AttributeError: 'Client' object has no attribute 'tpm'
11189 11:08:07.378818 #
11190 11:08:07.385337 # ======================================================================
11191 11:08:07.395339 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11192 11:08:07.402339 # ----------------------------------------------------------------------
11193 11:08:07.405270 # Traceback (most recent call last):
11194 11:08:07.415245 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11195 11:08:07.418828 # self.root_key = self.client.create_root_key()
11196 11:08:07.422066 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11197 11:08:07.435509 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11198 11:08:07.438595 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11199 11:08:07.445965 # ^^^^^^^^^^^^^^^^^^
11200 11:08:07.453383 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11201 11:08:07.456991 # raise ProtocolError(cc, rc)
11202 11:08:07.463694 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11203 11:08:07.464212 #
11204 11:08:07.470317 # ======================================================================
11205 11:08:07.477246 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11206 11:08:07.483924 # ----------------------------------------------------------------------
11207 11:08:07.487217 # Traceback (most recent call last):
11208 11:08:07.497279 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11209 11:08:07.500560 # self.client = tpm2.Client()
11210 11:08:07.504092 # ^^^^^^^^^^^^^
11211 11:08:07.510662 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11212 11:08:07.517422 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11213 11:08:07.520865 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11214 11:08:07.527256 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11215 11:08:07.527774 #
11216 11:08:07.533557 # ======================================================================
11217 11:08:07.540346 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11218 11:08:07.547393 # ----------------------------------------------------------------------
11219 11:08:07.550603 # Traceback (most recent call last):
11220 11:08:07.560537 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11221 11:08:07.563916 # self.client = tpm2.Client()
11222 11:08:07.567044 # ^^^^^^^^^^^^^
11223 11:08:07.577390 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11224 11:08:07.580606 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11225 11:08:07.587307 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11226 11:08:07.590185 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11227 11:08:07.590619 #
11228 11:08:07.597390 # ======================================================================
11229 11:08:07.603882 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11230 11:08:07.610297 # ----------------------------------------------------------------------
11231 11:08:07.613657 # Traceback (most recent call last):
11232 11:08:07.623632 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11233 11:08:07.627042 # self.client = tpm2.Client()
11234 11:08:07.630349 # ^^^^^^^^^^^^^
11235 11:08:07.640488 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11236 11:08:07.643808 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11237 11:08:07.650574 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11238 11:08:07.653427 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11239 11:08:07.653867 #
11240 11:08:07.660390 # ======================================================================
11241 11:08:07.670297 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11242 11:08:07.677254 # ----------------------------------------------------------------------
11243 11:08:07.680556 # Traceback (most recent call last):
11244 11:08:07.690507 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11245 11:08:07.693599 # self.client = tpm2.Client()
11246 11:08:07.697035 # ^^^^^^^^^^^^^
11247 11:08:07.707235 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11248 11:08:07.710230 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11249 11:08:07.713691 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11250 11:08:07.720235 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11251 11:08:07.720758 #
11252 11:08:07.726786 # ======================================================================
11253 11:08:07.733582 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11254 11:08:07.740598 # ----------------------------------------------------------------------
11255 11:08:07.743894 # Traceback (most recent call last):
11256 11:08:07.753921 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11257 11:08:07.757045 # self.client = tpm2.Client()
11258 11:08:07.760362 # ^^^^^^^^^^^^^
11259 11:08:07.768476 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11260 11:08:07.775433 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11261 11:08:07.778994 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11262 11:08:07.785617 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11263 11:08:07.786123 #
11264 11:08:07.789572 # ======================================================================
11265 11:08:07.797485 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11266 11:08:07.804344 # ----------------------------------------------------------------------
11267 11:08:07.807707 # Traceback (most recent call last):
11268 11:08:07.819964 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11269 11:08:07.820482 # self.client = tpm2.Client()
11270 11:08:07.823221 # ^^^^^^^^^^^^^
11271 11:08:07.834096 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11272 11:08:07.837464 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11273 11:08:07.841454 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11274 11:08:07.848125 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11275 11:08:07.848634 #
11276 11:08:07.854650 # ======================================================================
11277 11:08:07.861248 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11278 11:08:07.868068 # ----------------------------------------------------------------------
11279 11:08:07.871524 # Traceback (most recent call last):
11280 11:08:07.881529 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11281 11:08:07.884914 # self.client = tpm2.Client()
11282 11:08:07.887963 # ^^^^^^^^^^^^^
11283 11:08:07.898311 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11284 11:08:07.901668 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11285 11:08:07.908439 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11286 11:08:07.911600 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11287 11:08:07.915009 #
11288 11:08:07.918402 # ======================================================================
11289 11:08:07.928052 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11290 11:08:07.934842 # ----------------------------------------------------------------------
11291 11:08:07.937939 # Traceback (most recent call last):
11292 11:08:07.948573 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11293 11:08:07.951614 # self.client = tpm2.Client()
11294 11:08:07.954826 # ^^^^^^^^^^^^^
11295 11:08:07.964875 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11296 11:08:07.968243 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11297 11:08:07.971583 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11298 11:08:07.978343 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11299 11:08:07.978857 #
11300 11:08:07.985096 # ----------------------------------------------------------------------
11301 11:08:07.988372 # Ran 9 tests in 0.063s
11302 11:08:07.988882 #
11303 11:08:07.989273 # FAILED (errors=9)
11304 11:08:07.994935 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11305 11:08:08.001434 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11306 11:08:08.001935 #
11307 11:08:08.008750 # ----------------------------------------------------------------------
11308 11:08:08.011543 # Ran 2 tests in 0.030s
11309 11:08:08.011978 #
11310 11:08:08.012313 # OK
11311 11:08:08.014935 ok 1 selftests: tpm2: test_smoke.sh
11312 11:08:08.018332 # selftests: tpm2: test_space.sh
11313 11:08:08.025374 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11314 11:08:08.028427 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11315 11:08:08.035067 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11316 11:08:08.041911 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11317 11:08:08.042425 #
11318 11:08:08.048282 # ======================================================================
11319 11:08:08.055243 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11320 11:08:08.061508 # ----------------------------------------------------------------------
11321 11:08:08.064824 # Traceback (most recent call last):
11322 11:08:08.078395 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11323 11:08:08.081238 # root1 = space1.create_root_key()
11324 11:08:08.084835 # ^^^^^^^^^^^^^^^^^^^^^^^^
11325 11:08:08.094714 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11326 11:08:08.098032 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11327 11:08:08.104826 # ^^^^^^^^^^^^^^^^^^
11328 11:08:08.115225 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11329 11:08:08.118281 # raise ProtocolError(cc, rc)
11330 11:08:08.124963 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11331 11:08:08.125526 #
11332 11:08:08.131925 # ======================================================================
11333 11:08:08.134997 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11334 11:08:08.141615 # ----------------------------------------------------------------------
11335 11:08:08.144848 # Traceback (most recent call last):
11336 11:08:08.158211 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11337 11:08:08.158720 # space1.create_root_key()
11338 11:08:08.171571 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11339 11:08:08.174930 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11340 11:08:08.181559 # ^^^^^^^^^^^^^^^^^^
11341 11:08:08.191529 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11342 11:08:08.194431 # raise ProtocolError(cc, rc)
11343 11:08:08.197755 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11344 11:08:08.198196 #
11345 11:08:08.204858 # ======================================================================
11346 11:08:08.211338 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11347 11:08:08.217735 # ----------------------------------------------------------------------
11348 11:08:08.221652 # Traceback (most recent call last):
11349 11:08:08.231616 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11350 11:08:08.234637 # root1 = space1.create_root_key()
11351 11:08:08.237915 # ^^^^^^^^^^^^^^^^^^^^^^^^
11352 11:08:08.251097 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11353 11:08:08.254423 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11354 11:08:08.261203 # ^^^^^^^^^^^^^^^^^^
11355 11:08:08.271031 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11356 11:08:08.271470 # raise ProtocolError(cc, rc)
11357 11:08:08.277709 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11358 11:08:08.278181 #
11359 11:08:08.284361 # ======================================================================
11360 11:08:08.291016 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11361 11:08:08.297610 # ----------------------------------------------------------------------
11362 11:08:08.300885 # Traceback (most recent call last):
11363 11:08:08.314402 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11364 11:08:08.317558 # root1 = space1.create_root_key()
11365 11:08:08.321153 # ^^^^^^^^^^^^^^^^^^^^^^^^
11366 11:08:08.331249 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11367 11:08:08.337532 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11368 11:08:08.340845 # ^^^^^^^^^^^^^^^^^^
11369 11:08:08.350849 # File "/lava-14786841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11370 11:08:08.354229 # raise ProtocolError(cc, rc)
11371 11:08:08.360904 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11372 11:08:08.361379 #
11373 11:08:08.367739 # ----------------------------------------------------------------------
11374 11:08:08.368247 # Ran 4 tests in 0.092s
11375 11:08:08.368587 #
11376 11:08:08.371241 # FAILED (errors=4)
11377 11:08:08.374065 not ok 2 selftests: tpm2: test_space.sh # exit=1
11378 11:08:08.769647 tpm2_test_smoke_sh pass
11379 11:08:08.772713 tpm2_test_space_sh fail
11380 11:08:08.841282 + ../../utils/send-to-lava.sh ./output/result.txt
11381 11:08:08.919773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11382 11:08:08.920648 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11384 11:08:08.982063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11385 11:08:08.982741 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11387 11:08:09.039382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11388 11:08:09.040052 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11390 11:08:09.042641 + set +x
11391 11:08:09.045955 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14786841_1.6.2.3.5>
11392 11:08:09.046605 Received signal: <ENDRUN> 1_kselftest-tpm2 14786841_1.6.2.3.5
11393 11:08:09.046972 Ending use of test pattern.
11394 11:08:09.047328 Ending test lava.1_kselftest-tpm2 (14786841_1.6.2.3.5), duration 12.81
11396 11:08:09.049278 <LAVA_TEST_RUNNER EXIT>
11397 11:08:09.049916 ok: lava_test_shell seems to have completed
11398 11:08:09.050493 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11399 11:08:09.050943 end: 3.1 lava-test-shell (duration 00:00:14) [common]
11400 11:08:09.051404 end: 3 lava-test-retry (duration 00:00:14) [common]
11401 11:08:09.051869 start: 4 finalize (timeout 00:07:43) [common]
11402 11:08:09.052340 start: 4.1 power-off (timeout 00:00:30) [common]
11403 11:08:09.053011 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11404 11:08:11.187725 >> Command sent successfully.
11405 11:08:11.194515 Returned 0 in 2 seconds
11406 11:08:11.194648 end: 4.1 power-off (duration 00:00:02) [common]
11408 11:08:11.194862 start: 4.2 read-feedback (timeout 00:07:40) [common]
11409 11:08:11.195026 Listened to connection for namespace 'common' for up to 1s
11410 11:08:12.196205 Finalising connection for namespace 'common'
11411 11:08:12.196780 Disconnecting from shell: Finalise
11412 11:08:12.197160 / #
11413 11:08:12.297996 end: 4.2 read-feedback (duration 00:00:01) [common]
11414 11:08:12.298595 end: 4 finalize (duration 00:00:03) [common]
11415 11:08:12.299136 Cleaning after the job
11416 11:08:12.299607 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/ramdisk
11417 11:08:12.310176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/kernel
11418 11:08:12.341571 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/dtb
11419 11:08:12.341885 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/nfsrootfs
11420 11:08:12.410563 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786841/tftp-deploy-2dy1oftf/modules
11421 11:08:12.416208 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786841
11422 11:08:12.975679 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786841
11423 11:08:12.975847 Job finished correctly