Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 49
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 11:01:53.974788 lava-dispatcher, installed at version: 2024.05
2 11:01:53.975016 start: 0 validate
3 11:01:53.975145 Start time: 2024-07-10 11:01:53.975139+00:00 (UTC)
4 11:01:53.975290 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:01:53.975448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:01:54.257128 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:01:54.257349 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:03:29.332454 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:03:29.333120 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:03:29.602009 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:03:29.602562 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:03:30.140778 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:03:30.140932 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:04:30.471528 validate duration: 156.50
16 11:04:30.471799 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:04:30.471900 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:04:30.471988 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:04:30.472157 Not decompressing ramdisk as can be used compressed.
20 11:04:30.472246 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 11:04:30.472321 saving as /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/ramdisk/initrd.cpio.gz
22 11:04:30.472379 total size: 5628151 (5 MB)
23 11:04:30.738375 progress 0 % (0 MB)
24 11:04:30.740378 progress 5 % (0 MB)
25 11:04:30.742126 progress 10 % (0 MB)
26 11:04:30.743781 progress 15 % (0 MB)
27 11:04:30.745530 progress 20 % (1 MB)
28 11:04:30.747162 progress 25 % (1 MB)
29 11:04:30.748867 progress 30 % (1 MB)
30 11:04:30.750596 progress 35 % (1 MB)
31 11:04:30.752173 progress 40 % (2 MB)
32 11:04:30.753876 progress 45 % (2 MB)
33 11:04:30.755483 progress 50 % (2 MB)
34 11:04:30.757221 progress 55 % (2 MB)
35 11:04:30.758959 progress 60 % (3 MB)
36 11:04:30.760493 progress 65 % (3 MB)
37 11:04:30.762195 progress 70 % (3 MB)
38 11:04:30.763763 progress 75 % (4 MB)
39 11:04:30.765483 progress 80 % (4 MB)
40 11:04:30.767043 progress 85 % (4 MB)
41 11:04:30.768732 progress 90 % (4 MB)
42 11:04:30.770416 progress 95 % (5 MB)
43 11:04:30.772019 progress 100 % (5 MB)
44 11:04:30.772248 5 MB downloaded in 0.30 s (17.90 MB/s)
45 11:04:30.772413 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:04:30.772663 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:04:30.772750 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:04:30.772836 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:04:30.773008 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:04:30.773081 saving as /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/kernel/Image
52 11:04:30.773142 total size: 54813184 (52 MB)
53 11:04:30.773201 No compression specified
54 11:04:31.038961 progress 0 % (0 MB)
55 11:04:31.054729 progress 5 % (2 MB)
56 11:04:31.070406 progress 10 % (5 MB)
57 11:04:31.086125 progress 15 % (7 MB)
58 11:04:31.102396 progress 20 % (10 MB)
59 11:04:31.117956 progress 25 % (13 MB)
60 11:04:31.133551 progress 30 % (15 MB)
61 11:04:31.149522 progress 35 % (18 MB)
62 11:04:31.165770 progress 40 % (20 MB)
63 11:04:31.180992 progress 45 % (23 MB)
64 11:04:31.196363 progress 50 % (26 MB)
65 11:04:31.211448 progress 55 % (28 MB)
66 11:04:31.226494 progress 60 % (31 MB)
67 11:04:31.241600 progress 65 % (34 MB)
68 11:04:31.256573 progress 70 % (36 MB)
69 11:04:31.271969 progress 75 % (39 MB)
70 11:04:31.287241 progress 80 % (41 MB)
71 11:04:31.302370 progress 85 % (44 MB)
72 11:04:31.317954 progress 90 % (47 MB)
73 11:04:31.333107 progress 95 % (49 MB)
74 11:04:31.348353 progress 100 % (52 MB)
75 11:04:31.348604 52 MB downloaded in 0.58 s (90.84 MB/s)
76 11:04:31.348767 end: 1.2.1 http-download (duration 00:00:01) [common]
78 11:04:31.349004 end: 1.2 download-retry (duration 00:00:01) [common]
79 11:04:31.349094 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:04:31.349183 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:04:31.349334 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 11:04:31.349402 saving as /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 11:04:31.349469 total size: 57695 (0 MB)
84 11:04:31.349528 No compression specified
85 11:04:31.616929 progress 56 % (0 MB)
86 11:04:31.617262 progress 100 % (0 MB)
87 11:04:31.617505 0 MB downloaded in 0.27 s (0.21 MB/s)
88 11:04:31.617712 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:04:31.618111 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:04:31.618229 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:04:31.618359 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:04:31.618534 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 11:04:31.618628 saving as /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/nfsrootfs/full.rootfs.tar
95 11:04:31.618688 total size: 69067788 (65 MB)
96 11:04:31.618748 Using unxz to decompress xz
97 11:04:40.891192 progress 0 % (0 MB)
98 11:04:41.129919 progress 5 % (3 MB)
99 11:04:41.338191 progress 10 % (6 MB)
100 11:04:41.548506 progress 15 % (9 MB)
101 11:04:41.725928 progress 20 % (13 MB)
102 11:04:41.923972 progress 25 % (16 MB)
103 11:04:42.135110 progress 30 % (19 MB)
104 11:04:42.269278 progress 35 % (23 MB)
105 11:04:42.378160 progress 40 % (26 MB)
106 11:04:42.591288 progress 45 % (29 MB)
107 11:04:42.804901 progress 50 % (32 MB)
108 11:04:43.016543 progress 55 % (36 MB)
109 11:04:43.241866 progress 60 % (39 MB)
110 11:04:43.449936 progress 65 % (42 MB)
111 11:04:43.661362 progress 70 % (46 MB)
112 11:04:43.866364 progress 75 % (49 MB)
113 11:04:44.082103 progress 80 % (52 MB)
114 11:04:44.263434 progress 85 % (56 MB)
115 11:04:44.464517 progress 90 % (59 MB)
116 11:04:44.687898 progress 95 % (62 MB)
117 11:04:44.912216 progress 100 % (65 MB)
118 11:04:44.918884 65 MB downloaded in 13.30 s (4.95 MB/s)
119 11:04:44.919053 end: 1.4.1 http-download (duration 00:00:13) [common]
121 11:04:44.919287 end: 1.4 download-retry (duration 00:00:13) [common]
122 11:04:44.919378 start: 1.5 download-retry (timeout 00:09:46) [common]
123 11:04:44.919474 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 11:04:44.919626 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:04:44.919695 saving as /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/modules/modules.tar
126 11:04:44.919755 total size: 8607984 (8 MB)
127 11:04:44.919818 Using unxz to decompress xz
128 11:04:45.187187 progress 0 % (0 MB)
129 11:04:45.244067 progress 5 % (0 MB)
130 11:04:45.271392 progress 10 % (0 MB)
131 11:04:45.297155 progress 15 % (1 MB)
132 11:04:45.323103 progress 20 % (1 MB)
133 11:04:45.348334 progress 25 % (2 MB)
134 11:04:45.373658 progress 30 % (2 MB)
135 11:04:45.397699 progress 35 % (2 MB)
136 11:04:45.425805 progress 40 % (3 MB)
137 11:04:45.451817 progress 45 % (3 MB)
138 11:04:45.477677 progress 50 % (4 MB)
139 11:04:45.503966 progress 55 % (4 MB)
140 11:04:45.529652 progress 60 % (4 MB)
141 11:04:45.554618 progress 65 % (5 MB)
142 11:04:45.581742 progress 70 % (5 MB)
143 11:04:45.610546 progress 75 % (6 MB)
144 11:04:45.640204 progress 80 % (6 MB)
145 11:04:45.665650 progress 85 % (7 MB)
146 11:04:45.690575 progress 90 % (7 MB)
147 11:04:45.716087 progress 95 % (7 MB)
148 11:04:45.741050 progress 100 % (8 MB)
149 11:04:45.746886 8 MB downloaded in 0.83 s (9.93 MB/s)
150 11:04:45.747049 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:04:45.747421 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:04:45.747546 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
154 11:04:45.747669 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
155 11:04:47.485491 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786775/extract-nfsrootfs-q4z8imh0
156 11:04:47.485670 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:04:47.485766 start: 1.6.2 lava-overlay (timeout 00:09:43) [common]
158 11:04:47.485926 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j
159 11:04:47.486063 makedir: /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin
160 11:04:47.486183 makedir: /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/tests
161 11:04:47.486282 makedir: /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/results
162 11:04:47.486373 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-add-keys
163 11:04:47.486509 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-add-sources
164 11:04:47.486636 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-background-process-start
165 11:04:47.486762 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-background-process-stop
166 11:04:47.486903 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-common-functions
167 11:04:47.487028 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-echo-ipv4
168 11:04:47.487156 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-install-packages
169 11:04:47.487277 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-installed-packages
170 11:04:47.487396 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-os-build
171 11:04:47.487568 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-probe-channel
172 11:04:47.487689 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-probe-ip
173 11:04:47.487808 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-target-ip
174 11:04:47.487926 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-target-mac
175 11:04:47.488048 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-target-storage
176 11:04:47.488356 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-test-case
177 11:04:47.488529 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-test-event
178 11:04:47.488649 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-test-feedback
179 11:04:47.488769 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-test-raise
180 11:04:47.488889 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-test-reference
181 11:04:47.489011 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-test-runner
182 11:04:47.489130 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-test-set
183 11:04:47.489249 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-test-shell
184 11:04:47.489370 Updating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-install-packages (oe)
185 11:04:47.489517 Updating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/bin/lava-installed-packages (oe)
186 11:04:47.489636 Creating /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/environment
187 11:04:47.489727 LAVA metadata
188 11:04:47.489794 - LAVA_JOB_ID=14786775
189 11:04:47.489854 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:04:47.489950 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:43) [common]
191 11:04:47.490011 skipped lava-vland-overlay
192 11:04:47.490081 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:04:47.490157 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:43) [common]
194 11:04:47.490212 skipped lava-multinode-overlay
195 11:04:47.490280 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:04:47.490355 start: 1.6.2.3 test-definition (timeout 00:09:43) [common]
197 11:04:47.490419 Loading test definitions
198 11:04:47.490498 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:43) [common]
199 11:04:47.490560 Using /lava-14786775 at stage 0
200 11:04:47.490912 uuid=14786775_1.6.2.3.1 testdef=None
201 11:04:47.491029 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:04:47.491134 start: 1.6.2.3.2 test-overlay (timeout 00:09:43) [common]
203 11:04:47.491645 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:04:47.491857 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:43) [common]
206 11:04:47.492509 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:04:47.492732 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:43) [common]
209 11:04:47.493317 runner path: /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/0/tests/0_lc-compliance test_uuid 14786775_1.6.2.3.1
210 11:04:47.493466 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:04:47.493660 Creating lava-test-runner.conf files
213 11:04:47.493720 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786775/lava-overlay-j5m2s46j/lava-14786775/0 for stage 0
214 11:04:47.493804 - 0_lc-compliance
215 11:04:47.493897 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:04:47.493977 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
217 11:04:47.500024 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:04:47.500123 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:43) [common]
219 11:04:47.500206 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:04:47.500287 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:04:47.500367 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:43) [common]
222 11:04:47.657299 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:04:47.657450 start: 1.6.4 extract-modules (timeout 00:09:43) [common]
224 11:04:47.657527 extracting modules file /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786775/extract-nfsrootfs-q4z8imh0
225 11:04:47.936984 extracting modules file /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786775/extract-overlay-ramdisk-__2uqiwv/ramdisk
226 11:04:48.277660 end: 1.6.4 extract-modules (duration 00:00:01) [common]
227 11:04:48.277832 start: 1.6.5 apply-overlay-tftp (timeout 00:09:42) [common]
228 11:04:48.277944 [common] Applying overlay to NFS
229 11:04:48.278046 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786775/compress-overlay-ljkor5ea/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786775/extract-nfsrootfs-q4z8imh0
230 11:04:48.288192 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:04:48.288337 start: 1.6.6 configure-preseed-file (timeout 00:09:42) [common]
232 11:04:48.288452 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:04:48.288578 start: 1.6.7 compress-ramdisk (timeout 00:09:42) [common]
234 11:04:48.288678 Building ramdisk /var/lib/lava/dispatcher/tmp/14786775/extract-overlay-ramdisk-__2uqiwv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786775/extract-overlay-ramdisk-__2uqiwv/ramdisk
235 11:04:48.555783 >> 129845 blocks
236 11:04:50.905603 rename /var/lib/lava/dispatcher/tmp/14786775/extract-overlay-ramdisk-__2uqiwv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/ramdisk/ramdisk.cpio.gz
237 11:04:50.905775 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
238 11:04:50.905875 start: 1.6.8 prepare-kernel (timeout 00:09:40) [common]
239 11:04:50.905963 start: 1.6.8.1 prepare-fit (timeout 00:09:40) [common]
240 11:04:50.906050 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/kernel/Image']
241 11:05:05.891184 Returned 0 in 14 seconds
242 11:05:05.891382 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/kernel/image.itb
243 11:05:06.281106 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:05:06.281239 output: Created: Wed Jul 10 12:05:06 2024
245 11:05:06.281307 output: Image 0 (kernel-1)
246 11:05:06.281369 output: Description:
247 11:05:06.281428 output: Created: Wed Jul 10 12:05:06 2024
248 11:05:06.281486 output: Type: Kernel Image
249 11:05:06.281541 output: Compression: lzma compressed
250 11:05:06.281599 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
251 11:05:06.281655 output: Architecture: AArch64
252 11:05:06.281709 output: OS: Linux
253 11:05:06.281763 output: Load Address: 0x00000000
254 11:05:06.281819 output: Entry Point: 0x00000000
255 11:05:06.281883 output: Hash algo: crc32
256 11:05:06.281943 output: Hash value: 9bb85fb9
257 11:05:06.281998 output: Image 1 (fdt-1)
258 11:05:06.282052 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
259 11:05:06.282107 output: Created: Wed Jul 10 12:05:06 2024
260 11:05:06.282161 output: Type: Flat Device Tree
261 11:05:06.282214 output: Compression: uncompressed
262 11:05:06.282285 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
263 11:05:06.282340 output: Architecture: AArch64
264 11:05:06.282399 output: Hash algo: crc32
265 11:05:06.282459 output: Hash value: a9713552
266 11:05:06.282525 output: Image 2 (ramdisk-1)
267 11:05:06.282580 output: Description: unavailable
268 11:05:06.282634 output: Created: Wed Jul 10 12:05:06 2024
269 11:05:06.282688 output: Type: RAMDisk Image
270 11:05:06.282741 output: Compression: uncompressed
271 11:05:06.282794 output: Data Size: 18709639 Bytes = 18271.13 KiB = 17.84 MiB
272 11:05:06.282848 output: Architecture: AArch64
273 11:05:06.282901 output: OS: Linux
274 11:05:06.282954 output: Load Address: unavailable
275 11:05:06.283007 output: Entry Point: unavailable
276 11:05:06.283060 output: Hash algo: crc32
277 11:05:06.283113 output: Hash value: f8cfb559
278 11:05:06.283165 output: Default Configuration: 'conf-1'
279 11:05:06.283218 output: Configuration 0 (conf-1)
280 11:05:06.283271 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
281 11:05:06.283325 output: Kernel: kernel-1
282 11:05:06.283378 output: Init Ramdisk: ramdisk-1
283 11:05:06.283432 output: FDT: fdt-1
284 11:05:06.283498 output: Loadables: kernel-1
285 11:05:06.283552 output:
286 11:05:06.283664 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 11:05:06.283748 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 11:05:06.283830 end: 1.6 prepare-tftp-overlay (duration 00:00:21) [common]
289 11:05:06.283923 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:24) [common]
290 11:05:06.283990 No LXC device requested
291 11:05:06.284064 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:05:06.284142 start: 1.8 deploy-device-env (timeout 00:09:24) [common]
293 11:05:06.284217 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:05:06.284279 Checking files for TFTP limit of 4294967296 bytes.
295 11:05:06.284683 end: 1 tftp-deploy (duration 00:00:36) [common]
296 11:05:06.284782 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:05:06.284870 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:05:06.284969 substitutions:
299 11:05:06.285035 - {DTB}: 14786775/tftp-deploy-d4n7v1xj/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
300 11:05:06.285096 - {INITRD}: 14786775/tftp-deploy-d4n7v1xj/ramdisk/ramdisk.cpio.gz
301 11:05:06.285154 - {KERNEL}: 14786775/tftp-deploy-d4n7v1xj/kernel/Image
302 11:05:06.285210 - {LAVA_MAC}: None
303 11:05:06.285266 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786775/extract-nfsrootfs-q4z8imh0
304 11:05:06.285322 - {NFS_SERVER_IP}: 192.168.201.1
305 11:05:06.285377 - {PRESEED_CONFIG}: None
306 11:05:06.285436 - {PRESEED_LOCAL}: None
307 11:05:06.285490 - {RAMDISK}: 14786775/tftp-deploy-d4n7v1xj/ramdisk/ramdisk.cpio.gz
308 11:05:06.285564 - {ROOT_PART}: None
309 11:05:06.285620 - {ROOT}: None
310 11:05:06.285674 - {SERVER_IP}: 192.168.201.1
311 11:05:06.285729 - {TEE}: None
312 11:05:06.285783 Parsed boot commands:
313 11:05:06.285853 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:05:06.286006 Parsed boot commands: tftpboot 192.168.201.1 14786775/tftp-deploy-d4n7v1xj/kernel/image.itb 14786775/tftp-deploy-d4n7v1xj/kernel/cmdline
315 11:05:06.286104 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:05:06.286234 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:05:06.286348 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:05:06.286464 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:05:06.286533 Not connected, no need to disconnect.
320 11:05:06.286622 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:05:06.286733 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:05:06.286827 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-2'
323 11:05:06.290021 Setting prompt string to ['lava-test: # ']
324 11:05:06.290410 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:05:06.290526 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:05:06.290629 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:05:06.290721 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:05:06.290923 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2', '--port=1', '--command=reboot']
329 11:05:15.511894 >> Command sent successfully.
330 11:05:15.525954 Returned 0 in 9 seconds
331 11:05:15.526587 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 11:05:15.527678 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 11:05:15.528107 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 11:05:15.528452 Setting prompt string to 'Starting depthcharge on Juniper...'
336 11:05:15.528746 Changing prompt to 'Starting depthcharge on Juniper...'
337 11:05:15.529050 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
338 11:05:15.530937 [Enter `^Ec?' for help]
339 11:05:22.489054 [DL] 00000000 00000000 010701
340 11:05:22.494167
341 11:05:22.494587
342 11:05:22.494889 F0: 102B 0000
343 11:05:22.495332
344 11:05:22.497340 F3: 1006 0033 [0200]
345 11:05:22.497868
346 11:05:22.498270 F3: 4001 00E0 [0200]
347 11:05:22.498596
348 11:05:22.498865 F3: 0000 0000
349 11:05:22.501241
350 11:05:22.501685 V0: 0000 0000 [0001]
351 11:05:22.502178
352 11:05:22.502713 00: 1027 0002
353 11:05:22.503639
354 11:05:22.504009 01: 0000 0000
355 11:05:22.504289
356 11:05:22.504588 BP: 0C00 0251 [0000]
357 11:05:22.504902
358 11:05:22.507326 G0: 1182 0000
359 11:05:22.507743
360 11:05:22.508037 EC: 0004 0000 [0001]
361 11:05:22.508311
362 11:05:22.510460 S7: 0000 0000 [0000]
363 11:05:22.510842
364 11:05:22.513843 CC: 0000 0000 [0001]
365 11:05:22.514224
366 11:05:22.514518 T0: 0000 00DB [000F]
367 11:05:22.514791
368 11:05:22.515052 Jump to BL
369 11:05:22.517192
370 11:05:22.550384
371 11:05:22.550846
372 11:05:22.560160 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
373 11:05:22.563288 ARM64: Exception handlers installed.
374 11:05:22.563730 ARM64: Testing exception
375 11:05:22.566410 ARM64: Done test exception
376 11:05:22.569550 WDT: Last reset was cold boot
377 11:05:22.573048 SPI0(PAD0) initialized at 992727 Hz
378 11:05:22.575903 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
379 11:05:22.579471 Manufacturer: ef
380 11:05:22.583245 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
381 11:05:22.596584 Probing TPM: . done!
382 11:05:22.596973 TPM ready after 0 ms
383 11:05:22.603540 Connected to device vid:did:rid of 1ae0:0028:00
384 11:05:22.613128 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-afa1dd1
385 11:05:22.644037 Initialized TPM device CR50 revision 0
386 11:05:22.656779 tlcl_send_startup: Startup return code is 0
387 11:05:22.657355 TPM: setup succeeded
388 11:05:22.664706 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
389 11:05:22.667963 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
390 11:05:22.671368 in-header: 03 19 00 00 08 00 00 00
391 11:05:22.674481 in-data: a2 e0 47 00 13 00 00 00
392 11:05:22.677680 Chrome EC: UHEPI supported
393 11:05:22.684864 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
394 11:05:22.687901 in-header: 03 a1 00 00 08 00 00 00
395 11:05:22.691288 in-data: 84 60 60 10 00 00 00 00
396 11:05:22.691794 Phase 1
397 11:05:22.694313 FMAP: area GBB found @ 3f5000 (12032 bytes)
398 11:05:22.700748 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
399 11:05:22.707587 VB2:vb2_check_recovery() Recovery was requested manually
400 11:05:22.710513 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
401 11:05:22.714556 Recovery requested (1009000e)
402 11:05:22.726344 tlcl_extend: response is 0
403 11:05:22.731480 tlcl_extend: response is 0
404 11:05:22.756628
405 11:05:22.757058
406 11:05:22.766243 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
407 11:05:22.769634 ARM64: Exception handlers installed.
408 11:05:22.769997 ARM64: Testing exception
409 11:05:22.772707 ARM64: Done test exception
410 11:05:22.788994 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x926b, sec=0x2000
411 11:05:22.795400 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
412 11:05:22.798498 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
413 11:05:22.806969 [RTC]rtc_get_frequency_meter,134: input=0xf, output=864
414 11:05:22.813823 [RTC]rtc_get_frequency_meter,134: input=0x7, output=734
415 11:05:22.820931 [RTC]rtc_get_frequency_meter,134: input=0xb, output=799
416 11:05:22.827502 [RTC]rtc_get_frequency_meter,134: input=0x9, output=766
417 11:05:22.834683 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
418 11:05:22.841330 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
419 11:05:22.848432 [RTC]rtc_get_frequency_meter,134: input=0xb, output=798
420 11:05:22.854954 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x926b
421 11:05:22.858154 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
422 11:05:22.861484 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
423 11:05:22.868091 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
424 11:05:22.871322 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
425 11:05:22.874308 in-header: 03 19 00 00 08 00 00 00
426 11:05:22.878017 in-data: a2 e0 47 00 13 00 00 00
427 11:05:22.878377 Chrome EC: UHEPI supported
428 11:05:22.884462 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
429 11:05:22.887538 in-header: 03 a1 00 00 08 00 00 00
430 11:05:22.890879 in-data: 84 60 60 10 00 00 00 00
431 11:05:22.894583 Skip loading cached calibration data
432 11:05:22.900686 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
433 11:05:22.903949 in-header: 03 a1 00 00 08 00 00 00
434 11:05:22.906960 in-data: 84 60 60 10 00 00 00 00
435 11:05:22.913764 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
436 11:05:22.917392 in-header: 03 a1 00 00 08 00 00 00
437 11:05:22.920499 in-data: 84 60 60 10 00 00 00 00
438 11:05:22.923360 ADC[3]: Raw value=216116 ID=1
439 11:05:22.926689 Manufacturer: ef
440 11:05:22.930428 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
441 11:05:22.936572 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
442 11:05:22.937049 CBFS @ 21000 size 3d4000
443 11:05:22.943122 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
444 11:05:22.946570 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
445 11:05:22.949916 CBFS: Found @ offset 3c700 size 44
446 11:05:22.953317 DRAM-K: Full Calibration
447 11:05:22.956210 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
448 11:05:22.959394 CBFS @ 21000 size 3d4000
449 11:05:22.966211 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
450 11:05:22.969617 CBFS: Locating 'fallback/dram'
451 11:05:22.972723 CBFS: Found @ offset 24b00 size 12268
452 11:05:22.999424 read SPI 0x45b44 0x1224c: 22775 us, 3263 KB/s, 26.104 Mbps
453 11:05:23.002739 ddr_geometry: 1, config: 0x0
454 11:05:23.005969 header.status = 0x0
455 11:05:23.009565 header.magic = 0x44524d4b (expected: 0x44524d4b)
456 11:05:23.012409 header.version = 0x5 (expected: 0x5)
457 11:05:23.015750 header.size = 0x8f0 (expected: 0x8f0)
458 11:05:23.016169 header.config = 0x0
459 11:05:23.019205 header.flags = 0x0
460 11:05:23.022353 header.checksum = 0x0
461 11:05:23.029007 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
462 11:05:23.032326 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
463 11:05:23.038916 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
464 11:05:23.039301 ddr_geometry:1
465 11:05:23.042075 [EMI] new MDL number = 1
466 11:05:23.042434 dram_cbt_mode_extern: 0
467 11:05:23.045246 dram_cbt_mode [RK0]: 0, [RK1]: 0
468 11:05:23.052103 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
469 11:05:23.052592
470 11:05:23.052882
471 11:05:23.055498 [Bianco] ETT version 0.0.0.1
472 11:05:23.058699 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
473 11:05:23.059053
474 11:05:23.062277 vSetVcoreByFreq with vcore:762500, freq=1600
475 11:05:23.062754
476 11:05:23.065193 [DramcInit]
477 11:05:23.068409 AutoRefreshCKEOff AutoREF OFF
478 11:05:23.068767 DDRPhyPLLSetting-CKEOFF
479 11:05:23.071784 DDRPhyPLLSetting-CKEON
480 11:05:23.072200
481 11:05:23.072569 Enable WDQS
482 11:05:23.076917 [ModeRegInit_LP4] CH0 RK0
483 11:05:23.080258 Write Rank0 MR13 =0x18
484 11:05:23.080620 Write Rank0 MR12 =0x5d
485 11:05:23.083514 Write Rank0 MR1 =0x56
486 11:05:23.086843 Write Rank0 MR2 =0x1a
487 11:05:23.087297 Write Rank0 MR11 =0x0
488 11:05:23.090003 Write Rank0 MR22 =0x38
489 11:05:23.093308 Write Rank0 MR14 =0x5d
490 11:05:23.093734 Write Rank0 MR3 =0x30
491 11:05:23.096634 Write Rank0 MR13 =0x58
492 11:05:23.096983 Write Rank0 MR12 =0x5d
493 11:05:23.099591 Write Rank0 MR1 =0x56
494 11:05:23.103068 Write Rank0 MR2 =0x2d
495 11:05:23.103428 Write Rank0 MR11 =0x23
496 11:05:23.106331 Write Rank0 MR22 =0x34
497 11:05:23.109668 Write Rank0 MR14 =0x10
498 11:05:23.110066 Write Rank0 MR3 =0x30
499 11:05:23.112723 Write Rank0 MR13 =0xd8
500 11:05:23.113084 [ModeRegInit_LP4] CH0 RK1
501 11:05:23.116121 Write Rank1 MR13 =0x18
502 11:05:23.119448 Write Rank1 MR12 =0x5d
503 11:05:23.119962 Write Rank1 MR1 =0x56
504 11:05:23.122512 Write Rank1 MR2 =0x1a
505 11:05:23.125971 Write Rank1 MR11 =0x0
506 11:05:23.126360 Write Rank1 MR22 =0x38
507 11:05:23.129483 Write Rank1 MR14 =0x5d
508 11:05:23.129845 Write Rank1 MR3 =0x30
509 11:05:23.132531 Write Rank1 MR13 =0x58
510 11:05:23.135624 Write Rank1 MR12 =0x5d
511 11:05:23.136002 Write Rank1 MR1 =0x56
512 11:05:23.138900 Write Rank1 MR2 =0x2d
513 11:05:23.142153 Write Rank1 MR11 =0x23
514 11:05:23.142679 Write Rank1 MR22 =0x34
515 11:05:23.145396 Write Rank1 MR14 =0x10
516 11:05:23.145751 Write Rank1 MR3 =0x30
517 11:05:23.148965 Write Rank1 MR13 =0xd8
518 11:05:23.152121 [ModeRegInit_LP4] CH1 RK0
519 11:05:23.152575 Write Rank0 MR13 =0x18
520 11:05:23.155494 Write Rank0 MR12 =0x5d
521 11:05:23.158770 Write Rank0 MR1 =0x56
522 11:05:23.159299 Write Rank0 MR2 =0x1a
523 11:05:23.161783 Write Rank0 MR11 =0x0
524 11:05:23.162145 Write Rank0 MR22 =0x38
525 11:05:23.165252 Write Rank0 MR14 =0x5d
526 11:05:23.168649 Write Rank0 MR3 =0x30
527 11:05:23.169007 Write Rank0 MR13 =0x58
528 11:05:23.171506 Write Rank0 MR12 =0x5d
529 11:05:23.174718 Write Rank0 MR1 =0x56
530 11:05:23.175046 Write Rank0 MR2 =0x2d
531 11:05:23.178045 Write Rank0 MR11 =0x23
532 11:05:23.178437 Write Rank0 MR22 =0x34
533 11:05:23.181562 Write Rank0 MR14 =0x10
534 11:05:23.184708 Write Rank0 MR3 =0x30
535 11:05:23.185059 Write Rank0 MR13 =0xd8
536 11:05:23.188006 [ModeRegInit_LP4] CH1 RK1
537 11:05:23.191166 Write Rank1 MR13 =0x18
538 11:05:23.191713 Write Rank1 MR12 =0x5d
539 11:05:23.194437 Write Rank1 MR1 =0x56
540 11:05:23.194525 Write Rank1 MR2 =0x1a
541 11:05:23.197567 Write Rank1 MR11 =0x0
542 11:05:23.200984 Write Rank1 MR22 =0x38
543 11:05:23.201070 Write Rank1 MR14 =0x5d
544 11:05:23.204124 Write Rank1 MR3 =0x30
545 11:05:23.207577 Write Rank1 MR13 =0x58
546 11:05:23.207662 Write Rank1 MR12 =0x5d
547 11:05:23.210744 Write Rank1 MR1 =0x56
548 11:05:23.210841 Write Rank1 MR2 =0x2d
549 11:05:23.214001 Write Rank1 MR11 =0x23
550 11:05:23.217311 Write Rank1 MR22 =0x34
551 11:05:23.217465 Write Rank1 MR14 =0x10
552 11:05:23.220704 Write Rank1 MR3 =0x30
553 11:05:23.223734 Write Rank1 MR13 =0xd8
554 11:05:23.223833 match AC timing 3
555 11:05:23.234162 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
556 11:05:23.234711 [MiockJmeterHQA]
557 11:05:23.240477 vSetVcoreByFreq with vcore:762500, freq=1600
558 11:05:23.343781
559 11:05:23.344244 MIOCK jitter meter ch=0
560 11:05:23.344549
561 11:05:23.346930 1T = (101-17) = 84 dly cells
562 11:05:23.353531 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 744/100 ps
563 11:05:23.356955 vSetVcoreByFreq with vcore:725000, freq=1200
564 11:05:23.456041
565 11:05:23.456316 MIOCK jitter meter ch=0
566 11:05:23.456517
567 11:05:23.459533 1T = (96-16) = 80 dly cells
568 11:05:23.466493 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
569 11:05:23.469638 vSetVcoreByFreq with vcore:725000, freq=800
570 11:05:23.568676
571 11:05:23.569346 MIOCK jitter meter ch=0
572 11:05:23.569806
573 11:05:23.571810 1T = (96-16) = 80 dly cells
574 11:05:23.578547 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
575 11:05:23.581610 vSetVcoreByFreq with vcore:762500, freq=1600
576 11:05:23.584992 vSetVcoreByFreq with vcore:762500, freq=1600
577 11:05:23.585354
578 11:05:23.585635 K DRVP
579 11:05:23.588216 1. OCD DRVP=0 CALOUT=0
580 11:05:23.591365 1. OCD DRVP=1 CALOUT=0
581 11:05:23.591819 1. OCD DRVP=2 CALOUT=0
582 11:05:23.594454 1. OCD DRVP=3 CALOUT=0
583 11:05:23.598059 1. OCD DRVP=4 CALOUT=0
584 11:05:23.598417 1. OCD DRVP=5 CALOUT=0
585 11:05:23.601078 1. OCD DRVP=6 CALOUT=0
586 11:05:23.604522 1. OCD DRVP=7 CALOUT=0
587 11:05:23.605042 1. OCD DRVP=8 CALOUT=1
588 11:05:23.605434
589 11:05:23.607782 1. OCD DRVP calibration OK! DRVP=8
590 11:05:23.608373
591 11:05:23.608770
592 11:05:23.609141
593 11:05:23.611168 K ODTN
594 11:05:23.611558 3. OCD ODTN=0 ,CALOUT=1
595 11:05:23.614458 3. OCD ODTN=1 ,CALOUT=1
596 11:05:23.617558 3. OCD ODTN=2 ,CALOUT=1
597 11:05:23.617919 3. OCD ODTN=3 ,CALOUT=1
598 11:05:23.620849 3. OCD ODTN=4 ,CALOUT=1
599 11:05:23.621206 3. OCD ODTN=5 ,CALOUT=1
600 11:05:23.624310 3. OCD ODTN=6 ,CALOUT=1
601 11:05:23.627381 3. OCD ODTN=7 ,CALOUT=0
602 11:05:23.627924
603 11:05:23.630783 3. OCD ODTN calibration OK! ODTN=7
604 11:05:23.631290
605 11:05:23.633931 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
606 11:05:23.637287 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
607 11:05:23.643959 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
608 11:05:23.644332
609 11:05:23.644611 K DRVP
610 11:05:23.647318 1. OCD DRVP=0 CALOUT=0
611 11:05:23.647714 1. OCD DRVP=1 CALOUT=0
612 11:05:23.650506 1. OCD DRVP=2 CALOUT=0
613 11:05:23.653874 1. OCD DRVP=3 CALOUT=0
614 11:05:23.654241 1. OCD DRVP=4 CALOUT=0
615 11:05:23.656909 1. OCD DRVP=5 CALOUT=0
616 11:05:23.657278 1. OCD DRVP=6 CALOUT=0
617 11:05:23.660403 1. OCD DRVP=7 CALOUT=0
618 11:05:23.663490 1. OCD DRVP=8 CALOUT=0
619 11:05:23.664074 1. OCD DRVP=9 CALOUT=0
620 11:05:23.666629 1. OCD DRVP=10 CALOUT=1
621 11:05:23.666950
622 11:05:23.670333 1. OCD DRVP calibration OK! DRVP=10
623 11:05:23.670711
624 11:05:23.670986
625 11:05:23.671236
626 11:05:23.671519 K ODTN
627 11:05:23.673527 3. OCD ODTN=0 ,CALOUT=1
628 11:05:23.676716 3. OCD ODTN=1 ,CALOUT=1
629 11:05:23.677090 3. OCD ODTN=2 ,CALOUT=1
630 11:05:23.679750 3. OCD ODTN=3 ,CALOUT=1
631 11:05:23.683157 3. OCD ODTN=4 ,CALOUT=1
632 11:05:23.683554 3. OCD ODTN=5 ,CALOUT=1
633 11:05:23.686370 3. OCD ODTN=6 ,CALOUT=1
634 11:05:23.689658 3. OCD ODTN=7 ,CALOUT=1
635 11:05:23.690024 3. OCD ODTN=8 ,CALOUT=1
636 11:05:23.693223 3. OCD ODTN=9 ,CALOUT=1
637 11:05:23.696121 3. OCD ODTN=10 ,CALOUT=1
638 11:05:23.696489 3. OCD ODTN=11 ,CALOUT=1
639 11:05:23.699408 3. OCD ODTN=12 ,CALOUT=1
640 11:05:23.702668 3. OCD ODTN=13 ,CALOUT=1
641 11:05:23.703095 3. OCD ODTN=14 ,CALOUT=1
642 11:05:23.706267 3. OCD ODTN=15 ,CALOUT=0
643 11:05:23.706583
644 11:05:23.709596 3. OCD ODTN calibration OK! ODTN=15
645 11:05:23.709955
646 11:05:23.712573 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
647 11:05:23.716323 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
648 11:05:23.722541 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
649 11:05:23.722979
650 11:05:23.723262 [DramcInit]
651 11:05:23.725942 AutoRefreshCKEOff AutoREF OFF
652 11:05:23.728986 DDRPhyPLLSetting-CKEOFF
653 11:05:23.732214 DDRPhyPLLSetting-CKEON
654 11:05:23.732624
655 11:05:23.732926 Enable WDQS
656 11:05:23.733207 ==
657 11:05:23.739077 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
658 11:05:23.742138 fsp= 1, odt_onoff= 1, Byte mode= 0
659 11:05:23.742535 ==
660 11:05:23.742839 [Duty_Offset_Calibration]
661 11:05:23.743121
662 11:05:23.745341 ===========================
663 11:05:23.748367 B0:1 B1:-1 CA:0
664 11:05:23.769170 ==
665 11:05:23.772475 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
666 11:05:23.775711 fsp= 1, odt_onoff= 1, Byte mode= 0
667 11:05:23.776071 ==
668 11:05:23.778921 [Duty_Offset_Calibration]
669 11:05:23.779380
670 11:05:23.781955 ===========================
671 11:05:23.782312 B0:1 B1:0 CA:0
672 11:05:23.814512 [ModeRegInit_LP4] CH0 RK0
673 11:05:23.817781 Write Rank0 MR13 =0x18
674 11:05:23.818151 Write Rank0 MR12 =0x5d
675 11:05:23.820846 Write Rank0 MR1 =0x56
676 11:05:23.824283 Write Rank0 MR2 =0x1a
677 11:05:23.824649 Write Rank0 MR11 =0x0
678 11:05:23.827413 Write Rank0 MR22 =0x38
679 11:05:23.831003 Write Rank0 MR14 =0x5d
680 11:05:23.831371 Write Rank0 MR3 =0x30
681 11:05:23.834055 Write Rank0 MR13 =0x58
682 11:05:23.834456 Write Rank0 MR12 =0x5d
683 11:05:23.837259 Write Rank0 MR1 =0x56
684 11:05:23.840687 Write Rank0 MR2 =0x2d
685 11:05:23.841087 Write Rank0 MR11 =0x23
686 11:05:23.843688 Write Rank0 MR22 =0x34
687 11:05:23.847314 Write Rank0 MR14 =0x10
688 11:05:23.847741 Write Rank0 MR3 =0x30
689 11:05:23.850246 Write Rank0 MR13 =0xd8
690 11:05:23.850601 [ModeRegInit_LP4] CH0 RK1
691 11:05:23.853819 Write Rank1 MR13 =0x18
692 11:05:23.857144 Write Rank1 MR12 =0x5d
693 11:05:23.857534 Write Rank1 MR1 =0x56
694 11:05:23.860509 Write Rank1 MR2 =0x1a
695 11:05:23.863839 Write Rank1 MR11 =0x0
696 11:05:23.864189 Write Rank1 MR22 =0x38
697 11:05:23.866916 Write Rank1 MR14 =0x5d
698 11:05:23.867271 Write Rank1 MR3 =0x30
699 11:05:23.870257 Write Rank1 MR13 =0x58
700 11:05:23.873506 Write Rank1 MR12 =0x5d
701 11:05:23.873859 Write Rank1 MR1 =0x56
702 11:05:23.876786 Write Rank1 MR2 =0x2d
703 11:05:23.879860 Write Rank1 MR11 =0x23
704 11:05:23.880286 Write Rank1 MR22 =0x34
705 11:05:23.883328 Write Rank1 MR14 =0x10
706 11:05:23.883900 Write Rank1 MR3 =0x30
707 11:05:23.886341 Write Rank1 MR13 =0xd8
708 11:05:23.889737 [ModeRegInit_LP4] CH1 RK0
709 11:05:23.890201 Write Rank0 MR13 =0x18
710 11:05:23.893096 Write Rank0 MR12 =0x5d
711 11:05:23.896401 Write Rank0 MR1 =0x56
712 11:05:23.896753 Write Rank0 MR2 =0x1a
713 11:05:23.899784 Write Rank0 MR11 =0x0
714 11:05:23.900159 Write Rank0 MR22 =0x38
715 11:05:23.902735 Write Rank0 MR14 =0x5d
716 11:05:23.906510 Write Rank0 MR3 =0x30
717 11:05:23.906862 Write Rank0 MR13 =0x58
718 11:05:23.909903 Write Rank0 MR12 =0x5d
719 11:05:23.912911 Write Rank0 MR1 =0x56
720 11:05:23.913270 Write Rank0 MR2 =0x2d
721 11:05:23.916174 Write Rank0 MR11 =0x23
722 11:05:23.916526 Write Rank0 MR22 =0x34
723 11:05:23.919389 Write Rank0 MR14 =0x10
724 11:05:23.922425 Write Rank0 MR3 =0x30
725 11:05:23.922864 Write Rank0 MR13 =0xd8
726 11:05:23.925587 [ModeRegInit_LP4] CH1 RK1
727 11:05:23.928981 Write Rank1 MR13 =0x18
728 11:05:23.929382 Write Rank1 MR12 =0x5d
729 11:05:23.932232 Write Rank1 MR1 =0x56
730 11:05:23.932588 Write Rank1 MR2 =0x1a
731 11:05:23.935650 Write Rank1 MR11 =0x0
732 11:05:23.938778 Write Rank1 MR22 =0x38
733 11:05:23.939182 Write Rank1 MR14 =0x5d
734 11:05:23.941996 Write Rank1 MR3 =0x30
735 11:05:23.945656 Write Rank1 MR13 =0x58
736 11:05:23.946008 Write Rank1 MR12 =0x5d
737 11:05:23.948766 Write Rank1 MR1 =0x56
738 11:05:23.949116 Write Rank1 MR2 =0x2d
739 11:05:23.951859 Write Rank1 MR11 =0x23
740 11:05:23.955312 Write Rank1 MR22 =0x34
741 11:05:23.955698 Write Rank1 MR14 =0x10
742 11:05:23.958444 Write Rank1 MR3 =0x30
743 11:05:23.961787 Write Rank1 MR13 =0xd8
744 11:05:23.962140 match AC timing 3
745 11:05:23.971438 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
746 11:05:23.975157 DramC Write-DBI off
747 11:05:23.975544 DramC Read-DBI off
748 11:05:23.977990 Write Rank0 MR13 =0x59
749 11:05:23.978340 ==
750 11:05:23.981324 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
751 11:05:23.984692 fsp= 1, odt_onoff= 1, Byte mode= 0
752 11:05:23.985045 ==
753 11:05:23.988051 === u2Vref_new: 0x56 --> 0x2d
754 11:05:23.991536 === u2Vref_new: 0x58 --> 0x38
755 11:05:23.994443 === u2Vref_new: 0x5a --> 0x39
756 11:05:23.997789 === u2Vref_new: 0x5c --> 0x3c
757 11:05:24.000838 === u2Vref_new: 0x5e --> 0x3d
758 11:05:24.004184 === u2Vref_new: 0x60 --> 0xa0
759 11:05:24.007512 [CA 0] Center 34 (6~63) winsize 58
760 11:05:24.010805 [CA 1] Center 35 (7~63) winsize 57
761 11:05:24.014192 [CA 2] Center 28 (-1~58) winsize 60
762 11:05:24.017390 [CA 3] Center 23 (-4~51) winsize 56
763 11:05:24.020878 [CA 4] Center 25 (-3~53) winsize 57
764 11:05:24.023944 [CA 5] Center 29 (0~59) winsize 60
765 11:05:24.024382
766 11:05:24.027256 [CATrainingPosCal] consider 1 rank data
767 11:05:24.030543 u2DelayCellTimex100 = 744/100 ps
768 11:05:24.033745 CA0 delay=34 (6~63),Diff = 11 PI (14 cell)
769 11:05:24.037182 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
770 11:05:24.040209 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
771 11:05:24.043633 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
772 11:05:24.049934 CA4 delay=25 (-3~53),Diff = 2 PI (2 cell)
773 11:05:24.053617 CA5 delay=29 (0~59),Diff = 6 PI (7 cell)
774 11:05:24.054025
775 11:05:24.056629 CA PerBit enable=1, Macro0, CA PI delay=23
776 11:05:24.059990 === u2Vref_new: 0x5c --> 0x3c
777 11:05:24.060407
778 11:05:24.060771 Vref(ca) range 1: 28
779 11:05:24.061113
780 11:05:24.063105 CS Dly= 7 (38-0-32)
781 11:05:24.066733 Write Rank0 MR13 =0xd8
782 11:05:24.067139 Write Rank0 MR13 =0xd8
783 11:05:24.069660 Write Rank0 MR12 =0x5c
784 11:05:24.070077 Write Rank1 MR13 =0x59
785 11:05:24.073129 ==
786 11:05:24.076093 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
787 11:05:24.079363 fsp= 1, odt_onoff= 1, Byte mode= 0
788 11:05:24.079778 ==
789 11:05:24.082786 === u2Vref_new: 0x56 --> 0x2d
790 11:05:24.086057 === u2Vref_new: 0x58 --> 0x38
791 11:05:24.089533 === u2Vref_new: 0x5a --> 0x39
792 11:05:24.092628 === u2Vref_new: 0x5c --> 0x3c
793 11:05:24.096060 === u2Vref_new: 0x5e --> 0x3d
794 11:05:24.099049 === u2Vref_new: 0x60 --> 0xa0
795 11:05:24.102580 [CA 0] Center 35 (7~63) winsize 57
796 11:05:24.105464 [CA 1] Center 35 (7~63) winsize 57
797 11:05:24.108936 [CA 2] Center 29 (0~58) winsize 59
798 11:05:24.112231 [CA 3] Center 23 (-5~52) winsize 58
799 11:05:24.115625 [CA 4] Center 24 (-4~52) winsize 57
800 11:05:24.118975 [CA 5] Center 29 (0~58) winsize 59
801 11:05:24.119341
802 11:05:24.122291 [CATrainingPosCal] consider 2 rank data
803 11:05:24.125391 u2DelayCellTimex100 = 744/100 ps
804 11:05:24.128772 CA0 delay=35 (7~63),Diff = 12 PI (15 cell)
805 11:05:24.131579 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
806 11:05:24.135186 CA2 delay=29 (0~58),Diff = 6 PI (7 cell)
807 11:05:24.138401 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
808 11:05:24.141760 CA4 delay=24 (-3~52),Diff = 1 PI (1 cell)
809 11:05:24.145178 CA5 delay=29 (0~58),Diff = 6 PI (7 cell)
810 11:05:24.145681
811 11:05:24.151516 CA PerBit enable=1, Macro0, CA PI delay=23
812 11:05:24.151888 === u2Vref_new: 0x60 --> 0xa0
813 11:05:24.152252
814 11:05:24.154846 Vref(ca) range 1: 32
815 11:05:24.155213
816 11:05:24.158271 CS Dly= 6 (37-0-32)
817 11:05:24.158637 Write Rank1 MR13 =0xd8
818 11:05:24.161468 Write Rank1 MR13 =0xd8
819 11:05:24.164608 Write Rank1 MR12 =0x60
820 11:05:24.168015 [RankSwap] Rank num 2, (Multi 1), Rank 0
821 11:05:24.168381 Write Rank0 MR2 =0xad
822 11:05:24.171201 [Write Leveling]
823 11:05:24.174569 delay byte0 byte1 byte2 byte3
824 11:05:24.174931
825 11:05:24.175291 10 0 0
826 11:05:24.177659 11 0 0
827 11:05:24.178045 12 0 0
828 11:05:24.178412 13 0 0
829 11:05:24.180820 14 0 0
830 11:05:24.181189 15 0 0
831 11:05:24.184295 16 0 0
832 11:05:24.184664 17 0 0
833 11:05:24.185031 18 0 0
834 11:05:24.187860 19 0 0
835 11:05:24.188308 20 0 0
836 11:05:24.191139 21 0 0
837 11:05:24.191627 22 0 0
838 11:05:24.194357 23 0 0
839 11:05:24.194820 24 0 0
840 11:05:24.195201 25 0 0
841 11:05:24.197480 26 0 0
842 11:05:24.197853 27 0 ff
843 11:05:24.200704 28 0 ff
844 11:05:24.201081 29 0 ff
845 11:05:24.203910 30 0 ff
846 11:05:24.204285 31 0 ff
847 11:05:24.207109 32 ff ff
848 11:05:24.207502 33 ff ff
849 11:05:24.207802 34 ff ff
850 11:05:24.210975 35 ff ff
851 11:05:24.211424 36 ff ff
852 11:05:24.213902 37 ff ff
853 11:05:24.214264 38 ff ff
854 11:05:24.220135 pass bytecount = 0xff (0xff: all bytes pass)
855 11:05:24.220560
856 11:05:24.220834 DQS0 dly: 32
857 11:05:24.221088 DQS1 dly: 27
858 11:05:24.223617 Write Rank0 MR2 =0x2d
859 11:05:24.226700 [RankSwap] Rank num 2, (Multi 1), Rank 0
860 11:05:24.229920 Write Rank0 MR1 =0xd6
861 11:05:24.230274 [Gating]
862 11:05:24.230546 ==
863 11:05:24.237043 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
864 11:05:24.239733 fsp= 1, odt_onoff= 1, Byte mode= 0
865 11:05:24.240090 ==
866 11:05:24.242966 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
867 11:05:24.246051 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
868 11:05:24.253097 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
869 11:05:24.255993 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
870 11:05:24.259583 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
871 11:05:24.266075 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
872 11:05:24.269356 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
873 11:05:24.272753 [Byte 0] Lead/lag falling Transition (3, 1, 24)
874 11:05:24.278995 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
875 11:05:24.282418 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
876 11:05:24.286276 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
877 11:05:24.292189 3 2 8 |2c2c 2c2b |(11 0)(11 11) |(1 0)(1 0)| 0
878 11:05:24.295709 [Byte 0] Lead/lag Transition tap number (5)
879 11:05:24.298862 3 2 12 |201 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
880 11:05:24.302230 3 2 16 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
881 11:05:24.308289 3 2 20 |3534 1110 |(11 11)(11 11) |(0 0)(0 0)| 0
882 11:05:24.311922 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
883 11:05:24.315043 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
884 11:05:24.321506 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
885 11:05:24.324853 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
886 11:05:24.327904 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
887 11:05:24.334658 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
888 11:05:24.337821 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
889 11:05:24.341406 [Byte 1] Lead/lag falling Transition (3, 3, 16)
890 11:05:24.347823 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
891 11:05:24.351203 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
892 11:05:24.354537 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
893 11:05:24.361366 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
894 11:05:24.364464 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
895 11:05:24.367687 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
896 11:05:24.374046 3 4 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
897 11:05:24.377432 3 4 16 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
898 11:05:24.380838 3 4 20 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
899 11:05:24.387137 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
900 11:05:24.390459 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
901 11:05:24.393717 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
902 11:05:24.400307 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
903 11:05:24.403447 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
904 11:05:24.406677 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
905 11:05:24.413423 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
906 11:05:24.416658 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
907 11:05:24.420052 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
908 11:05:24.426282 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
909 11:05:24.429420 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
910 11:05:24.432777 [Byte 0] Lead/lag falling Transition (3, 6, 0)
911 11:05:24.435842 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
912 11:05:24.442684 [Byte 1] Lead/lag falling Transition (3, 6, 4)
913 11:05:24.445611 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
914 11:05:24.449202 [Byte 0] Lead/lag Transition tap number (3)
915 11:05:24.452608 [Byte 1] Lead/lag Transition tap number (2)
916 11:05:24.459246 3 6 12 |606 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
917 11:05:24.462060 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
918 11:05:24.465275 [Byte 0]First pass (3, 6, 16)
919 11:05:24.468519 3 6 20 |4646 3e3e |(0 0)(11 11) |(0 0)(0 0)| 0
920 11:05:24.472071 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
921 11:05:24.475212 [Byte 1]First pass (3, 6, 24)
922 11:05:24.478370 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
923 11:05:24.485007 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
924 11:05:24.488553 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
925 11:05:24.491800 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
926 11:05:24.495034 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
927 11:05:24.498146 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
928 11:05:24.504997 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
929 11:05:24.508086 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
930 11:05:24.511317 All bytes gating window > 1UI, Early break!
931 11:05:24.511482
932 11:05:24.514928 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
933 11:05:24.515375
934 11:05:24.518009 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
935 11:05:24.518440
936 11:05:24.521426
937 11:05:24.521907
938 11:05:24.524750 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
939 11:05:24.525152
940 11:05:24.527976 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
941 11:05:24.528405
942 11:05:24.528755
943 11:05:24.531110 Write Rank0 MR1 =0x56
944 11:05:24.531608
945 11:05:24.534743 best RODT dly(2T, 0.5T) = (2, 3)
946 11:05:24.535166
947 11:05:24.537943 best RODT dly(2T, 0.5T) = (2, 3)
948 11:05:24.538556 ==
949 11:05:24.541137 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
950 11:05:24.544548 fsp= 1, odt_onoff= 1, Byte mode= 0
951 11:05:24.545027 ==
952 11:05:24.550906 Start DQ dly to find pass range UseTestEngine =0
953 11:05:24.554154 x-axis: bit #, y-axis: DQ dly (-127~63)
954 11:05:24.554711 RX Vref Scan = 0
955 11:05:24.557409 -26, [0] xxxxxxxx xxxxxxxx [MSB]
956 11:05:24.560635 -25, [0] xxxxxxxx xxxxxxxx [MSB]
957 11:05:24.564135 -24, [0] xxxxxxxx xxxxxxxx [MSB]
958 11:05:24.567319 -23, [0] xxxxxxxx xxxxxxxx [MSB]
959 11:05:24.570691 -22, [0] xxxxxxxx xxxxxxxx [MSB]
960 11:05:24.571168 -21, [0] xxxxxxxx xxxxxxxx [MSB]
961 11:05:24.573692 -20, [0] xxxxxxxx xxxxxxxx [MSB]
962 11:05:24.577152 -19, [0] xxxxxxxx xxxxxxxx [MSB]
963 11:05:24.580309 -18, [0] xxxxxxxx xxxxxxxx [MSB]
964 11:05:24.583942 -17, [0] xxxxxxxx xxxxxxxx [MSB]
965 11:05:24.587150 -16, [0] xxxxxxxx xxxxxxxx [MSB]
966 11:05:24.590454 -15, [0] xxxxxxxx xxxxxxxx [MSB]
967 11:05:24.593492 -14, [0] xxxxxxxx xxxxxxxx [MSB]
968 11:05:24.596778 -13, [0] xxxxxxxx xxxxxxxx [MSB]
969 11:05:24.597210 -12, [0] xxxxxxxx xxxxxxxx [MSB]
970 11:05:24.600181 -11, [0] xxxxxxxx xxxxxxxx [MSB]
971 11:05:24.603306 -10, [0] xxxxxxxx xxxxxxxx [MSB]
972 11:05:24.606578 -9, [0] xxxxxxxx xxxxxxxx [MSB]
973 11:05:24.609858 -8, [0] xxxxxxxx xxxxxxxx [MSB]
974 11:05:24.613127 -7, [0] xxxxxxxx xxxxxxxx [MSB]
975 11:05:24.616678 -6, [0] xxxxxxxx xxxxxxxx [MSB]
976 11:05:24.619661 -5, [0] xxxxxxxx xxxxxxxx [MSB]
977 11:05:24.620045 -4, [0] xxxxxxxx oxxxxxxx [MSB]
978 11:05:24.622885 -3, [0] xxxxxxxx oxxoxxxx [MSB]
979 11:05:24.626293 -2, [0] xxxoxxxx oxxoxxxx [MSB]
980 11:05:24.629308 -1, [0] xxxoxxxx oxxoxxxx [MSB]
981 11:05:24.633098 0, [0] xxxoxxxx ooxoooxx [MSB]
982 11:05:24.635859 1, [0] xxxoxxxx ooxoooxx [MSB]
983 11:05:24.639427 2, [0] xxxoxoxx ooxoooox [MSB]
984 11:05:24.640071 3, [0] xxxoxoox ooxoooox [MSB]
985 11:05:24.642563 4, [0] xxxoxooo ooxooooo [MSB]
986 11:05:24.645956 5, [0] oxxooooo ooxooooo [MSB]
987 11:05:24.649211 6, [0] oxoooooo ooxooooo [MSB]
988 11:05:24.652476 7, [0] oooooooo ooxooooo [MSB]
989 11:05:24.655816 32, [0] oooxoooo oooooooo [MSB]
990 11:05:24.659409 33, [0] oooxoooo xooooooo [MSB]
991 11:05:24.659818 34, [0] oooxoooo xooxoooo [MSB]
992 11:05:24.662089 35, [0] oooxoooo xxoxoooo [MSB]
993 11:05:24.665541 36, [0] oooxoxoo xxoxxoxo [MSB]
994 11:05:24.668848 37, [0] oooxoxxx xxoxxxxo [MSB]
995 11:05:24.672107 38, [0] oooxoxxx xxoxxxxo [MSB]
996 11:05:24.675348 39, [0] oooxoxxx xxoxxxxx [MSB]
997 11:05:24.678474 40, [0] ooxxxxxx xxoxxxxx [MSB]
998 11:05:24.681976 41, [0] xxxxxxxx xxoxxxxx [MSB]
999 11:05:24.682434 42, [0] xxxxxxxx xxoxxxxx [MSB]
1000 11:05:24.685048 43, [0] xxxxxxxx xxxxxxxx [MSB]
1001 11:05:24.688464 iDelay=43, Bit 0, Center 22 (5 ~ 40) 36
1002 11:05:24.691753 iDelay=43, Bit 1, Center 23 (7 ~ 40) 34
1003 11:05:24.698289 iDelay=43, Bit 2, Center 22 (6 ~ 39) 34
1004 11:05:24.701728 iDelay=43, Bit 3, Center 14 (-2 ~ 31) 34
1005 11:05:24.704872 iDelay=43, Bit 4, Center 22 (5 ~ 39) 35
1006 11:05:24.707877 iDelay=43, Bit 5, Center 18 (2 ~ 35) 34
1007 11:05:24.711349 iDelay=43, Bit 6, Center 19 (3 ~ 36) 34
1008 11:05:24.714614 iDelay=43, Bit 7, Center 20 (4 ~ 36) 33
1009 11:05:24.718117 iDelay=43, Bit 8, Center 14 (-4 ~ 32) 37
1010 11:05:24.721436 iDelay=43, Bit 9, Center 17 (0 ~ 34) 35
1011 11:05:24.724450 iDelay=43, Bit 10, Center 25 (8 ~ 42) 35
1012 11:05:24.727881 iDelay=43, Bit 11, Center 15 (-3 ~ 33) 37
1013 11:05:24.730802 iDelay=43, Bit 12, Center 17 (0 ~ 35) 36
1014 11:05:24.737680 iDelay=43, Bit 13, Center 18 (0 ~ 36) 37
1015 11:05:24.740784 iDelay=43, Bit 14, Center 18 (2 ~ 35) 34
1016 11:05:24.743954 iDelay=43, Bit 15, Center 21 (4 ~ 38) 35
1017 11:05:24.744270 ==
1018 11:05:24.747270 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1019 11:05:24.750579 fsp= 1, odt_onoff= 1, Byte mode= 0
1020 11:05:24.750886 ==
1021 11:05:24.754401 DQS Delay:
1022 11:05:24.754711 DQS0 = 0, DQS1 = 0
1023 11:05:24.757037 DQM Delay:
1024 11:05:24.757326 DQM0 = 20, DQM1 = 18
1025 11:05:24.757582 DQ Delay:
1026 11:05:24.760293 DQ0 =22, DQ1 =23, DQ2 =22, DQ3 =14
1027 11:05:24.764011 DQ4 =22, DQ5 =18, DQ6 =19, DQ7 =20
1028 11:05:24.767358 DQ8 =14, DQ9 =17, DQ10 =25, DQ11 =15
1029 11:05:24.770112 DQ12 =17, DQ13 =18, DQ14 =18, DQ15 =21
1030 11:05:24.770413
1031 11:05:24.773407
1032 11:05:24.773695 DramC Write-DBI off
1033 11:05:24.773952 ==
1034 11:05:24.780055 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1035 11:05:24.783208 fsp= 1, odt_onoff= 1, Byte mode= 0
1036 11:05:24.783521 ==
1037 11:05:24.786539 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1038 11:05:24.786947
1039 11:05:24.790095 Begin, DQ Scan Range 923~1179
1040 11:05:24.790458
1041 11:05:24.790733
1042 11:05:24.792870 TX Vref Scan disable
1043 11:05:24.796087 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1044 11:05:24.799434 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1045 11:05:24.802599 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1046 11:05:24.806049 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1047 11:05:24.809179 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1048 11:05:24.812468 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1049 11:05:24.815881 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1050 11:05:24.818998 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1051 11:05:24.822382 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1052 11:05:24.825814 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1053 11:05:24.828988 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1054 11:05:24.835421 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1055 11:05:24.838806 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1056 11:05:24.841945 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1057 11:05:24.845208 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1058 11:05:24.848663 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1059 11:05:24.851799 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1060 11:05:24.855129 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1061 11:05:24.858661 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1062 11:05:24.861458 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1063 11:05:24.865004 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1064 11:05:24.868480 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1065 11:05:24.871521 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1066 11:05:24.874802 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1067 11:05:24.881252 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1068 11:05:24.884585 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1069 11:05:24.887860 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1070 11:05:24.891265 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1071 11:05:24.894313 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1072 11:05:24.897665 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1073 11:05:24.901018 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1074 11:05:24.904392 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1075 11:05:24.907472 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1076 11:05:24.910777 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1077 11:05:24.914152 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1078 11:05:24.917381 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1079 11:05:24.923897 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1080 11:05:24.927247 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1081 11:05:24.930317 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1082 11:05:24.933838 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1083 11:05:24.937064 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1084 11:05:24.940070 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1085 11:05:24.943585 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1086 11:05:24.947066 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1087 11:05:24.950058 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1088 11:05:24.953156 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1089 11:05:24.956600 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1090 11:05:24.959830 970 |3 6 10|[0] xxxxxxxx ooxoxxxx [MSB]
1091 11:05:24.963198 971 |3 6 11|[0] xxxxxxxx ooxoxxxx [MSB]
1092 11:05:24.966258 972 |3 6 12|[0] xxxxxxxx ooxooxxx [MSB]
1093 11:05:24.969650 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1094 11:05:24.973132 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1095 11:05:24.979403 975 |3 6 15|[0] xxxxxxxx ooxooooo [MSB]
1096 11:05:24.982712 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1097 11:05:24.985936 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1098 11:05:24.989404 978 |3 6 18|[0] xxxoooox oooooooo [MSB]
1099 11:05:24.992693 979 |3 6 19|[0] xoxooooo oooooooo [MSB]
1100 11:05:24.995812 980 |3 6 20|[0] xooooooo oooooooo [MSB]
1101 11:05:24.999098 990 |3 6 30|[0] oooooooo oooxoooo [MSB]
1102 11:05:25.002446 991 |3 6 31|[0] oooooooo xxoxxxoo [MSB]
1103 11:05:25.008918 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1104 11:05:25.012180 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1105 11:05:25.015423 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1106 11:05:25.018843 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1107 11:05:25.022155 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1108 11:05:25.025310 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
1109 11:05:25.028514 998 |3 6 38|[0] oooxoxxo xxxxxxxx [MSB]
1110 11:05:25.031840 999 |3 6 39|[0] oooxoxxo xxxxxxxx [MSB]
1111 11:05:25.035213 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
1112 11:05:25.038288 Byte0, DQ PI dly=988, DQM PI dly= 988
1113 11:05:25.045056 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
1114 11:05:25.045131
1115 11:05:25.048385 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
1116 11:05:25.048455
1117 11:05:25.051598 Byte1, DQ PI dly=981, DQM PI dly= 981
1118 11:05:25.054814 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1119 11:05:25.054884
1120 11:05:25.061313 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1121 11:05:25.061381
1122 11:05:25.061438 ==
1123 11:05:25.064913 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1124 11:05:25.068010 fsp= 1, odt_onoff= 1, Byte mode= 0
1125 11:05:25.068077 ==
1126 11:05:25.074503 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1127 11:05:25.074572
1128 11:05:25.077858 Begin, DQ Scan Range 957~1021
1129 11:05:25.077922 Write Rank0 MR14 =0x0
1130 11:05:25.086254
1131 11:05:25.086324 CH=0, VrefRange= 0, VrefLevel = 0
1132 11:05:25.092861 TX Bit0 (984~995) 12 989, Bit8 (971~985) 15 978,
1133 11:05:25.096175 TX Bit1 (982~995) 14 988, Bit9 (974~987) 14 980,
1134 11:05:25.102655 TX Bit2 (983~996) 14 989, Bit10 (977~991) 15 984,
1135 11:05:25.105987 TX Bit3 (977~991) 15 984, Bit11 (973~983) 11 978,
1136 11:05:25.109395 TX Bit4 (982~993) 12 987, Bit12 (975~985) 11 980,
1137 11:05:25.115626 TX Bit5 (978~992) 15 985, Bit13 (976~984) 9 980,
1138 11:05:25.119045 TX Bit6 (979~992) 14 985, Bit14 (976~989) 14 982,
1139 11:05:25.125716 TX Bit7 (982~993) 12 987, Bit15 (977~991) 15 984,
1140 11:05:25.125796
1141 11:05:25.125858 Write Rank0 MR14 =0x2
1142 11:05:25.134566
1143 11:05:25.134639 CH=0, VrefRange= 0, VrefLevel = 2
1144 11:05:25.140871 TX Bit0 (984~996) 13 990, Bit8 (971~986) 16 978,
1145 11:05:25.144299 TX Bit1 (981~996) 16 988, Bit9 (973~988) 16 980,
1146 11:05:25.150990 TX Bit2 (983~997) 15 990, Bit10 (977~992) 16 984,
1147 11:05:25.153966 TX Bit3 (977~991) 15 984, Bit11 (972~983) 12 977,
1148 11:05:25.157289 TX Bit4 (981~994) 14 987, Bit12 (975~986) 12 980,
1149 11:05:25.163915 TX Bit5 (978~993) 16 985, Bit13 (975~986) 12 980,
1150 11:05:25.167273 TX Bit6 (979~992) 14 985, Bit14 (975~989) 15 982,
1151 11:05:25.173805 TX Bit7 (981~993) 13 987, Bit15 (977~992) 16 984,
1152 11:05:25.173877
1153 11:05:25.176783 wait MRW command Rank0 MR14 =0x4 fired (1)
1154 11:05:25.176852 Write Rank0 MR14 =0x4
1155 11:05:25.186626
1156 11:05:25.186695 CH=0, VrefRange= 0, VrefLevel = 4
1157 11:05:25.193150 TX Bit0 (984~996) 13 990, Bit8 (970~987) 18 978,
1158 11:05:25.196746 TX Bit1 (982~996) 15 989, Bit9 (973~988) 16 980,
1159 11:05:25.203016 TX Bit2 (983~998) 16 990, Bit10 (977~993) 17 985,
1160 11:05:25.206117 TX Bit3 (977~992) 16 984, Bit11 (972~984) 13 978,
1161 11:05:25.209640 TX Bit4 (982~995) 14 988, Bit12 (975~987) 13 981,
1162 11:05:25.215998 TX Bit5 (978~993) 16 985, Bit13 (975~987) 13 981,
1163 11:05:25.219278 TX Bit6 (978~993) 16 985, Bit14 (975~990) 16 982,
1164 11:05:25.225995 TX Bit7 (981~994) 14 987, Bit15 (976~992) 17 984,
1165 11:05:25.226068
1166 11:05:25.226133 Write Rank0 MR14 =0x6
1167 11:05:25.235110
1168 11:05:25.235184 CH=0, VrefRange= 0, VrefLevel = 6
1169 11:05:25.241635 TX Bit0 (983~998) 16 990, Bit8 (970~988) 19 979,
1170 11:05:25.245104 TX Bit1 (981~998) 18 989, Bit9 (973~989) 17 981,
1171 11:05:25.299008 TX Bit2 (983~998) 16 990, Bit10 (977~993) 17 985,
1172 11:05:25.299149 TX Bit3 (976~992) 17 984, Bit11 (971~985) 15 978,
1173 11:05:25.299405 TX Bit4 (980~996) 17 988, Bit12 (974~988) 15 981,
1174 11:05:25.299494 TX Bit5 (978~994) 17 986, Bit13 (974~988) 15 981,
1175 11:05:25.299966 TX Bit6 (978~993) 16 985, Bit14 (975~990) 16 982,
1176 11:05:25.300213 TX Bit7 (980~995) 16 987, Bit15 (976~993) 18 984,
1177 11:05:25.300279
1178 11:05:25.300337 Write Rank0 MR14 =0x8
1179 11:05:25.300393
1180 11:05:25.300448 CH=0, VrefRange= 0, VrefLevel = 8
1181 11:05:25.300520 TX Bit0 (983~998) 16 990, Bit8 (969~988) 20 978,
1182 11:05:25.300579 TX Bit1 (981~998) 18 989, Bit9 (972~989) 18 980,
1183 11:05:25.300638 TX Bit2 (982~999) 18 990, Bit10 (977~995) 19 986,
1184 11:05:25.337477 TX Bit3 (976~993) 18 984, Bit11 (971~986) 16 978,
1185 11:05:25.337892 TX Bit4 (979~997) 19 988, Bit12 (974~988) 15 981,
1186 11:05:25.338143 TX Bit5 (977~994) 18 985, Bit13 (974~988) 15 981,
1187 11:05:25.338212 TX Bit6 (978~994) 17 986, Bit14 (974~991) 18 982,
1188 11:05:25.338457 TX Bit7 (981~996) 16 988, Bit15 (976~994) 19 985,
1189 11:05:25.338520
1190 11:05:25.338598 Write Rank0 MR14 =0xa
1191 11:05:25.338659
1192 11:05:25.338714 CH=0, VrefRange= 0, VrefLevel = 10
1193 11:05:25.341271 TX Bit0 (982~999) 18 990, Bit8 (969~989) 21 979,
1194 11:05:25.344558 TX Bit1 (980~999) 20 989, Bit9 (971~989) 19 980,
1195 11:05:25.347729 TX Bit2 (982~999) 18 990, Bit10 (976~995) 20 985,
1196 11:05:25.351040 TX Bit3 (976~993) 18 984, Bit11 (970~987) 18 978,
1197 11:05:25.357652 TX Bit4 (979~998) 20 988, Bit12 (974~989) 16 981,
1198 11:05:25.361403 TX Bit5 (977~995) 19 986, Bit13 (974~989) 16 981,
1199 11:05:25.364558 TX Bit6 (978~995) 18 986, Bit14 (974~991) 18 982,
1200 11:05:25.370847 TX Bit7 (980~997) 18 988, Bit15 (976~995) 20 985,
1201 11:05:25.370924
1202 11:05:25.370986 Write Rank0 MR14 =0xc
1203 11:05:25.380607
1204 11:05:25.383968 CH=0, VrefRange= 0, VrefLevel = 12
1205 11:05:25.387134 TX Bit0 (982~999) 18 990, Bit8 (969~989) 21 979,
1206 11:05:25.390651 TX Bit1 (979~999) 21 989, Bit9 (972~990) 19 981,
1207 11:05:25.397277 TX Bit2 (981~999) 19 990, Bit10 (976~996) 21 986,
1208 11:05:25.400290 TX Bit3 (976~993) 18 984, Bit11 (970~988) 19 979,
1209 11:05:25.403521 TX Bit4 (979~998) 20 988, Bit12 (973~989) 17 981,
1210 11:05:25.410372 TX Bit5 (977~995) 19 986, Bit13 (974~989) 16 981,
1211 11:05:25.413562 TX Bit6 (977~995) 19 986, Bit14 (974~992) 19 983,
1212 11:05:25.420148 TX Bit7 (980~998) 19 989, Bit15 (976~995) 20 985,
1213 11:05:25.420218
1214 11:05:25.420278 Write Rank0 MR14 =0xe
1215 11:05:25.429458
1216 11:05:25.432767 CH=0, VrefRange= 0, VrefLevel = 14
1217 11:05:25.436049 TX Bit0 (982~1000) 19 991, Bit8 (969~989) 21 979,
1218 11:05:25.439220 TX Bit1 (979~999) 21 989, Bit9 (970~990) 21 980,
1219 11:05:25.446020 TX Bit2 (980~1000) 21 990, Bit10 (976~996) 21 986,
1220 11:05:25.449066 TX Bit3 (976~994) 19 985, Bit11 (969~989) 21 979,
1221 11:05:25.452295 TX Bit4 (979~999) 21 989, Bit12 (973~989) 17 981,
1222 11:05:25.458759 TX Bit5 (977~996) 20 986, Bit13 (973~989) 17 981,
1223 11:05:25.462302 TX Bit6 (978~996) 19 987, Bit14 (974~993) 20 983,
1224 11:05:25.468554 TX Bit7 (979~999) 21 989, Bit15 (976~996) 21 986,
1225 11:05:25.468631
1226 11:05:25.468694 Write Rank0 MR14 =0x10
1227 11:05:25.478412
1228 11:05:25.482046 CH=0, VrefRange= 0, VrefLevel = 16
1229 11:05:25.484969 TX Bit0 (981~1000) 20 990, Bit8 (969~990) 22 979,
1230 11:05:25.488499 TX Bit1 (979~1000) 22 989, Bit9 (970~990) 21 980,
1231 11:05:25.494739 TX Bit2 (980~1000) 21 990, Bit10 (975~997) 23 986,
1232 11:05:25.497979 TX Bit3 (975~994) 20 984, Bit11 (969~989) 21 979,
1233 11:05:25.504681 TX Bit4 (978~999) 22 988, Bit12 (972~990) 19 981,
1234 11:05:25.507973 TX Bit5 (977~997) 21 987, Bit13 (972~989) 18 980,
1235 11:05:25.511066 TX Bit6 (977~997) 21 987, Bit14 (973~993) 21 983,
1236 11:05:25.517825 TX Bit7 (979~1000) 22 989, Bit15 (975~996) 22 985,
1237 11:05:25.517900
1238 11:05:25.517962 Write Rank0 MR14 =0x12
1239 11:05:25.527802
1240 11:05:25.530753 CH=0, VrefRange= 0, VrefLevel = 18
1241 11:05:25.534165 TX Bit0 (981~1000) 20 990, Bit8 (968~990) 23 979,
1242 11:05:25.537515 TX Bit1 (979~1000) 22 989, Bit9 (970~991) 22 980,
1243 11:05:25.544096 TX Bit2 (979~1000) 22 989, Bit10 (975~997) 23 986,
1244 11:05:25.547199 TX Bit3 (975~994) 20 984, Bit11 (969~989) 21 979,
1245 11:05:25.554095 TX Bit4 (978~999) 22 988, Bit12 (972~991) 20 981,
1246 11:05:25.557154 TX Bit5 (977~998) 22 987, Bit13 (972~990) 19 981,
1247 11:05:25.560654 TX Bit6 (977~998) 22 987, Bit14 (973~994) 22 983,
1248 11:05:25.566788 TX Bit7 (979~1000) 22 989, Bit15 (975~997) 23 986,
1249 11:05:25.566874
1250 11:05:25.566945 Write Rank0 MR14 =0x14
1251 11:05:25.577006
1252 11:05:25.580396 CH=0, VrefRange= 0, VrefLevel = 20
1253 11:05:25.583982 TX Bit0 (981~1001) 21 991, Bit8 (968~990) 23 979,
1254 11:05:25.586894 TX Bit1 (978~1000) 23 989, Bit9 (970~991) 22 980,
1255 11:05:25.593746 TX Bit2 (979~1001) 23 990, Bit10 (975~997) 23 986,
1256 11:05:25.596597 TX Bit3 (975~995) 21 985, Bit11 (969~989) 21 979,
1257 11:05:25.603395 TX Bit4 (978~1000) 23 989, Bit12 (971~991) 21 981,
1258 11:05:25.606774 TX Bit5 (977~998) 22 987, Bit13 (971~990) 20 980,
1259 11:05:25.610465 TX Bit6 (977~999) 23 988, Bit14 (973~995) 23 984,
1260 11:05:25.617161 TX Bit7 (978~1000) 23 989, Bit15 (975~997) 23 986,
1261 11:05:25.617591
1262 11:05:25.617875 Write Rank0 MR14 =0x16
1263 11:05:25.627164
1264 11:05:25.630505 CH=0, VrefRange= 0, VrefLevel = 22
1265 11:05:25.633480 TX Bit0 (980~1000) 21 990, Bit8 (968~991) 24 979,
1266 11:05:25.636988 TX Bit1 (978~1000) 23 989, Bit9 (969~991) 23 980,
1267 11:05:25.643866 TX Bit2 (980~1001) 22 990, Bit10 (975~997) 23 986,
1268 11:05:25.646699 TX Bit3 (975~996) 22 985, Bit11 (969~990) 22 979,
1269 11:05:25.653260 TX Bit4 (978~1000) 23 989, Bit12 (971~992) 22 981,
1270 11:05:25.656254 TX Bit5 (976~999) 24 987, Bit13 (971~991) 21 981,
1271 11:05:25.659834 TX Bit6 (977~999) 23 988, Bit14 (972~995) 24 983,
1272 11:05:25.666436 TX Bit7 (978~1001) 24 989, Bit15 (975~997) 23 986,
1273 11:05:25.666836
1274 11:05:25.667152 Write Rank0 MR14 =0x18
1275 11:05:25.676475
1276 11:05:25.679656 CH=0, VrefRange= 0, VrefLevel = 24
1277 11:05:25.683000 TX Bit0 (979~1001) 23 990, Bit8 (968~991) 24 979,
1278 11:05:25.686208 TX Bit1 (978~1001) 24 989, Bit9 (970~992) 23 981,
1279 11:05:25.692727 TX Bit2 (979~1001) 23 990, Bit10 (975~998) 24 986,
1280 11:05:25.696154 TX Bit3 (974~996) 23 985, Bit11 (969~990) 22 979,
1281 11:05:25.702639 TX Bit4 (978~1000) 23 989, Bit12 (970~992) 23 981,
1282 11:05:25.705939 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
1283 11:05:25.709004 TX Bit6 (977~1000) 24 988, Bit14 (972~996) 25 984,
1284 11:05:25.715717 TX Bit7 (978~1001) 24 989, Bit15 (975~997) 23 986,
1285 11:05:25.716163
1286 11:05:25.716488 Write Rank0 MR14 =0x1a
1287 11:05:25.725775
1288 11:05:25.728986 CH=0, VrefRange= 0, VrefLevel = 26
1289 11:05:25.732212 TX Bit0 (979~1002) 24 990, Bit8 (968~990) 23 979,
1290 11:05:25.735555 TX Bit1 (978~1001) 24 989, Bit9 (969~993) 25 981,
1291 11:05:25.742054 TX Bit2 (979~1002) 24 990, Bit10 (975~998) 24 986,
1292 11:05:25.745443 TX Bit3 (974~997) 24 985, Bit11 (968~990) 23 979,
1293 11:05:25.751912 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1294 11:05:25.755141 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
1295 11:05:25.758447 TX Bit6 (976~1000) 25 988, Bit14 (971~996) 26 983,
1296 11:05:25.765074 TX Bit7 (978~1001) 24 989, Bit15 (974~998) 25 986,
1297 11:05:25.765151
1298 11:05:25.765218 Write Rank0 MR14 =0x1c
1299 11:05:25.775293
1300 11:05:25.778735 CH=0, VrefRange= 0, VrefLevel = 28
1301 11:05:25.782266 TX Bit0 (979~1002) 24 990, Bit8 (968~990) 23 979,
1302 11:05:25.785336 TX Bit1 (978~1002) 25 990, Bit9 (969~992) 24 980,
1303 11:05:25.792174 TX Bit2 (979~1002) 24 990, Bit10 (974~998) 25 986,
1304 11:05:25.795015 TX Bit3 (974~997) 24 985, Bit11 (968~991) 24 979,
1305 11:05:25.801767 TX Bit4 (977~1001) 25 989, Bit12 (970~993) 24 981,
1306 11:05:25.805108 TX Bit5 (976~999) 24 987, Bit13 (970~993) 24 981,
1307 11:05:25.808336 TX Bit6 (977~1000) 24 988, Bit14 (970~996) 27 983,
1308 11:05:25.814782 TX Bit7 (978~1002) 25 990, Bit15 (974~998) 25 986,
1309 11:05:25.814858
1310 11:05:25.814923 Write Rank0 MR14 =0x1e
1311 11:05:25.825069
1312 11:05:25.828355 CH=0, VrefRange= 0, VrefLevel = 30
1313 11:05:25.831571 TX Bit0 (979~1002) 24 990, Bit8 (968~990) 23 979,
1314 11:05:25.835257 TX Bit1 (978~1002) 25 990, Bit9 (969~992) 24 980,
1315 11:05:25.841731 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1316 11:05:25.844975 TX Bit3 (974~997) 24 985, Bit11 (968~991) 24 979,
1317 11:05:25.851319 TX Bit4 (977~1001) 25 989, Bit12 (970~993) 24 981,
1318 11:05:25.854773 TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981,
1319 11:05:25.857833 TX Bit6 (977~1000) 24 988, Bit14 (970~996) 27 983,
1320 11:05:25.864247 TX Bit7 (978~1002) 25 990, Bit15 (974~998) 25 986,
1321 11:05:25.864317
1322 11:05:25.864377 Write Rank0 MR14 =0x20
1323 11:05:25.874904
1324 11:05:25.878238 CH=0, VrefRange= 0, VrefLevel = 32
1325 11:05:25.881818 TX Bit0 (979~1002) 24 990, Bit8 (968~990) 23 979,
1326 11:05:25.884815 TX Bit1 (978~1002) 25 990, Bit9 (969~992) 24 980,
1327 11:05:25.892065 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1328 11:05:25.894902 TX Bit3 (974~997) 24 985, Bit11 (968~991) 24 979,
1329 11:05:25.901349 TX Bit4 (977~1001) 25 989, Bit12 (970~993) 24 981,
1330 11:05:25.904569 TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981,
1331 11:05:25.907849 TX Bit6 (977~1000) 24 988, Bit14 (970~996) 27 983,
1332 11:05:25.914220 TX Bit7 (978~1002) 25 990, Bit15 (974~998) 25 986,
1333 11:05:25.914296
1334 11:05:25.914358 Write Rank0 MR14 =0x22
1335 11:05:25.925789
1336 11:05:25.928161 CH=0, VrefRange= 0, VrefLevel = 34
1337 11:05:25.931548 TX Bit0 (979~1002) 24 990, Bit8 (968~990) 23 979,
1338 11:05:25.934871 TX Bit1 (978~1002) 25 990, Bit9 (969~992) 24 980,
1339 11:05:25.941325 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1340 11:05:25.944538 TX Bit3 (974~997) 24 985, Bit11 (968~991) 24 979,
1341 11:05:25.951058 TX Bit4 (977~1001) 25 989, Bit12 (970~993) 24 981,
1342 11:05:25.954311 TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981,
1343 11:05:25.957867 TX Bit6 (977~1000) 24 988, Bit14 (970~996) 27 983,
1344 11:05:25.964295 TX Bit7 (978~1002) 25 990, Bit15 (974~998) 25 986,
1345 11:05:25.964387
1346 11:05:25.964458 Write Rank0 MR14 =0x24
1347 11:05:25.975091
1348 11:05:25.978363 CH=0, VrefRange= 0, VrefLevel = 36
1349 11:05:25.981539 TX Bit0 (979~1002) 24 990, Bit8 (968~990) 23 979,
1350 11:05:25.984894 TX Bit1 (978~1002) 25 990, Bit9 (969~992) 24 980,
1351 11:05:25.991353 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1352 11:05:25.994872 TX Bit3 (974~997) 24 985, Bit11 (968~991) 24 979,
1353 11:05:26.001514 TX Bit4 (977~1001) 25 989, Bit12 (970~993) 24 981,
1354 11:05:26.004466 TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981,
1355 11:05:26.008091 TX Bit6 (977~1000) 24 988, Bit14 (970~996) 27 983,
1356 11:05:26.014544 TX Bit7 (978~1002) 25 990, Bit15 (974~998) 25 986,
1357 11:05:26.014992
1358 11:05:26.015299 Write Rank0 MR14 =0x26
1359 11:05:26.025021
1360 11:05:26.027991 CH=0, VrefRange= 0, VrefLevel = 38
1361 11:05:26.031343 TX Bit0 (979~1002) 24 990, Bit8 (968~990) 23 979,
1362 11:05:26.035057 TX Bit1 (978~1002) 25 990, Bit9 (969~992) 24 980,
1363 11:05:26.041485 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1364 11:05:26.044728 TX Bit3 (974~997) 24 985, Bit11 (968~991) 24 979,
1365 11:05:26.051019 TX Bit4 (977~1001) 25 989, Bit12 (970~993) 24 981,
1366 11:05:26.054474 TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981,
1367 11:05:26.057559 TX Bit6 (977~1000) 24 988, Bit14 (970~996) 27 983,
1368 11:05:26.064609 TX Bit7 (978~1002) 25 990, Bit15 (974~998) 25 986,
1369 11:05:26.065109
1370 11:05:26.065449
1371 11:05:26.067558 TX Vref found, early break! 363< 373
1372 11:05:26.070854 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
1373 11:05:26.074012 u1DelayCellOfst[0]=6 cells (5 PI)
1374 11:05:26.077178 u1DelayCellOfst[1]=6 cells (5 PI)
1375 11:05:26.080515 u1DelayCellOfst[2]=6 cells (5 PI)
1376 11:05:26.083754 u1DelayCellOfst[3]=0 cells (0 PI)
1377 11:05:26.087070 u1DelayCellOfst[4]=5 cells (4 PI)
1378 11:05:26.090299 u1DelayCellOfst[5]=2 cells (2 PI)
1379 11:05:26.093622 u1DelayCellOfst[6]=3 cells (3 PI)
1380 11:05:26.097119 u1DelayCellOfst[7]=6 cells (5 PI)
1381 11:05:26.100108 Byte0, DQ PI dly=985, DQM PI dly= 987
1382 11:05:26.103444 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1383 11:05:26.103858
1384 11:05:26.106737 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1385 11:05:26.107122
1386 11:05:26.110168 u1DelayCellOfst[8]=0 cells (0 PI)
1387 11:05:26.113340 u1DelayCellOfst[9]=1 cells (1 PI)
1388 11:05:26.116425 u1DelayCellOfst[10]=9 cells (7 PI)
1389 11:05:26.119644 u1DelayCellOfst[11]=0 cells (0 PI)
1390 11:05:26.123372 u1DelayCellOfst[12]=2 cells (2 PI)
1391 11:05:26.126293 u1DelayCellOfst[13]=2 cells (2 PI)
1392 11:05:26.129553 u1DelayCellOfst[14]=5 cells (4 PI)
1393 11:05:26.133293 u1DelayCellOfst[15]=9 cells (7 PI)
1394 11:05:26.136473 Byte1, DQ PI dly=979, DQM PI dly= 982
1395 11:05:26.139205 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1396 11:05:26.139630
1397 11:05:26.145857 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1398 11:05:26.146256
1399 11:05:26.146551 Write Rank0 MR14 =0x1e
1400 11:05:26.146827
1401 11:05:26.149510 Final TX Range 0 Vref 30
1402 11:05:26.149894
1403 11:05:26.155701 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1404 11:05:26.156152
1405 11:05:26.162513 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1406 11:05:26.168755 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1407 11:05:26.175381 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1408 11:05:26.179165 Write Rank0 MR3 =0xb0
1409 11:05:26.181898 DramC Write-DBI on
1410 11:05:26.182290 ==
1411 11:05:26.185213 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1412 11:05:26.188998 fsp= 1, odt_onoff= 1, Byte mode= 0
1413 11:05:26.189474 ==
1414 11:05:26.195148 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1415 11:05:26.195677
1416 11:05:26.195995 Begin, DQ Scan Range 702~766
1417 11:05:26.196278
1418 11:05:26.198655
1419 11:05:26.199122 TX Vref Scan disable
1420 11:05:26.201932 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1421 11:05:26.204826 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1422 11:05:26.208287 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1423 11:05:26.211398 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1424 11:05:26.214744 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1425 11:05:26.217882 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1426 11:05:26.224851 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1427 11:05:26.227854 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1428 11:05:26.231144 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1429 11:05:26.234500 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1430 11:05:26.237693 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1431 11:05:26.241034 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1432 11:05:26.244321 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1433 11:05:26.247732 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1434 11:05:26.250631 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1435 11:05:26.253565 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1436 11:05:26.257019 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1437 11:05:26.260746 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1438 11:05:26.264009 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1439 11:05:26.272829 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1440 11:05:26.276250 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1441 11:05:26.279474 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1442 11:05:26.282479 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1443 11:05:26.285819 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1444 11:05:26.289428 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1445 11:05:26.292665 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1446 11:05:26.295986 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1447 11:05:26.299159 747 |2 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
1448 11:05:26.302336 Byte0, DQ PI dly=733, DQM PI dly= 733
1449 11:05:26.308969 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 29)
1450 11:05:26.309526
1451 11:05:26.312226 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 29)
1452 11:05:26.312632
1453 11:05:26.315326 Byte1, DQ PI dly=725, DQM PI dly= 725
1454 11:05:26.318519 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 21)
1455 11:05:26.318868
1456 11:05:26.325034 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 21)
1457 11:05:26.325423
1458 11:05:26.331876 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1459 11:05:26.338465 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1460 11:05:26.344696 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1461 11:05:26.348377 Write Rank0 MR3 =0x30
1462 11:05:26.348699 DramC Write-DBI off
1463 11:05:26.348982
1464 11:05:26.349254 [DATLAT]
1465 11:05:26.351302 Freq=1600, CH0 RK0, use_rxtx_scan=0
1466 11:05:26.351799
1467 11:05:26.354894 DATLAT Default: 0xf
1468 11:05:26.357864 7, 0xFFFF, sum=0
1469 11:05:26.358320 8, 0xFFFF, sum=0
1470 11:05:26.358670 9, 0xFFFF, sum=0
1471 11:05:26.361012 10, 0xFFFF, sum=0
1472 11:05:26.361389 11, 0xFFFF, sum=0
1473 11:05:26.364203 12, 0xFFFF, sum=0
1474 11:05:26.364713 13, 0xFFFF, sum=0
1475 11:05:26.367811 14, 0x0, sum=1
1476 11:05:26.368280 15, 0x0, sum=2
1477 11:05:26.370956 16, 0x0, sum=3
1478 11:05:26.371450 17, 0x0, sum=4
1479 11:05:26.374683 pattern=2 first_step=14 total pass=5 best_step=16
1480 11:05:26.377484 ==
1481 11:05:26.380878 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1482 11:05:26.384035 fsp= 1, odt_onoff= 1, Byte mode= 0
1483 11:05:26.384454 ==
1484 11:05:26.387514 Start DQ dly to find pass range UseTestEngine =1
1485 11:05:26.393750 x-axis: bit #, y-axis: DQ dly (-127~63)
1486 11:05:26.394138 RX Vref Scan = 1
1487 11:05:26.501001
1488 11:05:26.501116 RX Vref found, early break!
1489 11:05:26.501184
1490 11:05:26.507287 Final RX Vref 11, apply to both rank0 and 1
1491 11:05:26.507374 ==
1492 11:05:26.510994 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1493 11:05:26.513922 fsp= 1, odt_onoff= 1, Byte mode= 0
1494 11:05:26.514007 ==
1495 11:05:26.517230 DQS Delay:
1496 11:05:26.517308 DQS0 = 0, DQS1 = 0
1497 11:05:26.517372 DQM Delay:
1498 11:05:26.520501 DQM0 = 19, DQM1 = 17
1499 11:05:26.520576 DQ Delay:
1500 11:05:26.523940 DQ0 =22, DQ1 =22, DQ2 =23, DQ3 =14
1501 11:05:26.527107 DQ4 =22, DQ5 =17, DQ6 =18, DQ7 =20
1502 11:05:26.530184 DQ8 =13, DQ9 =17, DQ10 =23, DQ11 =15
1503 11:05:26.533763 DQ12 =17, DQ13 =16, DQ14 =18, DQ15 =20
1504 11:05:26.533838
1505 11:05:26.533900
1506 11:05:26.533957
1507 11:05:26.536944 [DramC_TX_OE_Calibration] TA2
1508 11:05:26.540277 Original DQ_B0 (3 6) =30, OEN = 27
1509 11:05:26.543540 Original DQ_B1 (3 6) =30, OEN = 27
1510 11:05:26.546629 23, 0x0, End_B0=23 End_B1=23
1511 11:05:26.550446 24, 0x0, End_B0=24 End_B1=24
1512 11:05:26.550539 25, 0x0, End_B0=25 End_B1=25
1513 11:05:26.553260 26, 0x0, End_B0=26 End_B1=26
1514 11:05:26.556631 27, 0x0, End_B0=27 End_B1=27
1515 11:05:26.559965 28, 0x0, End_B0=28 End_B1=28
1516 11:05:26.562971 29, 0x0, End_B0=29 End_B1=29
1517 11:05:26.563081 30, 0x0, End_B0=30 End_B1=30
1518 11:05:26.566224 31, 0xFFFF, End_B0=30 End_B1=30
1519 11:05:26.572908 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1520 11:05:26.579796 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1521 11:05:26.579959
1522 11:05:26.580092
1523 11:05:26.580263 Write Rank0 MR23 =0x3f
1524 11:05:26.583101 [DQSOSC]
1525 11:05:26.589201 [DQSOSCAuto] RK0, (LSB)MR18= 0xc2c2, (MSB)MR19= 0x202, tDQSOscB0 = 446 ps tDQSOscB1 = 446 ps
1526 11:05:26.596308 CH0_RK0: MR19=0x202, MR18=0xC2C2, DQSOSC=446, MR23=63, INC=12, DEC=18
1527 11:05:26.599279 Write Rank0 MR23 =0x3f
1528 11:05:26.599717 [DQSOSC]
1529 11:05:26.605819 [DQSOSCAuto] RK0, (LSB)MR18= 0xc2c2, (MSB)MR19= 0x202, tDQSOscB0 = 446 ps tDQSOscB1 = 446 ps
1530 11:05:26.609269 CH0 RK0: MR19=202, MR18=C2C2
1531 11:05:26.613133 [RankSwap] Rank num 2, (Multi 1), Rank 1
1532 11:05:26.615687 Write Rank0 MR2 =0xad
1533 11:05:26.616078 [Write Leveling]
1534 11:05:26.619313 delay byte0 byte1 byte2 byte3
1535 11:05:26.619751
1536 11:05:26.622308 10 0 0
1537 11:05:26.622786 11 0 0
1538 11:05:26.625883 12 0 0
1539 11:05:26.626222 13 0 0
1540 11:05:26.626510 14 0 0
1541 11:05:26.628981 15 0 0
1542 11:05:26.629369 16 0 0
1543 11:05:26.632116 17 0 0
1544 11:05:26.632505 18 0 0
1545 11:05:26.632809 19 0 0
1546 11:05:26.635343 20 0 0
1547 11:05:26.635765 21 0 0
1548 11:05:26.638651 22 0 0
1549 11:05:26.639095 23 0 0
1550 11:05:26.642074 24 0 0
1551 11:05:26.642594 25 0 ff
1552 11:05:26.643083 26 0 ff
1553 11:05:26.645051 27 0 ff
1554 11:05:26.645494 28 0 ff
1555 11:05:26.648555 29 0 ff
1556 11:05:26.648946 30 ff ff
1557 11:05:26.651875 31 ff ff
1558 11:05:26.652292 32 ff ff
1559 11:05:26.655188 33 ff ff
1560 11:05:26.655608 34 ff ff
1561 11:05:26.658459 35 ff ff
1562 11:05:26.658846 36 ff ff
1563 11:05:26.661958 pass bytecount = 0xff (0xff: all bytes pass)
1564 11:05:26.662343
1565 11:05:26.664940 DQS0 dly: 30
1566 11:05:26.665330 DQS1 dly: 25
1567 11:05:26.668258 Write Rank0 MR2 =0x2d
1568 11:05:26.671307 [RankSwap] Rank num 2, (Multi 1), Rank 0
1569 11:05:26.671901 Write Rank1 MR1 =0xd6
1570 11:05:26.674516 [Gating]
1571 11:05:26.674946 ==
1572 11:05:26.677805 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1573 11:05:26.681216 fsp= 1, odt_onoff= 1, Byte mode= 0
1574 11:05:26.681592 ==
1575 11:05:26.687908 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1576 11:05:26.691147 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1577 11:05:26.694401 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1578 11:05:26.701079 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1579 11:05:26.704199 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1580 11:05:26.707393 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1581 11:05:26.713765 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1582 11:05:26.717387 [Byte 0] Lead/lag falling Transition (3, 1, 24)
1583 11:05:26.720302 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1584 11:05:26.727242 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1585 11:05:26.730474 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1586 11:05:26.733823 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1587 11:05:26.740380 3 2 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1588 11:05:26.743422 3 2 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1589 11:05:26.746599 [Byte 0] Lead/lag Transition tap number (7)
1590 11:05:26.749911 3 2 20 |302 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1591 11:05:26.756657 3 2 24 |807 2c2c |(11 11)(11 10) |(0 0)(0 0)| 0
1592 11:05:26.759790 3 2 28 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
1593 11:05:26.763051 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1594 11:05:26.769689 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1595 11:05:26.772792 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1596 11:05:26.775979 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1597 11:05:26.782541 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1598 11:05:26.786092 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1599 11:05:26.789279 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1600 11:05:26.795961 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1601 11:05:26.799261 [Byte 1] Lead/lag falling Transition (3, 3, 28)
1602 11:05:26.802418 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1603 11:05:26.808824 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1604 11:05:26.812109 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1605 11:05:26.815349 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1606 11:05:26.821934 3 4 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1607 11:05:26.825061 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1608 11:05:26.828436 3 4 24 |3d3d 1d1c |(11 11)(11 11) |(1 1)(1 1)| 0
1609 11:05:26.835096 3 4 28 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1610 11:05:26.838409 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1611 11:05:26.841716 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1612 11:05:26.848197 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1613 11:05:26.851437 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1614 11:05:26.854861 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1615 11:05:26.861582 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1616 11:05:26.864478 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1617 11:05:26.867962 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1618 11:05:26.874432 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1619 11:05:26.877859 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1620 11:05:26.881084 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1621 11:05:26.887549 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1622 11:05:26.890845 [Byte 0] Lead/lag falling Transition (3, 6, 12)
1623 11:05:26.894305 [Byte 1] Lead/lag falling Transition (3, 6, 12)
1624 11:05:26.900615 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1625 11:05:26.904530 [Byte 0] Lead/lag Transition tap number (2)
1626 11:05:26.907185 3 6 20 |3c3b 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1627 11:05:26.910468 [Byte 1] Lead/lag Transition tap number (3)
1628 11:05:26.917092 3 6 24 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
1629 11:05:26.917507 [Byte 0]First pass (3, 6, 24)
1630 11:05:26.923567 3 6 28 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
1631 11:05:26.926772 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1632 11:05:26.929912 [Byte 1]First pass (3, 7, 0)
1633 11:05:26.933589 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1634 11:05:26.936988 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1635 11:05:26.940095 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1636 11:05:26.943327 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1637 11:05:26.949807 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1638 11:05:26.953460 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1639 11:05:26.956332 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1640 11:05:26.959513 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1641 11:05:26.966304 All bytes gating window > 1UI, Early break!
1642 11:05:26.966691
1643 11:05:26.969505 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 16)
1644 11:05:26.969915
1645 11:05:26.972798 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 18)
1646 11:05:26.973187
1647 11:05:26.973490
1648 11:05:26.973767
1649 11:05:26.976092 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
1650 11:05:26.976483
1651 11:05:26.979517 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 18)
1652 11:05:26.982392
1653 11:05:26.982746
1654 11:05:26.983049 Write Rank1 MR1 =0x56
1655 11:05:26.983345
1656 11:05:26.985902 best RODT dly(2T, 0.5T) = (2, 3)
1657 11:05:26.986309
1658 11:05:26.988854 best RODT dly(2T, 0.5T) = (2, 3)
1659 11:05:26.989246 ==
1660 11:05:26.995539 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1661 11:05:26.998758 fsp= 1, odt_onoff= 1, Byte mode= 0
1662 11:05:26.999116 ==
1663 11:05:27.002036 Start DQ dly to find pass range UseTestEngine =0
1664 11:05:27.005220 x-axis: bit #, y-axis: DQ dly (-127~63)
1665 11:05:27.008471 RX Vref Scan = 0
1666 11:05:27.011571 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1667 11:05:27.011665 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1668 11:05:27.015169 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1669 11:05:27.018315 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1670 11:05:27.021512 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1671 11:05:27.024884 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1672 11:05:27.027838 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1673 11:05:27.031378 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1674 11:05:27.034493 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1675 11:05:27.037626 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1676 11:05:27.037712 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1677 11:05:27.041118 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1678 11:05:27.044604 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1679 11:05:27.047560 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1680 11:05:27.051016 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1681 11:05:27.054294 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1682 11:05:27.057373 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1683 11:05:27.060653 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1684 11:05:27.064141 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1685 11:05:27.064234 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1686 11:05:27.067332 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1687 11:05:27.070532 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1688 11:05:27.074011 -4, [0] xxxoxxxx oxxxxxxx [MSB]
1689 11:05:27.077207 -3, [0] xxxoxxxx ooxoxxxx [MSB]
1690 11:05:27.080388 -2, [0] xxxoxxxx ooxoooxx [MSB]
1691 11:05:27.083622 -1, [0] xxxoxoxx ooxoooxx [MSB]
1692 11:05:27.083760 0, [0] xxxoxoox ooxoooox [MSB]
1693 11:05:27.087061 1, [0] xxxoxoox ooxoooox [MSB]
1694 11:05:27.090331 2, [0] xxxoxoox ooxoooox [MSB]
1695 11:05:27.093290 3, [0] xxxooooo ooxooooo [MSB]
1696 11:05:27.096787 4, [0] oxxooooo ooxooooo [MSB]
1697 11:05:27.100094 32, [0] oooxoooo oooooooo [MSB]
1698 11:05:27.103122 33, [0] oooxoooo oooooooo [MSB]
1699 11:05:27.106412 34, [0] oooxoooo xooxoooo [MSB]
1700 11:05:27.106498 35, [0] oooxoooo xxoxoooo [MSB]
1701 11:05:27.109761 36, [0] oooxoxoo xxoxxoxo [MSB]
1702 11:05:27.113142 37, [0] oooxoxxx xxoxxxxo [MSB]
1703 11:05:27.116370 38, [0] oooxoxxx xxoxxxxo [MSB]
1704 11:05:27.119746 39, [0] oooxoxxx xxoxxxxx [MSB]
1705 11:05:27.122813 40, [0] xoxxxxxx xxoxxxxx [MSB]
1706 11:05:27.126194 41, [0] xxxxxxxx xxoxxxxx [MSB]
1707 11:05:27.126278 42, [0] xxxxxxxx xxoxxxxx [MSB]
1708 11:05:27.129661 43, [0] xxxxxxxx xxxxxxxx [MSB]
1709 11:05:27.132784 iDelay=43, Bit 0, Center 21 (4 ~ 39) 36
1710 11:05:27.136035 iDelay=43, Bit 1, Center 22 (5 ~ 40) 36
1711 11:05:27.142643 iDelay=43, Bit 2, Center 22 (5 ~ 39) 35
1712 11:05:27.146188 iDelay=43, Bit 3, Center 13 (-4 ~ 31) 36
1713 11:05:27.149025 iDelay=43, Bit 4, Center 21 (3 ~ 39) 37
1714 11:05:27.152598 iDelay=43, Bit 5, Center 17 (-1 ~ 35) 37
1715 11:05:27.155655 iDelay=43, Bit 6, Center 18 (0 ~ 36) 37
1716 11:05:27.158870 iDelay=43, Bit 7, Center 19 (3 ~ 36) 34
1717 11:05:27.162370 iDelay=43, Bit 8, Center 14 (-4 ~ 33) 38
1718 11:05:27.165488 iDelay=43, Bit 9, Center 15 (-3 ~ 34) 38
1719 11:05:27.168906 iDelay=43, Bit 10, Center 23 (5 ~ 42) 38
1720 11:05:27.172198 iDelay=43, Bit 11, Center 15 (-3 ~ 33) 37
1721 11:05:27.178607 iDelay=43, Bit 12, Center 16 (-2 ~ 35) 38
1722 11:05:27.181948 iDelay=43, Bit 13, Center 17 (-2 ~ 36) 39
1723 11:05:27.185315 iDelay=43, Bit 14, Center 17 (0 ~ 35) 36
1724 11:05:27.188343 iDelay=43, Bit 15, Center 20 (3 ~ 38) 36
1725 11:05:27.188428 ==
1726 11:05:27.194998 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1727 11:05:27.195090 fsp= 1, odt_onoff= 1, Byte mode= 0
1728 11:05:27.198427 ==
1729 11:05:27.198527 DQS Delay:
1730 11:05:27.198603 DQS0 = 0, DQS1 = 0
1731 11:05:27.201425 DQM Delay:
1732 11:05:27.201523 DQM0 = 19, DQM1 = 17
1733 11:05:27.204586 DQ Delay:
1734 11:05:27.208053 DQ0 =21, DQ1 =22, DQ2 =22, DQ3 =13
1735 11:05:27.211446 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =19
1736 11:05:27.214668 DQ8 =14, DQ9 =15, DQ10 =23, DQ11 =15
1737 11:05:27.217986 DQ12 =16, DQ13 =17, DQ14 =17, DQ15 =20
1738 11:05:27.218085
1739 11:05:27.218161
1740 11:05:27.218230 DramC Write-DBI off
1741 11:05:27.218298 ==
1742 11:05:27.224428 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1743 11:05:27.227721 fsp= 1, odt_onoff= 1, Byte mode= 0
1744 11:05:27.227840 ==
1745 11:05:27.230889 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1746 11:05:27.231013
1747 11:05:27.234176 Begin, DQ Scan Range 921~1177
1748 11:05:27.234359
1749 11:05:27.234470
1750 11:05:27.237391 TX Vref Scan disable
1751 11:05:27.240835 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1752 11:05:27.244145 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1753 11:05:27.247469 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1754 11:05:27.250603 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1755 11:05:27.254179 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1756 11:05:27.257218 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1757 11:05:27.260668 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1758 11:05:27.263958 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1759 11:05:27.267155 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1760 11:05:27.273448 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1761 11:05:27.276818 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1762 11:05:27.280148 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1763 11:05:27.283170 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1764 11:05:27.286753 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1765 11:05:27.289945 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1766 11:05:27.293497 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1767 11:05:27.296347 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1768 11:05:27.299992 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1769 11:05:27.302719 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1770 11:05:27.306369 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1771 11:05:27.309557 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1772 11:05:27.312910 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1773 11:05:27.319795 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1774 11:05:27.323046 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1775 11:05:27.326002 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1776 11:05:27.329300 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1777 11:05:27.332782 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1778 11:05:27.336200 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1779 11:05:27.339263 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1780 11:05:27.342747 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1781 11:05:27.345959 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1782 11:05:27.349099 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1783 11:05:27.352291 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1784 11:05:27.355810 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1785 11:05:27.362131 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1786 11:05:27.365582 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1787 11:05:27.368560 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1788 11:05:27.371875 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1789 11:05:27.375432 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1790 11:05:27.378854 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1791 11:05:27.381823 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1792 11:05:27.385341 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1793 11:05:27.388268 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1794 11:05:27.391882 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1795 11:05:27.395320 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1796 11:05:27.398165 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1797 11:05:27.401495 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1798 11:05:27.404859 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1799 11:05:27.408172 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1800 11:05:27.411327 970 |3 6 10|[0] xxxxxxxx oxxxxxxx [MSB]
1801 11:05:27.417794 971 |3 6 11|[0] xxxxxxxx oxxxxxxx [MSB]
1802 11:05:27.420987 972 |3 6 12|[0] xxxxxxxx oxxoxxxx [MSB]
1803 11:05:27.424630 973 |3 6 13|[0] xxxxxxxx ooxoxoox [MSB]
1804 11:05:27.427987 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1805 11:05:27.431136 975 |3 6 15|[0] xxxxxxxx ooxoooox [MSB]
1806 11:05:27.434373 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1807 11:05:27.437660 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1808 11:05:27.440790 978 |3 6 18|[0] xoxooooo oooooooo [MSB]
1809 11:05:27.444156 979 |3 6 19|[0] ooxooooo oooooooo [MSB]
1810 11:05:27.451143 990 |3 6 30|[0] oooooooo oooxoooo [MSB]
1811 11:05:27.454405 991 |3 6 31|[0] oooooooo xooxoooo [MSB]
1812 11:05:27.457616 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1813 11:05:27.460944 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1814 11:05:27.464189 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1815 11:05:27.467268 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1816 11:05:27.470552 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1817 11:05:27.473833 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1818 11:05:27.477447 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB]
1819 11:05:27.480509 999 |3 6 39|[0] oooxoxxo xxxxxxxx [MSB]
1820 11:05:27.483810 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
1821 11:05:27.487220 Byte0, DQ PI dly=987, DQM PI dly= 987
1822 11:05:27.493492 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
1823 11:05:27.493883
1824 11:05:27.496812 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
1825 11:05:27.497353
1826 11:05:27.499800 Byte1, DQ PI dly=981, DQM PI dly= 981
1827 11:05:27.506817 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1828 11:05:27.507229
1829 11:05:27.509714 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1830 11:05:27.510110
1831 11:05:27.510412 ==
1832 11:05:27.516356 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1833 11:05:27.519556 fsp= 1, odt_onoff= 1, Byte mode= 0
1834 11:05:27.519949 ==
1835 11:05:27.523177 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1836 11:05:27.523607
1837 11:05:27.526043 Begin, DQ Scan Range 957~1021
1838 11:05:27.526432 Write Rank1 MR14 =0x0
1839 11:05:27.535306
1840 11:05:27.535777 CH=0, VrefRange= 0, VrefLevel = 0
1841 11:05:27.541739 TX Bit0 (983~994) 12 988, Bit8 (973~985) 13 979,
1842 11:05:27.544949 TX Bit1 (980~994) 15 987, Bit9 (976~986) 11 981,
1843 11:05:27.551635 TX Bit2 (983~993) 11 988, Bit10 (979~991) 13 985,
1844 11:05:27.554658 TX Bit3 (976~990) 15 983, Bit11 (975~983) 9 979,
1845 11:05:27.557979 TX Bit4 (981~994) 14 987, Bit12 (976~985) 10 980,
1846 11:05:27.564394 TX Bit5 (979~990) 12 984, Bit13 (975~988) 14 981,
1847 11:05:27.567561 TX Bit6 (979~992) 14 985, Bit14 (975~990) 16 982,
1848 11:05:27.574260 TX Bit7 (981~994) 14 987, Bit15 (978~991) 14 984,
1849 11:05:27.574362
1850 11:05:27.574462 Write Rank1 MR14 =0x2
1851 11:05:27.583090
1852 11:05:27.583219 CH=0, VrefRange= 0, VrefLevel = 2
1853 11:05:27.589430 TX Bit0 (982~995) 14 988, Bit8 (973~986) 14 979,
1854 11:05:27.592746 TX Bit1 (980~996) 17 988, Bit9 (975~986) 12 980,
1855 11:05:27.599363 TX Bit2 (983~994) 12 988, Bit10 (978~991) 14 984,
1856 11:05:27.602695 TX Bit3 (976~990) 15 983, Bit11 (974~984) 11 979,
1857 11:05:27.606004 TX Bit4 (980~995) 16 987, Bit12 (976~986) 11 981,
1858 11:05:27.612563 TX Bit5 (978~991) 14 984, Bit13 (975~988) 14 981,
1859 11:05:27.616182 TX Bit6 (978~993) 16 985, Bit14 (975~991) 17 983,
1860 11:05:27.622367 TX Bit7 (980~995) 16 987, Bit15 (977~992) 16 984,
1861 11:05:27.622760
1862 11:05:27.623066 Write Rank1 MR14 =0x4
1863 11:05:27.631404
1864 11:05:27.632001 CH=0, VrefRange= 0, VrefLevel = 4
1865 11:05:27.638052 TX Bit0 (982~996) 15 989, Bit8 (973~986) 14 979,
1866 11:05:27.641295 TX Bit1 (980~997) 18 988, Bit9 (975~987) 13 981,
1867 11:05:27.647685 TX Bit2 (982~995) 14 988, Bit10 (978~993) 16 985,
1868 11:05:27.651268 TX Bit3 (976~991) 16 983, Bit11 (974~985) 12 979,
1869 11:05:27.654579 TX Bit4 (979~996) 18 987, Bit12 (976~987) 12 981,
1870 11:05:27.661340 TX Bit5 (978~992) 15 985, Bit13 (975~989) 15 982,
1871 11:05:27.664165 TX Bit6 (978~994) 17 986, Bit14 (975~991) 17 983,
1872 11:05:27.670577 TX Bit7 (980~996) 17 988, Bit15 (977~994) 18 985,
1873 11:05:27.671053
1874 11:05:27.671368 Write Rank1 MR14 =0x6
1875 11:05:27.679962
1876 11:05:27.680357 CH=0, VrefRange= 0, VrefLevel = 6
1877 11:05:27.686412 TX Bit0 (982~997) 16 989, Bit8 (972~988) 17 980,
1878 11:05:27.689775 TX Bit1 (980~998) 19 989, Bit9 (974~988) 15 981,
1879 11:05:27.696203 TX Bit2 (982~996) 15 989, Bit10 (978~993) 16 985,
1880 11:05:27.699603 TX Bit3 (976~991) 16 983, Bit11 (974~986) 13 980,
1881 11:05:27.702723 TX Bit4 (980~997) 18 988, Bit12 (975~988) 14 981,
1882 11:05:27.709320 TX Bit5 (978~992) 15 985, Bit13 (975~989) 15 982,
1883 11:05:27.712680 TX Bit6 (978~995) 18 986, Bit14 (975~992) 18 983,
1884 11:05:27.719348 TX Bit7 (980~997) 18 988, Bit15 (977~993) 17 985,
1885 11:05:27.719982
1886 11:05:27.720488 Write Rank1 MR14 =0x8
1887 11:05:27.728430
1888 11:05:27.728956 CH=0, VrefRange= 0, VrefLevel = 8
1889 11:05:27.735321 TX Bit0 (981~998) 18 989, Bit8 (971~988) 18 979,
1890 11:05:27.738175 TX Bit1 (979~998) 20 988, Bit9 (974~989) 16 981,
1891 11:05:27.744648 TX Bit2 (981~997) 17 989, Bit10 (977~994) 18 985,
1892 11:05:27.748186 TX Bit3 (975~992) 18 983, Bit11 (973~986) 14 979,
1893 11:05:27.751546 TX Bit4 (979~998) 20 988, Bit12 (975~989) 15 982,
1894 11:05:27.757857 TX Bit5 (978~993) 16 985, Bit13 (974~989) 16 981,
1895 11:05:27.760963 TX Bit6 (978~995) 18 986, Bit14 (974~993) 20 983,
1896 11:05:27.767957 TX Bit7 (979~998) 20 988, Bit15 (977~995) 19 986,
1897 11:05:27.768346
1898 11:05:27.768646 Write Rank1 MR14 =0xa
1899 11:05:27.776843
1900 11:05:27.780076 CH=0, VrefRange= 0, VrefLevel = 10
1901 11:05:27.783437 TX Bit0 (981~999) 19 990, Bit8 (971~989) 19 980,
1902 11:05:27.786817 TX Bit1 (979~999) 21 989, Bit9 (974~989) 16 981,
1903 11:05:27.793347 TX Bit2 (980~998) 19 989, Bit10 (977~995) 19 986,
1904 11:05:27.796491 TX Bit3 (975~992) 18 983, Bit11 (973~988) 16 980,
1905 11:05:27.799945 TX Bit4 (979~998) 20 988, Bit12 (974~989) 16 981,
1906 11:05:27.806535 TX Bit5 (978~993) 16 985, Bit13 (974~990) 17 982,
1907 11:05:27.809651 TX Bit6 (978~996) 19 987, Bit14 (974~993) 20 983,
1908 11:05:27.816397 TX Bit7 (979~998) 20 988, Bit15 (976~995) 20 985,
1909 11:05:27.816804
1910 11:05:27.817112 Write Rank1 MR14 =0xc
1911 11:05:27.825598
1912 11:05:27.828920 CH=0, VrefRange= 0, VrefLevel = 12
1913 11:05:27.832242 TX Bit0 (981~999) 19 990, Bit8 (970~989) 20 979,
1914 11:05:27.835510 TX Bit1 (979~999) 21 989, Bit9 (973~990) 18 981,
1915 11:05:27.842027 TX Bit2 (981~998) 18 989, Bit10 (976~996) 21 986,
1916 11:05:27.845200 TX Bit3 (974~992) 19 983, Bit11 (973~988) 16 980,
1917 11:05:27.848346 TX Bit4 (979~999) 21 989, Bit12 (974~990) 17 982,
1918 11:05:27.854949 TX Bit5 (977~994) 18 985, Bit13 (974~990) 17 982,
1919 11:05:27.858370 TX Bit6 (977~997) 21 987, Bit14 (974~994) 21 984,
1920 11:05:27.864844 TX Bit7 (979~999) 21 989, Bit15 (976~996) 21 986,
1921 11:05:27.865294
1922 11:05:27.865692 Write Rank1 MR14 =0xe
1923 11:05:27.874458
1924 11:05:27.877744 CH=0, VrefRange= 0, VrefLevel = 14
1925 11:05:27.880988 TX Bit0 (980~999) 20 989, Bit8 (970~989) 20 979,
1926 11:05:27.884273 TX Bit1 (978~999) 22 988, Bit9 (974~990) 17 982,
1927 11:05:27.890485 TX Bit2 (980~999) 20 989, Bit10 (976~997) 22 986,
1928 11:05:27.894125 TX Bit3 (974~993) 20 983, Bit11 (972~989) 18 980,
1929 11:05:27.897419 TX Bit4 (978~999) 22 988, Bit12 (974~990) 17 982,
1930 11:05:27.904115 TX Bit5 (977~995) 19 986, Bit13 (974~991) 18 982,
1931 11:05:27.907255 TX Bit6 (977~998) 22 987, Bit14 (974~995) 22 984,
1932 11:05:27.913409 TX Bit7 (979~999) 21 989, Bit15 (976~997) 22 986,
1933 11:05:27.913976
1934 11:05:27.914378 Write Rank1 MR14 =0x10
1935 11:05:27.923388
1936 11:05:27.926614 CH=0, VrefRange= 0, VrefLevel = 16
1937 11:05:27.930149 TX Bit0 (979~1000) 22 989, Bit8 (970~990) 21 980,
1938 11:05:27.933066 TX Bit1 (979~1000) 22 989, Bit9 (973~991) 19 982,
1939 11:05:27.939870 TX Bit2 (979~999) 21 989, Bit10 (976~997) 22 986,
1940 11:05:27.943131 TX Bit3 (974~993) 20 983, Bit11 (972~989) 18 980,
1941 11:05:27.946295 TX Bit4 (978~999) 22 988, Bit12 (974~991) 18 982,
1942 11:05:27.952740 TX Bit5 (977~995) 19 986, Bit13 (973~992) 20 982,
1943 11:05:27.956254 TX Bit6 (977~998) 22 987, Bit14 (973~995) 23 984,
1944 11:05:27.963118 TX Bit7 (978~999) 22 988, Bit15 (976~997) 22 986,
1945 11:05:27.963521
1946 11:05:27.963812 Write Rank1 MR14 =0x12
1947 11:05:27.972224
1948 11:05:27.975629 CH=0, VrefRange= 0, VrefLevel = 18
1949 11:05:27.979124 TX Bit0 (979~1000) 22 989, Bit8 (969~990) 22 979,
1950 11:05:27.982434 TX Bit1 (978~1000) 23 989, Bit9 (973~991) 19 982,
1951 11:05:27.988869 TX Bit2 (980~1000) 21 990, Bit10 (976~997) 22 986,
1952 11:05:27.992088 TX Bit3 (974~994) 21 984, Bit11 (971~990) 20 980,
1953 11:05:27.999164 TX Bit4 (978~999) 22 988, Bit12 (973~991) 19 982,
1954 11:05:28.001895 TX Bit5 (977~997) 21 987, Bit13 (973~992) 20 982,
1955 11:05:28.005259 TX Bit6 (977~999) 23 988, Bit14 (973~996) 24 984,
1956 11:05:28.011696 TX Bit7 (978~1000) 23 989, Bit15 (976~997) 22 986,
1957 11:05:28.012050
1958 11:05:28.012322 Write Rank1 MR14 =0x14
1959 11:05:28.022141
1960 11:05:28.025363 CH=0, VrefRange= 0, VrefLevel = 20
1961 11:05:28.028341 TX Bit0 (979~1001) 23 990, Bit8 (969~991) 23 980,
1962 11:05:28.032013 TX Bit1 (978~1000) 23 989, Bit9 (972~992) 21 982,
1963 11:05:28.038546 TX Bit2 (979~1000) 22 989, Bit10 (976~997) 22 986,
1964 11:05:28.041704 TX Bit3 (973~994) 22 983, Bit11 (971~990) 20 980,
1965 11:05:28.048012 TX Bit4 (978~1000) 23 989, Bit12 (973~992) 20 982,
1966 11:05:28.051144 TX Bit5 (977~998) 22 987, Bit13 (972~993) 22 982,
1967 11:05:28.054489 TX Bit6 (977~999) 23 988, Bit14 (972~996) 25 984,
1968 11:05:28.061166 TX Bit7 (978~1000) 23 989, Bit15 (976~997) 22 986,
1969 11:05:28.061582
1970 11:05:28.061884 Write Rank1 MR14 =0x16
1971 11:05:28.071692
1972 11:05:28.074609 CH=0, VrefRange= 0, VrefLevel = 22
1973 11:05:28.077976 TX Bit0 (979~1001) 23 990, Bit8 (969~991) 23 980,
1974 11:05:28.081184 TX Bit1 (978~1001) 24 989, Bit9 (972~992) 21 982,
1975 11:05:28.087964 TX Bit2 (979~1000) 22 989, Bit10 (976~998) 23 987,
1976 11:05:28.090855 TX Bit3 (973~995) 23 984, Bit11 (970~991) 22 980,
1977 11:05:28.097376 TX Bit4 (978~1000) 23 989, Bit12 (972~992) 21 982,
1978 11:05:28.100801 TX Bit5 (976~998) 23 987, Bit13 (972~994) 23 983,
1979 11:05:28.103985 TX Bit6 (977~1000) 24 988, Bit14 (972~996) 25 984,
1980 11:05:28.110840 TX Bit7 (978~1001) 24 989, Bit15 (975~998) 24 986,
1981 11:05:28.111233
1982 11:05:28.111567 Write Rank1 MR14 =0x18
1983 11:05:28.120969
1984 11:05:28.124282 CH=0, VrefRange= 0, VrefLevel = 24
1985 11:05:28.127518 TX Bit0 (978~1001) 24 989, Bit8 (969~992) 24 980,
1986 11:05:28.130642 TX Bit1 (978~1001) 24 989, Bit9 (972~993) 22 982,
1987 11:05:28.137539 TX Bit2 (978~1001) 24 989, Bit10 (975~998) 24 986,
1988 11:05:28.140701 TX Bit3 (972~995) 24 983, Bit11 (970~991) 22 980,
1989 11:05:28.147044 TX Bit4 (977~1000) 24 988, Bit12 (972~993) 22 982,
1990 11:05:28.150431 TX Bit5 (976~998) 23 987, Bit13 (972~994) 23 983,
1991 11:05:28.153924 TX Bit6 (977~1000) 24 988, Bit14 (972~997) 26 984,
1992 11:05:28.160346 TX Bit7 (978~1001) 24 989, Bit15 (975~998) 24 986,
1993 11:05:28.160854
1994 11:05:28.161164 Write Rank1 MR14 =0x1a
1995 11:05:28.170636
1996 11:05:28.174232 CH=0, VrefRange= 0, VrefLevel = 26
1997 11:05:28.177215 TX Bit0 (978~1002) 25 990, Bit8 (968~992) 25 980,
1998 11:05:28.180792 TX Bit1 (978~1002) 25 990, Bit9 (971~994) 24 982,
1999 11:05:28.187218 TX Bit2 (979~1001) 23 990, Bit10 (976~999) 24 987,
2000 11:05:28.190539 TX Bit3 (972~996) 25 984, Bit11 (970~991) 22 980,
2001 11:05:28.197162 TX Bit4 (977~1001) 25 989, Bit12 (972~994) 23 983,
2002 11:05:28.200508 TX Bit5 (976~999) 24 987, Bit13 (971~995) 25 983,
2003 11:05:28.203438 TX Bit6 (976~1000) 25 988, Bit14 (972~997) 26 984,
2004 11:05:28.209809 TX Bit7 (978~1001) 24 989, Bit15 (975~998) 24 986,
2005 11:05:28.210195
2006 11:05:28.210492 Write Rank1 MR14 =0x1c
2007 11:05:28.220505
2008 11:05:28.223765 CH=0, VrefRange= 0, VrefLevel = 28
2009 11:05:28.227115 TX Bit0 (978~1002) 25 990, Bit8 (968~992) 25 980,
2010 11:05:28.230062 TX Bit1 (978~1002) 25 990, Bit9 (971~993) 23 982,
2011 11:05:28.236897 TX Bit2 (978~1002) 25 990, Bit10 (975~999) 25 987,
2012 11:05:28.240211 TX Bit3 (971~997) 27 984, Bit11 (969~992) 24 980,
2013 11:05:28.246980 TX Bit4 (977~1001) 25 989, Bit12 (971~994) 24 982,
2014 11:05:28.250109 TX Bit5 (975~999) 25 987, Bit13 (970~995) 26 982,
2015 11:05:28.253262 TX Bit6 (976~1000) 25 988, Bit14 (972~997) 26 984,
2016 11:05:28.259644 TX Bit7 (978~1002) 25 990, Bit15 (975~998) 24 986,
2017 11:05:28.260041
2018 11:05:28.260341 Write Rank1 MR14 =0x1e
2019 11:05:28.270498
2020 11:05:28.273647 CH=0, VrefRange= 0, VrefLevel = 30
2021 11:05:28.277004 TX Bit0 (978~1003) 26 990, Bit8 (968~991) 24 979,
2022 11:05:28.280361 TX Bit1 (978~1002) 25 990, Bit9 (970~994) 25 982,
2023 11:05:28.286967 TX Bit2 (978~1002) 25 990, Bit10 (975~999) 25 987,
2024 11:05:28.290003 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
2025 11:05:28.296515 TX Bit4 (978~1002) 25 990, Bit12 (971~995) 25 983,
2026 11:05:28.300069 TX Bit5 (975~999) 25 987, Bit13 (970~994) 25 982,
2027 11:05:28.303033 TX Bit6 (976~1000) 25 988, Bit14 (972~997) 26 984,
2028 11:05:28.309749 TX Bit7 (978~1003) 26 990, Bit15 (975~998) 24 986,
2029 11:05:28.310280
2030 11:05:28.310715 Write Rank1 MR14 =0x20
2031 11:05:28.320468
2032 11:05:28.323578 CH=0, VrefRange= 0, VrefLevel = 32
2033 11:05:28.327026 TX Bit0 (978~1003) 26 990, Bit8 (968~991) 24 979,
2034 11:05:28.330475 TX Bit1 (978~1002) 25 990, Bit9 (970~994) 25 982,
2035 11:05:28.337024 TX Bit2 (978~1002) 25 990, Bit10 (975~999) 25 987,
2036 11:05:28.340101 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
2037 11:05:28.346818 TX Bit4 (978~1002) 25 990, Bit12 (971~995) 25 983,
2038 11:05:28.350051 TX Bit5 (975~999) 25 987, Bit13 (970~994) 25 982,
2039 11:05:28.353279 TX Bit6 (976~1000) 25 988, Bit14 (972~997) 26 984,
2040 11:05:28.359730 TX Bit7 (978~1003) 26 990, Bit15 (975~998) 24 986,
2041 11:05:28.360100
2042 11:05:28.360480 Write Rank1 MR14 =0x22
2043 11:05:28.370622
2044 11:05:28.373725 CH=0, VrefRange= 0, VrefLevel = 34
2045 11:05:28.376761 TX Bit0 (978~1003) 26 990, Bit8 (968~991) 24 979,
2046 11:05:28.380236 TX Bit1 (978~1002) 25 990, Bit9 (970~994) 25 982,
2047 11:05:28.386896 TX Bit2 (978~1002) 25 990, Bit10 (975~999) 25 987,
2048 11:05:28.390292 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
2049 11:05:28.396614 TX Bit4 (978~1002) 25 990, Bit12 (971~995) 25 983,
2050 11:05:28.399950 TX Bit5 (975~999) 25 987, Bit13 (970~994) 25 982,
2051 11:05:28.403016 TX Bit6 (976~1000) 25 988, Bit14 (972~997) 26 984,
2052 11:05:28.409601 TX Bit7 (978~1003) 26 990, Bit15 (975~998) 24 986,
2053 11:05:28.409988
2054 11:05:28.410287 Write Rank1 MR14 =0x24
2055 11:05:28.420464
2056 11:05:28.424109 CH=0, VrefRange= 0, VrefLevel = 36
2057 11:05:28.427326 TX Bit0 (978~1003) 26 990, Bit8 (968~991) 24 979,
2058 11:05:28.430245 TX Bit1 (978~1002) 25 990, Bit9 (970~994) 25 982,
2059 11:05:28.436709 TX Bit2 (978~1002) 25 990, Bit10 (975~999) 25 987,
2060 11:05:28.440020 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
2061 11:05:28.446304 TX Bit4 (978~1002) 25 990, Bit12 (971~995) 25 983,
2062 11:05:28.449613 TX Bit5 (975~999) 25 987, Bit13 (970~994) 25 982,
2063 11:05:28.452968 TX Bit6 (976~1000) 25 988, Bit14 (972~997) 26 984,
2064 11:05:28.459763 TX Bit7 (978~1003) 26 990, Bit15 (975~998) 24 986,
2065 11:05:28.460216
2066 11:05:28.460519
2067 11:05:28.463020 TX Vref found, early break! 376< 380
2068 11:05:28.466074 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2069 11:05:28.469534 u1DelayCellOfst[0]=7 cells (6 PI)
2070 11:05:28.472776 u1DelayCellOfst[1]=7 cells (6 PI)
2071 11:05:28.476056 u1DelayCellOfst[2]=7 cells (6 PI)
2072 11:05:28.479155 u1DelayCellOfst[3]=0 cells (0 PI)
2073 11:05:28.482680 u1DelayCellOfst[4]=7 cells (6 PI)
2074 11:05:28.486109 u1DelayCellOfst[5]=3 cells (3 PI)
2075 11:05:28.488905 u1DelayCellOfst[6]=5 cells (4 PI)
2076 11:05:28.492195 u1DelayCellOfst[7]=7 cells (6 PI)
2077 11:05:28.495570 Byte0, DQ PI dly=984, DQM PI dly= 987
2078 11:05:28.498925 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2079 11:05:28.499532
2080 11:05:28.502040 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2081 11:05:28.502574
2082 11:05:28.505279 u1DelayCellOfst[8]=0 cells (0 PI)
2083 11:05:28.508334 u1DelayCellOfst[9]=3 cells (3 PI)
2084 11:05:28.512243 u1DelayCellOfst[10]=10 cells (8 PI)
2085 11:05:28.515064 u1DelayCellOfst[11]=1 cells (1 PI)
2086 11:05:28.518870 u1DelayCellOfst[12]=5 cells (4 PI)
2087 11:05:28.521640 u1DelayCellOfst[13]=3 cells (3 PI)
2088 11:05:28.524829 u1DelayCellOfst[14]=6 cells (5 PI)
2089 11:05:28.528038 u1DelayCellOfst[15]=9 cells (7 PI)
2090 11:05:28.531350 Byte1, DQ PI dly=979, DQM PI dly= 983
2091 11:05:28.534430 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2092 11:05:28.534575
2093 11:05:28.541034 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2094 11:05:28.541171
2095 11:05:28.541268 Write Rank1 MR14 =0x1e
2096 11:05:28.541359
2097 11:05:28.544175 Final TX Range 0 Vref 30
2098 11:05:28.544272
2099 11:05:28.550847 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2100 11:05:28.550961
2101 11:05:28.557720 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2102 11:05:28.563999 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2103 11:05:28.573771 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2104 11:05:28.573857 Write Rank1 MR3 =0xb0
2105 11:05:28.577123 DramC Write-DBI on
2106 11:05:28.577228 ==
2107 11:05:28.580597 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2108 11:05:28.583414 fsp= 1, odt_onoff= 1, Byte mode= 0
2109 11:05:28.583529 ==
2110 11:05:28.590049 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2111 11:05:28.590142
2112 11:05:28.590212 Begin, DQ Scan Range 703~767
2113 11:05:28.590278
2114 11:05:28.593505
2115 11:05:28.593596 TX Vref Scan disable
2116 11:05:28.596938 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2117 11:05:28.600146 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2118 11:05:28.603399 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2119 11:05:28.606405 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2120 11:05:28.609832 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2121 11:05:28.613157 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2122 11:05:28.619940 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2123 11:05:28.623082 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2124 11:05:28.626060 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2125 11:05:28.629557 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2126 11:05:28.633313 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2127 11:05:28.636719 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2128 11:05:28.639725 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2129 11:05:28.642986 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2130 11:05:28.646304 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2131 11:05:28.649207 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2132 11:05:28.652821 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2133 11:05:28.655843 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2134 11:05:28.665284 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2135 11:05:28.668595 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2136 11:05:28.671610 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2137 11:05:28.675268 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2138 11:05:28.677930 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2139 11:05:28.681714 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2140 11:05:28.684781 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2141 11:05:28.687735 747 |2 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
2142 11:05:28.691098 Byte0, DQ PI dly=733, DQM PI dly= 733
2143 11:05:28.694242 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 29)
2144 11:05:28.697743
2145 11:05:28.700975 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 29)
2146 11:05:28.701479
2147 11:05:28.704205 Byte1, DQ PI dly=726, DQM PI dly= 726
2148 11:05:28.707361 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 22)
2149 11:05:28.707775
2150 11:05:28.714193 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 22)
2151 11:05:28.714585
2152 11:05:28.720853 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2153 11:05:28.727686 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2154 11:05:28.734042 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2155 11:05:28.737173 Write Rank1 MR3 =0x30
2156 11:05:28.737649 DramC Write-DBI off
2157 11:05:28.737953
2158 11:05:28.738229 [DATLAT]
2159 11:05:28.740132 Freq=1600, CH0 RK1, use_rxtx_scan=0
2160 11:05:28.740521
2161 11:05:28.743447 DATLAT Default: 0x10
2162 11:05:28.743890 7, 0xFFFF, sum=0
2163 11:05:28.747027 8, 0xFFFF, sum=0
2164 11:05:28.747591 9, 0xFFFF, sum=0
2165 11:05:28.749976 10, 0xFFFF, sum=0
2166 11:05:28.750485 11, 0xFFFF, sum=0
2167 11:05:28.753145 12, 0xFFFF, sum=0
2168 11:05:28.753559 13, 0xFFFF, sum=0
2169 11:05:28.757023 14, 0x0, sum=1
2170 11:05:28.757428 15, 0x0, sum=2
2171 11:05:28.760361 16, 0x0, sum=3
2172 11:05:28.760765 17, 0x0, sum=4
2173 11:05:28.763816 pattern=2 first_step=14 total pass=5 best_step=16
2174 11:05:28.764232 ==
2175 11:05:28.769915 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2176 11:05:28.773581 fsp= 1, odt_onoff= 1, Byte mode= 0
2177 11:05:28.773983 ==
2178 11:05:28.776948 Start DQ dly to find pass range UseTestEngine =1
2179 11:05:28.779845 x-axis: bit #, y-axis: DQ dly (-127~63)
2180 11:05:28.783337 RX Vref Scan = 0
2181 11:05:28.786739 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2182 11:05:28.789630 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2183 11:05:28.793111 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2184 11:05:28.793518 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2185 11:05:28.796668 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2186 11:05:28.799547 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2187 11:05:28.802973 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2188 11:05:28.806152 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2189 11:05:28.809400 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2190 11:05:28.812582 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2191 11:05:28.815926 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2192 11:05:28.819361 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2193 11:05:28.819817 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2194 11:05:28.822536 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2195 11:05:28.825868 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2196 11:05:28.829206 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2197 11:05:28.832394 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2198 11:05:28.835507 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2199 11:05:28.838722 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2200 11:05:28.842185 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2201 11:05:28.845189 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2202 11:05:28.845566 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2203 11:05:28.848859 -4, [0] xxxxxxxx oxxxxxxx [MSB]
2204 11:05:28.852206 -3, [0] xxxxxxxx oxxxxxxx [MSB]
2205 11:05:28.855179 -2, [0] xxxoxxxx ooxoxxxx [MSB]
2206 11:05:28.858615 -1, [0] xxxoxoxx ooxoxoxx [MSB]
2207 11:05:28.861770 0, [0] xxxoxoxx ooxoooxx [MSB]
2208 11:05:28.865133 1, [0] xxxoxoox ooxoooox [MSB]
2209 11:05:28.865504 2, [0] xxxoxoox ooxoooox [MSB]
2210 11:05:28.868570 3, [0] oxxooooo ooxoooox [MSB]
2211 11:05:28.871900 4, [0] ooxooooo ooxoooox [MSB]
2212 11:05:28.875127 5, [0] ooxooooo ooxooooo [MSB]
2213 11:05:28.878177 6, [0] oooooooo ooxooooo [MSB]
2214 11:05:28.881532 32, [0] oooxoooo oooooooo [MSB]
2215 11:05:28.884958 33, [0] oooxoooo xooxoooo [MSB]
2216 11:05:28.887926 34, [0] oooxoooo xooxxxoo [MSB]
2217 11:05:28.891289 35, [0] oooxoxoo xxoxxxoo [MSB]
2218 11:05:28.894436 36, [0] oooxoxxo xxoxxxoo [MSB]
2219 11:05:28.897789 37, [0] oooxoxxo xxoxxxxo [MSB]
2220 11:05:28.898200 38, [0] oooxoxxx xxoxxxxo [MSB]
2221 11:05:28.901301 39, [0] xxoxxxxx xxoxxxxx [MSB]
2222 11:05:28.904525 40, [0] xxoxxxxx xxxxxxxx [MSB]
2223 11:05:28.907519 41, [0] xxxxxxxx xxxxxxxx [MSB]
2224 11:05:28.910772 iDelay=41, Bit 0, Center 20 (3 ~ 38) 36
2225 11:05:28.914387 iDelay=41, Bit 1, Center 21 (4 ~ 38) 35
2226 11:05:28.917934 iDelay=41, Bit 2, Center 23 (6 ~ 40) 35
2227 11:05:28.921330 iDelay=41, Bit 3, Center 14 (-2 ~ 31) 34
2228 11:05:28.924616 iDelay=41, Bit 4, Center 20 (3 ~ 38) 36
2229 11:05:28.930827 iDelay=41, Bit 5, Center 16 (-1 ~ 34) 36
2230 11:05:28.933991 iDelay=41, Bit 6, Center 18 (1 ~ 35) 35
2231 11:05:28.937370 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35
2232 11:05:28.940635 iDelay=41, Bit 8, Center 14 (-4 ~ 32) 37
2233 11:05:28.943935 iDelay=41, Bit 9, Center 16 (-2 ~ 34) 37
2234 11:05:28.947346 iDelay=41, Bit 10, Center 23 (7 ~ 39) 33
2235 11:05:28.950342 iDelay=41, Bit 11, Center 15 (-2 ~ 32) 35
2236 11:05:28.953531 iDelay=41, Bit 12, Center 16 (0 ~ 33) 34
2237 11:05:28.957023 iDelay=41, Bit 13, Center 16 (-1 ~ 33) 35
2238 11:05:28.963347 iDelay=41, Bit 14, Center 18 (1 ~ 36) 36
2239 11:05:28.966919 iDelay=41, Bit 15, Center 21 (5 ~ 38) 34
2240 11:05:28.967305 ==
2241 11:05:28.969879 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2242 11:05:28.973084 fsp= 1, odt_onoff= 1, Byte mode= 0
2243 11:05:28.973472 ==
2244 11:05:28.976849 DQS Delay:
2245 11:05:28.977232 DQS0 = 0, DQS1 = 0
2246 11:05:28.977528 DQM Delay:
2247 11:05:28.979587 DQM0 = 19, DQM1 = 17
2248 11:05:28.979986 DQ Delay:
2249 11:05:28.983211 DQ0 =20, DQ1 =21, DQ2 =23, DQ3 =14
2250 11:05:28.986265 DQ4 =20, DQ5 =16, DQ6 =18, DQ7 =20
2251 11:05:28.989623 DQ8 =14, DQ9 =16, DQ10 =23, DQ11 =15
2252 11:05:28.992514 DQ12 =16, DQ13 =16, DQ14 =18, DQ15 =21
2253 11:05:28.992916
2254 11:05:28.993229
2255 11:05:28.993505
2256 11:05:28.995987 [DramC_TX_OE_Calibration] TA2
2257 11:05:28.999237 Original DQ_B0 (3 6) =30, OEN = 27
2258 11:05:29.002463 Original DQ_B1 (3 6) =30, OEN = 27
2259 11:05:29.005641 23, 0x0, End_B0=23 End_B1=23
2260 11:05:29.009119 24, 0x0, End_B0=24 End_B1=24
2261 11:05:29.012219 25, 0x0, End_B0=25 End_B1=25
2262 11:05:29.012528 26, 0x0, End_B0=26 End_B1=26
2263 11:05:29.015391 27, 0x0, End_B0=27 End_B1=27
2264 11:05:29.018674 28, 0x0, End_B0=28 End_B1=28
2265 11:05:29.021909 29, 0x0, End_B0=29 End_B1=29
2266 11:05:29.022188 30, 0x0, End_B0=30 End_B1=30
2267 11:05:29.025377 31, 0xFFFF, End_B0=30 End_B1=30
2268 11:05:29.032142 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2269 11:05:29.038294 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2270 11:05:29.038651
2271 11:05:29.038925
2272 11:05:29.039215 Write Rank1 MR23 =0x3f
2273 11:05:29.041656 [DQSOSC]
2274 11:05:29.048265 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8a8, (MSB)MR19= 0x202, tDQSOscB0 = 463 ps tDQSOscB1 = 463 ps
2275 11:05:29.054685 CH0_RK1: MR19=0x202, MR18=0xA8A8, DQSOSC=463, MR23=63, INC=11, DEC=17
2276 11:05:29.058257 Write Rank1 MR23 =0x3f
2277 11:05:29.058613 [DQSOSC]
2278 11:05:29.064745 [DQSOSCAuto] RK1, (LSB)MR18= 0xa9a9, (MSB)MR19= 0x202, tDQSOscB0 = 462 ps tDQSOscB1 = 462 ps
2279 11:05:29.067751 CH0 RK1: MR19=202, MR18=A9A9
2280 11:05:29.071174 [RxdqsGatingPostProcess] freq 1600
2281 11:05:29.078005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2282 11:05:29.078421 Rank: 0
2283 11:05:29.081155 best DQS0 dly(2T, 0.5T) = (2, 6)
2284 11:05:29.084465 best DQS1 dly(2T, 0.5T) = (2, 6)
2285 11:05:29.087556 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2286 11:05:29.090824 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2287 11:05:29.091207 Rank: 1
2288 11:05:29.094033 best DQS0 dly(2T, 0.5T) = (2, 6)
2289 11:05:29.097382 best DQS1 dly(2T, 0.5T) = (2, 6)
2290 11:05:29.100627 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2291 11:05:29.104023 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2292 11:05:29.107358 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2293 11:05:29.110406 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2294 11:05:29.116941 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2295 11:05:29.117513 Write Rank0 MR13 =0x59
2296 11:05:29.120179 ==
2297 11:05:29.123558 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2298 11:05:29.126718 fsp= 1, odt_onoff= 1, Byte mode= 0
2299 11:05:29.127116 ==
2300 11:05:29.130370 === u2Vref_new: 0x56 --> 0x3a
2301 11:05:29.133303 === u2Vref_new: 0x58 --> 0x58
2302 11:05:29.136447 === u2Vref_new: 0x5a --> 0x5a
2303 11:05:29.139679 === u2Vref_new: 0x5c --> 0x78
2304 11:05:29.142915 === u2Vref_new: 0x5e --> 0x7a
2305 11:05:29.146496 === u2Vref_new: 0x60 --> 0x90
2306 11:05:29.149724 [CA 0] Center 37 (12~63) winsize 52
2307 11:05:29.152792 [CA 1] Center 37 (11~63) winsize 53
2308 11:05:29.156277 [CA 2] Center 34 (6~63) winsize 58
2309 11:05:29.159474 [CA 3] Center 34 (6~63) winsize 58
2310 11:05:29.162700 [CA 4] Center 34 (6~63) winsize 58
2311 11:05:29.165883 [CA 5] Center 28 (-1~57) winsize 59
2312 11:05:29.166287
2313 11:05:29.169195 [CATrainingPosCal] consider 1 rank data
2314 11:05:29.172290 u2DelayCellTimex100 = 744/100 ps
2315 11:05:29.176181 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2316 11:05:29.179110 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2317 11:05:29.182594 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2318 11:05:29.185515 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2319 11:05:29.188895 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2320 11:05:29.192437 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2321 11:05:29.192949
2322 11:05:29.198620 CA PerBit enable=1, Macro0, CA PI delay=28
2323 11:05:29.199100 === u2Vref_new: 0x5c --> 0x78
2324 11:05:29.199547
2325 11:05:29.201872 Vref(ca) range 1: 28
2326 11:05:29.202357
2327 11:05:29.205354 CS Dly= 11 (42-0-32)
2328 11:05:29.205892 Write Rank0 MR13 =0xd8
2329 11:05:29.208361 Write Rank0 MR13 =0xd8
2330 11:05:29.211760 Write Rank0 MR12 =0x5c
2331 11:05:29.212196 Write Rank1 MR13 =0x59
2332 11:05:29.212628 ==
2333 11:05:29.218261 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2334 11:05:29.221592 fsp= 1, odt_onoff= 1, Byte mode= 0
2335 11:05:29.222066 ==
2336 11:05:29.224660 === u2Vref_new: 0x56 --> 0x3a
2337 11:05:29.228021 === u2Vref_new: 0x58 --> 0x58
2338 11:05:29.231340 === u2Vref_new: 0x5a --> 0x5a
2339 11:05:29.231582 === u2Vref_new: 0x5c --> 0x78
2340 11:05:29.235000 === u2Vref_new: 0x5e --> 0x7a
2341 11:05:29.238269 === u2Vref_new: 0x60 --> 0x90
2342 11:05:29.241382 [CA 0] Center 37 (11~63) winsize 53
2343 11:05:29.244684 [CA 1] Center 37 (11~63) winsize 53
2344 11:05:29.248196 [CA 2] Center 34 (5~63) winsize 59
2345 11:05:29.251107 [CA 3] Center 35 (7~63) winsize 57
2346 11:05:29.254427 [CA 4] Center 33 (4~63) winsize 60
2347 11:05:29.257870 [CA 5] Center 28 (-1~58) winsize 60
2348 11:05:29.258039
2349 11:05:29.261022 [CATrainingPosCal] consider 2 rank data
2350 11:05:29.264327 u2DelayCellTimex100 = 744/100 ps
2351 11:05:29.267495 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2352 11:05:29.271180 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2353 11:05:29.277505 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2354 11:05:29.280610 CA3 delay=35 (7~63),Diff = 7 PI (9 cell)
2355 11:05:29.284153 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2356 11:05:29.287421 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2357 11:05:29.287894
2358 11:05:29.290679 CA PerBit enable=1, Macro0, CA PI delay=28
2359 11:05:29.294358 === u2Vref_new: 0x5c --> 0x78
2360 11:05:29.294835
2361 11:05:29.297385 Vref(ca) range 1: 28
2362 11:05:29.297825
2363 11:05:29.298288 CS Dly= 10 (41-0-32)
2364 11:05:29.300527 Write Rank1 MR13 =0xd8
2365 11:05:29.303847 Write Rank1 MR13 =0xd8
2366 11:05:29.304237 Write Rank1 MR12 =0x5c
2367 11:05:29.307148 [RankSwap] Rank num 2, (Multi 1), Rank 0
2368 11:05:29.310606 Write Rank0 MR2 =0xad
2369 11:05:29.311090 [Write Leveling]
2370 11:05:29.313850 delay byte0 byte1 byte2 byte3
2371 11:05:29.314238
2372 11:05:29.317516 10 0 0
2373 11:05:29.317991 11 0 0
2374 11:05:29.320139 12 0 0
2375 11:05:29.320550 13 0 0
2376 11:05:29.320860 14 0 0
2377 11:05:29.323501 15 0 0
2378 11:05:29.323906 16 0 0
2379 11:05:29.326736 17 0 0
2380 11:05:29.327129 18 0 0
2381 11:05:29.330430 19 0 0
2382 11:05:29.330907 20 0 0
2383 11:05:29.331219 21 0 0
2384 11:05:29.333826 22 0 0
2385 11:05:29.334307 23 0 0
2386 11:05:29.336792 24 0 0
2387 11:05:29.337189 25 0 0
2388 11:05:29.337498 26 0 0
2389 11:05:29.340008 27 0 0
2390 11:05:29.340463 28 0 0
2391 11:05:29.343168 29 0 ff
2392 11:05:29.343606 30 0 ff
2393 11:05:29.346509 31 0 ff
2394 11:05:29.346899 32 0 ff
2395 11:05:29.349694 33 0 ff
2396 11:05:29.350086 34 0 ff
2397 11:05:29.350387 35 0 ff
2398 11:05:29.352988 36 0 ff
2399 11:05:29.353390 37 ff ff
2400 11:05:29.356396 38 ff ff
2401 11:05:29.356882 39 ff ff
2402 11:05:29.359545 40 ff ff
2403 11:05:29.360021 41 ff ff
2404 11:05:29.363134 42 ff ff
2405 11:05:29.363652 43 ff ff
2406 11:05:29.366650 pass bytecount = 0xff (0xff: all bytes pass)
2407 11:05:29.367118
2408 11:05:29.369847 DQS0 dly: 37
2409 11:05:29.370309 DQS1 dly: 29
2410 11:05:29.372765 Write Rank0 MR2 =0x2d
2411 11:05:29.376211 [RankSwap] Rank num 2, (Multi 1), Rank 0
2412 11:05:29.379494 Write Rank0 MR1 =0xd6
2413 11:05:29.379967 [Gating]
2414 11:05:29.380270 ==
2415 11:05:29.382429 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2416 11:05:29.386254 fsp= 1, odt_onoff= 1, Byte mode= 0
2417 11:05:29.386716 ==
2418 11:05:29.392335 3 1 0 |2c2b 2423 |(11 11)(11 11) |(1 1)(1 1)| 0
2419 11:05:29.395482 3 1 4 |2c2b 3837 |(11 11)(11 11) |(1 1)(0 0)| 0
2420 11:05:29.398802 3 1 8 |2c2b 505 |(11 11)(11 11) |(1 1)(1 1)| 0
2421 11:05:29.405420 3 1 12 |2c2b 3535 |(11 11)(11 11) |(1 0)(1 1)| 0
2422 11:05:29.408805 3 1 16 |2c2b 3636 |(11 11)(11 11) |(1 0)(1 1)| 0
2423 11:05:29.412072 3 1 20 |2c2b 3635 |(11 11)(11 11) |(1 0)(1 1)| 0
2424 11:05:29.418496 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2425 11:05:29.421734 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2426 11:05:29.425138 [Byte 1] Lead/lag falling Transition (3, 1, 28)
2427 11:05:29.431426 3 2 0 |2c2b 1d1c |(11 11)(11 11) |(1 0)(0 1)| 0
2428 11:05:29.435375 3 2 4 |2c2b 1b1b |(11 11)(11 11) |(1 0)(0 1)| 0
2429 11:05:29.438905 3 2 8 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 1)| 0
2430 11:05:29.444918 3 2 12 |2c2b 302f |(11 11)(11 11) |(1 0)(0 1)| 0
2431 11:05:29.447947 3 2 16 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2432 11:05:29.451082 3 2 20 |3534 a09 |(11 11)(11 11) |(0 0)(1 1)| 0
2433 11:05:29.458068 3 2 24 |3534 b0a |(11 11)(11 11) |(0 0)(1 1)| 0
2434 11:05:29.461074 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2435 11:05:29.464470 3 3 0 |3534 e0e |(11 11)(11 11) |(0 0)(1 1)| 0
2436 11:05:29.467655 [Byte 1] Lead/lag Transition tap number (1)
2437 11:05:29.474207 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
2438 11:05:29.477173 3 3 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2439 11:05:29.480974 3 3 12 |3534 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
2440 11:05:29.487273 3 3 16 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2441 11:05:29.490195 3 3 20 |3534 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
2442 11:05:29.493495 3 3 24 |3534 807 |(11 11)(11 11) |(1 1)(1 1)| 0
2443 11:05:29.499992 [Byte 0] Lead/lag falling Transition (3, 3, 24)
2444 11:05:29.503522 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2445 11:05:29.506849 [Byte 1] Lead/lag falling Transition (3, 3, 28)
2446 11:05:29.513173 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2447 11:05:29.516582 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2448 11:05:29.520028 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2449 11:05:29.526233 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2450 11:05:29.529658 3 4 16 |b0a 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2451 11:05:29.532998 3 4 20 |3a39 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2452 11:05:29.539558 3 4 24 |3d3d 1211 |(11 11)(11 11) |(1 1)(1 1)| 0
2453 11:05:29.542870 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2454 11:05:29.545982 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2455 11:05:29.552554 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2456 11:05:29.555885 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2457 11:05:29.559294 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2458 11:05:29.565813 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2459 11:05:29.569280 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2460 11:05:29.572213 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2461 11:05:29.579077 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2462 11:05:29.582030 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2463 11:05:29.585526 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2464 11:05:29.592364 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2465 11:05:29.595541 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2466 11:05:29.598204 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2467 11:05:29.601928 [Byte 0] Lead/lag Transition tap number (2)
2468 11:05:29.608312 [Byte 1] Lead/lag falling Transition (3, 6, 12)
2469 11:05:29.611491 3 6 16 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2470 11:05:29.614878 [Byte 1] Lead/lag Transition tap number (2)
2471 11:05:29.617902 3 6 20 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
2472 11:05:29.621718 [Byte 0]First pass (3, 6, 20)
2473 11:05:29.627983 3 6 24 |4646 1818 |(0 0)(11 11) |(0 0)(0 0)| 0
2474 11:05:29.631571 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2475 11:05:29.634338 [Byte 1]First pass (3, 6, 28)
2476 11:05:29.637838 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2477 11:05:29.641307 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2478 11:05:29.645052 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2479 11:05:29.647701 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2480 11:05:29.654452 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2481 11:05:29.657459 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2482 11:05:29.660748 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2483 11:05:29.663855 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2484 11:05:29.670384 All bytes gating window > 1UI, Early break!
2485 11:05:29.670771
2486 11:05:29.673861 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2487 11:05:29.674355
2488 11:05:29.677230 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 16)
2489 11:05:29.677644
2490 11:05:29.677947
2491 11:05:29.678246
2492 11:05:29.680418 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2493 11:05:29.680810
2494 11:05:29.687032 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
2495 11:05:29.687423
2496 11:05:29.687760
2497 11:05:29.688042 Write Rank0 MR1 =0x56
2498 11:05:29.688311
2499 11:05:29.690042 best RODT dly(2T, 0.5T) = (2, 3)
2500 11:05:29.690428
2501 11:05:29.693447 best RODT dly(2T, 0.5T) = (2, 3)
2502 11:05:29.693839 ==
2503 11:05:29.700016 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2504 11:05:29.703541 fsp= 1, odt_onoff= 1, Byte mode= 0
2505 11:05:29.704024 ==
2506 11:05:29.706828 Start DQ dly to find pass range UseTestEngine =0
2507 11:05:29.709933 x-axis: bit #, y-axis: DQ dly (-127~63)
2508 11:05:29.713210 RX Vref Scan = 0
2509 11:05:29.716637 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2510 11:05:29.717033 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2511 11:05:29.720140 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2512 11:05:29.722958 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2513 11:05:29.726179 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2514 11:05:29.729415 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2515 11:05:29.732715 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2516 11:05:29.736090 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2517 11:05:29.739227 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2518 11:05:29.742455 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2519 11:05:29.742865 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2520 11:05:29.745718 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2521 11:05:29.749078 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2522 11:05:29.752446 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2523 11:05:29.755778 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2524 11:05:29.758865 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2525 11:05:29.762422 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2526 11:05:29.765678 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2527 11:05:29.768752 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2528 11:05:29.769171 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2529 11:05:29.771852 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2530 11:05:29.775384 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2531 11:05:29.778470 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2532 11:05:29.781723 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2533 11:05:29.785143 -2, [0] xxxxxxxx ooxxxxxo [MSB]
2534 11:05:29.788377 -1, [0] xxxoxxxx ooxxxxxo [MSB]
2535 11:05:29.791539 0, [0] xxxoxxxx ooxxxxxo [MSB]
2536 11:05:29.791938 1, [0] xxooxxxx oooxxxxo [MSB]
2537 11:05:29.794871 2, [0] xxooxxxo oooxxxxo [MSB]
2538 11:05:29.798275 3, [0] xxooxxxo ooooxxoo [MSB]
2539 11:05:29.801589 4, [0] xooooxxo oooooooo [MSB]
2540 11:05:29.804875 5, [0] oooooxoo oooooooo [MSB]
2541 11:05:29.808421 6, [0] oooooxoo oooooooo [MSB]
2542 11:05:29.808918 32, [0] oooooooo ooooooox [MSB]
2543 11:05:29.811297 33, [0] oooooooo ooooooox [MSB]
2544 11:05:29.814738 34, [0] oooooooo ooooooox [MSB]
2545 11:05:29.818257 35, [0] ooxooooo oxooooox [MSB]
2546 11:05:29.821455 36, [0] ooxxoooo oxooooox [MSB]
2547 11:05:29.824468 37, [0] ooxxoooo xxooooox [MSB]
2548 11:05:29.827796 38, [0] ooxxoooo xxooooox [MSB]
2549 11:05:29.831299 39, [0] oxxxooox xxoxxoox [MSB]
2550 11:05:29.831844 40, [0] oxxxxoox xxxxxoox [MSB]
2551 11:05:29.834601 41, [0] xxxxxoxx xxxxxxxx [MSB]
2552 11:05:29.837498 42, [0] xxxxxoxx xxxxxxxx [MSB]
2553 11:05:29.841166 43, [0] xxxxxxxx xxxxxxxx [MSB]
2554 11:05:29.844103 iDelay=43, Bit 0, Center 22 (5 ~ 40) 36
2555 11:05:29.847264 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
2556 11:05:29.850675 iDelay=43, Bit 2, Center 17 (1 ~ 34) 34
2557 11:05:29.854121 iDelay=43, Bit 3, Center 17 (-1 ~ 35) 37
2558 11:05:29.857235 iDelay=43, Bit 4, Center 21 (4 ~ 39) 36
2559 11:05:29.863810 iDelay=43, Bit 5, Center 24 (7 ~ 42) 36
2560 11:05:29.867224 iDelay=43, Bit 6, Center 22 (5 ~ 40) 36
2561 11:05:29.870616 iDelay=43, Bit 7, Center 20 (2 ~ 38) 37
2562 11:05:29.873285 iDelay=43, Bit 8, Center 17 (-2 ~ 36) 39
2563 11:05:29.876734 iDelay=43, Bit 9, Center 16 (-2 ~ 34) 37
2564 11:05:29.880041 iDelay=43, Bit 10, Center 20 (1 ~ 39) 39
2565 11:05:29.883169 iDelay=43, Bit 11, Center 20 (3 ~ 38) 36
2566 11:05:29.886544 iDelay=43, Bit 12, Center 21 (4 ~ 38) 35
2567 11:05:29.889712 iDelay=43, Bit 13, Center 22 (4 ~ 40) 37
2568 11:05:29.893061 iDelay=43, Bit 14, Center 21 (3 ~ 40) 38
2569 11:05:29.899480 iDelay=43, Bit 15, Center 13 (-4 ~ 31) 36
2570 11:05:29.899879 ==
2571 11:05:29.902846 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2572 11:05:29.906175 fsp= 1, odt_onoff= 1, Byte mode= 0
2573 11:05:29.906560 ==
2574 11:05:29.909312 DQS Delay:
2575 11:05:29.909696 DQS0 = 0, DQS1 = 0
2576 11:05:29.909997 DQM Delay:
2577 11:05:29.913098 DQM0 = 20, DQM1 = 18
2578 11:05:29.913480 DQ Delay:
2579 11:05:29.915959 DQ0 =22, DQ1 =21, DQ2 =17, DQ3 =17
2580 11:05:29.919375 DQ4 =21, DQ5 =24, DQ6 =22, DQ7 =20
2581 11:05:29.923025 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =20
2582 11:05:29.926332 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =13
2583 11:05:29.926795
2584 11:05:29.927094
2585 11:05:29.929617 DramC Write-DBI off
2586 11:05:29.930078 ==
2587 11:05:29.932292 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2588 11:05:29.935756 fsp= 1, odt_onoff= 1, Byte mode= 0
2589 11:05:29.938721 ==
2590 11:05:29.942443 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2591 11:05:29.942905
2592 11:05:29.945516 Begin, DQ Scan Range 925~1181
2593 11:05:29.945898
2594 11:05:29.946194
2595 11:05:29.946572 TX Vref Scan disable
2596 11:05:29.948527 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2597 11:05:29.955260 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2598 11:05:29.958809 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2599 11:05:29.962135 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2600 11:05:29.965178 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2601 11:05:29.968467 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2602 11:05:29.971768 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2603 11:05:29.975592 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2604 11:05:29.978564 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2605 11:05:29.981762 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2606 11:05:29.984772 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2607 11:05:29.988617 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2608 11:05:29.991570 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2609 11:05:29.994714 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2610 11:05:30.001045 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2611 11:05:30.004508 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2612 11:05:30.007824 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2613 11:05:30.011322 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2614 11:05:30.014180 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2615 11:05:30.017407 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2616 11:05:30.020727 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2617 11:05:30.024268 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2618 11:05:30.027374 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2619 11:05:30.030593 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2620 11:05:30.033769 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2621 11:05:30.037248 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2622 11:05:30.040885 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2623 11:05:30.047204 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2624 11:05:30.050664 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2625 11:05:30.053693 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2626 11:05:30.056694 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2627 11:05:30.060037 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2628 11:05:30.063421 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2629 11:05:30.066718 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2630 11:05:30.070117 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2631 11:05:30.073211 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2632 11:05:30.076504 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2633 11:05:30.079840 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2634 11:05:30.083065 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2635 11:05:30.086367 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2636 11:05:30.089494 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2637 11:05:30.093142 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2638 11:05:30.100060 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2639 11:05:30.102999 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2640 11:05:30.106008 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2641 11:05:30.109487 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2642 11:05:30.112510 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2643 11:05:30.115619 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2644 11:05:30.119286 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2645 11:05:30.122376 974 |3 6 14|[0] xxxxxxxx ooxxxxxo [MSB]
2646 11:05:30.125642 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
2647 11:05:30.128853 976 |3 6 16|[0] xxxxxxxx oooxxxxo [MSB]
2648 11:05:30.132101 977 |3 6 17|[0] xxxxxxxx oooxoxoo [MSB]
2649 11:05:30.135410 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2650 11:05:30.138550 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2651 11:05:30.145385 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2652 11:05:30.148761 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
2653 11:05:30.151619 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
2654 11:05:30.154847 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
2655 11:05:30.158252 991 |3 6 31|[0] oooooooo ooooooox [MSB]
2656 11:05:30.161701 992 |3 6 32|[0] oooooooo ooooooox [MSB]
2657 11:05:30.164695 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2658 11:05:30.168235 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2659 11:05:30.171382 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2660 11:05:30.177936 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2661 11:05:30.181339 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2662 11:05:30.184496 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2663 11:05:30.187811 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2664 11:05:30.191220 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
2665 11:05:30.194270 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2666 11:05:30.197550 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2667 11:05:30.200737 1003 |3 6 43|[0] ooxxoooo xxxxxxxx [MSB]
2668 11:05:30.204009 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB]
2669 11:05:30.207322 1005 |3 6 45|[0] ooxxxoox xxxxxxxx [MSB]
2670 11:05:30.213740 1006 |3 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
2671 11:05:30.217190 Byte0, DQ PI dly=992, DQM PI dly= 992
2672 11:05:30.220495 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32)
2673 11:05:30.220853
2674 11:05:30.223632 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32)
2675 11:05:30.223990
2676 11:05:30.226987 Byte1, DQ PI dly=983, DQM PI dly= 983
2677 11:05:30.233560 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
2678 11:05:30.233919
2679 11:05:30.236895 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
2680 11:05:30.237250
2681 11:05:30.237522 ==
2682 11:05:30.243390 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2683 11:05:30.246800 fsp= 1, odt_onoff= 1, Byte mode= 0
2684 11:05:30.247156 ==
2685 11:05:30.249748 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2686 11:05:30.250100
2687 11:05:30.253067 Begin, DQ Scan Range 959~1023
2688 11:05:30.253476 Write Rank0 MR14 =0x0
2689 11:05:30.263235
2690 11:05:30.263793 CH=1, VrefRange= 0, VrefLevel = 0
2691 11:05:30.269951 TX Bit0 (986~1001) 16 993, Bit8 (977~990) 14 983,
2692 11:05:30.273098 TX Bit1 (984~1000) 17 992, Bit9 (976~987) 12 981,
2693 11:05:30.279750 TX Bit2 (983~998) 16 990, Bit10 (978~992) 15 985,
2694 11:05:30.283166 TX Bit3 (981~996) 16 988, Bit11 (980~991) 12 985,
2695 11:05:30.286449 TX Bit4 (985~999) 15 992, Bit12 (979~991) 13 985,
2696 11:05:30.293145 TX Bit5 (986~1000) 15 993, Bit13 (980~993) 14 986,
2697 11:05:30.295987 TX Bit6 (986~999) 14 992, Bit14 (979~991) 13 985,
2698 11:05:30.302245 TX Bit7 (985~999) 15 992, Bit15 (976~984) 9 980,
2699 11:05:30.302882
2700 11:05:30.303484 Write Rank0 MR14 =0x2
2701 11:05:30.311842
2702 11:05:30.312375 CH=1, VrefRange= 0, VrefLevel = 2
2703 11:05:30.318655 TX Bit0 (986~1001) 16 993, Bit8 (976~990) 15 983,
2704 11:05:30.321883 TX Bit1 (984~1001) 18 992, Bit9 (976~989) 14 982,
2705 11:05:30.328312 TX Bit2 (983~999) 17 991, Bit10 (978~992) 15 985,
2706 11:05:30.331725 TX Bit3 (980~997) 18 988, Bit11 (980~992) 13 986,
2707 11:05:30.335164 TX Bit4 (985~1000) 16 992, Bit12 (978~992) 15 985,
2708 11:05:30.341365 TX Bit5 (986~1001) 16 993, Bit13 (981~993) 13 987,
2709 11:05:30.345079 TX Bit6 (985~1000) 16 992, Bit14 (978~991) 14 984,
2710 11:05:30.351324 TX Bit7 (984~1000) 17 992, Bit15 (975~984) 10 979,
2711 11:05:30.352032
2712 11:05:30.352644 Write Rank0 MR14 =0x4
2713 11:05:30.361017
2714 11:05:30.361496 CH=1, VrefRange= 0, VrefLevel = 4
2715 11:05:30.367494 TX Bit0 (986~1002) 17 994, Bit8 (976~991) 16 983,
2716 11:05:30.371031 TX Bit1 (984~1002) 19 993, Bit9 (976~990) 15 983,
2717 11:05:30.377573 TX Bit2 (983~999) 17 991, Bit10 (977~993) 17 985,
2718 11:05:30.380790 TX Bit3 (980~997) 18 988, Bit11 (979~992) 14 985,
2719 11:05:30.387203 TX Bit4 (985~1000) 16 992, Bit12 (978~992) 15 985,
2720 11:05:30.390451 TX Bit5 (985~1002) 18 993, Bit13 (980~994) 15 987,
2721 11:05:30.393523 TX Bit6 (985~1000) 16 992, Bit14 (978~992) 15 985,
2722 11:05:30.400157 TX Bit7 (984~1000) 17 992, Bit15 (975~985) 11 980,
2723 11:05:30.400478
2724 11:05:30.400720 Write Rank0 MR14 =0x6
2725 11:05:30.410259
2726 11:05:30.410550 CH=1, VrefRange= 0, VrefLevel = 6
2727 11:05:30.417185 TX Bit0 (985~1003) 19 994, Bit8 (976~991) 16 983,
2728 11:05:30.420280 TX Bit1 (984~1002) 19 993, Bit9 (975~990) 16 982,
2729 11:05:30.426855 TX Bit2 (982~999) 18 990, Bit10 (978~994) 17 986,
2730 11:05:30.430058 TX Bit3 (979~998) 20 988, Bit11 (979~993) 15 986,
2731 11:05:30.433531 TX Bit4 (984~1001) 18 992, Bit12 (978~993) 16 985,
2732 11:05:30.439896 TX Bit5 (985~1003) 19 994, Bit13 (979~995) 17 987,
2733 11:05:30.443339 TX Bit6 (985~1001) 17 993, Bit14 (978~992) 15 985,
2734 11:05:30.449902 TX Bit7 (984~1001) 18 992, Bit15 (974~987) 14 980,
2735 11:05:30.450378
2736 11:05:30.450776 Write Rank0 MR14 =0x8
2737 11:05:30.460158
2738 11:05:30.463402 CH=1, VrefRange= 0, VrefLevel = 8
2739 11:05:30.466750 TX Bit0 (986~1004) 19 995, Bit8 (976~992) 17 984,
2740 11:05:30.469616 TX Bit1 (984~1003) 20 993, Bit9 (975~990) 16 982,
2741 11:05:30.476234 TX Bit2 (982~1000) 19 991, Bit10 (977~994) 18 985,
2742 11:05:30.479522 TX Bit3 (979~998) 20 988, Bit11 (979~994) 16 986,
2743 11:05:30.486093 TX Bit4 (984~1001) 18 992, Bit12 (978~994) 17 986,
2744 11:05:30.489646 TX Bit5 (985~1003) 19 994, Bit13 (979~996) 18 987,
2745 11:05:30.492804 TX Bit6 (984~1002) 19 993, Bit14 (978~993) 16 985,
2746 11:05:30.500027 TX Bit7 (984~1001) 18 992, Bit15 (973~988) 16 980,
2747 11:05:30.500493
2748 11:05:30.500797 Write Rank0 MR14 =0xa
2749 11:05:30.509986
2750 11:05:30.513138 CH=1, VrefRange= 0, VrefLevel = 10
2751 11:05:30.516682 TX Bit0 (985~1004) 20 994, Bit8 (975~992) 18 983,
2752 11:05:30.519708 TX Bit1 (983~1004) 22 993, Bit9 (975~991) 17 983,
2753 11:05:30.526560 TX Bit2 (981~1001) 21 991, Bit10 (977~995) 19 986,
2754 11:05:30.529694 TX Bit3 (979~998) 20 988, Bit11 (978~994) 17 986,
2755 11:05:30.536422 TX Bit4 (984~1002) 19 993, Bit12 (977~995) 19 986,
2756 11:05:30.539556 TX Bit5 (985~1004) 20 994, Bit13 (978~997) 20 987,
2757 11:05:30.542882 TX Bit6 (984~1002) 19 993, Bit14 (978~994) 17 986,
2758 11:05:30.549127 TX Bit7 (984~1002) 19 993, Bit15 (973~989) 17 981,
2759 11:05:30.549642
2760 11:05:30.549970 Write Rank0 MR14 =0xc
2761 11:05:30.559996
2762 11:05:30.563219 CH=1, VrefRange= 0, VrefLevel = 12
2763 11:05:30.566378 TX Bit0 (985~1005) 21 995, Bit8 (975~993) 19 984,
2764 11:05:30.569931 TX Bit1 (984~1005) 22 994, Bit9 (974~991) 18 982,
2765 11:05:30.576389 TX Bit2 (981~1001) 21 991, Bit10 (977~996) 20 986,
2766 11:05:30.579376 TX Bit3 (978~999) 22 988, Bit11 (978~995) 18 986,
2767 11:05:30.585764 TX Bit4 (983~1003) 21 993, Bit12 (977~996) 20 986,
2768 11:05:30.589639 TX Bit5 (984~1005) 22 994, Bit13 (978~997) 20 987,
2769 11:05:30.592399 TX Bit6 (984~1003) 20 993, Bit14 (977~995) 19 986,
2770 11:05:30.599383 TX Bit7 (984~1003) 20 993, Bit15 (972~990) 19 981,
2771 11:05:30.599879
2772 11:05:30.600186 Write Rank0 MR14 =0xe
2773 11:05:30.609499
2774 11:05:30.612807 CH=1, VrefRange= 0, VrefLevel = 14
2775 11:05:30.616114 TX Bit0 (985~1005) 21 995, Bit8 (975~993) 19 984,
2776 11:05:30.619604 TX Bit1 (983~1005) 23 994, Bit9 (974~991) 18 982,
2777 11:05:30.626183 TX Bit2 (980~1001) 22 990, Bit10 (976~996) 21 986,
2778 11:05:30.629765 TX Bit3 (978~999) 22 988, Bit11 (978~996) 19 987,
2779 11:05:30.635750 TX Bit4 (983~1004) 22 993, Bit12 (977~997) 21 987,
2780 11:05:30.639007 TX Bit5 (985~1005) 21 995, Bit13 (978~997) 20 987,
2781 11:05:30.642316 TX Bit6 (983~1004) 22 993, Bit14 (977~996) 20 986,
2782 11:05:30.648891 TX Bit7 (983~1003) 21 993, Bit15 (971~990) 20 980,
2783 11:05:30.649341
2784 11:05:30.649641 Write Rank0 MR14 =0x10
2785 11:05:30.659799
2786 11:05:30.663299 CH=1, VrefRange= 0, VrefLevel = 16
2787 11:05:30.666371 TX Bit0 (984~1006) 23 995, Bit8 (975~994) 20 984,
2788 11:05:30.669738 TX Bit1 (983~1005) 23 994, Bit9 (974~992) 19 983,
2789 11:05:30.676448 TX Bit2 (981~1003) 23 992, Bit10 (976~997) 22 986,
2790 11:05:30.679662 TX Bit3 (978~1000) 23 989, Bit11 (978~997) 20 987,
2791 11:05:30.686082 TX Bit4 (982~1004) 23 993, Bit12 (977~997) 21 987,
2792 11:05:30.689245 TX Bit5 (984~1006) 23 995, Bit13 (978~998) 21 988,
2793 11:05:30.692468 TX Bit6 (984~1005) 22 994, Bit14 (976~996) 21 986,
2794 11:05:30.699434 TX Bit7 (983~1004) 22 993, Bit15 (971~990) 20 980,
2795 11:05:30.699967
2796 11:05:30.702635 Write Rank0 MR14 =0x12
2797 11:05:30.710003
2798 11:05:30.713321 CH=1, VrefRange= 0, VrefLevel = 18
2799 11:05:30.716382 TX Bit0 (984~1006) 23 995, Bit8 (974~995) 22 984,
2800 11:05:30.719669 TX Bit1 (982~1006) 25 994, Bit9 (973~992) 20 982,
2801 11:05:30.726401 TX Bit2 (980~1003) 24 991, Bit10 (976~997) 22 986,
2802 11:05:30.729954 TX Bit3 (978~1000) 23 989, Bit11 (978~997) 20 987,
2803 11:05:30.736454 TX Bit4 (982~1005) 24 993, Bit12 (977~997) 21 987,
2804 11:05:30.739313 TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987,
2805 11:05:30.743067 TX Bit6 (983~1005) 23 994, Bit14 (976~997) 22 986,
2806 11:05:30.749040 TX Bit7 (983~1004) 22 993, Bit15 (971~991) 21 981,
2807 11:05:30.749492
2808 11:05:30.752162 Write Rank0 MR14 =0x14
2809 11:05:30.760772
2810 11:05:30.763243 CH=1, VrefRange= 0, VrefLevel = 20
2811 11:05:30.766602 TX Bit0 (984~1006) 23 995, Bit8 (974~995) 22 984,
2812 11:05:30.769926 TX Bit1 (983~1006) 24 994, Bit9 (973~992) 20 982,
2813 11:05:30.776662 TX Bit2 (980~1004) 25 992, Bit10 (976~998) 23 987,
2814 11:05:30.779953 TX Bit3 (978~1000) 23 989, Bit11 (977~998) 22 987,
2815 11:05:30.786476 TX Bit4 (982~1006) 25 994, Bit12 (977~998) 22 987,
2816 11:05:30.789522 TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987,
2817 11:05:30.793032 TX Bit6 (983~1006) 24 994, Bit14 (976~998) 23 987,
2818 11:05:30.799556 TX Bit7 (983~1005) 23 994, Bit15 (970~991) 22 980,
2819 11:05:30.800039
2820 11:05:30.802486 Write Rank0 MR14 =0x16
2821 11:05:30.810320
2822 11:05:30.813358 CH=1, VrefRange= 0, VrefLevel = 22
2823 11:05:30.816860 TX Bit0 (984~1006) 23 995, Bit8 (974~996) 23 985,
2824 11:05:30.820302 TX Bit1 (982~1006) 25 994, Bit9 (973~993) 21 983,
2825 11:05:30.826893 TX Bit2 (979~1004) 26 991, Bit10 (976~998) 23 987,
2826 11:05:30.830222 TX Bit3 (978~1000) 23 989, Bit11 (977~998) 22 987,
2827 11:05:30.836613 TX Bit4 (981~1006) 26 993, Bit12 (976~998) 23 987,
2828 11:05:30.839963 TX Bit5 (983~1006) 24 994, Bit13 (977~999) 23 988,
2829 11:05:30.843319 TX Bit6 (983~1006) 24 994, Bit14 (976~998) 23 987,
2830 11:05:30.849640 TX Bit7 (983~1005) 23 994, Bit15 (970~991) 22 980,
2831 11:05:30.850091
2832 11:05:30.852782 Write Rank0 MR14 =0x18
2833 11:05:30.860543
2834 11:05:30.864446 CH=1, VrefRange= 0, VrefLevel = 24
2835 11:05:30.867619 TX Bit0 (983~1007) 25 995, Bit8 (973~997) 25 985,
2836 11:05:30.870550 TX Bit1 (982~1006) 25 994, Bit9 (972~993) 22 982,
2837 11:05:30.877852 TX Bit2 (979~1005) 27 992, Bit10 (975~998) 24 986,
2838 11:05:30.880592 TX Bit3 (977~1001) 25 989, Bit11 (977~999) 23 988,
2839 11:05:30.887181 TX Bit4 (981~1006) 26 993, Bit12 (976~999) 24 987,
2840 11:05:30.890204 TX Bit5 (983~1006) 24 994, Bit13 (977~999) 23 988,
2841 11:05:30.893754 TX Bit6 (982~1006) 25 994, Bit14 (976~998) 23 987,
2842 11:05:30.900462 TX Bit7 (982~1006) 25 994, Bit15 (970~991) 22 980,
2843 11:05:30.900928
2844 11:05:30.903347 Write Rank0 MR14 =0x1a
2845 11:05:30.910815
2846 11:05:30.914030 CH=1, VrefRange= 0, VrefLevel = 26
2847 11:05:30.917229 TX Bit0 (983~1006) 24 994, Bit8 (974~997) 24 985,
2848 11:05:30.920580 TX Bit1 (981~1006) 26 993, Bit9 (971~994) 24 982,
2849 11:05:30.927287 TX Bit2 (978~1005) 28 991, Bit10 (975~999) 25 987,
2850 11:05:30.930593 TX Bit3 (977~1002) 26 989, Bit11 (977~999) 23 988,
2851 11:05:30.937170 TX Bit4 (981~1006) 26 993, Bit12 (976~999) 24 987,
2852 11:05:30.940224 TX Bit5 (983~1006) 24 994, Bit13 (977~999) 23 988,
2853 11:05:30.943903 TX Bit6 (982~1006) 25 994, Bit14 (976~999) 24 987,
2854 11:05:30.950668 TX Bit7 (982~1006) 25 994, Bit15 (970~991) 22 980,
2855 11:05:30.951136
2856 11:05:30.953343 Write Rank0 MR14 =0x1c
2857 11:05:30.961482
2858 11:05:30.964558 CH=1, VrefRange= 0, VrefLevel = 28
2859 11:05:30.968144 TX Bit0 (983~1007) 25 995, Bit8 (972~997) 26 984,
2860 11:05:30.971611 TX Bit1 (981~1007) 27 994, Bit9 (971~995) 25 983,
2861 11:05:30.977440 TX Bit2 (979~1005) 27 992, Bit10 (975~999) 25 987,
2862 11:05:30.981062 TX Bit3 (978~1002) 25 990, Bit11 (976~999) 24 987,
2863 11:05:30.987581 TX Bit4 (981~1007) 27 994, Bit12 (975~999) 25 987,
2864 11:05:30.990796 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
2865 11:05:30.993876 TX Bit6 (982~1007) 26 994, Bit14 (976~999) 24 987,
2866 11:05:31.000706 TX Bit7 (981~1006) 26 993, Bit15 (970~992) 23 981,
2867 11:05:31.001211
2868 11:05:31.003599 Write Rank0 MR14 =0x1e
2869 11:05:31.011844
2870 11:05:31.015234 CH=1, VrefRange= 0, VrefLevel = 30
2871 11:05:31.018092 TX Bit0 (983~1007) 25 995, Bit8 (972~997) 26 984,
2872 11:05:31.021873 TX Bit1 (981~1006) 26 993, Bit9 (971~994) 24 982,
2873 11:05:31.027966 TX Bit2 (978~1005) 28 991, Bit10 (975~999) 25 987,
2874 11:05:31.031199 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
2875 11:05:31.038325 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
2876 11:05:31.041609 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
2877 11:05:31.044431 TX Bit6 (981~1006) 26 993, Bit14 (975~999) 25 987,
2878 11:05:31.051265 TX Bit7 (981~1006) 26 993, Bit15 (969~992) 24 980,
2879 11:05:31.051787
2880 11:05:31.054436 Write Rank0 MR14 =0x20
2881 11:05:31.062227
2882 11:05:31.065394 CH=1, VrefRange= 0, VrefLevel = 32
2883 11:05:31.069042 TX Bit0 (982~1008) 27 995, Bit8 (973~996) 24 984,
2884 11:05:31.072150 TX Bit1 (982~1007) 26 994, Bit9 (970~994) 25 982,
2885 11:05:31.078606 TX Bit2 (979~1005) 27 992, Bit10 (975~998) 24 986,
2886 11:05:31.081937 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
2887 11:05:31.088445 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
2888 11:05:31.091695 TX Bit5 (982~1007) 26 994, Bit13 (976~999) 24 987,
2889 11:05:31.095040 TX Bit6 (981~1007) 27 994, Bit14 (975~999) 25 987,
2890 11:05:31.101680 TX Bit7 (981~1006) 26 993, Bit15 (969~993) 25 981,
2891 11:05:31.102152
2892 11:05:31.104763 Write Rank0 MR14 =0x22
2893 11:05:31.113267
2894 11:05:31.115862 CH=1, VrefRange= 0, VrefLevel = 34
2895 11:05:31.119062 TX Bit0 (982~1008) 27 995, Bit8 (973~996) 24 984,
2896 11:05:31.122610 TX Bit1 (982~1007) 26 994, Bit9 (970~994) 25 982,
2897 11:05:31.129749 TX Bit2 (979~1005) 27 992, Bit10 (975~998) 24 986,
2898 11:05:31.132436 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
2899 11:05:31.138984 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
2900 11:05:31.141911 TX Bit5 (982~1007) 26 994, Bit13 (976~999) 24 987,
2901 11:05:31.145232 TX Bit6 (981~1007) 27 994, Bit14 (975~999) 25 987,
2902 11:05:31.151845 TX Bit7 (981~1006) 26 993, Bit15 (969~993) 25 981,
2903 11:05:31.152253
2904 11:05:31.155202 wait MRW command Rank0 MR14 =0x24 fired (1)
2905 11:05:31.158420 Write Rank0 MR14 =0x24
2906 11:05:31.167103
2907 11:05:31.170576 CH=1, VrefRange= 0, VrefLevel = 36
2908 11:05:31.173809 TX Bit0 (982~1008) 27 995, Bit8 (973~996) 24 984,
2909 11:05:31.177158 TX Bit1 (982~1007) 26 994, Bit9 (970~994) 25 982,
2910 11:05:31.183546 TX Bit2 (979~1005) 27 992, Bit10 (975~998) 24 986,
2911 11:05:31.186821 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
2912 11:05:31.192971 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
2913 11:05:31.196203 TX Bit5 (982~1007) 26 994, Bit13 (976~999) 24 987,
2914 11:05:31.199361 TX Bit6 (981~1007) 27 994, Bit14 (975~999) 25 987,
2915 11:05:31.206236 TX Bit7 (981~1006) 26 993, Bit15 (969~993) 25 981,
2916 11:05:31.206671
2917 11:05:31.209458 Write Rank0 MR14 =0x26
2918 11:05:31.217474
2919 11:05:31.220529 CH=1, VrefRange= 0, VrefLevel = 38
2920 11:05:31.223897 TX Bit0 (982~1008) 27 995, Bit8 (973~996) 24 984,
2921 11:05:31.227022 TX Bit1 (982~1007) 26 994, Bit9 (970~994) 25 982,
2922 11:05:31.233820 TX Bit2 (979~1005) 27 992, Bit10 (975~998) 24 986,
2923 11:05:31.236661 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
2924 11:05:31.243562 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
2925 11:05:31.246707 TX Bit5 (982~1007) 26 994, Bit13 (976~999) 24 987,
2926 11:05:31.249961 TX Bit6 (981~1007) 27 994, Bit14 (975~999) 25 987,
2927 11:05:31.256367 TX Bit7 (981~1006) 26 993, Bit15 (969~993) 25 981,
2928 11:05:31.256765
2929 11:05:31.257096
2930 11:05:31.259761 TX Vref found, early break! 380< 385
2931 11:05:31.262898 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2932 11:05:31.266258 u1DelayCellOfst[0]=7 cells (6 PI)
2933 11:05:31.269563 u1DelayCellOfst[1]=6 cells (5 PI)
2934 11:05:31.272673 u1DelayCellOfst[2]=3 cells (3 PI)
2935 11:05:31.276021 u1DelayCellOfst[3]=0 cells (0 PI)
2936 11:05:31.279304 u1DelayCellOfst[4]=6 cells (5 PI)
2937 11:05:31.282599 u1DelayCellOfst[5]=6 cells (5 PI)
2938 11:05:31.286191 u1DelayCellOfst[6]=6 cells (5 PI)
2939 11:05:31.289355 u1DelayCellOfst[7]=5 cells (4 PI)
2940 11:05:31.292589 Byte0, DQ PI dly=989, DQM PI dly= 992
2941 11:05:31.295609 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
2942 11:05:31.296018
2943 11:05:31.298842 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
2944 11:05:31.302549
2945 11:05:31.302993 u1DelayCellOfst[8]=3 cells (3 PI)
2946 11:05:31.305536 u1DelayCellOfst[9]=1 cells (1 PI)
2947 11:05:31.309162 u1DelayCellOfst[10]=6 cells (5 PI)
2948 11:05:31.312336 u1DelayCellOfst[11]=7 cells (6 PI)
2949 11:05:31.315389 u1DelayCellOfst[12]=7 cells (6 PI)
2950 11:05:31.318673 u1DelayCellOfst[13]=7 cells (6 PI)
2951 11:05:31.322358 u1DelayCellOfst[14]=7 cells (6 PI)
2952 11:05:31.325473 u1DelayCellOfst[15]=0 cells (0 PI)
2953 11:05:31.328507 Byte1, DQ PI dly=981, DQM PI dly= 984
2954 11:05:31.331545 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
2955 11:05:31.331904
2956 11:05:31.338391 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
2957 11:05:31.338822
2958 11:05:31.339107 Write Rank0 MR14 =0x20
2959 11:05:31.341488
2960 11:05:31.341873 Final TX Range 0 Vref 32
2961 11:05:31.342185
2962 11:05:31.348172 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2963 11:05:31.348597
2964 11:05:31.354435 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2965 11:05:31.361028 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2966 11:05:31.371157 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2967 11:05:31.371568 Write Rank0 MR3 =0xb0
2968 11:05:31.374138 DramC Write-DBI on
2969 11:05:31.374544 ==
2970 11:05:31.377324 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2971 11:05:31.380562 fsp= 1, odt_onoff= 1, Byte mode= 0
2972 11:05:31.380932 ==
2973 11:05:31.387234 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2974 11:05:31.387631
2975 11:05:31.388001 Begin, DQ Scan Range 704~768
2976 11:05:31.390544
2977 11:05:31.390911
2978 11:05:31.391272 TX Vref Scan disable
2979 11:05:31.394096 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2980 11:05:31.397040 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2981 11:05:31.400332 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2982 11:05:31.403704 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2983 11:05:31.407139 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2984 11:05:31.413400 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2985 11:05:31.416698 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2986 11:05:31.419885 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2987 11:05:31.423227 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2988 11:05:31.426503 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2989 11:05:31.429785 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2990 11:05:31.433035 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2991 11:05:31.436210 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2992 11:05:31.439426 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2993 11:05:31.442746 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2994 11:05:31.446315 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2995 11:05:31.449434 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2996 11:05:31.452770 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2997 11:05:31.456111 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2998 11:05:31.462497 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
2999 11:05:31.465809 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3000 11:05:31.472493 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3001 11:05:31.475545 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3002 11:05:31.478679 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3003 11:05:31.482142 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3004 11:05:31.485156 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3005 11:05:31.488693 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3006 11:05:31.491653 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3007 11:05:31.495282 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3008 11:05:31.498318 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3009 11:05:31.501658 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3010 11:05:31.505085 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3011 11:05:31.508261 Byte0, DQ PI dly=738, DQM PI dly= 738
3012 11:05:31.514990 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 34)
3013 11:05:31.515545
3014 11:05:31.518047 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 34)
3015 11:05:31.518605
3016 11:05:31.521295 Byte1, DQ PI dly=728, DQM PI dly= 728
3017 11:05:31.524578 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
3018 11:05:31.524965
3019 11:05:31.531366 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
3020 11:05:31.531787
3021 11:05:31.537679 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3022 11:05:31.544323 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3023 11:05:31.550658 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3024 11:05:31.553940 Write Rank0 MR3 =0x30
3025 11:05:31.554317 DramC Write-DBI off
3026 11:05:31.554595
3027 11:05:31.557198 [DATLAT]
3028 11:05:31.560913 Freq=1600, CH1 RK0, use_rxtx_scan=0
3029 11:05:31.561277
3030 11:05:31.561684 DATLAT Default: 0xf
3031 11:05:31.563661 7, 0xFFFF, sum=0
3032 11:05:31.564033 8, 0xFFFF, sum=0
3033 11:05:31.567261 9, 0xFFFF, sum=0
3034 11:05:31.567721 10, 0xFFFF, sum=0
3035 11:05:31.570422 11, 0xFFFF, sum=0
3036 11:05:31.570811 12, 0xFFFF, sum=0
3037 11:05:31.573547 13, 0xFFFF, sum=0
3038 11:05:31.574017 14, 0x0, sum=1
3039 11:05:31.574426 15, 0x0, sum=2
3040 11:05:31.576942 16, 0x0, sum=3
3041 11:05:31.577528 17, 0x0, sum=4
3042 11:05:31.583651 pattern=2 first_step=14 total pass=5 best_step=16
3043 11:05:31.584008 ==
3044 11:05:31.586853 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3045 11:05:31.590285 fsp= 1, odt_onoff= 1, Byte mode= 0
3046 11:05:31.591011 ==
3047 11:05:31.596601 Start DQ dly to find pass range UseTestEngine =1
3048 11:05:31.599771 x-axis: bit #, y-axis: DQ dly (-127~63)
3049 11:05:31.600146 RX Vref Scan = 1
3050 11:05:31.707440
3051 11:05:31.707566 RX Vref found, early break!
3052 11:05:31.707645
3053 11:05:31.714214 Final RX Vref 11, apply to both rank0 and 1
3054 11:05:31.714299 ==
3055 11:05:31.717460 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3056 11:05:31.720768 fsp= 1, odt_onoff= 1, Byte mode= 0
3057 11:05:31.720861 ==
3058 11:05:31.723957 DQS Delay:
3059 11:05:31.724118 DQS0 = 0, DQS1 = 0
3060 11:05:31.724213 DQM Delay:
3061 11:05:31.727054 DQM0 = 20, DQM1 = 18
3062 11:05:31.727209 DQ Delay:
3063 11:05:31.730363 DQ0 =21, DQ1 =21, DQ2 =18, DQ3 =16
3064 11:05:31.733702 DQ4 =20, DQ5 =23, DQ6 =22, DQ7 =20
3065 11:05:31.737052 DQ8 =17, DQ9 =16, DQ10 =19, DQ11 =20
3066 11:05:31.740764 DQ12 =20, DQ13 =21, DQ14 =20, DQ15 =12
3067 11:05:31.740976
3068 11:05:31.741111
3069 11:05:31.741236
3070 11:05:31.743493 [DramC_TX_OE_Calibration] TA2
3071 11:05:31.747138 Original DQ_B0 (3 6) =30, OEN = 27
3072 11:05:31.750268 Original DQ_B1 (3 6) =30, OEN = 27
3073 11:05:31.753515 23, 0x0, End_B0=23 End_B1=23
3074 11:05:31.756623 24, 0x0, End_B0=24 End_B1=24
3075 11:05:31.756885 25, 0x0, End_B0=25 End_B1=25
3076 11:05:31.760179 26, 0x0, End_B0=26 End_B1=26
3077 11:05:31.763392 27, 0x0, End_B0=27 End_B1=27
3078 11:05:31.766562 28, 0x0, End_B0=28 End_B1=28
3079 11:05:31.770044 29, 0x0, End_B0=29 End_B1=29
3080 11:05:31.770409 30, 0x0, End_B0=30 End_B1=30
3081 11:05:31.773382 31, 0xFFFF, End_B0=30 End_B1=30
3082 11:05:31.779884 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3083 11:05:31.786270 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3084 11:05:31.786628
3085 11:05:31.786902
3086 11:05:31.787155 Write Rank0 MR23 =0x3f
3087 11:05:31.789849 [DQSOSC]
3088 11:05:31.796046 [DQSOSCAuto] RK0, (LSB)MR18= 0xbaba, (MSB)MR19= 0x202, tDQSOscB0 = 451 ps tDQSOscB1 = 451 ps
3089 11:05:31.802657 CH1_RK0: MR19=0x202, MR18=0xBABA, DQSOSC=451, MR23=63, INC=12, DEC=18
3090 11:05:31.806200 Write Rank0 MR23 =0x3f
3091 11:05:31.806598 [DQSOSC]
3092 11:05:31.812483 [DQSOSCAuto] RK0, (LSB)MR18= 0xb9b9, (MSB)MR19= 0x202, tDQSOscB0 = 451 ps tDQSOscB1 = 451 ps
3093 11:05:31.815949 CH1 RK0: MR19=202, MR18=B9B9
3094 11:05:31.819141 [RankSwap] Rank num 2, (Multi 1), Rank 1
3095 11:05:31.822594 Write Rank0 MR2 =0xad
3096 11:05:31.822941 [Write Leveling]
3097 11:05:31.825878 delay byte0 byte1 byte2 byte3
3098 11:05:31.826228
3099 11:05:31.828932 10 0 0
3100 11:05:31.829287 11 0 0
3101 11:05:31.829562 12 0 0
3102 11:05:31.832121 13 0 0
3103 11:05:31.832479 14 0 0
3104 11:05:31.835517 15 0 0
3105 11:05:31.835874 16 0 0
3106 11:05:31.839331 17 0 0
3107 11:05:31.839718 18 0 0
3108 11:05:31.839999 19 0 0
3109 11:05:31.842277 20 0 0
3110 11:05:31.842630 21 0 0
3111 11:05:31.845367 22 0 0
3112 11:05:31.845724 23 0 0
3113 11:05:31.848552 24 0 0
3114 11:05:31.848907 25 0 0
3115 11:05:31.849182 26 0 0
3116 11:05:31.851865 27 0 0
3117 11:05:31.852223 28 0 0
3118 11:05:31.855087 29 0 ff
3119 11:05:31.855443 30 0 ff
3120 11:05:31.858637 31 0 ff
3121 11:05:31.859041 32 0 ff
3122 11:05:31.859329 33 0 ff
3123 11:05:31.861977 34 0 ff
3124 11:05:31.862339 35 0 ff
3125 11:05:31.864783 36 ff ff
3126 11:05:31.865148 37 ff ff
3127 11:05:31.868100 38 ff ff
3128 11:05:31.868463 39 ff ff
3129 11:05:31.871713 40 ff ff
3130 11:05:31.872075 41 ff ff
3131 11:05:31.874594 42 ff ff
3132 11:05:31.877838 pass bytecount = 0xff (0xff: all bytes pass)
3133 11:05:31.878198
3134 11:05:31.878473 DQS0 dly: 36
3135 11:05:31.881098 DQS1 dly: 29
3136 11:05:31.881456 Write Rank0 MR2 =0x2d
3137 11:05:31.884502 [RankSwap] Rank num 2, (Multi 1), Rank 0
3138 11:05:31.887971 Write Rank1 MR1 =0xd6
3139 11:05:31.888327 [Gating]
3140 11:05:31.888603 ==
3141 11:05:31.894567 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3142 11:05:31.897888 fsp= 1, odt_onoff= 1, Byte mode= 0
3143 11:05:31.898251 ==
3144 11:05:31.901056 3 1 0 |2c2b a09 |(11 11)(11 11) |(1 1)(0 0)| 0
3145 11:05:31.907496 3 1 4 |2c2b 3636 |(11 11)(10 10) |(1 1)(1 1)| 0
3146 11:05:31.910978 3 1 8 |2c2b 3636 |(11 11)(11 11) |(1 1)(0 0)| 0
3147 11:05:31.914109 3 1 12 |2c2b 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
3148 11:05:31.920718 3 1 16 |2c2b 3737 |(11 11)(11 11) |(1 0)(0 0)| 0
3149 11:05:31.923997 3 1 20 |2c2b 3636 |(11 11)(11 11) |(1 0)(1 1)| 0
3150 11:05:31.926888 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
3151 11:05:31.933650 3 1 28 |2c2b 3535 |(11 11)(11 11) |(1 0)(1 1)| 0
3152 11:05:31.937034 [Byte 1] Lead/lag falling Transition (3, 1, 28)
3153 11:05:31.940155 3 2 0 |2c2b f0f |(11 11)(11 11) |(1 0)(1 0)| 0
3154 11:05:31.943346 3 2 4 |2c2b 606 |(11 11)(11 11) |(1 0)(1 1)| 0
3155 11:05:31.950155 [Byte 1] Lead/lag falling Transition (3, 2, 4)
3156 11:05:31.953503 3 2 8 |2c2b 3535 |(11 11)(0 0) |(1 0)(0 1)| 0
3157 11:05:31.956744 3 2 12 |2c2b f0f |(11 11)(11 11) |(1 0)(0 1)| 0
3158 11:05:31.963385 3 2 16 |2c2b 3231 |(11 11)(11 11) |(0 0)(0 1)| 0
3159 11:05:31.966591 3 2 20 |302 3333 |(11 11)(11 11) |(0 0)(0 1)| 0
3160 11:05:31.969799 3 2 24 |3534 404 |(11 11)(11 11) |(0 0)(1 1)| 0
3161 11:05:31.972884 [Byte 1] Lead/lag Transition tap number (1)
3162 11:05:31.979983 3 2 28 |3534 3c3c |(11 11)(11 11) |(0 0)(0 0)| 0
3163 11:05:31.982699 3 3 0 |3534 3c3b |(11 11)(11 11) |(0 0)(1 1)| 0
3164 11:05:31.986028 3 3 4 |3534 3b3b |(11 11)(11 11) |(0 0)(1 1)| 0
3165 11:05:31.992491 3 3 8 |3534 3938 |(11 11)(11 11) |(0 0)(1 1)| 0
3166 11:05:31.996108 3 3 12 |3534 3b3b |(11 11)(11 11) |(0 0)(1 1)| 0
3167 11:05:31.999317 3 3 16 |3534 1313 |(11 11)(11 11) |(1 1)(1 1)| 0
3168 11:05:32.005614 3 3 20 |3534 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
3169 11:05:32.009346 [Byte 0] Lead/lag falling Transition (3, 3, 20)
3170 11:05:32.012340 3 3 24 |3534 b0b |(11 11)(11 11) |(0 1)(1 1)| 0
3171 11:05:32.018780 3 3 28 |3534 505 |(11 11)(11 11) |(0 1)(1 1)| 0
3172 11:05:32.022539 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3173 11:05:32.025259 [Byte 1] Lead/lag falling Transition (3, 4, 0)
3174 11:05:32.032017 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3175 11:05:32.035035 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3176 11:05:32.038646 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3177 11:05:32.041829 [Byte 1] Lead/lag Transition tap number (4)
3178 11:05:32.048239 3 4 16 |807 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3179 11:05:32.051405 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3180 11:05:32.054687 3 4 24 |3d3d 808 |(11 11)(11 11) |(1 1)(1 1)| 0
3181 11:05:32.061145 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3182 11:05:32.064241 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3183 11:05:32.067436 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3184 11:05:32.074170 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3185 11:05:32.077384 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3186 11:05:32.080633 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3187 11:05:32.087365 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3188 11:05:32.090307 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3189 11:05:32.093629 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3190 11:05:32.100523 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3191 11:05:32.103394 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3192 11:05:32.106866 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3193 11:05:32.113372 [Byte 0] Lead/lag falling Transition (3, 6, 8)
3194 11:05:32.116529 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3195 11:05:32.119792 [Byte 0] Lead/lag Transition tap number (2)
3196 11:05:32.123264 [Byte 1] Lead/lag falling Transition (3, 6, 12)
3197 11:05:32.129593 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3198 11:05:32.133007 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3199 11:05:32.136385 [Byte 1] Lead/lag Transition tap number (3)
3200 11:05:32.142748 3 6 24 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3201 11:05:32.142835 [Byte 0]First pass (3, 6, 24)
3202 11:05:32.149423 3 6 28 |4646 4040 |(0 0)(11 11) |(0 0)(0 0)| 0
3203 11:05:32.152693 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3204 11:05:32.155847 [Byte 1]First pass (3, 7, 0)
3205 11:05:32.159281 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3206 11:05:32.162239 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3207 11:05:32.165570 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3208 11:05:32.172310 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3209 11:05:32.175546 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3210 11:05:32.178795 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3211 11:05:32.182110 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3212 11:05:32.185576 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3213 11:05:32.192150 All bytes gating window > 1UI, Early break!
3214 11:05:32.192294
3215 11:05:32.195423 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
3216 11:05:32.195595
3217 11:05:32.198517 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 18)
3218 11:05:32.198671
3219 11:05:32.198788
3220 11:05:32.198918
3221 11:05:32.201941 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3222 11:05:32.202119
3223 11:05:32.208388 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 18)
3224 11:05:32.208599
3225 11:05:32.208761
3226 11:05:32.208941 Write Rank1 MR1 =0x56
3227 11:05:32.209116
3228 11:05:32.211843 best RODT dly(2T, 0.5T) = (2, 3)
3229 11:05:32.212100
3230 11:05:32.215151 best RODT dly(2T, 0.5T) = (2, 3)
3231 11:05:32.215515 ==
3232 11:05:32.221647 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3233 11:05:32.225005 fsp= 1, odt_onoff= 1, Byte mode= 0
3234 11:05:32.225365 ==
3235 11:05:32.228142 Start DQ dly to find pass range UseTestEngine =0
3236 11:05:32.231497 x-axis: bit #, y-axis: DQ dly (-127~63)
3237 11:05:32.234587 RX Vref Scan = 0
3238 11:05:32.237958 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3239 11:05:32.238326 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3240 11:05:32.241277 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3241 11:05:32.244812 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3242 11:05:32.247959 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3243 11:05:32.251251 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3244 11:05:32.254265 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3245 11:05:32.257836 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3246 11:05:32.261095 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3247 11:05:32.264135 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3248 11:05:32.264498 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3249 11:05:32.267726 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3250 11:05:32.270855 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3251 11:05:32.273944 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3252 11:05:32.277367 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3253 11:05:32.280571 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3254 11:05:32.284212 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3255 11:05:32.287131 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3256 11:05:32.290356 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3257 11:05:32.290716 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3258 11:05:32.293593 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3259 11:05:32.296840 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3260 11:05:32.300046 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3261 11:05:32.303799 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3262 11:05:32.306989 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3263 11:05:32.310106 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3264 11:05:32.313517 0, [0] xxxoxxxx ooxxxxxo [MSB]
3265 11:05:32.313878 1, [0] xxxoxxxx ooxxoxxo [MSB]
3266 11:05:32.316525 2, [0] xxooxxxx ooxxoxxo [MSB]
3267 11:05:32.319963 3, [0] xxooxxxo oooxoxxo [MSB]
3268 11:05:32.322930 4, [0] xoooxxxo oooooooo [MSB]
3269 11:05:32.326677 32, [0] oooooooo ooooooox [MSB]
3270 11:05:32.329874 33, [0] oooooooo ooooooox [MSB]
3271 11:05:32.332836 34, [0] oooooooo oxooooox [MSB]
3272 11:05:32.333231 35, [0] ooxxoooo oxooooox [MSB]
3273 11:05:32.336686 36, [0] ooxxoooo xxooooox [MSB]
3274 11:05:32.339562 37, [0] ooxxoooo xxooooox [MSB]
3275 11:05:32.342919 38, [0] ooxxoooo xxooooox [MSB]
3276 11:05:32.346491 39, [0] oxxxooox xxooooox [MSB]
3277 11:05:32.349467 40, [0] oxxxooox xxxxooox [MSB]
3278 11:05:32.352590 41, [0] oxxxxoxx xxxxxoox [MSB]
3279 11:05:32.355789 42, [0] xxxxxoxx xxxxxxxx [MSB]
3280 11:05:32.356186 43, [0] xxxxxxxx xxxxxxxx [MSB]
3281 11:05:32.359624 iDelay=43, Bit 0, Center 23 (5 ~ 41) 37
3282 11:05:32.365896 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
3283 11:05:32.369128 iDelay=43, Bit 2, Center 18 (2 ~ 34) 33
3284 11:05:32.372448 iDelay=43, Bit 3, Center 16 (-2 ~ 34) 37
3285 11:05:32.375933 iDelay=43, Bit 4, Center 22 (5 ~ 40) 36
3286 11:05:32.379395 iDelay=43, Bit 5, Center 23 (5 ~ 42) 38
3287 11:05:32.382234 iDelay=43, Bit 6, Center 22 (5 ~ 40) 36
3288 11:05:32.385781 iDelay=43, Bit 7, Center 20 (3 ~ 38) 36
3289 11:05:32.389222 iDelay=43, Bit 8, Center 17 (0 ~ 35) 36
3290 11:05:32.392398 iDelay=43, Bit 9, Center 15 (-2 ~ 33) 36
3291 11:05:32.395265 iDelay=43, Bit 10, Center 21 (3 ~ 39) 37
3292 11:05:32.398934 iDelay=43, Bit 11, Center 21 (4 ~ 39) 36
3293 11:05:32.404999 iDelay=43, Bit 12, Center 20 (1 ~ 40) 40
3294 11:05:32.408619 iDelay=43, Bit 13, Center 22 (4 ~ 41) 38
3295 11:05:32.411828 iDelay=43, Bit 14, Center 22 (4 ~ 41) 38
3296 11:05:32.415257 iDelay=43, Bit 15, Center 13 (-4 ~ 31) 36
3297 11:05:32.415772 ==
3298 11:05:32.417865 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3299 11:05:32.421503 fsp= 1, odt_onoff= 1, Byte mode= 0
3300 11:05:32.424738 ==
3301 11:05:32.425219 DQS Delay:
3302 11:05:32.425524 DQS0 = 0, DQS1 = 0
3303 11:05:32.427912 DQM Delay:
3304 11:05:32.428301 DQM0 = 20, DQM1 = 18
3305 11:05:32.431106 DQ Delay:
3306 11:05:32.434729 DQ0 =23, DQ1 =21, DQ2 =18, DQ3 =16
3307 11:05:32.435129 DQ4 =22, DQ5 =23, DQ6 =22, DQ7 =20
3308 11:05:32.438040 DQ8 =17, DQ9 =15, DQ10 =21, DQ11 =21
3309 11:05:32.444121 DQ12 =20, DQ13 =22, DQ14 =22, DQ15 =13
3310 11:05:32.444568
3311 11:05:32.444866
3312 11:05:32.445138 DramC Write-DBI off
3313 11:05:32.445399 ==
3314 11:05:32.450995 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3315 11:05:32.454484 fsp= 1, odt_onoff= 1, Byte mode= 0
3316 11:05:32.454945 ==
3317 11:05:32.457671 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3318 11:05:32.458137
3319 11:05:32.460552 Begin, DQ Scan Range 925~1181
3320 11:05:32.460942
3321 11:05:32.461238
3322 11:05:32.464337 TX Vref Scan disable
3323 11:05:32.467394 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3324 11:05:32.470970 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3325 11:05:32.473928 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3326 11:05:32.477145 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3327 11:05:32.480260 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3328 11:05:32.484003 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3329 11:05:32.486750 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3330 11:05:32.490270 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3331 11:05:32.493654 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3332 11:05:32.500113 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3333 11:05:32.502973 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3334 11:05:32.506651 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3335 11:05:32.510076 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3336 11:05:32.513285 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3337 11:05:32.516112 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3338 11:05:32.519732 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3339 11:05:32.522997 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3340 11:05:32.526416 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3341 11:05:32.529480 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3342 11:05:32.532772 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3343 11:05:32.536140 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3344 11:05:32.539569 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3345 11:05:32.546170 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3346 11:05:32.549288 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3347 11:05:32.552542 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3348 11:05:32.556012 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3349 11:05:32.558750 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3350 11:05:32.562066 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3351 11:05:32.565174 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3352 11:05:32.568421 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3353 11:05:32.571748 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3354 11:05:32.575123 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3355 11:05:32.578378 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3356 11:05:32.581625 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3357 11:05:32.585228 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3358 11:05:32.592115 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3359 11:05:32.594968 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3360 11:05:32.598076 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3361 11:05:32.601296 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3362 11:05:32.604927 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3363 11:05:32.608052 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3364 11:05:32.611135 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3365 11:05:32.614563 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3366 11:05:32.617621 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3367 11:05:32.620837 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3368 11:05:32.624337 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3369 11:05:32.627640 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3370 11:05:32.631102 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3371 11:05:32.634556 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3372 11:05:32.637311 974 |3 6 14|[0] xxxxxxxx xxxxxxxo [MSB]
3373 11:05:32.640824 975 |3 6 15|[0] xxxxxxxx xoxxxxxo [MSB]
3374 11:05:32.647054 976 |3 6 16|[0] xxxxxxxx oooxxxxo [MSB]
3375 11:05:32.650283 977 |3 6 17|[0] xxxxxxxx oooooxoo [MSB]
3376 11:05:32.653600 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
3377 11:05:32.657027 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
3378 11:05:32.660125 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
3379 11:05:32.663656 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3380 11:05:32.667152 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3381 11:05:32.670158 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
3382 11:05:32.676936 992 |3 6 32|[0] oooooooo ooooooox [MSB]
3383 11:05:32.680142 993 |3 6 33|[0] oooooooo xxooooox [MSB]
3384 11:05:32.683241 994 |3 6 34|[0] oooooooo xxooooox [MSB]
3385 11:05:32.686582 995 |3 6 35|[0] oooooooo xxooooox [MSB]
3386 11:05:32.689834 996 |3 6 36|[0] oooooooo xxooooox [MSB]
3387 11:05:32.692905 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3388 11:05:32.696503 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3389 11:05:32.699520 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3390 11:05:32.703169 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
3391 11:05:32.706369 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
3392 11:05:32.709488 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
3393 11:05:32.715910 1003 |3 6 43|[0] ooxxoooo xxxxxxxx [MSB]
3394 11:05:32.719449 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB]
3395 11:05:32.722724 1005 |3 6 45|[0] ooxxooox xxxxxxxx [MSB]
3396 11:05:32.726027 1006 |3 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
3397 11:05:32.729096 Byte0, DQ PI dly=992, DQM PI dly= 992
3398 11:05:32.732441 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32)
3399 11:05:32.732886
3400 11:05:32.738977 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32)
3401 11:05:32.739409
3402 11:05:32.742259 Byte1, DQ PI dly=984, DQM PI dly= 984
3403 11:05:32.745928 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
3404 11:05:32.746402
3405 11:05:32.748722 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
3406 11:05:32.749258
3407 11:05:32.749577 ==
3408 11:05:32.755112 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3409 11:05:32.758539 fsp= 1, odt_onoff= 1, Byte mode= 0
3410 11:05:32.758926 ==
3411 11:05:32.762027 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3412 11:05:32.762417
3413 11:05:32.764852 Begin, DQ Scan Range 960~1024
3414 11:05:32.768222 wait MRW command Rank1 MR14 =0x0 fired (1)
3415 11:05:32.771372 Write Rank1 MR14 =0x0
3416 11:05:32.779728
3417 11:05:32.780113 CH=1, VrefRange= 0, VrefLevel = 0
3418 11:05:32.786767 TX Bit0 (986~1001) 16 993, Bit8 (978~989) 12 983,
3419 11:05:32.789586 TX Bit1 (985~999) 15 992, Bit9 (977~988) 12 982,
3420 11:05:32.796048 TX Bit2 (983~998) 16 990, Bit10 (978~992) 15 985,
3421 11:05:32.799867 TX Bit3 (981~993) 13 987, Bit11 (979~992) 14 985,
3422 11:05:32.803104 TX Bit4 (984~1000) 17 992, Bit12 (981~991) 11 986,
3423 11:05:32.809742 TX Bit5 (985~1001) 17 993, Bit13 (980~993) 14 986,
3424 11:05:32.812769 TX Bit6 (985~999) 15 992, Bit14 (979~991) 13 985,
3425 11:05:32.819186 TX Bit7 (985~998) 14 991, Bit15 (975~985) 11 980,
3426 11:05:32.819741
3427 11:05:32.820228 Write Rank1 MR14 =0x2
3428 11:05:32.828781
3429 11:05:32.829214 CH=1, VrefRange= 0, VrefLevel = 2
3430 11:05:32.835482 TX Bit0 (985~1003) 19 994, Bit8 (977~990) 14 983,
3431 11:05:32.839310 TX Bit1 (985~1000) 16 992, Bit9 (977~989) 13 983,
3432 11:05:32.845796 TX Bit2 (983~998) 16 990, Bit10 (978~993) 16 985,
3433 11:05:32.848720 TX Bit3 (980~995) 16 987, Bit11 (979~993) 15 986,
3434 11:05:32.852395 TX Bit4 (984~1000) 17 992, Bit12 (980~991) 12 985,
3435 11:05:32.858691 TX Bit5 (985~1001) 17 993, Bit13 (980~994) 15 987,
3436 11:05:32.861732 TX Bit6 (985~1000) 16 992, Bit14 (979~992) 14 985,
3437 11:05:32.868202 TX Bit7 (985~999) 15 992, Bit15 (974~985) 12 979,
3438 11:05:32.868631
3439 11:05:32.868930 Write Rank1 MR14 =0x4
3440 11:05:32.878540
3441 11:05:32.879055 CH=1, VrefRange= 0, VrefLevel = 4
3442 11:05:32.884536 TX Bit0 (985~1003) 19 994, Bit8 (978~990) 13 984,
3443 11:05:32.887904 TX Bit1 (984~1000) 17 992, Bit9 (976~990) 15 983,
3444 11:05:32.895078 TX Bit2 (983~999) 17 991, Bit10 (977~994) 18 985,
3445 11:05:32.898105 TX Bit3 (980~996) 17 988, Bit11 (979~993) 15 986,
3446 11:05:32.901087 TX Bit4 (984~1001) 18 992, Bit12 (980~992) 13 986,
3447 11:05:32.907653 TX Bit5 (985~1002) 18 993, Bit13 (979~995) 17 987,
3448 11:05:32.911210 TX Bit6 (985~1001) 17 993, Bit14 (978~992) 15 985,
3449 11:05:32.917696 TX Bit7 (984~999) 16 991, Bit15 (974~986) 13 980,
3450 11:05:32.918166
3451 11:05:32.918571 Write Rank1 MR14 =0x6
3452 11:05:32.927852
3453 11:05:32.928311 CH=1, VrefRange= 0, VrefLevel = 6
3454 11:05:32.934319 TX Bit0 (985~1004) 20 994, Bit8 (978~991) 14 984,
3455 11:05:32.937453 TX Bit1 (984~1001) 18 992, Bit9 (976~990) 15 983,
3456 11:05:32.943893 TX Bit2 (982~999) 18 990, Bit10 (977~994) 18 985,
3457 11:05:32.947341 TX Bit3 (979~997) 19 988, Bit11 (978~994) 17 986,
3458 11:05:32.950491 TX Bit4 (984~1002) 19 993, Bit12 (978~993) 16 985,
3459 11:05:32.956995 TX Bit5 (985~1003) 19 994, Bit13 (979~996) 18 987,
3460 11:05:32.960197 TX Bit6 (985~1001) 17 993, Bit14 (978~993) 16 985,
3461 11:05:32.966789 TX Bit7 (984~1000) 17 992, Bit15 (973~987) 15 980,
3462 11:05:32.967191
3463 11:05:32.967520 Write Rank1 MR14 =0x8
3464 11:05:32.977279
3465 11:05:32.977744 CH=1, VrefRange= 0, VrefLevel = 8
3466 11:05:32.983505 TX Bit0 (985~1005) 21 995, Bit8 (976~991) 16 983,
3467 11:05:32.987166 TX Bit1 (984~1002) 19 993, Bit9 (976~990) 15 983,
3468 11:05:32.993270 TX Bit2 (982~1000) 19 991, Bit10 (977~995) 19 986,
3469 11:05:32.996790 TX Bit3 (979~997) 19 988, Bit11 (978~995) 18 986,
3470 11:05:33.003574 TX Bit4 (983~1003) 21 993, Bit12 (978~993) 16 985,
3471 11:05:33.006679 TX Bit5 (985~1004) 20 994, Bit13 (979~997) 19 988,
3472 11:05:33.009954 TX Bit6 (984~1002) 19 993, Bit14 (978~994) 17 986,
3473 11:05:33.016256 TX Bit7 (984~1000) 17 992, Bit15 (973~989) 17 981,
3474 11:05:33.016650
3475 11:05:33.016949 Write Rank1 MR14 =0xa
3476 11:05:33.027178
3477 11:05:33.030240 CH=1, VrefRange= 0, VrefLevel = 10
3478 11:05:33.033530 TX Bit0 (985~1005) 21 995, Bit8 (977~991) 15 984,
3479 11:05:33.036890 TX Bit1 (984~1003) 20 993, Bit9 (975~991) 17 983,
3480 11:05:33.043408 TX Bit2 (982~1000) 19 991, Bit10 (977~996) 20 986,
3481 11:05:33.046668 TX Bit3 (979~998) 20 988, Bit11 (978~996) 19 987,
3482 11:05:33.053406 TX Bit4 (983~1003) 21 993, Bit12 (978~994) 17 986,
3483 11:05:33.056544 TX Bit5 (985~1005) 21 995, Bit13 (978~997) 20 987,
3484 11:05:33.059663 TX Bit6 (984~1003) 20 993, Bit14 (977~994) 18 985,
3485 11:05:33.066306 TX Bit7 (984~1001) 18 992, Bit15 (972~990) 19 981,
3486 11:05:33.066812
3487 11:05:33.067125 Write Rank1 MR14 =0xc
3488 11:05:33.076854
3489 11:05:33.079846 CH=1, VrefRange= 0, VrefLevel = 12
3490 11:05:33.083412 TX Bit0 (984~1006) 23 995, Bit8 (976~992) 17 984,
3491 11:05:33.086917 TX Bit1 (983~1004) 22 993, Bit9 (975~991) 17 983,
3492 11:05:33.092969 TX Bit2 (982~1001) 20 991, Bit10 (977~997) 21 987,
3493 11:05:33.096293 TX Bit3 (978~998) 21 988, Bit11 (978~997) 20 987,
3494 11:05:33.102824 TX Bit4 (983~1004) 22 993, Bit12 (978~995) 18 986,
3495 11:05:33.106016 TX Bit5 (984~1005) 22 994, Bit13 (978~998) 21 988,
3496 11:05:33.109700 TX Bit6 (984~1004) 21 994, Bit14 (977~995) 19 986,
3497 11:05:33.116002 TX Bit7 (984~1002) 19 993, Bit15 (972~990) 19 981,
3498 11:05:33.116398
3499 11:05:33.116700 Write Rank1 MR14 =0xe
3500 11:05:33.127166
3501 11:05:33.130403 CH=1, VrefRange= 0, VrefLevel = 14
3502 11:05:33.133816 TX Bit0 (984~1006) 23 995, Bit8 (976~992) 17 984,
3503 11:05:33.136891 TX Bit1 (983~1005) 23 994, Bit9 (975~991) 17 983,
3504 11:05:33.143586 TX Bit2 (981~1001) 21 991, Bit10 (976~997) 22 986,
3505 11:05:33.146983 TX Bit3 (978~998) 21 988, Bit11 (977~997) 21 987,
3506 11:05:33.153200 TX Bit4 (983~1005) 23 994, Bit12 (978~996) 19 987,
3507 11:05:33.156077 TX Bit5 (984~1006) 23 995, Bit13 (978~998) 21 988,
3508 11:05:33.159684 TX Bit6 (984~1005) 22 994, Bit14 (977~996) 20 986,
3509 11:05:33.165955 TX Bit7 (984~1003) 20 993, Bit15 (971~991) 21 981,
3510 11:05:33.166349
3511 11:05:33.166651 Write Rank1 MR14 =0x10
3512 11:05:33.177120
3513 11:05:33.179883 CH=1, VrefRange= 0, VrefLevel = 16
3514 11:05:33.183420 TX Bit0 (984~1006) 23 995, Bit8 (975~993) 19 984,
3515 11:05:33.186763 TX Bit1 (983~1005) 23 994, Bit9 (975~992) 18 983,
3516 11:05:33.193229 TX Bit2 (980~1002) 23 991, Bit10 (977~998) 22 987,
3517 11:05:33.196203 TX Bit3 (978~999) 22 988, Bit11 (977~998) 22 987,
3518 11:05:33.202874 TX Bit4 (982~1005) 24 993, Bit12 (977~997) 21 987,
3519 11:05:33.206349 TX Bit5 (985~1006) 22 995, Bit13 (978~998) 21 988,
3520 11:05:33.209503 TX Bit6 (983~1005) 23 994, Bit14 (976~997) 22 986,
3521 11:05:33.216188 TX Bit7 (983~1004) 22 993, Bit15 (970~991) 22 980,
3522 11:05:33.216639
3523 11:05:33.218892 Write Rank1 MR14 =0x12
3524 11:05:33.226842
3525 11:05:33.229906 CH=1, VrefRange= 0, VrefLevel = 18
3526 11:05:33.233144 TX Bit0 (984~1006) 23 995, Bit8 (975~993) 19 984,
3527 11:05:33.236429 TX Bit1 (982~1005) 24 993, Bit9 (974~992) 19 983,
3528 11:05:33.243261 TX Bit2 (980~1004) 25 992, Bit10 (976~998) 23 987,
3529 11:05:33.246574 TX Bit3 (978~999) 22 988, Bit11 (977~998) 22 987,
3530 11:05:33.252847 TX Bit4 (982~1005) 24 993, Bit12 (977~997) 21 987,
3531 11:05:33.256194 TX Bit5 (984~1006) 23 995, Bit13 (977~999) 23 988,
3532 11:05:33.259640 TX Bit6 (983~1005) 23 994, Bit14 (976~997) 22 986,
3533 11:05:33.265890 TX Bit7 (983~1004) 22 993, Bit15 (971~991) 21 981,
3534 11:05:33.266282
3535 11:05:33.266580 Write Rank1 MR14 =0x14
3536 11:05:33.277050
3537 11:05:33.279973 CH=1, VrefRange= 0, VrefLevel = 20
3538 11:05:33.283781 TX Bit0 (984~1006) 23 995, Bit8 (975~994) 20 984,
3539 11:05:33.286641 TX Bit1 (983~1006) 24 994, Bit9 (974~993) 20 983,
3540 11:05:33.293054 TX Bit2 (979~1004) 26 991, Bit10 (976~998) 23 987,
3541 11:05:33.296290 TX Bit3 (978~1000) 23 989, Bit11 (977~998) 22 987,
3542 11:05:33.303227 TX Bit4 (982~1006) 25 994, Bit12 (977~998) 22 987,
3543 11:05:33.306228 TX Bit5 (984~1006) 23 995, Bit13 (977~999) 23 988,
3544 11:05:33.309897 TX Bit6 (983~1006) 24 994, Bit14 (977~998) 22 987,
3545 11:05:33.316148 TX Bit7 (983~1005) 23 994, Bit15 (970~992) 23 981,
3546 11:05:33.316540
3547 11:05:33.319558 Write Rank1 MR14 =0x16
3548 11:05:33.327428
3549 11:05:33.330592 CH=1, VrefRange= 0, VrefLevel = 22
3550 11:05:33.333719 TX Bit0 (983~1007) 25 995, Bit8 (975~994) 20 984,
3551 11:05:33.336980 TX Bit1 (982~1006) 25 994, Bit9 (974~993) 20 983,
3552 11:05:33.343895 TX Bit2 (980~1004) 25 992, Bit10 (976~999) 24 987,
3553 11:05:33.347056 TX Bit3 (978~1000) 23 989, Bit11 (977~999) 23 988,
3554 11:05:33.353429 TX Bit4 (982~1006) 25 994, Bit12 (977~998) 22 987,
3555 11:05:33.356453 TX Bit5 (983~1006) 24 994, Bit13 (977~999) 23 988,
3556 11:05:33.359817 TX Bit6 (982~1006) 25 994, Bit14 (976~998) 23 987,
3557 11:05:33.366110 TX Bit7 (983~1005) 23 994, Bit15 (970~992) 23 981,
3558 11:05:33.366633
3559 11:05:33.369491 Write Rank1 MR14 =0x18
3560 11:05:33.377726
3561 11:05:33.380389 CH=1, VrefRange= 0, VrefLevel = 24
3562 11:05:33.383758 TX Bit0 (984~1007) 24 995, Bit8 (975~995) 21 985,
3563 11:05:33.387293 TX Bit1 (982~1006) 25 994, Bit9 (973~994) 22 983,
3564 11:05:33.393659 TX Bit2 (980~1005) 26 992, Bit10 (976~999) 24 987,
3565 11:05:33.396849 TX Bit3 (978~1000) 23 989, Bit11 (976~999) 24 987,
3566 11:05:33.403426 TX Bit4 (981~1006) 26 993, Bit12 (977~998) 22 987,
3567 11:05:33.406557 TX Bit5 (983~1007) 25 995, Bit13 (977~1000) 24 988,
3568 11:05:33.409829 TX Bit6 (982~1006) 25 994, Bit14 (976~998) 23 987,
3569 11:05:33.416445 TX Bit7 (982~1006) 25 994, Bit15 (970~992) 23 981,
3570 11:05:33.416806
3571 11:05:33.419699 Write Rank1 MR14 =0x1a
3572 11:05:33.427492
3573 11:05:33.431161 CH=1, VrefRange= 0, VrefLevel = 26
3574 11:05:33.434082 TX Bit0 (983~1007) 25 995, Bit8 (974~996) 23 985,
3575 11:05:33.437704 TX Bit1 (981~1006) 26 993, Bit9 (973~995) 23 984,
3576 11:05:33.443873 TX Bit2 (979~1005) 27 992, Bit10 (976~999) 24 987,
3577 11:05:33.447047 TX Bit3 (977~1001) 25 989, Bit11 (976~999) 24 987,
3578 11:05:33.454352 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
3579 11:05:33.457211 TX Bit5 (982~1007) 26 994, Bit13 (977~1000) 24 988,
3580 11:05:33.460481 TX Bit6 (981~1006) 26 993, Bit14 (976~999) 24 987,
3581 11:05:33.467316 TX Bit7 (982~1006) 25 994, Bit15 (970~993) 24 981,
3582 11:05:33.467830
3583 11:05:33.470074 Write Rank1 MR14 =0x1c
3584 11:05:33.478330
3585 11:05:33.481782 CH=1, VrefRange= 0, VrefLevel = 28
3586 11:05:33.484696 TX Bit0 (983~1007) 25 995, Bit8 (974~997) 24 985,
3587 11:05:33.487780 TX Bit1 (981~1006) 26 993, Bit9 (972~995) 24 983,
3588 11:05:33.494664 TX Bit2 (978~1005) 28 991, Bit10 (976~999) 24 987,
3589 11:05:33.497711 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
3590 11:05:33.504196 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
3591 11:05:33.507949 TX Bit5 (982~1007) 26 994, Bit13 (977~1000) 24 988,
3592 11:05:33.510829 TX Bit6 (981~1007) 27 994, Bit14 (976~999) 24 987,
3593 11:05:33.517185 TX Bit7 (980~1006) 27 993, Bit15 (970~993) 24 981,
3594 11:05:33.517570
3595 11:05:33.520091 Write Rank1 MR14 =0x1e
3596 11:05:33.528534
3597 11:05:33.531812 CH=1, VrefRange= 0, VrefLevel = 30
3598 11:05:33.535334 TX Bit0 (983~1008) 26 995, Bit8 (974~997) 24 985,
3599 11:05:33.538513 TX Bit1 (980~1006) 27 993, Bit9 (972~995) 24 983,
3600 11:05:33.544914 TX Bit2 (978~1006) 29 992, Bit10 (976~999) 24 987,
3601 11:05:33.548421 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
3602 11:05:33.554982 TX Bit4 (981~1007) 27 994, Bit12 (976~999) 24 987,
3603 11:05:33.557905 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
3604 11:05:33.561631 TX Bit6 (981~1007) 27 994, Bit14 (976~999) 24 987,
3605 11:05:33.567715 TX Bit7 (981~1006) 26 993, Bit15 (969~993) 25 981,
3606 11:05:33.568183
3607 11:05:33.571212 Write Rank1 MR14 =0x20
3608 11:05:33.578741
3609 11:05:33.581655 CH=1, VrefRange= 0, VrefLevel = 32
3610 11:05:33.585138 TX Bit0 (983~1008) 26 995, Bit8 (974~997) 24 985,
3611 11:05:33.588345 TX Bit1 (980~1006) 27 993, Bit9 (972~995) 24 983,
3612 11:05:33.595150 TX Bit2 (978~1006) 29 992, Bit10 (976~999) 24 987,
3613 11:05:33.598494 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
3614 11:05:33.605003 TX Bit4 (981~1007) 27 994, Bit12 (976~999) 24 987,
3615 11:05:33.608017 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
3616 11:05:33.611678 TX Bit6 (981~1007) 27 994, Bit14 (976~999) 24 987,
3617 11:05:33.618493 TX Bit7 (981~1006) 26 993, Bit15 (969~993) 25 981,
3618 11:05:33.618771
3619 11:05:33.621255 Write Rank1 MR14 =0x22
3620 11:05:33.629296
3621 11:05:33.632378 CH=1, VrefRange= 0, VrefLevel = 34
3622 11:05:33.635825 TX Bit0 (983~1008) 26 995, Bit8 (974~997) 24 985,
3623 11:05:33.638707 TX Bit1 (980~1006) 27 993, Bit9 (972~995) 24 983,
3624 11:05:33.645546 TX Bit2 (978~1006) 29 992, Bit10 (976~999) 24 987,
3625 11:05:33.648766 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
3626 11:05:33.655539 TX Bit4 (981~1007) 27 994, Bit12 (976~999) 24 987,
3627 11:05:33.658498 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
3628 11:05:33.662062 TX Bit6 (981~1007) 27 994, Bit14 (976~999) 24 987,
3629 11:05:33.668010 TX Bit7 (981~1006) 26 993, Bit15 (969~993) 25 981,
3630 11:05:33.668509
3631 11:05:33.671286 Write Rank1 MR14 =0x24
3632 11:05:33.679823
3633 11:05:33.682945 CH=1, VrefRange= 0, VrefLevel = 36
3634 11:05:33.686108 TX Bit0 (983~1008) 26 995, Bit8 (974~997) 24 985,
3635 11:05:33.689538 TX Bit1 (980~1006) 27 993, Bit9 (972~995) 24 983,
3636 11:05:33.695896 TX Bit2 (978~1006) 29 992, Bit10 (976~999) 24 987,
3637 11:05:33.699388 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
3638 11:05:33.705874 TX Bit4 (981~1007) 27 994, Bit12 (976~999) 24 987,
3639 11:05:33.708817 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
3640 11:05:33.712379 TX Bit6 (981~1007) 27 994, Bit14 (976~999) 24 987,
3641 11:05:33.718700 TX Bit7 (981~1006) 26 993, Bit15 (969~993) 25 981,
3642 11:05:33.719121
3643 11:05:33.719429
3644 11:05:33.721957 TX Vref found, early break! 381< 385
3645 11:05:33.724986 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
3646 11:05:33.728815 u1DelayCellOfst[0]=7 cells (6 PI)
3647 11:05:33.731333 u1DelayCellOfst[1]=5 cells (4 PI)
3648 11:05:33.734891 u1DelayCellOfst[2]=3 cells (3 PI)
3649 11:05:33.738218 u1DelayCellOfst[3]=0 cells (0 PI)
3650 11:05:33.741406 u1DelayCellOfst[4]=6 cells (5 PI)
3651 11:05:33.744577 u1DelayCellOfst[5]=7 cells (6 PI)
3652 11:05:33.747800 u1DelayCellOfst[6]=6 cells (5 PI)
3653 11:05:33.751278 u1DelayCellOfst[7]=5 cells (4 PI)
3654 11:05:33.754424 Byte0, DQ PI dly=989, DQM PI dly= 992
3655 11:05:33.757715 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
3656 11:05:33.757914
3657 11:05:33.761260 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
3658 11:05:33.764280
3659 11:05:33.764496 u1DelayCellOfst[8]=5 cells (4 PI)
3660 11:05:33.767404 u1DelayCellOfst[9]=2 cells (2 PI)
3661 11:05:33.770896 u1DelayCellOfst[10]=7 cells (6 PI)
3662 11:05:33.773932 u1DelayCellOfst[11]=7 cells (6 PI)
3663 11:05:33.777218 u1DelayCellOfst[12]=7 cells (6 PI)
3664 11:05:33.780709 u1DelayCellOfst[13]=7 cells (6 PI)
3665 11:05:33.784023 u1DelayCellOfst[14]=7 cells (6 PI)
3666 11:05:33.787193 u1DelayCellOfst[15]=0 cells (0 PI)
3667 11:05:33.790542 Byte1, DQ PI dly=981, DQM PI dly= 984
3668 11:05:33.793731 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
3669 11:05:33.794117
3670 11:05:33.800206 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
3671 11:05:33.800575
3672 11:05:33.800875 Write Rank1 MR14 =0x1e
3673 11:05:33.801132
3674 11:05:33.803619 Final TX Range 0 Vref 30
3675 11:05:33.804245
3676 11:05:33.810027 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3677 11:05:33.810446
3678 11:05:33.816800 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3679 11:05:33.823315 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3680 11:05:33.833193 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3681 11:05:33.833558 Write Rank1 MR3 =0xb0
3682 11:05:33.836260 DramC Write-DBI on
3683 11:05:33.836619 ==
3684 11:05:33.839346 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3685 11:05:33.842810 fsp= 1, odt_onoff= 1, Byte mode= 0
3686 11:05:33.843170 ==
3687 11:05:33.849304 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3688 11:05:33.849661
3689 11:05:33.849937 Begin, DQ Scan Range 704~768
3690 11:05:33.852252
3691 11:05:33.852336
3692 11:05:33.852402 TX Vref Scan disable
3693 11:05:33.855511 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3694 11:05:33.858585 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3695 11:05:33.861959 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3696 11:05:33.865372 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3697 11:05:33.868516 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3698 11:05:33.874977 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3699 11:05:33.878288 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3700 11:05:33.881640 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3701 11:05:33.884905 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3702 11:05:33.888298 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3703 11:05:33.891476 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3704 11:05:33.894767 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3705 11:05:33.897911 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3706 11:05:33.901363 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3707 11:05:33.904421 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3708 11:05:33.907779 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3709 11:05:33.911073 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3710 11:05:33.914709 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3711 11:05:33.917748 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3712 11:05:33.924202 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3713 11:05:33.927513 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3714 11:05:33.934039 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3715 11:05:33.937478 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3716 11:05:33.940736 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3717 11:05:33.944129 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3718 11:05:33.947275 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3719 11:05:33.950471 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3720 11:05:33.953798 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3721 11:05:33.957184 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3722 11:05:33.960377 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3723 11:05:33.963575 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3724 11:05:33.967052 Byte0, DQ PI dly=738, DQM PI dly= 738
3725 11:05:33.973489 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 34)
3726 11:05:33.973822
3727 11:05:33.977019 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 34)
3728 11:05:33.977474
3729 11:05:33.980219 Byte1, DQ PI dly=728, DQM PI dly= 728
3730 11:05:33.983446 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
3731 11:05:33.983809
3732 11:05:33.990112 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
3733 11:05:33.990482
3734 11:05:33.996504 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3735 11:05:34.003140 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3736 11:05:34.009848 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3737 11:05:34.012848 Write Rank1 MR3 =0x30
3738 11:05:34.013207 DramC Write-DBI off
3739 11:05:34.013486
3740 11:05:34.016535 [DATLAT]
3741 11:05:34.019438 Freq=1600, CH1 RK1, use_rxtx_scan=0
3742 11:05:34.019898
3743 11:05:34.020182 DATLAT Default: 0x10
3744 11:05:34.022566 7, 0xFFFF, sum=0
3745 11:05:34.022928 8, 0xFFFF, sum=0
3746 11:05:34.026120 9, 0xFFFF, sum=0
3747 11:05:34.026483 10, 0xFFFF, sum=0
3748 11:05:34.029347 11, 0xFFFF, sum=0
3749 11:05:34.029732 12, 0xFFFF, sum=0
3750 11:05:34.032365 13, 0xFFFF, sum=0
3751 11:05:34.032726 14, 0x0, sum=1
3752 11:05:34.033005 15, 0x0, sum=2
3753 11:05:34.035922 16, 0x0, sum=3
3754 11:05:34.036401 17, 0x0, sum=4
3755 11:05:34.042645 pattern=2 first_step=14 total pass=5 best_step=16
3756 11:05:34.043002 ==
3757 11:05:34.045780 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3758 11:05:34.048830 fsp= 1, odt_onoff= 1, Byte mode= 0
3759 11:05:34.049188 ==
3760 11:05:34.055431 Start DQ dly to find pass range UseTestEngine =1
3761 11:05:34.058711 x-axis: bit #, y-axis: DQ dly (-127~63)
3762 11:05:34.059042 RX Vref Scan = 0
3763 11:05:34.062157 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3764 11:05:34.065533 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3765 11:05:34.068740 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3766 11:05:34.071931 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3767 11:05:34.075153 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3768 11:05:34.075635 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3769 11:05:34.078495 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3770 11:05:34.081943 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3771 11:05:34.085123 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3772 11:05:34.088238 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3773 11:05:34.091487 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3774 11:05:34.094964 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3775 11:05:34.098180 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3776 11:05:34.101338 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3777 11:05:34.104683 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3778 11:05:34.105050 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3779 11:05:34.107981 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3780 11:05:34.111382 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3781 11:05:34.114575 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3782 11:05:34.117718 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3783 11:05:34.121180 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3784 11:05:34.124510 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3785 11:05:34.127800 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3786 11:05:34.128165 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3787 11:05:34.130783 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3788 11:05:34.134290 -1, [0] xxxoxxxx ooxxxxxo [MSB]
3789 11:05:34.137477 0, [0] xxxoxxxx ooxxxxxo [MSB]
3790 11:05:34.140746 1, [0] xxxoxxxx ooxxxxxo [MSB]
3791 11:05:34.144181 2, [0] xxxoxxxx ooxxxxxo [MSB]
3792 11:05:34.144651 3, [0] xoooxxxo oooooxxo [MSB]
3793 11:05:34.147508 4, [0] oooooxxo oooooooo [MSB]
3794 11:05:34.150428 5, [0] ooooooxo oooooooo [MSB]
3795 11:05:34.154756 32, [0] oooooooo ooooooox [MSB]
3796 11:05:34.158067 33, [0] oooooooo ooooooox [MSB]
3797 11:05:34.161452 34, [0] oooxoooo oxooooox [MSB]
3798 11:05:34.164738 35, [0] ooxxoooo oxooooox [MSB]
3799 11:05:34.168120 36, [0] ooxxoooo xxooooox [MSB]
3800 11:05:34.171551 37, [0] ooxxoooo xxooooox [MSB]
3801 11:05:34.174416 38, [0] ooxxoooo xxooxoox [MSB]
3802 11:05:34.174736 39, [0] ooxxooox xxxxxoox [MSB]
3803 11:05:34.177723 40, [0] oxxxxoox xxxxxxox [MSB]
3804 11:05:34.181009 41, [0] xxxxxxxx xxxxxxxx [MSB]
3805 11:05:34.184335 iDelay=41, Bit 0, Center 22 (4 ~ 40) 37
3806 11:05:34.187562 iDelay=41, Bit 1, Center 21 (3 ~ 39) 37
3807 11:05:34.190693 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32
3808 11:05:34.197461 iDelay=41, Bit 3, Center 15 (-2 ~ 33) 36
3809 11:05:34.200701 iDelay=41, Bit 4, Center 21 (4 ~ 39) 36
3810 11:05:34.203874 iDelay=41, Bit 5, Center 22 (5 ~ 40) 36
3811 11:05:34.207131 iDelay=41, Bit 6, Center 23 (6 ~ 40) 35
3812 11:05:34.210559 iDelay=41, Bit 7, Center 20 (3 ~ 38) 36
3813 11:05:34.213895 iDelay=41, Bit 8, Center 17 (-1 ~ 35) 37
3814 11:05:34.217155 iDelay=41, Bit 9, Center 15 (-2 ~ 33) 36
3815 11:05:34.220334 iDelay=41, Bit 10, Center 20 (3 ~ 38) 36
3816 11:05:34.223633 iDelay=41, Bit 11, Center 20 (3 ~ 38) 36
3817 11:05:34.226818 iDelay=41, Bit 12, Center 20 (3 ~ 37) 35
3818 11:05:34.230393 iDelay=41, Bit 13, Center 21 (4 ~ 39) 36
3819 11:05:34.236669 iDelay=41, Bit 14, Center 22 (4 ~ 40) 37
3820 11:05:34.240063 iDelay=41, Bit 15, Center 13 (-4 ~ 31) 36
3821 11:05:34.240396 ==
3822 11:05:34.243392 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3823 11:05:34.246991 fsp= 1, odt_onoff= 1, Byte mode= 0
3824 11:05:34.247502 ==
3825 11:05:34.250032 DQS Delay:
3826 11:05:34.250479 DQS0 = 0, DQS1 = 0
3827 11:05:34.253130 DQM Delay:
3828 11:05:34.253601 DQM0 = 20, DQM1 = 18
3829 11:05:34.254048 DQ Delay:
3830 11:05:34.256239 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =15
3831 11:05:34.259594 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3832 11:05:34.262831 DQ8 =17, DQ9 =15, DQ10 =20, DQ11 =20
3833 11:05:34.266223 DQ12 =20, DQ13 =21, DQ14 =22, DQ15 =13
3834 11:05:34.266547
3835 11:05:34.266793
3836 11:05:34.267025
3837 11:05:34.269759 [DramC_TX_OE_Calibration] TA2
3838 11:05:34.272874 Original DQ_B0 (3 6) =30, OEN = 27
3839 11:05:34.276288 Original DQ_B1 (3 6) =30, OEN = 27
3840 11:05:34.279070 23, 0x0, End_B0=23 End_B1=23
3841 11:05:34.282413 24, 0x0, End_B0=24 End_B1=24
3842 11:05:34.285802 25, 0x0, End_B0=25 End_B1=25
3843 11:05:34.286170 26, 0x0, End_B0=26 End_B1=26
3844 11:05:34.289136 27, 0x0, End_B0=27 End_B1=27
3845 11:05:34.292305 28, 0x0, End_B0=28 End_B1=28
3846 11:05:34.295658 29, 0x0, End_B0=29 End_B1=29
3847 11:05:34.298840 30, 0x0, End_B0=30 End_B1=30
3848 11:05:34.299173 31, 0xFFFF, End_B0=30 End_B1=30
3849 11:05:34.305558 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3850 11:05:34.311947 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3851 11:05:34.312305
3852 11:05:34.312615
3853 11:05:34.313010 Write Rank1 MR23 =0x3f
3854 11:05:34.315124 [DQSOSC]
3855 11:05:34.321838 [DQSOSCAuto] RK1, (LSB)MR18= 0xbbbb, (MSB)MR19= 0x202, tDQSOscB0 = 450 ps tDQSOscB1 = 450 ps
3856 11:05:34.328365 CH1_RK1: MR19=0x202, MR18=0xBBBB, DQSOSC=450, MR23=63, INC=12, DEC=18
3857 11:05:34.331482 Write Rank1 MR23 =0x3f
3858 11:05:34.331849 [DQSOSC]
3859 11:05:34.338199 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0x202, tDQSOscB0 = 451 ps tDQSOscB1 = 451 ps
3860 11:05:34.341460 CH1 RK1: MR19=202, MR18=BABA
3861 11:05:34.344701 [RxdqsGatingPostProcess] freq 1600
3862 11:05:34.351116 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3863 11:05:34.351605 Rank: 0
3864 11:05:34.354616 best DQS0 dly(2T, 0.5T) = (2, 6)
3865 11:05:34.357504 best DQS1 dly(2T, 0.5T) = (2, 6)
3866 11:05:34.360988 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3867 11:05:34.364374 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3868 11:05:34.364747 Rank: 1
3869 11:05:34.367441 best DQS0 dly(2T, 0.5T) = (2, 6)
3870 11:05:34.370865 best DQS1 dly(2T, 0.5T) = (2, 6)
3871 11:05:34.373878 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3872 11:05:34.377280 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3873 11:05:34.380496 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3874 11:05:34.384021 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3875 11:05:34.390283 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3876 11:05:34.390610
3877 11:05:34.390896
3878 11:05:34.393829 [Calibration Summary] Freqency 1600
3879 11:05:34.394228 CH 0, Rank 0
3880 11:05:34.397170 All Pass.
3881 11:05:34.397496
3882 11:05:34.397787 CH 0, Rank 1
3883 11:05:34.398034 All Pass.
3884 11:05:34.398259
3885 11:05:34.400554 CH 1, Rank 0
3886 11:05:34.401005 All Pass.
3887 11:05:34.401275
3888 11:05:34.401546 CH 1, Rank 1
3889 11:05:34.403615 All Pass.
3890 11:05:34.403989
3891 11:05:34.410347 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3892 11:05:34.416697 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3893 11:05:34.423049 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3894 11:05:34.426367 Write Rank0 MR3 =0xb0
3895 11:05:34.433266 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3896 11:05:34.439806 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3897 11:05:34.446021 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3898 11:05:34.449378 Write Rank1 MR3 =0xb0
3899 11:05:34.452665 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3900 11:05:34.462473 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3901 11:05:34.469186 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3902 11:05:34.469556 Write Rank0 MR3 =0xb0
3903 11:05:34.475566 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3904 11:05:34.482324 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3905 11:05:34.492032 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3906 11:05:34.492404 Write Rank1 MR3 =0xb0
3907 11:05:34.495224 DramC Write-DBI on
3908 11:05:34.498311 [GetDramInforAfterCalByMRR] Vendor 6.
3909 11:05:34.501862 [GetDramInforAfterCalByMRR] Revision 505.
3910 11:05:34.502316 MR8 1111
3911 11:05:34.508462 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3912 11:05:34.508823 MR8 1111
3913 11:05:34.511376 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3914 11:05:34.514809 MR8 1111
3915 11:05:34.518065 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3916 11:05:34.518503 MR8 1111
3917 11:05:34.524676 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3918 11:05:34.534564 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3919 11:05:34.534947 Write Rank0 MR13 =0xd0
3920 11:05:34.537736 Write Rank1 MR13 =0xd0
3921 11:05:34.538163 Write Rank0 MR13 =0xd0
3922 11:05:34.541134 Write Rank1 MR13 =0xd0
3923 11:05:34.544491 Save calibration result to emmc
3924 11:05:34.544819
3925 11:05:34.545121
3926 11:05:34.547677 [DramcModeReg_Check] Freq_1600, FSP_1
3927 11:05:34.551274 FSP_1, CH_0, RK0
3928 11:05:34.551639 Write Rank0 MR13 =0xd8
3929 11:05:34.554182 MR12 = 0x5c (global = 0x5c) match
3930 11:05:34.557436 MR14 = 0x1e (global = 0x1e) match
3931 11:05:34.560765 FSP_1, CH_0, RK1
3932 11:05:34.561093 Write Rank1 MR13 =0xd8
3933 11:05:34.564021 MR12 = 0x60 (global = 0x60) match
3934 11:05:34.567442 MR14 = 0x1e (global = 0x1e) match
3935 11:05:34.570690 FSP_1, CH_1, RK0
3936 11:05:34.571063 Write Rank0 MR13 =0xd8
3937 11:05:34.573723 MR12 = 0x5c (global = 0x5c) match
3938 11:05:34.577084 MR14 = 0x20 (global = 0x20) match
3939 11:05:34.580323 FSP_1, CH_1, RK1
3940 11:05:34.580651 Write Rank1 MR13 =0xd8
3941 11:05:34.583614 MR12 = 0x5c (global = 0x5c) match
3942 11:05:34.587270 MR14 = 0x1e (global = 0x1e) match
3943 11:05:34.587657
3944 11:05:34.593702 [MEM_TEST] 02: After DFS, before run time config
3945 11:05:34.603509 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3946 11:05:34.603886
3947 11:05:34.604189 [TA2_TEST]
3948 11:05:34.604484 === TA2 HW
3949 11:05:34.606549 TA2 PAT: XTALK
3950 11:05:34.609858 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3951 11:05:34.616462 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3952 11:05:34.619779 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3953 11:05:34.626412 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3954 11:05:34.626739
3955 11:05:34.626991
3956 11:05:34.627224 Settings after calibration
3957 11:05:34.627475
3958 11:05:34.629416 [DramcRunTimeConfig]
3959 11:05:34.632606 TransferPLLToSPMControl - MODE SW PHYPLL
3960 11:05:34.635865 TX_TRACKING: ON
3961 11:05:34.636247 RX_TRACKING: ON
3962 11:05:34.636504 HW_GATING: ON
3963 11:05:34.639530 HW_GATING DBG: OFF
3964 11:05:34.639877 ddr_geometry:1
3965 11:05:34.642760 ddr_geometry:1
3966 11:05:34.643137 ddr_geometry:1
3967 11:05:34.645787 ddr_geometry:1
3968 11:05:34.646196 ddr_geometry:1
3969 11:05:34.646560 ddr_geometry:1
3970 11:05:34.649297 ddr_geometry:1
3971 11:05:34.649626 ddr_geometry:1
3972 11:05:34.652414 High Freq DUMMY_READ_FOR_TRACKING: ON
3973 11:05:34.655688 ZQCS_ENABLE_LP4: OFF
3974 11:05:34.659093 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3975 11:05:34.662422 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3976 11:05:34.662749 SPM_CONTROL_AFTERK: ON
3977 11:05:34.665542 IMPEDANCE_TRACKING: ON
3978 11:05:34.668818 TEMP_SENSOR: ON
3979 11:05:34.669209 PER_BANK_REFRESH: ON
3980 11:05:34.671711 HW_SAVE_FOR_SR: ON
3981 11:05:34.675168 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3982 11:05:34.678355 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3983 11:05:34.681821 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3984 11:05:34.681910 Read ODT Tracking: ON
3985 11:05:34.684898 =========================
3986 11:05:34.684973
3987 11:05:34.685043 [TA2_TEST]
3988 11:05:34.688352 === TA2 HW
3989 11:05:34.691659 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3990 11:05:34.698093 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3991 11:05:34.701245 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3992 11:05:34.707764 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3993 11:05:34.707853
3994 11:05:34.710777 [MEM_TEST] 03: After run time config
3995 11:05:34.720930 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3996 11:05:34.723828 [complex_mem_test] start addr:0x40024000, len:131072
3997 11:05:34.928728 1st complex R/W mem test pass
3998 11:05:34.934984 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3999 11:05:34.938277 sync preloader write leveling
4000 11:05:34.941270 sync preloader cbt_mr12
4001 11:05:34.944572 sync preloader cbt_clk_dly
4002 11:05:34.944657 sync preloader cbt_cmd_dly
4003 11:05:34.947809 sync preloader cbt_cs
4004 11:05:34.951303 sync preloader cbt_ca_perbit_delay
4005 11:05:34.954367 sync preloader clk_delay
4006 11:05:34.954487 sync preloader dqs_delay
4007 11:05:34.957903 sync preloader u1Gating2T_Save
4008 11:05:34.960985 sync preloader u1Gating05T_Save
4009 11:05:34.964209 sync preloader u1Gatingfine_tune_Save
4010 11:05:34.967427 sync preloader u1Gatingucpass_count_Save
4011 11:05:34.970806 sync preloader u1TxWindowPerbitVref_Save
4012 11:05:34.974127 sync preloader u1TxCenter_min_Save
4013 11:05:34.977556 sync preloader u1TxCenter_max_Save
4014 11:05:34.980685 sync preloader u1Txwin_center_Save
4015 11:05:34.983987 sync preloader u1Txfirst_pass_Save
4016 11:05:34.987339 sync preloader u1Txlast_pass_Save
4017 11:05:34.990545 sync preloader u1RxDatlat_Save
4018 11:05:34.994013 sync preloader u1RxWinPerbitVref_Save
4019 11:05:34.997179 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4020 11:05:35.000555 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4021 11:05:35.003874 sync preloader delay_cell_unit
4022 11:05:35.010388 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4023 11:05:35.013507 sync preloader write leveling
4024 11:05:35.016929 sync preloader cbt_mr12
4025 11:05:35.017419 sync preloader cbt_clk_dly
4026 11:05:35.020153 sync preloader cbt_cmd_dly
4027 11:05:35.023697 sync preloader cbt_cs
4028 11:05:35.026715 sync preloader cbt_ca_perbit_delay
4029 11:05:35.027166 sync preloader clk_delay
4030 11:05:35.030092 sync preloader dqs_delay
4031 11:05:35.033228 sync preloader u1Gating2T_Save
4032 11:05:35.036542 sync preloader u1Gating05T_Save
4033 11:05:35.039758 sync preloader u1Gatingfine_tune_Save
4034 11:05:35.043043 sync preloader u1Gatingucpass_count_Save
4035 11:05:35.046363 sync preloader u1TxWindowPerbitVref_Save
4036 11:05:35.049757 sync preloader u1TxCenter_min_Save
4037 11:05:35.053286 sync preloader u1TxCenter_max_Save
4038 11:05:35.056213 sync preloader u1Txwin_center_Save
4039 11:05:35.059588 sync preloader u1Txfirst_pass_Save
4040 11:05:35.062702 sync preloader u1Txlast_pass_Save
4041 11:05:35.065905 sync preloader u1RxDatlat_Save
4042 11:05:35.069246 sync preloader u1RxWinPerbitVref_Save
4043 11:05:35.072684 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4044 11:05:35.076187 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4045 11:05:35.079395 sync preloader delay_cell_unit
4046 11:05:35.085681 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4047 11:05:35.088789 sync preloader write leveling
4048 11:05:35.092493 sync preloader cbt_mr12
4049 11:05:35.092886 sync preloader cbt_clk_dly
4050 11:05:35.095327 sync preloader cbt_cmd_dly
4051 11:05:35.098762 sync preloader cbt_cs
4052 11:05:35.101899 sync preloader cbt_ca_perbit_delay
4053 11:05:35.102382 sync preloader clk_delay
4054 11:05:35.105180 sync preloader dqs_delay
4055 11:05:35.108515 sync preloader u1Gating2T_Save
4056 11:05:35.112067 sync preloader u1Gating05T_Save
4057 11:05:35.115267 sync preloader u1Gatingfine_tune_Save
4058 11:05:35.118442 sync preloader u1Gatingucpass_count_Save
4059 11:05:35.121882 sync preloader u1TxWindowPerbitVref_Save
4060 11:05:35.125021 sync preloader u1TxCenter_min_Save
4061 11:05:35.128265 sync preloader u1TxCenter_max_Save
4062 11:05:35.131429 sync preloader u1Txwin_center_Save
4063 11:05:35.134885 sync preloader u1Txfirst_pass_Save
4064 11:05:35.137914 sync preloader u1Txlast_pass_Save
4065 11:05:35.138002 sync preloader u1RxDatlat_Save
4066 11:05:35.140920 sync preloader u1RxWinPerbitVref_Save
4067 11:05:35.147662 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4068 11:05:35.151033 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4069 11:05:35.154444 sync preloader delay_cell_unit
4070 11:05:35.157543 just_for_test_dump_coreboot_params dump all params
4071 11:05:35.160603 dump source = 0x0
4072 11:05:35.160717 dump params frequency:1600
4073 11:05:35.163889 dump params rank number:2
4074 11:05:35.164011
4075 11:05:35.167588 dump params write leveling
4076 11:05:35.170671 write leveling[0][0][0] = 0x20
4077 11:05:35.174277 write leveling[0][0][1] = 0x1b
4078 11:05:35.174818 write leveling[0][1][0] = 0x1e
4079 11:05:35.177162 write leveling[0][1][1] = 0x19
4080 11:05:35.180625 write leveling[1][0][0] = 0x25
4081 11:05:35.183951 write leveling[1][0][1] = 0x1d
4082 11:05:35.187279 write leveling[1][1][0] = 0x24
4083 11:05:35.190613 write leveling[1][1][1] = 0x1d
4084 11:05:35.191199 dump params cbt_cs
4085 11:05:35.193726 cbt_cs[0][0] = 0x6
4086 11:05:35.194181 cbt_cs[0][1] = 0x6
4087 11:05:35.197102 cbt_cs[1][0] = 0xa
4088 11:05:35.197460 cbt_cs[1][1] = 0xa
4089 11:05:35.200168 dump params cbt_mr12
4090 11:05:35.203530 cbt_mr12[0][0] = 0x1c
4091 11:05:35.203929 cbt_mr12[0][1] = 0x20
4092 11:05:35.207006 cbt_mr12[1][0] = 0x1c
4093 11:05:35.207670 cbt_mr12[1][1] = 0x1c
4094 11:05:35.210110 dump params tx window
4095 11:05:35.213483 tx_center_min[0][0][0] = 985
4096 11:05:35.216637 tx_center_max[0][0][0] = 990
4097 11:05:35.216969 tx_center_min[0][0][1] = 979
4098 11:05:35.219867 tx_center_max[0][0][1] = 986
4099 11:05:35.223269 tx_center_min[0][1][0] = 984
4100 11:05:35.226417 tx_center_max[0][1][0] = 990
4101 11:05:35.229607 tx_center_min[0][1][1] = 979
4102 11:05:35.229984 tx_center_max[0][1][1] = 987
4103 11:05:35.233210 tx_center_min[1][0][0] = 989
4104 11:05:35.236170 tx_center_max[1][0][0] = 995
4105 11:05:35.240107 tx_center_min[1][0][1] = 981
4106 11:05:35.243450 tx_center_max[1][0][1] = 987
4107 11:05:35.243897 tx_center_min[1][1][0] = 989
4108 11:05:35.246178 tx_center_max[1][1][0] = 995
4109 11:05:35.249486 tx_center_min[1][1][1] = 981
4110 11:05:35.252843 tx_center_max[1][1][1] = 987
4111 11:05:35.253203 dump params tx window
4112 11:05:35.256092 tx_win_center[0][0][0] = 990
4113 11:05:35.259016 tx_first_pass[0][0][0] = 979
4114 11:05:35.262386 tx_last_pass[0][0][0] = 1002
4115 11:05:35.265647 tx_win_center[0][0][1] = 990
4116 11:05:35.266008 tx_first_pass[0][0][1] = 978
4117 11:05:35.269327 tx_last_pass[0][0][1] = 1002
4118 11:05:35.272307 tx_win_center[0][0][2] = 990
4119 11:05:35.275349 tx_first_pass[0][0][2] = 978
4120 11:05:35.278711 tx_last_pass[0][0][2] = 1002
4121 11:05:35.279153 tx_win_center[0][0][3] = 985
4122 11:05:35.282129 tx_first_pass[0][0][3] = 974
4123 11:05:35.285429 tx_last_pass[0][0][3] = 997
4124 11:05:35.288676 tx_win_center[0][0][4] = 989
4125 11:05:35.291878 tx_first_pass[0][0][4] = 977
4126 11:05:35.292273 tx_last_pass[0][0][4] = 1001
4127 11:05:35.295254 tx_win_center[0][0][5] = 987
4128 11:05:35.298529 tx_first_pass[0][0][5] = 976
4129 11:05:35.301748 tx_last_pass[0][0][5] = 999
4130 11:05:35.305166 tx_win_center[0][0][6] = 988
4131 11:05:35.305551 tx_first_pass[0][0][6] = 977
4132 11:05:35.308203 tx_last_pass[0][0][6] = 1000
4133 11:05:35.311443 tx_win_center[0][0][7] = 990
4134 11:05:35.314932 tx_first_pass[0][0][7] = 978
4135 11:05:35.318151 tx_last_pass[0][0][7] = 1002
4136 11:05:35.318525 tx_win_center[0][0][8] = 979
4137 11:05:35.321496 tx_first_pass[0][0][8] = 968
4138 11:05:35.324416 tx_last_pass[0][0][8] = 990
4139 11:05:35.327758 tx_win_center[0][0][9] = 980
4140 11:05:35.328102 tx_first_pass[0][0][9] = 969
4141 11:05:35.331149 tx_last_pass[0][0][9] = 992
4142 11:05:35.334620 tx_win_center[0][0][10] = 986
4143 11:05:35.337784 tx_first_pass[0][0][10] = 974
4144 11:05:35.341012 tx_last_pass[0][0][10] = 998
4145 11:05:35.344373 tx_win_center[0][0][11] = 979
4146 11:05:35.344748 tx_first_pass[0][0][11] = 968
4147 11:05:35.347584 tx_last_pass[0][0][11] = 991
4148 11:05:35.350828 tx_win_center[0][0][12] = 981
4149 11:05:35.354276 tx_first_pass[0][0][12] = 970
4150 11:05:35.357556 tx_last_pass[0][0][12] = 993
4151 11:05:35.357914 tx_win_center[0][0][13] = 981
4152 11:05:35.360761 tx_first_pass[0][0][13] = 969
4153 11:05:35.364016 tx_last_pass[0][0][13] = 993
4154 11:05:35.367145 tx_win_center[0][0][14] = 983
4155 11:05:35.370288 tx_first_pass[0][0][14] = 970
4156 11:05:35.373443 tx_last_pass[0][0][14] = 996
4157 11:05:35.373797 tx_win_center[0][0][15] = 986
4158 11:05:35.376843 tx_first_pass[0][0][15] = 974
4159 11:05:35.380212 tx_last_pass[0][0][15] = 998
4160 11:05:35.383398 tx_win_center[0][1][0] = 990
4161 11:05:35.386899 tx_first_pass[0][1][0] = 978
4162 11:05:35.387251 tx_last_pass[0][1][0] = 1003
4163 11:05:35.390034 tx_win_center[0][1][1] = 990
4164 11:05:35.393311 tx_first_pass[0][1][1] = 978
4165 11:05:35.396607 tx_last_pass[0][1][1] = 1002
4166 11:05:35.399917 tx_win_center[0][1][2] = 990
4167 11:05:35.400307 tx_first_pass[0][1][2] = 978
4168 11:05:35.403135 tx_last_pass[0][1][2] = 1002
4169 11:05:35.406440 tx_win_center[0][1][3] = 984
4170 11:05:35.409504 tx_first_pass[0][1][3] = 972
4171 11:05:35.413104 tx_last_pass[0][1][3] = 997
4172 11:05:35.413462 tx_win_center[0][1][4] = 990
4173 11:05:35.416314 tx_first_pass[0][1][4] = 978
4174 11:05:35.419358 tx_last_pass[0][1][4] = 1002
4175 11:05:35.422892 tx_win_center[0][1][5] = 987
4176 11:05:35.426172 tx_first_pass[0][1][5] = 975
4177 11:05:35.426570 tx_last_pass[0][1][5] = 999
4178 11:05:35.429475 tx_win_center[0][1][6] = 988
4179 11:05:35.432979 tx_first_pass[0][1][6] = 976
4180 11:05:35.435821 tx_last_pass[0][1][6] = 1000
4181 11:05:35.436216 tx_win_center[0][1][7] = 990
4182 11:05:35.438791 tx_first_pass[0][1][7] = 978
4183 11:05:35.442129 tx_last_pass[0][1][7] = 1003
4184 11:05:35.445631 tx_win_center[0][1][8] = 979
4185 11:05:35.448831 tx_first_pass[0][1][8] = 968
4186 11:05:35.448962 tx_last_pass[0][1][8] = 991
4187 11:05:35.451889 tx_win_center[0][1][9] = 982
4188 11:05:35.455365 tx_first_pass[0][1][9] = 970
4189 11:05:35.458661 tx_last_pass[0][1][9] = 994
4190 11:05:35.462487 tx_win_center[0][1][10] = 987
4191 11:05:35.462562 tx_first_pass[0][1][10] = 975
4192 11:05:35.465111 tx_last_pass[0][1][10] = 999
4193 11:05:35.468404 tx_win_center[0][1][11] = 980
4194 11:05:35.471414 tx_first_pass[0][1][11] = 969
4195 11:05:35.474727 tx_last_pass[0][1][11] = 992
4196 11:05:35.477973 tx_win_center[0][1][12] = 983
4197 11:05:35.478057 tx_first_pass[0][1][12] = 971
4198 11:05:35.481564 tx_last_pass[0][1][12] = 995
4199 11:05:35.484507 tx_win_center[0][1][13] = 982
4200 11:05:35.488191 tx_first_pass[0][1][13] = 970
4201 11:05:35.491381 tx_last_pass[0][1][13] = 994
4202 11:05:35.491464 tx_win_center[0][1][14] = 984
4203 11:05:35.494400 tx_first_pass[0][1][14] = 972
4204 11:05:35.497955 tx_last_pass[0][1][14] = 997
4205 11:05:35.501082 tx_win_center[0][1][15] = 986
4206 11:05:35.504347 tx_first_pass[0][1][15] = 975
4207 11:05:35.507598 tx_last_pass[0][1][15] = 998
4208 11:05:35.507675 tx_win_center[1][0][0] = 995
4209 11:05:35.510900 tx_first_pass[1][0][0] = 982
4210 11:05:35.514306 tx_last_pass[1][0][0] = 1008
4211 11:05:35.517511 tx_win_center[1][0][1] = 994
4212 11:05:35.520438 tx_first_pass[1][0][1] = 982
4213 11:05:35.520527 tx_last_pass[1][0][1] = 1007
4214 11:05:35.523894 tx_win_center[1][0][2] = 992
4215 11:05:35.527108 tx_first_pass[1][0][2] = 979
4216 11:05:35.530678 tx_last_pass[1][0][2] = 1005
4217 11:05:35.530782 tx_win_center[1][0][3] = 989
4218 11:05:35.533645 tx_first_pass[1][0][3] = 977
4219 11:05:35.536977 tx_last_pass[1][0][3] = 1002
4220 11:05:35.540455 tx_win_center[1][0][4] = 994
4221 11:05:35.543723 tx_first_pass[1][0][4] = 982
4222 11:05:35.543836 tx_last_pass[1][0][4] = 1006
4223 11:05:35.546701 tx_win_center[1][0][5] = 994
4224 11:05:35.550018 tx_first_pass[1][0][5] = 982
4225 11:05:35.553171 tx_last_pass[1][0][5] = 1007
4226 11:05:35.556622 tx_win_center[1][0][6] = 994
4227 11:05:35.556809 tx_first_pass[1][0][6] = 981
4228 11:05:35.560141 tx_last_pass[1][0][6] = 1007
4229 11:05:35.563170 tx_win_center[1][0][7] = 993
4230 11:05:35.566554 tx_first_pass[1][0][7] = 981
4231 11:05:35.569857 tx_last_pass[1][0][7] = 1006
4232 11:05:35.569935 tx_win_center[1][0][8] = 984
4233 11:05:35.573347 tx_first_pass[1][0][8] = 973
4234 11:05:35.576177 tx_last_pass[1][0][8] = 996
4235 11:05:35.579480 tx_win_center[1][0][9] = 982
4236 11:05:35.582608 tx_first_pass[1][0][9] = 970
4237 11:05:35.582728 tx_last_pass[1][0][9] = 994
4238 11:05:35.586382 tx_win_center[1][0][10] = 986
4239 11:05:35.589816 tx_first_pass[1][0][10] = 975
4240 11:05:35.593088 tx_last_pass[1][0][10] = 998
4241 11:05:35.596370 tx_win_center[1][0][11] = 987
4242 11:05:35.599826 tx_first_pass[1][0][11] = 976
4243 11:05:35.600069 tx_last_pass[1][0][11] = 999
4244 11:05:35.602427 tx_win_center[1][0][12] = 987
4245 11:05:35.605755 tx_first_pass[1][0][12] = 975
4246 11:05:35.608996 tx_last_pass[1][0][12] = 999
4247 11:05:35.612495 tx_win_center[1][0][13] = 987
4248 11:05:35.612746 tx_first_pass[1][0][13] = 976
4249 11:05:35.615901 tx_last_pass[1][0][13] = 999
4250 11:05:35.619340 tx_win_center[1][0][14] = 987
4251 11:05:35.622466 tx_first_pass[1][0][14] = 975
4252 11:05:35.625784 tx_last_pass[1][0][14] = 999
4253 11:05:35.626035 tx_win_center[1][0][15] = 981
4254 11:05:35.629347 tx_first_pass[1][0][15] = 969
4255 11:05:35.632347 tx_last_pass[1][0][15] = 993
4256 11:05:35.635844 tx_win_center[1][1][0] = 995
4257 11:05:35.638934 tx_first_pass[1][1][0] = 983
4258 11:05:35.639391 tx_last_pass[1][1][0] = 1008
4259 11:05:35.642237 tx_win_center[1][1][1] = 993
4260 11:05:35.645649 tx_first_pass[1][1][1] = 980
4261 11:05:35.648736 tx_last_pass[1][1][1] = 1006
4262 11:05:35.651860 tx_win_center[1][1][2] = 992
4263 11:05:35.652242 tx_first_pass[1][1][2] = 978
4264 11:05:35.655516 tx_last_pass[1][1][2] = 1006
4265 11:05:35.658526 tx_win_center[1][1][3] = 989
4266 11:05:35.661835 tx_first_pass[1][1][3] = 977
4267 11:05:35.664929 tx_last_pass[1][1][3] = 1002
4268 11:05:35.665312 tx_win_center[1][1][4] = 994
4269 11:05:35.668356 tx_first_pass[1][1][4] = 981
4270 11:05:35.671883 tx_last_pass[1][1][4] = 1007
4271 11:05:35.675070 tx_win_center[1][1][5] = 995
4272 11:05:35.678591 tx_first_pass[1][1][5] = 983
4273 11:05:35.679047 tx_last_pass[1][1][5] = 1007
4274 11:05:35.681229 tx_win_center[1][1][6] = 994
4275 11:05:35.684726 tx_first_pass[1][1][6] = 981
4276 11:05:35.687765 tx_last_pass[1][1][6] = 1007
4277 11:05:35.691160 tx_win_center[1][1][7] = 993
4278 11:05:35.691644 tx_first_pass[1][1][7] = 981
4279 11:05:35.694403 tx_last_pass[1][1][7] = 1006
4280 11:05:35.697547 tx_win_center[1][1][8] = 985
4281 11:05:35.700727 tx_first_pass[1][1][8] = 974
4282 11:05:35.704282 tx_last_pass[1][1][8] = 997
4283 11:05:35.704770 tx_win_center[1][1][9] = 983
4284 11:05:35.707179 tx_first_pass[1][1][9] = 972
4285 11:05:35.710725 tx_last_pass[1][1][9] = 995
4286 11:05:35.714043 tx_win_center[1][1][10] = 987
4287 11:05:35.717140 tx_first_pass[1][1][10] = 976
4288 11:05:35.717548 tx_last_pass[1][1][10] = 999
4289 11:05:35.720421 tx_win_center[1][1][11] = 987
4290 11:05:35.724034 tx_first_pass[1][1][11] = 976
4291 11:05:35.727171 tx_last_pass[1][1][11] = 999
4292 11:05:35.730834 tx_win_center[1][1][12] = 987
4293 11:05:35.733824 tx_first_pass[1][1][12] = 976
4294 11:05:35.734195 tx_last_pass[1][1][12] = 999
4295 11:05:35.736429 tx_win_center[1][1][13] = 987
4296 11:05:35.739628 tx_first_pass[1][1][13] = 976
4297 11:05:35.742964 tx_last_pass[1][1][13] = 999
4298 11:05:35.746429 tx_win_center[1][1][14] = 987
4299 11:05:35.746495 tx_first_pass[1][1][14] = 976
4300 11:05:35.749941 tx_last_pass[1][1][14] = 999
4301 11:05:35.752770 tx_win_center[1][1][15] = 981
4302 11:05:35.756302 tx_first_pass[1][1][15] = 969
4303 11:05:35.759515 tx_last_pass[1][1][15] = 993
4304 11:05:35.759600 dump params rx window
4305 11:05:35.762780 rx_firspass[0][0][0] = 7
4306 11:05:35.765918 rx_lastpass[0][0][0] = 36
4307 11:05:35.766002 rx_firspass[0][0][1] = 8
4308 11:05:35.769181 rx_lastpass[0][0][1] = 36
4309 11:05:35.772496 rx_firspass[0][0][2] = 5
4310 11:05:35.775756 rx_lastpass[0][0][2] = 39
4311 11:05:35.775841 rx_firspass[0][0][3] = -3
4312 11:05:35.779213 rx_lastpass[0][0][3] = 30
4313 11:05:35.782530 rx_firspass[0][0][4] = 6
4314 11:05:35.782615 rx_lastpass[0][0][4] = 36
4315 11:05:35.785630 rx_firspass[0][0][5] = 3
4316 11:05:35.788934 rx_lastpass[0][0][5] = 33
4317 11:05:35.792237 rx_firspass[0][0][6] = 3
4318 11:05:35.792352 rx_lastpass[0][0][6] = 33
4319 11:05:35.795340 rx_firspass[0][0][7] = 4
4320 11:05:35.798870 rx_lastpass[0][0][7] = 36
4321 11:05:35.798955 rx_firspass[0][0][8] = -2
4322 11:05:35.801871 rx_lastpass[0][0][8] = 30
4323 11:05:35.805216 rx_firspass[0][0][9] = 2
4324 11:05:35.808629 rx_lastpass[0][0][9] = 32
4325 11:05:35.808715 rx_firspass[0][0][10] = 9
4326 11:05:35.811849 rx_lastpass[0][0][10] = 37
4327 11:05:35.815228 rx_firspass[0][0][11] = 0
4328 11:05:35.815312 rx_lastpass[0][0][11] = 30
4329 11:05:35.818281 rx_firspass[0][0][12] = 3
4330 11:05:35.821541 rx_lastpass[0][0][12] = 31
4331 11:05:35.825094 rx_firspass[0][0][13] = 1
4332 11:05:35.825178 rx_lastpass[0][0][13] = 31
4333 11:05:35.828460 rx_firspass[0][0][14] = 0
4334 11:05:35.831584 rx_lastpass[0][0][14] = 35
4335 11:05:35.834797 rx_firspass[0][0][15] = 4
4336 11:05:35.834880 rx_lastpass[0][0][15] = 36
4337 11:05:35.837878 rx_firspass[0][1][0] = 3
4338 11:05:35.841339 rx_lastpass[0][1][0] = 38
4339 11:05:35.841423 rx_firspass[0][1][1] = 4
4340 11:05:35.844396 rx_lastpass[0][1][1] = 38
4341 11:05:35.847741 rx_firspass[0][1][2] = 6
4342 11:05:35.851257 rx_lastpass[0][1][2] = 40
4343 11:05:35.851341 rx_firspass[0][1][3] = -2
4344 11:05:35.854234 rx_lastpass[0][1][3] = 31
4345 11:05:35.857563 rx_firspass[0][1][4] = 3
4346 11:05:35.860802 rx_lastpass[0][1][4] = 38
4347 11:05:35.860888 rx_firspass[0][1][5] = -1
4348 11:05:35.864125 rx_lastpass[0][1][5] = 34
4349 11:05:35.867325 rx_firspass[0][1][6] = 1
4350 11:05:35.867439 rx_lastpass[0][1][6] = 35
4351 11:05:35.870992 rx_firspass[0][1][7] = 3
4352 11:05:35.874443 rx_lastpass[0][1][7] = 37
4353 11:05:35.877657 rx_firspass[0][1][8] = -4
4354 11:05:35.877787 rx_lastpass[0][1][8] = 32
4355 11:05:35.880800 rx_firspass[0][1][9] = -2
4356 11:05:35.883850 rx_lastpass[0][1][9] = 34
4357 11:05:35.883950 rx_firspass[0][1][10] = 7
4358 11:05:35.886991 rx_lastpass[0][1][10] = 39
4359 11:05:35.890533 rx_firspass[0][1][11] = -2
4360 11:05:35.894038 rx_lastpass[0][1][11] = 32
4361 11:05:35.894129 rx_firspass[0][1][12] = 0
4362 11:05:35.897336 rx_lastpass[0][1][12] = 33
4363 11:05:35.900143 rx_firspass[0][1][13] = -1
4364 11:05:35.903748 rx_lastpass[0][1][13] = 33
4365 11:05:35.903855 rx_firspass[0][1][14] = 1
4366 11:05:35.907126 rx_lastpass[0][1][14] = 36
4367 11:05:35.910573 rx_firspass[0][1][15] = 5
4368 11:05:35.913361 rx_lastpass[0][1][15] = 38
4369 11:05:35.913500 rx_firspass[1][0][0] = 6
4370 11:05:35.916879 rx_lastpass[1][0][0] = 36
4371 11:05:35.919914 rx_firspass[1][0][1] = 4
4372 11:05:35.920056 rx_lastpass[1][0][1] = 37
4373 11:05:35.923362 rx_firspass[1][0][2] = 1
4374 11:05:35.926670 rx_lastpass[1][0][2] = 34
4375 11:05:35.929736 rx_firspass[1][0][3] = 1
4376 11:05:35.929940 rx_lastpass[1][0][3] = 30
4377 11:05:35.933511 rx_firspass[1][0][4] = 5
4378 11:05:35.936616 rx_lastpass[1][0][4] = 35
4379 11:05:35.936898 rx_firspass[1][0][5] = 9
4380 11:05:35.939399 rx_lastpass[1][0][5] = 38
4381 11:05:35.942783 rx_firspass[1][0][6] = 6
4382 11:05:35.946289 rx_lastpass[1][0][6] = 38
4383 11:05:35.946358 rx_firspass[1][0][7] = 5
4384 11:05:35.949238 rx_lastpass[1][0][7] = 34
4385 11:05:35.952372 rx_firspass[1][0][8] = 1
4386 11:05:35.952441 rx_lastpass[1][0][8] = 33
4387 11:05:35.955714 rx_firspass[1][0][9] = 0
4388 11:05:35.959113 rx_lastpass[1][0][9] = 31
4389 11:05:35.962250 rx_firspass[1][0][10] = 3
4390 11:05:35.962326 rx_lastpass[1][0][10] = 36
4391 11:05:35.965552 rx_firspass[1][0][11] = 4
4392 11:05:35.968847 rx_lastpass[1][0][11] = 36
4393 11:05:35.968927 rx_firspass[1][0][12] = 6
4394 11:05:35.972302 rx_lastpass[1][0][12] = 34
4395 11:05:35.975450 rx_firspass[1][0][13] = 6
4396 11:05:35.978911 rx_lastpass[1][0][13] = 35
4397 11:05:35.979002 rx_firspass[1][0][14] = 5
4398 11:05:35.982509 rx_lastpass[1][0][14] = 36
4399 11:05:35.985837 rx_firspass[1][0][15] = -4
4400 11:05:35.989121 rx_lastpass[1][0][15] = 29
4401 11:05:35.989290 rx_firspass[1][1][0] = 4
4402 11:05:35.992472 rx_lastpass[1][1][0] = 40
4403 11:05:35.995239 rx_firspass[1][1][1] = 3
4404 11:05:35.998787 rx_lastpass[1][1][1] = 39
4405 11:05:35.998982 rx_firspass[1][1][2] = 3
4406 11:05:36.001999 rx_lastpass[1][1][2] = 34
4407 11:05:36.005070 rx_firspass[1][1][3] = -2
4408 11:05:36.005221 rx_lastpass[1][1][3] = 33
4409 11:05:36.008313 rx_firspass[1][1][4] = 4
4410 11:05:36.012002 rx_lastpass[1][1][4] = 39
4411 11:05:36.015214 rx_firspass[1][1][5] = 5
4412 11:05:36.015500 rx_lastpass[1][1][5] = 40
4413 11:05:36.018765 rx_firspass[1][1][6] = 6
4414 11:05:36.021482 rx_lastpass[1][1][6] = 40
4415 11:05:36.021795 rx_firspass[1][1][7] = 3
4416 11:05:36.025014 rx_lastpass[1][1][7] = 38
4417 11:05:36.028332 rx_firspass[1][1][8] = -1
4418 11:05:36.031622 rx_lastpass[1][1][8] = 35
4419 11:05:36.032012 rx_firspass[1][1][9] = -2
4420 11:05:36.035284 rx_lastpass[1][1][9] = 33
4421 11:05:36.038746 rx_firspass[1][1][10] = 3
4422 11:05:36.039221 rx_lastpass[1][1][10] = 38
4423 11:05:36.041545 rx_firspass[1][1][11] = 3
4424 11:05:36.045025 rx_lastpass[1][1][11] = 38
4425 11:05:36.048408 rx_firspass[1][1][12] = 3
4426 11:05:36.048882 rx_lastpass[1][1][12] = 37
4427 11:05:36.051254 rx_firspass[1][1][13] = 4
4428 11:05:36.054591 rx_lastpass[1][1][13] = 39
4429 11:05:36.058129 rx_firspass[1][1][14] = 4
4430 11:05:36.058603 rx_lastpass[1][1][14] = 40
4431 11:05:36.060857 rx_firspass[1][1][15] = -4
4432 11:05:36.064332 rx_lastpass[1][1][15] = 31
4433 11:05:36.064720 dump params clk_delay
4434 11:05:36.067784 clk_delay[0] = -1
4435 11:05:36.068250 clk_delay[1] = 0
4436 11:05:36.071020 dump params dqs_delay
4437 11:05:36.074508 dqs_delay[0][0] = 0
4438 11:05:36.075004 dqs_delay[0][1] = 0
4439 11:05:36.077259 dqs_delay[1][0] = 0
4440 11:05:36.077650 dqs_delay[1][1] = -1
4441 11:05:36.081101 dump params delay_cell_unit = 744
4442 11:05:36.084429 dump source = 0x0
4443 11:05:36.084899 dump params frequency:1200
4444 11:05:36.087679 dump params rank number:2
4445 11:05:36.088150
4446 11:05:36.090966 dump params write leveling
4447 11:05:36.093857 write leveling[0][0][0] = 0x0
4448 11:05:36.097476 write leveling[0][0][1] = 0x0
4449 11:05:36.097950 write leveling[0][1][0] = 0x0
4450 11:05:36.100405 write leveling[0][1][1] = 0x0
4451 11:05:36.103830 write leveling[1][0][0] = 0x0
4452 11:05:36.107377 write leveling[1][0][1] = 0x0
4453 11:05:36.110084 write leveling[1][1][0] = 0x0
4454 11:05:36.110476 write leveling[1][1][1] = 0x0
4455 11:05:36.113447 dump params cbt_cs
4456 11:05:36.116807 cbt_cs[0][0] = 0x0
4457 11:05:36.117274 cbt_cs[0][1] = 0x0
4458 11:05:36.119970 cbt_cs[1][0] = 0x0
4459 11:05:36.120357 cbt_cs[1][1] = 0x0
4460 11:05:36.123255 dump params cbt_mr12
4461 11:05:36.123828 cbt_mr12[0][0] = 0x0
4462 11:05:36.126497 cbt_mr12[0][1] = 0x0
4463 11:05:36.126901 cbt_mr12[1][0] = 0x0
4464 11:05:36.129667 cbt_mr12[1][1] = 0x0
4465 11:05:36.132637 dump params tx window
4466 11:05:36.132723 tx_center_min[0][0][0] = 0
4467 11:05:36.135984 tx_center_max[0][0][0] = 0
4468 11:05:36.139296 tx_center_min[0][0][1] = 0
4469 11:05:36.142700 tx_center_max[0][0][1] = 0
4470 11:05:36.142786 tx_center_min[0][1][0] = 0
4471 11:05:36.145812 tx_center_max[0][1][0] = 0
4472 11:05:36.149137 tx_center_min[0][1][1] = 0
4473 11:05:36.152166 tx_center_max[0][1][1] = 0
4474 11:05:36.152252 tx_center_min[1][0][0] = 0
4475 11:05:36.155673 tx_center_max[1][0][0] = 0
4476 11:05:36.158922 tx_center_min[1][0][1] = 0
4477 11:05:36.162296 tx_center_max[1][0][1] = 0
4478 11:05:36.162382 tx_center_min[1][1][0] = 0
4479 11:05:36.165333 tx_center_max[1][1][0] = 0
4480 11:05:36.168573 tx_center_min[1][1][1] = 0
4481 11:05:36.172122 tx_center_max[1][1][1] = 0
4482 11:05:36.172208 dump params tx window
4483 11:05:36.175353 tx_win_center[0][0][0] = 0
4484 11:05:36.178398 tx_first_pass[0][0][0] = 0
4485 11:05:36.178484 tx_last_pass[0][0][0] = 0
4486 11:05:36.181728 tx_win_center[0][0][1] = 0
4487 11:05:36.185251 tx_first_pass[0][0][1] = 0
4488 11:05:36.188212 tx_last_pass[0][0][1] = 0
4489 11:05:36.188297 tx_win_center[0][0][2] = 0
4490 11:05:36.191688 tx_first_pass[0][0][2] = 0
4491 11:05:36.194864 tx_last_pass[0][0][2] = 0
4492 11:05:36.198039 tx_win_center[0][0][3] = 0
4493 11:05:36.198125 tx_first_pass[0][0][3] = 0
4494 11:05:36.201407 tx_last_pass[0][0][3] = 0
4495 11:05:36.204727 tx_win_center[0][0][4] = 0
4496 11:05:36.208117 tx_first_pass[0][0][4] = 0
4497 11:05:36.208203 tx_last_pass[0][0][4] = 0
4498 11:05:36.211252 tx_win_center[0][0][5] = 0
4499 11:05:36.214738 tx_first_pass[0][0][5] = 0
4500 11:05:36.214826 tx_last_pass[0][0][5] = 0
4501 11:05:36.217759 tx_win_center[0][0][6] = 0
4502 11:05:36.221222 tx_first_pass[0][0][6] = 0
4503 11:05:36.224455 tx_last_pass[0][0][6] = 0
4504 11:05:36.224541 tx_win_center[0][0][7] = 0
4505 11:05:36.227823 tx_first_pass[0][0][7] = 0
4506 11:05:36.230911 tx_last_pass[0][0][7] = 0
4507 11:05:36.234445 tx_win_center[0][0][8] = 0
4508 11:05:36.234530 tx_first_pass[0][0][8] = 0
4509 11:05:36.237467 tx_last_pass[0][0][8] = 0
4510 11:05:36.240765 tx_win_center[0][0][9] = 0
4511 11:05:36.244116 tx_first_pass[0][0][9] = 0
4512 11:05:36.244201 tx_last_pass[0][0][9] = 0
4513 11:05:36.247403 tx_win_center[0][0][10] = 0
4514 11:05:36.250594 tx_first_pass[0][0][10] = 0
4515 11:05:36.253797 tx_last_pass[0][0][10] = 0
4516 11:05:36.253882 tx_win_center[0][0][11] = 0
4517 11:05:36.257036 tx_first_pass[0][0][11] = 0
4518 11:05:36.260189 tx_last_pass[0][0][11] = 0
4519 11:05:36.263616 tx_win_center[0][0][12] = 0
4520 11:05:36.263702 tx_first_pass[0][0][12] = 0
4521 11:05:36.266922 tx_last_pass[0][0][12] = 0
4522 11:05:36.270317 tx_win_center[0][0][13] = 0
4523 11:05:36.273475 tx_first_pass[0][0][13] = 0
4524 11:05:36.273561 tx_last_pass[0][0][13] = 0
4525 11:05:36.276691 tx_win_center[0][0][14] = 0
4526 11:05:36.280057 tx_first_pass[0][0][14] = 0
4527 11:05:36.283080 tx_last_pass[0][0][14] = 0
4528 11:05:36.286587 tx_win_center[0][0][15] = 0
4529 11:05:36.286671 tx_first_pass[0][0][15] = 0
4530 11:05:36.289523 tx_last_pass[0][0][15] = 0
4531 11:05:36.292856 tx_win_center[0][1][0] = 0
4532 11:05:36.296373 tx_first_pass[0][1][0] = 0
4533 11:05:36.296458 tx_last_pass[0][1][0] = 0
4534 11:05:36.299435 tx_win_center[0][1][1] = 0
4535 11:05:36.302970 tx_first_pass[0][1][1] = 0
4536 11:05:36.306154 tx_last_pass[0][1][1] = 0
4537 11:05:36.306242 tx_win_center[0][1][2] = 0
4538 11:05:36.309274 tx_first_pass[0][1][2] = 0
4539 11:05:36.312598 tx_last_pass[0][1][2] = 0
4540 11:05:36.312684 tx_win_center[0][1][3] = 0
4541 11:05:36.316018 tx_first_pass[0][1][3] = 0
4542 11:05:36.319171 tx_last_pass[0][1][3] = 0
4543 11:05:36.322401 tx_win_center[0][1][4] = 0
4544 11:05:36.322487 tx_first_pass[0][1][4] = 0
4545 11:05:36.325599 tx_last_pass[0][1][4] = 0
4546 11:05:36.328854 tx_win_center[0][1][5] = 0
4547 11:05:36.332153 tx_first_pass[0][1][5] = 0
4548 11:05:36.332239 tx_last_pass[0][1][5] = 0
4549 11:05:36.335364 tx_win_center[0][1][6] = 0
4550 11:05:36.338820 tx_first_pass[0][1][6] = 0
4551 11:05:36.341894 tx_last_pass[0][1][6] = 0
4552 11:05:36.341979 tx_win_center[0][1][7] = 0
4553 11:05:36.345247 tx_first_pass[0][1][7] = 0
4554 11:05:36.348670 tx_last_pass[0][1][7] = 0
4555 11:05:36.352026 tx_win_center[0][1][8] = 0
4556 11:05:36.352112 tx_first_pass[0][1][8] = 0
4557 11:05:36.354957 tx_last_pass[0][1][8] = 0
4558 11:05:36.358316 tx_win_center[0][1][9] = 0
4559 11:05:36.361608 tx_first_pass[0][1][9] = 0
4560 11:05:36.361693 tx_last_pass[0][1][9] = 0
4561 11:05:36.364952 tx_win_center[0][1][10] = 0
4562 11:05:36.368285 tx_first_pass[0][1][10] = 0
4563 11:05:36.371340 tx_last_pass[0][1][10] = 0
4564 11:05:36.371425 tx_win_center[0][1][11] = 0
4565 11:05:36.374574 tx_first_pass[0][1][11] = 0
4566 11:05:36.378165 tx_last_pass[0][1][11] = 0
4567 11:05:36.381135 tx_win_center[0][1][12] = 0
4568 11:05:36.381220 tx_first_pass[0][1][12] = 0
4569 11:05:36.384506 tx_last_pass[0][1][12] = 0
4570 11:05:36.387887 tx_win_center[0][1][13] = 0
4571 11:05:36.391078 tx_first_pass[0][1][13] = 0
4572 11:05:36.391164 tx_last_pass[0][1][13] = 0
4573 11:05:36.394220 tx_win_center[0][1][14] = 0
4574 11:05:36.397518 tx_first_pass[0][1][14] = 0
4575 11:05:36.401023 tx_last_pass[0][1][14] = 0
4576 11:05:36.401109 tx_win_center[0][1][15] = 0
4577 11:05:36.404307 tx_first_pass[0][1][15] = 0
4578 11:05:36.407381 tx_last_pass[0][1][15] = 0
4579 11:05:36.410591 tx_win_center[1][0][0] = 0
4580 11:05:36.410677 tx_first_pass[1][0][0] = 0
4581 11:05:36.414153 tx_last_pass[1][0][0] = 0
4582 11:05:36.417189 tx_win_center[1][0][1] = 0
4583 11:05:36.420495 tx_first_pass[1][0][1] = 0
4584 11:05:36.420581 tx_last_pass[1][0][1] = 0
4585 11:05:36.423659 tx_win_center[1][0][2] = 0
4586 11:05:36.427113 tx_first_pass[1][0][2] = 0
4587 11:05:36.430533 tx_last_pass[1][0][2] = 0
4588 11:05:36.430619 tx_win_center[1][0][3] = 0
4589 11:05:36.433617 tx_first_pass[1][0][3] = 0
4590 11:05:36.436731 tx_last_pass[1][0][3] = 0
4591 11:05:36.439969 tx_win_center[1][0][4] = 0
4592 11:05:36.440054 tx_first_pass[1][0][4] = 0
4593 11:05:36.443327 tx_last_pass[1][0][4] = 0
4594 11:05:36.446513 tx_win_center[1][0][5] = 0
4595 11:05:36.450126 tx_first_pass[1][0][5] = 0
4596 11:05:36.450212 tx_last_pass[1][0][5] = 0
4597 11:05:36.453275 tx_win_center[1][0][6] = 0
4598 11:05:36.456430 tx_first_pass[1][0][6] = 0
4599 11:05:36.456516 tx_last_pass[1][0][6] = 0
4600 11:05:36.459777 tx_win_center[1][0][7] = 0
4601 11:05:36.463010 tx_first_pass[1][0][7] = 0
4602 11:05:36.466304 tx_last_pass[1][0][7] = 0
4603 11:05:36.466390 tx_win_center[1][0][8] = 0
4604 11:05:36.469646 tx_first_pass[1][0][8] = 0
4605 11:05:36.472942 tx_last_pass[1][0][8] = 0
4606 11:05:36.475971 tx_win_center[1][0][9] = 0
4607 11:05:36.476057 tx_first_pass[1][0][9] = 0
4608 11:05:36.479445 tx_last_pass[1][0][9] = 0
4609 11:05:36.482693 tx_win_center[1][0][10] = 0
4610 11:05:36.485921 tx_first_pass[1][0][10] = 0
4611 11:05:36.486007 tx_last_pass[1][0][10] = 0
4612 11:05:36.489187 tx_win_center[1][0][11] = 0
4613 11:05:36.492687 tx_first_pass[1][0][11] = 0
4614 11:05:36.495637 tx_last_pass[1][0][11] = 0
4615 11:05:36.495722 tx_win_center[1][0][12] = 0
4616 11:05:36.498866 tx_first_pass[1][0][12] = 0
4617 11:05:36.502345 tx_last_pass[1][0][12] = 0
4618 11:05:36.505663 tx_win_center[1][0][13] = 0
4619 11:05:36.508928 tx_first_pass[1][0][13] = 0
4620 11:05:36.509051 tx_last_pass[1][0][13] = 0
4621 11:05:36.511996 tx_win_center[1][0][14] = 0
4622 11:05:36.515260 tx_first_pass[1][0][14] = 0
4623 11:05:36.518588 tx_last_pass[1][0][14] = 0
4624 11:05:36.518673 tx_win_center[1][0][15] = 0
4625 11:05:36.522057 tx_first_pass[1][0][15] = 0
4626 11:05:36.525235 tx_last_pass[1][0][15] = 0
4627 11:05:36.528316 tx_win_center[1][1][0] = 0
4628 11:05:36.528402 tx_first_pass[1][1][0] = 0
4629 11:05:36.531629 tx_last_pass[1][1][0] = 0
4630 11:05:36.534892 tx_win_center[1][1][1] = 0
4631 11:05:36.538241 tx_first_pass[1][1][1] = 0
4632 11:05:36.538328 tx_last_pass[1][1][1] = 0
4633 11:05:36.541762 tx_win_center[1][1][2] = 0
4634 11:05:36.544942 tx_first_pass[1][1][2] = 0
4635 11:05:36.545028 tx_last_pass[1][1][2] = 0
4636 11:05:36.548190 tx_win_center[1][1][3] = 0
4637 11:05:36.551589 tx_first_pass[1][1][3] = 0
4638 11:05:36.554575 tx_last_pass[1][1][3] = 0
4639 11:05:36.554661 tx_win_center[1][1][4] = 0
4640 11:05:36.557938 tx_first_pass[1][1][4] = 0
4641 11:05:36.561247 tx_last_pass[1][1][4] = 0
4642 11:05:36.564584 tx_win_center[1][1][5] = 0
4643 11:05:36.564670 tx_first_pass[1][1][5] = 0
4644 11:05:36.567981 tx_last_pass[1][1][5] = 0
4645 11:05:36.570902 tx_win_center[1][1][6] = 0
4646 11:05:36.574338 tx_first_pass[1][1][6] = 0
4647 11:05:36.574423 tx_last_pass[1][1][6] = 0
4648 11:05:36.577440 tx_win_center[1][1][7] = 0
4649 11:05:36.580808 tx_first_pass[1][1][7] = 0
4650 11:05:36.584185 tx_last_pass[1][1][7] = 0
4651 11:05:36.584271 tx_win_center[1][1][8] = 0
4652 11:05:36.587565 tx_first_pass[1][1][8] = 0
4653 11:05:36.590768 tx_last_pass[1][1][8] = 0
4654 11:05:36.590854 tx_win_center[1][1][9] = 0
4655 11:05:36.594109 tx_first_pass[1][1][9] = 0
4656 11:05:36.597474 tx_last_pass[1][1][9] = 0
4657 11:05:36.600516 tx_win_center[1][1][10] = 0
4658 11:05:36.600602 tx_first_pass[1][1][10] = 0
4659 11:05:36.604118 tx_last_pass[1][1][10] = 0
4660 11:05:36.607148 tx_win_center[1][1][11] = 0
4661 11:05:36.610314 tx_first_pass[1][1][11] = 0
4662 11:05:36.613676 tx_last_pass[1][1][11] = 0
4663 11:05:36.613762 tx_win_center[1][1][12] = 0
4664 11:05:36.616865 tx_first_pass[1][1][12] = 0
4665 11:05:36.620358 tx_last_pass[1][1][12] = 0
4666 11:05:36.623381 tx_win_center[1][1][13] = 0
4667 11:05:36.623476 tx_first_pass[1][1][13] = 0
4668 11:05:36.626749 tx_last_pass[1][1][13] = 0
4669 11:05:36.630080 tx_win_center[1][1][14] = 0
4670 11:05:36.633221 tx_first_pass[1][1][14] = 0
4671 11:05:36.633306 tx_last_pass[1][1][14] = 0
4672 11:05:36.636454 tx_win_center[1][1][15] = 0
4673 11:05:36.639932 tx_first_pass[1][1][15] = 0
4674 11:05:36.643092 tx_last_pass[1][1][15] = 0
4675 11:05:36.643177 dump params rx window
4676 11:05:36.646473 rx_firspass[0][0][0] = 0
4677 11:05:36.649488 rx_lastpass[0][0][0] = 0
4678 11:05:36.649574 rx_firspass[0][0][1] = 0
4679 11:05:36.652911 rx_lastpass[0][0][1] = 0
4680 11:05:36.656430 rx_firspass[0][0][2] = 0
4681 11:05:36.659441 rx_lastpass[0][0][2] = 0
4682 11:05:36.659532 rx_firspass[0][0][3] = 0
4683 11:05:36.662524 rx_lastpass[0][0][3] = 0
4684 11:05:36.665826 rx_firspass[0][0][4] = 0
4685 11:05:36.665911 rx_lastpass[0][0][4] = 0
4686 11:05:36.668984 rx_firspass[0][0][5] = 0
4687 11:05:36.672331 rx_lastpass[0][0][5] = 0
4688 11:05:36.672417 rx_firspass[0][0][6] = 0
4689 11:05:36.675784 rx_lastpass[0][0][6] = 0
4690 11:05:36.678783 rx_firspass[0][0][7] = 0
4691 11:05:36.678868 rx_lastpass[0][0][7] = 0
4692 11:05:36.682241 rx_firspass[0][0][8] = 0
4693 11:05:36.685486 rx_lastpass[0][0][8] = 0
4694 11:05:36.688945 rx_firspass[0][0][9] = 0
4695 11:05:36.689030 rx_lastpass[0][0][9] = 0
4696 11:05:36.691899 rx_firspass[0][0][10] = 0
4697 11:05:36.695208 rx_lastpass[0][0][10] = 0
4698 11:05:36.695293 rx_firspass[0][0][11] = 0
4699 11:05:36.698634 rx_lastpass[0][0][11] = 0
4700 11:05:36.701699 rx_firspass[0][0][12] = 0
4701 11:05:36.705194 rx_lastpass[0][0][12] = 0
4702 11:05:36.705279 rx_firspass[0][0][13] = 0
4703 11:05:36.708372 rx_lastpass[0][0][13] = 0
4704 11:05:36.711599 rx_firspass[0][0][14] = 0
4705 11:05:36.715062 rx_lastpass[0][0][14] = 0
4706 11:05:36.715147 rx_firspass[0][0][15] = 0
4707 11:05:36.718107 rx_lastpass[0][0][15] = 0
4708 11:05:36.721771 rx_firspass[0][1][0] = 0
4709 11:05:36.721857 rx_lastpass[0][1][0] = 0
4710 11:05:36.724815 rx_firspass[0][1][1] = 0
4711 11:05:36.728198 rx_lastpass[0][1][1] = 0
4712 11:05:36.728283 rx_firspass[0][1][2] = 0
4713 11:05:36.731355 rx_lastpass[0][1][2] = 0
4714 11:05:36.734554 rx_firspass[0][1][3] = 0
4715 11:05:36.737735 rx_lastpass[0][1][3] = 0
4716 11:05:36.737820 rx_firspass[0][1][4] = 0
4717 11:05:36.741296 rx_lastpass[0][1][4] = 0
4718 11:05:36.744333 rx_firspass[0][1][5] = 0
4719 11:05:36.744418 rx_lastpass[0][1][5] = 0
4720 11:05:36.747749 rx_firspass[0][1][6] = 0
4721 11:05:36.751073 rx_lastpass[0][1][6] = 0
4722 11:05:36.751159 rx_firspass[0][1][7] = 0
4723 11:05:36.754171 rx_lastpass[0][1][7] = 0
4724 11:05:36.757427 rx_firspass[0][1][8] = 0
4725 11:05:36.760845 rx_lastpass[0][1][8] = 0
4726 11:05:36.760930 rx_firspass[0][1][9] = 0
4727 11:05:36.764427 rx_lastpass[0][1][9] = 0
4728 11:05:36.767421 rx_firspass[0][1][10] = 0
4729 11:05:36.767514 rx_lastpass[0][1][10] = 0
4730 11:05:36.770900 rx_firspass[0][1][11] = 0
4731 11:05:36.773984 rx_lastpass[0][1][11] = 0
4732 11:05:36.777042 rx_firspass[0][1][12] = 0
4733 11:05:36.777128 rx_lastpass[0][1][12] = 0
4734 11:05:36.780473 rx_firspass[0][1][13] = 0
4735 11:05:36.783582 rx_lastpass[0][1][13] = 0
4736 11:05:36.783668 rx_firspass[0][1][14] = 0
4737 11:05:36.787273 rx_lastpass[0][1][14] = 0
4738 11:05:36.790394 rx_firspass[0][1][15] = 0
4739 11:05:36.793668 rx_lastpass[0][1][15] = 0
4740 11:05:36.793754 rx_firspass[1][0][0] = 0
4741 11:05:36.796913 rx_lastpass[1][0][0] = 0
4742 11:05:36.799990 rx_firspass[1][0][1] = 0
4743 11:05:36.800076 rx_lastpass[1][0][1] = 0
4744 11:05:36.803193 rx_firspass[1][0][2] = 0
4745 11:05:36.806506 rx_lastpass[1][0][2] = 0
4746 11:05:36.806592 rx_firspass[1][0][3] = 0
4747 11:05:36.809894 rx_lastpass[1][0][3] = 0
4748 11:05:36.813143 rx_firspass[1][0][4] = 0
4749 11:05:36.816650 rx_lastpass[1][0][4] = 0
4750 11:05:36.816736 rx_firspass[1][0][5] = 0
4751 11:05:36.819680 rx_lastpass[1][0][5] = 0
4752 11:05:36.822956 rx_firspass[1][0][6] = 0
4753 11:05:36.823040 rx_lastpass[1][0][6] = 0
4754 11:05:36.826189 rx_firspass[1][0][7] = 0
4755 11:05:36.829433 rx_lastpass[1][0][7] = 0
4756 11:05:36.829519 rx_firspass[1][0][8] = 0
4757 11:05:36.832765 rx_lastpass[1][0][8] = 0
4758 11:05:36.835915 rx_firspass[1][0][9] = 0
4759 11:05:36.839359 rx_lastpass[1][0][9] = 0
4760 11:05:36.839445 rx_firspass[1][0][10] = 0
4761 11:05:36.842486 rx_lastpass[1][0][10] = 0
4762 11:05:36.845711 rx_firspass[1][0][11] = 0
4763 11:05:36.845797 rx_lastpass[1][0][11] = 0
4764 11:05:36.849370 rx_firspass[1][0][12] = 0
4765 11:05:36.852363 rx_lastpass[1][0][12] = 0
4766 11:05:36.855719 rx_firspass[1][0][13] = 0
4767 11:05:36.855805 rx_lastpass[1][0][13] = 0
4768 11:05:36.858964 rx_firspass[1][0][14] = 0
4769 11:05:36.862225 rx_lastpass[1][0][14] = 0
4770 11:05:36.865621 rx_firspass[1][0][15] = 0
4771 11:05:36.865707 rx_lastpass[1][0][15] = 0
4772 11:05:36.868712 rx_firspass[1][1][0] = 0
4773 11:05:36.871840 rx_lastpass[1][1][0] = 0
4774 11:05:36.871926 rx_firspass[1][1][1] = 0
4775 11:05:36.875176 rx_lastpass[1][1][1] = 0
4776 11:05:36.878390 rx_firspass[1][1][2] = 0
4777 11:05:36.878476 rx_lastpass[1][1][2] = 0
4778 11:05:36.881669 rx_firspass[1][1][3] = 0
4779 11:05:36.885071 rx_lastpass[1][1][3] = 0
4780 11:05:36.888263 rx_firspass[1][1][4] = 0
4781 11:05:36.888349 rx_lastpass[1][1][4] = 0
4782 11:05:36.891572 rx_firspass[1][1][5] = 0
4783 11:05:36.895088 rx_lastpass[1][1][5] = 0
4784 11:05:36.895173 rx_firspass[1][1][6] = 0
4785 11:05:36.898061 rx_lastpass[1][1][6] = 0
4786 11:05:36.901424 rx_firspass[1][1][7] = 0
4787 11:05:36.901509 rx_lastpass[1][1][7] = 0
4788 11:05:36.904626 rx_firspass[1][1][8] = 0
4789 11:05:36.908110 rx_lastpass[1][1][8] = 0
4790 11:05:36.908196 rx_firspass[1][1][9] = 0
4791 11:05:36.911287 rx_lastpass[1][1][9] = 0
4792 11:05:36.914701 rx_firspass[1][1][10] = 0
4793 11:05:36.917850 rx_lastpass[1][1][10] = 0
4794 11:05:36.917935 rx_firspass[1][1][11] = 0
4795 11:05:36.920984 rx_lastpass[1][1][11] = 0
4796 11:05:36.924365 rx_firspass[1][1][12] = 0
4797 11:05:36.927570 rx_lastpass[1][1][12] = 0
4798 11:05:36.927656 rx_firspass[1][1][13] = 0
4799 11:05:36.931184 rx_lastpass[1][1][13] = 0
4800 11:05:36.934227 rx_firspass[1][1][14] = 0
4801 11:05:36.934312 rx_lastpass[1][1][14] = 0
4802 11:05:36.937578 rx_firspass[1][1][15] = 0
4803 11:05:36.940789 rx_lastpass[1][1][15] = 0
4804 11:05:36.940874 dump params clk_delay
4805 11:05:36.944132 clk_delay[0] = 0
4806 11:05:36.944217 clk_delay[1] = 0
4807 11:05:36.947566 dump params dqs_delay
4808 11:05:36.950423 dqs_delay[0][0] = 0
4809 11:05:36.950509 dqs_delay[0][1] = 0
4810 11:05:36.953847 dqs_delay[1][0] = 0
4811 11:05:36.953932 dqs_delay[1][1] = 0
4812 11:05:36.957325 dump params delay_cell_unit = 744
4813 11:05:36.960584 dump source = 0x0
4814 11:05:36.960669 dump params frequency:800
4815 11:05:36.963647 dump params rank number:2
4816 11:05:36.963732
4817 11:05:36.966802 dump params write leveling
4818 11:05:36.970337 write leveling[0][0][0] = 0x0
4819 11:05:36.973721 write leveling[0][0][1] = 0x0
4820 11:05:36.973807 write leveling[0][1][0] = 0x0
4821 11:05:36.976841 write leveling[0][1][1] = 0x0
4822 11:05:36.980326 write leveling[1][0][0] = 0x0
4823 11:05:36.983411 write leveling[1][0][1] = 0x0
4824 11:05:36.986720 write leveling[1][1][0] = 0x0
4825 11:05:36.986805 write leveling[1][1][1] = 0x0
4826 11:05:36.989999 dump params cbt_cs
4827 11:05:36.990084 cbt_cs[0][0] = 0x0
4828 11:05:36.993299 cbt_cs[0][1] = 0x0
4829 11:05:36.996656 cbt_cs[1][0] = 0x0
4830 11:05:36.996741 cbt_cs[1][1] = 0x0
4831 11:05:36.999843 dump params cbt_mr12
4832 11:05:36.999928 cbt_mr12[0][0] = 0x0
4833 11:05:37.003040 cbt_mr12[0][1] = 0x0
4834 11:05:37.003125 cbt_mr12[1][0] = 0x0
4835 11:05:37.006347 cbt_mr12[1][1] = 0x0
4836 11:05:37.009590 dump params tx window
4837 11:05:37.009675 tx_center_min[0][0][0] = 0
4838 11:05:37.012803 tx_center_max[0][0][0] = 0
4839 11:05:37.016112 tx_center_min[0][0][1] = 0
4840 11:05:37.019248 tx_center_max[0][0][1] = 0
4841 11:05:37.019333 tx_center_min[0][1][0] = 0
4842 11:05:37.022604 tx_center_max[0][1][0] = 0
4843 11:05:37.026022 tx_center_min[0][1][1] = 0
4844 11:05:37.029256 tx_center_max[0][1][1] = 0
4845 11:05:37.029342 tx_center_min[1][0][0] = 0
4846 11:05:37.032428 tx_center_max[1][0][0] = 0
4847 11:05:37.035739 tx_center_min[1][0][1] = 0
4848 11:05:37.039130 tx_center_max[1][0][1] = 0
4849 11:05:37.039215 tx_center_min[1][1][0] = 0
4850 11:05:37.042204 tx_center_max[1][1][0] = 0
4851 11:05:37.045625 tx_center_min[1][1][1] = 0
4852 11:05:37.048808 tx_center_max[1][1][1] = 0
4853 11:05:37.048894 dump params tx window
4854 11:05:37.052396 tx_win_center[0][0][0] = 0
4855 11:05:37.055261 tx_first_pass[0][0][0] = 0
4856 11:05:37.055347 tx_last_pass[0][0][0] = 0
4857 11:05:37.058950 tx_win_center[0][0][1] = 0
4858 11:05:37.062199 tx_first_pass[0][0][1] = 0
4859 11:05:37.065325 tx_last_pass[0][0][1] = 0
4860 11:05:37.065410 tx_win_center[0][0][2] = 0
4861 11:05:37.068378 tx_first_pass[0][0][2] = 0
4862 11:05:37.071951 tx_last_pass[0][0][2] = 0
4863 11:05:37.075041 tx_win_center[0][0][3] = 0
4864 11:05:37.075126 tx_first_pass[0][0][3] = 0
4865 11:05:37.078211 tx_last_pass[0][0][3] = 0
4866 11:05:37.081780 tx_win_center[0][0][4] = 0
4867 11:05:37.084883 tx_first_pass[0][0][4] = 0
4868 11:05:37.084968 tx_last_pass[0][0][4] = 0
4869 11:05:37.088126 tx_win_center[0][0][5] = 0
4870 11:05:37.091329 tx_first_pass[0][0][5] = 0
4871 11:05:37.091415 tx_last_pass[0][0][5] = 0
4872 11:05:37.094528 tx_win_center[0][0][6] = 0
4873 11:05:37.098116 tx_first_pass[0][0][6] = 0
4874 11:05:37.101287 tx_last_pass[0][0][6] = 0
4875 11:05:37.101373 tx_win_center[0][0][7] = 0
4876 11:05:37.104575 tx_first_pass[0][0][7] = 0
4877 11:05:37.107922 tx_last_pass[0][0][7] = 0
4878 11:05:37.111050 tx_win_center[0][0][8] = 0
4879 11:05:37.111135 tx_first_pass[0][0][8] = 0
4880 11:05:37.114436 tx_last_pass[0][0][8] = 0
4881 11:05:37.117535 tx_win_center[0][0][9] = 0
4882 11:05:37.120802 tx_first_pass[0][0][9] = 0
4883 11:05:37.120887 tx_last_pass[0][0][9] = 0
4884 11:05:37.123992 tx_win_center[0][0][10] = 0
4885 11:05:37.127339 tx_first_pass[0][0][10] = 0
4886 11:05:37.130629 tx_last_pass[0][0][10] = 0
4887 11:05:37.130716 tx_win_center[0][0][11] = 0
4888 11:05:37.133937 tx_first_pass[0][0][11] = 0
4889 11:05:37.137399 tx_last_pass[0][0][11] = 0
4890 11:05:37.140299 tx_win_center[0][0][12] = 0
4891 11:05:37.140394 tx_first_pass[0][0][12] = 0
4892 11:05:37.143740 tx_last_pass[0][0][12] = 0
4893 11:05:37.147008 tx_win_center[0][0][13] = 0
4894 11:05:37.150426 tx_first_pass[0][0][13] = 0
4895 11:05:37.150512 tx_last_pass[0][0][13] = 0
4896 11:05:37.153566 tx_win_center[0][0][14] = 0
4897 11:05:37.156796 tx_first_pass[0][0][14] = 0
4898 11:05:37.160062 tx_last_pass[0][0][14] = 0
4899 11:05:37.160148 tx_win_center[0][0][15] = 0
4900 11:05:37.163382 tx_first_pass[0][0][15] = 0
4901 11:05:37.166712 tx_last_pass[0][0][15] = 0
4902 11:05:37.170009 tx_win_center[0][1][0] = 0
4903 11:05:37.173197 tx_first_pass[0][1][0] = 0
4904 11:05:37.173283 tx_last_pass[0][1][0] = 0
4905 11:05:37.176594 tx_win_center[0][1][1] = 0
4906 11:05:37.179900 tx_first_pass[0][1][1] = 0
4907 11:05:37.179986 tx_last_pass[0][1][1] = 0
4908 11:05:37.182930 tx_win_center[0][1][2] = 0
4909 11:05:37.186288 tx_first_pass[0][1][2] = 0
4910 11:05:37.189736 tx_last_pass[0][1][2] = 0
4911 11:05:37.189821 tx_win_center[0][1][3] = 0
4912 11:05:37.192869 tx_first_pass[0][1][3] = 0
4913 11:05:37.196400 tx_last_pass[0][1][3] = 0
4914 11:05:37.199722 tx_win_center[0][1][4] = 0
4915 11:05:37.199808 tx_first_pass[0][1][4] = 0
4916 11:05:37.202603 tx_last_pass[0][1][4] = 0
4917 11:05:37.206041 tx_win_center[0][1][5] = 0
4918 11:05:37.209188 tx_first_pass[0][1][5] = 0
4919 11:05:37.209274 tx_last_pass[0][1][5] = 0
4920 11:05:37.212381 tx_win_center[0][1][6] = 0
4921 11:05:37.215559 tx_first_pass[0][1][6] = 0
4922 11:05:37.218975 tx_last_pass[0][1][6] = 0
4923 11:05:37.219061 tx_win_center[0][1][7] = 0
4924 11:05:37.222216 tx_first_pass[0][1][7] = 0
4925 11:05:37.225466 tx_last_pass[0][1][7] = 0
4926 11:05:37.225551 tx_win_center[0][1][8] = 0
4927 11:05:37.228756 tx_first_pass[0][1][8] = 0
4928 11:05:37.232069 tx_last_pass[0][1][8] = 0
4929 11:05:37.235209 tx_win_center[0][1][9] = 0
4930 11:05:37.235294 tx_first_pass[0][1][9] = 0
4931 11:05:37.238834 tx_last_pass[0][1][9] = 0
4932 11:05:37.241972 tx_win_center[0][1][10] = 0
4933 11:05:37.245262 tx_first_pass[0][1][10] = 0
4934 11:05:37.245347 tx_last_pass[0][1][10] = 0
4935 11:05:37.248442 tx_win_center[0][1][11] = 0
4936 11:05:37.251575 tx_first_pass[0][1][11] = 0
4937 11:05:37.254884 tx_last_pass[0][1][11] = 0
4938 11:05:37.254970 tx_win_center[0][1][12] = 0
4939 11:05:37.258240 tx_first_pass[0][1][12] = 0
4940 11:05:37.261559 tx_last_pass[0][1][12] = 0
4941 11:05:37.264894 tx_win_center[0][1][13] = 0
4942 11:05:37.268193 tx_first_pass[0][1][13] = 0
4943 11:05:37.268278 tx_last_pass[0][1][13] = 0
4944 11:05:37.271360 tx_win_center[0][1][14] = 0
4945 11:05:37.274671 tx_first_pass[0][1][14] = 0
4946 11:05:37.277996 tx_last_pass[0][1][14] = 0
4947 11:05:37.278082 tx_win_center[0][1][15] = 0
4948 11:05:37.281191 tx_first_pass[0][1][15] = 0
4949 11:05:37.284501 tx_last_pass[0][1][15] = 0
4950 11:05:37.287972 tx_win_center[1][0][0] = 0
4951 11:05:37.288057 tx_first_pass[1][0][0] = 0
4952 11:05:37.290997 tx_last_pass[1][0][0] = 0
4953 11:05:37.294291 tx_win_center[1][0][1] = 0
4954 11:05:37.297597 tx_first_pass[1][0][1] = 0
4955 11:05:37.297683 tx_last_pass[1][0][1] = 0
4956 11:05:37.300953 tx_win_center[1][0][2] = 0
4957 11:05:37.304296 tx_first_pass[1][0][2] = 0
4958 11:05:37.307311 tx_last_pass[1][0][2] = 0
4959 11:05:37.307397 tx_win_center[1][0][3] = 0
4960 11:05:37.310473 tx_first_pass[1][0][3] = 0
4961 11:05:37.314010 tx_last_pass[1][0][3] = 0
4962 11:05:37.314097 tx_win_center[1][0][4] = 0
4963 11:05:37.317275 tx_first_pass[1][0][4] = 0
4964 11:05:37.320622 tx_last_pass[1][0][4] = 0
4965 11:05:37.323988 tx_win_center[1][0][5] = 0
4966 11:05:37.324074 tx_first_pass[1][0][5] = 0
4967 11:05:37.327062 tx_last_pass[1][0][5] = 0
4968 11:05:37.330574 tx_win_center[1][0][6] = 0
4969 11:05:37.333743 tx_first_pass[1][0][6] = 0
4970 11:05:37.333829 tx_last_pass[1][0][6] = 0
4971 11:05:37.336691 tx_win_center[1][0][7] = 0
4972 11:05:37.340183 tx_first_pass[1][0][7] = 0
4973 11:05:37.343341 tx_last_pass[1][0][7] = 0
4974 11:05:37.343427 tx_win_center[1][0][8] = 0
4975 11:05:37.346851 tx_first_pass[1][0][8] = 0
4976 11:05:37.350049 tx_last_pass[1][0][8] = 0
4977 11:05:37.353075 tx_win_center[1][0][9] = 0
4978 11:05:37.353187 tx_first_pass[1][0][9] = 0
4979 11:05:37.356627 tx_last_pass[1][0][9] = 0
4980 11:05:37.359561 tx_win_center[1][0][10] = 0
4981 11:05:37.362886 tx_first_pass[1][0][10] = 0
4982 11:05:37.362971 tx_last_pass[1][0][10] = 0
4983 11:05:37.366220 tx_win_center[1][0][11] = 0
4984 11:05:37.369595 tx_first_pass[1][0][11] = 0
4985 11:05:37.372974 tx_last_pass[1][0][11] = 0
4986 11:05:37.373060 tx_win_center[1][0][12] = 0
4987 11:05:37.375954 tx_first_pass[1][0][12] = 0
4988 11:05:37.379404 tx_last_pass[1][0][12] = 0
4989 11:05:37.382702 tx_win_center[1][0][13] = 0
4990 11:05:37.382787 tx_first_pass[1][0][13] = 0
4991 11:05:37.386010 tx_last_pass[1][0][13] = 0
4992 11:05:37.389091 tx_win_center[1][0][14] = 0
4993 11:05:37.392394 tx_first_pass[1][0][14] = 0
4994 11:05:37.392479 tx_last_pass[1][0][14] = 0
4995 11:05:37.395702 tx_win_center[1][0][15] = 0
4996 11:05:37.399002 tx_first_pass[1][0][15] = 0
4997 11:05:37.402087 tx_last_pass[1][0][15] = 0
4998 11:05:37.402173 tx_win_center[1][1][0] = 0
4999 11:05:37.405513 tx_first_pass[1][1][0] = 0
5000 11:05:37.408972 tx_last_pass[1][1][0] = 0
5001 11:05:37.412037 tx_win_center[1][1][1] = 0
5002 11:05:37.412122 tx_first_pass[1][1][1] = 0
5003 11:05:37.415313 tx_last_pass[1][1][1] = 0
5004 11:05:37.418784 tx_win_center[1][1][2] = 0
5005 11:05:37.421713 tx_first_pass[1][1][2] = 0
5006 11:05:37.421799 tx_last_pass[1][1][2] = 0
5007 11:05:37.425041 tx_win_center[1][1][3] = 0
5008 11:05:37.428303 tx_first_pass[1][1][3] = 0
5009 11:05:37.431518 tx_last_pass[1][1][3] = 0
5010 11:05:37.431604 tx_win_center[1][1][4] = 0
5011 11:05:37.435114 tx_first_pass[1][1][4] = 0
5012 11:05:37.437954 tx_last_pass[1][1][4] = 0
5013 11:05:37.441569 tx_win_center[1][1][5] = 0
5014 11:05:37.441654 tx_first_pass[1][1][5] = 0
5015 11:05:37.444614 tx_last_pass[1][1][5] = 0
5016 11:05:37.447830 tx_win_center[1][1][6] = 0
5017 11:05:37.451081 tx_first_pass[1][1][6] = 0
5018 11:05:37.451166 tx_last_pass[1][1][6] = 0
5019 11:05:37.454317 tx_win_center[1][1][7] = 0
5020 11:05:37.457740 tx_first_pass[1][1][7] = 0
5021 11:05:37.457826 tx_last_pass[1][1][7] = 0
5022 11:05:37.461434 tx_win_center[1][1][8] = 0
5023 11:05:37.464309 tx_first_pass[1][1][8] = 0
5024 11:05:37.467659 tx_last_pass[1][1][8] = 0
5025 11:05:37.467744 tx_win_center[1][1][9] = 0
5026 11:05:37.471054 tx_first_pass[1][1][9] = 0
5027 11:05:37.474321 tx_last_pass[1][1][9] = 0
5028 11:05:37.477244 tx_win_center[1][1][10] = 0
5029 11:05:37.477330 tx_first_pass[1][1][10] = 0
5030 11:05:37.480518 tx_last_pass[1][1][10] = 0
5031 11:05:37.483973 tx_win_center[1][1][11] = 0
5032 11:05:37.487098 tx_first_pass[1][1][11] = 0
5033 11:05:37.487183 tx_last_pass[1][1][11] = 0
5034 11:05:37.490340 tx_win_center[1][1][12] = 0
5035 11:05:37.493860 tx_first_pass[1][1][12] = 0
5036 11:05:37.496917 tx_last_pass[1][1][12] = 0
5037 11:05:37.500242 tx_win_center[1][1][13] = 0
5038 11:05:37.500327 tx_first_pass[1][1][13] = 0
5039 11:05:37.503694 tx_last_pass[1][1][13] = 0
5040 11:05:37.506723 tx_win_center[1][1][14] = 0
5041 11:05:37.510264 tx_first_pass[1][1][14] = 0
5042 11:05:37.510350 tx_last_pass[1][1][14] = 0
5043 11:05:37.513562 tx_win_center[1][1][15] = 0
5044 11:05:37.517094 tx_first_pass[1][1][15] = 0
5045 11:05:37.520092 tx_last_pass[1][1][15] = 0
5046 11:05:37.520178 dump params rx window
5047 11:05:37.523404 rx_firspass[0][0][0] = 0
5048 11:05:37.526349 rx_lastpass[0][0][0] = 0
5049 11:05:37.526434 rx_firspass[0][0][1] = 0
5050 11:05:37.529861 rx_lastpass[0][0][1] = 0
5051 11:05:37.533026 rx_firspass[0][0][2] = 0
5052 11:05:37.533111 rx_lastpass[0][0][2] = 0
5053 11:05:37.536294 rx_firspass[0][0][3] = 0
5054 11:05:37.539460 rx_lastpass[0][0][3] = 0
5055 11:05:37.539547 rx_firspass[0][0][4] = 0
5056 11:05:37.542861 rx_lastpass[0][0][4] = 0
5057 11:05:37.546179 rx_firspass[0][0][5] = 0
5058 11:05:37.549457 rx_lastpass[0][0][5] = 0
5059 11:05:37.549543 rx_firspass[0][0][6] = 0
5060 11:05:37.552723 rx_lastpass[0][0][6] = 0
5061 11:05:37.556027 rx_firspass[0][0][7] = 0
5062 11:05:37.556114 rx_lastpass[0][0][7] = 0
5063 11:05:37.559247 rx_firspass[0][0][8] = 0
5064 11:05:37.562455 rx_lastpass[0][0][8] = 0
5065 11:05:37.562541 rx_firspass[0][0][9] = 0
5066 11:05:37.565756 rx_lastpass[0][0][9] = 0
5067 11:05:37.569010 rx_firspass[0][0][10] = 0
5068 11:05:37.572263 rx_lastpass[0][0][10] = 0
5069 11:05:37.572349 rx_firspass[0][0][11] = 0
5070 11:05:37.575804 rx_lastpass[0][0][11] = 0
5071 11:05:37.578842 rx_firspass[0][0][12] = 0
5072 11:05:37.582011 rx_lastpass[0][0][12] = 0
5073 11:05:37.582098 rx_firspass[0][0][13] = 0
5074 11:05:37.585565 rx_lastpass[0][0][13] = 0
5075 11:05:37.588961 rx_firspass[0][0][14] = 0
5076 11:05:37.589042 rx_lastpass[0][0][14] = 0
5077 11:05:37.591854 rx_firspass[0][0][15] = 0
5078 11:05:37.595234 rx_lastpass[0][0][15] = 0
5079 11:05:37.598410 rx_firspass[0][1][0] = 0
5080 11:05:37.598538 rx_lastpass[0][1][0] = 0
5081 11:05:37.601749 rx_firspass[0][1][1] = 0
5082 11:05:37.605104 rx_lastpass[0][1][1] = 0
5083 11:05:37.605205 rx_firspass[0][1][2] = 0
5084 11:05:37.608204 rx_lastpass[0][1][2] = 0
5085 11:05:37.611615 rx_firspass[0][1][3] = 0
5086 11:05:37.611725 rx_lastpass[0][1][3] = 0
5087 11:05:37.615066 rx_firspass[0][1][4] = 0
5088 11:05:37.618109 rx_lastpass[0][1][4] = 0
5089 11:05:37.621658 rx_firspass[0][1][5] = 0
5090 11:05:37.621794 rx_lastpass[0][1][5] = 0
5091 11:05:37.624907 rx_firspass[0][1][6] = 0
5092 11:05:37.628201 rx_lastpass[0][1][6] = 0
5093 11:05:37.628287 rx_firspass[0][1][7] = 0
5094 11:05:37.631465 rx_lastpass[0][1][7] = 0
5095 11:05:37.634811 rx_firspass[0][1][8] = 0
5096 11:05:37.634895 rx_lastpass[0][1][8] = 0
5097 11:05:37.637910 rx_firspass[0][1][9] = 0
5098 11:05:37.641008 rx_lastpass[0][1][9] = 0
5099 11:05:37.644349 rx_firspass[0][1][10] = 0
5100 11:05:37.644449 rx_lastpass[0][1][10] = 0
5101 11:05:37.647758 rx_firspass[0][1][11] = 0
5102 11:05:37.651068 rx_lastpass[0][1][11] = 0
5103 11:05:37.651182 rx_firspass[0][1][12] = 0
5104 11:05:37.654259 rx_lastpass[0][1][12] = 0
5105 11:05:37.657621 rx_firspass[0][1][13] = 0
5106 11:05:37.660844 rx_lastpass[0][1][13] = 0
5107 11:05:37.660983 rx_firspass[0][1][14] = 0
5108 11:05:37.664026 rx_lastpass[0][1][14] = 0
5109 11:05:37.667633 rx_firspass[0][1][15] = 0
5110 11:05:37.667791 rx_lastpass[0][1][15] = 0
5111 11:05:37.670919 rx_firspass[1][0][0] = 0
5112 11:05:37.674151 rx_lastpass[1][0][0] = 0
5113 11:05:37.677408 rx_firspass[1][0][1] = 0
5114 11:05:37.677623 rx_lastpass[1][0][1] = 0
5115 11:05:37.680655 rx_firspass[1][0][2] = 0
5116 11:05:37.684314 rx_lastpass[1][0][2] = 0
5117 11:05:37.684569 rx_firspass[1][0][3] = 0
5118 11:05:37.687134 rx_lastpass[1][0][3] = 0
5119 11:05:37.690612 rx_firspass[1][0][4] = 0
5120 11:05:37.690984 rx_lastpass[1][0][4] = 0
5121 11:05:37.693867 rx_firspass[1][0][5] = 0
5122 11:05:37.697455 rx_lastpass[1][0][5] = 0
5123 11:05:37.700316 rx_firspass[1][0][6] = 0
5124 11:05:37.700708 rx_lastpass[1][0][6] = 0
5125 11:05:37.703784 rx_firspass[1][0][7] = 0
5126 11:05:37.707249 rx_lastpass[1][0][7] = 0
5127 11:05:37.707787 rx_firspass[1][0][8] = 0
5128 11:05:37.710615 rx_lastpass[1][0][8] = 0
5129 11:05:37.713885 rx_firspass[1][0][9] = 0
5130 11:05:37.714356 rx_lastpass[1][0][9] = 0
5131 11:05:37.716866 rx_firspass[1][0][10] = 0
5132 11:05:37.720134 rx_lastpass[1][0][10] = 0
5133 11:05:37.723293 rx_firspass[1][0][11] = 0
5134 11:05:37.723752 rx_lastpass[1][0][11] = 0
5135 11:05:37.726600 rx_firspass[1][0][12] = 0
5136 11:05:37.729973 rx_lastpass[1][0][12] = 0
5137 11:05:37.730378 rx_firspass[1][0][13] = 0
5138 11:05:37.733433 rx_lastpass[1][0][13] = 0
5139 11:05:37.736568 rx_firspass[1][0][14] = 0
5140 11:05:37.739756 rx_lastpass[1][0][14] = 0
5141 11:05:37.740149 rx_firspass[1][0][15] = 0
5142 11:05:37.743155 rx_lastpass[1][0][15] = 0
5143 11:05:37.746324 rx_firspass[1][1][0] = 0
5144 11:05:37.749504 rx_lastpass[1][1][0] = 0
5145 11:05:37.749894 rx_firspass[1][1][1] = 0
5146 11:05:37.752752 rx_lastpass[1][1][1] = 0
5147 11:05:37.755940 rx_firspass[1][1][2] = 0
5148 11:05:37.756283 rx_lastpass[1][1][2] = 0
5149 11:05:37.759531 rx_firspass[1][1][3] = 0
5150 11:05:37.762510 rx_lastpass[1][1][3] = 0
5151 11:05:37.762922 rx_firspass[1][1][4] = 0
5152 11:05:37.766019 rx_lastpass[1][1][4] = 0
5153 11:05:37.769302 rx_firspass[1][1][5] = 0
5154 11:05:37.769741 rx_lastpass[1][1][5] = 0
5155 11:05:37.772560 rx_firspass[1][1][6] = 0
5156 11:05:37.775717 rx_lastpass[1][1][6] = 0
5157 11:05:37.778879 rx_firspass[1][1][7] = 0
5158 11:05:37.779391 rx_lastpass[1][1][7] = 0
5159 11:05:37.782311 rx_firspass[1][1][8] = 0
5160 11:05:37.785453 rx_lastpass[1][1][8] = 0
5161 11:05:37.785845 rx_firspass[1][1][9] = 0
5162 11:05:37.788654 rx_lastpass[1][1][9] = 0
5163 11:05:37.792131 rx_firspass[1][1][10] = 0
5164 11:05:37.795558 rx_lastpass[1][1][10] = 0
5165 11:05:37.795947 rx_firspass[1][1][11] = 0
5166 11:05:37.798957 rx_lastpass[1][1][11] = 0
5167 11:05:37.802085 rx_firspass[1][1][12] = 0
5168 11:05:37.802550 rx_lastpass[1][1][12] = 0
5169 11:05:37.805481 rx_firspass[1][1][13] = 0
5170 11:05:37.808479 rx_lastpass[1][1][13] = 0
5171 11:05:37.812044 rx_firspass[1][1][14] = 0
5172 11:05:37.812602 rx_lastpass[1][1][14] = 0
5173 11:05:37.815101 rx_firspass[1][1][15] = 0
5174 11:05:37.818361 rx_lastpass[1][1][15] = 0
5175 11:05:37.818754 dump params clk_delay
5176 11:05:37.821630 clk_delay[0] = 0
5177 11:05:37.822019 clk_delay[1] = 0
5178 11:05:37.825217 dump params dqs_delay
5179 11:05:37.825606 dqs_delay[0][0] = 0
5180 11:05:37.827955 dqs_delay[0][1] = 0
5181 11:05:37.831395 dqs_delay[1][0] = 0
5182 11:05:37.831848 dqs_delay[1][1] = 0
5183 11:05:37.834710 dump params delay_cell_unit = 744
5184 11:05:37.837840 mt_set_emi_preloader end
5185 11:05:37.841593 [mt_mem_init] dram size: 0x100000000, rank number: 2
5186 11:05:37.847884 [complex_mem_test] start addr:0x40000000, len:20480
5187 11:05:37.883029 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5188 11:05:37.889363 [complex_mem_test] start addr:0x80000000, len:20480
5189 11:05:37.925318 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5190 11:05:37.931859 [complex_mem_test] start addr:0xc0000000, len:20480
5191 11:05:37.967886 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5192 11:05:37.974278 [complex_mem_test] start addr:0x56000000, len:8192
5193 11:05:37.990699 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5194 11:05:37.994022 ddr_geometry:1
5195 11:05:37.997282 [complex_mem_test] start addr:0x80000000, len:8192
5196 11:05:38.014528 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5197 11:05:38.017825 dram_init: dram init end (result: 0)
5198 11:05:38.024301 Successfully loaded DRAM blobs and ran DRAM calibration
5199 11:05:38.034535 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5200 11:05:38.034975 CBMEM:
5201 11:05:38.037461 IMD: root @ 00000000fffff000 254 entries.
5202 11:05:38.041033 IMD: root @ 00000000ffffec00 62 entries.
5203 11:05:38.047568 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5204 11:05:38.054063 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5205 11:05:38.057296 in-header: 03 a1 00 00 08 00 00 00
5206 11:05:38.060765 in-data: 84 60 60 10 00 00 00 00
5207 11:05:38.063838 Chrome EC: clear events_b mask to 0x0000000020004000
5208 11:05:38.070265 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5209 11:05:38.074204 in-header: 03 fd 00 00 00 00 00 00
5210 11:05:38.077407 in-data:
5211 11:05:38.080596 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5212 11:05:38.083980 CBFS @ 21000 size 3d4000
5213 11:05:38.087169 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5214 11:05:38.090467 CBFS: Locating 'fallback/ramstage'
5215 11:05:38.093831 CBFS: Found @ offset 10d40 size d563
5216 11:05:38.116491 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5217 11:05:38.128689 Accumulated console time in romstage 13623 ms
5218 11:05:38.129083
5219 11:05:38.129384
5220 11:05:38.138385 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5221 11:05:38.141636 ARM64: Exception handlers installed.
5222 11:05:38.142135 ARM64: Testing exception
5223 11:05:38.144851 ARM64: Done test exception
5224 11:05:38.148288 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5225 11:05:38.151680 Manufacturer: ef
5226 11:05:38.157902 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5227 11:05:38.161375 WARNING: RO_VPD is uninitialized or empty.
5228 11:05:38.164602 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5229 11:05:38.167982 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5230 11:05:38.178560 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5231 11:05:38.182034 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5232 11:05:38.188201 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5233 11:05:38.188593 Enumerating buses...
5234 11:05:38.194754 Show all devs... Before device enumeration.
5235 11:05:38.195150 Root Device: enabled 1
5236 11:05:38.197706 CPU_CLUSTER: 0: enabled 1
5237 11:05:38.201104 CPU: 00: enabled 1
5238 11:05:38.201490 Compare with tree...
5239 11:05:38.204372 Root Device: enabled 1
5240 11:05:38.204817 CPU_CLUSTER: 0: enabled 1
5241 11:05:38.207879 CPU: 00: enabled 1
5242 11:05:38.210779 Root Device scanning...
5243 11:05:38.214197 root_dev_scan_bus for Root Device
5244 11:05:38.214581 CPU_CLUSTER: 0 enabled
5245 11:05:38.217370 root_dev_scan_bus for Root Device done
5246 11:05:38.223910 scan_bus: scanning of bus Root Device took 10688 usecs
5247 11:05:38.224299 done
5248 11:05:38.227201 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5249 11:05:38.230469 Allocating resources...
5250 11:05:38.233930 Reading resources...
5251 11:05:38.237165 Root Device read_resources bus 0 link: 0
5252 11:05:38.240724 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5253 11:05:38.243819 CPU: 00 missing read_resources
5254 11:05:38.247090 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5255 11:05:38.250402 Root Device read_resources bus 0 link: 0 done
5256 11:05:38.253473 Done reading resources.
5257 11:05:38.257079 Show resources in subtree (Root Device)...After reading.
5258 11:05:38.263694 Root Device child on link 0 CPU_CLUSTER: 0
5259 11:05:38.266956 CPU_CLUSTER: 0 child on link 0 CPU: 00
5260 11:05:38.273258 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5261 11:05:38.276512 CPU: 00
5262 11:05:38.276907 Setting resources...
5263 11:05:38.282808 Root Device assign_resources, bus 0 link: 0
5264 11:05:38.286298 CPU_CLUSTER: 0 missing set_resources
5265 11:05:38.289626 Root Device assign_resources, bus 0 link: 0
5266 11:05:38.290059 Done setting resources.
5267 11:05:38.296068 Show resources in subtree (Root Device)...After assigning values.
5268 11:05:38.299402 Root Device child on link 0 CPU_CLUSTER: 0
5269 11:05:38.302465 CPU_CLUSTER: 0 child on link 0 CPU: 00
5270 11:05:38.312426 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5271 11:05:38.312816 CPU: 00
5272 11:05:38.315519 Done allocating resources.
5273 11:05:38.322198 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5274 11:05:38.322585 Enabling resources...
5275 11:05:38.322939 done.
5276 11:05:38.328626 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5277 11:05:38.329069 Initializing devices...
5278 11:05:38.332019 Root Device init ...
5279 11:05:38.335451 mainboard_init: Starting display init.
5280 11:05:38.338431 ADC[4]: Raw value=76192 ID=0
5281 11:05:38.361013 anx7625_power_on_init: Init interface.
5282 11:05:38.364470 anx7625_disable_pd_protocol: Disabled PD feature.
5283 11:05:38.370703 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5284 11:05:38.427817 anx7625_start_dp_work: Secure OCM version=00
5285 11:05:38.431235 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5286 11:05:38.448438 sp_tx_get_edid_block: EDID Block = 1
5287 11:05:38.565817 Extracted contents:
5288 11:05:38.568990 header: 00 ff ff ff ff ff ff 00
5289 11:05:38.572342 serial number: 06 af 5c 14 00 00 00 00 00 1a
5290 11:05:38.575674 version: 01 04
5291 11:05:38.578623 basic params: 95 1a 0e 78 02
5292 11:05:38.581899 chroma info: 99 85 95 55 56 92 28 22 50 54
5293 11:05:38.585384 established: 00 00 00
5294 11:05:38.591915 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5295 11:05:38.598680 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5296 11:05:38.601835 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5297 11:05:38.608266 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5298 11:05:38.614762 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5299 11:05:38.618010 extensions: 00
5300 11:05:38.618400 checksum: ae
5301 11:05:38.618749
5302 11:05:38.624506 Manufacturer: AUO Model 145c Serial Number 0
5303 11:05:38.624894 Made week 0 of 2016
5304 11:05:38.627798 EDID version: 1.4
5305 11:05:38.628186 Digital display
5306 11:05:38.631010 6 bits per primary color channel
5307 11:05:38.634418 DisplayPort interface
5308 11:05:38.637546 Maximum image size: 26 cm x 14 cm
5309 11:05:38.637932 Gamma: 220%
5310 11:05:38.638236 Check DPMS levels
5311 11:05:38.640887 Supported color formats: RGB 4:4:4
5312 11:05:38.644121 First detailed timing is preferred timing
5313 11:05:38.647786 Established timings supported:
5314 11:05:38.650799 Standard timings supported:
5315 11:05:38.654022 Detailed timings
5316 11:05:38.657497 Hex of detail: ce1d56ea50001a3030204600009010000018
5317 11:05:38.660954 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5318 11:05:38.667325 0556 0586 05a6 0640 hborder 0
5319 11:05:38.670610 0300 0304 030a 031a vborder 0
5320 11:05:38.673766 -hsync -vsync
5321 11:05:38.674155 Did detailed timing
5322 11:05:38.680414 Hex of detail: 0000000f0000000000000000000000000020
5323 11:05:38.683509 Manufacturer-specified data, tag 15
5324 11:05:38.686679 Hex of detail: 000000fe0041554f0a202020202020202020
5325 11:05:38.690100 ASCII string: AUO
5326 11:05:38.693718 Hex of detail: 000000fe004231313658414230312e34200a
5327 11:05:38.696919 ASCII string: B116XAB01.4
5328 11:05:38.697307 Checksum
5329 11:05:38.700244 Checksum: 0xae (valid)
5330 11:05:38.703345 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5331 11:05:38.706549 DSI data_rate: 457800000 bps
5332 11:05:38.713264 anx7625_parse_edid: set default k value to 0x3d for panel
5333 11:05:38.716494 anx7625_parse_edid: pixelclock(76300).
5334 11:05:38.719565 hactive(1366), hsync(32), hfp(48), hbp(154)
5335 11:05:38.723178 vactive(768), vsync(6), vfp(4), vbp(16)
5336 11:05:38.726442 anx7625_dsi_config: config dsi.
5337 11:05:38.733895 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5338 11:05:38.755012 anx7625_dsi_config: success to config DSI
5339 11:05:38.758101 anx7625_dp_start: MIPI phy setup OK.
5340 11:05:38.761507 [SSUSB] Setting up USB HOST controller...
5341 11:05:38.764754 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5342 11:05:38.768030 [SSUSB] phy power-on done.
5343 11:05:38.771191 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5344 11:05:38.774597 in-header: 03 fc 01 00 00 00 00 00
5345 11:05:38.775048 in-data:
5346 11:05:38.781287 handle_proto3_response: EC response with error code: 1
5347 11:05:38.781697 SPM: pcm index = 1
5348 11:05:38.787542 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5349 11:05:38.787944 CBFS @ 21000 size 3d4000
5350 11:05:38.794430 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5351 11:05:38.797725 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5352 11:05:38.800709 CBFS: Found @ offset 1e7c0 size 1026
5353 11:05:38.807825 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5354 11:05:38.810798 SPM: binary array size = 2988
5355 11:05:38.814384 SPM: version = pcm_allinone_v1.17.2_20180829
5356 11:05:38.817661 SPM binary loaded in 32 msecs
5357 11:05:38.826187 spm_kick_im_to_fetch: ptr = 000000004021eec2
5358 11:05:38.829307 spm_kick_im_to_fetch: len = 2988
5359 11:05:38.829743 SPM: spm_kick_pcm_to_run
5360 11:05:38.832815 SPM: spm_kick_pcm_to_run done
5361 11:05:38.835803 SPM: spm_init done in 52 msecs
5362 11:05:38.839252 Root Device init finished in 505415 usecs
5363 11:05:38.842486 CPU_CLUSTER: 0 init ...
5364 11:05:38.852317 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5365 11:05:38.855764 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5366 11:05:38.859168 CBFS @ 21000 size 3d4000
5367 11:05:38.862421 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5368 11:05:38.865441 CBFS: Locating 'sspm.bin'
5369 11:05:38.868456 CBFS: Found @ offset 208c0 size 41cb
5370 11:05:38.879443 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5371 11:05:38.887207 CPU_CLUSTER: 0 init finished in 42801 usecs
5372 11:05:38.887634 Devices initialized
5373 11:05:38.890766 Show all devs... After init.
5374 11:05:38.894003 Root Device: enabled 1
5375 11:05:38.894389 CPU_CLUSTER: 0: enabled 1
5376 11:05:38.897024 CPU: 00: enabled 1
5377 11:05:38.900385 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5378 11:05:38.906859 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5379 11:05:38.910063 ELOG: NV offset 0x558000 size 0x1000
5380 11:05:38.913590 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5381 11:05:38.919919 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5382 11:05:38.926634 ELOG: Event(17) added with size 13 at 2024-07-10 11:05:38 UTC
5383 11:05:38.929747 out: cmd=0x121: 03 db 21 01 00 00 00 00
5384 11:05:38.933140 in-header: 03 1b 00 00 2c 00 00 00
5385 11:05:38.946139 in-data: 56 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 44 8c 01 00 0a 00 00 00 51 35 01 00 06 80 00 00 47 04 00 00 06 80 00 00 84 df 61 00
5386 11:05:38.949623 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5387 11:05:38.952560 in-header: 03 19 00 00 08 00 00 00
5388 11:05:38.956122 in-data: a2 e0 47 00 13 00 00 00
5389 11:05:38.959134 Chrome EC: UHEPI supported
5390 11:05:38.965743 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5391 11:05:38.968973 in-header: 03 e1 00 00 08 00 00 00
5392 11:05:38.972245 in-data: 84 20 60 10 00 00 00 00
5393 11:05:38.975569 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5394 11:05:38.982265 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5395 11:05:38.985627 in-header: 03 e1 00 00 08 00 00 00
5396 11:05:38.989137 in-data: 84 20 60 10 00 00 00 00
5397 11:05:38.995443 ELOG: Event(A1) added with size 10 at 2024-07-10 11:05:38 UTC
5398 11:05:39.001847 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5399 11:05:39.004965 ELOG: Event(A0) added with size 9 at 2024-07-10 11:05:38 UTC
5400 11:05:39.008174 elog_add_boot_reason: Logged dev mode boot
5401 11:05:39.011430 Finalize devices...
5402 11:05:39.014783 Devices finalized
5403 11:05:39.018201 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5404 11:05:39.021372 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5405 11:05:39.028198 ELOG: Event(91) added with size 10 at 2024-07-10 11:05:38 UTC
5406 11:05:39.031261 Writing coreboot table at 0xffeda000
5407 11:05:39.034621 0. 0000000000114000-000000000011efff: RAMSTAGE
5408 11:05:39.040959 1. 0000000040000000-000000004023cfff: RAMSTAGE
5409 11:05:39.044315 2. 000000004023d000-00000000545fffff: RAM
5410 11:05:39.047624 3. 0000000054600000-000000005465ffff: BL31
5411 11:05:39.051086 4. 0000000054660000-00000000ffed9fff: RAM
5412 11:05:39.057869 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5413 11:05:39.061539 6. 0000000100000000-000000013fffffff: RAM
5414 11:05:39.064037 Passing 5 GPIOs to payload:
5415 11:05:39.067215 NAME | PORT | POLARITY | VALUE
5416 11:05:39.074197 write protect | 0x00000096 | low | high
5417 11:05:39.076979 EC in RW | 0x000000b1 | high | undefined
5418 11:05:39.080345 EC interrupt | 0x00000097 | low | undefined
5419 11:05:39.086954 TPM interrupt | 0x00000099 | high | undefined
5420 11:05:39.090141 speaker enable | 0x000000af | high | undefined
5421 11:05:39.093337 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5422 11:05:39.096636 in-header: 03 f7 00 00 02 00 00 00
5423 11:05:39.099976 in-data: 04 00
5424 11:05:39.100365 Board ID: 4
5425 11:05:39.103279 ADC[3]: Raw value=215404 ID=1
5426 11:05:39.103696 RAM code: 1
5427 11:05:39.106847 SKU ID: 16
5428 11:05:39.110006 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5429 11:05:39.113197 CBFS @ 21000 size 3d4000
5430 11:05:39.116318 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5431 11:05:39.123067 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum dcb2
5432 11:05:39.126208 coreboot table: 940 bytes.
5433 11:05:39.129294 IMD ROOT 0. 00000000fffff000 00001000
5434 11:05:39.132965 IMD SMALL 1. 00000000ffffe000 00001000
5435 11:05:39.136158 CONSOLE 2. 00000000fffde000 00020000
5436 11:05:39.139355 FMAP 3. 00000000fffdd000 0000047c
5437 11:05:39.142683 TIME STAMP 4. 00000000fffdc000 00000910
5438 11:05:39.149202 RAMOOPS 5. 00000000ffedc000 00100000
5439 11:05:39.152222 COREBOOT 6. 00000000ffeda000 00002000
5440 11:05:39.152685 IMD small region:
5441 11:05:39.155561 IMD ROOT 0. 00000000ffffec00 00000400
5442 11:05:39.159110 VBOOT WORK 1. 00000000ffffeb00 00000100
5443 11:05:39.165618 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5444 11:05:39.168734 VPD 3. 00000000ffffea60 0000006c
5445 11:05:39.171932 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5446 11:05:39.178893 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5447 11:05:39.181715 in-header: 03 e1 00 00 08 00 00 00
5448 11:05:39.185186 in-data: 84 20 60 10 00 00 00 00
5449 11:05:39.191847 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5450 11:05:39.192371 CBFS @ 21000 size 3d4000
5451 11:05:39.198159 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5452 11:05:39.201428 CBFS: Locating 'fallback/payload'
5453 11:05:39.209073 CBFS: Found @ offset dc040 size 439a0
5454 11:05:39.296585 read SPI 0xfd078 0x439a0: 84380 us, 3281 KB/s, 26.248 Mbps
5455 11:05:39.303229 Checking segment from ROM address 0x0000000040003a00
5456 11:05:39.306537 Checking segment from ROM address 0x0000000040003a1c
5457 11:05:39.310059 Loading segment from ROM address 0x0000000040003a00
5458 11:05:39.312928 code (compression=0)
5459 11:05:39.322992 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5460 11:05:39.329496 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5461 11:05:39.332631 it's not compressed!
5462 11:05:39.335903 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5463 11:05:39.342460 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5464 11:05:39.351165 Loading segment from ROM address 0x0000000040003a1c
5465 11:05:39.354638 Entry Point 0x0000000080000000
5466 11:05:39.355029 Loaded segments
5467 11:05:39.360994 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5468 11:05:39.364301 Jumping to boot code at 0000000080000000(00000000ffeda000)
5469 11:05:39.374006 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5470 11:05:39.380577 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5471 11:05:39.381059 CBFS @ 21000 size 3d4000
5472 11:05:39.387088 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5473 11:05:39.390344 CBFS: Locating 'fallback/bl31'
5474 11:05:39.393363 CBFS: Found @ offset 36dc0 size 5820
5475 11:05:39.404962 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5476 11:05:39.408079 Checking segment from ROM address 0x0000000040003a00
5477 11:05:39.414781 Checking segment from ROM address 0x0000000040003a1c
5478 11:05:39.418172 Loading segment from ROM address 0x0000000040003a00
5479 11:05:39.421323 code (compression=1)
5480 11:05:39.431450 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5481 11:05:39.437594 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5482 11:05:39.437986 using LZMA
5483 11:05:39.447008 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5484 11:05:39.453266 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5485 11:05:39.456684 Loading segment from ROM address 0x0000000040003a1c
5486 11:05:39.459441 Entry Point 0x0000000054601000
5487 11:05:39.459536 Loaded segments
5488 11:05:39.462536 NOTICE: MT8183 bl31_setup
5489 11:05:39.470106 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5490 11:05:39.473336 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5491 11:05:39.476576 INFO: [DEVAPC] dump DEVAPC registers:
5492 11:05:39.486616 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5493 11:05:39.493044 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5494 11:05:39.503085 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5495 11:05:39.509337 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5496 11:05:39.519777 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5497 11:05:39.526258 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5498 11:05:39.536307 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5499 11:05:39.542881 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5500 11:05:39.552282 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5501 11:05:39.558955 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5502 11:05:39.568877 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5503 11:05:39.575204 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5504 11:05:39.585082 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5505 11:05:39.591718 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5506 11:05:39.598482 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5507 11:05:39.608092 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5508 11:05:39.614592 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5509 11:05:39.621189 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5510 11:05:39.627963 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5511 11:05:39.634258 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5512 11:05:39.644124 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5513 11:05:39.650772 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5514 11:05:39.654373 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5515 11:05:39.657585 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5516 11:05:39.660982 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5517 11:05:39.663836 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5518 11:05:39.667283 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5519 11:05:39.673766 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5520 11:05:39.676818 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5521 11:05:39.680435 WARNING: region 0:
5522 11:05:39.683785 WARNING: apc:0x168, sa:0x0, ea:0xfff
5523 11:05:39.684173 WARNING: region 1:
5524 11:05:39.690008 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5525 11:05:39.690397 WARNING: region 2:
5526 11:05:39.693175 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5527 11:05:39.696553 WARNING: region 3:
5528 11:05:39.700263 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5529 11:05:39.700652 WARNING: region 4:
5530 11:05:39.706360 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5531 11:05:39.706751 WARNING: region 5:
5532 11:05:39.709595 WARNING: apc:0x0, sa:0x0, ea:0x0
5533 11:05:39.713046 WARNING: region 6:
5534 11:05:39.716023 WARNING: apc:0x0, sa:0x0, ea:0x0
5535 11:05:39.716415 WARNING: region 7:
5536 11:05:39.719397 WARNING: apc:0x0, sa:0x0, ea:0x0
5537 11:05:39.726043 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5538 11:05:39.729259 INFO: SPM: enable SPMC mode
5539 11:05:39.732586 NOTICE: spm_boot_init() start
5540 11:05:39.735731 NOTICE: spm_boot_init() end
5541 11:05:39.739367 INFO: BL31: Initializing runtime services
5542 11:05:39.745767 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5543 11:05:39.748950 INFO: BL31: Preparing for EL3 exit to normal world
5544 11:05:39.752285 INFO: Entry point address = 0x80000000
5545 11:05:39.755643 INFO: SPSR = 0x8
5546 11:05:39.777277
5547 11:05:39.777665
5548 11:05:39.777965
5549 11:05:39.779517 end: 2.2.3 depthcharge-start (duration 00:00:24) [common]
5550 11:05:39.779966 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5551 11:05:39.780391 Setting prompt string to ['jacuzzi:']
5552 11:05:39.780738 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5553 11:05:39.781328 Starting depthcharge on Juniper...
5554 11:05:39.781644
5555 11:05:39.783840 vboot_handoff: creating legacy vboot_handoff structure
5556 11:05:39.784230
5557 11:05:39.786880 ec_init(0): CrosEC protocol v3 supported (544, 544)
5558 11:05:39.790047
5559 11:05:39.790434 Wipe memory regions:
5560 11:05:39.790738
5561 11:05:39.793569 [0x00000040000000, 0x00000054600000)
5562 11:05:39.836305
5563 11:05:39.836698 [0x00000054660000, 0x00000080000000)
5564 11:05:39.927723
5565 11:05:39.928147 [0x000000811994a0, 0x000000ffeda000)
5566 11:05:40.187589
5567 11:05:40.190432 [0x00000100000000, 0x00000140000000)
5568 11:05:40.319822
5569 11:05:40.322979 Initializing XHCI USB controller at 0x11200000.
5570 11:05:40.346313
5571 11:05:40.349380 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5572 11:05:40.349770
5573 11:05:40.350072
5574 11:05:40.350704 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5575 11:05:40.351047 Sending line: 'tftpboot 192.168.201.1 14786775/tftp-deploy-d4n7v1xj/kernel/image.itb 14786775/tftp-deploy-d4n7v1xj/kernel/cmdline '
5577 11:05:40.452319 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5578 11:05:40.452746 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
5579 11:05:40.456959 jacuzzi: tftpboot 192.168.201.1 14786775/tftp-deploy-d4n7v1xj/kernel/image.itp-deploy-d4n7v1xj/kernel/cmdline
5580 11:05:40.457381
5581 11:05:40.457828 Waiting for link
5582 11:05:40.859764
5583 11:05:40.859905 R8152: Initializing
5584 11:05:40.859972
5585 11:05:40.862892 Version 9 (ocp_data = 6010)
5586 11:05:40.862978
5587 11:05:40.866541 R8152: Done initializing
5588 11:05:40.866698
5589 11:05:40.866779 Adding net device
5590 11:05:41.251980
5591 11:05:41.252121 done.
5592 11:05:41.252187
5593 11:05:41.252248 MAC: 00:e0:4c:78:85:cb
5594 11:05:41.252306
5595 11:05:41.255227 Sending DHCP discover... done.
5596 11:05:41.255312
5597 11:05:41.258473 Waiting for reply... done.
5598 11:05:41.258565
5599 11:05:41.261808 Sending DHCP request... done.
5600 11:05:41.261907
5601 11:05:41.267103 Waiting for reply... done.
5602 11:05:41.267519
5603 11:05:41.267866 My ip is 192.168.201.22
5604 11:05:41.268192
5605 11:05:41.270363 The DHCP server ip is 192.168.201.1
5606 11:05:41.270890
5607 11:05:41.277281 TFTP server IP predefined by user: 192.168.201.1
5608 11:05:41.277672
5609 11:05:41.283426 Bootfile predefined by user: 14786775/tftp-deploy-d4n7v1xj/kernel/image.itb
5610 11:05:41.283853
5611 11:05:41.287048 Sending tftp read request... done.
5612 11:05:41.287488
5613 11:05:41.293773 Waiting for the transfer...
5614 11:05:41.294204
5615 11:05:41.620095 00000000 ################################################################
5616 11:05:41.620233
5617 11:05:41.870990 00080000 ################################################################
5618 11:05:41.871127
5619 11:05:42.130325 00100000 ################################################################
5620 11:05:42.130494
5621 11:05:42.389978 00180000 ################################################################
5622 11:05:42.390103
5623 11:05:42.654393 00200000 ################################################################
5624 11:05:42.654517
5625 11:05:42.910837 00280000 ################################################################
5626 11:05:42.910970
5627 11:05:43.173628 00300000 ################################################################
5628 11:05:43.173789
5629 11:05:43.439904 00380000 ################################################################
5630 11:05:43.440037
5631 11:05:43.711360 00400000 ################################################################
5632 11:05:43.711491
5633 11:05:43.975656 00480000 ################################################################
5634 11:05:43.975799
5635 11:05:44.254736 00500000 ################################################################
5636 11:05:44.254860
5637 11:05:44.509826 00580000 ################################################################
5638 11:05:44.509948
5639 11:05:44.783201 00600000 ################################################################
5640 11:05:44.783325
5641 11:05:45.054614 00680000 ################################################################
5642 11:05:45.054748
5643 11:05:45.334892 00700000 ################################################################
5644 11:05:45.335031
5645 11:05:45.609042 00780000 ################################################################
5646 11:05:45.609164
5647 11:05:45.887069 00800000 ################################################################
5648 11:05:45.887191
5649 11:05:46.169515 00880000 ################################################################
5650 11:05:46.169636
5651 11:05:46.453999 00900000 ################################################################
5652 11:05:46.454136
5653 11:05:46.736767 00980000 ################################################################
5654 11:05:46.736892
5655 11:05:47.022113 00a00000 ################################################################
5656 11:05:47.022238
5657 11:05:47.301098 00a80000 ################################################################
5658 11:05:47.301248
5659 11:05:47.578735 00b00000 ################################################################
5660 11:05:47.578869
5661 11:05:47.852943 00b80000 ################################################################
5662 11:05:47.853074
5663 11:05:48.125615 00c00000 ################################################################
5664 11:05:48.125737
5665 11:05:48.397113 00c80000 ################################################################
5666 11:05:48.397234
5667 11:05:48.671843 00d00000 ################################################################
5668 11:05:48.671972
5669 11:05:48.971082 00d80000 ################################################################
5670 11:05:48.971217
5671 11:05:49.272391 00e00000 ################################################################
5672 11:05:49.272517
5673 11:05:49.574390 00e80000 ################################################################
5674 11:05:49.574518
5675 11:05:49.871984 00f00000 ################################################################
5676 11:05:49.872114
5677 11:05:50.168571 00f80000 ################################################################
5678 11:05:50.168705
5679 11:05:50.452268 01000000 ################################################################
5680 11:05:50.452404
5681 11:05:50.740847 01080000 ################################################################
5682 11:05:50.740972
5683 11:05:51.040831 01100000 ################################################################
5684 11:05:51.040969
5685 11:05:51.323823 01180000 ################################################################
5686 11:05:51.323958
5687 11:05:51.587087 01200000 ################################################################
5688 11:05:51.587218
5689 11:05:51.866160 01280000 ################################################################
5690 11:05:51.866287
5691 11:05:52.166313 01300000 ################################################################
5692 11:05:52.166445
5693 11:05:52.463887 01380000 ################################################################
5694 11:05:52.464022
5695 11:05:52.740903 01400000 ################################################################
5696 11:05:52.741033
5697 11:05:53.028287 01480000 ################################################################
5698 11:05:53.028415
5699 11:05:53.321396 01500000 ################################################################
5700 11:05:53.321523
5701 11:05:53.613236 01580000 ################################################################
5702 11:05:53.613368
5703 11:05:53.901555 01600000 ################################################################
5704 11:05:53.901720
5705 11:05:54.200205 01680000 ################################################################
5706 11:05:54.200334
5707 11:05:54.483589 01700000 ################################################################
5708 11:05:54.483723
5709 11:05:54.778915 01780000 ################################################################
5710 11:05:54.779042
5711 11:05:55.041481 01800000 ################################################################
5712 11:05:55.041600
5713 11:05:55.298311 01880000 ################################################################
5714 11:05:55.298444
5715 11:05:55.582876 01900000 ################################################################
5716 11:05:55.583003
5717 11:05:55.875174 01980000 ################################################################
5718 11:05:55.875314
5719 11:05:56.152891 01a00000 ################################################################
5720 11:05:56.153023
5721 11:05:56.414750 01a80000 ################################################################
5722 11:05:56.414874
5723 11:05:56.681189 01b00000 ################################################################
5724 11:05:56.681326
5725 11:05:56.942041 01b80000 ################################################################
5726 11:05:56.942160
5727 11:05:57.200758 01c00000 ################################################################
5728 11:05:57.200890
5729 11:05:57.466449 01c80000 ################################################################
5730 11:05:57.466598
5731 11:05:57.725791 01d00000 ################################################################
5732 11:05:57.725914
5733 11:05:57.984184 01d80000 ################################################################
5734 11:05:57.984326
5735 11:05:58.202712 01e00000 ##################################################### done.
5736 11:05:58.202840
5737 11:05:58.206065 The bootfile was 31885634 bytes long.
5738 11:05:58.206153
5739 11:05:58.209355 Sending tftp read request... done.
5740 11:05:58.209444
5741 11:05:58.212562 Waiting for the transfer...
5742 11:05:58.212649
5743 11:05:58.212715 00000000 # done.
5744 11:05:58.212779
5745 11:05:58.222553 Command line loaded dynamically from TFTP file: 14786775/tftp-deploy-d4n7v1xj/kernel/cmdline
5746 11:05:58.222642
5747 11:05:58.248799 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786775/extract-nfsrootfs-q4z8imh0,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5748 11:05:58.248907
5749 11:05:58.248977 Loading FIT.
5750 11:05:58.249039
5751 11:05:58.252284 Image ramdisk-1 has 18709639 bytes.
5752 11:05:58.252370
5753 11:05:58.255168 Image fdt-1 has 57695 bytes.
5754 11:05:58.255285
5755 11:05:58.258562 Image kernel-1 has 13116259 bytes.
5756 11:05:58.258649
5757 11:05:58.264790 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5758 11:05:58.264878
5759 11:05:58.278542 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5760 11:05:58.278631
5761 11:05:58.284466 Choosing best match conf-1 for compat google,juniper-sku16.
5762 11:05:58.284553
5763 11:05:58.291628 Connected to device vid:did:rid of 1ae0:0028:00
5764 11:05:58.298944
5765 11:05:58.302192 tpm_get_response: command 0x17b, return code 0x0
5766 11:05:58.302279
5767 11:05:58.305258 tpm_cleanup: add release locality here.
5768 11:05:58.305345
5769 11:05:58.308648 Shutting down all USB controllers.
5770 11:05:58.308733
5771 11:05:58.311867 Removing current net device
5772 11:05:58.311960
5773 11:05:58.315076 Exiting depthcharge with code 4 at timestamp: 35788792
5774 11:05:58.315162
5775 11:05:58.321692 LZMA decompressing kernel-1 to 0x80193568
5776 11:05:58.321778
5777 11:05:58.325199 LZMA decompressing kernel-1 to 0x40000000
5778 11:06:00.188360
5779 11:06:00.188480 jumping to kernel
5780 11:06:00.188958 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5781 11:06:00.189060 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
5782 11:06:00.189135 Setting prompt string to ['Linux version [0-9]']
5783 11:06:00.189249 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5784 11:06:00.189352 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5785 11:06:00.263123
5786 11:06:00.266547 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5787 11:06:00.269813 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
5788 11:06:00.269939 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5789 11:06:00.270042 Setting prompt string to []
5790 11:06:00.270155 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5791 11:06:00.270264 Using line separator: #'\n'#
5792 11:06:00.270353 No login prompt set.
5793 11:06:00.270445 Parsing kernel messages
5794 11:06:00.270538 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5795 11:06:00.270651 [login-action] Waiting for messages, (timeout 00:04:06)
5796 11:06:00.270716 Waiting using forced prompt support (timeout 00:02:03)
5797 11:06:00.289543 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
5798 11:06:00.292632 [ 0.000000] random: crng init done
5799 11:06:00.295918 [ 0.000000] Machine model: Google juniper sku16 board
5800 11:06:00.299381 [ 0.000000] efi: UEFI not found.
5801 11:06:00.309059 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5802 11:06:00.315811 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5803 11:06:00.325823 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5804 11:06:00.328709 [ 0.000000] printk: bootconsole [mtk8250] enabled
5805 11:06:00.337116 [ 0.000000] NUMA: No NUMA configuration found
5806 11:06:00.343727 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5807 11:06:00.350660 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5808 11:06:00.353580 [ 0.000000] Zone ranges:
5809 11:06:00.356900 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5810 11:06:00.359866 [ 0.000000] DMA32 empty
5811 11:06:00.366615 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5812 11:06:00.369680 [ 0.000000] Movable zone start for each node
5813 11:06:00.376460 [ 0.000000] Early memory node ranges
5814 11:06:00.379591 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5815 11:06:00.386198 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5816 11:06:00.392682 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5817 11:06:00.399281 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5818 11:06:00.405710 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5819 11:06:00.412608 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5820 11:06:00.433719 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5821 11:06:00.440505 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5822 11:06:00.446633 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5823 11:06:00.450075 [ 0.000000] psci: probing for conduit method from DT.
5824 11:06:00.456540 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5825 11:06:00.459929 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5826 11:06:00.466336 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5827 11:06:00.469486 [ 0.000000] psci: SMC Calling Convention v1.1
5828 11:06:00.476064 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5829 11:06:00.479378 [ 0.000000] Detected VIPT I-cache on CPU0
5830 11:06:00.486018 [ 0.000000] CPU features: detected: GIC system register CPU interface
5831 11:06:00.492753 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5832 11:06:00.499179 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5833 11:06:00.505714 [ 0.000000] CPU features: detected: ARM erratum 845719
5834 11:06:00.508946 [ 0.000000] alternatives: applying boot alternatives
5835 11:06:00.515564 [ 0.000000] Fallback order for Node 0: 0
5836 11:06:00.522284 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5837 11:06:00.525697 [ 0.000000] Policy zone: Normal
5838 11:06:00.551493 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786775/extract-nfsrootfs-q4z8imh0,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5839 11:06:00.564842 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5840 11:06:00.571156 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5841 11:06:00.581320 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5842 11:06:00.587888 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5843 11:06:00.590920 <6>[ 0.000000] software IO TLB: area num 8.
5844 11:06:00.617654 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5845 11:06:00.675596 <6>[ 0.000000] Memory: 3896800K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 261664K reserved, 32768K cma-reserved)
5846 11:06:00.682294 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5847 11:06:00.688540 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5848 11:06:00.691858 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5849 11:06:00.698558 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5850 11:06:00.705320 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5851 11:06:00.711721 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5852 11:06:00.718219 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5853 11:06:00.724791 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5854 11:06:00.731279 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5855 11:06:00.740839 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5856 11:06:00.747566 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5857 11:06:00.750803 <6>[ 0.000000] GICv3: 640 SPIs implemented
5858 11:06:00.754004 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5859 11:06:00.760760 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5860 11:06:00.764086 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5861 11:06:00.770735 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5862 11:06:00.783406 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5863 11:06:00.793297 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5864 11:06:00.803091 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5865 11:06:00.812753 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5866 11:06:00.825789 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5867 11:06:00.832259 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5868 11:06:00.839253 <6>[ 0.009464] Console: colour dummy device 80x25
5869 11:06:00.842559 <6>[ 0.014500] printk: console [tty1] enabled
5870 11:06:00.855791 <6>[ 0.018892] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5871 11:06:00.859164 <6>[ 0.029357] pid_max: default: 32768 minimum: 301
5872 11:06:00.865701 <6>[ 0.034237] LSM: Security Framework initializing
5873 11:06:00.872044 <6>[ 0.039151] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5874 11:06:00.878581 <6>[ 0.046773] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5875 11:06:00.885497 <4>[ 0.055651] cacheinfo: Unable to detect cache hierarchy for CPU 0
5876 11:06:00.895406 <6>[ 0.062276] cblist_init_generic: Setting adjustable number of callback queues.
5877 11:06:00.902064 <6>[ 0.069722] cblist_init_generic: Setting shift to 3 and lim to 1.
5878 11:06:00.908541 <6>[ 0.076075] cblist_init_generic: Setting adjustable number of callback queues.
5879 11:06:00.915181 <6>[ 0.083520] cblist_init_generic: Setting shift to 3 and lim to 1.
5880 11:06:00.918544 <6>[ 0.089919] rcu: Hierarchical SRCU implementation.
5881 11:06:00.924759 <6>[ 0.094945] rcu: Max phase no-delay instances is 1000.
5882 11:06:00.932702 <6>[ 0.102852] EFI services will not be available.
5883 11:06:00.935795 <6>[ 0.107802] smp: Bringing up secondary CPUs ...
5884 11:06:00.946516 <6>[ 0.113095] Detected VIPT I-cache on CPU1
5885 11:06:00.953334 <4>[ 0.113143] cacheinfo: Unable to detect cache hierarchy for CPU 1
5886 11:06:00.959572 <6>[ 0.113151] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5887 11:06:00.966547 <6>[ 0.113183] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5888 11:06:00.969428 <6>[ 0.113663] Detected VIPT I-cache on CPU2
5889 11:06:00.976023 <4>[ 0.113697] cacheinfo: Unable to detect cache hierarchy for CPU 2
5890 11:06:00.982586 <6>[ 0.113702] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5891 11:06:00.989178 <6>[ 0.113714] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5892 11:06:00.995747 <6>[ 0.114160] Detected VIPT I-cache on CPU3
5893 11:06:01.002202 <4>[ 0.114190] cacheinfo: Unable to detect cache hierarchy for CPU 3
5894 11:06:01.009127 <6>[ 0.114195] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5895 11:06:01.015293 <6>[ 0.114206] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5896 11:06:01.018580 <6>[ 0.114781] CPU features: detected: Spectre-v2
5897 11:06:01.024989 <6>[ 0.114791] CPU features: detected: Spectre-BHB
5898 11:06:01.028465 <6>[ 0.114794] CPU features: detected: ARM erratum 858921
5899 11:06:01.034999 <6>[ 0.114800] Detected VIPT I-cache on CPU4
5900 11:06:01.041583 <4>[ 0.114848] cacheinfo: Unable to detect cache hierarchy for CPU 4
5901 11:06:01.048141 <6>[ 0.114855] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5902 11:06:01.054473 <6>[ 0.114863] arch_timer: Enabling local workaround for ARM erratum 858921
5903 11:06:01.061604 <6>[ 0.114874] arch_timer: CPU4: Trapping CNTVCT access
5904 11:06:01.067539 <6>[ 0.114882] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5905 11:06:01.071224 <6>[ 0.115368] Detected VIPT I-cache on CPU5
5906 11:06:01.077418 <4>[ 0.115408] cacheinfo: Unable to detect cache hierarchy for CPU 5
5907 11:06:01.084174 <6>[ 0.115414] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5908 11:06:01.090531 <6>[ 0.115421] arch_timer: Enabling local workaround for ARM erratum 858921
5909 11:06:01.097063 <6>[ 0.115427] arch_timer: CPU5: Trapping CNTVCT access
5910 11:06:01.103562 <6>[ 0.115432] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5911 11:06:01.106986 <6>[ 0.115967] Detected VIPT I-cache on CPU6
5912 11:06:01.113788 <4>[ 0.116013] cacheinfo: Unable to detect cache hierarchy for CPU 6
5913 11:06:01.119924 <6>[ 0.116019] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5914 11:06:01.126681 <6>[ 0.116026] arch_timer: Enabling local workaround for ARM erratum 858921
5915 11:06:01.133196 <6>[ 0.116032] arch_timer: CPU6: Trapping CNTVCT access
5916 11:06:01.139836 <6>[ 0.116037] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5917 11:06:01.142822 <6>[ 0.116568] Detected VIPT I-cache on CPU7
5918 11:06:01.149577 <4>[ 0.116610] cacheinfo: Unable to detect cache hierarchy for CPU 7
5919 11:06:01.155896 <6>[ 0.116617] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5920 11:06:01.165719 <6>[ 0.116624] arch_timer: Enabling local workaround for ARM erratum 858921
5921 11:06:01.169509 <6>[ 0.116630] arch_timer: CPU7: Trapping CNTVCT access
5922 11:06:01.175590 <6>[ 0.116635] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5923 11:06:01.179044 <6>[ 0.116682] smp: Brought up 1 node, 8 CPUs
5924 11:06:01.185477 <6>[ 0.355557] SMP: Total of 8 processors activated.
5925 11:06:01.192149 <6>[ 0.360492] CPU features: detected: 32-bit EL0 Support
5926 11:06:01.195406 <6>[ 0.365864] CPU features: detected: 32-bit EL1 Support
5927 11:06:01.201707 <6>[ 0.371230] CPU features: detected: CRC32 instructions
5928 11:06:01.205019 <6>[ 0.376656] CPU: All CPU(s) started at EL2
5929 11:06:01.211687 <6>[ 0.380993] alternatives: applying system-wide alternatives
5930 11:06:01.218724 <6>[ 0.389043] devtmpfs: initialized
5931 11:06:01.234433 <6>[ 0.397986] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5932 11:06:01.240956 <6>[ 0.407935] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5933 11:06:01.247556 <6>[ 0.415663] pinctrl core: initialized pinctrl subsystem
5934 11:06:01.250523 <6>[ 0.422783] DMI not present or invalid.
5935 11:06:01.257355 <6>[ 0.427152] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5936 11:06:01.267374 <6>[ 0.434048] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5937 11:06:01.274022 <6>[ 0.441561] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5938 11:06:01.283801 <6>[ 0.449732] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5939 11:06:01.286909 <6>[ 0.457879] audit: initializing netlink subsys (disabled)
5940 11:06:01.296846 <5>[ 0.463563] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5941 11:06:01.303376 <6>[ 0.464520] thermal_sys: Registered thermal governor 'step_wise'
5942 11:06:01.309904 <6>[ 0.471513] thermal_sys: Registered thermal governor 'power_allocator'
5943 11:06:01.312997 <6>[ 0.477760] cpuidle: using governor menu
5944 11:06:01.319736 <6>[ 0.488708] NET: Registered PF_QIPCRTR protocol family
5945 11:06:01.326321 <6>[ 0.494198] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5946 11:06:01.332865 <6>[ 0.501294] ASID allocator initialised with 32768 entries
5947 11:06:01.336029 <6>[ 0.508073] Serial: AMBA PL011 UART driver
5948 11:06:01.349384 <4>[ 0.519385] Trying to register duplicate clock ID: 113
5949 11:06:01.409349 <6>[ 0.576108] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5950 11:06:01.423678 <6>[ 0.590505] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5951 11:06:01.426979 <6>[ 0.600279] KASLR enabled
5952 11:06:01.441523 <6>[ 0.608227] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5953 11:06:01.447972 <6>[ 0.615230] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5954 11:06:01.454561 <6>[ 0.621706] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5955 11:06:01.461125 <6>[ 0.628699] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5956 11:06:01.467478 <6>[ 0.635172] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5957 11:06:01.474148 <6>[ 0.642164] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5958 11:06:01.480637 <6>[ 0.648638] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5959 11:06:01.487390 <6>[ 0.655628] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5960 11:06:01.493595 <6>[ 0.663166] ACPI: Interpreter disabled.
5961 11:06:01.501463 <6>[ 0.671181] iommu: Default domain type: Translated
5962 11:06:01.507827 <6>[ 0.676290] iommu: DMA domain TLB invalidation policy: strict mode
5963 11:06:01.511038 <5>[ 0.682942] SCSI subsystem initialized
5964 11:06:01.517481 <6>[ 0.687403] usbcore: registered new interface driver usbfs
5965 11:06:01.524058 <6>[ 0.693128] usbcore: registered new interface driver hub
5966 11:06:01.530400 <6>[ 0.698670] usbcore: registered new device driver usb
5967 11:06:01.533914 <6>[ 0.704989] pps_core: LinuxPPS API ver. 1 registered
5968 11:06:01.543642 <6>[ 0.710174] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5969 11:06:01.550198 <6>[ 0.719499] PTP clock support registered
5970 11:06:01.553618 <6>[ 0.723751] EDAC MC: Ver: 3.0.0
5971 11:06:01.556429 <6>[ 0.729407] FPGA manager framework
5972 11:06:01.562998 <6>[ 0.733088] Advanced Linux Sound Architecture Driver Initialized.
5973 11:06:01.566531 <6>[ 0.739829] vgaarb: loaded
5974 11:06:01.573060 <6>[ 0.742959] clocksource: Switched to clocksource arch_sys_counter
5975 11:06:01.579635 <5>[ 0.749392] VFS: Disk quotas dquot_6.6.0
5976 11:06:01.586591 <6>[ 0.753567] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5977 11:06:01.589523 <6>[ 0.760741] pnp: PnP ACPI: disabled
5978 11:06:01.597400 <6>[ 0.767632] NET: Registered PF_INET protocol family
5979 11:06:01.603835 <6>[ 0.772859] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5980 11:06:01.616121 <6>[ 0.782771] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5981 11:06:01.625826 <6>[ 0.791525] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5982 11:06:01.632463 <6>[ 0.799477] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5983 11:06:01.638675 <6>[ 0.807709] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5984 11:06:01.648952 <6>[ 0.815803] TCP: Hash tables configured (established 32768 bind 32768)
5985 11:06:01.655717 <6>[ 0.822631] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5986 11:06:01.662222 <6>[ 0.829608] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5987 11:06:01.668625 <6>[ 0.837090] NET: Registered PF_UNIX/PF_LOCAL protocol family
5988 11:06:01.675227 <6>[ 0.843227] RPC: Registered named UNIX socket transport module.
5989 11:06:01.678606 <6>[ 0.849373] RPC: Registered udp transport module.
5990 11:06:01.684984 <6>[ 0.854299] RPC: Registered tcp transport module.
5991 11:06:01.691562 <6>[ 0.859222] RPC: Registered tcp NFSv4.1 backchannel transport module.
5992 11:06:01.694635 <6>[ 0.865877] PCI: CLS 0 bytes, default 64
5993 11:06:01.697780 <6>[ 0.870164] Unpacking initramfs...
5994 11:06:01.717109 <6>[ 0.883600] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5995 11:06:01.726630 <6>[ 0.892320] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5996 11:06:01.729955 <6>[ 0.901230] kvm [1]: IPA Size Limit: 40 bits
5997 11:06:01.737428 <6>[ 0.907577] kvm [1]: vgic-v2@c420000
5998 11:06:01.743966 <6>[ 0.911406] kvm [1]: GIC system register CPU interface enabled
5999 11:06:01.747244 <6>[ 0.919030] kvm [1]: vgic interrupt IRQ18
6000 11:06:01.753782 <6>[ 0.923412] kvm [1]: Hyp mode initialized successfully
6001 11:06:01.760204 <5>[ 0.929761] Initialise system trusted keyrings
6002 11:06:01.766751 <6>[ 0.934552] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6003 11:06:01.774664 <6>[ 0.944466] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6004 11:06:01.781059 <5>[ 0.950900] NFS: Registering the id_resolver key type
6005 11:06:01.784609 <5>[ 0.956207] Key type id_resolver registered
6006 11:06:01.790832 <5>[ 0.960622] Key type id_legacy registered
6007 11:06:01.797205 <6>[ 0.964925] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6008 11:06:01.803769 <6>[ 0.971847] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6009 11:06:01.810190 <6>[ 0.979588] 9p: Installing v9fs 9p2000 file system support
6010 11:06:01.838689 <5>[ 1.008692] Key type asymmetric registered
6011 11:06:01.842057 <5>[ 1.013034] Asymmetric key parser 'x509' registered
6012 11:06:01.851866 <6>[ 1.018181] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6013 11:06:01.854995 <6>[ 1.025801] io scheduler mq-deadline registered
6014 11:06:01.858522 <6>[ 1.030558] io scheduler kyber registered
6015 11:06:01.881183 <6>[ 1.051314] EINJ: ACPI disabled.
6016 11:06:01.887814 <4>[ 1.055057] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6017 11:06:01.925647 <6>[ 1.095677] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6018 11:06:01.934259 <6>[ 1.104196] printk: console [ttyS0] disabled
6019 11:06:01.962008 <6>[ 1.128850] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6020 11:06:01.969038 <6>[ 1.138325] printk: console [ttyS0] enabled
6021 11:06:01.972076 <6>[ 1.138325] printk: console [ttyS0] enabled
6022 11:06:01.978709 <6>[ 1.147243] printk: bootconsole [mtk8250] disabled
6023 11:06:01.981737 <6>[ 1.147243] printk: bootconsole [mtk8250] disabled
6024 11:06:01.991577 <3>[ 1.157772] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6025 11:06:01.997952 <3>[ 1.166157] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6026 11:06:02.027749 <6>[ 1.194568] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6027 11:06:02.034515 <6>[ 1.204223] serial serial0: tty port ttyS1 registered
6028 11:06:02.040721 <6>[ 1.210814] SuperH (H)SCI(F) driver initialized
6029 11:06:02.047348 <6>[ 1.216334] msm_serial: driver initialized
6030 11:06:02.059690 <6>[ 1.226596] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6031 11:06:02.069633 <6>[ 1.235193] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6032 11:06:02.076169 <6>[ 1.243770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6033 11:06:02.086189 <6>[ 1.252342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6034 11:06:02.095793 <6>[ 1.260996] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6035 11:06:02.102289 <6>[ 1.269660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6036 11:06:02.112464 <6>[ 1.278401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6037 11:06:02.121797 <6>[ 1.287144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6038 11:06:02.128552 <6>[ 1.295714] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6039 11:06:02.138165 <6>[ 1.304517] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6040 11:06:02.146866 <4>[ 1.316941] cacheinfo: Unable to detect cache hierarchy for CPU 0
6041 11:06:02.156104 <6>[ 1.326257] loop: module loaded
6042 11:06:02.168282 <6>[ 1.338248] vsim1: Bringing 1800000uV into 2700000-2700000uV
6043 11:06:02.186318 <6>[ 1.356270] megasas: 07.719.03.00-rc1
6044 11:06:02.194748 <6>[ 1.365032] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6045 11:06:02.211832 <6>[ 1.378331] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6046 11:06:02.224831 <6>[ 1.394959] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6047 11:06:02.285102 <6>[ 1.448605] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-a
6048 11:06:02.329800 <6>[ 1.499809] Freeing initrd memory: 18268K
6049 11:06:02.345096 <4>[ 1.511656] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6050 11:06:02.351315 <4>[ 1.520887] CPU: 5 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6051 11:06:02.357980 <4>[ 1.527585] Hardware name: Google juniper sku16 board (DT)
6052 11:06:02.361470 <4>[ 1.533324] Call trace:
6053 11:06:02.364812 <4>[ 1.536024] dump_backtrace.part.0+0xe0/0xf0
6054 11:06:02.367760 <4>[ 1.540561] show_stack+0x18/0x30
6055 11:06:02.374476 <4>[ 1.544133] dump_stack_lvl+0x64/0x80
6056 11:06:02.377770 <4>[ 1.548053] dump_stack+0x18/0x34
6057 11:06:02.380932 <4>[ 1.551622] sysfs_warn_dup+0x64/0x80
6058 11:06:02.384192 <4>[ 1.555544] sysfs_do_create_link_sd+0xf0/0x100
6059 11:06:02.390813 <4>[ 1.560331] sysfs_create_link+0x20/0x40
6060 11:06:02.394234 <4>[ 1.564510] bus_add_device+0x64/0x120
6061 11:06:02.397488 <4>[ 1.568514] device_add+0x354/0x7ec
6062 11:06:02.400631 <4>[ 1.572260] of_device_add+0x44/0x60
6063 11:06:02.407176 <4>[ 1.576094] of_platform_device_create_pdata+0x90/0x124
6064 11:06:02.410389 <4>[ 1.581575] of_platform_bus_create+0x154/0x380
6065 11:06:02.417008 <4>[ 1.586362] of_platform_populate+0x50/0xfc
6066 11:06:02.420424 <4>[ 1.590801] parse_mtd_partitions+0x1d8/0x4e0
6067 11:06:02.426782 <4>[ 1.595418] mtd_device_parse_register+0xec/0x2e0
6068 11:06:02.430059 <4>[ 1.600379] spi_nor_probe+0x280/0x2f4
6069 11:06:02.433527 <4>[ 1.604384] spi_mem_probe+0x6c/0xc0
6070 11:06:02.436640 <4>[ 1.608216] spi_probe+0x84/0xe4
6071 11:06:02.439881 <4>[ 1.611701] really_probe+0xbc/0x2dc
6072 11:06:02.446538 <4>[ 1.615532] __driver_probe_device+0x78/0x114
6073 11:06:02.449852 <4>[ 1.620144] driver_probe_device+0xd8/0x15c
6074 11:06:02.453020 <4>[ 1.624582] __device_attach_driver+0xb8/0x134
6075 11:06:02.459628 <4>[ 1.629281] bus_for_each_drv+0x7c/0xd4
6076 11:06:02.462921 <4>[ 1.633373] __device_attach+0x9c/0x1a0
6077 11:06:02.466132 <4>[ 1.637463] device_initial_probe+0x14/0x20
6078 11:06:02.469429 <4>[ 1.641900] bus_probe_device+0x98/0xa0
6079 11:06:02.476034 <4>[ 1.645990] device_add+0x3c0/0x7ec
6080 11:06:02.479259 <4>[ 1.649735] __spi_add_device+0x78/0x120
6081 11:06:02.482835 <4>[ 1.653913] spi_add_device+0x44/0x80
6082 11:06:02.489083 <4>[ 1.657830] spi_register_controller+0x704/0xb20
6083 11:06:02.492297 <4>[ 1.662702] devm_spi_register_controller+0x4c/0xac
6084 11:06:02.495484 <4>[ 1.667835] mtk_spi_probe+0x4f4/0x684
6085 11:06:02.502205 <4>[ 1.671839] platform_probe+0x68/0xc0
6086 11:06:02.505409 <4>[ 1.675756] really_probe+0xbc/0x2dc
6087 11:06:02.508717 <4>[ 1.679586] __driver_probe_device+0x78/0x114
6088 11:06:02.511954 <4>[ 1.684198] driver_probe_device+0xd8/0x15c
6089 11:06:02.518851 <4>[ 1.688635] __driver_attach+0x94/0x19c
6090 11:06:02.521902 <4>[ 1.692725] bus_for_each_dev+0x74/0xd0
6091 11:06:02.525359 <4>[ 1.696818] driver_attach+0x24/0x30
6092 11:06:02.528698 <4>[ 1.700648] bus_add_driver+0x154/0x20c
6093 11:06:02.535365 <4>[ 1.704738] driver_register+0x78/0x130
6094 11:06:02.538565 <4>[ 1.708828] __platform_driver_register+0x28/0x34
6095 11:06:02.541619 <4>[ 1.713788] mtk_spi_driver_init+0x1c/0x28
6096 11:06:02.548240 <4>[ 1.718144] do_one_initcall+0x64/0x1dc
6097 11:06:02.551487 <4>[ 1.722236] kernel_init_freeable+0x218/0x284
6098 11:06:02.554952 <4>[ 1.726850] kernel_init+0x24/0x12c
6099 11:06:02.558166 <4>[ 1.730596] ret_from_fork+0x10/0x20
6100 11:06:02.569694 <6>[ 1.739477] tun: Universal TUN/TAP device driver, 1.6
6101 11:06:02.572707 <6>[ 1.745782] thunder_xcv, ver 1.0
6102 11:06:02.579087 <6>[ 1.749303] thunder_bgx, ver 1.0
6103 11:06:02.579180 <6>[ 1.752808] nicpf, ver 1.0
6104 11:06:02.590570 <6>[ 1.757180] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6105 11:06:02.593665 <6>[ 1.764664] hns3: Copyright (c) 2017 Huawei Corporation.
6106 11:06:02.600204 <6>[ 1.770262] hclge is initializing
6107 11:06:02.603390 <6>[ 1.773848] e1000: Intel(R) PRO/1000 Network Driver
6108 11:06:02.610307 <6>[ 1.778983] e1000: Copyright (c) 1999-2006 Intel Corporation.
6109 11:06:02.616854 <6>[ 1.785004] e1000e: Intel(R) PRO/1000 Network Driver
6110 11:06:02.620149 <6>[ 1.790225] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6111 11:06:02.626411 <6>[ 1.796421] igb: Intel(R) Gigabit Ethernet Network Driver
6112 11:06:02.633166 <6>[ 1.802076] igb: Copyright (c) 2007-2014 Intel Corporation.
6113 11:06:02.639811 <6>[ 1.807919] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6114 11:06:02.646307 <6>[ 1.814442] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6115 11:06:02.649581 <6>[ 1.821000] sky2: driver version 1.30
6116 11:06:02.656390 <6>[ 1.826251] usbcore: registered new device driver r8152-cfgselector
6117 11:06:02.662889 <6>[ 1.832795] usbcore: registered new interface driver r8152
6118 11:06:02.669211 <6>[ 1.838620] VFIO - User Level meta-driver version: 0.3
6119 11:06:02.676493 <6>[ 1.846441] mtu3 11201000.usb: uwk - reg:0x420, version:101
6120 11:06:02.683377 <4>[ 1.852315] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6121 11:06:02.689694 <6>[ 1.859594] mtu3 11201000.usb: dr_mode: 1, drd: auto
6122 11:06:02.695984 <6>[ 1.864823] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6123 11:06:02.699227 <6>[ 1.871020] mtu3 11201000.usb: usb3-drd: 0
6124 11:06:02.709655 <6>[ 1.876576] mtu3 11201000.usb: xHCI platform device register success...
6125 11:06:02.716234 <4>[ 1.885175] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6126 11:06:02.723041 <6>[ 1.893149] xhci-mtk 11200000.usb: xHCI Host Controller
6127 11:06:02.732859 <6>[ 1.898682] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6128 11:06:02.736288 <6>[ 1.906406] xhci-mtk 11200000.usb: USB3 root hub has no ports
6129 11:06:02.746062 <6>[ 1.912415] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6130 11:06:02.752535 <6>[ 1.921837] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6131 11:06:02.759293 <6>[ 1.927909] xhci-mtk 11200000.usb: xHCI Host Controller
6132 11:06:02.765607 <6>[ 1.933397] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6133 11:06:02.772117 <6>[ 1.941054] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6134 11:06:02.775586 <6>[ 1.947868] hub 1-0:1.0: USB hub found
6135 11:06:02.782113 <6>[ 1.951897] hub 1-0:1.0: 1 port detected
6136 11:06:02.792109 <6>[ 1.957262] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6137 11:06:02.795149 <6>[ 1.965883] hub 2-0:1.0: USB hub found
6138 11:06:02.801743 <3>[ 1.969910] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6139 11:06:02.808788 <6>[ 1.977781] usbcore: registered new interface driver usb-storage
6140 11:06:02.815039 <6>[ 1.984371] usbcore: registered new device driver onboard-usb-hub
6141 11:06:02.832190 <4>[ 1.999073] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6142 11:06:02.841177 <6>[ 2.011310] mt6397-rtc mt6358-rtc: registered as rtc0
6143 11:06:02.851091 <6>[ 2.016790] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-10T11:06:01 UTC (1720609561)
6144 11:06:02.857669 <6>[ 2.026655] i2c_dev: i2c /dev entries driver
6145 11:06:02.867664 <6>[ 2.033072] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6146 11:06:02.873952 <6>[ 2.041392] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6147 11:06:02.880700 <6>[ 2.050299] i2c 4-0058: Fixed dependency cycle(s) with /panel
6148 11:06:02.887411 <6>[ 2.056330] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6149 11:06:02.905613 <6>[ 2.075748] cpu cpu0: EM: created perf domain
6150 11:06:02.918696 <6>[ 2.081266] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6151 11:06:02.921958 <6>[ 2.092570] cpu cpu4: EM: created perf domain
6152 11:06:02.929729 <6>[ 2.099641] sdhci: Secure Digital Host Controller Interface driver
6153 11:06:02.935957 <6>[ 2.106094] sdhci: Copyright(c) Pierre Ossman
6154 11:06:02.942537 <6>[ 2.111472] Synopsys Designware Multimedia Card Interface Driver
6155 11:06:02.949179 <6>[ 2.111970] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6156 11:06:02.952736 <6>[ 2.118519] sdhci-pltfm: SDHCI platform and OF driver helper
6157 11:06:02.961192 <6>[ 2.131077] ledtrig-cpu: registered to indicate activity on CPUs
6158 11:06:02.968951 <6>[ 2.138781] usbcore: registered new interface driver usbhid
6159 11:06:02.975198 <6>[ 2.144625] usbhid: USB HID core driver
6160 11:06:02.982301 <6>[ 2.148909] spi_master spi2: will run message pump with realtime priority
6161 11:06:02.989582 <4>[ 2.149169] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6162 11:06:02.996207 <4>[ 2.163284] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6163 11:06:03.009291 <6>[ 2.167273] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6164 11:06:03.026098 <6>[ 2.186141] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6165 11:06:03.032477 <4>[ 2.195410] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6166 11:06:03.039441 <6>[ 2.207144] cros-ec-spi spi2.0: Chrome EC device registered
6167 11:06:03.048877 <4>[ 2.215177] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6168 11:06:03.059215 <4>[ 2.225999] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6169 11:06:03.065582 <4>[ 2.234767] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6170 11:06:03.078452 <6>[ 2.245162] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6171 11:06:03.095405 <6>[ 2.265380] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6172 11:06:03.102999 <6>[ 2.273035] mmc0: new HS400 MMC card at address 0001
6173 11:06:03.110257 <6>[ 2.280322] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6174 11:06:03.122929 <6>[ 2.292820] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6175 11:06:03.132685 <6>[ 2.296612] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6176 11:06:03.139004 <6>[ 2.302084] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6177 11:06:03.149247 <6>[ 2.311614] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6178 11:06:03.152331 <6>[ 2.314254] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6179 11:06:03.165746 <6>[ 2.315364] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6180 11:06:03.175338 <6>[ 2.315497] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6181 11:06:03.182032 <6>[ 2.325542] NET: Registered PF_PACKET protocol family
6182 11:06:03.188316 <6>[ 2.330057] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6183 11:06:03.191879 <6>[ 2.340937] 9pnet: Installing 9P2000 support
6184 11:06:03.198108 <5>[ 2.367205] Key type dns_resolver registered
6185 11:06:03.204930 <6>[ 2.371873] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6186 11:06:03.207765 <6>[ 2.372344] registered taskstats version 1
6187 11:06:03.214258 <5>[ 2.383022] Loading compiled-in X.509 certificates
6188 11:06:03.255305 <3>[ 2.421939] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6189 11:06:03.287273 <6>[ 2.450870] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6190 11:06:03.298598 <6>[ 2.465187] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6191 11:06:03.308271 <6>[ 2.473788] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6192 11:06:03.314759 <6>[ 2.482441] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6193 11:06:03.324928 <6>[ 2.491026] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6194 11:06:03.334591 <6>[ 2.499553] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6195 11:06:03.340832 <6>[ 2.508076] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6196 11:06:03.350525 <6>[ 2.516596] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6197 11:06:03.357128 <6>[ 2.525960] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6198 11:06:03.363995 <6>[ 2.533517] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6199 11:06:03.370232 <6>[ 2.534800] hub 1-1:1.0: USB hub found
6200 11:06:03.376903 <6>[ 2.540870] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6201 11:06:03.380042 <6>[ 2.544535] hub 1-1:1.0: 3 ports detected
6202 11:06:03.386467 <6>[ 2.551392] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6203 11:06:03.393349 <6>[ 2.562382] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6204 11:06:03.400557 <6>[ 2.570765] panfrost 13040000.gpu: clock rate = 511999970
6205 11:06:03.410671 <6>[ 2.576461] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6206 11:06:03.420500 <6>[ 2.586589] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6207 11:06:03.426795 <6>[ 2.594597] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6208 11:06:03.440041 <6>[ 2.603032] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6209 11:06:03.446160 <6>[ 2.615108] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6210 11:06:03.462233 <6>[ 2.628911] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6211 11:06:03.471990 <6>[ 2.638507] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6212 11:06:03.481837 <6>[ 2.647680] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6213 11:06:03.491332 <6>[ 2.656810] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6214 11:06:03.501517 <6>[ 2.665943] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6215 11:06:03.511134 <6>[ 2.675245] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6216 11:06:03.517533 <6>[ 2.684547] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6217 11:06:03.527443 <6>[ 2.694021] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6218 11:06:03.537285 <6>[ 2.703496] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6219 11:06:03.547134 <6>[ 2.712622] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6220 11:06:03.620025 <6>[ 2.786630] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6221 11:06:03.629628 <6>[ 2.795553] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6222 11:06:03.639964 <6>[ 2.806600] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6223 11:06:03.684514 <6>[ 2.850994] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6224 11:06:04.309850 <6>[ 3.039235] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6225 11:06:04.319642 <4>[ 3.142716] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6226 11:06:04.326421 <4>[ 3.142734] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6227 11:06:04.332895 <6>[ 3.180121] r8152 1-1.2:1.0 eth0: v1.12.13
6228 11:06:04.339672 <6>[ 3.258995] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6229 11:06:04.345826 <6>[ 3.460194] Console: switching to colour frame buffer device 170x48
6230 11:06:04.355685 <6>[ 3.520836] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6231 11:06:04.374750 <6>[ 3.537928] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6232 11:06:04.392101 <6>[ 3.555174] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6233 11:06:04.401616 <6>[ 3.567992] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6234 11:06:04.408100 <6>[ 3.576206] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6235 11:06:04.421405 <6>[ 3.582857] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6236 11:06:04.438582 <6>[ 3.602309] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6237 11:06:05.631602 <6>[ 4.801731] r8152 1-1.2:1.0 eth0: carrier on
6238 11:06:08.216997 <5>[ 4.826995] Sending DHCP requests .., OK
6239 11:06:08.223639 <6>[ 7.391317] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.22
6240 11:06:08.227018 <6>[ 7.399753] IP-Config: Complete:
6241 11:06:08.239988 <6>[ 7.403324] device=eth0, hwaddr=00:e0:4c:78:85:cb, ipaddr=192.168.201.22, mask=255.255.255.0, gw=192.168.201.1
6242 11:06:08.249688 <6>[ 7.414223] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2, domain=lava-rack, nis-domain=(none)
6243 11:06:08.261880 <6>[ 7.428594] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6244 11:06:08.270416 <6>[ 7.428604] nameserver0=192.168.201.1
6245 11:06:08.278454 <6>[ 7.448524] clk: Disabling unused clocks
6246 11:06:08.283311 <6>[ 7.456519] ALSA device list:
6247 11:06:08.292550 <6>[ 7.462608] No soundcards found.
6248 11:06:08.301536 <6>[ 7.471577] Freeing unused kernel memory: 8512K
6249 11:06:08.308925 <6>[ 7.478783] Run /init as init process
6250 11:06:08.320788 Loading, please wait...
6251 11:06:08.356483 Starting systemd-udevd version 252.22-1~deb12u1
6252 11:06:08.667854 <3>[ 7.837827] mtk-scp 10500000.scp: invalid resource
6253 11:06:08.674517 <6>[ 7.837925] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6254 11:06:08.684519 <6>[ 7.843026] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6255 11:06:08.694050 <4>[ 7.859454] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6256 11:06:08.703928 <3>[ 7.860558] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6257 11:06:08.714018 <4>[ 7.861736] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6258 11:06:08.717145 <6>[ 7.864098] remoteproc remoteproc0: scp is available
6259 11:06:08.726793 <4>[ 7.864144] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6260 11:06:08.733348 <4>[ 7.864221] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6261 11:06:08.739930 <6>[ 7.864229] remoteproc remoteproc0: powering up scp
6262 11:06:08.746195 <4>[ 7.864257] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6263 11:06:08.752750 <3>[ 7.864262] remoteproc remoteproc0: request_firmware failed: -2
6264 11:06:08.767259 <6>[ 7.871892] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6265 11:06:08.773879 <3>[ 7.880668] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6266 11:06:08.783733 <6>[ 7.892740] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6267 11:06:08.793506 <3>[ 7.893200] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6268 11:06:08.805448 <3>[ 7.905529] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6269 11:06:08.811821 <3>[ 7.908897] elan_i2c 2-0015: Error applying setting, reverse things back
6270 11:06:08.821783 <3>[ 7.913922] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6271 11:06:08.824699 <6>[ 7.928739] mc: Linux media interface: v0.10
6272 11:06:08.834729 <3>[ 7.930935] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6273 11:06:08.841204 <5>[ 7.945976] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6274 11:06:08.852079 <3>[ 7.948978] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6275 11:06:08.865844 <3>[ 7.950031] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6276 11:06:08.875462 <6>[ 7.957037] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6277 11:06:08.881882 <5>[ 7.972428] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6278 11:06:08.888767 <3>[ 7.980037] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6279 11:06:08.894900 <6>[ 7.980396] videodev: Linux video capture interface: v2.00
6280 11:06:08.904770 <5>[ 7.987407] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6281 11:06:08.911474 <6>[ 7.987663] cs_system_cfg: CoreSight Configuration manager initialised
6282 11:06:08.917937 <3>[ 7.995531] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6283 11:06:08.928248 <6>[ 7.995931] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6284 11:06:08.938292 <6>[ 7.996056] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6285 11:06:08.944875 <6>[ 7.996134] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6286 11:06:08.954588 <6>[ 7.996213] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6287 11:06:08.961046 <6>[ 7.996292] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6288 11:06:08.967822 <6>[ 7.996371] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6289 11:06:08.977535 <6>[ 8.000056] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6290 11:06:08.987159 <4>[ 8.000142] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6291 11:06:08.993675 <6>[ 8.000150] cfg80211: failed to load regulatory.db
6292 11:06:09.003495 <6>[ 8.006709] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6293 11:06:09.010083 <3>[ 8.008554] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6294 11:06:09.020488 <3>[ 8.008568] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6295 11:06:09.030360 <3>[ 8.008628] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6296 11:06:09.033835 <6>[ 8.029922] Bluetooth: Core ver 2.22
6297 11:06:09.040133 <6>[ 8.042492] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6298 11:06:09.046776 <6>[ 8.049654] NET: Registered PF_BLUETOOTH protocol family
6299 11:06:09.053385 <6>[ 8.049901] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6300 11:06:09.063600 <6>[ 8.056296] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6301 11:06:09.070246 <6>[ 8.056335] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6302 11:06:09.080124 <6>[ 8.056441] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6303 11:06:09.089775 <6>[ 8.058226] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6304 11:06:09.096245 <6>[ 8.064799] Bluetooth: HCI device and connection manager initialized
6305 11:06:09.109371 <6>[ 8.070282] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6306 11:06:09.115998 <6>[ 8.071435] usbcore: registered new interface driver uvcvideo
6307 11:06:09.122511 <6>[ 8.079044] Bluetooth: HCI socket layer initialized
6308 11:06:09.132318 <6>[ 8.116536] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6309 11:06:09.135564 <6>[ 8.120190] Bluetooth: L2CAP socket layer initialized
6310 11:06:09.149376 <3>[ 8.120762] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6311 11:06:09.155739 <3>[ 8.121728] debugfs: File 'Playback' in directory 'dapm' already present!
6312 11:06:09.166601 <3>[ 8.121737] debugfs: File 'Capture' in directory 'dapm' already present!
6313 11:06:09.176246 <6>[ 8.123336] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6314 11:06:09.179855 <3>[ 8.126281] thermal_sys: Failed to find 'trips' node
6315 11:06:09.186735 <3>[ 8.126291] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6316 11:06:09.196666 <3>[ 8.126300] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6317 11:06:09.202992 <4>[ 8.126306] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6318 11:06:09.213935 <6>[ 8.128094] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6319 11:06:09.223629 <6>[ 8.128189] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6320 11:06:09.230184 <3>[ 8.129098] thermal_sys: Failed to find 'trips' node
6321 11:06:09.236743 <3>[ 8.129104] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6322 11:06:09.247316 <3>[ 8.129115] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6323 11:06:09.256839 <4>[ 8.129120] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6324 11:06:09.259984 <6>[ 8.136042] Bluetooth: SCO socket layer initialized
6325 11:06:09.270370 <6>[ 8.292672] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6326 11:06:09.273611 <6>[ 8.333346] Bluetooth: HCI UART driver ver 2.3
6327 11:06:09.284041 <4>[ 8.346472] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6328 11:06:09.290416 <4>[ 8.346472] Fallback method does not support PEC.
6329 11:06:09.296935 <6>[ 8.350785] Bluetooth: HCI UART protocol H4 registered
6330 11:06:09.303580 <3>[ 8.359816] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6331 11:06:09.310156 <6>[ 8.363341] Bluetooth: HCI UART protocol LL registered
6332 11:06:09.319982 <3>[ 8.382735] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6333 11:06:09.326410 <6>[ 8.388530] Bluetooth: HCI UART protocol Three-wire (H5) registered
6334 11:06:09.358676 <6>[ 8.528710] Bluetooth: HCI UART protocol Broadcom registered
6335 11:06:09.365531 <6>[ 8.535425] Bluetooth: HCI UART protocol QCA registered
6336 11:06:09.372144 <6>[ 8.536489] Bluetooth: hci0: setting up ROME/QCA6390
6337 11:06:09.378449 <6>[ 8.540929] Bluetooth: HCI UART protocol Marvell registered
6338 11:06:09.386276 Begin: Loading essential drivers ... done.
6339 11:06:09.389674 Begin: Running /scripts/init-premount ... done.
6340 11:06:09.396125 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6341 11:06:09.405859 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
6342 11:06:09.409192 Device /sys/class/net/eth0 found
6343 11:06:09.409279 done.
6344 11:06:09.415535 Begin: Waiting up to 180 secs for any network device to become available ... done.
6345 11:06:09.441788 IP-Config: eth0 hardware address 00:e0:4c:78:85:cb mtu 1500 DHCP
6346 11:06:09.448306 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6347 11:06:09.454900 address: 192.168.201.22 broadcast: 192.168.201.255 netmask: 255.255.255.0
6348 11:06:09.461343 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6349 11:06:09.467862 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-2
6350 11:06:09.474341 domain : lava-rack
6351 11:06:09.477854 rootserver: 192.168.201.1 rootpath:
6352 11:06:09.480908 filename :
6353 11:06:09.484489 done.
6354 11:06:09.491227 Begin: Running /scripts/nfs-bottom ... done.
6355 11:06:09.507146 Begin: Running /scripts/init-bottom ... done.
6356 11:06:09.526210 <6>[ 8.692999] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6357 11:06:09.588349 <3>[ 8.758353] Bluetooth: hci0: Frame reassembly failed (-84)
6358 11:06:09.607644 <4>[ 8.774296] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6359 11:06:09.624778 <4>[ 8.791586] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6360 11:06:09.639835 <4>[ 8.806590] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6361 11:06:09.647497 <4>[ 8.817412] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6362 11:06:09.862006 <6>[ 9.032019] Bluetooth: hci0: QCA Product ID :0x00000008
6363 11:06:09.872577 <6>[ 9.042533] Bluetooth: hci0: QCA SOC Version :0x00000044
6364 11:06:09.882865 <6>[ 9.052873] Bluetooth: hci0: QCA ROM Version :0x00000302
6365 11:06:09.893205 <6>[ 9.063124] Bluetooth: hci0: QCA Patch Version:0x00000111
6366 11:06:09.903023 <6>[ 9.072717] Bluetooth: hci0: QCA controller version 0x00440302
6367 11:06:09.915697 <6>[ 9.082226] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6368 11:06:09.925459 <4>[ 9.092274] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6369 11:06:09.937618 <3>[ 9.104438] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6370 11:06:09.945475 <3>[ 9.115481] Bluetooth: hci0: QCA Failed to download patch (-2)
6371 11:06:10.925710 <6>[ 10.095616] NET: Registered PF_INET6 protocol family
6372 11:06:10.937483 <6>[ 10.107354] Segment Routing with IPv6
6373 11:06:10.945295 <6>[ 10.115423] In-situ OAM (IOAM) with IPv6
6374 11:06:11.123435 <30>[ 10.264019] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6375 11:06:11.140453 <30>[ 10.310169] systemd[1]: Detected architecture arm64.
6376 11:06:11.150535
6377 11:06:11.153462 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6378 11:06:11.153547
6379 11:06:11.182596 <30>[ 10.352590] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6380 11:06:12.156646 <30>[ 11.323172] systemd[1]: Queued start job for default target graphical.target.
6381 11:06:12.198230 <30>[ 11.364403] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6382 11:06:12.210244 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6383 11:06:12.230757 <30>[ 11.397259] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6384 11:06:12.243891 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6385 11:06:12.262949 <30>[ 11.429384] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6386 11:06:12.276521 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6387 11:06:12.294232 <30>[ 11.460588] systemd[1]: Created slice user.slice - User and Session Slice.
6388 11:06:12.305777 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6389 11:06:12.328006 <30>[ 11.491557] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6390 11:06:12.341192 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6391 11:06:12.360280 <30>[ 11.523402] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6392 11:06:12.372189 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6393 11:06:12.401847 <30>[ 11.555353] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6394 11:06:12.417547 <30>[ 11.584067] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6395 11:06:12.425201 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6396 11:06:12.444414 <30>[ 11.611177] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6397 11:06:12.457126 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6398 11:06:12.476676 <30>[ 11.643220] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6399 11:06:12.491039 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6400 11:06:12.505518 <30>[ 11.675292] systemd[1]: Reached target paths.target - Path Units.
6401 11:06:12.519850 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6402 11:06:12.536755 <30>[ 11.703168] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6403 11:06:12.548713 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6404 11:06:12.564342 <30>[ 11.731114] systemd[1]: Reached target slices.target - Slice Units.
6405 11:06:12.576153 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6406 11:06:12.589324 <30>[ 11.759175] systemd[1]: Reached target swap.target - Swaps.
6407 11:06:12.599839 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6408 11:06:12.620530 <30>[ 11.787200] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6409 11:06:12.633899 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6410 11:06:12.652916 <30>[ 11.819566] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6411 11:06:12.666631 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6412 11:06:12.687393 <30>[ 11.853956] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6413 11:06:12.700790 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6414 11:06:12.718239 <30>[ 11.884782] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6415 11:06:12.732352 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6416 11:06:12.749288 <30>[ 11.915926] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6417 11:06:12.761612 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6418 11:06:12.782408 <30>[ 11.948849] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6419 11:06:12.795801 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6420 11:06:12.816079 <30>[ 11.982803] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6421 11:06:12.829158 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6422 11:06:12.849621 <30>[ 12.015915] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6423 11:06:12.862028 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6424 11:06:12.905233 <30>[ 12.071338] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6425 11:06:12.916854 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6426 11:06:12.938316 <30>[ 12.104954] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6427 11:06:12.951376 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6428 11:06:12.973244 <30>[ 12.139984] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6429 11:06:12.986096 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6430 11:06:13.011764 <30>[ 12.171831] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6431 11:06:13.053629 <30>[ 12.220091] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6432 11:06:13.067823 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6433 11:06:13.091224 <30>[ 12.257792] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6434 11:06:13.105392 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6435 11:06:13.130668 <30>[ 12.297434] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6436 11:06:13.142524 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6437 11:06:13.189943 <30>[ 12.356351] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6438 11:06:13.199424 <6>[ 12.356819] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6439 11:06:13.213740 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6440 11:06:13.239271 <30>[ 12.405701] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6441 11:06:13.253836 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6442 11:06:13.305248 <30>[ 12.471645] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6443 11:06:13.318864 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6444 11:06:13.343838 <30>[ 12.510525] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6445 11:06:13.356039 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6446 11:06:13.374131 <6>[ 12.543805] fuse: init (API version 7.37)
6447 11:06:13.417608 <30>[ 12.584194] systemd[1]: Starting systemd-journald.service - Journal Service...
6448 11:06:13.430246 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6449 11:06:13.455382 <30>[ 12.621807] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6450 11:06:13.465997 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6451 11:06:13.492224 <30>[ 12.655423] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6452 11:06:13.502925 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6453 11:06:13.526536 <30>[ 12.692913] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6454 11:06:13.539949 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6455 11:06:13.581093 <30>[ 12.747675] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6456 11:06:13.592649 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6457 11:06:13.617564 <30>[ 12.784031] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6458 11:06:13.632081 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 12.799080] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6459 11:06:13.635406 uge Pages File System.
6460 11:06:13.649204 <3>[ 12.815448] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6461 11:06:13.659075 <30>[ 12.824897] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6462 11:06:13.669230 <3>[ 12.834818] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6463 11:06:13.685934 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 12.851435] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6464 11:06:13.686035 File System.
6465 11:06:13.702285 <3>[ 12.868514] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6466 11:06:13.712813 <30>[ 12.877494] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6467 11:06:13.719413 <3>[ 12.885836] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6468 11:06:13.733498 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6469 11:06:13.739968 <3>[ 12.906169] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6470 11:06:13.751565 <30>[ 12.916964] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6471 11:06:13.761511 <3>[ 12.923406] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6472 11:06:13.773860 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6473 11:06:13.789688 <30>[ 12.956104] systemd[1]: Started systemd-journald.service - Journal Service.
6474 11:06:13.799794 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6475 11:06:13.826227 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6476 11:06:13.851592 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6477 11:06:13.871085 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6478 11:06:13.895340 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6479 11:06:13.915816 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6480 11:06:13.935343 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6481 11:06:13.958374 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6482 11:06:13.982155 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6483 11:06:14.002346 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6484 11:06:14.027879 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6485 11:06:14.095017 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System..<4>[ 13.254452] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6486 11:06:14.098278 .
6487 11:06:14.104671 <3>[ 13.272734] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6488 11:06:14.122578 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6489 11:06:14.148520 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6490 11:06:14.173763 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6491 11:06:14.205017 <46>[ 13.371529] systemd-journald[322]: Received client request to flush runtime journal.
6492 11:06:14.216561 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6493 11:06:14.238064 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6494 11:06:14.265166 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6495 11:06:14.286050 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6496 11:06:14.306201 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6497 11:06:14.331154 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6498 11:06:14.351143 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6499 11:06:15.339138 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6500 11:06:15.381894 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6501 11:06:15.685031 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6502 11:06:15.772067 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6503 11:06:15.789594 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6504 11:06:15.808969 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6505 11:06:15.853817 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6506 11:06:15.878301 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6507 11:06:16.141978 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6508 11:06:16.193209 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6509 11:06:16.210385 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6510 11:06:16.271824 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6511 11:06:16.430404 <4>[ 15.599770] power_supply_show_property: 4 callbacks suppressed
6512 11:06:16.441319 <3>[ 15.599785] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6513 11:06:16.458573 <3>[ 15.624753] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6514 11:06:16.474138 <3>[ 15.640209] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6515 11:06:16.489099 <3>[ 15.655012] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6516 11:06:16.505272 <3>[ 15.671429] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6517 11:06:16.521950 <3>[ 15.687944] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6518 11:06:16.535626 [[0;32m OK [<3>[ 15.702599] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6519 11:06:16.542433 0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6520 11:06:16.553229 <3>[ 15.719324] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6521 11:06:16.570179 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Sup<3>[ 15.735816] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6522 11:06:16.570271 port.
6523 11:06:16.587231 <3>[ 15.753437] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6524 11:06:16.594568 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6525 11:06:16.613781 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6526 11:06:16.661821 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6527 11:06:16.734420 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6528 11:06:16.762792 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6529 11:06:16.783184 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6530 11:06:16.878166 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6531 11:06:16.897985 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6532 11:06:16.919450 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6533 11:06:16.935644 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6534 11:06:16.970305 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6535 11:06:16.989517 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6536 11:06:17.006347 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6537 11:06:17.025095 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6538 11:06:17.040965 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6539 11:06:17.062294 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6540 11:06:17.083121 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6541 11:06:17.101041 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6542 11:06:17.119503 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6543 11:06:17.139709 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6544 11:06:17.156664 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6545 11:06:17.174842 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6546 11:06:17.192985 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6547 11:06:17.209053 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6548 11:06:17.259475 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6549 11:06:17.342440 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6550 11:06:17.427134 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6551 11:06:17.454153 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6552 11:06:17.565658 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6553 11:06:17.606498 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6554 11:06:17.626241 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6555 11:06:17.646093 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6556 11:06:17.668830 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6557 11:06:17.697198 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6558 11:06:17.755706 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6559 11:06:17.777432 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6560 11:06:17.794956 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6561 11:06:17.843031 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6562 11:06:17.896220 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6563 11:06:17.980910
6564 11:06:17.984181 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6565 11:06:17.984272
6566 11:06:17.987371 debian-bookworm-arm64 login: root (automatic login)
6567 11:06:17.987468
6568 11:06:18.202594 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
6569 11:06:18.202726
6570 11:06:18.209220 The programs included with the Debian GNU/Linux system are free software;
6571 11:06:18.215412 the exact distribution terms for each program are described in the
6572 11:06:18.218764 individual files in /usr/share/doc/*/copyright.
6573 11:06:18.218852
6574 11:06:18.225387 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6575 11:06:18.228425 permitted by applicable law.
6576 11:06:18.293877 Matched prompt #10: / #
6578 11:06:18.294134 Setting prompt string to ['/ #']
6579 11:06:18.294233 end: 2.2.5.1 login-action (duration 00:00:18) [common]
6581 11:06:18.294427 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
6582 11:06:18.294511 start: 2.2.6 expect-shell-connection (timeout 00:03:48) [common]
6583 11:06:18.294578 Setting prompt string to ['/ #']
6584 11:06:18.294638 Forcing a shell prompt, looking for ['/ #']
6585 11:06:18.294699 Sending line: ''
6587 11:06:18.345009 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6588 11:06:18.345087 Waiting using forced prompt support (timeout 00:02:30)
6589 11:06:18.349983 / #
6590 11:06:18.350257 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6591 11:06:18.350354 start: 2.2.7 export-device-env (timeout 00:03:48) [common]
6592 11:06:18.350433 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786775/extract-nfsrootfs-q4z8imh0'"
6594 11:06:18.455806 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786775/extract-nfsrootfs-q4z8imh0'
6595 11:06:18.456070 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
6597 11:06:18.561587 / # export NFS_SERVER_IP='192.168.201.1'
6598 11:06:18.561873 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6599 11:06:18.561972 end: 2.2 depthcharge-retry (duration 00:01:12) [common]
6600 11:06:18.562069 end: 2 depthcharge-action (duration 00:01:12) [common]
6601 11:06:18.562158 start: 3 lava-test-retry (timeout 00:30:00) [common]
6602 11:06:18.562248 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
6603 11:06:18.562318 Using namespace: common
6604 11:06:18.562389 Sending line: '#'
6606 11:06:18.662823 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
6607 11:06:18.667792 / # #
6608 11:06:18.668057 Using /lava-14786775
6609 11:06:18.668127 Sending line: 'export SHELL=/bin/sh'
6611 11:06:18.773566 / # export SHELL=/bin/sh
6612 11:06:18.773824 Sending line: '. /lava-14786775/environment'
6614 11:06:18.879412 / # . /lava-14786775/environment
6615 11:06:18.885355 Sending line: '/lava-14786775/bin/lava-test-runner /lava-14786775/0'
6617 11:06:18.985878 Test shell timeout: 10s (minimum of the action and connection timeout)
6618 11:06:18.990868 / # /lava-14786775/bin/lava-test-runner /lava-14786775/0
6619 11:06:19.166906 + export TESTRUN_ID=0_lc-compliance
6620 11:06:19.173225 + cd /lava-14786775/0/tests/0_lc-compliance
6621 11:06:19.173314 + cat uuid
6622 11:06:19.176853 + UUID=14786775_1.6.2.3.1
6623 11:06:19.176940 + set +x
6624 11:06:19.183270 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14786775_1.6.2.3.1>
6625 11:06:19.183534 Received signal: <STARTRUN> 0_lc-compliance 14786775_1.6.2.3.1
6626 11:06:19.183610 Starting test lava.0_lc-compliance (14786775_1.6.2.3.1)
6627 11:06:19.183693 Skipping test definition patterns.
6628 11:06:19.186501 + /usr/bin/lc-compliance-parser.sh
6629 11:06:20.822849 [0:00:19.850857693] [429] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
6630 11:06:20.829177 Using camera /base/soc/usb@11201000/usb@11200000/hub@1-1.3:1.0-04f2:b567
6631 11:06:20.879992 [0:00:19.908208769] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6632 11:06:20.894445 [==========] Running 120 tests from 1 test suite.
6633 11:06:20.949610 [0:00:19.977827846] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6634 11:06:20.965234 [----------] Global test environment set-up.
6635 11:06:21.019384 [0:00:20.047748308] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6636 11:06:21.032373 [----------] 120 tests from CaptureTests/SingleStream
6637 11:06:21.088632 [0:00:20.116394000] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6638 11:06:21.103140 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
6639 11:06:21.156576 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
6640 11:06:21.156883 Received signal: <TESTSET> START CaptureTests/SingleStream
6641 11:06:21.156997 Starting test_set CaptureTests/SingleStream
6642 11:06:21.159857 Camera needs 4 requests, can't test only 1
6643 11:06:21.222736 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6644 11:06:21.280608
6645 11:06:21.343784 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (68 ms)
6646 11:06:21.419772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
6647 11:06:21.420076 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
6649 11:06:21.433273 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
6650 11:06:21.478313 Camera needs 4 requests, can't test only 2
6651 11:06:21.542705 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6652 11:06:21.607540
6653 11:06:21.666675 [0:00:20.694926308] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6654 11:06:21.682588 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (68 ms)
6655 11:06:21.765408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
6656 11:06:21.765736 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
6658 11:06:21.779908 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
6659 11:06:21.829357 Camera needs 4 requests, can't test only 3
6660 11:06:21.900780 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6661 11:06:21.965572
6662 11:06:22.032199 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (70 ms)
6663 11:06:22.104086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
6664 11:06:22.104398 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
6666 11:06:22.118701 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
6667 11:06:22.161150 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (475 ms)
6668 11:06:22.230137 [0:00:21.258207539] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6669 11:06:22.244048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
6670 11:06:22.244344 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
6672 11:06:22.255890 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
6673 11:06:22.297207 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (659 ms)
6674 11:06:22.364344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
6675 11:06:22.364658 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
6677 11:06:22.377135 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
6678 11:06:22.906207 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (728 ms)
6679 11:06:22.952582 [0:00:21.980354693] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6680 11:06:22.982244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
6681 11:06:22.982562 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
6683 11:06:22.995196 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
6684 11:06:25.081129 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (2174 ms)
6685 11:06:25.126128 [0:00:24.154004924] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6686 11:06:25.164847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
6687 11:06:25.165161 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
6689 11:06:25.178927 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
6690 11:06:28.892593 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (3811 ms)
6691 11:06:28.937831 [0:00:27.965469078] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6692 11:06:28.964933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
6693 11:06:28.965239 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
6695 11:06:28.978125 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
6696 11:06:34.798899 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (5905 ms)
6697 11:06:34.843926 [0:00:33.871800924] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6698 11:06:34.873511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
6699 11:06:34.873811 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
6701 11:06:34.887088 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
6702 11:06:38.818921 <6>[ 37.991605] vaux18: disabling
6703 11:06:38.822565 <6>[ 37.995293] vio28: disabling
6704 11:06:44.096230 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (9297 ms)
6705 11:06:44.140806 [0:00:43.168614694] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6706 11:06:44.170013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
6707 11:06:44.170288 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
6709 11:06:44.181597 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
6710 11:06:44.205196 [0:00:43.232929848] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6711 11:06:44.230931 Camera needs 4 requests, can't test only 1
6712 11:06:44.270984 [0:00:43.298647617] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6713 11:06:44.294286 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6714 11:06:44.337475 [0:00:43.365346232] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6715 11:06:44.357354
6716 11:06:44.422129 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (62 ms)
6717 11:06:44.496638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
6718 11:06:44.496934 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
6720 11:06:44.510451 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
6721 11:06:44.551509 Camera needs 4 requests, can't test only 2
6722 11:06:44.620562 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6723 11:06:44.686951
6724 11:06:44.756947 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (66 ms)
6725 11:06:44.832227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
6726 11:06:44.832522 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
6728 11:06:44.845525 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
6729 11:06:44.893542 Camera needs 4 requests, can't test only 3
6730 11:06:44.955279 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6731 11:06:45.021383
6732 11:06:45.093779 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (66 ms)
6733 11:06:45.168793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
6734 11:06:45.169082 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
6736 11:06:45.182680 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
6737 11:06:45.788935 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (1496 ms)
6738 11:06:45.833188 [0:00:44.860893617] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6739 11:06:45.869921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
6740 11:06:45.870243 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
6742 11:06:45.885238 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
6743 11:06:47.011094 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (1221 ms)
6744 11:06:47.057473 [0:00:46.085291540] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6745 11:06:47.086937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
6746 11:06:47.087247 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
6748 11:06:47.100598 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
6749 11:06:48.732676 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1721 ms)
6750 11:06:48.777594 [0:00:47.805159848] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6751 11:06:48.819310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
6752 11:06:48.819622 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
6754 11:06:48.830561 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
6755 11:06:51.250618 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (2517 ms)
6756 11:06:51.294578 [0:00:50.321998464] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6757 11:06:51.333523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
6758 11:06:51.333825 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
6760 11:06:51.346833 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
6761 11:06:55.063231 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (3812 ms)
6762 11:06:55.108882 [0:00:54.136344387] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6763 11:06:55.137444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
6764 11:06:55.137749 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
6766 11:06:55.149764 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
6767 11:07:00.970507 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (5906 ms)
6768 11:07:01.019488 [0:01:00.046959310] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6769 11:07:01.043200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
6770 11:07:01.043476 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
6772 11:07:01.057238 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
6773 11:07:10.269177 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (9298 ms)
6774 11:07:10.313785 [0:01:09.341192234] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6775 11:07:10.345318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
6776 11:07:10.345608 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
6778 11:07:10.358465 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
6779 11:07:10.378566 [0:01:09.405998003] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6780 11:07:10.399634 Camera needs 4 requests, can't test only 1
6781 11:07:10.444530 [0:01:09.471771772] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6782 11:07:10.469666 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6783 11:07:10.514603 [0:01:09.541812849] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6784 11:07:10.537239
6785 11:07:10.603189 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (64 ms)
6786 11:07:10.677701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
6787 11:07:10.677988 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
6789 11:07:10.690630 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
6790 11:07:10.730645 Camera needs 4 requests, can't test only 2
6791 11:07:10.789772 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6792 11:07:10.852381
6793 11:07:10.918301 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (64 ms)
6794 11:07:10.984548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
6795 11:07:10.984832 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
6797 11:07:10.998399 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
6798 11:07:11.041892 Camera needs 4 requests, can't test only 3
6799 11:07:11.100125 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6800 11:07:11.156636
6801 11:07:11.222654 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (71 ms)
6802 11:07:11.297910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
6803 11:07:11.298194 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
6805 11:07:11.311379 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
6806 11:07:11.981237 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (1511 ms)
6807 11:07:12.025141 [0:01:11.052671311] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6808 11:07:12.060447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
6809 11:07:12.060736 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
6811 11:07:12.074434 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
6812 11:07:13.204233 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (1222 ms)
6813 11:07:13.248510 [0:01:12.275749388] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6814 11:07:13.274397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
6815 11:07:13.274661 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
6817 11:07:13.286164 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
6818 11:07:14.929039 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1721 ms)
6819 11:07:14.972468 [0:01:13.999029465] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6820 11:07:15.009391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
6821 11:07:15.009708 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
6823 11:07:15.023120 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
6824 11:07:17.452777 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (2523 ms)
6825 11:07:17.496543 [0:01:16.523422311] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6826 11:07:17.544810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
6827 11:07:17.545110 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
6829 11:07:17.560019 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
6830 11:07:21.268540 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (3816 ms)
6831 11:07:21.311801 [0:01:20.338484235] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6832 11:07:21.358659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
6833 11:07:21.359223 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
6835 11:07:21.373365 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
6836 11:07:27.175359 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (5906 ms)
6837 11:07:27.217206 [0:01:26.243820389] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6838 11:07:27.265794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
6839 11:07:27.266392 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
6841 11:07:27.280814 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
6842 11:07:36.472222 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (9296 ms)
6843 11:07:36.515580 [0:01:35.542342543] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6844 11:07:36.544342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
6845 11:07:36.544607 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
6847 11:07:36.556072 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
6848 11:07:36.581790 [0:01:35.608664697] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6849 11:07:36.599624 Camera needs 4 requests, can't test only 1
6850 11:07:36.650091 [0:01:35.677182005] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6851 11:07:36.660155 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6852 11:07:36.717481 [0:01:35.744354928] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6853 11:07:36.717594
6854 11:07:36.780919 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (67 ms)
6855 11:07:36.845620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
6856 11:07:36.845895 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
6858 11:07:36.859406 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
6859 11:07:36.904247 Camera needs 4 requests, can't test only 2
6860 11:07:36.962634 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6861 11:07:37.021992
6862 11:07:37.091345 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (65 ms)
6863 11:07:37.163633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
6864 11:07:37.163921 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
6866 11:07:37.174729 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
6867 11:07:37.215218 Camera needs 4 requests, can't test only 3
6868 11:07:37.274235 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6869 11:07:37.333601
6870 11:07:37.407358 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (70 ms)
6871 11:07:37.473412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
6872 11:07:37.473689 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
6874 11:07:37.484276 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
6875 11:07:38.161970 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (1489 ms)
6876 11:07:38.206382 [0:01:37.232992082] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6877 11:07:38.239817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
6878 11:07:38.240099 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
6880 11:07:38.253034 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
6881 11:07:39.383142 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (1220 ms)
6882 11:07:39.428226 [0:01:38.455146774] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6883 11:07:39.457233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
6884 11:07:39.457503 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
6886 11:07:39.470228 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
6887 11:07:41.106832 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1723 ms)
6888 11:07:41.151690 [0:01:40.178269467] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6889 11:07:41.184496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
6890 11:07:41.184763 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
6892 11:07:41.197805 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
6893 11:07:43.625993 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (2519 ms)
6894 11:07:43.670484 [0:01:42.697121082] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6895 11:07:43.698860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
6896 11:07:43.699136 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
6898 11:07:43.711196 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
6899 11:07:47.439641 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (3813 ms)
6900 11:07:47.484398 [0:01:46.510929313] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6901 11:07:47.514880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
6902 11:07:47.515156 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
6904 11:07:47.526900 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
6905 11:07:53.344590 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (5904 ms)
6906 11:07:53.390423 [0:01:52.416635083] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6907 11:07:53.433505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
6908 11:07:53.433807 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
6910 11:07:53.451613 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
6911 11:08:02.643424 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (9298 ms)
6912 11:08:02.687775 [0:02:01.714181083] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6913 11:08:02.724861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
6914 11:08:02.725148 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
6916 11:08:02.736064 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
6917 11:08:02.750805 [0:02:01.777035622] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6918 11:08:02.777520 Camera needs 4 requests, can't test only 1
6919 11:08:02.815608 [0:02:01.841594314] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6920 11:08:02.843374 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6921 11:08:02.878182 [0:02:01.903953776] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6922 11:08:02.921335
6923 11:08:03.005884 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (62 ms)
6924 11:08:03.098184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
6925 11:08:03.098857 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
6927 11:08:03.116207 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
6928 11:08:03.170332 Camera needs 4 requests, can't test only 2
6929 11:08:03.253033 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6930 11:08:03.335403
6931 11:08:03.422202 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (63 ms)
6932 11:08:03.517841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
6933 11:08:03.518526 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
6935 11:08:03.533989 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
6936 11:08:03.586944 Camera needs 4 requests, can't test only 3
6937 11:08:03.661737 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6938 11:08:03.730252
6939 11:08:03.799382 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (63 ms)
6940 11:08:03.889467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
6941 11:08:03.890167 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
6943 11:08:03.906451 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
6944 11:08:06.076377 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (3243 ms)
6945 11:08:06.121306 [0:02:05.147243930] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6946 11:08:06.166410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
6947 11:08:06.166673 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
6949 11:08:06.183959 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
6950 11:08:09.642441 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (3566 ms)
6951 11:08:09.689345 [0:02:08.715311930] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6952 11:08:09.717401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
6953 11:08:09.717693 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
6955 11:08:09.729386 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
6956 11:08:14.712424 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (5068 ms)
6957 11:08:14.757177 [0:02:13.782813084] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6958 11:08:14.801619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
6959 11:08:14.802557 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
6961 11:08:14.815270 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
6962 11:08:22.165738 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (7453 ms)
6963 11:08:22.209987 [0:02:21.235479392] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6964 11:08:22.265702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
6965 11:08:22.266377 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
6967 11:08:22.282815 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
6968 11:08:33.508925 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (11343 ms)
6969 11:08:33.554281 [0:02:32.579731162] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6970 11:08:33.608238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
6971 11:08:33.608853 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
6973 11:08:33.625357 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
6974 11:08:51.133723 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (17624 ms)
6975 11:08:51.178800 [0:02:50.204091086] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6976 11:08:51.230479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
6977 11:08:51.231043 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
6979 11:08:51.246033 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
6980 11:09:18.925473 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (27791 ms)
6981 11:09:18.970223 [0:03:17.994912011] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6982 11:09:19.020805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
6983 11:09:19.021443 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
6985 11:09:19.035530 [0:03:18.060156549] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6986 11:09:19.041941 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
6987 11:09:19.098637 [0:03:18.122773626] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6988 11:09:19.101602 Camera needs 4 requests, can't test only 1
6989 11:09:19.165361 [0:03:18.189949088] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6990 11:09:19.176069 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6991 11:09:19.258860
6992 11:09:19.345628 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (65 ms)
6993 11:09:19.441230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
6994 11:09:19.441923 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
6996 11:09:19.455686 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
6997 11:09:19.515365 Camera needs 4 requests, can't test only 2
6998 11:09:19.597733 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6999 11:09:19.681795
7000 11:09:19.776665 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (62 ms)
7001 11:09:19.882955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
7002 11:09:19.883635 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
7004 11:09:19.894481 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
7005 11:09:19.948645 Camera needs 4 requests, can't test only 3
7006 11:09:20.029506 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7007 11:09:20.103942
7008 11:09:20.191986 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (65 ms)
7009 11:09:20.285362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
7010 11:09:20.286025 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
7012 11:09:20.299876 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
7013 11:09:22.395806 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (3272 ms)
7014 11:09:22.438177 [0:03:21.462876857] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7015 11:09:22.488356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
7016 11:09:22.488927 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
7018 11:09:22.502358 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
7019 11:09:25.962963 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (3566 ms)
7020 11:09:26.005110 [0:03:25.029566781] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7021 11:09:26.052901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
7022 11:09:26.053501 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
7024 11:09:26.064969 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
7025 11:09:31.028937 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (5065 ms)
7026 11:09:31.071133 [0:03:30.095660012] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7027 11:09:31.122009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
7028 11:09:31.122918 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
7030 11:09:31.136040 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
7031 11:09:38.481939 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (7453 ms)
7032 11:09:38.523222 [0:03:37.547342935] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7033 11:09:38.565121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
7034 11:09:38.565701 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
7036 11:09:38.577509 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
7037 11:09:49.823348 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (11340 ms)
7038 11:09:49.864965 [0:03:48.888772782] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7039 11:09:49.916692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
7040 11:09:49.917280 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
7042 11:09:49.929275 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
7043 11:10:07.441903 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (17618 ms)
7044 11:10:07.483508 [0:04:06.507215245] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7045 11:10:07.532935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
7046 11:10:07.533513 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
7048 11:10:07.544841 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
7049 11:10:35.234179 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (27791 ms)
7050 11:10:35.279784 [0:04:34.302913092] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7051 11:10:35.338484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
7052 11:10:35.339099 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
7054 11:10:35.348119 [0:04:34.367905708] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7055 11:10:35.354539 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
7056 11:10:35.409083 [0:04:34.432259246] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7057 11:10:35.412498 Camera needs 4 requests, can't test only 1
7058 11:10:35.475323 [0:04:34.498915785] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7059 11:10:35.489654 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7060 11:10:35.559909
7061 11:10:35.645676 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (63 ms)
7062 11:10:35.738247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
7063 11:10:35.738928 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
7065 11:10:35.752566 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
7066 11:10:35.808100 Camera needs 4 requests, can't test only 2
7067 11:10:35.895218 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7068 11:10:35.974435
7069 11:10:36.064424 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (66 ms)
7070 11:10:36.164673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
7071 11:10:36.165330 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
7073 11:10:36.180685 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
7074 11:10:36.238831 Camera needs 4 requests, can't test only 3
7075 11:10:36.311984 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7076 11:10:36.388010
7077 11:10:36.472791 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (65 ms)
7078 11:10:36.569762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
7079 11:10:36.570438 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
7081 11:10:36.583140 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
7082 11:10:38.701253 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (3267 ms)
7083 11:10:38.742396 [0:04:37.765281631] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7084 11:10:38.795254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
7085 11:10:38.795959 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
7087 11:10:38.808475 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
7088 11:10:42.261782 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (3560 ms)
7089 11:10:42.303520 [0:04:41.326632324] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7090 11:10:42.359021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
7091 11:10:42.359395 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
7093 11:10:42.371365 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
7094 11:10:47.325880 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (5063 ms)
7095 11:10:47.369841 [0:04:46.392772016] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7096 11:10:47.422798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
7097 11:10:47.423412 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
7099 11:10:47.436380 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
7100 11:10:54.778661 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (7452 ms)
7101 11:10:54.819400 [0:04:53.842204401] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7102 11:10:54.874018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
7103 11:10:54.874644 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
7105 11:10:54.887662 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
7106 11:11:06.117341 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (11338 ms)
7107 11:11:06.160631 [0:05:05.182841017] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7108 11:11:06.209243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
7109 11:11:06.209857 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
7111 11:11:06.219986 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
7112 11:11:23.737046 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (17619 ms)
7113 11:11:23.778802 [0:05:22.800908711] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7114 11:11:23.832464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
7115 11:11:23.833139 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
7117 11:11:23.846601 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
7118 11:11:51.529755 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (27792 ms)
7119 11:11:51.573934 [0:05:50.595660482] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7120 11:11:51.642341 [0:05:50.664103174] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7121 11:11:51.649037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
7122 11:11:51.649597 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
7124 11:11:51.655610 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
7125 11:11:51.709370 [0:05:50.731016097] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7126 11:11:51.712562 Camera needs 4 requests, can't test only 1
7127 11:11:51.777620 [0:05:50.799333482] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7128 11:11:51.784830 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7129 11:11:51.865328
7130 11:11:51.954631 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (66 ms)
7131 11:11:52.052897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
7132 11:11:52.053193 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
7134 11:11:52.064730 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
7135 11:11:52.115974 Camera needs 4 requests, can't test only 2
7136 11:11:52.186581 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7137 11:11:52.259098
7138 11:11:52.339857 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (65 ms)
7139 11:11:52.434606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
7140 11:11:52.435205 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
7142 11:11:52.449301 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
7143 11:11:52.505643 Camera needs 4 requests, can't test only 3
7144 11:11:52.587485 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7145 11:11:52.659840
7146 11:11:52.740651 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (67 ms)
7147 11:11:52.828171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
7148 11:11:52.828796 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
7150 11:11:52.839182 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
7151 11:11:54.982313 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (3248 ms)
7152 11:11:55.023445 [0:05:54.045111405] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7153 11:11:55.071868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
7154 11:11:55.072503 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
7156 11:11:55.086331 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
7157 11:11:58.548570 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (3566 ms)
7158 11:11:58.591923 [0:05:57.613542790] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7159 11:11:58.646931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
7160 11:11:58.647597 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
7162 11:11:58.660677 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
7163 11:12:03.614410 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (5065 ms)
7164 11:12:03.656095 [0:06:02.677472021] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7165 11:12:03.707353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
7166 11:12:03.708005 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
7168 11:12:03.721738 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
7169 11:12:11.067364 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (7453 ms)
7170 11:12:11.109242 [0:06:10.130293867] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7171 11:12:11.155813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
7172 11:12:11.156080 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
7174 11:12:11.164870 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
7175 11:12:22.410034 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (11342 ms)
7176 11:12:22.452837 [0:06:21.473695330] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7177 11:12:22.505715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
7178 11:12:22.506337 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
7180 11:12:22.518989 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
7181 11:12:40.029340 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (17618 ms)
7182 11:12:40.071790 [0:06:39.092569946] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7183 11:12:40.128482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
7184 11:12:40.129057 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
7186 11:12:40.139963 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
7187 11:13:07.825251 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (27795 ms)
7188 11:13:07.867205 [0:07:06.887137948] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7189 11:13:07.938017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
7190 11:13:07.938305 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
7192 11:13:07.948759 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
7193 11:13:08.347645 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (525 ms)
7194 11:13:08.444619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
7195 11:13:08.445283 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
7197 11:13:08.460791 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
7198 11:13:08.557776 [0:07:07.577574640] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7199 11:13:09.141605 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (794 ms)
7200 11:13:09.230069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
7201 11:13:09.230664 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
7203 11:13:09.251993 [0:07:08.272102794] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7204 11:13:09.255289 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
7205 11:13:09.932104 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (790 ms)
7206 11:13:09.976656 [0:07:08.997038486] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7207 11:13:10.030879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
7208 11:13:10.031548 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
7210 11:13:10.047725 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
7211 11:13:10.853622 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (920 ms)
7212 11:13:10.897934 [0:07:09.918262025] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7213 11:13:10.941781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
7214 11:13:10.942049 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
7216 11:13:10.956940 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
7217 11:13:12.074990 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (1221 ms)
7218 11:13:12.120409 [0:07:11.140443256] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7219 11:13:12.183921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
7220 11:13:12.184571 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
7222 11:13:12.202573 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
7223 11:13:13.798923 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1723 ms)
7224 11:13:13.843941 [0:07:12.863793025] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7225 11:13:13.898341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
7226 11:13:13.898948 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
7228 11:13:13.917164 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
7229 11:13:16.316285 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (2517 ms)
7230 11:13:16.361598 [0:07:15.381476256] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7231 11:13:16.423631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
7232 11:13:16.424275 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
7234 11:13:16.440264 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
7235 11:13:20.131401 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (3814 ms)
7236 11:13:20.175405 [0:07:19.195488410] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7237 11:13:20.222418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
7238 11:13:20.222978 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
7240 11:13:20.239058 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
7241 11:13:26.036021 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (5904 ms)
7242 11:13:26.080769 [0:07:25.100556333] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7243 11:13:26.136132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
7244 11:13:26.136842 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
7246 11:13:26.153927 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
7247 11:13:35.332743 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (9296 ms)
7248 11:13:35.377481 [0:07:34.397214718] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7249 11:13:35.421191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
7250 11:13:35.421802 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
7252 11:13:35.438007 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
7253 11:13:35.861219 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (524 ms)
7254 11:13:35.949422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
7255 11:13:35.949864 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
7257 11:13:35.963637 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
7258 11:13:36.056755 [0:07:35.076540565] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7259 11:13:36.646399 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (782 ms)
7260 11:13:36.729542 [0:07:35.749413257] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7261 11:13:36.736084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
7262 11:13:36.736435 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
7264 11:13:36.746552 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
7265 11:13:37.413572 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (767 ms)
7266 11:13:37.454650 [0:07:36.474238872] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7267 11:13:37.514913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
7268 11:13:37.515531 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
7270 11:13:37.527990 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
7271 11:13:38.335017 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (921 ms)
7272 11:13:38.377444 [0:07:37.397210026] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7273 11:13:38.420282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
7274 11:13:38.420591 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
7276 11:13:38.428065 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
7277 11:13:39.556586 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (1221 ms)
7278 11:13:39.597833 [0:07:38.617491334] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7279 11:13:39.641516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
7280 11:13:39.641818 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
7282 11:13:39.650540 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
7283 11:13:41.276785 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1720 ms)
7284 11:13:41.318879 [0:07:40.338332103] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7285 11:13:41.367091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
7286 11:13:41.367790 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
7288 11:13:41.379051 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
7289 11:13:43.794954 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (2517 ms)
7290 11:13:43.836171 [0:07:42.855779181] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7291 11:13:43.885457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
7292 11:13:43.885731 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
7294 11:13:43.897392 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
7295 11:13:47.606644 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (3811 ms)
7296 11:13:47.648854 [0:07:46.668623950] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7297 11:13:47.679060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
7298 11:13:47.679379 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
7300 11:13:47.688727 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
7301 11:13:53.513088 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (5905 ms)
7302 11:13:53.553532 [0:07:52.573276950] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7303 11:13:53.581528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
7304 11:13:53.581834 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
7306 11:13:53.593136 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
7307 11:14:02.811469 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (9298 ms)
7308 11:14:02.852500 [0:08:01.872116643] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7309 11:14:02.878459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
7310 11:14:02.878813 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
7312 11:14:02.888306 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
7313 11:14:03.336554 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (524 ms)
7314 11:14:03.417116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
7315 11:14:03.418017 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
7317 11:14:03.428699 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
7318 11:14:03.549479 [0:08:02.568548336] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7319 11:14:04.136690 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (799 ms)
7320 11:14:04.215099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
7321 11:14:04.215855 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
7323 11:14:04.226959 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
7324 11:14:04.247638 [0:08:03.266944028] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7325 11:14:04.932855 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (795 ms)
7326 11:14:04.972957 [0:08:03.992151874] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7327 11:14:05.016197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
7328 11:14:05.016881 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
7330 11:14:05.028864 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
7331 11:14:05.855807 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (923 ms)
7332 11:14:05.896381 [0:08:04.915502951] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7333 11:14:05.942077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
7334 11:14:05.942797 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
7336 11:14:05.953526 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
7337 11:14:07.076325 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (1219 ms)
7338 11:14:07.117048 [0:08:06.135992182] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7339 11:14:07.161128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
7340 11:14:07.161427 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
7342 11:14:07.174470 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
7343 11:14:08.798922 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1722 ms)
7344 11:14:08.839325 [0:08:07.858607028] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7345 11:14:08.893443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
7346 11:14:08.894054 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
7348 11:14:08.905250 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
7349 11:14:11.314492 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (2516 ms)
7350 11:14:11.355187 [0:08:10.374539721] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7351 11:14:11.384478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
7352 11:14:11.384748 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
7354 11:14:11.392442 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
7355 11:14:15.127892 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (3813 ms)
7356 11:14:15.169773 [0:08:14.188766336] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7357 11:14:15.190721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
7358 11:14:15.191023 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
7360 11:14:15.200001 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
7361 11:14:21.033071 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (5904 ms)
7362 11:14:21.075668 [0:08:20.094895183] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7363 11:14:21.099234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
7364 11:14:21.099529 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
7366 11:14:21.106638 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
7367 11:14:30.332048 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (9298 ms)
7368 11:14:30.374274 [0:08:29.392915183] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7369 11:14:30.420847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
7370 11:14:30.421641 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
7372 11:14:30.434764 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
7373 11:14:30.859079 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (527 ms)
7374 11:14:30.944921 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
7376 11:14:30.947919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
7377 11:14:30.959369 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
7378 11:14:31.056849 [0:08:30.075970645] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7379 11:14:31.642140 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (782 ms)
7380 11:14:31.718273 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
7382 11:14:31.721118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
7383 11:14:31.731831 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
7384 11:14:31.744942 [0:08:30.760283876] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7385 11:14:32.425438 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (783 ms)
7386 11:14:32.467517 [0:08:31.486359645] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7387 11:14:32.490411 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
7389 11:14:32.493356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
7390 11:14:32.503162 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
7391 11:14:33.348634 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (922 ms)
7392 11:14:33.389821 [0:08:32.408415491] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7393 11:14:33.436429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
7394 11:14:33.437233 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
7396 11:14:33.449780 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
7397 11:14:34.568513 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (1220 ms)
7398 11:14:34.610670 [0:08:33.629659722] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7399 11:14:34.633288 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
7401 11:14:34.636463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
7402 11:14:34.643268 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
7403 11:14:36.289995 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1720 ms)
7404 11:14:36.331327 [0:08:35.350097337] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7405 11:14:36.363237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
7406 11:14:36.363478 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
7408 11:14:36.372396 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
7409 11:14:38.808378 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (2518 ms)
7410 11:14:38.849686 [0:08:37.868262030] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7411 11:14:38.887310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
7412 11:14:38.888101 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
7414 11:14:38.898552 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
7415 11:14:42.622005 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (3813 ms)
7416 11:14:42.663542 [0:08:41.682207261] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7417 11:14:42.698951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
7418 11:14:42.699251 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
7420 11:14:42.712294 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
7421 11:14:48.528098 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (5905 ms)
7422 11:14:48.569388 [0:08:47.587885954] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7423 11:14:48.609538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
7424 11:14:48.610356 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
7426 11:14:48.620620 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
7427 11:14:57.823770 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (9295 ms)
7428 11:14:57.899580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
7429 11:14:57.899865 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
7431 11:14:57.909325 [----------] 120 tests from CaptureTests/SingleStream (516975 ms total)
7432 11:14:57.974686
7433 11:14:58.036088 [----------] Global test environment tear-down
7434 11:14:58.092967 [==========] 120 tests from 1 test suite ran. (516975 ms total)
7435 11:14:58.149863 <LAVA_SIGNAL_TESTSET STOP>
7436 11:14:58.150146 Received signal: <TESTSET> STOP
7437 11:14:58.150249 Closing test_set CaptureTests/SingleStream
7438 11:14:58.153027 + set +x
7439 11:14:58.156288 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14786775_1.6.2.3.1>
7440 11:14:58.156545 Received signal: <ENDRUN> 0_lc-compliance 14786775_1.6.2.3.1
7441 11:14:58.156641 Ending use of test pattern.
7442 11:14:58.156716 Ending test lava.0_lc-compliance (14786775_1.6.2.3.1), duration 518.97
7444 11:14:58.159396 <LAVA_TEST_RUNNER EXIT>
7445 11:14:58.159675 ok: lava_test_shell seems to have completed
7446 11:14:58.161819 Capture/Raw_1:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_2:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_3:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_5:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_8:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_13:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_21:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_34:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_55:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_89:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
7447 11:14:58.162044 end: 3.1 lava-test-shell (duration 00:08:40) [common]
7448 11:14:58.162150 end: 3 lava-test-retry (duration 00:08:40) [common]
7449 11:14:58.162251 start: 4 finalize (timeout 00:10:00) [common]
7450 11:14:58.162389 start: 4.1 power-off (timeout 00:00:30) [common]
7451 11:14:58.162658 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2', '--port=1', '--command=off']
7452 11:15:00.234088 >> Command sent successfully.
7453 11:15:00.248304 Returned 0 in 2 seconds
7454 11:15:00.248888 end: 4.1 power-off (duration 00:00:02) [common]
7456 11:15:00.249835 start: 4.2 read-feedback (timeout 00:09:58) [common]
7457 11:15:00.250490 Listened to connection for namespace 'common' for up to 1s
7458 11:15:01.251523 Finalising connection for namespace 'common'
7459 11:15:01.252044 Disconnecting from shell: Finalise
7460 11:15:01.252378 / #
7461 11:15:01.353123 end: 4.2 read-feedback (duration 00:00:01) [common]
7462 11:15:01.353630 end: 4 finalize (duration 00:00:03) [common]
7463 11:15:01.354077 Cleaning after the job
7464 11:15:01.354521 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/ramdisk
7465 11:15:01.364514 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/kernel
7466 11:15:01.397044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/dtb
7467 11:15:01.397371 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/nfsrootfs
7468 11:15:01.445719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786775/tftp-deploy-d4n7v1xj/modules
7469 11:15:01.451773 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786775
7470 11:15:01.754053 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786775
7471 11:15:01.754256 Job finished correctly