Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 11:06:22.182294 lava-dispatcher, installed at version: 2024.05
2 11:06:22.182500 start: 0 validate
3 11:06:22.182625 Start time: 2024-07-10 11:06:22.182619+00:00 (UTC)
4 11:06:22.182755 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:06:22.182894 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:06:22.454460 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:06:22.454668 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:06:24.671900 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:06:24.672105 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:06:24.937992 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:06:24.938140 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:06:25.206107 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:06:25.206267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:07:14.466141 validate duration: 52.28
16 11:07:14.466383 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:07:14.466478 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:07:14.466557 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:07:14.466714 Not decompressing ramdisk as can be used compressed.
20 11:07:14.466799 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 11:07:14.466857 saving as /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/ramdisk/initrd.cpio.gz
22 11:07:14.466939 total size: 5628151 (5 MB)
23 11:07:14.734182 progress 0 % (0 MB)
24 11:07:14.735948 progress 5 % (0 MB)
25 11:07:14.737583 progress 10 % (0 MB)
26 11:07:14.738945 progress 15 % (0 MB)
27 11:07:14.740632 progress 20 % (1 MB)
28 11:07:14.742024 progress 25 % (1 MB)
29 11:07:14.743638 progress 30 % (1 MB)
30 11:07:14.745150 progress 35 % (1 MB)
31 11:07:14.746481 progress 40 % (2 MB)
32 11:07:14.748022 progress 45 % (2 MB)
33 11:07:14.749384 progress 50 % (2 MB)
34 11:07:14.750867 progress 55 % (2 MB)
35 11:07:14.752417 progress 60 % (3 MB)
36 11:07:14.753745 progress 65 % (3 MB)
37 11:07:14.755245 progress 70 % (3 MB)
38 11:07:14.756652 progress 75 % (4 MB)
39 11:07:14.758199 progress 80 % (4 MB)
40 11:07:14.759610 progress 85 % (4 MB)
41 11:07:14.761132 progress 90 % (4 MB)
42 11:07:14.762618 progress 95 % (5 MB)
43 11:07:14.764034 progress 100 % (5 MB)
44 11:07:14.764242 5 MB downloaded in 0.30 s (18.05 MB/s)
45 11:07:14.764390 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:07:14.764606 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:07:14.764685 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:07:14.764760 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:07:14.764893 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:07:14.764954 saving as /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/kernel/Image
52 11:07:14.765006 total size: 54813184 (52 MB)
53 11:07:14.765059 No compression specified
54 11:07:15.032479 progress 0 % (0 MB)
55 11:07:15.046226 progress 5 % (2 MB)
56 11:07:15.060146 progress 10 % (5 MB)
57 11:07:15.074025 progress 15 % (7 MB)
58 11:07:15.087926 progress 20 % (10 MB)
59 11:07:15.101806 progress 25 % (13 MB)
60 11:07:15.115375 progress 30 % (15 MB)
61 11:07:15.129097 progress 35 % (18 MB)
62 11:07:15.142955 progress 40 % (20 MB)
63 11:07:15.156804 progress 45 % (23 MB)
64 11:07:15.170775 progress 50 % (26 MB)
65 11:07:15.185050 progress 55 % (28 MB)
66 11:07:15.198854 progress 60 % (31 MB)
67 11:07:15.212984 progress 65 % (34 MB)
68 11:07:15.226579 progress 70 % (36 MB)
69 11:07:15.240419 progress 75 % (39 MB)
70 11:07:15.254156 progress 80 % (41 MB)
71 11:07:15.267808 progress 85 % (44 MB)
72 11:07:15.281573 progress 90 % (47 MB)
73 11:07:15.295156 progress 95 % (49 MB)
74 11:07:15.308628 progress 100 % (52 MB)
75 11:07:15.308869 52 MB downloaded in 0.54 s (96.12 MB/s)
76 11:07:15.309013 end: 1.2.1 http-download (duration 00:00:01) [common]
78 11:07:15.309219 end: 1.2 download-retry (duration 00:00:01) [common]
79 11:07:15.309298 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:07:15.309372 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:07:15.309498 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:07:15.309558 saving as /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/dtb/mt8192-asurada-spherion-r0.dtb
83 11:07:15.309610 total size: 47258 (0 MB)
84 11:07:15.309662 No compression specified
85 11:07:15.576010 progress 69 % (0 MB)
86 11:07:15.576314 progress 100 % (0 MB)
87 11:07:15.576500 0 MB downloaded in 0.27 s (0.17 MB/s)
88 11:07:15.576630 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:07:15.576832 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:07:15.576908 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:07:15.576988 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:07:15.577115 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 11:07:15.577174 saving as /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/nfsrootfs/full.rootfs.tar
95 11:07:15.577226 total size: 69067788 (65 MB)
96 11:07:15.577280 Using unxz to decompress xz
97 11:07:15.843793 progress 0 % (0 MB)
98 11:07:16.029287 progress 5 % (3 MB)
99 11:07:16.233500 progress 10 % (6 MB)
100 11:07:16.447926 progress 15 % (9 MB)
101 11:07:16.612305 progress 20 % (13 MB)
102 11:07:16.794628 progress 25 % (16 MB)
103 11:07:16.986606 progress 30 % (19 MB)
104 11:07:17.108851 progress 35 % (23 MB)
105 11:07:17.208700 progress 40 % (26 MB)
106 11:07:17.410241 progress 45 % (29 MB)
107 11:07:17.620005 progress 50 % (32 MB)
108 11:07:17.819787 progress 55 % (36 MB)
109 11:07:18.033582 progress 60 % (39 MB)
110 11:07:18.225984 progress 65 % (42 MB)
111 11:07:18.424075 progress 70 % (46 MB)
112 11:07:18.614745 progress 75 % (49 MB)
113 11:07:18.817440 progress 80 % (52 MB)
114 11:07:18.988092 progress 85 % (56 MB)
115 11:07:19.177458 progress 90 % (59 MB)
116 11:07:19.378316 progress 95 % (62 MB)
117 11:07:19.580096 progress 100 % (65 MB)
118 11:07:19.586286 65 MB downloaded in 4.01 s (16.43 MB/s)
119 11:07:19.586436 end: 1.4.1 http-download (duration 00:00:04) [common]
121 11:07:19.586640 end: 1.4 download-retry (duration 00:00:04) [common]
122 11:07:19.586717 start: 1.5 download-retry (timeout 00:09:55) [common]
123 11:07:19.586790 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 11:07:19.586916 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:07:19.586975 saving as /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/modules/modules.tar
126 11:07:19.587028 total size: 8607984 (8 MB)
127 11:07:19.587081 Using unxz to decompress xz
128 11:07:19.588293 progress 0 % (0 MB)
129 11:07:19.609203 progress 5 % (0 MB)
130 11:07:19.633580 progress 10 % (0 MB)
131 11:07:19.657665 progress 15 % (1 MB)
132 11:07:19.681844 progress 20 % (1 MB)
133 11:07:19.704825 progress 25 % (2 MB)
134 11:07:19.727871 progress 30 % (2 MB)
135 11:07:19.749740 progress 35 % (2 MB)
136 11:07:19.775884 progress 40 % (3 MB)
137 11:07:19.800038 progress 45 % (3 MB)
138 11:07:19.824048 progress 50 % (4 MB)
139 11:07:19.848386 progress 55 % (4 MB)
140 11:07:19.873091 progress 60 % (4 MB)
141 11:07:19.896949 progress 65 % (5 MB)
142 11:07:19.922176 progress 70 % (5 MB)
143 11:07:19.949183 progress 75 % (6 MB)
144 11:07:19.977384 progress 80 % (6 MB)
145 11:07:20.001082 progress 85 % (7 MB)
146 11:07:20.023857 progress 90 % (7 MB)
147 11:07:20.047367 progress 95 % (7 MB)
148 11:07:20.069931 progress 100 % (8 MB)
149 11:07:20.075258 8 MB downloaded in 0.49 s (16.81 MB/s)
150 11:07:20.075404 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:07:20.075736 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:07:20.075854 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 11:07:20.075957 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 11:07:21.681870 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786847/extract-nfsrootfs-fdzh_dox
156 11:07:21.682042 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:07:21.682133 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 11:07:21.682286 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_
159 11:07:21.682400 makedir: /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin
160 11:07:21.682489 makedir: /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/tests
161 11:07:21.682576 makedir: /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/results
162 11:07:21.682659 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-add-keys
163 11:07:21.682781 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-add-sources
164 11:07:21.682896 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-background-process-start
165 11:07:21.683019 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-background-process-stop
166 11:07:21.683142 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-common-functions
167 11:07:21.683257 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-echo-ipv4
168 11:07:21.683370 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-install-packages
169 11:07:21.683489 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-installed-packages
170 11:07:21.683603 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-os-build
171 11:07:21.683716 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-probe-channel
172 11:07:21.683827 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-probe-ip
173 11:07:21.683941 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-target-ip
174 11:07:21.684051 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-target-mac
175 11:07:21.684163 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-target-storage
176 11:07:21.684280 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-test-case
177 11:07:21.684398 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-test-event
178 11:07:21.684508 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-test-feedback
179 11:07:21.684620 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-test-raise
180 11:07:21.684731 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-test-reference
181 11:07:21.684842 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-test-runner
182 11:07:21.684953 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-test-set
183 11:07:21.685063 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-test-shell
184 11:07:21.685176 Updating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-install-packages (oe)
185 11:07:21.685317 Updating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/bin/lava-installed-packages (oe)
186 11:07:21.685426 Creating /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/environment
187 11:07:21.685511 LAVA metadata
188 11:07:21.685572 - LAVA_JOB_ID=14786847
189 11:07:21.685627 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:07:21.685756 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 11:07:21.685817 skipped lava-vland-overlay
192 11:07:21.685885 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:07:21.685956 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 11:07:21.686011 skipped lava-multinode-overlay
195 11:07:21.686076 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:07:21.686145 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 11:07:21.686208 Loading test definitions
198 11:07:21.686281 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 11:07:21.686342 Using /lava-14786847 at stage 0
200 11:07:21.686639 uuid=14786847_1.6.2.3.1 testdef=None
201 11:07:21.686720 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:07:21.686795 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 11:07:21.687214 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:07:21.687413 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 11:07:21.688109 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:07:21.688315 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 11:07:21.688860 runner path: /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/0/tests/0_lc-compliance test_uuid 14786847_1.6.2.3.1
210 11:07:21.689005 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:07:21.689184 Creating lava-test-runner.conf files
213 11:07:21.689239 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786847/lava-overlay-bodo31y_/lava-14786847/0 for stage 0
214 11:07:21.689318 - 0_lc-compliance
215 11:07:21.689406 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:07:21.689482 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 11:07:21.695600 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:07:21.695693 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 11:07:21.695771 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:07:21.695850 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:07:21.695926 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 11:07:21.852297 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:07:21.852454 start: 1.6.4 extract-modules (timeout 00:09:53) [common]
224 11:07:21.852572 extracting modules file /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786847/extract-nfsrootfs-fdzh_dox
225 11:07:22.137153 extracting modules file /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786847/extract-overlay-ramdisk-l82rkai7/ramdisk
226 11:07:22.370071 end: 1.6.4 extract-modules (duration 00:00:01) [common]
227 11:07:22.370231 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 11:07:22.370340 [common] Applying overlay to NFS
229 11:07:22.370425 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786847/compress-overlay-w3eki0yf/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786847/extract-nfsrootfs-fdzh_dox
230 11:07:22.381159 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:07:22.381282 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 11:07:22.381386 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:07:22.381489 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 11:07:22.381579 Building ramdisk /var/lib/lava/dispatcher/tmp/14786847/extract-overlay-ramdisk-l82rkai7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786847/extract-overlay-ramdisk-l82rkai7/ramdisk
235 11:07:22.678030 >> 129845 blocks
236 11:07:24.745312 rename /var/lib/lava/dispatcher/tmp/14786847/extract-overlay-ramdisk-l82rkai7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/ramdisk/ramdisk.cpio.gz
237 11:07:24.745474 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:07:24.745561 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 11:07:24.745639 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 11:07:24.745716 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/kernel/Image']
241 11:07:38.610935 Returned 0 in 13 seconds
242 11:07:38.611101 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/kernel/image.itb
243 11:07:39.015004 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:07:39.015148 output: Created: Wed Jul 10 12:07:38 2024
245 11:07:39.015241 output: Image 0 (kernel-1)
246 11:07:39.015324 output: Description:
247 11:07:39.015403 output: Created: Wed Jul 10 12:07:38 2024
248 11:07:39.015475 output: Type: Kernel Image
249 11:07:39.015528 output: Compression: lzma compressed
250 11:07:39.015580 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
251 11:07:39.015630 output: Architecture: AArch64
252 11:07:39.015680 output: OS: Linux
253 11:07:39.015728 output: Load Address: 0x00000000
254 11:07:39.015777 output: Entry Point: 0x00000000
255 11:07:39.015825 output: Hash algo: crc32
256 11:07:39.015876 output: Hash value: 9bb85fb9
257 11:07:39.015925 output: Image 1 (fdt-1)
258 11:07:39.015975 output: Description: mt8192-asurada-spherion-r0
259 11:07:39.016023 output: Created: Wed Jul 10 12:07:38 2024
260 11:07:39.016071 output: Type: Flat Device Tree
261 11:07:39.016118 output: Compression: uncompressed
262 11:07:39.016166 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 11:07:39.016216 output: Architecture: AArch64
264 11:07:39.016265 output: Hash algo: crc32
265 11:07:39.016313 output: Hash value: 0f8e4d2e
266 11:07:39.016361 output: Image 2 (ramdisk-1)
267 11:07:39.016409 output: Description: unavailable
268 11:07:39.016457 output: Created: Wed Jul 10 12:07:38 2024
269 11:07:39.016505 output: Type: RAMDisk Image
270 11:07:39.016553 output: Compression: uncompressed
271 11:07:39.016600 output: Data Size: 18708428 Bytes = 18269.95 KiB = 17.84 MiB
272 11:07:39.016648 output: Architecture: AArch64
273 11:07:39.016696 output: OS: Linux
274 11:07:39.016742 output: Load Address: unavailable
275 11:07:39.016789 output: Entry Point: unavailable
276 11:07:39.016836 output: Hash algo: crc32
277 11:07:39.016883 output: Hash value: c332d312
278 11:07:39.016930 output: Default Configuration: 'conf-1'
279 11:07:39.016978 output: Configuration 0 (conf-1)
280 11:07:39.017026 output: Description: mt8192-asurada-spherion-r0
281 11:07:39.017073 output: Kernel: kernel-1
282 11:07:39.017121 output: Init Ramdisk: ramdisk-1
283 11:07:39.017168 output: FDT: fdt-1
284 11:07:39.017215 output: Loadables: kernel-1
285 11:07:39.017262 output:
286 11:07:39.017359 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 11:07:39.017434 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 11:07:39.017508 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 11:07:39.017583 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 11:07:39.017640 No LXC device requested
291 11:07:39.017704 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:07:39.017773 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 11:07:39.017841 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:07:39.017895 Checking files for TFTP limit of 4294967296 bytes.
295 11:07:39.018256 end: 1 tftp-deploy (duration 00:00:25) [common]
296 11:07:39.018350 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:07:39.018430 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:07:39.018535 substitutions:
299 11:07:39.018623 - {DTB}: 14786847/tftp-deploy-d2dascnn/dtb/mt8192-asurada-spherion-r0.dtb
300 11:07:39.018710 - {INITRD}: 14786847/tftp-deploy-d2dascnn/ramdisk/ramdisk.cpio.gz
301 11:07:39.018791 - {KERNEL}: 14786847/tftp-deploy-d2dascnn/kernel/Image
302 11:07:39.018869 - {LAVA_MAC}: None
303 11:07:39.018932 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786847/extract-nfsrootfs-fdzh_dox
304 11:07:39.018984 - {NFS_SERVER_IP}: 192.168.201.1
305 11:07:39.019034 - {PRESEED_CONFIG}: None
306 11:07:39.019088 - {PRESEED_LOCAL}: None
307 11:07:39.019137 - {RAMDISK}: 14786847/tftp-deploy-d2dascnn/ramdisk/ramdisk.cpio.gz
308 11:07:39.019187 - {ROOT_PART}: None
309 11:07:39.019236 - {ROOT}: None
310 11:07:39.019285 - {SERVER_IP}: 192.168.201.1
311 11:07:39.019334 - {TEE}: None
312 11:07:39.019383 Parsed boot commands:
313 11:07:39.019439 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:07:39.019583 Parsed boot commands: tftpboot 192.168.201.1 14786847/tftp-deploy-d2dascnn/kernel/image.itb 14786847/tftp-deploy-d2dascnn/kernel/cmdline
315 11:07:39.019662 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:07:39.019735 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:07:39.019805 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:07:39.019874 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:07:39.019928 Not connected, no need to disconnect.
320 11:07:39.019994 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:07:39.020060 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:07:39.020114 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 11:07:39.022917 Setting prompt string to ['lava-test: # ']
324 11:07:39.023221 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:07:39.023320 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:07:39.023408 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:07:39.023505 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:07:39.023680 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=reboot']
329 11:07:48.161930 >> Command sent successfully.
330 11:07:48.177340 Returned 0 in 9 seconds
331 11:07:48.178120 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 11:07:48.179818 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 11:07:48.180247 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 11:07:48.180640 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:07:48.180931 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:07:48.181259 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:07:48.183284 [Enter `^Ec?' for help]
339 11:07:49.800697
340 11:07:49.800815
341 11:07:49.800874 F0: 102B 0000
342 11:07:49.800942
343 11:07:49.800994 F3: 1001 0000 [0200]
344 11:07:49.803981
345 11:07:49.804074 F3: 1001 0000
346 11:07:49.804184
347 11:07:49.804265 F7: 102D 0000
348 11:07:49.804358
349 11:07:49.807917 F1: 0000 0000
350 11:07:49.808009
351 11:07:49.808104 V0: 0000 0000 [0001]
352 11:07:49.808184
353 11:07:49.808270 00: 0007 8000
354 11:07:49.808349
355 11:07:49.811358 01: 0000 0000
356 11:07:49.811493
357 11:07:49.811560 BP: 0C00 0209 [0000]
358 11:07:49.811612
359 11:07:49.814816 G0: 1182 0000
360 11:07:49.814889
361 11:07:49.814942 EC: 0000 0021 [4000]
362 11:07:49.814992
363 11:07:49.818192 S7: 0000 0000 [0000]
364 11:07:49.818251
365 11:07:49.818301 CC: 0000 0000 [0001]
366 11:07:49.818350
367 11:07:49.821662 T0: 0000 0040 [010F]
368 11:07:49.821729
369 11:07:49.821779 Jump to BL
370 11:07:49.821826
371 11:07:49.847267
372 11:07:49.847374
373 11:07:49.855011 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 11:07:49.858608 ARM64: Exception handlers installed.
375 11:07:49.862585 ARM64: Testing exception
376 11:07:49.866096 ARM64: Done test exception
377 11:07:49.872921 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 11:07:49.883231 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 11:07:49.889685 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 11:07:49.899661 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 11:07:49.906585 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 11:07:49.913200 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 11:07:49.923879 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 11:07:49.930589 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 11:07:49.950112 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 11:07:49.953667 WDT: Last reset was cold boot
387 11:07:49.956923 SPI1(PAD0) initialized at 2873684 Hz
388 11:07:49.960320 SPI5(PAD0) initialized at 992727 Hz
389 11:07:49.963843 VBOOT: Loading verstage.
390 11:07:49.970350 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 11:07:49.974167 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 11:07:49.977276 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 11:07:49.980141 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 11:07:49.987639 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 11:07:49.994459 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 11:07:50.005581 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 11:07:50.005653
398 11:07:50.005721
399 11:07:50.015401 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 11:07:50.018579 ARM64: Exception handlers installed.
401 11:07:50.022138 ARM64: Testing exception
402 11:07:50.022232 ARM64: Done test exception
403 11:07:50.028773 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 11:07:50.032168 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 11:07:50.046873 Probing TPM: . done!
406 11:07:50.047013 TPM ready after 0 ms
407 11:07:50.052919 Connected to device vid:did:rid of 1ae0:0028:00
408 11:07:50.063075 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
409 11:07:50.100080 Initialized TPM device CR50 revision 0
410 11:07:50.112037 tlcl_send_startup: Startup return code is 0
411 11:07:50.112122 TPM: setup succeeded
412 11:07:50.123548 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 11:07:50.131972 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 11:07:50.138878 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 11:07:50.151420 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 11:07:50.154195 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 11:07:50.158013 in-header: 03 07 00 00 08 00 00 00
418 11:07:50.161806 in-data: aa e4 47 04 13 02 00 00
419 11:07:50.164737 Chrome EC: UHEPI supported
420 11:07:50.171355 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 11:07:50.174723 in-header: 03 a9 00 00 08 00 00 00
422 11:07:50.177952 in-data: 84 60 60 08 00 00 00 00
423 11:07:50.178030 Phase 1
424 11:07:50.184969 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 11:07:50.187963 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 11:07:50.194648 VB2:vb2_check_recovery() Recovery was requested manually
427 11:07:50.201462 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 11:07:50.201538 Recovery requested (1009000e)
429 11:07:50.210690 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 11:07:50.215958 tlcl_extend: response is 0
431 11:07:50.224233 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 11:07:50.229603 tlcl_extend: response is 0
433 11:07:50.236121 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 11:07:50.256456 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 11:07:50.263349 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 11:07:50.263585
437 11:07:50.263722
438 11:07:50.274293 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 11:07:50.277301 ARM64: Exception handlers installed.
440 11:07:50.277685 ARM64: Testing exception
441 11:07:50.280803 ARM64: Done test exception
442 11:07:50.301481 pmic_efuse_setting: Set efuses in 11 msecs
443 11:07:50.304984 pmwrap_interface_init: Select PMIF_VLD_RDY
444 11:07:50.311351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 11:07:50.314708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 11:07:50.321357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 11:07:50.324776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 11:07:50.331152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 11:07:50.334368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 11:07:50.341514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 11:07:50.344481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 11:07:50.347907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 11:07:50.354325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 11:07:50.357844 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 11:07:50.364758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 11:07:50.367739 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 11:07:50.374715 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 11:07:50.381421 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 11:07:50.384520 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 11:07:50.391303 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 11:07:50.397703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 11:07:50.401301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 11:07:50.408018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 11:07:50.414478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 11:07:50.418152 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 11:07:50.424963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 11:07:50.431821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 11:07:50.434374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 11:07:50.441417 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 11:07:50.448192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 11:07:50.451312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 11:07:50.454293 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 11:07:50.461483 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 11:07:50.464769 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 11:07:50.471191 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 11:07:50.474709 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 11:07:50.481337 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 11:07:50.484549 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 11:07:50.491326 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 11:07:50.494358 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 11:07:50.501352 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 11:07:50.504253 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 11:07:50.508453 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 11:07:50.515018 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 11:07:50.518735 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 11:07:50.521681 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 11:07:50.528307 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 11:07:50.531554 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 11:07:50.535030 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 11:07:50.542067 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 11:07:50.545163 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 11:07:50.548145 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 11:07:50.551527 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 11:07:50.558723 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 11:07:50.564509 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 11:07:50.574336 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 11:07:50.578097 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 11:07:50.584432 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 11:07:50.594587 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 11:07:50.598059 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 11:07:50.604172 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:07:50.607663 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 11:07:50.615193 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x30
504 11:07:50.621656 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 11:07:50.624826 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
506 11:07:50.631478 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 11:07:50.639509 [RTC]rtc_get_frequency_meter,154: input=15, output=835
508 11:07:50.649188 [RTC]rtc_get_frequency_meter,154: input=7, output=709
509 11:07:50.658473 [RTC]rtc_get_frequency_meter,154: input=11, output=772
510 11:07:50.668001 [RTC]rtc_get_frequency_meter,154: input=13, output=804
511 11:07:50.677083 [RTC]rtc_get_frequency_meter,154: input=12, output=787
512 11:07:50.686673 [RTC]rtc_get_frequency_meter,154: input=12, output=789
513 11:07:50.696836 [RTC]rtc_get_frequency_meter,154: input=13, output=804
514 11:07:50.699729 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
515 11:07:50.706940 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
516 11:07:50.710284 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 11:07:50.713301 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
518 11:07:50.719955 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 11:07:50.723303 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
520 11:07:50.726497 ADC[4]: Raw value=903400 ID=7
521 11:07:50.726876 ADC[3]: Raw value=212912 ID=1
522 11:07:50.730211 RAM Code: 0x71
523 11:07:50.733395 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 11:07:50.740139 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 11:07:50.746346 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 11:07:50.753478 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 11:07:50.756573 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 11:07:50.759597 in-header: 03 07 00 00 08 00 00 00
529 11:07:50.762908 in-data: aa e4 47 04 13 02 00 00
530 11:07:50.766106 Chrome EC: UHEPI supported
531 11:07:50.772812 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 11:07:50.776272 in-header: 03 a9 00 00 08 00 00 00
533 11:07:50.779544 in-data: 84 60 60 08 00 00 00 00
534 11:07:50.782827 MRC: failed to locate region type 0.
535 11:07:50.789609 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 11:07:50.793144 DRAM-K: Running full calibration
537 11:07:50.799986 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 11:07:50.802865 header.status = 0x0
539 11:07:50.806489 header.version = 0x6 (expected: 0x6)
540 11:07:50.809713 header.size = 0xd00 (expected: 0xd00)
541 11:07:50.810100 header.flags = 0x0
542 11:07:50.815906 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 11:07:50.833698 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 11:07:50.840489 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 11:07:50.843935 dram_init: ddr_geometry: 2
546 11:07:50.846861 [EMI] MDL number = 2
547 11:07:50.847241 [EMI] Get MDL freq = 0
548 11:07:50.850306 dram_init: ddr_type: 0
549 11:07:50.850685 is_discrete_lpddr4: 1
550 11:07:50.853703 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 11:07:50.854115
552 11:07:50.854416
553 11:07:50.857178 [Bian_co] ETT version 0.0.0.1
554 11:07:50.863684 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 11:07:50.864065
556 11:07:50.867275 dramc_set_vcore_voltage set vcore to 650000
557 11:07:50.870315 Read voltage for 800, 4
558 11:07:50.870693 Vio18 = 0
559 11:07:50.870989 Vcore = 650000
560 11:07:50.871262 Vdram = 0
561 11:07:50.873558 Vddq = 0
562 11:07:50.873938 Vmddr = 0
563 11:07:50.877231 dram_init: config_dvfs: 1
564 11:07:50.880364 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 11:07:50.887068 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 11:07:50.890620 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
567 11:07:50.894066 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
568 11:07:50.896861 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
569 11:07:50.900270 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
570 11:07:50.903645 MEM_TYPE=3, freq_sel=18
571 11:07:50.906950 sv_algorithm_assistance_LP4_1600
572 11:07:50.910440 ============ PULL DRAM RESETB DOWN ============
573 11:07:50.913871 ========== PULL DRAM RESETB DOWN end =========
574 11:07:50.920242 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 11:07:50.924178 ===================================
576 11:07:50.927060 LPDDR4 DRAM CONFIGURATION
577 11:07:50.930283 ===================================
578 11:07:50.930664 EX_ROW_EN[0] = 0x0
579 11:07:50.934083 EX_ROW_EN[1] = 0x0
580 11:07:50.934509 LP4Y_EN = 0x0
581 11:07:50.937795 WORK_FSP = 0x0
582 11:07:50.938180 WL = 0x2
583 11:07:50.941541 RL = 0x2
584 11:07:50.941997 BL = 0x2
585 11:07:50.942300 RPST = 0x0
586 11:07:50.945502 RD_PRE = 0x0
587 11:07:50.945891 WR_PRE = 0x1
588 11:07:50.948459 WR_PST = 0x0
589 11:07:50.948891 DBI_WR = 0x0
590 11:07:50.952286 DBI_RD = 0x0
591 11:07:50.952685 OTF = 0x1
592 11:07:50.956436 ===================================
593 11:07:50.959669 ===================================
594 11:07:50.960064 ANA top config
595 11:07:50.963584 ===================================
596 11:07:50.967336 DLL_ASYNC_EN = 0
597 11:07:50.971043 ALL_SLAVE_EN = 1
598 11:07:50.971607 NEW_RANK_MODE = 1
599 11:07:50.973899 DLL_IDLE_MODE = 1
600 11:07:50.977308 LP45_APHY_COMB_EN = 1
601 11:07:50.980591 TX_ODT_DIS = 1
602 11:07:50.983967 NEW_8X_MODE = 1
603 11:07:50.987524 ===================================
604 11:07:50.990846 ===================================
605 11:07:50.991325 data_rate = 1600
606 11:07:50.994330 CKR = 1
607 11:07:50.997139 DQ_P2S_RATIO = 8
608 11:07:51.000909 ===================================
609 11:07:51.004296 CA_P2S_RATIO = 8
610 11:07:51.007414 DQ_CA_OPEN = 0
611 11:07:51.010734 DQ_SEMI_OPEN = 0
612 11:07:51.011117 CA_SEMI_OPEN = 0
613 11:07:51.013951 CA_FULL_RATE = 0
614 11:07:51.017289 DQ_CKDIV4_EN = 1
615 11:07:51.020824 CA_CKDIV4_EN = 1
616 11:07:51.023859 CA_PREDIV_EN = 0
617 11:07:51.027354 PH8_DLY = 0
618 11:07:51.027802 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 11:07:51.030559 DQ_AAMCK_DIV = 4
620 11:07:51.034104 CA_AAMCK_DIV = 4
621 11:07:51.037690 CA_ADMCK_DIV = 4
622 11:07:51.040468 DQ_TRACK_CA_EN = 0
623 11:07:51.043928 CA_PICK = 800
624 11:07:51.044340 CA_MCKIO = 800
625 11:07:51.047509 MCKIO_SEMI = 0
626 11:07:51.050843 PLL_FREQ = 3068
627 11:07:51.053817 DQ_UI_PI_RATIO = 32
628 11:07:51.057302 CA_UI_PI_RATIO = 0
629 11:07:51.060420 ===================================
630 11:07:51.063857 ===================================
631 11:07:51.066901 memory_type:LPDDR4
632 11:07:51.067300 GP_NUM : 10
633 11:07:51.070117 SRAM_EN : 1
634 11:07:51.073311 MD32_EN : 0
635 11:07:51.076956 ===================================
636 11:07:51.077415 [ANA_INIT] >>>>>>>>>>>>>>
637 11:07:51.080590 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 11:07:51.084055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 11:07:51.086587 ===================================
640 11:07:51.089919 data_rate = 1600,PCW = 0X7600
641 11:07:51.093272 ===================================
642 11:07:51.096477 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 11:07:51.103131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 11:07:51.106768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 11:07:51.113222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 11:07:51.116667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 11:07:51.120120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 11:07:51.120502 [ANA_INIT] flow start
649 11:07:51.123454 [ANA_INIT] PLL >>>>>>>>
650 11:07:51.126565 [ANA_INIT] PLL <<<<<<<<
651 11:07:51.130006 [ANA_INIT] MIDPI >>>>>>>>
652 11:07:51.130495 [ANA_INIT] MIDPI <<<<<<<<
653 11:07:51.133425 [ANA_INIT] DLL >>>>>>>>
654 11:07:51.136379 [ANA_INIT] flow end
655 11:07:51.139902 ============ LP4 DIFF to SE enter ============
656 11:07:51.143464 ============ LP4 DIFF to SE exit ============
657 11:07:51.146268 [ANA_INIT] <<<<<<<<<<<<<
658 11:07:51.149819 [Flow] Enable top DCM control >>>>>
659 11:07:51.153171 [Flow] Enable top DCM control <<<<<
660 11:07:51.156268 Enable DLL master slave shuffle
661 11:07:51.159594 ==============================================================
662 11:07:51.163081 Gating Mode config
663 11:07:51.166483 ==============================================================
664 11:07:51.169403 Config description:
665 11:07:51.179694 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 11:07:51.186078 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 11:07:51.189609 SELPH_MODE 0: By rank 1: By Phase
668 11:07:51.196185 ==============================================================
669 11:07:51.199577 GAT_TRACK_EN = 1
670 11:07:51.202820 RX_GATING_MODE = 2
671 11:07:51.205752 RX_GATING_TRACK_MODE = 2
672 11:07:51.209035 SELPH_MODE = 1
673 11:07:51.212667 PICG_EARLY_EN = 1
674 11:07:51.216058 VALID_LAT_VALUE = 1
675 11:07:51.219253 ==============================================================
676 11:07:51.223067 Enter into Gating configuration >>>>
677 11:07:51.225851 Exit from Gating configuration <<<<
678 11:07:51.229133 Enter into DVFS_PRE_config >>>>>
679 11:07:51.242578 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 11:07:51.243321 Exit from DVFS_PRE_config <<<<<
681 11:07:51.245747 Enter into PICG configuration >>>>
682 11:07:51.248968 Exit from PICG configuration <<<<
683 11:07:51.252556 [RX_INPUT] configuration >>>>>
684 11:07:51.254917 [RX_INPUT] configuration <<<<<
685 11:07:51.261760 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 11:07:51.265221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 11:07:51.271612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 11:07:51.278243 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 11:07:51.284696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 11:07:51.291265 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 11:07:51.294771 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 11:07:51.298121 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 11:07:51.301668 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 11:07:51.308284 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 11:07:51.311835 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 11:07:51.315110 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:07:51.318330 ===================================
698 11:07:51.321590 LPDDR4 DRAM CONFIGURATION
699 11:07:51.324905 ===================================
700 11:07:51.328172 EX_ROW_EN[0] = 0x0
701 11:07:51.328583 EX_ROW_EN[1] = 0x0
702 11:07:51.332026 LP4Y_EN = 0x0
703 11:07:51.332412 WORK_FSP = 0x0
704 11:07:51.334885 WL = 0x2
705 11:07:51.335350 RL = 0x2
706 11:07:51.338210 BL = 0x2
707 11:07:51.338626 RPST = 0x0
708 11:07:51.341999 RD_PRE = 0x0
709 11:07:51.342384 WR_PRE = 0x1
710 11:07:51.345358 WR_PST = 0x0
711 11:07:51.345738 DBI_WR = 0x0
712 11:07:51.348505 DBI_RD = 0x0
713 11:07:51.348886 OTF = 0x1
714 11:07:51.352077 ===================================
715 11:07:51.354930 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 11:07:51.361574 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 11:07:51.364902 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 11:07:51.368464 ===================================
719 11:07:51.371877 LPDDR4 DRAM CONFIGURATION
720 11:07:51.374623 ===================================
721 11:07:51.375023 EX_ROW_EN[0] = 0x10
722 11:07:51.378126 EX_ROW_EN[1] = 0x0
723 11:07:51.381263 LP4Y_EN = 0x0
724 11:07:51.381764 WORK_FSP = 0x0
725 11:07:51.385134 WL = 0x2
726 11:07:51.385537 RL = 0x2
727 11:07:51.388360 BL = 0x2
728 11:07:51.388740 RPST = 0x0
729 11:07:51.391560 RD_PRE = 0x0
730 11:07:51.391945 WR_PRE = 0x1
731 11:07:51.394821 WR_PST = 0x0
732 11:07:51.395216 DBI_WR = 0x0
733 11:07:51.398124 DBI_RD = 0x0
734 11:07:51.398628 OTF = 0x1
735 11:07:51.401500 ===================================
736 11:07:51.407628 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 11:07:51.411714 nWR fixed to 40
738 11:07:51.415208 [ModeRegInit_LP4] CH0 RK0
739 11:07:51.415283 [ModeRegInit_LP4] CH0 RK1
740 11:07:51.418675 [ModeRegInit_LP4] CH1 RK0
741 11:07:51.421510 [ModeRegInit_LP4] CH1 RK1
742 11:07:51.421584 match AC timing 13
743 11:07:51.428578 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 11:07:51.432420 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 11:07:51.435163 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 11:07:51.441706 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 11:07:51.444952 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 11:07:51.448349 [EMI DOE] emi_dcm 0
749 11:07:51.451456 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 11:07:51.451587 ==
751 11:07:51.454794 Dram Type= 6, Freq= 0, CH_0, rank 0
752 11:07:51.458266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 11:07:51.458405 ==
754 11:07:51.465198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 11:07:51.471652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 11:07:51.479332 [CA 0] Center 37 (6~68) winsize 63
757 11:07:51.482784 [CA 1] Center 37 (7~68) winsize 62
758 11:07:51.486421 [CA 2] Center 34 (4~65) winsize 62
759 11:07:51.489810 [CA 3] Center 34 (4~65) winsize 62
760 11:07:51.492931 [CA 4] Center 34 (4~64) winsize 61
761 11:07:51.496587 [CA 5] Center 33 (3~64) winsize 62
762 11:07:51.496987
763 11:07:51.499800 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 11:07:51.500183
765 11:07:51.502780 [CATrainingPosCal] consider 1 rank data
766 11:07:51.506784 u2DelayCellTimex100 = 270/100 ps
767 11:07:51.510440 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
768 11:07:51.513941 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
769 11:07:51.517134 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 11:07:51.521227 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 11:07:51.524005 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
772 11:07:51.530977 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 11:07:51.531553
774 11:07:51.534231 CA PerBit enable=1, Macro0, CA PI delay=33
775 11:07:51.534653
776 11:07:51.537400 [CBTSetCACLKResult] CA Dly = 33
777 11:07:51.537832 CS Dly: 6 (0~37)
778 11:07:51.538186 ==
779 11:07:51.540921 Dram Type= 6, Freq= 0, CH_0, rank 1
780 11:07:51.544115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 11:07:51.547354 ==
782 11:07:51.550427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 11:07:51.556756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 11:07:51.565892 [CA 0] Center 37 (6~68) winsize 63
785 11:07:51.569072 [CA 1] Center 37 (7~68) winsize 62
786 11:07:51.572469 [CA 2] Center 34 (4~65) winsize 62
787 11:07:51.576006 [CA 3] Center 34 (4~65) winsize 62
788 11:07:51.578856 [CA 4] Center 33 (3~64) winsize 62
789 11:07:51.582333 [CA 5] Center 33 (3~64) winsize 62
790 11:07:51.582714
791 11:07:51.585910 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 11:07:51.586293
793 11:07:51.589330 [CATrainingPosCal] consider 2 rank data
794 11:07:51.592608 u2DelayCellTimex100 = 270/100 ps
795 11:07:51.595494 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
796 11:07:51.601941 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 11:07:51.605370 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 11:07:51.608766 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 11:07:51.612378 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
800 11:07:51.615605 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 11:07:51.615988
802 11:07:51.618955 CA PerBit enable=1, Macro0, CA PI delay=33
803 11:07:51.619337
804 11:07:51.621987 [CBTSetCACLKResult] CA Dly = 33
805 11:07:51.622371 CS Dly: 6 (0~38)
806 11:07:51.625338
807 11:07:51.628870 ----->DramcWriteLeveling(PI) begin...
808 11:07:51.629258 ==
809 11:07:51.632254 Dram Type= 6, Freq= 0, CH_0, rank 0
810 11:07:51.635276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:07:51.635728 ==
812 11:07:51.638782 Write leveling (Byte 0): 33 => 33
813 11:07:51.642374 Write leveling (Byte 1): 28 => 28
814 11:07:51.645602 DramcWriteLeveling(PI) end<-----
815 11:07:51.646001
816 11:07:51.646296 ==
817 11:07:51.649128 Dram Type= 6, Freq= 0, CH_0, rank 0
818 11:07:51.653174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 11:07:51.653636 ==
820 11:07:51.655342 [Gating] SW mode calibration
821 11:07:51.662232 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 11:07:51.668785 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 11:07:51.671886 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 11:07:51.675650 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 11:07:51.681933 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 11:07:51.685151 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:07:51.688556 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:07:51.695267 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:07:51.698235 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:07:51.701524 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:07:51.708443 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:07:51.711508 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:07:51.715020 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:07:51.721742 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 11:07:51.724782 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:07:51.728242 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:07:51.735051 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:07:51.737818 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:07:51.741237 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:07:51.747880 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
841 11:07:51.751499 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
842 11:07:51.754897 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:07:51.757796 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:07:51.764851 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:07:51.768092 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:07:51.771566 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:07:51.777945 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:07:51.781227 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:07:51.784454 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
850 11:07:51.790830 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
851 11:07:51.794567 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 11:07:51.797519 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 11:07:51.804421 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 11:07:51.807565 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 11:07:51.810995 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 11:07:51.817972 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
857 11:07:51.820746 0 10 8 | B1->B0 | 3131 2a2a | 0 0 | (1 0) (0 0)
858 11:07:51.824144 0 10 12 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
859 11:07:51.831017 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:07:51.834257 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:07:51.837970 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:07:51.844442 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:07:51.847251 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:07:51.850676 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
865 11:07:51.857501 0 11 8 | B1->B0 | 2b2b 3a3a | 1 0 | (0 0) (0 0)
866 11:07:51.860522 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
867 11:07:51.864024 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:07:51.870449 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:07:51.874031 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:07:51.877531 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 11:07:51.883702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:07:51.887038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 11:07:51.890508 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 11:07:51.897359 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 11:07:51.901085 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:07:51.903997 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:07:51.910344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:07:51.913649 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:07:51.917602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:07:51.923948 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:07:51.927052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:07:51.930135 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:07:51.933399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:07:51.939790 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:07:51.942992 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 11:07:51.946354 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 11:07:51.953413 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 11:07:51.956345 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 11:07:51.959629 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 11:07:51.963242 Total UI for P1: 0, mck2ui 16
891 11:07:51.966700 best dqsien dly found for B0: ( 0, 14, 6)
892 11:07:51.973057 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 11:07:51.976494 Total UI for P1: 0, mck2ui 16
894 11:07:51.979443 best dqsien dly found for B1: ( 0, 14, 8)
895 11:07:51.982763 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
896 11:07:51.986247 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 11:07:51.986322
898 11:07:51.989456 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
899 11:07:51.992759 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 11:07:51.996451 [Gating] SW calibration Done
901 11:07:51.996526 ==
902 11:07:51.999608 Dram Type= 6, Freq= 0, CH_0, rank 0
903 11:07:52.002828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 11:07:52.002904 ==
905 11:07:52.006188 RX Vref Scan: 0
906 11:07:52.006267
907 11:07:52.006329 RX Vref 0 -> 0, step: 1
908 11:07:52.009435
909 11:07:52.009514 RX Delay -130 -> 252, step: 16
910 11:07:52.016095 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 11:07:52.019392 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 11:07:52.023137 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
913 11:07:52.026332 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 11:07:52.029661 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 11:07:52.036105 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 11:07:52.040272 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
917 11:07:52.043277 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
918 11:07:52.046330 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
919 11:07:52.049715 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
920 11:07:52.056197 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 11:07:52.059763 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 11:07:52.062827 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
923 11:07:52.066361 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
924 11:07:52.069933 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 11:07:52.076411 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
926 11:07:52.076798 ==
927 11:07:52.079577 Dram Type= 6, Freq= 0, CH_0, rank 0
928 11:07:52.082905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 11:07:52.083292 ==
930 11:07:52.083693 DQS Delay:
931 11:07:52.086466 DQS0 = 0, DQS1 = 0
932 11:07:52.086846 DQM Delay:
933 11:07:52.089325 DQM0 = 84, DQM1 = 71
934 11:07:52.089709 DQ Delay:
935 11:07:52.092639 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
936 11:07:52.095947 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
937 11:07:52.099338 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
938 11:07:52.102826 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
939 11:07:52.103208
940 11:07:52.103532
941 11:07:52.103811 ==
942 11:07:52.105975 Dram Type= 6, Freq= 0, CH_0, rank 0
943 11:07:52.109066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 11:07:52.109568 ==
945 11:07:52.109971
946 11:07:52.112831
947 11:07:52.113212 TX Vref Scan disable
948 11:07:52.115899 == TX Byte 0 ==
949 11:07:52.119704 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
950 11:07:52.122322 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
951 11:07:52.126029 == TX Byte 1 ==
952 11:07:52.129155 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
953 11:07:52.132479 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
954 11:07:52.135736 ==
955 11:07:52.136117 Dram Type= 6, Freq= 0, CH_0, rank 0
956 11:07:52.142294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 11:07:52.142809 ==
958 11:07:52.155119 TX Vref=22, minBit 5, minWin=27, winSum=439
959 11:07:52.158237 TX Vref=24, minBit 6, minWin=27, winSum=444
960 11:07:52.161808 TX Vref=26, minBit 8, minWin=27, winSum=445
961 11:07:52.165156 TX Vref=28, minBit 1, minWin=28, winSum=451
962 11:07:52.168255 TX Vref=30, minBit 10, minWin=27, winSum=451
963 11:07:52.174956 TX Vref=32, minBit 11, minWin=26, winSum=445
964 11:07:52.178257 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 28
965 11:07:52.178642
966 11:07:52.181324 Final TX Range 1 Vref 28
967 11:07:52.181710
968 11:07:52.182004 ==
969 11:07:52.184770 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:07:52.188305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:07:52.191419 ==
972 11:07:52.191932
973 11:07:52.192237
974 11:07:52.192511 TX Vref Scan disable
975 11:07:52.195127 == TX Byte 0 ==
976 11:07:52.198671 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 11:07:52.205304 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 11:07:52.205772 == TX Byte 1 ==
979 11:07:52.208664 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
980 11:07:52.214773 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
981 11:07:52.215154
982 11:07:52.215495 [DATLAT]
983 11:07:52.215811 Freq=800, CH0 RK0
984 11:07:52.216130
985 11:07:52.217873 DATLAT Default: 0xa
986 11:07:52.221565 0, 0xFFFF, sum = 0
987 11:07:52.221956 1, 0xFFFF, sum = 0
988 11:07:52.225354 2, 0xFFFF, sum = 0
989 11:07:52.225820 3, 0xFFFF, sum = 0
990 11:07:52.228278 4, 0xFFFF, sum = 0
991 11:07:52.228685 5, 0xFFFF, sum = 0
992 11:07:52.231518 6, 0xFFFF, sum = 0
993 11:07:52.231910 7, 0xFFFF, sum = 0
994 11:07:52.234664 8, 0xFFFF, sum = 0
995 11:07:52.235053 9, 0x0, sum = 1
996 11:07:52.238289 10, 0x0, sum = 2
997 11:07:52.238777 11, 0x0, sum = 3
998 11:07:52.239086 12, 0x0, sum = 4
999 11:07:52.241275 best_step = 10
1000 11:07:52.241656
1001 11:07:52.241952 ==
1002 11:07:52.245138 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 11:07:52.247887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 11:07:52.248275 ==
1005 11:07:52.251224 RX Vref Scan: 1
1006 11:07:52.251704
1007 11:07:52.254883 Set Vref Range= 32 -> 127
1008 11:07:52.255344
1009 11:07:52.255736 RX Vref 32 -> 127, step: 1
1010 11:07:52.256025
1011 11:07:52.257799 RX Delay -111 -> 252, step: 8
1012 11:07:52.258199
1013 11:07:52.261353 Set Vref, RX VrefLevel [Byte0]: 32
1014 11:07:52.264753 [Byte1]: 32
1015 11:07:52.268197
1016 11:07:52.268581 Set Vref, RX VrefLevel [Byte0]: 33
1017 11:07:52.271384 [Byte1]: 33
1018 11:07:52.275935
1019 11:07:52.276336 Set Vref, RX VrefLevel [Byte0]: 34
1020 11:07:52.278764 [Byte1]: 34
1021 11:07:52.283492
1022 11:07:52.283932 Set Vref, RX VrefLevel [Byte0]: 35
1023 11:07:52.286266 [Byte1]: 35
1024 11:07:52.290656
1025 11:07:52.291158 Set Vref, RX VrefLevel [Byte0]: 36
1026 11:07:52.294256 [Byte1]: 36
1027 11:07:52.298617
1028 11:07:52.299135 Set Vref, RX VrefLevel [Byte0]: 37
1029 11:07:52.301637 [Byte1]: 37
1030 11:07:52.306208
1031 11:07:52.306591 Set Vref, RX VrefLevel [Byte0]: 38
1032 11:07:52.309813 [Byte1]: 38
1033 11:07:52.314134
1034 11:07:52.314585 Set Vref, RX VrefLevel [Byte0]: 39
1035 11:07:52.316774 [Byte1]: 39
1036 11:07:52.321301
1037 11:07:52.321683 Set Vref, RX VrefLevel [Byte0]: 40
1038 11:07:52.324449 [Byte1]: 40
1039 11:07:52.328951
1040 11:07:52.329336 Set Vref, RX VrefLevel [Byte0]: 41
1041 11:07:52.332407 [Byte1]: 41
1042 11:07:52.336462
1043 11:07:52.336694 Set Vref, RX VrefLevel [Byte0]: 42
1044 11:07:52.339974 [Byte1]: 42
1045 11:07:52.344233
1046 11:07:52.344398 Set Vref, RX VrefLevel [Byte0]: 43
1047 11:07:52.347620 [Byte1]: 43
1048 11:07:52.351747
1049 11:07:52.351865 Set Vref, RX VrefLevel [Byte0]: 44
1050 11:07:52.354798 [Byte1]: 44
1051 11:07:52.359128
1052 11:07:52.359248 Set Vref, RX VrefLevel [Byte0]: 45
1053 11:07:52.362566 [Byte1]: 45
1054 11:07:52.367130
1055 11:07:52.367244 Set Vref, RX VrefLevel [Byte0]: 46
1056 11:07:52.370265 [Byte1]: 46
1057 11:07:52.374540
1058 11:07:52.374650 Set Vref, RX VrefLevel [Byte0]: 47
1059 11:07:52.378038 [Byte1]: 47
1060 11:07:52.382391
1061 11:07:52.382484 Set Vref, RX VrefLevel [Byte0]: 48
1062 11:07:52.385392 [Byte1]: 48
1063 11:07:52.389794
1064 11:07:52.389899 Set Vref, RX VrefLevel [Byte0]: 49
1065 11:07:52.392846 [Byte1]: 49
1066 11:07:52.397541
1067 11:07:52.397620 Set Vref, RX VrefLevel [Byte0]: 50
1068 11:07:52.400749 [Byte1]: 50
1069 11:07:52.404841
1070 11:07:52.404941 Set Vref, RX VrefLevel [Byte0]: 51
1071 11:07:52.408692 [Byte1]: 51
1072 11:07:52.412950
1073 11:07:52.413044 Set Vref, RX VrefLevel [Byte0]: 52
1074 11:07:52.419312 [Byte1]: 52
1075 11:07:52.419416
1076 11:07:52.422329 Set Vref, RX VrefLevel [Byte0]: 53
1077 11:07:52.426056 [Byte1]: 53
1078 11:07:52.426349
1079 11:07:52.429496 Set Vref, RX VrefLevel [Byte0]: 54
1080 11:07:52.432821 [Byte1]: 54
1081 11:07:52.435840
1082 11:07:52.436012 Set Vref, RX VrefLevel [Byte0]: 55
1083 11:07:52.439219 [Byte1]: 55
1084 11:07:52.443523
1085 11:07:52.443908 Set Vref, RX VrefLevel [Byte0]: 56
1086 11:07:52.446858 [Byte1]: 56
1087 11:07:52.451306
1088 11:07:52.451725 Set Vref, RX VrefLevel [Byte0]: 57
1089 11:07:52.454384 [Byte1]: 57
1090 11:07:52.458980
1091 11:07:52.459377 Set Vref, RX VrefLevel [Byte0]: 58
1092 11:07:52.462276 [Byte1]: 58
1093 11:07:52.466371
1094 11:07:52.466862 Set Vref, RX VrefLevel [Byte0]: 59
1095 11:07:52.470114 [Byte1]: 59
1096 11:07:52.474167
1097 11:07:52.474550 Set Vref, RX VrefLevel [Byte0]: 60
1098 11:07:52.477776 [Byte1]: 60
1099 11:07:52.482200
1100 11:07:52.482665 Set Vref, RX VrefLevel [Byte0]: 61
1101 11:07:52.484994 [Byte1]: 61
1102 11:07:52.489658
1103 11:07:52.490227 Set Vref, RX VrefLevel [Byte0]: 62
1104 11:07:52.492609 [Byte1]: 62
1105 11:07:52.497237
1106 11:07:52.497614 Set Vref, RX VrefLevel [Byte0]: 63
1107 11:07:52.500567 [Byte1]: 63
1108 11:07:52.505028
1109 11:07:52.505415 Set Vref, RX VrefLevel [Byte0]: 64
1110 11:07:52.508116 [Byte1]: 64
1111 11:07:52.512418
1112 11:07:52.512799 Set Vref, RX VrefLevel [Byte0]: 65
1113 11:07:52.515575 [Byte1]: 65
1114 11:07:52.519970
1115 11:07:52.520355 Set Vref, RX VrefLevel [Byte0]: 66
1116 11:07:52.523126 [Byte1]: 66
1117 11:07:52.527563
1118 11:07:52.527939 Set Vref, RX VrefLevel [Byte0]: 67
1119 11:07:52.530866 [Byte1]: 67
1120 11:07:52.535711
1121 11:07:52.536088 Set Vref, RX VrefLevel [Byte0]: 68
1122 11:07:52.538404 [Byte1]: 68
1123 11:07:52.543312
1124 11:07:52.543962 Set Vref, RX VrefLevel [Byte0]: 69
1125 11:07:52.546257 [Byte1]: 69
1126 11:07:52.550549
1127 11:07:52.550957 Set Vref, RX VrefLevel [Byte0]: 70
1128 11:07:52.554101 [Byte1]: 70
1129 11:07:52.558537
1130 11:07:52.558918 Set Vref, RX VrefLevel [Byte0]: 71
1131 11:07:52.561750 [Byte1]: 71
1132 11:07:52.565991
1133 11:07:52.566194 Set Vref, RX VrefLevel [Byte0]: 72
1134 11:07:52.568846 [Byte1]: 72
1135 11:07:52.573224
1136 11:07:52.573389 Set Vref, RX VrefLevel [Byte0]: 73
1137 11:07:52.576712 [Byte1]: 73
1138 11:07:52.581040
1139 11:07:52.581163 Set Vref, RX VrefLevel [Byte0]: 74
1140 11:07:52.584398 [Byte1]: 74
1141 11:07:52.588437
1142 11:07:52.588546 Set Vref, RX VrefLevel [Byte0]: 75
1143 11:07:52.591801 [Byte1]: 75
1144 11:07:52.596288
1145 11:07:52.596381 Set Vref, RX VrefLevel [Byte0]: 76
1146 11:07:52.599807 [Byte1]: 76
1147 11:07:52.603923
1148 11:07:52.604003 Set Vref, RX VrefLevel [Byte0]: 77
1149 11:07:52.607224 [Byte1]: 77
1150 11:07:52.611785
1151 11:07:52.611859 Set Vref, RX VrefLevel [Byte0]: 78
1152 11:07:52.614846 [Byte1]: 78
1153 11:07:52.618962
1154 11:07:52.619038 Set Vref, RX VrefLevel [Byte0]: 79
1155 11:07:52.622536 [Byte1]: 79
1156 11:07:52.626807
1157 11:07:52.626884 Set Vref, RX VrefLevel [Byte0]: 80
1158 11:07:52.630040 [Byte1]: 80
1159 11:07:52.634617
1160 11:07:52.634716 Set Vref, RX VrefLevel [Byte0]: 81
1161 11:07:52.637542 [Byte1]: 81
1162 11:07:52.642413
1163 11:07:52.642489 Set Vref, RX VrefLevel [Byte0]: 82
1164 11:07:52.645230 [Byte1]: 82
1165 11:07:52.649671
1166 11:07:52.649749 Final RX Vref Byte 0 = 64 to rank0
1167 11:07:52.653109 Final RX Vref Byte 1 = 51 to rank0
1168 11:07:52.656749 Final RX Vref Byte 0 = 64 to rank1
1169 11:07:52.659756 Final RX Vref Byte 1 = 51 to rank1==
1170 11:07:52.663167 Dram Type= 6, Freq= 0, CH_0, rank 0
1171 11:07:52.670074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 11:07:52.670237 ==
1173 11:07:52.670323 DQS Delay:
1174 11:07:52.670421 DQS0 = 0, DQS1 = 0
1175 11:07:52.672978 DQM Delay:
1176 11:07:52.673136 DQM0 = 87, DQM1 = 76
1177 11:07:52.676500 DQ Delay:
1178 11:07:52.679625 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1179 11:07:52.683205 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1180 11:07:52.686790 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1181 11:07:52.689862 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1182 11:07:52.690022
1183 11:07:52.690145
1184 11:07:52.696419 [DQSOSCAuto] RK0, (LSB)MR18= 0x4526, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1185 11:07:52.700203 CH0 RK0: MR19=606, MR18=4526
1186 11:07:52.706839 CH0_RK0: MR19=0x606, MR18=0x4526, DQSOSC=392, MR23=63, INC=96, DEC=64
1187 11:07:52.707280
1188 11:07:52.710295 ----->DramcWriteLeveling(PI) begin...
1189 11:07:52.710810 ==
1190 11:07:52.713649 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 11:07:52.757234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 11:07:52.757733 ==
1193 11:07:52.758061 Write leveling (Byte 0): 31 => 31
1194 11:07:52.758370 Write leveling (Byte 1): 31 => 31
1195 11:07:52.758660 DramcWriteLeveling(PI) end<-----
1196 11:07:52.758946
1197 11:07:52.759223 ==
1198 11:07:52.759540 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 11:07:52.760263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 11:07:52.760688 ==
1201 11:07:52.761020 [Gating] SW mode calibration
1202 11:07:52.761334 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1203 11:07:52.761699 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1204 11:07:52.762029 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1205 11:07:52.762325 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 11:07:52.762672 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1207 11:07:52.765628 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:07:52.772134 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:07:52.775028 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:07:52.779079 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:07:52.785111 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:07:52.788540 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:07:52.791826 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 11:07:52.798502 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:07:52.801881 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:07:52.805253 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:07:52.811676 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:07:52.814920 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:07:52.817935 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:07:52.825213 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:07:52.828398 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1222 11:07:52.831576 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1223 11:07:52.838059 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:07:52.841549 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:07:52.844710 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:07:52.851638 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:07:52.854667 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:07:52.858232 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:07:52.864582 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:07:52.867965 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (1 1) (1 1)
1231 11:07:52.871600 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (1 0) (1 1)
1232 11:07:52.877650 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 11:07:52.881527 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 11:07:52.884308 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 11:07:52.891186 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 11:07:52.894383 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 11:07:52.897683 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1238 11:07:52.904175 0 10 8 | B1->B0 | 3030 2c2c | 0 1 | (0 0) (1 1)
1239 11:07:52.907335 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:07:52.911161 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:07:52.917902 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:07:52.921119 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:07:52.924052 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:07:52.930649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:07:52.934056 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1246 11:07:52.937455 0 11 8 | B1->B0 | 302f 3c3c | 1 0 | (0 0) (0 0)
1247 11:07:52.940779 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1248 11:07:52.947482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 11:07:52.951081 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 11:07:52.954102 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 11:07:52.960648 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 11:07:52.963904 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 11:07:52.967539 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 11:07:52.974009 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1255 11:07:52.977729 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 11:07:52.980562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 11:07:52.987297 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 11:07:52.990927 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 11:07:52.993855 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 11:07:53.000779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 11:07:53.004041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 11:07:53.007406 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 11:07:53.013909 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:07:53.017040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:07:53.020598 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:07:53.027387 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:07:53.030644 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:07:53.033996 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:07:53.040737 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1270 11:07:53.043703 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 11:07:53.047305 Total UI for P1: 0, mck2ui 16
1272 11:07:53.051001 best dqsien dly found for B0: ( 0, 14, 4)
1273 11:07:53.054177 Total UI for P1: 0, mck2ui 16
1274 11:07:53.056937 best dqsien dly found for B1: ( 0, 14, 6)
1275 11:07:53.060584 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1276 11:07:53.064058 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1277 11:07:53.064688
1278 11:07:53.067357 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1279 11:07:53.070368 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1280 11:07:53.074055 [Gating] SW calibration Done
1281 11:07:53.074501 ==
1282 11:07:53.077413 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 11:07:53.080345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 11:07:53.080733 ==
1285 11:07:53.083634 RX Vref Scan: 0
1286 11:07:53.084020
1287 11:07:53.084319 RX Vref 0 -> 0, step: 1
1288 11:07:53.086914
1289 11:07:53.087297 RX Delay -130 -> 252, step: 16
1290 11:07:53.093769 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1291 11:07:53.097109 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1292 11:07:53.100454 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1293 11:07:53.103933 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1294 11:07:53.107095 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1295 11:07:53.114023 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1296 11:07:53.117190 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1297 11:07:53.120304 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1298 11:07:53.123516 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1299 11:07:53.126975 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1300 11:07:53.133258 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1301 11:07:53.136781 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1302 11:07:53.140028 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1303 11:07:53.143532 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1304 11:07:53.149966 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1305 11:07:53.153081 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1306 11:07:53.153157 ==
1307 11:07:53.156205 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 11:07:53.159395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 11:07:53.159533 ==
1310 11:07:53.159599 DQS Delay:
1311 11:07:53.162898 DQS0 = 0, DQS1 = 0
1312 11:07:53.162990 DQM Delay:
1313 11:07:53.166042 DQM0 = 84, DQM1 = 76
1314 11:07:53.166166 DQ Delay:
1315 11:07:53.169398 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1316 11:07:53.172506 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1317 11:07:53.176091 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1318 11:07:53.179518 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1319 11:07:53.179582
1320 11:07:53.179636
1321 11:07:53.179686 ==
1322 11:07:53.182668 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 11:07:53.186381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 11:07:53.189307 ==
1325 11:07:53.189387
1326 11:07:53.189448
1327 11:07:53.189503 TX Vref Scan disable
1328 11:07:53.192755 == TX Byte 0 ==
1329 11:07:53.196295 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1330 11:07:53.199243 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1331 11:07:53.202711 == TX Byte 1 ==
1332 11:07:53.205685 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1333 11:07:53.212303 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1334 11:07:53.212426 ==
1335 11:07:53.215870 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 11:07:53.218908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 11:07:53.219048 ==
1338 11:07:53.231310 TX Vref=22, minBit 8, minWin=26, winSum=444
1339 11:07:53.234450 TX Vref=24, minBit 3, minWin=27, winSum=449
1340 11:07:53.238243 TX Vref=26, minBit 9, minWin=27, winSum=446
1341 11:07:53.241193 TX Vref=28, minBit 9, minWin=27, winSum=446
1342 11:07:53.244597 TX Vref=30, minBit 8, minWin=27, winSum=443
1343 11:07:53.251225 TX Vref=32, minBit 9, minWin=27, winSum=447
1344 11:07:53.254522 [TxChooseVref] Worse bit 3, Min win 27, Win sum 449, Final Vref 24
1345 11:07:53.254621
1346 11:07:53.257883 Final TX Range 1 Vref 24
1347 11:07:53.257959
1348 11:07:53.258016 ==
1349 11:07:53.261017 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 11:07:53.264595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 11:07:53.264670 ==
1352 11:07:53.267637
1353 11:07:53.267712
1354 11:07:53.267770 TX Vref Scan disable
1355 11:07:53.271514 == TX Byte 0 ==
1356 11:07:53.274956 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1357 11:07:53.281299 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1358 11:07:53.281374 == TX Byte 1 ==
1359 11:07:53.284660 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1360 11:07:53.291111 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1361 11:07:53.291180
1362 11:07:53.291236 [DATLAT]
1363 11:07:53.291290 Freq=800, CH0 RK1
1364 11:07:53.291342
1365 11:07:53.294503 DATLAT Default: 0xa
1366 11:07:53.294564 0, 0xFFFF, sum = 0
1367 11:07:53.297914 1, 0xFFFF, sum = 0
1368 11:07:53.297982 2, 0xFFFF, sum = 0
1369 11:07:53.300855 3, 0xFFFF, sum = 0
1370 11:07:53.304389 4, 0xFFFF, sum = 0
1371 11:07:53.304456 5, 0xFFFF, sum = 0
1372 11:07:53.308082 6, 0xFFFF, sum = 0
1373 11:07:53.308146 7, 0xFFFF, sum = 0
1374 11:07:53.311095 8, 0xFFFF, sum = 0
1375 11:07:53.311162 9, 0x0, sum = 1
1376 11:07:53.311219 10, 0x0, sum = 2
1377 11:07:53.314311 11, 0x0, sum = 3
1378 11:07:53.314382 12, 0x0, sum = 4
1379 11:07:53.317585 best_step = 10
1380 11:07:53.317652
1381 11:07:53.317708 ==
1382 11:07:53.321005 Dram Type= 6, Freq= 0, CH_0, rank 1
1383 11:07:53.324509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 11:07:53.324610 ==
1385 11:07:53.327735 RX Vref Scan: 0
1386 11:07:53.327826
1387 11:07:53.327908 RX Vref 0 -> 0, step: 1
1388 11:07:53.330505
1389 11:07:53.330604 RX Delay -111 -> 252, step: 8
1390 11:07:53.337947 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1391 11:07:53.341246 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1392 11:07:53.344485 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1393 11:07:53.347960 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1394 11:07:53.351150 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1395 11:07:53.357655 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1396 11:07:53.361086 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1397 11:07:53.364318 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1398 11:07:53.367860 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1399 11:07:53.374401 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1400 11:07:53.377524 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1401 11:07:53.381168 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1402 11:07:53.384329 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1403 11:07:53.387226 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1404 11:07:53.394160 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1405 11:07:53.397773 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1406 11:07:53.397850 ==
1407 11:07:53.400605 Dram Type= 6, Freq= 0, CH_0, rank 1
1408 11:07:53.403879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 11:07:53.403944 ==
1410 11:07:53.407234 DQS Delay:
1411 11:07:53.407293 DQS0 = 0, DQS1 = 0
1412 11:07:53.407344 DQM Delay:
1413 11:07:53.410503 DQM0 = 86, DQM1 = 76
1414 11:07:53.410587 DQ Delay:
1415 11:07:53.413745 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1416 11:07:53.417406 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1417 11:07:53.420600 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1418 11:07:53.423907 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1419 11:07:53.423981
1420 11:07:53.424037
1421 11:07:53.434045 [DQSOSCAuto] RK1, (LSB)MR18= 0x4209, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1422 11:07:53.434120 CH0 RK1: MR19=606, MR18=4209
1423 11:07:53.440653 CH0_RK1: MR19=0x606, MR18=0x4209, DQSOSC=393, MR23=63, INC=95, DEC=63
1424 11:07:53.443867 [RxdqsGatingPostProcess] freq 800
1425 11:07:53.450561 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1426 11:07:53.453790 Pre-setting of DQS Precalculation
1427 11:07:53.456834 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1428 11:07:53.456924 ==
1429 11:07:53.460267 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 11:07:53.466702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 11:07:53.466817 ==
1432 11:07:53.470720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1433 11:07:53.476827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1434 11:07:53.486394 [CA 0] Center 36 (6~67) winsize 62
1435 11:07:53.489398 [CA 1] Center 36 (6~67) winsize 62
1436 11:07:53.493289 [CA 2] Center 34 (4~65) winsize 62
1437 11:07:53.496120 [CA 3] Center 34 (3~65) winsize 63
1438 11:07:53.499341 [CA 4] Center 34 (4~65) winsize 62
1439 11:07:53.503313 [CA 5] Center 34 (3~65) winsize 63
1440 11:07:53.503402
1441 11:07:53.506119 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1442 11:07:53.506212
1443 11:07:53.509693 [CATrainingPosCal] consider 1 rank data
1444 11:07:53.513166 u2DelayCellTimex100 = 270/100 ps
1445 11:07:53.516018 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1446 11:07:53.522363 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1447 11:07:53.525656 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 11:07:53.529285 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1449 11:07:53.532296 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1450 11:07:53.535996 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1451 11:07:53.536089
1452 11:07:53.539306 CA PerBit enable=1, Macro0, CA PI delay=34
1453 11:07:53.539396
1454 11:07:53.542657 [CBTSetCACLKResult] CA Dly = 34
1455 11:07:53.545803 CS Dly: 5 (0~36)
1456 11:07:53.545904 ==
1457 11:07:53.549267 Dram Type= 6, Freq= 0, CH_1, rank 1
1458 11:07:53.552472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 11:07:53.552571 ==
1460 11:07:53.559342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1461 11:07:53.562495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1462 11:07:53.572361 [CA 0] Center 36 (6~67) winsize 62
1463 11:07:53.575786 [CA 1] Center 36 (6~67) winsize 62
1464 11:07:53.579283 [CA 2] Center 34 (4~65) winsize 62
1465 11:07:53.582240 [CA 3] Center 34 (3~65) winsize 63
1466 11:07:53.585784 [CA 4] Center 34 (4~65) winsize 62
1467 11:07:53.588952 [CA 5] Center 34 (3~65) winsize 63
1468 11:07:53.589021
1469 11:07:53.592636 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1470 11:07:53.592706
1471 11:07:53.595833 [CATrainingPosCal] consider 2 rank data
1472 11:07:53.599309 u2DelayCellTimex100 = 270/100 ps
1473 11:07:53.602217 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 11:07:53.608839 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1475 11:07:53.612196 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 11:07:53.615537 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 11:07:53.618864 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 11:07:53.622431 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1479 11:07:53.622496
1480 11:07:53.625435 CA PerBit enable=1, Macro0, CA PI delay=34
1481 11:07:53.625499
1482 11:07:53.629428 [CBTSetCACLKResult] CA Dly = 34
1483 11:07:53.629492 CS Dly: 6 (0~38)
1484 11:07:53.632084
1485 11:07:53.635338 ----->DramcWriteLeveling(PI) begin...
1486 11:07:53.635435 ==
1487 11:07:53.638963 Dram Type= 6, Freq= 0, CH_1, rank 0
1488 11:07:53.642491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1489 11:07:53.642586 ==
1490 11:07:53.645572 Write leveling (Byte 0): 26 => 26
1491 11:07:53.648645 Write leveling (Byte 1): 26 => 26
1492 11:07:53.652022 DramcWriteLeveling(PI) end<-----
1493 11:07:53.652109
1494 11:07:53.652168 ==
1495 11:07:53.655696 Dram Type= 6, Freq= 0, CH_1, rank 0
1496 11:07:53.658410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1497 11:07:53.658475 ==
1498 11:07:53.662042 [Gating] SW mode calibration
1499 11:07:53.668765 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1500 11:07:53.675466 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1501 11:07:53.679045 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1502 11:07:53.682299 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1503 11:07:53.688726 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:07:53.691698 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:07:53.695624 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:07:53.701615 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 11:07:53.705224 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:07:53.708544 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:07:53.715266 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:07:53.718247 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 11:07:53.721830 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:07:53.728339 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:07:53.731396 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:07:53.734827 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:07:53.738224 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:07:53.744856 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:07:53.747992 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1518 11:07:53.751271 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1519 11:07:53.757905 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:07:53.761385 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:07:53.764453 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:07:53.771385 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:07:53.774522 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:07:53.777901 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:07:53.784813 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:07:53.788133 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1527 11:07:53.790990 0 9 8 | B1->B0 | 2c2c 2f2f | 1 0 | (1 1) (0 0)
1528 11:07:53.797664 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 11:07:53.800895 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 11:07:53.804502 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 11:07:53.811241 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 11:07:53.814286 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 11:07:53.817516 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1534 11:07:53.824276 0 10 4 | B1->B0 | 3333 3131 | 0 0 | (0 1) (1 1)
1535 11:07:53.827841 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1536 11:07:53.830775 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:07:53.837231 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:07:53.840562 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:07:53.844218 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:07:53.850684 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:07:53.853926 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:07:53.857317 0 11 4 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
1543 11:07:53.863850 0 11 8 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
1544 11:07:53.867316 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 11:07:53.870286 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 11:07:53.877530 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 11:07:53.880641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 11:07:53.883931 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 11:07:53.890505 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 11:07:53.893496 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1551 11:07:53.897252 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1552 11:07:53.903680 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 11:07:53.907079 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 11:07:53.910474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 11:07:53.917054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 11:07:53.919909 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 11:07:53.923338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 11:07:53.929875 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 11:07:53.933470 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 11:07:53.936653 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:07:53.943709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:07:53.947008 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:07:53.949928 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:07:53.957018 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:07:53.959814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:07:53.963612 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1567 11:07:53.969975 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 11:07:53.970164 Total UI for P1: 0, mck2ui 16
1569 11:07:53.976830 best dqsien dly found for B0: ( 0, 14, 4)
1570 11:07:53.977053 Total UI for P1: 0, mck2ui 16
1571 11:07:53.980152 best dqsien dly found for B1: ( 0, 14, 6)
1572 11:07:53.986629 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1573 11:07:53.989907 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1574 11:07:53.990189
1575 11:07:53.993300 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1576 11:07:53.996492 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1577 11:07:53.999942 [Gating] SW calibration Done
1578 11:07:54.000289 ==
1579 11:07:54.003202 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 11:07:54.007227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 11:07:54.007789 ==
1582 11:07:54.010337 RX Vref Scan: 0
1583 11:07:54.010873
1584 11:07:54.011361 RX Vref 0 -> 0, step: 1
1585 11:07:54.011749
1586 11:07:54.013425 RX Delay -130 -> 252, step: 16
1587 11:07:54.016925 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1588 11:07:54.023151 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1589 11:07:54.026698 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1590 11:07:54.029965 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1591 11:07:54.033503 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1592 11:07:54.037161 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1593 11:07:54.043667 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1594 11:07:54.046934 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1595 11:07:54.050547 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1596 11:07:54.053504 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1597 11:07:54.056527 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1598 11:07:54.063196 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1599 11:07:54.066410 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1600 11:07:54.070161 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1601 11:07:54.073165 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1602 11:07:54.076278 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1603 11:07:54.079828 ==
1604 11:07:54.080250 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 11:07:54.086416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 11:07:54.086802 ==
1607 11:07:54.087097 DQS Delay:
1608 11:07:54.089683 DQS0 = 0, DQS1 = 0
1609 11:07:54.090108 DQM Delay:
1610 11:07:54.092804 DQM0 = 88, DQM1 = 78
1611 11:07:54.093187 DQ Delay:
1612 11:07:54.096254 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1613 11:07:54.099744 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1614 11:07:54.102958 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1615 11:07:54.106448 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1616 11:07:54.106832
1617 11:07:54.107126
1618 11:07:54.107399 ==
1619 11:07:54.109495 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 11:07:54.113047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 11:07:54.113434 ==
1622 11:07:54.113785
1623 11:07:54.114221
1624 11:07:54.115940 TX Vref Scan disable
1625 11:07:54.119075 == TX Byte 0 ==
1626 11:07:54.122486 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1627 11:07:54.126072 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1628 11:07:54.129231 == TX Byte 1 ==
1629 11:07:54.132877 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1630 11:07:54.135792 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1631 11:07:54.136190 ==
1632 11:07:54.139018 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 11:07:54.145945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 11:07:54.146398 ==
1635 11:07:54.157619 TX Vref=22, minBit 8, minWin=27, winSum=444
1636 11:07:54.160911 TX Vref=24, minBit 9, minWin=27, winSum=445
1637 11:07:54.164419 TX Vref=26, minBit 1, minWin=28, winSum=452
1638 11:07:54.167646 TX Vref=28, minBit 10, minWin=27, winSum=448
1639 11:07:54.170608 TX Vref=30, minBit 8, minWin=27, winSum=447
1640 11:07:54.177350 TX Vref=32, minBit 8, minWin=27, winSum=447
1641 11:07:54.180991 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 26
1642 11:07:54.181375
1643 11:07:54.184296 Final TX Range 1 Vref 26
1644 11:07:54.184681
1645 11:07:54.184974 ==
1646 11:07:54.187798 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 11:07:54.190993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 11:07:54.191376 ==
1649 11:07:54.193857
1650 11:07:54.194236
1651 11:07:54.194527 TX Vref Scan disable
1652 11:07:54.197211 == TX Byte 0 ==
1653 11:07:54.200704 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1654 11:07:54.207507 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1655 11:07:54.207890 == TX Byte 1 ==
1656 11:07:54.211080 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1657 11:07:54.217583 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1658 11:07:54.218048
1659 11:07:54.218343 [DATLAT]
1660 11:07:54.218612 Freq=800, CH1 RK0
1661 11:07:54.218873
1662 11:07:54.220738 DATLAT Default: 0xa
1663 11:07:54.221118 0, 0xFFFF, sum = 0
1664 11:07:54.224183 1, 0xFFFF, sum = 0
1665 11:07:54.224570 2, 0xFFFF, sum = 0
1666 11:07:54.227047 3, 0xFFFF, sum = 0
1667 11:07:54.230768 4, 0xFFFF, sum = 0
1668 11:07:54.231315 5, 0xFFFF, sum = 0
1669 11:07:54.233873 6, 0xFFFF, sum = 0
1670 11:07:54.234260 7, 0xFFFF, sum = 0
1671 11:07:54.237401 8, 0xFFFF, sum = 0
1672 11:07:54.237785 9, 0x0, sum = 1
1673 11:07:54.238087 10, 0x0, sum = 2
1674 11:07:54.240390 11, 0x0, sum = 3
1675 11:07:54.240802 12, 0x0, sum = 4
1676 11:07:54.243559 best_step = 10
1677 11:07:54.243956
1678 11:07:54.244257 ==
1679 11:07:54.247496 Dram Type= 6, Freq= 0, CH_1, rank 0
1680 11:07:54.250592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1681 11:07:54.250993 ==
1682 11:07:54.253913 RX Vref Scan: 1
1683 11:07:54.254349
1684 11:07:54.254833 Set Vref Range= 32 -> 127
1685 11:07:54.257069
1686 11:07:54.257449 RX Vref 32 -> 127, step: 1
1687 11:07:54.257746
1688 11:07:54.260741 RX Delay -95 -> 252, step: 8
1689 11:07:54.261267
1690 11:07:54.263924 Set Vref, RX VrefLevel [Byte0]: 32
1691 11:07:54.266887 [Byte1]: 32
1692 11:07:54.267271
1693 11:07:54.270351 Set Vref, RX VrefLevel [Byte0]: 33
1694 11:07:54.273811 [Byte1]: 33
1695 11:07:54.277565
1696 11:07:54.277948 Set Vref, RX VrefLevel [Byte0]: 34
1697 11:07:54.280858 [Byte1]: 34
1698 11:07:54.285528
1699 11:07:54.285910 Set Vref, RX VrefLevel [Byte0]: 35
1700 11:07:54.288924 [Byte1]: 35
1701 11:07:54.292858
1702 11:07:54.293252 Set Vref, RX VrefLevel [Byte0]: 36
1703 11:07:54.296951 [Byte1]: 36
1704 11:07:54.300613
1705 11:07:54.300998 Set Vref, RX VrefLevel [Byte0]: 37
1706 11:07:54.303594 [Byte1]: 37
1707 11:07:54.308151
1708 11:07:54.308537 Set Vref, RX VrefLevel [Byte0]: 38
1709 11:07:54.312017 [Byte1]: 38
1710 11:07:54.315999
1711 11:07:54.316384 Set Vref, RX VrefLevel [Byte0]: 39
1712 11:07:54.318962 [Byte1]: 39
1713 11:07:54.323531
1714 11:07:54.323919 Set Vref, RX VrefLevel [Byte0]: 40
1715 11:07:54.326628 [Byte1]: 40
1716 11:07:54.331149
1717 11:07:54.331571 Set Vref, RX VrefLevel [Byte0]: 41
1718 11:07:54.334332 [Byte1]: 41
1719 11:07:54.338522
1720 11:07:54.338977 Set Vref, RX VrefLevel [Byte0]: 42
1721 11:07:54.341994 [Byte1]: 42
1722 11:07:54.345894
1723 11:07:54.346282 Set Vref, RX VrefLevel [Byte0]: 43
1724 11:07:54.349481 [Byte1]: 43
1725 11:07:54.353696
1726 11:07:54.354084 Set Vref, RX VrefLevel [Byte0]: 44
1727 11:07:54.357230 [Byte1]: 44
1728 11:07:54.361556
1729 11:07:54.361967 Set Vref, RX VrefLevel [Byte0]: 45
1730 11:07:54.364993 [Byte1]: 45
1731 11:07:54.368685
1732 11:07:54.369067 Set Vref, RX VrefLevel [Byte0]: 46
1733 11:07:54.372787 [Byte1]: 46
1734 11:07:54.376645
1735 11:07:54.377030 Set Vref, RX VrefLevel [Byte0]: 47
1736 11:07:54.380082 [Byte1]: 47
1737 11:07:54.384223
1738 11:07:54.384610 Set Vref, RX VrefLevel [Byte0]: 48
1739 11:07:54.387542 [Byte1]: 48
1740 11:07:54.391508
1741 11:07:54.391898 Set Vref, RX VrefLevel [Byte0]: 49
1742 11:07:54.395164 [Byte1]: 49
1743 11:07:54.399555
1744 11:07:54.399941 Set Vref, RX VrefLevel [Byte0]: 50
1745 11:07:54.402528 [Byte1]: 50
1746 11:07:54.407177
1747 11:07:54.407578 Set Vref, RX VrefLevel [Byte0]: 51
1748 11:07:54.410072 [Byte1]: 51
1749 11:07:54.414410
1750 11:07:54.414817 Set Vref, RX VrefLevel [Byte0]: 52
1751 11:07:54.417912 [Byte1]: 52
1752 11:07:54.422418
1753 11:07:54.422800 Set Vref, RX VrefLevel [Byte0]: 53
1754 11:07:54.425385 [Byte1]: 53
1755 11:07:54.429876
1756 11:07:54.430332 Set Vref, RX VrefLevel [Byte0]: 54
1757 11:07:54.433307 [Byte1]: 54
1758 11:07:54.437709
1759 11:07:54.438174 Set Vref, RX VrefLevel [Byte0]: 55
1760 11:07:54.440911 [Byte1]: 55
1761 11:07:54.444842
1762 11:07:54.445224 Set Vref, RX VrefLevel [Byte0]: 56
1763 11:07:54.448537 [Byte1]: 56
1764 11:07:54.452983
1765 11:07:54.453490 Set Vref, RX VrefLevel [Byte0]: 57
1766 11:07:54.455594 [Byte1]: 57
1767 11:07:54.460013
1768 11:07:54.460449 Set Vref, RX VrefLevel [Byte0]: 58
1769 11:07:54.463596 [Byte1]: 58
1770 11:07:54.467750
1771 11:07:54.468256 Set Vref, RX VrefLevel [Byte0]: 59
1772 11:07:54.471100 [Byte1]: 59
1773 11:07:54.475528
1774 11:07:54.476026 Set Vref, RX VrefLevel [Byte0]: 60
1775 11:07:54.478750 [Byte1]: 60
1776 11:07:54.482960
1777 11:07:54.483383 Set Vref, RX VrefLevel [Byte0]: 61
1778 11:07:54.486098 [Byte1]: 61
1779 11:07:54.490867
1780 11:07:54.491370 Set Vref, RX VrefLevel [Byte0]: 62
1781 11:07:54.494186 [Byte1]: 62
1782 11:07:54.498180
1783 11:07:54.498684 Set Vref, RX VrefLevel [Byte0]: 63
1784 11:07:54.501905 [Byte1]: 63
1785 11:07:54.505621
1786 11:07:54.506049 Set Vref, RX VrefLevel [Byte0]: 64
1787 11:07:54.509013 [Byte1]: 64
1788 11:07:54.513463
1789 11:07:54.514013 Set Vref, RX VrefLevel [Byte0]: 65
1790 11:07:54.516623 [Byte1]: 65
1791 11:07:54.521015
1792 11:07:54.521439 Set Vref, RX VrefLevel [Byte0]: 66
1793 11:07:54.523834 [Byte1]: 66
1794 11:07:54.528911
1795 11:07:54.529330 Set Vref, RX VrefLevel [Byte0]: 67
1796 11:07:54.531932 [Byte1]: 67
1797 11:07:54.535945
1798 11:07:54.536369 Set Vref, RX VrefLevel [Byte0]: 68
1799 11:07:54.539222 [Byte1]: 68
1800 11:07:54.543658
1801 11:07:54.544084 Set Vref, RX VrefLevel [Byte0]: 69
1802 11:07:54.546727 [Byte1]: 69
1803 11:07:54.551548
1804 11:07:54.552066 Set Vref, RX VrefLevel [Byte0]: 70
1805 11:07:54.554738 [Byte1]: 70
1806 11:07:54.559536
1807 11:07:54.560104 Set Vref, RX VrefLevel [Byte0]: 71
1808 11:07:54.562166 [Byte1]: 71
1809 11:07:54.566585
1810 11:07:54.567010 Set Vref, RX VrefLevel [Byte0]: 72
1811 11:07:54.569700 [Byte1]: 72
1812 11:07:54.574524
1813 11:07:54.575029 Set Vref, RX VrefLevel [Byte0]: 73
1814 11:07:54.577390 [Byte1]: 73
1815 11:07:54.581511
1816 11:07:54.581937 Set Vref, RX VrefLevel [Byte0]: 74
1817 11:07:54.584623 [Byte1]: 74
1818 11:07:54.589040
1819 11:07:54.589462 Set Vref, RX VrefLevel [Byte0]: 75
1820 11:07:54.592401 [Byte1]: 75
1821 11:07:54.596877
1822 11:07:54.597256 Set Vref, RX VrefLevel [Byte0]: 76
1823 11:07:54.599992 [Byte1]: 76
1824 11:07:54.604361
1825 11:07:54.604746 Set Vref, RX VrefLevel [Byte0]: 77
1826 11:07:54.607715 [Byte1]: 77
1827 11:07:54.612170
1828 11:07:54.612551 Final RX Vref Byte 0 = 56 to rank0
1829 11:07:54.615395 Final RX Vref Byte 1 = 62 to rank0
1830 11:07:54.618617 Final RX Vref Byte 0 = 56 to rank1
1831 11:07:54.622142 Final RX Vref Byte 1 = 62 to rank1==
1832 11:07:54.625070 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 11:07:54.631852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 11:07:54.632276 ==
1835 11:07:54.632600 DQS Delay:
1836 11:07:54.632872 DQS0 = 0, DQS1 = 0
1837 11:07:54.635135 DQM Delay:
1838 11:07:54.635546 DQM0 = 86, DQM1 = 78
1839 11:07:54.638730 DQ Delay:
1840 11:07:54.641996 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1841 11:07:54.645143 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1842 11:07:54.648562 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1843 11:07:54.651549 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =84
1844 11:07:54.651933
1845 11:07:54.652229
1846 11:07:54.658406 [DQSOSCAuto] RK0, (LSB)MR18= 0x311c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1847 11:07:54.661853 CH1 RK0: MR19=606, MR18=311C
1848 11:07:54.668270 CH1_RK0: MR19=0x606, MR18=0x311C, DQSOSC=397, MR23=63, INC=93, DEC=62
1849 11:07:54.668661
1850 11:07:54.671761 ----->DramcWriteLeveling(PI) begin...
1851 11:07:54.672150 ==
1852 11:07:54.675329 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 11:07:54.678206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 11:07:54.678639 ==
1855 11:07:54.681774 Write leveling (Byte 0): 27 => 27
1856 11:07:54.684923 Write leveling (Byte 1): 32 => 32
1857 11:07:54.687803 DramcWriteLeveling(PI) end<-----
1858 11:07:54.688183
1859 11:07:54.688478 ==
1860 11:07:54.691469 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 11:07:54.694869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 11:07:54.695256 ==
1863 11:07:54.697972 [Gating] SW mode calibration
1864 11:07:54.704505 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 11:07:54.711539 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 11:07:54.714630 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1867 11:07:54.721420 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1868 11:07:54.724681 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1869 11:07:54.727884 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:07:54.731581 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:07:54.738089 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:07:54.741438 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:07:54.744936 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:07:54.751480 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:07:54.754426 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:07:54.757982 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:07:54.765187 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:07:54.768051 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:07:54.771240 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:07:54.778110 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:07:54.781283 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:07:54.784169 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:07:54.790831 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1884 11:07:54.794420 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1885 11:07:54.797829 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:07:54.804158 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:07:54.807936 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:07:54.811125 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:07:54.818206 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:07:54.820864 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:07:54.824737 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:07:54.830914 0 9 8 | B1->B0 | 302f 2525 | 1 0 | (0 0) (1 1)
1893 11:07:54.834395 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 11:07:54.837871 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 11:07:54.844195 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 11:07:54.847844 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 11:07:54.850925 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 11:07:54.857863 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 11:07:54.861626 0 10 4 | B1->B0 | 3131 3434 | 1 0 | (1 0) (0 1)
1900 11:07:54.864015 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
1901 11:07:54.870753 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:07:54.874045 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:07:54.877657 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:07:54.884542 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:07:54.887475 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:07:54.890670 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:07:54.897416 0 11 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1908 11:07:54.901285 0 11 8 | B1->B0 | 4242 3939 | 0 0 | (0 0) (0 0)
1909 11:07:54.903952 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 11:07:54.907596 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 11:07:54.914103 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 11:07:54.917266 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:07:54.920202 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 11:07:54.926386 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:07:54.929801 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1916 11:07:54.933191 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 11:07:54.939541 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 11:07:54.943653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:07:54.946409 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:07:54.953405 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:07:54.956251 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:07:54.959737 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:07:54.966806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:07:54.969745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:07:54.973217 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:07:54.979841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:07:54.983293 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:07:54.986515 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:07:54.993869 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:07:54.996853 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:07:55.000239 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1932 11:07:55.006493 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1933 11:07:55.007002 Total UI for P1: 0, mck2ui 16
1934 11:07:55.013286 best dqsien dly found for B1: ( 0, 14, 4)
1935 11:07:55.016449 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 11:07:55.019851 Total UI for P1: 0, mck2ui 16
1937 11:07:55.023147 best dqsien dly found for B0: ( 0, 14, 6)
1938 11:07:55.026344 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1939 11:07:55.029599 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1940 11:07:55.030029
1941 11:07:55.032794 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1942 11:07:55.036318 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 11:07:55.039879 [Gating] SW calibration Done
1944 11:07:55.040301 ==
1945 11:07:55.043044 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 11:07:55.046449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 11:07:55.049602 ==
1948 11:07:55.049989 RX Vref Scan: 0
1949 11:07:55.050288
1950 11:07:55.052776 RX Vref 0 -> 0, step: 1
1951 11:07:55.053271
1952 11:07:55.056115 RX Delay -130 -> 252, step: 16
1953 11:07:55.059407 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1954 11:07:55.062821 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1955 11:07:55.066312 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1956 11:07:55.069008 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1957 11:07:55.075877 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1958 11:07:55.079390 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1959 11:07:55.082627 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1960 11:07:55.086270 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1961 11:07:55.089437 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1962 11:07:55.095927 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1963 11:07:55.098857 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1964 11:07:55.102340 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1965 11:07:55.105728 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1966 11:07:55.112470 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1967 11:07:55.115999 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1968 11:07:55.119144 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1969 11:07:55.119548 ==
1970 11:07:55.122606 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 11:07:55.126117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 11:07:55.126595 ==
1973 11:07:55.128885 DQS Delay:
1974 11:07:55.129271 DQS0 = 0, DQS1 = 0
1975 11:07:55.129574 DQM Delay:
1976 11:07:55.132303 DQM0 = 86, DQM1 = 78
1977 11:07:55.132690 DQ Delay:
1978 11:07:55.135625 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1979 11:07:55.139364 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1980 11:07:55.142533 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1981 11:07:55.145594 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1982 11:07:55.145979
1983 11:07:55.146277
1984 11:07:55.149086 ==
1985 11:07:55.149475 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 11:07:55.155702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 11:07:55.156090 ==
1988 11:07:55.156390
1989 11:07:55.156664
1990 11:07:55.159121 TX Vref Scan disable
1991 11:07:55.159545 == TX Byte 0 ==
1992 11:07:55.162636 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1993 11:07:55.168912 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1994 11:07:55.169380 == TX Byte 1 ==
1995 11:07:55.172159 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1996 11:07:55.178548 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1997 11:07:55.178940 ==
1998 11:07:55.182092 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 11:07:55.184677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 11:07:55.184753 ==
2001 11:07:55.198620 TX Vref=22, minBit 9, minWin=26, winSum=446
2002 11:07:55.201847 TX Vref=24, minBit 1, minWin=27, winSum=447
2003 11:07:55.205496 TX Vref=26, minBit 8, minWin=27, winSum=450
2004 11:07:55.208728 TX Vref=28, minBit 8, minWin=27, winSum=450
2005 11:07:55.212061 TX Vref=30, minBit 8, minWin=27, winSum=448
2006 11:07:55.218635 TX Vref=32, minBit 8, minWin=27, winSum=449
2007 11:07:55.221749 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 26
2008 11:07:55.221889
2009 11:07:55.224902 Final TX Range 1 Vref 26
2010 11:07:55.224977
2011 11:07:55.225036 ==
2012 11:07:55.228257 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 11:07:55.231553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 11:07:55.231634 ==
2015 11:07:55.235030
2016 11:07:55.235109
2017 11:07:55.235172 TX Vref Scan disable
2018 11:07:55.238911 == TX Byte 0 ==
2019 11:07:55.241966 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2020 11:07:55.248375 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2021 11:07:55.248477 == TX Byte 1 ==
2022 11:07:55.251939 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2023 11:07:55.258803 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2024 11:07:55.258992
2025 11:07:55.259111 [DATLAT]
2026 11:07:55.259215 Freq=800, CH1 RK1
2027 11:07:55.259305
2028 11:07:55.262113 DATLAT Default: 0xa
2029 11:07:55.262329 0, 0xFFFF, sum = 0
2030 11:07:55.265167 1, 0xFFFF, sum = 0
2031 11:07:55.268758 2, 0xFFFF, sum = 0
2032 11:07:55.268987 3, 0xFFFF, sum = 0
2033 11:07:55.271965 4, 0xFFFF, sum = 0
2034 11:07:55.272200 5, 0xFFFF, sum = 0
2035 11:07:55.275411 6, 0xFFFF, sum = 0
2036 11:07:55.275666 7, 0xFFFF, sum = 0
2037 11:07:55.278841 8, 0xFFFF, sum = 0
2038 11:07:55.279063 9, 0x0, sum = 1
2039 11:07:55.281995 10, 0x0, sum = 2
2040 11:07:55.282271 11, 0x0, sum = 3
2041 11:07:55.282492 12, 0x0, sum = 4
2042 11:07:55.285139 best_step = 10
2043 11:07:55.285443
2044 11:07:55.285729 ==
2045 11:07:55.288734 Dram Type= 6, Freq= 0, CH_1, rank 1
2046 11:07:55.292504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2047 11:07:55.293014 ==
2048 11:07:55.295989 RX Vref Scan: 0
2049 11:07:55.296485
2050 11:07:55.296815 RX Vref 0 -> 0, step: 1
2051 11:07:55.298525
2052 11:07:55.298945 RX Delay -95 -> 252, step: 8
2053 11:07:55.305465 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2054 11:07:55.309102 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2055 11:07:55.312507 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2056 11:07:55.315407 iDelay=217, Bit 3, Center 80 (-31 ~ 192) 224
2057 11:07:55.318980 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2058 11:07:55.325679 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2059 11:07:55.328867 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2060 11:07:55.332365 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2061 11:07:55.335508 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2062 11:07:55.339245 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2063 11:07:55.345549 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2064 11:07:55.348890 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2065 11:07:55.352134 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2066 11:07:55.355388 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2067 11:07:55.361925 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2068 11:07:55.365108 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2069 11:07:55.365523 ==
2070 11:07:55.368773 Dram Type= 6, Freq= 0, CH_1, rank 1
2071 11:07:55.372184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2072 11:07:55.372635 ==
2073 11:07:55.375056 DQS Delay:
2074 11:07:55.375469 DQS0 = 0, DQS1 = 0
2075 11:07:55.375779 DQM Delay:
2076 11:07:55.378332 DQM0 = 86, DQM1 = 78
2077 11:07:55.378711 DQ Delay:
2078 11:07:55.382169 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2079 11:07:55.385004 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2080 11:07:55.388458 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2081 11:07:55.391647 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2082 11:07:55.392025
2083 11:07:55.392319
2084 11:07:55.401902 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2085 11:07:55.402394 CH1 RK1: MR19=606, MR18=1B12
2086 11:07:55.408397 CH1_RK1: MR19=0x606, MR18=0x1B12, DQSOSC=403, MR23=63, INC=90, DEC=60
2087 11:07:55.411812 [RxdqsGatingPostProcess] freq 800
2088 11:07:55.418134 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2089 11:07:55.421549 Pre-setting of DQS Precalculation
2090 11:07:55.424946 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2091 11:07:55.434690 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2092 11:07:55.441496 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2093 11:07:55.441888
2094 11:07:55.442200
2095 11:07:55.444834 [Calibration Summary] 1600 Mbps
2096 11:07:55.445263 CH 0, Rank 0
2097 11:07:55.447754 SW Impedance : PASS
2098 11:07:55.448143 DUTY Scan : NO K
2099 11:07:55.451163 ZQ Calibration : PASS
2100 11:07:55.454841 Jitter Meter : NO K
2101 11:07:55.455231 CBT Training : PASS
2102 11:07:55.457997 Write leveling : PASS
2103 11:07:55.461168 RX DQS gating : PASS
2104 11:07:55.461665 RX DQ/DQS(RDDQC) : PASS
2105 11:07:55.464464 TX DQ/DQS : PASS
2106 11:07:55.467800 RX DATLAT : PASS
2107 11:07:55.468187 RX DQ/DQS(Engine): PASS
2108 11:07:55.471207 TX OE : NO K
2109 11:07:55.471636 All Pass.
2110 11:07:55.471940
2111 11:07:55.474571 CH 0, Rank 1
2112 11:07:55.474955 SW Impedance : PASS
2113 11:07:55.477972 DUTY Scan : NO K
2114 11:07:55.478359 ZQ Calibration : PASS
2115 11:07:55.480893 Jitter Meter : NO K
2116 11:07:55.484591 CBT Training : PASS
2117 11:07:55.484977 Write leveling : PASS
2118 11:07:55.487589 RX DQS gating : PASS
2119 11:07:55.491301 RX DQ/DQS(RDDQC) : PASS
2120 11:07:55.491743 TX DQ/DQS : PASS
2121 11:07:55.494813 RX DATLAT : PASS
2122 11:07:55.497649 RX DQ/DQS(Engine): PASS
2123 11:07:55.498038 TX OE : NO K
2124 11:07:55.501100 All Pass.
2125 11:07:55.501485
2126 11:07:55.501786 CH 1, Rank 0
2127 11:07:55.504657 SW Impedance : PASS
2128 11:07:55.505051 DUTY Scan : NO K
2129 11:07:55.507940 ZQ Calibration : PASS
2130 11:07:55.511227 Jitter Meter : NO K
2131 11:07:55.511656 CBT Training : PASS
2132 11:07:55.514249 Write leveling : PASS
2133 11:07:55.517374 RX DQS gating : PASS
2134 11:07:55.517770 RX DQ/DQS(RDDQC) : PASS
2135 11:07:55.520855 TX DQ/DQS : PASS
2136 11:07:55.521243 RX DATLAT : PASS
2137 11:07:55.524261 RX DQ/DQS(Engine): PASS
2138 11:07:55.527493 TX OE : NO K
2139 11:07:55.527885 All Pass.
2140 11:07:55.528184
2141 11:07:55.530702 CH 1, Rank 1
2142 11:07:55.531090 SW Impedance : PASS
2143 11:07:55.534072 DUTY Scan : NO K
2144 11:07:55.534457 ZQ Calibration : PASS
2145 11:07:55.537657 Jitter Meter : NO K
2146 11:07:55.540506 CBT Training : PASS
2147 11:07:55.540782 Write leveling : PASS
2148 11:07:55.543867 RX DQS gating : PASS
2149 11:07:55.547358 RX DQ/DQS(RDDQC) : PASS
2150 11:07:55.547691 TX DQ/DQS : PASS
2151 11:07:55.550671 RX DATLAT : PASS
2152 11:07:55.553843 RX DQ/DQS(Engine): PASS
2153 11:07:55.554116 TX OE : NO K
2154 11:07:55.557453 All Pass.
2155 11:07:55.557724
2156 11:07:55.557936 DramC Write-DBI off
2157 11:07:55.560626 PER_BANK_REFRESH: Hybrid Mode
2158 11:07:55.560901 TX_TRACKING: ON
2159 11:07:55.564418 [GetDramInforAfterCalByMRR] Vendor 6.
2160 11:07:55.570556 [GetDramInforAfterCalByMRR] Revision 606.
2161 11:07:55.574034 [GetDramInforAfterCalByMRR] Revision 2 0.
2162 11:07:55.574307 MR0 0x3b3b
2163 11:07:55.574518 MR8 0x5151
2164 11:07:55.577168 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2165 11:07:55.577444
2166 11:07:55.580911 MR0 0x3b3b
2167 11:07:55.581299 MR8 0x5151
2168 11:07:55.583691 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 11:07:55.584026
2170 11:07:55.593509 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2171 11:07:55.597011 [FAST_K] Save calibration result to emmc
2172 11:07:55.600707 [FAST_K] Save calibration result to emmc
2173 11:07:55.603453 dram_init: config_dvfs: 1
2174 11:07:55.607025 dramc_set_vcore_voltage set vcore to 662500
2175 11:07:55.610272 Read voltage for 1200, 2
2176 11:07:55.610545 Vio18 = 0
2177 11:07:55.610759 Vcore = 662500
2178 11:07:55.613835 Vdram = 0
2179 11:07:55.614304 Vddq = 0
2180 11:07:55.614656 Vmddr = 0
2181 11:07:55.620606 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2182 11:07:55.623312 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2183 11:07:55.626835 MEM_TYPE=3, freq_sel=15
2184 11:07:55.630006 sv_algorithm_assistance_LP4_1600
2185 11:07:55.633252 ============ PULL DRAM RESETB DOWN ============
2186 11:07:55.636684 ========== PULL DRAM RESETB DOWN end =========
2187 11:07:55.643713 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2188 11:07:55.647044 ===================================
2189 11:07:55.650283 LPDDR4 DRAM CONFIGURATION
2190 11:07:55.653686 ===================================
2191 11:07:55.654078 EX_ROW_EN[0] = 0x0
2192 11:07:55.656931 EX_ROW_EN[1] = 0x0
2193 11:07:55.657324 LP4Y_EN = 0x0
2194 11:07:55.660429 WORK_FSP = 0x0
2195 11:07:55.660816 WL = 0x4
2196 11:07:55.663470 RL = 0x4
2197 11:07:55.663873 BL = 0x2
2198 11:07:55.666742 RPST = 0x0
2199 11:07:55.667129 RD_PRE = 0x0
2200 11:07:55.669981 WR_PRE = 0x1
2201 11:07:55.670465 WR_PST = 0x0
2202 11:07:55.673180 DBI_WR = 0x0
2203 11:07:55.673569 DBI_RD = 0x0
2204 11:07:55.676367 OTF = 0x1
2205 11:07:55.679802 ===================================
2206 11:07:55.683191 ===================================
2207 11:07:55.683698 ANA top config
2208 11:07:55.686446 ===================================
2209 11:07:55.689915 DLL_ASYNC_EN = 0
2210 11:07:55.693192 ALL_SLAVE_EN = 0
2211 11:07:55.696408 NEW_RANK_MODE = 1
2212 11:07:55.699563 DLL_IDLE_MODE = 1
2213 11:07:55.699954 LP45_APHY_COMB_EN = 1
2214 11:07:55.703529 TX_ODT_DIS = 1
2215 11:07:55.706496 NEW_8X_MODE = 1
2216 11:07:55.709632 ===================================
2217 11:07:55.713310 ===================================
2218 11:07:55.716555 data_rate = 2400
2219 11:07:55.719533 CKR = 1
2220 11:07:55.719922 DQ_P2S_RATIO = 8
2221 11:07:55.722887 ===================================
2222 11:07:55.726451 CA_P2S_RATIO = 8
2223 11:07:55.729531 DQ_CA_OPEN = 0
2224 11:07:55.732616 DQ_SEMI_OPEN = 0
2225 11:07:55.736376 CA_SEMI_OPEN = 0
2226 11:07:55.739474 CA_FULL_RATE = 0
2227 11:07:55.739872 DQ_CKDIV4_EN = 0
2228 11:07:55.742956 CA_CKDIV4_EN = 0
2229 11:07:55.746391 CA_PREDIV_EN = 0
2230 11:07:55.749771 PH8_DLY = 17
2231 11:07:55.753152 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2232 11:07:55.756623 DQ_AAMCK_DIV = 4
2233 11:07:55.757010 CA_AAMCK_DIV = 4
2234 11:07:55.759314 CA_ADMCK_DIV = 4
2235 11:07:55.762850 DQ_TRACK_CA_EN = 0
2236 11:07:55.766538 CA_PICK = 1200
2237 11:07:55.769586 CA_MCKIO = 1200
2238 11:07:55.772833 MCKIO_SEMI = 0
2239 11:07:55.776455 PLL_FREQ = 2366
2240 11:07:55.776844 DQ_UI_PI_RATIO = 32
2241 11:07:55.779480 CA_UI_PI_RATIO = 0
2242 11:07:55.782598 ===================================
2243 11:07:55.786305 ===================================
2244 11:07:55.789600 memory_type:LPDDR4
2245 11:07:55.792460 GP_NUM : 10
2246 11:07:55.792875 SRAM_EN : 1
2247 11:07:55.796413 MD32_EN : 0
2248 11:07:55.799180 ===================================
2249 11:07:55.802467 [ANA_INIT] >>>>>>>>>>>>>>
2250 11:07:55.802855 <<<<<< [CONFIGURE PHASE]: ANA_TX
2251 11:07:55.806051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2252 11:07:55.809336 ===================================
2253 11:07:55.812739 data_rate = 2400,PCW = 0X5b00
2254 11:07:55.815953 ===================================
2255 11:07:55.818940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2256 11:07:55.825442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 11:07:55.832268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 11:07:55.836028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2259 11:07:55.838946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2260 11:07:55.842392 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2261 11:07:55.845816 [ANA_INIT] flow start
2262 11:07:55.846206 [ANA_INIT] PLL >>>>>>>>
2263 11:07:55.848709 [ANA_INIT] PLL <<<<<<<<
2264 11:07:55.852140 [ANA_INIT] MIDPI >>>>>>>>
2265 11:07:55.852526 [ANA_INIT] MIDPI <<<<<<<<
2266 11:07:55.855559 [ANA_INIT] DLL >>>>>>>>
2267 11:07:55.859054 [ANA_INIT] DLL <<<<<<<<
2268 11:07:55.859481 [ANA_INIT] flow end
2269 11:07:55.865793 ============ LP4 DIFF to SE enter ============
2270 11:07:55.869080 ============ LP4 DIFF to SE exit ============
2271 11:07:55.872106 [ANA_INIT] <<<<<<<<<<<<<
2272 11:07:55.875331 [Flow] Enable top DCM control >>>>>
2273 11:07:55.878678 [Flow] Enable top DCM control <<<<<
2274 11:07:55.879102 Enable DLL master slave shuffle
2275 11:07:55.885542 ==============================================================
2276 11:07:55.888960 Gating Mode config
2277 11:07:55.892112 ==============================================================
2278 11:07:55.894956 Config description:
2279 11:07:55.904886 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2280 11:07:55.911857 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2281 11:07:55.914756 SELPH_MODE 0: By rank 1: By Phase
2282 11:07:55.921786 ==============================================================
2283 11:07:55.925042 GAT_TRACK_EN = 1
2284 11:07:55.928300 RX_GATING_MODE = 2
2285 11:07:55.931356 RX_GATING_TRACK_MODE = 2
2286 11:07:55.934900 SELPH_MODE = 1
2287 11:07:55.938227 PICG_EARLY_EN = 1
2288 11:07:55.941397 VALID_LAT_VALUE = 1
2289 11:07:55.944927 ==============================================================
2290 11:07:55.948058 Enter into Gating configuration >>>>
2291 11:07:55.951236 Exit from Gating configuration <<<<
2292 11:07:55.954585 Enter into DVFS_PRE_config >>>>>
2293 11:07:55.964730 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2294 11:07:55.968110 Exit from DVFS_PRE_config <<<<<
2295 11:07:55.971380 Enter into PICG configuration >>>>
2296 11:07:55.974327 Exit from PICG configuration <<<<
2297 11:07:55.977718 [RX_INPUT] configuration >>>>>
2298 11:07:55.981149 [RX_INPUT] configuration <<<<<
2299 11:07:55.987723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2300 11:07:55.991219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2301 11:07:55.997884 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2302 11:07:56.004201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2303 11:07:56.010637 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2304 11:07:56.017794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2305 11:07:56.020799 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2306 11:07:56.023772 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2307 11:07:56.027250 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2308 11:07:56.034117 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2309 11:07:56.037427 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2310 11:07:56.040709 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2311 11:07:56.043944 ===================================
2312 11:07:56.047274 LPDDR4 DRAM CONFIGURATION
2313 11:07:56.050518 ===================================
2314 11:07:56.053705 EX_ROW_EN[0] = 0x0
2315 11:07:56.054287 EX_ROW_EN[1] = 0x0
2316 11:07:56.057100 LP4Y_EN = 0x0
2317 11:07:56.057487 WORK_FSP = 0x0
2318 11:07:56.060330 WL = 0x4
2319 11:07:56.060731 RL = 0x4
2320 11:07:56.063599 BL = 0x2
2321 11:07:56.063983 RPST = 0x0
2322 11:07:56.067098 RD_PRE = 0x0
2323 11:07:56.067578 WR_PRE = 0x1
2324 11:07:56.070661 WR_PST = 0x0
2325 11:07:56.071047 DBI_WR = 0x0
2326 11:07:56.073549 DBI_RD = 0x0
2327 11:07:56.074005 OTF = 0x1
2328 11:07:56.076892 ===================================
2329 11:07:56.080195 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2330 11:07:56.086768 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2331 11:07:56.090006 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2332 11:07:56.093307 ===================================
2333 11:07:56.096578 LPDDR4 DRAM CONFIGURATION
2334 11:07:56.099791 ===================================
2335 11:07:56.103185 EX_ROW_EN[0] = 0x10
2336 11:07:56.103260 EX_ROW_EN[1] = 0x0
2337 11:07:56.106503 LP4Y_EN = 0x0
2338 11:07:56.106579 WORK_FSP = 0x0
2339 11:07:56.109867 WL = 0x4
2340 11:07:56.109944 RL = 0x4
2341 11:07:56.112919 BL = 0x2
2342 11:07:56.112993 RPST = 0x0
2343 11:07:56.116181 RD_PRE = 0x0
2344 11:07:56.116261 WR_PRE = 0x1
2345 11:07:56.119540 WR_PST = 0x0
2346 11:07:56.119614 DBI_WR = 0x0
2347 11:07:56.123476 DBI_RD = 0x0
2348 11:07:56.123584 OTF = 0x1
2349 11:07:56.126325 ===================================
2350 11:07:56.132600 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2351 11:07:56.132675 ==
2352 11:07:56.135978 Dram Type= 6, Freq= 0, CH_0, rank 0
2353 11:07:56.142806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2354 11:07:56.142882 ==
2355 11:07:56.142940 [Duty_Offset_Calibration]
2356 11:07:56.146103 B0:1 B1:-1 CA:0
2357 11:07:56.146177
2358 11:07:56.149180 [DutyScan_Calibration_Flow] k_type=0
2359 11:07:56.158060
2360 11:07:56.158134 ==CLK 0==
2361 11:07:56.161753 Final CLK duty delay cell = 0
2362 11:07:56.164897 [0] MAX Duty = 5094%(X100), DQS PI = 16
2363 11:07:56.168303 [0] MIN Duty = 4875%(X100), DQS PI = 8
2364 11:07:56.168377 [0] AVG Duty = 4984%(X100)
2365 11:07:56.171279
2366 11:07:56.174505 CH0 CLK Duty spec in!! Max-Min= 219%
2367 11:07:56.177938 [DutyScan_Calibration_Flow] ====Done====
2368 11:07:56.178012
2369 11:07:56.181121 [DutyScan_Calibration_Flow] k_type=1
2370 11:07:56.196506
2371 11:07:56.196579 ==DQS 0 ==
2372 11:07:56.199861 Final DQS duty delay cell = -4
2373 11:07:56.203327 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2374 11:07:56.206242 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2375 11:07:56.209594 [-4] AVG Duty = 4968%(X100)
2376 11:07:56.209668
2377 11:07:56.209725 ==DQS 1 ==
2378 11:07:56.213396 Final DQS duty delay cell = 0
2379 11:07:56.216275 [0] MAX Duty = 5124%(X100), DQS PI = 6
2380 11:07:56.219579 [0] MIN Duty = 5000%(X100), DQS PI = 22
2381 11:07:56.223213 [0] AVG Duty = 5062%(X100)
2382 11:07:56.223288
2383 11:07:56.226466 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2384 11:07:56.226542
2385 11:07:56.229677 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2386 11:07:56.233330 [DutyScan_Calibration_Flow] ====Done====
2387 11:07:56.233404
2388 11:07:56.236761 [DutyScan_Calibration_Flow] k_type=3
2389 11:07:56.254403
2390 11:07:56.254479 ==DQM 0 ==
2391 11:07:56.257911 Final DQM duty delay cell = 0
2392 11:07:56.261199 [0] MAX Duty = 5062%(X100), DQS PI = 20
2393 11:07:56.264581 [0] MIN Duty = 4844%(X100), DQS PI = 8
2394 11:07:56.264659 [0] AVG Duty = 4953%(X100)
2395 11:07:56.267631
2396 11:07:56.267707 ==DQM 1 ==
2397 11:07:56.271182 Final DQM duty delay cell = 4
2398 11:07:56.274296 [4] MAX Duty = 5156%(X100), DQS PI = 8
2399 11:07:56.277474 [4] MIN Duty = 4969%(X100), DQS PI = 24
2400 11:07:56.277551 [4] AVG Duty = 5062%(X100)
2401 11:07:56.280739
2402 11:07:56.284016 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2403 11:07:56.284094
2404 11:07:56.287631 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2405 11:07:56.290684 [DutyScan_Calibration_Flow] ====Done====
2406 11:07:56.290759
2407 11:07:56.294099 [DutyScan_Calibration_Flow] k_type=2
2408 11:07:56.309960
2409 11:07:56.310035 ==DQ 0 ==
2410 11:07:56.313162 Final DQ duty delay cell = -4
2411 11:07:56.316627 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2412 11:07:56.319947 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2413 11:07:56.323218 [-4] AVG Duty = 4953%(X100)
2414 11:07:56.323292
2415 11:07:56.323351 ==DQ 1 ==
2416 11:07:56.326447 Final DQ duty delay cell = 0
2417 11:07:56.329922 [0] MAX Duty = 5125%(X100), DQS PI = 52
2418 11:07:56.333105 [0] MIN Duty = 4969%(X100), DQS PI = 40
2419 11:07:56.336718 [0] AVG Duty = 5047%(X100)
2420 11:07:56.336794
2421 11:07:56.339572 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2422 11:07:56.339647
2423 11:07:56.343048 CH0 DQ 1 Duty spec in!! Max-Min= 156%
2424 11:07:56.346376 [DutyScan_Calibration_Flow] ====Done====
2425 11:07:56.346462 ==
2426 11:07:56.349529 Dram Type= 6, Freq= 0, CH_1, rank 0
2427 11:07:56.353154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2428 11:07:56.353248 ==
2429 11:07:56.356243 [Duty_Offset_Calibration]
2430 11:07:56.356345 B0:-1 B1:1 CA:2
2431 11:07:56.356424
2432 11:07:56.359601 [DutyScan_Calibration_Flow] k_type=0
2433 11:07:56.370726
2434 11:07:56.370864 ==CLK 0==
2435 11:07:56.373815 Final CLK duty delay cell = 0
2436 11:07:56.377397 [0] MAX Duty = 5156%(X100), DQS PI = 22
2437 11:07:56.380017 [0] MIN Duty = 4969%(X100), DQS PI = 62
2438 11:07:56.380093 [0] AVG Duty = 5062%(X100)
2439 11:07:56.383368
2440 11:07:56.386961 CH1 CLK Duty spec in!! Max-Min= 187%
2441 11:07:56.390390 [DutyScan_Calibration_Flow] ====Done====
2442 11:07:56.390465
2443 11:07:56.393588 [DutyScan_Calibration_Flow] k_type=1
2444 11:07:56.410068
2445 11:07:56.410147 ==DQS 0 ==
2446 11:07:56.412579 Final DQS duty delay cell = 0
2447 11:07:56.416304 [0] MAX Duty = 5125%(X100), DQS PI = 48
2448 11:07:56.419690 [0] MIN Duty = 4875%(X100), DQS PI = 6
2449 11:07:56.422651 [0] AVG Duty = 5000%(X100)
2450 11:07:56.422725
2451 11:07:56.422784 ==DQS 1 ==
2452 11:07:56.426162 Final DQS duty delay cell = 0
2453 11:07:56.429224 [0] MAX Duty = 5094%(X100), DQS PI = 12
2454 11:07:56.435941 [0] MIN Duty = 4969%(X100), DQS PI = 58
2455 11:07:56.436020 [0] AVG Duty = 5031%(X100)
2456 11:07:56.436080
2457 11:07:56.439043 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2458 11:07:56.439118
2459 11:07:56.442546 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2460 11:07:56.446115 [DutyScan_Calibration_Flow] ====Done====
2461 11:07:56.446190
2462 11:07:56.449085 [DutyScan_Calibration_Flow] k_type=3
2463 11:07:56.465208
2464 11:07:56.465287 ==DQM 0 ==
2465 11:07:56.468445 Final DQM duty delay cell = -4
2466 11:07:56.471911 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2467 11:07:56.475128 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2468 11:07:56.478630 [-4] AVG Duty = 4937%(X100)
2469 11:07:56.478705
2470 11:07:56.478762 ==DQM 1 ==
2471 11:07:56.481967 Final DQM duty delay cell = 0
2472 11:07:56.485232 [0] MAX Duty = 5187%(X100), DQS PI = 8
2473 11:07:56.488206 [0] MIN Duty = 4969%(X100), DQS PI = 28
2474 11:07:56.491728 [0] AVG Duty = 5078%(X100)
2475 11:07:56.491803
2476 11:07:56.495259 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2477 11:07:56.495334
2478 11:07:56.498205 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2479 11:07:56.501870 [DutyScan_Calibration_Flow] ====Done====
2480 11:07:56.501946
2481 11:07:56.505349 [DutyScan_Calibration_Flow] k_type=2
2482 11:07:56.522051
2483 11:07:56.522127 ==DQ 0 ==
2484 11:07:56.525503 Final DQ duty delay cell = 0
2485 11:07:56.528802 [0] MAX Duty = 5156%(X100), DQS PI = 28
2486 11:07:56.531933 [0] MIN Duty = 4907%(X100), DQS PI = 6
2487 11:07:56.532008 [0] AVG Duty = 5031%(X100)
2488 11:07:56.532066
2489 11:07:56.535054 ==DQ 1 ==
2490 11:07:56.538487 Final DQ duty delay cell = 0
2491 11:07:56.541981 [0] MAX Duty = 5124%(X100), DQS PI = 10
2492 11:07:56.545237 [0] MIN Duty = 4969%(X100), DQS PI = 0
2493 11:07:56.545312 [0] AVG Duty = 5046%(X100)
2494 11:07:56.545370
2495 11:07:56.548710 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2496 11:07:56.551648
2497 11:07:56.554929 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2498 11:07:56.558504 [DutyScan_Calibration_Flow] ====Done====
2499 11:07:56.561839 nWR fixed to 30
2500 11:07:56.561918 [ModeRegInit_LP4] CH0 RK0
2501 11:07:56.565308 [ModeRegInit_LP4] CH0 RK1
2502 11:07:56.568006 [ModeRegInit_LP4] CH1 RK0
2503 11:07:56.571394 [ModeRegInit_LP4] CH1 RK1
2504 11:07:56.571511 match AC timing 7
2505 11:07:56.574748 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2506 11:07:56.581575 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2507 11:07:56.585087 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2508 11:07:56.591500 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2509 11:07:56.594651 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2510 11:07:56.594726 ==
2511 11:07:56.598256 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 11:07:56.601422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 11:07:56.601498 ==
2514 11:07:56.608114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2515 11:07:56.614803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2516 11:07:56.621496 [CA 0] Center 39 (9~70) winsize 62
2517 11:07:56.624930 [CA 1] Center 39 (9~70) winsize 62
2518 11:07:56.628378 [CA 2] Center 35 (5~66) winsize 62
2519 11:07:56.631727 [CA 3] Center 35 (5~65) winsize 61
2520 11:07:56.634728 [CA 4] Center 33 (3~64) winsize 62
2521 11:07:56.638021 [CA 5] Center 33 (4~63) winsize 60
2522 11:07:56.638098
2523 11:07:56.641652 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2524 11:07:56.641727
2525 11:07:56.644703 [CATrainingPosCal] consider 1 rank data
2526 11:07:56.648343 u2DelayCellTimex100 = 270/100 ps
2527 11:07:56.651623 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2528 11:07:56.657864 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 11:07:56.661641 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 11:07:56.664667 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2531 11:07:56.667750 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2532 11:07:56.671126 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2533 11:07:56.671204
2534 11:07:56.674792 CA PerBit enable=1, Macro0, CA PI delay=33
2535 11:07:56.674867
2536 11:07:56.677700 [CBTSetCACLKResult] CA Dly = 33
2537 11:07:56.681400 CS Dly: 8 (0~39)
2538 11:07:56.681474 ==
2539 11:07:56.684381 Dram Type= 6, Freq= 0, CH_0, rank 1
2540 11:07:56.687887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2541 11:07:56.687963 ==
2542 11:07:56.694257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2543 11:07:56.697851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2544 11:07:56.707419 [CA 0] Center 39 (8~70) winsize 63
2545 11:07:56.710731 [CA 1] Center 39 (9~70) winsize 62
2546 11:07:56.714125 [CA 2] Center 35 (5~66) winsize 62
2547 11:07:56.717405 [CA 3] Center 34 (4~65) winsize 62
2548 11:07:56.720639 [CA 4] Center 33 (3~64) winsize 62
2549 11:07:56.724206 [CA 5] Center 33 (3~63) winsize 61
2550 11:07:56.724308
2551 11:07:56.727369 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2552 11:07:56.727496
2553 11:07:56.730917 [CATrainingPosCal] consider 2 rank data
2554 11:07:56.733828 u2DelayCellTimex100 = 270/100 ps
2555 11:07:56.737216 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2556 11:07:56.744352 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2557 11:07:56.747450 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2558 11:07:56.750599 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2559 11:07:56.753933 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2560 11:07:56.757366 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2561 11:07:56.757645
2562 11:07:56.760918 CA PerBit enable=1, Macro0, CA PI delay=33
2563 11:07:56.761278
2564 11:07:56.763789 [CBTSetCACLKResult] CA Dly = 33
2565 11:07:56.767309 CS Dly: 9 (0~41)
2566 11:07:56.767743
2567 11:07:56.770713 ----->DramcWriteLeveling(PI) begin...
2568 11:07:56.771372 ==
2569 11:07:56.773949 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 11:07:56.777232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 11:07:56.777859 ==
2572 11:07:56.780588 Write leveling (Byte 0): 33 => 33
2573 11:07:56.783557 Write leveling (Byte 1): 27 => 27
2574 11:07:56.787008 DramcWriteLeveling(PI) end<-----
2575 11:07:56.787394
2576 11:07:56.787757 ==
2577 11:07:56.790505 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 11:07:56.793216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 11:07:56.793292 ==
2580 11:07:56.797152 [Gating] SW mode calibration
2581 11:07:56.803682 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2582 11:07:56.810212 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2583 11:07:56.813593 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2584 11:07:56.817178 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2585 11:07:56.823231 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 11:07:56.826837 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 11:07:56.830168 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 11:07:56.836996 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 11:07:56.839906 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 11:07:56.843230 0 15 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2591 11:07:56.850058 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2592 11:07:56.853582 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 11:07:56.856490 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 11:07:56.862941 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:07:56.866618 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 11:07:56.869972 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:07:56.876212 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:07:56.879864 1 0 28 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
2599 11:07:56.883225 1 1 0 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2600 11:07:56.889649 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2601 11:07:56.893215 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 11:07:56.896157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:07:56.903038 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 11:07:56.905980 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 11:07:56.909622 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:07:56.916344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2607 11:07:56.919825 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 11:07:56.922617 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 11:07:56.929187 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 11:07:56.932935 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:07:56.936092 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:07:56.942949 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:07:56.946283 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:07:56.949922 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:07:56.955711 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:07:56.959281 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:07:56.962643 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:07:56.969258 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:07:56.972461 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:07:56.975610 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:07:56.978981 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:07:56.985802 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 11:07:56.988956 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 11:07:56.992146 Total UI for P1: 0, mck2ui 16
2625 11:07:56.995380 best dqsien dly found for B0: ( 1, 3, 28)
2626 11:07:56.998960 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:07:57.002392 Total UI for P1: 0, mck2ui 16
2628 11:07:57.005606 best dqsien dly found for B1: ( 1, 4, 0)
2629 11:07:57.008954 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2630 11:07:57.012324 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2631 11:07:57.015765
2632 11:07:57.019198 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2633 11:07:57.021978 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2634 11:07:57.025419 [Gating] SW calibration Done
2635 11:07:57.025844 ==
2636 11:07:57.029141 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 11:07:57.032586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 11:07:57.032974 ==
2639 11:07:57.033274 RX Vref Scan: 0
2640 11:07:57.033548
2641 11:07:57.035418 RX Vref 0 -> 0, step: 1
2642 11:07:57.035842
2643 11:07:57.038825 RX Delay -40 -> 252, step: 8
2644 11:07:57.042283 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2645 11:07:57.045272 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2646 11:07:57.051977 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2647 11:07:57.055335 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2648 11:07:57.058542 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2649 11:07:57.061930 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2650 11:07:57.065418 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2651 11:07:57.071770 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2652 11:07:57.075313 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2653 11:07:57.078646 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2654 11:07:57.081844 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2655 11:07:57.085375 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2656 11:07:57.091700 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2657 11:07:57.094933 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2658 11:07:57.098363 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2659 11:07:57.101820 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2660 11:07:57.102208 ==
2661 11:07:57.104734 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 11:07:57.111636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 11:07:57.112024 ==
2664 11:07:57.112323 DQS Delay:
2665 11:07:57.115066 DQS0 = 0, DQS1 = 0
2666 11:07:57.115499 DQM Delay:
2667 11:07:57.115811 DQM0 = 119, DQM1 = 106
2668 11:07:57.118406 DQ Delay:
2669 11:07:57.121278 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2670 11:07:57.124814 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2671 11:07:57.128320 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2672 11:07:57.131752 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2673 11:07:57.132142
2674 11:07:57.132440
2675 11:07:57.132716 ==
2676 11:07:57.134559 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 11:07:57.137912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 11:07:57.141129 ==
2679 11:07:57.141514
2680 11:07:57.141834
2681 11:07:57.142118 TX Vref Scan disable
2682 11:07:57.144628 == TX Byte 0 ==
2683 11:07:57.148143 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2684 11:07:57.150997 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2685 11:07:57.154499 == TX Byte 1 ==
2686 11:07:57.158017 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2687 11:07:57.161703 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2688 11:07:57.164930 ==
2689 11:07:57.167602 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 11:07:57.170910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 11:07:57.171294 ==
2692 11:07:57.182788 TX Vref=22, minBit 5, minWin=25, winSum=421
2693 11:07:57.186055 TX Vref=24, minBit 4, minWin=26, winSum=429
2694 11:07:57.189528 TX Vref=26, minBit 1, minWin=25, winSum=433
2695 11:07:57.192830 TX Vref=28, minBit 4, minWin=26, winSum=439
2696 11:07:57.195908 TX Vref=30, minBit 4, minWin=26, winSum=434
2697 11:07:57.202409 TX Vref=32, minBit 4, minWin=26, winSum=431
2698 11:07:57.205621 [TxChooseVref] Worse bit 4, Min win 26, Win sum 439, Final Vref 28
2699 11:07:57.206009
2700 11:07:57.209263 Final TX Range 1 Vref 28
2701 11:07:57.209745
2702 11:07:57.210046 ==
2703 11:07:57.212712 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 11:07:57.215963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 11:07:57.218903 ==
2706 11:07:57.219286
2707 11:07:57.219609
2708 11:07:57.219885 TX Vref Scan disable
2709 11:07:57.222615 == TX Byte 0 ==
2710 11:07:57.226284 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2711 11:07:57.232240 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2712 11:07:57.232736 == TX Byte 1 ==
2713 11:07:57.235537 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2714 11:07:57.242247 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2715 11:07:57.242675
2716 11:07:57.243005 [DATLAT]
2717 11:07:57.243315 Freq=1200, CH0 RK0
2718 11:07:57.243669
2719 11:07:57.245534 DATLAT Default: 0xd
2720 11:07:57.245966 0, 0xFFFF, sum = 0
2721 11:07:57.249029 1, 0xFFFF, sum = 0
2722 11:07:57.252474 2, 0xFFFF, sum = 0
2723 11:07:57.252864 3, 0xFFFF, sum = 0
2724 11:07:57.255683 4, 0xFFFF, sum = 0
2725 11:07:57.256076 5, 0xFFFF, sum = 0
2726 11:07:57.258619 6, 0xFFFF, sum = 0
2727 11:07:57.259005 7, 0xFFFF, sum = 0
2728 11:07:57.261919 8, 0xFFFF, sum = 0
2729 11:07:57.262308 9, 0xFFFF, sum = 0
2730 11:07:57.265373 10, 0xFFFF, sum = 0
2731 11:07:57.265762 11, 0xFFFF, sum = 0
2732 11:07:57.268883 12, 0x0, sum = 1
2733 11:07:57.269270 13, 0x0, sum = 2
2734 11:07:57.272091 14, 0x0, sum = 3
2735 11:07:57.272569 15, 0x0, sum = 4
2736 11:07:57.275559 best_step = 13
2737 11:07:57.275942
2738 11:07:57.276244 ==
2739 11:07:57.278647 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 11:07:57.281888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 11:07:57.282273 ==
2742 11:07:57.282575 RX Vref Scan: 1
2743 11:07:57.282851
2744 11:07:57.285422 Set Vref Range= 32 -> 127
2745 11:07:57.285804
2746 11:07:57.289050 RX Vref 32 -> 127, step: 1
2747 11:07:57.289447
2748 11:07:57.292212 RX Delay -21 -> 252, step: 4
2749 11:07:57.292620
2750 11:07:57.295492 Set Vref, RX VrefLevel [Byte0]: 32
2751 11:07:57.298948 [Byte1]: 32
2752 11:07:57.299353
2753 11:07:57.302191 Set Vref, RX VrefLevel [Byte0]: 33
2754 11:07:57.305266 [Byte1]: 33
2755 11:07:57.309353
2756 11:07:57.309735 Set Vref, RX VrefLevel [Byte0]: 34
2757 11:07:57.312380 [Byte1]: 34
2758 11:07:57.316625
2759 11:07:57.317008 Set Vref, RX VrefLevel [Byte0]: 35
2760 11:07:57.319988 [Byte1]: 35
2761 11:07:57.324500
2762 11:07:57.324885 Set Vref, RX VrefLevel [Byte0]: 36
2763 11:07:57.328061 [Byte1]: 36
2764 11:07:57.332507
2765 11:07:57.332909 Set Vref, RX VrefLevel [Byte0]: 37
2766 11:07:57.335894 [Byte1]: 37
2767 11:07:57.340657
2768 11:07:57.341035 Set Vref, RX VrefLevel [Byte0]: 38
2769 11:07:57.344139 [Byte1]: 38
2770 11:07:57.348663
2771 11:07:57.349102 Set Vref, RX VrefLevel [Byte0]: 39
2772 11:07:57.352135 [Byte1]: 39
2773 11:07:57.356599
2774 11:07:57.356980 Set Vref, RX VrefLevel [Byte0]: 40
2775 11:07:57.360143 [Byte1]: 40
2776 11:07:57.364776
2777 11:07:57.365252 Set Vref, RX VrefLevel [Byte0]: 41
2778 11:07:57.367684 [Byte1]: 41
2779 11:07:57.372730
2780 11:07:57.373117 Set Vref, RX VrefLevel [Byte0]: 42
2781 11:07:57.376287 [Byte1]: 42
2782 11:07:57.380209
2783 11:07:57.380591 Set Vref, RX VrefLevel [Byte0]: 43
2784 11:07:57.383770 [Byte1]: 43
2785 11:07:57.388148
2786 11:07:57.388758 Set Vref, RX VrefLevel [Byte0]: 44
2787 11:07:57.391695 [Byte1]: 44
2788 11:07:57.396124
2789 11:07:57.396535 Set Vref, RX VrefLevel [Byte0]: 45
2790 11:07:57.399650 [Byte1]: 45
2791 11:07:57.403806
2792 11:07:57.404381 Set Vref, RX VrefLevel [Byte0]: 46
2793 11:07:57.407009 [Byte1]: 46
2794 11:07:57.411766
2795 11:07:57.412156 Set Vref, RX VrefLevel [Byte0]: 47
2796 11:07:57.415396 [Byte1]: 47
2797 11:07:57.419984
2798 11:07:57.420592 Set Vref, RX VrefLevel [Byte0]: 48
2799 11:07:57.423220 [Byte1]: 48
2800 11:07:57.427796
2801 11:07:57.428379 Set Vref, RX VrefLevel [Byte0]: 49
2802 11:07:57.430907 [Byte1]: 49
2803 11:07:57.435547
2804 11:07:57.436109 Set Vref, RX VrefLevel [Byte0]: 50
2805 11:07:57.438747 [Byte1]: 50
2806 11:07:57.443697
2807 11:07:57.444086 Set Vref, RX VrefLevel [Byte0]: 51
2808 11:07:57.446651 [Byte1]: 51
2809 11:07:57.451461
2810 11:07:57.451854 Set Vref, RX VrefLevel [Byte0]: 52
2811 11:07:57.454779 [Byte1]: 52
2812 11:07:57.459368
2813 11:07:57.459832 Set Vref, RX VrefLevel [Byte0]: 53
2814 11:07:57.462577 [Byte1]: 53
2815 11:07:57.467123
2816 11:07:57.467551 Set Vref, RX VrefLevel [Byte0]: 54
2817 11:07:57.470695 [Byte1]: 54
2818 11:07:57.475059
2819 11:07:57.475601 Set Vref, RX VrefLevel [Byte0]: 55
2820 11:07:57.478571 [Byte1]: 55
2821 11:07:57.482991
2822 11:07:57.483379 Set Vref, RX VrefLevel [Byte0]: 56
2823 11:07:57.486381 [Byte1]: 56
2824 11:07:57.491088
2825 11:07:57.491744 Set Vref, RX VrefLevel [Byte0]: 57
2826 11:07:57.494153 [Byte1]: 57
2827 11:07:57.499216
2828 11:07:57.499647 Set Vref, RX VrefLevel [Byte0]: 58
2829 11:07:57.502583 [Byte1]: 58
2830 11:07:57.507012
2831 11:07:57.507513 Set Vref, RX VrefLevel [Byte0]: 59
2832 11:07:57.510630 [Byte1]: 59
2833 11:07:57.515000
2834 11:07:57.515376 Set Vref, RX VrefLevel [Byte0]: 60
2835 11:07:57.521545 [Byte1]: 60
2836 11:07:57.521925
2837 11:07:57.524859 Set Vref, RX VrefLevel [Byte0]: 61
2838 11:07:57.528086 [Byte1]: 61
2839 11:07:57.528463
2840 11:07:57.531869 Set Vref, RX VrefLevel [Byte0]: 62
2841 11:07:57.534416 [Byte1]: 62
2842 11:07:57.538751
2843 11:07:57.539159 Set Vref, RX VrefLevel [Byte0]: 63
2844 11:07:57.542056 [Byte1]: 63
2845 11:07:57.546235
2846 11:07:57.546698 Set Vref, RX VrefLevel [Byte0]: 64
2847 11:07:57.550073 [Byte1]: 64
2848 11:07:57.554320
2849 11:07:57.554695 Set Vref, RX VrefLevel [Byte0]: 65
2850 11:07:57.558038 [Byte1]: 65
2851 11:07:57.562519
2852 11:07:57.562894 Set Vref, RX VrefLevel [Byte0]: 66
2853 11:07:57.565981 [Byte1]: 66
2854 11:07:57.570334
2855 11:07:57.570793 Set Vref, RX VrefLevel [Byte0]: 67
2856 11:07:57.573553 [Byte1]: 67
2857 11:07:57.578037
2858 11:07:57.578538 Set Vref, RX VrefLevel [Byte0]: 68
2859 11:07:57.581568 [Byte1]: 68
2860 11:07:57.586219
2861 11:07:57.586597 Set Vref, RX VrefLevel [Byte0]: 69
2862 11:07:57.589820 [Byte1]: 69
2863 11:07:57.594157
2864 11:07:57.594655 Set Vref, RX VrefLevel [Byte0]: 70
2865 11:07:57.597948 [Byte1]: 70
2866 11:07:57.602302
2867 11:07:57.602676 Set Vref, RX VrefLevel [Byte0]: 71
2868 11:07:57.605364 [Byte1]: 71
2869 11:07:57.609619
2870 11:07:57.609706 Set Vref, RX VrefLevel [Byte0]: 72
2871 11:07:57.613064 [Byte1]: 72
2872 11:07:57.617550
2873 11:07:57.617623 Set Vref, RX VrefLevel [Byte0]: 73
2874 11:07:57.620754 [Byte1]: 73
2875 11:07:57.625545
2876 11:07:57.625618 Set Vref, RX VrefLevel [Byte0]: 74
2877 11:07:57.628814 [Byte1]: 74
2878 11:07:57.633174
2879 11:07:57.633251 Set Vref, RX VrefLevel [Byte0]: 75
2880 11:07:57.636801 [Byte1]: 75
2881 11:07:57.641225
2882 11:07:57.641301 Set Vref, RX VrefLevel [Byte0]: 76
2883 11:07:57.644860 [Byte1]: 76
2884 11:07:57.649453
2885 11:07:57.652437 Set Vref, RX VrefLevel [Byte0]: 77
2886 11:07:57.652513 [Byte1]: 77
2887 11:07:57.657389
2888 11:07:57.657464 Set Vref, RX VrefLevel [Byte0]: 78
2889 11:07:57.660581 [Byte1]: 78
2890 11:07:57.665085
2891 11:07:57.665161 Final RX Vref Byte 0 = 60 to rank0
2892 11:07:57.668336 Final RX Vref Byte 1 = 50 to rank0
2893 11:07:57.672047 Final RX Vref Byte 0 = 60 to rank1
2894 11:07:57.674947 Final RX Vref Byte 1 = 50 to rank1==
2895 11:07:57.678515 Dram Type= 6, Freq= 0, CH_0, rank 0
2896 11:07:57.684806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 11:07:57.684901 ==
2898 11:07:57.684992 DQS Delay:
2899 11:07:57.688175 DQS0 = 0, DQS1 = 0
2900 11:07:57.688265 DQM Delay:
2901 11:07:57.688347 DQM0 = 119, DQM1 = 106
2902 11:07:57.691532 DQ Delay:
2903 11:07:57.694981 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2904 11:07:57.698643 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2905 11:07:57.701566 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =100
2906 11:07:57.705007 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2907 11:07:57.705083
2908 11:07:57.705159
2909 11:07:57.714875 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2910 11:07:57.714991 CH0 RK0: MR19=403, MR18=13FF
2911 11:07:57.721335 CH0_RK0: MR19=0x403, MR18=0x13FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2912 11:07:57.721468
2913 11:07:57.724761 ----->DramcWriteLeveling(PI) begin...
2914 11:07:57.724865 ==
2915 11:07:57.728585 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 11:07:57.734910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 11:07:57.735035 ==
2918 11:07:57.738450 Write leveling (Byte 0): 32 => 32
2919 11:07:57.738590 Write leveling (Byte 1): 30 => 30
2920 11:07:57.741353 DramcWriteLeveling(PI) end<-----
2921 11:07:57.741495
2922 11:07:57.745067 ==
2923 11:07:57.745226 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 11:07:57.751131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 11:07:57.751515 ==
2926 11:07:57.754433 [Gating] SW mode calibration
2927 11:07:57.761473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2928 11:07:57.764851 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2929 11:07:57.771041 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2930 11:07:57.774326 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2931 11:07:57.778208 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 11:07:57.784627 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 11:07:57.787770 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 11:07:57.791231 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 11:07:57.797812 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 11:07:57.801100 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2937 11:07:57.804648 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2938 11:07:57.811412 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 11:07:57.814378 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 11:07:57.817844 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 11:07:57.824216 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 11:07:57.827752 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 11:07:57.831212 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 11:07:57.837249 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2945 11:07:57.841104 1 1 0 | B1->B0 | 3736 4545 | 1 0 | (0 0) (0 0)
2946 11:07:57.844383 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:07:57.850609 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:07:57.854159 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 11:07:57.857413 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 11:07:57.863848 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 11:07:57.867414 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 11:07:57.870376 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2953 11:07:57.877547 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2954 11:07:57.880466 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:07:57.883681 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:07:57.890056 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:07:57.893789 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:07:57.896867 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:07:57.903419 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:07:57.906998 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:07:57.909967 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:07:57.916836 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:07:57.919809 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:07:57.923138 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 11:07:57.929965 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 11:07:57.932970 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 11:07:57.936427 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2968 11:07:57.943143 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2969 11:07:57.946487 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 11:07:57.949601 Total UI for P1: 0, mck2ui 16
2971 11:07:57.953286 best dqsien dly found for B0: ( 1, 3, 26)
2972 11:07:57.956323 Total UI for P1: 0, mck2ui 16
2973 11:07:57.959629 best dqsien dly found for B1: ( 1, 3, 28)
2974 11:07:57.962854 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2975 11:07:57.965829 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2976 11:07:57.966215
2977 11:07:57.969475 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2978 11:07:57.972817 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2979 11:07:57.976043 [Gating] SW calibration Done
2980 11:07:57.976403 ==
2981 11:07:57.979539 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 11:07:57.982477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 11:07:57.985988 ==
2984 11:07:57.986349 RX Vref Scan: 0
2985 11:07:57.986626
2986 11:07:57.989001 RX Vref 0 -> 0, step: 1
2987 11:07:57.989589
2988 11:07:57.992418 RX Delay -40 -> 252, step: 8
2989 11:07:57.995863 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2990 11:07:57.999367 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2991 11:07:58.002611 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2992 11:07:58.005399 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2993 11:07:58.012218 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2994 11:07:58.015815 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2995 11:07:58.019202 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2996 11:07:58.021950 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2997 11:07:58.025655 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2998 11:07:58.032252 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2999 11:07:58.035463 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3000 11:07:58.038822 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3001 11:07:58.042228 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3002 11:07:58.045185 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3003 11:07:58.051899 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3004 11:07:58.055127 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3005 11:07:58.055643 ==
3006 11:07:58.058787 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 11:07:58.061750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 11:07:58.062167 ==
3009 11:07:58.065121 DQS Delay:
3010 11:07:58.065474 DQS0 = 0, DQS1 = 0
3011 11:07:58.065852 DQM Delay:
3012 11:07:58.068357 DQM0 = 117, DQM1 = 107
3013 11:07:58.068968 DQ Delay:
3014 11:07:58.071537 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3015 11:07:58.078044 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3016 11:07:58.081570 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3017 11:07:58.084740 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3018 11:07:58.085097
3019 11:07:58.085371
3020 11:07:58.085625 ==
3021 11:07:58.088171 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 11:07:58.091356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 11:07:58.091765 ==
3024 11:07:58.092060
3025 11:07:58.092322
3026 11:07:58.094851 TX Vref Scan disable
3027 11:07:58.097731 == TX Byte 0 ==
3028 11:07:58.101104 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3029 11:07:58.104365 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3030 11:07:58.107532 == TX Byte 1 ==
3031 11:07:58.111055 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3032 11:07:58.114200 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3033 11:07:58.114556 ==
3034 11:07:58.117346 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 11:07:58.124299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 11:07:58.124700 ==
3037 11:07:58.134720 TX Vref=22, minBit 5, minWin=25, winSum=421
3038 11:07:58.137697 TX Vref=24, minBit 1, minWin=26, winSum=431
3039 11:07:58.141190 TX Vref=26, minBit 1, minWin=26, winSum=428
3040 11:07:58.144579 TX Vref=28, minBit 10, minWin=26, winSum=433
3041 11:07:58.148042 TX Vref=30, minBit 10, minWin=26, winSum=430
3042 11:07:58.154146 TX Vref=32, minBit 12, minWin=26, winSum=430
3043 11:07:58.157668 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 28
3044 11:07:58.158028
3045 11:07:58.160963 Final TX Range 1 Vref 28
3046 11:07:58.161353
3047 11:07:58.161629 ==
3048 11:07:58.164410 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 11:07:58.170915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 11:07:58.171413 ==
3051 11:07:58.171850
3052 11:07:58.172225
3053 11:07:58.172596 TX Vref Scan disable
3054 11:07:58.174799 == TX Byte 0 ==
3055 11:07:58.178055 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3056 11:07:58.184478 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3057 11:07:58.184885 == TX Byte 1 ==
3058 11:07:58.187900 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3059 11:07:58.194386 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3060 11:07:58.194842
3061 11:07:58.195232 [DATLAT]
3062 11:07:58.195604 Freq=1200, CH0 RK1
3063 11:07:58.195856
3064 11:07:58.197907 DATLAT Default: 0xd
3065 11:07:58.201183 0, 0xFFFF, sum = 0
3066 11:07:58.201537 1, 0xFFFF, sum = 0
3067 11:07:58.204542 2, 0xFFFF, sum = 0
3068 11:07:58.205162 3, 0xFFFF, sum = 0
3069 11:07:58.207845 4, 0xFFFF, sum = 0
3070 11:07:58.208209 5, 0xFFFF, sum = 0
3071 11:07:58.210614 6, 0xFFFF, sum = 0
3072 11:07:58.210968 7, 0xFFFF, sum = 0
3073 11:07:58.214480 8, 0xFFFF, sum = 0
3074 11:07:58.215063 9, 0xFFFF, sum = 0
3075 11:07:58.217403 10, 0xFFFF, sum = 0
3076 11:07:58.217869 11, 0xFFFF, sum = 0
3077 11:07:58.220675 12, 0x0, sum = 1
3078 11:07:58.221027 13, 0x0, sum = 2
3079 11:07:58.224139 14, 0x0, sum = 3
3080 11:07:58.224537 15, 0x0, sum = 4
3081 11:07:58.227561 best_step = 13
3082 11:07:58.227905
3083 11:07:58.228176 ==
3084 11:07:58.231024 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 11:07:58.234307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 11:07:58.234661 ==
3087 11:07:58.237129 RX Vref Scan: 0
3088 11:07:58.237472
3089 11:07:58.237744 RX Vref 0 -> 0, step: 1
3090 11:07:58.237995
3091 11:07:58.241214 RX Delay -21 -> 252, step: 4
3092 11:07:58.247071 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3093 11:07:58.250570 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3094 11:07:58.253793 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3095 11:07:58.257307 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3096 11:07:58.260461 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3097 11:07:58.267074 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3098 11:07:58.270490 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3099 11:07:58.273729 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3100 11:07:58.277221 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3101 11:07:58.280336 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3102 11:07:58.287152 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3103 11:07:58.290052 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3104 11:07:58.293796 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3105 11:07:58.296932 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3106 11:07:58.303472 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3107 11:07:58.306572 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3108 11:07:58.307040 ==
3109 11:07:58.310070 Dram Type= 6, Freq= 0, CH_0, rank 1
3110 11:07:58.313392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 11:07:58.313746 ==
3112 11:07:58.314022 DQS Delay:
3113 11:07:58.316405 DQS0 = 0, DQS1 = 0
3114 11:07:58.316760 DQM Delay:
3115 11:07:58.319765 DQM0 = 116, DQM1 = 107
3116 11:07:58.320119 DQ Delay:
3117 11:07:58.323162 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3118 11:07:58.326747 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3119 11:07:58.329831 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3120 11:07:58.336094 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3121 11:07:58.336290
3122 11:07:58.336443
3123 11:07:58.343108 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3124 11:07:58.346459 CH0 RK1: MR19=403, MR18=DE8
3125 11:07:58.352814 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3126 11:07:58.356228 [RxdqsGatingPostProcess] freq 1200
3127 11:07:58.359077 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3128 11:07:58.362598 best DQS0 dly(2T, 0.5T) = (0, 11)
3129 11:07:58.365690 best DQS1 dly(2T, 0.5T) = (0, 12)
3130 11:07:58.368815 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3131 11:07:58.372430 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3132 11:07:58.375506 best DQS0 dly(2T, 0.5T) = (0, 11)
3133 11:07:58.378936 best DQS1 dly(2T, 0.5T) = (0, 11)
3134 11:07:58.382323 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3135 11:07:58.385454 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3136 11:07:58.388878 Pre-setting of DQS Precalculation
3137 11:07:58.392239 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3138 11:07:58.392437 ==
3139 11:07:58.395322 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 11:07:58.402305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 11:07:58.402604 ==
3142 11:07:58.405734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 11:07:58.411991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3144 11:07:58.421040 [CA 0] Center 37 (7~67) winsize 61
3145 11:07:58.424038 [CA 1] Center 37 (7~68) winsize 62
3146 11:07:58.427387 [CA 2] Center 34 (4~64) winsize 61
3147 11:07:58.430909 [CA 3] Center 33 (3~64) winsize 62
3148 11:07:58.434086 [CA 4] Center 34 (4~64) winsize 61
3149 11:07:58.437371 [CA 5] Center 33 (3~64) winsize 62
3150 11:07:58.437670
3151 11:07:58.440656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3152 11:07:58.441021
3153 11:07:58.444005 [CATrainingPosCal] consider 1 rank data
3154 11:07:58.447322 u2DelayCellTimex100 = 270/100 ps
3155 11:07:58.450288 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3156 11:07:58.457100 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3157 11:07:58.460674 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3158 11:07:58.463930 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3159 11:07:58.467166 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 11:07:58.470463 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3161 11:07:58.470763
3162 11:07:58.473962 CA PerBit enable=1, Macro0, CA PI delay=33
3163 11:07:58.474258
3164 11:07:58.476924 [CBTSetCACLKResult] CA Dly = 33
3165 11:07:58.480224 CS Dly: 6 (0~37)
3166 11:07:58.480555 ==
3167 11:07:58.483471 Dram Type= 6, Freq= 0, CH_1, rank 1
3168 11:07:58.487053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 11:07:58.487365 ==
3170 11:07:58.493345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3171 11:07:58.496626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3172 11:07:58.506397 [CA 0] Center 37 (7~68) winsize 62
3173 11:07:58.509867 [CA 1] Center 38 (8~68) winsize 61
3174 11:07:58.513139 [CA 2] Center 34 (4~65) winsize 62
3175 11:07:58.516364 [CA 3] Center 33 (3~64) winsize 62
3176 11:07:58.519839 [CA 4] Center 34 (3~65) winsize 63
3177 11:07:58.522771 [CA 5] Center 33 (3~64) winsize 62
3178 11:07:58.523165
3179 11:07:58.525979 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3180 11:07:58.526286
3181 11:07:58.529757 [CATrainingPosCal] consider 2 rank data
3182 11:07:58.533018 u2DelayCellTimex100 = 270/100 ps
3183 11:07:58.536337 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3184 11:07:58.542846 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3185 11:07:58.545752 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3186 11:07:58.549450 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3187 11:07:58.552344 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3188 11:07:58.555800 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3189 11:07:58.556100
3190 11:07:58.559070 CA PerBit enable=1, Macro0, CA PI delay=33
3191 11:07:58.559371
3192 11:07:58.562861 [CBTSetCACLKResult] CA Dly = 33
3193 11:07:58.566044 CS Dly: 7 (0~40)
3194 11:07:58.566346
3195 11:07:58.568932 ----->DramcWriteLeveling(PI) begin...
3196 11:07:58.569237 ==
3197 11:07:58.572235 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 11:07:58.575474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 11:07:58.575780 ==
3200 11:07:58.579036 Write leveling (Byte 0): 27 => 27
3201 11:07:58.582304 Write leveling (Byte 1): 26 => 26
3202 11:07:58.585600 DramcWriteLeveling(PI) end<-----
3203 11:07:58.585907
3204 11:07:58.586138 ==
3205 11:07:58.588830 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 11:07:58.592064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 11:07:58.592366 ==
3208 11:07:58.595446 [Gating] SW mode calibration
3209 11:07:58.602056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3210 11:07:58.608698 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3211 11:07:58.612191 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3212 11:07:58.615323 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 11:07:58.621956 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 11:07:58.625010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 11:07:58.628376 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 11:07:58.635088 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 11:07:58.638163 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3218 11:07:58.641628 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
3219 11:07:58.648049 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 11:07:58.651271 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 11:07:58.654673 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 11:07:58.661409 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 11:07:58.664306 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 11:07:58.667729 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 11:07:58.674500 1 0 24 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
3226 11:07:58.677729 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:07:58.680684 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:07:58.687711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:07:58.690991 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 11:07:58.694080 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 11:07:58.700629 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 11:07:58.703883 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 11:07:58.707314 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3234 11:07:58.713959 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3235 11:07:58.717064 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:07:58.720420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:07:58.727306 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:07:58.730241 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:07:58.734000 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:07:58.740431 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:07:58.743668 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:07:58.747288 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:07:58.753978 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:07:58.757275 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:07:58.760254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:07:58.767077 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 11:07:58.770582 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 11:07:58.773962 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 11:07:58.780430 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3250 11:07:58.783211 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3251 11:07:58.786776 Total UI for P1: 0, mck2ui 16
3252 11:07:58.790049 best dqsien dly found for B0: ( 1, 3, 24)
3253 11:07:58.793055 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 11:07:58.796300 Total UI for P1: 0, mck2ui 16
3255 11:07:58.799556 best dqsien dly found for B1: ( 1, 3, 26)
3256 11:07:58.803135 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3257 11:07:58.806416 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3258 11:07:58.809650
3259 11:07:58.813067 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3260 11:07:58.815877 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3261 11:07:58.819258 [Gating] SW calibration Done
3262 11:07:58.819358 ==
3263 11:07:58.822546 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 11:07:58.826095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 11:07:58.826193 ==
3266 11:07:58.829449 RX Vref Scan: 0
3267 11:07:58.829548
3268 11:07:58.829636 RX Vref 0 -> 0, step: 1
3269 11:07:58.829717
3270 11:07:58.832629 RX Delay -40 -> 252, step: 8
3271 11:07:58.836142 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3272 11:07:58.842508 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3273 11:07:58.845818 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3274 11:07:58.849177 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3275 11:07:58.852407 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3276 11:07:58.855731 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3277 11:07:58.862008 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3278 11:07:58.865647 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3279 11:07:58.868560 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3280 11:07:58.872035 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3281 11:07:58.875420 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3282 11:07:58.881923 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3283 11:07:58.885118 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3284 11:07:58.888655 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3285 11:07:58.891651 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3286 11:07:58.898150 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3287 11:07:58.898386 ==
3288 11:07:58.901307 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 11:07:58.904744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 11:07:58.904967 ==
3291 11:07:58.905144 DQS Delay:
3292 11:07:58.908119 DQS0 = 0, DQS1 = 0
3293 11:07:58.908340 DQM Delay:
3294 11:07:58.911965 DQM0 = 117, DQM1 = 108
3295 11:07:58.912252 DQ Delay:
3296 11:07:58.914684 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3297 11:07:58.917918 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3298 11:07:58.921531 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3299 11:07:58.924902 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3300 11:07:58.925175
3301 11:07:58.925387
3302 11:07:58.925584 ==
3303 11:07:58.928100 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 11:07:58.934520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 11:07:58.934800 ==
3306 11:07:58.935170
3307 11:07:58.935630
3308 11:07:58.938045 TX Vref Scan disable
3309 11:07:58.938558 == TX Byte 0 ==
3310 11:07:58.941885 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3311 11:07:58.947949 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3312 11:07:58.948550 == TX Byte 1 ==
3313 11:07:58.951628 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3314 11:07:58.957891 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3315 11:07:58.958464 ==
3316 11:07:58.961126 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 11:07:58.964553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 11:07:58.965113 ==
3319 11:07:58.976406 TX Vref=22, minBit 10, minWin=25, winSum=416
3320 11:07:58.979936 TX Vref=24, minBit 9, minWin=25, winSum=420
3321 11:07:58.982511 TX Vref=26, minBit 10, minWin=25, winSum=425
3322 11:07:58.986185 TX Vref=28, minBit 15, minWin=25, winSum=429
3323 11:07:58.989367 TX Vref=30, minBit 9, minWin=25, winSum=426
3324 11:07:58.996109 TX Vref=32, minBit 9, minWin=25, winSum=427
3325 11:07:58.999336 [TxChooseVref] Worse bit 15, Min win 25, Win sum 429, Final Vref 28
3326 11:07:59.002195
3327 11:07:59.002471 Final TX Range 1 Vref 28
3328 11:07:59.002661
3329 11:07:59.002907 ==
3330 11:07:59.005846 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 11:07:59.012336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 11:07:59.012606 ==
3333 11:07:59.012855
3334 11:07:59.013082
3335 11:07:59.013315 TX Vref Scan disable
3336 11:07:59.015920 == TX Byte 0 ==
3337 11:07:59.019649 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3338 11:07:59.026216 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3339 11:07:59.026486 == TX Byte 1 ==
3340 11:07:59.029106 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3341 11:07:59.035946 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3342 11:07:59.036218
3343 11:07:59.036450 [DATLAT]
3344 11:07:59.036666 Freq=1200, CH1 RK0
3345 11:07:59.036879
3346 11:07:59.039354 DATLAT Default: 0xd
3347 11:07:59.042436 0, 0xFFFF, sum = 0
3348 11:07:59.042712 1, 0xFFFF, sum = 0
3349 11:07:59.045721 2, 0xFFFF, sum = 0
3350 11:07:59.045995 3, 0xFFFF, sum = 0
3351 11:07:59.049284 4, 0xFFFF, sum = 0
3352 11:07:59.049612 5, 0xFFFF, sum = 0
3353 11:07:59.052172 6, 0xFFFF, sum = 0
3354 11:07:59.052437 7, 0xFFFF, sum = 0
3355 11:07:59.055806 8, 0xFFFF, sum = 0
3356 11:07:59.056081 9, 0xFFFF, sum = 0
3357 11:07:59.058878 10, 0xFFFF, sum = 0
3358 11:07:59.059202 11, 0xFFFF, sum = 0
3359 11:07:59.062636 12, 0x0, sum = 1
3360 11:07:59.062904 13, 0x0, sum = 2
3361 11:07:59.065650 14, 0x0, sum = 3
3362 11:07:59.065905 15, 0x0, sum = 4
3363 11:07:59.068753 best_step = 13
3364 11:07:59.069018
3365 11:07:59.069247 ==
3366 11:07:59.072347 Dram Type= 6, Freq= 0, CH_1, rank 0
3367 11:07:59.075249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3368 11:07:59.075521 ==
3369 11:07:59.078688 RX Vref Scan: 1
3370 11:07:59.078956
3371 11:07:59.079184 Set Vref Range= 32 -> 127
3372 11:07:59.079404
3373 11:07:59.082085 RX Vref 32 -> 127, step: 1
3374 11:07:59.082333
3375 11:07:59.085446 RX Delay -21 -> 252, step: 4
3376 11:07:59.085543
3377 11:07:59.088656 Set Vref, RX VrefLevel [Byte0]: 32
3378 11:07:59.092095 [Byte1]: 32
3379 11:07:59.092203
3380 11:07:59.095124 Set Vref, RX VrefLevel [Byte0]: 33
3381 11:07:59.098797 [Byte1]: 33
3382 11:07:59.102663
3383 11:07:59.105553 Set Vref, RX VrefLevel [Byte0]: 34
3384 11:07:59.105638 [Byte1]: 34
3385 11:07:59.110255
3386 11:07:59.110351 Set Vref, RX VrefLevel [Byte0]: 35
3387 11:07:59.113756 [Byte1]: 35
3388 11:07:59.118886
3389 11:07:59.118982 Set Vref, RX VrefLevel [Byte0]: 36
3390 11:07:59.121871 [Byte1]: 36
3391 11:07:59.126593
3392 11:07:59.126703 Set Vref, RX VrefLevel [Byte0]: 37
3393 11:07:59.129805 [Byte1]: 37
3394 11:07:59.133927
3395 11:07:59.134048 Set Vref, RX VrefLevel [Byte0]: 38
3396 11:07:59.137311 [Byte1]: 38
3397 11:07:59.142233
3398 11:07:59.142387 Set Vref, RX VrefLevel [Byte0]: 39
3399 11:07:59.145169 [Byte1]: 39
3400 11:07:59.150127
3401 11:07:59.150308 Set Vref, RX VrefLevel [Byte0]: 40
3402 11:07:59.153209 [Byte1]: 40
3403 11:07:59.158197
3404 11:07:59.158415 Set Vref, RX VrefLevel [Byte0]: 41
3405 11:07:59.161572 [Byte1]: 41
3406 11:07:59.166182
3407 11:07:59.166446 Set Vref, RX VrefLevel [Byte0]: 42
3408 11:07:59.169314 [Byte1]: 42
3409 11:07:59.174387
3410 11:07:59.174730 Set Vref, RX VrefLevel [Byte0]: 43
3411 11:07:59.177446 [Byte1]: 43
3412 11:07:59.181845
3413 11:07:59.182221 Set Vref, RX VrefLevel [Byte0]: 44
3414 11:07:59.185179 [Byte1]: 44
3415 11:07:59.189732
3416 11:07:59.190106 Set Vref, RX VrefLevel [Byte0]: 45
3417 11:07:59.193315 [Byte1]: 45
3418 11:07:59.197844
3419 11:07:59.198217 Set Vref, RX VrefLevel [Byte0]: 46
3420 11:07:59.201142 [Byte1]: 46
3421 11:07:59.205904
3422 11:07:59.206288 Set Vref, RX VrefLevel [Byte0]: 47
3423 11:07:59.208882 [Byte1]: 47
3424 11:07:59.213781
3425 11:07:59.214158 Set Vref, RX VrefLevel [Byte0]: 48
3426 11:07:59.217169 [Byte1]: 48
3427 11:07:59.221653
3428 11:07:59.222046 Set Vref, RX VrefLevel [Byte0]: 49
3429 11:07:59.225066 [Byte1]: 49
3430 11:07:59.229636
3431 11:07:59.230014 Set Vref, RX VrefLevel [Byte0]: 50
3432 11:07:59.232796 [Byte1]: 50
3433 11:07:59.237561
3434 11:07:59.237942 Set Vref, RX VrefLevel [Byte0]: 51
3435 11:07:59.240939 [Byte1]: 51
3436 11:07:59.245174
3437 11:07:59.245554 Set Vref, RX VrefLevel [Byte0]: 52
3438 11:07:59.248556 [Byte1]: 52
3439 11:07:59.253919
3440 11:07:59.254494 Set Vref, RX VrefLevel [Byte0]: 53
3441 11:07:59.256796 [Byte1]: 53
3442 11:07:59.261073
3443 11:07:59.261571 Set Vref, RX VrefLevel [Byte0]: 54
3444 11:07:59.264620 [Byte1]: 54
3445 11:07:59.269456
3446 11:07:59.269986 Set Vref, RX VrefLevel [Byte0]: 55
3447 11:07:59.272534 [Byte1]: 55
3448 11:07:59.276671
3449 11:07:59.277159 Set Vref, RX VrefLevel [Byte0]: 56
3450 11:07:59.280582 [Byte1]: 56
3451 11:07:59.285441
3452 11:07:59.286084 Set Vref, RX VrefLevel [Byte0]: 57
3453 11:07:59.288180 [Byte1]: 57
3454 11:07:59.292967
3455 11:07:59.293483 Set Vref, RX VrefLevel [Byte0]: 58
3456 11:07:59.296477 [Byte1]: 58
3457 11:07:59.300958
3458 11:07:59.304047 Set Vref, RX VrefLevel [Byte0]: 59
3459 11:07:59.307150 [Byte1]: 59
3460 11:07:59.307576
3461 11:07:59.310753 Set Vref, RX VrefLevel [Byte0]: 60
3462 11:07:59.313870 [Byte1]: 60
3463 11:07:59.314254
3464 11:07:59.317205 Set Vref, RX VrefLevel [Byte0]: 61
3465 11:07:59.320634 [Byte1]: 61
3466 11:07:59.324463
3467 11:07:59.324849 Set Vref, RX VrefLevel [Byte0]: 62
3468 11:07:59.328139 [Byte1]: 62
3469 11:07:59.332502
3470 11:07:59.332884 Set Vref, RX VrefLevel [Byte0]: 63
3471 11:07:59.335834 [Byte1]: 63
3472 11:07:59.340450
3473 11:07:59.340983 Set Vref, RX VrefLevel [Byte0]: 64
3474 11:07:59.343887 [Byte1]: 64
3475 11:07:59.348651
3476 11:07:59.349037 Set Vref, RX VrefLevel [Byte0]: 65
3477 11:07:59.351467 [Byte1]: 65
3478 11:07:59.356554
3479 11:07:59.356939 Set Vref, RX VrefLevel [Byte0]: 66
3480 11:07:59.359524 [Byte1]: 66
3481 11:07:59.364245
3482 11:07:59.364771 Set Vref, RX VrefLevel [Byte0]: 67
3483 11:07:59.367403 [Byte1]: 67
3484 11:07:59.372039
3485 11:07:59.372422 Final RX Vref Byte 0 = 50 to rank0
3486 11:07:59.375732 Final RX Vref Byte 1 = 61 to rank0
3487 11:07:59.378846 Final RX Vref Byte 0 = 50 to rank1
3488 11:07:59.382006 Final RX Vref Byte 1 = 61 to rank1==
3489 11:07:59.385078 Dram Type= 6, Freq= 0, CH_1, rank 0
3490 11:07:59.391725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 11:07:59.392407 ==
3492 11:07:59.392927 DQS Delay:
3493 11:07:59.393354 DQS0 = 0, DQS1 = 0
3494 11:07:59.395162 DQM Delay:
3495 11:07:59.395619 DQM0 = 116, DQM1 = 111
3496 11:07:59.398573 DQ Delay:
3497 11:07:59.401988 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3498 11:07:59.405338 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3499 11:07:59.408289 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3500 11:07:59.411515 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =120
3501 11:07:59.411979
3502 11:07:59.412399
3503 11:07:59.421811 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3504 11:07:59.422207 CH1 RK0: MR19=403, MR18=2F5
3505 11:07:59.428449 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3506 11:07:59.428835
3507 11:07:59.431361 ----->DramcWriteLeveling(PI) begin...
3508 11:07:59.431814 ==
3509 11:07:59.434720 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 11:07:59.441218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 11:07:59.441701 ==
3512 11:07:59.444701 Write leveling (Byte 0): 25 => 25
3513 11:07:59.447900 Write leveling (Byte 1): 25 => 25
3514 11:07:59.448288 DramcWriteLeveling(PI) end<-----
3515 11:07:59.448590
3516 11:07:59.451056 ==
3517 11:07:59.454569 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 11:07:59.458063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 11:07:59.458453 ==
3520 11:07:59.460974 [Gating] SW mode calibration
3521 11:07:59.467964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3522 11:07:59.471214 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3523 11:07:59.477799 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 11:07:59.480925 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 11:07:59.484220 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 11:07:59.490580 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 11:07:59.493890 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 11:07:59.497560 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 11:07:59.504114 0 15 24 | B1->B0 | 2d2d 3333 | 0 1 | (1 0) (1 0)
3530 11:07:59.507560 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3531 11:07:59.510748 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 11:07:59.517611 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 11:07:59.520692 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 11:07:59.524389 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 11:07:59.530980 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 11:07:59.533766 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 11:07:59.537191 1 0 24 | B1->B0 | 3838 2424 | 0 1 | (1 1) (0 0)
3538 11:07:59.543900 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3539 11:07:59.547226 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:07:59.550130 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 11:07:59.557150 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 11:07:59.560024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 11:07:59.563814 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 11:07:59.570075 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 11:07:59.573435 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3546 11:07:59.576654 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3547 11:07:59.583549 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:07:59.586343 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:07:59.589880 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:07:59.596316 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:07:59.599998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:07:59.602985 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:07:59.609860 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:07:59.612688 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:07:59.616388 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 11:07:59.623058 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 11:07:59.626242 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 11:07:59.629568 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 11:07:59.635778 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 11:07:59.639228 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 11:07:59.642691 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3562 11:07:59.649304 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3563 11:07:59.652278 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 11:07:59.655517 Total UI for P1: 0, mck2ui 16
3565 11:07:59.658777 best dqsien dly found for B0: ( 1, 3, 26)
3566 11:07:59.662191 Total UI for P1: 0, mck2ui 16
3567 11:07:59.665288 best dqsien dly found for B1: ( 1, 3, 26)
3568 11:07:59.668988 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3569 11:07:59.672528 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3570 11:07:59.672951
3571 11:07:59.676167 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3572 11:07:59.678536 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3573 11:07:59.681962 [Gating] SW calibration Done
3574 11:07:59.682348 ==
3575 11:07:59.685202 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 11:07:59.692290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 11:07:59.692725 ==
3578 11:07:59.693029 RX Vref Scan: 0
3579 11:07:59.693308
3580 11:07:59.695528 RX Vref 0 -> 0, step: 1
3581 11:07:59.695916
3582 11:07:59.698869 RX Delay -40 -> 252, step: 8
3583 11:07:59.701688 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3584 11:07:59.705029 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3585 11:07:59.708497 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3586 11:07:59.714899 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3587 11:07:59.718155 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3588 11:07:59.721542 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3589 11:07:59.724946 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3590 11:07:59.728193 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3591 11:07:59.731986 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3592 11:07:59.738253 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3593 11:07:59.741692 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3594 11:07:59.745048 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3595 11:07:59.748608 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3596 11:07:59.754854 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3597 11:07:59.758109 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3598 11:07:59.761746 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3599 11:07:59.762202 ==
3600 11:07:59.764533 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 11:07:59.767845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 11:07:59.768068 ==
3603 11:07:59.771068 DQS Delay:
3604 11:07:59.771311 DQS0 = 0, DQS1 = 0
3605 11:07:59.774324 DQM Delay:
3606 11:07:59.774555 DQM0 = 116, DQM1 = 110
3607 11:07:59.777604 DQ Delay:
3608 11:07:59.780791 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3609 11:07:59.784167 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3610 11:07:59.787551 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3611 11:07:59.790848 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3612 11:07:59.790983
3613 11:07:59.791077
3614 11:07:59.791160 ==
3615 11:07:59.793508 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 11:07:59.797438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 11:07:59.797514 ==
3618 11:07:59.797574
3619 11:07:59.797627
3620 11:07:59.800403 TX Vref Scan disable
3621 11:07:59.803920 == TX Byte 0 ==
3622 11:07:59.807255 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3623 11:07:59.810180 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3624 11:07:59.813750 == TX Byte 1 ==
3625 11:07:59.817111 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3626 11:07:59.820464 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3627 11:07:59.820530 ==
3628 11:07:59.823349 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 11:07:59.830051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 11:07:59.830121 ==
3631 11:07:59.840927 TX Vref=22, minBit 2, minWin=26, winSum=426
3632 11:07:59.844094 TX Vref=24, minBit 8, minWin=26, winSum=430
3633 11:07:59.847375 TX Vref=26, minBit 11, minWin=26, winSum=435
3634 11:07:59.850478 TX Vref=28, minBit 9, minWin=26, winSum=438
3635 11:07:59.853442 TX Vref=30, minBit 9, minWin=26, winSum=433
3636 11:07:59.860238 TX Vref=32, minBit 7, minWin=26, winSum=431
3637 11:07:59.863438 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 28
3638 11:07:59.863545
3639 11:07:59.866931 Final TX Range 1 Vref 28
3640 11:07:59.866999
3641 11:07:59.867054 ==
3642 11:07:59.870355 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 11:07:59.873308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 11:07:59.876787 ==
3645 11:07:59.876853
3646 11:07:59.876907
3647 11:07:59.876958 TX Vref Scan disable
3648 11:07:59.880146 == TX Byte 0 ==
3649 11:07:59.883485 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3650 11:07:59.890227 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3651 11:07:59.890298 == TX Byte 1 ==
3652 11:07:59.893896 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3653 11:07:59.900031 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3654 11:07:59.900106
3655 11:07:59.900165 [DATLAT]
3656 11:07:59.900220 Freq=1200, CH1 RK1
3657 11:07:59.900275
3658 11:07:59.903872 DATLAT Default: 0xd
3659 11:07:59.903947 0, 0xFFFF, sum = 0
3660 11:07:59.907351 1, 0xFFFF, sum = 0
3661 11:07:59.910251 2, 0xFFFF, sum = 0
3662 11:07:59.910327 3, 0xFFFF, sum = 0
3663 11:07:59.913391 4, 0xFFFF, sum = 0
3664 11:07:59.913467 5, 0xFFFF, sum = 0
3665 11:07:59.916748 6, 0xFFFF, sum = 0
3666 11:07:59.916824 7, 0xFFFF, sum = 0
3667 11:07:59.919987 8, 0xFFFF, sum = 0
3668 11:07:59.920065 9, 0xFFFF, sum = 0
3669 11:07:59.923284 10, 0xFFFF, sum = 0
3670 11:07:59.923376 11, 0xFFFF, sum = 0
3671 11:07:59.926565 12, 0x0, sum = 1
3672 11:07:59.926650 13, 0x0, sum = 2
3673 11:07:59.929598 14, 0x0, sum = 3
3674 11:07:59.929675 15, 0x0, sum = 4
3675 11:07:59.933282 best_step = 13
3676 11:07:59.933377
3677 11:07:59.933459 ==
3678 11:07:59.936171 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 11:07:59.939793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 11:07:59.939857 ==
3681 11:07:59.942939 RX Vref Scan: 0
3682 11:07:59.943002
3683 11:07:59.943054 RX Vref 0 -> 0, step: 1
3684 11:07:59.943105
3685 11:07:59.946340 RX Delay -21 -> 252, step: 4
3686 11:07:59.953221 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3687 11:07:59.955981 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3688 11:07:59.959573 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3689 11:07:59.962735 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3690 11:07:59.965976 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3691 11:07:59.972894 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3692 11:07:59.975793 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3693 11:07:59.979323 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3694 11:07:59.982563 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3695 11:07:59.985793 iDelay=199, Bit 9, Center 98 (35 ~ 162) 128
3696 11:07:59.992545 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3697 11:07:59.996084 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3698 11:07:59.999355 iDelay=199, Bit 12, Center 118 (55 ~ 182) 128
3699 11:08:00.002433 iDelay=199, Bit 13, Center 118 (55 ~ 182) 128
3700 11:08:00.006096 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3701 11:08:00.012551 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3702 11:08:00.012627 ==
3703 11:08:00.016091 Dram Type= 6, Freq= 0, CH_1, rank 1
3704 11:08:00.019320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3705 11:08:00.019436 ==
3706 11:08:00.019556 DQS Delay:
3707 11:08:00.022514 DQS0 = 0, DQS1 = 0
3708 11:08:00.022580 DQM Delay:
3709 11:08:00.025996 DQM0 = 116, DQM1 = 110
3710 11:08:00.026087 DQ Delay:
3711 11:08:00.028879 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3712 11:08:00.032307 DQ4 =114, DQ5 =126, DQ6 =128, DQ7 =116
3713 11:08:00.035539 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =102
3714 11:08:00.038921 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3715 11:08:00.038986
3716 11:08:00.039043
3717 11:08:00.048939 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3718 11:08:00.052264 CH1 RK1: MR19=303, MR18=F6F1
3719 11:08:00.058777 CH1_RK1: MR19=0x303, MR18=0xF6F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3720 11:08:00.061939 [RxdqsGatingPostProcess] freq 1200
3721 11:08:00.065558 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3722 11:08:00.068717 best DQS0 dly(2T, 0.5T) = (0, 11)
3723 11:08:00.071909 best DQS1 dly(2T, 0.5T) = (0, 11)
3724 11:08:00.075372 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3725 11:08:00.078945 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3726 11:08:00.081884 best DQS0 dly(2T, 0.5T) = (0, 11)
3727 11:08:00.085263 best DQS1 dly(2T, 0.5T) = (0, 11)
3728 11:08:00.088513 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3729 11:08:00.091976 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3730 11:08:00.095379 Pre-setting of DQS Precalculation
3731 11:08:00.098732 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3732 11:08:00.105153 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3733 11:08:00.114999 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3734 11:08:00.115093
3735 11:08:00.115182
3736 11:08:00.118202 [Calibration Summary] 2400 Mbps
3737 11:08:00.118271 CH 0, Rank 0
3738 11:08:00.121694 SW Impedance : PASS
3739 11:08:00.121763 DUTY Scan : NO K
3740 11:08:00.124963 ZQ Calibration : PASS
3741 11:08:00.128218 Jitter Meter : NO K
3742 11:08:00.128282 CBT Training : PASS
3743 11:08:00.131404 Write leveling : PASS
3744 11:08:00.134901 RX DQS gating : PASS
3745 11:08:00.134976 RX DQ/DQS(RDDQC) : PASS
3746 11:08:00.138366 TX DQ/DQS : PASS
3747 11:08:00.141184 RX DATLAT : PASS
3748 11:08:00.141258 RX DQ/DQS(Engine): PASS
3749 11:08:00.144451 TX OE : NO K
3750 11:08:00.144533 All Pass.
3751 11:08:00.144591
3752 11:08:00.147872 CH 0, Rank 1
3753 11:08:00.147972 SW Impedance : PASS
3754 11:08:00.151402 DUTY Scan : NO K
3755 11:08:00.151482 ZQ Calibration : PASS
3756 11:08:00.154516 Jitter Meter : NO K
3757 11:08:00.157672 CBT Training : PASS
3758 11:08:00.157736 Write leveling : PASS
3759 11:08:00.160882 RX DQS gating : PASS
3760 11:08:00.164460 RX DQ/DQS(RDDQC) : PASS
3761 11:08:00.164523 TX DQ/DQS : PASS
3762 11:08:00.168038 RX DATLAT : PASS
3763 11:08:00.170926 RX DQ/DQS(Engine): PASS
3764 11:08:00.170990 TX OE : NO K
3765 11:08:00.174375 All Pass.
3766 11:08:00.174463
3767 11:08:00.174542 CH 1, Rank 0
3768 11:08:00.177856 SW Impedance : PASS
3769 11:08:00.177935 DUTY Scan : NO K
3770 11:08:00.180932 ZQ Calibration : PASS
3771 11:08:00.184389 Jitter Meter : NO K
3772 11:08:00.184459 CBT Training : PASS
3773 11:08:00.187660 Write leveling : PASS
3774 11:08:00.191091 RX DQS gating : PASS
3775 11:08:00.191180 RX DQ/DQS(RDDQC) : PASS
3776 11:08:00.194589 TX DQ/DQS : PASS
3777 11:08:00.197274 RX DATLAT : PASS
3778 11:08:00.197349 RX DQ/DQS(Engine): PASS
3779 11:08:00.200785 TX OE : NO K
3780 11:08:00.200861 All Pass.
3781 11:08:00.200919
3782 11:08:00.204233 CH 1, Rank 1
3783 11:08:00.204308 SW Impedance : PASS
3784 11:08:00.207435 DUTY Scan : NO K
3785 11:08:00.210896 ZQ Calibration : PASS
3786 11:08:00.210961 Jitter Meter : NO K
3787 11:08:00.214352 CBT Training : PASS
3788 11:08:00.214415 Write leveling : PASS
3789 11:08:00.217542 RX DQS gating : PASS
3790 11:08:00.220815 RX DQ/DQS(RDDQC) : PASS
3791 11:08:00.220889 TX DQ/DQS : PASS
3792 11:08:00.223975 RX DATLAT : PASS
3793 11:08:00.227494 RX DQ/DQS(Engine): PASS
3794 11:08:00.227592 TX OE : NO K
3795 11:08:00.230479 All Pass.
3796 11:08:00.230553
3797 11:08:00.230611 DramC Write-DBI off
3798 11:08:00.234008 PER_BANK_REFRESH: Hybrid Mode
3799 11:08:00.237349 TX_TRACKING: ON
3800 11:08:00.243559 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3801 11:08:00.247030 [FAST_K] Save calibration result to emmc
3802 11:08:00.253412 dramc_set_vcore_voltage set vcore to 650000
3803 11:08:00.253487 Read voltage for 600, 5
3804 11:08:00.253548 Vio18 = 0
3805 11:08:00.256929 Vcore = 650000
3806 11:08:00.257003 Vdram = 0
3807 11:08:00.257062 Vddq = 0
3808 11:08:00.260556 Vmddr = 0
3809 11:08:00.263705 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3810 11:08:00.270381 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3811 11:08:00.270501 MEM_TYPE=3, freq_sel=19
3812 11:08:00.273549 sv_algorithm_assistance_LP4_1600
3813 11:08:00.280074 ============ PULL DRAM RESETB DOWN ============
3814 11:08:00.283637 ========== PULL DRAM RESETB DOWN end =========
3815 11:08:00.286788 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3816 11:08:00.290062 ===================================
3817 11:08:00.293117 LPDDR4 DRAM CONFIGURATION
3818 11:08:00.296440 ===================================
3819 11:08:00.299722 EX_ROW_EN[0] = 0x0
3820 11:08:00.299787 EX_ROW_EN[1] = 0x0
3821 11:08:00.303099 LP4Y_EN = 0x0
3822 11:08:00.303167 WORK_FSP = 0x0
3823 11:08:00.306370 WL = 0x2
3824 11:08:00.306430 RL = 0x2
3825 11:08:00.309829 BL = 0x2
3826 11:08:00.309926 RPST = 0x0
3827 11:08:00.313093 RD_PRE = 0x0
3828 11:08:00.313173 WR_PRE = 0x1
3829 11:08:00.316122 WR_PST = 0x0
3830 11:08:00.316200 DBI_WR = 0x0
3831 11:08:00.319622 DBI_RD = 0x0
3832 11:08:00.323206 OTF = 0x1
3833 11:08:00.323271 ===================================
3834 11:08:00.326504 ===================================
3835 11:08:00.329825 ANA top config
3836 11:08:00.332991 ===================================
3837 11:08:00.336367 DLL_ASYNC_EN = 0
3838 11:08:00.336434 ALL_SLAVE_EN = 1
3839 11:08:00.339639 NEW_RANK_MODE = 1
3840 11:08:00.343094 DLL_IDLE_MODE = 1
3841 11:08:00.346126 LP45_APHY_COMB_EN = 1
3842 11:08:00.349512 TX_ODT_DIS = 1
3843 11:08:00.349613 NEW_8X_MODE = 1
3844 11:08:00.352604 ===================================
3845 11:08:00.356005 ===================================
3846 11:08:00.359708 data_rate = 1200
3847 11:08:00.362573 CKR = 1
3848 11:08:00.365901 DQ_P2S_RATIO = 8
3849 11:08:00.369486 ===================================
3850 11:08:00.372862 CA_P2S_RATIO = 8
3851 11:08:00.375906 DQ_CA_OPEN = 0
3852 11:08:00.376014 DQ_SEMI_OPEN = 0
3853 11:08:00.379905 CA_SEMI_OPEN = 0
3854 11:08:00.382712 CA_FULL_RATE = 0
3855 11:08:00.385716 DQ_CKDIV4_EN = 1
3856 11:08:00.389087 CA_CKDIV4_EN = 1
3857 11:08:00.392340 CA_PREDIV_EN = 0
3858 11:08:00.392415 PH8_DLY = 0
3859 11:08:00.395883 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3860 11:08:00.398955 DQ_AAMCK_DIV = 4
3861 11:08:00.402214 CA_AAMCK_DIV = 4
3862 11:08:00.405256 CA_ADMCK_DIV = 4
3863 11:08:00.409111 DQ_TRACK_CA_EN = 0
3864 11:08:00.409186 CA_PICK = 600
3865 11:08:00.411990 CA_MCKIO = 600
3866 11:08:00.415490 MCKIO_SEMI = 0
3867 11:08:00.418633 PLL_FREQ = 2288
3868 11:08:00.422092 DQ_UI_PI_RATIO = 32
3869 11:08:00.425375 CA_UI_PI_RATIO = 0
3870 11:08:00.428706 ===================================
3871 11:08:00.432143 ===================================
3872 11:08:00.435457 memory_type:LPDDR4
3873 11:08:00.435533 GP_NUM : 10
3874 11:08:00.438655 SRAM_EN : 1
3875 11:08:00.438730 MD32_EN : 0
3876 11:08:00.441541 ===================================
3877 11:08:00.445290 [ANA_INIT] >>>>>>>>>>>>>>
3878 11:08:00.448150 <<<<<< [CONFIGURE PHASE]: ANA_TX
3879 11:08:00.451827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3880 11:08:00.455003 ===================================
3881 11:08:00.458122 data_rate = 1200,PCW = 0X5800
3882 11:08:00.461694 ===================================
3883 11:08:00.464773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3884 11:08:00.471780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3885 11:08:00.474603 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3886 11:08:00.481397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3887 11:08:00.485196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3888 11:08:00.488316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3889 11:08:00.488387 [ANA_INIT] flow start
3890 11:08:00.491066 [ANA_INIT] PLL >>>>>>>>
3891 11:08:00.494403 [ANA_INIT] PLL <<<<<<<<
3892 11:08:00.494499 [ANA_INIT] MIDPI >>>>>>>>
3893 11:08:00.497659 [ANA_INIT] MIDPI <<<<<<<<
3894 11:08:00.501163 [ANA_INIT] DLL >>>>>>>>
3895 11:08:00.501246 [ANA_INIT] flow end
3896 11:08:00.507675 ============ LP4 DIFF to SE enter ============
3897 11:08:00.511015 ============ LP4 DIFF to SE exit ============
3898 11:08:00.514748 [ANA_INIT] <<<<<<<<<<<<<
3899 11:08:00.518041 [Flow] Enable top DCM control >>>>>
3900 11:08:00.521072 [Flow] Enable top DCM control <<<<<
3901 11:08:00.521143 Enable DLL master slave shuffle
3902 11:08:00.528043 ==============================================================
3903 11:08:00.531260 Gating Mode config
3904 11:08:00.534166 ==============================================================
3905 11:08:00.537593 Config description:
3906 11:08:00.547337 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3907 11:08:00.553987 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3908 11:08:00.557327 SELPH_MODE 0: By rank 1: By Phase
3909 11:08:00.563863 ==============================================================
3910 11:08:00.567179 GAT_TRACK_EN = 1
3911 11:08:00.570696 RX_GATING_MODE = 2
3912 11:08:00.573978 RX_GATING_TRACK_MODE = 2
3913 11:08:00.577528 SELPH_MODE = 1
3914 11:08:00.580471 PICG_EARLY_EN = 1
3915 11:08:00.583832 VALID_LAT_VALUE = 1
3916 11:08:00.586712 ==============================================================
3917 11:08:00.590087 Enter into Gating configuration >>>>
3918 11:08:00.593512 Exit from Gating configuration <<<<
3919 11:08:00.596953 Enter into DVFS_PRE_config >>>>>
3920 11:08:00.609821 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3921 11:08:00.613071 Exit from DVFS_PRE_config <<<<<
3922 11:08:00.613170 Enter into PICG configuration >>>>
3923 11:08:00.616170 Exit from PICG configuration <<<<
3924 11:08:00.619850 [RX_INPUT] configuration >>>>>
3925 11:08:00.623003 [RX_INPUT] configuration <<<<<
3926 11:08:00.629342 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3927 11:08:00.632735 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3928 11:08:00.639459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3929 11:08:00.646061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3930 11:08:00.652302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3931 11:08:00.658949 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3932 11:08:00.662480 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3933 11:08:00.665912 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3934 11:08:00.672463 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3935 11:08:00.675460 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3936 11:08:00.679102 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3937 11:08:00.682353 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3938 11:08:00.685635 ===================================
3939 11:08:00.688795 LPDDR4 DRAM CONFIGURATION
3940 11:08:00.692235 ===================================
3941 11:08:00.695612 EX_ROW_EN[0] = 0x0
3942 11:08:00.695687 EX_ROW_EN[1] = 0x0
3943 11:08:00.698462 LP4Y_EN = 0x0
3944 11:08:00.698537 WORK_FSP = 0x0
3945 11:08:00.702060 WL = 0x2
3946 11:08:00.702135 RL = 0x2
3947 11:08:00.705437 BL = 0x2
3948 11:08:00.708542 RPST = 0x0
3949 11:08:00.708633 RD_PRE = 0x0
3950 11:08:00.711977 WR_PRE = 0x1
3951 11:08:00.712052 WR_PST = 0x0
3952 11:08:00.714933 DBI_WR = 0x0
3953 11:08:00.715009 DBI_RD = 0x0
3954 11:08:00.718745 OTF = 0x1
3955 11:08:00.721918 ===================================
3956 11:08:00.725071 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3957 11:08:00.728483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3958 11:08:00.731694 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3959 11:08:00.734940 ===================================
3960 11:08:00.738042 LPDDR4 DRAM CONFIGURATION
3961 11:08:00.741683 ===================================
3962 11:08:00.744771 EX_ROW_EN[0] = 0x10
3963 11:08:00.744846 EX_ROW_EN[1] = 0x0
3964 11:08:00.748114 LP4Y_EN = 0x0
3965 11:08:00.748189 WORK_FSP = 0x0
3966 11:08:00.751714 WL = 0x2
3967 11:08:00.751788 RL = 0x2
3968 11:08:00.754591 BL = 0x2
3969 11:08:00.757951 RPST = 0x0
3970 11:08:00.758026 RD_PRE = 0x0
3971 11:08:00.761165 WR_PRE = 0x1
3972 11:08:00.761240 WR_PST = 0x0
3973 11:08:00.764390 DBI_WR = 0x0
3974 11:08:00.764465 DBI_RD = 0x0
3975 11:08:00.767800 OTF = 0x1
3976 11:08:00.771298 ===================================
3977 11:08:00.777474 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3978 11:08:00.781073 nWR fixed to 30
3979 11:08:00.781149 [ModeRegInit_LP4] CH0 RK0
3980 11:08:00.784050 [ModeRegInit_LP4] CH0 RK1
3981 11:08:00.787381 [ModeRegInit_LP4] CH1 RK0
3982 11:08:00.787492 [ModeRegInit_LP4] CH1 RK1
3983 11:08:00.791130 match AC timing 17
3984 11:08:00.794058 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3985 11:08:00.800793 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3986 11:08:00.803721 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3987 11:08:00.810498 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3988 11:08:00.814099 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3989 11:08:00.814172 ==
3990 11:08:00.817521 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 11:08:00.820478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 11:08:00.820544 ==
3993 11:08:00.827403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3994 11:08:00.833543 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3995 11:08:00.836870 [CA 0] Center 36 (6~66) winsize 61
3996 11:08:00.840368 [CA 1] Center 36 (6~66) winsize 61
3997 11:08:00.843493 [CA 2] Center 34 (4~65) winsize 62
3998 11:08:00.846756 [CA 3] Center 34 (4~65) winsize 62
3999 11:08:00.850211 [CA 4] Center 33 (3~64) winsize 62
4000 11:08:00.853742 [CA 5] Center 33 (3~64) winsize 62
4001 11:08:00.853843
4002 11:08:00.857080 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4003 11:08:00.857173
4004 11:08:00.860164 [CATrainingPosCal] consider 1 rank data
4005 11:08:00.863623 u2DelayCellTimex100 = 270/100 ps
4006 11:08:00.866898 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4007 11:08:00.870179 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4008 11:08:00.873925 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4009 11:08:00.877382 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4010 11:08:00.880210 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4011 11:08:00.883825 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4012 11:08:00.883900
4013 11:08:00.890271 CA PerBit enable=1, Macro0, CA PI delay=33
4014 11:08:00.890346
4015 11:08:00.890404 [CBTSetCACLKResult] CA Dly = 33
4016 11:08:00.893193 CS Dly: 6 (0~37)
4017 11:08:00.893267 ==
4018 11:08:00.896373 Dram Type= 6, Freq= 0, CH_0, rank 1
4019 11:08:00.899902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 11:08:00.899978 ==
4021 11:08:00.906644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4022 11:08:00.913081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4023 11:08:00.916723 [CA 0] Center 36 (6~66) winsize 61
4024 11:08:00.919655 [CA 1] Center 36 (6~66) winsize 61
4025 11:08:00.923314 [CA 2] Center 33 (3~64) winsize 62
4026 11:08:00.926651 [CA 3] Center 33 (3~64) winsize 62
4027 11:08:00.929662 [CA 4] Center 33 (2~64) winsize 63
4028 11:08:00.933218 [CA 5] Center 33 (2~64) winsize 63
4029 11:08:00.933294
4030 11:08:00.936528 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4031 11:08:00.936605
4032 11:08:00.939975 [CATrainingPosCal] consider 2 rank data
4033 11:08:00.942906 u2DelayCellTimex100 = 270/100 ps
4034 11:08:00.946212 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4035 11:08:00.949540 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4036 11:08:00.953165 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4037 11:08:00.956075 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4038 11:08:00.959370 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4039 11:08:00.966033 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4040 11:08:00.966111
4041 11:08:00.969534 CA PerBit enable=1, Macro0, CA PI delay=33
4042 11:08:00.969610
4043 11:08:00.972812 [CBTSetCACLKResult] CA Dly = 33
4044 11:08:00.972905 CS Dly: 6 (0~37)
4045 11:08:00.972990
4046 11:08:00.976669 ----->DramcWriteLeveling(PI) begin...
4047 11:08:00.976754 ==
4048 11:08:00.979832 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 11:08:00.985987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 11:08:00.986063 ==
4051 11:08:00.989205 Write leveling (Byte 0): 33 => 33
4052 11:08:00.989291 Write leveling (Byte 1): 29 => 29
4053 11:08:00.992724 DramcWriteLeveling(PI) end<-----
4054 11:08:00.992801
4055 11:08:00.992860 ==
4056 11:08:00.996262 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 11:08:01.002629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 11:08:01.002704 ==
4059 11:08:01.006044 [Gating] SW mode calibration
4060 11:08:01.012688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4061 11:08:01.015661 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4062 11:08:01.022300 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 11:08:01.025807 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 11:08:01.029297 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4065 11:08:01.035623 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4066 11:08:01.039007 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4067 11:08:01.041975 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:08:01.049124 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 11:08:01.052475 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 11:08:01.055166 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 11:08:01.062053 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 11:08:01.065375 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 11:08:01.068843 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
4074 11:08:01.074960 0 10 16 | B1->B0 | 3838 4343 | 0 0 | (0 0) (1 1)
4075 11:08:01.078214 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:08:01.081705 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 11:08:01.088554 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 11:08:01.091639 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 11:08:01.094979 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 11:08:01.101646 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 11:08:01.104661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4082 11:08:01.107893 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4083 11:08:01.114452 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:08:01.117972 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:08:01.121487 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:08:01.127948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:08:01.130985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:08:01.134618 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:08:01.141070 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:08:01.144497 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:08:01.147355 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:08:01.154169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 11:08:01.157414 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 11:08:01.161029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 11:08:01.167322 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 11:08:01.170567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 11:08:01.173894 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4098 11:08:01.177179 Total UI for P1: 0, mck2ui 16
4099 11:08:01.180431 best dqsien dly found for B0: ( 0, 13, 10)
4100 11:08:01.186938 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4101 11:08:01.190466 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 11:08:01.193560 Total UI for P1: 0, mck2ui 16
4103 11:08:01.197166 best dqsien dly found for B1: ( 0, 13, 16)
4104 11:08:01.200341 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4105 11:08:01.203744 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4106 11:08:01.203835
4107 11:08:01.207185 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4108 11:08:01.209977 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4109 11:08:01.213337 [Gating] SW calibration Done
4110 11:08:01.213428 ==
4111 11:08:01.216756 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 11:08:01.223366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 11:08:01.223499 ==
4114 11:08:01.223564 RX Vref Scan: 0
4115 11:08:01.223619
4116 11:08:01.226742 RX Vref 0 -> 0, step: 1
4117 11:08:01.226823
4118 11:08:01.230238 RX Delay -230 -> 252, step: 16
4119 11:08:01.233062 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4120 11:08:01.236521 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4121 11:08:01.240120 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4122 11:08:01.246745 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4123 11:08:01.249594 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4124 11:08:01.253115 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4125 11:08:01.256445 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4126 11:08:01.263421 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4127 11:08:01.266027 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4128 11:08:01.269763 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4129 11:08:01.272953 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4130 11:08:01.279898 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4131 11:08:01.282880 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4132 11:08:01.286430 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4133 11:08:01.289496 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4134 11:08:01.296138 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4135 11:08:01.296215 ==
4136 11:08:01.299468 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 11:08:01.302575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 11:08:01.302674 ==
4139 11:08:01.302759 DQS Delay:
4140 11:08:01.305960 DQS0 = 0, DQS1 = 0
4141 11:08:01.306047 DQM Delay:
4142 11:08:01.309554 DQM0 = 43, DQM1 = 29
4143 11:08:01.309617 DQ Delay:
4144 11:08:01.312677 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4145 11:08:01.315663 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4146 11:08:01.319153 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4147 11:08:01.322527 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4148 11:08:01.322625
4149 11:08:01.322708
4150 11:08:01.322787 ==
4151 11:08:01.325730 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 11:08:01.329004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 11:08:01.329075 ==
4154 11:08:01.329132
4155 11:08:01.329185
4156 11:08:01.332476 TX Vref Scan disable
4157 11:08:01.335452 == TX Byte 0 ==
4158 11:08:01.338875 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4159 11:08:01.342375 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4160 11:08:01.345596 == TX Byte 1 ==
4161 11:08:01.348923 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4162 11:08:01.352411 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4163 11:08:01.352486 ==
4164 11:08:01.355319 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 11:08:01.362253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 11:08:01.362351 ==
4167 11:08:01.362437
4168 11:08:01.362497
4169 11:08:01.365414 TX Vref Scan disable
4170 11:08:01.365520 == TX Byte 0 ==
4171 11:08:01.372110 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4172 11:08:01.375277 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4173 11:08:01.375371 == TX Byte 1 ==
4174 11:08:01.381816 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4175 11:08:01.385120 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4176 11:08:01.385212
4177 11:08:01.385294 [DATLAT]
4178 11:08:01.388724 Freq=600, CH0 RK0
4179 11:08:01.388792
4180 11:08:01.388848 DATLAT Default: 0x9
4181 11:08:01.391784 0, 0xFFFF, sum = 0
4182 11:08:01.391871 1, 0xFFFF, sum = 0
4183 11:08:01.395147 2, 0xFFFF, sum = 0
4184 11:08:01.398449 3, 0xFFFF, sum = 0
4185 11:08:01.398549 4, 0xFFFF, sum = 0
4186 11:08:01.401827 5, 0xFFFF, sum = 0
4187 11:08:01.401942 6, 0xFFFF, sum = 0
4188 11:08:01.405183 7, 0xFFFF, sum = 0
4189 11:08:01.405276 8, 0x0, sum = 1
4190 11:08:01.408292 9, 0x0, sum = 2
4191 11:08:01.408367 10, 0x0, sum = 3
4192 11:08:01.408427 11, 0x0, sum = 4
4193 11:08:01.411882 best_step = 9
4194 11:08:01.411978
4195 11:08:01.412061 ==
4196 11:08:01.414825 Dram Type= 6, Freq= 0, CH_0, rank 0
4197 11:08:01.418371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 11:08:01.418471 ==
4199 11:08:01.421397 RX Vref Scan: 1
4200 11:08:01.421494
4201 11:08:01.421579 RX Vref 0 -> 0, step: 1
4202 11:08:01.424532
4203 11:08:01.424610 RX Delay -195 -> 252, step: 8
4204 11:08:01.424668
4205 11:08:01.428035 Set Vref, RX VrefLevel [Byte0]: 60
4206 11:08:01.431177 [Byte1]: 50
4207 11:08:01.438965
4208 11:08:01.439058 Final RX Vref Byte 0 = 60 to rank0
4209 11:08:01.439320 Final RX Vref Byte 1 = 50 to rank0
4210 11:08:01.442152 Final RX Vref Byte 0 = 60 to rank1
4211 11:08:01.445617 Final RX Vref Byte 1 = 50 to rank1==
4212 11:08:01.448604 Dram Type= 6, Freq= 0, CH_0, rank 0
4213 11:08:01.455363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 11:08:01.455482 ==
4215 11:08:01.455544 DQS Delay:
4216 11:08:01.458938 DQS0 = 0, DQS1 = 0
4217 11:08:01.459037 DQM Delay:
4218 11:08:01.459124 DQM0 = 43, DQM1 = 32
4219 11:08:01.462431 DQ Delay:
4220 11:08:01.465401 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4221 11:08:01.468843 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4222 11:08:01.472317 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4223 11:08:01.475228 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4224 11:08:01.475365
4225 11:08:01.475477
4226 11:08:01.482033 [DQSOSCAuto] RK0, (LSB)MR18= 0x663d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4227 11:08:01.485347 CH0 RK0: MR19=808, MR18=663D
4228 11:08:01.492006 CH0_RK0: MR19=0x808, MR18=0x663D, DQSOSC=390, MR23=63, INC=172, DEC=114
4229 11:08:01.492082
4230 11:08:01.495159 ----->DramcWriteLeveling(PI) begin...
4231 11:08:01.495258 ==
4232 11:08:01.498378 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 11:08:01.501702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 11:08:01.501777 ==
4235 11:08:01.505135 Write leveling (Byte 0): 32 => 32
4236 11:08:01.507902 Write leveling (Byte 1): 33 => 33
4237 11:08:01.511551 DramcWriteLeveling(PI) end<-----
4238 11:08:01.511625
4239 11:08:01.511683 ==
4240 11:08:01.514650 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 11:08:01.518321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 11:08:01.521279 ==
4243 11:08:01.521366 [Gating] SW mode calibration
4244 11:08:01.531154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4245 11:08:01.534510 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4246 11:08:01.538157 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4247 11:08:01.544263 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4248 11:08:01.547714 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4249 11:08:01.551586 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4250 11:08:01.558217 0 9 16 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (0 0)
4251 11:08:01.561488 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 11:08:01.564452 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 11:08:01.571263 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 11:08:01.574883 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 11:08:01.577873 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 11:08:01.584806 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 11:08:01.587940 0 10 12 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4258 11:08:01.591241 0 10 16 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
4259 11:08:01.598204 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:08:01.600727 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 11:08:01.604368 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 11:08:01.611219 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 11:08:01.614178 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 11:08:01.617520 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 11:08:01.624111 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4266 11:08:01.627546 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:08:01.630904 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:08:01.637608 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:08:01.640506 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:08:01.644001 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:08:01.650573 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:08:01.653917 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:08:01.657221 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:08:01.663857 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:08:01.667100 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 11:08:01.670286 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:08:01.676815 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 11:08:01.680337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 11:08:01.683766 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 11:08:01.690072 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 11:08:01.693318 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4282 11:08:01.696883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4283 11:08:01.700115 Total UI for P1: 0, mck2ui 16
4284 11:08:01.703123 best dqsien dly found for B0: ( 0, 13, 12)
4285 11:08:01.709838 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 11:08:01.710235 Total UI for P1: 0, mck2ui 16
4287 11:08:01.716412 best dqsien dly found for B1: ( 0, 13, 16)
4288 11:08:01.719998 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4289 11:08:01.723282 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4290 11:08:01.723750
4291 11:08:01.726172 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4292 11:08:01.730098 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4293 11:08:01.733142 [Gating] SW calibration Done
4294 11:08:01.733535 ==
4295 11:08:01.736571 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 11:08:01.739771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 11:08:01.740167 ==
4298 11:08:01.742924 RX Vref Scan: 0
4299 11:08:01.743305
4300 11:08:01.743658 RX Vref 0 -> 0, step: 1
4301 11:08:01.745928
4302 11:08:01.746398 RX Delay -230 -> 252, step: 16
4303 11:08:01.752738 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4304 11:08:01.756241 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4305 11:08:01.759118 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4306 11:08:01.762352 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4307 11:08:01.769542 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4308 11:08:01.772696 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4309 11:08:01.775869 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4310 11:08:01.779032 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4311 11:08:01.782300 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4312 11:08:01.788955 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4313 11:08:01.792251 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4314 11:08:01.795711 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4315 11:08:01.798857 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4316 11:08:01.805829 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4317 11:08:01.808540 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4318 11:08:01.811841 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4319 11:08:01.812267 ==
4320 11:08:01.815785 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 11:08:01.821987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 11:08:01.822528 ==
4323 11:08:01.822931 DQS Delay:
4324 11:08:01.825365 DQS0 = 0, DQS1 = 0
4325 11:08:01.825760 DQM Delay:
4326 11:08:01.826060 DQM0 = 47, DQM1 = 39
4327 11:08:01.828521 DQ Delay:
4328 11:08:01.831586 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4329 11:08:01.835093 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4330 11:08:01.838477 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4331 11:08:01.841709 DQ12 =49, DQ13 =41, DQ14 =57, DQ15 =49
4332 11:08:01.842119
4333 11:08:01.842421
4334 11:08:01.842747 ==
4335 11:08:01.845268 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 11:08:01.847976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 11:08:01.848379 ==
4338 11:08:01.848771
4339 11:08:01.849137
4340 11:08:01.851404 TX Vref Scan disable
4341 11:08:01.854561 == TX Byte 0 ==
4342 11:08:01.858237 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4343 11:08:01.861097 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4344 11:08:01.864543 == TX Byte 1 ==
4345 11:08:01.867775 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4346 11:08:01.871212 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4347 11:08:01.871495 ==
4348 11:08:01.874268 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 11:08:01.877691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:08:01.880723 ==
4351 11:08:01.880887
4352 11:08:01.881013
4353 11:08:01.881132 TX Vref Scan disable
4354 11:08:01.884721 == TX Byte 0 ==
4355 11:08:01.888216 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4356 11:08:01.894585 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4357 11:08:01.894751 == TX Byte 1 ==
4358 11:08:01.898022 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4359 11:08:01.904540 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4360 11:08:01.904615
4361 11:08:01.904673 [DATLAT]
4362 11:08:01.904727 Freq=600, CH0 RK1
4363 11:08:01.904779
4364 11:08:01.907668 DATLAT Default: 0x9
4365 11:08:01.911043 0, 0xFFFF, sum = 0
4366 11:08:01.911119 1, 0xFFFF, sum = 0
4367 11:08:01.914627 2, 0xFFFF, sum = 0
4368 11:08:01.914704 3, 0xFFFF, sum = 0
4369 11:08:01.917628 4, 0xFFFF, sum = 0
4370 11:08:01.917704 5, 0xFFFF, sum = 0
4371 11:08:01.920639 6, 0xFFFF, sum = 0
4372 11:08:01.920714 7, 0xFFFF, sum = 0
4373 11:08:01.923966 8, 0x0, sum = 1
4374 11:08:01.924042 9, 0x0, sum = 2
4375 11:08:01.927296 10, 0x0, sum = 3
4376 11:08:01.927372 11, 0x0, sum = 4
4377 11:08:01.927460 best_step = 9
4378 11:08:01.927529
4379 11:08:01.930645 ==
4380 11:08:01.933866 Dram Type= 6, Freq= 0, CH_0, rank 1
4381 11:08:01.937472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 11:08:01.937547 ==
4383 11:08:01.937605 RX Vref Scan: 0
4384 11:08:01.937660
4385 11:08:01.940753 RX Vref 0 -> 0, step: 1
4386 11:08:01.940830
4387 11:08:01.944087 RX Delay -179 -> 252, step: 8
4388 11:08:01.950650 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4389 11:08:01.954110 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4390 11:08:01.957019 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4391 11:08:01.960210 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4392 11:08:01.966854 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4393 11:08:01.970345 iDelay=205, Bit 5, Center 36 (-115 ~ 188) 304
4394 11:08:01.973658 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4395 11:08:01.976658 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4396 11:08:01.980145 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4397 11:08:01.986945 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4398 11:08:01.990590 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4399 11:08:01.993421 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4400 11:08:01.996795 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4401 11:08:02.003496 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4402 11:08:02.006756 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4403 11:08:02.010443 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4404 11:08:02.010818 ==
4405 11:08:02.013735 Dram Type= 6, Freq= 0, CH_0, rank 1
4406 11:08:02.017045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 11:08:02.019792 ==
4408 11:08:02.020244 DQS Delay:
4409 11:08:02.020545 DQS0 = 0, DQS1 = 0
4410 11:08:02.023474 DQM Delay:
4411 11:08:02.023870 DQM0 = 42, DQM1 = 37
4412 11:08:02.026929 DQ Delay:
4413 11:08:02.029898 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4414 11:08:02.030274 DQ4 =44, DQ5 =36, DQ6 =48, DQ7 =52
4415 11:08:02.033437 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4416 11:08:02.036343 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4417 11:08:02.039775
4418 11:08:02.040148
4419 11:08:02.046194 [DQSOSCAuto] RK1, (LSB)MR18= 0x6519, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4420 11:08:02.049772 CH0 RK1: MR19=808, MR18=6519
4421 11:08:02.056669 CH0_RK1: MR19=0x808, MR18=0x6519, DQSOSC=390, MR23=63, INC=172, DEC=114
4422 11:08:02.059587 [RxdqsGatingPostProcess] freq 600
4423 11:08:02.063016 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4424 11:08:02.066714 Pre-setting of DQS Precalculation
4425 11:08:02.072839 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4426 11:08:02.073272 ==
4427 11:08:02.076280 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 11:08:02.079493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 11:08:02.079880 ==
4430 11:08:02.086522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4431 11:08:02.089505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4432 11:08:02.093668 [CA 0] Center 35 (5~66) winsize 62
4433 11:08:02.097439 [CA 1] Center 35 (5~66) winsize 62
4434 11:08:02.100474 [CA 2] Center 34 (4~65) winsize 62
4435 11:08:02.104052 [CA 3] Center 33 (3~64) winsize 62
4436 11:08:02.106972 [CA 4] Center 34 (4~64) winsize 61
4437 11:08:02.110396 [CA 5] Center 33 (3~64) winsize 62
4438 11:08:02.110916
4439 11:08:02.113739 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4440 11:08:02.114141
4441 11:08:02.117116 [CATrainingPosCal] consider 1 rank data
4442 11:08:02.119977 u2DelayCellTimex100 = 270/100 ps
4443 11:08:02.123639 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4444 11:08:02.129885 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 11:08:02.133247 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4446 11:08:02.136892 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4447 11:08:02.140121 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4448 11:08:02.143045 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4449 11:08:02.143422
4450 11:08:02.146159 CA PerBit enable=1, Macro0, CA PI delay=33
4451 11:08:02.146537
4452 11:08:02.149714 [CBTSetCACLKResult] CA Dly = 33
4453 11:08:02.153238 CS Dly: 5 (0~36)
4454 11:08:02.153787 ==
4455 11:08:02.156394 Dram Type= 6, Freq= 0, CH_1, rank 1
4456 11:08:02.159660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 11:08:02.160047 ==
4458 11:08:02.166302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4459 11:08:02.169843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4460 11:08:02.174166 [CA 0] Center 35 (5~66) winsize 62
4461 11:08:02.177558 [CA 1] Center 36 (6~66) winsize 61
4462 11:08:02.180797 [CA 2] Center 34 (4~65) winsize 62
4463 11:08:02.183979 [CA 3] Center 33 (3~64) winsize 62
4464 11:08:02.187559 [CA 4] Center 34 (3~65) winsize 63
4465 11:08:02.190166 [CA 5] Center 34 (3~65) winsize 63
4466 11:08:02.190551
4467 11:08:02.193545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4468 11:08:02.193933
4469 11:08:02.197136 [CATrainingPosCal] consider 2 rank data
4470 11:08:02.200109 u2DelayCellTimex100 = 270/100 ps
4471 11:08:02.203654 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4472 11:08:02.209996 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4473 11:08:02.213780 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4474 11:08:02.216855 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4475 11:08:02.220121 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4476 11:08:02.223141 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4477 11:08:02.223561
4478 11:08:02.226415 CA PerBit enable=1, Macro0, CA PI delay=33
4479 11:08:02.226795
4480 11:08:02.230377 [CBTSetCACLKResult] CA Dly = 33
4481 11:08:02.233038 CS Dly: 5 (0~37)
4482 11:08:02.233137
4483 11:08:02.236229 ----->DramcWriteLeveling(PI) begin...
4484 11:08:02.236304 ==
4485 11:08:02.239613 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 11:08:02.243304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 11:08:02.243378 ==
4488 11:08:02.246439 Write leveling (Byte 0): 31 => 31
4489 11:08:02.249501 Write leveling (Byte 1): 31 => 31
4490 11:08:02.253052 DramcWriteLeveling(PI) end<-----
4491 11:08:02.253126
4492 11:08:02.253184 ==
4493 11:08:02.255871 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 11:08:02.259303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 11:08:02.259379 ==
4496 11:08:02.262910 [Gating] SW mode calibration
4497 11:08:02.269165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4498 11:08:02.275779 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4499 11:08:02.279332 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4500 11:08:02.282230 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 11:08:02.288740 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 11:08:02.292449 0 9 12 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (1 1)
4503 11:08:02.295360 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:08:02.302093 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 11:08:02.305564 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 11:08:02.308970 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 11:08:02.315375 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 11:08:02.318941 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 11:08:02.321768 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4510 11:08:02.328786 0 10 12 | B1->B0 | 3838 4040 | 0 0 | (0 0) (0 0)
4511 11:08:02.331671 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:08:02.335066 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:08:02.341721 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 11:08:02.344631 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 11:08:02.347968 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 11:08:02.354898 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 11:08:02.358334 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 11:08:02.361111 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4519 11:08:02.368104 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:08:02.371335 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:08:02.374823 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:08:02.381602 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:08:02.384500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:08:02.387826 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:08:02.394548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:08:02.397712 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:08:02.401170 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:08:02.407576 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 11:08:02.410898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 11:08:02.414213 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 11:08:02.421122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 11:08:02.424596 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 11:08:02.427435 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 11:08:02.434208 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4535 11:08:02.437803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 11:08:02.441366 Total UI for P1: 0, mck2ui 16
4537 11:08:02.444115 best dqsien dly found for B0: ( 0, 13, 12)
4538 11:08:02.447765 Total UI for P1: 0, mck2ui 16
4539 11:08:02.450949 best dqsien dly found for B1: ( 0, 13, 14)
4540 11:08:02.453992 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4541 11:08:02.457549 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4542 11:08:02.457689
4543 11:08:02.461014 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4544 11:08:02.464019 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4545 11:08:02.467593 [Gating] SW calibration Done
4546 11:08:02.467774 ==
4547 11:08:02.470422 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 11:08:02.477369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 11:08:02.477642 ==
4550 11:08:02.477856 RX Vref Scan: 0
4551 11:08:02.478054
4552 11:08:02.480833 RX Vref 0 -> 0, step: 1
4553 11:08:02.481188
4554 11:08:02.484550 RX Delay -230 -> 252, step: 16
4555 11:08:02.487175 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4556 11:08:02.490957 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4557 11:08:02.493957 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4558 11:08:02.500740 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4559 11:08:02.504101 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4560 11:08:02.507492 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4561 11:08:02.510622 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4562 11:08:02.517141 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4563 11:08:02.520661 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4564 11:08:02.523990 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4565 11:08:02.526902 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4566 11:08:02.533674 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4567 11:08:02.537116 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4568 11:08:02.539952 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4569 11:08:02.543531 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4570 11:08:02.550443 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4571 11:08:02.550832 ==
4572 11:08:02.553646 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 11:08:02.556836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 11:08:02.557223 ==
4575 11:08:02.557525 DQS Delay:
4576 11:08:02.559921 DQS0 = 0, DQS1 = 0
4577 11:08:02.560306 DQM Delay:
4578 11:08:02.563396 DQM0 = 41, DQM1 = 35
4579 11:08:02.563828 DQ Delay:
4580 11:08:02.566731 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4581 11:08:02.569963 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4582 11:08:02.573643 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4583 11:08:02.576612 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4584 11:08:02.576999
4585 11:08:02.577296
4586 11:08:02.577574 ==
4587 11:08:02.579911 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 11:08:02.583206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:08:02.583664 ==
4590 11:08:02.583973
4591 11:08:02.584247
4592 11:08:02.586601 TX Vref Scan disable
4593 11:08:02.590375 == TX Byte 0 ==
4594 11:08:02.593539 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4595 11:08:02.596808 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4596 11:08:02.599953 == TX Byte 1 ==
4597 11:08:02.603171 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4598 11:08:02.606509 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4599 11:08:02.606896 ==
4600 11:08:02.609878 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 11:08:02.616265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 11:08:02.616655 ==
4603 11:08:02.616952
4604 11:08:02.617230
4605 11:08:02.617495 TX Vref Scan disable
4606 11:08:02.621206 == TX Byte 0 ==
4607 11:08:02.624162 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4608 11:08:02.630814 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4609 11:08:02.631204 == TX Byte 1 ==
4610 11:08:02.634280 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4611 11:08:02.640435 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4612 11:08:02.640822
4613 11:08:02.641180 [DATLAT]
4614 11:08:02.641466 Freq=600, CH1 RK0
4615 11:08:02.641740
4616 11:08:02.643864 DATLAT Default: 0x9
4617 11:08:02.644249 0, 0xFFFF, sum = 0
4618 11:08:02.647482 1, 0xFFFF, sum = 0
4619 11:08:02.650292 2, 0xFFFF, sum = 0
4620 11:08:02.650691 3, 0xFFFF, sum = 0
4621 11:08:02.653731 4, 0xFFFF, sum = 0
4622 11:08:02.654157 5, 0xFFFF, sum = 0
4623 11:08:02.657059 6, 0xFFFF, sum = 0
4624 11:08:02.657454 7, 0xFFFF, sum = 0
4625 11:08:02.660698 8, 0x0, sum = 1
4626 11:08:02.661112 9, 0x0, sum = 2
4627 11:08:02.661542 10, 0x0, sum = 3
4628 11:08:02.663722 11, 0x0, sum = 4
4629 11:08:02.664121 best_step = 9
4630 11:08:02.664424
4631 11:08:02.664700 ==
4632 11:08:02.667526 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 11:08:02.673974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 11:08:02.674364 ==
4635 11:08:02.674668 RX Vref Scan: 1
4636 11:08:02.674945
4637 11:08:02.676777 RX Vref 0 -> 0, step: 1
4638 11:08:02.677170
4639 11:08:02.680198 RX Delay -179 -> 252, step: 8
4640 11:08:02.680587
4641 11:08:02.684040 Set Vref, RX VrefLevel [Byte0]: 50
4642 11:08:02.686966 [Byte1]: 61
4643 11:08:02.687350
4644 11:08:02.690237 Final RX Vref Byte 0 = 50 to rank0
4645 11:08:02.693162 Final RX Vref Byte 1 = 61 to rank0
4646 11:08:02.696896 Final RX Vref Byte 0 = 50 to rank1
4647 11:08:02.699743 Final RX Vref Byte 1 = 61 to rank1==
4648 11:08:02.703335 Dram Type= 6, Freq= 0, CH_1, rank 0
4649 11:08:02.706701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 11:08:02.710141 ==
4651 11:08:02.710533 DQS Delay:
4652 11:08:02.710837 DQS0 = 0, DQS1 = 0
4653 11:08:02.713214 DQM Delay:
4654 11:08:02.713597 DQM0 = 45, DQM1 = 34
4655 11:08:02.713900 DQ Delay:
4656 11:08:02.716340 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4657 11:08:02.720025 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =40
4658 11:08:02.723211 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4659 11:08:02.726793 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4660 11:08:02.727290
4661 11:08:02.727695
4662 11:08:02.736750 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d32, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4663 11:08:02.739854 CH1 RK0: MR19=808, MR18=4D32
4664 11:08:02.746556 CH1_RK0: MR19=0x808, MR18=0x4D32, DQSOSC=395, MR23=63, INC=168, DEC=112
4665 11:08:02.746941
4666 11:08:02.749488 ----->DramcWriteLeveling(PI) begin...
4667 11:08:02.749879 ==
4668 11:08:02.752826 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 11:08:02.756162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 11:08:02.756551 ==
4671 11:08:02.759456 Write leveling (Byte 0): 29 => 29
4672 11:08:02.762842 Write leveling (Byte 1): 31 => 31
4673 11:08:02.765734 DramcWriteLeveling(PI) end<-----
4674 11:08:02.766117
4675 11:08:02.766415 ==
4676 11:08:02.769584 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 11:08:02.772950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 11:08:02.773333 ==
4679 11:08:02.776096 [Gating] SW mode calibration
4680 11:08:02.782808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4681 11:08:02.789117 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4682 11:08:02.792905 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4683 11:08:02.796033 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4684 11:08:02.802671 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 11:08:02.805933 0 9 12 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 0)
4686 11:08:02.808951 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 11:08:02.815514 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 11:08:02.818879 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 11:08:02.822198 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 11:08:02.829075 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 11:08:02.832222 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 11:08:02.835585 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 11:08:02.842163 0 10 12 | B1->B0 | 3535 2c2c | 0 0 | (0 0) (0 0)
4694 11:08:02.845287 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:08:02.848792 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 11:08:02.855089 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 11:08:02.858577 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 11:08:02.862080 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 11:08:02.868503 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 11:08:02.872001 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 11:08:02.875082 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4702 11:08:02.881771 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:08:02.884699 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:08:02.888148 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:08:02.894511 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:08:02.897915 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:08:02.901333 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:08:02.908062 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:08:02.911459 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:08:02.914616 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:08:02.921530 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 11:08:02.924387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 11:08:02.927970 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 11:08:02.934487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 11:08:02.938017 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 11:08:02.941166 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4717 11:08:02.947997 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4718 11:08:02.950724 Total UI for P1: 0, mck2ui 16
4719 11:08:02.954444 best dqsien dly found for B1: ( 0, 13, 10)
4720 11:08:02.957525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 11:08:02.960944 Total UI for P1: 0, mck2ui 16
4722 11:08:02.964232 best dqsien dly found for B0: ( 0, 13, 10)
4723 11:08:02.967671 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4724 11:08:02.970632 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4725 11:08:02.971053
4726 11:08:02.974105 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4727 11:08:02.981139 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4728 11:08:02.981679 [Gating] SW calibration Done
4729 11:08:02.982165 ==
4730 11:08:02.984250 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 11:08:02.990524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 11:08:02.991186 ==
4733 11:08:02.991757 RX Vref Scan: 0
4734 11:08:02.992247
4735 11:08:02.994011 RX Vref 0 -> 0, step: 1
4736 11:08:02.994539
4737 11:08:02.997022 RX Delay -230 -> 252, step: 16
4738 11:08:03.000289 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4739 11:08:03.004026 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4740 11:08:03.007219 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4741 11:08:03.013674 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4742 11:08:03.017018 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4743 11:08:03.020487 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4744 11:08:03.023797 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4745 11:08:03.030324 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4746 11:08:03.033828 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4747 11:08:03.036795 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4748 11:08:03.040347 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4749 11:08:03.046689 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4750 11:08:03.050282 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4751 11:08:03.053600 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4752 11:08:03.056910 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4753 11:08:03.063232 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4754 11:08:03.063712 ==
4755 11:08:03.066901 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 11:08:03.069955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 11:08:03.070389 ==
4758 11:08:03.070811 DQS Delay:
4759 11:08:03.073104 DQS0 = 0, DQS1 = 0
4760 11:08:03.073492 DQM Delay:
4761 11:08:03.076571 DQM0 = 39, DQM1 = 36
4762 11:08:03.076954 DQ Delay:
4763 11:08:03.079906 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4764 11:08:03.083269 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4765 11:08:03.086441 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4766 11:08:03.089732 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4767 11:08:03.090135
4768 11:08:03.090436
4769 11:08:03.090713 ==
4770 11:08:03.093319 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 11:08:03.096304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 11:08:03.096758 ==
4773 11:08:03.099858
4774 11:08:03.100244
4775 11:08:03.100582 TX Vref Scan disable
4776 11:08:03.103320 == TX Byte 0 ==
4777 11:08:03.106009 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4778 11:08:03.109635 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4779 11:08:03.112918 == TX Byte 1 ==
4780 11:08:03.116112 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4781 11:08:03.119596 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4782 11:08:03.122941 ==
4783 11:08:03.123325 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 11:08:03.129122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 11:08:03.129714 ==
4786 11:08:03.130163
4787 11:08:03.130607
4788 11:08:03.132710 TX Vref Scan disable
4789 11:08:03.133105 == TX Byte 0 ==
4790 11:08:03.139253 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4791 11:08:03.142672 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4792 11:08:03.143060 == TX Byte 1 ==
4793 11:08:03.148868 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4794 11:08:03.152182 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4795 11:08:03.152778
4796 11:08:03.153219 [DATLAT]
4797 11:08:03.155647 Freq=600, CH1 RK1
4798 11:08:03.156205
4799 11:08:03.156678 DATLAT Default: 0x9
4800 11:08:03.158881 0, 0xFFFF, sum = 0
4801 11:08:03.161954 1, 0xFFFF, sum = 0
4802 11:08:03.162567 2, 0xFFFF, sum = 0
4803 11:08:03.165715 3, 0xFFFF, sum = 0
4804 11:08:03.166103 4, 0xFFFF, sum = 0
4805 11:08:03.169161 5, 0xFFFF, sum = 0
4806 11:08:03.169553 6, 0xFFFF, sum = 0
4807 11:08:03.172077 7, 0xFFFF, sum = 0
4808 11:08:03.172494 8, 0x0, sum = 1
4809 11:08:03.175482 9, 0x0, sum = 2
4810 11:08:03.175887 10, 0x0, sum = 3
4811 11:08:03.176185 11, 0x0, sum = 4
4812 11:08:03.178923 best_step = 9
4813 11:08:03.179306
4814 11:08:03.179662 ==
4815 11:08:03.182014 Dram Type= 6, Freq= 0, CH_1, rank 1
4816 11:08:03.185588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4817 11:08:03.185974 ==
4818 11:08:03.188881 RX Vref Scan: 0
4819 11:08:03.189430
4820 11:08:03.189756 RX Vref 0 -> 0, step: 1
4821 11:08:03.192024
4822 11:08:03.192407 RX Delay -195 -> 252, step: 8
4823 11:08:03.199490 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4824 11:08:03.202653 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4825 11:08:03.206179 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4826 11:08:03.209394 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4827 11:08:03.216086 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4828 11:08:03.219194 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4829 11:08:03.222499 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4830 11:08:03.225570 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4831 11:08:03.232508 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4832 11:08:03.235789 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4833 11:08:03.238996 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4834 11:08:03.242264 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4835 11:08:03.248618 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4836 11:08:03.252289 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4837 11:08:03.255288 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4838 11:08:03.258604 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4839 11:08:03.259053 ==
4840 11:08:03.261886 Dram Type= 6, Freq= 0, CH_1, rank 1
4841 11:08:03.268199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4842 11:08:03.268583 ==
4843 11:08:03.269001 DQS Delay:
4844 11:08:03.271754 DQS0 = 0, DQS1 = 0
4845 11:08:03.272137 DQM Delay:
4846 11:08:03.275137 DQM0 = 42, DQM1 = 34
4847 11:08:03.275561 DQ Delay:
4848 11:08:03.278482 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4849 11:08:03.281500 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4850 11:08:03.284811 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4851 11:08:03.288233 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4852 11:08:03.288617
4853 11:08:03.288917
4854 11:08:03.294749 [DQSOSCAuto] RK1, (LSB)MR18= 0x3126, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4855 11:08:03.297886 CH1 RK1: MR19=808, MR18=3126
4856 11:08:03.304613 CH1_RK1: MR19=0x808, MR18=0x3126, DQSOSC=400, MR23=63, INC=163, DEC=109
4857 11:08:03.307852 [RxdqsGatingPostProcess] freq 600
4858 11:08:03.315184 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4859 11:08:03.315674 Pre-setting of DQS Precalculation
4860 11:08:03.321112 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4861 11:08:03.327983 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4862 11:08:03.334481 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4863 11:08:03.334866
4864 11:08:03.335212
4865 11:08:03.337977 [Calibration Summary] 1200 Mbps
4866 11:08:03.341271 CH 0, Rank 0
4867 11:08:03.341656 SW Impedance : PASS
4868 11:08:03.344397 DUTY Scan : NO K
4869 11:08:03.347969 ZQ Calibration : PASS
4870 11:08:03.348355 Jitter Meter : NO K
4871 11:08:03.350890 CBT Training : PASS
4872 11:08:03.354383 Write leveling : PASS
4873 11:08:03.354773 RX DQS gating : PASS
4874 11:08:03.357570 RX DQ/DQS(RDDQC) : PASS
4875 11:08:03.357978 TX DQ/DQS : PASS
4876 11:08:03.360860 RX DATLAT : PASS
4877 11:08:03.363940 RX DQ/DQS(Engine): PASS
4878 11:08:03.364324 TX OE : NO K
4879 11:08:03.367304 All Pass.
4880 11:08:03.367723
4881 11:08:03.368025 CH 0, Rank 1
4882 11:08:03.370895 SW Impedance : PASS
4883 11:08:03.371275 DUTY Scan : NO K
4884 11:08:03.373797 ZQ Calibration : PASS
4885 11:08:03.377576 Jitter Meter : NO K
4886 11:08:03.377955 CBT Training : PASS
4887 11:08:03.380835 Write leveling : PASS
4888 11:08:03.383977 RX DQS gating : PASS
4889 11:08:03.384358 RX DQ/DQS(RDDQC) : PASS
4890 11:08:03.387424 TX DQ/DQS : PASS
4891 11:08:03.390512 RX DATLAT : PASS
4892 11:08:03.390901 RX DQ/DQS(Engine): PASS
4893 11:08:03.393915 TX OE : NO K
4894 11:08:03.394311 All Pass.
4895 11:08:03.394702
4896 11:08:03.397509 CH 1, Rank 0
4897 11:08:03.397904 SW Impedance : PASS
4898 11:08:03.400455 DUTY Scan : NO K
4899 11:08:03.403962 ZQ Calibration : PASS
4900 11:08:03.404353 Jitter Meter : NO K
4901 11:08:03.407374 CBT Training : PASS
4902 11:08:03.410630 Write leveling : PASS
4903 11:08:03.411016 RX DQS gating : PASS
4904 11:08:03.413719 RX DQ/DQS(RDDQC) : PASS
4905 11:08:03.416885 TX DQ/DQS : PASS
4906 11:08:03.417275 RX DATLAT : PASS
4907 11:08:03.420364 RX DQ/DQS(Engine): PASS
4908 11:08:03.420750 TX OE : NO K
4909 11:08:03.423953 All Pass.
4910 11:08:03.424395
4911 11:08:03.424944 CH 1, Rank 1
4912 11:08:03.426554 SW Impedance : PASS
4913 11:08:03.430033 DUTY Scan : NO K
4914 11:08:03.430420 ZQ Calibration : PASS
4915 11:08:03.433421 Jitter Meter : NO K
4916 11:08:03.436748 CBT Training : PASS
4917 11:08:03.437134 Write leveling : PASS
4918 11:08:03.439967 RX DQS gating : PASS
4919 11:08:03.440502 RX DQ/DQS(RDDQC) : PASS
4920 11:08:03.443179 TX DQ/DQS : PASS
4921 11:08:03.447015 RX DATLAT : PASS
4922 11:08:03.447401 RX DQ/DQS(Engine): PASS
4923 11:08:03.450002 TX OE : NO K
4924 11:08:03.450386 All Pass.
4925 11:08:03.450683
4926 11:08:03.453172 DramC Write-DBI off
4927 11:08:03.456668 PER_BANK_REFRESH: Hybrid Mode
4928 11:08:03.457237 TX_TRACKING: ON
4929 11:08:03.466440 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4930 11:08:03.469836 [FAST_K] Save calibration result to emmc
4931 11:08:03.472935 dramc_set_vcore_voltage set vcore to 662500
4932 11:08:03.476366 Read voltage for 933, 3
4933 11:08:03.476748 Vio18 = 0
4934 11:08:03.477046 Vcore = 662500
4935 11:08:03.479858 Vdram = 0
4936 11:08:03.480388 Vddq = 0
4937 11:08:03.480777 Vmddr = 0
4938 11:08:03.486015 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4939 11:08:03.489717 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4940 11:08:03.492781 MEM_TYPE=3, freq_sel=17
4941 11:08:03.495934 sv_algorithm_assistance_LP4_1600
4942 11:08:03.499415 ============ PULL DRAM RESETB DOWN ============
4943 11:08:03.506052 ========== PULL DRAM RESETB DOWN end =========
4944 11:08:03.509764 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4945 11:08:03.512762 ===================================
4946 11:08:03.515947 LPDDR4 DRAM CONFIGURATION
4947 11:08:03.519530 ===================================
4948 11:08:03.519931 EX_ROW_EN[0] = 0x0
4949 11:08:03.522463 EX_ROW_EN[1] = 0x0
4950 11:08:03.522870 LP4Y_EN = 0x0
4951 11:08:03.525792 WORK_FSP = 0x0
4952 11:08:03.526327 WL = 0x3
4953 11:08:03.529300 RL = 0x3
4954 11:08:03.532559 BL = 0x2
4955 11:08:03.533081 RPST = 0x0
4956 11:08:03.535685 RD_PRE = 0x0
4957 11:08:03.536072 WR_PRE = 0x1
4958 11:08:03.539228 WR_PST = 0x0
4959 11:08:03.539657 DBI_WR = 0x0
4960 11:08:03.542603 DBI_RD = 0x0
4961 11:08:03.542991 OTF = 0x1
4962 11:08:03.545743 ===================================
4963 11:08:03.548654 ===================================
4964 11:08:03.551958 ANA top config
4965 11:08:03.555276 ===================================
4966 11:08:03.555745 DLL_ASYNC_EN = 0
4967 11:08:03.558513 ALL_SLAVE_EN = 1
4968 11:08:03.562051 NEW_RANK_MODE = 1
4969 11:08:03.565522 DLL_IDLE_MODE = 1
4970 11:08:03.565902 LP45_APHY_COMB_EN = 1
4971 11:08:03.568945 TX_ODT_DIS = 1
4972 11:08:03.572021 NEW_8X_MODE = 1
4973 11:08:03.575298 ===================================
4974 11:08:03.579219 ===================================
4975 11:08:03.581931 data_rate = 1866
4976 11:08:03.585734 CKR = 1
4977 11:08:03.588372 DQ_P2S_RATIO = 8
4978 11:08:03.591831 ===================================
4979 11:08:03.592221 CA_P2S_RATIO = 8
4980 11:08:03.595136 DQ_CA_OPEN = 0
4981 11:08:03.598758 DQ_SEMI_OPEN = 0
4982 11:08:03.602142 CA_SEMI_OPEN = 0
4983 11:08:03.605383 CA_FULL_RATE = 0
4984 11:08:03.608292 DQ_CKDIV4_EN = 1
4985 11:08:03.608794 CA_CKDIV4_EN = 1
4986 11:08:03.611781 CA_PREDIV_EN = 0
4987 11:08:03.615216 PH8_DLY = 0
4988 11:08:03.618068 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4989 11:08:03.621569 DQ_AAMCK_DIV = 4
4990 11:08:03.625074 CA_AAMCK_DIV = 4
4991 11:08:03.625454 CA_ADMCK_DIV = 4
4992 11:08:03.628531 DQ_TRACK_CA_EN = 0
4993 11:08:03.631813 CA_PICK = 933
4994 11:08:03.635016 CA_MCKIO = 933
4995 11:08:03.638121 MCKIO_SEMI = 0
4996 11:08:03.641475 PLL_FREQ = 3732
4997 11:08:03.644578 DQ_UI_PI_RATIO = 32
4998 11:08:03.644961 CA_UI_PI_RATIO = 0
4999 11:08:03.647955 ===================================
5000 11:08:03.650909 ===================================
5001 11:08:03.654481 memory_type:LPDDR4
5002 11:08:03.657812 GP_NUM : 10
5003 11:08:03.658192 SRAM_EN : 1
5004 11:08:03.661417 MD32_EN : 0
5005 11:08:03.664407 ===================================
5006 11:08:03.667880 [ANA_INIT] >>>>>>>>>>>>>>
5007 11:08:03.670778 <<<<<< [CONFIGURE PHASE]: ANA_TX
5008 11:08:03.674315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5009 11:08:03.677308 ===================================
5010 11:08:03.681023 data_rate = 1866,PCW = 0X8f00
5011 11:08:03.684016 ===================================
5012 11:08:03.687354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5013 11:08:03.690823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5014 11:08:03.697461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5015 11:08:03.700601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5016 11:08:03.703814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5017 11:08:03.707348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5018 11:08:03.710705 [ANA_INIT] flow start
5019 11:08:03.713862 [ANA_INIT] PLL >>>>>>>>
5020 11:08:03.714306 [ANA_INIT] PLL <<<<<<<<
5021 11:08:03.717092 [ANA_INIT] MIDPI >>>>>>>>
5022 11:08:03.720382 [ANA_INIT] MIDPI <<<<<<<<
5023 11:08:03.723993 [ANA_INIT] DLL >>>>>>>>
5024 11:08:03.724380 [ANA_INIT] flow end
5025 11:08:03.727234 ============ LP4 DIFF to SE enter ============
5026 11:08:03.733346 ============ LP4 DIFF to SE exit ============
5027 11:08:03.733737 [ANA_INIT] <<<<<<<<<<<<<
5028 11:08:03.736814 [Flow] Enable top DCM control >>>>>
5029 11:08:03.740169 [Flow] Enable top DCM control <<<<<
5030 11:08:03.743207 Enable DLL master slave shuffle
5031 11:08:03.749996 ==============================================================
5032 11:08:03.750384 Gating Mode config
5033 11:08:03.756788 ==============================================================
5034 11:08:03.759715 Config description:
5035 11:08:03.769676 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5036 11:08:03.776171 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5037 11:08:03.779470 SELPH_MODE 0: By rank 1: By Phase
5038 11:08:03.785912 ==============================================================
5039 11:08:03.789674 GAT_TRACK_EN = 1
5040 11:08:03.793134 RX_GATING_MODE = 2
5041 11:08:03.795945 RX_GATING_TRACK_MODE = 2
5042 11:08:03.796283 SELPH_MODE = 1
5043 11:08:03.800027 PICG_EARLY_EN = 1
5044 11:08:03.802758 VALID_LAT_VALUE = 1
5045 11:08:03.809446 ==============================================================
5046 11:08:03.812775 Enter into Gating configuration >>>>
5047 11:08:03.815770 Exit from Gating configuration <<<<
5048 11:08:03.819298 Enter into DVFS_PRE_config >>>>>
5049 11:08:03.828865 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5050 11:08:03.832922 Exit from DVFS_PRE_config <<<<<
5051 11:08:03.835804 Enter into PICG configuration >>>>
5052 11:08:03.839258 Exit from PICG configuration <<<<
5053 11:08:03.842640 [RX_INPUT] configuration >>>>>
5054 11:08:03.845466 [RX_INPUT] configuration <<<<<
5055 11:08:03.849197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5056 11:08:03.855655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5057 11:08:03.862196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5058 11:08:03.868694 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5059 11:08:03.875326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5060 11:08:03.881703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5061 11:08:03.885468 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5062 11:08:03.888261 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5063 11:08:03.891922 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5064 11:08:03.895010 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5065 11:08:03.901781 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5066 11:08:03.904655 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5067 11:08:03.908409 ===================================
5068 11:08:03.911774 LPDDR4 DRAM CONFIGURATION
5069 11:08:03.915053 ===================================
5070 11:08:03.915503 EX_ROW_EN[0] = 0x0
5071 11:08:03.918429 EX_ROW_EN[1] = 0x0
5072 11:08:03.918810 LP4Y_EN = 0x0
5073 11:08:03.921522 WORK_FSP = 0x0
5074 11:08:03.921905 WL = 0x3
5075 11:08:03.924646 RL = 0x3
5076 11:08:03.928059 BL = 0x2
5077 11:08:03.928443 RPST = 0x0
5078 11:08:03.931374 RD_PRE = 0x0
5079 11:08:03.931980 WR_PRE = 0x1
5080 11:08:03.934827 WR_PST = 0x0
5081 11:08:03.935459 DBI_WR = 0x0
5082 11:08:03.938079 DBI_RD = 0x0
5083 11:08:03.938464 OTF = 0x1
5084 11:08:03.941719 ===================================
5085 11:08:03.944447 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5086 11:08:03.951167 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5087 11:08:03.954785 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5088 11:08:03.957594 ===================================
5089 11:08:03.961034 LPDDR4 DRAM CONFIGURATION
5090 11:08:03.964325 ===================================
5091 11:08:03.964711 EX_ROW_EN[0] = 0x10
5092 11:08:03.967820 EX_ROW_EN[1] = 0x0
5093 11:08:03.968202 LP4Y_EN = 0x0
5094 11:08:03.970720 WORK_FSP = 0x0
5095 11:08:03.974260 WL = 0x3
5096 11:08:03.974672 RL = 0x3
5097 11:08:03.977319 BL = 0x2
5098 11:08:03.977698 RPST = 0x0
5099 11:08:03.980712 RD_PRE = 0x0
5100 11:08:03.981099 WR_PRE = 0x1
5101 11:08:03.984199 WR_PST = 0x0
5102 11:08:03.984580 DBI_WR = 0x0
5103 11:08:03.987546 DBI_RD = 0x0
5104 11:08:03.987946 OTF = 0x1
5105 11:08:03.990667 ===================================
5106 11:08:03.997305 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5107 11:08:04.001943 nWR fixed to 30
5108 11:08:04.004846 [ModeRegInit_LP4] CH0 RK0
5109 11:08:04.005252 [ModeRegInit_LP4] CH0 RK1
5110 11:08:04.007947 [ModeRegInit_LP4] CH1 RK0
5111 11:08:04.011272 [ModeRegInit_LP4] CH1 RK1
5112 11:08:04.011700 match AC timing 9
5113 11:08:04.017843 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5114 11:08:04.021275 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5115 11:08:04.024442 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5116 11:08:04.031091 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5117 11:08:04.034539 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5118 11:08:04.034924 ==
5119 11:08:04.037656 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 11:08:04.040751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 11:08:04.044345 ==
5122 11:08:04.047773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5123 11:08:04.053920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5124 11:08:04.056874 [CA 0] Center 37 (7~68) winsize 62
5125 11:08:04.060216 [CA 1] Center 37 (7~68) winsize 62
5126 11:08:04.063504 [CA 2] Center 34 (4~65) winsize 62
5127 11:08:04.066970 [CA 3] Center 35 (5~65) winsize 61
5128 11:08:04.070775 [CA 4] Center 33 (3~64) winsize 62
5129 11:08:04.073495 [CA 5] Center 33 (4~63) winsize 60
5130 11:08:04.073575
5131 11:08:04.076897 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5132 11:08:04.076984
5133 11:08:04.080281 [CATrainingPosCal] consider 1 rank data
5134 11:08:04.083758 u2DelayCellTimex100 = 270/100 ps
5135 11:08:04.086869 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5136 11:08:04.090196 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5137 11:08:04.093608 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5138 11:08:04.100234 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5139 11:08:04.103065 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5140 11:08:04.106655 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5141 11:08:04.106812
5142 11:08:04.110065 CA PerBit enable=1, Macro0, CA PI delay=33
5143 11:08:04.110223
5144 11:08:04.113441 [CBTSetCACLKResult] CA Dly = 33
5145 11:08:04.113625 CS Dly: 7 (0~38)
5146 11:08:04.113771 ==
5147 11:08:04.116307 Dram Type= 6, Freq= 0, CH_0, rank 1
5148 11:08:04.122957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 11:08:04.123366 ==
5150 11:08:04.126081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5151 11:08:04.132588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5152 11:08:04.136047 [CA 0] Center 37 (7~68) winsize 62
5153 11:08:04.139472 [CA 1] Center 37 (7~68) winsize 62
5154 11:08:04.142698 [CA 2] Center 34 (4~65) winsize 62
5155 11:08:04.145819 [CA 3] Center 34 (4~65) winsize 62
5156 11:08:04.149689 [CA 4] Center 33 (3~64) winsize 62
5157 11:08:04.152373 [CA 5] Center 33 (3~63) winsize 61
5158 11:08:04.152448
5159 11:08:04.155880 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5160 11:08:04.155955
5161 11:08:04.159244 [CATrainingPosCal] consider 2 rank data
5162 11:08:04.162888 u2DelayCellTimex100 = 270/100 ps
5163 11:08:04.165795 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5164 11:08:04.172419 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5165 11:08:04.175763 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5166 11:08:04.178883 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5167 11:08:04.181935 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5168 11:08:04.185377 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5169 11:08:04.185451
5170 11:08:04.188933 CA PerBit enable=1, Macro0, CA PI delay=33
5171 11:08:04.189008
5172 11:08:04.191960 [CBTSetCACLKResult] CA Dly = 33
5173 11:08:04.195348 CS Dly: 7 (0~39)
5174 11:08:04.195481
5175 11:08:04.198754 ----->DramcWriteLeveling(PI) begin...
5176 11:08:04.198831 ==
5177 11:08:04.202066 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 11:08:04.205383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 11:08:04.205460 ==
5180 11:08:04.208670 Write leveling (Byte 0): 30 => 30
5181 11:08:04.211672 Write leveling (Byte 1): 30 => 30
5182 11:08:04.215112 DramcWriteLeveling(PI) end<-----
5183 11:08:04.215209
5184 11:08:04.215327 ==
5185 11:08:04.218552 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 11:08:04.222084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 11:08:04.222160 ==
5188 11:08:04.224985 [Gating] SW mode calibration
5189 11:08:04.231664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5190 11:08:04.238727 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5191 11:08:04.241864 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5192 11:08:04.244976 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5193 11:08:04.251386 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 11:08:04.254845 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 11:08:04.258168 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 11:08:04.264657 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 11:08:04.268219 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 11:08:04.271461 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
5199 11:08:04.278112 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
5200 11:08:04.281597 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 11:08:04.284530 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 11:08:04.291298 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 11:08:04.294188 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 11:08:04.297703 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 11:08:04.304268 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 11:08:04.307670 0 15 28 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5207 11:08:04.311134 1 0 0 | B1->B0 | 2f2f 4343 | 0 0 | (1 1) (0 0)
5208 11:08:04.317375 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 11:08:04.320776 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 11:08:04.324139 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 11:08:04.330653 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 11:08:04.334153 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 11:08:04.340462 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 11:08:04.343912 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5215 11:08:04.347218 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5216 11:08:04.350408 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:08:04.357241 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:08:04.360034 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:08:04.363724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:08:04.369963 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:08:04.373654 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:08:04.376970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:08:04.383727 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:08:04.386650 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 11:08:04.390055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 11:08:04.396546 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 11:08:04.399947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 11:08:04.403380 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 11:08:04.409673 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 11:08:04.413180 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5231 11:08:04.416439 Total UI for P1: 0, mck2ui 16
5232 11:08:04.420013 best dqsien dly found for B0: ( 1, 2, 26)
5233 11:08:04.423168 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5234 11:08:04.429655 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 11:08:04.432720 Total UI for P1: 0, mck2ui 16
5236 11:08:04.436194 best dqsien dly found for B1: ( 1, 2, 30)
5237 11:08:04.439104 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5238 11:08:04.442692 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5239 11:08:04.442769
5240 11:08:04.446306 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5241 11:08:04.449546 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5242 11:08:04.452672 [Gating] SW calibration Done
5243 11:08:04.452749 ==
5244 11:08:04.455858 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 11:08:04.459068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 11:08:04.459174 ==
5247 11:08:04.462395 RX Vref Scan: 0
5248 11:08:04.462471
5249 11:08:04.466042 RX Vref 0 -> 0, step: 1
5250 11:08:04.466120
5251 11:08:04.466181 RX Delay -80 -> 252, step: 8
5252 11:08:04.472947 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5253 11:08:04.475731 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5254 11:08:04.478857 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5255 11:08:04.482329 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5256 11:08:04.485876 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5257 11:08:04.492267 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5258 11:08:04.495511 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5259 11:08:04.499047 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5260 11:08:04.502030 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5261 11:08:04.505522 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5262 11:08:04.508999 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5263 11:08:04.515498 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5264 11:08:04.518536 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5265 11:08:04.521756 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5266 11:08:04.525492 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5267 11:08:04.528662 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5268 11:08:04.532218 ==
5269 11:08:04.535106 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 11:08:04.538461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 11:08:04.538560 ==
5272 11:08:04.538644 DQS Delay:
5273 11:08:04.541467 DQS0 = 0, DQS1 = 0
5274 11:08:04.541543 DQM Delay:
5275 11:08:04.545134 DQM0 = 96, DQM1 = 85
5276 11:08:04.545210 DQ Delay:
5277 11:08:04.548166 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5278 11:08:04.551543 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5279 11:08:04.555066 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5280 11:08:04.558049 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5281 11:08:04.558124
5282 11:08:04.558182
5283 11:08:04.558235 ==
5284 11:08:04.561360 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 11:08:04.564739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 11:08:04.564833 ==
5287 11:08:04.564906
5288 11:08:04.568396
5289 11:08:04.568470 TX Vref Scan disable
5290 11:08:04.571315 == TX Byte 0 ==
5291 11:08:04.574811 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5292 11:08:04.578129 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5293 11:08:04.581199 == TX Byte 1 ==
5294 11:08:04.584733 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5295 11:08:04.587727 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5296 11:08:04.587825 ==
5297 11:08:04.591086 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 11:08:04.597817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 11:08:04.597931 ==
5300 11:08:04.598016
5301 11:08:04.598097
5302 11:08:04.598176 TX Vref Scan disable
5303 11:08:04.602176 == TX Byte 0 ==
5304 11:08:04.605498 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5305 11:08:04.612262 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5306 11:08:04.612338 == TX Byte 1 ==
5307 11:08:04.615216 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5308 11:08:04.621880 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5309 11:08:04.621978
5310 11:08:04.622062 [DATLAT]
5311 11:08:04.622143 Freq=933, CH0 RK0
5312 11:08:04.622222
5313 11:08:04.625115 DATLAT Default: 0xd
5314 11:08:04.628790 0, 0xFFFF, sum = 0
5315 11:08:04.628866 1, 0xFFFF, sum = 0
5316 11:08:04.631836 2, 0xFFFF, sum = 0
5317 11:08:04.631911 3, 0xFFFF, sum = 0
5318 11:08:04.635090 4, 0xFFFF, sum = 0
5319 11:08:04.635165 5, 0xFFFF, sum = 0
5320 11:08:04.638501 6, 0xFFFF, sum = 0
5321 11:08:04.638577 7, 0xFFFF, sum = 0
5322 11:08:04.641429 8, 0xFFFF, sum = 0
5323 11:08:04.641505 9, 0xFFFF, sum = 0
5324 11:08:04.645133 10, 0x0, sum = 1
5325 11:08:04.645209 11, 0x0, sum = 2
5326 11:08:04.648175 12, 0x0, sum = 3
5327 11:08:04.648251 13, 0x0, sum = 4
5328 11:08:04.651264 best_step = 11
5329 11:08:04.651338
5330 11:08:04.651394 ==
5331 11:08:04.654728 Dram Type= 6, Freq= 0, CH_0, rank 0
5332 11:08:04.658110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 11:08:04.658185 ==
5334 11:08:04.658243 RX Vref Scan: 1
5335 11:08:04.661133
5336 11:08:04.661207 RX Vref 0 -> 0, step: 1
5337 11:08:04.661265
5338 11:08:04.664694 RX Delay -61 -> 252, step: 4
5339 11:08:04.664768
5340 11:08:04.667655 Set Vref, RX VrefLevel [Byte0]: 60
5341 11:08:04.671173 [Byte1]: 50
5342 11:08:04.674430
5343 11:08:04.674504 Final RX Vref Byte 0 = 60 to rank0
5344 11:08:04.677741 Final RX Vref Byte 1 = 50 to rank0
5345 11:08:04.681208 Final RX Vref Byte 0 = 60 to rank1
5346 11:08:04.684566 Final RX Vref Byte 1 = 50 to rank1==
5347 11:08:04.687907 Dram Type= 6, Freq= 0, CH_0, rank 0
5348 11:08:04.694231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 11:08:04.694331 ==
5350 11:08:04.694424 DQS Delay:
5351 11:08:04.697622 DQS0 = 0, DQS1 = 0
5352 11:08:04.697714 DQM Delay:
5353 11:08:04.697796 DQM0 = 96, DQM1 = 84
5354 11:08:04.700716 DQ Delay:
5355 11:08:04.704317 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =90
5356 11:08:04.707121 DQ4 =96, DQ5 =86, DQ6 =108, DQ7 =106
5357 11:08:04.710686 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5358 11:08:04.714178 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5359 11:08:04.714276
5360 11:08:04.714358
5361 11:08:04.720416 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5362 11:08:04.723849 CH0 RK0: MR19=505, MR18=2E15
5363 11:08:04.730050 CH0_RK0: MR19=0x505, MR18=0x2E15, DQSOSC=407, MR23=63, INC=65, DEC=43
5364 11:08:04.730138
5365 11:08:04.733434 ----->DramcWriteLeveling(PI) begin...
5366 11:08:04.733499 ==
5367 11:08:04.736804 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 11:08:04.740394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 11:08:04.740460 ==
5370 11:08:04.743357 Write leveling (Byte 0): 35 => 35
5371 11:08:04.746760 Write leveling (Byte 1): 30 => 30
5372 11:08:04.750184 DramcWriteLeveling(PI) end<-----
5373 11:08:04.750246
5374 11:08:04.750298 ==
5375 11:08:04.753442 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 11:08:04.760070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 11:08:04.760167 ==
5378 11:08:04.760254 [Gating] SW mode calibration
5379 11:08:04.769846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5380 11:08:04.773189 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5381 11:08:04.777006 0 14 0 | B1->B0 | 2d2d 3131 | 0 1 | (0 0) (1 1)
5382 11:08:04.782869 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 11:08:04.786462 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 11:08:04.789571 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 11:08:04.796261 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 11:08:04.799691 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 11:08:04.802829 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 11:08:04.809624 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5389 11:08:04.813040 0 15 0 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (1 0)
5390 11:08:04.816543 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 11:08:04.822633 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 11:08:04.826315 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 11:08:04.829778 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 11:08:04.835919 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 11:08:04.839388 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 11:08:04.842948 0 15 28 | B1->B0 | 2a29 3939 | 1 0 | (1 1) (0 0)
5397 11:08:04.849505 1 0 0 | B1->B0 | 4141 4141 | 0 1 | (0 0) (0 0)
5398 11:08:04.852842 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 11:08:04.855668 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 11:08:04.862272 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 11:08:04.865667 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 11:08:04.869157 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 11:08:04.875661 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 11:08:04.878821 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 11:08:04.882107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:08:04.888833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:08:04.892092 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:08:04.895684 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:08:04.902206 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:08:04.905616 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:08:04.908615 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:08:04.915226 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:08:04.918363 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 11:08:04.922030 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 11:08:04.928434 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 11:08:04.931641 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 11:08:04.934905 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 11:08:04.941551 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 11:08:04.945030 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 11:08:04.948362 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5421 11:08:04.954822 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5422 11:08:04.958358 Total UI for P1: 0, mck2ui 16
5423 11:08:04.961512 best dqsien dly found for B0: ( 1, 2, 28)
5424 11:08:04.964711 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 11:08:04.968157 Total UI for P1: 0, mck2ui 16
5426 11:08:04.971568 best dqsien dly found for B1: ( 1, 2, 30)
5427 11:08:04.974490 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5428 11:08:04.977780 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5429 11:08:04.977854
5430 11:08:04.981321 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5431 11:08:04.984565 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5432 11:08:04.988028 [Gating] SW calibration Done
5433 11:08:04.988102 ==
5434 11:08:04.990993 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 11:08:04.997653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 11:08:04.997729 ==
5437 11:08:04.997787 RX Vref Scan: 0
5438 11:08:04.997840
5439 11:08:05.001198 RX Vref 0 -> 0, step: 1
5440 11:08:05.001272
5441 11:08:05.004635 RX Delay -80 -> 252, step: 8
5442 11:08:05.007439 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5443 11:08:05.010888 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5444 11:08:05.014286 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5445 11:08:05.017339 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5446 11:08:05.023939 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5447 11:08:05.027244 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5448 11:08:05.030688 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5449 11:08:05.033813 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5450 11:08:05.037082 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5451 11:08:05.040529 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5452 11:08:05.047258 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5453 11:08:05.050286 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5454 11:08:05.053524 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5455 11:08:05.057073 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5456 11:08:05.063341 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5457 11:08:05.066662 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5458 11:08:05.066755 ==
5459 11:08:05.070195 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 11:08:05.073672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 11:08:05.073738 ==
5462 11:08:05.073793 DQS Delay:
5463 11:08:05.076698 DQS0 = 0, DQS1 = 0
5464 11:08:05.076761 DQM Delay:
5465 11:08:05.079716 DQM0 = 97, DQM1 = 87
5466 11:08:05.079777 DQ Delay:
5467 11:08:05.083189 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5468 11:08:05.086845 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5469 11:08:05.089834 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5470 11:08:05.093366 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5471 11:08:05.093433
5472 11:08:05.093489
5473 11:08:05.093541 ==
5474 11:08:05.096771 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 11:08:05.103065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 11:08:05.103131 ==
5477 11:08:05.103186
5478 11:08:05.103251
5479 11:08:05.103303 TX Vref Scan disable
5480 11:08:05.106498 == TX Byte 0 ==
5481 11:08:05.109980 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5482 11:08:05.116657 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5483 11:08:05.116730 == TX Byte 1 ==
5484 11:08:05.119952 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5485 11:08:05.126532 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5486 11:08:05.126611 ==
5487 11:08:05.129508 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 11:08:05.132798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 11:08:05.132870 ==
5490 11:08:05.132927
5491 11:08:05.132978
5492 11:08:05.136357 TX Vref Scan disable
5493 11:08:05.139384 == TX Byte 0 ==
5494 11:08:05.142765 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5495 11:08:05.146733 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5496 11:08:05.149669 == TX Byte 1 ==
5497 11:08:05.152530 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5498 11:08:05.156100 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5499 11:08:05.156167
5500 11:08:05.156222 [DATLAT]
5501 11:08:05.159392 Freq=933, CH0 RK1
5502 11:08:05.159507
5503 11:08:05.159561 DATLAT Default: 0xb
5504 11:08:05.162696 0, 0xFFFF, sum = 0
5505 11:08:05.166211 1, 0xFFFF, sum = 0
5506 11:08:05.166291 2, 0xFFFF, sum = 0
5507 11:08:05.169461 3, 0xFFFF, sum = 0
5508 11:08:05.169537 4, 0xFFFF, sum = 0
5509 11:08:05.172593 5, 0xFFFF, sum = 0
5510 11:08:05.172668 6, 0xFFFF, sum = 0
5511 11:08:05.175619 7, 0xFFFF, sum = 0
5512 11:08:05.175694 8, 0xFFFF, sum = 0
5513 11:08:05.179316 9, 0xFFFF, sum = 0
5514 11:08:05.179394 10, 0x0, sum = 1
5515 11:08:05.182805 11, 0x0, sum = 2
5516 11:08:05.182881 12, 0x0, sum = 3
5517 11:08:05.186080 13, 0x0, sum = 4
5518 11:08:05.186155 best_step = 11
5519 11:08:05.186213
5520 11:08:05.186266 ==
5521 11:08:05.189382 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 11:08:05.192569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 11:08:05.192645 ==
5524 11:08:05.195948 RX Vref Scan: 0
5525 11:08:05.196022
5526 11:08:05.199280 RX Vref 0 -> 0, step: 1
5527 11:08:05.199353
5528 11:08:05.199411 RX Delay -61 -> 252, step: 4
5529 11:08:05.207190 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5530 11:08:05.210617 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5531 11:08:05.213336 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5532 11:08:05.216861 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5533 11:08:05.220447 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5534 11:08:05.226562 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5535 11:08:05.230024 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5536 11:08:05.233389 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5537 11:08:05.237262 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5538 11:08:05.240194 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5539 11:08:05.243408 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5540 11:08:05.250864 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5541 11:08:05.253725 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5542 11:08:05.256863 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5543 11:08:05.259922 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5544 11:08:05.266221 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5545 11:08:05.266333 ==
5546 11:08:05.269714 Dram Type= 6, Freq= 0, CH_0, rank 1
5547 11:08:05.272972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 11:08:05.273096 ==
5549 11:08:05.273193 DQS Delay:
5550 11:08:05.276369 DQS0 = 0, DQS1 = 0
5551 11:08:05.276518 DQM Delay:
5552 11:08:05.279646 DQM0 = 95, DQM1 = 86
5553 11:08:05.279785 DQ Delay:
5554 11:08:05.282809 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5555 11:08:05.286528 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5556 11:08:05.289664 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5557 11:08:05.293395 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5558 11:08:05.293614
5559 11:08:05.293784
5560 11:08:05.299863 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5561 11:08:05.302910 CH0 RK1: MR19=504, MR18=25F7
5562 11:08:05.310001 CH0_RK1: MR19=0x504, MR18=0x25F7, DQSOSC=410, MR23=63, INC=64, DEC=42
5563 11:08:05.312968 [RxdqsGatingPostProcess] freq 933
5564 11:08:05.319122 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5565 11:08:05.323179 best DQS0 dly(2T, 0.5T) = (0, 10)
5566 11:08:05.326166 best DQS1 dly(2T, 0.5T) = (0, 10)
5567 11:08:05.329612 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5568 11:08:05.332882 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5569 11:08:05.333271 best DQS0 dly(2T, 0.5T) = (0, 10)
5570 11:08:05.335735 best DQS1 dly(2T, 0.5T) = (0, 10)
5571 11:08:05.339019 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5572 11:08:05.342370 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5573 11:08:05.345661 Pre-setting of DQS Precalculation
5574 11:08:05.352738 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5575 11:08:05.353122 ==
5576 11:08:05.355593 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 11:08:05.358756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 11:08:05.359162 ==
5579 11:08:05.365695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 11:08:05.371998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5581 11:08:05.375915 [CA 0] Center 36 (6~67) winsize 62
5582 11:08:05.378941 [CA 1] Center 36 (6~67) winsize 62
5583 11:08:05.381891 [CA 2] Center 34 (4~65) winsize 62
5584 11:08:05.385296 [CA 3] Center 33 (3~64) winsize 62
5585 11:08:05.388677 [CA 4] Center 34 (4~64) winsize 61
5586 11:08:05.392014 [CA 5] Center 33 (3~64) winsize 62
5587 11:08:05.392397
5588 11:08:05.395100 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5589 11:08:05.395521
5590 11:08:05.398706 [CATrainingPosCal] consider 1 rank data
5591 11:08:05.401771 u2DelayCellTimex100 = 270/100 ps
5592 11:08:05.405534 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5593 11:08:05.408298 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5594 11:08:05.411774 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5595 11:08:05.414909 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5596 11:08:05.418291 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5597 11:08:05.421755 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 11:08:05.425283
5599 11:08:05.428014 CA PerBit enable=1, Macro0, CA PI delay=33
5600 11:08:05.428383
5601 11:08:05.431417 [CBTSetCACLKResult] CA Dly = 33
5602 11:08:05.431930 CS Dly: 5 (0~36)
5603 11:08:05.432295 ==
5604 11:08:05.434879 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 11:08:05.437731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 11:08:05.441180 ==
5607 11:08:05.444398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5608 11:08:05.451474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5609 11:08:05.454673 [CA 0] Center 36 (6~67) winsize 62
5610 11:08:05.457928 [CA 1] Center 37 (7~67) winsize 61
5611 11:08:05.460841 [CA 2] Center 34 (4~65) winsize 62
5612 11:08:05.464402 [CA 3] Center 33 (3~64) winsize 62
5613 11:08:05.468285 [CA 4] Center 34 (3~65) winsize 63
5614 11:08:05.471064 [CA 5] Center 33 (3~64) winsize 62
5615 11:08:05.471503
5616 11:08:05.473983 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5617 11:08:05.474363
5618 11:08:05.477624 [CATrainingPosCal] consider 2 rank data
5619 11:08:05.480598 u2DelayCellTimex100 = 270/100 ps
5620 11:08:05.483956 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5621 11:08:05.487581 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5622 11:08:05.490583 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5623 11:08:05.497639 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5624 11:08:05.500765 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5625 11:08:05.504086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5626 11:08:05.504597
5627 11:08:05.507304 CA PerBit enable=1, Macro0, CA PI delay=33
5628 11:08:05.507801
5629 11:08:05.510154 [CBTSetCACLKResult] CA Dly = 33
5630 11:08:05.510537 CS Dly: 6 (0~39)
5631 11:08:05.510834
5632 11:08:05.513921 ----->DramcWriteLeveling(PI) begin...
5633 11:08:05.516955 ==
5634 11:08:05.517337 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:08:05.523863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:08:05.524245 ==
5637 11:08:05.527033 Write leveling (Byte 0): 26 => 26
5638 11:08:05.529923 Write leveling (Byte 1): 26 => 26
5639 11:08:05.533557 DramcWriteLeveling(PI) end<-----
5640 11:08:05.533935
5641 11:08:05.534229 ==
5642 11:08:05.536949 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 11:08:05.539818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 11:08:05.540203 ==
5645 11:08:05.543368 [Gating] SW mode calibration
5646 11:08:05.550013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5647 11:08:05.556504 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5648 11:08:05.559759 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5649 11:08:05.562626 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 11:08:05.568878 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 11:08:05.572579 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 11:08:05.575516 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 11:08:05.582256 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 11:08:05.585435 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 1)
5655 11:08:05.588693 0 14 28 | B1->B0 | 2d2d 2929 | 0 0 | (0 1) (0 0)
5656 11:08:05.595477 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5657 11:08:05.598632 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 11:08:05.602210 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 11:08:05.608575 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 11:08:05.611739 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 11:08:05.615255 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 11:08:05.621335 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 11:08:05.625076 0 15 28 | B1->B0 | 3535 3c3b | 0 1 | (0 0) (0 0)
5664 11:08:05.628038 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 11:08:05.634925 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:08:05.638328 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 11:08:05.641177 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 11:08:05.648354 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 11:08:05.651134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5670 11:08:05.654600 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5671 11:08:05.661197 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:08:05.664723 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5673 11:08:05.668083 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:08:05.674556 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:08:05.677933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:08:05.681261 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:08:05.687571 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:08:05.690796 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:08:05.694118 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 11:08:05.700656 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 11:08:05.704152 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:08:05.707386 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 11:08:05.713938 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 11:08:05.717355 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 11:08:05.720676 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5686 11:08:05.726917 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5687 11:08:05.730678 Total UI for P1: 0, mck2ui 16
5688 11:08:05.733678 best dqsien dly found for B0: ( 1, 2, 20)
5689 11:08:05.737427 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 11:08:05.740311 Total UI for P1: 0, mck2ui 16
5691 11:08:05.743801 best dqsien dly found for B1: ( 1, 2, 24)
5692 11:08:05.747200 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5693 11:08:05.750563 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5694 11:08:05.750638
5695 11:08:05.753423 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5696 11:08:05.756854 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5697 11:08:05.760360 [Gating] SW calibration Done
5698 11:08:05.760441 ==
5699 11:08:05.763782 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 11:08:05.770152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 11:08:05.770227 ==
5702 11:08:05.770289 RX Vref Scan: 0
5703 11:08:05.770362
5704 11:08:05.773865 RX Vref 0 -> 0, step: 1
5705 11:08:05.773942
5706 11:08:05.776688 RX Delay -80 -> 252, step: 8
5707 11:08:05.779935 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5708 11:08:05.783575 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5709 11:08:05.786505 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5710 11:08:05.789782 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5711 11:08:05.793407 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5712 11:08:05.800049 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5713 11:08:05.803342 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5714 11:08:05.806227 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5715 11:08:05.810019 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5716 11:08:05.813112 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5717 11:08:05.819481 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5718 11:08:05.823185 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5719 11:08:05.826790 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5720 11:08:05.829911 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5721 11:08:05.832677 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5722 11:08:05.839389 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5723 11:08:05.839517 ==
5724 11:08:05.842796 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 11:08:05.846806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 11:08:05.846885 ==
5727 11:08:05.846962 DQS Delay:
5728 11:08:05.849501 DQS0 = 0, DQS1 = 0
5729 11:08:05.849578 DQM Delay:
5730 11:08:05.852642 DQM0 = 102, DQM1 = 90
5731 11:08:05.852726 DQ Delay:
5732 11:08:05.856076 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5733 11:08:05.859247 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5734 11:08:05.862443 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5735 11:08:05.865808 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5736 11:08:05.865874
5737 11:08:05.865932
5738 11:08:05.865983 ==
5739 11:08:05.869341 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 11:08:05.872097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:08:05.875564 ==
5742 11:08:05.875631
5743 11:08:05.875703
5744 11:08:05.875787 TX Vref Scan disable
5745 11:08:05.879090 == TX Byte 0 ==
5746 11:08:05.882130 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5747 11:08:05.885960 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5748 11:08:05.889017 == TX Byte 1 ==
5749 11:08:05.892141 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5750 11:08:05.895381 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5751 11:08:05.898572 ==
5752 11:08:05.901803 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 11:08:05.905114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 11:08:05.905191 ==
5755 11:08:05.905266
5756 11:08:05.905339
5757 11:08:05.908755 TX Vref Scan disable
5758 11:08:05.908843 == TX Byte 0 ==
5759 11:08:05.915693 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5760 11:08:05.918626 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5761 11:08:05.918703 == TX Byte 1 ==
5762 11:08:05.924758 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5763 11:08:05.928316 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5764 11:08:05.928392
5765 11:08:05.928469 [DATLAT]
5766 11:08:05.931376 Freq=933, CH1 RK0
5767 11:08:05.931504
5768 11:08:05.931580 DATLAT Default: 0xd
5769 11:08:05.935241 0, 0xFFFF, sum = 0
5770 11:08:05.935332 1, 0xFFFF, sum = 0
5771 11:08:05.938404 2, 0xFFFF, sum = 0
5772 11:08:05.941392 3, 0xFFFF, sum = 0
5773 11:08:05.941469 4, 0xFFFF, sum = 0
5774 11:08:05.944605 5, 0xFFFF, sum = 0
5775 11:08:05.944684 6, 0xFFFF, sum = 0
5776 11:08:05.948038 7, 0xFFFF, sum = 0
5777 11:08:05.948117 8, 0xFFFF, sum = 0
5778 11:08:05.951410 9, 0xFFFF, sum = 0
5779 11:08:05.951516 10, 0x0, sum = 1
5780 11:08:05.954956 11, 0x0, sum = 2
5781 11:08:05.955033 12, 0x0, sum = 3
5782 11:08:05.957731 13, 0x0, sum = 4
5783 11:08:05.957810 best_step = 11
5784 11:08:05.957886
5785 11:08:05.957958 ==
5786 11:08:05.961147 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 11:08:05.964612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 11:08:05.964690 ==
5789 11:08:05.967804 RX Vref Scan: 1
5790 11:08:05.967882
5791 11:08:05.971308 RX Vref 0 -> 0, step: 1
5792 11:08:05.971382
5793 11:08:05.971470 RX Delay -69 -> 252, step: 4
5794 11:08:05.971540
5795 11:08:05.974759 Set Vref, RX VrefLevel [Byte0]: 50
5796 11:08:05.977792 [Byte1]: 61
5797 11:08:05.982501
5798 11:08:05.982575 Final RX Vref Byte 0 = 50 to rank0
5799 11:08:05.985732 Final RX Vref Byte 1 = 61 to rank0
5800 11:08:05.989209 Final RX Vref Byte 0 = 50 to rank1
5801 11:08:05.992616 Final RX Vref Byte 1 = 61 to rank1==
5802 11:08:05.996017 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 11:08:06.002567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 11:08:06.002642 ==
5805 11:08:06.002707 DQS Delay:
5806 11:08:06.005580 DQS0 = 0, DQS1 = 0
5807 11:08:06.005655 DQM Delay:
5808 11:08:06.005712 DQM0 = 100, DQM1 = 94
5809 11:08:06.009317 DQ Delay:
5810 11:08:06.012184 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5811 11:08:06.015943 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5812 11:08:06.019296 DQ8 =82, DQ9 =86, DQ10 =98, DQ11 =86
5813 11:08:06.022510 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5814 11:08:06.022594
5815 11:08:06.022658
5816 11:08:06.028731 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5817 11:08:06.032153 CH1 RK0: MR19=505, MR18=1F0F
5818 11:08:06.038726 CH1_RK0: MR19=0x505, MR18=0x1F0F, DQSOSC=412, MR23=63, INC=63, DEC=42
5819 11:08:06.038801
5820 11:08:06.042153 ----->DramcWriteLeveling(PI) begin...
5821 11:08:06.042230 ==
5822 11:08:06.045373 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:08:06.048483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:08:06.048558 ==
5825 11:08:06.051859 Write leveling (Byte 0): 28 => 28
5826 11:08:06.055447 Write leveling (Byte 1): 30 => 30
5827 11:08:06.058962 DramcWriteLeveling(PI) end<-----
5828 11:08:06.059029
5829 11:08:06.059085 ==
5830 11:08:06.062025 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 11:08:06.068351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 11:08:06.068426 ==
5833 11:08:06.068485 [Gating] SW mode calibration
5834 11:08:06.078313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5835 11:08:06.081725 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5836 11:08:06.088200 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5837 11:08:06.091342 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 11:08:06.094816 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 11:08:06.101353 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 11:08:06.104924 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 11:08:06.107868 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 11:08:06.114900 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5843 11:08:06.118015 0 14 28 | B1->B0 | 2828 3030 | 0 1 | (1 0) (1 0)
5844 11:08:06.121499 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5845 11:08:06.127846 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 11:08:06.131254 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 11:08:06.134805 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 11:08:06.140942 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 11:08:06.144244 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 11:08:06.147628 0 15 24 | B1->B0 | 2c2b 2424 | 1 0 | (0 0) (0 0)
5851 11:08:06.150834 0 15 28 | B1->B0 | 4444 3939 | 0 0 | (0 0) (1 1)
5852 11:08:06.157663 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 11:08:06.161036 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 11:08:06.164531 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 11:08:06.171020 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 11:08:06.174249 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 11:08:06.177794 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 11:08:06.184051 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 11:08:06.187604 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5860 11:08:06.190817 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:08:06.197328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:08:06.200748 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:08:06.203859 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:08:06.210148 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:08:06.213426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:08:06.220259 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:08:06.223395 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:08:06.227280 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:08:06.233739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:08:06.236384 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 11:08:06.239857 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 11:08:06.246301 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 11:08:06.249756 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 11:08:06.253371 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5875 11:08:06.256425 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 11:08:06.259995 Total UI for P1: 0, mck2ui 16
5877 11:08:06.263253 best dqsien dly found for B0: ( 1, 2, 26)
5878 11:08:06.266448 Total UI for P1: 0, mck2ui 16
5879 11:08:06.269884 best dqsien dly found for B1: ( 1, 2, 24)
5880 11:08:06.273381 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5881 11:08:06.279586 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5882 11:08:06.279661
5883 11:08:06.282830 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5884 11:08:06.286456 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5885 11:08:06.289379 [Gating] SW calibration Done
5886 11:08:06.289446 ==
5887 11:08:06.293017 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 11:08:06.296008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 11:08:06.296075 ==
5890 11:08:06.299373 RX Vref Scan: 0
5891 11:08:06.299508
5892 11:08:06.299581 RX Vref 0 -> 0, step: 1
5893 11:08:06.299661
5894 11:08:06.302832 RX Delay -80 -> 252, step: 8
5895 11:08:06.305703 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5896 11:08:06.309049 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5897 11:08:06.315908 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5898 11:08:06.319135 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5899 11:08:06.322686 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5900 11:08:06.326103 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5901 11:08:06.329306 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5902 11:08:06.335724 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5903 11:08:06.339272 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5904 11:08:06.342312 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5905 11:08:06.345901 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5906 11:08:06.348889 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5907 11:08:06.356072 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5908 11:08:06.359310 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5909 11:08:06.362568 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5910 11:08:06.366173 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5911 11:08:06.366692 ==
5912 11:08:06.368839 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 11:08:06.372312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 11:08:06.375306 ==
5915 11:08:06.375797 DQS Delay:
5916 11:08:06.376130 DQS0 = 0, DQS1 = 0
5917 11:08:06.378957 DQM Delay:
5918 11:08:06.379378 DQM0 = 100, DQM1 = 91
5919 11:08:06.382298 DQ Delay:
5920 11:08:06.385860 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5921 11:08:06.389023 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =95
5922 11:08:06.391820 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5923 11:08:06.396254 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =99
5924 11:08:06.396678
5925 11:08:06.396989
5926 11:08:06.397263 ==
5927 11:08:06.398556 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 11:08:06.402264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 11:08:06.402648 ==
5930 11:08:06.403013
5931 11:08:06.403335
5932 11:08:06.405378 TX Vref Scan disable
5933 11:08:06.405759 == TX Byte 0 ==
5934 11:08:06.412092 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5935 11:08:06.415007 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5936 11:08:06.415392 == TX Byte 1 ==
5937 11:08:06.421845 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5938 11:08:06.425208 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5939 11:08:06.425610 ==
5940 11:08:06.428578 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 11:08:06.431900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 11:08:06.432307 ==
5943 11:08:06.432605
5944 11:08:06.434835
5945 11:08:06.435212 TX Vref Scan disable
5946 11:08:06.438210 == TX Byte 0 ==
5947 11:08:06.441414 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5948 11:08:06.444819 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5949 11:08:06.448693 == TX Byte 1 ==
5950 11:08:06.451480 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5951 11:08:06.458160 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5952 11:08:06.458545
5953 11:08:06.458872 [DATLAT]
5954 11:08:06.459149 Freq=933, CH1 RK1
5955 11:08:06.459415
5956 11:08:06.461343 DATLAT Default: 0xb
5957 11:08:06.461722 0, 0xFFFF, sum = 0
5958 11:08:06.464726 1, 0xFFFF, sum = 0
5959 11:08:06.465117 2, 0xFFFF, sum = 0
5960 11:08:06.468359 3, 0xFFFF, sum = 0
5961 11:08:06.471270 4, 0xFFFF, sum = 0
5962 11:08:06.471755 5, 0xFFFF, sum = 0
5963 11:08:06.474807 6, 0xFFFF, sum = 0
5964 11:08:06.475195 7, 0xFFFF, sum = 0
5965 11:08:06.478424 8, 0xFFFF, sum = 0
5966 11:08:06.478847 9, 0xFFFF, sum = 0
5967 11:08:06.481363 10, 0x0, sum = 1
5968 11:08:06.481780 11, 0x0, sum = 2
5969 11:08:06.485023 12, 0x0, sum = 3
5970 11:08:06.485411 13, 0x0, sum = 4
5971 11:08:06.485714 best_step = 11
5972 11:08:06.485986
5973 11:08:06.488674 ==
5974 11:08:06.491666 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 11:08:06.494610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 11:08:06.494989 ==
5977 11:08:06.495282 RX Vref Scan: 0
5978 11:08:06.495606
5979 11:08:06.498126 RX Vref 0 -> 0, step: 1
5980 11:08:06.498504
5981 11:08:06.501214 RX Delay -61 -> 252, step: 4
5982 11:08:06.507653 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5983 11:08:06.511145 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5984 11:08:06.514364 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5985 11:08:06.517968 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5986 11:08:06.520969 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5987 11:08:06.524292 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5988 11:08:06.530836 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5989 11:08:06.534106 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5990 11:08:06.537571 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5991 11:08:06.540617 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5992 11:08:06.544070 iDelay=207, Bit 10, Center 96 (7 ~ 186) 180
5993 11:08:06.547509 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
5994 11:08:06.554073 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5995 11:08:06.557343 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
5996 11:08:06.560462 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5997 11:08:06.563893 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
5998 11:08:06.564429 ==
5999 11:08:06.567471 Dram Type= 6, Freq= 0, CH_1, rank 1
6000 11:08:06.574050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6001 11:08:06.574454 ==
6002 11:08:06.574975 DQS Delay:
6003 11:08:06.575521 DQS0 = 0, DQS1 = 0
6004 11:08:06.577262 DQM Delay:
6005 11:08:06.577677 DQM0 = 100, DQM1 = 93
6006 11:08:06.580656 DQ Delay:
6007 11:08:06.584208 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6008 11:08:06.587207 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =96
6009 11:08:06.590451 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =82
6010 11:08:06.593845 DQ12 =104, DQ13 =98, DQ14 =100, DQ15 =100
6011 11:08:06.594274
6012 11:08:06.594637
6013 11:08:06.600405 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6014 11:08:06.603407 CH1 RK1: MR19=505, MR18=701
6015 11:08:06.610555 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
6016 11:08:06.614200 [RxdqsGatingPostProcess] freq 933
6017 11:08:06.616738 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6018 11:08:06.620142 best DQS0 dly(2T, 0.5T) = (0, 10)
6019 11:08:06.623586 best DQS1 dly(2T, 0.5T) = (0, 10)
6020 11:08:06.626914 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6021 11:08:06.630527 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6022 11:08:06.633184 best DQS0 dly(2T, 0.5T) = (0, 10)
6023 11:08:06.636620 best DQS1 dly(2T, 0.5T) = (0, 10)
6024 11:08:06.640020 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6025 11:08:06.643902 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6026 11:08:06.646480 Pre-setting of DQS Precalculation
6027 11:08:06.649798 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6028 11:08:06.660218 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6029 11:08:06.666644 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6030 11:08:06.667241
6031 11:08:06.667700
6032 11:08:06.669712 [Calibration Summary] 1866 Mbps
6033 11:08:06.670075 CH 0, Rank 0
6034 11:08:06.672948 SW Impedance : PASS
6035 11:08:06.676742 DUTY Scan : NO K
6036 11:08:06.677136 ZQ Calibration : PASS
6037 11:08:06.679389 Jitter Meter : NO K
6038 11:08:06.679847 CBT Training : PASS
6039 11:08:06.682750 Write leveling : PASS
6040 11:08:06.686202 RX DQS gating : PASS
6041 11:08:06.686594 RX DQ/DQS(RDDQC) : PASS
6042 11:08:06.689370 TX DQ/DQS : PASS
6043 11:08:06.692780 RX DATLAT : PASS
6044 11:08:06.693178 RX DQ/DQS(Engine): PASS
6045 11:08:06.695796 TX OE : NO K
6046 11:08:06.696188 All Pass.
6047 11:08:06.696574
6048 11:08:06.699725 CH 0, Rank 1
6049 11:08:06.700143 SW Impedance : PASS
6050 11:08:06.703039 DUTY Scan : NO K
6051 11:08:06.705914 ZQ Calibration : PASS
6052 11:08:06.706293 Jitter Meter : NO K
6053 11:08:06.709130 CBT Training : PASS
6054 11:08:06.712505 Write leveling : PASS
6055 11:08:06.712891 RX DQS gating : PASS
6056 11:08:06.716416 RX DQ/DQS(RDDQC) : PASS
6057 11:08:06.719361 TX DQ/DQS : PASS
6058 11:08:06.719786 RX DATLAT : PASS
6059 11:08:06.722264 RX DQ/DQS(Engine): PASS
6060 11:08:06.725977 TX OE : NO K
6061 11:08:06.726355 All Pass.
6062 11:08:06.726649
6063 11:08:06.726924 CH 1, Rank 0
6064 11:08:06.729283 SW Impedance : PASS
6065 11:08:06.732279 DUTY Scan : NO K
6066 11:08:06.732657 ZQ Calibration : PASS
6067 11:08:06.735807 Jitter Meter : NO K
6068 11:08:06.739184 CBT Training : PASS
6069 11:08:06.739602 Write leveling : PASS
6070 11:08:06.742144 RX DQS gating : PASS
6071 11:08:06.745537 RX DQ/DQS(RDDQC) : PASS
6072 11:08:06.745915 TX DQ/DQS : PASS
6073 11:08:06.748891 RX DATLAT : PASS
6074 11:08:06.749283 RX DQ/DQS(Engine): PASS
6075 11:08:06.751966 TX OE : NO K
6076 11:08:06.752346 All Pass.
6077 11:08:06.752640
6078 11:08:06.755492 CH 1, Rank 1
6079 11:08:06.755923 SW Impedance : PASS
6080 11:08:06.758816 DUTY Scan : NO K
6081 11:08:06.762994 ZQ Calibration : PASS
6082 11:08:06.763373 Jitter Meter : NO K
6083 11:08:06.765421 CBT Training : PASS
6084 11:08:06.768797 Write leveling : PASS
6085 11:08:06.769310 RX DQS gating : PASS
6086 11:08:06.772052 RX DQ/DQS(RDDQC) : PASS
6087 11:08:06.775405 TX DQ/DQS : PASS
6088 11:08:06.775830 RX DATLAT : PASS
6089 11:08:06.778551 RX DQ/DQS(Engine): PASS
6090 11:08:06.781715 TX OE : NO K
6091 11:08:06.782099 All Pass.
6092 11:08:06.782392
6093 11:08:06.785294 DramC Write-DBI off
6094 11:08:06.785676 PER_BANK_REFRESH: Hybrid Mode
6095 11:08:06.788549 TX_TRACKING: ON
6096 11:08:06.795086 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6097 11:08:06.801806 [FAST_K] Save calibration result to emmc
6098 11:08:06.805098 dramc_set_vcore_voltage set vcore to 650000
6099 11:08:06.805530 Read voltage for 400, 6
6100 11:08:06.808599 Vio18 = 0
6101 11:08:06.808979 Vcore = 650000
6102 11:08:06.809275 Vdram = 0
6103 11:08:06.811876 Vddq = 0
6104 11:08:06.812259 Vmddr = 0
6105 11:08:06.814713 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6106 11:08:06.821325 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6107 11:08:06.824678 MEM_TYPE=3, freq_sel=20
6108 11:08:06.828170 sv_algorithm_assistance_LP4_800
6109 11:08:06.831239 ============ PULL DRAM RESETB DOWN ============
6110 11:08:06.834630 ========== PULL DRAM RESETB DOWN end =========
6111 11:08:06.841114 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6112 11:08:06.844437 ===================================
6113 11:08:06.844818 LPDDR4 DRAM CONFIGURATION
6114 11:08:06.848140 ===================================
6115 11:08:06.851424 EX_ROW_EN[0] = 0x0
6116 11:08:06.851844 EX_ROW_EN[1] = 0x0
6117 11:08:06.854350 LP4Y_EN = 0x0
6118 11:08:06.858034 WORK_FSP = 0x0
6119 11:08:06.858414 WL = 0x2
6120 11:08:06.861478 RL = 0x2
6121 11:08:06.861854 BL = 0x2
6122 11:08:06.864300 RPST = 0x0
6123 11:08:06.864692 RD_PRE = 0x0
6124 11:08:06.867885 WR_PRE = 0x1
6125 11:08:06.868267 WR_PST = 0x0
6126 11:08:06.870998 DBI_WR = 0x0
6127 11:08:06.871377 DBI_RD = 0x0
6128 11:08:06.874319 OTF = 0x1
6129 11:08:06.877872 ===================================
6130 11:08:06.881258 ===================================
6131 11:08:06.881634 ANA top config
6132 11:08:06.884053 ===================================
6133 11:08:06.887524 DLL_ASYNC_EN = 0
6134 11:08:06.890941 ALL_SLAVE_EN = 1
6135 11:08:06.891320 NEW_RANK_MODE = 1
6136 11:08:06.894017 DLL_IDLE_MODE = 1
6137 11:08:06.897752 LP45_APHY_COMB_EN = 1
6138 11:08:06.900783 TX_ODT_DIS = 1
6139 11:08:06.904045 NEW_8X_MODE = 1
6140 11:08:06.907398 ===================================
6141 11:08:06.910902 ===================================
6142 11:08:06.911280 data_rate = 800
6143 11:08:06.914398 CKR = 1
6144 11:08:06.917579 DQ_P2S_RATIO = 4
6145 11:08:06.920726 ===================================
6146 11:08:06.924105 CA_P2S_RATIO = 4
6147 11:08:06.927351 DQ_CA_OPEN = 0
6148 11:08:06.930664 DQ_SEMI_OPEN = 1
6149 11:08:06.933755 CA_SEMI_OPEN = 1
6150 11:08:06.934134 CA_FULL_RATE = 0
6151 11:08:06.936865 DQ_CKDIV4_EN = 0
6152 11:08:06.940432 CA_CKDIV4_EN = 1
6153 11:08:06.943883 CA_PREDIV_EN = 0
6154 11:08:06.947073 PH8_DLY = 0
6155 11:08:06.950344 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6156 11:08:06.950723 DQ_AAMCK_DIV = 0
6157 11:08:06.953740 CA_AAMCK_DIV = 0
6158 11:08:06.956970 CA_ADMCK_DIV = 4
6159 11:08:06.959926 DQ_TRACK_CA_EN = 0
6160 11:08:06.963352 CA_PICK = 800
6161 11:08:06.966763 CA_MCKIO = 400
6162 11:08:06.970226 MCKIO_SEMI = 400
6163 11:08:06.970607 PLL_FREQ = 3016
6164 11:08:06.973703 DQ_UI_PI_RATIO = 32
6165 11:08:06.976538 CA_UI_PI_RATIO = 32
6166 11:08:06.980096 ===================================
6167 11:08:06.983483 ===================================
6168 11:08:06.987116 memory_type:LPDDR4
6169 11:08:06.990072 GP_NUM : 10
6170 11:08:06.990449 SRAM_EN : 1
6171 11:08:06.993488 MD32_EN : 0
6172 11:08:06.996753 ===================================
6173 11:08:06.997131 [ANA_INIT] >>>>>>>>>>>>>>
6174 11:08:06.999877 <<<<<< [CONFIGURE PHASE]: ANA_TX
6175 11:08:07.003567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6176 11:08:07.006206 ===================================
6177 11:08:07.009708 data_rate = 800,PCW = 0X7400
6178 11:08:07.012831 ===================================
6179 11:08:07.016396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6180 11:08:07.022538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6181 11:08:07.032316 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6182 11:08:07.038897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6183 11:08:07.042482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6184 11:08:07.045714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6185 11:08:07.045880 [ANA_INIT] flow start
6186 11:08:07.049518 [ANA_INIT] PLL >>>>>>>>
6187 11:08:07.052037 [ANA_INIT] PLL <<<<<<<<
6188 11:08:07.055380 [ANA_INIT] MIDPI >>>>>>>>
6189 11:08:07.055579 [ANA_INIT] MIDPI <<<<<<<<
6190 11:08:07.058652 [ANA_INIT] DLL >>>>>>>>
6191 11:08:07.062147 [ANA_INIT] flow end
6192 11:08:07.065680 ============ LP4 DIFF to SE enter ============
6193 11:08:07.068816 ============ LP4 DIFF to SE exit ============
6194 11:08:07.072633 [ANA_INIT] <<<<<<<<<<<<<
6195 11:08:07.075348 [Flow] Enable top DCM control >>>>>
6196 11:08:07.078761 [Flow] Enable top DCM control <<<<<
6197 11:08:07.082470 Enable DLL master slave shuffle
6198 11:08:07.085847 ==============================================================
6199 11:08:07.089221 Gating Mode config
6200 11:08:07.092112 ==============================================================
6201 11:08:07.095541 Config description:
6202 11:08:07.105389 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6203 11:08:07.112036 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6204 11:08:07.115503 SELPH_MODE 0: By rank 1: By Phase
6205 11:08:07.121953 ==============================================================
6206 11:08:07.125199 GAT_TRACK_EN = 0
6207 11:08:07.128919 RX_GATING_MODE = 2
6208 11:08:07.132311 RX_GATING_TRACK_MODE = 2
6209 11:08:07.135185 SELPH_MODE = 1
6210 11:08:07.138926 PICG_EARLY_EN = 1
6211 11:08:07.142319 VALID_LAT_VALUE = 1
6212 11:08:07.145214 ==============================================================
6213 11:08:07.148748 Enter into Gating configuration >>>>
6214 11:08:07.151729 Exit from Gating configuration <<<<
6215 11:08:07.154890 Enter into DVFS_PRE_config >>>>>
6216 11:08:07.168186 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6217 11:08:07.168581 Exit from DVFS_PRE_config <<<<<
6218 11:08:07.171263 Enter into PICG configuration >>>>
6219 11:08:07.174980 Exit from PICG configuration <<<<
6220 11:08:07.178198 [RX_INPUT] configuration >>>>>
6221 11:08:07.181282 [RX_INPUT] configuration <<<<<
6222 11:08:07.187827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6223 11:08:07.191499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6224 11:08:07.197768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6225 11:08:07.204801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6226 11:08:07.210818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6227 11:08:07.217704 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6228 11:08:07.221016 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6229 11:08:07.223931 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6230 11:08:07.230831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6231 11:08:07.233806 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6232 11:08:07.237411 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6233 11:08:07.240130 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6234 11:08:07.243536 ===================================
6235 11:08:07.247277 LPDDR4 DRAM CONFIGURATION
6236 11:08:07.250186 ===================================
6237 11:08:07.254026 EX_ROW_EN[0] = 0x0
6238 11:08:07.254408 EX_ROW_EN[1] = 0x0
6239 11:08:07.257001 LP4Y_EN = 0x0
6240 11:08:07.257384 WORK_FSP = 0x0
6241 11:08:07.260493 WL = 0x2
6242 11:08:07.260878 RL = 0x2
6243 11:08:07.263498 BL = 0x2
6244 11:08:07.263883 RPST = 0x0
6245 11:08:07.267128 RD_PRE = 0x0
6246 11:08:07.270009 WR_PRE = 0x1
6247 11:08:07.270385 WR_PST = 0x0
6248 11:08:07.273647 DBI_WR = 0x0
6249 11:08:07.274023 DBI_RD = 0x0
6250 11:08:07.276711 OTF = 0x1
6251 11:08:07.279891 ===================================
6252 11:08:07.283136 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6253 11:08:07.286477 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6254 11:08:07.290199 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6255 11:08:07.293267 ===================================
6256 11:08:07.296329 LPDDR4 DRAM CONFIGURATION
6257 11:08:07.299795 ===================================
6258 11:08:07.303244 EX_ROW_EN[0] = 0x10
6259 11:08:07.303728 EX_ROW_EN[1] = 0x0
6260 11:08:07.306551 LP4Y_EN = 0x0
6261 11:08:07.306930 WORK_FSP = 0x0
6262 11:08:07.309782 WL = 0x2
6263 11:08:07.310208 RL = 0x2
6264 11:08:07.313292 BL = 0x2
6265 11:08:07.313670 RPST = 0x0
6266 11:08:07.316571 RD_PRE = 0x0
6267 11:08:07.316949 WR_PRE = 0x1
6268 11:08:07.319679 WR_PST = 0x0
6269 11:08:07.323011 DBI_WR = 0x0
6270 11:08:07.323395 DBI_RD = 0x0
6271 11:08:07.326480 OTF = 0x1
6272 11:08:07.329863 ===================================
6273 11:08:07.333137 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6274 11:08:07.338448 nWR fixed to 30
6275 11:08:07.341295 [ModeRegInit_LP4] CH0 RK0
6276 11:08:07.341674 [ModeRegInit_LP4] CH0 RK1
6277 11:08:07.345112 [ModeRegInit_LP4] CH1 RK0
6278 11:08:07.348693 [ModeRegInit_LP4] CH1 RK1
6279 11:08:07.349072 match AC timing 19
6280 11:08:07.354979 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6281 11:08:07.358515 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6282 11:08:07.361376 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6283 11:08:07.368249 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6284 11:08:07.371557 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6285 11:08:07.371907 ==
6286 11:08:07.374596 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 11:08:07.377939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 11:08:07.378317 ==
6289 11:08:07.384528 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 11:08:07.391053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6291 11:08:07.394612 [CA 0] Center 36 (8~64) winsize 57
6292 11:08:07.397904 [CA 1] Center 36 (8~64) winsize 57
6293 11:08:07.401195 [CA 2] Center 36 (8~64) winsize 57
6294 11:08:07.404581 [CA 3] Center 36 (8~64) winsize 57
6295 11:08:07.407747 [CA 4] Center 36 (8~64) winsize 57
6296 11:08:07.408125 [CA 5] Center 36 (8~64) winsize 57
6297 11:08:07.410753
6298 11:08:07.414121 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6299 11:08:07.414505
6300 11:08:07.417613 [CATrainingPosCal] consider 1 rank data
6301 11:08:07.421088 u2DelayCellTimex100 = 270/100 ps
6302 11:08:07.424007 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:08:07.427483 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:08:07.430799 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:08:07.434293 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:08:07.437586 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:08:07.440857 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:08:07.441243
6309 11:08:07.444236 CA PerBit enable=1, Macro0, CA PI delay=36
6310 11:08:07.444616
6311 11:08:07.447269 [CBTSetCACLKResult] CA Dly = 36
6312 11:08:07.451015 CS Dly: 1 (0~32)
6313 11:08:07.451399 ==
6314 11:08:07.454039 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 11:08:07.457451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 11:08:07.457835 ==
6317 11:08:07.463864 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6318 11:08:07.470931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6319 11:08:07.473810 [CA 0] Center 36 (8~64) winsize 57
6320 11:08:07.477440 [CA 1] Center 36 (8~64) winsize 57
6321 11:08:07.477830 [CA 2] Center 36 (8~64) winsize 57
6322 11:08:07.480857 [CA 3] Center 36 (8~64) winsize 57
6323 11:08:07.483876 [CA 4] Center 36 (8~64) winsize 57
6324 11:08:07.486824 [CA 5] Center 36 (8~64) winsize 57
6325 11:08:07.487212
6326 11:08:07.493377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6327 11:08:07.493767
6328 11:08:07.496728 [CATrainingPosCal] consider 2 rank data
6329 11:08:07.500246 u2DelayCellTimex100 = 270/100 ps
6330 11:08:07.503082 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:08:07.506599 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:08:07.510071 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:08:07.513135 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 11:08:07.516298 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 11:08:07.519860 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 11:08:07.520248
6337 11:08:07.523150 CA PerBit enable=1, Macro0, CA PI delay=36
6338 11:08:07.523580
6339 11:08:07.526320 [CBTSetCACLKResult] CA Dly = 36
6340 11:08:07.529574 CS Dly: 1 (0~32)
6341 11:08:07.530084
6342 11:08:07.532846 ----->DramcWriteLeveling(PI) begin...
6343 11:08:07.533341 ==
6344 11:08:07.536275 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 11:08:07.539512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 11:08:07.539996 ==
6347 11:08:07.542668 Write leveling (Byte 0): 40 => 8
6348 11:08:07.546047 Write leveling (Byte 1): 32 => 0
6349 11:08:07.549660 DramcWriteLeveling(PI) end<-----
6350 11:08:07.549990
6351 11:08:07.550269 ==
6352 11:08:07.552357 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 11:08:07.556018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 11:08:07.556182 ==
6355 11:08:07.559240 [Gating] SW mode calibration
6356 11:08:07.565781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6357 11:08:07.572289 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6358 11:08:07.575644 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6359 11:08:07.581980 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6360 11:08:07.585842 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 11:08:07.588930 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 11:08:07.595412 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 11:08:07.599113 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 11:08:07.602594 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 11:08:07.608857 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 11:08:07.612285 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6367 11:08:07.615666 Total UI for P1: 0, mck2ui 16
6368 11:08:07.618636 best dqsien dly found for B0: ( 0, 14, 24)
6369 11:08:07.622235 Total UI for P1: 0, mck2ui 16
6370 11:08:07.625511 best dqsien dly found for B1: ( 0, 14, 24)
6371 11:08:07.628777 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6372 11:08:07.632054 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6373 11:08:07.632430
6374 11:08:07.635089 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6375 11:08:07.638622 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6376 11:08:07.642158 [Gating] SW calibration Done
6377 11:08:07.642532 ==
6378 11:08:07.645110 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 11:08:07.648546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 11:08:07.651713 ==
6381 11:08:07.652084 RX Vref Scan: 0
6382 11:08:07.652494
6383 11:08:07.654812 RX Vref 0 -> 0, step: 1
6384 11:08:07.655186
6385 11:08:07.658606 RX Delay -410 -> 252, step: 16
6386 11:08:07.661566 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6387 11:08:07.664790 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6388 11:08:07.668435 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6389 11:08:07.675016 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6390 11:08:07.677967 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6391 11:08:07.681624 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6392 11:08:07.684897 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6393 11:08:07.691701 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6394 11:08:07.695315 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6395 11:08:07.698650 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6396 11:08:07.702257 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6397 11:08:07.708087 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6398 11:08:07.711590 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6399 11:08:07.714643 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6400 11:08:07.721138 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6401 11:08:07.724702 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6402 11:08:07.725094 ==
6403 11:08:07.727707 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 11:08:07.731025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 11:08:07.731559 ==
6406 11:08:07.734400 DQS Delay:
6407 11:08:07.734792 DQS0 = 43, DQS1 = 59
6408 11:08:07.735182 DQM Delay:
6409 11:08:07.737836 DQM0 = 9, DQM1 = 11
6410 11:08:07.738227 DQ Delay:
6411 11:08:07.741035 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6412 11:08:07.744775 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6413 11:08:07.747881 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6414 11:08:07.751179 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6415 11:08:07.751627
6416 11:08:07.752009
6417 11:08:07.752367 ==
6418 11:08:07.754459 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 11:08:07.757725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 11:08:07.758122 ==
6421 11:08:07.761001
6422 11:08:07.761536
6423 11:08:07.761978 TX Vref Scan disable
6424 11:08:07.764182 == TX Byte 0 ==
6425 11:08:07.767481 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6426 11:08:07.770924 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6427 11:08:07.774350 == TX Byte 1 ==
6428 11:08:07.777638 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6429 11:08:07.780806 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6430 11:08:07.781199 ==
6431 11:08:07.783873 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 11:08:07.790380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 11:08:07.790773 ==
6434 11:08:07.791161
6435 11:08:07.791636
6436 11:08:07.791938 TX Vref Scan disable
6437 11:08:07.793713 == TX Byte 0 ==
6438 11:08:07.797109 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6439 11:08:07.800744 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6440 11:08:07.803937 == TX Byte 1 ==
6441 11:08:07.806772 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6442 11:08:07.810429 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6443 11:08:07.810825
6444 11:08:07.813721 [DATLAT]
6445 11:08:07.814191 Freq=400, CH0 RK0
6446 11:08:07.814501
6447 11:08:07.816766 DATLAT Default: 0xf
6448 11:08:07.817151 0, 0xFFFF, sum = 0
6449 11:08:07.820165 1, 0xFFFF, sum = 0
6450 11:08:07.820557 2, 0xFFFF, sum = 0
6451 11:08:07.823696 3, 0xFFFF, sum = 0
6452 11:08:07.824084 4, 0xFFFF, sum = 0
6453 11:08:07.826923 5, 0xFFFF, sum = 0
6454 11:08:07.827312 6, 0xFFFF, sum = 0
6455 11:08:07.830272 7, 0xFFFF, sum = 0
6456 11:08:07.833260 8, 0xFFFF, sum = 0
6457 11:08:07.833650 9, 0xFFFF, sum = 0
6458 11:08:07.836589 10, 0xFFFF, sum = 0
6459 11:08:07.836981 11, 0xFFFF, sum = 0
6460 11:08:07.840103 12, 0xFFFF, sum = 0
6461 11:08:07.840493 13, 0x0, sum = 1
6462 11:08:07.843527 14, 0x0, sum = 2
6463 11:08:07.843917 15, 0x0, sum = 3
6464 11:08:07.846529 16, 0x0, sum = 4
6465 11:08:07.846921 best_step = 14
6466 11:08:07.847220
6467 11:08:07.847527 ==
6468 11:08:07.849908 Dram Type= 6, Freq= 0, CH_0, rank 0
6469 11:08:07.852981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 11:08:07.853370 ==
6471 11:08:07.856635 RX Vref Scan: 1
6472 11:08:07.857020
6473 11:08:07.859844 RX Vref 0 -> 0, step: 1
6474 11:08:07.860234
6475 11:08:07.860534 RX Delay -359 -> 252, step: 8
6476 11:08:07.862933
6477 11:08:07.863522 Set Vref, RX VrefLevel [Byte0]: 60
6478 11:08:07.866135 [Byte1]: 50
6479 11:08:07.872313
6480 11:08:07.872697 Final RX Vref Byte 0 = 60 to rank0
6481 11:08:07.875656 Final RX Vref Byte 1 = 50 to rank0
6482 11:08:07.879123 Final RX Vref Byte 0 = 60 to rank1
6483 11:08:07.882033 Final RX Vref Byte 1 = 50 to rank1==
6484 11:08:07.885312 Dram Type= 6, Freq= 0, CH_0, rank 0
6485 11:08:07.891999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 11:08:07.892387 ==
6487 11:08:07.892686 DQS Delay:
6488 11:08:07.895079 DQS0 = 48, DQS1 = 60
6489 11:08:07.895508 DQM Delay:
6490 11:08:07.895905 DQM0 = 11, DQM1 = 11
6491 11:08:07.898185 DQ Delay:
6492 11:08:07.901630 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6493 11:08:07.904818 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6494 11:08:07.905208 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6495 11:08:07.911506 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6496 11:08:07.911944
6497 11:08:07.912448
6498 11:08:07.918331 [DQSOSCAuto] RK0, (LSB)MR18= 0xc184, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6499 11:08:07.921293 CH0 RK0: MR19=C0C, MR18=C184
6500 11:08:07.928203 CH0_RK0: MR19=0xC0C, MR18=0xC184, DQSOSC=385, MR23=63, INC=398, DEC=265
6501 11:08:07.928706 ==
6502 11:08:07.931127 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 11:08:07.935129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 11:08:07.935557 ==
6505 11:08:07.938490 [Gating] SW mode calibration
6506 11:08:07.944466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6507 11:08:07.951236 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6508 11:08:07.954418 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 11:08:07.958031 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6510 11:08:07.964508 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 11:08:07.967973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 11:08:07.970793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 11:08:07.977667 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 11:08:07.981170 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 11:08:07.984355 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 11:08:07.990614 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 11:08:07.994289 Total UI for P1: 0, mck2ui 16
6518 11:08:07.997562 best dqsien dly found for B0: ( 0, 14, 24)
6519 11:08:07.998035 Total UI for P1: 0, mck2ui 16
6520 11:08:08.003980 best dqsien dly found for B1: ( 0, 14, 24)
6521 11:08:08.007355 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6522 11:08:08.010710 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6523 11:08:08.011095
6524 11:08:08.013750 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6525 11:08:08.017329 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6526 11:08:08.020515 [Gating] SW calibration Done
6527 11:08:08.020898 ==
6528 11:08:08.023962 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 11:08:08.027415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 11:08:08.027830 ==
6531 11:08:08.030344 RX Vref Scan: 0
6532 11:08:08.030724
6533 11:08:08.031024 RX Vref 0 -> 0, step: 1
6534 11:08:08.033718
6535 11:08:08.034102 RX Delay -410 -> 252, step: 16
6536 11:08:08.040595 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6537 11:08:08.043983 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6538 11:08:08.047000 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6539 11:08:08.050429 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6540 11:08:08.056983 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6541 11:08:08.060396 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6542 11:08:08.064007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6543 11:08:08.067169 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6544 11:08:08.073566 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6545 11:08:08.076955 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6546 11:08:08.080134 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6547 11:08:08.086697 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6548 11:08:08.090036 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6549 11:08:08.093313 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6550 11:08:08.096679 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6551 11:08:08.102863 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6552 11:08:08.103289 ==
6553 11:08:08.106243 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:08:08.109527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:08:08.109952 ==
6556 11:08:08.110305 DQS Delay:
6557 11:08:08.113143 DQS0 = 43, DQS1 = 59
6558 11:08:08.113643 DQM Delay:
6559 11:08:08.116619 DQM0 = 10, DQM1 = 16
6560 11:08:08.117128 DQ Delay:
6561 11:08:08.119748 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6562 11:08:08.122794 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6563 11:08:08.125906 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6564 11:08:08.129391 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6565 11:08:08.129895
6566 11:08:08.130287
6567 11:08:08.130756 ==
6568 11:08:08.132799 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 11:08:08.136050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 11:08:08.136575 ==
6571 11:08:08.137005
6572 11:08:08.139509
6573 11:08:08.139908 TX Vref Scan disable
6574 11:08:08.142501 == TX Byte 0 ==
6575 11:08:08.145975 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6576 11:08:08.149424 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6577 11:08:08.152250 == TX Byte 1 ==
6578 11:08:08.155978 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6579 11:08:08.159128 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6580 11:08:08.159543 ==
6581 11:08:08.162327 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 11:08:08.165744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 11:08:08.169080 ==
6584 11:08:08.169501
6585 11:08:08.169937
6586 11:08:08.170364 TX Vref Scan disable
6587 11:08:08.172374 == TX Byte 0 ==
6588 11:08:08.175856 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6589 11:08:08.178868 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6590 11:08:08.182297 == TX Byte 1 ==
6591 11:08:08.185595 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6592 11:08:08.188794 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6593 11:08:08.189294
6594 11:08:08.189724 [DATLAT]
6595 11:08:08.192189 Freq=400, CH0 RK1
6596 11:08:08.192599
6597 11:08:08.195535 DATLAT Default: 0xe
6598 11:08:08.195924 0, 0xFFFF, sum = 0
6599 11:08:08.198481 1, 0xFFFF, sum = 0
6600 11:08:08.198866 2, 0xFFFF, sum = 0
6601 11:08:08.201789 3, 0xFFFF, sum = 0
6602 11:08:08.202199 4, 0xFFFF, sum = 0
6603 11:08:08.205161 5, 0xFFFF, sum = 0
6604 11:08:08.205548 6, 0xFFFF, sum = 0
6605 11:08:08.208338 7, 0xFFFF, sum = 0
6606 11:08:08.208775 8, 0xFFFF, sum = 0
6607 11:08:08.211760 9, 0xFFFF, sum = 0
6608 11:08:08.212148 10, 0xFFFF, sum = 0
6609 11:08:08.214940 11, 0xFFFF, sum = 0
6610 11:08:08.215326 12, 0xFFFF, sum = 0
6611 11:08:08.218354 13, 0x0, sum = 1
6612 11:08:08.218747 14, 0x0, sum = 2
6613 11:08:08.221826 15, 0x0, sum = 3
6614 11:08:08.222213 16, 0x0, sum = 4
6615 11:08:08.224910 best_step = 14
6616 11:08:08.225292
6617 11:08:08.225588 ==
6618 11:08:08.228173 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 11:08:08.231486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 11:08:08.231870 ==
6621 11:08:08.235518 RX Vref Scan: 0
6622 11:08:08.235901
6623 11:08:08.236202 RX Vref 0 -> 0, step: 1
6624 11:08:08.236477
6625 11:08:08.238634 RX Delay -359 -> 252, step: 8
6626 11:08:08.246265 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6627 11:08:08.249384 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6628 11:08:08.252860 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6629 11:08:08.259472 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6630 11:08:08.262851 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6631 11:08:08.265950 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6632 11:08:08.269439 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6633 11:08:08.275873 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6634 11:08:08.279190 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6635 11:08:08.282509 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6636 11:08:08.285758 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6637 11:08:08.292383 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6638 11:08:08.295930 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6639 11:08:08.299189 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6640 11:08:08.302629 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6641 11:08:08.309284 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6642 11:08:08.309664 ==
6643 11:08:08.312724 Dram Type= 6, Freq= 0, CH_0, rank 1
6644 11:08:08.315825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 11:08:08.316209 ==
6646 11:08:08.316504 DQS Delay:
6647 11:08:08.319257 DQS0 = 44, DQS1 = 60
6648 11:08:08.319679 DQM Delay:
6649 11:08:08.322228 DQM0 = 7, DQM1 = 14
6650 11:08:08.322605 DQ Delay:
6651 11:08:08.325473 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6652 11:08:08.328947 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6653 11:08:08.332276 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6654 11:08:08.335696 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6655 11:08:08.336082
6656 11:08:08.336380
6657 11:08:08.342218 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc48, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6658 11:08:08.345421 CH0 RK1: MR19=C0C, MR18=BC48
6659 11:08:08.352215 CH0_RK1: MR19=0xC0C, MR18=0xBC48, DQSOSC=386, MR23=63, INC=396, DEC=264
6660 11:08:08.355509 [RxdqsGatingPostProcess] freq 400
6661 11:08:08.361569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6662 11:08:08.364991 best DQS0 dly(2T, 0.5T) = (0, 10)
6663 11:08:08.368257 best DQS1 dly(2T, 0.5T) = (0, 10)
6664 11:08:08.371906 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6665 11:08:08.374824 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6666 11:08:08.378341 best DQS0 dly(2T, 0.5T) = (0, 10)
6667 11:08:08.378740 best DQS1 dly(2T, 0.5T) = (0, 10)
6668 11:08:08.381340 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6669 11:08:08.384566 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6670 11:08:08.388432 Pre-setting of DQS Precalculation
6671 11:08:08.394994 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6672 11:08:08.395377 ==
6673 11:08:08.397951 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 11:08:08.401240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 11:08:08.401624 ==
6676 11:08:08.407807 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 11:08:08.414434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6678 11:08:08.417762 [CA 0] Center 36 (8~64) winsize 57
6679 11:08:08.421210 [CA 1] Center 36 (8~64) winsize 57
6680 11:08:08.421594 [CA 2] Center 36 (8~64) winsize 57
6681 11:08:08.424792 [CA 3] Center 36 (8~64) winsize 57
6682 11:08:08.427907 [CA 4] Center 36 (8~64) winsize 57
6683 11:08:08.431120 [CA 5] Center 36 (8~64) winsize 57
6684 11:08:08.431687
6685 11:08:08.434667 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6686 11:08:08.437754
6687 11:08:08.440780 [CATrainingPosCal] consider 1 rank data
6688 11:08:08.441161 u2DelayCellTimex100 = 270/100 ps
6689 11:08:08.447849 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:08:08.450950 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:08:08.453945 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:08:08.457423 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:08:08.461233 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:08:08.463957 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:08:08.464337
6696 11:08:08.467554 CA PerBit enable=1, Macro0, CA PI delay=36
6697 11:08:08.467957
6698 11:08:08.470593 [CBTSetCACLKResult] CA Dly = 36
6699 11:08:08.474091 CS Dly: 1 (0~32)
6700 11:08:08.474474 ==
6701 11:08:08.477071 Dram Type= 6, Freq= 0, CH_1, rank 1
6702 11:08:08.480598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 11:08:08.480987 ==
6704 11:08:08.487143 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6705 11:08:08.493548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6706 11:08:08.493932 [CA 0] Center 36 (8~64) winsize 57
6707 11:08:08.497268 [CA 1] Center 36 (8~64) winsize 57
6708 11:08:08.500217 [CA 2] Center 36 (8~64) winsize 57
6709 11:08:08.503780 [CA 3] Center 36 (8~64) winsize 57
6710 11:08:08.507275 [CA 4] Center 36 (8~64) winsize 57
6711 11:08:08.510815 [CA 5] Center 36 (8~64) winsize 57
6712 11:08:08.511281
6713 11:08:08.513448 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6714 11:08:08.513822
6715 11:08:08.516964 [CATrainingPosCal] consider 2 rank data
6716 11:08:08.519885 u2DelayCellTimex100 = 270/100 ps
6717 11:08:08.523343 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:08:08.530167 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:08:08.533371 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:08:08.536803 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 11:08:08.540361 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 11:08:08.543245 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 11:08:08.543670
6724 11:08:08.546650 CA PerBit enable=1, Macro0, CA PI delay=36
6725 11:08:08.547026
6726 11:08:08.550073 [CBTSetCACLKResult] CA Dly = 36
6727 11:08:08.553536 CS Dly: 1 (0~32)
6728 11:08:08.554016
6729 11:08:08.556325 ----->DramcWriteLeveling(PI) begin...
6730 11:08:08.556708 ==
6731 11:08:08.559894 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 11:08:08.562882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 11:08:08.563261 ==
6734 11:08:08.566019 Write leveling (Byte 0): 40 => 8
6735 11:08:08.569394 Write leveling (Byte 1): 32 => 0
6736 11:08:08.573062 DramcWriteLeveling(PI) end<-----
6737 11:08:08.573440
6738 11:08:08.573730 ==
6739 11:08:08.576206 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 11:08:08.579717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 11:08:08.580100 ==
6742 11:08:08.582608 [Gating] SW mode calibration
6743 11:08:08.589152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6744 11:08:08.595951 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6745 11:08:08.599647 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6746 11:08:08.602466 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6747 11:08:08.609286 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 11:08:08.612198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 11:08:08.615695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 11:08:08.622614 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 11:08:08.625568 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 11:08:08.629061 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 11:08:08.635809 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6754 11:08:08.638745 Total UI for P1: 0, mck2ui 16
6755 11:08:08.641960 best dqsien dly found for B0: ( 0, 14, 24)
6756 11:08:08.642345 Total UI for P1: 0, mck2ui 16
6757 11:08:08.648584 best dqsien dly found for B1: ( 0, 14, 24)
6758 11:08:08.652275 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6759 11:08:08.655639 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6760 11:08:08.656022
6761 11:08:08.658419 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6762 11:08:08.661961 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6763 11:08:08.665261 [Gating] SW calibration Done
6764 11:08:08.665646 ==
6765 11:08:08.668416 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 11:08:08.671823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 11:08:08.672213 ==
6768 11:08:08.675008 RX Vref Scan: 0
6769 11:08:08.675390
6770 11:08:08.678574 RX Vref 0 -> 0, step: 1
6771 11:08:08.678963
6772 11:08:08.679261 RX Delay -410 -> 252, step: 16
6773 11:08:08.685030 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6774 11:08:08.688040 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6775 11:08:08.691775 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6776 11:08:08.698111 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6777 11:08:08.701138 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6778 11:08:08.704384 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6779 11:08:08.707886 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6780 11:08:08.714754 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6781 11:08:08.718044 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6782 11:08:08.721093 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6783 11:08:08.724589 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6784 11:08:08.730849 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6785 11:08:08.734427 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6786 11:08:08.737462 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6787 11:08:08.743909 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6788 11:08:08.747870 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6789 11:08:08.748339 ==
6790 11:08:08.751137 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 11:08:08.753847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 11:08:08.754233 ==
6793 11:08:08.756977 DQS Delay:
6794 11:08:08.757396 DQS0 = 43, DQS1 = 51
6795 11:08:08.757708 DQM Delay:
6796 11:08:08.760796 DQM0 = 12, DQM1 = 14
6797 11:08:08.761179 DQ Delay:
6798 11:08:08.763910 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6799 11:08:08.767536 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6800 11:08:08.770305 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6801 11:08:08.773878 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6802 11:08:08.774272
6803 11:08:08.774592
6804 11:08:08.774911 ==
6805 11:08:08.777147 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 11:08:08.780349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 11:08:08.783705 ==
6808 11:08:08.784137
6809 11:08:08.784443
6810 11:08:08.784721 TX Vref Scan disable
6811 11:08:08.786909 == TX Byte 0 ==
6812 11:08:08.790107 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 11:08:08.793675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 11:08:08.796936 == TX Byte 1 ==
6815 11:08:08.800689 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6816 11:08:08.803725 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6817 11:08:08.804253 ==
6818 11:08:08.806919 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 11:08:08.813658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 11:08:08.814075 ==
6821 11:08:08.814386
6822 11:08:08.814664
6823 11:08:08.814930 TX Vref Scan disable
6824 11:08:08.816598 == TX Byte 0 ==
6825 11:08:08.820063 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 11:08:08.823648 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 11:08:08.826583 == TX Byte 1 ==
6828 11:08:08.830018 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6829 11:08:08.833459 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6830 11:08:08.833844
6831 11:08:08.836575 [DATLAT]
6832 11:08:08.836958 Freq=400, CH1 RK0
6833 11:08:08.837260
6834 11:08:08.839473 DATLAT Default: 0xf
6835 11:08:08.839878 0, 0xFFFF, sum = 0
6836 11:08:08.842934 1, 0xFFFF, sum = 0
6837 11:08:08.843326 2, 0xFFFF, sum = 0
6838 11:08:08.846268 3, 0xFFFF, sum = 0
6839 11:08:08.846659 4, 0xFFFF, sum = 0
6840 11:08:08.849674 5, 0xFFFF, sum = 0
6841 11:08:08.852825 6, 0xFFFF, sum = 0
6842 11:08:08.853222 7, 0xFFFF, sum = 0
6843 11:08:08.856120 8, 0xFFFF, sum = 0
6844 11:08:08.856511 9, 0xFFFF, sum = 0
6845 11:08:08.859415 10, 0xFFFF, sum = 0
6846 11:08:08.859868 11, 0xFFFF, sum = 0
6847 11:08:08.863016 12, 0xFFFF, sum = 0
6848 11:08:08.863409 13, 0x0, sum = 1
6849 11:08:08.865764 14, 0x0, sum = 2
6850 11:08:08.866193 15, 0x0, sum = 3
6851 11:08:08.869545 16, 0x0, sum = 4
6852 11:08:08.869933 best_step = 14
6853 11:08:08.870233
6854 11:08:08.870525 ==
6855 11:08:08.872646 Dram Type= 6, Freq= 0, CH_1, rank 0
6856 11:08:08.875526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 11:08:08.879020 ==
6858 11:08:08.879406 RX Vref Scan: 1
6859 11:08:08.879753
6860 11:08:08.882483 RX Vref 0 -> 0, step: 1
6861 11:08:08.882868
6862 11:08:08.885699 RX Delay -343 -> 252, step: 8
6863 11:08:08.886086
6864 11:08:08.889101 Set Vref, RX VrefLevel [Byte0]: 50
6865 11:08:08.892424 [Byte1]: 61
6866 11:08:08.892810
6867 11:08:08.895302 Final RX Vref Byte 0 = 50 to rank0
6868 11:08:08.899230 Final RX Vref Byte 1 = 61 to rank0
6869 11:08:08.902522 Final RX Vref Byte 0 = 50 to rank1
6870 11:08:08.905855 Final RX Vref Byte 1 = 61 to rank1==
6871 11:08:08.908814 Dram Type= 6, Freq= 0, CH_1, rank 0
6872 11:08:08.912159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 11:08:08.912572 ==
6874 11:08:08.915768 DQS Delay:
6875 11:08:08.916152 DQS0 = 44, DQS1 = 56
6876 11:08:08.918878 DQM Delay:
6877 11:08:08.919276 DQM0 = 7, DQM1 = 12
6878 11:08:08.919636 DQ Delay:
6879 11:08:08.921889 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6880 11:08:08.925388 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6881 11:08:08.928701 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6882 11:08:08.932248 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6883 11:08:08.932631
6884 11:08:08.932930
6885 11:08:08.941874 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f74, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 389 ps
6886 11:08:08.944885 CH1 RK0: MR19=C0C, MR18=9F74
6887 11:08:08.948322 CH1_RK0: MR19=0xC0C, MR18=0x9F74, DQSOSC=389, MR23=63, INC=390, DEC=260
6888 11:08:08.951990 ==
6889 11:08:08.955362 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 11:08:08.958512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 11:08:08.958899 ==
6892 11:08:08.961792 [Gating] SW mode calibration
6893 11:08:08.968270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6894 11:08:08.971808 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6895 11:08:08.978695 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6896 11:08:08.981905 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6897 11:08:08.984877 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 11:08:08.991547 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 11:08:08.995002 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 11:08:08.998128 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 11:08:09.004641 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 11:08:09.008179 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 11:08:09.011122 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6904 11:08:09.014864 Total UI for P1: 0, mck2ui 16
6905 11:08:09.017814 best dqsien dly found for B0: ( 0, 14, 24)
6906 11:08:09.021396 Total UI for P1: 0, mck2ui 16
6907 11:08:09.024675 best dqsien dly found for B1: ( 0, 14, 24)
6908 11:08:09.027623 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6909 11:08:09.031207 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6910 11:08:09.031689
6911 11:08:09.037661 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6912 11:08:09.040858 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6913 11:08:09.044158 [Gating] SW calibration Done
6914 11:08:09.044535 ==
6915 11:08:09.047625 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 11:08:09.051067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 11:08:09.051493 ==
6918 11:08:09.051809 RX Vref Scan: 0
6919 11:08:09.052090
6920 11:08:09.054299 RX Vref 0 -> 0, step: 1
6921 11:08:09.054691
6922 11:08:09.057343 RX Delay -410 -> 252, step: 16
6923 11:08:09.060754 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6924 11:08:09.067137 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6925 11:08:09.070907 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6926 11:08:09.074500 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6927 11:08:09.077813 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6928 11:08:09.083899 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6929 11:08:09.087173 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6930 11:08:09.090342 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6931 11:08:09.094205 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6932 11:08:09.100606 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6933 11:08:09.103688 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6934 11:08:09.106963 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6935 11:08:09.110320 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6936 11:08:09.117515 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6937 11:08:09.120210 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6938 11:08:09.123804 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6939 11:08:09.124285 ==
6940 11:08:09.127111 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:08:09.133547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:08:09.133931 ==
6943 11:08:09.134225 DQS Delay:
6944 11:08:09.136411 DQS0 = 51, DQS1 = 59
6945 11:08:09.136789 DQM Delay:
6946 11:08:09.140177 DQM0 = 19, DQM1 = 22
6947 11:08:09.140556 DQ Delay:
6948 11:08:09.143471 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6949 11:08:09.146458 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6950 11:08:09.149599 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6951 11:08:09.152980 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6952 11:08:09.153365
6953 11:08:09.153664
6954 11:08:09.153936 ==
6955 11:08:09.156538 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 11:08:09.159342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 11:08:09.159774 ==
6958 11:08:09.160078
6959 11:08:09.160459
6960 11:08:09.163040 TX Vref Scan disable
6961 11:08:09.163423 == TX Byte 0 ==
6962 11:08:09.169619 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6963 11:08:09.172899 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6964 11:08:09.173301 == TX Byte 1 ==
6965 11:08:09.179311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6966 11:08:09.182590 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6967 11:08:09.182975 ==
6968 11:08:09.186035 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 11:08:09.189163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 11:08:09.189552 ==
6971 11:08:09.189852
6972 11:08:09.190166
6973 11:08:09.192678 TX Vref Scan disable
6974 11:08:09.195995 == TX Byte 0 ==
6975 11:08:09.199214 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6976 11:08:09.202424 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6977 11:08:09.202880 == TX Byte 1 ==
6978 11:08:09.209279 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6979 11:08:09.212735 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6980 11:08:09.213138
6981 11:08:09.213728 [DATLAT]
6982 11:08:09.215942 Freq=400, CH1 RK1
6983 11:08:09.216326
6984 11:08:09.216623 DATLAT Default: 0xe
6985 11:08:09.219204 0, 0xFFFF, sum = 0
6986 11:08:09.219663 1, 0xFFFF, sum = 0
6987 11:08:09.222877 2, 0xFFFF, sum = 0
6988 11:08:09.223271 3, 0xFFFF, sum = 0
6989 11:08:09.225740 4, 0xFFFF, sum = 0
6990 11:08:09.228962 5, 0xFFFF, sum = 0
6991 11:08:09.229353 6, 0xFFFF, sum = 0
6992 11:08:09.232444 7, 0xFFFF, sum = 0
6993 11:08:09.232855 8, 0xFFFF, sum = 0
6994 11:08:09.235343 9, 0xFFFF, sum = 0
6995 11:08:09.236127 10, 0xFFFF, sum = 0
6996 11:08:09.238901 11, 0xFFFF, sum = 0
6997 11:08:09.239336 12, 0xFFFF, sum = 0
6998 11:08:09.242413 13, 0x0, sum = 1
6999 11:08:09.242826 14, 0x0, sum = 2
7000 11:08:09.245532 15, 0x0, sum = 3
7001 11:08:09.245925 16, 0x0, sum = 4
7002 11:08:09.249061 best_step = 14
7003 11:08:09.249443
7004 11:08:09.249741 ==
7005 11:08:09.252318 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 11:08:09.255519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 11:08:09.255914 ==
7008 11:08:09.258543 RX Vref Scan: 0
7009 11:08:09.258926
7010 11:08:09.259222 RX Vref 0 -> 0, step: 1
7011 11:08:09.259543
7012 11:08:09.262258 RX Delay -359 -> 252, step: 8
7013 11:08:09.269610 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7014 11:08:09.272818 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7015 11:08:09.276287 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7016 11:08:09.282667 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7017 11:08:09.286036 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7018 11:08:09.289195 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7019 11:08:09.292759 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7020 11:08:09.296203 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7021 11:08:09.302525 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7022 11:08:09.305893 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7023 11:08:09.309342 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7024 11:08:09.315853 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
7025 11:08:09.319107 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
7026 11:08:09.322601 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7027 11:08:09.325630 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7028 11:08:09.332079 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7029 11:08:09.332470 ==
7030 11:08:09.335953 Dram Type= 6, Freq= 0, CH_1, rank 1
7031 11:08:09.339049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7032 11:08:09.339452 ==
7033 11:08:09.339756 DQS Delay:
7034 11:08:09.342060 DQS0 = 44, DQS1 = 60
7035 11:08:09.342444 DQM Delay:
7036 11:08:09.345133 DQM0 = 9, DQM1 = 14
7037 11:08:09.345529 DQ Delay:
7038 11:08:09.348569 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
7039 11:08:09.352090 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7040 11:08:09.355771 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7041 11:08:09.358909 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7042 11:08:09.359369
7043 11:08:09.359711
7044 11:08:09.364935 [DQSOSCAuto] RK1, (LSB)MR18= 0x7060, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7045 11:08:09.368723 CH1 RK1: MR19=C0C, MR18=7060
7046 11:08:09.374773 CH1_RK1: MR19=0xC0C, MR18=0x7060, DQSOSC=395, MR23=63, INC=378, DEC=252
7047 11:08:09.378234 [RxdqsGatingPostProcess] freq 400
7048 11:08:09.385328 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7049 11:08:09.388669 best DQS0 dly(2T, 0.5T) = (0, 10)
7050 11:08:09.391733 best DQS1 dly(2T, 0.5T) = (0, 10)
7051 11:08:09.394918 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7052 11:08:09.397876 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7053 11:08:09.401197 best DQS0 dly(2T, 0.5T) = (0, 10)
7054 11:08:09.401619 best DQS1 dly(2T, 0.5T) = (0, 10)
7055 11:08:09.404722 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7056 11:08:09.408046 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7057 11:08:09.411499 Pre-setting of DQS Precalculation
7058 11:08:09.417732 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7059 11:08:09.424748 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7060 11:08:09.431105 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7061 11:08:09.431538
7062 11:08:09.431847
7063 11:08:09.434429 [Calibration Summary] 800 Mbps
7064 11:08:09.434891 CH 0, Rank 0
7065 11:08:09.437723 SW Impedance : PASS
7066 11:08:09.441435 DUTY Scan : NO K
7067 11:08:09.441872 ZQ Calibration : PASS
7068 11:08:09.444580 Jitter Meter : NO K
7069 11:08:09.447693 CBT Training : PASS
7070 11:08:09.448078 Write leveling : PASS
7071 11:08:09.451008 RX DQS gating : PASS
7072 11:08:09.454473 RX DQ/DQS(RDDQC) : PASS
7073 11:08:09.454928 TX DQ/DQS : PASS
7074 11:08:09.457726 RX DATLAT : PASS
7075 11:08:09.461412 RX DQ/DQS(Engine): PASS
7076 11:08:09.461926 TX OE : NO K
7077 11:08:09.464658 All Pass.
7078 11:08:09.465103
7079 11:08:09.465438 CH 0, Rank 1
7080 11:08:09.467496 SW Impedance : PASS
7081 11:08:09.467961 DUTY Scan : NO K
7082 11:08:09.470981 ZQ Calibration : PASS
7083 11:08:09.473929 Jitter Meter : NO K
7084 11:08:09.474377 CBT Training : PASS
7085 11:08:09.477236 Write leveling : NO K
7086 11:08:09.480785 RX DQS gating : PASS
7087 11:08:09.481213 RX DQ/DQS(RDDQC) : PASS
7088 11:08:09.483703 TX DQ/DQS : PASS
7089 11:08:09.487504 RX DATLAT : PASS
7090 11:08:09.487893 RX DQ/DQS(Engine): PASS
7091 11:08:09.490737 TX OE : NO K
7092 11:08:09.491124 All Pass.
7093 11:08:09.491458
7094 11:08:09.491760 CH 1, Rank 0
7095 11:08:09.494523 SW Impedance : PASS
7096 11:08:09.497190 DUTY Scan : NO K
7097 11:08:09.497578 ZQ Calibration : PASS
7098 11:08:09.500497 Jitter Meter : NO K
7099 11:08:09.504099 CBT Training : PASS
7100 11:08:09.504481 Write leveling : PASS
7101 11:08:09.507116 RX DQS gating : PASS
7102 11:08:09.510234 RX DQ/DQS(RDDQC) : PASS
7103 11:08:09.510612 TX DQ/DQS : PASS
7104 11:08:09.513807 RX DATLAT : PASS
7105 11:08:09.517333 RX DQ/DQS(Engine): PASS
7106 11:08:09.517735 TX OE : NO K
7107 11:08:09.520239 All Pass.
7108 11:08:09.520618
7109 11:08:09.520918 CH 1, Rank 1
7110 11:08:09.523745 SW Impedance : PASS
7111 11:08:09.524130 DUTY Scan : NO K
7112 11:08:09.527076 ZQ Calibration : PASS
7113 11:08:09.530399 Jitter Meter : NO K
7114 11:08:09.530800 CBT Training : PASS
7115 11:08:09.533520 Write leveling : NO K
7116 11:08:09.536977 RX DQS gating : PASS
7117 11:08:09.537394 RX DQ/DQS(RDDQC) : PASS
7118 11:08:09.540359 TX DQ/DQS : PASS
7119 11:08:09.543590 RX DATLAT : PASS
7120 11:08:09.543687 RX DQ/DQS(Engine): PASS
7121 11:08:09.546303 TX OE : NO K
7122 11:08:09.546395 All Pass.
7123 11:08:09.546475
7124 11:08:09.549641 DramC Write-DBI off
7125 11:08:09.553346 PER_BANK_REFRESH: Hybrid Mode
7126 11:08:09.553420 TX_TRACKING: ON
7127 11:08:09.563193 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7128 11:08:09.566352 [FAST_K] Save calibration result to emmc
7129 11:08:09.569630 dramc_set_vcore_voltage set vcore to 725000
7130 11:08:09.573107 Read voltage for 1600, 0
7131 11:08:09.573182 Vio18 = 0
7132 11:08:09.573240 Vcore = 725000
7133 11:08:09.576137 Vdram = 0
7134 11:08:09.576220 Vddq = 0
7135 11:08:09.576279 Vmddr = 0
7136 11:08:09.582526 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7137 11:08:09.586474 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7138 11:08:09.589625 MEM_TYPE=3, freq_sel=13
7139 11:08:09.593110 sv_algorithm_assistance_LP4_3733
7140 11:08:09.596078 ============ PULL DRAM RESETB DOWN ============
7141 11:08:09.599338 ========== PULL DRAM RESETB DOWN end =========
7142 11:08:09.605880 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7143 11:08:09.609061 ===================================
7144 11:08:09.612542 LPDDR4 DRAM CONFIGURATION
7145 11:08:09.615935 ===================================
7146 11:08:09.616012 EX_ROW_EN[0] = 0x0
7147 11:08:09.618900 EX_ROW_EN[1] = 0x0
7148 11:08:09.618976 LP4Y_EN = 0x0
7149 11:08:09.622235 WORK_FSP = 0x1
7150 11:08:09.622312 WL = 0x5
7151 11:08:09.626217 RL = 0x5
7152 11:08:09.626294 BL = 0x2
7153 11:08:09.628962 RPST = 0x0
7154 11:08:09.629038 RD_PRE = 0x0
7155 11:08:09.632286 WR_PRE = 0x1
7156 11:08:09.632362 WR_PST = 0x1
7157 11:08:09.635728 DBI_WR = 0x0
7158 11:08:09.635805 DBI_RD = 0x0
7159 11:08:09.639238 OTF = 0x1
7160 11:08:09.642504 ===================================
7161 11:08:09.645941 ===================================
7162 11:08:09.646019 ANA top config
7163 11:08:09.648646 ===================================
7164 11:08:09.651948 DLL_ASYNC_EN = 0
7165 11:08:09.655661 ALL_SLAVE_EN = 0
7166 11:08:09.658502 NEW_RANK_MODE = 1
7167 11:08:09.662173 DLL_IDLE_MODE = 1
7168 11:08:09.662571 LP45_APHY_COMB_EN = 1
7169 11:08:09.665779 TX_ODT_DIS = 0
7170 11:08:09.669083 NEW_8X_MODE = 1
7171 11:08:09.672360 ===================================
7172 11:08:09.675599 ===================================
7173 11:08:09.678903 data_rate = 3200
7174 11:08:09.682435 CKR = 1
7175 11:08:09.682834 DQ_P2S_RATIO = 8
7176 11:08:09.685636 ===================================
7177 11:08:09.688929 CA_P2S_RATIO = 8
7178 11:08:09.692223 DQ_CA_OPEN = 0
7179 11:08:09.695226 DQ_SEMI_OPEN = 0
7180 11:08:09.698903 CA_SEMI_OPEN = 0
7181 11:08:09.702203 CA_FULL_RATE = 0
7182 11:08:09.702605 DQ_CKDIV4_EN = 0
7183 11:08:09.705706 CA_CKDIV4_EN = 0
7184 11:08:09.708385 CA_PREDIV_EN = 0
7185 11:08:09.711719 PH8_DLY = 12
7186 11:08:09.715261 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7187 11:08:09.718673 DQ_AAMCK_DIV = 4
7188 11:08:09.719070 CA_AAMCK_DIV = 4
7189 11:08:09.721773 CA_ADMCK_DIV = 4
7190 11:08:09.725287 DQ_TRACK_CA_EN = 0
7191 11:08:09.728299 CA_PICK = 1600
7192 11:08:09.731770 CA_MCKIO = 1600
7193 11:08:09.734881 MCKIO_SEMI = 0
7194 11:08:09.738092 PLL_FREQ = 3068
7195 11:08:09.741525 DQ_UI_PI_RATIO = 32
7196 11:08:09.741926 CA_UI_PI_RATIO = 0
7197 11:08:09.745170 ===================================
7198 11:08:09.748718 ===================================
7199 11:08:09.751625 memory_type:LPDDR4
7200 11:08:09.754555 GP_NUM : 10
7201 11:08:09.754984 SRAM_EN : 1
7202 11:08:09.757725 MD32_EN : 0
7203 11:08:09.761519 ===================================
7204 11:08:09.764648 [ANA_INIT] >>>>>>>>>>>>>>
7205 11:08:09.768025 <<<<<< [CONFIGURE PHASE]: ANA_TX
7206 11:08:09.771332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7207 11:08:09.774440 ===================================
7208 11:08:09.774835 data_rate = 3200,PCW = 0X7600
7209 11:08:09.777815 ===================================
7210 11:08:09.784420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7211 11:08:09.787694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7212 11:08:09.794266 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7213 11:08:09.797464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7214 11:08:09.800987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7215 11:08:09.804302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7216 11:08:09.807825 [ANA_INIT] flow start
7217 11:08:09.810537 [ANA_INIT] PLL >>>>>>>>
7218 11:08:09.810921 [ANA_INIT] PLL <<<<<<<<
7219 11:08:09.814116 [ANA_INIT] MIDPI >>>>>>>>
7220 11:08:09.817343 [ANA_INIT] MIDPI <<<<<<<<
7221 11:08:09.817772 [ANA_INIT] DLL >>>>>>>>
7222 11:08:09.820591 [ANA_INIT] DLL <<<<<<<<
7223 11:08:09.824101 [ANA_INIT] flow end
7224 11:08:09.827582 ============ LP4 DIFF to SE enter ============
7225 11:08:09.831273 ============ LP4 DIFF to SE exit ============
7226 11:08:09.834356 [ANA_INIT] <<<<<<<<<<<<<
7227 11:08:09.837323 [Flow] Enable top DCM control >>>>>
7228 11:08:09.840536 [Flow] Enable top DCM control <<<<<
7229 11:08:09.843775 Enable DLL master slave shuffle
7230 11:08:09.847483 ==============================================================
7231 11:08:09.850483 Gating Mode config
7232 11:08:09.857394 ==============================================================
7233 11:08:09.857783 Config description:
7234 11:08:09.867211 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7235 11:08:09.873947 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7236 11:08:09.880471 SELPH_MODE 0: By rank 1: By Phase
7237 11:08:09.883529 ==============================================================
7238 11:08:09.886714 GAT_TRACK_EN = 1
7239 11:08:09.890076 RX_GATING_MODE = 2
7240 11:08:09.893800 RX_GATING_TRACK_MODE = 2
7241 11:08:09.897330 SELPH_MODE = 1
7242 11:08:09.900327 PICG_EARLY_EN = 1
7243 11:08:09.904006 VALID_LAT_VALUE = 1
7244 11:08:09.906819 ==============================================================
7245 11:08:09.910287 Enter into Gating configuration >>>>
7246 11:08:09.913617 Exit from Gating configuration <<<<
7247 11:08:09.916728 Enter into DVFS_PRE_config >>>>>
7248 11:08:09.929774 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7249 11:08:09.933270 Exit from DVFS_PRE_config <<<<<
7250 11:08:09.936842 Enter into PICG configuration >>>>
7251 11:08:09.939724 Exit from PICG configuration <<<<
7252 11:08:09.940111 [RX_INPUT] configuration >>>>>
7253 11:08:09.943279 [RX_INPUT] configuration <<<<<
7254 11:08:09.949704 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7255 11:08:09.953247 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7256 11:08:09.959841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7257 11:08:09.966559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7258 11:08:09.972877 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7259 11:08:09.979371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7260 11:08:09.982895 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7261 11:08:09.986172 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7262 11:08:09.992577 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7263 11:08:09.995630 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7264 11:08:09.998941 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7265 11:08:10.005359 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7266 11:08:10.009195 ===================================
7267 11:08:10.009608 LPDDR4 DRAM CONFIGURATION
7268 11:08:10.012101 ===================================
7269 11:08:10.015492 EX_ROW_EN[0] = 0x0
7270 11:08:10.015899 EX_ROW_EN[1] = 0x0
7271 11:08:10.019285 LP4Y_EN = 0x0
7272 11:08:10.019759 WORK_FSP = 0x1
7273 11:08:10.022269 WL = 0x5
7274 11:08:10.025529 RL = 0x5
7275 11:08:10.025925 BL = 0x2
7276 11:08:10.028893 RPST = 0x0
7277 11:08:10.029293 RD_PRE = 0x0
7278 11:08:10.031843 WR_PRE = 0x1
7279 11:08:10.032229 WR_PST = 0x1
7280 11:08:10.035200 DBI_WR = 0x0
7281 11:08:10.035696 DBI_RD = 0x0
7282 11:08:10.038877 OTF = 0x1
7283 11:08:10.041709 ===================================
7284 11:08:10.045228 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7285 11:08:10.048483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7286 11:08:10.055893 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7287 11:08:10.058336 ===================================
7288 11:08:10.058717 LPDDR4 DRAM CONFIGURATION
7289 11:08:10.061979 ===================================
7290 11:08:10.064962 EX_ROW_EN[0] = 0x10
7291 11:08:10.065417 EX_ROW_EN[1] = 0x0
7292 11:08:10.068766 LP4Y_EN = 0x0
7293 11:08:10.069146 WORK_FSP = 0x1
7294 11:08:10.071841 WL = 0x5
7295 11:08:10.075094 RL = 0x5
7296 11:08:10.075661 BL = 0x2
7297 11:08:10.078382 RPST = 0x0
7298 11:08:10.078932 RD_PRE = 0x0
7299 11:08:10.081498 WR_PRE = 0x1
7300 11:08:10.081892 WR_PST = 0x1
7301 11:08:10.084840 DBI_WR = 0x0
7302 11:08:10.085263 DBI_RD = 0x0
7303 11:08:10.088488 OTF = 0x1
7304 11:08:10.091544 ===================================
7305 11:08:10.098318 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7306 11:08:10.098706 ==
7307 11:08:10.101767 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 11:08:10.104536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 11:08:10.104919 ==
7310 11:08:10.107735 [Duty_Offset_Calibration]
7311 11:08:10.108158 B0:1 B1:-1 CA:0
7312 11:08:10.108549
7313 11:08:10.111589 [DutyScan_Calibration_Flow] k_type=0
7314 11:08:10.121565
7315 11:08:10.122063 ==CLK 0==
7316 11:08:10.124766 Final CLK duty delay cell = 0
7317 11:08:10.128391 [0] MAX Duty = 5124%(X100), DQS PI = 22
7318 11:08:10.131537 [0] MIN Duty = 4907%(X100), DQS PI = 4
7319 11:08:10.132000 [0] AVG Duty = 5015%(X100)
7320 11:08:10.134705
7321 11:08:10.138055 CH0 CLK Duty spec in!! Max-Min= 217%
7322 11:08:10.141602 [DutyScan_Calibration_Flow] ====Done====
7323 11:08:10.141985
7324 11:08:10.144414 [DutyScan_Calibration_Flow] k_type=1
7325 11:08:10.161037
7326 11:08:10.161462 ==DQS 0 ==
7327 11:08:10.164335 Final DQS duty delay cell = -4
7328 11:08:10.167076 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7329 11:08:10.170755 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7330 11:08:10.173614 [-4] AVG Duty = 4906%(X100)
7331 11:08:10.174056
7332 11:08:10.174383 ==DQS 1 ==
7333 11:08:10.177427 Final DQS duty delay cell = 0
7334 11:08:10.180300 [0] MAX Duty = 5156%(X100), DQS PI = 2
7335 11:08:10.183498 [0] MIN Duty = 5000%(X100), DQS PI = 18
7336 11:08:10.186984 [0] AVG Duty = 5078%(X100)
7337 11:08:10.187362
7338 11:08:10.190162 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7339 11:08:10.190553
7340 11:08:10.194136 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7341 11:08:10.197098 [DutyScan_Calibration_Flow] ====Done====
7342 11:08:10.197477
7343 11:08:10.200229 [DutyScan_Calibration_Flow] k_type=3
7344 11:08:10.218373
7345 11:08:10.218754 ==DQM 0 ==
7346 11:08:10.221579 Final DQM duty delay cell = 0
7347 11:08:10.225207 [0] MAX Duty = 5093%(X100), DQS PI = 20
7348 11:08:10.228287 [0] MIN Duty = 4876%(X100), DQS PI = 12
7349 11:08:10.231298 [0] AVG Duty = 4984%(X100)
7350 11:08:10.231866
7351 11:08:10.232214 ==DQM 1 ==
7352 11:08:10.234895 Final DQM duty delay cell = 0
7353 11:08:10.238142 [0] MAX Duty = 5000%(X100), DQS PI = 10
7354 11:08:10.241758 [0] MIN Duty = 4782%(X100), DQS PI = 20
7355 11:08:10.244513 [0] AVG Duty = 4891%(X100)
7356 11:08:10.244945
7357 11:08:10.247820 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7358 11:08:10.248221
7359 11:08:10.250873 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7360 11:08:10.254722 [DutyScan_Calibration_Flow] ====Done====
7361 11:08:10.255104
7362 11:08:10.257534 [DutyScan_Calibration_Flow] k_type=2
7363 11:08:10.274899
7364 11:08:10.275326 ==DQ 0 ==
7365 11:08:10.278107 Final DQ duty delay cell = -4
7366 11:08:10.281116 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7367 11:08:10.284468 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7368 11:08:10.288012 [-4] AVG Duty = 4953%(X100)
7369 11:08:10.288417
7370 11:08:10.288706 ==DQ 1 ==
7371 11:08:10.291262 Final DQ duty delay cell = 0
7372 11:08:10.294639 [0] MAX Duty = 5125%(X100), DQS PI = 2
7373 11:08:10.298075 [0] MIN Duty = 5000%(X100), DQS PI = 34
7374 11:08:10.300995 [0] AVG Duty = 5062%(X100)
7375 11:08:10.301615
7376 11:08:10.304346 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7377 11:08:10.304933
7378 11:08:10.307879 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7379 11:08:10.310884 [DutyScan_Calibration_Flow] ====Done====
7380 11:08:10.311313 ==
7381 11:08:10.314235 Dram Type= 6, Freq= 0, CH_1, rank 0
7382 11:08:10.317811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7383 11:08:10.318422 ==
7384 11:08:10.320830 [Duty_Offset_Calibration]
7385 11:08:10.321213 B0:-1 B1:1 CA:2
7386 11:08:10.321558
7387 11:08:10.323976 [DutyScan_Calibration_Flow] k_type=0
7388 11:08:10.335012
7389 11:08:10.335391 ==CLK 0==
7390 11:08:10.338285 Final CLK duty delay cell = 0
7391 11:08:10.341790 [0] MAX Duty = 5187%(X100), DQS PI = 22
7392 11:08:10.345485 [0] MIN Duty = 4969%(X100), DQS PI = 0
7393 11:08:10.345871 [0] AVG Duty = 5078%(X100)
7394 11:08:10.348568
7395 11:08:10.351498 CH1 CLK Duty spec in!! Max-Min= 218%
7396 11:08:10.355171 [DutyScan_Calibration_Flow] ====Done====
7397 11:08:10.355595
7398 11:08:10.358211 [DutyScan_Calibration_Flow] k_type=1
7399 11:08:10.374668
7400 11:08:10.375142 ==DQS 0 ==
7401 11:08:10.378388 Final DQS duty delay cell = 0
7402 11:08:10.381771 [0] MAX Duty = 5124%(X100), DQS PI = 18
7403 11:08:10.384620 [0] MIN Duty = 4907%(X100), DQS PI = 8
7404 11:08:10.388304 [0] AVG Duty = 5015%(X100)
7405 11:08:10.388748
7406 11:08:10.389056 ==DQS 1 ==
7407 11:08:10.391314 Final DQS duty delay cell = 0
7408 11:08:10.394617 [0] MAX Duty = 5093%(X100), DQS PI = 26
7409 11:08:10.398010 [0] MIN Duty = 4969%(X100), DQS PI = 54
7410 11:08:10.401333 [0] AVG Duty = 5031%(X100)
7411 11:08:10.401713
7412 11:08:10.404225 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7413 11:08:10.404606
7414 11:08:10.407693 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7415 11:08:10.411192 [DutyScan_Calibration_Flow] ====Done====
7416 11:08:10.411681
7417 11:08:10.414524 [DutyScan_Calibration_Flow] k_type=3
7418 11:08:10.431518
7419 11:08:10.431946 ==DQM 0 ==
7420 11:08:10.434694 Final DQM duty delay cell = 0
7421 11:08:10.438003 [0] MAX Duty = 5218%(X100), DQS PI = 18
7422 11:08:10.441414 [0] MIN Duty = 5000%(X100), DQS PI = 8
7423 11:08:10.445059 [0] AVG Duty = 5109%(X100)
7424 11:08:10.445439
7425 11:08:10.445731 ==DQM 1 ==
7426 11:08:10.447948 Final DQM duty delay cell = 0
7427 11:08:10.451413 [0] MAX Duty = 5156%(X100), DQS PI = 6
7428 11:08:10.454586 [0] MIN Duty = 4938%(X100), DQS PI = 34
7429 11:08:10.458147 [0] AVG Duty = 5047%(X100)
7430 11:08:10.458535
7431 11:08:10.461063 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7432 11:08:10.461446
7433 11:08:10.464417 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7434 11:08:10.467959 [DutyScan_Calibration_Flow] ====Done====
7435 11:08:10.468343
7436 11:08:10.471228 [DutyScan_Calibration_Flow] k_type=2
7437 11:08:10.488170
7438 11:08:10.488579 ==DQ 0 ==
7439 11:08:10.491735 Final DQ duty delay cell = 0
7440 11:08:10.495084 [0] MAX Duty = 5156%(X100), DQS PI = 30
7441 11:08:10.498383 [0] MIN Duty = 4906%(X100), DQS PI = 8
7442 11:08:10.498764 [0] AVG Duty = 5031%(X100)
7443 11:08:10.501542
7444 11:08:10.502014 ==DQ 1 ==
7445 11:08:10.504734 Final DQ duty delay cell = 0
7446 11:08:10.508313 [0] MAX Duty = 5156%(X100), DQS PI = 8
7447 11:08:10.511852 [0] MIN Duty = 4969%(X100), DQS PI = 54
7448 11:08:10.512320 [0] AVG Duty = 5062%(X100)
7449 11:08:10.514428
7450 11:08:10.517846 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7451 11:08:10.518227
7452 11:08:10.521367 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7453 11:08:10.524464 [DutyScan_Calibration_Flow] ====Done====
7454 11:08:10.528386 nWR fixed to 30
7455 11:08:10.528764 [ModeRegInit_LP4] CH0 RK0
7456 11:08:10.531083 [ModeRegInit_LP4] CH0 RK1
7457 11:08:10.534325 [ModeRegInit_LP4] CH1 RK0
7458 11:08:10.538145 [ModeRegInit_LP4] CH1 RK1
7459 11:08:10.538521 match AC timing 5
7460 11:08:10.544302 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7461 11:08:10.547773 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7462 11:08:10.550965 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7463 11:08:10.557413 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7464 11:08:10.560578 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7465 11:08:10.561092 [MiockJmeterHQA]
7466 11:08:10.561464
7467 11:08:10.563916 [DramcMiockJmeter] u1RxGatingPI = 0
7468 11:08:10.567267 0 : 4363, 4138
7469 11:08:10.567760 4 : 4255, 4029
7470 11:08:10.570959 8 : 4365, 4140
7471 11:08:10.571337 12 : 4258, 4029
7472 11:08:10.573894 16 : 4255, 4030
7473 11:08:10.574293 20 : 4363, 4137
7474 11:08:10.574655 24 : 4255, 4030
7475 11:08:10.577645 28 : 4255, 4029
7476 11:08:10.577968 32 : 4253, 4027
7477 11:08:10.580771 36 : 4252, 4027
7478 11:08:10.581164 40 : 4368, 4140
7479 11:08:10.583936 44 : 4252, 4026
7480 11:08:10.584398 48 : 4252, 4027
7481 11:08:10.587336 52 : 4252, 4026
7482 11:08:10.587819 56 : 4255, 4030
7483 11:08:10.588173 60 : 4255, 4030
7484 11:08:10.590587 64 : 4361, 4137
7485 11:08:10.591048 68 : 4360, 4138
7486 11:08:10.593766 72 : 4363, 4140
7487 11:08:10.594179 76 : 4255, 4029
7488 11:08:10.596925 80 : 4252, 4030
7489 11:08:10.597416 84 : 4252, 4030
7490 11:08:10.600544 88 : 4250, 4027
7491 11:08:10.600930 92 : 4365, 896
7492 11:08:10.601230 96 : 4252, 0
7493 11:08:10.603499 100 : 4363, 0
7494 11:08:10.603955 104 : 4360, 0
7495 11:08:10.604258 108 : 4363, 0
7496 11:08:10.607066 112 : 4249, 0
7497 11:08:10.607494 116 : 4250, 0
7498 11:08:10.610266 120 : 4250, 0
7499 11:08:10.610653 124 : 4250, 0
7500 11:08:10.610950 128 : 4250, 0
7501 11:08:10.613769 132 : 4360, 0
7502 11:08:10.614286 136 : 4250, 0
7503 11:08:10.616958 140 : 4250, 0
7504 11:08:10.617342 144 : 4249, 0
7505 11:08:10.617643 148 : 4255, 0
7506 11:08:10.620379 152 : 4361, 0
7507 11:08:10.620869 156 : 4250, 0
7508 11:08:10.623193 160 : 4360, 0
7509 11:08:10.623624 164 : 4250, 0
7510 11:08:10.623979 168 : 4250, 0
7511 11:08:10.626859 172 : 4250, 0
7512 11:08:10.627458 176 : 4249, 0
7513 11:08:10.630027 180 : 4250, 0
7514 11:08:10.630515 184 : 4250, 0
7515 11:08:10.630899 188 : 4252, 0
7516 11:08:10.633668 192 : 4250, 0
7517 11:08:10.634052 196 : 4250, 0
7518 11:08:10.634353 200 : 4252, 0
7519 11:08:10.636993 204 : 4361, 0
7520 11:08:10.637380 208 : 4250, 0
7521 11:08:10.640010 212 : 4360, 0
7522 11:08:10.640424 216 : 4250, 0
7523 11:08:10.640733 220 : 4250, 0
7524 11:08:10.643280 224 : 4360, 189
7525 11:08:10.643708 228 : 4250, 2927
7526 11:08:10.646753 232 : 4250, 4027
7527 11:08:10.647148 236 : 4254, 4032
7528 11:08:10.649675 240 : 4250, 4027
7529 11:08:10.650084 244 : 4250, 4027
7530 11:08:10.653408 248 : 4250, 4027
7531 11:08:10.653818 252 : 4250, 4027
7532 11:08:10.656475 256 : 4250, 4027
7533 11:08:10.656869 260 : 4250, 4027
7534 11:08:10.659988 264 : 4250, 4027
7535 11:08:10.660535 268 : 4253, 4029
7536 11:08:10.663315 272 : 4252, 4027
7537 11:08:10.663720 276 : 4252, 4029
7538 11:08:10.664057 280 : 4249, 4027
7539 11:08:10.666648 284 : 4250, 4027
7540 11:08:10.666993 288 : 4363, 4139
7541 11:08:10.669799 292 : 4250, 4026
7542 11:08:10.670188 296 : 4252, 4030
7543 11:08:10.673239 300 : 4361, 4138
7544 11:08:10.673622 304 : 4250, 4026
7545 11:08:10.676173 308 : 4250, 4027
7546 11:08:10.676560 312 : 4361, 4137
7547 11:08:10.679539 316 : 4362, 4137
7548 11:08:10.679922 320 : 4250, 4026
7549 11:08:10.683077 324 : 4250, 4027
7550 11:08:10.683502 328 : 4252, 4029
7551 11:08:10.686550 332 : 4250, 4027
7552 11:08:10.686933 336 : 4249, 3963
7553 11:08:10.687234 340 : 4363, 2371
7554 11:08:10.689492 344 : 4252, 63
7555 11:08:10.689876
7556 11:08:10.692838 MIOCK jitter meter ch=0
7557 11:08:10.693213
7558 11:08:10.693507 1T = (344-92) = 252 dly cells
7559 11:08:10.699281 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7560 11:08:10.699741 ==
7561 11:08:10.702710 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 11:08:10.706065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 11:08:10.709895 ==
7564 11:08:10.712642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7565 11:08:10.716503 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7566 11:08:10.723066 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7567 11:08:10.729875 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7568 11:08:10.736639 [CA 0] Center 43 (13~74) winsize 62
7569 11:08:10.740337 [CA 1] Center 43 (13~74) winsize 62
7570 11:08:10.743231 [CA 2] Center 39 (10~69) winsize 60
7571 11:08:10.746313 [CA 3] Center 38 (9~68) winsize 60
7572 11:08:10.749682 [CA 4] Center 37 (8~66) winsize 59
7573 11:08:10.753286 [CA 5] Center 36 (7~66) winsize 60
7574 11:08:10.753668
7575 11:08:10.756246 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7576 11:08:10.756626
7577 11:08:10.762774 [CATrainingPosCal] consider 1 rank data
7578 11:08:10.763155 u2DelayCellTimex100 = 258/100 ps
7579 11:08:10.769984 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7580 11:08:10.772802 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7581 11:08:10.776337 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7582 11:08:10.779766 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7583 11:08:10.782939 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7584 11:08:10.786002 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7585 11:08:10.786381
7586 11:08:10.789292 CA PerBit enable=1, Macro0, CA PI delay=36
7587 11:08:10.789682
7588 11:08:10.792561 [CBTSetCACLKResult] CA Dly = 36
7589 11:08:10.796037 CS Dly: 11 (0~42)
7590 11:08:10.799471 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7591 11:08:10.802834 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7592 11:08:10.803215 ==
7593 11:08:10.805938 Dram Type= 6, Freq= 0, CH_0, rank 1
7594 11:08:10.812326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 11:08:10.812714 ==
7596 11:08:10.815767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7597 11:08:10.822440 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7598 11:08:10.825561 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7599 11:08:10.832191 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7600 11:08:10.840402 [CA 0] Center 42 (12~73) winsize 62
7601 11:08:10.843415 [CA 1] Center 43 (13~73) winsize 61
7602 11:08:10.847252 [CA 2] Center 37 (8~67) winsize 60
7603 11:08:10.850554 [CA 3] Center 37 (7~67) winsize 61
7604 11:08:10.853954 [CA 4] Center 36 (6~66) winsize 61
7605 11:08:10.857143 [CA 5] Center 35 (5~65) winsize 61
7606 11:08:10.857522
7607 11:08:10.860205 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7608 11:08:10.860586
7609 11:08:10.863527 [CATrainingPosCal] consider 2 rank data
7610 11:08:10.866966 u2DelayCellTimex100 = 258/100 ps
7611 11:08:10.873381 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7612 11:08:10.876731 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7613 11:08:10.879812 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7614 11:08:10.883512 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7615 11:08:10.886723 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7616 11:08:10.890169 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7617 11:08:10.890696
7618 11:08:10.892988 CA PerBit enable=1, Macro0, CA PI delay=36
7619 11:08:10.893368
7620 11:08:10.896495 [CBTSetCACLKResult] CA Dly = 36
7621 11:08:10.899556 CS Dly: 11 (0~43)
7622 11:08:10.903169 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7623 11:08:10.906114 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7624 11:08:10.906489
7625 11:08:10.909592 ----->DramcWriteLeveling(PI) begin...
7626 11:08:10.909976 ==
7627 11:08:10.912886 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 11:08:10.919379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 11:08:10.919786 ==
7630 11:08:10.922665 Write leveling (Byte 0): 36 => 36
7631 11:08:10.926109 Write leveling (Byte 1): 28 => 28
7632 11:08:10.929592 DramcWriteLeveling(PI) end<-----
7633 11:08:10.929969
7634 11:08:10.930260 ==
7635 11:08:10.932435 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 11:08:10.935874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 11:08:10.936334 ==
7638 11:08:10.939277 [Gating] SW mode calibration
7639 11:08:10.946157 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7640 11:08:10.953010 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7641 11:08:10.955676 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 11:08:10.958873 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 11:08:10.965912 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 11:08:10.969052 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7645 11:08:10.972314 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7646 11:08:10.979008 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7647 11:08:10.982314 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7648 11:08:10.985485 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 11:08:10.991887 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 11:08:10.995502 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 11:08:10.998776 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 11:08:11.004980 1 5 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7653 11:08:11.008696 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7654 11:08:11.011616 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7655 11:08:11.018470 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7656 11:08:11.021431 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 11:08:11.025115 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 11:08:11.031593 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 11:08:11.034749 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 11:08:11.038350 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7661 11:08:11.045053 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7662 11:08:11.048173 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7663 11:08:11.050931 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7664 11:08:11.058314 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 11:08:11.060866 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 11:08:11.064252 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 11:08:11.070984 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7668 11:08:11.074254 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7669 11:08:11.077633 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7670 11:08:11.084163 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7671 11:08:11.087543 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 11:08:11.090646 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 11:08:11.097517 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 11:08:11.100869 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 11:08:11.104281 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 11:08:11.110703 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 11:08:11.114151 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 11:08:11.117061 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 11:08:11.120391 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 11:08:11.127163 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 11:08:11.130613 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 11:08:11.133957 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 11:08:11.140274 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 11:08:11.143633 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7685 11:08:11.147164 Total UI for P1: 0, mck2ui 16
7686 11:08:11.150010 best dqsien dly found for B0: ( 1, 9, 10)
7687 11:08:11.153388 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7688 11:08:11.160011 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7689 11:08:11.163390 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 11:08:11.167117 Total UI for P1: 0, mck2ui 16
7691 11:08:11.169985 best dqsien dly found for B1: ( 1, 9, 18)
7692 11:08:11.173304 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7693 11:08:11.176952 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7694 11:08:11.177479
7695 11:08:11.179974 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7696 11:08:11.186313 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7697 11:08:11.186848 [Gating] SW calibration Done
7698 11:08:11.187314 ==
7699 11:08:11.190008 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 11:08:11.200775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 11:08:11.201165 ==
7702 11:08:11.201460 RX Vref Scan: 0
7703 11:08:11.201736
7704 11:08:11.201996 RX Vref 0 -> 0, step: 1
7705 11:08:11.202252
7706 11:08:11.203187 RX Delay 0 -> 252, step: 8
7707 11:08:11.206413 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7708 11:08:11.209800 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7709 11:08:11.212732 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7710 11:08:11.219540 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7711 11:08:11.222650 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7712 11:08:11.226363 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7713 11:08:11.229572 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7714 11:08:11.232639 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7715 11:08:11.239708 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7716 11:08:11.242704 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7717 11:08:11.245911 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7718 11:08:11.249260 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7719 11:08:11.252774 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7720 11:08:11.259097 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7721 11:08:11.262261 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7722 11:08:11.265861 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7723 11:08:11.266383 ==
7724 11:08:11.269052 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 11:08:11.272570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 11:08:11.275725 ==
7727 11:08:11.276227 DQS Delay:
7728 11:08:11.276683 DQS0 = 0, DQS1 = 0
7729 11:08:11.279175 DQM Delay:
7730 11:08:11.279696 DQM0 = 133, DQM1 = 125
7731 11:08:11.282504 DQ Delay:
7732 11:08:11.286032 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7733 11:08:11.289046 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7734 11:08:11.292346 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7735 11:08:11.295630 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7736 11:08:11.296029
7737 11:08:11.296329
7738 11:08:11.296601 ==
7739 11:08:11.298959 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 11:08:11.302135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 11:08:11.302519 ==
7742 11:08:11.305571
7743 11:08:11.306055
7744 11:08:11.306362 TX Vref Scan disable
7745 11:08:11.308880 == TX Byte 0 ==
7746 11:08:11.312235 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7747 11:08:11.315288 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7748 11:08:11.318686 == TX Byte 1 ==
7749 11:08:11.322036 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7750 11:08:11.325372 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7751 11:08:11.325893 ==
7752 11:08:11.328804 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 11:08:11.334634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 11:08:11.334731 ==
7755 11:08:11.347095
7756 11:08:11.350492 TX Vref early break, caculate TX vref
7757 11:08:11.353831 TX Vref=16, minBit 4, minWin=22, winSum=372
7758 11:08:11.357254 TX Vref=18, minBit 1, minWin=23, winSum=383
7759 11:08:11.360508 TX Vref=20, minBit 3, minWin=23, winSum=390
7760 11:08:11.363800 TX Vref=22, minBit 0, minWin=24, winSum=403
7761 11:08:11.367227 TX Vref=24, minBit 0, minWin=24, winSum=406
7762 11:08:11.373467 TX Vref=26, minBit 0, minWin=25, winSum=418
7763 11:08:11.377050 TX Vref=28, minBit 4, minWin=24, winSum=422
7764 11:08:11.380650 TX Vref=30, minBit 0, minWin=24, winSum=413
7765 11:08:11.383389 TX Vref=32, minBit 7, minWin=23, winSum=404
7766 11:08:11.386995 TX Vref=34, minBit 4, minWin=23, winSum=394
7767 11:08:11.393672 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
7768 11:08:11.393750
7769 11:08:11.396988 Final TX Range 0 Vref 26
7770 11:08:11.397065
7771 11:08:11.397123 ==
7772 11:08:11.400122 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 11:08:11.403389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 11:08:11.403492 ==
7775 11:08:11.403553
7776 11:08:11.403608
7777 11:08:11.406790 TX Vref Scan disable
7778 11:08:11.413334 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7779 11:08:11.413411 == TX Byte 0 ==
7780 11:08:11.416554 u2DelayCellOfst[0]=15 cells (4 PI)
7781 11:08:11.419567 u2DelayCellOfst[1]=18 cells (5 PI)
7782 11:08:11.423007 u2DelayCellOfst[2]=15 cells (4 PI)
7783 11:08:11.426655 u2DelayCellOfst[3]=15 cells (4 PI)
7784 11:08:11.429574 u2DelayCellOfst[4]=11 cells (3 PI)
7785 11:08:11.432927 u2DelayCellOfst[5]=0 cells (0 PI)
7786 11:08:11.436266 u2DelayCellOfst[6]=18 cells (5 PI)
7787 11:08:11.439746 u2DelayCellOfst[7]=22 cells (6 PI)
7788 11:08:11.442875 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7789 11:08:11.446309 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7790 11:08:11.449456 == TX Byte 1 ==
7791 11:08:11.452884 u2DelayCellOfst[8]=0 cells (0 PI)
7792 11:08:11.456632 u2DelayCellOfst[9]=0 cells (0 PI)
7793 11:08:11.456706 u2DelayCellOfst[10]=7 cells (2 PI)
7794 11:08:11.459771 u2DelayCellOfst[11]=0 cells (0 PI)
7795 11:08:11.463116 u2DelayCellOfst[12]=11 cells (3 PI)
7796 11:08:11.466818 u2DelayCellOfst[13]=7 cells (2 PI)
7797 11:08:11.469608 u2DelayCellOfst[14]=15 cells (4 PI)
7798 11:08:11.473175 u2DelayCellOfst[15]=11 cells (3 PI)
7799 11:08:11.476368 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7800 11:08:11.482754 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7801 11:08:11.482845 DramC Write-DBI on
7802 11:08:11.482903 ==
7803 11:08:11.486414 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 11:08:11.493077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 11:08:11.493159 ==
7806 11:08:11.493218
7807 11:08:11.493271
7808 11:08:11.493322 TX Vref Scan disable
7809 11:08:11.497270 == TX Byte 0 ==
7810 11:08:11.500182 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7811 11:08:11.503341 == TX Byte 1 ==
7812 11:08:11.506545 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7813 11:08:11.509968 DramC Write-DBI off
7814 11:08:11.510043
7815 11:08:11.510101 [DATLAT]
7816 11:08:11.510155 Freq=1600, CH0 RK0
7817 11:08:11.510207
7818 11:08:11.513355 DATLAT Default: 0xf
7819 11:08:11.513435 0, 0xFFFF, sum = 0
7820 11:08:11.516972 1, 0xFFFF, sum = 0
7821 11:08:11.519804 2, 0xFFFF, sum = 0
7822 11:08:11.519882 3, 0xFFFF, sum = 0
7823 11:08:11.523103 4, 0xFFFF, sum = 0
7824 11:08:11.523178 5, 0xFFFF, sum = 0
7825 11:08:11.526549 6, 0xFFFF, sum = 0
7826 11:08:11.526626 7, 0xFFFF, sum = 0
7827 11:08:11.529972 8, 0xFFFF, sum = 0
7828 11:08:11.530048 9, 0xFFFF, sum = 0
7829 11:08:11.533327 10, 0xFFFF, sum = 0
7830 11:08:11.533404 11, 0xFFFF, sum = 0
7831 11:08:11.536767 12, 0xFFFF, sum = 0
7832 11:08:11.536842 13, 0xFFFF, sum = 0
7833 11:08:11.539670 14, 0x0, sum = 1
7834 11:08:11.539770 15, 0x0, sum = 2
7835 11:08:11.543405 16, 0x0, sum = 3
7836 11:08:11.543526 17, 0x0, sum = 4
7837 11:08:11.546146 best_step = 15
7838 11:08:11.546219
7839 11:08:11.546276 ==
7840 11:08:11.549555 Dram Type= 6, Freq= 0, CH_0, rank 0
7841 11:08:11.552906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7842 11:08:11.553014 ==
7843 11:08:11.556064 RX Vref Scan: 1
7844 11:08:11.556157
7845 11:08:11.556234 Set Vref Range= 24 -> 127
7846 11:08:11.556288
7847 11:08:11.559513 RX Vref 24 -> 127, step: 1
7848 11:08:11.559587
7849 11:08:11.562963 RX Delay 11 -> 252, step: 4
7850 11:08:11.563038
7851 11:08:11.565762 Set Vref, RX VrefLevel [Byte0]: 24
7852 11:08:11.569917 [Byte1]: 24
7853 11:08:11.569991
7854 11:08:11.572420 Set Vref, RX VrefLevel [Byte0]: 25
7855 11:08:11.575929 [Byte1]: 25
7856 11:08:11.579165
7857 11:08:11.582713 Set Vref, RX VrefLevel [Byte0]: 26
7858 11:08:11.586019 [Byte1]: 26
7859 11:08:11.586096
7860 11:08:11.589515 Set Vref, RX VrefLevel [Byte0]: 27
7861 11:08:11.592480 [Byte1]: 27
7862 11:08:11.592570
7863 11:08:11.595836 Set Vref, RX VrefLevel [Byte0]: 28
7864 11:08:11.599217 [Byte1]: 28
7865 11:08:11.602709
7866 11:08:11.602783 Set Vref, RX VrefLevel [Byte0]: 29
7867 11:08:11.605625 [Byte1]: 29
7868 11:08:11.609878
7869 11:08:11.609955 Set Vref, RX VrefLevel [Byte0]: 30
7870 11:08:11.613007 [Byte1]: 30
7871 11:08:11.617829
7872 11:08:11.617906 Set Vref, RX VrefLevel [Byte0]: 31
7873 11:08:11.621045 [Byte1]: 31
7874 11:08:11.625652
7875 11:08:11.625742 Set Vref, RX VrefLevel [Byte0]: 32
7876 11:08:11.628642 [Byte1]: 32
7877 11:08:11.632740
7878 11:08:11.632814 Set Vref, RX VrefLevel [Byte0]: 33
7879 11:08:11.636152 [Byte1]: 33
7880 11:08:11.640283
7881 11:08:11.640357 Set Vref, RX VrefLevel [Byte0]: 34
7882 11:08:11.643654 [Byte1]: 34
7883 11:08:11.647803
7884 11:08:11.647877 Set Vref, RX VrefLevel [Byte0]: 35
7885 11:08:11.651463 [Byte1]: 35
7886 11:08:11.655389
7887 11:08:11.655515 Set Vref, RX VrefLevel [Byte0]: 36
7888 11:08:11.658889 [Byte1]: 36
7889 11:08:11.663353
7890 11:08:11.663489 Set Vref, RX VrefLevel [Byte0]: 37
7891 11:08:11.666601 [Byte1]: 37
7892 11:08:11.670747
7893 11:08:11.670821 Set Vref, RX VrefLevel [Byte0]: 38
7894 11:08:11.674294 [Byte1]: 38
7895 11:08:11.678367
7896 11:08:11.681877 Set Vref, RX VrefLevel [Byte0]: 39
7897 11:08:11.681952 [Byte1]: 39
7898 11:08:11.685921
7899 11:08:11.686034 Set Vref, RX VrefLevel [Byte0]: 40
7900 11:08:11.689464 [Byte1]: 40
7901 11:08:11.694015
7902 11:08:11.694107 Set Vref, RX VrefLevel [Byte0]: 41
7903 11:08:11.697242 [Byte1]: 41
7904 11:08:11.701306
7905 11:08:11.701376 Set Vref, RX VrefLevel [Byte0]: 42
7906 11:08:11.705283 [Byte1]: 42
7907 11:08:11.709083
7908 11:08:11.709151 Set Vref, RX VrefLevel [Byte0]: 43
7909 11:08:11.712183 [Byte1]: 43
7910 11:08:11.716671
7911 11:08:11.716748 Set Vref, RX VrefLevel [Byte0]: 44
7912 11:08:11.719910 [Byte1]: 44
7913 11:08:11.723950
7914 11:08:11.724026 Set Vref, RX VrefLevel [Byte0]: 45
7915 11:08:11.727771 [Byte1]: 45
7916 11:08:11.732036
7917 11:08:11.732115 Set Vref, RX VrefLevel [Byte0]: 46
7918 11:08:11.734908 [Byte1]: 46
7919 11:08:11.739520
7920 11:08:11.739596 Set Vref, RX VrefLevel [Byte0]: 47
7921 11:08:11.742884 [Byte1]: 47
7922 11:08:11.747135
7923 11:08:11.747227 Set Vref, RX VrefLevel [Byte0]: 48
7924 11:08:11.750522 [Byte1]: 48
7925 11:08:11.754510
7926 11:08:11.754586 Set Vref, RX VrefLevel [Byte0]: 49
7927 11:08:11.757785 [Byte1]: 49
7928 11:08:11.762529
7929 11:08:11.762604 Set Vref, RX VrefLevel [Byte0]: 50
7930 11:08:11.765451 [Byte1]: 50
7931 11:08:11.770036
7932 11:08:11.770111 Set Vref, RX VrefLevel [Byte0]: 51
7933 11:08:11.773392 [Byte1]: 51
7934 11:08:11.777161
7935 11:08:11.780487 Set Vref, RX VrefLevel [Byte0]: 52
7936 11:08:11.783704 [Byte1]: 52
7937 11:08:11.783782
7938 11:08:11.787477 Set Vref, RX VrefLevel [Byte0]: 53
7939 11:08:11.790271 [Byte1]: 53
7940 11:08:11.790341
7941 11:08:11.794001 Set Vref, RX VrefLevel [Byte0]: 54
7942 11:08:11.797244 [Byte1]: 54
7943 11:08:11.800040
7944 11:08:11.800115 Set Vref, RX VrefLevel [Byte0]: 55
7945 11:08:11.803407 [Byte1]: 55
7946 11:08:11.808060
7947 11:08:11.808135 Set Vref, RX VrefLevel [Byte0]: 56
7948 11:08:11.811241 [Byte1]: 56
7949 11:08:11.815975
7950 11:08:11.816084 Set Vref, RX VrefLevel [Byte0]: 57
7951 11:08:11.818923 [Byte1]: 57
7952 11:08:11.823298
7953 11:08:11.823397 Set Vref, RX VrefLevel [Byte0]: 58
7954 11:08:11.826345 [Byte1]: 58
7955 11:08:11.830562
7956 11:08:11.830637 Set Vref, RX VrefLevel [Byte0]: 59
7957 11:08:11.833764 [Byte1]: 59
7958 11:08:11.838437
7959 11:08:11.838512 Set Vref, RX VrefLevel [Byte0]: 60
7960 11:08:11.841881 [Byte1]: 60
7961 11:08:11.846121
7962 11:08:11.846196 Set Vref, RX VrefLevel [Byte0]: 61
7963 11:08:11.849252 [Byte1]: 61
7964 11:08:11.853852
7965 11:08:11.853927 Set Vref, RX VrefLevel [Byte0]: 62
7966 11:08:11.856797 [Byte1]: 62
7967 11:08:11.861293
7968 11:08:11.861367 Set Vref, RX VrefLevel [Byte0]: 63
7969 11:08:11.864760 [Byte1]: 63
7970 11:08:11.868787
7971 11:08:11.868902 Set Vref, RX VrefLevel [Byte0]: 64
7972 11:08:11.872306 [Byte1]: 64
7973 11:08:11.876341
7974 11:08:11.879621 Set Vref, RX VrefLevel [Byte0]: 65
7975 11:08:11.883062 [Byte1]: 65
7976 11:08:11.883140
7977 11:08:11.886384 Set Vref, RX VrefLevel [Byte0]: 66
7978 11:08:11.889297 [Byte1]: 66
7979 11:08:11.889371
7980 11:08:11.892882 Set Vref, RX VrefLevel [Byte0]: 67
7981 11:08:11.895734 [Byte1]: 67
7982 11:08:11.899344
7983 11:08:11.899418 Set Vref, RX VrefLevel [Byte0]: 68
7984 11:08:11.902257 [Byte1]: 68
7985 11:08:11.906583
7986 11:08:11.906657 Set Vref, RX VrefLevel [Byte0]: 69
7987 11:08:11.909951 [Byte1]: 69
7988 11:08:11.914338
7989 11:08:11.914412 Set Vref, RX VrefLevel [Byte0]: 70
7990 11:08:11.917587 [Byte1]: 70
7991 11:08:11.922626
7992 11:08:11.922700 Set Vref, RX VrefLevel [Byte0]: 71
7993 11:08:11.925097 [Byte1]: 71
7994 11:08:11.930255
7995 11:08:11.930330 Set Vref, RX VrefLevel [Byte0]: 72
7996 11:08:11.932969 [Byte1]: 72
7997 11:08:11.937167
7998 11:08:11.937240 Set Vref, RX VrefLevel [Byte0]: 73
7999 11:08:11.940645 [Byte1]: 73
8000 11:08:11.945178
8001 11:08:11.945256 Set Vref, RX VrefLevel [Byte0]: 74
8002 11:08:11.948203 [Byte1]: 74
8003 11:08:11.952464
8004 11:08:11.952539 Set Vref, RX VrefLevel [Byte0]: 75
8005 11:08:11.955980 [Byte1]: 75
8006 11:08:11.960048
8007 11:08:11.960122 Set Vref, RX VrefLevel [Byte0]: 76
8008 11:08:11.963220 [Byte1]: 76
8009 11:08:11.967976
8010 11:08:11.968067 Set Vref, RX VrefLevel [Byte0]: 77
8011 11:08:11.970747 [Byte1]: 77
8012 11:08:11.975221
8013 11:08:11.975296 Set Vref, RX VrefLevel [Byte0]: 78
8014 11:08:11.978868 [Byte1]: 78
8015 11:08:11.982755
8016 11:08:11.982829 Set Vref, RX VrefLevel [Byte0]: 79
8017 11:08:11.986542 [Byte1]: 79
8018 11:08:11.990739
8019 11:08:11.990814 Final RX Vref Byte 0 = 64 to rank0
8020 11:08:11.993854 Final RX Vref Byte 1 = 57 to rank0
8021 11:08:11.997559 Final RX Vref Byte 0 = 64 to rank1
8022 11:08:12.000784 Final RX Vref Byte 1 = 57 to rank1==
8023 11:08:12.004128 Dram Type= 6, Freq= 0, CH_0, rank 0
8024 11:08:12.010606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 11:08:12.010682 ==
8026 11:08:12.010740 DQS Delay:
8027 11:08:12.010793 DQS0 = 0, DQS1 = 0
8028 11:08:12.013510 DQM Delay:
8029 11:08:12.013584 DQM0 = 132, DQM1 = 123
8030 11:08:12.016875 DQ Delay:
8031 11:08:12.020344 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
8032 11:08:12.023658 DQ4 =132, DQ5 =122, DQ6 =138, DQ7 =142
8033 11:08:12.026692 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8034 11:08:12.030064 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8035 11:08:12.030138
8036 11:08:12.030195
8037 11:08:12.030249
8038 11:08:12.033409 [DramC_TX_OE_Calibration] TA2
8039 11:08:12.036693 Original DQ_B0 (3 6) =30, OEN = 27
8040 11:08:12.040138 Original DQ_B1 (3 6) =30, OEN = 27
8041 11:08:12.043361 24, 0x0, End_B0=24 End_B1=24
8042 11:08:12.043495 25, 0x0, End_B0=25 End_B1=25
8043 11:08:12.046931 26, 0x0, End_B0=26 End_B1=26
8044 11:08:12.049999 27, 0x0, End_B0=27 End_B1=27
8045 11:08:12.053275 28, 0x0, End_B0=28 End_B1=28
8046 11:08:12.056995 29, 0x0, End_B0=29 End_B1=29
8047 11:08:12.057071 30, 0x0, End_B0=30 End_B1=30
8048 11:08:12.060073 31, 0x4141, End_B0=30 End_B1=30
8049 11:08:12.063010 Byte0 end_step=30 best_step=27
8050 11:08:12.066788 Byte1 end_step=30 best_step=27
8051 11:08:12.069674 Byte0 TX OE(2T, 0.5T) = (3, 3)
8052 11:08:12.073072 Byte1 TX OE(2T, 0.5T) = (3, 3)
8053 11:08:12.073147
8054 11:08:12.073205
8055 11:08:12.080006 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8056 11:08:12.082967 CH0 RK0: MR19=303, MR18=2112
8057 11:08:12.089947 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8058 11:08:12.090026
8059 11:08:12.093281 ----->DramcWriteLeveling(PI) begin...
8060 11:08:12.093380 ==
8061 11:08:12.096559 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 11:08:12.099295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 11:08:12.099394 ==
8064 11:08:12.102756 Write leveling (Byte 0): 35 => 35
8065 11:08:12.106239 Write leveling (Byte 1): 26 => 26
8066 11:08:12.109563 DramcWriteLeveling(PI) end<-----
8067 11:08:12.109639
8068 11:08:12.109697 ==
8069 11:08:12.112475 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 11:08:12.116255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 11:08:12.119424 ==
8072 11:08:12.119537 [Gating] SW mode calibration
8073 11:08:12.129574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8074 11:08:12.132384 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8075 11:08:12.136247 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 11:08:12.142547 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 11:08:12.145672 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 11:08:12.149142 1 4 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8079 11:08:12.156008 1 4 16 | B1->B0 | 2423 3434 | 1 0 | (0 0) (0 0)
8080 11:08:12.159223 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8081 11:08:12.162298 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 11:08:12.169051 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 11:08:12.172413 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 11:08:12.175561 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 11:08:12.182488 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8086 11:08:12.185395 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8087 11:08:12.188730 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 1)
8088 11:08:12.195384 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8089 11:08:12.199116 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 11:08:12.202521 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 11:08:12.209106 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 11:08:12.212264 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 11:08:12.215448 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 11:08:12.221892 1 6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8095 11:08:12.225222 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
8096 11:08:12.228821 1 6 20 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
8097 11:08:12.235391 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 11:08:12.238408 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 11:08:12.241751 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 11:08:12.248945 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 11:08:12.251725 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8102 11:08:12.255131 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8103 11:08:12.261553 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8104 11:08:12.264878 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:08:12.268350 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:08:12.274863 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:08:12.278030 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 11:08:12.281395 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 11:08:12.288401 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 11:08:12.291120 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:08:12.294634 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:08:12.300873 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:08:12.304341 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 11:08:12.307581 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 11:08:12.314568 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 11:08:12.317894 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 11:08:12.321422 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 11:08:12.327896 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8119 11:08:12.331298 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8120 11:08:12.334488 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8121 11:08:12.337814 Total UI for P1: 0, mck2ui 16
8122 11:08:12.340804 best dqsien dly found for B0: ( 1, 9, 14)
8123 11:08:12.344346 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 11:08:12.347670 Total UI for P1: 0, mck2ui 16
8125 11:08:12.350882 best dqsien dly found for B1: ( 1, 9, 20)
8126 11:08:12.354154 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8127 11:08:12.361009 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8128 11:08:12.361106
8129 11:08:12.364389 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8130 11:08:12.367134 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8131 11:08:12.370798 [Gating] SW calibration Done
8132 11:08:12.370878 ==
8133 11:08:12.374055 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 11:08:12.376958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 11:08:12.377034 ==
8136 11:08:12.380597 RX Vref Scan: 0
8137 11:08:12.380672
8138 11:08:12.380728 RX Vref 0 -> 0, step: 1
8139 11:08:12.380781
8140 11:08:12.383951 RX Delay 0 -> 252, step: 8
8141 11:08:12.386912 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8142 11:08:12.393943 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8143 11:08:12.396753 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8144 11:08:12.400578 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8145 11:08:12.403360 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8146 11:08:12.406725 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8147 11:08:12.413544 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8148 11:08:12.416621 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8149 11:08:12.420042 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8150 11:08:12.423434 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8151 11:08:12.426696 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8152 11:08:12.433410 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8153 11:08:12.436369 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8154 11:08:12.440231 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8155 11:08:12.443050 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8156 11:08:12.446713 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8157 11:08:12.449979 ==
8158 11:08:12.453373 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 11:08:12.456578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 11:08:12.456676 ==
8161 11:08:12.456758 DQS Delay:
8162 11:08:12.459802 DQS0 = 0, DQS1 = 0
8163 11:08:12.459866 DQM Delay:
8164 11:08:12.463614 DQM0 = 132, DQM1 = 128
8165 11:08:12.463676 DQ Delay:
8166 11:08:12.466643 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8167 11:08:12.470072 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8168 11:08:12.472875 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8169 11:08:12.476868 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8170 11:08:12.476981
8171 11:08:12.477047
8172 11:08:12.477100 ==
8173 11:08:12.479606 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 11:08:12.487087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 11:08:12.487192 ==
8176 11:08:12.487284
8177 11:08:12.487376
8178 11:08:12.487477 TX Vref Scan disable
8179 11:08:12.490024 == TX Byte 0 ==
8180 11:08:12.493736 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8181 11:08:12.500081 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8182 11:08:12.500149 == TX Byte 1 ==
8183 11:08:12.503383 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8184 11:08:12.509682 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8185 11:08:12.509758 ==
8186 11:08:12.512997 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 11:08:12.516268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 11:08:12.516346 ==
8189 11:08:12.530030
8190 11:08:12.532971 TX Vref early break, caculate TX vref
8191 11:08:12.536488 TX Vref=16, minBit 0, minWin=23, winSum=377
8192 11:08:12.540097 TX Vref=18, minBit 0, minWin=23, winSum=386
8193 11:08:12.543243 TX Vref=20, minBit 1, minWin=23, winSum=391
8194 11:08:12.546123 TX Vref=22, minBit 1, minWin=24, winSum=399
8195 11:08:12.549573 TX Vref=24, minBit 1, minWin=24, winSum=407
8196 11:08:12.556122 TX Vref=26, minBit 0, minWin=25, winSum=410
8197 11:08:12.559346 TX Vref=28, minBit 0, minWin=24, winSum=410
8198 11:08:12.562928 TX Vref=30, minBit 1, minWin=24, winSum=400
8199 11:08:12.566308 TX Vref=32, minBit 2, minWin=23, winSum=389
8200 11:08:12.569556 TX Vref=34, minBit 1, minWin=23, winSum=386
8201 11:08:12.576399 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 26
8202 11:08:12.576471
8203 11:08:12.579461 Final TX Range 0 Vref 26
8204 11:08:12.579541
8205 11:08:12.579595 ==
8206 11:08:12.582654 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 11:08:12.586091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 11:08:12.586172 ==
8209 11:08:12.586227
8210 11:08:12.586288
8211 11:08:12.589344 TX Vref Scan disable
8212 11:08:12.596263 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8213 11:08:12.596346 == TX Byte 0 ==
8214 11:08:12.599500 u2DelayCellOfst[0]=15 cells (4 PI)
8215 11:08:12.602512 u2DelayCellOfst[1]=18 cells (5 PI)
8216 11:08:12.605871 u2DelayCellOfst[2]=15 cells (4 PI)
8217 11:08:12.609310 u2DelayCellOfst[3]=18 cells (5 PI)
8218 11:08:12.612779 u2DelayCellOfst[4]=11 cells (3 PI)
8219 11:08:12.615576 u2DelayCellOfst[5]=0 cells (0 PI)
8220 11:08:12.618858 u2DelayCellOfst[6]=22 cells (6 PI)
8221 11:08:12.622273 u2DelayCellOfst[7]=22 cells (6 PI)
8222 11:08:12.625633 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8223 11:08:12.628915 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8224 11:08:12.632326 == TX Byte 1 ==
8225 11:08:12.635713 u2DelayCellOfst[8]=0 cells (0 PI)
8226 11:08:12.639454 u2DelayCellOfst[9]=3 cells (1 PI)
8227 11:08:12.642331 u2DelayCellOfst[10]=11 cells (3 PI)
8228 11:08:12.642399 u2DelayCellOfst[11]=7 cells (2 PI)
8229 11:08:12.645780 u2DelayCellOfst[12]=15 cells (4 PI)
8230 11:08:12.649015 u2DelayCellOfst[13]=15 cells (4 PI)
8231 11:08:12.651925 u2DelayCellOfst[14]=18 cells (5 PI)
8232 11:08:12.655397 u2DelayCellOfst[15]=11 cells (3 PI)
8233 11:08:12.662056 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8234 11:08:12.665528 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8235 11:08:12.665609 DramC Write-DBI on
8236 11:08:12.665669 ==
8237 11:08:12.668857 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 11:08:12.675115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 11:08:12.675189 ==
8240 11:08:12.675261
8241 11:08:12.675316
8242 11:08:12.678358 TX Vref Scan disable
8243 11:08:12.678426 == TX Byte 0 ==
8244 11:08:12.685295 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8245 11:08:12.685370 == TX Byte 1 ==
8246 11:08:12.688637 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8247 11:08:12.692207 DramC Write-DBI off
8248 11:08:12.692283
8249 11:08:12.692341 [DATLAT]
8250 11:08:12.695356 Freq=1600, CH0 RK1
8251 11:08:12.695497
8252 11:08:12.695559 DATLAT Default: 0xf
8253 11:08:12.698367 0, 0xFFFF, sum = 0
8254 11:08:12.698444 1, 0xFFFF, sum = 0
8255 11:08:12.701852 2, 0xFFFF, sum = 0
8256 11:08:12.701928 3, 0xFFFF, sum = 0
8257 11:08:12.705187 4, 0xFFFF, sum = 0
8258 11:08:12.705286 5, 0xFFFF, sum = 0
8259 11:08:12.708491 6, 0xFFFF, sum = 0
8260 11:08:12.708587 7, 0xFFFF, sum = 0
8261 11:08:12.711661 8, 0xFFFF, sum = 0
8262 11:08:12.711780 9, 0xFFFF, sum = 0
8263 11:08:12.714730 10, 0xFFFF, sum = 0
8264 11:08:12.719249 11, 0xFFFF, sum = 0
8265 11:08:12.719351 12, 0xFFFF, sum = 0
8266 11:08:12.721858 13, 0xFFFF, sum = 0
8267 11:08:12.721934 14, 0x0, sum = 1
8268 11:08:12.725159 15, 0x0, sum = 2
8269 11:08:12.725235 16, 0x0, sum = 3
8270 11:08:12.728682 17, 0x0, sum = 4
8271 11:08:12.728758 best_step = 15
8272 11:08:12.728815
8273 11:08:12.728868 ==
8274 11:08:12.731402 Dram Type= 6, Freq= 0, CH_0, rank 1
8275 11:08:12.734847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 11:08:12.734993 ==
8277 11:08:12.738304 RX Vref Scan: 0
8278 11:08:12.738379
8279 11:08:12.741402 RX Vref 0 -> 0, step: 1
8280 11:08:12.741488
8281 11:08:12.741547 RX Delay 11 -> 252, step: 4
8282 11:08:12.748495 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8283 11:08:12.751936 iDelay=191, Bit 1, Center 134 (83 ~ 186) 104
8284 11:08:12.754891 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8285 11:08:12.758423 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
8286 11:08:12.762300 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8287 11:08:12.768220 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8288 11:08:12.771585 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8289 11:08:12.774792 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8290 11:08:12.777892 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8291 11:08:12.784676 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8292 11:08:12.788029 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8293 11:08:12.791417 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8294 11:08:12.794356 iDelay=191, Bit 12, Center 130 (75 ~ 186) 112
8295 11:08:12.797791 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8296 11:08:12.804313 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8297 11:08:12.807723 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8298 11:08:12.807798 ==
8299 11:08:12.810725 Dram Type= 6, Freq= 0, CH_0, rank 1
8300 11:08:12.814041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 11:08:12.814120 ==
8302 11:08:12.817524 DQS Delay:
8303 11:08:12.817599 DQS0 = 0, DQS1 = 0
8304 11:08:12.820866 DQM Delay:
8305 11:08:12.820940 DQM0 = 129, DQM1 = 125
8306 11:08:12.820999 DQ Delay:
8307 11:08:12.827384 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8308 11:08:12.830672 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
8309 11:08:12.833855 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8310 11:08:12.837411 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8311 11:08:12.837509
8312 11:08:12.837592
8313 11:08:12.837672
8314 11:08:12.840605 [DramC_TX_OE_Calibration] TA2
8315 11:08:12.843869 Original DQ_B0 (3 6) =30, OEN = 27
8316 11:08:12.847382 Original DQ_B1 (3 6) =30, OEN = 27
8317 11:08:12.847516 24, 0x0, End_B0=24 End_B1=24
8318 11:08:12.850846 25, 0x0, End_B0=25 End_B1=25
8319 11:08:12.854049 26, 0x0, End_B0=26 End_B1=26
8320 11:08:12.857048 27, 0x0, End_B0=27 End_B1=27
8321 11:08:12.860492 28, 0x0, End_B0=28 End_B1=28
8322 11:08:12.860571 29, 0x0, End_B0=29 End_B1=29
8323 11:08:12.864030 30, 0x0, End_B0=30 End_B1=30
8324 11:08:12.866938 31, 0x4141, End_B0=30 End_B1=30
8325 11:08:12.870391 Byte0 end_step=30 best_step=27
8326 11:08:12.873869 Byte1 end_step=30 best_step=27
8327 11:08:12.876964 Byte0 TX OE(2T, 0.5T) = (3, 3)
8328 11:08:12.877038 Byte1 TX OE(2T, 0.5T) = (3, 3)
8329 11:08:12.877098
8330 11:08:12.877152
8331 11:08:12.886625 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8332 11:08:12.890413 CH0 RK1: MR19=303, MR18=1E01
8333 11:08:12.896763 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8334 11:08:12.899704 [RxdqsGatingPostProcess] freq 1600
8335 11:08:12.903018 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8336 11:08:12.906386 best DQS0 dly(2T, 0.5T) = (1, 1)
8337 11:08:12.910051 best DQS1 dly(2T, 0.5T) = (1, 1)
8338 11:08:12.913383 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8339 11:08:12.916289 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8340 11:08:12.919829 best DQS0 dly(2T, 0.5T) = (1, 1)
8341 11:08:12.922926 best DQS1 dly(2T, 0.5T) = (1, 1)
8342 11:08:12.926449 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8343 11:08:12.929874 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8344 11:08:12.933200 Pre-setting of DQS Precalculation
8345 11:08:12.935977 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8346 11:08:12.936091 ==
8347 11:08:12.939288 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 11:08:12.942939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 11:08:12.946131 ==
8350 11:08:12.949458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8351 11:08:12.952765 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8352 11:08:12.959327 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8353 11:08:12.962765 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8354 11:08:12.972792 [CA 0] Center 42 (13~71) winsize 59
8355 11:08:12.976159 [CA 1] Center 41 (12~71) winsize 60
8356 11:08:12.979348 [CA 2] Center 37 (8~66) winsize 59
8357 11:08:12.982808 [CA 3] Center 36 (7~65) winsize 59
8358 11:08:12.986381 [CA 4] Center 37 (7~67) winsize 61
8359 11:08:12.989837 [CA 5] Center 36 (7~66) winsize 60
8360 11:08:12.990389
8361 11:08:12.992649 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8362 11:08:12.993199
8363 11:08:12.996127 [CATrainingPosCal] consider 1 rank data
8364 11:08:12.999709 u2DelayCellTimex100 = 258/100 ps
8365 11:08:13.005868 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8366 11:08:13.009189 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8367 11:08:13.012571 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8368 11:08:13.016428 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8369 11:08:13.019323 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8370 11:08:13.022222 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8371 11:08:13.022719
8372 11:08:13.025707 CA PerBit enable=1, Macro0, CA PI delay=36
8373 11:08:13.026221
8374 11:08:13.029095 [CBTSetCACLKResult] CA Dly = 36
8375 11:08:13.032523 CS Dly: 9 (0~40)
8376 11:08:13.035811 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8377 11:08:13.038639 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8378 11:08:13.039017 ==
8379 11:08:13.042230 Dram Type= 6, Freq= 0, CH_1, rank 1
8380 11:08:13.048533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 11:08:13.049075 ==
8382 11:08:13.052252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8383 11:08:13.058991 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8384 11:08:13.062535 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8385 11:08:13.068713 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8386 11:08:13.076283 [CA 0] Center 42 (13~72) winsize 60
8387 11:08:13.079702 [CA 1] Center 42 (13~72) winsize 60
8388 11:08:13.083099 [CA 2] Center 37 (8~67) winsize 60
8389 11:08:13.085881 [CA 3] Center 37 (8~66) winsize 59
8390 11:08:13.089634 [CA 4] Center 37 (8~67) winsize 60
8391 11:08:13.092618 [CA 5] Center 36 (7~66) winsize 60
8392 11:08:13.093085
8393 11:08:13.096028 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8394 11:08:13.096501
8395 11:08:13.099733 [CATrainingPosCal] consider 2 rank data
8396 11:08:13.102707 u2DelayCellTimex100 = 258/100 ps
8397 11:08:13.109293 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8398 11:08:13.112793 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8399 11:08:13.116292 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8400 11:08:13.119079 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8401 11:08:13.122371 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8402 11:08:13.125826 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8403 11:08:13.126325
8404 11:08:13.129253 CA PerBit enable=1, Macro0, CA PI delay=36
8405 11:08:13.129832
8406 11:08:13.132628 [CBTSetCACLKResult] CA Dly = 36
8407 11:08:13.135490 CS Dly: 11 (0~44)
8408 11:08:13.138771 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8409 11:08:13.142368 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8410 11:08:13.142830
8411 11:08:13.146167 ----->DramcWriteLeveling(PI) begin...
8412 11:08:13.146703 ==
8413 11:08:13.149106 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 11:08:13.155817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 11:08:13.156208 ==
8416 11:08:13.159082 Write leveling (Byte 0): 26 => 26
8417 11:08:13.162168 Write leveling (Byte 1): 27 => 27
8418 11:08:13.162631 DramcWriteLeveling(PI) end<-----
8419 11:08:13.162971
8420 11:08:13.165077 ==
8421 11:08:13.168744 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 11:08:13.171861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 11:08:13.172244 ==
8424 11:08:13.175090 [Gating] SW mode calibration
8425 11:08:13.181668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8426 11:08:13.185255 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8427 11:08:13.192051 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:08:13.195246 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 11:08:13.198096 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 11:08:13.204764 1 4 12 | B1->B0 | 2b2b 3333 | 1 1 | (0 0) (1 1)
8431 11:08:13.208105 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 11:08:13.211368 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 11:08:13.218067 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 11:08:13.221533 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 11:08:13.224937 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 11:08:13.231748 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 11:08:13.234876 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8438 11:08:13.237716 1 5 12 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
8439 11:08:13.244577 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8440 11:08:13.247791 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 11:08:13.251264 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 11:08:13.257758 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 11:08:13.260724 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 11:08:13.264203 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 11:08:13.270871 1 6 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8446 11:08:13.274057 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8447 11:08:13.277071 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 11:08:13.284183 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 11:08:13.287390 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 11:08:13.291233 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 11:08:13.297479 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 11:08:13.300584 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 11:08:13.304012 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8454 11:08:13.310575 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8455 11:08:13.313797 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8456 11:08:13.317325 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 11:08:13.323945 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 11:08:13.327264 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 11:08:13.330472 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:08:13.337314 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 11:08:13.340265 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 11:08:13.343573 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 11:08:13.350275 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 11:08:13.353621 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 11:08:13.356526 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 11:08:13.363369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 11:08:13.366698 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 11:08:13.369547 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 11:08:13.376275 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8470 11:08:13.379822 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8471 11:08:13.382759 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8472 11:08:13.386340 Total UI for P1: 0, mck2ui 16
8473 11:08:13.388912 best dqsien dly found for B0: ( 1, 9, 10)
8474 11:08:13.395358 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 11:08:13.399064 Total UI for P1: 0, mck2ui 16
8476 11:08:13.402156 best dqsien dly found for B1: ( 1, 9, 14)
8477 11:08:13.405683 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8478 11:08:13.409081 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8479 11:08:13.409177
8480 11:08:13.412319 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8481 11:08:13.415643 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8482 11:08:13.418612 [Gating] SW calibration Done
8483 11:08:13.418702 ==
8484 11:08:13.421937 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 11:08:13.425438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 11:08:13.425529 ==
8487 11:08:13.428633 RX Vref Scan: 0
8488 11:08:13.428724
8489 11:08:13.431720 RX Vref 0 -> 0, step: 1
8490 11:08:13.431789
8491 11:08:13.431891 RX Delay 0 -> 252, step: 8
8492 11:08:13.438499 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8493 11:08:13.442071 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8494 11:08:13.444839 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8495 11:08:13.448468 iDelay=208, Bit 3, Center 135 (88 ~ 183) 96
8496 11:08:13.451882 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8497 11:08:13.458089 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8498 11:08:13.461602 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8499 11:08:13.464962 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8500 11:08:13.468195 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8501 11:08:13.474655 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8502 11:08:13.477603 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8503 11:08:13.481023 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8504 11:08:13.484437 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8505 11:08:13.487906 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8506 11:08:13.494302 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8507 11:08:13.497544 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8508 11:08:13.497637 ==
8509 11:08:13.500740 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 11:08:13.504306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 11:08:13.504374 ==
8512 11:08:13.507258 DQS Delay:
8513 11:08:13.507353 DQS0 = 0, DQS1 = 0
8514 11:08:13.510329 DQM Delay:
8515 11:08:13.510450 DQM0 = 137, DQM1 = 130
8516 11:08:13.510534 DQ Delay:
8517 11:08:13.513966 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8518 11:08:13.520448 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8519 11:08:13.523687 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8520 11:08:13.526937 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8521 11:08:13.527011
8522 11:08:13.527068
8523 11:08:13.527122 ==
8524 11:08:13.530454 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 11:08:13.533656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 11:08:13.533731 ==
8527 11:08:13.533788
8528 11:08:13.533841
8529 11:08:13.536827 TX Vref Scan disable
8530 11:08:13.540138 == TX Byte 0 ==
8531 11:08:13.543636 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8532 11:08:13.547198 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8533 11:08:13.550028 == TX Byte 1 ==
8534 11:08:13.553450 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8535 11:08:13.556990 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8536 11:08:13.557083 ==
8537 11:08:13.560446 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 11:08:13.566934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 11:08:13.567007 ==
8540 11:08:13.578032
8541 11:08:13.581539 TX Vref early break, caculate TX vref
8542 11:08:13.584503 TX Vref=16, minBit 10, minWin=22, winSum=380
8543 11:08:13.587905 TX Vref=18, minBit 0, minWin=23, winSum=393
8544 11:08:13.591011 TX Vref=20, minBit 0, minWin=24, winSum=399
8545 11:08:13.594355 TX Vref=22, minBit 0, minWin=24, winSum=402
8546 11:08:13.597959 TX Vref=24, minBit 0, minWin=25, winSum=423
8547 11:08:13.604816 TX Vref=26, minBit 0, minWin=25, winSum=420
8548 11:08:13.608030 TX Vref=28, minBit 5, minWin=25, winSum=424
8549 11:08:13.611649 TX Vref=30, minBit 1, minWin=25, winSum=419
8550 11:08:13.614529 TX Vref=32, minBit 1, minWin=25, winSum=410
8551 11:08:13.617607 TX Vref=34, minBit 5, minWin=23, winSum=399
8552 11:08:13.624398 [TxChooseVref] Worse bit 5, Min win 25, Win sum 424, Final Vref 28
8553 11:08:13.624473
8554 11:08:13.627442 Final TX Range 0 Vref 28
8555 11:08:13.627529
8556 11:08:13.627593 ==
8557 11:08:13.631287 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 11:08:13.634386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 11:08:13.634496 ==
8560 11:08:13.634619
8561 11:08:13.634723
8562 11:08:13.637491 TX Vref Scan disable
8563 11:08:13.643809 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8564 11:08:13.643885 == TX Byte 0 ==
8565 11:08:13.647587 u2DelayCellOfst[0]=18 cells (5 PI)
8566 11:08:13.650670 u2DelayCellOfst[1]=15 cells (4 PI)
8567 11:08:13.653955 u2DelayCellOfst[2]=0 cells (0 PI)
8568 11:08:13.657594 u2DelayCellOfst[3]=7 cells (2 PI)
8569 11:08:13.660796 u2DelayCellOfst[4]=7 cells (2 PI)
8570 11:08:13.663682 u2DelayCellOfst[5]=22 cells (6 PI)
8571 11:08:13.667055 u2DelayCellOfst[6]=18 cells (5 PI)
8572 11:08:13.670413 u2DelayCellOfst[7]=7 cells (2 PI)
8573 11:08:13.673686 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8574 11:08:13.677020 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8575 11:08:13.680508 == TX Byte 1 ==
8576 11:08:13.683531 u2DelayCellOfst[8]=0 cells (0 PI)
8577 11:08:13.683630 u2DelayCellOfst[9]=3 cells (1 PI)
8578 11:08:13.686819 u2DelayCellOfst[10]=11 cells (3 PI)
8579 11:08:13.690291 u2DelayCellOfst[11]=7 cells (2 PI)
8580 11:08:13.693144 u2DelayCellOfst[12]=15 cells (4 PI)
8581 11:08:13.696916 u2DelayCellOfst[13]=18 cells (5 PI)
8582 11:08:13.700110 u2DelayCellOfst[14]=18 cells (5 PI)
8583 11:08:13.703557 u2DelayCellOfst[15]=18 cells (5 PI)
8584 11:08:13.706957 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8585 11:08:13.713302 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8586 11:08:13.713398 DramC Write-DBI on
8587 11:08:13.713459 ==
8588 11:08:13.716699 Dram Type= 6, Freq= 0, CH_1, rank 0
8589 11:08:13.722936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8590 11:08:13.723011 ==
8591 11:08:13.723069
8592 11:08:13.723122
8593 11:08:13.723175 TX Vref Scan disable
8594 11:08:13.726917 == TX Byte 0 ==
8595 11:08:13.730346 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8596 11:08:13.733487 == TX Byte 1 ==
8597 11:08:13.736915 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8598 11:08:13.740365 DramC Write-DBI off
8599 11:08:13.740473
8600 11:08:13.740568 [DATLAT]
8601 11:08:13.740625 Freq=1600, CH1 RK0
8602 11:08:13.740677
8603 11:08:13.743435 DATLAT Default: 0xf
8604 11:08:13.746942 0, 0xFFFF, sum = 0
8605 11:08:13.747034 1, 0xFFFF, sum = 0
8606 11:08:13.750551 2, 0xFFFF, sum = 0
8607 11:08:13.750630 3, 0xFFFF, sum = 0
8608 11:08:13.753285 4, 0xFFFF, sum = 0
8609 11:08:13.753401 5, 0xFFFF, sum = 0
8610 11:08:13.756595 6, 0xFFFF, sum = 0
8611 11:08:13.756671 7, 0xFFFF, sum = 0
8612 11:08:13.760106 8, 0xFFFF, sum = 0
8613 11:08:13.760206 9, 0xFFFF, sum = 0
8614 11:08:13.763565 10, 0xFFFF, sum = 0
8615 11:08:13.763675 11, 0xFFFF, sum = 0
8616 11:08:13.766441 12, 0xFFFF, sum = 0
8617 11:08:13.766541 13, 0xBFFF, sum = 0
8618 11:08:13.770293 14, 0x0, sum = 1
8619 11:08:13.770370 15, 0x0, sum = 2
8620 11:08:13.773427 16, 0x0, sum = 3
8621 11:08:13.773504 17, 0x0, sum = 4
8622 11:08:13.776812 best_step = 15
8623 11:08:13.776885
8624 11:08:13.776943 ==
8625 11:08:13.779936 Dram Type= 6, Freq= 0, CH_1, rank 0
8626 11:08:13.783390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8627 11:08:13.783505 ==
8628 11:08:13.786291 RX Vref Scan: 1
8629 11:08:13.786365
8630 11:08:13.786460 Set Vref Range= 24 -> 127
8631 11:08:13.786514
8632 11:08:13.789941 RX Vref 24 -> 127, step: 1
8633 11:08:13.790016
8634 11:08:13.792917 RX Delay 19 -> 252, step: 4
8635 11:08:13.792992
8636 11:08:13.796393 Set Vref, RX VrefLevel [Byte0]: 24
8637 11:08:13.799774 [Byte1]: 24
8638 11:08:13.799848
8639 11:08:13.802854 Set Vref, RX VrefLevel [Byte0]: 25
8640 11:08:13.805831 [Byte1]: 25
8641 11:08:13.810057
8642 11:08:13.810133 Set Vref, RX VrefLevel [Byte0]: 26
8643 11:08:13.813363 [Byte1]: 26
8644 11:08:13.817434
8645 11:08:13.817510 Set Vref, RX VrefLevel [Byte0]: 27
8646 11:08:13.820922 [Byte1]: 27
8647 11:08:13.824923
8648 11:08:13.828111 Set Vref, RX VrefLevel [Byte0]: 28
8649 11:08:13.831374 [Byte1]: 28
8650 11:08:13.831490
8651 11:08:13.834444 Set Vref, RX VrefLevel [Byte0]: 29
8652 11:08:13.838077 [Byte1]: 29
8653 11:08:13.838155
8654 11:08:13.841094 Set Vref, RX VrefLevel [Byte0]: 30
8655 11:08:13.844316 [Byte1]: 30
8656 11:08:13.847840
8657 11:08:13.847918 Set Vref, RX VrefLevel [Byte0]: 31
8658 11:08:13.851166 [Byte1]: 31
8659 11:08:13.855177
8660 11:08:13.855254 Set Vref, RX VrefLevel [Byte0]: 32
8661 11:08:13.858404 [Byte1]: 32
8662 11:08:13.862877
8663 11:08:13.862954 Set Vref, RX VrefLevel [Byte0]: 33
8664 11:08:13.865794 [Byte1]: 33
8665 11:08:13.870557
8666 11:08:13.870633 Set Vref, RX VrefLevel [Byte0]: 34
8667 11:08:13.873713 [Byte1]: 34
8668 11:08:13.877963
8669 11:08:13.878038 Set Vref, RX VrefLevel [Byte0]: 35
8670 11:08:13.881189 [Byte1]: 35
8671 11:08:13.885295
8672 11:08:13.885410 Set Vref, RX VrefLevel [Byte0]: 36
8673 11:08:13.888688 [Byte1]: 36
8674 11:08:13.893190
8675 11:08:13.893281 Set Vref, RX VrefLevel [Byte0]: 37
8676 11:08:13.896851 [Byte1]: 37
8677 11:08:13.900531
8678 11:08:13.900610 Set Vref, RX VrefLevel [Byte0]: 38
8679 11:08:13.904207 [Byte1]: 38
8680 11:08:13.908450
8681 11:08:13.908526 Set Vref, RX VrefLevel [Byte0]: 39
8682 11:08:13.911548 [Byte1]: 39
8683 11:08:13.916057
8684 11:08:13.916132 Set Vref, RX VrefLevel [Byte0]: 40
8685 11:08:13.919062 [Byte1]: 40
8686 11:08:13.923257
8687 11:08:13.923332 Set Vref, RX VrefLevel [Byte0]: 41
8688 11:08:13.926742 [Byte1]: 41
8689 11:08:13.930842
8690 11:08:13.930918 Set Vref, RX VrefLevel [Byte0]: 42
8691 11:08:13.934315 [Byte1]: 42
8692 11:08:13.938503
8693 11:08:13.938582 Set Vref, RX VrefLevel [Byte0]: 43
8694 11:08:13.941697 [Byte1]: 43
8695 11:08:13.946143
8696 11:08:13.946252 Set Vref, RX VrefLevel [Byte0]: 44
8697 11:08:13.949368 [Byte1]: 44
8698 11:08:13.953500
8699 11:08:13.953574 Set Vref, RX VrefLevel [Byte0]: 45
8700 11:08:13.959986 [Byte1]: 45
8701 11:08:13.960063
8702 11:08:13.963431 Set Vref, RX VrefLevel [Byte0]: 46
8703 11:08:13.966956 [Byte1]: 46
8704 11:08:13.967034
8705 11:08:13.970193 Set Vref, RX VrefLevel [Byte0]: 47
8706 11:08:13.973257 [Byte1]: 47
8707 11:08:13.976357
8708 11:08:13.976431 Set Vref, RX VrefLevel [Byte0]: 48
8709 11:08:13.979923 [Byte1]: 48
8710 11:08:13.984047
8711 11:08:13.984122 Set Vref, RX VrefLevel [Byte0]: 49
8712 11:08:13.987286 [Byte1]: 49
8713 11:08:13.991500
8714 11:08:13.991576 Set Vref, RX VrefLevel [Byte0]: 50
8715 11:08:13.994889 [Byte1]: 50
8716 11:08:13.999144
8717 11:08:13.999220 Set Vref, RX VrefLevel [Byte0]: 51
8718 11:08:14.002167 [Byte1]: 51
8719 11:08:14.006637
8720 11:08:14.006711 Set Vref, RX VrefLevel [Byte0]: 52
8721 11:08:14.010024 [Byte1]: 52
8722 11:08:14.014165
8723 11:08:14.014239 Set Vref, RX VrefLevel [Byte0]: 53
8724 11:08:14.017512 [Byte1]: 53
8725 11:08:14.021963
8726 11:08:14.022041 Set Vref, RX VrefLevel [Byte0]: 54
8727 11:08:14.025396 [Byte1]: 54
8728 11:08:14.029502
8729 11:08:14.029579 Set Vref, RX VrefLevel [Byte0]: 55
8730 11:08:14.032633 [Byte1]: 55
8731 11:08:14.037011
8732 11:08:14.037110 Set Vref, RX VrefLevel [Byte0]: 56
8733 11:08:14.039971 [Byte1]: 56
8734 11:08:14.044521
8735 11:08:14.044622 Set Vref, RX VrefLevel [Byte0]: 57
8736 11:08:14.047758 [Byte1]: 57
8737 11:08:14.052075
8738 11:08:14.052168 Set Vref, RX VrefLevel [Byte0]: 58
8739 11:08:14.055202 [Byte1]: 58
8740 11:08:14.060003
8741 11:08:14.060092 Set Vref, RX VrefLevel [Byte0]: 59
8742 11:08:14.063146 [Byte1]: 59
8743 11:08:14.067255
8744 11:08:14.067347 Set Vref, RX VrefLevel [Byte0]: 60
8745 11:08:14.070481 [Byte1]: 60
8746 11:08:14.074660
8747 11:08:14.074724 Set Vref, RX VrefLevel [Byte0]: 61
8748 11:08:14.077989 [Byte1]: 61
8749 11:08:14.082434
8750 11:08:14.082522 Set Vref, RX VrefLevel [Byte0]: 62
8751 11:08:14.085924 [Byte1]: 62
8752 11:08:14.090134
8753 11:08:14.090200 Set Vref, RX VrefLevel [Byte0]: 63
8754 11:08:14.093014 [Byte1]: 63
8755 11:08:14.097437
8756 11:08:14.097512 Set Vref, RX VrefLevel [Byte0]: 64
8757 11:08:14.100797 [Byte1]: 64
8758 11:08:14.105222
8759 11:08:14.105319 Set Vref, RX VrefLevel [Byte0]: 65
8760 11:08:14.108563 [Byte1]: 65
8761 11:08:14.112483
8762 11:08:14.112558 Set Vref, RX VrefLevel [Byte0]: 66
8763 11:08:14.115914 [Byte1]: 66
8764 11:08:14.120353
8765 11:08:14.120452 Set Vref, RX VrefLevel [Byte0]: 67
8766 11:08:14.123621 [Byte1]: 67
8767 11:08:14.128117
8768 11:08:14.128215 Set Vref, RX VrefLevel [Byte0]: 68
8769 11:08:14.131073 [Byte1]: 68
8770 11:08:14.135299
8771 11:08:14.135422 Set Vref, RX VrefLevel [Byte0]: 69
8772 11:08:14.138642 [Byte1]: 69
8773 11:08:14.143181
8774 11:08:14.143281 Set Vref, RX VrefLevel [Byte0]: 70
8775 11:08:14.146064 [Byte1]: 70
8776 11:08:14.150533
8777 11:08:14.150655 Set Vref, RX VrefLevel [Byte0]: 71
8778 11:08:14.154085 [Byte1]: 71
8779 11:08:14.158480
8780 11:08:14.158579 Set Vref, RX VrefLevel [Byte0]: 72
8781 11:08:14.161925 [Byte1]: 72
8782 11:08:14.165707
8783 11:08:14.165790 Set Vref, RX VrefLevel [Byte0]: 73
8784 11:08:14.168983 [Byte1]: 73
8785 11:08:14.173366
8786 11:08:14.173493 Set Vref, RX VrefLevel [Byte0]: 74
8787 11:08:14.176713 [Byte1]: 74
8788 11:08:14.180711
8789 11:08:14.180810 Final RX Vref Byte 0 = 53 to rank0
8790 11:08:14.184419 Final RX Vref Byte 1 = 55 to rank0
8791 11:08:14.187283 Final RX Vref Byte 0 = 53 to rank1
8792 11:08:14.191049 Final RX Vref Byte 1 = 55 to rank1==
8793 11:08:14.194005 Dram Type= 6, Freq= 0, CH_1, rank 0
8794 11:08:14.200566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 11:08:14.200665 ==
8796 11:08:14.200756 DQS Delay:
8797 11:08:14.204058 DQS0 = 0, DQS1 = 0
8798 11:08:14.204163 DQM Delay:
8799 11:08:14.204248 DQM0 = 134, DQM1 = 128
8800 11:08:14.207068 DQ Delay:
8801 11:08:14.210565 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8802 11:08:14.213914 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8803 11:08:14.217847 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =118
8804 11:08:14.220411 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =136
8805 11:08:14.220502
8806 11:08:14.220585
8807 11:08:14.220666
8808 11:08:14.223424 [DramC_TX_OE_Calibration] TA2
8809 11:08:14.226900 Original DQ_B0 (3 6) =30, OEN = 27
8810 11:08:14.230296 Original DQ_B1 (3 6) =30, OEN = 27
8811 11:08:14.233687 24, 0x0, End_B0=24 End_B1=24
8812 11:08:14.233787 25, 0x0, End_B0=25 End_B1=25
8813 11:08:14.237008 26, 0x0, End_B0=26 End_B1=26
8814 11:08:14.240147 27, 0x0, End_B0=27 End_B1=27
8815 11:08:14.243649 28, 0x0, End_B0=28 End_B1=28
8816 11:08:14.246916 29, 0x0, End_B0=29 End_B1=29
8817 11:08:14.247010 30, 0x0, End_B0=30 End_B1=30
8818 11:08:14.250359 31, 0x4141, End_B0=30 End_B1=30
8819 11:08:14.253303 Byte0 end_step=30 best_step=27
8820 11:08:14.256515 Byte1 end_step=30 best_step=27
8821 11:08:14.260157 Byte0 TX OE(2T, 0.5T) = (3, 3)
8822 11:08:14.263537 Byte1 TX OE(2T, 0.5T) = (3, 3)
8823 11:08:14.263613
8824 11:08:14.263670
8825 11:08:14.269930 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8826 11:08:14.273160 CH1 RK0: MR19=303, MR18=180E
8827 11:08:14.279999 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8828 11:08:14.280071
8829 11:08:14.282889 ----->DramcWriteLeveling(PI) begin...
8830 11:08:14.282993 ==
8831 11:08:14.286280 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 11:08:14.289647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 11:08:14.289745 ==
8834 11:08:14.293172 Write leveling (Byte 0): 24 => 24
8835 11:08:14.296377 Write leveling (Byte 1): 27 => 27
8836 11:08:14.299951 DramcWriteLeveling(PI) end<-----
8837 11:08:14.300040
8838 11:08:14.300120 ==
8839 11:08:14.302867 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 11:08:14.306368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 11:08:14.309451 ==
8842 11:08:14.309542 [Gating] SW mode calibration
8843 11:08:14.319332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8844 11:08:14.322719 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8845 11:08:14.325922 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 11:08:14.332471 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:08:14.335931 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 11:08:14.339294 1 4 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8849 11:08:14.345920 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8850 11:08:14.349301 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 11:08:14.352646 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 11:08:14.358841 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 11:08:14.362419 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 11:08:14.365326 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 11:08:14.372225 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8856 11:08:14.375372 1 5 12 | B1->B0 | 2a2a 3434 | 0 1 | (1 0) (1 0)
8857 11:08:14.378797 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 11:08:14.385546 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 11:08:14.388858 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 11:08:14.392045 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 11:08:14.398872 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 11:08:14.402318 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 11:08:14.405705 1 6 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8864 11:08:14.412038 1 6 12 | B1->B0 | 4545 3030 | 0 0 | (0 0) (0 0)
8865 11:08:14.415405 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 11:08:14.418359 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 11:08:14.425275 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 11:08:14.428406 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 11:08:14.431845 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 11:08:14.438279 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 11:08:14.442035 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8872 11:08:14.445175 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8873 11:08:14.451643 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8874 11:08:14.454789 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:08:14.458157 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 11:08:14.464944 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 11:08:14.468129 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 11:08:14.471630 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 11:08:14.477801 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 11:08:14.481518 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 11:08:14.484585 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 11:08:14.491342 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 11:08:14.494617 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 11:08:14.497589 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 11:08:14.504330 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 11:08:14.507686 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 11:08:14.511029 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8888 11:08:14.517814 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8889 11:08:14.517885 Total UI for P1: 0, mck2ui 16
8890 11:08:14.523978 best dqsien dly found for B1: ( 1, 9, 8)
8891 11:08:14.527628 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8892 11:08:14.530460 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 11:08:14.534042 Total UI for P1: 0, mck2ui 16
8894 11:08:14.536955 best dqsien dly found for B0: ( 1, 9, 12)
8895 11:08:14.540572 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8896 11:08:14.544094 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8897 11:08:14.544162
8898 11:08:14.550457 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8899 11:08:14.553669 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8900 11:08:14.556849 [Gating] SW calibration Done
8901 11:08:14.556930 ==
8902 11:08:14.560174 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 11:08:14.563670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 11:08:14.563735 ==
8905 11:08:14.563789 RX Vref Scan: 0
8906 11:08:14.563841
8907 11:08:14.566874 RX Vref 0 -> 0, step: 1
8908 11:08:14.566934
8909 11:08:14.570596 RX Delay 0 -> 252, step: 8
8910 11:08:14.573127 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8911 11:08:14.576758 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8912 11:08:14.583376 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8913 11:08:14.586635 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8914 11:08:14.590102 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8915 11:08:14.593615 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8916 11:08:14.596323 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8917 11:08:14.603013 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8918 11:08:14.606152 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8919 11:08:14.609756 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8920 11:08:14.612695 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8921 11:08:14.616263 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8922 11:08:14.622633 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8923 11:08:14.626004 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8924 11:08:14.629184 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8925 11:08:14.633059 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8926 11:08:14.633167 ==
8927 11:08:14.635923 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:08:14.642903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:08:14.643011 ==
8930 11:08:14.643102 DQS Delay:
8931 11:08:14.645997 DQS0 = 0, DQS1 = 0
8932 11:08:14.646088 DQM Delay:
8933 11:08:14.649088 DQM0 = 136, DQM1 = 129
8934 11:08:14.649162 DQ Delay:
8935 11:08:14.652524 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8936 11:08:14.655961 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8937 11:08:14.659328 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8938 11:08:14.662353 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8939 11:08:14.662445
8940 11:08:14.662530
8941 11:08:14.662610 ==
8942 11:08:14.665512 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 11:08:14.672629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 11:08:14.672721 ==
8945 11:08:14.672804
8946 11:08:14.672883
8947 11:08:14.672961 TX Vref Scan disable
8948 11:08:14.675893 == TX Byte 0 ==
8949 11:08:14.679198 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8950 11:08:14.685288 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8951 11:08:14.685386 == TX Byte 1 ==
8952 11:08:14.688730 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8953 11:08:14.695365 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8954 11:08:14.695494 ==
8955 11:08:14.698709 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 11:08:14.702267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 11:08:14.702358 ==
8958 11:08:14.714710
8959 11:08:14.717780 TX Vref early break, caculate TX vref
8960 11:08:14.721345 TX Vref=16, minBit 1, minWin=22, winSum=384
8961 11:08:14.724649 TX Vref=18, minBit 0, minWin=23, winSum=391
8962 11:08:14.727782 TX Vref=20, minBit 1, minWin=24, winSum=407
8963 11:08:14.731343 TX Vref=22, minBit 0, minWin=24, winSum=406
8964 11:08:14.734635 TX Vref=24, minBit 0, minWin=26, winSum=419
8965 11:08:14.741158 TX Vref=26, minBit 0, minWin=26, winSum=426
8966 11:08:14.744342 TX Vref=28, minBit 0, minWin=26, winSum=426
8967 11:08:14.747529 TX Vref=30, minBit 1, minWin=24, winSum=412
8968 11:08:14.750843 TX Vref=32, minBit 0, minWin=24, winSum=410
8969 11:08:14.754103 TX Vref=34, minBit 0, minWin=24, winSum=401
8970 11:08:14.760872 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8971 11:08:14.760962
8972 11:08:14.764413 Final TX Range 0 Vref 26
8973 11:08:14.764479
8974 11:08:14.764533 ==
8975 11:08:14.767283 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 11:08:14.770884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 11:08:14.770952 ==
8978 11:08:14.771031
8979 11:08:14.771108
8980 11:08:14.773923 TX Vref Scan disable
8981 11:08:14.781037 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8982 11:08:14.781131 == TX Byte 0 ==
8983 11:08:14.783961 u2DelayCellOfst[0]=22 cells (6 PI)
8984 11:08:14.787329 u2DelayCellOfst[1]=11 cells (3 PI)
8985 11:08:14.790486 u2DelayCellOfst[2]=0 cells (0 PI)
8986 11:08:14.793839 u2DelayCellOfst[3]=7 cells (2 PI)
8987 11:08:14.797118 u2DelayCellOfst[4]=7 cells (2 PI)
8988 11:08:14.800696 u2DelayCellOfst[5]=22 cells (6 PI)
8989 11:08:14.803755 u2DelayCellOfst[6]=18 cells (5 PI)
8990 11:08:14.807181 u2DelayCellOfst[7]=3 cells (1 PI)
8991 11:08:14.810740 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8992 11:08:14.813900 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8993 11:08:14.816807 == TX Byte 1 ==
8994 11:08:14.820395 u2DelayCellOfst[8]=0 cells (0 PI)
8995 11:08:14.820461 u2DelayCellOfst[9]=7 cells (2 PI)
8996 11:08:14.823631 u2DelayCellOfst[10]=11 cells (3 PI)
8997 11:08:14.826858 u2DelayCellOfst[11]=7 cells (2 PI)
8998 11:08:14.830411 u2DelayCellOfst[12]=15 cells (4 PI)
8999 11:08:14.833629 u2DelayCellOfst[13]=18 cells (5 PI)
9000 11:08:14.836784 u2DelayCellOfst[14]=18 cells (5 PI)
9001 11:08:14.840562 u2DelayCellOfst[15]=18 cells (5 PI)
9002 11:08:14.846910 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9003 11:08:14.850009 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9004 11:08:14.850103 DramC Write-DBI on
9005 11:08:14.850187 ==
9006 11:08:14.853071 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 11:08:14.860063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 11:08:14.860132 ==
9009 11:08:14.860187
9010 11:08:14.860242
9011 11:08:14.860294 TX Vref Scan disable
9012 11:08:14.863863 == TX Byte 0 ==
9013 11:08:14.867313 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9014 11:08:14.870651 == TX Byte 1 ==
9015 11:08:14.873968 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9016 11:08:14.877184 DramC Write-DBI off
9017 11:08:14.877276
9018 11:08:14.877357 [DATLAT]
9019 11:08:14.877439 Freq=1600, CH1 RK1
9020 11:08:14.877518
9021 11:08:14.880366 DATLAT Default: 0xf
9022 11:08:14.883828 0, 0xFFFF, sum = 0
9023 11:08:14.883937 1, 0xFFFF, sum = 0
9024 11:08:14.887109 2, 0xFFFF, sum = 0
9025 11:08:14.887204 3, 0xFFFF, sum = 0
9026 11:08:14.890531 4, 0xFFFF, sum = 0
9027 11:08:14.890597 5, 0xFFFF, sum = 0
9028 11:08:14.893888 6, 0xFFFF, sum = 0
9029 11:08:14.893979 7, 0xFFFF, sum = 0
9030 11:08:14.896997 8, 0xFFFF, sum = 0
9031 11:08:14.897085 9, 0xFFFF, sum = 0
9032 11:08:14.900736 10, 0xFFFF, sum = 0
9033 11:08:14.900828 11, 0xFFFF, sum = 0
9034 11:08:14.903423 12, 0xFFFF, sum = 0
9035 11:08:14.903547 13, 0xFFFF, sum = 0
9036 11:08:14.906640 14, 0x0, sum = 1
9037 11:08:14.906730 15, 0x0, sum = 2
9038 11:08:14.910076 16, 0x0, sum = 3
9039 11:08:14.910168 17, 0x0, sum = 4
9040 11:08:14.913369 best_step = 15
9041 11:08:14.913455
9042 11:08:14.913535 ==
9043 11:08:14.916974 Dram Type= 6, Freq= 0, CH_1, rank 1
9044 11:08:14.919764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9045 11:08:14.919828 ==
9046 11:08:14.923284 RX Vref Scan: 0
9047 11:08:14.923368
9048 11:08:14.923482 RX Vref 0 -> 0, step: 1
9049 11:08:14.923534
9050 11:08:14.926785 RX Delay 11 -> 252, step: 4
9051 11:08:14.933119 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9052 11:08:14.936650 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9053 11:08:14.939532 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9054 11:08:14.943346 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9055 11:08:14.946189 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9056 11:08:14.952700 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9057 11:08:14.956512 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9058 11:08:14.959324 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9059 11:08:14.962643 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9060 11:08:14.966313 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9061 11:08:14.972710 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9062 11:08:14.976163 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9063 11:08:14.979071 iDelay=203, Bit 12, Center 136 (79 ~ 194) 116
9064 11:08:14.982732 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9065 11:08:14.989165 iDelay=203, Bit 14, Center 130 (75 ~ 186) 112
9066 11:08:14.992287 iDelay=203, Bit 15, Center 136 (83 ~ 190) 108
9067 11:08:14.992369 ==
9068 11:08:14.995597 Dram Type= 6, Freq= 0, CH_1, rank 1
9069 11:08:14.998872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9070 11:08:14.998971 ==
9071 11:08:15.002323 DQS Delay:
9072 11:08:15.002399 DQS0 = 0, DQS1 = 0
9073 11:08:15.002458 DQM Delay:
9074 11:08:15.005694 DQM0 = 134, DQM1 = 125
9075 11:08:15.005771 DQ Delay:
9076 11:08:15.009122 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9077 11:08:15.012051 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9078 11:08:15.015400 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9079 11:08:15.022481 DQ12 =136, DQ13 =134, DQ14 =130, DQ15 =136
9080 11:08:15.022567
9081 11:08:15.022634
9082 11:08:15.022694
9083 11:08:15.025204 [DramC_TX_OE_Calibration] TA2
9084 11:08:15.028595 Original DQ_B0 (3 6) =30, OEN = 27
9085 11:08:15.028711 Original DQ_B1 (3 6) =30, OEN = 27
9086 11:08:15.031819 24, 0x0, End_B0=24 End_B1=24
9087 11:08:15.035470 25, 0x0, End_B0=25 End_B1=25
9088 11:08:15.039047 26, 0x0, End_B0=26 End_B1=26
9089 11:08:15.041901 27, 0x0, End_B0=27 End_B1=27
9090 11:08:15.042018 28, 0x0, End_B0=28 End_B1=28
9091 11:08:15.045160 29, 0x0, End_B0=29 End_B1=29
9092 11:08:15.048544 30, 0x0, End_B0=30 End_B1=30
9093 11:08:15.051987 31, 0x4141, End_B0=30 End_B1=30
9094 11:08:15.055272 Byte0 end_step=30 best_step=27
9095 11:08:15.058439 Byte1 end_step=30 best_step=27
9096 11:08:15.058679 Byte0 TX OE(2T, 0.5T) = (3, 3)
9097 11:08:15.061905 Byte1 TX OE(2T, 0.5T) = (3, 3)
9098 11:08:15.062258
9099 11:08:15.062581
9100 11:08:15.071782 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9101 11:08:15.075029 CH1 RK1: MR19=303, MR18=D0A
9102 11:08:15.078490 CH1_RK1: MR19=0x303, MR18=0xD0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9103 11:08:15.082180 [RxdqsGatingPostProcess] freq 1600
9104 11:08:15.088508 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9105 11:08:15.091947 best DQS0 dly(2T, 0.5T) = (1, 1)
9106 11:08:15.095072 best DQS1 dly(2T, 0.5T) = (1, 1)
9107 11:08:15.098337 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9108 11:08:15.101567 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9109 11:08:15.104931 best DQS0 dly(2T, 0.5T) = (1, 1)
9110 11:08:15.105573 best DQS1 dly(2T, 0.5T) = (1, 1)
9111 11:08:15.108586 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9112 11:08:15.111304 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9113 11:08:15.115203 Pre-setting of DQS Precalculation
9114 11:08:15.121726 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9115 11:08:15.128323 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9116 11:08:15.134691 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 11:08:15.135071
9118 11:08:15.135363
9119 11:08:15.137998 [Calibration Summary] 3200 Mbps
9120 11:08:15.141438 CH 0, Rank 0
9121 11:08:15.141887 SW Impedance : PASS
9122 11:08:15.144469 DUTY Scan : NO K
9123 11:08:15.147772 ZQ Calibration : PASS
9124 11:08:15.148135 Jitter Meter : NO K
9125 11:08:15.150713 CBT Training : PASS
9126 11:08:15.154567 Write leveling : PASS
9127 11:08:15.154994 RX DQS gating : PASS
9128 11:08:15.157589 RX DQ/DQS(RDDQC) : PASS
9129 11:08:15.157967 TX DQ/DQS : PASS
9130 11:08:15.160833 RX DATLAT : PASS
9131 11:08:15.164479 RX DQ/DQS(Engine): PASS
9132 11:08:15.164910 TX OE : PASS
9133 11:08:15.167630 All Pass.
9134 11:08:15.168006
9135 11:08:15.168347 CH 0, Rank 1
9136 11:08:15.170618 SW Impedance : PASS
9137 11:08:15.170997 DUTY Scan : NO K
9138 11:08:15.174584 ZQ Calibration : PASS
9139 11:08:15.177698 Jitter Meter : NO K
9140 11:08:15.178077 CBT Training : PASS
9141 11:08:15.180843 Write leveling : PASS
9142 11:08:15.183658 RX DQS gating : PASS
9143 11:08:15.184057 RX DQ/DQS(RDDQC) : PASS
9144 11:08:15.187320 TX DQ/DQS : PASS
9145 11:08:15.190320 RX DATLAT : PASS
9146 11:08:15.190702 RX DQ/DQS(Engine): PASS
9147 11:08:15.193673 TX OE : PASS
9148 11:08:15.194059 All Pass.
9149 11:08:15.194352
9150 11:08:15.197276 CH 1, Rank 0
9151 11:08:15.197663 SW Impedance : PASS
9152 11:08:15.200748 DUTY Scan : NO K
9153 11:08:15.203981 ZQ Calibration : PASS
9154 11:08:15.204425 Jitter Meter : NO K
9155 11:08:15.206828 CBT Training : PASS
9156 11:08:15.210306 Write leveling : PASS
9157 11:08:15.210874 RX DQS gating : PASS
9158 11:08:15.213590 RX DQ/DQS(RDDQC) : PASS
9159 11:08:15.216948 TX DQ/DQS : PASS
9160 11:08:15.217582 RX DATLAT : PASS
9161 11:08:15.220481 RX DQ/DQS(Engine): PASS
9162 11:08:15.223539 TX OE : PASS
9163 11:08:15.223936 All Pass.
9164 11:08:15.224326
9165 11:08:15.224759 CH 1, Rank 1
9166 11:08:15.226686 SW Impedance : PASS
9167 11:08:15.229684 DUTY Scan : NO K
9168 11:08:15.230183 ZQ Calibration : PASS
9169 11:08:15.233155 Jitter Meter : NO K
9170 11:08:15.236619 CBT Training : PASS
9171 11:08:15.237126 Write leveling : PASS
9172 11:08:15.239861 RX DQS gating : PASS
9173 11:08:15.242909 RX DQ/DQS(RDDQC) : PASS
9174 11:08:15.243297 TX DQ/DQS : PASS
9175 11:08:15.246402 RX DATLAT : PASS
9176 11:08:15.246787 RX DQ/DQS(Engine): PASS
9177 11:08:15.249487 TX OE : PASS
9178 11:08:15.250017 All Pass.
9179 11:08:15.250332
9180 11:08:15.252785 DramC Write-DBI on
9181 11:08:15.256687 PER_BANK_REFRESH: Hybrid Mode
9182 11:08:15.257180 TX_TRACKING: ON
9183 11:08:15.266096 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9184 11:08:15.272644 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9185 11:08:15.282782 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9186 11:08:15.286141 [FAST_K] Save calibration result to emmc
9187 11:08:15.289637 sync common calibartion params.
9188 11:08:15.290179 sync cbt_mode0:1, 1:1
9189 11:08:15.293014 dram_init: ddr_geometry: 2
9190 11:08:15.296233 dram_init: ddr_geometry: 2
9191 11:08:15.296773 dram_init: ddr_geometry: 2
9192 11:08:15.299222 0:dram_rank_size:100000000
9193 11:08:15.303360 1:dram_rank_size:100000000
9194 11:08:15.306151 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9195 11:08:15.309088 DFS_SHUFFLE_HW_MODE: ON
9196 11:08:15.312453 dramc_set_vcore_voltage set vcore to 725000
9197 11:08:15.315679 Read voltage for 1600, 0
9198 11:08:15.316105 Vio18 = 0
9199 11:08:15.319282 Vcore = 725000
9200 11:08:15.319765 Vdram = 0
9201 11:08:15.320075 Vddq = 0
9202 11:08:15.320411 Vmddr = 0
9203 11:08:15.322567 switch to 3200 Mbps bootup
9204 11:08:15.326028 [DramcRunTimeConfig]
9205 11:08:15.326534 PHYPLL
9206 11:08:15.328904 DPM_CONTROL_AFTERK: ON
9207 11:08:15.329429 PER_BANK_REFRESH: ON
9208 11:08:15.332391 REFRESH_OVERHEAD_REDUCTION: ON
9209 11:08:15.335833 CMD_PICG_NEW_MODE: OFF
9210 11:08:15.336263 XRTWTW_NEW_MODE: ON
9211 11:08:15.338712 XRTRTR_NEW_MODE: ON
9212 11:08:15.339182 TX_TRACKING: ON
9213 11:08:15.342951 RDSEL_TRACKING: OFF
9214 11:08:15.345587 DQS Precalculation for DVFS: ON
9215 11:08:15.345966 RX_TRACKING: OFF
9216 11:08:15.348934 HW_GATING DBG: ON
9217 11:08:15.349335 ZQCS_ENABLE_LP4: ON
9218 11:08:15.352198 RX_PICG_NEW_MODE: ON
9219 11:08:15.352735 TX_PICG_NEW_MODE: ON
9220 11:08:15.355570 ENABLE_RX_DCM_DPHY: ON
9221 11:08:15.358844 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9222 11:08:15.361998 DUMMY_READ_FOR_TRACKING: OFF
9223 11:08:15.362379 !!! SPM_CONTROL_AFTERK: OFF
9224 11:08:15.365381 !!! SPM could not control APHY
9225 11:08:15.368848 IMPEDANCE_TRACKING: ON
9226 11:08:15.369251 TEMP_SENSOR: ON
9227 11:08:15.371980 HW_SAVE_FOR_SR: OFF
9228 11:08:15.375389 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9229 11:08:15.378425 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9230 11:08:15.381473 Read ODT Tracking: ON
9231 11:08:15.381543 Refresh Rate DeBounce: ON
9232 11:08:15.384644 DFS_NO_QUEUE_FLUSH: ON
9233 11:08:15.388137 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9234 11:08:15.391072 ENABLE_DFS_RUNTIME_MRW: OFF
9235 11:08:15.391134 DDR_RESERVE_NEW_MODE: ON
9236 11:08:15.394415 MR_CBT_SWITCH_FREQ: ON
9237 11:08:15.397915 =========================
9238 11:08:15.415768 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9239 11:08:15.418372 dram_init: ddr_geometry: 2
9240 11:08:15.437005 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9241 11:08:15.440030 dram_init: dram init end (result: 0)
9242 11:08:15.446796 DRAM-K: Full calibration passed in 24641 msecs
9243 11:08:15.450136 MRC: failed to locate region type 0.
9244 11:08:15.450350 DRAM rank0 size:0x100000000,
9245 11:08:15.453863 DRAM rank1 size=0x100000000
9246 11:08:15.463216 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9247 11:08:15.470590 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9248 11:08:15.476749 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9249 11:08:15.483482 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9250 11:08:15.486706 DRAM rank0 size:0x100000000,
9251 11:08:15.490263 DRAM rank1 size=0x100000000
9252 11:08:15.490647 CBMEM:
9253 11:08:15.493382 IMD: root @ 0xfffff000 254 entries.
9254 11:08:15.496901 IMD: root @ 0xffffec00 62 entries.
9255 11:08:15.500186 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9256 11:08:15.506895 WARNING: RO_VPD is uninitialized or empty.
9257 11:08:15.510246 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9258 11:08:15.517233 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9259 11:08:15.530204 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9260 11:08:15.541379 BS: romstage times (exec / console): total (unknown) / 24128 ms
9261 11:08:15.541766
9262 11:08:15.542061
9263 11:08:15.551204 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9264 11:08:15.554671 ARM64: Exception handlers installed.
9265 11:08:15.557653 ARM64: Testing exception
9266 11:08:15.561174 ARM64: Done test exception
9267 11:08:15.561555 Enumerating buses...
9268 11:08:15.564043 Show all devs... Before device enumeration.
9269 11:08:15.567790 Root Device: enabled 1
9270 11:08:15.571145 CPU_CLUSTER: 0: enabled 1
9271 11:08:15.571676 CPU: 00: enabled 1
9272 11:08:15.574633 Compare with tree...
9273 11:08:15.575025 Root Device: enabled 1
9274 11:08:15.577203 CPU_CLUSTER: 0: enabled 1
9275 11:08:15.581101 CPU: 00: enabled 1
9276 11:08:15.581591 Root Device scanning...
9277 11:08:15.584307 scan_static_bus for Root Device
9278 11:08:15.587169 CPU_CLUSTER: 0 enabled
9279 11:08:15.591021 scan_static_bus for Root Device done
9280 11:08:15.594207 scan_bus: bus Root Device finished in 8 msecs
9281 11:08:15.594635 done
9282 11:08:15.600805 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9283 11:08:15.604314 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9284 11:08:15.610720 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9285 11:08:15.617137 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9286 11:08:15.617525 Allocating resources...
9287 11:08:15.620023 Reading resources...
9288 11:08:15.623391 Root Device read_resources bus 0 link: 0
9289 11:08:15.626952 DRAM rank0 size:0x100000000,
9290 11:08:15.627504 DRAM rank1 size=0x100000000
9291 11:08:15.633611 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9292 11:08:15.634206 CPU: 00 missing read_resources
9293 11:08:15.640030 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9294 11:08:15.643463 Root Device read_resources bus 0 link: 0 done
9295 11:08:15.647242 Done reading resources.
9296 11:08:15.649739 Show resources in subtree (Root Device)...After reading.
9297 11:08:15.653343 Root Device child on link 0 CPU_CLUSTER: 0
9298 11:08:15.656215 CPU_CLUSTER: 0 child on link 0 CPU: 00
9299 11:08:15.666673 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9300 11:08:15.666930 CPU: 00
9301 11:08:15.672904 Root Device assign_resources, bus 0 link: 0
9302 11:08:15.676327 CPU_CLUSTER: 0 missing set_resources
9303 11:08:15.679263 Root Device assign_resources, bus 0 link: 0 done
9304 11:08:15.682665 Done setting resources.
9305 11:08:15.685839 Show resources in subtree (Root Device)...After assigning values.
9306 11:08:15.689448 Root Device child on link 0 CPU_CLUSTER: 0
9307 11:08:15.695960 CPU_CLUSTER: 0 child on link 0 CPU: 00
9308 11:08:15.702577 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9309 11:08:15.705937 CPU: 00
9310 11:08:15.706226 Done allocating resources.
9311 11:08:15.712345 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9312 11:08:15.712586 Enabling resources...
9313 11:08:15.715361 done.
9314 11:08:15.718926 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9315 11:08:15.722292 Initializing devices...
9316 11:08:15.722559 Root Device init
9317 11:08:15.725930 init hardware done!
9318 11:08:15.726196 0x00000018: ctrlr->caps
9319 11:08:15.728969 52.000 MHz: ctrlr->f_max
9320 11:08:15.732350 0.400 MHz: ctrlr->f_min
9321 11:08:15.735495 0x40ff8080: ctrlr->voltages
9322 11:08:15.735729 sclk: 390625
9323 11:08:15.735921 Bus Width = 1
9324 11:08:15.738793 sclk: 390625
9325 11:08:15.739092 Bus Width = 1
9326 11:08:15.742123 Early init status = 3
9327 11:08:15.745539 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9328 11:08:15.749176 in-header: 03 fc 00 00 01 00 00 00
9329 11:08:15.752269 in-data: 00
9330 11:08:15.755699 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9331 11:08:15.761075 in-header: 03 fd 00 00 00 00 00 00
9332 11:08:15.764254 in-data:
9333 11:08:15.767561 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9334 11:08:15.775422 in-header: 03 fc 00 00 01 00 00 00
9335 11:08:15.775857 in-data: 00
9336 11:08:15.778670 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9337 11:08:15.784710 in-header: 03 fd 00 00 00 00 00 00
9338 11:08:15.787825 in-data:
9339 11:08:15.791145 [SSUSB] Setting up USB HOST controller...
9340 11:08:15.794339 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9341 11:08:15.797632 [SSUSB] phy power-on done.
9342 11:08:15.800666 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9343 11:08:15.807704 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9344 11:08:15.810528 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9345 11:08:15.817026 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9346 11:08:15.824045 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9347 11:08:15.830554 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9348 11:08:15.837441 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9349 11:08:15.843801 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9350 11:08:15.847214 SPM: binary array size = 0x9dc
9351 11:08:15.850106 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9352 11:08:15.857225 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9353 11:08:15.863435 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9354 11:08:15.870106 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9355 11:08:15.873299 configure_display: Starting display init
9356 11:08:15.907358 anx7625_power_on_init: Init interface.
9357 11:08:15.910687 anx7625_disable_pd_protocol: Disabled PD feature.
9358 11:08:15.913968 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9359 11:08:15.941575 anx7625_start_dp_work: Secure OCM version=00
9360 11:08:15.944964 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9361 11:08:15.959814 sp_tx_get_edid_block: EDID Block = 1
9362 11:08:16.062609 Extracted contents:
9363 11:08:16.065879 header: 00 ff ff ff ff ff ff 00
9364 11:08:16.069202 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9365 11:08:16.072143 version: 01 04
9366 11:08:16.075944 basic params: 95 1f 11 78 0a
9367 11:08:16.079333 chroma info: 76 90 94 55 54 90 27 21 50 54
9368 11:08:16.082853 established: 00 00 00
9369 11:08:16.089529 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9370 11:08:16.095587 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9371 11:08:16.099263 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 11:08:16.105195 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9373 11:08:16.112277 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9374 11:08:16.115533 extensions: 00
9375 11:08:16.115981 checksum: fb
9376 11:08:16.116312
9377 11:08:16.122185 Manufacturer: IVO Model 57d Serial Number 0
9378 11:08:16.122595 Made week 0 of 2020
9379 11:08:16.125173 EDID version: 1.4
9380 11:08:16.125424 Digital display
9381 11:08:16.128521 6 bits per primary color channel
9382 11:08:16.131382 DisplayPort interface
9383 11:08:16.131507 Maximum image size: 31 cm x 17 cm
9384 11:08:16.134908 Gamma: 220%
9385 11:08:16.134984 Check DPMS levels
9386 11:08:16.141330 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9387 11:08:16.144772 First detailed timing is preferred timing
9388 11:08:16.148527 Established timings supported:
9389 11:08:16.148598 Standard timings supported:
9390 11:08:16.151100 Detailed timings
9391 11:08:16.154564 Hex of detail: 383680a07038204018303c0035ae10000019
9392 11:08:16.160930 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9393 11:08:16.164360 0780 0798 07c8 0820 hborder 0
9394 11:08:16.167857 0438 043b 0447 0458 vborder 0
9395 11:08:16.171476 -hsync -vsync
9396 11:08:16.171553 Did detailed timing
9397 11:08:16.177457 Hex of detail: 000000000000000000000000000000000000
9398 11:08:16.181390 Manufacturer-specified data, tag 0
9399 11:08:16.184041 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9400 11:08:16.187599 ASCII string: InfoVision
9401 11:08:16.191095 Hex of detail: 000000fe00523134304e574635205248200a
9402 11:08:16.194209 ASCII string: R140NWF5 RH
9403 11:08:16.194292 Checksum
9404 11:08:16.197733 Checksum: 0xfb (valid)
9405 11:08:16.201098 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9406 11:08:16.203892 DSI data_rate: 832800000 bps
9407 11:08:16.210871 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9408 11:08:16.213813 anx7625_parse_edid: pixelclock(138800).
9409 11:08:16.217109 hactive(1920), hsync(48), hfp(24), hbp(88)
9410 11:08:16.220654 vactive(1080), vsync(12), vfp(3), vbp(17)
9411 11:08:16.224168 anx7625_dsi_config: config dsi.
9412 11:08:16.230840 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9413 11:08:16.245045 anx7625_dsi_config: success to config DSI
9414 11:08:16.248395 anx7625_dp_start: MIPI phy setup OK.
9415 11:08:16.251393 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9416 11:08:16.254607 mtk_ddp_mode_set invalid vrefresh 60
9417 11:08:16.257940 main_disp_path_setup
9418 11:08:16.258324 ovl_layer_smi_id_en
9419 11:08:16.261385 ovl_layer_smi_id_en
9420 11:08:16.261764 ccorr_config
9421 11:08:16.262089 aal_config
9422 11:08:16.264640 gamma_config
9423 11:08:16.265026 postmask_config
9424 11:08:16.268040 dither_config
9425 11:08:16.270971 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9426 11:08:16.277598 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9427 11:08:16.280857 Root Device init finished in 554 msecs
9428 11:08:16.284338 CPU_CLUSTER: 0 init
9429 11:08:16.291404 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9430 11:08:16.297603 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9431 11:08:16.297989 APU_MBOX 0x190000b0 = 0x10001
9432 11:08:16.301088 APU_MBOX 0x190001b0 = 0x10001
9433 11:08:16.304025 APU_MBOX 0x190005b0 = 0x10001
9434 11:08:16.307222 APU_MBOX 0x190006b0 = 0x10001
9435 11:08:16.313817 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9436 11:08:16.323656 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9437 11:08:16.335956 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9438 11:08:16.342745 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9439 11:08:16.354779 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9440 11:08:16.364045 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9441 11:08:16.367098 CPU_CLUSTER: 0 init finished in 81 msecs
9442 11:08:16.370212 Devices initialized
9443 11:08:16.373310 Show all devs... After init.
9444 11:08:16.373693 Root Device: enabled 1
9445 11:08:16.376868 CPU_CLUSTER: 0: enabled 1
9446 11:08:16.380221 CPU: 00: enabled 1
9447 11:08:16.383949 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9448 11:08:16.386744 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9449 11:08:16.389789 ELOG: NV offset 0x57f000 size 0x1000
9450 11:08:16.396647 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9451 11:08:16.403261 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9452 11:08:16.406874 ELOG: Event(17) added with size 13 at 2024-07-10 11:08:16 UTC
9453 11:08:16.413732 out: cmd=0x121: 03 db 21 01 00 00 00 00
9454 11:08:16.416652 in-header: 03 37 00 00 2c 00 00 00
9455 11:08:16.429910 in-data: 05 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9456 11:08:16.433068 ELOG: Event(A1) added with size 10 at 2024-07-10 11:08:16 UTC
9457 11:08:16.439631 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9458 11:08:16.446138 ELOG: Event(A0) added with size 9 at 2024-07-10 11:08:16 UTC
9459 11:08:16.449599 elog_add_boot_reason: Logged dev mode boot
9460 11:08:16.455922 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9461 11:08:16.456327 Finalize devices...
9462 11:08:16.459340 Devices finalized
9463 11:08:16.462814 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9464 11:08:16.465943 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9465 11:08:16.469815 in-header: 03 07 00 00 08 00 00 00
9466 11:08:16.472747 in-data: aa e4 47 04 13 02 00 00
9467 11:08:16.476268 Chrome EC: UHEPI supported
9468 11:08:16.482803 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9469 11:08:16.485995 in-header: 03 a9 00 00 08 00 00 00
9470 11:08:16.489464 in-data: 84 60 60 08 00 00 00 00
9471 11:08:16.496011 ELOG: Event(91) added with size 10 at 2024-07-10 11:08:16 UTC
9472 11:08:16.499667 Chrome EC: clear events_b mask to 0x0000000020004000
9473 11:08:16.505937 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9474 11:08:16.509054 in-header: 03 fd 00 00 00 00 00 00
9475 11:08:16.512432 in-data:
9476 11:08:16.516020 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9477 11:08:16.518871 Writing coreboot table at 0xffe64000
9478 11:08:16.525554 0. 000000000010a000-0000000000113fff: RAMSTAGE
9479 11:08:16.529036 1. 0000000040000000-00000000400fffff: RAM
9480 11:08:16.532373 2. 0000000040100000-000000004032afff: RAMSTAGE
9481 11:08:16.535655 3. 000000004032b000-00000000545fffff: RAM
9482 11:08:16.538874 4. 0000000054600000-000000005465ffff: BL31
9483 11:08:16.545367 5. 0000000054660000-00000000ffe63fff: RAM
9484 11:08:16.548945 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9485 11:08:16.551646 7. 0000000100000000-000000023fffffff: RAM
9486 11:08:16.555276 Passing 5 GPIOs to payload:
9487 11:08:16.558345 NAME | PORT | POLARITY | VALUE
9488 11:08:16.564808 EC in RW | 0x000000aa | low | undefined
9489 11:08:16.568261 EC interrupt | 0x00000005 | low | undefined
9490 11:08:16.574535 TPM interrupt | 0x000000ab | high | undefined
9491 11:08:16.578030 SD card detect | 0x00000011 | high | undefined
9492 11:08:16.584755 speaker enable | 0x00000093 | high | undefined
9493 11:08:16.588114 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9494 11:08:16.591485 in-header: 03 f9 00 00 02 00 00 00
9495 11:08:16.591559 in-data: 02 00
9496 11:08:16.594589 ADC[4]: Raw value=901552 ID=7
9497 11:08:16.597525 ADC[3]: Raw value=213282 ID=1
9498 11:08:16.597622 RAM Code: 0x71
9499 11:08:16.601411 ADC[6]: Raw value=75036 ID=0
9500 11:08:16.604592 ADC[5]: Raw value=213282 ID=1
9501 11:08:16.604666 SKU Code: 0x1
9502 11:08:16.610958 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3539
9503 11:08:16.614149 coreboot table: 964 bytes.
9504 11:08:16.617967 IMD ROOT 0. 0xfffff000 0x00001000
9505 11:08:16.620782 IMD SMALL 1. 0xffffe000 0x00001000
9506 11:08:16.624398 RO MCACHE 2. 0xffffc000 0x00001104
9507 11:08:16.627259 CONSOLE 3. 0xfff7c000 0x00080000
9508 11:08:16.630850 FMAP 4. 0xfff7b000 0x00000452
9509 11:08:16.634106 TIME STAMP 5. 0xfff7a000 0x00000910
9510 11:08:16.637543 VBOOT WORK 6. 0xfff66000 0x00014000
9511 11:08:16.640362 RAMOOPS 7. 0xffe66000 0x00100000
9512 11:08:16.643676 COREBOOT 8. 0xffe64000 0x00002000
9513 11:08:16.643750 IMD small region:
9514 11:08:16.647272 IMD ROOT 0. 0xffffec00 0x00000400
9515 11:08:16.650220 VPD 1. 0xffffeb80 0x0000006c
9516 11:08:16.657029 MMC STATUS 2. 0xffffeb60 0x00000004
9517 11:08:16.660336 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9518 11:08:16.667102 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9519 11:08:16.707166 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9520 11:08:16.710677 Checking segment from ROM address 0x40100000
9521 11:08:16.717100 Checking segment from ROM address 0x4010001c
9522 11:08:16.720702 Loading segment from ROM address 0x40100000
9523 11:08:16.720778 code (compression=0)
9524 11:08:16.730576 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9525 11:08:16.736726 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9526 11:08:16.736820 it's not compressed!
9527 11:08:16.743632 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9528 11:08:16.749722 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9529 11:08:16.767373 Loading segment from ROM address 0x4010001c
9530 11:08:16.767501 Entry Point 0x80000000
9531 11:08:16.771027 Loaded segments
9532 11:08:16.774147 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9533 11:08:16.780551 Jumping to boot code at 0x80000000(0xffe64000)
9534 11:08:16.787599 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9535 11:08:16.793835 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9536 11:08:16.801658 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9537 11:08:16.805163 Checking segment from ROM address 0x40100000
9538 11:08:16.808547 Checking segment from ROM address 0x4010001c
9539 11:08:16.814982 Loading segment from ROM address 0x40100000
9540 11:08:16.815057 code (compression=1)
9541 11:08:16.821848 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9542 11:08:16.831615 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9543 11:08:16.831725 using LZMA
9544 11:08:16.840274 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9545 11:08:16.846688 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9546 11:08:16.850276 Loading segment from ROM address 0x4010001c
9547 11:08:16.853614 Entry Point 0x54601000
9548 11:08:16.853689 Loaded segments
9549 11:08:16.856895 NOTICE: MT8192 bl31_setup
9550 11:08:16.863866 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9551 11:08:16.867609 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9552 11:08:16.870659 WARNING: region 0:
9553 11:08:16.874179 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9554 11:08:16.874244 WARNING: region 1:
9555 11:08:16.880390 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9556 11:08:16.883544 WARNING: region 2:
9557 11:08:16.886950 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9558 11:08:16.890117 WARNING: region 3:
9559 11:08:16.896716 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9560 11:08:16.896786 WARNING: region 4:
9561 11:08:16.903487 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9562 11:08:16.903579 WARNING: region 5:
9563 11:08:16.906514 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 11:08:16.909940 WARNING: region 6:
9565 11:08:16.913462 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 11:08:16.916500 WARNING: region 7:
9567 11:08:16.919893 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9568 11:08:16.926694 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9569 11:08:16.929514 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9570 11:08:16.936028 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9571 11:08:16.939409 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9572 11:08:16.942841 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9573 11:08:16.949377 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9574 11:08:16.952728 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9575 11:08:16.956163 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9576 11:08:16.963286 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9577 11:08:16.966024 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9578 11:08:16.972767 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9579 11:08:16.975908 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9580 11:08:16.979315 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9581 11:08:16.986029 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9582 11:08:16.989597 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9583 11:08:16.995717 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9584 11:08:16.999109 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9585 11:08:17.002508 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9586 11:08:17.009405 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9587 11:08:17.012615 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9588 11:08:17.015721 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9589 11:08:17.022562 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9590 11:08:17.025564 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9591 11:08:17.033176 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9592 11:08:17.035585 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9593 11:08:17.039462 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9594 11:08:17.045333 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9595 11:08:17.048831 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9596 11:08:17.055468 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9597 11:08:17.058837 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9598 11:08:17.065942 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9599 11:08:17.069055 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9600 11:08:17.072026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9601 11:08:17.075293 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9602 11:08:17.081920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9603 11:08:17.085591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9604 11:08:17.088849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9605 11:08:17.091888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9606 11:08:17.098694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9607 11:08:17.101902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9608 11:08:17.105305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9609 11:08:17.108592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9610 11:08:17.115103 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9611 11:08:17.118101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9612 11:08:17.121444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9613 11:08:17.128321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9614 11:08:17.131350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9615 11:08:17.134738 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9616 11:08:17.141471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9617 11:08:17.145026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9618 11:08:17.147980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9619 11:08:17.154744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9620 11:08:17.158060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9621 11:08:17.164709 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9622 11:08:17.168168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9623 11:08:17.174231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9624 11:08:17.178514 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9625 11:08:17.184107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9626 11:08:17.187890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9627 11:08:17.191211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9628 11:08:17.197819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9629 11:08:17.201261 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9630 11:08:17.207665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9631 11:08:17.211129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9632 11:08:17.218074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9633 11:08:17.220927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9634 11:08:17.227589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9635 11:08:17.230969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9636 11:08:17.234080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9637 11:08:17.240723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9638 11:08:17.243872 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9639 11:08:17.250095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9640 11:08:17.253453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9641 11:08:17.259848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9642 11:08:17.263433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9643 11:08:17.266903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9644 11:08:17.273425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9645 11:08:17.276604 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9646 11:08:17.283388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9647 11:08:17.286722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9648 11:08:17.293237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9649 11:08:17.296708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9650 11:08:17.302862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9651 11:08:17.306137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9652 11:08:17.312880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9653 11:08:17.316232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9654 11:08:17.319272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9655 11:08:17.326099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9656 11:08:17.329328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9657 11:08:17.336161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9658 11:08:17.339361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9659 11:08:17.345784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9660 11:08:17.349194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9661 11:08:17.355535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9662 11:08:17.358908 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9663 11:08:17.365716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9664 11:08:17.368874 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9665 11:08:17.372272 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9666 11:08:17.375676 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9667 11:08:17.378925 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9668 11:08:17.385753 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9669 11:08:17.388788 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9670 11:08:17.395648 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9671 11:08:17.398876 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9672 11:08:17.402159 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9673 11:08:17.408983 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9674 11:08:17.412310 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9675 11:08:17.418858 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9676 11:08:17.421828 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9677 11:08:17.428753 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9678 11:08:17.431833 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9679 11:08:17.435124 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9680 11:08:17.441652 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9681 11:08:17.445312 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9682 11:08:17.451594 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9683 11:08:17.455132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9684 11:08:17.458025 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9685 11:08:17.461438 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9686 11:08:17.467954 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9687 11:08:17.471421 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9688 11:08:17.475029 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9689 11:08:17.481825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9690 11:08:17.484688 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9691 11:08:17.487928 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9692 11:08:17.494426 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9693 11:08:17.498038 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9694 11:08:17.501307 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9695 11:08:17.507586 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9696 11:08:17.511022 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9697 11:08:17.517797 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9698 11:08:17.521275 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9699 11:08:17.524265 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9700 11:08:17.531034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9701 11:08:17.534576 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9702 11:08:17.537827 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9703 11:08:17.544822 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9704 11:08:17.547803 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9705 11:08:17.554622 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9706 11:08:17.557413 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9707 11:08:17.560761 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9708 11:08:17.567310 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9709 11:08:17.571079 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9710 11:08:17.577085 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9711 11:08:17.581014 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9712 11:08:17.583997 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9713 11:08:17.590490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9714 11:08:17.593736 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9715 11:08:17.600441 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9716 11:08:17.603822 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9717 11:08:17.610403 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9718 11:08:17.613712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9719 11:08:17.616897 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9720 11:08:17.623683 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9721 11:08:17.626531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9722 11:08:17.633531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9723 11:08:17.636995 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9724 11:08:17.639841 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9725 11:08:17.646534 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9726 11:08:17.649822 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9727 11:08:17.653277 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9728 11:08:17.660411 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9729 11:08:17.663292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9730 11:08:17.670152 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9731 11:08:17.673104 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9732 11:08:17.676552 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9733 11:08:17.682787 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9734 11:08:17.686244 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9735 11:08:17.692900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9736 11:08:17.696215 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9737 11:08:17.699851 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9738 11:08:17.706226 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9739 11:08:17.709626 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9740 11:08:17.715952 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9741 11:08:17.719261 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9742 11:08:17.722597 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9743 11:08:17.729221 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9744 11:08:17.732829 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9745 11:08:17.739018 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9746 11:08:17.742376 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9747 11:08:17.745580 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9748 11:08:17.751966 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9749 11:08:17.755295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9750 11:08:17.761880 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9751 11:08:17.765260 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9752 11:08:17.771921 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9753 11:08:17.775391 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9754 11:08:17.778916 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9755 11:08:17.785035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9756 11:08:17.788399 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9757 11:08:17.795345 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9758 11:08:17.798381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9759 11:08:17.802246 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9760 11:08:17.808392 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9761 11:08:17.811729 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9762 11:08:17.818134 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9763 11:08:17.821511 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9764 11:08:17.828147 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9765 11:08:17.831550 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9766 11:08:17.834937 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9767 11:08:17.841457 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9768 11:08:17.844969 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9769 11:08:17.851080 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9770 11:08:17.854419 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9771 11:08:17.857663 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9772 11:08:17.864852 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9773 11:08:17.868418 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9774 11:08:17.874483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9775 11:08:17.877583 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9776 11:08:17.884204 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9777 11:08:17.887821 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9778 11:08:17.891086 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9779 11:08:17.897829 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9780 11:08:17.900686 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9781 11:08:17.907341 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9782 11:08:17.910590 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9783 11:08:17.917344 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9784 11:08:17.920660 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9785 11:08:17.923833 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9786 11:08:17.930277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9787 11:08:17.933863 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9788 11:08:17.940196 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9789 11:08:17.943399 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9790 11:08:17.949787 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9791 11:08:17.952977 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9792 11:08:17.956541 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9793 11:08:17.963270 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9794 11:08:17.966649 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9795 11:08:17.973227 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9796 11:08:17.976689 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9797 11:08:17.979909 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9798 11:08:17.983159 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9799 11:08:17.990053 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9800 11:08:17.992760 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9801 11:08:17.996201 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9802 11:08:18.002810 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9803 11:08:18.006146 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9804 11:08:18.009327 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9805 11:08:18.016190 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9806 11:08:18.019782 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9807 11:08:18.022961 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9808 11:08:18.029342 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9809 11:08:18.032805 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9810 11:08:18.039086 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9811 11:08:18.042485 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9812 11:08:18.045794 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9813 11:08:18.052112 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9814 11:08:18.055825 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9815 11:08:18.062690 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9816 11:08:18.065396 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9817 11:08:18.068703 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9818 11:08:18.075649 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9819 11:08:18.078546 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9820 11:08:18.082007 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9821 11:08:18.088924 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9822 11:08:18.091863 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9823 11:08:18.095387 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9824 11:08:18.101971 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9825 11:08:18.105636 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9826 11:08:18.112032 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9827 11:08:18.115080 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9828 11:08:18.118204 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9829 11:08:18.124710 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9830 11:08:18.128298 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9831 11:08:18.131402 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9832 11:08:18.138049 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9833 11:08:18.141635 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9834 11:08:18.147941 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9835 11:08:18.151395 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9836 11:08:18.154849 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9837 11:08:18.157722 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9838 11:08:18.164400 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9839 11:08:18.168084 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9840 11:08:18.171081 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9841 11:08:18.174506 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9842 11:08:18.181007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9843 11:08:18.184422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9844 11:08:18.187457 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9845 11:08:18.190730 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9846 11:08:18.197583 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9847 11:08:18.200858 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9848 11:08:18.204305 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9849 11:08:18.210433 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9850 11:08:18.213856 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9851 11:08:18.217295 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9852 11:08:18.224041 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9853 11:08:18.227259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9854 11:08:18.234196 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9855 11:08:18.237103 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9856 11:08:18.243618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9857 11:08:18.246682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9858 11:08:18.250058 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9859 11:08:18.256711 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9860 11:08:18.260107 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9861 11:08:18.266597 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9862 11:08:18.269891 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9863 11:08:18.276803 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9864 11:08:18.279932 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9865 11:08:18.283060 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9866 11:08:18.289731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9867 11:08:18.293185 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9868 11:08:18.299366 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9869 11:08:18.302880 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9870 11:08:18.306117 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9871 11:08:18.312693 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9872 11:08:18.315959 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9873 11:08:18.322137 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9874 11:08:18.325511 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9875 11:08:18.332265 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9876 11:08:18.335689 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9877 11:08:18.338958 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9878 11:08:18.345332 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9879 11:08:18.348744 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9880 11:08:18.355286 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9881 11:08:18.358837 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9882 11:08:18.361950 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9883 11:08:18.368833 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9884 11:08:18.371690 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9885 11:08:18.378340 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9886 11:08:18.381833 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9887 11:08:18.388288 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9888 11:08:18.391643 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9889 11:08:18.395090 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9890 11:08:18.401896 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9891 11:08:18.405211 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9892 11:08:18.411368 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9893 11:08:18.414677 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9894 11:08:18.421491 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9895 11:08:18.424659 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9896 11:08:18.428117 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9897 11:08:18.434427 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9898 11:08:18.437772 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9899 11:08:18.444601 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9900 11:08:18.448069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9901 11:08:18.451179 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9902 11:08:18.457965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9903 11:08:18.461838 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9904 11:08:18.467650 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9905 11:08:18.471145 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9906 11:08:18.474735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9907 11:08:18.480867 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9908 11:08:18.484038 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9909 11:08:18.490366 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9910 11:08:18.493832 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9911 11:08:18.500512 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9912 11:08:18.503874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9913 11:08:18.507245 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9914 11:08:18.513410 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9915 11:08:18.516720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9916 11:08:18.523501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9917 11:08:18.526918 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9918 11:08:18.533554 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9919 11:08:18.536936 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9920 11:08:18.540019 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9921 11:08:18.546769 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9922 11:08:18.549726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9923 11:08:18.556872 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9924 11:08:18.560016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9925 11:08:18.566448 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9926 11:08:18.569376 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9927 11:08:18.576131 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9928 11:08:18.579572 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9929 11:08:18.582991 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9930 11:08:18.589662 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9931 11:08:18.592525 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9932 11:08:18.599234 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9933 11:08:18.602608 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9934 11:08:18.609400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9935 11:08:18.612956 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9936 11:08:18.619107 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9937 11:08:18.622377 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9938 11:08:18.625710 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9939 11:08:18.632459 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9940 11:08:18.635749 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9941 11:08:18.642556 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9942 11:08:18.645473 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9943 11:08:18.652350 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9944 11:08:18.655646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9945 11:08:18.658513 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9946 11:08:18.665318 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9947 11:08:18.668317 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9948 11:08:18.674964 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9949 11:08:18.678540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9950 11:08:18.684798 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9951 11:08:18.688262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9952 11:08:18.695128 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9953 11:08:18.697996 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9954 11:08:18.701482 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9955 11:08:18.707877 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9956 11:08:18.711316 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9957 11:08:18.718232 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9958 11:08:18.721397 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9959 11:08:18.727554 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9960 11:08:18.731183 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9961 11:08:18.737666 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9962 11:08:18.741036 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9963 11:08:18.744358 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9964 11:08:18.750958 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9965 11:08:18.754362 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9966 11:08:18.760767 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9967 11:08:18.764337 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9968 11:08:18.770741 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9969 11:08:18.774128 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9970 11:08:18.777167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9971 11:08:18.783844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9972 11:08:18.787088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9973 11:08:18.793979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9974 11:08:18.796904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9975 11:08:18.803570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9976 11:08:18.807286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9977 11:08:18.813511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9978 11:08:18.816906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9979 11:08:18.823121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9980 11:08:18.826598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9981 11:08:18.833091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9982 11:08:18.836371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9983 11:08:18.842939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9984 11:08:18.846319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9985 11:08:18.853094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9986 11:08:18.856596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9987 11:08:18.862646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9988 11:08:18.866015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9989 11:08:18.872818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9990 11:08:18.876274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9991 11:08:18.882476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9992 11:08:18.885959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9993 11:08:18.892292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9994 11:08:18.895719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9995 11:08:18.902646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9996 11:08:18.905998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9997 11:08:18.912700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9998 11:08:18.915981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9999 11:08:18.922414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10000 11:08:18.925778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10001 11:08:18.932342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10002 11:08:18.935873 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10003 11:08:18.939130 INFO: [APUAPC] vio 0
10004 11:08:18.942123 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10005 11:08:18.948831 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10006 11:08:18.952221 INFO: [APUAPC] D0_APC_0: 0x400510
10007 11:08:18.955810 INFO: [APUAPC] D0_APC_1: 0x0
10008 11:08:18.956272 INFO: [APUAPC] D0_APC_2: 0x1540
10009 11:08:18.958836 INFO: [APUAPC] D0_APC_3: 0x0
10010 11:08:18.962382 INFO: [APUAPC] D1_APC_0: 0xffffffff
10011 11:08:18.966338 INFO: [APUAPC] D1_APC_1: 0xffffffff
10012 11:08:18.968912 INFO: [APUAPC] D1_APC_2: 0x3fffff
10013 11:08:18.972227 INFO: [APUAPC] D1_APC_3: 0x0
10014 11:08:18.975360 INFO: [APUAPC] D2_APC_0: 0xffffffff
10015 11:08:18.979232 INFO: [APUAPC] D2_APC_1: 0xffffffff
10016 11:08:18.982719 INFO: [APUAPC] D2_APC_2: 0x3fffff
10017 11:08:18.985460 INFO: [APUAPC] D2_APC_3: 0x0
10018 11:08:18.989025 INFO: [APUAPC] D3_APC_0: 0xffffffff
10019 11:08:18.992374 INFO: [APUAPC] D3_APC_1: 0xffffffff
10020 11:08:18.995473 INFO: [APUAPC] D3_APC_2: 0x3fffff
10021 11:08:18.998834 INFO: [APUAPC] D3_APC_3: 0x0
10022 11:08:19.002458 INFO: [APUAPC] D4_APC_0: 0xffffffff
10023 11:08:19.007280 INFO: [APUAPC] D4_APC_1: 0xffffffff
10024 11:08:19.008790 INFO: [APUAPC] D4_APC_2: 0x3fffff
10025 11:08:19.011735 INFO: [APUAPC] D4_APC_3: 0x0
10026 11:08:19.015072 INFO: [APUAPC] D5_APC_0: 0xffffffff
10027 11:08:19.018377 INFO: [APUAPC] D5_APC_1: 0xffffffff
10028 11:08:19.022095 INFO: [APUAPC] D5_APC_2: 0x3fffff
10029 11:08:19.025534 INFO: [APUAPC] D5_APC_3: 0x0
10030 11:08:19.028478 INFO: [APUAPC] D6_APC_0: 0xffffffff
10031 11:08:19.031880 INFO: [APUAPC] D6_APC_1: 0xffffffff
10032 11:08:19.035329 INFO: [APUAPC] D6_APC_2: 0x3fffff
10033 11:08:19.038279 INFO: [APUAPC] D6_APC_3: 0x0
10034 11:08:19.041910 INFO: [APUAPC] D7_APC_0: 0xffffffff
10035 11:08:19.044905 INFO: [APUAPC] D7_APC_1: 0xffffffff
10036 11:08:19.048590 INFO: [APUAPC] D7_APC_2: 0x3fffff
10037 11:08:19.051938 INFO: [APUAPC] D7_APC_3: 0x0
10038 11:08:19.055271 INFO: [APUAPC] D8_APC_0: 0xffffffff
10039 11:08:19.058228 INFO: [APUAPC] D8_APC_1: 0xffffffff
10040 11:08:19.061529 INFO: [APUAPC] D8_APC_2: 0x3fffff
10041 11:08:19.065022 INFO: [APUAPC] D8_APC_3: 0x0
10042 11:08:19.068326 INFO: [APUAPC] D9_APC_0: 0xffffffff
10043 11:08:19.071371 INFO: [APUAPC] D9_APC_1: 0xffffffff
10044 11:08:19.075033 INFO: [APUAPC] D9_APC_2: 0x3fffff
10045 11:08:19.078415 INFO: [APUAPC] D9_APC_3: 0x0
10046 11:08:19.081311 INFO: [APUAPC] D10_APC_0: 0xffffffff
10047 11:08:19.084849 INFO: [APUAPC] D10_APC_1: 0xffffffff
10048 11:08:19.088246 INFO: [APUAPC] D10_APC_2: 0x3fffff
10049 11:08:19.091481 INFO: [APUAPC] D10_APC_3: 0x0
10050 11:08:19.094490 INFO: [APUAPC] D11_APC_0: 0xffffffff
10051 11:08:19.098121 INFO: [APUAPC] D11_APC_1: 0xffffffff
10052 11:08:19.101418 INFO: [APUAPC] D11_APC_2: 0x3fffff
10053 11:08:19.105289 INFO: [APUAPC] D11_APC_3: 0x0
10054 11:08:19.108114 INFO: [APUAPC] D12_APC_0: 0xffffffff
10055 11:08:19.110946 INFO: [APUAPC] D12_APC_1: 0xffffffff
10056 11:08:19.114415 INFO: [APUAPC] D12_APC_2: 0x3fffff
10057 11:08:19.117954 INFO: [APUAPC] D12_APC_3: 0x0
10058 11:08:19.121316 INFO: [APUAPC] D13_APC_0: 0xffffffff
10059 11:08:19.124617 INFO: [APUAPC] D13_APC_1: 0xffffffff
10060 11:08:19.127525 INFO: [APUAPC] D13_APC_2: 0x3fffff
10061 11:08:19.131168 INFO: [APUAPC] D13_APC_3: 0x0
10062 11:08:19.134684 INFO: [APUAPC] D14_APC_0: 0xffffffff
10063 11:08:19.137676 INFO: [APUAPC] D14_APC_1: 0xffffffff
10064 11:08:19.140897 INFO: [APUAPC] D14_APC_2: 0x3fffff
10065 11:08:19.144594 INFO: [APUAPC] D14_APC_3: 0x0
10066 11:08:19.147944 INFO: [APUAPC] D15_APC_0: 0xffffffff
10067 11:08:19.151094 INFO: [APUAPC] D15_APC_1: 0xffffffff
10068 11:08:19.154175 INFO: [APUAPC] D15_APC_2: 0x3fffff
10069 11:08:19.157673 INFO: [APUAPC] D15_APC_3: 0x0
10070 11:08:19.160581 INFO: [APUAPC] APC_CON: 0x4
10071 11:08:19.163910 INFO: [NOCDAPC] D0_APC_0: 0x0
10072 11:08:19.167722 INFO: [NOCDAPC] D0_APC_1: 0x0
10073 11:08:19.168230 INFO: [NOCDAPC] D1_APC_0: 0x0
10074 11:08:19.170575 INFO: [NOCDAPC] D1_APC_1: 0xfff
10075 11:08:19.173815 INFO: [NOCDAPC] D2_APC_0: 0x0
10076 11:08:19.177482 INFO: [NOCDAPC] D2_APC_1: 0xfff
10077 11:08:19.180583 INFO: [NOCDAPC] D3_APC_0: 0x0
10078 11:08:19.183925 INFO: [NOCDAPC] D3_APC_1: 0xfff
10079 11:08:19.187307 INFO: [NOCDAPC] D4_APC_0: 0x0
10080 11:08:19.190208 INFO: [NOCDAPC] D4_APC_1: 0xfff
10081 11:08:19.194227 INFO: [NOCDAPC] D5_APC_0: 0x0
10082 11:08:19.196820 INFO: [NOCDAPC] D5_APC_1: 0xfff
10083 11:08:19.200251 INFO: [NOCDAPC] D6_APC_0: 0x0
10084 11:08:19.203457 INFO: [NOCDAPC] D6_APC_1: 0xfff
10085 11:08:19.203851 INFO: [NOCDAPC] D7_APC_0: 0x0
10086 11:08:19.206841 INFO: [NOCDAPC] D7_APC_1: 0xfff
10087 11:08:19.210373 INFO: [NOCDAPC] D8_APC_0: 0x0
10088 11:08:19.213217 INFO: [NOCDAPC] D8_APC_1: 0xfff
10089 11:08:19.216827 INFO: [NOCDAPC] D9_APC_0: 0x0
10090 11:08:19.220384 INFO: [NOCDAPC] D9_APC_1: 0xfff
10091 11:08:19.223235 INFO: [NOCDAPC] D10_APC_0: 0x0
10092 11:08:19.226683 INFO: [NOCDAPC] D10_APC_1: 0xfff
10093 11:08:19.230016 INFO: [NOCDAPC] D11_APC_0: 0x0
10094 11:08:19.233282 INFO: [NOCDAPC] D11_APC_1: 0xfff
10095 11:08:19.236655 INFO: [NOCDAPC] D12_APC_0: 0x0
10096 11:08:19.239748 INFO: [NOCDAPC] D12_APC_1: 0xfff
10097 11:08:19.242764 INFO: [NOCDAPC] D13_APC_0: 0x0
10098 11:08:19.246391 INFO: [NOCDAPC] D13_APC_1: 0xfff
10099 11:08:19.249526 INFO: [NOCDAPC] D14_APC_0: 0x0
10100 11:08:19.250074 INFO: [NOCDAPC] D14_APC_1: 0xfff
10101 11:08:19.252832 INFO: [NOCDAPC] D15_APC_0: 0x0
10102 11:08:19.256032 INFO: [NOCDAPC] D15_APC_1: 0xfff
10103 11:08:19.259390 INFO: [NOCDAPC] APC_CON: 0x4
10104 11:08:19.262646 INFO: [APUAPC] set_apusys_apc done
10105 11:08:19.266453 INFO: [DEVAPC] devapc_init done
10106 11:08:19.269247 INFO: GICv3 without legacy support detected.
10107 11:08:19.276442 INFO: ARM GICv3 driver initialized in EL3
10108 11:08:19.279801 INFO: Maximum SPI INTID supported: 639
10109 11:08:19.282715 INFO: BL31: Initializing runtime services
10110 11:08:19.289266 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10111 11:08:19.292709 INFO: SPM: enable CPC mode
10112 11:08:19.295967 INFO: mcdi ready for mcusys-off-idle and system suspend
10113 11:08:19.302248 INFO: BL31: Preparing for EL3 exit to normal world
10114 11:08:19.305677 INFO: Entry point address = 0x80000000
10115 11:08:19.306219 INFO: SPSR = 0x8
10116 11:08:19.312460
10117 11:08:19.312846
10118 11:08:19.313139
10119 11:08:19.315831 Starting depthcharge on Spherion...
10120 11:08:19.316208
10121 11:08:19.316501 Wipe memory regions:
10122 11:08:19.316770
10123 11:08:19.319065 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10124 11:08:19.319543 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10125 11:08:19.319911 Setting prompt string to ['asurada:']
10126 11:08:19.320226 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10127 11:08:19.320795 [0x00000040000000, 0x00000054600000)
10128 11:08:19.441245
10129 11:08:19.441648 [0x00000054660000, 0x00000080000000)
10130 11:08:19.701771
10131 11:08:19.702198 [0x000000821a7280, 0x000000ffe64000)
10132 11:08:20.446936
10133 11:08:20.447481 [0x00000100000000, 0x00000240000000)
10134 11:08:22.336316
10135 11:08:22.339522 Initializing XHCI USB controller at 0x11200000.
10136 11:08:23.377660
10137 11:08:23.380828 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10138 11:08:23.380914
10139 11:08:23.380975
10140 11:08:23.381236 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10141 11:08:23.381313 Sending line: 'tftpboot 192.168.201.1 14786847/tftp-deploy-d2dascnn/kernel/image.itb 14786847/tftp-deploy-d2dascnn/kernel/cmdline '
10143 11:08:23.481774 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10144 11:08:23.481862 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10145 11:08:23.486389 asurada: tftpboot 192.168.201.1 14786847/tftp-deploy-d2dascnn/kernel/image.itp-deploy-d2dascnn/kernel/cmdline
10146 11:08:23.486470
10147 11:08:23.486529 Waiting for link
10148 11:08:23.644615
10149 11:08:23.644748 R8152: Initializing
10150 11:08:23.644809
10151 11:08:23.647858 Version 6 (ocp_data = 5c30)
10152 11:08:23.647937
10153 11:08:23.650945 R8152: Done initializing
10154 11:08:23.651019
10155 11:08:23.651076 Adding net device
10156 11:08:25.510197
10157 11:08:25.510705 done.
10158 11:08:25.511115
10159 11:08:25.511489 MAC: 00:e0:4c:68:02:81
10160 11:08:25.511781
10161 11:08:25.513246 Sending DHCP discover... done.
10162 11:08:25.513633
10163 11:08:25.516966 Waiting for reply... done.
10164 11:08:25.517404
10165 11:08:25.520257 Sending DHCP request... done.
10166 11:08:25.520758
10167 11:08:25.525710 Waiting for reply... done.
10168 11:08:25.526104
10169 11:08:25.526408 My ip is 192.168.201.14
10170 11:08:25.526844
10171 11:08:25.528849 The DHCP server ip is 192.168.201.1
10172 11:08:25.529203
10173 11:08:25.535602 TFTP server IP predefined by user: 192.168.201.1
10174 11:08:25.535991
10175 11:08:25.542094 Bootfile predefined by user: 14786847/tftp-deploy-d2dascnn/kernel/image.itb
10176 11:08:25.542600
10177 11:08:25.545052 Sending tftp read request... done.
10178 11:08:25.545472
10179 11:08:25.552168 Waiting for the transfer...
10180 11:08:25.552551
10181 11:08:26.146413 00000000 ################################################################
10182 11:08:26.146565
10183 11:08:26.728566 00080000 ################################################################
10184 11:08:26.728715
10185 11:08:27.301898 00100000 ################################################################
10186 11:08:27.302048
10187 11:08:27.865549 00180000 ################################################################
10188 11:08:27.865707
10189 11:08:28.420366 00200000 ################################################################
10190 11:08:28.420540
10191 11:08:28.964978 00280000 ################################################################
10192 11:08:28.965093
10193 11:08:29.529540 00300000 ################################################################
10194 11:08:29.529667
10195 11:08:30.092808 00380000 ################################################################
10196 11:08:30.092939
10197 11:08:30.671356 00400000 ################################################################
10198 11:08:30.671528
10199 11:08:31.235146 00480000 ################################################################
10200 11:08:31.235263
10201 11:08:31.874258 00500000 ################################################################
10202 11:08:31.874704
10203 11:08:32.547258 00580000 ################################################################
10204 11:08:32.547850
10205 11:08:33.161588 00600000 ################################################################
10206 11:08:33.161705
10207 11:08:33.723512 00680000 ################################################################
10208 11:08:33.723635
10209 11:08:34.316219 00700000 ################################################################
10210 11:08:34.316366
10211 11:08:34.877031 00780000 ################################################################
10212 11:08:34.877155
10213 11:08:35.424502 00800000 ################################################################
10214 11:08:35.424620
10215 11:08:35.997228 00880000 ################################################################
10216 11:08:35.997353
10217 11:08:36.573640 00900000 ################################################################
10218 11:08:36.573762
10219 11:08:37.149556 00980000 ################################################################
10220 11:08:37.149676
10221 11:08:37.703555 00a00000 ################################################################
10222 11:08:37.703677
10223 11:08:38.282539 00a80000 ################################################################
10224 11:08:38.282667
10225 11:08:38.867677 00b00000 ################################################################
10226 11:08:38.867802
10227 11:08:39.433423 00b80000 ################################################################
10228 11:08:39.433582
10229 11:08:40.009630 00c00000 ################################################################
10230 11:08:40.009789
10231 11:08:40.568632 00c80000 ################################################################
10232 11:08:40.568761
10233 11:08:41.121463 00d00000 ################################################################
10234 11:08:41.121590
10235 11:08:41.707541 00d80000 ################################################################
10236 11:08:41.707668
10237 11:08:42.278693 00e00000 ################################################################
10238 11:08:42.278817
10239 11:08:42.849487 00e80000 ################################################################
10240 11:08:42.849613
10241 11:08:43.433041 00f00000 ################################################################
10242 11:08:43.433165
10243 11:08:44.115593 00f80000 ################################################################
10244 11:08:44.116052
10245 11:08:44.813384 01000000 ################################################################
10246 11:08:44.813840
10247 11:08:45.514503 01080000 ################################################################
10248 11:08:45.514971
10249 11:08:46.207940 01100000 ################################################################
10250 11:08:46.208407
10251 11:08:46.853803 01180000 ################################################################
10252 11:08:46.854325
10253 11:08:47.525696 01200000 ################################################################
10254 11:08:47.525819
10255 11:08:48.151286 01280000 ################################################################
10256 11:08:48.151814
10257 11:08:48.830834 01300000 ################################################################
10258 11:08:48.831479
10259 11:08:49.480058 01380000 ################################################################
10260 11:08:49.480514
10261 11:08:50.116827 01400000 ################################################################
10262 11:08:50.116955
10263 11:08:50.704587 01480000 ################################################################
10264 11:08:50.704728
10265 11:08:51.300454 01500000 ################################################################
10266 11:08:51.300582
10267 11:08:51.903699 01580000 ################################################################
10268 11:08:51.903848
10269 11:08:52.495802 01600000 ################################################################
10270 11:08:52.495931
10271 11:08:53.059610 01680000 ################################################################
10272 11:08:53.059735
10273 11:08:53.677968 01700000 ################################################################
10274 11:08:53.678431
10275 11:08:54.338477 01780000 ################################################################
10276 11:08:54.338931
10277 11:08:55.022573 01800000 ################################################################
10278 11:08:55.023032
10279 11:08:55.714907 01880000 ################################################################
10280 11:08:55.715371
10281 11:08:56.394138 01900000 ################################################################
10282 11:08:56.394599
10283 11:08:57.004246 01980000 ################################################################
10284 11:08:57.004371
10285 11:08:57.638987 01a00000 ################################################################
10286 11:08:57.639530
10287 11:08:58.320726 01a80000 ################################################################
10288 11:08:58.321256
10289 11:08:58.991389 01b00000 ################################################################
10290 11:08:58.991887
10291 11:08:59.665369 01b80000 ################################################################
10292 11:08:59.665831
10293 11:09:00.347027 01c00000 ################################################################
10294 11:09:00.347526
10295 11:09:01.024350 01c80000 ################################################################
10296 11:09:01.024810
10297 11:09:01.683410 01d00000 ################################################################
10298 11:09:01.683930
10299 11:09:02.359115 01d80000 ################################################################
10300 11:09:02.359758
10301 11:09:02.904068 01e00000 ################################################### done.
10302 11:09:02.904581
10303 11:09:02.907004 The bootfile was 31873970 bytes long.
10304 11:09:02.907391
10305 11:09:02.910431 Sending tftp read request... done.
10306 11:09:02.910825
10307 11:09:02.914898 Waiting for the transfer...
10308 11:09:02.915285
10309 11:09:02.915636 00000000 # done.
10310 11:09:02.915930
10311 11:09:02.921826 Command line loaded dynamically from TFTP file: 14786847/tftp-deploy-d2dascnn/kernel/cmdline
10312 11:09:02.922358
10313 11:09:02.944521 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786847/extract-nfsrootfs-fdzh_dox,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10314 11:09:02.944943
10315 11:09:02.947867 Loading FIT.
10316 11:09:02.948288
10317 11:09:02.951032 Image ramdisk-1 has 18708428 bytes.
10318 11:09:02.951415
10319 11:09:02.951875 Image fdt-1 has 47258 bytes.
10320 11:09:02.952177
10321 11:09:02.954699 Image kernel-1 has 13116259 bytes.
10322 11:09:02.955080
10323 11:09:02.964588 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10324 11:09:02.964979
10325 11:09:02.980576 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10326 11:09:02.981075
10327 11:09:02.987707 Choosing best match conf-1 for compat google,spherion-rev2.
10328 11:09:02.990965
10329 11:09:02.995393 Connected to device vid:did:rid of 1ae0:0028:00
10330 11:09:03.002361
10331 11:09:03.005432 tpm_get_response: command 0x17b, return code 0x0
10332 11:09:03.005822
10333 11:09:03.008908 ec_init: CrosEC protocol v3 supported (256, 248)
10334 11:09:03.013340
10335 11:09:03.016595 tpm_cleanup: add release locality here.
10336 11:09:03.016980
10337 11:09:03.017283 Shutting down all USB controllers.
10338 11:09:03.019975
10339 11:09:03.020389 Removing current net device
10340 11:09:03.020808
10341 11:09:03.026860 Exiting depthcharge with code 4 at timestamp: 73175129
10342 11:09:03.027323
10343 11:09:03.029709 LZMA decompressing kernel-1 to 0x821a6718
10344 11:09:03.030091
10345 11:09:03.033283 LZMA decompressing kernel-1 to 0x40000000
10346 11:09:04.648956
10347 11:09:04.649453 jumping to kernel
10348 11:09:04.651205 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10349 11:09:04.651967 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10350 11:09:04.652462 Setting prompt string to ['Linux version [0-9]']
10351 11:09:04.652813 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10352 11:09:04.653184 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10353 11:09:04.730644
10354 11:09:04.733695 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10355 11:09:04.737350 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10356 11:09:04.737836 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10357 11:09:04.738207 Setting prompt string to []
10358 11:09:04.738642 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10359 11:09:04.739000 Using line separator: #'\n'#
10360 11:09:04.739294 No login prompt set.
10361 11:09:04.739634 Parsing kernel messages
10362 11:09:04.739914 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10363 11:09:04.740555 [login-action] Waiting for messages, (timeout 00:03:34)
10364 11:09:04.740882 Waiting using forced prompt support (timeout 00:01:47)
10365 11:09:04.757257 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10366 11:09:04.760383 [ 0.000000] random: crng init done
10367 11:09:04.763538 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10368 11:09:04.766914 [ 0.000000] efi: UEFI not found.
10369 11:09:04.776918 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10370 11:09:04.783036 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10371 11:09:04.793490 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10372 11:09:04.802831 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10373 11:09:04.810228 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10374 11:09:04.812867 [ 0.000000] printk: bootconsole [mtk8250] enabled
10375 11:09:04.821732 [ 0.000000] NUMA: No NUMA configuration found
10376 11:09:04.827942 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10377 11:09:04.834903 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10378 11:09:04.835462 [ 0.000000] Zone ranges:
10379 11:09:04.841513 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10380 11:09:04.844705 [ 0.000000] DMA32 empty
10381 11:09:04.851571 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10382 11:09:04.854481 [ 0.000000] Movable zone start for each node
10383 11:09:04.858063 [ 0.000000] Early memory node ranges
10384 11:09:04.864832 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10385 11:09:04.870898 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10386 11:09:04.877539 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10387 11:09:04.884332 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10388 11:09:04.890651 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10389 11:09:04.897548 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10390 11:09:04.955052 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10391 11:09:04.961389 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10392 11:09:04.968217 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10393 11:09:04.971961 [ 0.000000] psci: probing for conduit method from DT.
10394 11:09:04.977855 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10395 11:09:04.981645 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10396 11:09:04.987717 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10397 11:09:04.990945 [ 0.000000] psci: SMC Calling Convention v1.2
10398 11:09:04.997630 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10399 11:09:05.000858 [ 0.000000] Detected VIPT I-cache on CPU0
10400 11:09:05.007404 [ 0.000000] CPU features: detected: GIC system register CPU interface
10401 11:09:05.014687 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10402 11:09:05.020805 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10403 11:09:05.027645 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10404 11:09:05.037497 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10405 11:09:05.044624 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10406 11:09:05.047798 [ 0.000000] alternatives: applying boot alternatives
10407 11:09:05.054076 [ 0.000000] Fallback order for Node 0: 0
10408 11:09:05.060313 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10409 11:09:05.063658 [ 0.000000] Policy zone: Normal
10410 11:09:05.086872 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786847/extract-nfsrootfs-fdzh_dox,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10411 11:09:05.096424 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10412 11:09:05.108276 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10413 11:09:05.118103 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10414 11:09:05.124880 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10415 11:09:05.127627 <6>[ 0.000000] software IO TLB: area num 8.
10416 11:09:05.185971 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10417 11:09:05.334808 <6>[ 0.000000] Memory: 7945788K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406980K reserved, 32768K cma-reserved)
10418 11:09:05.340888 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10419 11:09:05.347364 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10420 11:09:05.350538 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10421 11:09:05.357366 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10422 11:09:05.364170 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10423 11:09:05.367392 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10424 11:09:05.377244 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10425 11:09:05.383643 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10426 11:09:05.390265 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10427 11:09:05.396976 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10428 11:09:05.400689 <6>[ 0.000000] GICv3: 608 SPIs implemented
10429 11:09:05.403341 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10430 11:09:05.410246 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10431 11:09:05.413894 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10432 11:09:05.420400 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10433 11:09:05.433265 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10434 11:09:05.446150 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10435 11:09:05.453174 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10436 11:09:05.460941 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10437 11:09:05.474253 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10438 11:09:05.480804 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10439 11:09:05.487227 <6>[ 0.009226] Console: colour dummy device 80x25
10440 11:09:05.497444 <6>[ 0.013976] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10441 11:09:05.504101 <6>[ 0.024483] pid_max: default: 32768 minimum: 301
10442 11:09:05.507280 <6>[ 0.029356] LSM: Security Framework initializing
10443 11:09:05.513902 <6>[ 0.034294] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 11:09:05.523805 <6>[ 0.042106] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10445 11:09:05.534301 <6>[ 0.051525] cblist_init_generic: Setting adjustable number of callback queues.
10446 11:09:05.537316 <6>[ 0.059012] cblist_init_generic: Setting shift to 3 and lim to 1.
10447 11:09:05.547001 <6>[ 0.065392] cblist_init_generic: Setting adjustable number of callback queues.
10448 11:09:05.553811 <6>[ 0.072818] cblist_init_generic: Setting shift to 3 and lim to 1.
10449 11:09:05.557397 <6>[ 0.079262] rcu: Hierarchical SRCU implementation.
10450 11:09:05.563635 <6>[ 0.084277] rcu: Max phase no-delay instances is 1000.
10451 11:09:05.570540 <6>[ 0.091311] EFI services will not be available.
10452 11:09:05.573859 <6>[ 0.096268] smp: Bringing up secondary CPUs ...
10453 11:09:05.582410 <6>[ 0.101319] Detected VIPT I-cache on CPU1
10454 11:09:05.589043 <6>[ 0.101391] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10455 11:09:05.595884 <6>[ 0.101421] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10456 11:09:05.598785 <6>[ 0.101771] Detected VIPT I-cache on CPU2
10457 11:09:05.606162 <6>[ 0.101826] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10458 11:09:05.615603 <6>[ 0.101842] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10459 11:09:05.618897 <6>[ 0.102111] Detected VIPT I-cache on CPU3
10460 11:09:05.625632 <6>[ 0.102161] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10461 11:09:05.631903 <6>[ 0.102176] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10462 11:09:05.635326 <6>[ 0.102482] CPU features: detected: Spectre-v4
10463 11:09:05.641715 <6>[ 0.102488] CPU features: detected: Spectre-BHB
10464 11:09:05.644939 <6>[ 0.102493] Detected PIPT I-cache on CPU4
10465 11:09:05.651603 <6>[ 0.102553] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10466 11:09:05.658612 <6>[ 0.102569] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10467 11:09:05.664862 <6>[ 0.102867] Detected PIPT I-cache on CPU5
10468 11:09:05.671271 <6>[ 0.102929] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10469 11:09:05.677936 <6>[ 0.102945] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10470 11:09:05.681803 <6>[ 0.103227] Detected PIPT I-cache on CPU6
10471 11:09:05.688385 <6>[ 0.103292] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10472 11:09:05.697726 <6>[ 0.103308] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10473 11:09:05.701040 <6>[ 0.103607] Detected PIPT I-cache on CPU7
10474 11:09:05.708194 <6>[ 0.103672] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10475 11:09:05.714278 <6>[ 0.103688] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10476 11:09:05.717925 <6>[ 0.103735] smp: Brought up 1 node, 8 CPUs
10477 11:09:05.724556 <6>[ 0.245067] SMP: Total of 8 processors activated.
10478 11:09:05.727717 <6>[ 0.249988] CPU features: detected: 32-bit EL0 Support
10479 11:09:05.737339 <6>[ 0.255384] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10480 11:09:05.744321 <6>[ 0.264239] CPU features: detected: Common not Private translations
10481 11:09:05.750851 <6>[ 0.270715] CPU features: detected: CRC32 instructions
10482 11:09:05.753940 <6>[ 0.276067] CPU features: detected: RCpc load-acquire (LDAPR)
10483 11:09:05.760954 <6>[ 0.282027] CPU features: detected: LSE atomic instructions
10484 11:09:05.767241 <6>[ 0.287844] CPU features: detected: Privileged Access Never
10485 11:09:05.773755 <6>[ 0.293660] CPU features: detected: RAS Extension Support
10486 11:09:05.780455 <6>[ 0.299303] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10487 11:09:05.783875 <6>[ 0.306525] CPU: All CPU(s) started at EL2
10488 11:09:05.790181 <6>[ 0.310868] alternatives: applying system-wide alternatives
10489 11:09:05.800112 <6>[ 0.321753] devtmpfs: initialized
10490 11:09:05.815883 <6>[ 0.330649] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10491 11:09:05.822659 <6>[ 0.340609] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10492 11:09:05.829117 <6>[ 0.348840] pinctrl core: initialized pinctrl subsystem
10493 11:09:05.832344 <6>[ 0.355526] DMI not present or invalid.
10494 11:09:05.839128 <6>[ 0.359947] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10495 11:09:05.850062 <6>[ 0.366848] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10496 11:09:05.855525 <6>[ 0.374432] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10497 11:09:05.865533 <6>[ 0.382644] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10498 11:09:05.868907 <6>[ 0.390892] audit: initializing netlink subsys (disabled)
10499 11:09:05.878651 <5>[ 0.396592] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10500 11:09:05.885692 <6>[ 0.397328] thermal_sys: Registered thermal governor 'step_wise'
10501 11:09:05.891973 <6>[ 0.404560] thermal_sys: Registered thermal governor 'power_allocator'
10502 11:09:05.894875 <6>[ 0.410817] cpuidle: using governor menu
10503 11:09:05.902061 <6>[ 0.421780] NET: Registered PF_QIPCRTR protocol family
10504 11:09:05.908953 <6>[ 0.427319] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10505 11:09:05.914908 <6>[ 0.434418] ASID allocator initialised with 32768 entries
10506 11:09:05.918178 <6>[ 0.441014] Serial: AMBA PL011 UART driver
10507 11:09:05.929071 <4>[ 0.450461] Trying to register duplicate clock ID: 134
10508 11:09:05.989068 <6>[ 0.513515] KASLR enabled
10509 11:09:06.002997 <6>[ 0.521153] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10510 11:09:06.009746 <6>[ 0.528165] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10511 11:09:06.015962 <6>[ 0.534654] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10512 11:09:06.022802 <6>[ 0.541656] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10513 11:09:06.029258 <6>[ 0.548142] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10514 11:09:06.035969 <6>[ 0.555146] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10515 11:09:06.042943 <6>[ 0.561633] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10516 11:09:06.049320 <6>[ 0.568638] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10517 11:09:06.052231 <6>[ 0.576120] ACPI: Interpreter disabled.
10518 11:09:06.061534 <6>[ 0.582570] iommu: Default domain type: Translated
10519 11:09:06.067954 <6>[ 0.587719] iommu: DMA domain TLB invalidation policy: strict mode
10520 11:09:06.071119 <5>[ 0.594371] SCSI subsystem initialized
10521 11:09:06.077553 <6>[ 0.598619] usbcore: registered new interface driver usbfs
10522 11:09:06.084358 <6>[ 0.604348] usbcore: registered new interface driver hub
10523 11:09:06.087910 <6>[ 0.609900] usbcore: registered new device driver usb
10524 11:09:06.094430 <6>[ 0.616031] pps_core: LinuxPPS API ver. 1 registered
10525 11:09:06.104727 <6>[ 0.621225] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10526 11:09:06.107912 <6>[ 0.630568] PTP clock support registered
10527 11:09:06.111124 <6>[ 0.634810] EDAC MC: Ver: 3.0.0
10528 11:09:06.118482 <6>[ 0.640012] FPGA manager framework
10529 11:09:06.125003 <6>[ 0.643693] Advanced Linux Sound Architecture Driver Initialized.
10530 11:09:06.128781 <6>[ 0.650485] vgaarb: loaded
10531 11:09:06.135204 <6>[ 0.653661] clocksource: Switched to clocksource arch_sys_counter
10532 11:09:06.138561 <5>[ 0.660115] VFS: Disk quotas dquot_6.6.0
10533 11:09:06.144774 <6>[ 0.664304] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10534 11:09:06.148214 <6>[ 0.671492] pnp: PnP ACPI: disabled
10535 11:09:06.156841 <6>[ 0.678203] NET: Registered PF_INET protocol family
10536 11:09:06.166786 <6>[ 0.683790] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10537 11:09:06.177737 <6>[ 0.696117] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10538 11:09:06.187892 <6>[ 0.704934] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10539 11:09:06.194466 <6>[ 0.712904] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10540 11:09:06.204406 <6>[ 0.721605] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10541 11:09:06.211089 <6>[ 0.731364] TCP: Hash tables configured (established 65536 bind 65536)
10542 11:09:06.217834 <6>[ 0.738235] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10543 11:09:06.227109 <6>[ 0.745431] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10544 11:09:06.234203 <6>[ 0.753135] NET: Registered PF_UNIX/PF_LOCAL protocol family
10545 11:09:06.240323 <6>[ 0.759284] RPC: Registered named UNIX socket transport module.
10546 11:09:06.243833 <6>[ 0.765439] RPC: Registered udp transport module.
10547 11:09:06.250189 <6>[ 0.770373] RPC: Registered tcp transport module.
10548 11:09:06.256789 <6>[ 0.775305] RPC: Registered tcp NFSv4.1 backchannel transport module.
10549 11:09:06.260175 <6>[ 0.781969] PCI: CLS 0 bytes, default 64
10550 11:09:06.263599 <6>[ 0.786274] Unpacking initramfs...
10551 11:09:06.279855 <6>[ 0.798238] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10552 11:09:06.289659 <6>[ 0.806880] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10553 11:09:06.293446 <6>[ 0.815718] kvm [1]: IPA Size Limit: 40 bits
10554 11:09:06.299661 <6>[ 0.820246] kvm [1]: GICv3: no GICV resource entry
10555 11:09:06.302949 <6>[ 0.825264] kvm [1]: disabling GICv2 emulation
10556 11:09:06.309213 <6>[ 0.829948] kvm [1]: GIC system register CPU interface enabled
10557 11:09:06.316140 <6>[ 0.837717] kvm [1]: vgic interrupt IRQ18
10558 11:09:06.319622 <6>[ 0.842092] kvm [1]: VHE mode initialized successfully
10559 11:09:06.327488 <5>[ 0.848519] Initialise system trusted keyrings
10560 11:09:06.333492 <6>[ 0.853294] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10561 11:09:06.342146 <6>[ 0.863339] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10562 11:09:06.348353 <5>[ 0.869757] NFS: Registering the id_resolver key type
10563 11:09:06.352119 <5>[ 0.875059] Key type id_resolver registered
10564 11:09:06.358572 <5>[ 0.879473] Key type id_legacy registered
10565 11:09:06.365434 <6>[ 0.883754] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10566 11:09:06.371837 <6>[ 0.890677] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10567 11:09:06.378039 <6>[ 0.898410] 9p: Installing v9fs 9p2000 file system support
10568 11:09:06.415309 <5>[ 0.936462] Key type asymmetric registered
10569 11:09:06.418714 <5>[ 0.940794] Asymmetric key parser 'x509' registered
10570 11:09:06.428483 <6>[ 0.946031] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10571 11:09:06.431344 <6>[ 0.953656] io scheduler mq-deadline registered
10572 11:09:06.434961 <6>[ 0.958421] io scheduler kyber registered
10573 11:09:06.454053 <6>[ 0.975666] EINJ: ACPI disabled.
10574 11:09:06.488421 <4>[ 1.002328] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10575 11:09:06.497085 <4>[ 1.012959] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10576 11:09:06.512460 <6>[ 1.034169] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10577 11:09:06.521225 <6>[ 1.042272] printk: console [ttyS0] disabled
10578 11:09:06.548899 <6>[ 1.066905] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10579 11:09:06.555272 <6>[ 1.076397] printk: console [ttyS0] enabled
10580 11:09:06.558986 <6>[ 1.076397] printk: console [ttyS0] enabled
10581 11:09:06.565526 <6>[ 1.085293] printk: bootconsole [mtk8250] disabled
10582 11:09:06.568610 <6>[ 1.085293] printk: bootconsole [mtk8250] disabled
10583 11:09:06.575195 <6>[ 1.096602] SuperH (H)SCI(F) driver initialized
10584 11:09:06.578326 <6>[ 1.101921] msm_serial: driver initialized
10585 11:09:06.593123 <6>[ 1.110968] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10586 11:09:06.602745 <6>[ 1.119519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10587 11:09:06.609542 <6>[ 1.128061] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10588 11:09:06.619554 <6>[ 1.136688] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10589 11:09:06.629202 <6>[ 1.145394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10590 11:09:06.635533 <6>[ 1.154108] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10591 11:09:06.645498 <6>[ 1.162649] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10592 11:09:06.651989 <6>[ 1.171458] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10593 11:09:06.661683 <6>[ 1.180001] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10594 11:09:06.674450 <6>[ 1.195790] loop: module loaded
10595 11:09:06.680720 <6>[ 1.201766] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10596 11:09:06.703643 <4>[ 1.225324] mtk-pmic-keys: Failed to locate of_node [id: -1]
10597 11:09:06.710473 <6>[ 1.232189] megasas: 07.719.03.00-rc1
10598 11:09:06.720081 <6>[ 1.241879] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10599 11:09:06.728155 <6>[ 1.249045] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10600 11:09:06.744155 <6>[ 1.265667] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10601 11:09:06.805447 <6>[ 1.319809] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10602 11:09:07.066389 <6>[ 1.588228] Freeing initrd memory: 18268K
10603 11:09:07.077981 <6>[ 1.599895] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10604 11:09:07.089799 <6>[ 1.611017] tun: Universal TUN/TAP device driver, 1.6
10605 11:09:07.092644 <6>[ 1.617093] thunder_xcv, ver 1.0
10606 11:09:07.096310 <6>[ 1.620600] thunder_bgx, ver 1.0
10607 11:09:07.099525 <6>[ 1.624096] nicpf, ver 1.0
10608 11:09:07.109917 <6>[ 1.628134] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10609 11:09:07.113424 <6>[ 1.635610] hns3: Copyright (c) 2017 Huawei Corporation.
10610 11:09:07.119647 <6>[ 1.641198] hclge is initializing
10611 11:09:07.123124 <6>[ 1.644780] e1000: Intel(R) PRO/1000 Network Driver
10612 11:09:07.129511 <6>[ 1.649909] e1000: Copyright (c) 1999-2006 Intel Corporation.
10613 11:09:07.132729 <6>[ 1.655925] e1000e: Intel(R) PRO/1000 Network Driver
10614 11:09:07.139494 <6>[ 1.661141] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10615 11:09:07.145802 <6>[ 1.667330] igb: Intel(R) Gigabit Ethernet Network Driver
10616 11:09:07.152715 <6>[ 1.672979] igb: Copyright (c) 2007-2014 Intel Corporation.
10617 11:09:07.159356 <6>[ 1.678817] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10618 11:09:07.165700 <6>[ 1.685335] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10619 11:09:07.169095 <6>[ 1.691797] sky2: driver version 1.30
10620 11:09:07.175348 <6>[ 1.696740] usbcore: registered new device driver r8152-cfgselector
10621 11:09:07.181874 <6>[ 1.703275] usbcore: registered new interface driver r8152
10622 11:09:07.188457 <6>[ 1.709095] VFIO - User Level meta-driver version: 0.3
10623 11:09:07.195370 <6>[ 1.717371] usbcore: registered new interface driver usb-storage
10624 11:09:07.201909 <6>[ 1.723822] usbcore: registered new device driver onboard-usb-hub
10625 11:09:07.211246 <6>[ 1.733017] mt6397-rtc mt6359-rtc: registered as rtc0
10626 11:09:07.220861 <6>[ 1.738484] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:09:06 UTC (1720609746)
10627 11:09:07.224910 <6>[ 1.748056] i2c_dev: i2c /dev entries driver
10628 11:09:07.238660 <4>[ 1.760223] cpu cpu0: supply cpu not found, using dummy regulator
10629 11:09:07.245042 <4>[ 1.766650] cpu cpu1: supply cpu not found, using dummy regulator
10630 11:09:07.251781 <4>[ 1.773071] cpu cpu2: supply cpu not found, using dummy regulator
10631 11:09:07.258160 <4>[ 1.779479] cpu cpu3: supply cpu not found, using dummy regulator
10632 11:09:07.265135 <4>[ 1.785879] cpu cpu4: supply cpu not found, using dummy regulator
10633 11:09:07.271655 <4>[ 1.792281] cpu cpu5: supply cpu not found, using dummy regulator
10634 11:09:07.278298 <4>[ 1.798678] cpu cpu6: supply cpu not found, using dummy regulator
10635 11:09:07.285383 <4>[ 1.805093] cpu cpu7: supply cpu not found, using dummy regulator
10636 11:09:07.303999 <6>[ 1.825737] cpu cpu0: EM: created perf domain
10637 11:09:07.307785 <6>[ 1.830650] cpu cpu4: EM: created perf domain
10638 11:09:07.315167 <6>[ 1.836290] sdhci: Secure Digital Host Controller Interface driver
10639 11:09:07.321522 <6>[ 1.842722] sdhci: Copyright(c) Pierre Ossman
10640 11:09:07.328072 <6>[ 1.847681] Synopsys Designware Multimedia Card Interface Driver
10641 11:09:07.334454 <6>[ 1.854327] sdhci-pltfm: SDHCI platform and OF driver helper
10642 11:09:07.338028 <6>[ 1.854389] mmc0: CQHCI version 5.10
10643 11:09:07.344412 <6>[ 1.864684] ledtrig-cpu: registered to indicate activity on CPUs
10644 11:09:07.351281 <6>[ 1.871725] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10645 11:09:07.357811 <6>[ 1.878773] usbcore: registered new interface driver usbhid
10646 11:09:07.360891 <6>[ 1.884595] usbhid: USB HID core driver
10647 11:09:07.367627 <6>[ 1.888790] spi_master spi0: will run message pump with realtime priority
10648 11:09:07.413093 <6>[ 1.927929] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10649 11:09:07.431261 <6>[ 1.943091] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10650 11:09:07.434547 <6>[ 1.956137] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15c14
10651 11:09:07.441994 <6>[ 1.963651] cros-ec-spi spi0.0: Chrome EC device registered
10652 11:09:07.449126 <6>[ 1.969691] mmc0: Command Queue Engine enabled
10653 11:09:07.455008 <6>[ 1.974439] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10654 11:09:07.461299 <6>[ 1.982297] mmcblk0: mmc0:0001 DA4128 116 GiB
10655 11:09:07.469974 <6>[ 1.991940] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10656 11:09:07.477773 <6>[ 1.999788] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10657 11:09:07.487789 <6>[ 2.005763] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10658 11:09:07.494672 <6>[ 2.006090] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10659 11:09:07.497598 <6>[ 2.016669] NET: Registered PF_PACKET protocol family
10660 11:09:07.504478 <6>[ 2.020979] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10661 11:09:07.511223 <6>[ 2.025710] 9pnet: Installing 9P2000 support
10662 11:09:07.514284 <5>[ 2.036692] Key type dns_resolver registered
10663 11:09:07.517906 <6>[ 2.041638] registered taskstats version 1
10664 11:09:07.524230 <5>[ 2.046021] Loading compiled-in X.509 certificates
10665 11:09:07.554455 <4>[ 2.069490] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 11:09:07.563777 <4>[ 2.080429] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10667 11:09:07.578753 <6>[ 2.101012] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10668 11:09:07.586145 <6>[ 2.107990] xhci-mtk 11200000.usb: xHCI Host Controller
10669 11:09:07.592758 <6>[ 2.113516] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10670 11:09:07.602967 <6>[ 2.121384] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10671 11:09:07.609696 <6>[ 2.130818] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10672 11:09:07.616092 <6>[ 2.136995] xhci-mtk 11200000.usb: xHCI Host Controller
10673 11:09:07.622605 <6>[ 2.142493] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10674 11:09:07.629190 <6>[ 2.150150] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10675 11:09:07.636168 <6>[ 2.158004] hub 1-0:1.0: USB hub found
10676 11:09:07.639792 <6>[ 2.162025] hub 1-0:1.0: 1 port detected
10677 11:09:07.646211 <6>[ 2.166307] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10678 11:09:07.654280 <6>[ 2.175047] hub 2-0:1.0: USB hub found
10679 11:09:07.656606 <6>[ 2.179076] hub 2-0:1.0: 1 port detected
10680 11:09:07.663826 <6>[ 2.185683] mtk-msdc 11f70000.mmc: Got CD GPIO
10681 11:09:07.677874 <6>[ 2.195778] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10682 11:09:07.687382 <6>[ 2.204155] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10683 11:09:07.694149 <6>[ 2.212498] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10684 11:09:07.704027 <6>[ 2.220845] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10685 11:09:07.711148 <6>[ 2.229184] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10686 11:09:07.720358 <6>[ 2.237527] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10687 11:09:07.727285 <6>[ 2.245867] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10688 11:09:07.737215 <6>[ 2.254206] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10689 11:09:07.744388 <6>[ 2.262545] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10690 11:09:07.753817 <6>[ 2.270883] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10691 11:09:07.760398 <6>[ 2.279222] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10692 11:09:07.770698 <6>[ 2.287573] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10693 11:09:07.777209 <6>[ 2.295912] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10694 11:09:07.786941 <6>[ 2.304251] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10695 11:09:07.793647 <6>[ 2.312590] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10696 11:09:07.800559 <6>[ 2.321305] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10697 11:09:07.806779 <6>[ 2.328503] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10698 11:09:07.813947 <6>[ 2.335279] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10699 11:09:07.823655 <6>[ 2.342082] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10700 11:09:07.830091 <6>[ 2.349013] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10701 11:09:07.836932 <6>[ 2.355904] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10702 11:09:07.847054 <6>[ 2.365044] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10703 11:09:07.856781 <6>[ 2.374168] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10704 11:09:07.866688 <6>[ 2.383463] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10705 11:09:07.876313 <6>[ 2.392931] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10706 11:09:07.886974 <6>[ 2.402400] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10707 11:09:07.892934 <6>[ 2.411522] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10708 11:09:07.903148 <6>[ 2.420990] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10709 11:09:07.913071 <6>[ 2.430110] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10710 11:09:07.923192 <6>[ 2.439422] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10711 11:09:07.932764 <6>[ 2.449584] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10712 11:09:07.942639 <6>[ 2.461038] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 11:09:07.950976 <6>[ 2.472027] Trying to probe devices needed for running init ...
10714 11:09:07.960728 <3>[ 2.479234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10715 11:09:08.072182 <6>[ 2.589953] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10716 11:09:08.226184 <6>[ 2.747549] hub 1-1:1.0: USB hub found
10717 11:09:08.229428 <6>[ 2.752059] hub 1-1:1.0: 4 ports detected
10718 11:09:08.241286 <6>[ 2.763011] hub 1-1:1.0: USB hub found
10719 11:09:08.245065 <6>[ 2.767321] hub 1-1:1.0: 4 ports detected
10720 11:09:08.352163 <6>[ 2.870317] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10721 11:09:08.379342 <6>[ 2.900909] hub 2-1:1.0: USB hub found
10722 11:09:08.382221 <6>[ 2.905484] hub 2-1:1.0: 3 ports detected
10723 11:09:08.395093 <6>[ 2.916571] hub 2-1:1.0: USB hub found
10724 11:09:08.398225 <6>[ 2.920977] hub 2-1:1.0: 3 ports detected
10725 11:09:08.564050 <6>[ 3.081978] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10726 11:09:08.696058 <6>[ 3.217817] hub 1-1.4:1.0: USB hub found
10727 11:09:08.699305 <6>[ 3.222478] hub 1-1.4:1.0: 2 ports detected
10728 11:09:08.712471 <6>[ 3.234023] hub 1-1.4:1.0: USB hub found
10729 11:09:08.715653 <6>[ 3.238628] hub 1-1.4:1.0: 2 ports detected
10730 11:09:08.776093 <6>[ 3.294184] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10731 11:09:08.884391 <6>[ 3.402607] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10732 11:09:08.920316 <4>[ 3.438744] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10733 11:09:08.930344 <4>[ 3.447837] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10734 11:09:08.969641 <6>[ 3.491493] r8152 2-1.3:1.0 eth0: v1.12.13
10735 11:09:09.023286 <6>[ 3.541936] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10736 11:09:09.219796 <6>[ 3.737995] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10737 11:09:10.678209 <6>[ 5.200211] r8152 2-1.3:1.0 eth0: carrier on
10738 11:09:10.715777 <5>[ 5.221734] Sending DHCP requests ., OK
10739 11:09:10.722472 <6>[ 5.241974] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10740 11:09:10.725760 <6>[ 5.250257] IP-Config: Complete:
10741 11:09:10.739163 <6>[ 5.253753] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10742 11:09:10.746013 <6>[ 5.264459] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10743 11:09:10.751982 <6>[ 5.273078] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10744 11:09:10.758396 <6>[ 5.273087] nameserver0=192.168.201.1
10745 11:09:10.761567 <6>[ 5.285224] clk: Disabling unused clocks
10746 11:09:10.765361 <6>[ 5.290744] ALSA device list:
10747 11:09:10.771924 <6>[ 5.293994] No soundcards found.
10748 11:09:10.779529 <6>[ 5.301734] Freeing unused kernel memory: 8512K
10749 11:09:10.782843 <6>[ 5.306655] Run /init as init process
10750 11:09:10.793357 Loading, please wait...
10751 11:09:10.820456 Starting systemd-udevd version 252.22-1~deb12u1
10752 11:09:11.115298 <6>[ 5.633835] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10753 11:09:11.121779 <6>[ 5.635235] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10754 11:09:11.132021 <6>[ 5.649741] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10755 11:09:11.138862 <6>[ 5.651069] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10756 11:09:11.148349 <6>[ 5.651307] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10757 11:09:11.155270 <6>[ 5.651313] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10758 11:09:11.164561 <4>[ 5.651514] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10759 11:09:11.171698 <6>[ 5.652249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10760 11:09:11.181559 <6>[ 5.652265] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10761 11:09:11.187572 <6>[ 5.652950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10762 11:09:11.194935 <6>[ 5.652970] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10763 11:09:11.204454 <6>[ 5.652975] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10764 11:09:11.214400 <6>[ 5.652982] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10765 11:09:11.220725 <6>[ 5.658472] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10766 11:09:11.228469 <3>[ 5.686812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 11:09:11.234380 <6>[ 5.698229] mc: Linux media interface: v0.10
10768 11:09:11.240994 <3>[ 5.698874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 11:09:11.247931 <6>[ 5.715117] remoteproc remoteproc0: scp is available
10770 11:09:11.255149 <6>[ 5.715809] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10771 11:09:11.265084 <3>[ 5.722603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 11:09:11.271217 <4>[ 5.723811] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10773 11:09:11.277997 <4>[ 5.727594] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10774 11:09:11.281171 <6>[ 5.730763] remoteproc remoteproc0: powering up scp
10775 11:09:11.291289 <4>[ 5.739181] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10776 11:09:11.298426 <4>[ 5.739181] Fallback method does not support PEC.
10777 11:09:11.304830 <3>[ 5.739780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 11:09:11.314663 <6>[ 5.748514] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10779 11:09:11.321270 <3>[ 5.756268] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10780 11:09:11.331563 <3>[ 5.756635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 11:09:11.334300 <6>[ 5.760956] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10782 11:09:11.344225 <3>[ 5.768963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 11:09:11.350881 <6>[ 5.779039] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10784 11:09:11.360918 <3>[ 5.779330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10785 11:09:11.367601 <3>[ 5.781833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 11:09:11.377281 <3>[ 5.781839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 11:09:11.383909 <3>[ 5.781913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 11:09:11.390456 <3>[ 5.781967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 11:09:11.400216 <3>[ 5.781972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 11:09:11.406965 <3>[ 5.781975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 11:09:11.417085 <3>[ 5.782046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 11:09:11.423713 <3>[ 5.782049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 11:09:11.432949 <3>[ 5.782053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 11:09:11.440029 <3>[ 5.782056] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 11:09:11.449525 <3>[ 5.782059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 11:09:11.456184 <3>[ 5.782074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 11:09:11.462772 <6>[ 5.790242] pci_bus 0000:00: root bus resource [bus 00-ff]
10798 11:09:11.473000 <6>[ 5.793401] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10799 11:09:11.482535 <6>[ 5.793764] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10800 11:09:11.489443 <6>[ 5.832806] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10801 11:09:11.499408 <6>[ 5.840152] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10802 11:09:11.502330 <6>[ 5.864264] videodev: Linux video capture interface: v2.00
10803 11:09:11.512396 <6>[ 5.870777] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10804 11:09:11.515824 <6>[ 5.895258] Bluetooth: Core ver 2.22
10805 11:09:11.525754 <6>[ 5.899485] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10806 11:09:11.529030 <6>[ 5.902795] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10807 11:09:11.539076 <6>[ 5.910834] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10808 11:09:11.545720 <6>[ 5.910962] NET: Registered PF_BLUETOOTH protocol family
10809 11:09:11.552076 <6>[ 5.910964] Bluetooth: HCI device and connection manager initialized
10810 11:09:11.555986 <6>[ 5.910988] Bluetooth: HCI socket layer initialized
10811 11:09:11.562278 <6>[ 5.910995] Bluetooth: L2CAP socket layer initialized
10812 11:09:11.565345 <6>[ 5.911038] Bluetooth: SCO socket layer initialized
10813 11:09:11.575504 <6>[ 5.912903] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10814 11:09:11.581643 <6>[ 5.915139] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10815 11:09:11.591384 <6>[ 5.919082] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10816 11:09:11.598026 <6>[ 5.926960] remoteproc remoteproc0: remote processor scp is now up
10817 11:09:11.605006 <6>[ 5.944166] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10818 11:09:11.607969 <6>[ 5.951310] pci 0000:00:00.0: supports D1 D2
10819 11:09:11.614558 <6>[ 5.960471] usbcore: registered new interface driver btusb
10820 11:09:11.624612 <4>[ 5.960934] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10821 11:09:11.631214 <3>[ 5.960944] Bluetooth: hci0: Failed to load firmware file (-2)
10822 11:09:11.637762 <3>[ 5.960949] Bluetooth: hci0: Failed to set up firmware (-2)
10823 11:09:11.647915 <4>[ 5.960954] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10824 11:09:11.660863 <6>[ 5.961165] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10825 11:09:11.664206 <6>[ 5.961269] usbcore: registered new interface driver uvcvideo
10826 11:09:11.674394 <6>[ 5.967409] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10827 11:09:11.681151 <6>[ 5.968485] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10828 11:09:11.687758 <6>[ 5.968785] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10829 11:09:11.694363 <6>[ 6.214408] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10830 11:09:11.700412 <6>[ 6.220699] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10831 11:09:11.707168 <6>[ 6.228218] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10832 11:09:11.717034 <6>[ 6.235702] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10833 11:09:11.720650 <6>[ 6.243277] pci 0000:01:00.0: supports D1 D2
10834 11:09:11.727040 <6>[ 6.247795] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10835 11:09:11.751344 <6>[ 6.269990] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10836 11:09:11.758290 <6>[ 6.276894] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10837 11:09:11.764448 <6>[ 6.284978] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10838 11:09:11.774968 <6>[ 6.292976] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10839 11:09:11.781464 <6>[ 6.300981] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10840 11:09:11.791030 <6>[ 6.308983] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10841 11:09:11.794176 <6>[ 6.316982] pci 0000:00:00.0: PCI bridge to [bus 01]
10842 11:09:11.804171 <6>[ 6.322198] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10843 11:09:11.810522 <6>[ 6.330322] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10844 11:09:11.817265 <6>[ 6.337168] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10845 11:09:11.824085 <6>[ 6.344119] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10846 11:09:11.842926 <5>[ 6.361612] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10847 11:09:11.864651 <5>[ 6.383498] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10848 11:09:11.871215 <5>[ 6.391455] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10849 11:09:11.881983 <4>[ 6.399951] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10850 11:09:11.887877 <6>[ 6.408865] cfg80211: failed to load regulatory.db
10851 11:09:11.948297 <6>[ 6.466368] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10852 11:09:11.954290 <6>[ 6.473914] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10853 11:09:11.978853 <6>[ 6.500788] mt7921e 0000:01:00.0: ASIC revision: 79610010
10854 11:09:12.083702 <6>[ 6.602440] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10855 11:09:12.087223 <6>[ 6.602440]
10856 11:09:12.096912 Begin: Loading essential drivers ... done.
10857 11:09:12.100164 Begin: Running /scripts/init-premount ... done.
10858 11:09:12.106550 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10859 11:09:12.117272 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10860 11:09:12.119745 Device /sys/class/net/eth0 found
10861 11:09:12.120320 done.
10862 11:09:12.147933 Begin: Waiting up to 180 secs for any network device to become available ... done.
10863 11:09:12.207983 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10864 11:09:12.215751 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10865 11:09:12.222338 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10866 11:09:12.229071 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10867 11:09:12.235796 host : mt8192-asurada-spherion-r0-cbg-9
10868 11:09:12.242446 domain : lava-rack
10869 11:09:12.245327 rootserver: 192.168.201.1 rootpath:
10870 11:09:12.248574 filename :
10871 11:09:12.276864 done.
10872 11:09:12.286147 Begin: Running /scripts/nfs-bottom ... done.
10873 11:09:12.307595 Begin: Running /scripts/init-bottom ... done.
10874 11:09:12.350507 <6>[ 6.869529] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10875 11:09:13.685843 <6>[ 8.208158] NET: Registered PF_INET6 protocol family
10876 11:09:13.693183 <6>[ 8.215605] Segment Routing with IPv6
10877 11:09:13.696642 <6>[ 8.219614] In-situ OAM (IOAM) with IPv6
10878 11:09:13.878185 <30>[ 8.374033] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10879 11:09:13.884893 <30>[ 8.407140] systemd[1]: Detected architecture arm64.
10880 11:09:13.895779
10881 11:09:13.899135 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10882 11:09:13.899755
10883 11:09:13.921955 <30>[ 8.444387] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10884 11:09:15.143613 <30>[ 9.662842] systemd[1]: Queued start job for default target graphical.target.
10885 11:09:15.179959 <30>[ 9.698868] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10886 11:09:15.186608 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10887 11:09:15.208855 <30>[ 9.727742] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10888 11:09:15.218106 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10889 11:09:15.236722 <30>[ 9.755736] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10890 11:09:15.246755 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10891 11:09:15.264389 <30>[ 9.783299] systemd[1]: Created slice user.slice - User and Session Slice.
10892 11:09:15.270743 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10893 11:09:15.294331 <30>[ 9.810258] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10894 11:09:15.304279 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10895 11:09:15.322671 <30>[ 9.838199] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10896 11:09:15.328838 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10897 11:09:15.357458 <30>[ 9.866637] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10898 11:09:15.367650 <30>[ 9.886541] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10899 11:09:15.374365 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10900 11:09:15.390458 <30>[ 9.909960] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10901 11:09:15.397887 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10902 11:09:15.415592 <30>[ 9.934027] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10903 11:09:15.425093 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10904 11:09:15.439841 <30>[ 9.962042] systemd[1]: Reached target paths.target - Path Units.
10905 11:09:15.449613 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10906 11:09:15.467625 <30>[ 9.986424] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10907 11:09:15.474293 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10908 11:09:15.487729 <30>[ 10.009938] systemd[1]: Reached target slices.target - Slice Units.
10909 11:09:15.497394 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10910 11:09:15.512242 <30>[ 10.034384] systemd[1]: Reached target swap.target - Swaps.
10911 11:09:15.518627 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10912 11:09:15.539398 <30>[ 10.058451] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10913 11:09:15.549301 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10914 11:09:15.567181 <30>[ 10.086447] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10915 11:09:15.577468 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10916 11:09:15.598779 <30>[ 10.117548] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10917 11:09:15.608181 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10918 11:09:15.624141 <30>[ 10.143504] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10919 11:09:15.634091 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10920 11:09:15.651350 <30>[ 10.170605] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10921 11:09:15.658062 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10922 11:09:15.676398 <30>[ 10.195687] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10923 11:09:15.686603 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10924 11:09:15.707700 <30>[ 10.226376] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10925 11:09:15.716852 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10926 11:09:15.735797 <30>[ 10.254564] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10927 11:09:15.745060 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10928 11:09:15.795029 <30>[ 10.314413] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10929 11:09:15.802016 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10930 11:09:15.821610 <30>[ 10.340378] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10931 11:09:15.827731 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10932 11:09:15.886894 <30>[ 10.406158] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10933 11:09:15.893235 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10934 11:09:15.917239 <30>[ 10.430273] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10935 11:09:15.930879 <30>[ 10.450189] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10936 11:09:15.940723 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10937 11:09:15.968000 <30>[ 10.487386] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10938 11:09:15.974611 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10939 11:09:16.004588 <30>[ 10.523424] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10940 11:09:16.011004 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10941 11:09:16.036480 <30>[ 10.555258] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10942 11:09:16.042723 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10943 11:09:16.052454 <6>[ 10.569015] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10944 11:09:16.052892
10945 11:09:16.075535 <30>[ 10.594757] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10946 11:09:16.085614 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10947 11:09:16.112284 <30>[ 10.631305] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10948 11:09:16.118695 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10949 11:09:16.143291 <30>[ 10.662527] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10950 11:09:16.149894 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10951 11:09:16.159529 <6>[ 10.681821] fuse: init (API version 7.37)
10952 11:09:16.179639 <30>[ 10.698882] systemd[1]: Starting systemd-journald.service - Journal Service...
10953 11:09:16.187236 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10954 11:09:16.212318 <30>[ 10.731167] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10955 11:09:16.218625 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10956 11:09:16.246634 <30>[ 10.762666] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10957 11:09:16.253190 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10958 11:09:16.299268 <30>[ 10.818838] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10959 11:09:16.308882 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10960 11:09:16.334152 <30>[ 10.853753] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10961 11:09:16.340543 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10962 11:09:16.372607 <30>[ 10.891606] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10963 11:09:16.378678 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10964 11:09:16.399171 <3>[ 10.918326] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:09:16.409196 <30>[ 10.918328] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10966 11:09:16.422566 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 10.940551] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 11:09:16.425405 X Message Queue File System.
10968 11:09:16.442830 <30>[ 10.962280] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10969 11:09:16.449772 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10970 11:09:16.468741 <30>[ 10.986995] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10971 11:09:16.478294 [[0;32m OK [<3>[ 10.996624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:09:16.485009 0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10973 11:09:16.503663 <30>[ 11.022695] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10974 11:09:16.510060 <3>[ 11.027763] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 11:09:16.519905 <30>[ 11.030819] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10976 11:09:16.526980 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10977 11:09:16.539531 <3>[ 11.058600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 11:09:16.549483 <30>[ 11.068266] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10979 11:09:16.556004 <30>[ 11.076034] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10980 11:09:16.569878 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 11.087503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 11:09:16.572606 m_mod.s…e[0m - Load Kernel Module dm_mod.
10982 11:09:16.591415 <30>[ 11.110874] systemd[1]: modprobe@drm.service: Deactivated successfully.
10983 11:09:16.598415 <3>[ 11.117521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 11:09:16.604717 <30>[ 11.118478] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10985 11:09:16.615042 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10986 11:09:16.627669 <3>[ 11.147495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 11:09:16.639363 <30>[ 11.158717] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10988 11:09:16.649222 <30>[ 11.166824] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10989 11:09:16.659345 [[0;32m OK [<3>[ 11.177084] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 11:09:16.666049 0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10991 11:09:16.684627 <30>[ 11.203213] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10992 11:09:16.690818 <30>[ 11.210849] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10993 11:09:16.704280 [[0;32m OK [0m] Finished [0<3>[ 11.221445] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 11:09:16.707260 ;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10995 11:09:16.732569 <30>[ 11.251802] systemd[1]: modprobe@loop.service: Deactivated successfully.
10996 11:09:16.739030 <30>[ 11.259466] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10997 11:09:16.748711 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10998 11:09:16.772416 <30>[ 11.292033] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10999 11:09:16.782230 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11000 11:09:16.807009 <4>[ 11.319541] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11001 11:09:16.817254 <3>[ 11.335199] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11002 11:09:16.823240 <30>[ 11.335794] systemd[1]: Started systemd-journald.service - Journal Service.
11003 11:09:16.830038 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11004 11:09:16.851123 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11005 11:09:16.872217 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11006 11:09:16.896118 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11007 11:09:16.921804 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11008 11:09:16.991475 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11009 11:09:17.014216 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11010 11:09:17.036817 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11011 11:09:17.064826 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11012 11:09:17.104995 <46>[ 11.624473] systemd-journald[309]: Received client request to flush runtime journal.
11013 11:09:17.123993 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11014 11:09:17.360246 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11015 11:09:17.690058 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11016 11:09:17.707758 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11017 11:09:17.728288 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11018 11:09:18.199998 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11019 11:09:18.528117 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11020 11:09:18.558321 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11021 11:09:18.611635 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11022 11:09:18.722375 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11023 11:09:18.743129 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11024 11:09:18.766717 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11025 11:09:18.831755 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11026 11:09:18.854827 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11027 11:09:19.076273 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11028 11:09:19.135950 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11029 11:09:19.194664 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11030 11:09:19.502713 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11031 11:09:19.543335 <6>[ 14.066261] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11032 11:09:19.564330 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11033 11:09:19.590093 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11034 11:09:19.667570 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11035 11:09:19.686928 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11036 11:09:19.749142 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11037 11:09:19.780928 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11038 11:09:19.807295 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11039 11:09:19.832353 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11040 11:09:19.864861 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11041 11:09:19.907931 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11042 11:09:19.939052 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11043 11:09:19.969639 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11044 11:09:20.007277 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11045 11:09:20.030917 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11046 11:09:20.050695 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11047 11:09:20.066453 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11048 11:09:20.095221 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11049 11:09:20.118304 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11050 11:09:20.134988 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11051 11:09:20.154623 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11052 11:09:20.174616 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11053 11:09:20.190913 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11054 11:09:20.208880 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11055 11:09:20.226512 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11056 11:09:20.242655 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11057 11:09:20.283996 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11058 11:09:20.321596 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11059 11:09:20.423891 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11060 11:09:20.452858 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11061 11:09:20.492766 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11062 11:09:20.568787 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11063 11:09:20.626916 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11064 11:09:20.647303 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11065 11:09:20.706771 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11066 11:09:20.766223 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11067 11:09:20.788476 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11068 11:09:20.812103 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11069 11:09:20.831256 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11070 11:09:20.889430 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11071 11:09:20.942229 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11072 11:09:21.024845
11073 11:09:21.027916 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11074 11:09:21.028315
11075 11:09:21.030856 debian-bookworm-arm64 login: root (automatic login)
11076 11:09:21.031254
11077 11:09:21.306857 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11078 11:09:21.307306
11079 11:09:21.313818 The programs included with the Debian GNU/Linux system are free software;
11080 11:09:21.319991 the exact distribution terms for each program are described in the
11081 11:09:21.323245 individual files in /usr/share/doc/*/copyright.
11082 11:09:21.323714
11083 11:09:21.330337 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11084 11:09:21.333572 permitted by applicable law.
11085 11:09:21.448302 Matched prompt #10: / #
11087 11:09:21.448552 Setting prompt string to ['/ #']
11088 11:09:21.448641 end: 2.2.5.1 login-action (duration 00:00:17) [common]
11090 11:09:21.448821 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
11091 11:09:21.448899 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11092 11:09:21.448975 Setting prompt string to ['/ #']
11093 11:09:21.449029 Forcing a shell prompt, looking for ['/ #']
11094 11:09:21.449081 Sending line: ''
11096 11:09:21.499372 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11097 11:09:21.499491 Waiting using forced prompt support (timeout 00:02:30)
11098 11:09:21.504034 / #
11099 11:09:21.504287 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11100 11:09:21.504372 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11101 11:09:21.504453 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786847/extract-nfsrootfs-fdzh_dox'"
11103 11:09:21.609805 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786847/extract-nfsrootfs-fdzh_dox'
11104 11:09:21.610070 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11106 11:09:21.717015 / # export NFS_SERVER_IP='192.168.201.1'
11107 11:09:21.717811 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11108 11:09:21.718294 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
11109 11:09:21.718762 end: 2 depthcharge-action (duration 00:01:43) [common]
11110 11:09:21.719231 start: 3 lava-test-retry (timeout 00:30:00) [common]
11111 11:09:21.719734 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11112 11:09:21.720126 Using namespace: common
11113 11:09:21.720493 Sending line: '#'
11115 11:09:21.821813 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11116 11:09:21.827108 / # #
11117 11:09:21.827813 Using /lava-14786847
11118 11:09:21.828135 Sending line: 'export SHELL=/bin/sh'
11120 11:09:21.935035 / # export SHELL=/bin/sh
11121 11:09:21.943564 Sending line: '. /lava-14786847/environment'
11123 11:09:22.049497 / # . /lava-14786847/environment
11124 11:09:22.056032 Sending line: '/lava-14786847/bin/lava-test-runner /lava-14786847/0'
11126 11:09:22.156535 Test shell timeout: 10s (minimum of the action and connection timeout)
11127 11:09:22.161323 / # /lava-14786847/bin/lava-test-runner /lava-14786847/0
11128 11:09:22.437931 + export TESTRUN_ID=0_lc-compliance
11129 11:09:22.444824 + cd /lava-14786847/0/tests/0_lc-compliance
11130 11:09:22.445265 + cat uuid
11131 11:09:22.456943 + UUID=14786847_1.6.2.3.1
11132 11:09:22.457400 + set +x
11133 11:09:22.463978 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14786847_1.6.2.3.1>
11134 11:09:22.464733 Received signal: <STARTRUN> 0_lc-compliance 14786847_1.6.2.3.1
11135 11:09:22.465162 Starting test lava.0_lc-compliance (14786847_1.6.2.3.1)
11136 11:09:22.465665 Skipping test definition patterns.
11137 11:09:22.467042 + /usr/bin/lc-compliance-parser.sh
11138 11:09:24.165676 [0:00:18.568779847] [415] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11139 11:09:24.169208 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11140 11:09:24.183399 [0:00:18.586548385] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11141 11:09:24.245102 [0:00:18.648470000] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11142 11:09:24.265092 [==========] Running 120 tests from 1 test suite.
11143 11:09:24.299721 [0:00:18.702714231] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11144 11:09:24.355538 [0:00:18.758750539] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11145 11:09:24.362222 [----------] Global test environment set-up.
11146 11:09:24.461279 [----------] 120 tests from CaptureTests/SingleStream
11147 11:09:24.559562 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11148 11:09:24.636161 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11149 11:09:24.636844 Received signal: <TESTSET> START CaptureTests/SingleStream
11150 11:09:24.637186 Starting test_set CaptureTests/SingleStream
11151 11:09:24.639246 Camera needs 4 requests, can't test only 1
11152 11:09:24.732220 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11153 11:09:24.784320 [0:00:19.187290462] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11154 11:09:24.827605
11155 11:09:24.932435 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
11156 11:09:25.063851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11157 11:09:25.064547 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11159 11:09:25.083898 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11160 11:09:25.149039 Camera needs 4 requests, can't test only 2
11161 11:09:25.247208 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11162 11:09:25.355615
11163 11:09:25.456877 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (54 ms)
11164 11:09:25.476684 [0:00:19.879740924] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11165 11:09:25.576922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11166 11:09:25.577721 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11168 11:09:25.597231 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11169 11:09:25.665772 Camera needs 4 requests, can't test only 3
11170 11:09:25.767121 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11171 11:09:25.857145
11172 11:09:25.961983 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (55 ms)
11173 11:09:26.080105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11174 11:09:26.080793 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11176 11:09:26.100370 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11177 11:09:26.167004 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (429 ms)
11178 11:09:26.280839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11179 11:09:26.281520 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11181 11:09:26.300424 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11182 11:09:26.366920 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (691 ms)
11183 11:09:26.489274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11184 11:09:26.489950 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11186 11:09:26.510911 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11187 11:09:26.725463 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1257 ms)
11188 11:09:26.735121 [0:00:21.137846616] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11189 11:09:26.848858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11190 11:09:26.849291 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11192 11:09:26.869844 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11193 11:09:28.542837 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1817 ms)
11194 11:09:28.552756 [0:00:22.955738616] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11195 11:09:28.664728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11196 11:09:28.665416 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11198 11:09:28.683476 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11199 11:09:31.271396 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2728 ms)
11200 11:09:31.281294 [0:00:25.684772539] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11201 11:09:31.378532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11202 11:09:31.378815 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11204 11:09:31.395850 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11205 11:09:35.469643 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4198 ms)
11206 11:09:35.479194 [0:00:29.883297616] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11207 11:09:35.575714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11208 11:09:35.576004 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11210 11:09:35.591310 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11211 11:09:41.389017 <6>[ 35.917953] vpu: disabling
11212 11:09:41.391880 <6>[ 35.921053] vproc2: disabling
11213 11:09:41.395326 <6>[ 35.924378] vproc1: disabling
11214 11:09:41.398589 <6>[ 35.927687] vaud18: disabling
11215 11:09:41.405215 <6>[ 35.931193] vsram_others: disabling
11216 11:09:41.408575 <6>[ 35.935156] va09: disabling
11217 11:09:41.411801 <6>[ 35.938318] vsram_md: disabling
11218 11:09:41.415087 <6>[ 35.941883] Vgpu: disabling
11219 11:09:42.047588 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6578 ms)
11220 11:09:42.057201 [0:00:36.462174078] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11221 11:09:42.113597 [0:00:36.519104694] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11222 11:09:42.156446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11223 11:09:42.156834 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11225 11:09:42.166233 [0:00:36.574199848] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 11:09:42.177475 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11227 11:09:42.220688 [0:00:36.626137771] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11228 11:09:42.239811 Camera needs 4 requests, can't test only 1
11229 11:09:42.327034 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11230 11:09:42.400612
11231 11:09:42.495793 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11232 11:09:42.586292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11233 11:09:42.586588 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11235 11:09:42.604446 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11236 11:09:42.661966 Camera needs 4 requests, can't test only 2
11237 11:09:42.744724 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11238 11:09:42.821910
11239 11:09:42.905482 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (56 ms)
11240 11:09:42.919492 [0:00:37.325363386] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 11:09:43.003739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11242 11:09:43.004037 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11244 11:09:43.020182 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11245 11:09:43.074008 Camera needs 4 requests, can't test only 3
11246 11:09:43.160646 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11247 11:09:43.239403
11248 11:09:43.321208 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (51 ms)
11249 11:09:43.418608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11250 11:09:43.418905 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11252 11:09:43.434423 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11253 11:09:43.488481 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (698 ms)
11254 11:09:43.584058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11255 11:09:43.584362 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11257 11:09:43.601668 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11258 11:09:43.818637 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (907 ms)
11259 11:09:43.831484 [0:00:38.233489925] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11260 11:09:43.921040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11261 11:09:43.921343 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11263 11:09:43.936287 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11264 11:09:45.076365 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1257 ms)
11265 11:09:45.089655 [0:00:39.491426694] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11266 11:09:45.186007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11267 11:09:45.186330 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11269 11:09:45.202031 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11270 11:09:46.895278 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1819 ms)
11271 11:09:46.909076 [0:00:41.310812771] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11272 11:09:46.993955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11273 11:09:46.994245 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11275 11:09:47.009220 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11276 11:09:49.624956 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2729 ms)
11277 11:09:49.638093 [0:00:44.040214463] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11278 11:09:49.725546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11279 11:09:49.725862 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11281 11:09:49.744821 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11282 11:09:53.822975 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4198 ms)
11283 11:09:53.835923 [0:00:48.238763618] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11284 11:09:53.942242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11285 11:09:53.943081 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11287 11:09:53.959839 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11288 11:10:00.401259 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6578 ms)
11289 11:10:00.414396 [0:00:54.817680695] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11290 11:10:00.467043 [0:00:54.874219926] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11291 11:10:00.520208 [0:00:54.927735541] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 11:10:00.528313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11293 11:10:00.528949 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11295 11:10:00.546673 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11296 11:10:00.574311 [0:00:54.981930464] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11297 11:10:00.614236 Camera needs 4 requests, can't test only 1
11298 11:10:00.709803 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11299 11:10:00.805101
11300 11:10:00.892621 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11301 11:10:00.999022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11302 11:10:00.999741 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11304 11:10:01.017063 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11305 11:10:01.080600 Camera needs 4 requests, can't test only 2
11306 11:10:01.181460 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11307 11:10:01.269125 [0:00:55.676368695] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11308 11:10:01.277413
11309 11:10:01.382474 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (54 ms)
11310 11:10:01.491870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11311 11:10:01.492546 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11313 11:10:01.510592 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11314 11:10:01.569299 Camera needs 4 requests, can't test only 3
11315 11:10:01.661965 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11316 11:10:01.744352
11317 11:10:01.824463 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (52 ms)
11318 11:10:01.926719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11319 11:10:01.927460 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11321 11:10:01.944003 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11322 11:10:02.009645 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (695 ms)
11323 11:10:02.127417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11324 11:10:02.128141 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11326 11:10:02.147993 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11327 11:10:02.176311 [0:00:56.583556310] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11328 11:10:02.218681 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (905 ms)
11329 11:10:02.328927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11330 11:10:02.329579 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11332 11:10:02.347966 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11333 11:10:03.427029 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1257 ms)
11334 11:10:03.436960 [0:00:57.840614157] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11335 11:10:03.548705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11336 11:10:03.549378 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11338 11:10:03.568240 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11339 11:10:05.241408 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1818 ms)
11340 11:10:05.254662 [0:00:59.658866003] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11341 11:10:05.343756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11342 11:10:05.344037 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11344 11:10:05.359512 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11345 11:10:07.970454 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2729 ms)
11346 11:10:07.983393 [0:01:02.388137157] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11347 11:10:08.072727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11348 11:10:08.073046 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11350 11:10:08.087342 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11351 11:10:12.169136 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4198 ms)
11352 11:10:12.182516 [0:01:06.586650388] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11353 11:10:12.288072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11354 11:10:12.288793 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11356 11:10:12.306551 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11357 11:10:18.746347 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6578 ms)
11358 11:10:18.760033 [0:01:13.164939542] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11359 11:10:18.812290 [0:01:13.221531081] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 11:10:18.867522 [0:01:13.276965388] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 11:10:18.874331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11362 11:10:18.874981 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11364 11:10:18.893584 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11365 11:10:18.924117 [0:01:13.333315465] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11366 11:10:18.957133 Camera needs 4 requests, can't test only 1
11367 11:10:19.039777 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11368 11:10:19.120281
11369 11:10:19.219010 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (56 ms)
11370 11:10:19.322721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11371 11:10:19.323462 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11373 11:10:19.342449 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11374 11:10:19.410951 Camera needs 4 requests, can't test only 2
11375 11:10:19.507590 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11376 11:10:19.606416
11377 11:10:19.616116 [0:01:14.026421388] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11378 11:10:19.709911 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (55 ms)
11379 11:10:19.816236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11380 11:10:19.816961 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11382 11:10:19.836468 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11383 11:10:19.903022 Camera needs 4 requests, can't test only 3
11384 11:10:19.998560 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11385 11:10:20.085967
11386 11:10:20.171910 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)
11387 11:10:20.283086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11388 11:10:20.283939 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11390 11:10:20.303855 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11391 11:10:20.372184 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (694 ms)
11392 11:10:20.486225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11393 11:10:20.486994 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11395 11:10:20.504266 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11396 11:10:20.523334 [0:01:14.932694388] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11397 11:10:20.568835 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (906 ms)
11398 11:10:20.678240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11399 11:10:20.678899 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11401 11:10:20.696727 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11402 11:10:21.769770 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1255 ms)
11403 11:10:21.782748 [0:01:16.189185927] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11404 11:10:21.870846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11405 11:10:21.871129 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11407 11:10:21.888135 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11408 11:10:23.587948 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1818 ms)
11409 11:10:23.601051 [0:01:18.007696158] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11410 11:10:23.685829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11411 11:10:23.686121 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11413 11:10:23.702492 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11414 11:10:26.316617 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11415 11:10:26.329570 [0:01:20.736049696] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11416 11:10:26.420268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11417 11:10:26.420575 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11419 11:10:26.436828 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11420 11:10:30.514323 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4198 ms)
11421 11:10:30.527374 [0:01:24.934248312] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11422 11:10:30.618395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11423 11:10:30.618679 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11425 11:10:30.634659 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11426 11:10:37.092565 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6579 ms)
11427 11:10:37.105521 [0:01:31.513353543] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11428 11:10:37.158194 [0:01:31.569763620] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11429 11:10:37.189967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11430 11:10:37.190235 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11432 11:10:37.211649 [0:01:31.623341005] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 11:10:37.214685 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11434 11:10:37.266698 [0:01:31.678824543] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11435 11:10:37.270189 Camera needs 4 requests, can't test only 1
11436 11:10:37.347760 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11437 11:10:37.423129
11438 11:10:37.505107 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (56 ms)
11439 11:10:37.604097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11440 11:10:37.604379 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11442 11:10:37.619844 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11443 11:10:37.672509 Camera needs 4 requests, can't test only 2
11444 11:10:37.750562 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11445 11:10:37.833225
11446 11:10:37.922086 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11447 11:10:38.014694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11448 11:10:38.014986 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11450 11:10:38.031160 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11451 11:10:38.087808 Camera needs 4 requests, can't test only 3
11452 11:10:38.176321 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11453 11:10:38.254357
11454 11:10:38.333782 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (54 ms)
11455 11:10:38.425859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11456 11:10:38.426135 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11458 11:10:38.443385 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11459 11:10:39.337900 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2079 ms)
11460 11:10:39.350732 [0:01:33.759092005] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11461 11:10:39.439758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11462 11:10:39.440038 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11464 11:10:39.455933 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11465 11:10:42.054867 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2717 ms)
11466 11:10:42.068227 [0:01:36.478674928] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11467 11:10:42.159182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11468 11:10:42.159473 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11470 11:10:42.176357 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11471 11:10:45.818438 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3763 ms)
11472 11:10:45.831274 [0:01:40.242010005] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11473 11:10:45.915655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11474 11:10:45.915928 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11476 11:10:45.929892 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11477 11:10:51.261029 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5442 ms)
11478 11:10:51.273730 [0:01:45.685517621] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11479 11:10:51.362604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11480 11:10:51.362897 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11482 11:10:51.379508 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11483 11:10:59.437360 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8176 ms)
11484 11:10:59.450411 [0:01:53.862033545] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11485 11:10:59.560601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11486 11:10:59.561297 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11488 11:10:59.578336 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11489 11:11:12.020696 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12584 ms)
11490 11:11:12.033527 [0:02:06.447252468] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11491 11:11:12.140363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11492 11:11:12.141071 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11494 11:11:12.160118 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11495 11:11:31.744771 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19726 ms)
11496 11:11:31.757571 [0:02:26.173953316] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11497 11:11:31.811664 [0:02:26.230051239] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11498 11:11:31.847214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11499 11:11:31.847482 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11501 11:11:31.866508 [0:02:26.284417470] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 11:11:31.872886 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11503 11:11:31.921536 [0:02:26.339474085] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11504 11:11:31.924829 Camera needs 4 requests, can't test only 1
11505 11:11:31.993007 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11506 11:11:32.072723
11507 11:11:32.162037 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (58 ms)
11508 11:11:32.254917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11509 11:11:32.255217 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11511 11:11:32.266543 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11512 11:11:32.317871 Camera needs 4 requests, can't test only 2
11513 11:11:32.401467 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11514 11:11:32.481673
11515 11:11:32.562082 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (55 ms)
11516 11:11:32.657865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11517 11:11:32.658181 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11519 11:11:32.671570 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11520 11:11:32.730790 Camera needs 4 requests, can't test only 3
11521 11:11:32.823803 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11522 11:11:32.913816
11523 11:11:33.003130 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11524 11:11:33.102997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11525 11:11:33.103279 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11527 11:11:33.117896 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11528 11:11:33.997537 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2081 ms)
11529 11:11:34.007366 [0:02:28.421665162] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11530 11:11:34.101922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11531 11:11:34.102225 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11533 11:11:34.116515 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11534 11:11:36.710370 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2712 ms)
11535 11:11:36.720049 [0:02:31.136179239] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11536 11:11:36.831372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11537 11:11:36.832148 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11539 11:11:36.847907 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11540 11:11:40.473046 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3762 ms)
11541 11:11:40.482495 [0:02:34.899390316] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11542 11:11:40.600093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11543 11:11:40.600803 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11545 11:11:40.617102 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11546 11:11:45.916041 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5443 ms)
11547 11:11:45.926044 [0:02:40.343354547] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11548 11:11:46.037291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11549 11:11:46.038004 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11551 11:11:46.054299 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11552 11:11:54.092332 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8177 ms)
11553 11:11:54.102230 [0:02:48.520163779] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11554 11:11:54.219280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11555 11:11:54.219983 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11557 11:11:54.233726 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11558 11:12:06.675764 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12584 ms)
11559 11:12:06.685579 [0:03:01.105686087] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11560 11:12:06.791940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11561 11:12:06.792220 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11563 11:12:06.806679 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11564 11:12:26.401227 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19726 ms)
11565 11:12:26.410318 [0:03:20.832061704] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11566 11:12:26.464203 [0:03:20.887760934] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11567 11:12:26.518722 [0:03:20.941746319] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 11:12:26.524848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11569 11:12:26.525636 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11571 11:12:26.539251 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11572 11:12:26.571558 [0:03:20.995033704] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11573 11:12:26.601191 Camera needs 4 requests, can't test only 1
11574 11:12:26.695581 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11575 11:12:26.796463
11576 11:12:26.898058 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (57 ms)
11577 11:12:27.011495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11578 11:12:27.012179 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11580 11:12:27.030486 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11581 11:12:27.092743 Camera needs 4 requests, can't test only 2
11582 11:12:27.191597 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11583 11:12:27.293502
11584 11:12:27.392578 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (54 ms)
11585 11:12:27.493676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11586 11:12:27.494424 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11588 11:12:27.509494 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11589 11:12:27.576361 Camera needs 4 requests, can't test only 3
11590 11:12:27.674339 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11591 11:12:27.770556
11592 11:12:27.875844 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11593 11:12:27.994143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11594 11:12:27.994818 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11596 11:12:28.009782 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11597 11:12:28.645391 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2078 ms)
11598 11:12:28.655412 [0:03:23.075540473] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11599 11:12:28.764472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11600 11:12:28.765152 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11602 11:12:28.779895 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11603 11:12:31.358529 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11604 11:12:31.367899 [0:03:25.790409935] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11605 11:12:31.482618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11606 11:12:31.483303 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11608 11:12:31.499815 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11609 11:12:35.120892 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3763 ms)
11610 11:12:35.130843 [0:03:29.553789935] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11611 11:12:35.244456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11612 11:12:35.244806 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11614 11:12:35.260623 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11615 11:12:40.564370 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5444 ms)
11616 11:12:40.574348 [0:03:34.997747858] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11617 11:12:40.680947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11618 11:12:40.681598 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11620 11:12:40.696268 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11621 11:12:48.740557 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8176 ms)
11622 11:12:48.750463 [0:03:43.174410705] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11623 11:12:48.860203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11624 11:12:48.860854 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11626 11:12:48.875883 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11627 11:13:01.323306 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12584 ms)
11628 11:13:01.333415 [0:03:55.759349552] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11629 11:13:01.433072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11630 11:13:01.433733 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11632 11:13:01.450947 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11633 11:13:21.048393 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19726 ms)
11634 11:13:21.058001 [0:04:15.485685784] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11635 11:13:21.110717 [0:04:15.540860245] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 11:13:21.164905 [0:04:15.594958245] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11637 11:13:21.180298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11638 11:13:21.180926 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11640 11:13:21.197578 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11641 11:13:21.217880 [0:04:15.647893168] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 11:13:21.263367 Camera needs 4 requests, can't test only 1
11643 11:13:21.360616 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11644 11:13:21.458268
11645 11:13:21.566145 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (58 ms)
11646 11:13:21.675066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11647 11:13:21.675917 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11649 11:13:21.691477 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11650 11:13:21.757383 Camera needs 4 requests, can't test only 2
11651 11:13:21.853923 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11652 11:13:21.954264
11653 11:13:22.057051 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11654 11:13:22.162055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11655 11:13:22.162340 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11657 11:13:22.175839 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11658 11:13:22.232325 Camera needs 4 requests, can't test only 3
11659 11:13:22.329513 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11660 11:13:22.427961
11661 11:13:22.540608 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11662 11:13:22.660292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11663 11:13:22.660971 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11665 11:13:22.678719 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11666 11:13:23.295203 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2082 ms)
11667 11:13:23.305168 [0:04:17.731252169] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11668 11:13:23.407718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11669 11:13:23.408455 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11671 11:13:23.425635 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11672 11:13:26.007314 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2712 ms)
11673 11:13:26.016847 [0:04:20.444495784] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11674 11:13:26.110172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11675 11:13:26.110479 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11677 11:13:26.122957 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11678 11:13:29.768863 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3762 ms)
11679 11:13:29.778717 [0:04:24.206805554] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11680 11:13:29.873595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11681 11:13:29.873901 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11683 11:13:29.887630 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11684 11:13:35.210940 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5442 ms)
11685 11:13:35.220495 [0:04:29.649034323] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11686 11:13:35.319955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11687 11:13:35.320658 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11689 11:13:35.335844 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11690 11:13:43.384974 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8175 ms)
11691 11:13:43.395164 [0:04:37.823970939] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11692 11:13:43.509816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11693 11:13:43.510488 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11695 11:13:43.527173 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11696 11:13:55.966658 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12583 ms)
11697 11:13:55.976792 [0:04:50.407709863] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11698 11:13:56.076897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11699 11:13:56.077189 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11701 11:13:56.092033 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11702 11:14:15.689274 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19724 ms)
11703 11:14:15.699540 [0:05:10.132702402] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11704 11:14:15.790950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11705 11:14:15.791242 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11707 11:14:15.804706 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11708 11:14:16.104407 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (418 ms)
11709 11:14:16.117538 [0:05:10.550752095] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11710 11:14:16.202173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11711 11:14:16.202455 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11713 11:14:16.218085 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11714 11:14:16.594095 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (489 ms)
11715 11:14:16.607305 [0:05:11.040306479] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11716 11:14:16.697831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11717 11:14:16.698116 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11719 11:14:16.714718 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11720 11:14:17.151372 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11721 11:14:17.164699 [0:05:11.598336326] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11722 11:14:17.248306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11723 11:14:17.248587 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11725 11:14:17.264301 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11726 11:14:17.849453 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (697 ms)
11727 11:14:17.862420 [0:05:12.296039326] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11728 11:14:17.957073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11729 11:14:17.957356 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11731 11:14:17.974238 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11732 11:14:18.758393 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (908 ms)
11733 11:14:18.771027 [0:05:13.205096018] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11734 11:14:18.859900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11735 11:14:18.860176 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11737 11:14:18.877446 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11738 11:14:20.016689 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1258 ms)
11739 11:14:20.029693 [0:05:14.463182172] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11740 11:14:20.124287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11741 11:14:20.124564 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11743 11:14:20.141528 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11744 11:14:21.834459 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1817 ms)
11745 11:14:21.847207 [0:05:16.281363864] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11746 11:14:21.945560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11747 11:14:21.945837 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11749 11:14:21.962338 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11750 11:14:24.562248 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2728 ms)
11751 11:14:24.575199 [0:05:19.009919864] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11752 11:14:24.666541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11753 11:14:24.666817 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11755 11:14:24.683185 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11756 11:14:28.761900 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4199 ms)
11757 11:14:28.774495 [0:05:23.209058172] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11758 11:14:28.881556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11759 11:14:28.882253 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11761 11:14:28.900584 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11762 11:14:35.339713 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6578 ms)
11763 11:14:35.352838 [0:05:29.787886634] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11764 11:14:35.454689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11765 11:14:35.455384 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11767 11:14:35.473849 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11768 11:14:35.760389 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (417 ms)
11769 11:14:35.769894 [0:05:30.205422404] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11770 11:14:35.877836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11771 11:14:35.878524 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11773 11:14:35.893829 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11774 11:14:36.248498 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (487 ms)
11775 11:14:36.257925 [0:05:30.692583557] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11776 11:14:36.356599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11777 11:14:36.357521 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11779 11:14:36.372360 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11780 11:14:36.805371 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (556 ms)
11781 11:14:36.814977 [0:05:31.249616250] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11782 11:14:36.921473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11783 11:14:36.922151 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11785 11:14:36.937115 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11786 11:14:37.502167 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (697 ms)
11787 11:14:37.512187 [0:05:31.947225788] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11788 11:14:37.617674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11789 11:14:37.618356 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11791 11:14:37.633925 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11792 11:14:38.411221 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (909 ms)
11793 11:14:38.420748 [0:05:32.856827481] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11794 11:14:38.517643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11795 11:14:38.517927 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11797 11:14:38.531385 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11798 11:14:39.668825 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1257 ms)
11799 11:14:39.678274 [0:05:34.113994788] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11800 11:14:39.778642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11801 11:14:39.779001 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11803 11:14:39.793030 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11804 11:14:41.486956 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1818 ms)
11805 11:14:41.496856 [0:05:35.932868942] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11806 11:14:41.586591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11807 11:14:41.586874 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11809 11:14:41.599603 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11810 11:14:44.216682 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2730 ms)
11811 11:14:44.226638 [0:05:38.663189020] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11812 11:14:44.319049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11813 11:14:44.319335 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11815 11:14:44.332619 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11816 11:14:48.415638 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4198 ms)
11817 11:14:48.425239 [0:05:42.862121712] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11818 11:14:48.532372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11819 11:14:48.533250 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11821 11:14:48.548554 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11822 11:14:54.993810 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6579 ms)
11823 11:14:55.003954 [0:05:49.441570789] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11824 11:14:55.097356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11825 11:14:55.097644 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11827 11:14:55.110631 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11828 11:14:55.412231 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (418 ms)
11829 11:14:55.422012 [0:05:49.859733559] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11830 11:14:55.506776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11831 11:14:55.507053 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11833 11:14:55.518989 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11834 11:14:55.900950 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (488 ms)
11835 11:14:55.911000 [0:05:50.347153636] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11836 11:14:55.996032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11837 11:14:55.996322 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11839 11:14:56.008823 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11840 11:14:56.456250 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (554 ms)
11841 11:14:56.465735 [0:05:50.902018943] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11842 11:14:56.549418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11843 11:14:56.549691 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11845 11:14:56.560885 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11846 11:14:57.151048 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (694 ms)
11847 11:14:57.160794 [0:05:51.596642636] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11848 11:14:57.253560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11849 11:14:57.253871 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11851 11:14:57.265324 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11852 11:14:58.056571 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (906 ms)
11853 11:14:58.066602 [0:05:52.503227713] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11854 11:14:58.149916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11855 11:14:58.150196 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11857 11:14:58.162723 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11858 11:14:59.312807 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1255 ms)
11859 11:14:59.322499 [0:05:53.758363328] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11860 11:14:59.412583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11861 11:14:59.413265 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11863 11:14:59.427566 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11864 11:15:01.126004 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1813 ms)
11865 11:15:01.135689 [0:05:55.572456482] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11866 11:15:01.227683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11867 11:15:01.228385 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11869 11:15:01.242317 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11870 11:15:03.853220 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2727 ms)
11871 11:15:03.863323 [0:05:58.299841021] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11872 11:15:03.965098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11873 11:15:03.965765 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11875 11:15:03.981119 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11876 11:15:08.048214 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4195 ms)
11877 11:15:08.058115 [0:06:02.495527636] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11878 11:15:08.150031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11879 11:15:08.150692 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11881 11:15:08.166504 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11882 11:15:14.623650 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6575 ms)
11883 11:15:14.633722 [0:06:09.071341637] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11884 11:15:14.730246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11885 11:15:14.730898 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11887 11:15:14.745561 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11888 11:15:15.038431 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (414 ms)
11889 11:15:15.047994 [0:06:09.486172329] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11890 11:15:15.143380 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11892 11:15:15.146194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11893 11:15:15.161611 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11894 11:15:15.523532 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (485 ms)
11895 11:15:15.533222 [0:06:09.971274868] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11896 11:15:15.632761 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11898 11:15:15.635531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11899 11:15:15.651290 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11900 11:15:16.078071 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (554 ms)
11901 11:15:16.088349 [0:06:10.526333637] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11902 11:15:16.186873 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11904 11:15:16.189827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11905 11:15:16.205014 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11906 11:15:16.773647 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (694 ms)
11907 11:15:16.782890 [0:06:11.221101252] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11908 11:15:16.883546 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11910 11:15:16.886400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11911 11:15:16.901135 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11912 11:15:17.678601 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (905 ms)
11913 11:15:17.688445 [0:06:12.126792252] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11914 11:15:17.779959 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11916 11:15:17.782724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11917 11:15:17.796272 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11918 11:15:18.933551 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1254 ms)
11919 11:15:18.943210 [0:06:13.381600714] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11920 11:15:19.039068 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11922 11:15:19.041445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11923 11:15:19.055063 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11924 11:15:20.748044 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1814 ms)
11925 11:15:20.758073 [0:06:15.196340406] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11926 11:15:20.842524 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11928 11:15:20.845429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11929 11:15:20.861150 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11930 11:15:23.472863 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2725 ms)
11931 11:15:23.483152 [0:06:17.922243253] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11932 11:15:23.587031 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11934 11:15:23.589921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11935 11:15:23.605476 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11936 11:15:27.668296 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4195 ms)
11937 11:15:27.677672 [0:06:22.117362868] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11938 11:15:27.776077 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11940 11:15:27.778966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11941 11:15:27.793095 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11942 11:15:34.243899 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6576 ms)
11943 11:15:34.326373 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11945 11:15:34.329231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11946 11:15:34.340814 [----------] 120 tests from CaptureTests/SingleStream (370107 ms total)
11947 11:15:34.413375
11948 11:15:34.485545 [----------] Global test environment tear-down
11949 11:15:34.555488 [==========] 120 tests from 1 test suite ran. (370107 ms total)
11950 11:15:34.630958 <LAVA_SIGNAL_TESTSET STOP>
11951 11:15:34.631260 Received signal: <TESTSET> STOP
11952 11:15:34.631324 Closing test_set CaptureTests/SingleStream
11953 11:15:34.634232 + set +x
11954 11:15:34.637445 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14786847_1.6.2.3.1>
11955 11:15:34.637687 Received signal: <ENDRUN> 0_lc-compliance 14786847_1.6.2.3.1
11956 11:15:34.637762 Ending use of test pattern.
11957 11:15:34.637817 Ending test lava.0_lc-compliance (14786847_1.6.2.3.1), duration 372.17
11959 11:15:34.640719 <LAVA_TEST_RUNNER EXIT>
11960 11:15:34.640961 ok: lava_test_shell seems to have completed
11961 11:15:34.642641 Capture/Raw_1:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_2:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_3:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_5:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_8:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_13:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_21:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_34:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_55:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_89:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
11962 11:15:34.642836 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11963 11:15:34.642924 end: 3 lava-test-retry (duration 00:06:13) [common]
11964 11:15:34.643004 start: 4 finalize (timeout 00:10:00) [common]
11965 11:15:34.643093 start: 4.1 power-off (timeout 00:00:30) [common]
11966 11:15:34.643214 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11967 11:15:36.718511 >> Command sent successfully.
11968 11:15:36.736609 Returned 0 in 2 seconds
11969 11:15:36.737131 end: 4.1 power-off (duration 00:00:02) [common]
11971 11:15:36.737896 start: 4.2 read-feedback (timeout 00:09:58) [common]
11972 11:15:36.738379 Listened to connection for namespace 'common' for up to 1s
11973 11:15:37.739370 Finalising connection for namespace 'common'
11974 11:15:37.739569 Disconnecting from shell: Finalise
11975 11:15:37.739654 / #
11976 11:15:37.839943 end: 4.2 read-feedback (duration 00:00:01) [common]
11977 11:15:37.840091 end: 4 finalize (duration 00:00:03) [common]
11978 11:15:37.840233 Cleaning after the job
11979 11:15:37.840360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/ramdisk
11980 11:15:37.843179 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/kernel
11981 11:15:37.853772 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/dtb
11982 11:15:37.853938 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/nfsrootfs
11983 11:15:37.894919 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786847/tftp-deploy-d2dascnn/modules
11984 11:15:37.900635 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786847
11985 11:15:38.149260 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786847
11986 11:15:38.149425 Job finished correctly