Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 11:06:44.122778 lava-dispatcher, installed at version: 2024.05
2 11:06:44.122980 start: 0 validate
3 11:06:44.123094 Start time: 2024-07-10 11:06:44.123089+00:00 (UTC)
4 11:06:44.123221 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:06:44.123363 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:06:44.421297 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:06:44.421763 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:06:54.238110 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:06:54.238281 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:06:54.503306 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:06:54.503452 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:06:54.771006 validate duration: 10.65
14 11:06:54.771244 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:06:54.771337 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:06:54.771416 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:06:54.771587 Not decompressing ramdisk as can be used compressed.
18 11:06:54.771696 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 11:06:54.771760 saving as /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/ramdisk/rootfs.cpio.gz
20 11:06:54.771853 total size: 28105535 (26 MB)
21 11:06:54.772806 progress 0 % (0 MB)
22 11:06:54.779926 progress 5 % (1 MB)
23 11:06:54.787020 progress 10 % (2 MB)
24 11:06:54.793882 progress 15 % (4 MB)
25 11:06:54.800791 progress 20 % (5 MB)
26 11:06:54.807727 progress 25 % (6 MB)
27 11:06:54.815069 progress 30 % (8 MB)
28 11:06:54.822164 progress 35 % (9 MB)
29 11:06:54.829243 progress 40 % (10 MB)
30 11:06:54.836088 progress 45 % (12 MB)
31 11:06:54.843231 progress 50 % (13 MB)
32 11:06:54.850461 progress 55 % (14 MB)
33 11:06:54.857856 progress 60 % (16 MB)
34 11:06:54.865064 progress 65 % (17 MB)
35 11:06:54.872058 progress 70 % (18 MB)
36 11:06:54.878964 progress 75 % (20 MB)
37 11:06:54.885850 progress 80 % (21 MB)
38 11:06:54.892787 progress 85 % (22 MB)
39 11:06:54.899760 progress 90 % (24 MB)
40 11:06:54.906932 progress 95 % (25 MB)
41 11:06:54.914229 progress 100 % (26 MB)
42 11:06:54.914499 26 MB downloaded in 0.14 s (187.91 MB/s)
43 11:06:54.914650 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:06:54.914866 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:06:54.914943 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:06:54.915054 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:06:54.915194 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:06:54.915255 saving as /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/kernel/Image
50 11:06:54.915308 total size: 54813184 (52 MB)
51 11:06:54.915362 No compression specified
52 11:06:54.916427 progress 0 % (0 MB)
53 11:06:54.929700 progress 5 % (2 MB)
54 11:06:54.943196 progress 10 % (5 MB)
55 11:06:54.956532 progress 15 % (7 MB)
56 11:06:54.970335 progress 20 % (10 MB)
57 11:06:54.984268 progress 25 % (13 MB)
58 11:06:54.997712 progress 30 % (15 MB)
59 11:06:55.011318 progress 35 % (18 MB)
60 11:06:55.025290 progress 40 % (20 MB)
61 11:06:55.038898 progress 45 % (23 MB)
62 11:06:55.052457 progress 50 % (26 MB)
63 11:06:55.066253 progress 55 % (28 MB)
64 11:06:55.079678 progress 60 % (31 MB)
65 11:06:55.093353 progress 65 % (34 MB)
66 11:06:55.106805 progress 70 % (36 MB)
67 11:06:55.120406 progress 75 % (39 MB)
68 11:06:55.133817 progress 80 % (41 MB)
69 11:06:55.147179 progress 85 % (44 MB)
70 11:06:55.160513 progress 90 % (47 MB)
71 11:06:55.173920 progress 95 % (49 MB)
72 11:06:55.187287 progress 100 % (52 MB)
73 11:06:55.187513 52 MB downloaded in 0.27 s (192.04 MB/s)
74 11:06:55.187660 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:06:55.187873 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:06:55.187955 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:06:55.188031 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:06:55.188160 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:06:55.188221 saving as /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/dtb/mt8192-asurada-spherion-r0.dtb
81 11:06:55.188275 total size: 47258 (0 MB)
82 11:06:55.188328 No compression specified
83 11:06:55.189297 progress 69 % (0 MB)
84 11:06:55.189553 progress 100 % (0 MB)
85 11:06:55.189698 0 MB downloaded in 0.00 s (31.71 MB/s)
86 11:06:55.189826 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:06:55.190108 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:06:55.190185 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:06:55.190260 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:06:55.190366 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:06:55.190428 saving as /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/modules/modules.tar
93 11:06:55.190481 total size: 8607984 (8 MB)
94 11:06:55.190536 Using unxz to decompress xz
95 11:06:55.191794 progress 0 % (0 MB)
96 11:06:55.213402 progress 5 % (0 MB)
97 11:06:55.240341 progress 10 % (0 MB)
98 11:06:55.266641 progress 15 % (1 MB)
99 11:06:55.292388 progress 20 % (1 MB)
100 11:06:55.316070 progress 25 % (2 MB)
101 11:06:55.341526 progress 30 % (2 MB)
102 11:06:55.365838 progress 35 % (2 MB)
103 11:06:55.394582 progress 40 % (3 MB)
104 11:06:55.421201 progress 45 % (3 MB)
105 11:06:55.447102 progress 50 % (4 MB)
106 11:06:55.473704 progress 55 % (4 MB)
107 11:06:55.500353 progress 60 % (4 MB)
108 11:06:55.526589 progress 65 % (5 MB)
109 11:06:55.554747 progress 70 % (5 MB)
110 11:06:55.585215 progress 75 % (6 MB)
111 11:06:55.615066 progress 80 % (6 MB)
112 11:06:55.640164 progress 85 % (7 MB)
113 11:06:55.664977 progress 90 % (7 MB)
114 11:06:55.689627 progress 95 % (7 MB)
115 11:06:55.713762 progress 100 % (8 MB)
116 11:06:55.719317 8 MB downloaded in 0.53 s (15.52 MB/s)
117 11:06:55.719525 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:06:55.719874 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:06:55.719986 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:06:55.720092 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:06:55.720196 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:06:55.720297 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:06:55.720502 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0
125 11:06:55.720649 makedir: /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin
126 11:06:55.720772 makedir: /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/tests
127 11:06:55.720892 makedir: /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/results
128 11:06:55.721012 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-add-keys
129 11:06:55.721172 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-add-sources
130 11:06:55.721302 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-background-process-start
131 11:06:55.721424 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-background-process-stop
132 11:06:55.721561 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-common-functions
133 11:06:55.721709 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-echo-ipv4
134 11:06:55.721856 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-install-packages
135 11:06:55.722012 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-installed-packages
136 11:06:55.722142 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-os-build
137 11:06:55.722262 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-probe-channel
138 11:06:55.722377 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-probe-ip
139 11:06:55.722498 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-target-ip
140 11:06:55.722646 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-target-mac
141 11:06:55.722788 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-target-storage
142 11:06:55.722937 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-test-case
143 11:06:55.723079 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-test-event
144 11:06:55.723226 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-test-feedback
145 11:06:55.723375 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-test-raise
146 11:06:55.723522 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-test-reference
147 11:06:55.723666 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-test-runner
148 11:06:55.723808 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-test-set
149 11:06:55.723951 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-test-shell
150 11:06:55.724094 Updating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-install-packages (oe)
151 11:06:55.724265 Updating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/bin/lava-installed-packages (oe)
152 11:06:55.724404 Creating /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/environment
153 11:06:55.724522 LAVA metadata
154 11:06:55.724613 - LAVA_JOB_ID=14786851
155 11:06:55.724701 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:06:55.724822 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:06:55.724906 skipped lava-vland-overlay
158 11:06:55.725002 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:06:55.725101 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:06:55.725181 skipped lava-multinode-overlay
161 11:06:55.725257 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:06:55.725328 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:06:55.725398 Loading test definitions
164 11:06:55.725474 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:06:55.725566 Using /lava-14786851 at stage 0
166 11:06:55.725965 uuid=14786851_1.5.2.3.1 testdef=None
167 11:06:55.726069 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:06:55.726151 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:06:55.726586 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:06:55.726790 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:06:55.727365 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:06:55.727629 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:06:55.728435 runner path: /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14786851_1.5.2.3.1
176 11:06:55.728612 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:06:55.728931 Creating lava-test-runner.conf files
179 11:06:55.729020 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786851/lava-overlay-509x68f0/lava-14786851/0 for stage 0
180 11:06:55.729133 - 0_v4l2-compliance-mtk-vcodec-enc
181 11:06:55.729228 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:06:55.729305 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:06:55.736941 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:06:55.737066 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:06:55.737167 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:06:55.737246 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:06:55.737329 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:06:56.529490 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:06:56.529655 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:06:56.529757 extracting modules file /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786851/extract-overlay-ramdisk-kkx4l9d9/ramdisk
191 11:06:56.812096 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:06:56.812231 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:06:56.812322 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786851/compress-overlay-um5h9e2t/overlay-1.5.2.4.tar.gz to ramdisk
194 11:06:56.812382 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786851/compress-overlay-um5h9e2t/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786851/extract-overlay-ramdisk-kkx4l9d9/ramdisk
195 11:06:56.819011 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:06:56.819105 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:06:56.819185 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:06:56.819266 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:06:56.819339 Building ramdisk /var/lib/lava/dispatcher/tmp/14786851/extract-overlay-ramdisk-kkx4l9d9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786851/extract-overlay-ramdisk-kkx4l9d9/ramdisk
200 11:06:57.405810 >> 275391 blocks
201 11:07:01.598527 rename /var/lib/lava/dispatcher/tmp/14786851/extract-overlay-ramdisk-kkx4l9d9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/ramdisk/ramdisk.cpio.gz
202 11:07:01.598696 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:07:01.598790 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:07:01.598868 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:07:01.598944 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/kernel/Image']
206 11:07:15.027909 Returned 0 in 13 seconds
207 11:07:15.028078 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/kernel/image.itb
208 11:07:15.627989 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:07:15.628196 output: Created: Wed Jul 10 12:07:15 2024
210 11:07:15.628320 output: Image 0 (kernel-1)
211 11:07:15.628437 output: Description:
212 11:07:15.628549 output: Created: Wed Jul 10 12:07:15 2024
213 11:07:15.628659 output: Type: Kernel Image
214 11:07:15.628769 output: Compression: lzma compressed
215 11:07:15.628880 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
216 11:07:15.628988 output: Architecture: AArch64
217 11:07:15.629096 output: OS: Linux
218 11:07:15.629203 output: Load Address: 0x00000000
219 11:07:15.629309 output: Entry Point: 0x00000000
220 11:07:15.629414 output: Hash algo: crc32
221 11:07:15.629519 output: Hash value: 9bb85fb9
222 11:07:15.629626 output: Image 1 (fdt-1)
223 11:07:15.629746 output: Description: mt8192-asurada-spherion-r0
224 11:07:15.629878 output: Created: Wed Jul 10 12:07:15 2024
225 11:07:15.629986 output: Type: Flat Device Tree
226 11:07:15.630120 output: Compression: uncompressed
227 11:07:15.630227 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:07:15.630330 output: Architecture: AArch64
229 11:07:15.630408 output: Hash algo: crc32
230 11:07:15.630484 output: Hash value: 0f8e4d2e
231 11:07:15.630558 output: Image 2 (ramdisk-1)
232 11:07:15.630632 output: Description: unavailable
233 11:07:15.630705 output: Created: Wed Jul 10 12:07:15 2024
234 11:07:15.630780 output: Type: RAMDisk Image
235 11:07:15.630853 output: Compression: uncompressed
236 11:07:15.630933 output: Data Size: 41181828 Bytes = 40216.63 KiB = 39.27 MiB
237 11:07:15.631049 output: Architecture: AArch64
238 11:07:15.631122 output: OS: Linux
239 11:07:15.631196 output: Load Address: unavailable
240 11:07:15.631270 output: Entry Point: unavailable
241 11:07:15.631344 output: Hash algo: crc32
242 11:07:15.631418 output: Hash value: 76ee5170
243 11:07:15.631491 output: Default Configuration: 'conf-1'
244 11:07:15.631565 output: Configuration 0 (conf-1)
245 11:07:15.631639 output: Description: mt8192-asurada-spherion-r0
246 11:07:15.631732 output: Kernel: kernel-1
247 11:07:15.631920 output: Init Ramdisk: ramdisk-1
248 11:07:15.632062 output: FDT: fdt-1
249 11:07:15.632196 output: Loadables: kernel-1
250 11:07:15.632279 output:
251 11:07:15.632421 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:07:15.632530 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:07:15.632641 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:07:15.632751 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:07:15.632838 No LXC device requested
256 11:07:15.632947 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:07:15.633054 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:07:15.633158 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:07:15.633241 Checking files for TFTP limit of 4294967296 bytes.
260 11:07:15.633778 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:07:15.633897 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:07:15.634018 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:07:15.634186 substitutions:
264 11:07:15.634274 - {DTB}: 14786851/tftp-deploy-spy6iyge/dtb/mt8192-asurada-spherion-r0.dtb
265 11:07:15.634365 - {INITRD}: 14786851/tftp-deploy-spy6iyge/ramdisk/ramdisk.cpio.gz
266 11:07:15.634453 - {KERNEL}: 14786851/tftp-deploy-spy6iyge/kernel/Image
267 11:07:15.634539 - {LAVA_MAC}: None
268 11:07:15.634625 - {PRESEED_CONFIG}: None
269 11:07:15.634710 - {PRESEED_LOCAL}: None
270 11:07:15.634794 - {RAMDISK}: 14786851/tftp-deploy-spy6iyge/ramdisk/ramdisk.cpio.gz
271 11:07:15.634894 - {ROOT_PART}: None
272 11:07:15.634979 - {ROOT}: None
273 11:07:15.635062 - {SERVER_IP}: 192.168.201.1
274 11:07:15.635145 - {TEE}: None
275 11:07:15.635229 Parsed boot commands:
276 11:07:15.635315 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:07:15.635504 Parsed boot commands: tftpboot 192.168.201.1 14786851/tftp-deploy-spy6iyge/kernel/image.itb 14786851/tftp-deploy-spy6iyge/kernel/cmdline
278 11:07:15.635613 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:07:15.635733 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:07:15.635841 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:07:15.635957 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:07:15.636041 Not connected, no need to disconnect.
283 11:07:15.636188 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:07:15.636272 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:07:15.636357 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 11:07:15.639483 Setting prompt string to ['lava-test: # ']
287 11:07:15.639814 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:07:15.639945 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:07:15.640065 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:07:15.640179 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:07:15.640478 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 11:07:24.781747 >> Command sent successfully.
293 11:07:24.795817 Returned 0 in 9 seconds
294 11:07:24.796412 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:07:24.797451 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:07:24.797889 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:07:24.798278 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:07:24.798590 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:07:24.798907 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:07:24.800476 [Enter `^Ec?' for help]
302 11:07:26.392353
303 11:07:26.392875
304 11:07:26.393228 F0: 102B 0000
305 11:07:26.393554
306 11:07:26.393841 F3: 1001 0000 [0200]
307 11:07:26.396120
308 11:07:26.396597 F3: 1001 0000
309 11:07:26.396928
310 11:07:26.397227 F7: 102D 0000
311 11:07:26.397520
312 11:07:26.400140 F1: 0000 0000
313 11:07:26.400652
314 11:07:26.400976 V0: 0000 0000 [0001]
315 11:07:26.401271
316 11:07:26.401553 00: 0007 8000
317 11:07:26.401840
318 11:07:26.404132 01: 0000 0000
319 11:07:26.404677
320 11:07:26.405006 BP: 0C00 0209 [0000]
321 11:07:26.405303
322 11:07:26.405588 G0: 1182 0000
323 11:07:26.407636
324 11:07:26.408050 EC: 0000 0021 [4000]
325 11:07:26.408374
326 11:07:26.411818 S7: 0000 0000 [0000]
327 11:07:26.412236
328 11:07:26.412558 CC: 0000 0000 [0001]
329 11:07:26.412859
330 11:07:26.414658 T0: 0000 0040 [010F]
331 11:07:26.415083
332 11:07:26.415419 Jump to BL
333 11:07:26.415721
334 11:07:26.439801
335 11:07:26.440296
336 11:07:26.447737 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:07:26.450794 ARM64: Exception handlers installed.
338 11:07:26.454659 ARM64: Testing exception
339 11:07:26.455086 ARM64: Done test exception
340 11:07:26.462111 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:07:26.473083 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:07:26.479678 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:07:26.490372 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:07:26.496774 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:07:26.507336 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:07:26.517659 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:07:26.524235 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:07:26.542177 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:07:26.545643 WDT: Last reset was cold boot
350 11:07:26.548779 SPI1(PAD0) initialized at 2873684 Hz
351 11:07:26.552557 SPI5(PAD0) initialized at 992727 Hz
352 11:07:26.555622 VBOOT: Loading verstage.
353 11:07:26.562177 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:07:26.565537 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:07:26.569138 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:07:26.572184 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:07:26.579775 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:07:26.586370 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:07:26.597364 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 11:07:26.597758
361 11:07:26.598085
362 11:07:26.607661 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:07:26.610703 ARM64: Exception handlers installed.
364 11:07:26.614258 ARM64: Testing exception
365 11:07:26.614650 ARM64: Done test exception
366 11:07:26.620575 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:07:26.623900 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:07:26.638241 Probing TPM: . done!
369 11:07:26.638751 TPM ready after 0 ms
370 11:07:26.645551 Connected to device vid:did:rid of 1ae0:0028:00
371 11:07:26.652101 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 11:07:26.691876 Initialized TPM device CR50 revision 0
373 11:07:26.703746 tlcl_send_startup: Startup return code is 0
374 11:07:26.704144 TPM: setup succeeded
375 11:07:26.715257 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:07:26.723997 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:07:26.734387 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:07:26.742934 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:07:26.746490 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:07:26.749737 in-header: 03 07 00 00 08 00 00 00
381 11:07:26.753162 in-data: aa e4 47 04 13 02 00 00
382 11:07:26.756412 Chrome EC: UHEPI supported
383 11:07:26.763103 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:07:26.766550 in-header: 03 a9 00 00 08 00 00 00
385 11:07:26.769549 in-data: 84 60 60 08 00 00 00 00
386 11:07:26.773197 Phase 1
387 11:07:26.776694 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:07:26.783399 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:07:26.786377 VB2:vb2_check_recovery() Recovery was requested manually
390 11:07:26.793396 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:07:26.797270 Recovery requested (1009000e)
392 11:07:26.802976 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:07:26.808125 tlcl_extend: response is 0
394 11:07:26.815978 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:07:26.822086 tlcl_extend: response is 0
396 11:07:26.828489 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:07:26.849113 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:07:26.855511 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:07:26.856030
400 11:07:26.856369
401 11:07:26.865304 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:07:26.868952 ARM64: Exception handlers installed.
403 11:07:26.872277 ARM64: Testing exception
404 11:07:26.872734 ARM64: Done test exception
405 11:07:26.894461 pmic_efuse_setting: Set efuses in 11 msecs
406 11:07:26.898527 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:07:26.901951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:07:26.909096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:07:26.912673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:07:26.919336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:07:26.923699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:07:26.926584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:07:26.934252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:07:26.937153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:07:26.940403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:07:26.946787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:07:26.951010 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:07:26.957131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:07:26.960016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:07:26.967572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:07:26.974094 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:07:26.977646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:07:26.983823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:07:26.990549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:07:26.993971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:07:27.000657 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:07:27.007812 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:07:27.010677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:07:27.017863 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:07:27.024253 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:07:27.027901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:07:27.033918 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:07:27.037298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:07:27.044388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:07:27.047503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:07:27.054163 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:07:27.057869 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:07:27.064248 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:07:27.067364 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:07:27.074961 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:07:27.077720 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:07:27.084570 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:07:27.088204 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:07:27.091592 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:07:27.098762 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:07:27.102173 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:07:27.106179 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:07:27.112467 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:07:27.115912 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:07:27.119058 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:07:27.125886 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:07:27.129649 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:07:27.132528 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:07:27.135879 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:07:27.142514 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:07:27.146360 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:07:27.149597 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:07:27.155795 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:07:27.165791 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:07:27.169570 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:07:27.179505 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:07:27.186234 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:07:27.192885 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:07:27.195898 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:07:27.198884 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:07:27.206768 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 11:07:27.214368 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:07:27.217772 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:07:27.220798 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:07:27.231866 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 11:07:27.241246 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 11:07:27.251012 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 11:07:27.260062 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 11:07:27.269169 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 11:07:27.279500 [RTC]rtc_get_frequency_meter,154: input=16, output=780
476 11:07:27.288750 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 11:07:27.292094 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:07:27.299109 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:07:27.302588 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:07:27.305993 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:07:27.312248 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:07:27.315912 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:07:27.319466 ADC[4]: Raw value=906203 ID=7
484 11:07:27.320025 ADC[3]: Raw value=213441 ID=1
485 11:07:27.322605 RAM Code: 0x71
486 11:07:27.325615 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:07:27.332792 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:07:27.339137 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:07:27.346196 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:07:27.349436 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:07:27.352980 in-header: 03 07 00 00 08 00 00 00
492 11:07:27.356641 in-data: aa e4 47 04 13 02 00 00
493 11:07:27.359620 Chrome EC: UHEPI supported
494 11:07:27.366196 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:07:27.370199 in-header: 03 a9 00 00 08 00 00 00
496 11:07:27.373088 in-data: 84 60 60 08 00 00 00 00
497 11:07:27.376314 MRC: failed to locate region type 0.
498 11:07:27.382879 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:07:27.386050 DRAM-K: Running full calibration
500 11:07:27.392430 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:07:27.392941 header.status = 0x0
502 11:07:27.396252 header.version = 0x6 (expected: 0x6)
503 11:07:27.399365 header.size = 0xd00 (expected: 0xd00)
504 11:07:27.402514 header.flags = 0x0
505 11:07:27.409483 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:07:27.426349 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 11:07:27.432246 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:07:27.435750 dram_init: ddr_geometry: 2
509 11:07:27.439125 [EMI] MDL number = 2
510 11:07:27.439649 [EMI] Get MDL freq = 0
511 11:07:27.441917 dram_init: ddr_type: 0
512 11:07:27.442493 is_discrete_lpddr4: 1
513 11:07:27.445660 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:07:27.446262
515 11:07:27.446788
516 11:07:27.449127 [Bian_co] ETT version 0.0.0.1
517 11:07:27.455792 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:07:27.456221
519 11:07:27.459005 dramc_set_vcore_voltage set vcore to 650000
520 11:07:27.459463 Read voltage for 800, 4
521 11:07:27.462782 Vio18 = 0
522 11:07:27.463229 Vcore = 650000
523 11:07:27.463682 Vdram = 0
524 11:07:27.465720 Vddq = 0
525 11:07:27.466250 Vmddr = 0
526 11:07:27.469137 dram_init: config_dvfs: 1
527 11:07:27.472549 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:07:27.479138 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:07:27.482413 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 11:07:27.485566 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 11:07:27.488888 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 11:07:27.492445 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 11:07:27.495777 MEM_TYPE=3, freq_sel=18
534 11:07:27.499131 sv_algorithm_assistance_LP4_1600
535 11:07:27.502568 ============ PULL DRAM RESETB DOWN ============
536 11:07:27.506047 ========== PULL DRAM RESETB DOWN end =========
537 11:07:27.511953 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:07:27.515267 ===================================
539 11:07:27.515395 LPDDR4 DRAM CONFIGURATION
540 11:07:27.518704 ===================================
541 11:07:27.522317 EX_ROW_EN[0] = 0x0
542 11:07:27.525309 EX_ROW_EN[1] = 0x0
543 11:07:27.525405 LP4Y_EN = 0x0
544 11:07:27.529369 WORK_FSP = 0x0
545 11:07:27.529455 WL = 0x2
546 11:07:27.532016 RL = 0x2
547 11:07:27.532103 BL = 0x2
548 11:07:27.535728 RPST = 0x0
549 11:07:27.535811 RD_PRE = 0x0
550 11:07:27.538969 WR_PRE = 0x1
551 11:07:27.539080 WR_PST = 0x0
552 11:07:27.542475 DBI_WR = 0x0
553 11:07:27.542552 DBI_RD = 0x0
554 11:07:27.545994 OTF = 0x1
555 11:07:27.548682 ===================================
556 11:07:27.552727 ===================================
557 11:07:27.552804 ANA top config
558 11:07:27.555872 ===================================
559 11:07:27.559043 DLL_ASYNC_EN = 0
560 11:07:27.562805 ALL_SLAVE_EN = 1
561 11:07:27.562902 NEW_RANK_MODE = 1
562 11:07:27.566928 DLL_IDLE_MODE = 1
563 11:07:27.570479 LP45_APHY_COMB_EN = 1
564 11:07:27.570557 TX_ODT_DIS = 1
565 11:07:27.574957 NEW_8X_MODE = 1
566 11:07:27.578810 ===================================
567 11:07:27.582571 ===================================
568 11:07:27.582652 data_rate = 1600
569 11:07:27.586023 CKR = 1
570 11:07:27.589966 DQ_P2S_RATIO = 8
571 11:07:27.593274 ===================================
572 11:07:27.596696 CA_P2S_RATIO = 8
573 11:07:27.596806 DQ_CA_OPEN = 0
574 11:07:27.600409 DQ_SEMI_OPEN = 0
575 11:07:27.604146 CA_SEMI_OPEN = 0
576 11:07:27.606731 CA_FULL_RATE = 0
577 11:07:27.610134 DQ_CKDIV4_EN = 1
578 11:07:27.610315 CA_CKDIV4_EN = 1
579 11:07:27.613502 CA_PREDIV_EN = 0
580 11:07:27.616689 PH8_DLY = 0
581 11:07:27.620909 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:07:27.623426 DQ_AAMCK_DIV = 4
583 11:07:27.627632 CA_AAMCK_DIV = 4
584 11:07:27.627707 CA_ADMCK_DIV = 4
585 11:07:27.629992 DQ_TRACK_CA_EN = 0
586 11:07:27.633331 CA_PICK = 800
587 11:07:27.637160 CA_MCKIO = 800
588 11:07:27.640042 MCKIO_SEMI = 0
589 11:07:27.643827 PLL_FREQ = 3068
590 11:07:27.646691 DQ_UI_PI_RATIO = 32
591 11:07:27.646767 CA_UI_PI_RATIO = 0
592 11:07:27.650086 ===================================
593 11:07:27.653787 ===================================
594 11:07:27.657141 memory_type:LPDDR4
595 11:07:27.660447 GP_NUM : 10
596 11:07:27.660522 SRAM_EN : 1
597 11:07:27.663804 MD32_EN : 0
598 11:07:27.667521 ===================================
599 11:07:27.670692 [ANA_INIT] >>>>>>>>>>>>>>
600 11:07:27.670769 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:07:27.677076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:07:27.677154 ===================================
603 11:07:27.680761 data_rate = 1600,PCW = 0X7600
604 11:07:27.683726 ===================================
605 11:07:27.687698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:07:27.693934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:07:27.701006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:07:27.704192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:07:27.707485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:07:27.710710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:07:27.713763 [ANA_INIT] flow start
612 11:07:27.713839 [ANA_INIT] PLL >>>>>>>>
613 11:07:27.717400 [ANA_INIT] PLL <<<<<<<<
614 11:07:27.720820 [ANA_INIT] MIDPI >>>>>>>>
615 11:07:27.720903 [ANA_INIT] MIDPI <<<<<<<<
616 11:07:27.724238 [ANA_INIT] DLL >>>>>>>>
617 11:07:27.727619 [ANA_INIT] flow end
618 11:07:27.730882 ============ LP4 DIFF to SE enter ============
619 11:07:27.734129 ============ LP4 DIFF to SE exit ============
620 11:07:27.737849 [ANA_INIT] <<<<<<<<<<<<<
621 11:07:27.740888 [Flow] Enable top DCM control >>>>>
622 11:07:27.744069 [Flow] Enable top DCM control <<<<<
623 11:07:27.747335 Enable DLL master slave shuffle
624 11:07:27.750585 ==============================================================
625 11:07:27.754233 Gating Mode config
626 11:07:27.757487 ==============================================================
627 11:07:27.761102 Config description:
628 11:07:27.771322 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:07:27.777484 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:07:27.780651 SELPH_MODE 0: By rank 1: By Phase
631 11:07:27.788020 ==============================================================
632 11:07:27.790845 GAT_TRACK_EN = 1
633 11:07:27.794016 RX_GATING_MODE = 2
634 11:07:27.797915 RX_GATING_TRACK_MODE = 2
635 11:07:27.801212 SELPH_MODE = 1
636 11:07:27.801288 PICG_EARLY_EN = 1
637 11:07:27.804155 VALID_LAT_VALUE = 1
638 11:07:27.811062 ==============================================================
639 11:07:27.814271 Enter into Gating configuration >>>>
640 11:07:27.817487 Exit from Gating configuration <<<<
641 11:07:27.821452 Enter into DVFS_PRE_config >>>>>
642 11:07:27.831263 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:07:27.834761 Exit from DVFS_PRE_config <<<<<
644 11:07:27.837514 Enter into PICG configuration >>>>
645 11:07:27.841700 Exit from PICG configuration <<<<
646 11:07:27.844528 [RX_INPUT] configuration >>>>>
647 11:07:27.847943 [RX_INPUT] configuration <<<<<
648 11:07:27.851453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:07:27.857828 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:07:27.864435 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:07:27.871185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:07:27.875225 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:07:27.881390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:07:27.884879 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:07:27.891329 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:07:27.894445 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:07:27.897979 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:07:27.901770 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:07:27.908196 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:07:27.911438 ===================================
661 11:07:27.911515 LPDDR4 DRAM CONFIGURATION
662 11:07:27.915006 ===================================
663 11:07:27.918051 EX_ROW_EN[0] = 0x0
664 11:07:27.921835 EX_ROW_EN[1] = 0x0
665 11:07:27.921911 LP4Y_EN = 0x0
666 11:07:27.925263 WORK_FSP = 0x0
667 11:07:27.925403 WL = 0x2
668 11:07:27.928270 RL = 0x2
669 11:07:27.928405 BL = 0x2
670 11:07:27.931898 RPST = 0x0
671 11:07:27.932037 RD_PRE = 0x0
672 11:07:27.934731 WR_PRE = 0x1
673 11:07:27.934849 WR_PST = 0x0
674 11:07:27.938339 DBI_WR = 0x0
675 11:07:27.938414 DBI_RD = 0x0
676 11:07:27.941837 OTF = 0x1
677 11:07:27.946252 ===================================
678 11:07:27.949672 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:07:27.952455 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:07:27.956195 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:07:27.959127 ===================================
682 11:07:27.962563 LPDDR4 DRAM CONFIGURATION
683 11:07:27.965524 ===================================
684 11:07:27.969172 EX_ROW_EN[0] = 0x10
685 11:07:27.969730 EX_ROW_EN[1] = 0x0
686 11:07:27.972764 LP4Y_EN = 0x0
687 11:07:27.973273 WORK_FSP = 0x0
688 11:07:27.975820 WL = 0x2
689 11:07:27.976250 RL = 0x2
690 11:07:27.978923 BL = 0x2
691 11:07:27.979431 RPST = 0x0
692 11:07:27.982483 RD_PRE = 0x0
693 11:07:27.982984 WR_PRE = 0x1
694 11:07:27.985880 WR_PST = 0x0
695 11:07:27.986337 DBI_WR = 0x0
696 11:07:27.988950 DBI_RD = 0x0
697 11:07:27.992547 OTF = 0x1
698 11:07:27.992977 ===================================
699 11:07:27.999023 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:07:28.004452 nWR fixed to 40
701 11:07:28.007057 [ModeRegInit_LP4] CH0 RK0
702 11:07:28.007593 [ModeRegInit_LP4] CH0 RK1
703 11:07:28.010336 [ModeRegInit_LP4] CH1 RK0
704 11:07:28.013438 [ModeRegInit_LP4] CH1 RK1
705 11:07:28.013847 match AC timing 13
706 11:07:28.020709 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:07:28.023678 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:07:28.026947 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:07:28.034113 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:07:28.037186 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:07:28.040382 [EMI DOE] emi_dcm 0
712 11:07:28.043606 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:07:28.044009 ==
714 11:07:28.046669 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:07:28.050337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:07:28.050558 ==
717 11:07:28.056627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:07:28.063428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:07:28.071094 [CA 0] Center 36 (6~67) winsize 62
720 11:07:28.074642 [CA 1] Center 36 (6~67) winsize 62
721 11:07:28.077578 [CA 2] Center 34 (4~65) winsize 62
722 11:07:28.081238 [CA 3] Center 33 (3~64) winsize 62
723 11:07:28.084285 [CA 4] Center 33 (3~63) winsize 61
724 11:07:28.088394 [CA 5] Center 32 (3~62) winsize 60
725 11:07:28.088491
726 11:07:28.092399 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:07:28.092478
728 11:07:28.095279 [CATrainingPosCal] consider 1 rank data
729 11:07:28.098199 u2DelayCellTimex100 = 270/100 ps
730 11:07:28.101786 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 11:07:28.105539 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 11:07:28.108435 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 11:07:28.112335 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 11:07:28.114995 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 11:07:28.121949 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 11:07:28.122081
737 11:07:28.124788 CA PerBit enable=1, Macro0, CA PI delay=32
738 11:07:28.124854
739 11:07:28.128747 [CBTSetCACLKResult] CA Dly = 32
740 11:07:28.128840 CS Dly: 5 (0~36)
741 11:07:28.128923 ==
742 11:07:28.132198 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:07:28.135303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:07:28.139109 ==
745 11:07:28.143126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:07:28.149869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:07:28.157510 [CA 0] Center 36 (6~67) winsize 62
748 11:07:28.161035 [CA 1] Center 36 (6~67) winsize 62
749 11:07:28.164274 [CA 2] Center 34 (3~65) winsize 63
750 11:07:28.168001 [CA 3] Center 33 (3~64) winsize 62
751 11:07:28.170718 [CA 4] Center 32 (2~63) winsize 62
752 11:07:28.174041 [CA 5] Center 32 (2~63) winsize 62
753 11:07:28.174242
754 11:07:28.177763 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 11:07:28.178039
756 11:07:28.180784 [CATrainingPosCal] consider 2 rank data
757 11:07:28.184478 u2DelayCellTimex100 = 270/100 ps
758 11:07:28.187537 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 11:07:28.190937 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 11:07:28.197892 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 11:07:28.201168 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 11:07:28.205066 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 11:07:28.207806 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 11:07:28.208277
765 11:07:28.211175 CA PerBit enable=1, Macro0, CA PI delay=32
766 11:07:28.211606
767 11:07:28.214518 [CBTSetCACLKResult] CA Dly = 32
768 11:07:28.215051 CS Dly: 5 (0~36)
769 11:07:28.215393
770 11:07:28.218891 ----->DramcWriteLeveling(PI) begin...
771 11:07:28.219412 ==
772 11:07:28.221830 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:07:28.228563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:07:28.229004 ==
775 11:07:28.231653 Write leveling (Byte 0): 33 => 33
776 11:07:28.234741 Write leveling (Byte 1): 31 => 31
777 11:07:28.235175 DramcWriteLeveling(PI) end<-----
778 11:07:28.235514
779 11:07:28.238428 ==
780 11:07:28.241704 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:07:28.244753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:07:28.245191 ==
783 11:07:28.247660 [Gating] SW mode calibration
784 11:07:28.254696 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:07:28.257888 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:07:28.264911 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:07:28.268456 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:07:28.271283 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 11:07:28.278493 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 11:07:28.282076 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:07:28.285124 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:07:28.288322 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:07:28.294615 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:07:28.298586 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:07:28.301944 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:07:28.308605 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:07:28.311440 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:07:28.315007 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:07:28.321352 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:07:28.325228 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:07:28.328272 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:07:28.335727 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 11:07:28.338478 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:07:28.342107 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
805 11:07:28.348367 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:07:28.351794 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:07:28.354793 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:07:28.361737 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:07:28.365173 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:07:28.368854 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:07:28.371598 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:07:28.378774 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
813 11:07:28.382259 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
814 11:07:28.385799 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:07:28.392076 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:07:28.395630 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:07:28.398282 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:07:28.405464 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:07:28.408521 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
820 11:07:28.411530 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 0) (1 1)
821 11:07:28.418624 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
822 11:07:28.422002 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:07:28.425450 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:07:28.431981 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:07:28.435136 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:07:28.438198 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:07:28.445665 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 11:07:28.448615 0 11 8 | B1->B0 | 2d2d 3b3b | 0 1 | (1 1) (0 0)
829 11:07:28.452525 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 11:07:28.455293 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:07:28.462089 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:07:28.465272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:07:28.468759 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:07:28.475584 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:07:28.478776 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:07:28.481860 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 11:07:28.488723 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:07:28.492166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:07:28.495606 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:07:28.501901 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:07:28.505618 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:07:28.509032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:07:28.515365 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:07:28.518891 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:07:28.522047 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:07:28.528774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:07:28.532126 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:07:28.535772 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:07:28.538781 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:07:28.545996 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:07:28.549126 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:07:28.552772 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 11:07:28.555534 Total UI for P1: 0, mck2ui 16
854 11:07:28.558947 best dqsien dly found for B0: ( 0, 14, 4)
855 11:07:28.565674 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 11:07:28.568965 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 11:07:28.572279 Total UI for P1: 0, mck2ui 16
858 11:07:28.575330 best dqsien dly found for B1: ( 0, 14, 10)
859 11:07:28.579060 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 11:07:28.582439 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 11:07:28.582942
862 11:07:28.586080 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 11:07:28.589365 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 11:07:28.592499 [Gating] SW calibration Done
865 11:07:28.593007 ==
866 11:07:28.595782 Dram Type= 6, Freq= 0, CH_0, rank 0
867 11:07:28.599062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 11:07:28.599494 ==
869 11:07:28.602323 RX Vref Scan: 0
870 11:07:28.602745
871 11:07:28.605564 RX Vref 0 -> 0, step: 1
872 11:07:28.605986
873 11:07:28.606378 RX Delay -130 -> 252, step: 16
874 11:07:28.612679 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
875 11:07:28.616494 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
876 11:07:28.619560 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 11:07:28.622419 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 11:07:28.626383 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 11:07:28.633027 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 11:07:28.636042 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 11:07:28.639200 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 11:07:28.642294 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 11:07:28.645964 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 11:07:28.653207 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
885 11:07:28.656010 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 11:07:28.659101 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
887 11:07:28.662818 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
888 11:07:28.665712 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 11:07:28.673804 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
890 11:07:28.674423 ==
891 11:07:28.675904 Dram Type= 6, Freq= 0, CH_0, rank 0
892 11:07:28.679543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 11:07:28.680049 ==
894 11:07:28.680382 DQS Delay:
895 11:07:28.682866 DQS0 = 0, DQS1 = 0
896 11:07:28.683374 DQM Delay:
897 11:07:28.686650 DQM0 = 90, DQM1 = 83
898 11:07:28.687158 DQ Delay:
899 11:07:28.690065 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 11:07:28.693349 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
901 11:07:28.696471 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
902 11:07:28.699831 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
903 11:07:28.700370
904 11:07:28.700843
905 11:07:28.701279 ==
906 11:07:28.702551 Dram Type= 6, Freq= 0, CH_0, rank 0
907 11:07:28.706199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 11:07:28.706710 ==
909 11:07:28.707047
910 11:07:28.709413
911 11:07:28.709877 TX Vref Scan disable
912 11:07:28.712531 == TX Byte 0 ==
913 11:07:28.716503 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 11:07:28.719548 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 11:07:28.723228 == TX Byte 1 ==
916 11:07:28.726733 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 11:07:28.729678 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 11:07:28.730213 ==
919 11:07:28.732678 Dram Type= 6, Freq= 0, CH_0, rank 0
920 11:07:28.736995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 11:07:28.739972 ==
922 11:07:28.751386 TX Vref=22, minBit 8, minWin=27, winSum=449
923 11:07:28.754749 TX Vref=24, minBit 8, minWin=27, winSum=453
924 11:07:28.758053 TX Vref=26, minBit 9, minWin=27, winSum=453
925 11:07:28.761457 TX Vref=28, minBit 8, minWin=27, winSum=454
926 11:07:28.764543 TX Vref=30, minBit 5, minWin=28, winSum=457
927 11:07:28.768116 TX Vref=32, minBit 5, minWin=28, winSum=455
928 11:07:28.774680 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
929 11:07:28.775187
930 11:07:28.778163 Final TX Range 1 Vref 30
931 11:07:28.778674
932 11:07:28.779010 ==
933 11:07:28.781142 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:07:28.784966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:07:28.785405 ==
936 11:07:28.785739
937 11:07:28.788010
938 11:07:28.788512 TX Vref Scan disable
939 11:07:28.791402 == TX Byte 0 ==
940 11:07:28.794960 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
941 11:07:28.798453 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
942 11:07:28.801000 == TX Byte 1 ==
943 11:07:28.804960 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 11:07:28.807885 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 11:07:28.808389
946 11:07:28.811139 [DATLAT]
947 11:07:28.811574 Freq=800, CH0 RK0
948 11:07:28.811913
949 11:07:28.814859 DATLAT Default: 0xa
950 11:07:28.815366 0, 0xFFFF, sum = 0
951 11:07:28.818207 1, 0xFFFF, sum = 0
952 11:07:28.818654 2, 0xFFFF, sum = 0
953 11:07:28.821569 3, 0xFFFF, sum = 0
954 11:07:28.822131 4, 0xFFFF, sum = 0
955 11:07:28.824803 5, 0xFFFF, sum = 0
956 11:07:28.825246 6, 0xFFFF, sum = 0
957 11:07:28.828391 7, 0xFFFF, sum = 0
958 11:07:28.828952 8, 0xFFFF, sum = 0
959 11:07:28.831635 9, 0x0, sum = 1
960 11:07:28.832150 10, 0x0, sum = 2
961 11:07:28.834947 11, 0x0, sum = 3
962 11:07:28.835468 12, 0x0, sum = 4
963 11:07:28.838673 best_step = 10
964 11:07:28.839194
965 11:07:28.839534 ==
966 11:07:28.841969 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:07:28.844992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 11:07:28.845427 ==
969 11:07:28.848009 RX Vref Scan: 1
970 11:07:28.848436
971 11:07:28.848767 Set Vref Range= 32 -> 127
972 11:07:28.849078
973 11:07:28.852108 RX Vref 32 -> 127, step: 1
974 11:07:28.852610
975 11:07:28.854712 RX Delay -95 -> 252, step: 8
976 11:07:28.855147
977 11:07:28.858708 Set Vref, RX VrefLevel [Byte0]: 32
978 11:07:28.861573 [Byte1]: 32
979 11:07:28.862039
980 11:07:28.865123 Set Vref, RX VrefLevel [Byte0]: 33
981 11:07:28.867973 [Byte1]: 33
982 11:07:28.871756
983 11:07:28.872189 Set Vref, RX VrefLevel [Byte0]: 34
984 11:07:28.874878 [Byte1]: 34
985 11:07:28.879486
986 11:07:28.879981 Set Vref, RX VrefLevel [Byte0]: 35
987 11:07:28.882580 [Byte1]: 35
988 11:07:28.886697
989 11:07:28.887125 Set Vref, RX VrefLevel [Byte0]: 36
990 11:07:28.889955 [Byte1]: 36
991 11:07:28.893540
992 11:07:28.893642 Set Vref, RX VrefLevel [Byte0]: 37
993 11:07:28.897235 [Byte1]: 37
994 11:07:28.901433
995 11:07:28.901510 Set Vref, RX VrefLevel [Byte0]: 38
996 11:07:28.904787 [Byte1]: 38
997 11:07:28.908940
998 11:07:28.909017 Set Vref, RX VrefLevel [Byte0]: 39
999 11:07:28.912012 [Byte1]: 39
1000 11:07:28.916402
1001 11:07:28.916478 Set Vref, RX VrefLevel [Byte0]: 40
1002 11:07:28.919736 [Byte1]: 40
1003 11:07:28.929295
1004 11:07:28.929372 Set Vref, RX VrefLevel [Byte0]: 41
1005 11:07:28.929432 [Byte1]: 41
1006 11:07:28.931950
1007 11:07:28.932029 Set Vref, RX VrefLevel [Byte0]: 42
1008 11:07:28.934881 [Byte1]: 42
1009 11:07:28.939823
1010 11:07:28.939915 Set Vref, RX VrefLevel [Byte0]: 43
1011 11:07:28.942769 [Byte1]: 43
1012 11:07:28.947323
1013 11:07:28.947400 Set Vref, RX VrefLevel [Byte0]: 44
1014 11:07:28.950343 [Byte1]: 44
1015 11:07:28.954671
1016 11:07:28.954758 Set Vref, RX VrefLevel [Byte0]: 45
1017 11:07:28.957662 [Byte1]: 45
1018 11:07:28.962631
1019 11:07:28.962717 Set Vref, RX VrefLevel [Byte0]: 46
1020 11:07:28.965373 [Byte1]: 46
1021 11:07:28.969961
1022 11:07:28.970082 Set Vref, RX VrefLevel [Byte0]: 47
1023 11:07:28.972951 [Byte1]: 47
1024 11:07:28.977827
1025 11:07:28.977904 Set Vref, RX VrefLevel [Byte0]: 48
1026 11:07:28.980410 [Byte1]: 48
1027 11:07:28.984988
1028 11:07:28.985064 Set Vref, RX VrefLevel [Byte0]: 49
1029 11:07:28.988124 [Byte1]: 49
1030 11:07:28.992572
1031 11:07:28.992649 Set Vref, RX VrefLevel [Byte0]: 50
1032 11:07:28.995939 [Byte1]: 50
1033 11:07:29.000522
1034 11:07:29.000623 Set Vref, RX VrefLevel [Byte0]: 51
1035 11:07:29.003440 [Byte1]: 51
1036 11:07:29.007824
1037 11:07:29.007900 Set Vref, RX VrefLevel [Byte0]: 52
1038 11:07:29.011235 [Byte1]: 52
1039 11:07:29.015620
1040 11:07:29.015697 Set Vref, RX VrefLevel [Byte0]: 53
1041 11:07:29.018430 [Byte1]: 53
1042 11:07:29.022825
1043 11:07:29.022917 Set Vref, RX VrefLevel [Byte0]: 54
1044 11:07:29.026223 [Byte1]: 54
1045 11:07:29.030259
1046 11:07:29.030337 Set Vref, RX VrefLevel [Byte0]: 55
1047 11:07:29.033967 [Byte1]: 55
1048 11:07:29.037845
1049 11:07:29.037921 Set Vref, RX VrefLevel [Byte0]: 56
1050 11:07:29.041487 [Byte1]: 56
1051 11:07:29.046039
1052 11:07:29.046116 Set Vref, RX VrefLevel [Byte0]: 57
1053 11:07:29.049126 [Byte1]: 57
1054 11:07:29.053165
1055 11:07:29.053241 Set Vref, RX VrefLevel [Byte0]: 58
1056 11:07:29.056716 [Byte1]: 58
1057 11:07:29.060827
1058 11:07:29.060905 Set Vref, RX VrefLevel [Byte0]: 59
1059 11:07:29.064543 [Byte1]: 59
1060 11:07:29.068506
1061 11:07:29.068650 Set Vref, RX VrefLevel [Byte0]: 60
1062 11:07:29.071662 [Byte1]: 60
1063 11:07:29.076186
1064 11:07:29.076294 Set Vref, RX VrefLevel [Byte0]: 61
1065 11:07:29.079304 [Byte1]: 61
1066 11:07:29.083537
1067 11:07:29.083614 Set Vref, RX VrefLevel [Byte0]: 62
1068 11:07:29.087218 [Byte1]: 62
1069 11:07:29.091492
1070 11:07:29.091567 Set Vref, RX VrefLevel [Byte0]: 63
1071 11:07:29.094328 [Byte1]: 63
1072 11:07:29.099543
1073 11:07:29.099618 Set Vref, RX VrefLevel [Byte0]: 64
1074 11:07:29.102409 [Byte1]: 64
1075 11:07:29.106676
1076 11:07:29.106751 Set Vref, RX VrefLevel [Byte0]: 65
1077 11:07:29.110249 [Byte1]: 65
1078 11:07:29.114351
1079 11:07:29.114426 Set Vref, RX VrefLevel [Byte0]: 66
1080 11:07:29.117802 [Byte1]: 66
1081 11:07:29.121805
1082 11:07:29.121881 Set Vref, RX VrefLevel [Byte0]: 67
1083 11:07:29.125052 [Byte1]: 67
1084 11:07:29.129689
1085 11:07:29.129764 Set Vref, RX VrefLevel [Byte0]: 68
1086 11:07:29.132877 [Byte1]: 68
1087 11:07:29.136704
1088 11:07:29.136779 Set Vref, RX VrefLevel [Byte0]: 69
1089 11:07:29.140299 [Byte1]: 69
1090 11:07:29.145141
1091 11:07:29.145306 Set Vref, RX VrefLevel [Byte0]: 70
1092 11:07:29.148070 [Byte1]: 70
1093 11:07:29.152412
1094 11:07:29.152575 Set Vref, RX VrefLevel [Byte0]: 71
1095 11:07:29.155224 [Byte1]: 71
1096 11:07:29.160290
1097 11:07:29.160464 Set Vref, RX VrefLevel [Byte0]: 72
1098 11:07:29.162794 [Byte1]: 72
1099 11:07:29.167329
1100 11:07:29.167552 Set Vref, RX VrefLevel [Byte0]: 73
1101 11:07:29.170405 [Byte1]: 73
1102 11:07:29.175054
1103 11:07:29.175220 Set Vref, RX VrefLevel [Byte0]: 74
1104 11:07:29.178347 [Byte1]: 74
1105 11:07:29.182292
1106 11:07:29.182491 Set Vref, RX VrefLevel [Byte0]: 75
1107 11:07:29.185638 [Byte1]: 75
1108 11:07:29.189881
1109 11:07:29.190121 Set Vref, RX VrefLevel [Byte0]: 76
1110 11:07:29.193682 [Byte1]: 76
1111 11:07:29.197784
1112 11:07:29.201125 Set Vref, RX VrefLevel [Byte0]: 77
1113 11:07:29.204423 [Byte1]: 77
1114 11:07:29.204590
1115 11:07:29.207656 Final RX Vref Byte 0 = 59 to rank0
1116 11:07:29.211486 Final RX Vref Byte 1 = 60 to rank0
1117 11:07:29.214074 Final RX Vref Byte 0 = 59 to rank1
1118 11:07:29.217865 Final RX Vref Byte 1 = 60 to rank1==
1119 11:07:29.221150 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 11:07:29.224543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 11:07:29.224900 ==
1122 11:07:29.225137 DQS Delay:
1123 11:07:29.227640 DQS0 = 0, DQS1 = 0
1124 11:07:29.227936 DQM Delay:
1125 11:07:29.230926 DQM0 = 92, DQM1 = 86
1126 11:07:29.231310 DQ Delay:
1127 11:07:29.234344 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1128 11:07:29.238102 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1129 11:07:29.241566 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1130 11:07:29.244904 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1131 11:07:29.245290
1132 11:07:29.245588
1133 11:07:29.251137 [DQSOSCAuto] RK0, (LSB)MR18= 0x544a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
1134 11:07:29.255057 CH0 RK0: MR19=606, MR18=544A
1135 11:07:29.261866 CH0_RK0: MR19=0x606, MR18=0x544A, DQSOSC=388, MR23=63, INC=98, DEC=65
1136 11:07:29.262299
1137 11:07:29.264984 ----->DramcWriteLeveling(PI) begin...
1138 11:07:29.265379 ==
1139 11:07:29.267872 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 11:07:29.271246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 11:07:29.271654 ==
1142 11:07:29.274667 Write leveling (Byte 0): 34 => 34
1143 11:07:29.278196 Write leveling (Byte 1): 27 => 27
1144 11:07:29.281386 DramcWriteLeveling(PI) end<-----
1145 11:07:29.281785
1146 11:07:29.282122 ==
1147 11:07:29.285634 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 11:07:29.288077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 11:07:29.291200 ==
1150 11:07:29.291584 [Gating] SW mode calibration
1151 11:07:29.301281 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 11:07:29.304723 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 11:07:29.307847 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 11:07:29.355205 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 11:07:29.355369 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 11:07:29.355692 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:07:29.356285 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:07:29.356643 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:07:29.357003 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:07:29.357144 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:07:29.357303 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:07:29.358122 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:07:29.358733 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:07:29.399824 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:07:29.400264 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:07:29.400905 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:07:29.401218 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:07:29.401641 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:07:29.402121 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:07:29.402723 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1171 11:07:29.403202 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1172 11:07:29.403518 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:07:29.403815 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:07:29.417721 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:07:29.418312 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:07:29.419103 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:07:29.419431 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:07:29.421543 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:07:29.424803 0 9 8 | B1->B0 | 2f2f 2c2c | 1 0 | (1 1) (0 0)
1180 11:07:29.428109 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:07:29.431532 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:07:29.438400 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:07:29.441695 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:07:29.444851 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:07:29.447917 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:07:29.454933 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
1187 11:07:29.458055 0 10 8 | B1->B0 | 2b2b 2525 | 0 0 | (1 1) (0 0)
1188 11:07:29.461308 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:07:29.468256 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:07:29.471110 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:07:29.474683 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:07:29.481490 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:07:29.484855 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:07:29.487806 0 11 4 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
1195 11:07:29.494922 0 11 8 | B1->B0 | 4343 3c3c | 0 0 | (0 0) (1 1)
1196 11:07:29.498404 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:07:29.501661 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:07:29.508159 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:07:29.511121 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:07:29.514895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:07:29.518320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:07:29.525406 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:07:29.528245 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 11:07:29.531473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:07:29.538473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:07:29.541922 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:07:29.545174 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:07:29.551229 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:07:29.555132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:07:29.558395 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:07:29.564816 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:07:29.568206 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:07:29.571576 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:07:29.578321 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:07:29.581825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:07:29.584983 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:07:29.592097 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:07:29.595066 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:07:29.598142 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1220 11:07:29.601614 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1221 11:07:29.604699 Total UI for P1: 0, mck2ui 16
1222 11:07:29.608589 best dqsien dly found for B1: ( 0, 14, 8)
1223 11:07:29.615200 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 11:07:29.618296 Total UI for P1: 0, mck2ui 16
1225 11:07:29.621778 best dqsien dly found for B0: ( 0, 14, 10)
1226 11:07:29.625132 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1227 11:07:29.629048 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1228 11:07:29.629154
1229 11:07:29.631659 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1230 11:07:29.635497 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 11:07:29.638701 [Gating] SW calibration Done
1232 11:07:29.638824 ==
1233 11:07:29.642140 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 11:07:29.645145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 11:07:29.645360 ==
1236 11:07:29.648929 RX Vref Scan: 0
1237 11:07:29.649087
1238 11:07:29.649212 RX Vref 0 -> 0, step: 1
1239 11:07:29.649347
1240 11:07:29.652579 RX Delay -130 -> 252, step: 16
1241 11:07:29.655249 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1242 11:07:29.661831 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1243 11:07:29.665376 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1244 11:07:29.669087 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1245 11:07:29.672586 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1246 11:07:29.675935 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1247 11:07:29.682515 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1248 11:07:29.685899 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1249 11:07:29.688930 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1250 11:07:29.692756 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1251 11:07:29.695840 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1252 11:07:29.702369 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1253 11:07:29.705765 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1254 11:07:29.709334 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1255 11:07:29.712555 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1256 11:07:29.716231 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1257 11:07:29.719440 ==
1258 11:07:29.719823 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 11:07:29.726214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 11:07:29.726737 ==
1261 11:07:29.727075 DQS Delay:
1262 11:07:29.729315 DQS0 = 0, DQS1 = 0
1263 11:07:29.729739 DQM Delay:
1264 11:07:29.732897 DQM0 = 93, DQM1 = 83
1265 11:07:29.733413 DQ Delay:
1266 11:07:29.736052 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1267 11:07:29.739231 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =109
1268 11:07:29.743226 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1269 11:07:29.745953 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1270 11:07:29.746434
1271 11:07:29.746764
1272 11:07:29.747063 ==
1273 11:07:29.749327 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 11:07:29.752701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 11:07:29.753206 ==
1276 11:07:29.753542
1277 11:07:29.753843
1278 11:07:29.756310 TX Vref Scan disable
1279 11:07:29.759624 == TX Byte 0 ==
1280 11:07:29.762406 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1281 11:07:29.766358 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1282 11:07:29.769120 == TX Byte 1 ==
1283 11:07:29.773182 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1284 11:07:29.776239 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1285 11:07:29.776665 ==
1286 11:07:29.779483 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 11:07:29.782991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 11:07:29.783495 ==
1289 11:07:29.797852 TX Vref=22, minBit 8, minWin=27, winSum=448
1290 11:07:29.801458 TX Vref=24, minBit 12, minWin=27, winSum=453
1291 11:07:29.804232 TX Vref=26, minBit 1, minWin=28, winSum=455
1292 11:07:29.807681 TX Vref=28, minBit 7, minWin=28, winSum=457
1293 11:07:29.811355 TX Vref=30, minBit 4, minWin=28, winSum=458
1294 11:07:29.817900 TX Vref=32, minBit 2, minWin=28, winSum=457
1295 11:07:29.821399 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 30
1296 11:07:29.821904
1297 11:07:29.824611 Final TX Range 1 Vref 30
1298 11:07:29.825109
1299 11:07:29.825477 ==
1300 11:07:29.828001 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 11:07:29.831663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 11:07:29.832173 ==
1303 11:07:29.832506
1304 11:07:29.834713
1305 11:07:29.835136 TX Vref Scan disable
1306 11:07:29.837926 == TX Byte 0 ==
1307 11:07:29.841236 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1308 11:07:29.844742 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1309 11:07:29.848312 == TX Byte 1 ==
1310 11:07:29.851395 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1311 11:07:29.854670 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1312 11:07:29.855097
1313 11:07:29.858459 [DATLAT]
1314 11:07:29.858882 Freq=800, CH0 RK1
1315 11:07:29.859210
1316 11:07:29.861051 DATLAT Default: 0xa
1317 11:07:29.861345 0, 0xFFFF, sum = 0
1318 11:07:29.864660 1, 0xFFFF, sum = 0
1319 11:07:29.864885 2, 0xFFFF, sum = 0
1320 11:07:29.868073 3, 0xFFFF, sum = 0
1321 11:07:29.868295 4, 0xFFFF, sum = 0
1322 11:07:29.871561 5, 0xFFFF, sum = 0
1323 11:07:29.871851 6, 0xFFFF, sum = 0
1324 11:07:29.874467 7, 0xFFFF, sum = 0
1325 11:07:29.874692 8, 0xFFFF, sum = 0
1326 11:07:29.877949 9, 0x0, sum = 1
1327 11:07:29.878270 10, 0x0, sum = 2
1328 11:07:29.881521 11, 0x0, sum = 3
1329 11:07:29.881810 12, 0x0, sum = 4
1330 11:07:29.885505 best_step = 10
1331 11:07:29.885795
1332 11:07:29.885967 ==
1333 11:07:29.888597 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 11:07:29.891707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 11:07:29.892056 ==
1336 11:07:29.895371 RX Vref Scan: 0
1337 11:07:29.895801
1338 11:07:29.896071 RX Vref 0 -> 0, step: 1
1339 11:07:29.896324
1340 11:07:29.898934 RX Delay -79 -> 252, step: 8
1341 11:07:29.905776 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1342 11:07:29.908077 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1343 11:07:29.911645 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 11:07:29.915735 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1345 11:07:29.918953 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1346 11:07:29.922053 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1347 11:07:29.928625 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 11:07:29.932102 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 11:07:29.935260 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1350 11:07:29.939111 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1351 11:07:29.942084 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1352 11:07:29.948593 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1353 11:07:29.951613 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1354 11:07:29.955471 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1355 11:07:29.959457 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 11:07:29.962156 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1357 11:07:29.965066 ==
1358 11:07:29.965493 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 11:07:29.971978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 11:07:29.972496 ==
1361 11:07:29.972832 DQS Delay:
1362 11:07:29.975436 DQS0 = 0, DQS1 = 0
1363 11:07:29.975860 DQM Delay:
1364 11:07:29.978888 DQM0 = 93, DQM1 = 82
1365 11:07:29.979317 DQ Delay:
1366 11:07:29.982155 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1367 11:07:29.985506 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1368 11:07:29.988806 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1369 11:07:29.991736 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1370 11:07:29.992160
1371 11:07:29.992487
1372 11:07:29.999101 [DQSOSCAuto] RK1, (LSB)MR18= 0x4819, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
1373 11:07:30.002448 CH0 RK1: MR19=606, MR18=4819
1374 11:07:30.008808 CH0_RK1: MR19=0x606, MR18=0x4819, DQSOSC=391, MR23=63, INC=96, DEC=64
1375 11:07:30.011872 [RxdqsGatingPostProcess] freq 800
1376 11:07:30.015211 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 11:07:30.019074 Pre-setting of DQS Precalculation
1378 11:07:30.025082 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 11:07:30.025570 ==
1380 11:07:30.029044 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 11:07:30.032098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 11:07:30.032619 ==
1383 11:07:30.038984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 11:07:30.045358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 11:07:30.052908 [CA 0] Center 36 (6~67) winsize 62
1386 11:07:30.056459 [CA 1] Center 36 (6~67) winsize 62
1387 11:07:30.059617 [CA 2] Center 35 (5~66) winsize 62
1388 11:07:30.063001 [CA 3] Center 35 (5~65) winsize 61
1389 11:07:30.066460 [CA 4] Center 35 (5~65) winsize 61
1390 11:07:30.069673 [CA 5] Center 34 (3~65) winsize 63
1391 11:07:30.070141
1392 11:07:30.073198 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1393 11:07:30.073620
1394 11:07:30.076827 [CATrainingPosCal] consider 1 rank data
1395 11:07:30.080028 u2DelayCellTimex100 = 270/100 ps
1396 11:07:30.083038 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 11:07:30.086944 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 11:07:30.093603 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1399 11:07:30.096319 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1400 11:07:30.099637 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1401 11:07:30.103238 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1402 11:07:30.103661
1403 11:07:30.106649 CA PerBit enable=1, Macro0, CA PI delay=34
1404 11:07:30.107075
1405 11:07:30.109926 [CBTSetCACLKResult] CA Dly = 34
1406 11:07:30.110482 CS Dly: 5 (0~36)
1407 11:07:30.110818 ==
1408 11:07:30.112932 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 11:07:30.119774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 11:07:30.120266 ==
1411 11:07:30.123303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 11:07:30.129691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 11:07:30.139332 [CA 0] Center 36 (6~67) winsize 62
1414 11:07:30.142564 [CA 1] Center 37 (6~68) winsize 63
1415 11:07:30.146453 [CA 2] Center 35 (5~66) winsize 62
1416 11:07:30.149102 [CA 3] Center 35 (4~66) winsize 63
1417 11:07:30.152669 [CA 4] Center 35 (4~66) winsize 63
1418 11:07:30.156111 [CA 5] Center 34 (4~65) winsize 62
1419 11:07:30.156610
1420 11:07:30.159095 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1421 11:07:30.159520
1422 11:07:30.162308 [CATrainingPosCal] consider 2 rank data
1423 11:07:30.165624 u2DelayCellTimex100 = 270/100 ps
1424 11:07:30.169699 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 11:07:30.173095 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 11:07:30.176277 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1427 11:07:30.182757 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 11:07:30.186153 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 11:07:30.189569 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 11:07:30.190116
1431 11:07:30.193048 CA PerBit enable=1, Macro0, CA PI delay=34
1432 11:07:30.193579
1433 11:07:30.195994 [CBTSetCACLKResult] CA Dly = 34
1434 11:07:30.196424 CS Dly: 6 (0~38)
1435 11:07:30.196753
1436 11:07:30.199340 ----->DramcWriteLeveling(PI) begin...
1437 11:07:30.199779 ==
1438 11:07:30.202509 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 11:07:30.209180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 11:07:30.209698 ==
1441 11:07:30.212889 Write leveling (Byte 0): 26 => 26
1442 11:07:30.216425 Write leveling (Byte 1): 29 => 29
1443 11:07:30.216852 DramcWriteLeveling(PI) end<-----
1444 11:07:30.217185
1445 11:07:30.219614 ==
1446 11:07:30.223001 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 11:07:30.225923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 11:07:30.226403 ==
1449 11:07:30.229488 [Gating] SW mode calibration
1450 11:07:30.236615 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 11:07:30.239269 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 11:07:30.246180 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 11:07:30.249580 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 11:07:30.252841 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:07:30.259896 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:07:30.262809 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:07:30.266045 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:07:30.269754 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:07:30.276229 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:07:30.280260 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:07:30.282983 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:07:30.290373 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:07:30.292991 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:07:30.296605 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:07:30.302889 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:07:30.306457 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:07:30.310126 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:07:30.316936 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:07:30.320044 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1470 11:07:30.323783 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:07:30.329985 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:07:30.333857 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:07:30.336681 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:07:30.340014 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:07:30.346571 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:07:30.349842 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:07:30.353315 0 9 4 | B1->B0 | 2323 2626 | 1 0 | (1 1) (0 0)
1478 11:07:30.360571 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1479 11:07:30.363508 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:07:30.366791 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:07:30.373546 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:07:30.376849 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:07:30.379806 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:07:30.386900 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1485 11:07:30.389671 0 10 4 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (0 1)
1486 11:07:30.393558 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
1487 11:07:30.400087 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:07:30.403870 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:07:30.406627 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:07:30.413401 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:07:30.416629 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:07:30.419991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:07:30.426419 0 11 4 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
1494 11:07:30.429799 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1495 11:07:30.433058 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:07:30.437255 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:07:30.443807 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:07:30.446715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:07:30.449998 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:07:30.456834 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:07:30.459980 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 11:07:30.463461 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:07:30.470395 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:07:30.473695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:07:30.477186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:07:30.484218 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:07:30.487405 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:07:30.490658 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:07:30.493668 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:07:30.500625 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:07:30.503834 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:07:30.507293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:07:30.513776 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:07:30.518640 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:07:30.521099 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:07:30.527027 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:07:30.531356 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 11:07:30.534246 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 11:07:30.537789 Total UI for P1: 0, mck2ui 16
1520 11:07:30.540621 best dqsien dly found for B0: ( 0, 14, 4)
1521 11:07:30.543882 Total UI for P1: 0, mck2ui 16
1522 11:07:30.547719 best dqsien dly found for B1: ( 0, 14, 4)
1523 11:07:30.551093 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1524 11:07:30.554181 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1525 11:07:30.554612
1526 11:07:30.558058 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1527 11:07:30.561205 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 11:07:30.563947 [Gating] SW calibration Done
1529 11:07:30.564438 ==
1530 11:07:30.567446 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 11:07:30.574482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 11:07:30.574994 ==
1533 11:07:30.575329 RX Vref Scan: 0
1534 11:07:30.575635
1535 11:07:30.577709 RX Vref 0 -> 0, step: 1
1536 11:07:30.578171
1537 11:07:30.580999 RX Delay -130 -> 252, step: 16
1538 11:07:30.584472 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 11:07:30.588362 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1540 11:07:30.591493 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 11:07:30.594697 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1542 11:07:30.601653 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1543 11:07:30.604541 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1544 11:07:30.607549 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1545 11:07:30.611494 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1546 11:07:30.614410 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1547 11:07:30.621364 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1548 11:07:30.624341 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1549 11:07:30.627873 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1550 11:07:30.631583 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1551 11:07:30.634256 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1552 11:07:30.641076 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1553 11:07:30.644319 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1554 11:07:30.644751 ==
1555 11:07:30.648197 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 11:07:30.650875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 11:07:30.651308 ==
1558 11:07:30.654575 DQS Delay:
1559 11:07:30.655001 DQS0 = 0, DQS1 = 0
1560 11:07:30.655330 DQM Delay:
1561 11:07:30.658296 DQM0 = 93, DQM1 = 87
1562 11:07:30.658797 DQ Delay:
1563 11:07:30.661340 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1564 11:07:30.664093 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1565 11:07:30.667653 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1566 11:07:30.671348 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1567 11:07:30.671794
1568 11:07:30.672131
1569 11:07:30.672434 ==
1570 11:07:30.674194 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 11:07:30.681037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 11:07:30.681554 ==
1573 11:07:30.681937
1574 11:07:30.682296
1575 11:07:30.682590 TX Vref Scan disable
1576 11:07:30.685082 == TX Byte 0 ==
1577 11:07:30.687827 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1578 11:07:30.691432 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1579 11:07:30.694391 == TX Byte 1 ==
1580 11:07:30.697741 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1581 11:07:30.701406 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1582 11:07:30.704620 ==
1583 11:07:30.707863 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 11:07:30.710951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 11:07:30.711385 ==
1586 11:07:30.723744 TX Vref=22, minBit 3, minWin=26, winSum=434
1587 11:07:30.726968 TX Vref=24, minBit 1, minWin=26, winSum=438
1588 11:07:30.730644 TX Vref=26, minBit 1, minWin=27, winSum=445
1589 11:07:30.734060 TX Vref=28, minBit 2, minWin=27, winSum=447
1590 11:07:30.736849 TX Vref=30, minBit 1, minWin=27, winSum=447
1591 11:07:30.740886 TX Vref=32, minBit 1, minWin=27, winSum=447
1592 11:07:30.747328 [TxChooseVref] Worse bit 2, Min win 27, Win sum 447, Final Vref 28
1593 11:07:30.747829
1594 11:07:30.750332 Final TX Range 1 Vref 28
1595 11:07:30.750762
1596 11:07:30.751229 ==
1597 11:07:30.753508 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 11:07:30.757813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 11:07:30.758380 ==
1600 11:07:30.758724
1601 11:07:30.759033
1602 11:07:30.760571 TX Vref Scan disable
1603 11:07:30.763949 == TX Byte 0 ==
1604 11:07:30.767114 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1605 11:07:30.770661 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1606 11:07:30.774092 == TX Byte 1 ==
1607 11:07:30.777426 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1608 11:07:30.780592 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1609 11:07:30.781021
1610 11:07:30.784134 [DATLAT]
1611 11:07:30.784651 Freq=800, CH1 RK0
1612 11:07:30.784987
1613 11:07:30.787723 DATLAT Default: 0xa
1614 11:07:30.788231 0, 0xFFFF, sum = 0
1615 11:07:30.790920 1, 0xFFFF, sum = 0
1616 11:07:30.791357 2, 0xFFFF, sum = 0
1617 11:07:30.794264 3, 0xFFFF, sum = 0
1618 11:07:30.794817 4, 0xFFFF, sum = 0
1619 11:07:30.797704 5, 0xFFFF, sum = 0
1620 11:07:30.798191 6, 0xFFFF, sum = 0
1621 11:07:30.800977 7, 0xFFFF, sum = 0
1622 11:07:30.801494 8, 0xFFFF, sum = 0
1623 11:07:30.804277 9, 0x0, sum = 1
1624 11:07:30.804864 10, 0x0, sum = 2
1625 11:07:30.807371 11, 0x0, sum = 3
1626 11:07:30.807810 12, 0x0, sum = 4
1627 11:07:30.810800 best_step = 10
1628 11:07:30.811228
1629 11:07:30.811557 ==
1630 11:07:30.814343 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 11:07:30.818045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 11:07:30.818489 ==
1633 11:07:30.818830 RX Vref Scan: 1
1634 11:07:30.821024
1635 11:07:30.821451 Set Vref Range= 32 -> 127
1636 11:07:30.821789
1637 11:07:30.824213 RX Vref 32 -> 127, step: 1
1638 11:07:30.824642
1639 11:07:30.827674 RX Delay -79 -> 252, step: 8
1640 11:07:30.828187
1641 11:07:30.831190 Set Vref, RX VrefLevel [Byte0]: 32
1642 11:07:30.834648 [Byte1]: 32
1643 11:07:30.835159
1644 11:07:30.838048 Set Vref, RX VrefLevel [Byte0]: 33
1645 11:07:30.840631 [Byte1]: 33
1646 11:07:30.841139
1647 11:07:30.844895 Set Vref, RX VrefLevel [Byte0]: 34
1648 11:07:30.847470 [Byte1]: 34
1649 11:07:30.851511
1650 11:07:30.852016 Set Vref, RX VrefLevel [Byte0]: 35
1651 11:07:30.854773 [Byte1]: 35
1652 11:07:30.859027
1653 11:07:30.859534 Set Vref, RX VrefLevel [Byte0]: 36
1654 11:07:30.861953 [Byte1]: 36
1655 11:07:30.866311
1656 11:07:30.866741 Set Vref, RX VrefLevel [Byte0]: 37
1657 11:07:30.870087 [Byte1]: 37
1658 11:07:30.874621
1659 11:07:30.875189 Set Vref, RX VrefLevel [Byte0]: 38
1660 11:07:30.877610 [Byte1]: 38
1661 11:07:30.881995
1662 11:07:30.882540 Set Vref, RX VrefLevel [Byte0]: 39
1663 11:07:30.885662 [Byte1]: 39
1664 11:07:30.889543
1665 11:07:30.890084 Set Vref, RX VrefLevel [Byte0]: 40
1666 11:07:30.892609 [Byte1]: 40
1667 11:07:30.897127
1668 11:07:30.897624 Set Vref, RX VrefLevel [Byte0]: 41
1669 11:07:30.899880 [Byte1]: 41
1670 11:07:30.904274
1671 11:07:30.904765 Set Vref, RX VrefLevel [Byte0]: 42
1672 11:07:30.907374 [Byte1]: 42
1673 11:07:30.912054
1674 11:07:30.912475 Set Vref, RX VrefLevel [Byte0]: 43
1675 11:07:30.914824 [Byte1]: 43
1676 11:07:30.919568
1677 11:07:30.920064 Set Vref, RX VrefLevel [Byte0]: 44
1678 11:07:30.922892 [Byte1]: 44
1679 11:07:30.927081
1680 11:07:30.927576 Set Vref, RX VrefLevel [Byte0]: 45
1681 11:07:30.929843 [Byte1]: 45
1682 11:07:30.934436
1683 11:07:30.935033 Set Vref, RX VrefLevel [Byte0]: 46
1684 11:07:30.937491 [Byte1]: 46
1685 11:07:30.941971
1686 11:07:30.942516 Set Vref, RX VrefLevel [Byte0]: 47
1687 11:07:30.945394 [Byte1]: 47
1688 11:07:30.949712
1689 11:07:30.950311 Set Vref, RX VrefLevel [Byte0]: 48
1690 11:07:30.952434 [Byte1]: 48
1691 11:07:30.957208
1692 11:07:30.957632 Set Vref, RX VrefLevel [Byte0]: 49
1693 11:07:30.960610 [Byte1]: 49
1694 11:07:30.965036
1695 11:07:30.965490 Set Vref, RX VrefLevel [Byte0]: 50
1696 11:07:30.967674 [Byte1]: 50
1697 11:07:30.972076
1698 11:07:30.972500 Set Vref, RX VrefLevel [Byte0]: 51
1699 11:07:30.975379 [Byte1]: 51
1700 11:07:30.980463
1701 11:07:30.980961 Set Vref, RX VrefLevel [Byte0]: 52
1702 11:07:30.983229 [Byte1]: 52
1703 11:07:30.987408
1704 11:07:30.987908 Set Vref, RX VrefLevel [Byte0]: 53
1705 11:07:30.990646 [Byte1]: 53
1706 11:07:30.995576
1707 11:07:30.996079 Set Vref, RX VrefLevel [Byte0]: 54
1708 11:07:30.998520 [Byte1]: 54
1709 11:07:31.002640
1710 11:07:31.003140 Set Vref, RX VrefLevel [Byte0]: 55
1711 11:07:31.005522 [Byte1]: 55
1712 11:07:31.009862
1713 11:07:31.010543 Set Vref, RX VrefLevel [Byte0]: 56
1714 11:07:31.013248 [Byte1]: 56
1715 11:07:31.017682
1716 11:07:31.018155 Set Vref, RX VrefLevel [Byte0]: 57
1717 11:07:31.021370 [Byte1]: 57
1718 11:07:31.025383
1719 11:07:31.025882 Set Vref, RX VrefLevel [Byte0]: 58
1720 11:07:31.028605 [Byte1]: 58
1721 11:07:31.032648
1722 11:07:31.033076 Set Vref, RX VrefLevel [Byte0]: 59
1723 11:07:31.035990 [Byte1]: 59
1724 11:07:31.040522
1725 11:07:31.041042 Set Vref, RX VrefLevel [Byte0]: 60
1726 11:07:31.043413 [Byte1]: 60
1727 11:07:31.047725
1728 11:07:31.048250 Set Vref, RX VrefLevel [Byte0]: 61
1729 11:07:31.050494 [Byte1]: 61
1730 11:07:31.054835
1731 11:07:31.055308 Set Vref, RX VrefLevel [Byte0]: 62
1732 11:07:31.057971 [Byte1]: 62
1733 11:07:31.062483
1734 11:07:31.062911 Set Vref, RX VrefLevel [Byte0]: 63
1735 11:07:31.065621 [Byte1]: 63
1736 11:07:31.070137
1737 11:07:31.070528 Set Vref, RX VrefLevel [Byte0]: 64
1738 11:07:31.073789 [Byte1]: 64
1739 11:07:31.077927
1740 11:07:31.078485 Set Vref, RX VrefLevel [Byte0]: 65
1741 11:07:31.080864 [Byte1]: 65
1742 11:07:31.085059
1743 11:07:31.085448 Set Vref, RX VrefLevel [Byte0]: 66
1744 11:07:31.088590 [Byte1]: 66
1745 11:07:31.092983
1746 11:07:31.093484 Set Vref, RX VrefLevel [Byte0]: 67
1747 11:07:31.096278 [Byte1]: 67
1748 11:07:31.101079
1749 11:07:31.101581 Set Vref, RX VrefLevel [Byte0]: 68
1750 11:07:31.104287 [Byte1]: 68
1751 11:07:31.107665
1752 11:07:31.108091 Set Vref, RX VrefLevel [Byte0]: 69
1753 11:07:31.111303 [Byte1]: 69
1754 11:07:31.115536
1755 11:07:31.116056 Set Vref, RX VrefLevel [Byte0]: 70
1756 11:07:31.119025 [Byte1]: 70
1757 11:07:31.122886
1758 11:07:31.123386 Set Vref, RX VrefLevel [Byte0]: 71
1759 11:07:31.126565 [Byte1]: 71
1760 11:07:31.131329
1761 11:07:31.131838 Set Vref, RX VrefLevel [Byte0]: 72
1762 11:07:31.134274 [Byte1]: 72
1763 11:07:31.138847
1764 11:07:31.139361 Final RX Vref Byte 0 = 59 to rank0
1765 11:07:31.141775 Final RX Vref Byte 1 = 57 to rank0
1766 11:07:31.145307 Final RX Vref Byte 0 = 59 to rank1
1767 11:07:31.148402 Final RX Vref Byte 1 = 57 to rank1==
1768 11:07:31.151846 Dram Type= 6, Freq= 0, CH_1, rank 0
1769 11:07:31.155283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1770 11:07:31.157927 ==
1771 11:07:31.158502 DQS Delay:
1772 11:07:31.158874 DQS0 = 0, DQS1 = 0
1773 11:07:31.161366 DQM Delay:
1774 11:07:31.161789 DQM0 = 95, DQM1 = 89
1775 11:07:31.164717 DQ Delay:
1776 11:07:31.168138 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1777 11:07:31.171951 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1778 11:07:31.172378 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1779 11:07:31.178390 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1780 11:07:31.178910
1781 11:07:31.179206
1782 11:07:31.184999 [DQSOSCAuto] RK0, (LSB)MR18= 0x3551, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1783 11:07:31.188136 CH1 RK0: MR19=606, MR18=3551
1784 11:07:31.195293 CH1_RK0: MR19=0x606, MR18=0x3551, DQSOSC=389, MR23=63, INC=97, DEC=65
1785 11:07:31.195761
1786 11:07:31.198598 ----->DramcWriteLeveling(PI) begin...
1787 11:07:31.199020 ==
1788 11:07:31.201596 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 11:07:31.205288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 11:07:31.205762 ==
1791 11:07:31.208233 Write leveling (Byte 0): 27 => 27
1792 11:07:31.212352 Write leveling (Byte 1): 28 => 28
1793 11:07:31.214821 DramcWriteLeveling(PI) end<-----
1794 11:07:31.215254
1795 11:07:31.215582 ==
1796 11:07:31.218798 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 11:07:31.221493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 11:07:31.221925 ==
1799 11:07:31.224771 [Gating] SW mode calibration
1800 11:07:31.231750 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1801 11:07:31.238974 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1802 11:07:31.242121 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1803 11:07:31.245336 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1804 11:07:31.252368 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 11:07:31.255025 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:07:31.258651 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:07:31.265302 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:07:31.268618 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:07:31.272048 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:07:31.275681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:07:31.282153 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:07:31.285762 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:07:31.288514 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:07:31.295360 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:07:31.299242 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:07:31.302596 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:07:31.309246 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:07:31.312019 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1819 11:07:31.315366 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:07:31.322346 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1821 11:07:31.326250 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:07:31.328833 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:07:31.335682 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:07:31.338625 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:07:31.342266 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:07:31.345223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:07:31.352050 0 9 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1828 11:07:31.355437 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1829 11:07:31.358853 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 11:07:31.365384 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 11:07:31.368832 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 11:07:31.372650 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:07:31.378823 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 11:07:31.382315 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1835 11:07:31.385666 0 10 4 | B1->B0 | 2c2c 2f2f | 0 1 | (0 0) (1 0)
1836 11:07:31.392059 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1837 11:07:31.395498 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:07:31.398482 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:07:31.405612 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:07:31.408880 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:07:31.412777 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:07:31.418672 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1843 11:07:31.422204 0 11 4 | B1->B0 | 3f3f 3131 | 0 0 | (0 0) (1 1)
1844 11:07:31.425411 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1845 11:07:31.432636 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 11:07:31.435482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 11:07:31.438902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 11:07:31.441938 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 11:07:31.448742 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 11:07:31.452104 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 11:07:31.455635 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1852 11:07:31.462300 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1853 11:07:31.465633 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:07:31.468806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:07:31.475413 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:07:31.478560 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:07:31.482346 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:07:31.489090 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:07:31.491886 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:07:31.495598 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:07:31.502220 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:07:31.505668 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:07:31.509024 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:07:31.515359 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:07:31.519355 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:07:31.522609 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:07:31.526064 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1868 11:07:31.533368 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 11:07:31.535664 Total UI for P1: 0, mck2ui 16
1870 11:07:31.539693 best dqsien dly found for B0: ( 0, 14, 6)
1871 11:07:31.540211 Total UI for P1: 0, mck2ui 16
1872 11:07:31.546120 best dqsien dly found for B1: ( 0, 14, 4)
1873 11:07:31.549346 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1874 11:07:31.552596 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1875 11:07:31.553114
1876 11:07:31.556051 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1877 11:07:31.559298 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 11:07:31.562622 [Gating] SW calibration Done
1879 11:07:31.563053 ==
1880 11:07:31.565589 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 11:07:31.569193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 11:07:31.569628 ==
1883 11:07:31.572859 RX Vref Scan: 0
1884 11:07:31.573245
1885 11:07:31.573549 RX Vref 0 -> 0, step: 1
1886 11:07:31.573830
1887 11:07:31.575603 RX Delay -130 -> 252, step: 16
1888 11:07:31.579497 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1889 11:07:31.585764 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1890 11:07:31.589726 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1891 11:07:31.592319 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1892 11:07:31.595700 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1893 11:07:31.598987 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1894 11:07:31.605764 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1895 11:07:31.609119 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1896 11:07:31.612392 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1897 11:07:31.615730 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1898 11:07:31.619203 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1899 11:07:31.625825 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1900 11:07:31.629485 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1901 11:07:31.633142 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1902 11:07:31.636312 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1903 11:07:31.639600 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1904 11:07:31.642726 ==
1905 11:07:31.643200 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 11:07:31.649426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 11:07:31.649907 ==
1908 11:07:31.650274 DQS Delay:
1909 11:07:31.652516 DQS0 = 0, DQS1 = 0
1910 11:07:31.652906 DQM Delay:
1911 11:07:31.655842 DQM0 = 94, DQM1 = 91
1912 11:07:31.656232 DQ Delay:
1913 11:07:31.659249 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =85
1914 11:07:31.663083 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1915 11:07:31.665813 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1916 11:07:31.669343 DQ12 =101, DQ13 =101, DQ14 =93, DQ15 =101
1917 11:07:31.669753
1918 11:07:31.670221
1919 11:07:31.670516 ==
1920 11:07:31.672455 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 11:07:31.676319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 11:07:31.676715 ==
1923 11:07:31.677023
1924 11:07:31.677304
1925 11:07:31.679209 TX Vref Scan disable
1926 11:07:31.682623 == TX Byte 0 ==
1927 11:07:31.686042 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1928 11:07:31.689335 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1929 11:07:31.692738 == TX Byte 1 ==
1930 11:07:31.696179 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1931 11:07:31.699864 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1932 11:07:31.700347 ==
1933 11:07:31.702938 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 11:07:31.706614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 11:07:31.709660 ==
1936 11:07:31.721418 TX Vref=22, minBit 1, minWin=26, winSum=444
1937 11:07:31.723968 TX Vref=24, minBit 0, minWin=27, winSum=445
1938 11:07:31.727273 TX Vref=26, minBit 0, minWin=27, winSum=449
1939 11:07:31.730610 TX Vref=28, minBit 2, minWin=27, winSum=450
1940 11:07:31.734337 TX Vref=30, minBit 2, minWin=27, winSum=452
1941 11:07:31.737581 TX Vref=32, minBit 2, minWin=27, winSum=449
1942 11:07:31.744336 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
1943 11:07:31.744806
1944 11:07:31.747571 Final TX Range 1 Vref 30
1945 11:07:31.748086
1946 11:07:31.748423 ==
1947 11:07:31.750901 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 11:07:31.754169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 11:07:31.754590 ==
1950 11:07:31.754889
1951 11:07:31.755161
1952 11:07:31.757391 TX Vref Scan disable
1953 11:07:31.761006 == TX Byte 0 ==
1954 11:07:31.764192 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1955 11:07:31.768128 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1956 11:07:31.770999 == TX Byte 1 ==
1957 11:07:31.773966 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1958 11:07:31.777453 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1959 11:07:31.777841
1960 11:07:31.780526 [DATLAT]
1961 11:07:31.780912 Freq=800, CH1 RK1
1962 11:07:31.781210
1963 11:07:31.784480 DATLAT Default: 0xa
1964 11:07:31.784951 0, 0xFFFF, sum = 0
1965 11:07:31.787753 1, 0xFFFF, sum = 0
1966 11:07:31.788149 2, 0xFFFF, sum = 0
1967 11:07:31.791071 3, 0xFFFF, sum = 0
1968 11:07:31.791543 4, 0xFFFF, sum = 0
1969 11:07:31.795145 5, 0xFFFF, sum = 0
1970 11:07:31.795619 6, 0xFFFF, sum = 0
1971 11:07:31.797903 7, 0xFFFF, sum = 0
1972 11:07:31.798347 8, 0xFFFF, sum = 0
1973 11:07:31.801433 9, 0x0, sum = 1
1974 11:07:31.801910 10, 0x0, sum = 2
1975 11:07:31.804571 11, 0x0, sum = 3
1976 11:07:31.805052 12, 0x0, sum = 4
1977 11:07:31.807446 best_step = 10
1978 11:07:31.807835
1979 11:07:31.808133 ==
1980 11:07:31.811529 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 11:07:31.814421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 11:07:31.814932 ==
1983 11:07:31.817937 RX Vref Scan: 0
1984 11:07:31.818360
1985 11:07:31.818664 RX Vref 0 -> 0, step: 1
1986 11:07:31.818946
1987 11:07:31.821142 RX Delay -79 -> 252, step: 8
1988 11:07:31.824242 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1989 11:07:31.831398 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1990 11:07:31.834674 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1991 11:07:31.838111 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1992 11:07:31.840908 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1993 11:07:31.844952 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1994 11:07:31.847869 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1995 11:07:31.854693 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1996 11:07:31.858149 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1997 11:07:31.861182 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1998 11:07:31.864265 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1999 11:07:31.867564 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2000 11:07:31.874589 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2001 11:07:31.878150 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2002 11:07:31.880899 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2003 11:07:31.884709 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2004 11:07:31.885182 ==
2005 11:07:31.888172 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 11:07:31.894344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 11:07:31.894805 ==
2008 11:07:31.895111 DQS Delay:
2009 11:07:31.895391 DQS0 = 0, DQS1 = 0
2010 11:07:31.899582 DQM Delay:
2011 11:07:31.900059 DQM0 = 97, DQM1 = 91
2012 11:07:31.901264 DQ Delay:
2013 11:07:31.904522 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2014 11:07:31.907465 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2015 11:07:31.911018 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2016 11:07:31.914721 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2017 11:07:31.915384
2018 11:07:31.915769
2019 11:07:31.921165 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2020 11:07:31.924462 CH1 RK1: MR19=606, MR18=4D16
2021 11:07:31.931016 CH1_RK1: MR19=0x606, MR18=0x4D16, DQSOSC=390, MR23=63, INC=97, DEC=64
2022 11:07:31.934801 [RxdqsGatingPostProcess] freq 800
2023 11:07:31.937673 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 11:07:31.941124 Pre-setting of DQS Precalculation
2025 11:07:31.947583 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 11:07:31.954338 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 11:07:31.960962 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 11:07:31.961432
2029 11:07:31.961735
2030 11:07:31.965203 [Calibration Summary] 1600 Mbps
2031 11:07:31.965718 CH 0, Rank 0
2032 11:07:31.967900 SW Impedance : PASS
2033 11:07:31.971075 DUTY Scan : NO K
2034 11:07:31.971515 ZQ Calibration : PASS
2035 11:07:31.974708 Jitter Meter : NO K
2036 11:07:31.978232 CBT Training : PASS
2037 11:07:31.978711 Write leveling : PASS
2038 11:07:31.981457 RX DQS gating : PASS
2039 11:07:31.981934 RX DQ/DQS(RDDQC) : PASS
2040 11:07:31.985037 TX DQ/DQS : PASS
2041 11:07:31.987545 RX DATLAT : PASS
2042 11:07:31.987936 RX DQ/DQS(Engine): PASS
2043 11:07:31.991292 TX OE : NO K
2044 11:07:31.991771 All Pass.
2045 11:07:31.992084
2046 11:07:31.994797 CH 0, Rank 1
2047 11:07:31.995270 SW Impedance : PASS
2048 11:07:31.997754 DUTY Scan : NO K
2049 11:07:32.001591 ZQ Calibration : PASS
2050 11:07:32.002113 Jitter Meter : NO K
2051 11:07:32.004761 CBT Training : PASS
2052 11:07:32.007872 Write leveling : PASS
2053 11:07:32.008264 RX DQS gating : PASS
2054 11:07:32.010940 RX DQ/DQS(RDDQC) : PASS
2055 11:07:32.014780 TX DQ/DQS : PASS
2056 11:07:32.015258 RX DATLAT : PASS
2057 11:07:32.018050 RX DQ/DQS(Engine): PASS
2058 11:07:32.020882 TX OE : NO K
2059 11:07:32.021273 All Pass.
2060 11:07:32.021575
2061 11:07:32.021852 CH 1, Rank 0
2062 11:07:32.024325 SW Impedance : PASS
2063 11:07:32.027656 DUTY Scan : NO K
2064 11:07:32.028148 ZQ Calibration : PASS
2065 11:07:32.031482 Jitter Meter : NO K
2066 11:07:32.031907 CBT Training : PASS
2067 11:07:32.034576 Write leveling : PASS
2068 11:07:32.038151 RX DQS gating : PASS
2069 11:07:32.038619 RX DQ/DQS(RDDQC) : PASS
2070 11:07:32.040888 TX DQ/DQS : PASS
2071 11:07:32.044799 RX DATLAT : PASS
2072 11:07:32.045270 RX DQ/DQS(Engine): PASS
2073 11:07:32.047825 TX OE : NO K
2074 11:07:32.048301 All Pass.
2075 11:07:32.048606
2076 11:07:32.051372 CH 1, Rank 1
2077 11:07:32.051761 SW Impedance : PASS
2078 11:07:32.054132 DUTY Scan : NO K
2079 11:07:32.058062 ZQ Calibration : PASS
2080 11:07:32.058455 Jitter Meter : NO K
2081 11:07:32.060721 CBT Training : PASS
2082 11:07:32.064739 Write leveling : PASS
2083 11:07:32.065161 RX DQS gating : PASS
2084 11:07:32.068040 RX DQ/DQS(RDDQC) : PASS
2085 11:07:32.071021 TX DQ/DQS : PASS
2086 11:07:32.071427 RX DATLAT : PASS
2087 11:07:32.074517 RX DQ/DQS(Engine): PASS
2088 11:07:32.074908 TX OE : NO K
2089 11:07:32.077368 All Pass.
2090 11:07:32.077753
2091 11:07:32.078096 DramC Write-DBI off
2092 11:07:32.081169 PER_BANK_REFRESH: Hybrid Mode
2093 11:07:32.084405 TX_TRACKING: ON
2094 11:07:32.087456 [GetDramInforAfterCalByMRR] Vendor 6.
2095 11:07:32.091451 [GetDramInforAfterCalByMRR] Revision 606.
2096 11:07:32.094519 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 11:07:32.094912 MR0 0x3b3b
2098 11:07:32.095214 MR8 0x5151
2099 11:07:32.101048 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 11:07:32.101514
2101 11:07:32.101822 MR0 0x3b3b
2102 11:07:32.102147 MR8 0x5151
2103 11:07:32.104312 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 11:07:32.104702
2105 11:07:32.114164 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 11:07:32.117625 [FAST_K] Save calibration result to emmc
2107 11:07:32.121376 [FAST_K] Save calibration result to emmc
2108 11:07:32.124686 dram_init: config_dvfs: 1
2109 11:07:32.127762 dramc_set_vcore_voltage set vcore to 662500
2110 11:07:32.131696 Read voltage for 1200, 2
2111 11:07:32.132208 Vio18 = 0
2112 11:07:32.132542 Vcore = 662500
2113 11:07:32.134189 Vdram = 0
2114 11:07:32.134707 Vddq = 0
2115 11:07:32.135047 Vmddr = 0
2116 11:07:32.141834 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 11:07:32.144771 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 11:07:32.148158 MEM_TYPE=3, freq_sel=15
2119 11:07:32.150978 sv_algorithm_assistance_LP4_1600
2120 11:07:32.154458 ============ PULL DRAM RESETB DOWN ============
2121 11:07:32.157737 ========== PULL DRAM RESETB DOWN end =========
2122 11:07:32.164590 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 11:07:32.168246 ===================================
2124 11:07:32.171488 LPDDR4 DRAM CONFIGURATION
2125 11:07:32.171933 ===================================
2126 11:07:32.174570 EX_ROW_EN[0] = 0x0
2127 11:07:32.177538 EX_ROW_EN[1] = 0x0
2128 11:07:32.177973 LP4Y_EN = 0x0
2129 11:07:32.180842 WORK_FSP = 0x0
2130 11:07:32.181232 WL = 0x4
2131 11:07:32.184479 RL = 0x4
2132 11:07:32.184949 BL = 0x2
2133 11:07:32.187618 RPST = 0x0
2134 11:07:32.188008 RD_PRE = 0x0
2135 11:07:32.191034 WR_PRE = 0x1
2136 11:07:32.191463 WR_PST = 0x0
2137 11:07:32.194840 DBI_WR = 0x0
2138 11:07:32.195232 DBI_RD = 0x0
2139 11:07:32.198102 OTF = 0x1
2140 11:07:32.201064 ===================================
2141 11:07:32.204522 ===================================
2142 11:07:32.204989 ANA top config
2143 11:07:32.207611 ===================================
2144 11:07:32.211293 DLL_ASYNC_EN = 0
2145 11:07:32.214894 ALL_SLAVE_EN = 0
2146 11:07:32.217480 NEW_RANK_MODE = 1
2147 11:07:32.217884 DLL_IDLE_MODE = 1
2148 11:07:32.221150 LP45_APHY_COMB_EN = 1
2149 11:07:32.224454 TX_ODT_DIS = 1
2150 11:07:32.227675 NEW_8X_MODE = 1
2151 11:07:32.231454 ===================================
2152 11:07:32.234920 ===================================
2153 11:07:32.238160 data_rate = 2400
2154 11:07:32.238624 CKR = 1
2155 11:07:32.240872 DQ_P2S_RATIO = 8
2156 11:07:32.244716 ===================================
2157 11:07:32.247942 CA_P2S_RATIO = 8
2158 11:07:32.251368 DQ_CA_OPEN = 0
2159 11:07:32.254594 DQ_SEMI_OPEN = 0
2160 11:07:32.255038 CA_SEMI_OPEN = 0
2161 11:07:32.257848 CA_FULL_RATE = 0
2162 11:07:32.260971 DQ_CKDIV4_EN = 0
2163 11:07:32.264697 CA_CKDIV4_EN = 0
2164 11:07:32.267692 CA_PREDIV_EN = 0
2165 11:07:32.270982 PH8_DLY = 17
2166 11:07:32.271374 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 11:07:32.274579 DQ_AAMCK_DIV = 4
2168 11:07:32.277861 CA_AAMCK_DIV = 4
2169 11:07:32.281107 CA_ADMCK_DIV = 4
2170 11:07:32.284956 DQ_TRACK_CA_EN = 0
2171 11:07:32.287866 CA_PICK = 1200
2172 11:07:32.290766 CA_MCKIO = 1200
2173 11:07:32.291158 MCKIO_SEMI = 0
2174 11:07:32.294843 PLL_FREQ = 2366
2175 11:07:32.297460 DQ_UI_PI_RATIO = 32
2176 11:07:32.301026 CA_UI_PI_RATIO = 0
2177 11:07:32.304715 ===================================
2178 11:07:32.307725 ===================================
2179 11:07:32.311403 memory_type:LPDDR4
2180 11:07:32.311887 GP_NUM : 10
2181 11:07:32.314438 SRAM_EN : 1
2182 11:07:32.317555 MD32_EN : 0
2183 11:07:32.321358 ===================================
2184 11:07:32.321867 [ANA_INIT] >>>>>>>>>>>>>>
2185 11:07:32.324385 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 11:07:32.327855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 11:07:32.331170 ===================================
2188 11:07:32.334768 data_rate = 2400,PCW = 0X5b00
2189 11:07:32.337738 ===================================
2190 11:07:32.341580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 11:07:32.347881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 11:07:32.351344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 11:07:32.358192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 11:07:32.361056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 11:07:32.364136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 11:07:32.364707 [ANA_INIT] flow start
2197 11:07:32.368078 [ANA_INIT] PLL >>>>>>>>
2198 11:07:32.371221 [ANA_INIT] PLL <<<<<<<<
2199 11:07:32.371651 [ANA_INIT] MIDPI >>>>>>>>
2200 11:07:32.374204 [ANA_INIT] MIDPI <<<<<<<<
2201 11:07:32.377650 [ANA_INIT] DLL >>>>>>>>
2202 11:07:32.378063 [ANA_INIT] DLL <<<<<<<<
2203 11:07:32.381412 [ANA_INIT] flow end
2204 11:07:32.385299 ============ LP4 DIFF to SE enter ============
2205 11:07:32.387460 ============ LP4 DIFF to SE exit ============
2206 11:07:32.391272 [ANA_INIT] <<<<<<<<<<<<<
2207 11:07:32.394270 [Flow] Enable top DCM control >>>>>
2208 11:07:32.398205 [Flow] Enable top DCM control <<<<<
2209 11:07:32.401364 Enable DLL master slave shuffle
2210 11:07:32.407645 ==============================================================
2211 11:07:32.408161 Gating Mode config
2212 11:07:32.414775 ==============================================================
2213 11:07:32.415277 Config description:
2214 11:07:32.424650 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 11:07:32.431499 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 11:07:32.438723 SELPH_MODE 0: By rank 1: By Phase
2217 11:07:32.441603 ==============================================================
2218 11:07:32.444946 GAT_TRACK_EN = 1
2219 11:07:32.447982 RX_GATING_MODE = 2
2220 11:07:32.451676 RX_GATING_TRACK_MODE = 2
2221 11:07:32.454508 SELPH_MODE = 1
2222 11:07:32.457726 PICG_EARLY_EN = 1
2223 11:07:32.461021 VALID_LAT_VALUE = 1
2224 11:07:32.464937 ==============================================================
2225 11:07:32.467804 Enter into Gating configuration >>>>
2226 11:07:32.471212 Exit from Gating configuration <<<<
2227 11:07:32.474665 Enter into DVFS_PRE_config >>>>>
2228 11:07:32.488038 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 11:07:32.491953 Exit from DVFS_PRE_config <<<<<
2230 11:07:32.494946 Enter into PICG configuration >>>>
2231 11:07:32.495408 Exit from PICG configuration <<<<
2232 11:07:32.498053 [RX_INPUT] configuration >>>>>
2233 11:07:32.501507 [RX_INPUT] configuration <<<<<
2234 11:07:32.508219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 11:07:32.511232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 11:07:32.517947 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 11:07:32.524641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 11:07:32.531212 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 11:07:32.537879 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 11:07:32.541959 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 11:07:32.545314 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 11:07:32.548556 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 11:07:32.555131 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 11:07:32.558440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 11:07:32.561917 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 11:07:32.565406 ===================================
2247 11:07:32.568375 LPDDR4 DRAM CONFIGURATION
2248 11:07:32.571574 ===================================
2249 11:07:32.572138 EX_ROW_EN[0] = 0x0
2250 11:07:32.574683 EX_ROW_EN[1] = 0x0
2251 11:07:32.578602 LP4Y_EN = 0x0
2252 11:07:32.578992 WORK_FSP = 0x0
2253 11:07:32.582674 WL = 0x4
2254 11:07:32.583074 RL = 0x4
2255 11:07:32.585033 BL = 0x2
2256 11:07:32.585532 RPST = 0x0
2257 11:07:32.588870 RD_PRE = 0x0
2258 11:07:32.589338 WR_PRE = 0x1
2259 11:07:32.591590 WR_PST = 0x0
2260 11:07:32.591980 DBI_WR = 0x0
2261 11:07:32.595306 DBI_RD = 0x0
2262 11:07:32.595794 OTF = 0x1
2263 11:07:32.598249 ===================================
2264 11:07:32.601861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 11:07:32.607976 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 11:07:32.611901 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 11:07:32.615187 ===================================
2268 11:07:32.618742 LPDDR4 DRAM CONFIGURATION
2269 11:07:32.621626 ===================================
2270 11:07:32.622107 EX_ROW_EN[0] = 0x10
2271 11:07:32.624883 EX_ROW_EN[1] = 0x0
2272 11:07:32.625396 LP4Y_EN = 0x0
2273 11:07:32.628642 WORK_FSP = 0x0
2274 11:07:32.629153 WL = 0x4
2275 11:07:32.632129 RL = 0x4
2276 11:07:32.632558 BL = 0x2
2277 11:07:32.635144 RPST = 0x0
2278 11:07:32.638115 RD_PRE = 0x0
2279 11:07:32.638549 WR_PRE = 0x1
2280 11:07:32.642431 WR_PST = 0x0
2281 11:07:32.642937 DBI_WR = 0x0
2282 11:07:32.645211 DBI_RD = 0x0
2283 11:07:32.645724 OTF = 0x1
2284 11:07:32.648817 ===================================
2285 11:07:32.655060 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 11:07:32.655555 ==
2287 11:07:32.658330 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 11:07:32.661942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 11:07:32.662509 ==
2290 11:07:32.665320 [Duty_Offset_Calibration]
2291 11:07:32.665758 B0:2 B1:1 CA:1
2292 11:07:32.666166
2293 11:07:32.668593 [DutyScan_Calibration_Flow] k_type=0
2294 11:07:32.679438
2295 11:07:32.679982 ==CLK 0==
2296 11:07:32.682995 Final CLK duty delay cell = 0
2297 11:07:32.686296 [0] MAX Duty = 5218%(X100), DQS PI = 24
2298 11:07:32.689463 [0] MIN Duty = 4844%(X100), DQS PI = 48
2299 11:07:32.689977 [0] AVG Duty = 5031%(X100)
2300 11:07:32.692714
2301 11:07:32.693225 CH0 CLK Duty spec in!! Max-Min= 374%
2302 11:07:32.699307 [DutyScan_Calibration_Flow] ====Done====
2303 11:07:32.699738
2304 11:07:32.702684 [DutyScan_Calibration_Flow] k_type=1
2305 11:07:32.717893
2306 11:07:32.718327 ==DQS 0 ==
2307 11:07:32.721445 Final DQS duty delay cell = -4
2308 11:07:32.724655 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2309 11:07:32.727692 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2310 11:07:32.731161 [-4] AVG Duty = 4937%(X100)
2311 11:07:32.731437
2312 11:07:32.731646 ==DQS 1 ==
2313 11:07:32.734421 Final DQS duty delay cell = 0
2314 11:07:32.737541 [0] MAX Duty = 5156%(X100), DQS PI = 0
2315 11:07:32.741674 [0] MIN Duty = 5000%(X100), DQS PI = 32
2316 11:07:32.744666 [0] AVG Duty = 5078%(X100)
2317 11:07:32.744940
2318 11:07:32.747951 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2319 11:07:32.748229
2320 11:07:32.750988 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2321 11:07:32.754446 [DutyScan_Calibration_Flow] ====Done====
2322 11:07:32.754722
2323 11:07:32.757682 [DutyScan_Calibration_Flow] k_type=3
2324 11:07:32.775010
2325 11:07:32.775509 ==DQM 0 ==
2326 11:07:32.777969 Final DQM duty delay cell = 0
2327 11:07:32.781656 [0] MAX Duty = 5156%(X100), DQS PI = 32
2328 11:07:32.784750 [0] MIN Duty = 4907%(X100), DQS PI = 58
2329 11:07:32.785378 [0] AVG Duty = 5031%(X100)
2330 11:07:32.788166
2331 11:07:32.788663 ==DQM 1 ==
2332 11:07:32.791906 Final DQM duty delay cell = 0
2333 11:07:32.795236 [0] MAX Duty = 5093%(X100), DQS PI = 0
2334 11:07:32.798725 [0] MIN Duty = 5031%(X100), DQS PI = 14
2335 11:07:32.799237 [0] AVG Duty = 5062%(X100)
2336 11:07:32.799568
2337 11:07:32.805411 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2338 11:07:32.805934
2339 11:07:32.808374 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2340 11:07:32.811543 [DutyScan_Calibration_Flow] ====Done====
2341 11:07:32.812043
2342 11:07:32.814900 [DutyScan_Calibration_Flow] k_type=2
2343 11:07:32.831399
2344 11:07:32.831896 ==DQ 0 ==
2345 11:07:32.835092 Final DQ duty delay cell = 0
2346 11:07:32.838083 [0] MAX Duty = 5031%(X100), DQS PI = 24
2347 11:07:32.841055 [0] MIN Duty = 4875%(X100), DQS PI = 0
2348 11:07:32.841628 [0] AVG Duty = 4953%(X100)
2349 11:07:32.841975
2350 11:07:32.844652 ==DQ 1 ==
2351 11:07:32.847630 Final DQ duty delay cell = 0
2352 11:07:32.851099 [0] MAX Duty = 5093%(X100), DQS PI = 24
2353 11:07:32.854298 [0] MIN Duty = 4907%(X100), DQS PI = 36
2354 11:07:32.854794 [0] AVG Duty = 5000%(X100)
2355 11:07:32.855202
2356 11:07:32.858134 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2357 11:07:32.858639
2358 11:07:32.861194 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2359 11:07:32.867635 [DutyScan_Calibration_Flow] ====Done====
2360 11:07:32.868116 ==
2361 11:07:32.871094 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 11:07:32.874239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 11:07:32.874665 ==
2364 11:07:32.878541 [Duty_Offset_Calibration]
2365 11:07:32.878966 B0:1 B1:0 CA:0
2366 11:07:32.879295
2367 11:07:32.881200 [DutyScan_Calibration_Flow] k_type=0
2368 11:07:32.890186
2369 11:07:32.890702 ==CLK 0==
2370 11:07:32.893851 Final CLK duty delay cell = -4
2371 11:07:32.897185 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2372 11:07:32.900567 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2373 11:07:32.903621 [-4] AVG Duty = 4953%(X100)
2374 11:07:32.904122
2375 11:07:32.906808 CH1 CLK Duty spec in!! Max-Min= 156%
2376 11:07:32.910404 [DutyScan_Calibration_Flow] ====Done====
2377 11:07:32.910832
2378 11:07:32.913684 [DutyScan_Calibration_Flow] k_type=1
2379 11:07:32.930767
2380 11:07:32.931268 ==DQS 0 ==
2381 11:07:32.933843 Final DQS duty delay cell = 0
2382 11:07:32.936774 [0] MAX Duty = 5094%(X100), DQS PI = 26
2383 11:07:32.940272 [0] MIN Duty = 4844%(X100), DQS PI = 0
2384 11:07:32.940772 [0] AVG Duty = 4969%(X100)
2385 11:07:32.941104
2386 11:07:32.943572 ==DQS 1 ==
2387 11:07:32.946942 Final DQS duty delay cell = 0
2388 11:07:32.950376 [0] MAX Duty = 5187%(X100), DQS PI = 20
2389 11:07:32.953248 [0] MIN Duty = 4969%(X100), DQS PI = 10
2390 11:07:32.953679 [0] AVG Duty = 5078%(X100)
2391 11:07:32.954043
2392 11:07:32.960306 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2393 11:07:32.960808
2394 11:07:32.963585 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2395 11:07:32.966662 [DutyScan_Calibration_Flow] ====Done====
2396 11:07:32.967090
2397 11:07:32.969841 [DutyScan_Calibration_Flow] k_type=3
2398 11:07:32.986660
2399 11:07:32.987159 ==DQM 0 ==
2400 11:07:32.989612 Final DQM duty delay cell = 0
2401 11:07:32.993292 [0] MAX Duty = 5156%(X100), DQS PI = 6
2402 11:07:32.996475 [0] MIN Duty = 5000%(X100), DQS PI = 62
2403 11:07:32.996983 [0] AVG Duty = 5078%(X100)
2404 11:07:32.999865
2405 11:07:33.000325 ==DQM 1 ==
2406 11:07:33.002919 Final DQM duty delay cell = 0
2407 11:07:33.006664 [0] MAX Duty = 5031%(X100), DQS PI = 16
2408 11:07:33.009753 [0] MIN Duty = 4907%(X100), DQS PI = 36
2409 11:07:33.013724 [0] AVG Duty = 4969%(X100)
2410 11:07:33.014430
2411 11:07:33.016769 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2412 11:07:33.017272
2413 11:07:33.020282 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 11:07:33.023059 [DutyScan_Calibration_Flow] ====Done====
2415 11:07:33.023486
2416 11:07:33.027096 [DutyScan_Calibration_Flow] k_type=2
2417 11:07:33.042645
2418 11:07:33.043150 ==DQ 0 ==
2419 11:07:33.046263 Final DQ duty delay cell = -4
2420 11:07:33.049540 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2421 11:07:33.052924 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2422 11:07:33.053431 [-4] AVG Duty = 4984%(X100)
2423 11:07:33.056110
2424 11:07:33.056568 ==DQ 1 ==
2425 11:07:33.059531 Final DQ duty delay cell = 0
2426 11:07:33.062976 [0] MAX Duty = 5125%(X100), DQS PI = 20
2427 11:07:33.066107 [0] MIN Duty = 4938%(X100), DQS PI = 34
2428 11:07:33.066630 [0] AVG Duty = 5031%(X100)
2429 11:07:33.066964
2430 11:07:33.069172 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2431 11:07:33.073030
2432 11:07:33.075689 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2433 11:07:33.078880 [DutyScan_Calibration_Flow] ====Done====
2434 11:07:33.082254 nWR fixed to 30
2435 11:07:33.082696 [ModeRegInit_LP4] CH0 RK0
2436 11:07:33.085624 [ModeRegInit_LP4] CH0 RK1
2437 11:07:33.089280 [ModeRegInit_LP4] CH1 RK0
2438 11:07:33.089701 [ModeRegInit_LP4] CH1 RK1
2439 11:07:33.092881 match AC timing 7
2440 11:07:33.095770 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 11:07:33.099150 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 11:07:33.106408 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 11:07:33.109312 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 11:07:33.115930 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 11:07:33.116426 ==
2446 11:07:33.119071 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 11:07:33.122867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 11:07:33.123301 ==
2449 11:07:33.129349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 11:07:33.132621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 11:07:33.142710 [CA 0] Center 39 (8~70) winsize 63
2452 11:07:33.146231 [CA 1] Center 39 (8~70) winsize 63
2453 11:07:33.149355 [CA 2] Center 35 (5~66) winsize 62
2454 11:07:33.152782 [CA 3] Center 34 (4~65) winsize 62
2455 11:07:33.156176 [CA 4] Center 33 (3~64) winsize 62
2456 11:07:33.159607 [CA 5] Center 32 (3~62) winsize 60
2457 11:07:33.160114
2458 11:07:33.162574 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2459 11:07:33.163002
2460 11:07:33.165816 [CATrainingPosCal] consider 1 rank data
2461 11:07:33.168904 u2DelayCellTimex100 = 270/100 ps
2462 11:07:33.172754 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2463 11:07:33.175768 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 11:07:33.182393 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2465 11:07:33.185593 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2466 11:07:33.189509 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2467 11:07:33.192670 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2468 11:07:33.193180
2469 11:07:33.195685 CA PerBit enable=1, Macro0, CA PI delay=32
2470 11:07:33.196110
2471 11:07:33.199284 [CBTSetCACLKResult] CA Dly = 32
2472 11:07:33.199773 CS Dly: 6 (0~37)
2473 11:07:33.202675 ==
2474 11:07:33.203172 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 11:07:33.209748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 11:07:33.210399 ==
2477 11:07:33.212250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 11:07:33.219554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2479 11:07:33.228571 [CA 0] Center 38 (8~69) winsize 62
2480 11:07:33.231858 [CA 1] Center 38 (8~69) winsize 62
2481 11:07:33.234852 [CA 2] Center 35 (4~66) winsize 63
2482 11:07:33.238561 [CA 3] Center 34 (4~65) winsize 62
2483 11:07:33.242069 [CA 4] Center 33 (3~64) winsize 62
2484 11:07:33.245245 [CA 5] Center 32 (3~62) winsize 60
2485 11:07:33.245749
2486 11:07:33.248143 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 11:07:33.248570
2488 11:07:33.252006 [CATrainingPosCal] consider 2 rank data
2489 11:07:33.254802 u2DelayCellTimex100 = 270/100 ps
2490 11:07:33.258533 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2491 11:07:33.262171 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 11:07:33.268629 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2493 11:07:33.271866 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2494 11:07:33.275134 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2495 11:07:33.278824 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2496 11:07:33.279281
2497 11:07:33.281784 CA PerBit enable=1, Macro0, CA PI delay=32
2498 11:07:33.282343
2499 11:07:33.285611 [CBTSetCACLKResult] CA Dly = 32
2500 11:07:33.286151 CS Dly: 6 (0~38)
2501 11:07:33.286487
2502 11:07:33.288788 ----->DramcWriteLeveling(PI) begin...
2503 11:07:33.289292 ==
2504 11:07:33.291907 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 11:07:33.299069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 11:07:33.299570 ==
2507 11:07:33.302507 Write leveling (Byte 0): 35 => 35
2508 11:07:33.305104 Write leveling (Byte 1): 30 => 30
2509 11:07:33.305527 DramcWriteLeveling(PI) end<-----
2510 11:07:33.305856
2511 11:07:33.309363 ==
2512 11:07:33.312217 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 11:07:33.315084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 11:07:33.315514 ==
2515 11:07:33.318736 [Gating] SW mode calibration
2516 11:07:33.325692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 11:07:33.328981 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 11:07:33.335908 0 15 0 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2519 11:07:33.338867 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2520 11:07:33.342255 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 11:07:33.348506 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 11:07:33.352360 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 11:07:33.355607 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 11:07:33.362613 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 11:07:33.365513 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2526 11:07:33.368922 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2527 11:07:33.372076 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 11:07:33.379375 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 11:07:33.382979 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 11:07:33.385589 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 11:07:33.392521 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 11:07:33.395994 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2533 11:07:33.398897 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2534 11:07:33.405733 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2535 11:07:33.409441 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 11:07:33.412897 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 11:07:33.419083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 11:07:33.422200 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 11:07:33.425515 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 11:07:33.432219 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2541 11:07:33.435788 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 11:07:33.438793 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2543 11:07:33.445661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 11:07:33.449363 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:07:33.452442 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:07:33.456041 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:07:33.462387 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:07:33.465669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:07:33.469152 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:07:33.475796 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:07:33.479643 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:07:33.482678 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:07:33.489189 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:07:33.492559 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:07:33.495903 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:07:33.502557 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:07:33.505562 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 11:07:33.509178 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 11:07:33.512583 Total UI for P1: 0, mck2ui 16
2560 11:07:33.515756 best dqsien dly found for B0: ( 1, 3, 28)
2561 11:07:33.522610 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 11:07:33.523103 Total UI for P1: 0, mck2ui 16
2563 11:07:33.526220 best dqsien dly found for B1: ( 1, 4, 0)
2564 11:07:33.532574 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2565 11:07:33.535876 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 11:07:33.536310
2567 11:07:33.538958 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 11:07:33.542097 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 11:07:33.546075 [Gating] SW calibration Done
2570 11:07:33.546540 ==
2571 11:07:33.548907 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 11:07:33.552234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 11:07:33.552649 ==
2574 11:07:33.552945 RX Vref Scan: 0
2575 11:07:33.556028
2576 11:07:33.556516 RX Vref 0 -> 0, step: 1
2577 11:07:33.556839
2578 11:07:33.558864 RX Delay -40 -> 252, step: 8
2579 11:07:33.562107 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2580 11:07:33.565458 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2581 11:07:33.572250 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 11:07:33.575767 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 11:07:33.578960 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2584 11:07:33.582730 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 11:07:33.585452 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 11:07:33.592661 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 11:07:33.596039 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 11:07:33.599552 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2589 11:07:33.603041 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2590 11:07:33.605940 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 11:07:33.609500 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2592 11:07:33.616665 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2593 11:07:33.619566 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 11:07:33.622772 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2595 11:07:33.623202 ==
2596 11:07:33.626172 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 11:07:33.629667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 11:07:33.633033 ==
2599 11:07:33.633546 DQS Delay:
2600 11:07:33.633880 DQS0 = 0, DQS1 = 0
2601 11:07:33.636537 DQM Delay:
2602 11:07:33.637043 DQM0 = 121, DQM1 = 113
2603 11:07:33.639136 DQ Delay:
2604 11:07:33.643039 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2605 11:07:33.646693 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2606 11:07:33.649244 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2607 11:07:33.652898 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2608 11:07:33.653331
2609 11:07:33.653661
2610 11:07:33.653959 ==
2611 11:07:33.656121 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 11:07:33.659281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 11:07:33.659711 ==
2614 11:07:33.660037
2615 11:07:33.660334
2616 11:07:33.663079 TX Vref Scan disable
2617 11:07:33.666556 == TX Byte 0 ==
2618 11:07:33.669512 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2619 11:07:33.672762 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2620 11:07:33.675993 == TX Byte 1 ==
2621 11:07:33.680023 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2622 11:07:33.683008 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2623 11:07:33.683557 ==
2624 11:07:33.686265 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 11:07:33.689680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 11:07:33.693549 ==
2627 11:07:33.703037 TX Vref=22, minBit 0, minWin=25, winSum=406
2628 11:07:33.707653 TX Vref=24, minBit 12, minWin=24, winSum=415
2629 11:07:33.710063 TX Vref=26, minBit 10, minWin=25, winSum=420
2630 11:07:33.713121 TX Vref=28, minBit 0, minWin=26, winSum=421
2631 11:07:33.716828 TX Vref=30, minBit 12, minWin=25, winSum=420
2632 11:07:33.723239 TX Vref=32, minBit 5, minWin=25, winSum=421
2633 11:07:33.726509 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 28
2634 11:07:33.726950
2635 11:07:33.730082 Final TX Range 1 Vref 28
2636 11:07:33.730587
2637 11:07:33.730913 ==
2638 11:07:33.734154 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 11:07:33.737260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 11:07:33.740172 ==
2641 11:07:33.740677
2642 11:07:33.741008
2643 11:07:33.741310 TX Vref Scan disable
2644 11:07:33.742949 == TX Byte 0 ==
2645 11:07:33.746993 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2646 11:07:33.749912 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2647 11:07:33.752978 == TX Byte 1 ==
2648 11:07:33.756663 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2649 11:07:33.759848 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2650 11:07:33.763457
2651 11:07:33.763879 [DATLAT]
2652 11:07:33.764208 Freq=1200, CH0 RK0
2653 11:07:33.764514
2654 11:07:33.766834 DATLAT Default: 0xd
2655 11:07:33.767260 0, 0xFFFF, sum = 0
2656 11:07:33.769770 1, 0xFFFF, sum = 0
2657 11:07:33.770400 2, 0xFFFF, sum = 0
2658 11:07:33.773288 3, 0xFFFF, sum = 0
2659 11:07:33.773719 4, 0xFFFF, sum = 0
2660 11:07:33.777108 5, 0xFFFF, sum = 0
2661 11:07:33.777544 6, 0xFFFF, sum = 0
2662 11:07:33.780314 7, 0xFFFF, sum = 0
2663 11:07:33.783625 8, 0xFFFF, sum = 0
2664 11:07:33.784142 9, 0xFFFF, sum = 0
2665 11:07:33.787185 10, 0xFFFF, sum = 0
2666 11:07:33.787702 11, 0xFFFF, sum = 0
2667 11:07:33.790711 12, 0x0, sum = 1
2668 11:07:33.791229 13, 0x0, sum = 2
2669 11:07:33.793794 14, 0x0, sum = 3
2670 11:07:33.794364 15, 0x0, sum = 4
2671 11:07:33.794705 best_step = 13
2672 11:07:33.795009
2673 11:07:33.797209 ==
2674 11:07:33.797740 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 11:07:33.803633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 11:07:33.804133 ==
2677 11:07:33.804468 RX Vref Scan: 1
2678 11:07:33.804772
2679 11:07:33.806628 Set Vref Range= 32 -> 127
2680 11:07:33.807053
2681 11:07:33.810245 RX Vref 32 -> 127, step: 1
2682 11:07:33.810750
2683 11:07:33.813356 RX Delay -13 -> 252, step: 4
2684 11:07:33.813796
2685 11:07:33.817220 Set Vref, RX VrefLevel [Byte0]: 32
2686 11:07:33.820115 [Byte1]: 32
2687 11:07:33.820619
2688 11:07:33.823494 Set Vref, RX VrefLevel [Byte0]: 33
2689 11:07:33.827046 [Byte1]: 33
2690 11:07:33.827556
2691 11:07:33.830638 Set Vref, RX VrefLevel [Byte0]: 34
2692 11:07:33.833708 [Byte1]: 34
2693 11:07:33.838120
2694 11:07:33.838635 Set Vref, RX VrefLevel [Byte0]: 35
2695 11:07:33.840842 [Byte1]: 35
2696 11:07:33.845786
2697 11:07:33.846348 Set Vref, RX VrefLevel [Byte0]: 36
2698 11:07:33.848911 [Byte1]: 36
2699 11:07:33.853571
2700 11:07:33.854125 Set Vref, RX VrefLevel [Byte0]: 37
2701 11:07:33.856959 [Byte1]: 37
2702 11:07:33.861474
2703 11:07:33.861981 Set Vref, RX VrefLevel [Byte0]: 38
2704 11:07:33.864734 [Byte1]: 38
2705 11:07:33.868916
2706 11:07:33.869438 Set Vref, RX VrefLevel [Byte0]: 39
2707 11:07:33.872375 [Byte1]: 39
2708 11:07:33.877697
2709 11:07:33.878160 Set Vref, RX VrefLevel [Byte0]: 40
2710 11:07:33.880578 [Byte1]: 40
2711 11:07:33.885090
2712 11:07:33.885601 Set Vref, RX VrefLevel [Byte0]: 41
2713 11:07:33.888383 [Byte1]: 41
2714 11:07:33.892918
2715 11:07:33.893455 Set Vref, RX VrefLevel [Byte0]: 42
2716 11:07:33.896751 [Byte1]: 42
2717 11:07:33.901214
2718 11:07:33.901727 Set Vref, RX VrefLevel [Byte0]: 43
2719 11:07:33.904093 [Byte1]: 43
2720 11:07:33.908669
2721 11:07:33.909176 Set Vref, RX VrefLevel [Byte0]: 44
2722 11:07:33.911673 [Byte1]: 44
2723 11:07:33.916713
2724 11:07:33.917217 Set Vref, RX VrefLevel [Byte0]: 45
2725 11:07:33.920033 [Byte1]: 45
2726 11:07:33.924742
2727 11:07:33.925169 Set Vref, RX VrefLevel [Byte0]: 46
2728 11:07:33.927581 [Byte1]: 46
2729 11:07:33.932299
2730 11:07:33.932466 Set Vref, RX VrefLevel [Byte0]: 47
2731 11:07:33.935063 [Byte1]: 47
2732 11:07:33.939955
2733 11:07:33.940223 Set Vref, RX VrefLevel [Byte0]: 48
2734 11:07:33.942994 [Byte1]: 48
2735 11:07:33.947990
2736 11:07:33.948517 Set Vref, RX VrefLevel [Byte0]: 49
2737 11:07:33.951353 [Byte1]: 49
2738 11:07:33.956158
2739 11:07:33.956551 Set Vref, RX VrefLevel [Byte0]: 50
2740 11:07:33.959309 [Byte1]: 50
2741 11:07:33.964394
2742 11:07:33.964899 Set Vref, RX VrefLevel [Byte0]: 51
2743 11:07:33.967384 [Byte1]: 51
2744 11:07:33.971796
2745 11:07:33.972227 Set Vref, RX VrefLevel [Byte0]: 52
2746 11:07:33.974782 [Byte1]: 52
2747 11:07:33.979488
2748 11:07:33.979994 Set Vref, RX VrefLevel [Byte0]: 53
2749 11:07:33.982987 [Byte1]: 53
2750 11:07:33.988062
2751 11:07:33.988561 Set Vref, RX VrefLevel [Byte0]: 54
2752 11:07:33.990942 [Byte1]: 54
2753 11:07:33.995644
2754 11:07:33.996146 Set Vref, RX VrefLevel [Byte0]: 55
2755 11:07:33.998854 [Byte1]: 55
2756 11:07:34.003705
2757 11:07:34.004204 Set Vref, RX VrefLevel [Byte0]: 56
2758 11:07:34.006632 [Byte1]: 56
2759 11:07:34.011092
2760 11:07:34.011597 Set Vref, RX VrefLevel [Byte0]: 57
2761 11:07:34.014730 [Byte1]: 57
2762 11:07:34.019550
2763 11:07:34.020053 Set Vref, RX VrefLevel [Byte0]: 58
2764 11:07:34.022079 [Byte1]: 58
2765 11:07:34.027531
2766 11:07:34.028032 Set Vref, RX VrefLevel [Byte0]: 59
2767 11:07:34.030611 [Byte1]: 59
2768 11:07:34.035608
2769 11:07:34.036107 Set Vref, RX VrefLevel [Byte0]: 60
2770 11:07:34.038135 [Byte1]: 60
2771 11:07:34.042994
2772 11:07:34.043493 Set Vref, RX VrefLevel [Byte0]: 61
2773 11:07:34.046089 [Byte1]: 61
2774 11:07:34.050966
2775 11:07:34.051468 Set Vref, RX VrefLevel [Byte0]: 62
2776 11:07:34.053881 [Byte1]: 62
2777 11:07:34.058536
2778 11:07:34.059086 Set Vref, RX VrefLevel [Byte0]: 63
2779 11:07:34.061762 [Byte1]: 63
2780 11:07:34.066685
2781 11:07:34.067355 Set Vref, RX VrefLevel [Byte0]: 64
2782 11:07:34.069698 [Byte1]: 64
2783 11:07:34.074404
2784 11:07:34.074835 Set Vref, RX VrefLevel [Byte0]: 65
2785 11:07:34.077477 [Byte1]: 65
2786 11:07:34.082759
2787 11:07:34.083262 Set Vref, RX VrefLevel [Byte0]: 66
2788 11:07:34.085944 [Byte1]: 66
2789 11:07:34.090693
2790 11:07:34.091215 Set Vref, RX VrefLevel [Byte0]: 67
2791 11:07:34.093241 [Byte1]: 67
2792 11:07:34.097586
2793 11:07:34.101004 Set Vref, RX VrefLevel [Byte0]: 68
2794 11:07:34.101438 [Byte1]: 68
2795 11:07:34.106058
2796 11:07:34.106559 Set Vref, RX VrefLevel [Byte0]: 69
2797 11:07:34.109616 [Byte1]: 69
2798 11:07:34.113893
2799 11:07:34.114448 Final RX Vref Byte 0 = 55 to rank0
2800 11:07:34.117049 Final RX Vref Byte 1 = 54 to rank0
2801 11:07:34.120523 Final RX Vref Byte 0 = 55 to rank1
2802 11:07:34.123884 Final RX Vref Byte 1 = 54 to rank1==
2803 11:07:34.127355 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 11:07:34.133797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 11:07:34.134356 ==
2806 11:07:34.134690 DQS Delay:
2807 11:07:34.134990 DQS0 = 0, DQS1 = 0
2808 11:07:34.137002 DQM Delay:
2809 11:07:34.137430 DQM0 = 121, DQM1 = 113
2810 11:07:34.140179 DQ Delay:
2811 11:07:34.143908 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =120
2812 11:07:34.147439 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2813 11:07:34.150580 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2814 11:07:34.154066 DQ12 =120, DQ13 =116, DQ14 =124, DQ15 =122
2815 11:07:34.154585
2816 11:07:34.154921
2817 11:07:34.160858 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2818 11:07:34.164205 CH0 RK0: MR19=404, MR18=150E
2819 11:07:34.170749 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2820 11:07:34.171279
2821 11:07:34.173618 ----->DramcWriteLeveling(PI) begin...
2822 11:07:34.174274 ==
2823 11:07:34.176981 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 11:07:34.180891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 11:07:34.184002 ==
2826 11:07:34.184481 Write leveling (Byte 0): 34 => 34
2827 11:07:34.187216 Write leveling (Byte 1): 28 => 28
2828 11:07:34.190352 DramcWriteLeveling(PI) end<-----
2829 11:07:34.190736
2830 11:07:34.191031 ==
2831 11:07:34.193961 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 11:07:34.200589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 11:07:34.201048 ==
2834 11:07:34.201352 [Gating] SW mode calibration
2835 11:07:34.211023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 11:07:34.214101 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 11:07:34.217073 0 15 0 | B1->B0 | 3333 2f2e | 0 1 | (0 0) (1 1)
2838 11:07:34.223528 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 11:07:34.227189 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 11:07:34.230349 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 11:07:34.237344 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 11:07:34.240389 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 11:07:34.243701 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 11:07:34.250621 0 15 28 | B1->B0 | 2d2d 2929 | 1 1 | (1 0) (1 0)
2845 11:07:34.253727 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 11:07:34.257234 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 11:07:34.263745 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 11:07:34.266657 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 11:07:34.270656 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 11:07:34.277000 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 11:07:34.281199 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2852 11:07:34.283880 1 0 28 | B1->B0 | 3c3c 3a3a | 0 0 | (0 0) (0 0)
2853 11:07:34.290854 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 11:07:34.294517 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 11:07:34.297261 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 11:07:34.303918 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 11:07:34.307231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 11:07:34.310790 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 11:07:34.313792 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 11:07:34.320215 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 11:07:34.323474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2862 11:07:34.327459 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 11:07:34.333640 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:07:34.337801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:07:34.340911 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:07:34.347249 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:07:34.351090 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:07:34.353748 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:07:34.360221 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:07:34.364167 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:07:34.367551 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:07:34.374170 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:07:34.377258 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:07:34.381043 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:07:34.384319 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2876 11:07:34.390860 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 11:07:34.394001 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 11:07:34.397301 Total UI for P1: 0, mck2ui 16
2879 11:07:34.400775 best dqsien dly found for B0: ( 1, 3, 26)
2880 11:07:34.404236 Total UI for P1: 0, mck2ui 16
2881 11:07:34.408163 best dqsien dly found for B1: ( 1, 3, 26)
2882 11:07:34.410915 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2883 11:07:34.414362 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2884 11:07:34.414868
2885 11:07:34.417102 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2886 11:07:34.420630 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2887 11:07:34.423929 [Gating] SW calibration Done
2888 11:07:34.424358 ==
2889 11:07:34.427116 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 11:07:34.434101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 11:07:34.434603 ==
2892 11:07:34.434934 RX Vref Scan: 0
2893 11:07:34.435245
2894 11:07:34.437398 RX Vref 0 -> 0, step: 1
2895 11:07:34.437923
2896 11:07:34.440754 RX Delay -40 -> 252, step: 8
2897 11:07:34.444627 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2898 11:07:34.447687 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2899 11:07:34.450875 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2900 11:07:34.454162 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2901 11:07:34.461080 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2902 11:07:34.464311 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2903 11:07:34.467501 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2904 11:07:34.471067 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2905 11:07:34.474045 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2906 11:07:34.477635 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2907 11:07:34.484854 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2908 11:07:34.488032 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2909 11:07:34.490626 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2910 11:07:34.494145 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2911 11:07:34.501322 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2912 11:07:34.504288 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2913 11:07:34.504801 ==
2914 11:07:34.507709 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 11:07:34.510618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 11:07:34.511056 ==
2917 11:07:34.511415 DQS Delay:
2918 11:07:34.514104 DQS0 = 0, DQS1 = 0
2919 11:07:34.514601 DQM Delay:
2920 11:07:34.517366 DQM0 = 121, DQM1 = 113
2921 11:07:34.517797 DQ Delay:
2922 11:07:34.520717 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2923 11:07:34.523942 DQ4 =127, DQ5 =115, DQ6 =123, DQ7 =127
2924 11:07:34.527647 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2925 11:07:34.530888 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2926 11:07:34.533989
2927 11:07:34.534456
2928 11:07:34.534780 ==
2929 11:07:34.537329 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 11:07:34.540665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 11:07:34.541177 ==
2932 11:07:34.541511
2933 11:07:34.541815
2934 11:07:34.544635 TX Vref Scan disable
2935 11:07:34.545147 == TX Byte 0 ==
2936 11:07:34.550752 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2937 11:07:34.554417 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2938 11:07:34.554933 == TX Byte 1 ==
2939 11:07:34.560776 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2940 11:07:34.564152 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2941 11:07:34.564667 ==
2942 11:07:34.567393 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 11:07:34.571081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 11:07:34.571517 ==
2945 11:07:34.583458 TX Vref=22, minBit 1, minWin=25, winSum=414
2946 11:07:34.586655 TX Vref=24, minBit 1, minWin=25, winSum=417
2947 11:07:34.589958 TX Vref=26, minBit 3, minWin=25, winSum=421
2948 11:07:34.593384 TX Vref=28, minBit 1, minWin=26, winSum=426
2949 11:07:34.596575 TX Vref=30, minBit 3, minWin=26, winSum=431
2950 11:07:34.603671 TX Vref=32, minBit 0, minWin=26, winSum=428
2951 11:07:34.606488 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 30
2952 11:07:34.606884
2953 11:07:34.610511 Final TX Range 1 Vref 30
2954 11:07:34.610899
2955 11:07:34.611195 ==
2956 11:07:34.613338 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 11:07:34.617174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 11:07:34.618130 ==
2959 11:07:34.620229
2960 11:07:34.620564
2961 11:07:34.620844 TX Vref Scan disable
2962 11:07:34.623542 == TX Byte 0 ==
2963 11:07:34.626562 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2964 11:07:34.630173 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2965 11:07:34.633246 == TX Byte 1 ==
2966 11:07:34.636994 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2967 11:07:34.640132 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2968 11:07:34.643515
2969 11:07:34.643992 [DATLAT]
2970 11:07:34.644304 Freq=1200, CH0 RK1
2971 11:07:34.644589
2972 11:07:34.647258 DATLAT Default: 0xd
2973 11:07:34.647651 0, 0xFFFF, sum = 0
2974 11:07:34.650157 1, 0xFFFF, sum = 0
2975 11:07:34.650554 2, 0xFFFF, sum = 0
2976 11:07:34.653500 3, 0xFFFF, sum = 0
2977 11:07:34.657164 4, 0xFFFF, sum = 0
2978 11:07:34.657641 5, 0xFFFF, sum = 0
2979 11:07:34.660301 6, 0xFFFF, sum = 0
2980 11:07:34.660696 7, 0xFFFF, sum = 0
2981 11:07:34.663556 8, 0xFFFF, sum = 0
2982 11:07:34.663990 9, 0xFFFF, sum = 0
2983 11:07:34.666665 10, 0xFFFF, sum = 0
2984 11:07:34.667256 11, 0xFFFF, sum = 0
2985 11:07:34.669870 12, 0x0, sum = 1
2986 11:07:34.670387 13, 0x0, sum = 2
2987 11:07:34.673454 14, 0x0, sum = 3
2988 11:07:34.673887 15, 0x0, sum = 4
2989 11:07:34.676668 best_step = 13
2990 11:07:34.677093
2991 11:07:34.677421 ==
2992 11:07:34.679824 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 11:07:34.683639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 11:07:34.684147 ==
2995 11:07:34.684481 RX Vref Scan: 0
2996 11:07:34.684787
2997 11:07:34.686655 RX Vref 0 -> 0, step: 1
2998 11:07:34.687175
2999 11:07:34.689611 RX Delay -13 -> 252, step: 4
3000 11:07:34.693119 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3001 11:07:34.699812 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3002 11:07:34.703915 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3003 11:07:34.707098 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3004 11:07:34.709896 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3005 11:07:34.713837 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3006 11:07:34.719883 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3007 11:07:34.723326 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3008 11:07:34.726763 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3009 11:07:34.730128 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3010 11:07:34.733570 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3011 11:07:34.739611 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3012 11:07:34.743295 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3013 11:07:34.746547 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3014 11:07:34.749524 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3015 11:07:34.753368 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3016 11:07:34.756567 ==
3017 11:07:34.757077 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 11:07:34.763307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 11:07:34.763739 ==
3020 11:07:34.764067 DQS Delay:
3021 11:07:34.766654 DQS0 = 0, DQS1 = 0
3022 11:07:34.767160 DQM Delay:
3023 11:07:34.769966 DQM0 = 121, DQM1 = 111
3024 11:07:34.770426 DQ Delay:
3025 11:07:34.773216 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3026 11:07:34.776881 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3027 11:07:34.779893 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3028 11:07:34.783431 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3029 11:07:34.784088
3030 11:07:34.784421
3031 11:07:34.793677 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3032 11:07:34.794249 CH0 RK1: MR19=403, MR18=11F3
3033 11:07:34.799815 CH0_RK1: MR19=0x403, MR18=0x11F3, DQSOSC=403, MR23=63, INC=40, DEC=26
3034 11:07:34.802893 [RxdqsGatingPostProcess] freq 1200
3035 11:07:34.809827 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3036 11:07:34.813774 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 11:07:34.816942 best DQS1 dly(2T, 0.5T) = (0, 12)
3038 11:07:34.819953 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 11:07:34.822917 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3040 11:07:34.826163 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 11:07:34.829764 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 11:07:34.833111 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 11:07:34.836268 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 11:07:34.836778 Pre-setting of DQS Precalculation
3045 11:07:34.843241 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3046 11:07:34.843754 ==
3047 11:07:34.846052 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 11:07:34.849924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 11:07:34.850383 ==
3050 11:07:34.856513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3051 11:07:34.863526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3052 11:07:34.870568 [CA 0] Center 37 (7~68) winsize 62
3053 11:07:34.873550 [CA 1] Center 37 (7~68) winsize 62
3054 11:07:34.876743 [CA 2] Center 35 (5~65) winsize 61
3055 11:07:34.879979 [CA 3] Center 34 (4~64) winsize 61
3056 11:07:34.883592 [CA 4] Center 34 (5~64) winsize 60
3057 11:07:34.886766 [CA 5] Center 33 (3~63) winsize 61
3058 11:07:34.887270
3059 11:07:34.890529 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3060 11:07:34.891036
3061 11:07:34.893431 [CATrainingPosCal] consider 1 rank data
3062 11:07:34.896655 u2DelayCellTimex100 = 270/100 ps
3063 11:07:34.900102 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 11:07:34.907001 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 11:07:34.910187 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 11:07:34.913594 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3067 11:07:34.916471 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3068 11:07:34.920436 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3069 11:07:34.921027
3070 11:07:34.923099 CA PerBit enable=1, Macro0, CA PI delay=33
3071 11:07:34.923524
3072 11:07:34.926506 [CBTSetCACLKResult] CA Dly = 33
3073 11:07:34.926937 CS Dly: 7 (0~38)
3074 11:07:34.930002 ==
3075 11:07:34.930558 Dram Type= 6, Freq= 0, CH_1, rank 1
3076 11:07:34.936586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 11:07:34.937290 ==
3078 11:07:34.940301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 11:07:34.946995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3080 11:07:34.955906 [CA 0] Center 37 (7~68) winsize 62
3081 11:07:34.959445 [CA 1] Center 37 (7~68) winsize 62
3082 11:07:34.962640 [CA 2] Center 35 (5~66) winsize 62
3083 11:07:34.965918 [CA 3] Center 34 (4~65) winsize 62
3084 11:07:34.969858 [CA 4] Center 34 (4~65) winsize 62
3085 11:07:34.972635 [CA 5] Center 34 (4~64) winsize 61
3086 11:07:34.973068
3087 11:07:34.975904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3088 11:07:34.976349
3089 11:07:34.979102 [CATrainingPosCal] consider 2 rank data
3090 11:07:34.982812 u2DelayCellTimex100 = 270/100 ps
3091 11:07:34.985760 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 11:07:34.989508 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 11:07:34.996116 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 11:07:34.999486 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 11:07:35.002669 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3096 11:07:35.005622 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3097 11:07:35.006192
3098 11:07:35.009369 CA PerBit enable=1, Macro0, CA PI delay=33
3099 11:07:35.009875
3100 11:07:35.013374 [CBTSetCACLKResult] CA Dly = 33
3101 11:07:35.013882 CS Dly: 8 (0~41)
3102 11:07:35.014282
3103 11:07:35.015359 ----->DramcWriteLeveling(PI) begin...
3104 11:07:35.019212 ==
3105 11:07:35.022810 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 11:07:35.025485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 11:07:35.025916 ==
3108 11:07:35.029129 Write leveling (Byte 0): 24 => 24
3109 11:07:35.032291 Write leveling (Byte 1): 27 => 27
3110 11:07:35.035696 DramcWriteLeveling(PI) end<-----
3111 11:07:35.036126
3112 11:07:35.036454 ==
3113 11:07:35.038742 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 11:07:35.042452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 11:07:35.042884 ==
3116 11:07:35.045767 [Gating] SW mode calibration
3117 11:07:35.051937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3118 11:07:35.058695 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3119 11:07:35.062202 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 11:07:35.065937 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 11:07:35.072161 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 11:07:35.075118 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 11:07:35.078621 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 11:07:35.086078 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 11:07:35.089089 0 15 24 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (0 1)
3126 11:07:35.092412 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3127 11:07:35.095531 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 11:07:35.101949 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 11:07:35.105118 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 11:07:35.108737 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 11:07:35.115197 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 11:07:35.118535 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 11:07:35.122400 1 0 24 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3134 11:07:35.128623 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 11:07:35.132572 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 11:07:35.135363 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 11:07:35.141865 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 11:07:35.145825 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 11:07:35.148949 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 11:07:35.155127 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:07:35.158920 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3142 11:07:35.161897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 11:07:35.169183 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 11:07:35.171974 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:07:35.175100 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:07:35.181634 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:07:35.185002 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:07:35.188331 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:07:35.195424 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:07:35.198777 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:07:35.201590 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:07:35.208568 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:07:35.212364 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:07:35.214968 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:07:35.222044 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:07:35.224906 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:07:35.227921 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3158 11:07:35.234667 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 11:07:35.238329 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 11:07:35.241059 Total UI for P1: 0, mck2ui 16
3161 11:07:35.244375 best dqsien dly found for B0: ( 1, 3, 28)
3162 11:07:35.247849 Total UI for P1: 0, mck2ui 16
3163 11:07:35.251269 best dqsien dly found for B1: ( 1, 3, 26)
3164 11:07:35.254415 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3165 11:07:35.258271 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3166 11:07:35.258773
3167 11:07:35.261374 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3168 11:07:35.264349 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 11:07:35.267789 [Gating] SW calibration Done
3170 11:07:35.268305 ==
3171 11:07:35.271284 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 11:07:35.274687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 11:07:35.275121 ==
3174 11:07:35.277820 RX Vref Scan: 0
3175 11:07:35.278360
3176 11:07:35.281501 RX Vref 0 -> 0, step: 1
3177 11:07:35.281934
3178 11:07:35.282319 RX Delay -40 -> 252, step: 8
3179 11:07:35.287920 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3180 11:07:35.291518 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3181 11:07:35.294604 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3182 11:07:35.297761 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3183 11:07:35.301030 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3184 11:07:35.308171 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3185 11:07:35.311283 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3186 11:07:35.314202 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3187 11:07:35.318235 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3188 11:07:35.321226 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3189 11:07:35.327967 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3190 11:07:35.331387 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3191 11:07:35.334369 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 11:07:35.337748 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3193 11:07:35.340754 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3194 11:07:35.347909 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3195 11:07:35.348434 ==
3196 11:07:35.351373 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 11:07:35.354381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 11:07:35.354812 ==
3199 11:07:35.355141 DQS Delay:
3200 11:07:35.357421 DQS0 = 0, DQS1 = 0
3201 11:07:35.357808 DQM Delay:
3202 11:07:35.360808 DQM0 = 119, DQM1 = 116
3203 11:07:35.361198 DQ Delay:
3204 11:07:35.364699 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3205 11:07:35.368222 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3206 11:07:35.371167 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3207 11:07:35.374316 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3208 11:07:35.374795
3209 11:07:35.378308
3210 11:07:35.378758 ==
3211 11:07:35.380915 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 11:07:35.383952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 11:07:35.384344 ==
3214 11:07:35.384647
3215 11:07:35.384925
3216 11:07:35.387194 TX Vref Scan disable
3217 11:07:35.387590 == TX Byte 0 ==
3218 11:07:35.390979 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3219 11:07:35.398171 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3220 11:07:35.398649 == TX Byte 1 ==
3221 11:07:35.400635 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3222 11:07:35.407377 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3223 11:07:35.407848 ==
3224 11:07:35.411391 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 11:07:35.414363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 11:07:35.414760 ==
3227 11:07:35.426799 TX Vref=22, minBit 9, minWin=24, winSum=411
3228 11:07:35.429490 TX Vref=24, minBit 1, minWin=25, winSum=417
3229 11:07:35.433154 TX Vref=26, minBit 9, minWin=25, winSum=425
3230 11:07:35.435858 TX Vref=28, minBit 1, minWin=26, winSum=427
3231 11:07:35.439577 TX Vref=30, minBit 2, minWin=26, winSum=428
3232 11:07:35.446565 TX Vref=32, minBit 2, minWin=26, winSum=428
3233 11:07:35.449345 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 30
3234 11:07:35.449875
3235 11:07:35.452657 Final TX Range 1 Vref 30
3236 11:07:35.453171
3237 11:07:35.453554 ==
3238 11:07:35.455776 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:07:35.459119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:07:35.462320 ==
3241 11:07:35.462750
3242 11:07:35.463079
3243 11:07:35.463437 TX Vref Scan disable
3244 11:07:35.465654 == TX Byte 0 ==
3245 11:07:35.468843 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3246 11:07:35.475668 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3247 11:07:35.476124 == TX Byte 1 ==
3248 11:07:35.478959 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3249 11:07:35.486382 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3250 11:07:35.486912
3251 11:07:35.487251 [DATLAT]
3252 11:07:35.487559 Freq=1200, CH1 RK0
3253 11:07:35.487851
3254 11:07:35.489108 DATLAT Default: 0xd
3255 11:07:35.492534 0, 0xFFFF, sum = 0
3256 11:07:35.493076 1, 0xFFFF, sum = 0
3257 11:07:35.495720 2, 0xFFFF, sum = 0
3258 11:07:35.496367 3, 0xFFFF, sum = 0
3259 11:07:35.498936 4, 0xFFFF, sum = 0
3260 11:07:35.499376 5, 0xFFFF, sum = 0
3261 11:07:35.502220 6, 0xFFFF, sum = 0
3262 11:07:35.502750 7, 0xFFFF, sum = 0
3263 11:07:35.505768 8, 0xFFFF, sum = 0
3264 11:07:35.506337 9, 0xFFFF, sum = 0
3265 11:07:35.508593 10, 0xFFFF, sum = 0
3266 11:07:35.509034 11, 0xFFFF, sum = 0
3267 11:07:35.511912 12, 0x0, sum = 1
3268 11:07:35.512349 13, 0x0, sum = 2
3269 11:07:35.515499 14, 0x0, sum = 3
3270 11:07:35.516031 15, 0x0, sum = 4
3271 11:07:35.518562 best_step = 13
3272 11:07:35.519009
3273 11:07:35.519346 ==
3274 11:07:35.522554 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 11:07:35.525556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 11:07:35.526139 ==
3277 11:07:35.526652 RX Vref Scan: 1
3278 11:07:35.528902
3279 11:07:35.529331 Set Vref Range= 32 -> 127
3280 11:07:35.529666
3281 11:07:35.532029 RX Vref 32 -> 127, step: 1
3282 11:07:35.532458
3283 11:07:35.535219 RX Delay -5 -> 252, step: 4
3284 11:07:35.535649
3285 11:07:35.538944 Set Vref, RX VrefLevel [Byte0]: 32
3286 11:07:35.541893 [Byte1]: 32
3287 11:07:35.542347
3288 11:07:35.545927 Set Vref, RX VrefLevel [Byte0]: 33
3289 11:07:35.548784 [Byte1]: 33
3290 11:07:35.552023
3291 11:07:35.552528 Set Vref, RX VrefLevel [Byte0]: 34
3292 11:07:35.555734 [Byte1]: 34
3293 11:07:35.559961
3294 11:07:35.560447 Set Vref, RX VrefLevel [Byte0]: 35
3295 11:07:35.563052 [Byte1]: 35
3296 11:07:35.567843
3297 11:07:35.568342 Set Vref, RX VrefLevel [Byte0]: 36
3298 11:07:35.571171 [Byte1]: 36
3299 11:07:35.575480
3300 11:07:35.575964 Set Vref, RX VrefLevel [Byte0]: 37
3301 11:07:35.578735 [Byte1]: 37
3302 11:07:35.583542
3303 11:07:35.584087 Set Vref, RX VrefLevel [Byte0]: 38
3304 11:07:35.586794 [Byte1]: 38
3305 11:07:35.591116
3306 11:07:35.591539 Set Vref, RX VrefLevel [Byte0]: 39
3307 11:07:35.594291 [Byte1]: 39
3308 11:07:35.599285
3309 11:07:35.599672 Set Vref, RX VrefLevel [Byte0]: 40
3310 11:07:35.602208 [Byte1]: 40
3311 11:07:35.607232
3312 11:07:35.607537 Set Vref, RX VrefLevel [Byte0]: 41
3313 11:07:35.610362 [Byte1]: 41
3314 11:07:35.615016
3315 11:07:35.615373 Set Vref, RX VrefLevel [Byte0]: 42
3316 11:07:35.617938 [Byte1]: 42
3317 11:07:35.622700
3318 11:07:35.622970 Set Vref, RX VrefLevel [Byte0]: 43
3319 11:07:35.625699 [Byte1]: 43
3320 11:07:35.630411
3321 11:07:35.630700 Set Vref, RX VrefLevel [Byte0]: 44
3322 11:07:35.634030 [Byte1]: 44
3323 11:07:35.638274
3324 11:07:35.638704 Set Vref, RX VrefLevel [Byte0]: 45
3325 11:07:35.641544 [Byte1]: 45
3326 11:07:35.645887
3327 11:07:35.646229 Set Vref, RX VrefLevel [Byte0]: 46
3328 11:07:35.649239 [Byte1]: 46
3329 11:07:35.653827
3330 11:07:35.654128 Set Vref, RX VrefLevel [Byte0]: 47
3331 11:07:35.657251 [Byte1]: 47
3332 11:07:35.661822
3333 11:07:35.662177 Set Vref, RX VrefLevel [Byte0]: 48
3334 11:07:35.665399 [Byte1]: 48
3335 11:07:35.669748
3336 11:07:35.670330 Set Vref, RX VrefLevel [Byte0]: 49
3337 11:07:35.673415 [Byte1]: 49
3338 11:07:35.677452
3339 11:07:35.677818 Set Vref, RX VrefLevel [Byte0]: 50
3340 11:07:35.680658 [Byte1]: 50
3341 11:07:35.685308
3342 11:07:35.685758 Set Vref, RX VrefLevel [Byte0]: 51
3343 11:07:35.689060 [Byte1]: 51
3344 11:07:35.693755
3345 11:07:35.694277 Set Vref, RX VrefLevel [Byte0]: 52
3346 11:07:35.696403 [Byte1]: 52
3347 11:07:35.701250
3348 11:07:35.701717 Set Vref, RX VrefLevel [Byte0]: 53
3349 11:07:35.704558 [Byte1]: 53
3350 11:07:35.708945
3351 11:07:35.709442 Set Vref, RX VrefLevel [Byte0]: 54
3352 11:07:35.712419 [Byte1]: 54
3353 11:07:35.716977
3354 11:07:35.717373 Set Vref, RX VrefLevel [Byte0]: 55
3355 11:07:35.720297 [Byte1]: 55
3356 11:07:35.725067
3357 11:07:35.725504 Set Vref, RX VrefLevel [Byte0]: 56
3358 11:07:35.728237 [Byte1]: 56
3359 11:07:35.732740
3360 11:07:35.733239 Set Vref, RX VrefLevel [Byte0]: 57
3361 11:07:35.735779 [Byte1]: 57
3362 11:07:35.740367
3363 11:07:35.740867 Set Vref, RX VrefLevel [Byte0]: 58
3364 11:07:35.743452 [Byte1]: 58
3365 11:07:35.748114
3366 11:07:35.748539 Set Vref, RX VrefLevel [Byte0]: 59
3367 11:07:35.751459 [Byte1]: 59
3368 11:07:35.756638
3369 11:07:35.757200 Set Vref, RX VrefLevel [Byte0]: 60
3370 11:07:35.759526 [Byte1]: 60
3371 11:07:35.763772
3372 11:07:35.764255 Set Vref, RX VrefLevel [Byte0]: 61
3373 11:07:35.767410 [Byte1]: 61
3374 11:07:35.772078
3375 11:07:35.772576 Set Vref, RX VrefLevel [Byte0]: 62
3376 11:07:35.775067 [Byte1]: 62
3377 11:07:35.779898
3378 11:07:35.780328 Set Vref, RX VrefLevel [Byte0]: 63
3379 11:07:35.783006 [Byte1]: 63
3380 11:07:35.787356
3381 11:07:35.787858 Set Vref, RX VrefLevel [Byte0]: 64
3382 11:07:35.790499 [Byte1]: 64
3383 11:07:35.795286
3384 11:07:35.795798 Set Vref, RX VrefLevel [Byte0]: 65
3385 11:07:35.799416 [Byte1]: 65
3386 11:07:35.803935
3387 11:07:35.804443 Set Vref, RX VrefLevel [Byte0]: 66
3388 11:07:35.807249 [Byte1]: 66
3389 11:07:35.811500
3390 11:07:35.812027 Set Vref, RX VrefLevel [Byte0]: 67
3391 11:07:35.814438 [Byte1]: 67
3392 11:07:35.818838
3393 11:07:35.819340 Set Vref, RX VrefLevel [Byte0]: 68
3394 11:07:35.822809 [Byte1]: 68
3395 11:07:35.826565
3396 11:07:35.826992 Final RX Vref Byte 0 = 55 to rank0
3397 11:07:35.829976 Final RX Vref Byte 1 = 52 to rank0
3398 11:07:35.833671 Final RX Vref Byte 0 = 55 to rank1
3399 11:07:35.836896 Final RX Vref Byte 1 = 52 to rank1==
3400 11:07:35.839982 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 11:07:35.846886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 11:07:35.847400 ==
3403 11:07:35.847793 DQS Delay:
3404 11:07:35.848110 DQS0 = 0, DQS1 = 0
3405 11:07:35.850371 DQM Delay:
3406 11:07:35.850889 DQM0 = 120, DQM1 = 117
3407 11:07:35.853382 DQ Delay:
3408 11:07:35.856671 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3409 11:07:35.859988 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3410 11:07:35.863043 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3411 11:07:35.866449 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3412 11:07:35.866877
3413 11:07:35.867206
3414 11:07:35.873500 [DQSOSCAuto] RK0, (LSB)MR18= 0x214, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3415 11:07:35.876760 CH1 RK0: MR19=404, MR18=214
3416 11:07:35.883438 CH1_RK0: MR19=0x404, MR18=0x214, DQSOSC=402, MR23=63, INC=40, DEC=27
3417 11:07:35.883920
3418 11:07:35.886844 ----->DramcWriteLeveling(PI) begin...
3419 11:07:35.887375 ==
3420 11:07:35.890388 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 11:07:35.893741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 11:07:35.894240 ==
3423 11:07:35.897031 Write leveling (Byte 0): 27 => 27
3424 11:07:35.900148 Write leveling (Byte 1): 29 => 29
3425 11:07:35.903732 DramcWriteLeveling(PI) end<-----
3426 11:07:35.904159
3427 11:07:35.904486 ==
3428 11:07:35.906993 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 11:07:35.913991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 11:07:35.914566 ==
3431 11:07:35.914905 [Gating] SW mode calibration
3432 11:07:35.924185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 11:07:35.927238 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 11:07:35.930692 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 11:07:35.936693 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 11:07:35.939798 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 11:07:35.943572 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 11:07:35.950277 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 11:07:35.953035 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3440 11:07:35.956876 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (1 0) (0 1)
3441 11:07:35.963236 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3442 11:07:35.966634 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 11:07:35.969995 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 11:07:35.976486 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 11:07:35.979770 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 11:07:35.983102 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 11:07:35.989561 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3448 11:07:35.993175 1 0 24 | B1->B0 | 4444 2929 | 0 0 | (0 0) (0 0)
3449 11:07:35.996337 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3450 11:07:36.002899 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 11:07:36.006780 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 11:07:36.009720 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 11:07:36.016052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 11:07:36.019670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 11:07:36.023367 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3456 11:07:36.029661 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3457 11:07:36.033203 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3458 11:07:36.036656 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 11:07:36.043029 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 11:07:36.045858 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:07:36.049575 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:07:36.056584 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:07:36.059875 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:07:36.062733 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:07:36.065959 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:07:36.072758 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:07:36.076283 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:07:36.079416 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:07:36.085712 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:07:36.089940 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:07:36.092733 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3472 11:07:36.099413 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3473 11:07:36.102884 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3474 11:07:36.106039 Total UI for P1: 0, mck2ui 16
3475 11:07:36.109691 best dqsien dly found for B1: ( 1, 3, 22)
3476 11:07:36.112676 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 11:07:36.115891 Total UI for P1: 0, mck2ui 16
3478 11:07:36.119712 best dqsien dly found for B0: ( 1, 3, 26)
3479 11:07:36.122187 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3480 11:07:36.126168 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3481 11:07:36.126617
3482 11:07:36.132644 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3483 11:07:36.136420 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3484 11:07:36.136985 [Gating] SW calibration Done
3485 11:07:36.139105 ==
3486 11:07:36.142556 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 11:07:36.145885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 11:07:36.146393 ==
3489 11:07:36.146730 RX Vref Scan: 0
3490 11:07:36.147038
3491 11:07:36.149262 RX Vref 0 -> 0, step: 1
3492 11:07:36.149760
3493 11:07:36.152366 RX Delay -40 -> 252, step: 8
3494 11:07:36.155796 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3495 11:07:36.159396 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3496 11:07:36.165883 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3497 11:07:36.168995 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3498 11:07:36.172169 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3499 11:07:36.175912 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 11:07:36.179167 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3501 11:07:36.186248 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3502 11:07:36.189634 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3503 11:07:36.192449 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3504 11:07:36.195227 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3505 11:07:36.198633 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3506 11:07:36.205494 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3507 11:07:36.208778 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3508 11:07:36.212104 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3509 11:07:36.215791 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3510 11:07:36.216259 ==
3511 11:07:36.219022 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 11:07:36.225647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 11:07:36.226181 ==
3514 11:07:36.226521 DQS Delay:
3515 11:07:36.228552 DQS0 = 0, DQS1 = 0
3516 11:07:36.228982 DQM Delay:
3517 11:07:36.229427 DQM0 = 120, DQM1 = 117
3518 11:07:36.232224 DQ Delay:
3519 11:07:36.235227 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3520 11:07:36.238711 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3521 11:07:36.242356 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3522 11:07:36.245243 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3523 11:07:36.245675
3524 11:07:36.246038
3525 11:07:36.246351 ==
3526 11:07:36.248719 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 11:07:36.252378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 11:07:36.255286 ==
3529 11:07:36.255720
3530 11:07:36.256055
3531 11:07:36.256362 TX Vref Scan disable
3532 11:07:36.259098 == TX Byte 0 ==
3533 11:07:36.261964 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3534 11:07:36.265270 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3535 11:07:36.268710 == TX Byte 1 ==
3536 11:07:36.271878 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3537 11:07:36.275279 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3538 11:07:36.275712 ==
3539 11:07:36.278790 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 11:07:36.285071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 11:07:36.285508 ==
3542 11:07:36.296096 TX Vref=22, minBit 9, minWin=25, winSum=421
3543 11:07:36.299169 TX Vref=24, minBit 0, minWin=26, winSum=427
3544 11:07:36.302446 TX Vref=26, minBit 3, minWin=26, winSum=432
3545 11:07:36.305946 TX Vref=28, minBit 2, minWin=26, winSum=432
3546 11:07:36.309195 TX Vref=30, minBit 1, minWin=27, winSum=436
3547 11:07:36.315835 TX Vref=32, minBit 9, minWin=26, winSum=435
3548 11:07:36.319375 [TxChooseVref] Worse bit 1, Min win 27, Win sum 436, Final Vref 30
3549 11:07:36.319810
3550 11:07:36.322352 Final TX Range 1 Vref 30
3551 11:07:36.322788
3552 11:07:36.323119 ==
3553 11:07:36.326099 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 11:07:36.329369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 11:07:36.329815 ==
3556 11:07:36.330211
3557 11:07:36.332709
3558 11:07:36.333140 TX Vref Scan disable
3559 11:07:36.335672 == TX Byte 0 ==
3560 11:07:36.338980 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 11:07:36.342159 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 11:07:36.345720 == TX Byte 1 ==
3563 11:07:36.349129 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 11:07:36.352124 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 11:07:36.355304
3566 11:07:36.355541 [DATLAT]
3567 11:07:36.355716 Freq=1200, CH1 RK1
3568 11:07:36.355880
3569 11:07:36.359250 DATLAT Default: 0xd
3570 11:07:36.359435 0, 0xFFFF, sum = 0
3571 11:07:36.362372 1, 0xFFFF, sum = 0
3572 11:07:36.362528 2, 0xFFFF, sum = 0
3573 11:07:36.365616 3, 0xFFFF, sum = 0
3574 11:07:36.365785 4, 0xFFFF, sum = 0
3575 11:07:36.368661 5, 0xFFFF, sum = 0
3576 11:07:36.368802 6, 0xFFFF, sum = 0
3577 11:07:36.371869 7, 0xFFFF, sum = 0
3578 11:07:36.375342 8, 0xFFFF, sum = 0
3579 11:07:36.375481 9, 0xFFFF, sum = 0
3580 11:07:36.378634 10, 0xFFFF, sum = 0
3581 11:07:36.378739 11, 0xFFFF, sum = 0
3582 11:07:36.382105 12, 0x0, sum = 1
3583 11:07:36.382246 13, 0x0, sum = 2
3584 11:07:36.385297 14, 0x0, sum = 3
3585 11:07:36.385404 15, 0x0, sum = 4
3586 11:07:36.385501 best_step = 13
3587 11:07:36.385592
3588 11:07:36.388345 ==
3589 11:07:36.391753 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 11:07:36.395041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 11:07:36.395125 ==
3592 11:07:36.395187 RX Vref Scan: 0
3593 11:07:36.395243
3594 11:07:36.399099 RX Vref 0 -> 0, step: 1
3595 11:07:36.399525
3596 11:07:36.402557 RX Delay -5 -> 252, step: 4
3597 11:07:36.405789 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3598 11:07:36.409286 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3599 11:07:36.415771 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3600 11:07:36.419228 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3601 11:07:36.422027 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3602 11:07:36.425663 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3603 11:07:36.428924 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3604 11:07:36.436011 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3605 11:07:36.439033 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3606 11:07:36.442529 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3607 11:07:36.445621 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3608 11:07:36.449170 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3609 11:07:36.455691 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3610 11:07:36.459551 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3611 11:07:36.462619 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3612 11:07:36.466308 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3613 11:07:36.466828 ==
3614 11:07:36.469041 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:07:36.476120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:07:36.476582 ==
3617 11:07:36.476951 DQS Delay:
3618 11:07:36.479304 DQS0 = 0, DQS1 = 0
3619 11:07:36.479732 DQM Delay:
3620 11:07:36.480105 DQM0 = 120, DQM1 = 118
3621 11:07:36.481918 DQ Delay:
3622 11:07:36.485719 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3623 11:07:36.488852 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3624 11:07:36.492218 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3625 11:07:36.495299 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3626 11:07:36.495686
3627 11:07:36.495986
3628 11:07:36.505738 [DQSOSCAuto] RK1, (LSB)MR18= 0x16f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 401 ps
3629 11:07:36.506316 CH1 RK1: MR19=403, MR18=16F3
3630 11:07:36.512435 CH1_RK1: MR19=0x403, MR18=0x16F3, DQSOSC=401, MR23=63, INC=40, DEC=27
3631 11:07:36.515302 [RxdqsGatingPostProcess] freq 1200
3632 11:07:36.521850 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 11:07:36.525635 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 11:07:36.528537 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 11:07:36.532067 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 11:07:36.535407 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 11:07:36.538973 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 11:07:36.539476 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 11:07:36.542239 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 11:07:36.545121 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 11:07:36.548620 Pre-setting of DQS Precalculation
3642 11:07:36.555233 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 11:07:36.562322 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 11:07:36.568899 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 11:07:36.569389
3646 11:07:36.569695
3647 11:07:36.571817 [Calibration Summary] 2400 Mbps
3648 11:07:36.572206 CH 0, Rank 0
3649 11:07:36.575543 SW Impedance : PASS
3650 11:07:36.578528 DUTY Scan : NO K
3651 11:07:36.578921 ZQ Calibration : PASS
3652 11:07:36.581725 Jitter Meter : NO K
3653 11:07:36.585142 CBT Training : PASS
3654 11:07:36.585532 Write leveling : PASS
3655 11:07:36.588417 RX DQS gating : PASS
3656 11:07:36.591907 RX DQ/DQS(RDDQC) : PASS
3657 11:07:36.592299 TX DQ/DQS : PASS
3658 11:07:36.595142 RX DATLAT : PASS
3659 11:07:36.598372 RX DQ/DQS(Engine): PASS
3660 11:07:36.598763 TX OE : NO K
3661 11:07:36.602098 All Pass.
3662 11:07:36.602571
3663 11:07:36.602881 CH 0, Rank 1
3664 11:07:36.605086 SW Impedance : PASS
3665 11:07:36.605479 DUTY Scan : NO K
3666 11:07:36.608997 ZQ Calibration : PASS
3667 11:07:36.611953 Jitter Meter : NO K
3668 11:07:36.612349 CBT Training : PASS
3669 11:07:36.615628 Write leveling : PASS
3670 11:07:36.616135 RX DQS gating : PASS
3671 11:07:36.618620 RX DQ/DQS(RDDQC) : PASS
3672 11:07:36.622531 TX DQ/DQS : PASS
3673 11:07:36.623048 RX DATLAT : PASS
3674 11:07:36.625521 RX DQ/DQS(Engine): PASS
3675 11:07:36.628755 TX OE : NO K
3676 11:07:36.629339 All Pass.
3677 11:07:36.629869
3678 11:07:36.630459 CH 1, Rank 0
3679 11:07:36.631708 SW Impedance : PASS
3680 11:07:36.635426 DUTY Scan : NO K
3681 11:07:36.636016 ZQ Calibration : PASS
3682 11:07:36.638842 Jitter Meter : NO K
3683 11:07:36.642257 CBT Training : PASS
3684 11:07:36.642761 Write leveling : PASS
3685 11:07:36.645668 RX DQS gating : PASS
3686 11:07:36.648646 RX DQ/DQS(RDDQC) : PASS
3687 11:07:36.649148 TX DQ/DQS : PASS
3688 11:07:36.652264 RX DATLAT : PASS
3689 11:07:36.654791 RX DQ/DQS(Engine): PASS
3690 11:07:36.655220 TX OE : NO K
3691 11:07:36.658569 All Pass.
3692 11:07:36.659077
3693 11:07:36.659412 CH 1, Rank 1
3694 11:07:36.661524 SW Impedance : PASS
3695 11:07:36.661985 DUTY Scan : NO K
3696 11:07:36.665199 ZQ Calibration : PASS
3697 11:07:36.668722 Jitter Meter : NO K
3698 11:07:36.669229 CBT Training : PASS
3699 11:07:36.672530 Write leveling : PASS
3700 11:07:36.674529 RX DQS gating : PASS
3701 11:07:36.674958 RX DQ/DQS(RDDQC) : PASS
3702 11:07:36.677939 TX DQ/DQS : PASS
3703 11:07:36.678464 RX DATLAT : PASS
3704 11:07:36.681621 RX DQ/DQS(Engine): PASS
3705 11:07:36.684822 TX OE : NO K
3706 11:07:36.685326 All Pass.
3707 11:07:36.685655
3708 11:07:36.688089 DramC Write-DBI off
3709 11:07:36.688477 PER_BANK_REFRESH: Hybrid Mode
3710 11:07:36.691628 TX_TRACKING: ON
3711 11:07:36.701189 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 11:07:36.704579 [FAST_K] Save calibration result to emmc
3713 11:07:36.708458 dramc_set_vcore_voltage set vcore to 650000
3714 11:07:36.708879 Read voltage for 600, 5
3715 11:07:36.711592 Vio18 = 0
3716 11:07:36.711999 Vcore = 650000
3717 11:07:36.712330 Vdram = 0
3718 11:07:36.715070 Vddq = 0
3719 11:07:36.715730 Vmddr = 0
3720 11:07:36.718142 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 11:07:36.725053 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 11:07:36.727942 MEM_TYPE=3, freq_sel=19
3723 11:07:36.731125 sv_algorithm_assistance_LP4_1600
3724 11:07:36.734665 ============ PULL DRAM RESETB DOWN ============
3725 11:07:36.738389 ========== PULL DRAM RESETB DOWN end =========
3726 11:07:36.744529 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 11:07:36.747798 ===================================
3728 11:07:36.748196 LPDDR4 DRAM CONFIGURATION
3729 11:07:36.751109 ===================================
3730 11:07:36.754440 EX_ROW_EN[0] = 0x0
3731 11:07:36.754833 EX_ROW_EN[1] = 0x0
3732 11:07:36.757929 LP4Y_EN = 0x0
3733 11:07:36.758411 WORK_FSP = 0x0
3734 11:07:36.761540 WL = 0x2
3735 11:07:36.764745 RL = 0x2
3736 11:07:36.765132 BL = 0x2
3737 11:07:36.768024 RPST = 0x0
3738 11:07:36.768413 RD_PRE = 0x0
3739 11:07:36.771525 WR_PRE = 0x1
3740 11:07:36.771915 WR_PST = 0x0
3741 11:07:36.774368 DBI_WR = 0x0
3742 11:07:36.774647 DBI_RD = 0x0
3743 11:07:36.777925 OTF = 0x1
3744 11:07:36.781169 ===================================
3745 11:07:36.784712 ===================================
3746 11:07:36.784991 ANA top config
3747 11:07:36.787778 ===================================
3748 11:07:36.791035 DLL_ASYNC_EN = 0
3749 11:07:36.794904 ALL_SLAVE_EN = 1
3750 11:07:36.795257 NEW_RANK_MODE = 1
3751 11:07:36.797926 DLL_IDLE_MODE = 1
3752 11:07:36.801327 LP45_APHY_COMB_EN = 1
3753 11:07:36.804562 TX_ODT_DIS = 1
3754 11:07:36.805084 NEW_8X_MODE = 1
3755 11:07:36.808214 ===================================
3756 11:07:36.811677 ===================================
3757 11:07:36.814698 data_rate = 1200
3758 11:07:36.818230 CKR = 1
3759 11:07:36.821466 DQ_P2S_RATIO = 8
3760 11:07:36.824499 ===================================
3761 11:07:36.828146 CA_P2S_RATIO = 8
3762 11:07:36.830892 DQ_CA_OPEN = 0
3763 11:07:36.831285 DQ_SEMI_OPEN = 0
3764 11:07:36.834604 CA_SEMI_OPEN = 0
3765 11:07:36.838692 CA_FULL_RATE = 0
3766 11:07:36.841152 DQ_CKDIV4_EN = 1
3767 11:07:36.844225 CA_CKDIV4_EN = 1
3768 11:07:36.847743 CA_PREDIV_EN = 0
3769 11:07:36.848131 PH8_DLY = 0
3770 11:07:36.850852 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 11:07:36.854538 DQ_AAMCK_DIV = 4
3772 11:07:36.858115 CA_AAMCK_DIV = 4
3773 11:07:36.861279 CA_ADMCK_DIV = 4
3774 11:07:36.864734 DQ_TRACK_CA_EN = 0
3775 11:07:36.865132 CA_PICK = 600
3776 11:07:36.867728 CA_MCKIO = 600
3777 11:07:36.870968 MCKIO_SEMI = 0
3778 11:07:36.874379 PLL_FREQ = 2288
3779 11:07:36.878194 DQ_UI_PI_RATIO = 32
3780 11:07:36.881210 CA_UI_PI_RATIO = 0
3781 11:07:36.884369 ===================================
3782 11:07:36.887793 ===================================
3783 11:07:36.888190 memory_type:LPDDR4
3784 11:07:36.890983 GP_NUM : 10
3785 11:07:36.894837 SRAM_EN : 1
3786 11:07:36.895327 MD32_EN : 0
3787 11:07:36.898085 ===================================
3788 11:07:36.901373 [ANA_INIT] >>>>>>>>>>>>>>
3789 11:07:36.904433 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 11:07:36.907962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 11:07:36.911021 ===================================
3792 11:07:36.914718 data_rate = 1200,PCW = 0X5800
3793 11:07:36.917553 ===================================
3794 11:07:36.921131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 11:07:36.924408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 11:07:36.930946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 11:07:36.934230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 11:07:36.937584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 11:07:36.941468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 11:07:36.944085 [ANA_INIT] flow start
3801 11:07:36.947634 [ANA_INIT] PLL >>>>>>>>
3802 11:07:36.948066 [ANA_INIT] PLL <<<<<<<<
3803 11:07:36.950681 [ANA_INIT] MIDPI >>>>>>>>
3804 11:07:36.954102 [ANA_INIT] MIDPI <<<<<<<<
3805 11:07:36.958210 [ANA_INIT] DLL >>>>>>>>
3806 11:07:36.958639 [ANA_INIT] flow end
3807 11:07:36.961355 ============ LP4 DIFF to SE enter ============
3808 11:07:36.967895 ============ LP4 DIFF to SE exit ============
3809 11:07:36.968392 [ANA_INIT] <<<<<<<<<<<<<
3810 11:07:36.970818 [Flow] Enable top DCM control >>>>>
3811 11:07:36.973902 [Flow] Enable top DCM control <<<<<
3812 11:07:36.977544 Enable DLL master slave shuffle
3813 11:07:36.984239 ==============================================================
3814 11:07:36.984673 Gating Mode config
3815 11:07:36.990532 ==============================================================
3816 11:07:36.993971 Config description:
3817 11:07:37.003813 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 11:07:37.010567 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 11:07:37.013896 SELPH_MODE 0: By rank 1: By Phase
3820 11:07:37.020791 ==============================================================
3821 11:07:37.023978 GAT_TRACK_EN = 1
3822 11:07:37.024415 RX_GATING_MODE = 2
3823 11:07:37.027034 RX_GATING_TRACK_MODE = 2
3824 11:07:37.030269 SELPH_MODE = 1
3825 11:07:37.033552 PICG_EARLY_EN = 1
3826 11:07:37.037220 VALID_LAT_VALUE = 1
3827 11:07:37.043666 ==============================================================
3828 11:07:37.047450 Enter into Gating configuration >>>>
3829 11:07:37.050619 Exit from Gating configuration <<<<
3830 11:07:37.054554 Enter into DVFS_PRE_config >>>>>
3831 11:07:37.064058 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 11:07:37.067266 Exit from DVFS_PRE_config <<<<<
3833 11:07:37.070770 Enter into PICG configuration >>>>
3834 11:07:37.073670 Exit from PICG configuration <<<<
3835 11:07:37.077000 [RX_INPUT] configuration >>>>>
3836 11:07:37.080566 [RX_INPUT] configuration <<<<<
3837 11:07:37.084051 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 11:07:37.090801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 11:07:37.097383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 11:07:37.100374 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 11:07:37.107247 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 11:07:37.114194 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 11:07:37.117512 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 11:07:37.120491 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 11:07:37.126766 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 11:07:37.130680 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 11:07:37.134320 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 11:07:37.140131 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 11:07:37.143236 ===================================
3850 11:07:37.143664 LPDDR4 DRAM CONFIGURATION
3851 11:07:37.147290 ===================================
3852 11:07:37.150533 EX_ROW_EN[0] = 0x0
3853 11:07:37.153460 EX_ROW_EN[1] = 0x0
3854 11:07:37.153960 LP4Y_EN = 0x0
3855 11:07:37.156544 WORK_FSP = 0x0
3856 11:07:37.156965 WL = 0x2
3857 11:07:37.160516 RL = 0x2
3858 11:07:37.161015 BL = 0x2
3859 11:07:37.163375 RPST = 0x0
3860 11:07:37.163795 RD_PRE = 0x0
3861 11:07:37.166661 WR_PRE = 0x1
3862 11:07:37.167086 WR_PST = 0x0
3863 11:07:37.170199 DBI_WR = 0x0
3864 11:07:37.170686 DBI_RD = 0x0
3865 11:07:37.173879 OTF = 0x1
3866 11:07:37.176885 ===================================
3867 11:07:37.181018 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 11:07:37.183475 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 11:07:37.189776 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 11:07:37.193196 ===================================
3871 11:07:37.193591 LPDDR4 DRAM CONFIGURATION
3872 11:07:37.196523 ===================================
3873 11:07:37.200529 EX_ROW_EN[0] = 0x10
3874 11:07:37.200991 EX_ROW_EN[1] = 0x0
3875 11:07:37.203655 LP4Y_EN = 0x0
3876 11:07:37.206928 WORK_FSP = 0x0
3877 11:07:37.207337 WL = 0x2
3878 11:07:37.210100 RL = 0x2
3879 11:07:37.210486 BL = 0x2
3880 11:07:37.213020 RPST = 0x0
3881 11:07:37.213445 RD_PRE = 0x0
3882 11:07:37.216568 WR_PRE = 0x1
3883 11:07:37.216951 WR_PST = 0x0
3884 11:07:37.220017 DBI_WR = 0x0
3885 11:07:37.220422 DBI_RD = 0x0
3886 11:07:37.222973 OTF = 0x1
3887 11:07:37.226877 ===================================
3888 11:07:37.230089 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 11:07:37.235843 nWR fixed to 30
3890 11:07:37.238970 [ModeRegInit_LP4] CH0 RK0
3891 11:07:37.239397 [ModeRegInit_LP4] CH0 RK1
3892 11:07:37.242108 [ModeRegInit_LP4] CH1 RK0
3893 11:07:37.245448 [ModeRegInit_LP4] CH1 RK1
3894 11:07:37.245874 match AC timing 17
3895 11:07:37.252210 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 11:07:37.255993 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 11:07:37.258966 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 11:07:37.265509 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 11:07:37.268930 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 11:07:37.269449 ==
3901 11:07:37.272138 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 11:07:37.275777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 11:07:37.276245 ==
3904 11:07:37.281803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 11:07:37.289006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3906 11:07:37.292492 [CA 0] Center 35 (5~66) winsize 62
3907 11:07:37.295645 [CA 1] Center 35 (5~66) winsize 62
3908 11:07:37.298993 [CA 2] Center 33 (3~64) winsize 62
3909 11:07:37.302860 [CA 3] Center 33 (2~64) winsize 63
3910 11:07:37.305407 [CA 4] Center 33 (2~64) winsize 63
3911 11:07:37.309050 [CA 5] Center 32 (2~63) winsize 62
3912 11:07:37.309568
3913 11:07:37.312222 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3914 11:07:37.312667
3915 11:07:37.315199 [CATrainingPosCal] consider 1 rank data
3916 11:07:37.318616 u2DelayCellTimex100 = 270/100 ps
3917 11:07:37.321861 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3918 11:07:37.325027 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3919 11:07:37.328422 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3920 11:07:37.331564 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3921 11:07:37.334516 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 11:07:37.341716 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3923 11:07:37.342228
3924 11:07:37.344616 CA PerBit enable=1, Macro0, CA PI delay=32
3925 11:07:37.345193
3926 11:07:37.347940 [CBTSetCACLKResult] CA Dly = 32
3927 11:07:37.348384 CS Dly: 4 (0~35)
3928 11:07:37.348824 ==
3929 11:07:37.351913 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 11:07:37.354832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 11:07:37.358331 ==
3932 11:07:37.362042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 11:07:37.368453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 11:07:37.371717 [CA 0] Center 35 (5~66) winsize 62
3935 11:07:37.375337 [CA 1] Center 35 (5~66) winsize 62
3936 11:07:37.378556 [CA 2] Center 34 (3~65) winsize 63
3937 11:07:37.381428 [CA 3] Center 33 (3~64) winsize 62
3938 11:07:37.385008 [CA 4] Center 32 (2~63) winsize 62
3939 11:07:37.388356 [CA 5] Center 32 (2~63) winsize 62
3940 11:07:37.388787
3941 11:07:37.391497 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 11:07:37.392009
3943 11:07:37.394840 [CATrainingPosCal] consider 2 rank data
3944 11:07:37.398179 u2DelayCellTimex100 = 270/100 ps
3945 11:07:37.402000 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 11:07:37.404772 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 11:07:37.408033 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3948 11:07:37.411192 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3949 11:07:37.417832 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3950 11:07:37.421241 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3951 11:07:37.421684
3952 11:07:37.424365 CA PerBit enable=1, Macro0, CA PI delay=32
3953 11:07:37.424810
3954 11:07:37.428027 [CBTSetCACLKResult] CA Dly = 32
3955 11:07:37.428435 CS Dly: 4 (0~36)
3956 11:07:37.428833
3957 11:07:37.431057 ----->DramcWriteLeveling(PI) begin...
3958 11:07:37.431468 ==
3959 11:07:37.434154 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 11:07:37.441027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 11:07:37.441437 ==
3962 11:07:37.444387 Write leveling (Byte 0): 34 => 34
3963 11:07:37.447785 Write leveling (Byte 1): 31 => 31
3964 11:07:37.448178 DramcWriteLeveling(PI) end<-----
3965 11:07:37.448481
3966 11:07:37.450934 ==
3967 11:07:37.454550 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 11:07:37.457603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 11:07:37.458001 ==
3970 11:07:37.460842 [Gating] SW mode calibration
3971 11:07:37.467652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 11:07:37.470989 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 11:07:37.477672 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 11:07:37.480772 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 11:07:37.483937 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 11:07:37.490703 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
3977 11:07:37.494174 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
3978 11:07:37.497450 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 11:07:37.504460 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 11:07:37.506971 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:07:37.510557 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 11:07:37.517477 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 11:07:37.520907 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 11:07:37.523939 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
3985 11:07:37.530497 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3986 11:07:37.534365 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 11:07:37.536883 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 11:07:37.543557 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:07:37.546847 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 11:07:37.550352 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 11:07:37.557335 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:07:37.560657 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3993 11:07:37.563721 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3994 11:07:37.570126 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:07:37.574095 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:07:37.577265 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:07:37.583730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:07:37.586840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:07:37.590320 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:07:37.596897 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:07:37.599887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:07:37.603269 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:07:37.610156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:07:37.613595 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:07:37.617008 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:07:37.620129 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:07:37.626906 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:07:37.629943 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4009 11:07:37.633187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4010 11:07:37.637448 Total UI for P1: 0, mck2ui 16
4011 11:07:37.640184 best dqsien dly found for B0: ( 0, 13, 12)
4012 11:07:37.646952 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 11:07:37.650090 Total UI for P1: 0, mck2ui 16
4014 11:07:37.653410 best dqsien dly found for B1: ( 0, 13, 16)
4015 11:07:37.657099 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4016 11:07:37.660083 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4017 11:07:37.660581
4018 11:07:37.663045 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4019 11:07:37.666535 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4020 11:07:37.670219 [Gating] SW calibration Done
4021 11:07:37.670644 ==
4022 11:07:37.673569 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 11:07:37.676497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 11:07:37.676924 ==
4025 11:07:37.679613 RX Vref Scan: 0
4026 11:07:37.680111
4027 11:07:37.680444 RX Vref 0 -> 0, step: 1
4028 11:07:37.683134
4029 11:07:37.683644 RX Delay -230 -> 252, step: 16
4030 11:07:37.690285 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4031 11:07:37.693978 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4032 11:07:37.696659 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 11:07:37.699978 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4034 11:07:37.703592 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4035 11:07:37.709725 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4036 11:07:37.713130 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4037 11:07:37.716186 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4038 11:07:37.720415 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4039 11:07:37.727064 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4040 11:07:37.730077 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4041 11:07:37.733285 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4042 11:07:37.736268 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4043 11:07:37.743161 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4044 11:07:37.746722 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4045 11:07:37.749876 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4046 11:07:37.750379 ==
4047 11:07:37.752930 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 11:07:37.756565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 11:07:37.757161 ==
4050 11:07:37.759591 DQS Delay:
4051 11:07:37.759977 DQS0 = 0, DQS1 = 0
4052 11:07:37.762712 DQM Delay:
4053 11:07:37.763447 DQM0 = 52, DQM1 = 43
4054 11:07:37.764389 DQ Delay:
4055 11:07:37.766415 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4056 11:07:37.769442 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4057 11:07:37.772624 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4058 11:07:37.776336 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4059 11:07:37.776796
4060 11:07:37.777341
4061 11:07:37.779472 ==
4062 11:07:37.782620 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 11:07:37.786434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 11:07:37.786949 ==
4065 11:07:37.787384
4066 11:07:37.787795
4067 11:07:37.789589 TX Vref Scan disable
4068 11:07:37.790112 == TX Byte 0 ==
4069 11:07:37.792875 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4070 11:07:37.799261 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4071 11:07:37.799831 == TX Byte 1 ==
4072 11:07:37.802862 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4073 11:07:37.809230 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4074 11:07:37.809735 ==
4075 11:07:37.812585 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 11:07:37.816400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 11:07:37.816791 ==
4078 11:07:37.817090
4079 11:07:37.817484
4080 11:07:37.819645 TX Vref Scan disable
4081 11:07:37.822914 == TX Byte 0 ==
4082 11:07:37.825973 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4083 11:07:37.829617 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4084 11:07:37.832438 == TX Byte 1 ==
4085 11:07:37.836304 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4086 11:07:37.839422 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4087 11:07:37.839820
4088 11:07:37.843113 [DATLAT]
4089 11:07:37.843501 Freq=600, CH0 RK0
4090 11:07:37.843805
4091 11:07:37.846234 DATLAT Default: 0x9
4092 11:07:37.846630 0, 0xFFFF, sum = 0
4093 11:07:37.849340 1, 0xFFFF, sum = 0
4094 11:07:37.849735 2, 0xFFFF, sum = 0
4095 11:07:37.852910 3, 0xFFFF, sum = 0
4096 11:07:37.853344 4, 0xFFFF, sum = 0
4097 11:07:37.856140 5, 0xFFFF, sum = 0
4098 11:07:37.856577 6, 0xFFFF, sum = 0
4099 11:07:37.859257 7, 0xFFFF, sum = 0
4100 11:07:37.859655 8, 0x0, sum = 1
4101 11:07:37.862671 9, 0x0, sum = 2
4102 11:07:37.863066 10, 0x0, sum = 3
4103 11:07:37.866620 11, 0x0, sum = 4
4104 11:07:37.867088 best_step = 9
4105 11:07:37.867403
4106 11:07:37.867681 ==
4107 11:07:37.869631 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 11:07:37.873061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 11:07:37.873527 ==
4110 11:07:37.876139 RX Vref Scan: 1
4111 11:07:37.876529
4112 11:07:37.879786 RX Vref 0 -> 0, step: 1
4113 11:07:37.880172
4114 11:07:37.880471 RX Delay -179 -> 252, step: 8
4115 11:07:37.880751
4116 11:07:37.882909 Set Vref, RX VrefLevel [Byte0]: 55
4117 11:07:37.886458 [Byte1]: 54
4118 11:07:37.891334
4119 11:07:37.891718 Final RX Vref Byte 0 = 55 to rank0
4120 11:07:37.893972 Final RX Vref Byte 1 = 54 to rank0
4121 11:07:37.897997 Final RX Vref Byte 0 = 55 to rank1
4122 11:07:37.901504 Final RX Vref Byte 1 = 54 to rank1==
4123 11:07:37.904108 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 11:07:37.910777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 11:07:37.911192 ==
4126 11:07:37.911498 DQS Delay:
4127 11:07:37.911776 DQS0 = 0, DQS1 = 0
4128 11:07:37.914542 DQM Delay:
4129 11:07:37.914924 DQM0 = 54, DQM1 = 47
4130 11:07:37.918062 DQ Delay:
4131 11:07:37.920892 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4132 11:07:37.921297 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4133 11:07:37.923976 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =44
4134 11:07:37.930570 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4135 11:07:37.931051
4136 11:07:37.931387
4137 11:07:37.937505 [DQSOSCAuto] RK0, (LSB)MR18= 0x786c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
4138 11:07:37.940723 CH0 RK0: MR19=808, MR18=786C
4139 11:07:37.947315 CH0_RK0: MR19=0x808, MR18=0x786C, DQSOSC=387, MR23=63, INC=175, DEC=116
4140 11:07:37.947724
4141 11:07:37.951025 ----->DramcWriteLeveling(PI) begin...
4142 11:07:37.951439 ==
4143 11:07:37.953780 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 11:07:37.957375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 11:07:37.957760 ==
4146 11:07:37.961011 Write leveling (Byte 0): 35 => 35
4147 11:07:37.963728 Write leveling (Byte 1): 31 => 31
4148 11:07:37.967272 DramcWriteLeveling(PI) end<-----
4149 11:07:37.967747
4150 11:07:37.968151 ==
4151 11:07:37.970595 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 11:07:37.974506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 11:07:37.974895 ==
4154 11:07:37.977747 [Gating] SW mode calibration
4155 11:07:37.983980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 11:07:37.990666 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 11:07:37.994541 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 11:07:37.997467 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 11:07:38.004077 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 11:07:38.007650 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 11:07:38.010491 0 9 16 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
4162 11:07:38.017430 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 11:07:38.020992 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 11:07:38.024253 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 11:07:38.030860 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 11:07:38.033708 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 11:07:38.037009 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 11:07:38.044161 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4169 11:07:38.047252 0 10 16 | B1->B0 | 3e3e 4040 | 1 1 | (0 0) (0 0)
4170 11:07:38.050440 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 11:07:38.058060 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 11:07:38.060592 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 11:07:38.063833 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 11:07:38.070762 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:07:38.073499 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 11:07:38.077004 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4177 11:07:38.083318 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 11:07:38.086903 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 11:07:38.090413 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 11:07:38.096938 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:07:38.100390 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:07:38.104128 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:07:38.110676 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:07:38.114057 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:07:38.117201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:07:38.123257 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:07:38.127349 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:07:38.130632 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:07:38.133731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:07:38.140578 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:07:38.143424 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:07:38.146595 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4193 11:07:38.153465 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 11:07:38.156447 Total UI for P1: 0, mck2ui 16
4195 11:07:38.159984 best dqsien dly found for B0: ( 0, 13, 12)
4196 11:07:38.160387 Total UI for P1: 0, mck2ui 16
4197 11:07:38.166957 best dqsien dly found for B1: ( 0, 13, 14)
4198 11:07:38.170266 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4199 11:07:38.173469 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4200 11:07:38.173855
4201 11:07:38.176869 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4202 11:07:38.180073 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4203 11:07:38.183900 [Gating] SW calibration Done
4204 11:07:38.184292 ==
4205 11:07:38.186837 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 11:07:38.190627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 11:07:38.191106 ==
4208 11:07:38.193118 RX Vref Scan: 0
4209 11:07:38.193509
4210 11:07:38.193810 RX Vref 0 -> 0, step: 1
4211 11:07:38.196429
4212 11:07:38.196844 RX Delay -230 -> 252, step: 16
4213 11:07:38.203637 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4214 11:07:38.206687 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4215 11:07:38.210194 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4216 11:07:38.213358 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4217 11:07:38.216334 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4218 11:07:38.223545 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4219 11:07:38.226630 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4220 11:07:38.229806 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4221 11:07:38.232948 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4222 11:07:38.239421 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4223 11:07:38.243402 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4224 11:07:38.246307 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4225 11:07:38.249470 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4226 11:07:38.256797 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4227 11:07:38.259765 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4228 11:07:38.262855 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4229 11:07:38.263250 ==
4230 11:07:38.266509 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 11:07:38.270111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 11:07:38.270757 ==
4233 11:07:38.273883 DQS Delay:
4234 11:07:38.274440 DQS0 = 0, DQS1 = 0
4235 11:07:38.276687 DQM Delay:
4236 11:07:38.277150 DQM0 = 49, DQM1 = 41
4237 11:07:38.277530 DQ Delay:
4238 11:07:38.279890 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4239 11:07:38.283076 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4240 11:07:38.286530 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4241 11:07:38.289423 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4242 11:07:38.289816
4243 11:07:38.290167
4244 11:07:38.292692 ==
4245 11:07:38.296423 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 11:07:38.299624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 11:07:38.300049 ==
4248 11:07:38.300350
4249 11:07:38.300623
4250 11:07:38.303046 TX Vref Scan disable
4251 11:07:38.303460 == TX Byte 0 ==
4252 11:07:38.309431 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4253 11:07:38.312863 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4254 11:07:38.313328 == TX Byte 1 ==
4255 11:07:38.319361 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4256 11:07:38.323091 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4257 11:07:38.323508 ==
4258 11:07:38.326207 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 11:07:38.329458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 11:07:38.330175 ==
4261 11:07:38.330498
4262 11:07:38.330776
4263 11:07:38.332861 TX Vref Scan disable
4264 11:07:38.336194 == TX Byte 0 ==
4265 11:07:38.339307 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4266 11:07:38.342613 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4267 11:07:38.346045 == TX Byte 1 ==
4268 11:07:38.349227 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 11:07:38.353373 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 11:07:38.353835
4271 11:07:38.356303 [DATLAT]
4272 11:07:38.356768 Freq=600, CH0 RK1
4273 11:07:38.357071
4274 11:07:38.359434 DATLAT Default: 0x9
4275 11:07:38.359818 0, 0xFFFF, sum = 0
4276 11:07:38.362982 1, 0xFFFF, sum = 0
4277 11:07:38.363374 2, 0xFFFF, sum = 0
4278 11:07:38.365954 3, 0xFFFF, sum = 0
4279 11:07:38.366518 4, 0xFFFF, sum = 0
4280 11:07:38.369547 5, 0xFFFF, sum = 0
4281 11:07:38.369938 6, 0xFFFF, sum = 0
4282 11:07:38.372584 7, 0xFFFF, sum = 0
4283 11:07:38.372977 8, 0x0, sum = 1
4284 11:07:38.375785 9, 0x0, sum = 2
4285 11:07:38.376181 10, 0x0, sum = 3
4286 11:07:38.379201 11, 0x0, sum = 4
4287 11:07:38.379636 best_step = 9
4288 11:07:38.379940
4289 11:07:38.380280 ==
4290 11:07:38.382259 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 11:07:38.388811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 11:07:38.389201 ==
4293 11:07:38.389547 RX Vref Scan: 0
4294 11:07:38.389834
4295 11:07:38.392514 RX Vref 0 -> 0, step: 1
4296 11:07:38.393099
4297 11:07:38.395574 RX Delay -163 -> 252, step: 8
4298 11:07:38.398847 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4299 11:07:38.402307 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4300 11:07:38.408979 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4301 11:07:38.412022 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4302 11:07:38.415551 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4303 11:07:38.418824 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4304 11:07:38.422102 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4305 11:07:38.428849 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4306 11:07:38.432167 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4307 11:07:38.435506 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4308 11:07:38.438980 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4309 11:07:38.442095 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4310 11:07:38.448738 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4311 11:07:38.452545 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4312 11:07:38.455710 iDelay=197, Bit 14, Center 52 (-91 ~ 196) 288
4313 11:07:38.458911 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4314 11:07:38.459181 ==
4315 11:07:38.462404 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 11:07:38.468822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 11:07:38.469126 ==
4318 11:07:38.469337 DQS Delay:
4319 11:07:38.471768 DQS0 = 0, DQS1 = 0
4320 11:07:38.472055 DQM Delay:
4321 11:07:38.472289 DQM0 = 53, DQM1 = 46
4322 11:07:38.475282 DQ Delay:
4323 11:07:38.478585 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4324 11:07:38.482290 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4325 11:07:38.485425 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4326 11:07:38.488957 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4327 11:07:38.489374
4328 11:07:38.489794
4329 11:07:38.495633 [DQSOSCAuto] RK1, (LSB)MR18= 0x6525, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4330 11:07:38.498735 CH0 RK1: MR19=808, MR18=6525
4331 11:07:38.505737 CH0_RK1: MR19=0x808, MR18=0x6525, DQSOSC=390, MR23=63, INC=172, DEC=114
4332 11:07:38.509545 [RxdqsGatingPostProcess] freq 600
4333 11:07:38.512643 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 11:07:38.515849 Pre-setting of DQS Precalculation
4335 11:07:38.522490 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 11:07:38.522895 ==
4337 11:07:38.525390 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 11:07:38.529788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 11:07:38.530315 ==
4340 11:07:38.535319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 11:07:38.538804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4342 11:07:38.543372 [CA 0] Center 36 (5~67) winsize 63
4343 11:07:38.546378 [CA 1] Center 36 (5~67) winsize 63
4344 11:07:38.549939 [CA 2] Center 34 (4~65) winsize 62
4345 11:07:38.553731 [CA 3] Center 34 (4~65) winsize 62
4346 11:07:38.556758 [CA 4] Center 34 (4~65) winsize 62
4347 11:07:38.559869 [CA 5] Center 33 (3~64) winsize 62
4348 11:07:38.560328
4349 11:07:38.563129 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4350 11:07:38.563638
4351 11:07:38.566880 [CATrainingPosCal] consider 1 rank data
4352 11:07:38.569793 u2DelayCellTimex100 = 270/100 ps
4353 11:07:38.573071 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4354 11:07:38.576532 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4355 11:07:38.583176 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 11:07:38.587217 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4357 11:07:38.589918 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 11:07:38.593047 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 11:07:38.593602
4360 11:07:38.596731 CA PerBit enable=1, Macro0, CA PI delay=33
4361 11:07:38.597119
4362 11:07:38.599719 [CBTSetCACLKResult] CA Dly = 33
4363 11:07:38.600106 CS Dly: 5 (0~36)
4364 11:07:38.600462 ==
4365 11:07:38.603939 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 11:07:38.610122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 11:07:38.610511 ==
4368 11:07:38.612928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 11:07:38.619942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 11:07:38.623303 [CA 0] Center 36 (6~67) winsize 62
4371 11:07:38.627179 [CA 1] Center 36 (6~67) winsize 62
4372 11:07:38.630316 [CA 2] Center 35 (5~66) winsize 62
4373 11:07:38.633563 [CA 3] Center 35 (4~66) winsize 63
4374 11:07:38.637688 [CA 4] Center 35 (4~66) winsize 63
4375 11:07:38.639801 [CA 5] Center 34 (4~65) winsize 62
4376 11:07:38.640187
4377 11:07:38.643053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 11:07:38.643444
4379 11:07:38.646463 [CATrainingPosCal] consider 2 rank data
4380 11:07:38.650661 u2DelayCellTimex100 = 270/100 ps
4381 11:07:38.653140 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4382 11:07:38.656502 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4383 11:07:38.663218 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4384 11:07:38.667071 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 11:07:38.670276 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 11:07:38.673459 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4387 11:07:38.674045
4388 11:07:38.676448 CA PerBit enable=1, Macro0, CA PI delay=34
4389 11:07:38.676838
4390 11:07:38.680086 [CBTSetCACLKResult] CA Dly = 34
4391 11:07:38.680474 CS Dly: 6 (0~38)
4392 11:07:38.680771
4393 11:07:38.683392 ----->DramcWriteLeveling(PI) begin...
4394 11:07:38.686869 ==
4395 11:07:38.689807 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:07:38.693348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:07:38.693737 ==
4398 11:07:38.696361 Write leveling (Byte 0): 32 => 32
4399 11:07:38.700042 Write leveling (Byte 1): 29 => 29
4400 11:07:38.703283 DramcWriteLeveling(PI) end<-----
4401 11:07:38.703812
4402 11:07:38.704112 ==
4403 11:07:38.706797 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 11:07:38.709632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:07:38.710068 ==
4406 11:07:38.713719 [Gating] SW mode calibration
4407 11:07:38.719709 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 11:07:38.726127 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 11:07:38.730308 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 11:07:38.733056 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 11:07:38.736190 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 11:07:38.743039 0 9 12 | B1->B0 | 2f2f 2b2b | 1 1 | (1 0) (1 0)
4413 11:07:38.746314 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 11:07:38.749919 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 11:07:38.756499 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 11:07:38.759322 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 11:07:38.763710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 11:07:38.769456 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:07:38.773102 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 11:07:38.776525 0 10 12 | B1->B0 | 3332 3d3d | 1 0 | (0 0) (0 0)
4421 11:07:38.782519 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 11:07:38.786525 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 11:07:38.789089 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 11:07:38.795922 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:07:38.799367 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:07:38.802753 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:07:38.809537 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:07:38.812772 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4429 11:07:38.815739 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:07:38.822776 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:07:38.825987 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:07:38.829051 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:07:38.835964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:07:38.839218 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:07:38.842467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:07:38.849038 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:07:38.852441 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:07:38.855540 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:07:38.862682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:07:38.865844 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:07:38.869252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:07:38.875555 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:07:38.878927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:07:38.882544 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4445 11:07:38.885543 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 11:07:38.888987 Total UI for P1: 0, mck2ui 16
4447 11:07:38.892590 best dqsien dly found for B0: ( 0, 13, 12)
4448 11:07:38.895709 Total UI for P1: 0, mck2ui 16
4449 11:07:38.899120 best dqsien dly found for B1: ( 0, 13, 12)
4450 11:07:38.902300 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4451 11:07:38.908663 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4452 11:07:38.909122
4453 11:07:38.912212 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4454 11:07:38.915376 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4455 11:07:38.918815 [Gating] SW calibration Done
4456 11:07:38.919223 ==
4457 11:07:38.922311 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 11:07:38.925917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 11:07:38.926473 ==
4460 11:07:38.929113 RX Vref Scan: 0
4461 11:07:38.929334
4462 11:07:38.929523 RX Vref 0 -> 0, step: 1
4463 11:07:38.929702
4464 11:07:38.932308 RX Delay -230 -> 252, step: 16
4465 11:07:38.935326 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4466 11:07:38.942163 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4467 11:07:38.945567 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4468 11:07:38.948971 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4469 11:07:38.951811 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4470 11:07:38.955485 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4471 11:07:38.962552 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4472 11:07:38.965561 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4473 11:07:38.968815 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4474 11:07:38.972248 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4475 11:07:38.978922 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4476 11:07:38.982070 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4477 11:07:38.985081 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4478 11:07:38.989108 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4479 11:07:38.995260 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4480 11:07:38.998458 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4481 11:07:38.998932 ==
4482 11:07:39.002290 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 11:07:39.005083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 11:07:39.005559 ==
4485 11:07:39.008707 DQS Delay:
4486 11:07:39.009223 DQS0 = 0, DQS1 = 0
4487 11:07:39.009531 DQM Delay:
4488 11:07:39.012127 DQM0 = 51, DQM1 = 47
4489 11:07:39.012461 DQ Delay:
4490 11:07:39.014995 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4491 11:07:39.018608 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4492 11:07:39.021671 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49
4493 11:07:39.025312 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4494 11:07:39.025822
4495 11:07:39.026380
4496 11:07:39.026772 ==
4497 11:07:39.028346 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 11:07:39.032240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 11:07:39.035252 ==
4500 11:07:39.035674
4501 11:07:39.036067
4502 11:07:39.036448 TX Vref Scan disable
4503 11:07:39.038387 == TX Byte 0 ==
4504 11:07:39.041875 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4505 11:07:39.049112 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4506 11:07:39.049617 == TX Byte 1 ==
4507 11:07:39.051532 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4508 11:07:39.055493 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4509 11:07:39.059945 ==
4510 11:07:39.062093 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 11:07:39.065266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 11:07:39.065829 ==
4513 11:07:39.066284
4514 11:07:39.066572
4515 11:07:39.068613 TX Vref Scan disable
4516 11:07:39.072055 == TX Byte 0 ==
4517 11:07:39.075246 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4518 11:07:39.078507 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4519 11:07:39.081773 == TX Byte 1 ==
4520 11:07:39.085028 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4521 11:07:39.088469 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4522 11:07:39.089005
4523 11:07:39.089429 [DATLAT]
4524 11:07:39.092042 Freq=600, CH1 RK0
4525 11:07:39.092431
4526 11:07:39.092733 DATLAT Default: 0x9
4527 11:07:39.095095 0, 0xFFFF, sum = 0
4528 11:07:39.098461 1, 0xFFFF, sum = 0
4529 11:07:39.098935 2, 0xFFFF, sum = 0
4530 11:07:39.101280 3, 0xFFFF, sum = 0
4531 11:07:39.101803 4, 0xFFFF, sum = 0
4532 11:07:39.105351 5, 0xFFFF, sum = 0
4533 11:07:39.105736 6, 0xFFFF, sum = 0
4534 11:07:39.108081 7, 0xFFFF, sum = 0
4535 11:07:39.108562 8, 0x0, sum = 1
4536 11:07:39.111916 9, 0x0, sum = 2
4537 11:07:39.112527 10, 0x0, sum = 3
4538 11:07:39.112978 11, 0x0, sum = 4
4539 11:07:39.114911 best_step = 9
4540 11:07:39.115322
4541 11:07:39.115737 ==
4542 11:07:39.118192 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 11:07:39.121468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 11:07:39.121860 ==
4545 11:07:39.124645 RX Vref Scan: 1
4546 11:07:39.125029
4547 11:07:39.125334 RX Vref 0 -> 0, step: 1
4548 11:07:39.128400
4549 11:07:39.128921 RX Delay -163 -> 252, step: 8
4550 11:07:39.129294
4551 11:07:39.131170 Set Vref, RX VrefLevel [Byte0]: 55
4552 11:07:39.134827 [Byte1]: 52
4553 11:07:39.139397
4554 11:07:39.139787 Final RX Vref Byte 0 = 55 to rank0
4555 11:07:39.142443 Final RX Vref Byte 1 = 52 to rank0
4556 11:07:39.145793 Final RX Vref Byte 0 = 55 to rank1
4557 11:07:39.148923 Final RX Vref Byte 1 = 52 to rank1==
4558 11:07:39.152323 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 11:07:39.159252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 11:07:39.159645 ==
4561 11:07:39.159959 DQS Delay:
4562 11:07:39.160237 DQS0 = 0, DQS1 = 0
4563 11:07:39.162285 DQM Delay:
4564 11:07:39.162671 DQM0 = 48, DQM1 = 45
4565 11:07:39.165854 DQ Delay:
4566 11:07:39.168536 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4567 11:07:39.171852 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4568 11:07:39.175660 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4569 11:07:39.178658 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4570 11:07:39.179045
4571 11:07:39.179379
4572 11:07:39.185852 [DQSOSCAuto] RK0, (LSB)MR18= 0x5076, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4573 11:07:39.188989 CH1 RK0: MR19=808, MR18=5076
4574 11:07:39.196020 CH1_RK0: MR19=0x808, MR18=0x5076, DQSOSC=387, MR23=63, INC=175, DEC=116
4575 11:07:39.196585
4576 11:07:39.199088 ----->DramcWriteLeveling(PI) begin...
4577 11:07:39.199513 ==
4578 11:07:39.202137 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 11:07:39.205512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 11:07:39.206198 ==
4581 11:07:39.208782 Write leveling (Byte 0): 30 => 30
4582 11:07:39.212960 Write leveling (Byte 1): 33 => 33
4583 11:07:39.215570 DramcWriteLeveling(PI) end<-----
4584 11:07:39.216026
4585 11:07:39.216556 ==
4586 11:07:39.219385 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 11:07:39.222467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 11:07:39.222885 ==
4589 11:07:39.225337 [Gating] SW mode calibration
4590 11:07:39.232173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4591 11:07:39.238741 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4592 11:07:39.241892 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 11:07:39.245759 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 11:07:39.251955 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4595 11:07:39.255303 0 9 12 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 0)
4596 11:07:39.259107 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 11:07:39.265196 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 11:07:39.268569 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 11:07:39.272068 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 11:07:39.278526 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 11:07:39.281768 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 11:07:39.285015 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4603 11:07:39.292392 0 10 12 | B1->B0 | 4343 3333 | 0 1 | (0 0) (0 0)
4604 11:07:39.295345 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 11:07:39.298287 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 11:07:39.305823 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 11:07:39.308298 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 11:07:39.311692 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 11:07:39.318591 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 11:07:39.321920 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4611 11:07:39.325112 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4612 11:07:39.331465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 11:07:39.334881 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 11:07:39.338303 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:07:39.344710 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:07:39.348045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:07:39.351604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:07:39.358562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:07:39.361663 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:07:39.365402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:07:39.371715 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:07:39.375116 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:07:39.378147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:07:39.382062 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:07:39.388361 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:07:39.391444 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4627 11:07:39.395257 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4628 11:07:39.398292 Total UI for P1: 0, mck2ui 16
4629 11:07:39.401428 best dqsien dly found for B1: ( 0, 13, 8)
4630 11:07:39.408610 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 11:07:39.411499 Total UI for P1: 0, mck2ui 16
4632 11:07:39.414587 best dqsien dly found for B0: ( 0, 13, 12)
4633 11:07:39.418160 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4634 11:07:39.421293 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4635 11:07:39.421687
4636 11:07:39.424831 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4637 11:07:39.427873 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4638 11:07:39.431848 [Gating] SW calibration Done
4639 11:07:39.432237 ==
4640 11:07:39.434679 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 11:07:39.438314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:07:39.438710 ==
4643 11:07:39.441745 RX Vref Scan: 0
4644 11:07:39.442317
4645 11:07:39.442799 RX Vref 0 -> 0, step: 1
4646 11:07:39.443242
4647 11:07:39.444675 RX Delay -230 -> 252, step: 16
4648 11:07:39.451677 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4649 11:07:39.455085 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 11:07:39.457936 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4651 11:07:39.461216 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4652 11:07:39.464825 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4653 11:07:39.471597 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4654 11:07:39.474630 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4655 11:07:39.478389 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4656 11:07:39.481392 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 11:07:39.488252 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4658 11:07:39.491528 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 11:07:39.494702 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 11:07:39.497891 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4661 11:07:39.500997 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4662 11:07:39.507859 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4663 11:07:39.511386 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4664 11:07:39.511774 ==
4665 11:07:39.514678 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 11:07:39.517804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 11:07:39.518309 ==
4668 11:07:39.521187 DQS Delay:
4669 11:07:39.521663 DQS0 = 0, DQS1 = 0
4670 11:07:39.525069 DQM Delay:
4671 11:07:39.525601 DQM0 = 50, DQM1 = 47
4672 11:07:39.526125 DQ Delay:
4673 11:07:39.527944 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4674 11:07:39.530812 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4675 11:07:39.534259 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4676 11:07:39.537948 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4677 11:07:39.538424
4678 11:07:39.538751
4679 11:07:39.540909 ==
4680 11:07:39.544094 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 11:07:39.547505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 11:07:39.548011 ==
4683 11:07:39.548444
4684 11:07:39.548868
4685 11:07:39.550854 TX Vref Scan disable
4686 11:07:39.551239 == TX Byte 0 ==
4687 11:07:39.554173 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4688 11:07:39.561103 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4689 11:07:39.561610 == TX Byte 1 ==
4690 11:07:39.564697 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4691 11:07:39.570506 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4692 11:07:39.571032 ==
4693 11:07:39.573929 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 11:07:39.577793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 11:07:39.578240 ==
4696 11:07:39.578541
4697 11:07:39.578811
4698 11:07:39.580783 TX Vref Scan disable
4699 11:07:39.584032 == TX Byte 0 ==
4700 11:07:39.587297 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4701 11:07:39.590426 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4702 11:07:39.593947 == TX Byte 1 ==
4703 11:07:39.597273 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4704 11:07:39.601065 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4705 11:07:39.601503
4706 11:07:39.603886 [DATLAT]
4707 11:07:39.604236 Freq=600, CH1 RK1
4708 11:07:39.604635
4709 11:07:39.607538 DATLAT Default: 0x9
4710 11:07:39.607924 0, 0xFFFF, sum = 0
4711 11:07:39.610783 1, 0xFFFF, sum = 0
4712 11:07:39.611192 2, 0xFFFF, sum = 0
4713 11:07:39.614238 3, 0xFFFF, sum = 0
4714 11:07:39.614700 4, 0xFFFF, sum = 0
4715 11:07:39.617677 5, 0xFFFF, sum = 0
4716 11:07:39.618227 6, 0xFFFF, sum = 0
4717 11:07:39.620797 7, 0xFFFF, sum = 0
4718 11:07:39.621356 8, 0x0, sum = 1
4719 11:07:39.624125 9, 0x0, sum = 2
4720 11:07:39.624554 10, 0x0, sum = 3
4721 11:07:39.627594 11, 0x0, sum = 4
4722 11:07:39.628035 best_step = 9
4723 11:07:39.628336
4724 11:07:39.628606 ==
4725 11:07:39.630784 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 11:07:39.634467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 11:07:39.634875 ==
4728 11:07:39.637203 RX Vref Scan: 0
4729 11:07:39.637586
4730 11:07:39.640746 RX Vref 0 -> 0, step: 1
4731 11:07:39.641152
4732 11:07:39.641605 RX Delay -163 -> 252, step: 8
4733 11:07:39.649108 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4734 11:07:39.652428 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4735 11:07:39.655326 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4736 11:07:39.658445 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4737 11:07:39.662166 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4738 11:07:39.668816 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 11:07:39.671900 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4740 11:07:39.675052 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4741 11:07:39.678742 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4742 11:07:39.685142 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4743 11:07:39.688347 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4744 11:07:39.691821 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4745 11:07:39.695359 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4746 11:07:39.698493 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4747 11:07:39.705017 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4748 11:07:39.708348 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4749 11:07:39.708761 ==
4750 11:07:39.711677 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 11:07:39.715459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 11:07:39.715847 ==
4753 11:07:39.718960 DQS Delay:
4754 11:07:39.719377 DQS0 = 0, DQS1 = 0
4755 11:07:39.719706 DQM Delay:
4756 11:07:39.721872 DQM0 = 49, DQM1 = 45
4757 11:07:39.722482 DQ Delay:
4758 11:07:39.725244 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4759 11:07:39.728452 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4760 11:07:39.732151 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4761 11:07:39.735651 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4762 11:07:39.736032
4763 11:07:39.736329
4764 11:07:39.745294 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4765 11:07:39.745684 CH1 RK1: MR19=808, MR18=6B21
4766 11:07:39.752026 CH1_RK1: MR19=0x808, MR18=0x6B21, DQSOSC=389, MR23=63, INC=173, DEC=115
4767 11:07:39.755043 [RxdqsGatingPostProcess] freq 600
4768 11:07:39.761550 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 11:07:39.764674 Pre-setting of DQS Precalculation
4770 11:07:39.768699 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 11:07:39.774918 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 11:07:39.784976 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 11:07:39.785447
4774 11:07:39.785884
4775 11:07:39.788766 [Calibration Summary] 1200 Mbps
4776 11:07:39.789166 CH 0, Rank 0
4777 11:07:39.791177 SW Impedance : PASS
4778 11:07:39.791725 DUTY Scan : NO K
4779 11:07:39.794839 ZQ Calibration : PASS
4780 11:07:39.798409 Jitter Meter : NO K
4781 11:07:39.798840 CBT Training : PASS
4782 11:07:39.801476 Write leveling : PASS
4783 11:07:39.801859 RX DQS gating : PASS
4784 11:07:39.805126 RX DQ/DQS(RDDQC) : PASS
4785 11:07:39.808017 TX DQ/DQS : PASS
4786 11:07:39.808448 RX DATLAT : PASS
4787 11:07:39.811117 RX DQ/DQS(Engine): PASS
4788 11:07:39.814695 TX OE : NO K
4789 11:07:39.815087 All Pass.
4790 11:07:39.815383
4791 11:07:39.815654 CH 0, Rank 1
4792 11:07:39.817990 SW Impedance : PASS
4793 11:07:39.821292 DUTY Scan : NO K
4794 11:07:39.821679 ZQ Calibration : PASS
4795 11:07:39.824541 Jitter Meter : NO K
4796 11:07:39.828038 CBT Training : PASS
4797 11:07:39.828428 Write leveling : PASS
4798 11:07:39.831010 RX DQS gating : PASS
4799 11:07:39.834505 RX DQ/DQS(RDDQC) : PASS
4800 11:07:39.834906 TX DQ/DQS : PASS
4801 11:07:39.838621 RX DATLAT : PASS
4802 11:07:39.841190 RX DQ/DQS(Engine): PASS
4803 11:07:39.841591 TX OE : NO K
4804 11:07:39.841989 All Pass.
4805 11:07:39.844625
4806 11:07:39.845062 CH 1, Rank 0
4807 11:07:39.848211 SW Impedance : PASS
4808 11:07:39.848608 DUTY Scan : NO K
4809 11:07:39.851368 ZQ Calibration : PASS
4810 11:07:39.854289 Jitter Meter : NO K
4811 11:07:39.854688 CBT Training : PASS
4812 11:07:39.858066 Write leveling : PASS
4813 11:07:39.858469 RX DQS gating : PASS
4814 11:07:39.861484 RX DQ/DQS(RDDQC) : PASS
4815 11:07:39.864537 TX DQ/DQS : PASS
4816 11:07:39.864983 RX DATLAT : PASS
4817 11:07:39.867680 RX DQ/DQS(Engine): PASS
4818 11:07:39.871249 TX OE : NO K
4819 11:07:39.871687 All Pass.
4820 11:07:39.871993
4821 11:07:39.872274 CH 1, Rank 1
4822 11:07:39.874659 SW Impedance : PASS
4823 11:07:39.877978 DUTY Scan : NO K
4824 11:07:39.878491 ZQ Calibration : PASS
4825 11:07:39.880925 Jitter Meter : NO K
4826 11:07:39.884298 CBT Training : PASS
4827 11:07:39.884685 Write leveling : PASS
4828 11:07:39.887439 RX DQS gating : PASS
4829 11:07:39.891233 RX DQ/DQS(RDDQC) : PASS
4830 11:07:39.891722 TX DQ/DQS : PASS
4831 11:07:39.894544 RX DATLAT : PASS
4832 11:07:39.897962 RX DQ/DQS(Engine): PASS
4833 11:07:39.898574 TX OE : NO K
4834 11:07:39.899020 All Pass.
4835 11:07:39.899359
4836 11:07:39.901513 DramC Write-DBI off
4837 11:07:39.904153 PER_BANK_REFRESH: Hybrid Mode
4838 11:07:39.904544 TX_TRACKING: ON
4839 11:07:39.914506 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 11:07:39.917271 [FAST_K] Save calibration result to emmc
4841 11:07:39.920805 dramc_set_vcore_voltage set vcore to 662500
4842 11:07:39.924194 Read voltage for 933, 3
4843 11:07:39.924763 Vio18 = 0
4844 11:07:39.927659 Vcore = 662500
4845 11:07:39.928047 Vdram = 0
4846 11:07:39.928347 Vddq = 0
4847 11:07:39.928667 Vmddr = 0
4848 11:07:39.933971 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 11:07:39.941052 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 11:07:39.941611 MEM_TYPE=3, freq_sel=17
4851 11:07:39.944044 sv_algorithm_assistance_LP4_1600
4852 11:07:39.947624 ============ PULL DRAM RESETB DOWN ============
4853 11:07:39.954169 ========== PULL DRAM RESETB DOWN end =========
4854 11:07:39.957200 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 11:07:39.960563 ===================================
4856 11:07:39.963790 LPDDR4 DRAM CONFIGURATION
4857 11:07:39.967465 ===================================
4858 11:07:39.968009 EX_ROW_EN[0] = 0x0
4859 11:07:39.970513 EX_ROW_EN[1] = 0x0
4860 11:07:39.970901 LP4Y_EN = 0x0
4861 11:07:39.974377 WORK_FSP = 0x0
4862 11:07:39.974817 WL = 0x3
4863 11:07:39.977414 RL = 0x3
4864 11:07:39.980599 BL = 0x2
4865 11:07:39.980986 RPST = 0x0
4866 11:07:39.983885 RD_PRE = 0x0
4867 11:07:39.984360 WR_PRE = 0x1
4868 11:07:39.987342 WR_PST = 0x0
4869 11:07:39.987899 DBI_WR = 0x0
4870 11:07:39.990599 DBI_RD = 0x0
4871 11:07:39.991081 OTF = 0x1
4872 11:07:39.993623 ===================================
4873 11:07:39.997067 ===================================
4874 11:07:40.000351 ANA top config
4875 11:07:40.003587 ===================================
4876 11:07:40.004006 DLL_ASYNC_EN = 0
4877 11:07:40.007091 ALL_SLAVE_EN = 1
4878 11:07:40.010479 NEW_RANK_MODE = 1
4879 11:07:40.013627 DLL_IDLE_MODE = 1
4880 11:07:40.014205 LP45_APHY_COMB_EN = 1
4881 11:07:40.017198 TX_ODT_DIS = 1
4882 11:07:40.020790 NEW_8X_MODE = 1
4883 11:07:40.023814 ===================================
4884 11:07:40.026831 ===================================
4885 11:07:40.030570 data_rate = 1866
4886 11:07:40.033251 CKR = 1
4887 11:07:40.037020 DQ_P2S_RATIO = 8
4888 11:07:40.040343 ===================================
4889 11:07:40.040736 CA_P2S_RATIO = 8
4890 11:07:40.043432 DQ_CA_OPEN = 0
4891 11:07:40.046995 DQ_SEMI_OPEN = 0
4892 11:07:40.050349 CA_SEMI_OPEN = 0
4893 11:07:40.053301 CA_FULL_RATE = 0
4894 11:07:40.053688 DQ_CKDIV4_EN = 1
4895 11:07:40.056774 CA_CKDIV4_EN = 1
4896 11:07:40.060194 CA_PREDIV_EN = 0
4897 11:07:40.063289 PH8_DLY = 0
4898 11:07:40.066856 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 11:07:40.070098 DQ_AAMCK_DIV = 4
4900 11:07:40.070502 CA_AAMCK_DIV = 4
4901 11:07:40.073666 CA_ADMCK_DIV = 4
4902 11:07:40.076955 DQ_TRACK_CA_EN = 0
4903 11:07:40.079883 CA_PICK = 933
4904 11:07:40.083226 CA_MCKIO = 933
4905 11:07:40.086880 MCKIO_SEMI = 0
4906 11:07:40.089868 PLL_FREQ = 3732
4907 11:07:40.090466 DQ_UI_PI_RATIO = 32
4908 11:07:40.093080 CA_UI_PI_RATIO = 0
4909 11:07:40.096390 ===================================
4910 11:07:40.100096 ===================================
4911 11:07:40.103461 memory_type:LPDDR4
4912 11:07:40.106494 GP_NUM : 10
4913 11:07:40.107003 SRAM_EN : 1
4914 11:07:40.109718 MD32_EN : 0
4915 11:07:40.112993 ===================================
4916 11:07:40.116138 [ANA_INIT] >>>>>>>>>>>>>>
4917 11:07:40.116548 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 11:07:40.123450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 11:07:40.126828 ===================================
4920 11:07:40.127328 data_rate = 1866,PCW = 0X8f00
4921 11:07:40.130481 ===================================
4922 11:07:40.133121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 11:07:40.139708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 11:07:40.146395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 11:07:40.149815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 11:07:40.153151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 11:07:40.156323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 11:07:40.159703 [ANA_INIT] flow start
4929 11:07:40.160095 [ANA_INIT] PLL >>>>>>>>
4930 11:07:40.162940 [ANA_INIT] PLL <<<<<<<<
4931 11:07:40.166354 [ANA_INIT] MIDPI >>>>>>>>
4932 11:07:40.169924 [ANA_INIT] MIDPI <<<<<<<<
4933 11:07:40.170364 [ANA_INIT] DLL >>>>>>>>
4934 11:07:40.173205 [ANA_INIT] flow end
4935 11:07:40.176506 ============ LP4 DIFF to SE enter ============
4936 11:07:40.179727 ============ LP4 DIFF to SE exit ============
4937 11:07:40.183225 [ANA_INIT] <<<<<<<<<<<<<
4938 11:07:40.186636 [Flow] Enable top DCM control >>>>>
4939 11:07:40.189578 [Flow] Enable top DCM control <<<<<
4940 11:07:40.192842 Enable DLL master slave shuffle
4941 11:07:40.196158 ==============================================================
4942 11:07:40.199501 Gating Mode config
4943 11:07:40.206541 ==============================================================
4944 11:07:40.206938 Config description:
4945 11:07:40.216199 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 11:07:40.223129 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 11:07:40.229543 SELPH_MODE 0: By rank 1: By Phase
4948 11:07:40.232825 ==============================================================
4949 11:07:40.236064 GAT_TRACK_EN = 1
4950 11:07:40.239371 RX_GATING_MODE = 2
4951 11:07:40.243313 RX_GATING_TRACK_MODE = 2
4952 11:07:40.246609 SELPH_MODE = 1
4953 11:07:40.250097 PICG_EARLY_EN = 1
4954 11:07:40.253393 VALID_LAT_VALUE = 1
4955 11:07:40.256423 ==============================================================
4956 11:07:40.259426 Enter into Gating configuration >>>>
4957 11:07:40.262972 Exit from Gating configuration <<<<
4958 11:07:40.266086 Enter into DVFS_PRE_config >>>>>
4959 11:07:40.279744 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 11:07:40.280331 Exit from DVFS_PRE_config <<<<<
4961 11:07:40.282518 Enter into PICG configuration >>>>
4962 11:07:40.286678 Exit from PICG configuration <<<<
4963 11:07:40.289370 [RX_INPUT] configuration >>>>>
4964 11:07:40.292692 [RX_INPUT] configuration <<<<<
4965 11:07:40.299554 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 11:07:40.303177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 11:07:40.309764 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 11:07:40.316450 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 11:07:40.322761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 11:07:40.329507 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 11:07:40.332837 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 11:07:40.336101 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 11:07:40.339828 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 11:07:40.346301 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 11:07:40.349109 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 11:07:40.352699 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 11:07:40.356116 ===================================
4978 11:07:40.359268 LPDDR4 DRAM CONFIGURATION
4979 11:07:40.362840 ===================================
4980 11:07:40.363230 EX_ROW_EN[0] = 0x0
4981 11:07:40.366068 EX_ROW_EN[1] = 0x0
4982 11:07:40.369151 LP4Y_EN = 0x0
4983 11:07:40.369536 WORK_FSP = 0x0
4984 11:07:40.372411 WL = 0x3
4985 11:07:40.372801 RL = 0x3
4986 11:07:40.376104 BL = 0x2
4987 11:07:40.376492 RPST = 0x0
4988 11:07:40.379509 RD_PRE = 0x0
4989 11:07:40.379897 WR_PRE = 0x1
4990 11:07:40.382535 WR_PST = 0x0
4991 11:07:40.382928 DBI_WR = 0x0
4992 11:07:40.386112 DBI_RD = 0x0
4993 11:07:40.386572 OTF = 0x1
4994 11:07:40.389218 ===================================
4995 11:07:40.392705 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 11:07:40.399399 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 11:07:40.401962 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 11:07:40.406112 ===================================
4999 11:07:40.408903 LPDDR4 DRAM CONFIGURATION
5000 11:07:40.412467 ===================================
5001 11:07:40.412859 EX_ROW_EN[0] = 0x10
5002 11:07:40.415956 EX_ROW_EN[1] = 0x0
5003 11:07:40.419098 LP4Y_EN = 0x0
5004 11:07:40.419489 WORK_FSP = 0x0
5005 11:07:40.422873 WL = 0x3
5006 11:07:40.423265 RL = 0x3
5007 11:07:40.425521 BL = 0x2
5008 11:07:40.426084 RPST = 0x0
5009 11:07:40.429016 RD_PRE = 0x0
5010 11:07:40.429533 WR_PRE = 0x1
5011 11:07:40.432249 WR_PST = 0x0
5012 11:07:40.432639 DBI_WR = 0x0
5013 11:07:40.435540 DBI_RD = 0x0
5014 11:07:40.435932 OTF = 0x1
5015 11:07:40.438749 ===================================
5016 11:07:40.445249 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 11:07:40.449626 nWR fixed to 30
5018 11:07:40.452956 [ModeRegInit_LP4] CH0 RK0
5019 11:07:40.453412 [ModeRegInit_LP4] CH0 RK1
5020 11:07:40.456482 [ModeRegInit_LP4] CH1 RK0
5021 11:07:40.459552 [ModeRegInit_LP4] CH1 RK1
5022 11:07:40.459947 match AC timing 9
5023 11:07:40.466175 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 11:07:40.469827 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 11:07:40.472956 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 11:07:40.479843 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 11:07:40.483414 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 11:07:40.483928 ==
5029 11:07:40.486369 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 11:07:40.490169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 11:07:40.490567 ==
5032 11:07:40.496508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 11:07:40.502702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5034 11:07:40.506508 [CA 0] Center 37 (6~68) winsize 63
5035 11:07:40.509645 [CA 1] Center 37 (7~68) winsize 62
5036 11:07:40.513260 [CA 2] Center 34 (4~65) winsize 62
5037 11:07:40.516031 [CA 3] Center 34 (3~65) winsize 63
5038 11:07:40.519416 [CA 4] Center 33 (3~64) winsize 62
5039 11:07:40.522671 [CA 5] Center 32 (2~62) winsize 61
5040 11:07:40.523163
5041 11:07:40.526347 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5042 11:07:40.526737
5043 11:07:40.529476 [CATrainingPosCal] consider 1 rank data
5044 11:07:40.532574 u2DelayCellTimex100 = 270/100 ps
5045 11:07:40.536100 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5046 11:07:40.539283 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 11:07:40.543019 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5048 11:07:40.545932 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5049 11:07:40.549537 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5050 11:07:40.552706 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5051 11:07:40.556250
5052 11:07:40.559532 CA PerBit enable=1, Macro0, CA PI delay=32
5053 11:07:40.559937
5054 11:07:40.563030 [CBTSetCACLKResult] CA Dly = 32
5055 11:07:40.563418 CS Dly: 5 (0~36)
5056 11:07:40.563717 ==
5057 11:07:40.565788 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 11:07:40.569026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 11:07:40.569432 ==
5060 11:07:40.576080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 11:07:40.581899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 11:07:40.585189 [CA 0] Center 37 (6~68) winsize 63
5063 11:07:40.588586 [CA 1] Center 37 (7~68) winsize 62
5064 11:07:40.592376 [CA 2] Center 34 (4~65) winsize 62
5065 11:07:40.595659 [CA 3] Center 34 (4~64) winsize 61
5066 11:07:40.598703 [CA 4] Center 32 (2~63) winsize 62
5067 11:07:40.601882 [CA 5] Center 32 (2~62) winsize 61
5068 11:07:40.601965
5069 11:07:40.605668 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 11:07:40.605756
5071 11:07:40.609032 [CATrainingPosCal] consider 2 rank data
5072 11:07:40.612607 u2DelayCellTimex100 = 270/100 ps
5073 11:07:40.616163 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5074 11:07:40.619215 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 11:07:40.622718 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 11:07:40.626468 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5077 11:07:40.629288 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5078 11:07:40.635570 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5079 11:07:40.636110
5080 11:07:40.639062 CA PerBit enable=1, Macro0, CA PI delay=32
5081 11:07:40.639453
5082 11:07:40.642391 [CBTSetCACLKResult] CA Dly = 32
5083 11:07:40.642914 CS Dly: 5 (0~37)
5084 11:07:40.643389
5085 11:07:40.645837 ----->DramcWriteLeveling(PI) begin...
5086 11:07:40.646424 ==
5087 11:07:40.649287 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 11:07:40.652882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:07:40.655909 ==
5090 11:07:40.656315 Write leveling (Byte 0): 32 => 32
5091 11:07:40.659183 Write leveling (Byte 1): 29 => 29
5092 11:07:40.662448 DramcWriteLeveling(PI) end<-----
5093 11:07:40.662884
5094 11:07:40.663377 ==
5095 11:07:40.666264 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 11:07:40.672562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 11:07:40.673107 ==
5098 11:07:40.675612 [Gating] SW mode calibration
5099 11:07:40.682451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 11:07:40.685915 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 11:07:40.692666 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5102 11:07:40.695783 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 11:07:40.698992 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 11:07:40.702666 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 11:07:40.709542 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 11:07:40.712705 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 11:07:40.715875 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5108 11:07:40.722568 0 14 28 | B1->B0 | 3434 2727 | 0 0 | (0 0) (1 0)
5109 11:07:40.725534 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5110 11:07:40.729207 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 11:07:40.735474 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 11:07:40.738751 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 11:07:40.742156 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 11:07:40.749257 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 11:07:40.752118 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
5116 11:07:40.755586 0 15 28 | B1->B0 | 2626 4040 | 0 0 | (0 0) (0 0)
5117 11:07:40.762625 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5118 11:07:40.765536 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 11:07:40.769006 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:07:40.775383 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:07:40.778938 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 11:07:40.782078 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 11:07:40.788889 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 11:07:40.792077 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 11:07:40.795345 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5126 11:07:40.802575 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:07:40.805247 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:07:40.809052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:07:40.815181 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:07:40.818825 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:07:40.821839 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:07:40.828181 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:07:40.831868 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:07:40.835211 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:07:40.841958 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:07:40.845068 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:07:40.848239 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:07:40.855118 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:07:40.858890 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:07:40.861938 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5141 11:07:40.864830 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5142 11:07:40.872074 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 11:07:40.875030 Total UI for P1: 0, mck2ui 16
5144 11:07:40.878861 best dqsien dly found for B0: ( 1, 2, 30)
5145 11:07:40.881596 Total UI for P1: 0, mck2ui 16
5146 11:07:40.885482 best dqsien dly found for B1: ( 1, 3, 0)
5147 11:07:40.888467 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5148 11:07:40.891949 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5149 11:07:40.892360
5150 11:07:40.894709 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5151 11:07:40.898129 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5152 11:07:40.901894 [Gating] SW calibration Done
5153 11:07:40.902583 ==
5154 11:07:40.905055 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 11:07:40.908600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 11:07:40.908992 ==
5157 11:07:40.911674 RX Vref Scan: 0
5158 11:07:40.912229
5159 11:07:40.912738 RX Vref 0 -> 0, step: 1
5160 11:07:40.913192
5161 11:07:40.914862 RX Delay -80 -> 252, step: 8
5162 11:07:40.921852 iDelay=200, Bit 0, Center 107 (16 ~ 199) 184
5163 11:07:40.925107 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5164 11:07:40.928076 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5165 11:07:40.931942 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5166 11:07:40.934823 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5167 11:07:40.937651 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5168 11:07:40.944436 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5169 11:07:40.948371 iDelay=200, Bit 7, Center 111 (24 ~ 199) 176
5170 11:07:40.951562 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5171 11:07:40.954588 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5172 11:07:40.957839 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5173 11:07:40.961296 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5174 11:07:40.968173 iDelay=200, Bit 12, Center 103 (16 ~ 191) 176
5175 11:07:40.971412 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5176 11:07:40.974726 iDelay=200, Bit 14, Center 107 (16 ~ 199) 184
5177 11:07:40.978330 iDelay=200, Bit 15, Center 103 (16 ~ 191) 176
5178 11:07:40.978715 ==
5179 11:07:40.981652 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 11:07:40.987876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 11:07:40.988276 ==
5182 11:07:40.988674 DQS Delay:
5183 11:07:40.991297 DQS0 = 0, DQS1 = 0
5184 11:07:40.991699 DQM Delay:
5185 11:07:40.992095 DQM0 = 103, DQM1 = 96
5186 11:07:40.994374 DQ Delay:
5187 11:07:40.997634 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5188 11:07:41.001047 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =111
5189 11:07:41.004909 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5190 11:07:41.008239 DQ12 =103, DQ13 =103, DQ14 =107, DQ15 =103
5191 11:07:41.008631
5192 11:07:41.008929
5193 11:07:41.009208 ==
5194 11:07:41.011419 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 11:07:41.014603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 11:07:41.015007 ==
5197 11:07:41.015308
5198 11:07:41.015584
5199 11:07:41.017640 TX Vref Scan disable
5200 11:07:41.020953 == TX Byte 0 ==
5201 11:07:41.024866 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5202 11:07:41.027826 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5203 11:07:41.031138 == TX Byte 1 ==
5204 11:07:41.034240 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5205 11:07:41.037508 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5206 11:07:41.037901 ==
5207 11:07:41.041246 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 11:07:41.047818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 11:07:41.048214 ==
5210 11:07:41.048514
5211 11:07:41.048791
5212 11:07:41.049057 TX Vref Scan disable
5213 11:07:41.051550 == TX Byte 0 ==
5214 11:07:41.054712 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5215 11:07:41.061628 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5216 11:07:41.062084 == TX Byte 1 ==
5217 11:07:41.064955 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5218 11:07:41.068556 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5219 11:07:41.071553
5220 11:07:41.071940 [DATLAT]
5221 11:07:41.072244 Freq=933, CH0 RK0
5222 11:07:41.072526
5223 11:07:41.074828 DATLAT Default: 0xd
5224 11:07:41.075215 0, 0xFFFF, sum = 0
5225 11:07:41.078215 1, 0xFFFF, sum = 0
5226 11:07:41.078619 2, 0xFFFF, sum = 0
5227 11:07:41.081258 3, 0xFFFF, sum = 0
5228 11:07:41.081703 4, 0xFFFF, sum = 0
5229 11:07:41.084915 5, 0xFFFF, sum = 0
5230 11:07:41.088738 6, 0xFFFF, sum = 0
5231 11:07:41.089142 7, 0xFFFF, sum = 0
5232 11:07:41.091802 8, 0xFFFF, sum = 0
5233 11:07:41.092198 9, 0xFFFF, sum = 0
5234 11:07:41.094492 10, 0x0, sum = 1
5235 11:07:41.094897 11, 0x0, sum = 2
5236 11:07:41.095388 12, 0x0, sum = 3
5237 11:07:41.098426 13, 0x0, sum = 4
5238 11:07:41.098831 best_step = 11
5239 11:07:41.099219
5240 11:07:41.101640 ==
5241 11:07:41.102062 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 11:07:41.107803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 11:07:41.108216 ==
5244 11:07:41.108609 RX Vref Scan: 1
5245 11:07:41.108997
5246 11:07:41.111526 RX Vref 0 -> 0, step: 1
5247 11:07:41.111921
5248 11:07:41.114867 RX Delay -53 -> 252, step: 4
5249 11:07:41.115264
5250 11:07:41.117931 Set Vref, RX VrefLevel [Byte0]: 55
5251 11:07:41.121278 [Byte1]: 54
5252 11:07:41.121662
5253 11:07:41.124488 Final RX Vref Byte 0 = 55 to rank0
5254 11:07:41.128089 Final RX Vref Byte 1 = 54 to rank0
5255 11:07:41.131208 Final RX Vref Byte 0 = 55 to rank1
5256 11:07:41.135286 Final RX Vref Byte 1 = 54 to rank1==
5257 11:07:41.138358 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:07:41.141262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:07:41.141649 ==
5260 11:07:41.144652 DQS Delay:
5261 11:07:41.145036 DQS0 = 0, DQS1 = 0
5262 11:07:41.147882 DQM Delay:
5263 11:07:41.148264 DQM0 = 105, DQM1 = 97
5264 11:07:41.151151 DQ Delay:
5265 11:07:41.154917 DQ0 =104, DQ1 =104, DQ2 =104, DQ3 =102
5266 11:07:41.157534 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =110
5267 11:07:41.161254 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5268 11:07:41.164459 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5269 11:07:41.164848
5270 11:07:41.165146
5271 11:07:41.171549 [DQSOSCAuto] RK0, (LSB)MR18= 0x332a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5272 11:07:41.174630 CH0 RK0: MR19=505, MR18=332A
5273 11:07:41.180981 CH0_RK0: MR19=0x505, MR18=0x332A, DQSOSC=405, MR23=63, INC=66, DEC=44
5274 11:07:41.181367
5275 11:07:41.184266 ----->DramcWriteLeveling(PI) begin...
5276 11:07:41.184660 ==
5277 11:07:41.188259 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 11:07:41.191316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 11:07:41.191706 ==
5280 11:07:41.194304 Write leveling (Byte 0): 34 => 34
5281 11:07:41.197858 Write leveling (Byte 1): 28 => 28
5282 11:07:41.200944 DramcWriteLeveling(PI) end<-----
5283 11:07:41.201455
5284 11:07:41.202041 ==
5285 11:07:41.204411 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 11:07:41.207859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:07:41.208318 ==
5288 11:07:41.211354 [Gating] SW mode calibration
5289 11:07:41.217804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 11:07:41.224592 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 11:07:41.227897 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5292 11:07:41.234748 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 11:07:41.237575 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 11:07:41.241094 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 11:07:41.247825 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 11:07:41.251193 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 11:07:41.254415 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
5298 11:07:41.258097 0 14 28 | B1->B0 | 2727 2929 | 0 0 | (0 0) (1 0)
5299 11:07:41.264580 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 11:07:41.267644 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 11:07:41.271039 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 11:07:41.278104 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 11:07:41.281355 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 11:07:41.284568 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 11:07:41.291590 0 15 24 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
5306 11:07:41.294739 0 15 28 | B1->B0 | 3939 3434 | 1 0 | (0 0) (0 0)
5307 11:07:41.297761 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 11:07:41.304585 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 11:07:41.308169 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 11:07:41.311126 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 11:07:41.317669 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 11:07:41.321463 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 11:07:41.324744 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 11:07:41.331221 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 11:07:41.334448 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 11:07:41.337595 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 11:07:41.344665 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 11:07:41.347687 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:07:41.351232 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:07:41.354454 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:07:41.361322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:07:41.364616 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:07:41.367761 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:07:41.374825 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:07:41.378200 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:07:41.380666 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:07:41.387475 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:07:41.390788 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:07:41.394263 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:07:41.401020 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5331 11:07:41.404216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 11:07:41.407783 Total UI for P1: 0, mck2ui 16
5333 11:07:41.411147 best dqsien dly found for B0: ( 1, 2, 28)
5334 11:07:41.414226 Total UI for P1: 0, mck2ui 16
5335 11:07:41.417422 best dqsien dly found for B1: ( 1, 2, 28)
5336 11:07:41.420706 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 11:07:41.424169 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5338 11:07:41.424563
5339 11:07:41.427252 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 11:07:41.430594 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 11:07:41.433800 [Gating] SW calibration Done
5342 11:07:41.434387 ==
5343 11:07:41.437511 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 11:07:41.440711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 11:07:41.444146 ==
5346 11:07:41.444524 RX Vref Scan: 0
5347 11:07:41.444818
5348 11:07:41.448054 RX Vref 0 -> 0, step: 1
5349 11:07:41.448437
5350 11:07:41.450624 RX Delay -80 -> 252, step: 8
5351 11:07:41.453696 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5352 11:07:41.457338 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5353 11:07:41.460289 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5354 11:07:41.463790 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 11:07:41.470620 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 11:07:41.473837 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5357 11:07:41.477009 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5358 11:07:41.480062 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5359 11:07:41.484004 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5360 11:07:41.487188 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5361 11:07:41.493760 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5362 11:07:41.497018 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 11:07:41.500088 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5364 11:07:41.503555 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5365 11:07:41.506889 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5366 11:07:41.510211 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5367 11:07:41.513388 ==
5368 11:07:41.517463 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 11:07:41.520713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 11:07:41.521097 ==
5371 11:07:41.521392 DQS Delay:
5372 11:07:41.524266 DQS0 = 0, DQS1 = 0
5373 11:07:41.524651 DQM Delay:
5374 11:07:41.526924 DQM0 = 105, DQM1 = 94
5375 11:07:41.527508 DQ Delay:
5376 11:07:41.530260 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5377 11:07:41.533306 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5378 11:07:41.536555 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =87
5379 11:07:41.540102 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5380 11:07:41.540553
5381 11:07:41.540852
5382 11:07:41.541126 ==
5383 11:07:41.543365 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 11:07:41.546483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 11:07:41.549913 ==
5386 11:07:41.550357
5387 11:07:41.550651
5388 11:07:41.550925 TX Vref Scan disable
5389 11:07:41.553216 == TX Byte 0 ==
5390 11:07:41.556448 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5391 11:07:41.560144 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5392 11:07:41.563587 == TX Byte 1 ==
5393 11:07:41.566690 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5394 11:07:41.569973 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5395 11:07:41.572866 ==
5396 11:07:41.576442 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 11:07:41.580146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 11:07:41.580655 ==
5399 11:07:41.581011
5400 11:07:41.581409
5401 11:07:41.583175 TX Vref Scan disable
5402 11:07:41.583596 == TX Byte 0 ==
5403 11:07:41.590093 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5404 11:07:41.592999 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5405 11:07:41.593434 == TX Byte 1 ==
5406 11:07:41.600098 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5407 11:07:41.603068 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5408 11:07:41.603572
5409 11:07:41.603879 [DATLAT]
5410 11:07:41.606615 Freq=933, CH0 RK1
5411 11:07:41.607040
5412 11:07:41.607384 DATLAT Default: 0xb
5413 11:07:41.609861 0, 0xFFFF, sum = 0
5414 11:07:41.610420 1, 0xFFFF, sum = 0
5415 11:07:41.612940 2, 0xFFFF, sum = 0
5416 11:07:41.613381 3, 0xFFFF, sum = 0
5417 11:07:41.616790 4, 0xFFFF, sum = 0
5418 11:07:41.617186 5, 0xFFFF, sum = 0
5419 11:07:41.619997 6, 0xFFFF, sum = 0
5420 11:07:41.620528 7, 0xFFFF, sum = 0
5421 11:07:41.623315 8, 0xFFFF, sum = 0
5422 11:07:41.626525 9, 0xFFFF, sum = 0
5423 11:07:41.626949 10, 0x0, sum = 1
5424 11:07:41.627257 11, 0x0, sum = 2
5425 11:07:41.629769 12, 0x0, sum = 3
5426 11:07:41.630213 13, 0x0, sum = 4
5427 11:07:41.633819 best_step = 11
5428 11:07:41.634270
5429 11:07:41.634571 ==
5430 11:07:41.636445 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 11:07:41.639788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 11:07:41.640367 ==
5433 11:07:41.642879 RX Vref Scan: 0
5434 11:07:41.643267
5435 11:07:41.643571 RX Vref 0 -> 0, step: 1
5436 11:07:41.643854
5437 11:07:41.646620 RX Delay -45 -> 252, step: 4
5438 11:07:41.653451 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5439 11:07:41.656969 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5440 11:07:41.660331 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5441 11:07:41.663320 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5442 11:07:41.666896 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5443 11:07:41.673226 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5444 11:07:41.676348 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5445 11:07:41.679903 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5446 11:07:41.683661 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5447 11:07:41.686875 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5448 11:07:41.689889 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5449 11:07:41.696528 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5450 11:07:41.699906 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5451 11:07:41.703139 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5452 11:07:41.706931 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5453 11:07:41.710193 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5454 11:07:41.713100 ==
5455 11:07:41.716791 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:07:41.720111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:07:41.720505 ==
5458 11:07:41.720807 DQS Delay:
5459 11:07:41.723350 DQS0 = 0, DQS1 = 0
5460 11:07:41.723741 DQM Delay:
5461 11:07:41.726565 DQM0 = 104, DQM1 = 94
5462 11:07:41.727116 DQ Delay:
5463 11:07:41.730309 DQ0 =100, DQ1 =108, DQ2 =102, DQ3 =100
5464 11:07:41.733441 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5465 11:07:41.736994 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5466 11:07:41.739762 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5467 11:07:41.740151
5468 11:07:41.740448
5469 11:07:41.750123 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5470 11:07:41.750519 CH0 RK1: MR19=505, MR18=2A03
5471 11:07:41.756688 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5472 11:07:41.760016 [RxdqsGatingPostProcess] freq 933
5473 11:07:41.766834 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 11:07:41.769998 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 11:07:41.773442 best DQS1 dly(2T, 0.5T) = (0, 11)
5476 11:07:41.776723 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 11:07:41.779766 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5478 11:07:41.783382 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 11:07:41.783806 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 11:07:41.786369 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 11:07:41.789905 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 11:07:41.793366 Pre-setting of DQS Precalculation
5483 11:07:41.799685 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 11:07:41.800152 ==
5485 11:07:41.803593 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 11:07:41.806287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:07:41.806681 ==
5488 11:07:41.812721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 11:07:41.819642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5490 11:07:41.822621 [CA 0] Center 36 (6~67) winsize 62
5491 11:07:41.826088 [CA 1] Center 37 (6~68) winsize 63
5492 11:07:41.829411 [CA 2] Center 34 (4~65) winsize 62
5493 11:07:41.832921 [CA 3] Center 34 (4~65) winsize 62
5494 11:07:41.836003 [CA 4] Center 34 (4~65) winsize 62
5495 11:07:41.839322 [CA 5] Center 33 (3~64) winsize 62
5496 11:07:41.839861
5497 11:07:41.842852 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5498 11:07:41.843242
5499 11:07:41.846403 [CATrainingPosCal] consider 1 rank data
5500 11:07:41.849657 u2DelayCellTimex100 = 270/100 ps
5501 11:07:41.852957 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 11:07:41.856294 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5503 11:07:41.859494 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 11:07:41.862776 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 11:07:41.866467 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 11:07:41.869366 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 11:07:41.869756
5508 11:07:41.873622 CA PerBit enable=1, Macro0, CA PI delay=33
5509 11:07:41.874046
5510 11:07:41.876302 [CBTSetCACLKResult] CA Dly = 33
5511 11:07:41.879869 CS Dly: 6 (0~37)
5512 11:07:41.880256 ==
5513 11:07:41.883373 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 11:07:41.886135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:07:41.886620 ==
5516 11:07:41.892908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 11:07:41.899287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5518 11:07:41.902942 [CA 0] Center 37 (6~68) winsize 63
5519 11:07:41.906034 [CA 1] Center 37 (6~68) winsize 63
5520 11:07:41.909342 [CA 2] Center 35 (4~66) winsize 63
5521 11:07:41.912865 [CA 3] Center 34 (4~65) winsize 62
5522 11:07:41.915843 [CA 4] Center 34 (4~65) winsize 62
5523 11:07:41.919426 [CA 5] Center 34 (4~64) winsize 61
5524 11:07:41.919813
5525 11:07:41.922856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5526 11:07:41.923363
5527 11:07:41.925903 [CATrainingPosCal] consider 2 rank data
5528 11:07:41.929332 u2DelayCellTimex100 = 270/100 ps
5529 11:07:41.932639 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5530 11:07:41.935814 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5531 11:07:41.939556 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5532 11:07:41.942823 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5533 11:07:41.945923 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5534 11:07:41.948887 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5535 11:07:41.949055
5536 11:07:41.952862 CA PerBit enable=1, Macro0, CA PI delay=34
5537 11:07:41.955538
5538 11:07:41.955706 [CBTSetCACLKResult] CA Dly = 34
5539 11:07:41.959514 CS Dly: 7 (0~40)
5540 11:07:41.959683
5541 11:07:41.962036 ----->DramcWriteLeveling(PI) begin...
5542 11:07:41.962209 ==
5543 11:07:41.965863 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 11:07:41.969229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 11:07:41.969826 ==
5546 11:07:41.972525 Write leveling (Byte 0): 26 => 26
5547 11:07:41.975782 Write leveling (Byte 1): 27 => 27
5548 11:07:41.979651 DramcWriteLeveling(PI) end<-----
5549 11:07:41.980169
5550 11:07:41.980651 ==
5551 11:07:41.982510 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 11:07:41.985618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 11:07:41.988783 ==
5554 11:07:41.989332 [Gating] SW mode calibration
5555 11:07:41.995833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 11:07:42.002265 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 11:07:42.005813 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 11:07:42.012446 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 11:07:42.015619 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 11:07:42.018982 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 11:07:42.025412 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 11:07:42.028538 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 11:07:42.032402 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 1)
5564 11:07:42.038880 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5565 11:07:42.042155 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 11:07:42.045367 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 11:07:42.052391 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 11:07:42.055637 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 11:07:42.058836 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 11:07:42.065706 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 11:07:42.068868 0 15 24 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
5572 11:07:42.072430 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5573 11:07:42.075997 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 11:07:42.082368 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 11:07:42.085707 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 11:07:42.088804 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 11:07:42.095278 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:07:42.098662 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:07:42.101887 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 11:07:42.108650 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 11:07:42.112097 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:07:42.115288 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:07:42.121610 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:07:42.125260 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:07:42.128800 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:07:42.135144 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:07:42.138291 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:07:42.141554 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:07:42.148406 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:07:42.152291 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:07:42.155126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:07:42.161826 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:07:42.164843 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:07:42.168803 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:07:42.175061 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5596 11:07:42.178001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 11:07:42.181845 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 11:07:42.184645 Total UI for P1: 0, mck2ui 16
5599 11:07:42.188073 best dqsien dly found for B0: ( 1, 2, 28)
5600 11:07:42.191849 Total UI for P1: 0, mck2ui 16
5601 11:07:42.195009 best dqsien dly found for B1: ( 1, 2, 26)
5602 11:07:42.198072 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5603 11:07:42.201404 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5604 11:07:42.201936
5605 11:07:42.205327 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5606 11:07:42.211961 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5607 11:07:42.212603 [Gating] SW calibration Done
5608 11:07:42.215051 ==
5609 11:07:42.217989 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 11:07:42.222042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 11:07:42.222528 ==
5612 11:07:42.222913 RX Vref Scan: 0
5613 11:07:42.223195
5614 11:07:42.224471 RX Vref 0 -> 0, step: 1
5615 11:07:42.224872
5616 11:07:42.228364 RX Delay -80 -> 252, step: 8
5617 11:07:42.231323 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5618 11:07:42.234565 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5619 11:07:42.238164 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5620 11:07:42.244489 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5621 11:07:42.247917 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5622 11:07:42.251277 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5623 11:07:42.254234 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5624 11:07:42.258083 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5625 11:07:42.260775 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5626 11:07:42.267878 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5627 11:07:42.270880 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5628 11:07:42.274381 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5629 11:07:42.277297 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5630 11:07:42.280854 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5631 11:07:42.287708 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5632 11:07:42.290697 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5633 11:07:42.291080 ==
5634 11:07:42.294215 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:07:42.297248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:07:42.297649 ==
5637 11:07:42.301077 DQS Delay:
5638 11:07:42.301483 DQS0 = 0, DQS1 = 0
5639 11:07:42.301789 DQM Delay:
5640 11:07:42.303777 DQM0 = 102, DQM1 = 97
5641 11:07:42.304325 DQ Delay:
5642 11:07:42.307258 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5643 11:07:42.310618 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5644 11:07:42.313879 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5645 11:07:42.317294 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5646 11:07:42.317682
5647 11:07:42.318033
5648 11:07:42.320637 ==
5649 11:07:42.324105 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 11:07:42.327266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 11:07:42.327656 ==
5652 11:07:42.327955
5653 11:07:42.328230
5654 11:07:42.330254 TX Vref Scan disable
5655 11:07:42.330639 == TX Byte 0 ==
5656 11:07:42.337376 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5657 11:07:42.340346 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5658 11:07:42.340906 == TX Byte 1 ==
5659 11:07:42.347226 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5660 11:07:42.350411 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5661 11:07:42.350910 ==
5662 11:07:42.353639 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 11:07:42.356946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 11:07:42.357337 ==
5665 11:07:42.357634
5666 11:07:42.357906
5667 11:07:42.360278 TX Vref Scan disable
5668 11:07:42.363769 == TX Byte 0 ==
5669 11:07:42.367364 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5670 11:07:42.370695 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5671 11:07:42.373592 == TX Byte 1 ==
5672 11:07:42.376835 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5673 11:07:42.380413 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5674 11:07:42.380796
5675 11:07:42.383391 [DATLAT]
5676 11:07:42.383838 Freq=933, CH1 RK0
5677 11:07:42.384204
5678 11:07:42.386702 DATLAT Default: 0xd
5679 11:07:42.387181 0, 0xFFFF, sum = 0
5680 11:07:42.390054 1, 0xFFFF, sum = 0
5681 11:07:42.390408 2, 0xFFFF, sum = 0
5682 11:07:42.393211 3, 0xFFFF, sum = 0
5683 11:07:42.393626 4, 0xFFFF, sum = 0
5684 11:07:42.396990 5, 0xFFFF, sum = 0
5685 11:07:42.397378 6, 0xFFFF, sum = 0
5686 11:07:42.400394 7, 0xFFFF, sum = 0
5687 11:07:42.400785 8, 0xFFFF, sum = 0
5688 11:07:42.404013 9, 0xFFFF, sum = 0
5689 11:07:42.404458 10, 0x0, sum = 1
5690 11:07:42.407028 11, 0x0, sum = 2
5691 11:07:42.407610 12, 0x0, sum = 3
5692 11:07:42.409980 13, 0x0, sum = 4
5693 11:07:42.410403 best_step = 11
5694 11:07:42.410715
5695 11:07:42.411002 ==
5696 11:07:42.413686 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:07:42.416948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:07:42.419925 ==
5699 11:07:42.420342 RX Vref Scan: 1
5700 11:07:42.420881
5701 11:07:42.423443 RX Vref 0 -> 0, step: 1
5702 11:07:42.423837
5703 11:07:42.426881 RX Delay -45 -> 252, step: 4
5704 11:07:42.427241
5705 11:07:42.427573 Set Vref, RX VrefLevel [Byte0]: 55
5706 11:07:42.430362 [Byte1]: 52
5707 11:07:42.434987
5708 11:07:42.435372 Final RX Vref Byte 0 = 55 to rank0
5709 11:07:42.438596 Final RX Vref Byte 1 = 52 to rank0
5710 11:07:42.441914 Final RX Vref Byte 0 = 55 to rank1
5711 11:07:42.444962 Final RX Vref Byte 1 = 52 to rank1==
5712 11:07:42.448891 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 11:07:42.455149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 11:07:42.455538 ==
5715 11:07:42.455840 DQS Delay:
5716 11:07:42.456116 DQS0 = 0, DQS1 = 0
5717 11:07:42.458481 DQM Delay:
5718 11:07:42.459003 DQM0 = 103, DQM1 = 98
5719 11:07:42.461530 DQ Delay:
5720 11:07:42.465213 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5721 11:07:42.468179 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5722 11:07:42.471535 DQ8 =86, DQ9 =90, DQ10 =100, DQ11 =94
5723 11:07:42.475055 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =104
5724 11:07:42.475444
5725 11:07:42.475740
5726 11:07:42.481942 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5727 11:07:42.484996 CH1 RK0: MR19=505, MR18=1930
5728 11:07:42.491575 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5729 11:07:42.491965
5730 11:07:42.494861 ----->DramcWriteLeveling(PI) begin...
5731 11:07:42.495252 ==
5732 11:07:42.498725 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 11:07:42.501444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 11:07:42.504815 ==
5735 11:07:42.505205 Write leveling (Byte 0): 26 => 26
5736 11:07:42.507886 Write leveling (Byte 1): 27 => 27
5737 11:07:42.511208 DramcWriteLeveling(PI) end<-----
5738 11:07:42.511597
5739 11:07:42.511893 ==
5740 11:07:42.515158 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 11:07:42.521242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 11:07:42.521634 ==
5743 11:07:42.521932 [Gating] SW mode calibration
5744 11:07:42.531583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5745 11:07:42.534746 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5746 11:07:42.541185 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 11:07:42.544191 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 11:07:42.547792 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 11:07:42.554646 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 11:07:42.557934 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 11:07:42.560965 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 11:07:42.564349 0 14 24 | B1->B0 | 2a2a 3030 | 0 0 | (0 0) (0 0)
5753 11:07:42.571166 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5754 11:07:42.574177 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 11:07:42.577855 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 11:07:42.584354 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 11:07:42.587914 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 11:07:42.591296 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 11:07:42.597491 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 11:07:42.600726 0 15 24 | B1->B0 | 3131 2828 | 1 0 | (0 0) (0 0)
5761 11:07:42.603771 0 15 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
5762 11:07:42.610992 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 11:07:42.614462 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 11:07:42.617374 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 11:07:42.624320 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 11:07:42.627548 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 11:07:42.630685 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 11:07:42.637409 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5769 11:07:42.640424 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5770 11:07:42.643938 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5771 11:07:42.650554 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:07:42.653869 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:07:42.657455 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:07:42.663831 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:07:42.667070 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:07:42.670717 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:07:42.676731 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:07:42.680305 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:07:42.683687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:07:42.690230 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:07:42.693810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:07:42.697149 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:07:42.703836 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:07:42.707057 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5785 11:07:42.710516 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 11:07:42.713301 Total UI for P1: 0, mck2ui 16
5787 11:07:42.716835 best dqsien dly found for B0: ( 1, 2, 24)
5788 11:07:42.720303 Total UI for P1: 0, mck2ui 16
5789 11:07:42.723509 best dqsien dly found for B1: ( 1, 2, 24)
5790 11:07:42.727424 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5791 11:07:42.730504 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5792 11:07:42.730887
5793 11:07:42.733552 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 11:07:42.739818 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5795 11:07:42.740204 [Gating] SW calibration Done
5796 11:07:42.740501 ==
5797 11:07:42.743856 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 11:07:42.750111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 11:07:42.750515 ==
5800 11:07:42.750817 RX Vref Scan: 0
5801 11:07:42.751093
5802 11:07:42.753379 RX Vref 0 -> 0, step: 1
5803 11:07:42.753762
5804 11:07:42.756489 RX Delay -80 -> 252, step: 8
5805 11:07:42.760225 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5806 11:07:42.763705 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5807 11:07:42.767196 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5808 11:07:42.770042 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5809 11:07:42.776993 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5810 11:07:42.780287 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5811 11:07:42.783526 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5812 11:07:42.786877 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5813 11:07:42.790553 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5814 11:07:42.793131 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5815 11:07:42.797074 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5816 11:07:42.803305 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5817 11:07:42.807335 iDelay=208, Bit 12, Center 111 (24 ~ 199) 176
5818 11:07:42.809868 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5819 11:07:42.813632 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5820 11:07:42.820652 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5821 11:07:42.821208 ==
5822 11:07:42.823677 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:07:42.826837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:07:42.827337 ==
5825 11:07:42.827646 DQS Delay:
5826 11:07:42.830317 DQS0 = 0, DQS1 = 0
5827 11:07:42.830714 DQM Delay:
5828 11:07:42.833646 DQM0 = 102, DQM1 = 100
5829 11:07:42.834069 DQ Delay:
5830 11:07:42.837286 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =95
5831 11:07:42.839751 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5832 11:07:42.843531 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5833 11:07:42.846836 DQ12 =111, DQ13 =111, DQ14 =103, DQ15 =107
5834 11:07:42.847228
5835 11:07:42.847530
5836 11:07:42.847805 ==
5837 11:07:42.850159 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 11:07:42.856443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 11:07:42.856866 ==
5840 11:07:42.857175
5841 11:07:42.857529
5842 11:07:42.857830 TX Vref Scan disable
5843 11:07:42.859638 == TX Byte 0 ==
5844 11:07:42.863572 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5845 11:07:42.866606 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5846 11:07:42.869876 == TX Byte 1 ==
5847 11:07:42.872968 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5848 11:07:42.876398 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5849 11:07:42.879722 ==
5850 11:07:42.883133 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 11:07:42.886503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 11:07:42.886893 ==
5853 11:07:42.887194
5854 11:07:42.887468
5855 11:07:42.889784 TX Vref Scan disable
5856 11:07:42.890247 == TX Byte 0 ==
5857 11:07:42.896461 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5858 11:07:42.899512 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5859 11:07:42.899903 == TX Byte 1 ==
5860 11:07:42.906099 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5861 11:07:42.909502 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5862 11:07:42.909893
5863 11:07:42.910260 [DATLAT]
5864 11:07:42.913225 Freq=933, CH1 RK1
5865 11:07:42.913613
5866 11:07:42.913911 DATLAT Default: 0xb
5867 11:07:42.916413 0, 0xFFFF, sum = 0
5868 11:07:42.916806 1, 0xFFFF, sum = 0
5869 11:07:42.919464 2, 0xFFFF, sum = 0
5870 11:07:42.919991 3, 0xFFFF, sum = 0
5871 11:07:42.922702 4, 0xFFFF, sum = 0
5872 11:07:42.923094 5, 0xFFFF, sum = 0
5873 11:07:42.926316 6, 0xFFFF, sum = 0
5874 11:07:42.929425 7, 0xFFFF, sum = 0
5875 11:07:42.930055 8, 0xFFFF, sum = 0
5876 11:07:42.932937 9, 0xFFFF, sum = 0
5877 11:07:42.933457 10, 0x0, sum = 1
5878 11:07:42.936272 11, 0x0, sum = 2
5879 11:07:42.936663 12, 0x0, sum = 3
5880 11:07:42.936969 13, 0x0, sum = 4
5881 11:07:42.939635 best_step = 11
5882 11:07:42.940024
5883 11:07:42.940327 ==
5884 11:07:42.942773 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 11:07:42.945948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 11:07:42.946403 ==
5887 11:07:42.949252 RX Vref Scan: 0
5888 11:07:42.949642
5889 11:07:42.949944 RX Vref 0 -> 0, step: 1
5890 11:07:42.950275
5891 11:07:42.952548 RX Delay -45 -> 252, step: 4
5892 11:07:42.960007 iDelay=203, Bit 0, Center 108 (23 ~ 194) 172
5893 11:07:42.963214 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5894 11:07:42.966954 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5895 11:07:42.969836 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5896 11:07:42.973768 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5897 11:07:42.979650 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5898 11:07:42.983217 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5899 11:07:42.986603 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5900 11:07:42.989817 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5901 11:07:42.993983 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5902 11:07:42.999723 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5903 11:07:43.003502 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5904 11:07:43.006232 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5905 11:07:43.009724 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5906 11:07:43.012980 iDelay=203, Bit 14, Center 104 (19 ~ 190) 172
5907 11:07:43.020090 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5908 11:07:43.020483 ==
5909 11:07:43.023295 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:07:43.026418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:07:43.026944 ==
5912 11:07:43.027444 DQS Delay:
5913 11:07:43.030264 DQS0 = 0, DQS1 = 0
5914 11:07:43.030655 DQM Delay:
5915 11:07:43.033048 DQM0 = 104, DQM1 = 98
5916 11:07:43.033435 DQ Delay:
5917 11:07:43.036545 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5918 11:07:43.039711 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5919 11:07:43.043332 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5920 11:07:43.046101 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5921 11:07:43.046669
5922 11:07:43.047026
5923 11:07:43.056224 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5924 11:07:43.059395 CH1 RK1: MR19=505, MR18=2E01
5925 11:07:43.063084 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5926 11:07:43.065705 [RxdqsGatingPostProcess] freq 933
5927 11:07:43.072879 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5928 11:07:43.076422 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 11:07:43.079518 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 11:07:43.082786 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 11:07:43.086003 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 11:07:43.089490 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 11:07:43.092552 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 11:07:43.096187 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 11:07:43.099409 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 11:07:43.100052 Pre-setting of DQS Precalculation
5937 11:07:43.106209 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5938 11:07:43.113203 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5939 11:07:43.119338 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5940 11:07:43.119928
5941 11:07:43.120356
5942 11:07:43.122948 [Calibration Summary] 1866 Mbps
5943 11:07:43.126349 CH 0, Rank 0
5944 11:07:43.126790 SW Impedance : PASS
5945 11:07:43.129387 DUTY Scan : NO K
5946 11:07:43.132802 ZQ Calibration : PASS
5947 11:07:43.133191 Jitter Meter : NO K
5948 11:07:43.135765 CBT Training : PASS
5949 11:07:43.139213 Write leveling : PASS
5950 11:07:43.139731 RX DQS gating : PASS
5951 11:07:43.142861 RX DQ/DQS(RDDQC) : PASS
5952 11:07:43.145483 TX DQ/DQS : PASS
5953 11:07:43.146248 RX DATLAT : PASS
5954 11:07:43.149397 RX DQ/DQS(Engine): PASS
5955 11:07:43.149905 TX OE : NO K
5956 11:07:43.152622 All Pass.
5957 11:07:43.153091
5958 11:07:43.153434 CH 0, Rank 1
5959 11:07:43.156032 SW Impedance : PASS
5960 11:07:43.156424 DUTY Scan : NO K
5961 11:07:43.159847 ZQ Calibration : PASS
5962 11:07:43.162372 Jitter Meter : NO K
5963 11:07:43.162762 CBT Training : PASS
5964 11:07:43.165730 Write leveling : PASS
5965 11:07:43.169563 RX DQS gating : PASS
5966 11:07:43.169951 RX DQ/DQS(RDDQC) : PASS
5967 11:07:43.172247 TX DQ/DQS : PASS
5968 11:07:43.175609 RX DATLAT : PASS
5969 11:07:43.175991 RX DQ/DQS(Engine): PASS
5970 11:07:43.179114 TX OE : NO K
5971 11:07:43.179500 All Pass.
5972 11:07:43.179796
5973 11:07:43.182162 CH 1, Rank 0
5974 11:07:43.182548 SW Impedance : PASS
5975 11:07:43.185757 DUTY Scan : NO K
5976 11:07:43.188932 ZQ Calibration : PASS
5977 11:07:43.189327 Jitter Meter : NO K
5978 11:07:43.192763 CBT Training : PASS
5979 11:07:43.196054 Write leveling : PASS
5980 11:07:43.196445 RX DQS gating : PASS
5981 11:07:43.198965 RX DQ/DQS(RDDQC) : PASS
5982 11:07:43.199359 TX DQ/DQS : PASS
5983 11:07:43.202319 RX DATLAT : PASS
5984 11:07:43.205740 RX DQ/DQS(Engine): PASS
5985 11:07:43.206185 TX OE : NO K
5986 11:07:43.208822 All Pass.
5987 11:07:43.209212
5988 11:07:43.209531 CH 1, Rank 1
5989 11:07:43.212205 SW Impedance : PASS
5990 11:07:43.212594 DUTY Scan : NO K
5991 11:07:43.216262 ZQ Calibration : PASS
5992 11:07:43.219197 Jitter Meter : NO K
5993 11:07:43.219589 CBT Training : PASS
5994 11:07:43.222597 Write leveling : PASS
5995 11:07:43.225514 RX DQS gating : PASS
5996 11:07:43.225932 RX DQ/DQS(RDDQC) : PASS
5997 11:07:43.229452 TX DQ/DQS : PASS
5998 11:07:43.232722 RX DATLAT : PASS
5999 11:07:43.233109 RX DQ/DQS(Engine): PASS
6000 11:07:43.235883 TX OE : NO K
6001 11:07:43.236434 All Pass.
6002 11:07:43.236750
6003 11:07:43.238984 DramC Write-DBI off
6004 11:07:43.242516 PER_BANK_REFRESH: Hybrid Mode
6005 11:07:43.242918 TX_TRACKING: ON
6006 11:07:43.252387 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6007 11:07:43.255830 [FAST_K] Save calibration result to emmc
6008 11:07:43.259084 dramc_set_vcore_voltage set vcore to 650000
6009 11:07:43.262598 Read voltage for 400, 6
6010 11:07:43.263150 Vio18 = 0
6011 11:07:43.263472 Vcore = 650000
6012 11:07:43.265540 Vdram = 0
6013 11:07:43.265921 Vddq = 0
6014 11:07:43.266278 Vmddr = 0
6015 11:07:43.272543 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6016 11:07:43.275738 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6017 11:07:43.278844 MEM_TYPE=3, freq_sel=20
6018 11:07:43.282467 sv_algorithm_assistance_LP4_800
6019 11:07:43.285340 ============ PULL DRAM RESETB DOWN ============
6020 11:07:43.288816 ========== PULL DRAM RESETB DOWN end =========
6021 11:07:43.295764 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 11:07:43.299238 ===================================
6023 11:07:43.299626 LPDDR4 DRAM CONFIGURATION
6024 11:07:43.302560 ===================================
6025 11:07:43.305540 EX_ROW_EN[0] = 0x0
6026 11:07:43.308879 EX_ROW_EN[1] = 0x0
6027 11:07:43.309261 LP4Y_EN = 0x0
6028 11:07:43.312113 WORK_FSP = 0x0
6029 11:07:43.312500 WL = 0x2
6030 11:07:43.315865 RL = 0x2
6031 11:07:43.316351 BL = 0x2
6032 11:07:43.319472 RPST = 0x0
6033 11:07:43.319857 RD_PRE = 0x0
6034 11:07:43.322307 WR_PRE = 0x1
6035 11:07:43.322662 WR_PST = 0x0
6036 11:07:43.325673 DBI_WR = 0x0
6037 11:07:43.326099 DBI_RD = 0x0
6038 11:07:43.328679 OTF = 0x1
6039 11:07:43.331784 ===================================
6040 11:07:43.335343 ===================================
6041 11:07:43.335728 ANA top config
6042 11:07:43.338745 ===================================
6043 11:07:43.341932 DLL_ASYNC_EN = 0
6044 11:07:43.345571 ALL_SLAVE_EN = 1
6045 11:07:43.345955 NEW_RANK_MODE = 1
6046 11:07:43.348432 DLL_IDLE_MODE = 1
6047 11:07:43.352615 LP45_APHY_COMB_EN = 1
6048 11:07:43.355589 TX_ODT_DIS = 1
6049 11:07:43.359110 NEW_8X_MODE = 1
6050 11:07:43.361897 ===================================
6051 11:07:43.365069 ===================================
6052 11:07:43.365453 data_rate = 800
6053 11:07:43.368985 CKR = 1
6054 11:07:43.371686 DQ_P2S_RATIO = 4
6055 11:07:43.375278 ===================================
6056 11:07:43.378941 CA_P2S_RATIO = 4
6057 11:07:43.382079 DQ_CA_OPEN = 0
6058 11:07:43.385809 DQ_SEMI_OPEN = 1
6059 11:07:43.386316 CA_SEMI_OPEN = 1
6060 11:07:43.388391 CA_FULL_RATE = 0
6061 11:07:43.391482 DQ_CKDIV4_EN = 0
6062 11:07:43.395101 CA_CKDIV4_EN = 1
6063 11:07:43.398464 CA_PREDIV_EN = 0
6064 11:07:43.401444 PH8_DLY = 0
6065 11:07:43.401829 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6066 11:07:43.405076 DQ_AAMCK_DIV = 0
6067 11:07:43.408451 CA_AAMCK_DIV = 0
6068 11:07:43.411846 CA_ADMCK_DIV = 4
6069 11:07:43.415194 DQ_TRACK_CA_EN = 0
6070 11:07:43.418309 CA_PICK = 800
6071 11:07:43.418696 CA_MCKIO = 400
6072 11:07:43.421527 MCKIO_SEMI = 400
6073 11:07:43.424954 PLL_FREQ = 3016
6074 11:07:43.428497 DQ_UI_PI_RATIO = 32
6075 11:07:43.431688 CA_UI_PI_RATIO = 32
6076 11:07:43.435091 ===================================
6077 11:07:43.438041 ===================================
6078 11:07:43.441623 memory_type:LPDDR4
6079 11:07:43.442042 GP_NUM : 10
6080 11:07:43.444901 SRAM_EN : 1
6081 11:07:43.448183 MD32_EN : 0
6082 11:07:43.452092 ===================================
6083 11:07:43.452517 [ANA_INIT] >>>>>>>>>>>>>>
6084 11:07:43.454832 <<<<<< [CONFIGURE PHASE]: ANA_TX
6085 11:07:43.457981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6086 11:07:43.461333 ===================================
6087 11:07:43.464737 data_rate = 800,PCW = 0X7400
6088 11:07:43.468139 ===================================
6089 11:07:43.471161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6090 11:07:43.478446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 11:07:43.488655 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 11:07:43.491619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6093 11:07:43.497734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6094 11:07:43.501581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6095 11:07:43.501971 [ANA_INIT] flow start
6096 11:07:43.504787 [ANA_INIT] PLL >>>>>>>>
6097 11:07:43.507693 [ANA_INIT] PLL <<<<<<<<
6098 11:07:43.508209 [ANA_INIT] MIDPI >>>>>>>>
6099 11:07:43.511163 [ANA_INIT] MIDPI <<<<<<<<
6100 11:07:43.514529 [ANA_INIT] DLL >>>>>>>>
6101 11:07:43.514942 [ANA_INIT] flow end
6102 11:07:43.517615 ============ LP4 DIFF to SE enter ============
6103 11:07:43.524523 ============ LP4 DIFF to SE exit ============
6104 11:07:43.525127 [ANA_INIT] <<<<<<<<<<<<<
6105 11:07:43.527643 [Flow] Enable top DCM control >>>>>
6106 11:07:43.530866 [Flow] Enable top DCM control <<<<<
6107 11:07:43.534207 Enable DLL master slave shuffle
6108 11:07:43.540770 ==============================================================
6109 11:07:43.544695 Gating Mode config
6110 11:07:43.548052 ==============================================================
6111 11:07:43.551176 Config description:
6112 11:07:43.561366 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6113 11:07:43.567488 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6114 11:07:43.571099 SELPH_MODE 0: By rank 1: By Phase
6115 11:07:43.577441 ==============================================================
6116 11:07:43.581172 GAT_TRACK_EN = 0
6117 11:07:43.584473 RX_GATING_MODE = 2
6118 11:07:43.584918 RX_GATING_TRACK_MODE = 2
6119 11:07:43.587861 SELPH_MODE = 1
6120 11:07:43.590768 PICG_EARLY_EN = 1
6121 11:07:43.594328 VALID_LAT_VALUE = 1
6122 11:07:43.600738 ==============================================================
6123 11:07:43.604470 Enter into Gating configuration >>>>
6124 11:07:43.607522 Exit from Gating configuration <<<<
6125 11:07:43.610720 Enter into DVFS_PRE_config >>>>>
6126 11:07:43.620755 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6127 11:07:43.624536 Exit from DVFS_PRE_config <<<<<
6128 11:07:43.627468 Enter into PICG configuration >>>>
6129 11:07:43.631185 Exit from PICG configuration <<<<
6130 11:07:43.634192 [RX_INPUT] configuration >>>>>
6131 11:07:43.637368 [RX_INPUT] configuration <<<<<
6132 11:07:43.640495 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6133 11:07:43.647563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6134 11:07:43.654210 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 11:07:43.657399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 11:07:43.663908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 11:07:43.671022 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 11:07:43.674265 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6139 11:07:43.680664 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6140 11:07:43.684394 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6141 11:07:43.687480 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6142 11:07:43.690700 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6143 11:07:43.697490 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 11:07:43.700695 ===================================
6145 11:07:43.701102 LPDDR4 DRAM CONFIGURATION
6146 11:07:43.704013 ===================================
6147 11:07:43.707225 EX_ROW_EN[0] = 0x0
6148 11:07:43.710468 EX_ROW_EN[1] = 0x0
6149 11:07:43.710901 LP4Y_EN = 0x0
6150 11:07:43.714313 WORK_FSP = 0x0
6151 11:07:43.714717 WL = 0x2
6152 11:07:43.717524 RL = 0x2
6153 11:07:43.717924 BL = 0x2
6154 11:07:43.720780 RPST = 0x0
6155 11:07:43.721186 RD_PRE = 0x0
6156 11:07:43.723824 WR_PRE = 0x1
6157 11:07:43.724225 WR_PST = 0x0
6158 11:07:43.727615 DBI_WR = 0x0
6159 11:07:43.728016 DBI_RD = 0x0
6160 11:07:43.730774 OTF = 0x1
6161 11:07:43.733791 ===================================
6162 11:07:43.736701 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6163 11:07:43.740957 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6164 11:07:43.747075 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 11:07:43.750496 ===================================
6166 11:07:43.750936 LPDDR4 DRAM CONFIGURATION
6167 11:07:43.753814 ===================================
6168 11:07:43.757727 EX_ROW_EN[0] = 0x10
6169 11:07:43.758273 EX_ROW_EN[1] = 0x0
6170 11:07:43.760371 LP4Y_EN = 0x0
6171 11:07:43.763743 WORK_FSP = 0x0
6172 11:07:43.764130 WL = 0x2
6173 11:07:43.767024 RL = 0x2
6174 11:07:43.767415 BL = 0x2
6175 11:07:43.770426 RPST = 0x0
6176 11:07:43.770814 RD_PRE = 0x0
6177 11:07:43.773820 WR_PRE = 0x1
6178 11:07:43.774381 WR_PST = 0x0
6179 11:07:43.776873 DBI_WR = 0x0
6180 11:07:43.777261 DBI_RD = 0x0
6181 11:07:43.780292 OTF = 0x1
6182 11:07:43.783797 ===================================
6183 11:07:43.790510 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6184 11:07:43.793622 nWR fixed to 30
6185 11:07:43.794204 [ModeRegInit_LP4] CH0 RK0
6186 11:07:43.796873 [ModeRegInit_LP4] CH0 RK1
6187 11:07:43.800763 [ModeRegInit_LP4] CH1 RK0
6188 11:07:43.801267 [ModeRegInit_LP4] CH1 RK1
6189 11:07:43.803661 match AC timing 19
6190 11:07:43.806868 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6191 11:07:43.810173 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6192 11:07:43.816913 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6193 11:07:43.820024 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6194 11:07:43.827084 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6195 11:07:43.827469 ==
6196 11:07:43.830616 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 11:07:43.833772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6198 11:07:43.834316 ==
6199 11:07:43.840647 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6200 11:07:43.843710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6201 11:07:43.847057 [CA 0] Center 36 (8~64) winsize 57
6202 11:07:43.850655 [CA 1] Center 36 (8~64) winsize 57
6203 11:07:43.853677 [CA 2] Center 36 (8~64) winsize 57
6204 11:07:43.857150 [CA 3] Center 36 (8~64) winsize 57
6205 11:07:43.860245 [CA 4] Center 36 (8~64) winsize 57
6206 11:07:43.863646 [CA 5] Center 36 (8~64) winsize 57
6207 11:07:43.863724
6208 11:07:43.866847 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6209 11:07:43.866925
6210 11:07:43.870050 [CATrainingPosCal] consider 1 rank data
6211 11:07:43.873162 u2DelayCellTimex100 = 270/100 ps
6212 11:07:43.876699 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 11:07:43.879575 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 11:07:43.883166 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:07:43.889745 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 11:07:43.893513 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 11:07:43.896634 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:07:43.896731
6219 11:07:43.900040 CA PerBit enable=1, Macro0, CA PI delay=36
6220 11:07:43.900146
6221 11:07:43.902907 [CBTSetCACLKResult] CA Dly = 36
6222 11:07:43.903013 CS Dly: 1 (0~32)
6223 11:07:43.903118 ==
6224 11:07:43.906194 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 11:07:43.913314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 11:07:43.913460 ==
6227 11:07:43.916255 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 11:07:43.923494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6229 11:07:43.926164 [CA 0] Center 36 (8~64) winsize 57
6230 11:07:43.930233 [CA 1] Center 36 (8~64) winsize 57
6231 11:07:43.933299 [CA 2] Center 36 (8~64) winsize 57
6232 11:07:43.936227 [CA 3] Center 36 (8~64) winsize 57
6233 11:07:43.940095 [CA 4] Center 36 (8~64) winsize 57
6234 11:07:43.943327 [CA 5] Center 36 (8~64) winsize 57
6235 11:07:43.943729
6236 11:07:43.946449 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6237 11:07:43.946939
6238 11:07:43.949958 [CATrainingPosCal] consider 2 rank data
6239 11:07:43.953406 u2DelayCellTimex100 = 270/100 ps
6240 11:07:43.956387 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 11:07:43.959759 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:07:43.963096 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:07:43.965968 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:07:43.969593 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:07:43.976477 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:07:43.976878
6247 11:07:43.979828 CA PerBit enable=1, Macro0, CA PI delay=36
6248 11:07:43.980230
6249 11:07:43.983465 [CBTSetCACLKResult] CA Dly = 36
6250 11:07:43.983867 CS Dly: 1 (0~32)
6251 11:07:43.984263
6252 11:07:43.986384 ----->DramcWriteLeveling(PI) begin...
6253 11:07:43.987050 ==
6254 11:07:43.989791 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 11:07:43.992898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 11:07:43.996336 ==
6257 11:07:43.996753 Write leveling (Byte 0): 40 => 8
6258 11:07:43.999372 Write leveling (Byte 1): 40 => 8
6259 11:07:44.002887 DramcWriteLeveling(PI) end<-----
6260 11:07:44.003289
6261 11:07:44.003687 ==
6262 11:07:44.006287 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 11:07:44.012898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 11:07:44.013302 ==
6265 11:07:44.013708 [Gating] SW mode calibration
6266 11:07:44.022715 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6267 11:07:44.025881 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6268 11:07:44.029389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 11:07:44.036077 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 11:07:44.039414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 11:07:44.042828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 11:07:44.049713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 11:07:44.052773 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 11:07:44.056381 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 11:07:44.062999 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 11:07:44.066173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 11:07:44.069271 Total UI for P1: 0, mck2ui 16
6278 11:07:44.072939 best dqsien dly found for B0: ( 0, 14, 24)
6279 11:07:44.076003 Total UI for P1: 0, mck2ui 16
6280 11:07:44.079290 best dqsien dly found for B1: ( 0, 14, 24)
6281 11:07:44.082896 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6282 11:07:44.085993 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6283 11:07:44.086420
6284 11:07:44.089258 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 11:07:44.092758 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 11:07:44.096273 [Gating] SW calibration Done
6287 11:07:44.096655 ==
6288 11:07:44.099234 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 11:07:44.105922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 11:07:44.106357 ==
6291 11:07:44.106656 RX Vref Scan: 0
6292 11:07:44.106931
6293 11:07:44.109018 RX Vref 0 -> 0, step: 1
6294 11:07:44.109404
6295 11:07:44.112349 RX Delay -410 -> 252, step: 16
6296 11:07:44.115858 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6297 11:07:44.119442 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6298 11:07:44.125748 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6299 11:07:44.128871 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6300 11:07:44.132279 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6301 11:07:44.136164 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6302 11:07:44.139037 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6303 11:07:44.145850 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6304 11:07:44.149070 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6305 11:07:44.152204 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6306 11:07:44.155396 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6307 11:07:44.162758 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6308 11:07:44.165634 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6309 11:07:44.168623 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6310 11:07:44.175789 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6311 11:07:44.178428 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6312 11:07:44.178589 ==
6313 11:07:44.182640 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 11:07:44.185761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:07:44.185988 ==
6316 11:07:44.186149 DQS Delay:
6317 11:07:44.188942 DQS0 = 27, DQS1 = 35
6318 11:07:44.189090 DQM Delay:
6319 11:07:44.191913 DQM0 = 10, DQM1 = 11
6320 11:07:44.192109 DQ Delay:
6321 11:07:44.195899 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6322 11:07:44.199257 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6323 11:07:44.202515 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6324 11:07:44.205251 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6325 11:07:44.205414
6326 11:07:44.205559
6327 11:07:44.205679 ==
6328 11:07:44.208841 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 11:07:44.212571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 11:07:44.212758 ==
6331 11:07:44.212895
6332 11:07:44.215160
6333 11:07:44.215299 TX Vref Scan disable
6334 11:07:44.218847 == TX Byte 0 ==
6335 11:07:44.222143 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 11:07:44.225280 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 11:07:44.228818 == TX Byte 1 ==
6338 11:07:44.232217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 11:07:44.235605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 11:07:44.235994 ==
6341 11:07:44.239169 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 11:07:44.242164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 11:07:44.242605 ==
6344 11:07:44.245172
6345 11:07:44.245592
6346 11:07:44.246180 TX Vref Scan disable
6347 11:07:44.248920 == TX Byte 0 ==
6348 11:07:44.251980 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 11:07:44.255651 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 11:07:44.258530 == TX Byte 1 ==
6351 11:07:44.262062 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 11:07:44.265798 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 11:07:44.266244
6354 11:07:44.266536 [DATLAT]
6355 11:07:44.269007 Freq=400, CH0 RK0
6356 11:07:44.269385
6357 11:07:44.269678 DATLAT Default: 0xf
6358 11:07:44.272333 0, 0xFFFF, sum = 0
6359 11:07:44.275354 1, 0xFFFF, sum = 0
6360 11:07:44.275757 2, 0xFFFF, sum = 0
6361 11:07:44.279251 3, 0xFFFF, sum = 0
6362 11:07:44.279639 4, 0xFFFF, sum = 0
6363 11:07:44.281989 5, 0xFFFF, sum = 0
6364 11:07:44.282425 6, 0xFFFF, sum = 0
6365 11:07:44.285203 7, 0xFFFF, sum = 0
6366 11:07:44.285594 8, 0xFFFF, sum = 0
6367 11:07:44.289379 9, 0xFFFF, sum = 0
6368 11:07:44.289811 10, 0xFFFF, sum = 0
6369 11:07:44.292324 11, 0xFFFF, sum = 0
6370 11:07:44.292748 12, 0xFFFF, sum = 0
6371 11:07:44.295587 13, 0x0, sum = 1
6372 11:07:44.296068 14, 0x0, sum = 2
6373 11:07:44.298678 15, 0x0, sum = 3
6374 11:07:44.299101 16, 0x0, sum = 4
6375 11:07:44.302081 best_step = 14
6376 11:07:44.302475
6377 11:07:44.302903 ==
6378 11:07:44.305790 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 11:07:44.308589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 11:07:44.308973 ==
6381 11:07:44.309267 RX Vref Scan: 1
6382 11:07:44.312365
6383 11:07:44.312822 RX Vref 0 -> 0, step: 1
6384 11:07:44.313119
6385 11:07:44.315986 RX Delay -311 -> 252, step: 8
6386 11:07:44.316409
6387 11:07:44.318679 Set Vref, RX VrefLevel [Byte0]: 55
6388 11:07:44.321750 [Byte1]: 54
6389 11:07:44.325597
6390 11:07:44.326197 Final RX Vref Byte 0 = 55 to rank0
6391 11:07:44.328987 Final RX Vref Byte 1 = 54 to rank0
6392 11:07:44.332505 Final RX Vref Byte 0 = 55 to rank1
6393 11:07:44.336043 Final RX Vref Byte 1 = 54 to rank1==
6394 11:07:44.339195 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 11:07:44.346323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 11:07:44.346729 ==
6397 11:07:44.347169 DQS Delay:
6398 11:07:44.349316 DQS0 = 28, DQS1 = 36
6399 11:07:44.349687 DQM Delay:
6400 11:07:44.350151 DQM0 = 11, DQM1 = 12
6401 11:07:44.352758 DQ Delay:
6402 11:07:44.355923 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6403 11:07:44.356311 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6404 11:07:44.359445 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6405 11:07:44.362481 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6406 11:07:44.362884
6407 11:07:44.363186
6408 11:07:44.372567 [DQSOSCAuto] RK0, (LSB)MR18= 0xd7c4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6409 11:07:44.375769 CH0 RK0: MR19=C0C, MR18=D7C4
6410 11:07:44.382556 CH0_RK0: MR19=0xC0C, MR18=0xD7C4, DQSOSC=383, MR23=63, INC=402, DEC=268
6411 11:07:44.382950 ==
6412 11:07:44.385665 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 11:07:44.389361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 11:07:44.389782 ==
6415 11:07:44.392521 [Gating] SW mode calibration
6416 11:07:44.399200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6417 11:07:44.402587 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6418 11:07:44.409035 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 11:07:44.413228 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 11:07:44.416445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 11:07:44.422596 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 11:07:44.425794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 11:07:44.429365 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 11:07:44.436070 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:07:44.439475 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:07:44.442355 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 11:07:44.445982 Total UI for P1: 0, mck2ui 16
6428 11:07:44.449392 best dqsien dly found for B0: ( 0, 14, 24)
6429 11:07:44.452768 Total UI for P1: 0, mck2ui 16
6430 11:07:44.455992 best dqsien dly found for B1: ( 0, 14, 24)
6431 11:07:44.459301 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6432 11:07:44.462970 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6433 11:07:44.463923
6434 11:07:44.469569 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 11:07:44.472886 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 11:07:44.473301 [Gating] SW calibration Done
6437 11:07:44.475788 ==
6438 11:07:44.476285 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 11:07:44.482692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 11:07:44.483103 ==
6441 11:07:44.483403 RX Vref Scan: 0
6442 11:07:44.483676
6443 11:07:44.485468 RX Vref 0 -> 0, step: 1
6444 11:07:44.485543
6445 11:07:44.489500 RX Delay -410 -> 252, step: 16
6446 11:07:44.492599 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6447 11:07:44.495744 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6448 11:07:44.502659 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6449 11:07:44.505559 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6450 11:07:44.508785 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6451 11:07:44.511932 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6452 11:07:44.518920 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6453 11:07:44.522435 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6454 11:07:44.525344 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6455 11:07:44.528852 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6456 11:07:44.535688 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6457 11:07:44.538808 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6458 11:07:44.541893 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6459 11:07:44.548527 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6460 11:07:44.551847 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6461 11:07:44.555356 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6462 11:07:44.555658 ==
6463 11:07:44.558692 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 11:07:44.561680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 11:07:44.562042 ==
6466 11:07:44.565519 DQS Delay:
6467 11:07:44.565901 DQS0 = 19, DQS1 = 35
6468 11:07:44.568429 DQM Delay:
6469 11:07:44.568980 DQM0 = 5, DQM1 = 10
6470 11:07:44.571719 DQ Delay:
6471 11:07:44.572190 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6472 11:07:44.575762 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6473 11:07:44.578481 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6474 11:07:44.582228 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6475 11:07:44.582675
6476 11:07:44.583009
6477 11:07:44.583303 ==
6478 11:07:44.585320 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 11:07:44.591635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 11:07:44.592210 ==
6481 11:07:44.592657
6482 11:07:44.593212
6483 11:07:44.593516 TX Vref Scan disable
6484 11:07:44.595420 == TX Byte 0 ==
6485 11:07:44.598179 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6486 11:07:44.601937 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6487 11:07:44.604754 == TX Byte 1 ==
6488 11:07:44.608853 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6489 11:07:44.611602 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6490 11:07:44.611987 ==
6491 11:07:44.615287 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 11:07:44.621441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 11:07:44.621948 ==
6494 11:07:44.622490
6495 11:07:44.622825
6496 11:07:44.625667 TX Vref Scan disable
6497 11:07:44.626543 == TX Byte 0 ==
6498 11:07:44.628465 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6499 11:07:44.631915 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6500 11:07:44.635118 == TX Byte 1 ==
6501 11:07:44.638233 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6502 11:07:44.642190 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6503 11:07:44.642585
6504 11:07:44.644518 [DATLAT]
6505 11:07:44.644856 Freq=400, CH0 RK1
6506 11:07:44.645136
6507 11:07:44.648166 DATLAT Default: 0xe
6508 11:07:44.648600 0, 0xFFFF, sum = 0
6509 11:07:44.651489 1, 0xFFFF, sum = 0
6510 11:07:44.651878 2, 0xFFFF, sum = 0
6511 11:07:44.654878 3, 0xFFFF, sum = 0
6512 11:07:44.655280 4, 0xFFFF, sum = 0
6513 11:07:44.658260 5, 0xFFFF, sum = 0
6514 11:07:44.658679 6, 0xFFFF, sum = 0
6515 11:07:44.661394 7, 0xFFFF, sum = 0
6516 11:07:44.664732 8, 0xFFFF, sum = 0
6517 11:07:44.665143 9, 0xFFFF, sum = 0
6518 11:07:44.668210 10, 0xFFFF, sum = 0
6519 11:07:44.668626 11, 0xFFFF, sum = 0
6520 11:07:44.671418 12, 0xFFFF, sum = 0
6521 11:07:44.671764 13, 0x0, sum = 1
6522 11:07:44.674983 14, 0x0, sum = 2
6523 11:07:44.675494 15, 0x0, sum = 3
6524 11:07:44.677713 16, 0x0, sum = 4
6525 11:07:44.678182 best_step = 14
6526 11:07:44.678491
6527 11:07:44.678787 ==
6528 11:07:44.681351 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 11:07:44.684694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 11:07:44.685197 ==
6531 11:07:44.687960 RX Vref Scan: 0
6532 11:07:44.688408
6533 11:07:44.691002 RX Vref 0 -> 0, step: 1
6534 11:07:44.691384
6535 11:07:44.691724 RX Delay -311 -> 252, step: 8
6536 11:07:44.700080 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6537 11:07:44.703011 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6538 11:07:44.706996 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6539 11:07:44.710065 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6540 11:07:44.716173 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6541 11:07:44.719795 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6542 11:07:44.723091 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6543 11:07:44.726695 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6544 11:07:44.733325 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6545 11:07:44.736514 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6546 11:07:44.739688 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6547 11:07:44.742860 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6548 11:07:44.749255 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6549 11:07:44.752626 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6550 11:07:44.756488 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6551 11:07:44.762960 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6552 11:07:44.763346 ==
6553 11:07:44.765898 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:07:44.769586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:07:44.770134 ==
6556 11:07:44.770473 DQS Delay:
6557 11:07:44.772688 DQS0 = 24, DQS1 = 32
6558 11:07:44.773095 DQM Delay:
6559 11:07:44.776344 DQM0 = 9, DQM1 = 9
6560 11:07:44.776746 DQ Delay:
6561 11:07:44.779334 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6562 11:07:44.783070 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6563 11:07:44.785991 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6564 11:07:44.789218 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6565 11:07:44.789721
6566 11:07:44.790071
6567 11:07:44.796218 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6568 11:07:44.799413 CH0 RK1: MR19=C0C, MR18=BE5D
6569 11:07:44.805868 CH0_RK1: MR19=0xC0C, MR18=0xBE5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6570 11:07:44.808857 [RxdqsGatingPostProcess] freq 400
6571 11:07:44.815684 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6572 11:07:44.816165 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 11:07:44.819404 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 11:07:44.822416 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 11:07:44.825894 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 11:07:44.829304 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 11:07:44.832529 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 11:07:44.836023 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 11:07:44.839224 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 11:07:44.842487 Pre-setting of DQS Precalculation
6581 11:07:44.846467 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6582 11:07:44.849445 ==
6583 11:07:44.852465 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 11:07:44.855821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 11:07:44.856219 ==
6586 11:07:44.859102 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6587 11:07:44.865684 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6588 11:07:44.868981 [CA 0] Center 36 (8~64) winsize 57
6589 11:07:44.872462 [CA 1] Center 36 (8~64) winsize 57
6590 11:07:44.875590 [CA 2] Center 36 (8~64) winsize 57
6591 11:07:44.878988 [CA 3] Center 36 (8~64) winsize 57
6592 11:07:44.882301 [CA 4] Center 36 (8~64) winsize 57
6593 11:07:44.885753 [CA 5] Center 36 (8~64) winsize 57
6594 11:07:44.886188
6595 11:07:44.888736 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6596 11:07:44.889143
6597 11:07:44.892667 [CATrainingPosCal] consider 1 rank data
6598 11:07:44.895964 u2DelayCellTimex100 = 270/100 ps
6599 11:07:44.898912 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 11:07:44.902173 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 11:07:44.905783 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:07:44.909398 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 11:07:44.912461 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 11:07:44.918962 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:07:44.919346
6606 11:07:44.922902 CA PerBit enable=1, Macro0, CA PI delay=36
6607 11:07:44.923348
6608 11:07:44.926096 [CBTSetCACLKResult] CA Dly = 36
6609 11:07:44.926494 CS Dly: 1 (0~32)
6610 11:07:44.926791 ==
6611 11:07:44.929314 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 11:07:44.932305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 11:07:44.932691 ==
6614 11:07:44.939228 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 11:07:44.945848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6616 11:07:44.949021 [CA 0] Center 36 (8~64) winsize 57
6617 11:07:44.952344 [CA 1] Center 36 (8~64) winsize 57
6618 11:07:44.955582 [CA 2] Center 36 (8~64) winsize 57
6619 11:07:44.959267 [CA 3] Center 36 (8~64) winsize 57
6620 11:07:44.962224 [CA 4] Center 36 (8~64) winsize 57
6621 11:07:44.962602 [CA 5] Center 36 (8~64) winsize 57
6622 11:07:44.965280
6623 11:07:44.968647 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6624 11:07:44.969032
6625 11:07:44.972125 [CATrainingPosCal] consider 2 rank data
6626 11:07:44.976064 u2DelayCellTimex100 = 270/100 ps
6627 11:07:44.979347 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 11:07:44.982417 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:07:44.985418 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:07:44.988809 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:07:44.992429 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:07:44.996091 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:07:44.996474
6634 11:07:44.999039 CA PerBit enable=1, Macro0, CA PI delay=36
6635 11:07:44.999421
6636 11:07:45.002501 [CBTSetCACLKResult] CA Dly = 36
6637 11:07:45.005468 CS Dly: 1 (0~32)
6638 11:07:45.005885
6639 11:07:45.008994 ----->DramcWriteLeveling(PI) begin...
6640 11:07:45.009388 ==
6641 11:07:45.012271 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 11:07:45.015830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:07:45.016223 ==
6644 11:07:45.019056 Write leveling (Byte 0): 40 => 8
6645 11:07:45.022306 Write leveling (Byte 1): 40 => 8
6646 11:07:45.025497 DramcWriteLeveling(PI) end<-----
6647 11:07:45.025959
6648 11:07:45.026423 ==
6649 11:07:45.029190 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 11:07:45.032787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 11:07:45.033260 ==
6652 11:07:45.035778 [Gating] SW mode calibration
6653 11:07:45.041967 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 11:07:45.048835 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6655 11:07:45.052785 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 11:07:45.055857 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 11:07:45.061988 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 11:07:45.065512 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 11:07:45.069198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 11:07:45.075219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 11:07:45.078860 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 11:07:45.082060 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 11:07:45.088276 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 11:07:45.092132 Total UI for P1: 0, mck2ui 16
6665 11:07:45.095223 best dqsien dly found for B0: ( 0, 14, 24)
6666 11:07:45.098560 Total UI for P1: 0, mck2ui 16
6667 11:07:45.101697 best dqsien dly found for B1: ( 0, 14, 24)
6668 11:07:45.105410 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6669 11:07:45.108662 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6670 11:07:45.109048
6671 11:07:45.111921 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 11:07:45.115536 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 11:07:45.118614 [Gating] SW calibration Done
6674 11:07:45.119002 ==
6675 11:07:45.121852 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 11:07:45.125404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 11:07:45.125792 ==
6678 11:07:45.128758 RX Vref Scan: 0
6679 11:07:45.129164
6680 11:07:45.129467 RX Vref 0 -> 0, step: 1
6681 11:07:45.129750
6682 11:07:45.131999 RX Delay -410 -> 252, step: 16
6683 11:07:45.138760 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6684 11:07:45.141669 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6685 11:07:45.145151 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6686 11:07:45.148675 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6687 11:07:45.155483 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6688 11:07:45.158857 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6689 11:07:45.162277 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6690 11:07:45.165452 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6691 11:07:45.171957 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6692 11:07:45.175330 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6693 11:07:45.178096 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6694 11:07:45.181431 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6695 11:07:45.188163 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6696 11:07:45.191561 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6697 11:07:45.194924 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6698 11:07:45.201450 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6699 11:07:45.202071 ==
6700 11:07:45.205037 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 11:07:45.208014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:07:45.208437 ==
6703 11:07:45.208951 DQS Delay:
6704 11:07:45.211466 DQS0 = 35, DQS1 = 35
6705 11:07:45.212040 DQM Delay:
6706 11:07:45.214622 DQM0 = 18, DQM1 = 13
6707 11:07:45.215146 DQ Delay:
6708 11:07:45.217787 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6709 11:07:45.221697 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6710 11:07:45.224853 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6711 11:07:45.228090 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6712 11:07:45.228582
6713 11:07:45.229075
6714 11:07:45.229561 ==
6715 11:07:45.231454 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 11:07:45.235061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 11:07:45.235549 ==
6718 11:07:45.236076
6719 11:07:45.236540
6720 11:07:45.238396 TX Vref Scan disable
6721 11:07:45.238799 == TX Byte 0 ==
6722 11:07:45.244469 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 11:07:45.248257 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 11:07:45.248730 == TX Byte 1 ==
6725 11:07:45.254707 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 11:07:45.257727 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 11:07:45.258378 ==
6728 11:07:45.261597 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 11:07:45.264714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 11:07:45.265330 ==
6731 11:07:45.265781
6732 11:07:45.266260
6733 11:07:45.267745 TX Vref Scan disable
6734 11:07:45.268143 == TX Byte 0 ==
6735 11:07:45.274871 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 11:07:45.277596 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 11:07:45.277987 == TX Byte 1 ==
6738 11:07:45.284865 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 11:07:45.288215 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 11:07:45.288617
6741 11:07:45.289114 [DATLAT]
6742 11:07:45.290990 Freq=400, CH1 RK0
6743 11:07:45.291398
6744 11:07:45.291790 DATLAT Default: 0xf
6745 11:07:45.294707 0, 0xFFFF, sum = 0
6746 11:07:45.295114 1, 0xFFFF, sum = 0
6747 11:07:45.298060 2, 0xFFFF, sum = 0
6748 11:07:45.298474 3, 0xFFFF, sum = 0
6749 11:07:45.301398 4, 0xFFFF, sum = 0
6750 11:07:45.301807 5, 0xFFFF, sum = 0
6751 11:07:45.304890 6, 0xFFFF, sum = 0
6752 11:07:45.305328 7, 0xFFFF, sum = 0
6753 11:07:45.308028 8, 0xFFFF, sum = 0
6754 11:07:45.311081 9, 0xFFFF, sum = 0
6755 11:07:45.311510 10, 0xFFFF, sum = 0
6756 11:07:45.314880 11, 0xFFFF, sum = 0
6757 11:07:45.315431 12, 0xFFFF, sum = 0
6758 11:07:45.318085 13, 0x0, sum = 1
6759 11:07:45.318491 14, 0x0, sum = 2
6760 11:07:45.321074 15, 0x0, sum = 3
6761 11:07:45.321480 16, 0x0, sum = 4
6762 11:07:45.321886 best_step = 14
6763 11:07:45.322317
6764 11:07:45.324928 ==
6765 11:07:45.328039 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 11:07:45.331055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 11:07:45.331459 ==
6768 11:07:45.331859 RX Vref Scan: 1
6769 11:07:45.332232
6770 11:07:45.334423 RX Vref 0 -> 0, step: 1
6771 11:07:45.334828
6772 11:07:45.338073 RX Delay -311 -> 252, step: 8
6773 11:07:45.338479
6774 11:07:45.340912 Set Vref, RX VrefLevel [Byte0]: 55
6775 11:07:45.344199 [Byte1]: 52
6776 11:07:45.347965
6777 11:07:45.348352 Final RX Vref Byte 0 = 55 to rank0
6778 11:07:45.351320 Final RX Vref Byte 1 = 52 to rank0
6779 11:07:45.354296 Final RX Vref Byte 0 = 55 to rank1
6780 11:07:45.357806 Final RX Vref Byte 1 = 52 to rank1==
6781 11:07:45.361393 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 11:07:45.368096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 11:07:45.368603 ==
6784 11:07:45.369006 DQS Delay:
6785 11:07:45.370904 DQS0 = 32, DQS1 = 32
6786 11:07:45.371306 DQM Delay:
6787 11:07:45.371704 DQM0 = 13, DQM1 = 10
6788 11:07:45.374102 DQ Delay:
6789 11:07:45.377642 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6790 11:07:45.381730 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6791 11:07:45.382172 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6792 11:07:45.384592 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6793 11:07:45.384997
6794 11:07:45.387886
6795 11:07:45.394646 [DQSOSCAuto] RK0, (LSB)MR18= 0x9bd3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6796 11:07:45.397624 CH1 RK0: MR19=C0C, MR18=9BD3
6797 11:07:45.404289 CH1_RK0: MR19=0xC0C, MR18=0x9BD3, DQSOSC=383, MR23=63, INC=402, DEC=268
6798 11:07:45.404693 ==
6799 11:07:45.408167 Dram Type= 6, Freq= 0, CH_1, rank 1
6800 11:07:45.411671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 11:07:45.412076 ==
6802 11:07:45.414864 [Gating] SW mode calibration
6803 11:07:45.421517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6804 11:07:45.424692 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6805 11:07:45.431242 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 11:07:45.434485 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 11:07:45.437685 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 11:07:45.444872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 11:07:45.447722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 11:07:45.451141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 11:07:45.457710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 11:07:45.461059 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 11:07:45.464447 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 11:07:45.468231 Total UI for P1: 0, mck2ui 16
6815 11:07:45.470953 best dqsien dly found for B0: ( 0, 14, 24)
6816 11:07:45.474608 Total UI for P1: 0, mck2ui 16
6817 11:07:45.477378 best dqsien dly found for B1: ( 0, 14, 24)
6818 11:07:45.481176 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6819 11:07:45.484305 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6820 11:07:45.487439
6821 11:07:45.491283 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 11:07:45.494386 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 11:07:45.497489 [Gating] SW calibration Done
6824 11:07:45.497892 ==
6825 11:07:45.501413 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 11:07:45.504262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 11:07:45.504653 ==
6828 11:07:45.504990 RX Vref Scan: 0
6829 11:07:45.505273
6830 11:07:45.507502 RX Vref 0 -> 0, step: 1
6831 11:07:45.508061
6832 11:07:45.511307 RX Delay -410 -> 252, step: 16
6833 11:07:45.513894 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6834 11:07:45.520680 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6835 11:07:45.523982 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6836 11:07:45.527609 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6837 11:07:45.531005 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6838 11:07:45.536867 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6839 11:07:45.540500 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6840 11:07:45.543957 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6841 11:07:45.546920 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6842 11:07:45.550334 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6843 11:07:45.557901 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6844 11:07:45.560827 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6845 11:07:45.563709 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6846 11:07:45.570846 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6847 11:07:45.573900 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6848 11:07:45.577193 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6849 11:07:45.577602 ==
6850 11:07:45.580132 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 11:07:45.583636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 11:07:45.586873 ==
6853 11:07:45.587281 DQS Delay:
6854 11:07:45.587687 DQS0 = 35, DQS1 = 35
6855 11:07:45.590179 DQM Delay:
6856 11:07:45.590569 DQM0 = 18, DQM1 = 13
6857 11:07:45.593906 DQ Delay:
6858 11:07:45.597599 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6859 11:07:45.597984 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6860 11:07:45.600245 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6861 11:07:45.603874 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6862 11:07:45.604403
6863 11:07:45.604838
6864 11:07:45.606958 ==
6865 11:07:45.610516 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 11:07:45.613636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 11:07:45.614080 ==
6868 11:07:45.614433
6869 11:07:45.614910
6870 11:07:45.617521 TX Vref Scan disable
6871 11:07:45.617904 == TX Byte 0 ==
6872 11:07:45.620190 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6873 11:07:45.626889 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6874 11:07:45.627276 == TX Byte 1 ==
6875 11:07:45.630166 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6876 11:07:45.636959 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6877 11:07:45.637343 ==
6878 11:07:45.640109 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 11:07:45.643759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 11:07:45.644143 ==
6881 11:07:45.644440
6882 11:07:45.644709
6883 11:07:45.647041 TX Vref Scan disable
6884 11:07:45.647430 == TX Byte 0 ==
6885 11:07:45.650068 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6886 11:07:45.656736 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6887 11:07:45.657164 == TX Byte 1 ==
6888 11:07:45.660513 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6889 11:07:45.667252 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6890 11:07:45.667647
6891 11:07:45.667942 [DATLAT]
6892 11:07:45.668264 Freq=400, CH1 RK1
6893 11:07:45.668725
6894 11:07:45.670141 DATLAT Default: 0xe
6895 11:07:45.670528 0, 0xFFFF, sum = 0
6896 11:07:45.673527 1, 0xFFFF, sum = 0
6897 11:07:45.677108 2, 0xFFFF, sum = 0
6898 11:07:45.677505 3, 0xFFFF, sum = 0
6899 11:07:45.680426 4, 0xFFFF, sum = 0
6900 11:07:45.680822 5, 0xFFFF, sum = 0
6901 11:07:45.683675 6, 0xFFFF, sum = 0
6902 11:07:45.684072 7, 0xFFFF, sum = 0
6903 11:07:45.686637 8, 0xFFFF, sum = 0
6904 11:07:45.687031 9, 0xFFFF, sum = 0
6905 11:07:45.690317 10, 0xFFFF, sum = 0
6906 11:07:45.690712 11, 0xFFFF, sum = 0
6907 11:07:45.693257 12, 0xFFFF, sum = 0
6908 11:07:45.693664 13, 0x0, sum = 1
6909 11:07:45.696606 14, 0x0, sum = 2
6910 11:07:45.697001 15, 0x0, sum = 3
6911 11:07:45.700060 16, 0x0, sum = 4
6912 11:07:45.700455 best_step = 14
6913 11:07:45.700759
6914 11:07:45.701037 ==
6915 11:07:45.703318 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 11:07:45.706768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 11:07:45.710071 ==
6918 11:07:45.710480 RX Vref Scan: 0
6919 11:07:45.710783
6920 11:07:45.713312 RX Vref 0 -> 0, step: 1
6921 11:07:45.713698
6922 11:07:45.716732 RX Delay -311 -> 252, step: 8
6923 11:07:45.720083 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6924 11:07:45.726469 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6925 11:07:45.729967 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6926 11:07:45.733141 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6927 11:07:45.736545 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6928 11:07:45.742982 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6929 11:07:45.746412 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6930 11:07:45.749558 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6931 11:07:45.753162 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6932 11:07:45.759491 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6933 11:07:45.763220 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6934 11:07:45.766181 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6935 11:07:45.769663 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6936 11:07:45.776203 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6937 11:07:45.779524 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6938 11:07:45.782827 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6939 11:07:45.783221 ==
6940 11:07:45.786217 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:07:45.792955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:07:45.793352 ==
6943 11:07:45.793650 DQS Delay:
6944 11:07:45.796607 DQS0 = 28, DQS1 = 36
6945 11:07:45.796998 DQM Delay:
6946 11:07:45.797301 DQM0 = 10, DQM1 = 14
6947 11:07:45.799652 DQ Delay:
6948 11:07:45.802683 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6949 11:07:45.803075 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6950 11:07:45.806464 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6951 11:07:45.809370 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6952 11:07:45.809760
6953 11:07:45.812723
6954 11:07:45.819932 [DQSOSCAuto] RK1, (LSB)MR18= 0xc95a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6955 11:07:45.823025 CH1 RK1: MR19=C0C, MR18=C95A
6956 11:07:45.829717 CH1_RK1: MR19=0xC0C, MR18=0xC95A, DQSOSC=384, MR23=63, INC=400, DEC=267
6957 11:07:45.832558 [RxdqsGatingPostProcess] freq 400
6958 11:07:45.836395 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6959 11:07:45.839729 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 11:07:45.842808 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 11:07:45.846767 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 11:07:45.849793 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 11:07:45.852621 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 11:07:45.856010 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 11:07:45.859212 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 11:07:45.863223 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 11:07:45.866588 Pre-setting of DQS Precalculation
6968 11:07:45.869385 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6969 11:07:45.876318 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6970 11:07:45.883467 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6971 11:07:45.885967
6972 11:07:45.886397
6973 11:07:45.886737 [Calibration Summary] 800 Mbps
6974 11:07:45.889664 CH 0, Rank 0
6975 11:07:45.890278 SW Impedance : PASS
6976 11:07:45.892870 DUTY Scan : NO K
6977 11:07:45.896721 ZQ Calibration : PASS
6978 11:07:45.897113 Jitter Meter : NO K
6979 11:07:45.899442 CBT Training : PASS
6980 11:07:45.902734 Write leveling : PASS
6981 11:07:45.903251 RX DQS gating : PASS
6982 11:07:45.906603 RX DQ/DQS(RDDQC) : PASS
6983 11:07:45.909431 TX DQ/DQS : PASS
6984 11:07:45.909826 RX DATLAT : PASS
6985 11:07:45.912955 RX DQ/DQS(Engine): PASS
6986 11:07:45.916795 TX OE : NO K
6987 11:07:45.917188 All Pass.
6988 11:07:45.917489
6989 11:07:45.917764 CH 0, Rank 1
6990 11:07:45.919442 SW Impedance : PASS
6991 11:07:45.919831 DUTY Scan : NO K
6992 11:07:45.923005 ZQ Calibration : PASS
6993 11:07:45.926073 Jitter Meter : NO K
6994 11:07:45.926603 CBT Training : PASS
6995 11:07:45.929384 Write leveling : NO K
6996 11:07:45.932792 RX DQS gating : PASS
6997 11:07:45.933182 RX DQ/DQS(RDDQC) : PASS
6998 11:07:45.936080 TX DQ/DQS : PASS
6999 11:07:45.939109 RX DATLAT : PASS
7000 11:07:45.939645 RX DQ/DQS(Engine): PASS
7001 11:07:45.942770 TX OE : NO K
7002 11:07:45.943158 All Pass.
7003 11:07:45.943456
7004 11:07:45.946492 CH 1, Rank 0
7005 11:07:45.946887 SW Impedance : PASS
7006 11:07:45.949341 DUTY Scan : NO K
7007 11:07:45.952459 ZQ Calibration : PASS
7008 11:07:45.952847 Jitter Meter : NO K
7009 11:07:45.956246 CBT Training : PASS
7010 11:07:45.959446 Write leveling : PASS
7011 11:07:45.959834 RX DQS gating : PASS
7012 11:07:45.962684 RX DQ/DQS(RDDQC) : PASS
7013 11:07:45.965896 TX DQ/DQS : PASS
7014 11:07:45.966362 RX DATLAT : PASS
7015 11:07:45.968973 RX DQ/DQS(Engine): PASS
7016 11:07:45.972920 TX OE : NO K
7017 11:07:45.973312 All Pass.
7018 11:07:45.973609
7019 11:07:45.973882 CH 1, Rank 1
7020 11:07:45.975883 SW Impedance : PASS
7021 11:07:45.979178 DUTY Scan : NO K
7022 11:07:45.979565 ZQ Calibration : PASS
7023 11:07:45.982750 Jitter Meter : NO K
7024 11:07:45.983332 CBT Training : PASS
7025 11:07:45.985575 Write leveling : NO K
7026 11:07:45.989052 RX DQS gating : PASS
7027 11:07:45.989466 RX DQ/DQS(RDDQC) : PASS
7028 11:07:45.992329 TX DQ/DQS : PASS
7029 11:07:45.995517 RX DATLAT : PASS
7030 11:07:45.995905 RX DQ/DQS(Engine): PASS
7031 11:07:45.998834 TX OE : NO K
7032 11:07:45.999347 All Pass.
7033 11:07:45.999779
7034 11:07:46.002094 DramC Write-DBI off
7035 11:07:46.005335 PER_BANK_REFRESH: Hybrid Mode
7036 11:07:46.005720 TX_TRACKING: ON
7037 11:07:46.015683 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7038 11:07:46.019215 [FAST_K] Save calibration result to emmc
7039 11:07:46.022507 dramc_set_vcore_voltage set vcore to 725000
7040 11:07:46.025405 Read voltage for 1600, 0
7041 11:07:46.025801 Vio18 = 0
7042 11:07:46.026281 Vcore = 725000
7043 11:07:46.029009 Vdram = 0
7044 11:07:46.029404 Vddq = 0
7045 11:07:46.029803 Vmddr = 0
7046 11:07:46.035709 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7047 11:07:46.038567 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7048 11:07:46.043129 MEM_TYPE=3, freq_sel=13
7049 11:07:46.046110 sv_algorithm_assistance_LP4_3733
7050 11:07:46.049227 ============ PULL DRAM RESETB DOWN ============
7051 11:07:46.055302 ========== PULL DRAM RESETB DOWN end =========
7052 11:07:46.058832 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7053 11:07:46.061831 ===================================
7054 11:07:46.065604 LPDDR4 DRAM CONFIGURATION
7055 11:07:46.068667 ===================================
7056 11:07:46.069128 EX_ROW_EN[0] = 0x0
7057 11:07:46.072206 EX_ROW_EN[1] = 0x0
7058 11:07:46.072658 LP4Y_EN = 0x0
7059 11:07:46.075654 WORK_FSP = 0x1
7060 11:07:46.076153 WL = 0x5
7061 11:07:46.078800 RL = 0x5
7062 11:07:46.079188 BL = 0x2
7063 11:07:46.082488 RPST = 0x0
7064 11:07:46.083044 RD_PRE = 0x0
7065 11:07:46.085373 WR_PRE = 0x1
7066 11:07:46.085891 WR_PST = 0x1
7067 11:07:46.088601 DBI_WR = 0x0
7068 11:07:46.089124 DBI_RD = 0x0
7069 11:07:46.091994 OTF = 0x1
7070 11:07:46.095456 ===================================
7071 11:07:46.098753 ===================================
7072 11:07:46.099287 ANA top config
7073 11:07:46.101891 ===================================
7074 11:07:46.105730 DLL_ASYNC_EN = 0
7075 11:07:46.108891 ALL_SLAVE_EN = 0
7076 11:07:46.112020 NEW_RANK_MODE = 1
7077 11:07:46.112412 DLL_IDLE_MODE = 1
7078 11:07:46.115202 LP45_APHY_COMB_EN = 1
7079 11:07:46.118823 TX_ODT_DIS = 0
7080 11:07:46.121766 NEW_8X_MODE = 1
7081 11:07:46.125857 ===================================
7082 11:07:46.128757 ===================================
7083 11:07:46.132046 data_rate = 3200
7084 11:07:46.135392 CKR = 1
7085 11:07:46.135948 DQ_P2S_RATIO = 8
7086 11:07:46.138338 ===================================
7087 11:07:46.142128 CA_P2S_RATIO = 8
7088 11:07:46.145151 DQ_CA_OPEN = 0
7089 11:07:46.148841 DQ_SEMI_OPEN = 0
7090 11:07:46.152395 CA_SEMI_OPEN = 0
7091 11:07:46.152784 CA_FULL_RATE = 0
7092 11:07:46.155383 DQ_CKDIV4_EN = 0
7093 11:07:46.158697 CA_CKDIV4_EN = 0
7094 11:07:46.161621 CA_PREDIV_EN = 0
7095 11:07:46.165810 PH8_DLY = 12
7096 11:07:46.168859 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7097 11:07:46.169259 DQ_AAMCK_DIV = 4
7098 11:07:46.171974 CA_AAMCK_DIV = 4
7099 11:07:46.175210 CA_ADMCK_DIV = 4
7100 11:07:46.178321 DQ_TRACK_CA_EN = 0
7101 11:07:46.181502 CA_PICK = 1600
7102 11:07:46.185303 CA_MCKIO = 1600
7103 11:07:46.188345 MCKIO_SEMI = 0
7104 11:07:46.191490 PLL_FREQ = 3068
7105 11:07:46.191957 DQ_UI_PI_RATIO = 32
7106 11:07:46.195028 CA_UI_PI_RATIO = 0
7107 11:07:46.198117 ===================================
7108 11:07:46.201817 ===================================
7109 11:07:46.204855 memory_type:LPDDR4
7110 11:07:46.208515 GP_NUM : 10
7111 11:07:46.209078 SRAM_EN : 1
7112 11:07:46.211574 MD32_EN : 0
7113 11:07:46.214969 ===================================
7114 11:07:46.215588 [ANA_INIT] >>>>>>>>>>>>>>
7115 11:07:46.218102 <<<<<< [CONFIGURE PHASE]: ANA_TX
7116 11:07:46.221412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7117 11:07:46.224761 ===================================
7118 11:07:46.228155 data_rate = 3200,PCW = 0X7600
7119 11:07:46.231350 ===================================
7120 11:07:46.235008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7121 11:07:46.241614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 11:07:46.248783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 11:07:46.251133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7124 11:07:46.254682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7125 11:07:46.257953 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7126 11:07:46.261800 [ANA_INIT] flow start
7127 11:07:46.262287 [ANA_INIT] PLL >>>>>>>>
7128 11:07:46.264782 [ANA_INIT] PLL <<<<<<<<
7129 11:07:46.267876 [ANA_INIT] MIDPI >>>>>>>>
7130 11:07:46.268524 [ANA_INIT] MIDPI <<<<<<<<
7131 11:07:46.271429 [ANA_INIT] DLL >>>>>>>>
7132 11:07:46.274615 [ANA_INIT] DLL <<<<<<<<
7133 11:07:46.275229 [ANA_INIT] flow end
7134 11:07:46.281032 ============ LP4 DIFF to SE enter ============
7135 11:07:46.285190 ============ LP4 DIFF to SE exit ============
7136 11:07:46.285680 [ANA_INIT] <<<<<<<<<<<<<
7137 11:07:46.288107 [Flow] Enable top DCM control >>>>>
7138 11:07:46.291340 [Flow] Enable top DCM control <<<<<
7139 11:07:46.294594 Enable DLL master slave shuffle
7140 11:07:46.301616 ==============================================================
7141 11:07:46.304514 Gating Mode config
7142 11:07:46.308392 ==============================================================
7143 11:07:46.311228 Config description:
7144 11:07:46.321107 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7145 11:07:46.328035 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7146 11:07:46.331631 SELPH_MODE 0: By rank 1: By Phase
7147 11:07:46.337884 ==============================================================
7148 11:07:46.341935 GAT_TRACK_EN = 1
7149 11:07:46.344583 RX_GATING_MODE = 2
7150 11:07:46.345011 RX_GATING_TRACK_MODE = 2
7151 11:07:46.348244 SELPH_MODE = 1
7152 11:07:46.351408 PICG_EARLY_EN = 1
7153 11:07:46.354543 VALID_LAT_VALUE = 1
7154 11:07:46.361141 ==============================================================
7155 11:07:46.364700 Enter into Gating configuration >>>>
7156 11:07:46.367876 Exit from Gating configuration <<<<
7157 11:07:46.371453 Enter into DVFS_PRE_config >>>>>
7158 11:07:46.381044 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7159 11:07:46.384934 Exit from DVFS_PRE_config <<<<<
7160 11:07:46.387788 Enter into PICG configuration >>>>
7161 11:07:46.390997 Exit from PICG configuration <<<<
7162 11:07:46.394930 [RX_INPUT] configuration >>>>>
7163 11:07:46.398210 [RX_INPUT] configuration <<<<<
7164 11:07:46.401396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7165 11:07:46.407873 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7166 11:07:46.414537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 11:07:46.421020 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 11:07:46.424334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 11:07:46.431012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 11:07:46.434728 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7171 11:07:46.440707 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7172 11:07:46.444214 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7173 11:07:46.447951 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7174 11:07:46.451021 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7175 11:07:46.457896 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7176 11:07:46.460938 ===================================
7177 11:07:46.461447 LPDDR4 DRAM CONFIGURATION
7178 11:07:46.464223 ===================================
7179 11:07:46.467707 EX_ROW_EN[0] = 0x0
7180 11:07:46.471313 EX_ROW_EN[1] = 0x0
7181 11:07:46.471799 LP4Y_EN = 0x0
7182 11:07:46.474078 WORK_FSP = 0x1
7183 11:07:46.474567 WL = 0x5
7184 11:07:46.477284 RL = 0x5
7185 11:07:46.477694 BL = 0x2
7186 11:07:46.481184 RPST = 0x0
7187 11:07:46.481563 RD_PRE = 0x0
7188 11:07:46.483939 WR_PRE = 0x1
7189 11:07:46.484443 WR_PST = 0x1
7190 11:07:46.487993 DBI_WR = 0x0
7191 11:07:46.488405 DBI_RD = 0x0
7192 11:07:46.490790 OTF = 0x1
7193 11:07:46.494085 ===================================
7194 11:07:46.497506 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7195 11:07:46.500619 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7196 11:07:46.507648 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 11:07:46.510828 ===================================
7198 11:07:46.511229 LPDDR4 DRAM CONFIGURATION
7199 11:07:46.513866 ===================================
7200 11:07:46.517345 EX_ROW_EN[0] = 0x10
7201 11:07:46.520818 EX_ROW_EN[1] = 0x0
7202 11:07:46.521218 LP4Y_EN = 0x0
7203 11:07:46.524202 WORK_FSP = 0x1
7204 11:07:46.524601 WL = 0x5
7205 11:07:46.527353 RL = 0x5
7206 11:07:46.527734 BL = 0x2
7207 11:07:46.530865 RPST = 0x0
7208 11:07:46.531414 RD_PRE = 0x0
7209 11:07:46.534656 WR_PRE = 0x1
7210 11:07:46.535113 WR_PST = 0x1
7211 11:07:46.537625 DBI_WR = 0x0
7212 11:07:46.538189 DBI_RD = 0x0
7213 11:07:46.540819 OTF = 0x1
7214 11:07:46.543838 ===================================
7215 11:07:46.550943 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7216 11:07:46.551523 ==
7217 11:07:46.553893 Dram Type= 6, Freq= 0, CH_0, rank 0
7218 11:07:46.557071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7219 11:07:46.557553 ==
7220 11:07:46.560547 [Duty_Offset_Calibration]
7221 11:07:46.561184 B0:2 B1:1 CA:1
7222 11:07:46.561716
7223 11:07:46.563624 [DutyScan_Calibration_Flow] k_type=0
7224 11:07:46.574596
7225 11:07:46.575113 ==CLK 0==
7226 11:07:46.577526 Final CLK duty delay cell = 0
7227 11:07:46.581144 [0] MAX Duty = 5156%(X100), DQS PI = 22
7228 11:07:46.584597 [0] MIN Duty = 4876%(X100), DQS PI = 48
7229 11:07:46.587330 [0] AVG Duty = 5016%(X100)
7230 11:07:46.587858
7231 11:07:46.590960 CH0 CLK Duty spec in!! Max-Min= 280%
7232 11:07:46.594373 [DutyScan_Calibration_Flow] ====Done====
7233 11:07:46.594978
7234 11:07:46.597739 [DutyScan_Calibration_Flow] k_type=1
7235 11:07:46.613989
7236 11:07:46.614428 ==DQS 0 ==
7237 11:07:46.616734 Final DQS duty delay cell = -4
7238 11:07:46.620549 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7239 11:07:46.623515 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7240 11:07:46.626836 [-4] AVG Duty = 4906%(X100)
7241 11:07:46.627258
7242 11:07:46.627561 ==DQS 1 ==
7243 11:07:46.630096 Final DQS duty delay cell = 0
7244 11:07:46.633436 [0] MAX Duty = 5187%(X100), DQS PI = 20
7245 11:07:46.636970 [0] MIN Duty = 5031%(X100), DQS PI = 32
7246 11:07:46.639935 [0] AVG Duty = 5109%(X100)
7247 11:07:46.640521
7248 11:07:46.643435 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7249 11:07:46.643964
7250 11:07:46.646953 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7251 11:07:46.650308 [DutyScan_Calibration_Flow] ====Done====
7252 11:07:46.650871
7253 11:07:46.653388 [DutyScan_Calibration_Flow] k_type=3
7254 11:07:46.670966
7255 11:07:46.671514 ==DQM 0 ==
7256 11:07:46.674196 Final DQM duty delay cell = 0
7257 11:07:46.677681 [0] MAX Duty = 5187%(X100), DQS PI = 26
7258 11:07:46.680935 [0] MIN Duty = 4875%(X100), DQS PI = 58
7259 11:07:46.684581 [0] AVG Duty = 5031%(X100)
7260 11:07:46.685118
7261 11:07:46.685654 ==DQM 1 ==
7262 11:07:46.687400 Final DQM duty delay cell = 0
7263 11:07:46.691387 [0] MAX Duty = 5187%(X100), DQS PI = 8
7264 11:07:46.694449 [0] MIN Duty = 5062%(X100), DQS PI = 14
7265 11:07:46.697374 [0] AVG Duty = 5124%(X100)
7266 11:07:46.697759
7267 11:07:46.701749 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7268 11:07:46.702174
7269 11:07:46.704182 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7270 11:07:46.707487 [DutyScan_Calibration_Flow] ====Done====
7271 11:07:46.707869
7272 11:07:46.710602 [DutyScan_Calibration_Flow] k_type=2
7273 11:07:46.727938
7274 11:07:46.728375 ==DQ 0 ==
7275 11:07:46.731183 Final DQ duty delay cell = 0
7276 11:07:46.735085 [0] MAX Duty = 5062%(X100), DQS PI = 26
7277 11:07:46.737766 [0] MIN Duty = 4907%(X100), DQS PI = 0
7278 11:07:46.738194 [0] AVG Duty = 4984%(X100)
7279 11:07:46.738497
7280 11:07:46.741684 ==DQ 1 ==
7281 11:07:46.744651 Final DQ duty delay cell = 0
7282 11:07:46.747797 [0] MAX Duty = 5125%(X100), DQS PI = 6
7283 11:07:46.751015 [0] MIN Duty = 4907%(X100), DQS PI = 34
7284 11:07:46.751397 [0] AVG Duty = 5016%(X100)
7285 11:07:46.751693
7286 11:07:46.754413 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7287 11:07:46.757811
7288 11:07:46.761126 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7289 11:07:46.764540 [DutyScan_Calibration_Flow] ====Done====
7290 11:07:46.764922 ==
7291 11:07:46.768259 Dram Type= 6, Freq= 0, CH_1, rank 0
7292 11:07:46.771552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7293 11:07:46.771934 ==
7294 11:07:46.774662 [Duty_Offset_Calibration]
7295 11:07:46.775041 B0:1 B1:0 CA:0
7296 11:07:46.775333
7297 11:07:46.778040 [DutyScan_Calibration_Flow] k_type=0
7298 11:07:46.787107
7299 11:07:46.787538 ==CLK 0==
7300 11:07:46.790952 Final CLK duty delay cell = -4
7301 11:07:46.794422 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7302 11:07:46.796997 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7303 11:07:46.800935 [-4] AVG Duty = 4906%(X100)
7304 11:07:46.801420
7305 11:07:46.804220 CH1 CLK Duty spec in!! Max-Min= 125%
7306 11:07:46.807336 [DutyScan_Calibration_Flow] ====Done====
7307 11:07:46.807738
7308 11:07:46.811415 [DutyScan_Calibration_Flow] k_type=1
7309 11:07:46.827390
7310 11:07:46.827594 ==DQS 0 ==
7311 11:07:46.830197 Final DQS duty delay cell = 0
7312 11:07:46.833693 [0] MAX Duty = 5062%(X100), DQS PI = 10
7313 11:07:46.837297 [0] MIN Duty = 4844%(X100), DQS PI = 46
7314 11:07:46.840595 [0] AVG Duty = 4953%(X100)
7315 11:07:46.840798
7316 11:07:46.840956 ==DQS 1 ==
7317 11:07:46.844151 Final DQS duty delay cell = 0
7318 11:07:46.847222 [0] MAX Duty = 5249%(X100), DQS PI = 16
7319 11:07:46.850632 [0] MIN Duty = 4938%(X100), DQS PI = 10
7320 11:07:46.853926 [0] AVG Duty = 5093%(X100)
7321 11:07:46.854071
7322 11:07:46.856814 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7323 11:07:46.856891
7324 11:07:46.860029 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7325 11:07:46.863809 [DutyScan_Calibration_Flow] ====Done====
7326 11:07:46.863895
7327 11:07:46.867074 [DutyScan_Calibration_Flow] k_type=3
7328 11:07:46.884316
7329 11:07:46.884711 ==DQM 0 ==
7330 11:07:46.888052 Final DQM duty delay cell = 0
7331 11:07:46.890707 [0] MAX Duty = 5187%(X100), DQS PI = 8
7332 11:07:46.894292 [0] MIN Duty = 4969%(X100), DQS PI = 48
7333 11:07:46.894702 [0] AVG Duty = 5078%(X100)
7334 11:07:46.898211
7335 11:07:46.898590 ==DQM 1 ==
7336 11:07:46.901135 Final DQM duty delay cell = 0
7337 11:07:46.904544 [0] MAX Duty = 5093%(X100), DQS PI = 42
7338 11:07:46.907728 [0] MIN Duty = 4907%(X100), DQS PI = 32
7339 11:07:46.910990 [0] AVG Duty = 5000%(X100)
7340 11:07:46.911369
7341 11:07:46.914216 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7342 11:07:46.914730
7343 11:07:46.918099 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7344 11:07:46.920867 [DutyScan_Calibration_Flow] ====Done====
7345 11:07:46.921274
7346 11:07:46.924634 [DutyScan_Calibration_Flow] k_type=2
7347 11:07:46.940823
7348 11:07:46.941205 ==DQ 0 ==
7349 11:07:46.943548 Final DQ duty delay cell = -4
7350 11:07:46.947159 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7351 11:07:46.950862 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7352 11:07:46.953816 [-4] AVG Duty = 4953%(X100)
7353 11:07:46.954294
7354 11:07:46.954648 ==DQ 1 ==
7355 11:07:46.957496 Final DQ duty delay cell = 0
7356 11:07:46.960411 [0] MAX Duty = 5124%(X100), DQS PI = 18
7357 11:07:46.963542 [0] MIN Duty = 4938%(X100), DQS PI = 8
7358 11:07:46.963932 [0] AVG Duty = 5031%(X100)
7359 11:07:46.967073
7360 11:07:46.970454 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7361 11:07:46.970961
7362 11:07:46.973964 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7363 11:07:46.977091 [DutyScan_Calibration_Flow] ====Done====
7364 11:07:46.980418 nWR fixed to 30
7365 11:07:46.980889 [ModeRegInit_LP4] CH0 RK0
7366 11:07:46.983600 [ModeRegInit_LP4] CH0 RK1
7367 11:07:46.987422 [ModeRegInit_LP4] CH1 RK0
7368 11:07:46.990711 [ModeRegInit_LP4] CH1 RK1
7369 11:07:46.991236 match AC timing 5
7370 11:07:46.993491 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7371 11:07:47.000159 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7372 11:07:47.003891 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7373 11:07:47.010838 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7374 11:07:47.014367 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7375 11:07:47.014755 [MiockJmeterHQA]
7376 11:07:47.015095
7377 11:07:47.017506 [DramcMiockJmeter] u1RxGatingPI = 0
7378 11:07:47.020929 0 : 4253, 4026
7379 11:07:47.021429 4 : 4253, 4026
7380 11:07:47.024107 8 : 4253, 4027
7381 11:07:47.024535 12 : 4252, 4027
7382 11:07:47.025039 16 : 4253, 4026
7383 11:07:47.027308 20 : 4363, 4138
7384 11:07:47.027698 24 : 4252, 4027
7385 11:07:47.030528 28 : 4363, 4137
7386 11:07:47.030980 32 : 4253, 4027
7387 11:07:47.034224 36 : 4253, 4026
7388 11:07:47.034885 40 : 4252, 4027
7389 11:07:47.035354 44 : 4255, 4029
7390 11:07:47.037505 48 : 4363, 4138
7391 11:07:47.037895 52 : 4252, 4027
7392 11:07:47.040911 56 : 4363, 4137
7393 11:07:47.041306 60 : 4250, 4027
7394 11:07:47.043818 64 : 4250, 4027
7395 11:07:47.044226 68 : 4250, 4027
7396 11:07:47.047044 72 : 4360, 4138
7397 11:07:47.047434 76 : 4250, 4027
7398 11:07:47.047739 80 : 4360, 4138
7399 11:07:47.050588 84 : 4249, 4027
7400 11:07:47.051057 88 : 4250, 91
7401 11:07:47.053643 92 : 4253, 0
7402 11:07:47.054078 96 : 4250, 0
7403 11:07:47.054395 100 : 4253, 0
7404 11:07:47.056678 104 : 4250, 0
7405 11:07:47.057084 108 : 4252, 0
7406 11:07:47.060635 112 : 4360, 0
7407 11:07:47.061023 116 : 4250, 0
7408 11:07:47.061326 120 : 4250, 0
7409 11:07:47.064222 124 : 4249, 0
7410 11:07:47.064617 128 : 4250, 0
7411 11:07:47.065036 132 : 4249, 0
7412 11:07:47.066921 136 : 4253, 0
7413 11:07:47.067411 140 : 4361, 0
7414 11:07:47.070499 144 : 4360, 0
7415 11:07:47.070891 148 : 4363, 0
7416 11:07:47.071191 152 : 4250, 0
7417 11:07:47.073393 156 : 4250, 0
7418 11:07:47.073778 160 : 4252, 0
7419 11:07:47.077120 164 : 4250, 0
7420 11:07:47.077543 168 : 4250, 0
7421 11:07:47.077860 172 : 4251, 0
7422 11:07:47.080427 176 : 4250, 0
7423 11:07:47.080816 180 : 4361, 0
7424 11:07:47.083474 184 : 4360, 0
7425 11:07:47.083917 188 : 4249, 0
7426 11:07:47.084278 192 : 4250, 0
7427 11:07:47.086925 196 : 4250, 0
7428 11:07:47.087431 200 : 4363, 0
7429 11:07:47.090661 204 : 4250, 1082
7430 11:07:47.091050 208 : 4249, 4015
7431 11:07:47.091353 212 : 4249, 4027
7432 11:07:47.093407 216 : 4250, 4026
7433 11:07:47.094034 220 : 4250, 4027
7434 11:07:47.097027 224 : 4249, 4027
7435 11:07:47.097492 228 : 4252, 4029
7436 11:07:47.100083 232 : 4250, 4026
7437 11:07:47.100544 236 : 4361, 4137
7438 11:07:47.104154 240 : 4360, 4138
7439 11:07:47.104595 244 : 4250, 4027
7440 11:07:47.107117 248 : 4363, 4140
7441 11:07:47.107522 252 : 4250, 4026
7442 11:07:47.110600 256 : 4250, 4027
7443 11:07:47.111019 260 : 4249, 4027
7444 11:07:47.111359 264 : 4252, 4029
7445 11:07:47.113915 268 : 4250, 4026
7446 11:07:47.114479 272 : 4250, 4027
7447 11:07:47.117078 276 : 4249, 4027
7448 11:07:47.117523 280 : 4252, 4029
7449 11:07:47.120760 284 : 4250, 4026
7450 11:07:47.121307 288 : 4361, 4137
7451 11:07:47.123654 292 : 4360, 4138
7452 11:07:47.124041 296 : 4250, 4027
7453 11:07:47.127002 300 : 4363, 4140
7454 11:07:47.127461 304 : 4250, 4026
7455 11:07:47.130470 308 : 4250, 3946
7456 11:07:47.130862 312 : 4249, 2021
7457 11:07:47.131179
7458 11:07:47.133611 MIOCK jitter meter ch=0
7459 11:07:47.134133
7460 11:07:47.136824 1T = (312-88) = 224 dly cells
7461 11:07:47.140200 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7462 11:07:47.140606 ==
7463 11:07:47.143530 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 11:07:47.150540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 11:07:47.150995 ==
7466 11:07:47.153822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 11:07:47.160320 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 11:07:47.163390 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 11:07:47.170092 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 11:07:47.178369 [CA 0] Center 42 (12~73) winsize 62
7471 11:07:47.181266 [CA 1] Center 42 (12~73) winsize 62
7472 11:07:47.184782 [CA 2] Center 37 (8~67) winsize 60
7473 11:07:47.187928 [CA 3] Center 37 (7~67) winsize 61
7474 11:07:47.191416 [CA 4] Center 36 (6~66) winsize 61
7475 11:07:47.194738 [CA 5] Center 35 (6~64) winsize 59
7476 11:07:47.195124
7477 11:07:47.197926 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7478 11:07:47.198381
7479 11:07:47.201368 [CATrainingPosCal] consider 1 rank data
7480 11:07:47.204620 u2DelayCellTimex100 = 290/100 ps
7481 11:07:47.208270 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 11:07:47.214495 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7483 11:07:47.218454 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7484 11:07:47.220813 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7485 11:07:47.224303 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7486 11:07:47.227731 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7487 11:07:47.228139
7488 11:07:47.231568 CA PerBit enable=1, Macro0, CA PI delay=35
7489 11:07:47.231972
7490 11:07:47.234139 [CBTSetCACLKResult] CA Dly = 35
7491 11:07:47.237419 CS Dly: 8 (0~39)
7492 11:07:47.241070 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 11:07:47.244171 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 11:07:47.244558 ==
7495 11:07:47.247443 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 11:07:47.250821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 11:07:47.254444 ==
7498 11:07:47.258161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 11:07:47.260911 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 11:07:47.267241 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 11:07:47.274330 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 11:07:47.281300 [CA 0] Center 42 (12~73) winsize 62
7503 11:07:47.284731 [CA 1] Center 42 (12~73) winsize 62
7504 11:07:47.287741 [CA 2] Center 37 (8~67) winsize 60
7505 11:07:47.291188 [CA 3] Center 37 (7~68) winsize 62
7506 11:07:47.294490 [CA 4] Center 35 (5~65) winsize 61
7507 11:07:47.297905 [CA 5] Center 35 (5~65) winsize 61
7508 11:07:47.298364
7509 11:07:47.301104 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7510 11:07:47.301632
7511 11:07:47.304886 [CATrainingPosCal] consider 2 rank data
7512 11:07:47.307974 u2DelayCellTimex100 = 290/100 ps
7513 11:07:47.311356 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7514 11:07:47.317634 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 11:07:47.320901 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 11:07:47.324794 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7517 11:07:47.327839 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7518 11:07:47.331289 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7519 11:07:47.331928
7520 11:07:47.334410 CA PerBit enable=1, Macro0, CA PI delay=35
7521 11:07:47.334848
7522 11:07:47.337747 [CBTSetCACLKResult] CA Dly = 35
7523 11:07:47.341083 CS Dly: 9 (0~42)
7524 11:07:47.344418 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 11:07:47.348064 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 11:07:47.348471
7527 11:07:47.351136 ----->DramcWriteLeveling(PI) begin...
7528 11:07:47.351562 ==
7529 11:07:47.354640 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 11:07:47.357900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 11:07:47.360965 ==
7532 11:07:47.361345 Write leveling (Byte 0): 34 => 34
7533 11:07:47.364472 Write leveling (Byte 1): 28 => 28
7534 11:07:47.367208 DramcWriteLeveling(PI) end<-----
7535 11:07:47.367728
7536 11:07:47.368254 ==
7537 11:07:47.371102 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 11:07:47.377598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 11:07:47.378179 ==
7540 11:07:47.378567 [Gating] SW mode calibration
7541 11:07:47.387276 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 11:07:47.390579 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 11:07:47.397330 1 4 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7544 11:07:47.400816 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7545 11:07:47.404091 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7546 11:07:47.410904 1 4 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7547 11:07:47.413929 1 4 16 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
7548 11:07:47.417190 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7549 11:07:47.420449 1 4 24 | B1->B0 | 3434 3a3a | 1 0 | (1 1) (0 0)
7550 11:07:47.426985 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7551 11:07:47.430608 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7552 11:07:47.433847 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7553 11:07:47.440348 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7554 11:07:47.443520 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
7555 11:07:47.447185 1 5 16 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
7556 11:07:47.453539 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7557 11:07:47.457341 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7558 11:07:47.460565 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7559 11:07:47.467280 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7560 11:07:47.470135 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7561 11:07:47.473699 1 6 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
7562 11:07:47.480063 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7563 11:07:47.483599 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7564 11:07:47.486917 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (1 1)
7565 11:07:47.493571 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 11:07:47.496995 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 11:07:47.500148 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 11:07:47.507478 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 11:07:47.510144 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 11:07:47.513574 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 11:07:47.520133 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 11:07:47.523390 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 11:07:47.526629 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 11:07:47.533485 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 11:07:47.536987 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 11:07:47.540091 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 11:07:47.546501 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 11:07:47.550112 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 11:07:47.553121 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 11:07:47.559918 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:07:47.563275 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 11:07:47.566709 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:07:47.573219 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:07:47.577031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:07:47.580125 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 11:07:47.583033 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 11:07:47.589993 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 11:07:47.593060 Total UI for P1: 0, mck2ui 16
7589 11:07:47.596852 best dqsien dly found for B0: ( 1, 9, 10)
7590 11:07:47.600264 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 11:07:47.603199 Total UI for P1: 0, mck2ui 16
7592 11:07:47.606601 best dqsien dly found for B1: ( 1, 9, 16)
7593 11:07:47.609605 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7594 11:07:47.613697 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7595 11:07:47.614145
7596 11:07:47.616745 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7597 11:07:47.623116 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7598 11:07:47.623521 [Gating] SW calibration Done
7599 11:07:47.623920 ==
7600 11:07:47.626514 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 11:07:47.633018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 11:07:47.633429 ==
7603 11:07:47.633872 RX Vref Scan: 0
7604 11:07:47.634332
7605 11:07:47.636117 RX Vref 0 -> 0, step: 1
7606 11:07:47.636664
7607 11:07:47.640246 RX Delay 0 -> 252, step: 8
7608 11:07:47.643445 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7609 11:07:47.646785 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7610 11:07:47.650333 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7611 11:07:47.652791 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7612 11:07:47.659738 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7613 11:07:47.662973 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7614 11:07:47.666093 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7615 11:07:47.669347 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7616 11:07:47.672744 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7617 11:07:47.680018 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7618 11:07:47.682904 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7619 11:07:47.685830 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7620 11:07:47.689643 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7621 11:07:47.692866 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7622 11:07:47.699425 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7623 11:07:47.702732 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7624 11:07:47.703122 ==
7625 11:07:47.706462 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 11:07:47.709211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 11:07:47.709602 ==
7628 11:07:47.712523 DQS Delay:
7629 11:07:47.712908 DQS0 = 0, DQS1 = 0
7630 11:07:47.713207 DQM Delay:
7631 11:07:47.716240 DQM0 = 136, DQM1 = 131
7632 11:07:47.716633 DQ Delay:
7633 11:07:47.719538 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7634 11:07:47.722826 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7635 11:07:47.725905 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7636 11:07:47.732597 DQ12 =135, DQ13 =139, DQ14 =143, DQ15 =135
7637 11:07:47.732988
7638 11:07:47.733286
7639 11:07:47.733565 ==
7640 11:07:47.736318 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 11:07:47.739394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 11:07:47.739788 ==
7643 11:07:47.740088
7644 11:07:47.740363
7645 11:07:47.742436 TX Vref Scan disable
7646 11:07:47.742828 == TX Byte 0 ==
7647 11:07:47.749217 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7648 11:07:47.752407 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7649 11:07:47.752816 == TX Byte 1 ==
7650 11:07:47.758921 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7651 11:07:47.762664 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7652 11:07:47.763057 ==
7653 11:07:47.765711 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 11:07:47.769258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 11:07:47.769687 ==
7656 11:07:47.783633
7657 11:07:47.786892 TX Vref early break, caculate TX vref
7658 11:07:47.790117 TX Vref=16, minBit 0, minWin=23, winSum=379
7659 11:07:47.793922 TX Vref=18, minBit 7, minWin=23, winSum=388
7660 11:07:47.796944 TX Vref=20, minBit 3, minWin=23, winSum=401
7661 11:07:47.800105 TX Vref=22, minBit 0, minWin=25, winSum=409
7662 11:07:47.803491 TX Vref=24, minBit 5, minWin=25, winSum=417
7663 11:07:47.810160 TX Vref=26, minBit 6, minWin=25, winSum=425
7664 11:07:47.813236 TX Vref=28, minBit 6, minWin=24, winSum=421
7665 11:07:47.817014 TX Vref=30, minBit 6, minWin=24, winSum=412
7666 11:07:47.819974 TX Vref=32, minBit 1, minWin=24, winSum=406
7667 11:07:47.823551 TX Vref=34, minBit 1, minWin=23, winSum=398
7668 11:07:47.830215 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 26
7669 11:07:47.830613
7670 11:07:47.833280 Final TX Range 0 Vref 26
7671 11:07:47.833672
7672 11:07:47.833975 ==
7673 11:07:47.836512 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 11:07:47.839808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 11:07:47.840218 ==
7676 11:07:47.840619
7677 11:07:47.840991
7678 11:07:47.843367 TX Vref Scan disable
7679 11:07:47.849647 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7680 11:07:47.850071 == TX Byte 0 ==
7681 11:07:47.853552 u2DelayCellOfst[0]=10 cells (3 PI)
7682 11:07:47.856731 u2DelayCellOfst[1]=13 cells (4 PI)
7683 11:07:47.859953 u2DelayCellOfst[2]=6 cells (2 PI)
7684 11:07:47.863133 u2DelayCellOfst[3]=10 cells (3 PI)
7685 11:07:47.866201 u2DelayCellOfst[4]=6 cells (2 PI)
7686 11:07:47.870096 u2DelayCellOfst[5]=0 cells (0 PI)
7687 11:07:47.873139 u2DelayCellOfst[6]=16 cells (5 PI)
7688 11:07:47.873527 u2DelayCellOfst[7]=13 cells (4 PI)
7689 11:07:47.880384 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7690 11:07:47.883734 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7691 11:07:47.884128 == TX Byte 1 ==
7692 11:07:47.886747 u2DelayCellOfst[8]=0 cells (0 PI)
7693 11:07:47.890653 u2DelayCellOfst[9]=0 cells (0 PI)
7694 11:07:47.893281 u2DelayCellOfst[10]=6 cells (2 PI)
7695 11:07:47.896852 u2DelayCellOfst[11]=6 cells (2 PI)
7696 11:07:47.899888 u2DelayCellOfst[12]=10 cells (3 PI)
7697 11:07:47.903009 u2DelayCellOfst[13]=13 cells (4 PI)
7698 11:07:47.906552 u2DelayCellOfst[14]=13 cells (4 PI)
7699 11:07:47.909808 u2DelayCellOfst[15]=10 cells (3 PI)
7700 11:07:47.912967 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7701 11:07:47.919929 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7702 11:07:47.920321 DramC Write-DBI on
7703 11:07:47.920624 ==
7704 11:07:47.923028 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 11:07:47.926103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 11:07:47.926509 ==
7707 11:07:47.929183
7708 11:07:47.929569
7709 11:07:47.929869 TX Vref Scan disable
7710 11:07:47.933251 == TX Byte 0 ==
7711 11:07:47.935943 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7712 11:07:47.939160 == TX Byte 1 ==
7713 11:07:47.942812 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7714 11:07:47.946809 DramC Write-DBI off
7715 11:07:47.947312
7716 11:07:47.947621 [DATLAT]
7717 11:07:47.947901 Freq=1600, CH0 RK0
7718 11:07:47.948175
7719 11:07:47.949685 DATLAT Default: 0xf
7720 11:07:47.950127 0, 0xFFFF, sum = 0
7721 11:07:47.952753 1, 0xFFFF, sum = 0
7722 11:07:47.956082 2, 0xFFFF, sum = 0
7723 11:07:47.956478 3, 0xFFFF, sum = 0
7724 11:07:47.959510 4, 0xFFFF, sum = 0
7725 11:07:47.959906 5, 0xFFFF, sum = 0
7726 11:07:47.963044 6, 0xFFFF, sum = 0
7727 11:07:47.963438 7, 0xFFFF, sum = 0
7728 11:07:47.965859 8, 0xFFFF, sum = 0
7729 11:07:47.966326 9, 0xFFFF, sum = 0
7730 11:07:47.969189 10, 0xFFFF, sum = 0
7731 11:07:47.969591 11, 0xFFFF, sum = 0
7732 11:07:47.972370 12, 0xFFFF, sum = 0
7733 11:07:47.972766 13, 0xFFFF, sum = 0
7734 11:07:47.975928 14, 0x0, sum = 1
7735 11:07:47.976436 15, 0x0, sum = 2
7736 11:07:47.979421 16, 0x0, sum = 3
7737 11:07:47.979862 17, 0x0, sum = 4
7738 11:07:47.983337 best_step = 15
7739 11:07:47.983729
7740 11:07:47.984030 ==
7741 11:07:47.986065 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 11:07:47.989682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 11:07:47.990115 ==
7744 11:07:47.992825 RX Vref Scan: 1
7745 11:07:47.993269
7746 11:07:47.993579 Set Vref Range= 24 -> 127
7747 11:07:47.994037
7748 11:07:47.995920 RX Vref 24 -> 127, step: 1
7749 11:07:47.996371
7750 11:07:47.999426 RX Delay 27 -> 252, step: 4
7751 11:07:47.999953
7752 11:07:48.002512 Set Vref, RX VrefLevel [Byte0]: 24
7753 11:07:48.006612 [Byte1]: 24
7754 11:07:48.007002
7755 11:07:48.009482 Set Vref, RX VrefLevel [Byte0]: 25
7756 11:07:48.012650 [Byte1]: 25
7757 11:07:48.013043
7758 11:07:48.016307 Set Vref, RX VrefLevel [Byte0]: 26
7759 11:07:48.019623 [Byte1]: 26
7760 11:07:48.023231
7761 11:07:48.023629 Set Vref, RX VrefLevel [Byte0]: 27
7762 11:07:48.026440 [Byte1]: 27
7763 11:07:48.030920
7764 11:07:48.031308 Set Vref, RX VrefLevel [Byte0]: 28
7765 11:07:48.033867 [Byte1]: 28
7766 11:07:48.038377
7767 11:07:48.038765 Set Vref, RX VrefLevel [Byte0]: 29
7768 11:07:48.041848 [Byte1]: 29
7769 11:07:48.045830
7770 11:07:48.046268 Set Vref, RX VrefLevel [Byte0]: 30
7771 11:07:48.048857 [Byte1]: 30
7772 11:07:48.053150
7773 11:07:48.053540 Set Vref, RX VrefLevel [Byte0]: 31
7774 11:07:48.056976 [Byte1]: 31
7775 11:07:48.060667
7776 11:07:48.061058 Set Vref, RX VrefLevel [Byte0]: 32
7777 11:07:48.063838 [Byte1]: 32
7778 11:07:48.068332
7779 11:07:48.068742 Set Vref, RX VrefLevel [Byte0]: 33
7780 11:07:48.071658 [Byte1]: 33
7781 11:07:48.075772
7782 11:07:48.076164 Set Vref, RX VrefLevel [Byte0]: 34
7783 11:07:48.078994 [Byte1]: 34
7784 11:07:48.084115
7785 11:07:48.084520 Set Vref, RX VrefLevel [Byte0]: 35
7786 11:07:48.087199 [Byte1]: 35
7787 11:07:48.090840
7788 11:07:48.091232 Set Vref, RX VrefLevel [Byte0]: 36
7789 11:07:48.094429 [Byte1]: 36
7790 11:07:48.098475
7791 11:07:48.098880 Set Vref, RX VrefLevel [Byte0]: 37
7792 11:07:48.101595 [Byte1]: 37
7793 11:07:48.105863
7794 11:07:48.106295 Set Vref, RX VrefLevel [Byte0]: 38
7795 11:07:48.109666 [Byte1]: 38
7796 11:07:48.113523
7797 11:07:48.113911 Set Vref, RX VrefLevel [Byte0]: 39
7798 11:07:48.116779 [Byte1]: 39
7799 11:07:48.121230
7800 11:07:48.121663 Set Vref, RX VrefLevel [Byte0]: 40
7801 11:07:48.124595 [Byte1]: 40
7802 11:07:48.128939
7803 11:07:48.129490 Set Vref, RX VrefLevel [Byte0]: 41
7804 11:07:48.132103 [Byte1]: 41
7805 11:07:48.136228
7806 11:07:48.136624 Set Vref, RX VrefLevel [Byte0]: 42
7807 11:07:48.139455 [Byte1]: 42
7808 11:07:48.143582
7809 11:07:48.144060 Set Vref, RX VrefLevel [Byte0]: 43
7810 11:07:48.147038 [Byte1]: 43
7811 11:07:48.150971
7812 11:07:48.151503 Set Vref, RX VrefLevel [Byte0]: 44
7813 11:07:48.154756 [Byte1]: 44
7814 11:07:48.158980
7815 11:07:48.159475 Set Vref, RX VrefLevel [Byte0]: 45
7816 11:07:48.162326 [Byte1]: 45
7817 11:07:48.166128
7818 11:07:48.166614 Set Vref, RX VrefLevel [Byte0]: 46
7819 11:07:48.169324 [Byte1]: 46
7820 11:07:48.173759
7821 11:07:48.174196 Set Vref, RX VrefLevel [Byte0]: 47
7822 11:07:48.177346 [Byte1]: 47
7823 11:07:48.181699
7824 11:07:48.182271 Set Vref, RX VrefLevel [Byte0]: 48
7825 11:07:48.184756 [Byte1]: 48
7826 11:07:48.188839
7827 11:07:48.189241 Set Vref, RX VrefLevel [Byte0]: 49
7828 11:07:48.192275 [Byte1]: 49
7829 11:07:48.196352
7830 11:07:48.196790 Set Vref, RX VrefLevel [Byte0]: 50
7831 11:07:48.199401 [Byte1]: 50
7832 11:07:48.203948
7833 11:07:48.204331 Set Vref, RX VrefLevel [Byte0]: 51
7834 11:07:48.207216 [Byte1]: 51
7835 11:07:48.211402
7836 11:07:48.211838 Set Vref, RX VrefLevel [Byte0]: 52
7837 11:07:48.214822 [Byte1]: 52
7838 11:07:48.218874
7839 11:07:48.219384 Set Vref, RX VrefLevel [Byte0]: 53
7840 11:07:48.221959 [Byte1]: 53
7841 11:07:48.227094
7842 11:07:48.227638 Set Vref, RX VrefLevel [Byte0]: 54
7843 11:07:48.229485 [Byte1]: 54
7844 11:07:48.233850
7845 11:07:48.234305 Set Vref, RX VrefLevel [Byte0]: 55
7846 11:07:48.237288 [Byte1]: 55
7847 11:07:48.241435
7848 11:07:48.241817 Set Vref, RX VrefLevel [Byte0]: 56
7849 11:07:48.245464 [Byte1]: 56
7850 11:07:48.248973
7851 11:07:48.249361 Set Vref, RX VrefLevel [Byte0]: 57
7852 11:07:48.252337 [Byte1]: 57
7853 11:07:48.256505
7854 11:07:48.257012 Set Vref, RX VrefLevel [Byte0]: 58
7855 11:07:48.259675 [Byte1]: 58
7856 11:07:48.263982
7857 11:07:48.264428 Set Vref, RX VrefLevel [Byte0]: 59
7858 11:07:48.267703 [Byte1]: 59
7859 11:07:48.272181
7860 11:07:48.272565 Set Vref, RX VrefLevel [Byte0]: 60
7861 11:07:48.274967 [Byte1]: 60
7862 11:07:48.279335
7863 11:07:48.279774 Set Vref, RX VrefLevel [Byte0]: 61
7864 11:07:48.282545 [Byte1]: 61
7865 11:07:48.286742
7866 11:07:48.287561 Set Vref, RX VrefLevel [Byte0]: 62
7867 11:07:48.289983 [Byte1]: 62
7868 11:07:48.294756
7869 11:07:48.295143 Set Vref, RX VrefLevel [Byte0]: 63
7870 11:07:48.297741 [Byte1]: 63
7871 11:07:48.301686
7872 11:07:48.305191 Set Vref, RX VrefLevel [Byte0]: 64
7873 11:07:48.308374 [Byte1]: 64
7874 11:07:48.308848
7875 11:07:48.311965 Set Vref, RX VrefLevel [Byte0]: 65
7876 11:07:48.314786 [Byte1]: 65
7877 11:07:48.315246
7878 11:07:48.318187 Set Vref, RX VrefLevel [Byte0]: 66
7879 11:07:48.321487 [Byte1]: 66
7880 11:07:48.321910
7881 11:07:48.324687 Set Vref, RX VrefLevel [Byte0]: 67
7882 11:07:48.327903 [Byte1]: 67
7883 11:07:48.332117
7884 11:07:48.332504 Set Vref, RX VrefLevel [Byte0]: 68
7885 11:07:48.335521 [Byte1]: 68
7886 11:07:48.339786
7887 11:07:48.340176 Set Vref, RX VrefLevel [Byte0]: 69
7888 11:07:48.343048 [Byte1]: 69
7889 11:07:48.347155
7890 11:07:48.347543 Set Vref, RX VrefLevel [Byte0]: 70
7891 11:07:48.350470 [Byte1]: 70
7892 11:07:48.354484
7893 11:07:48.355053 Set Vref, RX VrefLevel [Byte0]: 71
7894 11:07:48.357428 [Byte1]: 71
7895 11:07:48.361895
7896 11:07:48.362371 Set Vref, RX VrefLevel [Byte0]: 72
7897 11:07:48.365157 [Byte1]: 72
7898 11:07:48.369369
7899 11:07:48.369818 Set Vref, RX VrefLevel [Byte0]: 73
7900 11:07:48.372679 [Byte1]: 73
7901 11:07:48.377009
7902 11:07:48.377398 Set Vref, RX VrefLevel [Byte0]: 74
7903 11:07:48.380586 [Byte1]: 74
7904 11:07:48.384674
7905 11:07:48.385063 Final RX Vref Byte 0 = 56 to rank0
7906 11:07:48.387713 Final RX Vref Byte 1 = 63 to rank0
7907 11:07:48.391513 Final RX Vref Byte 0 = 56 to rank1
7908 11:07:48.395001 Final RX Vref Byte 1 = 63 to rank1==
7909 11:07:48.397802 Dram Type= 6, Freq= 0, CH_0, rank 0
7910 11:07:48.404837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7911 11:07:48.405231 ==
7912 11:07:48.405534 DQS Delay:
7913 11:07:48.407953 DQS0 = 0, DQS1 = 0
7914 11:07:48.408344 DQM Delay:
7915 11:07:48.408719 DQM0 = 133, DQM1 = 127
7916 11:07:48.410745 DQ Delay:
7917 11:07:48.414367 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =132
7918 11:07:48.417414 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7919 11:07:48.421373 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7920 11:07:48.424543 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7921 11:07:48.425079
7922 11:07:48.425547
7923 11:07:48.425844
7924 11:07:48.427492 [DramC_TX_OE_Calibration] TA2
7925 11:07:48.430969 Original DQ_B0 (3 6) =30, OEN = 27
7926 11:07:48.434035 Original DQ_B1 (3 6) =30, OEN = 27
7927 11:07:48.437383 24, 0x0, End_B0=24 End_B1=24
7928 11:07:48.437813 25, 0x0, End_B0=25 End_B1=25
7929 11:07:48.441261 26, 0x0, End_B0=26 End_B1=26
7930 11:07:48.443926 27, 0x0, End_B0=27 End_B1=27
7931 11:07:48.447416 28, 0x0, End_B0=28 End_B1=28
7932 11:07:48.450566 29, 0x0, End_B0=29 End_B1=29
7933 11:07:48.450967 30, 0x0, End_B0=30 End_B1=30
7934 11:07:48.454156 31, 0x4545, End_B0=30 End_B1=30
7935 11:07:48.457380 Byte0 end_step=30 best_step=27
7936 11:07:48.460837 Byte1 end_step=30 best_step=27
7937 11:07:48.464405 Byte0 TX OE(2T, 0.5T) = (3, 3)
7938 11:07:48.467455 Byte1 TX OE(2T, 0.5T) = (3, 3)
7939 11:07:48.467861
7940 11:07:48.468162
7941 11:07:48.473923 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7942 11:07:48.477068 CH0 RK0: MR19=303, MR18=2521
7943 11:07:48.484115 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7944 11:07:48.484623
7945 11:07:48.487834 ----->DramcWriteLeveling(PI) begin...
7946 11:07:48.488412 ==
7947 11:07:48.490975 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 11:07:48.493988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 11:07:48.494585 ==
7950 11:07:48.497581 Write leveling (Byte 0): 36 => 36
7951 11:07:48.500954 Write leveling (Byte 1): 26 => 26
7952 11:07:48.504180 DramcWriteLeveling(PI) end<-----
7953 11:07:48.504685
7954 11:07:48.505196 ==
7955 11:07:48.507429 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 11:07:48.510696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 11:07:48.511228 ==
7958 11:07:48.514543 [Gating] SW mode calibration
7959 11:07:48.520502 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7960 11:07:48.527754 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7961 11:07:48.530776 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)
7962 11:07:48.534096 1 4 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7963 11:07:48.540651 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7964 11:07:48.544376 1 4 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7965 11:07:48.547315 1 4 16 | B1->B0 | 2c2c 3736 | 0 1 | (0 0) (0 0)
7966 11:07:48.553820 1 4 20 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
7967 11:07:48.557566 1 4 24 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (1 1)
7968 11:07:48.560796 1 4 28 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (1 1)
7969 11:07:48.567452 1 5 0 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7970 11:07:48.570560 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7971 11:07:48.573819 1 5 8 | B1->B0 | 3434 3837 | 1 1 | (1 0) (0 0)
7972 11:07:48.580685 1 5 12 | B1->B0 | 3434 3838 | 1 1 | (1 0) (1 0)
7973 11:07:48.584154 1 5 16 | B1->B0 | 2e2e 2f2e | 0 1 | (0 1) (1 0)
7974 11:07:48.587056 1 5 20 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7975 11:07:48.594083 1 5 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7976 11:07:48.597141 1 5 28 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7977 11:07:48.600318 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7978 11:07:48.607346 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7979 11:07:48.610396 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7980 11:07:48.613869 1 6 12 | B1->B0 | 2727 3e3d | 1 1 | (0 0) (0 0)
7981 11:07:48.620737 1 6 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7982 11:07:48.623726 1 6 20 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7983 11:07:48.627347 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 11:07:48.631053 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 11:07:48.637020 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7986 11:07:48.640741 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 11:07:48.643941 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 11:07:48.650765 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7989 11:07:48.654051 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7990 11:07:48.657245 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 11:07:48.663871 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 11:07:48.667912 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 11:07:48.671077 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 11:07:48.677441 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 11:07:48.680650 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 11:07:48.683853 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 11:07:48.690769 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 11:07:48.693725 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 11:07:48.697313 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 11:07:48.703861 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 11:07:48.706997 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:07:48.710343 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:07:48.716838 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:07:48.719961 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8005 11:07:48.723575 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 11:07:48.726939 Total UI for P1: 0, mck2ui 16
8007 11:07:48.730525 best dqsien dly found for B0: ( 1, 9, 12)
8008 11:07:48.733708 Total UI for P1: 0, mck2ui 16
8009 11:07:48.736654 best dqsien dly found for B1: ( 1, 9, 12)
8010 11:07:48.739981 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8011 11:07:48.743406 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8012 11:07:48.743956
8013 11:07:48.749786 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8014 11:07:48.753265 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8015 11:07:48.753884 [Gating] SW calibration Done
8016 11:07:48.756589 ==
8017 11:07:48.760278 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 11:07:48.763440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 11:07:48.764063 ==
8020 11:07:48.764579 RX Vref Scan: 0
8021 11:07:48.765090
8022 11:07:48.767022 RX Vref 0 -> 0, step: 1
8023 11:07:48.767578
8024 11:07:48.769967 RX Delay 0 -> 252, step: 8
8025 11:07:48.772974 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8026 11:07:48.776989 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8027 11:07:48.780338 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8028 11:07:48.786600 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8029 11:07:48.789898 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8030 11:07:48.792911 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8031 11:07:48.796444 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8032 11:07:48.799963 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8033 11:07:48.806046 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8034 11:07:48.809449 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8035 11:07:48.813337 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8036 11:07:48.816100 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8037 11:07:48.823157 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8038 11:07:48.826444 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8039 11:07:48.829726 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8040 11:07:48.832879 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8041 11:07:48.833422 ==
8042 11:07:48.836204 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 11:07:48.842723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 11:07:48.843117 ==
8045 11:07:48.843422 DQS Delay:
8046 11:07:48.843700 DQS0 = 0, DQS1 = 0
8047 11:07:48.845873 DQM Delay:
8048 11:07:48.846315 DQM0 = 136, DQM1 = 129
8049 11:07:48.849433 DQ Delay:
8050 11:07:48.852896 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8051 11:07:48.856482 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8052 11:07:48.859215 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8053 11:07:48.862613 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8054 11:07:48.863003
8055 11:07:48.863300
8056 11:07:48.863578 ==
8057 11:07:48.865715 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 11:07:48.868988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 11:07:48.872320 ==
8060 11:07:48.872736
8061 11:07:48.873036
8062 11:07:48.873313 TX Vref Scan disable
8063 11:07:48.875504 == TX Byte 0 ==
8064 11:07:48.879352 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8065 11:07:48.882770 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8066 11:07:48.885481 == TX Byte 1 ==
8067 11:07:48.888750 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8068 11:07:48.892552 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8069 11:07:48.895348 ==
8070 11:07:48.898663 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 11:07:48.902108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 11:07:48.902475 ==
8073 11:07:48.916140
8074 11:07:48.919064 TX Vref early break, caculate TX vref
8075 11:07:48.922075 TX Vref=16, minBit 1, minWin=23, winSum=386
8076 11:07:48.925588 TX Vref=18, minBit 1, minWin=23, winSum=397
8077 11:07:48.928834 TX Vref=20, minBit 4, minWin=23, winSum=404
8078 11:07:48.932209 TX Vref=22, minBit 1, minWin=24, winSum=415
8079 11:07:48.935501 TX Vref=24, minBit 1, minWin=25, winSum=418
8080 11:07:48.942334 TX Vref=26, minBit 1, minWin=25, winSum=425
8081 11:07:48.945532 TX Vref=28, minBit 0, minWin=25, winSum=425
8082 11:07:48.948988 TX Vref=30, minBit 3, minWin=25, winSum=416
8083 11:07:48.952256 TX Vref=32, minBit 4, minWin=24, winSum=408
8084 11:07:48.955850 TX Vref=34, minBit 0, minWin=24, winSum=401
8085 11:07:48.962408 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
8086 11:07:48.962803
8087 11:07:48.965435 Final TX Range 0 Vref 26
8088 11:07:48.966003
8089 11:07:48.966576 ==
8090 11:07:48.968806 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 11:07:48.971939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 11:07:48.972328 ==
8093 11:07:48.972626
8094 11:07:48.972900
8095 11:07:48.975501 TX Vref Scan disable
8096 11:07:48.982414 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8097 11:07:48.982801 == TX Byte 0 ==
8098 11:07:48.985246 u2DelayCellOfst[0]=13 cells (4 PI)
8099 11:07:48.988309 u2DelayCellOfst[1]=16 cells (5 PI)
8100 11:07:48.992429 u2DelayCellOfst[2]=13 cells (4 PI)
8101 11:07:48.995651 u2DelayCellOfst[3]=10 cells (3 PI)
8102 11:07:48.998774 u2DelayCellOfst[4]=6 cells (2 PI)
8103 11:07:49.002038 u2DelayCellOfst[5]=0 cells (0 PI)
8104 11:07:49.005284 u2DelayCellOfst[6]=16 cells (5 PI)
8105 11:07:49.005795 u2DelayCellOfst[7]=16 cells (5 PI)
8106 11:07:49.012262 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8107 11:07:49.015454 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8108 11:07:49.016071 == TX Byte 1 ==
8109 11:07:49.019739 u2DelayCellOfst[8]=0 cells (0 PI)
8110 11:07:49.021794 u2DelayCellOfst[9]=0 cells (0 PI)
8111 11:07:49.025413 u2DelayCellOfst[10]=6 cells (2 PI)
8112 11:07:49.028477 u2DelayCellOfst[11]=3 cells (1 PI)
8113 11:07:49.032300 u2DelayCellOfst[12]=10 cells (3 PI)
8114 11:07:49.035221 u2DelayCellOfst[13]=10 cells (3 PI)
8115 11:07:49.038554 u2DelayCellOfst[14]=13 cells (4 PI)
8116 11:07:49.041710 u2DelayCellOfst[15]=10 cells (3 PI)
8117 11:07:49.045245 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8118 11:07:49.052269 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8119 11:07:49.052859 DramC Write-DBI on
8120 11:07:49.053342 ==
8121 11:07:49.054911 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 11:07:49.058914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 11:07:49.059302 ==
8124 11:07:49.062082
8125 11:07:49.062483
8126 11:07:49.062792 TX Vref Scan disable
8127 11:07:49.064751 == TX Byte 0 ==
8128 11:07:49.068525 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8129 11:07:49.072086 == TX Byte 1 ==
8130 11:07:49.075186 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8131 11:07:49.078917 DramC Write-DBI off
8132 11:07:49.079299
8133 11:07:49.079597 [DATLAT]
8134 11:07:49.079876 Freq=1600, CH0 RK1
8135 11:07:49.080140
8136 11:07:49.081974 DATLAT Default: 0xf
8137 11:07:49.082460 0, 0xFFFF, sum = 0
8138 11:07:49.085490 1, 0xFFFF, sum = 0
8139 11:07:49.086081 2, 0xFFFF, sum = 0
8140 11:07:49.088412 3, 0xFFFF, sum = 0
8141 11:07:49.091799 4, 0xFFFF, sum = 0
8142 11:07:49.092277 5, 0xFFFF, sum = 0
8143 11:07:49.095576 6, 0xFFFF, sum = 0
8144 11:07:49.096168 7, 0xFFFF, sum = 0
8145 11:07:49.098128 8, 0xFFFF, sum = 0
8146 11:07:49.098650 9, 0xFFFF, sum = 0
8147 11:07:49.101674 10, 0xFFFF, sum = 0
8148 11:07:49.102192 11, 0xFFFF, sum = 0
8149 11:07:49.105010 12, 0xFFFF, sum = 0
8150 11:07:49.105424 13, 0xFFFF, sum = 0
8151 11:07:49.108514 14, 0x0, sum = 1
8152 11:07:49.108909 15, 0x0, sum = 2
8153 11:07:49.111667 16, 0x0, sum = 3
8154 11:07:49.112142 17, 0x0, sum = 4
8155 11:07:49.115393 best_step = 15
8156 11:07:49.115920
8157 11:07:49.116405 ==
8158 11:07:49.118586 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 11:07:49.121705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 11:07:49.122235 ==
8161 11:07:49.122665 RX Vref Scan: 0
8162 11:07:49.123124
8163 11:07:49.125438 RX Vref 0 -> 0, step: 1
8164 11:07:49.125891
8165 11:07:49.128423 RX Delay 19 -> 252, step: 4
8166 11:07:49.131521 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8167 11:07:49.139190 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8168 11:07:49.141663 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8169 11:07:49.145026 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8170 11:07:49.148060 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8171 11:07:49.152055 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8172 11:07:49.154901 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8173 11:07:49.161818 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8174 11:07:49.164998 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8175 11:07:49.168071 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8176 11:07:49.171766 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8177 11:07:49.178638 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8178 11:07:49.181641 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8179 11:07:49.184848 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8180 11:07:49.188345 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8181 11:07:49.191700 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8182 11:07:49.192222 ==
8183 11:07:49.194606 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 11:07:49.201230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 11:07:49.201625 ==
8186 11:07:49.201931 DQS Delay:
8187 11:07:49.204634 DQS0 = 0, DQS1 = 0
8188 11:07:49.205114 DQM Delay:
8189 11:07:49.207813 DQM0 = 133, DQM1 = 127
8190 11:07:49.208268 DQ Delay:
8191 11:07:49.211851 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8192 11:07:49.215098 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140
8193 11:07:49.218198 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8194 11:07:49.221431 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8195 11:07:49.221816
8196 11:07:49.222162
8197 11:07:49.222449
8198 11:07:49.224626 [DramC_TX_OE_Calibration] TA2
8199 11:07:49.227973 Original DQ_B0 (3 6) =30, OEN = 27
8200 11:07:49.231624 Original DQ_B1 (3 6) =30, OEN = 27
8201 11:07:49.235441 24, 0x0, End_B0=24 End_B1=24
8202 11:07:49.235915 25, 0x0, End_B0=25 End_B1=25
8203 11:07:49.238410 26, 0x0, End_B0=26 End_B1=26
8204 11:07:49.241430 27, 0x0, End_B0=27 End_B1=27
8205 11:07:49.244880 28, 0x0, End_B0=28 End_B1=28
8206 11:07:49.248597 29, 0x0, End_B0=29 End_B1=29
8207 11:07:49.248993 30, 0x0, End_B0=30 End_B1=30
8208 11:07:49.251721 31, 0x4141, End_B0=30 End_B1=30
8209 11:07:49.255058 Byte0 end_step=30 best_step=27
8210 11:07:49.258153 Byte1 end_step=30 best_step=27
8211 11:07:49.261501 Byte0 TX OE(2T, 0.5T) = (3, 3)
8212 11:07:49.264476 Byte1 TX OE(2T, 0.5T) = (3, 3)
8213 11:07:49.265022
8214 11:07:49.265472
8215 11:07:49.271166 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8216 11:07:49.274725 CH0 RK1: MR19=303, MR18=210A
8217 11:07:49.281427 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8218 11:07:49.284612 [RxdqsGatingPostProcess] freq 1600
8219 11:07:49.287959 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8220 11:07:49.291549 best DQS0 dly(2T, 0.5T) = (1, 1)
8221 11:07:49.294733 best DQS1 dly(2T, 0.5T) = (1, 1)
8222 11:07:49.298253 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8223 11:07:49.301503 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8224 11:07:49.304608 best DQS0 dly(2T, 0.5T) = (1, 1)
8225 11:07:49.308103 best DQS1 dly(2T, 0.5T) = (1, 1)
8226 11:07:49.311066 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8227 11:07:49.314431 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8228 11:07:49.317771 Pre-setting of DQS Precalculation
8229 11:07:49.320887 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8230 11:07:49.321312 ==
8231 11:07:49.324226 Dram Type= 6, Freq= 0, CH_1, rank 0
8232 11:07:49.327571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 11:07:49.330716 ==
8234 11:07:49.334337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8235 11:07:49.337646 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8236 11:07:49.344532 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8237 11:07:49.350817 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8238 11:07:49.358136 [CA 0] Center 41 (12~71) winsize 60
8239 11:07:49.361125 [CA 1] Center 41 (12~71) winsize 60
8240 11:07:49.364340 [CA 2] Center 38 (9~68) winsize 60
8241 11:07:49.367937 [CA 3] Center 37 (8~66) winsize 59
8242 11:07:49.371332 [CA 4] Center 37 (8~67) winsize 60
8243 11:07:49.374458 [CA 5] Center 36 (7~66) winsize 60
8244 11:07:49.375015
8245 11:07:49.378219 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8246 11:07:49.378602
8247 11:07:49.381429 [CATrainingPosCal] consider 1 rank data
8248 11:07:49.384714 u2DelayCellTimex100 = 290/100 ps
8249 11:07:49.388119 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8250 11:07:49.394228 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8251 11:07:49.398069 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8252 11:07:49.401129 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8253 11:07:49.404406 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8254 11:07:49.407942 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8255 11:07:49.408489
8256 11:07:49.410961 CA PerBit enable=1, Macro0, CA PI delay=36
8257 11:07:49.411555
8258 11:07:49.414126 [CBTSetCACLKResult] CA Dly = 36
8259 11:07:49.417663 CS Dly: 11 (0~42)
8260 11:07:49.421071 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8261 11:07:49.424376 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8262 11:07:49.424904 ==
8263 11:07:49.427590 Dram Type= 6, Freq= 0, CH_1, rank 1
8264 11:07:49.431118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 11:07:49.434895 ==
8266 11:07:49.437439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8267 11:07:49.440785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8268 11:07:49.447920 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8269 11:07:49.450689 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8270 11:07:49.461466 [CA 0] Center 41 (12~71) winsize 60
8271 11:07:49.464511 [CA 1] Center 41 (12~71) winsize 60
8272 11:07:49.467913 [CA 2] Center 38 (9~68) winsize 60
8273 11:07:49.471303 [CA 3] Center 38 (8~68) winsize 61
8274 11:07:49.474493 [CA 4] Center 38 (8~69) winsize 62
8275 11:07:49.477527 [CA 5] Center 36 (7~66) winsize 60
8276 11:07:49.477911
8277 11:07:49.481216 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8278 11:07:49.481604
8279 11:07:49.484571 [CATrainingPosCal] consider 2 rank data
8280 11:07:49.487946 u2DelayCellTimex100 = 290/100 ps
8281 11:07:49.490891 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8282 11:07:49.497845 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8283 11:07:49.501593 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8284 11:07:49.504610 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8285 11:07:49.508071 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8286 11:07:49.511352 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8287 11:07:49.511753
8288 11:07:49.514810 CA PerBit enable=1, Macro0, CA PI delay=36
8289 11:07:49.515196
8290 11:07:49.517455 [CBTSetCACLKResult] CA Dly = 36
8291 11:07:49.520676 CS Dly: 12 (0~45)
8292 11:07:49.524898 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8293 11:07:49.528039 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8294 11:07:49.528465
8295 11:07:49.531375 ----->DramcWriteLeveling(PI) begin...
8296 11:07:49.531767 ==
8297 11:07:49.534469 Dram Type= 6, Freq= 0, CH_1, rank 0
8298 11:07:49.537665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 11:07:49.541056 ==
8300 11:07:49.541438 Write leveling (Byte 0): 27 => 27
8301 11:07:49.544722 Write leveling (Byte 1): 29 => 29
8302 11:07:49.548165 DramcWriteLeveling(PI) end<-----
8303 11:07:49.548635
8304 11:07:49.548965 ==
8305 11:07:49.551141 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 11:07:49.557782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 11:07:49.558428 ==
8308 11:07:49.558931 [Gating] SW mode calibration
8309 11:07:49.567852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8310 11:07:49.570713 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8311 11:07:49.574365 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 11:07:49.580625 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 11:07:49.583901 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
8314 11:07:49.591168 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 11:07:49.593487 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 11:07:49.597029 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 11:07:49.603891 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 11:07:49.607058 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 11:07:49.610576 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 11:07:49.617354 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 11:07:49.620166 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8322 11:07:49.623792 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
8323 11:07:49.629927 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 11:07:49.633377 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 11:07:49.636723 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 11:07:49.643135 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 11:07:49.647065 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 11:07:49.650122 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 11:07:49.656953 1 6 8 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
8330 11:07:49.659813 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8331 11:07:49.663051 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 11:07:49.669337 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 11:07:49.672659 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 11:07:49.676084 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 11:07:49.679812 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 11:07:49.686369 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 11:07:49.689888 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8338 11:07:49.693194 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8339 11:07:49.699380 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 11:07:49.702778 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 11:07:49.706155 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 11:07:49.712558 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 11:07:49.715961 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 11:07:49.719705 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 11:07:49.726101 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 11:07:49.729484 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 11:07:49.733364 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 11:07:49.739844 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 11:07:49.743100 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 11:07:49.745841 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:07:49.752652 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:07:49.756139 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8353 11:07:49.759316 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8354 11:07:49.765861 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8355 11:07:49.769735 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 11:07:49.772342 Total UI for P1: 0, mck2ui 16
8357 11:07:49.776015 best dqsien dly found for B0: ( 1, 9, 8)
8358 11:07:49.779360 Total UI for P1: 0, mck2ui 16
8359 11:07:49.782489 best dqsien dly found for B1: ( 1, 9, 10)
8360 11:07:49.785701 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8361 11:07:49.789454 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8362 11:07:49.789840
8363 11:07:49.792642 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8364 11:07:49.795771 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8365 11:07:49.799004 [Gating] SW calibration Done
8366 11:07:49.799475 ==
8367 11:07:49.802742 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 11:07:49.806074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 11:07:49.809358 ==
8370 11:07:49.809750 RX Vref Scan: 0
8371 11:07:49.810276
8372 11:07:49.812315 RX Vref 0 -> 0, step: 1
8373 11:07:49.812738
8374 11:07:49.813139 RX Delay 0 -> 252, step: 8
8375 11:07:49.819600 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8376 11:07:49.822856 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8377 11:07:49.825664 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8378 11:07:49.829339 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8379 11:07:49.832431 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8380 11:07:49.839398 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8381 11:07:49.842647 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8382 11:07:49.845820 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8383 11:07:49.848973 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8384 11:07:49.852732 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8385 11:07:49.859145 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8386 11:07:49.862374 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8387 11:07:49.865580 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8388 11:07:49.868606 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8389 11:07:49.872043 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8390 11:07:49.879058 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8391 11:07:49.879504 ==
8392 11:07:49.882220 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 11:07:49.885631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 11:07:49.886082 ==
8395 11:07:49.886488 DQS Delay:
8396 11:07:49.888912 DQS0 = 0, DQS1 = 0
8397 11:07:49.889304 DQM Delay:
8398 11:07:49.891934 DQM0 = 136, DQM1 = 132
8399 11:07:49.892361 DQ Delay:
8400 11:07:49.895602 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8401 11:07:49.898604 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8402 11:07:49.902226 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8403 11:07:49.905342 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8404 11:07:49.908524
8405 11:07:49.908909
8406 11:07:49.909207 ==
8407 11:07:49.911926 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 11:07:49.915097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 11:07:49.915490 ==
8410 11:07:49.915790
8411 11:07:49.916064
8412 11:07:49.918459 TX Vref Scan disable
8413 11:07:49.918848 == TX Byte 0 ==
8414 11:07:49.925657 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8415 11:07:49.928445 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8416 11:07:49.928837 == TX Byte 1 ==
8417 11:07:49.935139 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8418 11:07:49.938358 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8419 11:07:49.938740 ==
8420 11:07:49.942116 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 11:07:49.945287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 11:07:49.945692 ==
8423 11:07:49.958689
8424 11:07:49.961730 TX Vref early break, caculate TX vref
8425 11:07:49.964981 TX Vref=16, minBit 1, minWin=22, winSum=376
8426 11:07:49.968677 TX Vref=18, minBit 0, minWin=23, winSum=382
8427 11:07:49.971897 TX Vref=20, minBit 0, minWin=23, winSum=391
8428 11:07:49.974989 TX Vref=22, minBit 1, minWin=24, winSum=409
8429 11:07:49.978966 TX Vref=24, minBit 0, minWin=24, winSum=414
8430 11:07:49.985016 TX Vref=26, minBit 0, minWin=25, winSum=421
8431 11:07:49.988306 TX Vref=28, minBit 1, minWin=25, winSum=424
8432 11:07:49.991568 TX Vref=30, minBit 0, minWin=25, winSum=419
8433 11:07:49.995340 TX Vref=32, minBit 0, minWin=25, winSum=412
8434 11:07:49.998412 TX Vref=34, minBit 0, minWin=23, winSum=399
8435 11:07:50.004828 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 28
8436 11:07:50.005390
8437 11:07:50.008201 Final TX Range 0 Vref 28
8438 11:07:50.008561
8439 11:07:50.009030 ==
8440 11:07:50.011496 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 11:07:50.014825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 11:07:50.015237 ==
8443 11:07:50.015629
8444 11:07:50.015994
8445 11:07:50.019063 TX Vref Scan disable
8446 11:07:50.024971 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8447 11:07:50.025493 == TX Byte 0 ==
8448 11:07:50.028171 u2DelayCellOfst[0]=16 cells (5 PI)
8449 11:07:50.031385 u2DelayCellOfst[1]=6 cells (2 PI)
8450 11:07:50.035029 u2DelayCellOfst[2]=0 cells (0 PI)
8451 11:07:50.038126 u2DelayCellOfst[3]=6 cells (2 PI)
8452 11:07:50.041440 u2DelayCellOfst[4]=6 cells (2 PI)
8453 11:07:50.044711 u2DelayCellOfst[5]=16 cells (5 PI)
8454 11:07:50.045256 u2DelayCellOfst[6]=16 cells (5 PI)
8455 11:07:50.048169 u2DelayCellOfst[7]=6 cells (2 PI)
8456 11:07:50.054516 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8457 11:07:50.058444 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8458 11:07:50.058832 == TX Byte 1 ==
8459 11:07:50.061823 u2DelayCellOfst[8]=0 cells (0 PI)
8460 11:07:50.064434 u2DelayCellOfst[9]=6 cells (2 PI)
8461 11:07:50.068074 u2DelayCellOfst[10]=13 cells (4 PI)
8462 11:07:50.071713 u2DelayCellOfst[11]=6 cells (2 PI)
8463 11:07:50.074761 u2DelayCellOfst[12]=13 cells (4 PI)
8464 11:07:50.078298 u2DelayCellOfst[13]=16 cells (5 PI)
8465 11:07:50.081286 u2DelayCellOfst[14]=16 cells (5 PI)
8466 11:07:50.085228 u2DelayCellOfst[15]=16 cells (5 PI)
8467 11:07:50.088280 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8468 11:07:50.092020 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8469 11:07:50.095215 DramC Write-DBI on
8470 11:07:50.095625 ==
8471 11:07:50.097996 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 11:07:50.101873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 11:07:50.102437 ==
8474 11:07:50.102743
8475 11:07:50.103016
8476 11:07:50.105015 TX Vref Scan disable
8477 11:07:50.108439 == TX Byte 0 ==
8478 11:07:50.111572 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8479 11:07:50.114840 == TX Byte 1 ==
8480 11:07:50.118133 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8481 11:07:50.118520 DramC Write-DBI off
8482 11:07:50.118817
8483 11:07:50.121439 [DATLAT]
8484 11:07:50.121820 Freq=1600, CH1 RK0
8485 11:07:50.122172
8486 11:07:50.124455 DATLAT Default: 0xf
8487 11:07:50.124906 0, 0xFFFF, sum = 0
8488 11:07:50.128428 1, 0xFFFF, sum = 0
8489 11:07:50.128852 2, 0xFFFF, sum = 0
8490 11:07:50.131404 3, 0xFFFF, sum = 0
8491 11:07:50.131879 4, 0xFFFF, sum = 0
8492 11:07:50.135302 5, 0xFFFF, sum = 0
8493 11:07:50.135694 6, 0xFFFF, sum = 0
8494 11:07:50.138356 7, 0xFFFF, sum = 0
8495 11:07:50.138749 8, 0xFFFF, sum = 0
8496 11:07:50.141406 9, 0xFFFF, sum = 0
8497 11:07:50.144427 10, 0xFFFF, sum = 0
8498 11:07:50.145046 11, 0xFFFF, sum = 0
8499 11:07:50.148345 12, 0xFFFF, sum = 0
8500 11:07:50.148865 13, 0xFFFF, sum = 0
8501 11:07:50.150962 14, 0x0, sum = 1
8502 11:07:50.151352 15, 0x0, sum = 2
8503 11:07:50.154473 16, 0x0, sum = 3
8504 11:07:50.155061 17, 0x0, sum = 4
8505 11:07:50.157736 best_step = 15
8506 11:07:50.158245
8507 11:07:50.158555 ==
8508 11:07:50.161085 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 11:07:50.164340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 11:07:50.164900 ==
8511 11:07:50.165325 RX Vref Scan: 1
8512 11:07:50.165667
8513 11:07:50.167830 Set Vref Range= 24 -> 127
8514 11:07:50.168246
8515 11:07:50.171299 RX Vref 24 -> 127, step: 1
8516 11:07:50.171729
8517 11:07:50.173978 RX Delay 27 -> 252, step: 4
8518 11:07:50.174502
8519 11:07:50.177509 Set Vref, RX VrefLevel [Byte0]: 24
8520 11:07:50.181010 [Byte1]: 24
8521 11:07:50.181437
8522 11:07:50.184248 Set Vref, RX VrefLevel [Byte0]: 25
8523 11:07:50.187502 [Byte1]: 25
8524 11:07:50.188120
8525 11:07:50.191210 Set Vref, RX VrefLevel [Byte0]: 26
8526 11:07:50.194433 [Byte1]: 26
8527 11:07:50.197711
8528 11:07:50.198256 Set Vref, RX VrefLevel [Byte0]: 27
8529 11:07:50.201668 [Byte1]: 27
8530 11:07:50.205145
8531 11:07:50.205680 Set Vref, RX VrefLevel [Byte0]: 28
8532 11:07:50.208700 [Byte1]: 28
8533 11:07:50.212978
8534 11:07:50.213489 Set Vref, RX VrefLevel [Byte0]: 29
8535 11:07:50.216224 [Byte1]: 29
8536 11:07:50.220574
8537 11:07:50.221081 Set Vref, RX VrefLevel [Byte0]: 30
8538 11:07:50.224047 [Byte1]: 30
8539 11:07:50.227883
8540 11:07:50.228416 Set Vref, RX VrefLevel [Byte0]: 31
8541 11:07:50.231208 [Byte1]: 31
8542 11:07:50.235852
8543 11:07:50.236385 Set Vref, RX VrefLevel [Byte0]: 32
8544 11:07:50.238922 [Byte1]: 32
8545 11:07:50.243091
8546 11:07:50.243535 Set Vref, RX VrefLevel [Byte0]: 33
8547 11:07:50.246398 [Byte1]: 33
8548 11:07:50.250717
8549 11:07:50.251141 Set Vref, RX VrefLevel [Byte0]: 34
8550 11:07:50.254076 [Byte1]: 34
8551 11:07:50.257816
8552 11:07:50.258403 Set Vref, RX VrefLevel [Byte0]: 35
8553 11:07:50.261672 [Byte1]: 35
8554 11:07:50.265740
8555 11:07:50.266319 Set Vref, RX VrefLevel [Byte0]: 36
8556 11:07:50.269053 [Byte1]: 36
8557 11:07:50.273253
8558 11:07:50.273660 Set Vref, RX VrefLevel [Byte0]: 37
8559 11:07:50.276394 [Byte1]: 37
8560 11:07:50.280715
8561 11:07:50.281244 Set Vref, RX VrefLevel [Byte0]: 38
8562 11:07:50.283862 [Byte1]: 38
8563 11:07:50.288300
8564 11:07:50.288815 Set Vref, RX VrefLevel [Byte0]: 39
8565 11:07:50.291524 [Byte1]: 39
8566 11:07:50.295309
8567 11:07:50.295840 Set Vref, RX VrefLevel [Byte0]: 40
8568 11:07:50.298980 [Byte1]: 40
8569 11:07:50.303199
8570 11:07:50.303711 Set Vref, RX VrefLevel [Byte0]: 41
8571 11:07:50.306550 [Byte1]: 41
8572 11:07:50.310547
8573 11:07:50.311104 Set Vref, RX VrefLevel [Byte0]: 42
8574 11:07:50.314828 [Byte1]: 42
8575 11:07:50.318352
8576 11:07:50.318900 Set Vref, RX VrefLevel [Byte0]: 43
8577 11:07:50.321575 [Byte1]: 43
8578 11:07:50.325715
8579 11:07:50.326229 Set Vref, RX VrefLevel [Byte0]: 44
8580 11:07:50.329524 [Byte1]: 44
8581 11:07:50.333191
8582 11:07:50.333697 Set Vref, RX VrefLevel [Byte0]: 45
8583 11:07:50.336627 [Byte1]: 45
8584 11:07:50.341106
8585 11:07:50.341549 Set Vref, RX VrefLevel [Byte0]: 46
8586 11:07:50.344570 [Byte1]: 46
8587 11:07:50.348312
8588 11:07:50.348701 Set Vref, RX VrefLevel [Byte0]: 47
8589 11:07:50.351562 [Byte1]: 47
8590 11:07:50.356212
8591 11:07:50.356726 Set Vref, RX VrefLevel [Byte0]: 48
8592 11:07:50.359589 [Byte1]: 48
8593 11:07:50.363504
8594 11:07:50.363964 Set Vref, RX VrefLevel [Byte0]: 49
8595 11:07:50.366791 [Byte1]: 49
8596 11:07:50.371130
8597 11:07:50.371556 Set Vref, RX VrefLevel [Byte0]: 50
8598 11:07:50.374501 [Byte1]: 50
8599 11:07:50.378810
8600 11:07:50.381851 Set Vref, RX VrefLevel [Byte0]: 51
8601 11:07:50.382324 [Byte1]: 51
8602 11:07:50.386236
8603 11:07:50.386671 Set Vref, RX VrefLevel [Byte0]: 52
8604 11:07:50.389483 [Byte1]: 52
8605 11:07:50.394105
8606 11:07:50.394615 Set Vref, RX VrefLevel [Byte0]: 53
8607 11:07:50.397002 [Byte1]: 53
8608 11:07:50.401090
8609 11:07:50.401684 Set Vref, RX VrefLevel [Byte0]: 54
8610 11:07:50.404339 [Byte1]: 54
8611 11:07:50.408811
8612 11:07:50.409317 Set Vref, RX VrefLevel [Byte0]: 55
8613 11:07:50.411970 [Byte1]: 55
8614 11:07:50.416184
8615 11:07:50.416693 Set Vref, RX VrefLevel [Byte0]: 56
8616 11:07:50.419652 [Byte1]: 56
8617 11:07:50.424097
8618 11:07:50.424633 Set Vref, RX VrefLevel [Byte0]: 57
8619 11:07:50.426913 [Byte1]: 57
8620 11:07:50.430964
8621 11:07:50.431377 Set Vref, RX VrefLevel [Byte0]: 58
8622 11:07:50.434748 [Byte1]: 58
8623 11:07:50.439124
8624 11:07:50.439678 Set Vref, RX VrefLevel [Byte0]: 59
8625 11:07:50.442099 [Byte1]: 59
8626 11:07:50.446507
8627 11:07:50.446896 Set Vref, RX VrefLevel [Byte0]: 60
8628 11:07:50.449538 [Byte1]: 60
8629 11:07:50.453651
8630 11:07:50.454166 Set Vref, RX VrefLevel [Byte0]: 61
8631 11:07:50.457096 [Byte1]: 61
8632 11:07:50.461660
8633 11:07:50.462262 Set Vref, RX VrefLevel [Byte0]: 62
8634 11:07:50.464635 [Byte1]: 62
8635 11:07:50.468784
8636 11:07:50.469403 Set Vref, RX VrefLevel [Byte0]: 63
8637 11:07:50.472296 [Byte1]: 63
8638 11:07:50.476260
8639 11:07:50.476832 Set Vref, RX VrefLevel [Byte0]: 64
8640 11:07:50.479502 [Byte1]: 64
8641 11:07:50.484062
8642 11:07:50.484622 Set Vref, RX VrefLevel [Byte0]: 65
8643 11:07:50.487118 [Byte1]: 65
8644 11:07:50.491290
8645 11:07:50.491882 Set Vref, RX VrefLevel [Byte0]: 66
8646 11:07:50.494976 [Byte1]: 66
8647 11:07:50.498861
8648 11:07:50.499399 Set Vref, RX VrefLevel [Byte0]: 67
8649 11:07:50.502621 [Byte1]: 67
8650 11:07:50.506732
8651 11:07:50.507338 Set Vref, RX VrefLevel [Byte0]: 68
8652 11:07:50.509822 [Byte1]: 68
8653 11:07:50.513631
8654 11:07:50.513858 Set Vref, RX VrefLevel [Byte0]: 69
8655 11:07:50.517185 [Byte1]: 69
8656 11:07:50.521052
8657 11:07:50.521221 Set Vref, RX VrefLevel [Byte0]: 70
8658 11:07:50.525130 [Byte1]: 70
8659 11:07:50.529018
8660 11:07:50.529551 Set Vref, RX VrefLevel [Byte0]: 71
8661 11:07:50.532773 [Byte1]: 71
8662 11:07:50.537027
8663 11:07:50.537590 Set Vref, RX VrefLevel [Byte0]: 72
8664 11:07:50.540133 [Byte1]: 72
8665 11:07:50.544240
8666 11:07:50.544624 Set Vref, RX VrefLevel [Byte0]: 73
8667 11:07:50.547669 [Byte1]: 73
8668 11:07:50.551757
8669 11:07:50.552148 Set Vref, RX VrefLevel [Byte0]: 74
8670 11:07:50.554936 [Byte1]: 74
8671 11:07:50.559973
8672 11:07:50.560372 Set Vref, RX VrefLevel [Byte0]: 75
8673 11:07:50.562448 [Byte1]: 75
8674 11:07:50.566875
8675 11:07:50.567274 Set Vref, RX VrefLevel [Byte0]: 76
8676 11:07:50.570108 [Byte1]: 76
8677 11:07:50.574573
8678 11:07:50.574961 Set Vref, RX VrefLevel [Byte0]: 77
8679 11:07:50.577635 [Byte1]: 77
8680 11:07:50.581732
8681 11:07:50.582165 Final RX Vref Byte 0 = 58 to rank0
8682 11:07:50.584963 Final RX Vref Byte 1 = 57 to rank0
8683 11:07:50.588231 Final RX Vref Byte 0 = 58 to rank1
8684 11:07:50.591974 Final RX Vref Byte 1 = 57 to rank1==
8685 11:07:50.595693 Dram Type= 6, Freq= 0, CH_1, rank 0
8686 11:07:50.601547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8687 11:07:50.601942 ==
8688 11:07:50.602298 DQS Delay:
8689 11:07:50.605227 DQS0 = 0, DQS1 = 0
8690 11:07:50.605715 DQM Delay:
8691 11:07:50.606280 DQM0 = 133, DQM1 = 131
8692 11:07:50.608437 DQ Delay:
8693 11:07:50.611501 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8694 11:07:50.614806 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8695 11:07:50.618694 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8696 11:07:50.621805 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8697 11:07:50.622264
8698 11:07:50.622570
8699 11:07:50.622869
8700 11:07:50.624764 [DramC_TX_OE_Calibration] TA2
8701 11:07:50.628036 Original DQ_B0 (3 6) =30, OEN = 27
8702 11:07:50.631636 Original DQ_B1 (3 6) =30, OEN = 27
8703 11:07:50.635196 24, 0x0, End_B0=24 End_B1=24
8704 11:07:50.635710 25, 0x0, End_B0=25 End_B1=25
8705 11:07:50.638375 26, 0x0, End_B0=26 End_B1=26
8706 11:07:50.641345 27, 0x0, End_B0=27 End_B1=27
8707 11:07:50.644990 28, 0x0, End_B0=28 End_B1=28
8708 11:07:50.648022 29, 0x0, End_B0=29 End_B1=29
8709 11:07:50.648631 30, 0x0, End_B0=30 End_B1=30
8710 11:07:50.651531 31, 0x4141, End_B0=30 End_B1=30
8711 11:07:50.654611 Byte0 end_step=30 best_step=27
8712 11:07:50.658494 Byte1 end_step=30 best_step=27
8713 11:07:50.661624 Byte0 TX OE(2T, 0.5T) = (3, 3)
8714 11:07:50.664578 Byte1 TX OE(2T, 0.5T) = (3, 3)
8715 11:07:50.664984
8716 11:07:50.665394
8717 11:07:50.671335 [DQSOSCAuto] RK0, (LSB)MR18= 0x1926, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8718 11:07:50.674611 CH1 RK0: MR19=303, MR18=1926
8719 11:07:50.680967 CH1_RK0: MR19=0x303, MR18=0x1926, DQSOSC=390, MR23=63, INC=24, DEC=16
8720 11:07:50.681346
8721 11:07:50.684872 ----->DramcWriteLeveling(PI) begin...
8722 11:07:50.685379 ==
8723 11:07:50.687968 Dram Type= 6, Freq= 0, CH_1, rank 1
8724 11:07:50.691163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 11:07:50.691704 ==
8726 11:07:50.694378 Write leveling (Byte 0): 26 => 26
8727 11:07:50.698080 Write leveling (Byte 1): 27 => 27
8728 11:07:50.700935 DramcWriteLeveling(PI) end<-----
8729 11:07:50.701368
8730 11:07:50.701671 ==
8731 11:07:50.704801 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 11:07:50.707332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 11:07:50.707723 ==
8734 11:07:50.710829 [Gating] SW mode calibration
8735 11:07:50.717489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8736 11:07:50.724159 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8737 11:07:50.727794 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 11:07:50.734254 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 11:07:50.737318 1 4 8 | B1->B0 | 2e2e 2322 | 0 1 | (0 0) (0 0)
8740 11:07:50.741027 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8741 11:07:50.748207 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 11:07:50.750704 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 11:07:50.754416 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 11:07:50.757726 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 11:07:50.764044 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 11:07:50.767769 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8747 11:07:50.770812 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8748 11:07:50.777573 1 5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8749 11:07:50.780955 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8750 11:07:50.783900 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 11:07:50.790389 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 11:07:50.793526 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 11:07:50.797263 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 11:07:50.803670 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8755 11:07:50.807287 1 6 8 | B1->B0 | 3535 2323 | 0 0 | (0 0) (0 0)
8756 11:07:50.810535 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 11:07:50.816938 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 11:07:50.820250 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 11:07:50.823672 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 11:07:50.830528 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 11:07:50.833751 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 11:07:50.837582 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 11:07:50.843542 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8764 11:07:50.846746 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8765 11:07:50.850383 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 11:07:50.856723 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 11:07:50.860236 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 11:07:50.863528 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 11:07:50.870282 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 11:07:50.873117 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 11:07:50.876826 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 11:07:50.883171 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 11:07:50.886440 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 11:07:50.890037 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 11:07:50.896794 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 11:07:50.900139 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 11:07:50.903153 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 11:07:50.909844 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8779 11:07:50.913566 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8780 11:07:50.916547 Total UI for P1: 0, mck2ui 16
8781 11:07:50.920009 best dqsien dly found for B1: ( 1, 9, 4)
8782 11:07:50.922912 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8783 11:07:50.926456 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 11:07:50.930098 Total UI for P1: 0, mck2ui 16
8785 11:07:50.933162 best dqsien dly found for B0: ( 1, 9, 10)
8786 11:07:50.936586 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8787 11:07:50.939793 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8788 11:07:50.942947
8789 11:07:50.946432 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8790 11:07:50.949420 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8791 11:07:50.953201 [Gating] SW calibration Done
8792 11:07:50.953442 ==
8793 11:07:50.956712 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 11:07:50.960085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 11:07:50.960315 ==
8796 11:07:50.960503 RX Vref Scan: 0
8797 11:07:50.963254
8798 11:07:50.963484 RX Vref 0 -> 0, step: 1
8799 11:07:50.963710
8800 11:07:50.966623 RX Delay 0 -> 252, step: 8
8801 11:07:50.969416 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8802 11:07:50.973316 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8803 11:07:50.979437 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8804 11:07:50.983268 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8805 11:07:50.986537 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8806 11:07:50.989991 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8807 11:07:50.992925 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8808 11:07:50.999581 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8809 11:07:51.002793 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8810 11:07:51.006320 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8811 11:07:51.009851 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8812 11:07:51.013022 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8813 11:07:51.020082 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8814 11:07:51.022641 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8815 11:07:51.025995 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8816 11:07:51.029585 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8817 11:07:51.029840 ==
8818 11:07:51.032755 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 11:07:51.039696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 11:07:51.039955 ==
8821 11:07:51.040155 DQS Delay:
8822 11:07:51.040337 DQS0 = 0, DQS1 = 0
8823 11:07:51.042834 DQM Delay:
8824 11:07:51.043091 DQM0 = 136, DQM1 = 133
8825 11:07:51.046216 DQ Delay:
8826 11:07:51.049466 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8827 11:07:51.052859 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8828 11:07:51.056569 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8829 11:07:51.059681 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8830 11:07:51.059937
8831 11:07:51.060134
8832 11:07:51.060315 ==
8833 11:07:51.062998 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 11:07:51.065708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 11:07:51.069951 ==
8836 11:07:51.070273
8837 11:07:51.070471
8838 11:07:51.070652 TX Vref Scan disable
8839 11:07:51.072851 == TX Byte 0 ==
8840 11:07:51.076250 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8841 11:07:51.079616 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8842 11:07:51.082778 == TX Byte 1 ==
8843 11:07:51.085892 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8844 11:07:51.089164 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8845 11:07:51.089422 ==
8846 11:07:51.092484 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 11:07:51.099198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 11:07:51.099554 ==
8849 11:07:51.111965
8850 11:07:51.114968 TX Vref early break, caculate TX vref
8851 11:07:51.118589 TX Vref=16, minBit 0, minWin=23, winSum=384
8852 11:07:51.122279 TX Vref=18, minBit 0, minWin=23, winSum=390
8853 11:07:51.125236 TX Vref=20, minBit 0, minWin=24, winSum=405
8854 11:07:51.128301 TX Vref=22, minBit 0, minWin=24, winSum=407
8855 11:07:51.131628 TX Vref=24, minBit 0, minWin=25, winSum=418
8856 11:07:51.138270 TX Vref=26, minBit 0, minWin=26, winSum=428
8857 11:07:51.141469 TX Vref=28, minBit 0, minWin=25, winSum=426
8858 11:07:51.144952 TX Vref=30, minBit 6, minWin=25, winSum=420
8859 11:07:51.148540 TX Vref=32, minBit 0, minWin=25, winSum=415
8860 11:07:51.151792 TX Vref=34, minBit 0, minWin=24, winSum=407
8861 11:07:51.155414 TX Vref=36, minBit 6, minWin=23, winSum=396
8862 11:07:51.162174 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8863 11:07:51.162326
8864 11:07:51.165206 Final TX Range 0 Vref 26
8865 11:07:51.165347
8866 11:07:51.165456 ==
8867 11:07:51.168594 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 11:07:51.171844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 11:07:51.172017 ==
8870 11:07:51.172144
8871 11:07:51.172272
8872 11:07:51.175016 TX Vref Scan disable
8873 11:07:51.181495 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8874 11:07:51.181718 == TX Byte 0 ==
8875 11:07:51.185260 u2DelayCellOfst[0]=16 cells (5 PI)
8876 11:07:51.188719 u2DelayCellOfst[1]=10 cells (3 PI)
8877 11:07:51.191950 u2DelayCellOfst[2]=0 cells (0 PI)
8878 11:07:51.195077 u2DelayCellOfst[3]=6 cells (2 PI)
8879 11:07:51.198317 u2DelayCellOfst[4]=10 cells (3 PI)
8880 11:07:51.201542 u2DelayCellOfst[5]=16 cells (5 PI)
8881 11:07:51.204919 u2DelayCellOfst[6]=16 cells (5 PI)
8882 11:07:51.208703 u2DelayCellOfst[7]=3 cells (1 PI)
8883 11:07:51.211757 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8884 11:07:51.215060 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8885 11:07:51.218506 == TX Byte 1 ==
8886 11:07:51.221973 u2DelayCellOfst[8]=0 cells (0 PI)
8887 11:07:51.222381 u2DelayCellOfst[9]=3 cells (1 PI)
8888 11:07:51.225462 u2DelayCellOfst[10]=10 cells (3 PI)
8889 11:07:51.228915 u2DelayCellOfst[11]=3 cells (1 PI)
8890 11:07:51.231815 u2DelayCellOfst[12]=13 cells (4 PI)
8891 11:07:51.234875 u2DelayCellOfst[13]=13 cells (4 PI)
8892 11:07:51.238452 u2DelayCellOfst[14]=16 cells (5 PI)
8893 11:07:51.241313 u2DelayCellOfst[15]=16 cells (5 PI)
8894 11:07:51.245374 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8895 11:07:51.251614 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8896 11:07:51.252054 DramC Write-DBI on
8897 11:07:51.252341 ==
8898 11:07:51.255332 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 11:07:51.261522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 11:07:51.262085 ==
8901 11:07:51.262487
8902 11:07:51.262781
8903 11:07:51.263035 TX Vref Scan disable
8904 11:07:51.265309 == TX Byte 0 ==
8905 11:07:51.268956 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8906 11:07:51.271827 == TX Byte 1 ==
8907 11:07:51.275120 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8908 11:07:51.278414 DramC Write-DBI off
8909 11:07:51.278773
8910 11:07:51.279079 [DATLAT]
8911 11:07:51.279423 Freq=1600, CH1 RK1
8912 11:07:51.279783
8913 11:07:51.281893 DATLAT Default: 0xf
8914 11:07:51.282335 0, 0xFFFF, sum = 0
8915 11:07:51.285436 1, 0xFFFF, sum = 0
8916 11:07:51.285949 2, 0xFFFF, sum = 0
8917 11:07:51.288626 3, 0xFFFF, sum = 0
8918 11:07:51.291878 4, 0xFFFF, sum = 0
8919 11:07:51.292240 5, 0xFFFF, sum = 0
8920 11:07:51.294948 6, 0xFFFF, sum = 0
8921 11:07:51.295436 7, 0xFFFF, sum = 0
8922 11:07:51.298814 8, 0xFFFF, sum = 0
8923 11:07:51.299177 9, 0xFFFF, sum = 0
8924 11:07:51.301711 10, 0xFFFF, sum = 0
8925 11:07:51.302112 11, 0xFFFF, sum = 0
8926 11:07:51.305410 12, 0xFFFF, sum = 0
8927 11:07:51.305775 13, 0xFFFF, sum = 0
8928 11:07:51.308510 14, 0x0, sum = 1
8929 11:07:51.308966 15, 0x0, sum = 2
8930 11:07:51.311927 16, 0x0, sum = 3
8931 11:07:51.312430 17, 0x0, sum = 4
8932 11:07:51.315151 best_step = 15
8933 11:07:51.315659
8934 11:07:51.316069 ==
8935 11:07:51.318650 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 11:07:51.322328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 11:07:51.322822 ==
8938 11:07:51.323257 RX Vref Scan: 0
8939 11:07:51.325123
8940 11:07:51.325549 RX Vref 0 -> 0, step: 1
8941 11:07:51.325958
8942 11:07:51.328478 RX Delay 19 -> 252, step: 4
8943 11:07:51.331838 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8944 11:07:51.338358 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8945 11:07:51.342308 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
8946 11:07:51.344989 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8947 11:07:51.348432 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8948 11:07:51.351912 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8949 11:07:51.355121 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8950 11:07:51.361630 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8951 11:07:51.364858 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8952 11:07:51.368270 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8953 11:07:51.371695 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8954 11:07:51.375645 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8955 11:07:51.381606 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8956 11:07:51.385194 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8957 11:07:51.388268 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8958 11:07:51.391745 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8959 11:07:51.392194 ==
8960 11:07:51.394921 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 11:07:51.401607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 11:07:51.401968 ==
8963 11:07:51.402306 DQS Delay:
8964 11:07:51.405036 DQS0 = 0, DQS1 = 0
8965 11:07:51.405390 DQM Delay:
8966 11:07:51.405662 DQM0 = 134, DQM1 = 130
8967 11:07:51.408278 DQ Delay:
8968 11:07:51.411509 DQ0 =138, DQ1 =132, DQ2 =124, DQ3 =130
8969 11:07:51.415208 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8970 11:07:51.418632 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8971 11:07:51.421411 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8972 11:07:51.421867
8973 11:07:51.422238
8974 11:07:51.422496
8975 11:07:51.424720 [DramC_TX_OE_Calibration] TA2
8976 11:07:51.428541 Original DQ_B0 (3 6) =30, OEN = 27
8977 11:07:51.431597 Original DQ_B1 (3 6) =30, OEN = 27
8978 11:07:51.435198 24, 0x0, End_B0=24 End_B1=24
8979 11:07:51.435602 25, 0x0, End_B0=25 End_B1=25
8980 11:07:51.438638 26, 0x0, End_B0=26 End_B1=26
8981 11:07:51.441898 27, 0x0, End_B0=27 End_B1=27
8982 11:07:51.444688 28, 0x0, End_B0=28 End_B1=28
8983 11:07:51.448586 29, 0x0, End_B0=29 End_B1=29
8984 11:07:51.448961 30, 0x0, End_B0=30 End_B1=30
8985 11:07:51.452013 31, 0x4141, End_B0=30 End_B1=30
8986 11:07:51.455102 Byte0 end_step=30 best_step=27
8987 11:07:51.458469 Byte1 end_step=30 best_step=27
8988 11:07:51.461843 Byte0 TX OE(2T, 0.5T) = (3, 3)
8989 11:07:51.465023 Byte1 TX OE(2T, 0.5T) = (3, 3)
8990 11:07:51.465380
8991 11:07:51.465652
8992 11:07:51.471687 [DQSOSCAuto] RK1, (LSB)MR18= 0x260a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
8993 11:07:51.475191 CH1 RK1: MR19=303, MR18=260A
8994 11:07:51.481662 CH1_RK1: MR19=0x303, MR18=0x260A, DQSOSC=390, MR23=63, INC=24, DEC=16
8995 11:07:51.484813 [RxdqsGatingPostProcess] freq 1600
8996 11:07:51.487959 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8997 11:07:51.491907 best DQS0 dly(2T, 0.5T) = (1, 1)
8998 11:07:51.494809 best DQS1 dly(2T, 0.5T) = (1, 1)
8999 11:07:51.498088 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9000 11:07:51.501410 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9001 11:07:51.504989 best DQS0 dly(2T, 0.5T) = (1, 1)
9002 11:07:51.507903 best DQS1 dly(2T, 0.5T) = (1, 1)
9003 11:07:51.511271 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9004 11:07:51.514638 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9005 11:07:51.517822 Pre-setting of DQS Precalculation
9006 11:07:51.521146 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9007 11:07:51.527792 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9008 11:07:51.534710 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9009 11:07:51.535389
9010 11:07:51.538234
9011 11:07:51.538608 [Calibration Summary] 3200 Mbps
9012 11:07:51.541820 CH 0, Rank 0
9013 11:07:51.542466 SW Impedance : PASS
9014 11:07:51.544997 DUTY Scan : NO K
9015 11:07:51.548624 ZQ Calibration : PASS
9016 11:07:51.549221 Jitter Meter : NO K
9017 11:07:51.551227 CBT Training : PASS
9018 11:07:51.554937 Write leveling : PASS
9019 11:07:51.555275 RX DQS gating : PASS
9020 11:07:51.558518 RX DQ/DQS(RDDQC) : PASS
9021 11:07:51.561257 TX DQ/DQS : PASS
9022 11:07:51.561729 RX DATLAT : PASS
9023 11:07:51.564438 RX DQ/DQS(Engine): PASS
9024 11:07:51.568142 TX OE : PASS
9025 11:07:51.568504 All Pass.
9026 11:07:51.568845
9027 11:07:51.569249 CH 0, Rank 1
9028 11:07:51.571282 SW Impedance : PASS
9029 11:07:51.574191 DUTY Scan : NO K
9030 11:07:51.574546 ZQ Calibration : PASS
9031 11:07:51.578299 Jitter Meter : NO K
9032 11:07:51.581456 CBT Training : PASS
9033 11:07:51.581805 Write leveling : PASS
9034 11:07:51.584607 RX DQS gating : PASS
9035 11:07:51.585099 RX DQ/DQS(RDDQC) : PASS
9036 11:07:51.587892 TX DQ/DQS : PASS
9037 11:07:51.591292 RX DATLAT : PASS
9038 11:07:51.591771 RX DQ/DQS(Engine): PASS
9039 11:07:51.594396 TX OE : PASS
9040 11:07:51.594879 All Pass.
9041 11:07:51.595173
9042 11:07:51.597780 CH 1, Rank 0
9043 11:07:51.598163 SW Impedance : PASS
9044 11:07:51.601062 DUTY Scan : NO K
9045 11:07:51.604350 ZQ Calibration : PASS
9046 11:07:51.604860 Jitter Meter : NO K
9047 11:07:51.607736 CBT Training : PASS
9048 11:07:51.610797 Write leveling : PASS
9049 11:07:51.611256 RX DQS gating : PASS
9050 11:07:51.614553 RX DQ/DQS(RDDQC) : PASS
9051 11:07:51.617680 TX DQ/DQS : PASS
9052 11:07:51.618070 RX DATLAT : PASS
9053 11:07:51.620768 RX DQ/DQS(Engine): PASS
9054 11:07:51.624436 TX OE : PASS
9055 11:07:51.624933 All Pass.
9056 11:07:51.625311
9057 11:07:51.625733 CH 1, Rank 1
9058 11:07:51.627547 SW Impedance : PASS
9059 11:07:51.631414 DUTY Scan : NO K
9060 11:07:51.631767 ZQ Calibration : PASS
9061 11:07:51.633968 Jitter Meter : NO K
9062 11:07:51.637226 CBT Training : PASS
9063 11:07:51.637576 Write leveling : PASS
9064 11:07:51.640564 RX DQS gating : PASS
9065 11:07:51.641025 RX DQ/DQS(RDDQC) : PASS
9066 11:07:51.644035 TX DQ/DQS : PASS
9067 11:07:51.647870 RX DATLAT : PASS
9068 11:07:51.648311 RX DQ/DQS(Engine): PASS
9069 11:07:51.650566 TX OE : PASS
9070 11:07:51.650919 All Pass.
9071 11:07:51.651188
9072 11:07:51.654237 DramC Write-DBI on
9073 11:07:51.657306 PER_BANK_REFRESH: Hybrid Mode
9074 11:07:51.657654 TX_TRACKING: ON
9075 11:07:51.667195 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9076 11:07:51.673841 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9077 11:07:51.684259 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9078 11:07:51.686974 [FAST_K] Save calibration result to emmc
9079 11:07:51.687365 sync common calibartion params.
9080 11:07:51.690670 sync cbt_mode0:1, 1:1
9081 11:07:51.693362 dram_init: ddr_geometry: 2
9082 11:07:51.697040 dram_init: ddr_geometry: 2
9083 11:07:51.697118 dram_init: ddr_geometry: 2
9084 11:07:51.700532 0:dram_rank_size:100000000
9085 11:07:51.703566 1:dram_rank_size:100000000
9086 11:07:51.707151 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9087 11:07:51.710383 DFS_SHUFFLE_HW_MODE: ON
9088 11:07:51.713554 dramc_set_vcore_voltage set vcore to 725000
9089 11:07:51.716684 Read voltage for 1600, 0
9090 11:07:51.716761 Vio18 = 0
9091 11:07:51.720082 Vcore = 725000
9092 11:07:51.720159 Vdram = 0
9093 11:07:51.720219 Vddq = 0
9094 11:07:51.720275 Vmddr = 0
9095 11:07:51.723287 switch to 3200 Mbps bootup
9096 11:07:51.726999 [DramcRunTimeConfig]
9097 11:07:51.727074 PHYPLL
9098 11:07:51.727133 DPM_CONTROL_AFTERK: ON
9099 11:07:51.730187 PER_BANK_REFRESH: ON
9100 11:07:51.733351 REFRESH_OVERHEAD_REDUCTION: ON
9101 11:07:51.733427 CMD_PICG_NEW_MODE: OFF
9102 11:07:51.736910 XRTWTW_NEW_MODE: ON
9103 11:07:51.740333 XRTRTR_NEW_MODE: ON
9104 11:07:51.740409 TX_TRACKING: ON
9105 11:07:51.743366 RDSEL_TRACKING: OFF
9106 11:07:51.743463 DQS Precalculation for DVFS: ON
9107 11:07:51.746886 RX_TRACKING: OFF
9108 11:07:51.746986 HW_GATING DBG: ON
9109 11:07:51.750003 ZQCS_ENABLE_LP4: ON
9110 11:07:51.750087 RX_PICG_NEW_MODE: ON
9111 11:07:51.753431 TX_PICG_NEW_MODE: ON
9112 11:07:51.756554 ENABLE_RX_DCM_DPHY: ON
9113 11:07:51.759897 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9114 11:07:51.759992 DUMMY_READ_FOR_TRACKING: OFF
9115 11:07:51.763469 !!! SPM_CONTROL_AFTERK: OFF
9116 11:07:51.766456 !!! SPM could not control APHY
9117 11:07:51.769707 IMPEDANCE_TRACKING: ON
9118 11:07:51.769859 TEMP_SENSOR: ON
9119 11:07:51.773571 HW_SAVE_FOR_SR: OFF
9120 11:07:51.773698 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9121 11:07:51.779804 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9122 11:07:51.779945 Read ODT Tracking: ON
9123 11:07:51.783502 Refresh Rate DeBounce: ON
9124 11:07:51.786709 DFS_NO_QUEUE_FLUSH: ON
9125 11:07:51.786937 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9126 11:07:51.789583 ENABLE_DFS_RUNTIME_MRW: OFF
9127 11:07:51.793563 DDR_RESERVE_NEW_MODE: ON
9128 11:07:51.796855 MR_CBT_SWITCH_FREQ: ON
9129 11:07:51.797133 =========================
9130 11:07:51.816610 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9131 11:07:51.820343 dram_init: ddr_geometry: 2
9132 11:07:51.837916 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9133 11:07:51.841476 dram_init: dram init end (result: 0)
9134 11:07:51.847872 DRAM-K: Full calibration passed in 24450 msecs
9135 11:07:51.851322 MRC: failed to locate region type 0.
9136 11:07:51.851777 DRAM rank0 size:0x100000000,
9137 11:07:51.855120 DRAM rank1 size=0x100000000
9138 11:07:51.864642 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9139 11:07:51.871137 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9140 11:07:51.877719 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9141 11:07:51.884728 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9142 11:07:51.887893 DRAM rank0 size:0x100000000,
9143 11:07:51.891317 DRAM rank1 size=0x100000000
9144 11:07:51.891669 CBMEM:
9145 11:07:51.894358 IMD: root @ 0xfffff000 254 entries.
9146 11:07:51.897988 IMD: root @ 0xffffec00 62 entries.
9147 11:07:51.901307 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9148 11:07:51.904571 WARNING: RO_VPD is uninitialized or empty.
9149 11:07:51.910864 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9150 11:07:51.918201 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9151 11:07:51.930620 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9152 11:07:51.942464 BS: romstage times (exec / console): total (unknown) / 23981 ms
9153 11:07:51.942697
9154 11:07:51.942860
9155 11:07:51.951738 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9156 11:07:51.955216 ARM64: Exception handlers installed.
9157 11:07:51.958966 ARM64: Testing exception
9158 11:07:51.961845 ARM64: Done test exception
9159 11:07:51.962069 Enumerating buses...
9160 11:07:51.965422 Show all devs... Before device enumeration.
9161 11:07:51.968695 Root Device: enabled 1
9162 11:07:51.971695 CPU_CLUSTER: 0: enabled 1
9163 11:07:51.971947 CPU: 00: enabled 1
9164 11:07:51.975383 Compare with tree...
9165 11:07:51.975675 Root Device: enabled 1
9166 11:07:51.978611 CPU_CLUSTER: 0: enabled 1
9167 11:07:51.981967 CPU: 00: enabled 1
9168 11:07:51.982215 Root Device scanning...
9169 11:07:51.985283 scan_static_bus for Root Device
9170 11:07:51.988341 CPU_CLUSTER: 0 enabled
9171 11:07:51.992280 scan_static_bus for Root Device done
9172 11:07:51.995318 scan_bus: bus Root Device finished in 8 msecs
9173 11:07:51.995565 done
9174 11:07:52.001702 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9175 11:07:52.005095 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9176 11:07:52.011581 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9177 11:07:52.015420 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9178 11:07:52.018454 Allocating resources...
9179 11:07:52.021598 Reading resources...
9180 11:07:52.025234 Root Device read_resources bus 0 link: 0
9181 11:07:52.025497 DRAM rank0 size:0x100000000,
9182 11:07:52.028617 DRAM rank1 size=0x100000000
9183 11:07:52.031676 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9184 11:07:52.035007 CPU: 00 missing read_resources
9185 11:07:52.038447 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9186 11:07:52.044855 Root Device read_resources bus 0 link: 0 done
9187 11:07:52.045172 Done reading resources.
9188 11:07:52.052082 Show resources in subtree (Root Device)...After reading.
9189 11:07:52.055332 Root Device child on link 0 CPU_CLUSTER: 0
9190 11:07:52.058661 CPU_CLUSTER: 0 child on link 0 CPU: 00
9191 11:07:52.068283 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9192 11:07:52.068557 CPU: 00
9193 11:07:52.071503 Root Device assign_resources, bus 0 link: 0
9194 11:07:52.075310 CPU_CLUSTER: 0 missing set_resources
9195 11:07:52.078426 Root Device assign_resources, bus 0 link: 0 done
9196 11:07:52.081861 Done setting resources.
9197 11:07:52.088299 Show resources in subtree (Root Device)...After assigning values.
9198 11:07:52.091342 Root Device child on link 0 CPU_CLUSTER: 0
9199 11:07:52.094955 CPU_CLUSTER: 0 child on link 0 CPU: 00
9200 11:07:52.104904 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9201 11:07:52.105181 CPU: 00
9202 11:07:52.108239 Done allocating resources.
9203 11:07:52.111723 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9204 11:07:52.115071 Enabling resources...
9205 11:07:52.115321 done.
9206 11:07:52.121113 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9207 11:07:52.121460 Initializing devices...
9208 11:07:52.124467 Root Device init
9209 11:07:52.124717 init hardware done!
9210 11:07:52.127838 0x00000018: ctrlr->caps
9211 11:07:52.131043 52.000 MHz: ctrlr->f_max
9212 11:07:52.131406 0.400 MHz: ctrlr->f_min
9213 11:07:52.134475 0x40ff8080: ctrlr->voltages
9214 11:07:52.134842 sclk: 390625
9215 11:07:52.138222 Bus Width = 1
9216 11:07:52.138514 sclk: 390625
9217 11:07:52.141605 Bus Width = 1
9218 11:07:52.141974 Early init status = 3
9219 11:07:52.147543 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9220 11:07:52.150818 in-header: 03 fc 00 00 01 00 00 00
9221 11:07:52.151089 in-data: 00
9222 11:07:52.157313 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9223 11:07:52.161082 in-header: 03 fd 00 00 00 00 00 00
9224 11:07:52.164337 in-data:
9225 11:07:52.167332 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9226 11:07:52.171174 in-header: 03 fc 00 00 01 00 00 00
9227 11:07:52.174042 in-data: 00
9228 11:07:52.177304 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9229 11:07:52.182634 in-header: 03 fd 00 00 00 00 00 00
9230 11:07:52.185767 in-data:
9231 11:07:52.188752 [SSUSB] Setting up USB HOST controller...
9232 11:07:52.192423 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9233 11:07:52.196207 [SSUSB] phy power-on done.
9234 11:07:52.199598 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9235 11:07:52.205589 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9236 11:07:52.208755 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9237 11:07:52.215506 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9238 11:07:52.222221 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9239 11:07:52.228786 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9240 11:07:52.236234 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9241 11:07:52.242327 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9242 11:07:52.245696 SPM: binary array size = 0x9dc
9243 11:07:52.248916 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9244 11:07:52.256000 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9245 11:07:52.262183 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9246 11:07:52.265536 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9247 11:07:52.272539 configure_display: Starting display init
9248 11:07:52.306065 anx7625_power_on_init: Init interface.
9249 11:07:52.309247 anx7625_disable_pd_protocol: Disabled PD feature.
9250 11:07:52.312424 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9251 11:07:52.340002 anx7625_start_dp_work: Secure OCM version=00
9252 11:07:52.343759 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9253 11:07:52.358957 sp_tx_get_edid_block: EDID Block = 1
9254 11:07:52.460642 Extracted contents:
9255 11:07:52.464027 header: 00 ff ff ff ff ff ff 00
9256 11:07:52.467742 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9257 11:07:52.471432 version: 01 04
9258 11:07:52.474365 basic params: 95 1f 11 78 0a
9259 11:07:52.477663 chroma info: 76 90 94 55 54 90 27 21 50 54
9260 11:07:52.481078 established: 00 00 00
9261 11:07:52.484483 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9262 11:07:52.490973 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9263 11:07:52.497547 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9264 11:07:52.504219 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9265 11:07:52.510520 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9266 11:07:52.514258 extensions: 00
9267 11:07:52.514685 checksum: fb
9268 11:07:52.515048
9269 11:07:52.517244 Manufacturer: IVO Model 57d Serial Number 0
9270 11:07:52.520779 Made week 0 of 2020
9271 11:07:52.521155 EDID version: 1.4
9272 11:07:52.523887 Digital display
9273 11:07:52.527589 6 bits per primary color channel
9274 11:07:52.527925 DisplayPort interface
9275 11:07:52.531082 Maximum image size: 31 cm x 17 cm
9276 11:07:52.531527 Gamma: 220%
9277 11:07:52.534115 Check DPMS levels
9278 11:07:52.537867 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9279 11:07:52.541107 First detailed timing is preferred timing
9280 11:07:52.544002 Established timings supported:
9281 11:07:52.547699 Standard timings supported:
9282 11:07:52.548028 Detailed timings
9283 11:07:52.553847 Hex of detail: 383680a07038204018303c0035ae10000019
9284 11:07:52.557760 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9285 11:07:52.560771 0780 0798 07c8 0820 hborder 0
9286 11:07:52.567245 0438 043b 0447 0458 vborder 0
9287 11:07:52.567602 -hsync -vsync
9288 11:07:52.571179 Did detailed timing
9289 11:07:52.574348 Hex of detail: 000000000000000000000000000000000000
9290 11:07:52.577427 Manufacturer-specified data, tag 0
9291 11:07:52.584375 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9292 11:07:52.584809 ASCII string: InfoVision
9293 11:07:52.591166 Hex of detail: 000000fe00523134304e574635205248200a
9294 11:07:52.591568 ASCII string: R140NWF5 RH
9295 11:07:52.594345 Checksum
9296 11:07:52.594676 Checksum: 0xfb (valid)
9297 11:07:52.600362 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9298 11:07:52.600765 DSI data_rate: 832800000 bps
9299 11:07:52.608399 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9300 11:07:52.611446 anx7625_parse_edid: pixelclock(138800).
9301 11:07:52.615139 hactive(1920), hsync(48), hfp(24), hbp(88)
9302 11:07:52.618197 vactive(1080), vsync(12), vfp(3), vbp(17)
9303 11:07:52.621932 anx7625_dsi_config: config dsi.
9304 11:07:52.628500 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9305 11:07:52.642602 anx7625_dsi_config: success to config DSI
9306 11:07:52.645938 anx7625_dp_start: MIPI phy setup OK.
9307 11:07:52.649602 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9308 11:07:52.652672 mtk_ddp_mode_set invalid vrefresh 60
9309 11:07:52.656185 main_disp_path_setup
9310 11:07:52.656336 ovl_layer_smi_id_en
9311 11:07:52.659569 ovl_layer_smi_id_en
9312 11:07:52.659722 ccorr_config
9313 11:07:52.659839 aal_config
9314 11:07:52.662622 gamma_config
9315 11:07:52.662773 postmask_config
9316 11:07:52.666406 dither_config
9317 11:07:52.669352 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9318 11:07:52.675760 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9319 11:07:52.679727 Root Device init finished in 551 msecs
9320 11:07:52.679885 CPU_CLUSTER: 0 init
9321 11:07:52.689217 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9322 11:07:52.692869 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9323 11:07:52.696068 APU_MBOX 0x190000b0 = 0x10001
9324 11:07:52.698987 APU_MBOX 0x190001b0 = 0x10001
9325 11:07:52.702503 APU_MBOX 0x190005b0 = 0x10001
9326 11:07:52.705568 APU_MBOX 0x190006b0 = 0x10001
9327 11:07:52.709219 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9328 11:07:52.721958 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9329 11:07:52.734062 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9330 11:07:52.740349 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9331 11:07:52.752602 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9332 11:07:52.761443 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9333 11:07:52.764784 CPU_CLUSTER: 0 init finished in 81 msecs
9334 11:07:52.768096 Devices initialized
9335 11:07:52.771552 Show all devs... After init.
9336 11:07:52.771641 Root Device: enabled 1
9337 11:07:52.774715 CPU_CLUSTER: 0: enabled 1
9338 11:07:52.778307 CPU: 00: enabled 1
9339 11:07:52.781308 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9340 11:07:52.784986 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9341 11:07:52.787758 ELOG: NV offset 0x57f000 size 0x1000
9342 11:07:52.794663 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9343 11:07:52.801485 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9344 11:07:52.804907 ELOG: Event(17) added with size 13 at 2024-07-10 11:07:38 UTC
9345 11:07:52.808008 out: cmd=0x121: 03 db 21 01 00 00 00 00
9346 11:07:52.811809 in-header: 03 b6 00 00 2c 00 00 00
9347 11:07:52.824891 in-data: 87 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 11:07:52.831179 ELOG: Event(A1) added with size 10 at 2024-07-10 11:07:38 UTC
9349 11:07:52.838301 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9350 11:07:52.844444 ELOG: Event(A0) added with size 9 at 2024-07-10 11:07:38 UTC
9351 11:07:52.848102 elog_add_boot_reason: Logged dev mode boot
9352 11:07:52.851483 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9353 11:07:52.855014 Finalize devices...
9354 11:07:52.855109 Devices finalized
9355 11:07:52.861331 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9356 11:07:52.864822 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9357 11:07:52.868121 in-header: 03 07 00 00 08 00 00 00
9358 11:07:52.871354 in-data: aa e4 47 04 13 02 00 00
9359 11:07:52.874760 Chrome EC: UHEPI supported
9360 11:07:52.881062 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9361 11:07:52.884466 in-header: 03 a9 00 00 08 00 00 00
9362 11:07:52.887771 in-data: 84 60 60 08 00 00 00 00
9363 11:07:52.891317 ELOG: Event(91) added with size 10 at 2024-07-10 11:07:38 UTC
9364 11:07:52.898072 Chrome EC: clear events_b mask to 0x0000000020004000
9365 11:07:52.905040 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9366 11:07:52.908412 in-header: 03 fd 00 00 00 00 00 00
9367 11:07:52.908596 in-data:
9368 11:07:52.915181 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9369 11:07:52.918971 Writing coreboot table at 0xffe64000
9370 11:07:52.922106 0. 000000000010a000-0000000000113fff: RAMSTAGE
9371 11:07:52.925093 1. 0000000040000000-00000000400fffff: RAM
9372 11:07:52.928876 2. 0000000040100000-000000004032afff: RAMSTAGE
9373 11:07:52.935055 3. 000000004032b000-00000000545fffff: RAM
9374 11:07:52.938668 4. 0000000054600000-000000005465ffff: BL31
9375 11:07:52.941777 5. 0000000054660000-00000000ffe63fff: RAM
9376 11:07:52.945846 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9377 11:07:52.952316 7. 0000000100000000-000000023fffffff: RAM
9378 11:07:52.952678 Passing 5 GPIOs to payload:
9379 11:07:52.958804 NAME | PORT | POLARITY | VALUE
9380 11:07:52.961839 EC in RW | 0x000000aa | low | undefined
9381 11:07:52.968848 EC interrupt | 0x00000005 | low | undefined
9382 11:07:52.972033 TPM interrupt | 0x000000ab | high | undefined
9383 11:07:52.975173 SD card detect | 0x00000011 | high | undefined
9384 11:07:52.981785 speaker enable | 0x00000093 | high | undefined
9385 11:07:52.985139 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9386 11:07:52.988930 in-header: 03 f9 00 00 02 00 00 00
9387 11:07:52.989291 in-data: 02 00
9388 11:07:52.991593 ADC[4]: Raw value=904726 ID=7
9389 11:07:52.994851 ADC[3]: Raw value=213072 ID=1
9390 11:07:52.995213 RAM Code: 0x71
9391 11:07:52.998572 ADC[6]: Raw value=75332 ID=0
9392 11:07:53.002280 ADC[5]: Raw value=213072 ID=1
9393 11:07:53.002640 SKU Code: 0x1
9394 11:07:53.008331 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e7ab
9395 11:07:53.012100 coreboot table: 964 bytes.
9396 11:07:53.014872 IMD ROOT 0. 0xfffff000 0x00001000
9397 11:07:53.018045 IMD SMALL 1. 0xffffe000 0x00001000
9398 11:07:53.021874 RO MCACHE 2. 0xffffc000 0x00001104
9399 11:07:53.025157 CONSOLE 3. 0xfff7c000 0x00080000
9400 11:07:53.028607 FMAP 4. 0xfff7b000 0x00000452
9401 11:07:53.031661 TIME STAMP 5. 0xfff7a000 0x00000910
9402 11:07:53.034902 VBOOT WORK 6. 0xfff66000 0x00014000
9403 11:07:53.038125 RAMOOPS 7. 0xffe66000 0x00100000
9404 11:07:53.041494 COREBOOT 8. 0xffe64000 0x00002000
9405 11:07:53.041752 IMD small region:
9406 11:07:53.044923 IMD ROOT 0. 0xffffec00 0x00000400
9407 11:07:53.048275 VPD 1. 0xffffeb80 0x0000006c
9408 11:07:53.051566 MMC STATUS 2. 0xffffeb60 0x00000004
9409 11:07:53.058635 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9410 11:07:53.064336 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9411 11:07:53.104719 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9412 11:07:53.107822 Checking segment from ROM address 0x40100000
9413 11:07:53.111020 Checking segment from ROM address 0x4010001c
9414 11:07:53.117408 Loading segment from ROM address 0x40100000
9415 11:07:53.117744 code (compression=0)
9416 11:07:53.127656 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9417 11:07:53.134290 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9418 11:07:53.134585 it's not compressed!
9419 11:07:53.141072 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9420 11:07:53.144357 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9421 11:07:53.164407 Loading segment from ROM address 0x4010001c
9422 11:07:53.164668 Entry Point 0x80000000
9423 11:07:53.168351 Loaded segments
9424 11:07:53.171465 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9425 11:07:53.177734 Jumping to boot code at 0x80000000(0xffe64000)
9426 11:07:53.185180 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9427 11:07:53.190999 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9428 11:07:53.198856 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9429 11:07:53.202182 Checking segment from ROM address 0x40100000
9430 11:07:53.205941 Checking segment from ROM address 0x4010001c
9431 11:07:53.213074 Loading segment from ROM address 0x40100000
9432 11:07:53.213334 code (compression=1)
9433 11:07:53.219303 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9434 11:07:53.228642 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9435 11:07:53.228904 using LZMA
9436 11:07:53.237784 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9437 11:07:53.244105 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9438 11:07:53.248003 Loading segment from ROM address 0x4010001c
9439 11:07:53.248261 Entry Point 0x54601000
9440 11:07:53.250508 Loaded segments
9441 11:07:53.254151 NOTICE: MT8192 bl31_setup
9442 11:07:53.261232 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9443 11:07:53.264780 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9444 11:07:53.268075 WARNING: region 0:
9445 11:07:53.271077 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 11:07:53.271345 WARNING: region 1:
9447 11:07:53.277809 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9448 11:07:53.280820 WARNING: region 2:
9449 11:07:53.284232 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9450 11:07:53.287526 WARNING: region 3:
9451 11:07:53.291320 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9452 11:07:53.294534 WARNING: region 4:
9453 11:07:53.300928 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 11:07:53.301302 WARNING: region 5:
9455 11:07:53.304196 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 11:07:53.307669 WARNING: region 6:
9457 11:07:53.311568 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 11:07:53.314601 WARNING: region 7:
9459 11:07:53.318026 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 11:07:53.324573 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9461 11:07:53.328233 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9462 11:07:53.331454 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9463 11:07:53.338301 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9464 11:07:53.341480 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9465 11:07:53.344935 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9466 11:07:53.351183 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9467 11:07:53.354567 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9468 11:07:53.361664 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9469 11:07:53.364258 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9470 11:07:53.368211 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9471 11:07:53.374379 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9472 11:07:53.377824 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9473 11:07:53.384288 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9474 11:07:53.387273 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9475 11:07:53.390934 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9476 11:07:53.397485 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9477 11:07:53.401059 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9478 11:07:53.404169 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9479 11:07:53.410713 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9480 11:07:53.414154 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9481 11:07:53.420555 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9482 11:07:53.424682 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9483 11:07:53.427851 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9484 11:07:53.434400 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9485 11:07:53.437503 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9486 11:07:53.444057 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9487 11:07:53.447591 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9488 11:07:53.451023 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9489 11:07:53.457086 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9490 11:07:53.460573 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9491 11:07:53.468152 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9492 11:07:53.470508 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9493 11:07:53.474420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9494 11:07:53.477529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9495 11:07:53.484263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9496 11:07:53.487533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9497 11:07:53.490280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9498 11:07:53.494223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9499 11:07:53.496922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9500 11:07:53.503920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9501 11:07:53.507780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9502 11:07:53.510502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9503 11:07:53.517482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9504 11:07:53.520680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9505 11:07:53.524130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9506 11:07:53.527103 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9507 11:07:53.533434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9508 11:07:53.537231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9509 11:07:53.540539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9510 11:07:53.547124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9511 11:07:53.550722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9512 11:07:53.556749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9513 11:07:53.560222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9514 11:07:53.566686 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9515 11:07:53.570133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9516 11:07:53.574268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9517 11:07:53.580593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9518 11:07:53.584233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9519 11:07:53.590702 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9520 11:07:53.593351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9521 11:07:53.601024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9522 11:07:53.603831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9523 11:07:53.610437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9524 11:07:53.613845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9525 11:07:53.616921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9526 11:07:53.623301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9527 11:07:53.626602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9528 11:07:53.634131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9529 11:07:53.636684 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9530 11:07:53.643483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9531 11:07:53.646465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9532 11:07:53.650420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9533 11:07:53.656530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9534 11:07:53.659995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9535 11:07:53.666582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9536 11:07:53.669617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9537 11:07:53.676661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9538 11:07:53.679773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9539 11:07:53.686517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9540 11:07:53.689841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9541 11:07:53.693119 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9542 11:07:53.700056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9543 11:07:53.703306 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9544 11:07:53.709683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9545 11:07:53.713371 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9546 11:07:53.716878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9547 11:07:53.723160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9548 11:07:53.727135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9549 11:07:53.733610 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9550 11:07:53.736891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9551 11:07:53.743383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9552 11:07:53.746917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9553 11:07:53.753542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9554 11:07:53.756761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9555 11:07:53.760232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9556 11:07:53.766700 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9557 11:07:53.769946 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9558 11:07:53.773321 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9559 11:07:53.776526 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9560 11:07:53.783259 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9561 11:07:53.786646 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9562 11:07:53.790118 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9563 11:07:53.796867 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9564 11:07:53.799866 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9565 11:07:53.806581 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9566 11:07:53.810227 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9567 11:07:53.816507 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9568 11:07:53.820028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9569 11:07:53.823589 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9570 11:07:53.829885 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9571 11:07:53.832911 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9572 11:07:53.840490 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9573 11:07:53.843149 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9574 11:07:53.846574 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9575 11:07:53.852635 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9576 11:07:53.856307 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9577 11:07:53.859862 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9578 11:07:53.866398 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9579 11:07:53.869511 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9580 11:07:53.872740 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9581 11:07:53.876366 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9582 11:07:53.882867 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9583 11:07:53.885809 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9584 11:07:53.889451 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9585 11:07:53.896597 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9586 11:07:53.899089 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9587 11:07:53.905547 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9588 11:07:53.909223 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9589 11:07:53.912339 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9590 11:07:53.918585 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9591 11:07:53.922445 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9592 11:07:53.929321 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9593 11:07:53.932194 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9594 11:07:53.935503 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9595 11:07:53.942343 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9596 11:07:53.945969 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9597 11:07:53.948853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9598 11:07:53.955477 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9599 11:07:53.958875 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9600 11:07:53.965674 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9601 11:07:53.969142 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9602 11:07:53.972082 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9603 11:07:53.978887 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9604 11:07:53.982157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9605 11:07:53.989089 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9606 11:07:53.991830 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9607 11:07:53.995034 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9608 11:07:54.001900 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9609 11:07:54.005127 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9610 11:07:54.012068 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9611 11:07:54.015223 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9612 11:07:54.018739 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9613 11:07:54.025467 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9614 11:07:54.028695 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9615 11:07:54.031737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9616 11:07:54.038968 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9617 11:07:54.041712 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9618 11:07:54.048647 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9619 11:07:54.051951 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9620 11:07:54.055126 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9621 11:07:54.061517 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9622 11:07:54.065494 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9623 11:07:54.071538 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9624 11:07:54.075345 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9625 11:07:54.078348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9626 11:07:54.084837 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9627 11:07:54.088932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9628 11:07:54.091726 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9629 11:07:54.099017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9630 11:07:54.101932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9631 11:07:54.108487 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9632 11:07:54.112074 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9633 11:07:54.114918 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9634 11:07:54.121906 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9635 11:07:54.125656 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9636 11:07:54.132176 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9637 11:07:54.135055 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9638 11:07:54.139109 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9639 11:07:54.145244 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9640 11:07:54.148760 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9641 11:07:54.151694 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9642 11:07:54.158839 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9643 11:07:54.161843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9644 11:07:54.169567 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9645 11:07:54.172467 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9646 11:07:54.175677 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9647 11:07:54.181904 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9648 11:07:54.185435 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9649 11:07:54.191886 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9650 11:07:54.195890 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9651 11:07:54.198702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9652 11:07:54.205244 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9653 11:07:54.208364 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9654 11:07:54.215208 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9655 11:07:54.219099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9656 11:07:54.222495 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9657 11:07:54.228719 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9658 11:07:54.231863 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9659 11:07:54.238464 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9660 11:07:54.241769 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9661 11:07:54.245964 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9662 11:07:54.251911 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9663 11:07:54.256093 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9664 11:07:54.262244 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9665 11:07:54.265487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9666 11:07:54.272180 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9667 11:07:54.275733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9668 11:07:54.278542 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9669 11:07:54.285286 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9670 11:07:54.288656 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9671 11:07:54.294854 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9672 11:07:54.298822 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9673 11:07:54.305402 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9674 11:07:54.308857 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9675 11:07:54.312137 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9676 11:07:54.318472 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9677 11:07:54.321986 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9678 11:07:54.328654 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9679 11:07:54.331890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9680 11:07:54.335305 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9681 11:07:54.341744 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9682 11:07:54.344960 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9683 11:07:54.351782 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9684 11:07:54.355023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9685 11:07:54.358429 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9686 11:07:54.364862 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9687 11:07:54.368057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9688 11:07:54.374948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9689 11:07:54.378332 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9690 11:07:54.382069 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9691 11:07:54.385003 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9692 11:07:54.392435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9693 11:07:54.395314 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9694 11:07:54.398331 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9695 11:07:54.405087 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9696 11:07:54.408008 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9697 11:07:54.411564 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9698 11:07:54.418103 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9699 11:07:54.421416 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9700 11:07:54.425393 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9701 11:07:54.432140 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9702 11:07:54.434997 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9703 11:07:54.438216 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9704 11:07:54.444815 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9705 11:07:54.447978 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9706 11:07:54.454693 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9707 11:07:54.458227 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9708 11:07:54.461626 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9709 11:07:54.467802 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9710 11:07:54.471672 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9711 11:07:54.474591 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9712 11:07:54.481547 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9713 11:07:54.484842 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9714 11:07:54.487810 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9715 11:07:54.494584 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9716 11:07:54.497990 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9717 11:07:54.505107 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9718 11:07:54.508105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9719 11:07:54.511330 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9720 11:07:54.518570 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9721 11:07:54.521528 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9722 11:07:54.524532 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9723 11:07:54.531968 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9724 11:07:54.534543 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9725 11:07:54.538268 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9726 11:07:54.544628 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9727 11:07:54.548501 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9728 11:07:54.551558 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9729 11:07:54.558219 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9730 11:07:54.561364 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9731 11:07:54.564304 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9732 11:07:54.568009 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9733 11:07:54.571010 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9734 11:07:54.578391 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9735 11:07:54.581019 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9736 11:07:54.584870 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9737 11:07:54.591469 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9738 11:07:54.594434 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9739 11:07:54.598256 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9740 11:07:54.601150 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9741 11:07:54.607502 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9742 11:07:54.610939 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9743 11:07:54.617608 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9744 11:07:54.620658 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9745 11:07:54.624432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9746 11:07:54.631126 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9747 11:07:54.634199 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9748 11:07:54.641112 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9749 11:07:54.644110 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9750 11:07:54.647943 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9751 11:07:54.654200 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9752 11:07:54.657647 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9753 11:07:54.664397 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9754 11:07:54.667520 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9755 11:07:54.670855 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9756 11:07:54.678338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9757 11:07:54.680527 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9758 11:07:54.687279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9759 11:07:54.690828 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9760 11:07:54.693955 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9761 11:07:54.701210 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9762 11:07:54.704254 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9763 11:07:54.710867 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9764 11:07:54.713964 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9765 11:07:54.717358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9766 11:07:54.723885 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9767 11:07:54.728222 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9768 11:07:54.734056 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9769 11:07:54.737219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9770 11:07:54.740503 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9771 11:07:54.747269 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9772 11:07:54.750835 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9773 11:07:54.757733 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9774 11:07:54.760838 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9775 11:07:54.763873 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9776 11:07:54.770979 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9777 11:07:54.774605 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9778 11:07:54.780596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9779 11:07:54.783993 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9780 11:07:54.790608 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9781 11:07:54.794081 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9782 11:07:54.797897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9783 11:07:54.803898 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9784 11:07:54.807061 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9785 11:07:54.813916 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9786 11:07:54.817496 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9787 11:07:54.821285 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9788 11:07:54.827242 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9789 11:07:54.830353 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9790 11:07:54.837246 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9791 11:07:54.840609 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9792 11:07:54.843965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9793 11:07:54.850493 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9794 11:07:54.854058 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9795 11:07:54.860437 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9796 11:07:54.863797 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9797 11:07:54.866993 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9798 11:07:54.873784 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9799 11:07:54.877205 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9800 11:07:54.883771 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9801 11:07:54.887204 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9802 11:07:54.890080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9803 11:07:54.897148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9804 11:07:54.900248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9805 11:07:54.906738 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9806 11:07:54.910557 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9807 11:07:54.913974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9808 11:07:54.920340 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9809 11:07:54.923372 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9810 11:07:54.930450 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9811 11:07:54.934344 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9812 11:07:54.940317 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9813 11:07:54.943589 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9814 11:07:54.946823 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9815 11:07:54.953892 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9816 11:07:54.957254 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9817 11:07:54.963786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9818 11:07:54.966916 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9819 11:07:54.970785 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9820 11:07:54.977315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9821 11:07:54.980709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9822 11:07:54.986713 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9823 11:07:54.990633 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9824 11:07:54.996765 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9825 11:07:55.000593 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9826 11:07:55.003439 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9827 11:07:55.010129 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9828 11:07:55.013479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9829 11:07:55.020059 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9830 11:07:55.023688 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9831 11:07:55.030198 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9832 11:07:55.033965 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9833 11:07:55.040603 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9834 11:07:55.043435 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9835 11:07:55.046597 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9836 11:07:55.053585 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9837 11:07:55.056734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9838 11:07:55.063227 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9839 11:07:55.066825 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9840 11:07:55.070637 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9841 11:07:55.077039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9842 11:07:55.079990 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9843 11:07:55.086779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9844 11:07:55.090158 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9845 11:07:55.096993 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9846 11:07:55.100324 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9847 11:07:55.103609 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9848 11:07:55.110063 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9849 11:07:55.113843 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9850 11:07:55.120423 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9851 11:07:55.123502 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9852 11:07:55.130334 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9853 11:07:55.133922 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9854 11:07:55.136883 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9855 11:07:55.143884 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9856 11:07:55.146750 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9857 11:07:55.154190 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9858 11:07:55.157092 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9859 11:07:55.163127 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9860 11:07:55.166507 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9861 11:07:55.169994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9862 11:07:55.176584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9863 11:07:55.180124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9864 11:07:55.186664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9865 11:07:55.190245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9866 11:07:55.197879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9867 11:07:55.200510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9868 11:07:55.206466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9869 11:07:55.209793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9870 11:07:55.216997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9871 11:07:55.219697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9872 11:07:55.226641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9873 11:07:55.229642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9874 11:07:55.232952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9875 11:07:55.239755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9876 11:07:55.243483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9877 11:07:55.249947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9878 11:07:55.252962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9879 11:07:55.260080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9880 11:07:55.262887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9881 11:07:55.269389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9882 11:07:55.272786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9883 11:07:55.279384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9884 11:07:55.283164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9885 11:07:55.289584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9886 11:07:55.292954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9887 11:07:55.299759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9888 11:07:55.302511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9889 11:07:55.310113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9890 11:07:55.312845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9891 11:07:55.319617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9892 11:07:55.322522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9893 11:07:55.329448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9894 11:07:55.332883 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9895 11:07:55.336913 INFO: [APUAPC] vio 0
9896 11:07:55.339448 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9897 11:07:55.346120 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9898 11:07:55.349376 INFO: [APUAPC] D0_APC_0: 0x400510
9899 11:07:55.349813 INFO: [APUAPC] D0_APC_1: 0x0
9900 11:07:55.352970 INFO: [APUAPC] D0_APC_2: 0x1540
9901 11:07:55.356479 INFO: [APUAPC] D0_APC_3: 0x0
9902 11:07:55.359689 INFO: [APUAPC] D1_APC_0: 0xffffffff
9903 11:07:55.362905 INFO: [APUAPC] D1_APC_1: 0xffffffff
9904 11:07:55.366553 INFO: [APUAPC] D1_APC_2: 0x3fffff
9905 11:07:55.369321 INFO: [APUAPC] D1_APC_3: 0x0
9906 11:07:55.373088 INFO: [APUAPC] D2_APC_0: 0xffffffff
9907 11:07:55.376580 INFO: [APUAPC] D2_APC_1: 0xffffffff
9908 11:07:55.379468 INFO: [APUAPC] D2_APC_2: 0x3fffff
9909 11:07:55.382923 INFO: [APUAPC] D2_APC_3: 0x0
9910 11:07:55.386168 INFO: [APUAPC] D3_APC_0: 0xffffffff
9911 11:07:55.389336 INFO: [APUAPC] D3_APC_1: 0xffffffff
9912 11:07:55.392969 INFO: [APUAPC] D3_APC_2: 0x3fffff
9913 11:07:55.396340 INFO: [APUAPC] D3_APC_3: 0x0
9914 11:07:55.399764 INFO: [APUAPC] D4_APC_0: 0xffffffff
9915 11:07:55.403050 INFO: [APUAPC] D4_APC_1: 0xffffffff
9916 11:07:55.406412 INFO: [APUAPC] D4_APC_2: 0x3fffff
9917 11:07:55.409502 INFO: [APUAPC] D4_APC_3: 0x0
9918 11:07:55.413564 INFO: [APUAPC] D5_APC_0: 0xffffffff
9919 11:07:55.416110 INFO: [APUAPC] D5_APC_1: 0xffffffff
9920 11:07:55.419329 INFO: [APUAPC] D5_APC_2: 0x3fffff
9921 11:07:55.422907 INFO: [APUAPC] D5_APC_3: 0x0
9922 11:07:55.425838 INFO: [APUAPC] D6_APC_0: 0xffffffff
9923 11:07:55.429202 INFO: [APUAPC] D6_APC_1: 0xffffffff
9924 11:07:55.432690 INFO: [APUAPC] D6_APC_2: 0x3fffff
9925 11:07:55.435979 INFO: [APUAPC] D6_APC_3: 0x0
9926 11:07:55.440195 INFO: [APUAPC] D7_APC_0: 0xffffffff
9927 11:07:55.442479 INFO: [APUAPC] D7_APC_1: 0xffffffff
9928 11:07:55.445964 INFO: [APUAPC] D7_APC_2: 0x3fffff
9929 11:07:55.449078 INFO: [APUAPC] D7_APC_3: 0x0
9930 11:07:55.453289 INFO: [APUAPC] D8_APC_0: 0xffffffff
9931 11:07:55.456487 INFO: [APUAPC] D8_APC_1: 0xffffffff
9932 11:07:55.459098 INFO: [APUAPC] D8_APC_2: 0x3fffff
9933 11:07:55.462819 INFO: [APUAPC] D8_APC_3: 0x0
9934 11:07:55.465876 INFO: [APUAPC] D9_APC_0: 0xffffffff
9935 11:07:55.469100 INFO: [APUAPC] D9_APC_1: 0xffffffff
9936 11:07:55.472698 INFO: [APUAPC] D9_APC_2: 0x3fffff
9937 11:07:55.473183 INFO: [APUAPC] D9_APC_3: 0x0
9938 11:07:55.476126 INFO: [APUAPC] D10_APC_0: 0xffffffff
9939 11:07:55.482328 INFO: [APUAPC] D10_APC_1: 0xffffffff
9940 11:07:55.485687 INFO: [APUAPC] D10_APC_2: 0x3fffff
9941 11:07:55.486205 INFO: [APUAPC] D10_APC_3: 0x0
9942 11:07:55.492652 INFO: [APUAPC] D11_APC_0: 0xffffffff
9943 11:07:55.495774 INFO: [APUAPC] D11_APC_1: 0xffffffff
9944 11:07:55.499223 INFO: [APUAPC] D11_APC_2: 0x3fffff
9945 11:07:55.499751 INFO: [APUAPC] D11_APC_3: 0x0
9946 11:07:55.505940 INFO: [APUAPC] D12_APC_0: 0xffffffff
9947 11:07:55.509239 INFO: [APUAPC] D12_APC_1: 0xffffffff
9948 11:07:55.512564 INFO: [APUAPC] D12_APC_2: 0x3fffff
9949 11:07:55.513077 INFO: [APUAPC] D12_APC_3: 0x0
9950 11:07:55.518921 INFO: [APUAPC] D13_APC_0: 0xffffffff
9951 11:07:55.522655 INFO: [APUAPC] D13_APC_1: 0xffffffff
9952 11:07:55.525855 INFO: [APUAPC] D13_APC_2: 0x3fffff
9953 11:07:55.526232 INFO: [APUAPC] D13_APC_3: 0x0
9954 11:07:55.532458 INFO: [APUAPC] D14_APC_0: 0xffffffff
9955 11:07:55.536170 INFO: [APUAPC] D14_APC_1: 0xffffffff
9956 11:07:55.539065 INFO: [APUAPC] D14_APC_2: 0x3fffff
9957 11:07:55.542206 INFO: [APUAPC] D14_APC_3: 0x0
9958 11:07:55.546192 INFO: [APUAPC] D15_APC_0: 0xffffffff
9959 11:07:55.549206 INFO: [APUAPC] D15_APC_1: 0xffffffff
9960 11:07:55.552496 INFO: [APUAPC] D15_APC_2: 0x3fffff
9961 11:07:55.555801 INFO: [APUAPC] D15_APC_3: 0x0
9962 11:07:55.556305 INFO: [APUAPC] APC_CON: 0x4
9963 11:07:55.560765 INFO: [NOCDAPC] D0_APC_0: 0x0
9964 11:07:55.563372 INFO: [NOCDAPC] D0_APC_1: 0x0
9965 11:07:55.565711 INFO: [NOCDAPC] D1_APC_0: 0x0
9966 11:07:55.568607 INFO: [NOCDAPC] D1_APC_1: 0xfff
9967 11:07:55.572845 INFO: [NOCDAPC] D2_APC_0: 0x0
9968 11:07:55.576002 INFO: [NOCDAPC] D2_APC_1: 0xfff
9969 11:07:55.578934 INFO: [NOCDAPC] D3_APC_0: 0x0
9970 11:07:55.582183 INFO: [NOCDAPC] D3_APC_1: 0xfff
9971 11:07:55.582620 INFO: [NOCDAPC] D4_APC_0: 0x0
9972 11:07:55.586078 INFO: [NOCDAPC] D4_APC_1: 0xfff
9973 11:07:55.588840 INFO: [NOCDAPC] D5_APC_0: 0x0
9974 11:07:55.592508 INFO: [NOCDAPC] D5_APC_1: 0xfff
9975 11:07:55.595398 INFO: [NOCDAPC] D6_APC_0: 0x0
9976 11:07:55.598498 INFO: [NOCDAPC] D6_APC_1: 0xfff
9977 11:07:55.602223 INFO: [NOCDAPC] D7_APC_0: 0x0
9978 11:07:55.605172 INFO: [NOCDAPC] D7_APC_1: 0xfff
9979 11:07:55.608849 INFO: [NOCDAPC] D8_APC_0: 0x0
9980 11:07:55.612071 INFO: [NOCDAPC] D8_APC_1: 0xfff
9981 11:07:55.615690 INFO: [NOCDAPC] D9_APC_0: 0x0
9982 11:07:55.618328 INFO: [NOCDAPC] D9_APC_1: 0xfff
9983 11:07:55.618761 INFO: [NOCDAPC] D10_APC_0: 0x0
9984 11:07:55.622055 INFO: [NOCDAPC] D10_APC_1: 0xfff
9985 11:07:55.625077 INFO: [NOCDAPC] D11_APC_0: 0x0
9986 11:07:55.628408 INFO: [NOCDAPC] D11_APC_1: 0xfff
9987 11:07:55.631813 INFO: [NOCDAPC] D12_APC_0: 0x0
9988 11:07:55.636026 INFO: [NOCDAPC] D12_APC_1: 0xfff
9989 11:07:55.638875 INFO: [NOCDAPC] D13_APC_0: 0x0
9990 11:07:55.642438 INFO: [NOCDAPC] D13_APC_1: 0xfff
9991 11:07:55.645407 INFO: [NOCDAPC] D14_APC_0: 0x0
9992 11:07:55.648491 INFO: [NOCDAPC] D14_APC_1: 0xfff
9993 11:07:55.651950 INFO: [NOCDAPC] D15_APC_0: 0x0
9994 11:07:55.655779 INFO: [NOCDAPC] D15_APC_1: 0xfff
9995 11:07:55.658650 INFO: [NOCDAPC] APC_CON: 0x4
9996 11:07:55.662319 INFO: [APUAPC] set_apusys_apc done
9997 11:07:55.665762 INFO: [DEVAPC] devapc_init done
9998 11:07:55.668445 INFO: GICv3 without legacy support detected.
9999 11:07:55.672287 INFO: ARM GICv3 driver initialized in EL3
10000 11:07:55.675861 INFO: Maximum SPI INTID supported: 639
10001 11:07:55.678886 INFO: BL31: Initializing runtime services
10002 11:07:55.685814 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10003 11:07:55.688427 INFO: SPM: enable CPC mode
10004 11:07:55.692314 INFO: mcdi ready for mcusys-off-idle and system suspend
10005 11:07:55.698731 INFO: BL31: Preparing for EL3 exit to normal world
10006 11:07:55.701754 INFO: Entry point address = 0x80000000
10007 11:07:55.702317 INFO: SPSR = 0x8
10008 11:07:55.709472
10009 11:07:55.709901
10010 11:07:55.710278
10011 11:07:55.712933 Starting depthcharge on Spherion...
10012 11:07:55.713361
10013 11:07:55.713691 Wipe memory regions:
10014 11:07:55.713999
10015 11:07:55.716553 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10016 11:07:55.717057 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10017 11:07:55.717446 Setting prompt string to ['asurada:']
10018 11:07:55.717792 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10019 11:07:55.718483 [0x00000040000000, 0x00000054600000)
10020 11:07:55.838182
10021 11:07:55.838681 [0x00000054660000, 0x00000080000000)
10022 11:07:56.098798
10023 11:07:56.099299 [0x000000821a7280, 0x000000ffe64000)
10024 11:07:56.844011
10025 11:07:56.844467 [0x00000100000000, 0x00000240000000)
10026 11:07:58.734100
10027 11:07:58.737445 Initializing XHCI USB controller at 0x11200000.
10028 11:07:59.775301
10029 11:07:59.778982 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10030 11:07:59.779416
10031 11:07:59.779750
10032 11:07:59.780449 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10033 11:07:59.780849 Sending line: 'tftpboot 192.168.201.1 14786851/tftp-deploy-spy6iyge/kernel/image.itb 14786851/tftp-deploy-spy6iyge/kernel/cmdline '
10035 11:07:59.882512 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10036 11:07:59.882938 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10037 11:07:59.888629 asurada: tftpboot 192.168.201.1 14786851/tftp-deploy-spy6iyge/kernel/image.ittp-deploy-spy6iyge/kernel/cmdline
10038 11:07:59.889137
10039 11:07:59.889474 Waiting for link
10040 11:08:00.045748
10041 11:08:00.046438 R8152: Initializing
10042 11:08:00.046803
10043 11:08:00.049037 Version 9 (ocp_data = 6010)
10044 11:08:00.049545
10045 11:08:00.052322 R8152: Done initializing
10046 11:08:00.052751
10047 11:08:00.053084 Adding net device
10048 11:08:01.997447
10049 11:08:01.998151 done.
10050 11:08:01.998655
10051 11:08:01.998964 MAC: 00:e0:4c:78:7a:aa
10052 11:08:01.999241
10053 11:08:02.000478 Sending DHCP discover... done.
10054 11:08:02.000906
10055 11:08:02.003771 Waiting for reply... done.
10056 11:08:02.004268
10057 11:08:02.006895 Sending DHCP request... done.
10058 11:08:02.007128
10059 11:08:02.010811 Waiting for reply... done.
10060 11:08:02.011026
10061 11:08:02.011164 My ip is 192.168.201.12
10062 11:08:02.011290
10063 11:08:02.013909 The DHCP server ip is 192.168.201.1
10064 11:08:02.014119
10065 11:08:02.020164 TFTP server IP predefined by user: 192.168.201.1
10066 11:08:02.020366
10067 11:08:02.026898 Bootfile predefined by user: 14786851/tftp-deploy-spy6iyge/kernel/image.itb
10068 11:08:02.027276
10069 11:08:02.027513 Sending tftp read request... done.
10070 11:08:02.030033
10071 11:08:02.036540 Waiting for the transfer...
10072 11:08:02.037127
10073 11:08:02.365278 00000000 ################################################################
10074 11:08:02.365400
10075 11:08:02.633701 00080000 ################################################################
10076 11:08:02.633819
10077 11:08:02.905079 00100000 ################################################################
10078 11:08:02.905204
10079 11:08:03.176039 00180000 ################################################################
10080 11:08:03.176190
10081 11:08:03.445107 00200000 ################################################################
10082 11:08:03.445233
10083 11:08:03.701230 00280000 ################################################################
10084 11:08:03.701351
10085 11:08:03.961973 00300000 ################################################################
10086 11:08:03.962122
10087 11:08:04.233943 00380000 ################################################################
10088 11:08:04.234128
10089 11:08:04.516750 00400000 ################################################################
10090 11:08:04.516875
10091 11:08:04.789902 00480000 ################################################################
10092 11:08:04.790061
10093 11:08:05.048035 00500000 ################################################################
10094 11:08:05.048156
10095 11:08:05.326848 00580000 ################################################################
10096 11:08:05.326974
10097 11:08:05.601547 00600000 ################################################################
10098 11:08:05.601665
10099 11:08:05.879422 00680000 ################################################################
10100 11:08:05.879550
10101 11:08:06.166492 00700000 ################################################################
10102 11:08:06.166619
10103 11:08:06.430168 00780000 ################################################################
10104 11:08:06.430295
10105 11:08:06.692942 00800000 ################################################################
10106 11:08:06.693067
10107 11:08:06.965150 00880000 ################################################################
10108 11:08:06.965281
10109 11:08:07.225794 00900000 ################################################################
10110 11:08:07.225921
10111 11:08:07.496001 00980000 ################################################################
10112 11:08:07.496129
10113 11:08:07.770843 00a00000 ################################################################
10114 11:08:07.770981
10115 11:08:08.029191 00a80000 ################################################################
10116 11:08:08.029334
10117 11:08:08.302379 00b00000 ################################################################
10118 11:08:08.302533
10119 11:08:08.582482 00b80000 ################################################################
10120 11:08:08.582599
10121 11:08:08.856652 00c00000 ################################################################
10122 11:08:08.856779
10123 11:08:09.114948 00c80000 ################################################################
10124 11:08:09.115075
10125 11:08:09.368319 00d00000 ################################################################
10126 11:08:09.368453
10127 11:08:09.639815 00d80000 ################################################################
10128 11:08:09.639939
10129 11:08:09.910340 00e00000 ################################################################
10130 11:08:09.910464
10131 11:08:10.196323 00e80000 ################################################################
10132 11:08:10.196450
10133 11:08:10.487355 00f00000 ################################################################
10134 11:08:10.487508
10135 11:08:10.748918 00f80000 ################################################################
10136 11:08:10.749048
10137 11:08:11.005475 01000000 ################################################################
10138 11:08:11.005609
10139 11:08:11.271890 01080000 ################################################################
10140 11:08:11.272009
10141 11:08:11.533281 01100000 ################################################################
10142 11:08:11.533450
10143 11:08:11.796826 01180000 ################################################################
10144 11:08:11.796956
10145 11:08:12.058481 01200000 ################################################################
10146 11:08:12.058592
10147 11:08:12.318089 01280000 ################################################################
10148 11:08:12.318238
10149 11:08:12.587852 01300000 ################################################################
10150 11:08:12.587999
10151 11:08:12.845753 01380000 ################################################################
10152 11:08:12.845864
10153 11:08:13.122791 01400000 ################################################################
10154 11:08:13.122906
10155 11:08:13.393191 01480000 ################################################################
10156 11:08:13.393300
10157 11:08:13.650663 01500000 ################################################################
10158 11:08:13.650776
10159 11:08:13.917409 01580000 ################################################################
10160 11:08:13.917518
10161 11:08:14.177825 01600000 ################################################################
10162 11:08:14.177953
10163 11:08:14.451078 01680000 ################################################################
10164 11:08:14.451210
10165 11:08:14.718835 01700000 ################################################################
10166 11:08:14.718950
10167 11:08:14.985758 01780000 ################################################################
10168 11:08:14.985901
10169 11:08:15.255450 01800000 ################################################################
10170 11:08:15.255559
10171 11:08:15.528731 01880000 ################################################################
10172 11:08:15.528871
10173 11:08:15.791881 01900000 ################################################################
10174 11:08:15.791994
10175 11:08:16.065858 01980000 ################################################################
10176 11:08:16.065974
10177 11:08:16.346576 01a00000 ################################################################
10178 11:08:16.346701
10179 11:08:16.618325 01a80000 ################################################################
10180 11:08:16.618437
10181 11:08:16.886163 01b00000 ################################################################
10182 11:08:16.886320
10183 11:08:17.137442 01b80000 ################################################################
10184 11:08:17.137548
10185 11:08:17.399690 01c00000 ################################################################
10186 11:08:17.399822
10187 11:08:17.665581 01c80000 ################################################################
10188 11:08:17.665691
10189 11:08:17.928551 01d00000 ################################################################
10190 11:08:17.928661
10191 11:08:18.208754 01d80000 ################################################################
10192 11:08:18.208864
10193 11:08:18.471997 01e00000 ################################################################
10194 11:08:18.472129
10195 11:08:18.729652 01e80000 ################################################################
10196 11:08:18.729761
10197 11:08:19.007772 01f00000 ################################################################
10198 11:08:19.007882
10199 11:08:19.284515 01f80000 ################################################################
10200 11:08:19.284673
10201 11:08:19.571933 02000000 ################################################################
10202 11:08:19.572074
10203 11:08:19.837113 02080000 ################################################################
10204 11:08:19.837278
10205 11:08:20.106260 02100000 ################################################################
10206 11:08:20.106375
10207 11:08:20.373861 02180000 ################################################################
10208 11:08:20.373993
10209 11:08:20.625846 02200000 ################################################################
10210 11:08:20.625960
10211 11:08:20.875214 02280000 ################################################################
10212 11:08:20.875323
10213 11:08:21.128673 02300000 ################################################################
10214 11:08:21.128783
10215 11:08:21.406965 02380000 ################################################################
10216 11:08:21.407077
10217 11:08:21.677777 02400000 ################################################################
10218 11:08:21.677887
10219 11:08:21.936379 02480000 ################################################################
10220 11:08:21.936490
10221 11:08:22.187804 02500000 ################################################################
10222 11:08:22.187915
10223 11:08:22.440096 02580000 ################################################################
10224 11:08:22.440228
10225 11:08:22.697594 02600000 ################################################################
10226 11:08:22.697741
10227 11:08:22.970869 02680000 ################################################################
10228 11:08:22.970988
10229 11:08:23.249554 02700000 ################################################################
10230 11:08:23.249677
10231 11:08:23.515497 02780000 ################################################################
10232 11:08:23.515617
10233 11:08:23.767062 02800000 ################################################################
10234 11:08:23.767177
10235 11:08:24.023886 02880000 ################################################################
10236 11:08:24.024012
10237 11:08:24.290018 02900000 ################################################################
10238 11:08:24.290142
10239 11:08:24.583244 02980000 ################################################################
10240 11:08:24.583361
10241 11:08:24.871137 02a00000 ################################################################
10242 11:08:24.871274
10243 11:08:25.155821 02a80000 ################################################################
10244 11:08:25.155944
10245 11:08:25.445331 02b00000 ################################################################
10246 11:08:25.445447
10247 11:08:25.704987 02b80000 ################################################################
10248 11:08:25.705107
10249 11:08:25.959022 02c00000 ################################################################
10250 11:08:25.959135
10251 11:08:26.222443 02c80000 ################################################################
10252 11:08:26.222563
10253 11:08:26.510787 02d00000 ################################################################
10254 11:08:26.510906
10255 11:08:26.807089 02d80000 ################################################################
10256 11:08:26.807229
10257 11:08:27.101958 02e00000 ################################################################
10258 11:08:27.102091
10259 11:08:27.381478 02e80000 ################################################################
10260 11:08:27.381600
10261 11:08:27.657152 02f00000 ################################################################
10262 11:08:27.657275
10263 11:08:27.928102 02f80000 ################################################################
10264 11:08:27.928211
10265 11:08:28.222648 03000000 ################################################################
10266 11:08:28.222773
10267 11:08:28.509460 03080000 ################################################################
10268 11:08:28.509575
10269 11:08:28.801015 03100000 ################################################################
10270 11:08:28.801129
10271 11:08:29.083637 03180000 ################################################################
10272 11:08:29.083755
10273 11:08:29.374133 03200000 ################################################################
10274 11:08:29.374309
10275 11:08:29.659875 03280000 ################################################################
10276 11:08:29.660004
10277 11:08:29.950537 03300000 ################################################################
10278 11:08:29.950680
10279 11:08:30.140501 03380000 ########################################### done.
10280 11:08:30.140618
10281 11:08:30.144204 The bootfile was 54347370 bytes long.
10282 11:08:30.144352
10283 11:08:30.147830 Sending tftp read request... done.
10284 11:08:30.147969
10285 11:08:30.150476 Waiting for the transfer...
10286 11:08:30.150585
10287 11:08:30.150651 00000000 # done.
10288 11:08:30.150714
10289 11:08:30.160861 Command line loaded dynamically from TFTP file: 14786851/tftp-deploy-spy6iyge/kernel/cmdline
10290 11:08:30.161080
10291 11:08:30.174306 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10292 11:08:30.174486
10293 11:08:30.174581 Loading FIT.
10294 11:08:30.174669
10295 11:08:30.177793 Image ramdisk-1 has 41181828 bytes.
10296 11:08:30.177990
10297 11:08:30.181020 Image fdt-1 has 47258 bytes.
10298 11:08:30.181244
10299 11:08:30.184212 Image kernel-1 has 13116259 bytes.
10300 11:08:30.184431
10301 11:08:30.190803 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10302 11:08:30.191055
10303 11:08:30.211335 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10304 11:08:30.211844
10305 11:08:30.213985 Choosing best match conf-1 for compat google,spherion-rev2.
10306 11:08:30.219090
10307 11:08:30.223682 Connected to device vid:did:rid of 1ae0:0028:00
10308 11:08:30.232004
10309 11:08:30.235175 tpm_get_response: command 0x17b, return code 0x0
10310 11:08:30.235558
10311 11:08:30.238372 ec_init: CrosEC protocol v3 supported (256, 248)
10312 11:08:30.242822
10313 11:08:30.246507 tpm_cleanup: add release locality here.
10314 11:08:30.246913
10315 11:08:30.247239 Shutting down all USB controllers.
10316 11:08:30.247513
10317 11:08:30.249319 Removing current net device
10318 11:08:30.249691
10319 11:08:30.255741 Exiting depthcharge with code 4 at timestamp: 63812596
10320 11:08:30.256117
10321 11:08:30.259094 LZMA decompressing kernel-1 to 0x821a6718
10322 11:08:30.259473
10323 11:08:30.262238 LZMA decompressing kernel-1 to 0x40000000
10324 11:08:31.878508
10325 11:08:31.879114 jumping to kernel
10326 11:08:31.881317 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10327 11:08:31.881802 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10328 11:08:31.882218 Setting prompt string to ['Linux version [0-9]']
10329 11:08:31.882555 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10330 11:08:31.882916 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10331 11:08:31.959191
10332 11:08:31.962464 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10333 11:08:31.965703 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10334 11:08:31.966194 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10335 11:08:31.966563 Setting prompt string to []
10336 11:08:31.966952 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10337 11:08:31.967292 Using line separator: #'\n'#
10338 11:08:31.967587 No login prompt set.
10339 11:08:31.967913 Parsing kernel messages
10340 11:08:31.968199 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10341 11:08:31.968805 [login-action] Waiting for messages, (timeout 00:03:44)
10342 11:08:31.969159 Waiting using forced prompt support (timeout 00:01:52)
10343 11:08:31.985148 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10344 11:08:31.988727 [ 0.000000] random: crng init done
10345 11:08:31.992253 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10346 11:08:31.995280 [ 0.000000] efi: UEFI not found.
10347 11:08:32.005695 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10348 11:08:32.011714 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10349 11:08:32.021814 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10350 11:08:32.031797 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10351 11:08:32.038333 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10352 11:08:32.041911 [ 0.000000] printk: bootconsole [mtk8250] enabled
10353 11:08:32.049932 [ 0.000000] NUMA: No NUMA configuration found
10354 11:08:32.056794 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10355 11:08:32.063556 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10356 11:08:32.064063 [ 0.000000] Zone ranges:
10357 11:08:32.069920 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10358 11:08:32.073323 [ 0.000000] DMA32 empty
10359 11:08:32.079816 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10360 11:08:32.083478 [ 0.000000] Movable zone start for each node
10361 11:08:32.086486 [ 0.000000] Early memory node ranges
10362 11:08:32.093010 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10363 11:08:32.099680 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10364 11:08:32.106744 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10365 11:08:32.112966 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10366 11:08:32.119931 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10367 11:08:32.126165 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10368 11:08:32.182861 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10369 11:08:32.189919 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10370 11:08:32.196716 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10371 11:08:32.199927 [ 0.000000] psci: probing for conduit method from DT.
10372 11:08:32.206508 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10373 11:08:32.210166 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10374 11:08:32.216498 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10375 11:08:32.219494 [ 0.000000] psci: SMC Calling Convention v1.2
10376 11:08:32.226371 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10377 11:08:32.229703 [ 0.000000] Detected VIPT I-cache on CPU0
10378 11:08:32.236067 [ 0.000000] CPU features: detected: GIC system register CPU interface
10379 11:08:32.242602 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10380 11:08:32.249792 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10381 11:08:32.256088 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10382 11:08:32.262818 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10383 11:08:32.270003 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10384 11:08:32.276647 [ 0.000000] alternatives: applying boot alternatives
10385 11:08:32.280141 [ 0.000000] Fallback order for Node 0: 0
10386 11:08:32.289573 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10387 11:08:32.290001 [ 0.000000] Policy zone: Normal
10388 11:08:32.306529 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10389 11:08:32.316186 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10390 11:08:32.326583 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10391 11:08:32.336181 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10392 11:08:32.342813 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10393 11:08:32.346518 <6>[ 0.000000] software IO TLB: area num 8.
10394 11:08:32.403703 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10395 11:08:32.552774 <6>[ 0.000000] Memory: 7923840K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 428928K reserved, 32768K cma-reserved)
10396 11:08:32.559325 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10397 11:08:32.565903 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10398 11:08:32.569231 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10399 11:08:32.576091 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10400 11:08:32.582992 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10401 11:08:32.585575 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10402 11:08:32.595806 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10403 11:08:32.602486 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10404 11:08:32.605904 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10405 11:08:32.613878 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10406 11:08:32.617826 <6>[ 0.000000] GICv3: 608 SPIs implemented
10407 11:08:32.624163 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10408 11:08:32.626859 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10409 11:08:32.629984 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10410 11:08:32.640246 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10411 11:08:32.650616 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10412 11:08:32.663685 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10413 11:08:32.670158 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10414 11:08:32.679074 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10415 11:08:32.693352 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10416 11:08:32.698595 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10417 11:08:32.706041 <6>[ 0.009228] Console: colour dummy device 80x25
10418 11:08:32.715504 <6>[ 0.013988] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10419 11:08:32.722323 <6>[ 0.024430] pid_max: default: 32768 minimum: 301
10420 11:08:32.725644 <6>[ 0.029304] LSM: Security Framework initializing
10421 11:08:32.732790 <6>[ 0.034273] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 11:08:32.742440 <6>[ 0.042085] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 11:08:32.749409 <6>[ 0.051505] cblist_init_generic: Setting adjustable number of callback queues.
10424 11:08:32.755514 <6>[ 0.058992] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 11:08:32.765704 <6>[ 0.065370] cblist_init_generic: Setting adjustable number of callback queues.
10426 11:08:32.768897 <6>[ 0.072796] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 11:08:32.776315 <6>[ 0.079197] rcu: Hierarchical SRCU implementation.
10428 11:08:32.782799 <6>[ 0.084212] rcu: Max phase no-delay instances is 1000.
10429 11:08:32.789296 <6>[ 0.091230] EFI services will not be available.
10430 11:08:32.792542 <6>[ 0.096188] smp: Bringing up secondary CPUs ...
10431 11:08:32.800350 <6>[ 0.101238] Detected VIPT I-cache on CPU1
10432 11:08:32.806450 <6>[ 0.101310] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10433 11:08:32.813152 <6>[ 0.101339] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10434 11:08:32.816581 <6>[ 0.101685] Detected VIPT I-cache on CPU2
10435 11:08:32.823008 <6>[ 0.101742] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10436 11:08:32.829551 <6>[ 0.101759] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10437 11:08:32.836935 <6>[ 0.102024] Detected VIPT I-cache on CPU3
10438 11:08:32.843158 <6>[ 0.102072] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10439 11:08:32.849609 <6>[ 0.102087] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10440 11:08:32.853347 <6>[ 0.102393] CPU features: detected: Spectre-v4
10441 11:08:32.859805 <6>[ 0.102399] CPU features: detected: Spectre-BHB
10442 11:08:32.863461 <6>[ 0.102404] Detected PIPT I-cache on CPU4
10443 11:08:32.869513 <6>[ 0.102465] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10444 11:08:32.876429 <6>[ 0.102482] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10445 11:08:32.883547 <6>[ 0.102775] Detected PIPT I-cache on CPU5
10446 11:08:32.889982 <6>[ 0.102838] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10447 11:08:32.896443 <6>[ 0.102854] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10448 11:08:32.899349 <6>[ 0.103136] Detected PIPT I-cache on CPU6
10449 11:08:32.906564 <6>[ 0.103202] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10450 11:08:32.912799 <6>[ 0.103217] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10451 11:08:32.919628 <6>[ 0.103515] Detected PIPT I-cache on CPU7
10452 11:08:32.926366 <6>[ 0.103579] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10453 11:08:32.932849 <6>[ 0.103595] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10454 11:08:32.935966 <6>[ 0.103642] smp: Brought up 1 node, 8 CPUs
10455 11:08:32.939731 <6>[ 0.244900] SMP: Total of 8 processors activated.
10456 11:08:32.945832 <6>[ 0.249821] CPU features: detected: 32-bit EL0 Support
10457 11:08:32.955824 <6>[ 0.255183] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10458 11:08:32.962462 <6>[ 0.264039] CPU features: detected: Common not Private translations
10459 11:08:32.965962 <6>[ 0.270515] CPU features: detected: CRC32 instructions
10460 11:08:32.972888 <6>[ 0.275900] CPU features: detected: RCpc load-acquire (LDAPR)
10461 11:08:32.979638 <6>[ 0.281860] CPU features: detected: LSE atomic instructions
10462 11:08:32.985895 <6>[ 0.287641] CPU features: detected: Privileged Access Never
10463 11:08:32.989392 <6>[ 0.293421] CPU features: detected: RAS Extension Support
10464 11:08:32.999444 <6>[ 0.299030] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10465 11:08:33.002310 <6>[ 0.306252] CPU: All CPU(s) started at EL2
10466 11:08:33.008807 <6>[ 0.310568] alternatives: applying system-wide alternatives
10467 11:08:33.017594 <6>[ 0.321450] devtmpfs: initialized
10468 11:08:33.033358 <6>[ 0.330104] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10469 11:08:33.039585 <6>[ 0.340062] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10470 11:08:33.046650 <6>[ 0.348313] pinctrl core: initialized pinctrl subsystem
10471 11:08:33.050269 <6>[ 0.354984] DMI not present or invalid.
10472 11:08:33.056099 <6>[ 0.359402] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10473 11:08:33.065923 <6>[ 0.366285] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10474 11:08:33.072791 <6>[ 0.373874] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10475 11:08:33.082509 <6>[ 0.382103] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10476 11:08:33.086165 <6>[ 0.390350] audit: initializing netlink subsys (disabled)
10477 11:08:33.096486 <5>[ 0.396047] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10478 11:08:33.102471 <6>[ 0.396776] thermal_sys: Registered thermal governor 'step_wise'
10479 11:08:33.109153 <6>[ 0.404012] thermal_sys: Registered thermal governor 'power_allocator'
10480 11:08:33.112799 <6>[ 0.410264] cpuidle: using governor menu
10481 11:08:33.118904 <6>[ 0.421223] NET: Registered PF_QIPCRTR protocol family
10482 11:08:33.125622 <6>[ 0.426719] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10483 11:08:33.132584 <6>[ 0.433823] ASID allocator initialised with 32768 entries
10484 11:08:33.135618 <6>[ 0.440400] Serial: AMBA PL011 UART driver
10485 11:08:33.145923 <4>[ 0.449753] Trying to register duplicate clock ID: 134
10486 11:08:33.203895 <6>[ 0.511006] KASLR enabled
10487 11:08:33.218800 <6>[ 0.518670] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10488 11:08:33.224992 <6>[ 0.525683] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10489 11:08:33.231866 <6>[ 0.532170] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10490 11:08:33.238094 <6>[ 0.539174] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10491 11:08:33.244698 <6>[ 0.545660] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10492 11:08:33.251655 <6>[ 0.552663] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10493 11:08:33.257988 <6>[ 0.559148] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10494 11:08:33.264494 <6>[ 0.566150] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10495 11:08:33.268195 <6>[ 0.573680] ACPI: Interpreter disabled.
10496 11:08:33.276239 <6>[ 0.580114] iommu: Default domain type: Translated
10497 11:08:33.283344 <6>[ 0.585227] iommu: DMA domain TLB invalidation policy: strict mode
10498 11:08:33.286453 <5>[ 0.591876] SCSI subsystem initialized
10499 11:08:33.293289 <6>[ 0.596034] usbcore: registered new interface driver usbfs
10500 11:08:33.299853 <6>[ 0.601765] usbcore: registered new interface driver hub
10501 11:08:33.303223 <6>[ 0.607319] usbcore: registered new device driver usb
10502 11:08:33.310065 <6>[ 0.613425] pps_core: LinuxPPS API ver. 1 registered
10503 11:08:33.319502 <6>[ 0.618619] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10504 11:08:33.323139 <6>[ 0.627964] PTP clock support registered
10505 11:08:33.326161 <6>[ 0.632205] EDAC MC: Ver: 3.0.0
10506 11:08:33.334099 <6>[ 0.637367] FPGA manager framework
10507 11:08:33.340358 <6>[ 0.641053] Advanced Linux Sound Architecture Driver Initialized.
10508 11:08:33.343564 <6>[ 0.647846] vgaarb: loaded
10509 11:08:33.349801 <6>[ 0.651007] clocksource: Switched to clocksource arch_sys_counter
10510 11:08:33.353773 <5>[ 0.657454] VFS: Disk quotas dquot_6.6.0
10511 11:08:33.359858 <6>[ 0.661638] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10512 11:08:33.363357 <6>[ 0.668827] pnp: PnP ACPI: disabled
10513 11:08:33.372209 <6>[ 0.675536] NET: Registered PF_INET protocol family
10514 11:08:33.381870 <6>[ 0.681128] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10515 11:08:33.393159 <6>[ 0.693434] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10516 11:08:33.402683 <6>[ 0.702247] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10517 11:08:33.409357 <6>[ 0.710218] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10518 11:08:33.415892 <6>[ 0.718920] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10519 11:08:33.428089 <6>[ 0.728676] TCP: Hash tables configured (established 65536 bind 65536)
10520 11:08:33.434706 <6>[ 0.735545] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 11:08:33.441884 <6>[ 0.742742] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 11:08:33.448013 <6>[ 0.750439] NET: Registered PF_UNIX/PF_LOCAL protocol family
10523 11:08:33.454983 <6>[ 0.756603] RPC: Registered named UNIX socket transport module.
10524 11:08:33.458038 <6>[ 0.762752] RPC: Registered udp transport module.
10525 11:08:33.464781 <6>[ 0.767683] RPC: Registered tcp transport module.
10526 11:08:33.471173 <6>[ 0.772612] RPC: Registered tcp NFSv4.1 backchannel transport module.
10527 11:08:33.474871 <6>[ 0.779276] PCI: CLS 0 bytes, default 64
10528 11:08:33.478065 <6>[ 0.783599] Unpacking initramfs...
10529 11:08:33.494996 <6>[ 0.795529] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10530 11:08:33.505223 <6>[ 0.804173] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10531 11:08:33.508006 <6>[ 0.813015] kvm [1]: IPA Size Limit: 40 bits
10532 11:08:33.514842 <6>[ 0.817543] kvm [1]: GICv3: no GICV resource entry
10533 11:08:33.518482 <6>[ 0.822563] kvm [1]: disabling GICv2 emulation
10534 11:08:33.525097 <6>[ 0.827251] kvm [1]: GIC system register CPU interface enabled
10535 11:08:33.528155 <6>[ 0.833412] kvm [1]: vgic interrupt IRQ18
10536 11:08:33.534838 <6>[ 0.837768] kvm [1]: VHE mode initialized successfully
10537 11:08:33.541423 <5>[ 0.844295] Initialise system trusted keyrings
10538 11:08:33.547638 <6>[ 0.849098] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10539 11:08:33.555103 <6>[ 0.859043] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10540 11:08:33.561979 <5>[ 0.865440] NFS: Registering the id_resolver key type
10541 11:08:33.565308 <5>[ 0.870740] Key type id_resolver registered
10542 11:08:33.571746 <5>[ 0.875157] Key type id_legacy registered
10543 11:08:33.578517 <6>[ 0.879434] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10544 11:08:33.585223 <6>[ 0.886356] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10545 11:08:33.591775 <6>[ 0.894071] 9p: Installing v9fs 9p2000 file system support
10546 11:08:33.628164 <5>[ 0.931758] Key type asymmetric registered
10547 11:08:33.631106 <5>[ 0.936089] Asymmetric key parser 'x509' registered
10548 11:08:33.641390 <6>[ 0.941252] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10549 11:08:33.644511 <6>[ 0.948869] io scheduler mq-deadline registered
10550 11:08:33.647833 <6>[ 0.953644] io scheduler kyber registered
10551 11:08:33.667135 <6>[ 0.970840] EINJ: ACPI disabled.
10552 11:08:33.700093 <4>[ 0.997088] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 11:08:33.710283 <4>[ 1.007722] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 11:08:33.725177 <6>[ 1.028643] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10555 11:08:33.732463 <6>[ 1.036635] printk: console [ttyS0] disabled
10556 11:08:33.760589 <6>[ 1.061267] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10557 11:08:33.767909 <6>[ 1.070756] printk: console [ttyS0] enabled
10558 11:08:33.770577 <6>[ 1.070756] printk: console [ttyS0] enabled
10559 11:08:33.778146 <6>[ 1.079651] printk: bootconsole [mtk8250] disabled
10560 11:08:33.780776 <6>[ 1.079651] printk: bootconsole [mtk8250] disabled
10561 11:08:33.787422 <6>[ 1.091024] SuperH (H)SCI(F) driver initialized
10562 11:08:33.790426 <6>[ 1.096318] msm_serial: driver initialized
10563 11:08:33.805384 <6>[ 1.105270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10564 11:08:33.814928 <6>[ 1.113817] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10565 11:08:33.821406 <6>[ 1.122360] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10566 11:08:33.831450 <6>[ 1.130987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10567 11:08:33.838347 <6>[ 1.139694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10568 11:08:33.847823 <6>[ 1.148419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10569 11:08:33.858597 <6>[ 1.156967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10570 11:08:33.865066 <6>[ 1.165771] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10571 11:08:33.874900 <6>[ 1.174316] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10572 11:08:33.886915 <6>[ 1.190128] loop: module loaded
10573 11:08:33.893103 <6>[ 1.196069] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10574 11:08:33.914899 <4>[ 1.218918] mtk-pmic-keys: Failed to locate of_node [id: -1]
10575 11:08:33.922114 <6>[ 1.225941] megasas: 07.719.03.00-rc1
10576 11:08:33.931872 <6>[ 1.235664] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10577 11:08:33.942535 <6>[ 1.246399] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10578 11:08:33.960130 <6>[ 1.263265] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10579 11:08:34.016077 <6>[ 1.313749] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10580 11:08:35.221719 <6>[ 2.525398] Freeing initrd memory: 40216K
10581 11:08:35.233118 <6>[ 2.537137] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10582 11:08:35.244304 <6>[ 2.548095] tun: Universal TUN/TAP device driver, 1.6
10583 11:08:35.247447 <6>[ 2.554154] thunder_xcv, ver 1.0
10584 11:08:35.250564 <6>[ 2.557657] thunder_bgx, ver 1.0
10585 11:08:35.254470 <6>[ 2.561153] nicpf, ver 1.0
10586 11:08:35.264824 <6>[ 2.565172] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10587 11:08:35.268174 <6>[ 2.572648] hns3: Copyright (c) 2017 Huawei Corporation.
10588 11:08:35.271417 <6>[ 2.578235] hclge is initializing
10589 11:08:35.277501 <6>[ 2.581814] e1000: Intel(R) PRO/1000 Network Driver
10590 11:08:35.284682 <6>[ 2.586943] e1000: Copyright (c) 1999-2006 Intel Corporation.
10591 11:08:35.287863 <6>[ 2.592956] e1000e: Intel(R) PRO/1000 Network Driver
10592 11:08:35.294536 <6>[ 2.598172] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10593 11:08:35.301189 <6>[ 2.604360] igb: Intel(R) Gigabit Ethernet Network Driver
10594 11:08:35.307694 <6>[ 2.610010] igb: Copyright (c) 2007-2014 Intel Corporation.
10595 11:08:35.314901 <6>[ 2.615846] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10596 11:08:35.321167 <6>[ 2.622364] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10597 11:08:35.324721 <6>[ 2.628824] sky2: driver version 1.30
10598 11:08:35.330822 <6>[ 2.633765] usbcore: registered new device driver r8152-cfgselector
10599 11:08:35.337149 <6>[ 2.640301] usbcore: registered new interface driver r8152
10600 11:08:35.344843 <6>[ 2.646122] VFIO - User Level meta-driver version: 0.3
10601 11:08:35.350962 <6>[ 2.654369] usbcore: registered new interface driver usb-storage
10602 11:08:35.357397 <6>[ 2.660817] usbcore: registered new device driver onboard-usb-hub
10603 11:08:35.366167 <6>[ 2.669989] mt6397-rtc mt6359-rtc: registered as rtc0
10604 11:08:35.375885 <6>[ 2.675454] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:08:21 UTC (1720609701)
10605 11:08:35.379416 <6>[ 2.685023] i2c_dev: i2c /dev entries driver
10606 11:08:35.393398 <4>[ 2.697164] cpu cpu0: supply cpu not found, using dummy regulator
10607 11:08:35.400060 <4>[ 2.703587] cpu cpu1: supply cpu not found, using dummy regulator
10608 11:08:35.406832 <4>[ 2.709984] cpu cpu2: supply cpu not found, using dummy regulator
10609 11:08:35.413568 <4>[ 2.716402] cpu cpu3: supply cpu not found, using dummy regulator
10610 11:08:35.419832 <4>[ 2.722799] cpu cpu4: supply cpu not found, using dummy regulator
10611 11:08:35.426454 <4>[ 2.729205] cpu cpu5: supply cpu not found, using dummy regulator
10612 11:08:35.432576 <4>[ 2.735601] cpu cpu6: supply cpu not found, using dummy regulator
10613 11:08:35.439486 <4>[ 2.741993] cpu cpu7: supply cpu not found, using dummy regulator
10614 11:08:35.459954 <6>[ 2.763652] cpu cpu0: EM: created perf domain
10615 11:08:35.462819 <6>[ 2.768599] cpu cpu4: EM: created perf domain
10616 11:08:35.470322 <6>[ 2.774244] sdhci: Secure Digital Host Controller Interface driver
10617 11:08:35.476781 <6>[ 2.780678] sdhci: Copyright(c) Pierre Ossman
10618 11:08:35.483935 <6>[ 2.785632] Synopsys Designware Multimedia Card Interface Driver
10619 11:08:35.489851 <6>[ 2.792270] sdhci-pltfm: SDHCI platform and OF driver helper
10620 11:08:35.493887 <6>[ 2.792342] mmc0: CQHCI version 5.10
10621 11:08:35.500712 <6>[ 2.802260] ledtrig-cpu: registered to indicate activity on CPUs
10622 11:08:35.506909 <6>[ 2.809252] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10623 11:08:35.513407 <6>[ 2.816304] usbcore: registered new interface driver usbhid
10624 11:08:35.517180 <6>[ 2.822126] usbhid: USB HID core driver
10625 11:08:35.523056 <6>[ 2.826322] spi_master spi0: will run message pump with realtime priority
10626 11:08:35.568617 <6>[ 2.866220] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10627 11:08:35.588153 <6>[ 2.882095] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10628 11:08:35.591390 <6>[ 2.892434] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10629 11:08:35.599203 <6>[ 2.902923] cros-ec-spi spi0.0: Chrome EC device registered
10630 11:08:35.606245 <6>[ 2.909000] mmc0: Command Queue Engine enabled
10631 11:08:35.612505 <6>[ 2.913763] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10632 11:08:35.616108 <6>[ 2.921349] mmcblk0: mmc0:0001 DA4128 116 GiB
10633 11:08:35.626989 <6>[ 2.930508] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10634 11:08:35.634328 <6>[ 2.938054] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10635 11:08:35.640842 <6>[ 2.944175] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10636 11:08:35.650675 <6>[ 2.948034] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10637 11:08:35.657323 <6>[ 2.950307] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10638 11:08:35.660710 <6>[ 2.959748] NET: Registered PF_PACKET protocol family
10639 11:08:35.667410 <6>[ 2.970646] 9pnet: Installing 9P2000 support
10640 11:08:35.670625 <5>[ 2.975224] Key type dns_resolver registered
10641 11:08:35.677241 <6>[ 2.980332] registered taskstats version 1
10642 11:08:35.680211 <5>[ 2.984721] Loading compiled-in X.509 certificates
10643 11:08:35.709968 <4>[ 3.007264] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 11:08:35.719389 <4>[ 3.018031] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 11:08:35.734135 <6>[ 3.038621] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10646 11:08:35.740829 <6>[ 3.045444] xhci-mtk 11200000.usb: xHCI Host Controller
10647 11:08:35.747844 <6>[ 3.050952] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10648 11:08:35.757564 <6>[ 3.058805] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10649 11:08:35.764187 <6>[ 3.068240] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10650 11:08:35.770621 <6>[ 3.074420] xhci-mtk 11200000.usb: xHCI Host Controller
10651 11:08:35.777846 <6>[ 3.079916] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10652 11:08:35.784294 <6>[ 3.087571] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10653 11:08:35.791026 <6>[ 3.095303] hub 1-0:1.0: USB hub found
10654 11:08:35.794313 <6>[ 3.099324] hub 1-0:1.0: 1 port detected
10655 11:08:35.804009 <6>[ 3.103604] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10656 11:08:35.807770 <6>[ 3.112266] hub 2-0:1.0: USB hub found
10657 11:08:35.810631 <6>[ 3.116285] hub 2-0:1.0: 1 port detected
10658 11:08:35.819301 <6>[ 3.123391] mtk-msdc 11f70000.mmc: Got CD GPIO
10659 11:08:35.831889 <6>[ 3.132622] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10660 11:08:35.838899 <6>[ 3.141014] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10661 11:08:35.848880 <6>[ 3.149355] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10662 11:08:35.858829 <6>[ 3.157700] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10663 11:08:35.865255 <6>[ 3.166039] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10664 11:08:35.875648 <6>[ 3.174379] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10665 11:08:35.881938 <6>[ 3.182717] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10666 11:08:35.892238 <6>[ 3.191057] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10667 11:08:35.898496 <6>[ 3.199395] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10668 11:08:35.908324 <6>[ 3.207734] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10669 11:08:35.915424 <6>[ 3.216074] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10670 11:08:35.925507 <6>[ 3.224422] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10671 11:08:35.931638 <6>[ 3.232762] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10672 11:08:35.941465 <6>[ 3.241100] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10673 11:08:35.948183 <6>[ 3.249445] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10674 11:08:35.954790 <6>[ 3.258142] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10675 11:08:35.961445 <6>[ 3.265312] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10676 11:08:35.968376 <6>[ 3.272073] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10677 11:08:35.975368 <6>[ 3.278873] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10678 11:08:35.985335 <6>[ 3.285811] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10679 11:08:35.991882 <6>[ 3.292679] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10680 11:08:36.002111 <6>[ 3.301817] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10681 11:08:36.011465 <6>[ 3.310937] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10682 11:08:36.021736 <6>[ 3.320232] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10683 11:08:36.031997 <6>[ 3.329702] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10684 11:08:36.038178 <6>[ 3.339171] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10685 11:08:36.048204 <6>[ 3.348291] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10686 11:08:36.058212 <6>[ 3.357759] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10687 11:08:36.068356 <6>[ 3.366879] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10688 11:08:36.077973 <6>[ 3.376191] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10689 11:08:36.087756 <6>[ 3.386352] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10690 11:08:36.097602 <6>[ 3.397887] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 11:08:36.226701 <6>[ 3.527304] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10692 11:08:36.381691 <6>[ 3.685381] hub 1-1:1.0: USB hub found
10693 11:08:36.385027 <6>[ 3.689892] hub 1-1:1.0: 4 ports detected
10694 11:08:36.395774 <6>[ 3.699671] hub 1-1:1.0: USB hub found
10695 11:08:36.398756 <6>[ 3.703996] hub 1-1:1.0: 4 ports detected
10696 11:08:36.507532 <6>[ 3.807635] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10697 11:08:36.534404 <6>[ 3.838276] hub 2-1:1.0: USB hub found
10698 11:08:36.537384 <6>[ 3.842842] hub 2-1:1.0: 3 ports detected
10699 11:08:36.550600 <6>[ 3.854682] hub 2-1:1.0: USB hub found
10700 11:08:36.553657 <6>[ 3.859214] hub 2-1:1.0: 3 ports detected
10701 11:08:36.718956 <6>[ 4.019325] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10702 11:08:36.851358 <6>[ 4.155117] hub 1-1.4:1.0: USB hub found
10703 11:08:36.854164 <6>[ 4.159778] hub 1-1.4:1.0: 2 ports detected
10704 11:08:36.867367 <6>[ 4.171475] hub 1-1.4:1.0: USB hub found
10705 11:08:36.870849 <6>[ 4.176089] hub 1-1.4:1.0: 2 ports detected
10706 11:08:36.930713 <6>[ 4.231528] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10707 11:08:37.039144 <6>[ 4.339965] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10708 11:08:37.075194 <4>[ 4.375916] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10709 11:08:37.084838 <4>[ 4.385068] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10710 11:08:37.128643 <6>[ 4.432915] r8152 2-1.3:1.0 eth0: v1.12.13
10711 11:08:37.166068 <6>[ 4.467169] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10712 11:08:37.362455 <6>[ 4.663375] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10713 11:08:38.899122 <6>[ 6.203854] r8152 2-1.3:1.0 eth0: carrier on
10714 11:08:41.382918 <5>[ 6.231124] Sending DHCP requests .., OK
10715 11:08:41.389239 <6>[ 8.691456] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10716 11:08:41.392506 <6>[ 8.699752] IP-Config: Complete:
10717 11:08:41.405459 <6>[ 8.703243] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10718 11:08:41.412760 <6>[ 8.713960] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10719 11:08:41.419207 <6>[ 8.722583] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10720 11:08:41.425806 <6>[ 8.722592] nameserver0=192.168.201.1
10721 11:08:41.428895 <6>[ 8.734747] clk: Disabling unused clocks
10722 11:08:41.432682 <6>[ 8.740279] ALSA device list:
10723 11:08:41.438924 <6>[ 8.743529] No soundcards found.
10724 11:08:41.447107 <6>[ 8.751396] Freeing unused kernel memory: 8512K
10725 11:08:41.450465 <6>[ 8.756414] Run /init as init process
10726 11:08:41.483503 <6>[ 8.788283] NET: Registered PF_INET6 protocol family
10727 11:08:41.490805 <6>[ 8.795305] Segment Routing with IPv6
10728 11:08:41.493982 <6>[ 8.799274] In-situ OAM (IOAM) with IPv6
10729 11:08:41.535397 <30>[ 8.813109] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10730 11:08:41.541681 <30>[ 8.846150] systemd[1]: Detected architecture arm64.
10731 11:08:41.542172
10732 11:08:41.547982 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10733 11:08:41.548382
10734 11:08:41.562820 <30>[ 8.867420] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10735 11:08:41.695243 <30>[ 8.996322] systemd[1]: Queued start job for default target graphical.target.
10736 11:08:41.740496 <30>[ 9.041167] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10737 11:08:41.746558 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10738 11:08:41.766860 <30>[ 9.067833] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10739 11:08:41.776515 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10740 11:08:41.795282 <30>[ 9.096637] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10741 11:08:41.805678 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10742 11:08:41.823524 <30>[ 9.124695] systemd[1]: Created slice user.slice - User and Session Slice.
10743 11:08:41.829984 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10744 11:08:41.854219 <30>[ 9.151933] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10745 11:08:41.860614 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10746 11:08:41.881260 <30>[ 9.179322] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10747 11:08:41.888153 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10748 11:08:41.915882 <30>[ 9.207396] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10749 11:08:41.926214 <30>[ 9.227277] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10750 11:08:41.932242 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10751 11:08:41.950066 <30>[ 9.251301] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10752 11:08:41.956732 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10753 11:08:41.974071 <30>[ 9.275354] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10754 11:08:41.984084 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10755 11:08:41.999302 <30>[ 9.303442] systemd[1]: Reached target paths.target - Path Units.
10756 11:08:42.005525 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10757 11:08:42.026441 <30>[ 9.327741] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10758 11:08:42.033341 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10759 11:08:42.047030 <30>[ 9.351302] systemd[1]: Reached target slices.target - Slice Units.
10760 11:08:42.056907 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10761 11:08:42.071163 <30>[ 9.375796] systemd[1]: Reached target swap.target - Swaps.
10762 11:08:42.077464 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10763 11:08:42.098114 <30>[ 9.399406] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10764 11:08:42.107727 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10765 11:08:42.126850 <30>[ 9.428211] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10766 11:08:42.136679 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10767 11:08:42.155651 <30>[ 9.457415] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10768 11:08:42.165639 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10769 11:08:42.182626 <30>[ 9.483922] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10770 11:08:42.192392 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10771 11:08:42.210710 <30>[ 9.511947] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10772 11:08:42.217156 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10773 11:08:42.235167 <30>[ 9.536043] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10774 11:08:42.244819 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10775 11:08:42.263022 <30>[ 9.564106] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10776 11:08:42.273068 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10777 11:08:42.290742 <30>[ 9.591760] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10778 11:08:42.300370 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10779 11:08:42.349874 <30>[ 9.651397] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10780 11:08:42.357633 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10781 11:08:42.377787 <30>[ 9.679434] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10782 11:08:42.385017 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10783 11:08:42.406314 <30>[ 9.707653] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10784 11:08:42.413007 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10785 11:08:42.441301 <30>[ 9.735743] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10786 11:08:42.470669 <30>[ 9.771588] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10787 11:08:42.479821 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10788 11:08:42.503195 <30>[ 9.804607] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10789 11:08:42.509718 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10790 11:08:42.550155 <30>[ 9.851601] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10791 11:08:42.563338 Starting [0;1;39mmodprobe@dm_mod.s…[<6>[ 9.863221] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10792 11:08:42.566481 0m - Load Kernel Module dm_mod...
10793 11:08:42.591762 <30>[ 9.892583] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10794 11:08:42.598208 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10795 11:08:42.642493 <30>[ 9.943752] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10796 11:08:42.652317 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10797 11:08:42.675530 <30>[ 9.976735] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10798 11:08:42.681924 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10799 11:08:42.726174 <30>[ 10.027745] systemd[1]: Starting systemd-journald.service - Journal Service...
10800 11:08:42.733192 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10801 11:08:42.752860 <30>[ 10.054474] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10802 11:08:42.760049 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10803 11:08:42.784128 <30>[ 10.082220] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10804 11:08:42.790507 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10805 11:08:42.818117 <30>[ 10.119427] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10806 11:08:42.828139 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10807 11:08:42.849704 <30>[ 10.150816] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10808 11:08:42.856529 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10809 11:08:42.879619 <30>[ 10.180941] systemd[1]: Started systemd-journald.service - Journal Service.
10810 11:08:42.885904 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10811 11:08:42.907824 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10812 11:08:42.926581 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10813 11:08:42.943021 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10814 11:08:42.963107 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10815 11:08:42.982956 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10816 11:08:43.003339 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10817 11:08:43.024686 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10818 11:08:43.043954 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10819 11:08:43.063330 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10820 11:08:43.084265 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10821 11:08:43.104378 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10822 11:08:43.129196 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10823 11:08:43.142712 See 'systemctl status systemd-remount-fs.service' for details.
10824 11:08:43.153580 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10825 11:08:43.176638 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10826 11:08:43.226322 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10827 11:08:43.247924 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10828 11:08:43.263154 <46>[ 10.564775] systemd-journald[190]: Received client request to flush runtime journal.
10829 11:08:43.295323 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10830 11:08:43.318369 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10831 11:08:43.338654 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10832 11:08:43.369085 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10833 11:08:43.387475 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10834 11:08:43.407217 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10835 11:08:43.427403 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10836 11:08:43.447675 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10837 11:08:43.494855 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10838 11:08:43.517010 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10839 11:08:43.534553 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10840 11:08:43.549984 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10841 11:08:43.615249 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10842 11:08:43.640763 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10843 11:08:43.664710 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10844 11:08:43.685318 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10845 11:08:43.753717 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10846 11:08:43.789788 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10847 11:08:43.817679 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10848 11:08:43.847491 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10849 11:08:43.874511 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10850 11:08:43.881277 <5>[ 11.183684] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10851 11:08:43.905593 <46>[ 11.210668] systemd-journald[190]: Time jumped backwards, rotating.
10852 11:08:43.916031 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10853 11:08:43.931534 <5>[ 11.232969] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10854 11:08:43.937997 <5>[ 11.240445] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10855 11:08:43.948224 <4>[ 11.249035] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10856 11:08:43.955234 <6>[ 11.257962] cfg80211: failed to load regulatory.db
10857 11:08:43.976958 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10858 11:08:44.041856 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10859 11:08:44.062809 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10860 11:08:44.078539 <6>[ 11.379714] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10861 11:08:44.084646 <3>[ 11.384736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 11:08:44.094882 <6>[ 11.387349] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10863 11:08:44.101770 <6>[ 11.387356] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10864 11:08:44.111661 <3>[ 11.413154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 11:08:44.118380 <6>[ 11.415751] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10866 11:08:44.128582 [[0;32m OK [<3>[ 11.421552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 11:08:44.138396 0m] Started [0;<6>[ 11.432493] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10868 11:08:44.144472 1;39msystemd-tmp<6>[ 11.432556] mc: Linux media interface: v0.10
10869 11:08:44.151658 <4>[ 11.432585] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10870 11:08:44.161348 files-c… Clean<4>[ 11.432737] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10871 11:08:44.168034 <6>[ 11.432936] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10872 11:08:44.178200 up of Temporary <6>[ 11.439705] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10873 11:08:44.178681 Directories.
10874 11:08:44.184457 <3>[ 11.445712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 11:08:44.194760 <3>[ 11.445728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 11:08:44.201142 <3>[ 11.445733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 11:08:44.211225 <3>[ 11.445738] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 11:08:44.217344 <3>[ 11.445741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 11:08:44.225220 <6>[ 11.451795] remoteproc remoteproc0: scp is available
10880 11:08:44.230777 <6>[ 11.454152] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10881 11:08:44.237471 <6>[ 11.461420] remoteproc remoteproc0: powering up scp
10882 11:08:44.243850 <3>[ 11.462929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10883 11:08:44.253817 <3>[ 11.465580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 11:08:44.261143 <3>[ 11.465614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 11:08:44.270646 <3>[ 11.465619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 11:08:44.277411 <3>[ 11.468625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 11:08:44.284057 <3>[ 11.468664] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 11:08:44.293943 <3>[ 11.468671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 11:08:44.300405 <3>[ 11.468678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 11:08:44.310869 <3>[ 11.468682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 11:08:44.320473 <4>[ 11.470257] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10892 11:08:44.326987 <3>[ 11.470636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 11:08:44.337101 <6>[ 11.477100] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10894 11:08:44.340534 <6>[ 11.477154] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10895 11:08:44.346926 <6>[ 11.503248] videodev: Linux video capture interface: v2.00
10896 11:08:44.353570 <6>[ 11.505124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10897 11:08:44.363467 <6>[ 11.512380] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10898 11:08:44.369922 <6>[ 11.520266] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10899 11:08:44.376827 <6>[ 11.528283] pci_bus 0000:00: root bus resource [bus 00-ff]
10900 11:08:44.382951 <6>[ 11.528287] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10901 11:08:44.393501 <6>[ 11.528289] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10902 11:08:44.400262 <6>[ 11.528324] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10903 11:08:44.407082 <6>[ 11.528337] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10904 11:08:44.409417 <6>[ 11.528406] pci 0000:00:00.0: supports D1 D2
10905 11:08:44.419920 <6>[ 11.533789] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10906 11:08:44.427324 <6>[ 11.541479] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10907 11:08:44.433786 <6>[ 11.546889] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10908 11:08:44.444487 <6>[ 11.547687] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10909 11:08:44.454482 <6>[ 11.551578] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10910 11:08:44.460871 <6>[ 11.552057] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10911 11:08:44.471158 <6>[ 11.555837] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10912 11:08:44.477834 <6>[ 11.563700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10913 11:08:44.484312 <6>[ 11.573412] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10914 11:08:44.494247 <6>[ 11.579170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10915 11:08:44.500763 <6>[ 11.587238] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10916 11:08:44.504128 <6>[ 11.588287] Bluetooth: Core ver 2.22
10917 11:08:44.510645 <6>[ 11.588596] NET: Registered PF_BLUETOOTH protocol family
10918 11:08:44.517097 <6>[ 11.588606] Bluetooth: HCI device and connection manager initialized
10919 11:08:44.520894 <6>[ 11.588655] Bluetooth: HCI socket layer initialized
10920 11:08:44.527546 <6>[ 11.588689] Bluetooth: L2CAP socket layer initialized
10921 11:08:44.533687 <6>[ 11.588734] Bluetooth: SCO socket layer initialized
10922 11:08:44.540753 <6>[ 11.603417] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10923 11:08:44.547472 <6>[ 11.603448] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10924 11:08:44.553474 <6>[ 11.603456] remoteproc remoteproc0: remote processor scp is now up
10925 11:08:44.560634 <6>[ 11.611459] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10926 11:08:44.570102 <6>[ 11.611475] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10927 11:08:44.573469 <6>[ 11.611604] pci 0000:01:00.0: supports D1 D2
10928 11:08:44.580429 <6>[ 11.619809] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10929 11:08:44.586904 <6>[ 11.628706] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10930 11:08:44.596930 <6>[ 11.636869] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10931 11:08:44.603584 <6>[ 11.637374] usbcore: registered new interface driver btusb
10932 11:08:44.613158 <4>[ 11.638212] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10933 11:08:44.619622 <3>[ 11.638223] Bluetooth: hci0: Failed to load firmware file (-2)
10934 11:08:44.622894 <3>[ 11.638228] Bluetooth: hci0: Failed to set up firmware (-2)
10935 11:08:44.632869 <4>[ 11.638232] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10936 11:08:44.642689 <6>[ 11.639185] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10937 11:08:44.649460 <6>[ 11.639247] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10938 11:08:44.656022 <6>[ 11.639256] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10939 11:08:44.665958 <6>[ 11.639271] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10940 11:08:44.672698 <6>[ 11.639285] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10941 11:08:44.682635 <6>[ 11.639298] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10942 11:08:44.686583 <6>[ 11.639313] pci 0000:00:00.0: PCI bridge to [bus 01]
10943 11:08:44.696429 <6>[ 11.639319] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10944 11:08:44.699425 <6>[ 11.639531] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10945 11:08:44.705826 <6>[ 11.640346] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10946 11:08:44.713151 <6>[ 11.642183] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10947 11:08:44.726624 <6>[ 11.648421] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10948 11:08:44.732804 <6>[ 11.653073] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10949 11:08:44.739238 <6>[ 11.657117] usbcore: registered new interface driver uvcvideo
10950 11:08:44.746492 <6>[ 11.667786] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10951 11:08:44.755527 <4>[ 11.680484] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10952 11:08:44.759013 <4>[ 11.680484] Fallback method does not support PEC.
10953 11:08:44.768897 <3>[ 11.733072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 11:08:44.775914 <6>[ 11.752654] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10955 11:08:44.782588 <6>[ 12.086204] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10956 11:08:44.792085 [[0;32m OK [<3>[ 12.094159] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 11:08:44.798890 0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10958 11:08:44.806471 <6>[ 12.111210] mt7921e 0000:01:00.0: ASIC revision: 79610010
10959 11:08:44.823157 [[0;32m OK [0m] Started [0;<3>[ 12.122207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 11:08:44.826975 1;39mfstrim.timer[0m - Discard unused blocks once a week.
10961 11:08:44.837440 <3>[ 12.137748] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:08:44.849932 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10963 11:08:44.865709 <3>[ 12.166706] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 11:08:44.878406 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10965 11:08:44.899990 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10966 11:08:44.910051 [[0;32m OK [<6>[ 12.210964] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10967 11:08:44.912711 <6>[ 12.210964]
10968 11:08:44.916422 0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10969 11:08:44.933917 <3>[ 12.235337] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 11:08:44.951212 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10971 11:08:44.970967 <3>[ 12.272128] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:08:44.983478 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10973 11:08:45.005553 <3>[ 12.307311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 11:08:45.012349 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10975 11:08:45.033811 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10976 11:08:45.043560 <3>[ 12.344654] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 11:08:45.064463 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10978 11:08:45.084759 <3>[ 12.385869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 11:08:45.105566 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10980 11:08:45.125642 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10981 11:08:45.143002 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10982 11:08:45.163623 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10983 11:08:45.180853 <6>[ 12.481384] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10984 11:08:45.219200 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10985 11:08:45.267894 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10986 11:08:45.286887 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10987 11:08:45.302679 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10988 11:08:45.322579 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10989 11:08:45.383729 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10990 11:08:45.408978 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10991 11:08:45.434118 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10992 11:08:45.508321 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10993 11:08:45.531348 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10994 11:08:45.556185 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10995 11:08:45.630601
10996 11:08:45.633993 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10997 11:08:45.634458
10998 11:08:45.636931 debian-bookworm-arm64 login: root (automatic login)
10999 11:08:45.637350
11000 11:08:45.649397 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11001 11:08:45.649851
11002 11:08:45.655562 The programs included with the Debian GNU/Linux system are free software;
11003 11:08:45.662681 the exact distribution terms for each program are described in the
11004 11:08:45.665815 individual files in /usr/share/doc/*/copyright.
11005 11:08:45.666365
11006 11:08:45.672133 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11007 11:08:45.675875 permitted by applicable law.
11008 11:08:45.677209 Matched prompt #10: / #
11010 11:08:45.678228 Setting prompt string to ['/ #']
11011 11:08:45.678836 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11013 11:08:45.679837 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11014 11:08:45.680290 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11015 11:08:45.680627 Setting prompt string to ['/ #']
11016 11:08:45.680929 Forcing a shell prompt, looking for ['/ #']
11017 11:08:45.681196 Sending line: ''
11019 11:08:45.732120 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11020 11:08:45.732467 Waiting using forced prompt support (timeout 00:02:30)
11021 11:08:45.737650 / #
11022 11:08:45.738459 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11023 11:08:45.738892 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11024 11:08:45.739317 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11025 11:08:45.739734 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11026 11:08:45.740197 end: 2 depthcharge-action (duration 00:01:30) [common]
11027 11:08:45.740621 start: 3 lava-test-retry (timeout 00:08:09) [common]
11028 11:08:45.741188 start: 3.1 lava-test-shell (timeout 00:08:09) [common]
11029 11:08:45.741536 Using namespace: common
11030 11:08:45.741848 Sending line: '#'
11032 11:08:45.843284 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11033 11:08:45.849388 / # #
11034 11:08:45.850161 Using /lava-14786851
11035 11:08:45.850514 Sending line: 'export SHELL=/bin/sh'
11037 11:08:45.958210 / # export SHELL=/bin/sh
11038 11:08:45.958937 Sending line: '. /lava-14786851/environment'
11040 11:08:46.060449 / # . /lava-14786851/environment<6>[ 13.347410] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11041 11:08:46.066453
11042 11:08:46.067404 Sending line: '/lava-14786851/bin/lava-test-runner /lava-14786851/0'
11044 11:08:46.168905 Test shell timeout: 10s (minimum of the action and connection timeout)
11045 11:08:46.175284 / # /lava-14786851/bin/lava-test-runner /lava-14786851/0
11046 11:08:46.201141 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11047 11:08:46.207395 + cd /lava-14786851/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11048 11:08:46.207909 + cat uuid
11049 11:08:46.211034 + UUID=14786851_1.5.2.3.1
11050 11:08:46.211682 + set +x
11051 11:08:46.217615 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14786851_1.5.2.3.1>
11052 11:08:46.218413 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14786851_1.5.2.3.1
11053 11:08:46.218772 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14786851_1.5.2.3.1)
11054 11:08:46.219140 Skipping test definition patterns.
11055 11:08:46.221224 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11056 11:08:46.228023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11057 11:08:46.228451 device: /dev/video2
11058 11:08:46.229017 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11060 11:08:46.237107 <4>[ 13.538820] use of bytesused == 0 is deprecated and will be removed in the future,
11061 11:08:46.240467 <4>[ 13.546754] use the actual size instead.
11062 11:08:46.255019 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11063 11:08:46.265755 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11064 11:08:46.273011
11065 11:08:46.288856 Compliance test for mtk-vcodec-enc device /dev/video2:
11066 11:08:46.296596
11067 11:08:46.307676 Driver Info:
11068 11:08:46.316707 Driver name : mtk-vcodec-enc
11069 11:08:46.332023 Card type : MT8192 video encoder
11070 11:08:46.342442 Bus info : platform:17020000.vcodec
11071 11:08:46.354938 Driver version : 6.1.96
11072 11:08:46.368748 Capabilities : 0x84204000
11073 11:08:46.382926 Video Memory-to-Memory Multiplanar
11074 11:08:46.395481 Streaming
11075 11:08:46.408498 Extended Pix Format
11076 11:08:46.420197 Device Capabilities
11077 11:08:46.434133 Device Caps : 0x04204000
11078 11:08:46.443606 Video Memory-to-Memory Multiplanar
11079 11:08:46.459727 Streaming
11080 11:08:46.471780 Extended Pix Format
11081 11:08:46.485070 Detected Stateful Encoder
11082 11:08:46.501503
11083 11:08:46.511786 Required ioctls:
11084 11:08:46.527652 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11085 11:08:46.527740 test VIDIOC_QUERYCAP: OK
11086 11:08:46.527988 Received signal: <TESTSET> START Required-ioctls
11087 11:08:46.528061 Starting test_set Required-ioctls
11088 11:08:46.556308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11089 11:08:46.556642 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11091 11:08:46.559813 test invalid ioctls: OK
11092 11:08:46.579581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11093 11:08:46.579707
11094 11:08:46.579960 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11096 11:08:46.589765 Allow for multiple opens:
11097 11:08:46.596211 <LAVA_SIGNAL_TESTSET STOP>
11098 11:08:46.596477 Received signal: <TESTSET> STOP
11099 11:08:46.596544 Closing test_set Required-ioctls
11100 11:08:46.605816 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11101 11:08:46.606061 Received signal: <TESTSET> START Allow-for-multiple-opens
11102 11:08:46.606161 Starting test_set Allow-for-multiple-opens
11103 11:08:46.609344 test second /dev/video2 open: OK
11104 11:08:46.631637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11105 11:08:46.631929 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11107 11:08:46.634688 test VIDIOC_QUERYCAP: OK
11108 11:08:46.658405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11109 11:08:46.658672 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11111 11:08:46.661424 test VIDIOC_G/S_PRIORITY: OK
11112 11:08:46.683587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11113 11:08:46.683892 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11115 11:08:46.686772 test for unlimited opens: OK
11116 11:08:46.707445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11117 11:08:46.707591
11118 11:08:46.707847 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11120 11:08:46.721208 Debug ioctls:
11121 11:08:46.728830 <LAVA_SIGNAL_TESTSET STOP>
11122 11:08:46.729080 Received signal: <TESTSET> STOP
11123 11:08:46.729141 Closing test_set Allow-for-multiple-opens
11124 11:08:46.738277 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11125 11:08:46.738527 Received signal: <TESTSET> START Debug-ioctls
11126 11:08:46.738589 Starting test_set Debug-ioctls
11127 11:08:46.741426 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11128 11:08:46.768451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11129 11:08:46.768727 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11131 11:08:46.774944 test VIDIOC_LOG_STATUS: OK (Not Supported)
11132 11:08:46.799257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11133 11:08:46.799384
11134 11:08:46.799629 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11136 11:08:46.808427 Input ioctls:
11137 11:08:46.816621 <LAVA_SIGNAL_TESTSET STOP>
11138 11:08:46.816909 Received signal: <TESTSET> STOP
11139 11:08:46.816999 Closing test_set Debug-ioctls
11140 11:08:46.825682 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11141 11:08:46.825978 Received signal: <TESTSET> START Input-ioctls
11142 11:08:46.826081 Starting test_set Input-ioctls
11143 11:08:46.829111 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11144 11:08:46.853496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11145 11:08:46.853807 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11147 11:08:46.856905 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11148 11:08:46.875163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11149 11:08:46.875475 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11151 11:08:46.881689 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11152 11:08:46.900548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11153 11:08:46.900855 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11155 11:08:46.906940 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11156 11:08:46.924004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11157 11:08:46.924297 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11159 11:08:46.927242 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11160 11:08:46.950011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11161 11:08:46.950279 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11163 11:08:46.954470 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11164 11:08:46.975630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11165 11:08:46.976306 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11167 11:08:46.978848 Inputs: 0 Audio Inputs: 0 Tuners: 0
11168 11:08:46.985487
11169 11:08:47.001790 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11170 11:08:47.023619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11171 11:08:47.024341 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11173 11:08:47.030126 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11174 11:08:47.050987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11175 11:08:47.051716 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11177 11:08:47.056874 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11178 11:08:47.079605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11179 11:08:47.080354 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11181 11:08:47.085477 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11182 11:08:47.104498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11183 11:08:47.105239 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11185 11:08:47.111041 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11186 11:08:47.128986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11187 11:08:47.129512
11188 11:08:47.130117 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11190 11:08:47.147744 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11191 11:08:47.169116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11192 11:08:47.169838 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11194 11:08:47.175497 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11195 11:08:47.195825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11196 11:08:47.196501 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11198 11:08:47.199208 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11199 11:08:47.220229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11200 11:08:47.220965 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11202 11:08:47.222987 test VIDIOC_G/S_EDID: OK (Not Supported)
11203 11:08:47.244372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11204 11:08:47.244868
11205 11:08:47.245441 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11207 11:08:47.256521 Control ioctls:
11208 11:08:47.263331 <LAVA_SIGNAL_TESTSET STOP>
11209 11:08:47.264147 Received signal: <TESTSET> STOP
11210 11:08:47.264578 Closing test_set Input-ioctls
11211 11:08:47.273071 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11212 11:08:47.273845 Received signal: <TESTSET> START Control-ioctls
11213 11:08:47.274254 Starting test_set Control-ioctls
11214 11:08:47.276256 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11215 11:08:47.299478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11216 11:08:47.299963 test VIDIOC_QUERYCTRL: OK
11217 11:08:47.300531 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11219 11:08:47.326979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11220 11:08:47.327900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11222 11:08:47.330514 test VIDIOC_G/S_CTRL: OK
11223 11:08:47.351779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11224 11:08:47.352497 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11226 11:08:47.355502 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11227 11:08:47.377001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11228 11:08:47.377732 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11230 11:08:47.383690 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11231 11:08:47.392102 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11232 11:08:47.416472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11233 11:08:47.417233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11235 11:08:47.419645 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11236 11:08:47.438701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11237 11:08:47.439521 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11239 11:08:47.441015 Standard Controls: 16 Private Controls: 0
11240 11:08:47.448268
11241 11:08:47.460070 Format ioctls:
11242 11:08:47.466175 <LAVA_SIGNAL_TESTSET STOP>
11243 11:08:47.467089 Received signal: <TESTSET> STOP
11244 11:08:47.467512 Closing test_set Control-ioctls
11245 11:08:47.476410 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11246 11:08:47.477071 Received signal: <TESTSET> START Format-ioctls
11247 11:08:47.477385 Starting test_set Format-ioctls
11248 11:08:47.479637 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11249 11:08:47.504434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11250 11:08:47.505073 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11252 11:08:47.507742 test VIDIOC_G/S_PARM: OK
11253 11:08:47.525428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11254 11:08:47.526168 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11256 11:08:47.527991 test VIDIOC_G_FBUF: OK (Not Supported)
11257 11:08:47.549689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11258 11:08:47.550554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11260 11:08:47.552510 test VIDIOC_G_FMT: OK
11261 11:08:47.573545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11262 11:08:47.574328 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11264 11:08:47.576645 test VIDIOC_TRY_FMT: OK
11265 11:08:47.599591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11266 11:08:47.600323 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11268 11:08:47.605735 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11269 11:08:47.611457 test VIDIOC_S_FMT: FAIL
11270 11:08:47.636924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11271 11:08:47.637635 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11273 11:08:47.639990 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11274 11:08:47.660857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11275 11:08:47.661665 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11277 11:08:47.664443 test Cropping: OK
11278 11:08:47.686068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11279 11:08:47.686935 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11281 11:08:47.689119 test Composing: OK (Not Supported)
11282 11:08:47.715945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11283 11:08:47.716658 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11285 11:08:47.719655 test Scaling: OK (Not Supported)
11286 11:08:47.741017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11287 11:08:47.741476
11288 11:08:47.742092 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11290 11:08:47.750108 Codec ioctls:
11291 11:08:47.757880 <LAVA_SIGNAL_TESTSET STOP>
11292 11:08:47.758699 Received signal: <TESTSET> STOP
11293 11:08:47.759064 Closing test_set Format-ioctls
11294 11:08:47.766815 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11295 11:08:47.767478 Received signal: <TESTSET> START Codec-ioctls
11296 11:08:47.767831 Starting test_set Codec-ioctls
11297 11:08:47.769916 test VIDIOC_(TRY_)ENCODER_CMD: OK
11298 11:08:47.795514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11299 11:08:47.796229 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11301 11:08:47.802258 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11302 11:08:47.820353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11303 11:08:47.821065 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11305 11:08:47.827079 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11306 11:08:47.851403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11307 11:08:47.851907
11308 11:08:47.852514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11310 11:08:47.861434 Buffer ioctls:
11311 11:08:47.870069 <LAVA_SIGNAL_TESTSET STOP>
11312 11:08:47.870842 Received signal: <TESTSET> STOP
11313 11:08:47.871207 Closing test_set Codec-ioctls
11314 11:08:47.881646 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11315 11:08:47.882518 Received signal: <TESTSET> START Buffer-ioctls
11316 11:08:47.882863 Starting test_set Buffer-ioctls
11317 11:08:47.884773 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11318 11:08:47.910369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11319 11:08:47.911097 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11321 11:08:47.913307 test CREATE_BUFS maximum buffers: OK
11322 11:08:47.931213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11323 11:08:47.931928 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11325 11:08:47.934382 test VIDIOC_EXPBUF: OK
11326 11:08:47.957469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11327 11:08:47.958197 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11329 11:08:47.960899 test Requests: OK (Not Supported)
11330 11:08:47.982354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11331 11:08:47.982891
11332 11:08:47.983455 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11334 11:08:47.993929 Test input 0:
11335 11:08:48.003940
11336 11:08:48.015104 Streaming ioctls:
11337 11:08:48.022459 <LAVA_SIGNAL_TESTSET STOP>
11338 11:08:48.023185 Received signal: <TESTSET> STOP
11339 11:08:48.023518 Closing test_set Buffer-ioctls
11340 11:08:48.031978 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11341 11:08:48.032700 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11342 11:08:48.033043 Starting test_set Streaming-ioctls_Test-input-0
11343 11:08:48.035189 test read/write: OK (Not Supported)
11344 11:08:48.059565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11345 11:08:48.060279 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11347 11:08:48.066095 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11348 11:08:48.074437 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11349 11:08:48.083048 test blocking wait: FAIL
11350 11:08:48.108148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11351 11:08:48.108873 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11353 11:08:48.115063 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11354 11:08:48.120054 test MMAP (select): FAIL
11355 11:08:48.145878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11356 11:08:48.146669 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11358 11:08:48.152196 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11359 11:08:48.156693 test MMAP (epoll): FAIL
11360 11:08:48.181744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11361 11:08:48.182540 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11363 11:08:48.188040 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11364 11:08:48.195161 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11365 11:08:48.203655 test USERPTR (select): FAIL
11366 11:08:48.232550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11367 11:08:48.233366 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11369 11:08:48.239694 test DMABUF: Cannot test, specify --expbuf-device
11370 11:08:48.242896
11371 11:08:48.261722 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11372 11:08:48.268665 <LAVA_TEST_RUNNER EXIT>
11373 11:08:48.269388 ok: lava_test_shell seems to have completed
11374 11:08:48.269751 Marking unfinished test run as failed
11376 11:08:48.274497 device-presence: pass
VIDIOC_QUERYCAP:
set: Allow-for-multiple-opens
result: pass
invalid-ioctls:
set: Required-ioctls
result: pass
second-/dev/video2-open:
set: Allow-for-multiple-opens
result: pass
VIDIOC_G/S_PRIORITY:
set: Allow-for-multiple-opens
result: pass
for-unlimited-opens:
set: Allow-for-multiple-opens
result: pass
VIDIOC_DBG_G/S_REGISTER:
set: Debug-ioctls
result: pass
VIDIOC_LOG_STATUS:
set: Debug-ioctls
result: pass
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
set: Input-ioctls
result: pass
VIDIOC_G/S_FREQUENCY:
set: Input-ioctls
result: pass
VIDIOC_S_HW_FREQ_SEEK:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMINPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S_MODULATOR:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDOUT:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMOUTPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDOUT:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_STD:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
set: Input-ioctls
result: pass
VIDIOC_DV_TIMINGS_CAP:
set: Input-ioctls
result: pass
VIDIOC_G/S_EDID:
set: Input-ioctls
result: pass
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
set: Control-ioctls
result: pass
VIDIOC_QUERYCTRL:
set: Control-ioctls
result: pass
VIDIOC_G/S_CTRL:
set: Control-ioctls
result: pass
VIDIOC_G/S/TRY_EXT_CTRLS:
set: Control-ioctls
result: pass
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
set: Control-ioctls
result: fail
VIDIOC_G/S_JPEGCOMP:
set: Control-ioctls
result: pass
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
set: Format-ioctls
result: pass
VIDIOC_G/S_PARM:
set: Format-ioctls
result: pass
VIDIOC_G_FBUF:
set: Format-ioctls
result: pass
VIDIOC_G_FMT:
set: Format-ioctls
result: pass
VIDIOC_TRY_FMT:
set: Format-ioctls
result: pass
VIDIOC_S_FMT:
set: Format-ioctls
result: fail
VIDIOC_G_SLICED_VBI_CAP:
set: Format-ioctls
result: pass
Cropping:
set: Format-ioctls
result: pass
Composing:
set: Format-ioctls
result: pass
Scaling:
set: Format-ioctls
result: pass
VIDIOC_TRY_ENCODER_CMD:
set: Codec-ioctls
result: pass
VIDIOC_G_ENC_INDEX:
set: Codec-ioctls
result: pass
VIDIOC_TRY_DECODER_CMD:
set: Codec-ioctls
result: pass
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
set: Buffer-ioctls
result: pass
CREATE_BUFS-maximum-buffers:
set: Buffer-ioctls
result: pass
VIDIOC_EXPBUF:
set: Buffer-ioctls
result: pass
Requests:
set: Buffer-ioctls
result: pass
read/write:
set: Streaming-ioctls_Test-input-0
result: pass
blocking-wait:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-select:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-epoll:
set: Streaming-ioctls_Test-input-0
result: fail
USERPTR-select:
set: Streaming-ioctls_Test-input-0
result: fail
11377 11:08:48.275151 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11378 11:08:48.275576 end: 3 lava-test-retry (duration 00:00:03) [common]
11379 11:08:48.275999 start: 4 finalize (timeout 00:08:06) [common]
11380 11:08:48.276417 start: 4.1 power-off (timeout 00:00:30) [common]
11381 11:08:48.277048 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11382 11:08:50.393874 >> Command sent successfully.
11383 11:08:50.407368 Returned 0 in 2 seconds
11384 11:08:50.407907 end: 4.1 power-off (duration 00:00:02) [common]
11386 11:08:50.408818 start: 4.2 read-feedback (timeout 00:08:04) [common]
11387 11:08:50.409388 Listened to connection for namespace 'common' for up to 1s
11388 11:08:51.410291 Finalising connection for namespace 'common'
11389 11:08:51.410826 Disconnecting from shell: Finalise
11390 11:08:51.411171 / #
11391 11:08:51.511985 end: 4.2 read-feedback (duration 00:00:01) [common]
11392 11:08:51.512589 end: 4 finalize (duration 00:00:03) [common]
11393 11:08:51.513158 Cleaning after the job
11394 11:08:51.513631 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/ramdisk
11395 11:08:51.532661 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/kernel
11396 11:08:51.547752 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/dtb
11397 11:08:51.548049 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786851/tftp-deploy-spy6iyge/modules
11398 11:08:51.555985 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786851
11399 11:08:51.620895 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786851
11400 11:08:51.621042 Job finished correctly