Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:02:02.308352 lava-dispatcher, installed at version: 2024.05
2 11:02:02.308579 start: 0 validate
3 11:02:02.308725 Start time: 2024-07-10 11:02:02.308719+00:00 (UTC)
4 11:02:02.308890 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:02.309078 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:02:03.291422 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:03.291636 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:03:04.356595 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:03:04.357326 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:03:04.627743 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:03:04.628309 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:03:05.156230 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:03:05.156879 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:03:14.172413 validate duration: 71.86
16 11:03:14.173491 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:03:14.173945 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:03:14.174335 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:03:14.174964 Not decompressing ramdisk as can be used compressed.
20 11:03:14.175353 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 11:03:14.175707 saving as /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/ramdisk/initrd.cpio.gz
22 11:03:14.175999 total size: 5628182 (5 MB)
23 11:03:14.445000 progress 0 % (0 MB)
24 11:03:14.446473 progress 5 % (0 MB)
25 11:03:14.448048 progress 10 % (0 MB)
26 11:03:14.449382 progress 15 % (0 MB)
27 11:03:14.450867 progress 20 % (1 MB)
28 11:03:14.452224 progress 25 % (1 MB)
29 11:03:14.453709 progress 30 % (1 MB)
30 11:03:14.455194 progress 35 % (1 MB)
31 11:03:14.456526 progress 40 % (2 MB)
32 11:03:14.458015 progress 45 % (2 MB)
33 11:03:14.459346 progress 50 % (2 MB)
34 11:03:14.460874 progress 55 % (2 MB)
35 11:03:14.462369 progress 60 % (3 MB)
36 11:03:14.463801 progress 65 % (3 MB)
37 11:03:14.465315 progress 70 % (3 MB)
38 11:03:14.466639 progress 75 % (4 MB)
39 11:03:14.468160 progress 80 % (4 MB)
40 11:03:14.469480 progress 85 % (4 MB)
41 11:03:14.470968 progress 90 % (4 MB)
42 11:03:14.472495 progress 95 % (5 MB)
43 11:03:14.473872 progress 100 % (5 MB)
44 11:03:14.474081 5 MB downloaded in 0.30 s (18.01 MB/s)
45 11:03:14.474225 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:03:14.474438 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:03:14.474515 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:03:14.474588 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:03:14.474712 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:03:14.474771 saving as /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/kernel/Image
52 11:03:14.474822 total size: 54813184 (52 MB)
53 11:03:14.474874 No compression specified
54 11:03:14.475872 progress 0 % (0 MB)
55 11:03:14.489476 progress 5 % (2 MB)
56 11:03:14.503183 progress 10 % (5 MB)
57 11:03:14.516874 progress 15 % (7 MB)
58 11:03:14.531076 progress 20 % (10 MB)
59 11:03:14.544801 progress 25 % (13 MB)
60 11:03:14.558658 progress 30 % (15 MB)
61 11:03:14.572272 progress 35 % (18 MB)
62 11:03:14.585832 progress 40 % (20 MB)
63 11:03:14.599363 progress 45 % (23 MB)
64 11:03:14.613342 progress 50 % (26 MB)
65 11:03:14.627023 progress 55 % (28 MB)
66 11:03:14.640706 progress 60 % (31 MB)
67 11:03:14.654809 progress 65 % (34 MB)
68 11:03:14.668668 progress 70 % (36 MB)
69 11:03:14.682410 progress 75 % (39 MB)
70 11:03:14.696094 progress 80 % (41 MB)
71 11:03:14.709663 progress 85 % (44 MB)
72 11:03:14.723373 progress 90 % (47 MB)
73 11:03:14.737009 progress 95 % (49 MB)
74 11:03:14.750403 progress 100 % (52 MB)
75 11:03:14.750654 52 MB downloaded in 0.28 s (189.52 MB/s)
76 11:03:14.750803 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:03:14.751007 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:03:14.751084 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:03:14.751158 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:03:14.751283 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:03:14.751342 saving as /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/dtb/mt8192-asurada-spherion-r0.dtb
83 11:03:14.751393 total size: 47258 (0 MB)
84 11:03:14.751475 No compression specified
85 11:03:14.752518 progress 69 % (0 MB)
86 11:03:14.752774 progress 100 % (0 MB)
87 11:03:14.752921 0 MB downloaded in 0.00 s (29.54 MB/s)
88 11:03:14.753029 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:03:14.753224 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:03:14.753297 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:03:14.753375 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:03:14.753476 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 11:03:14.753533 saving as /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/nfsrootfs/full.rootfs.tar
95 11:03:14.753583 total size: 107552908 (102 MB)
96 11:03:14.753636 Using unxz to decompress xz
97 11:03:14.756911 progress 0 % (0 MB)
98 11:03:15.044704 progress 5 % (5 MB)
99 11:03:15.356537 progress 10 % (10 MB)
100 11:03:15.655812 progress 15 % (15 MB)
101 11:03:15.963925 progress 20 % (20 MB)
102 11:03:16.237382 progress 25 % (25 MB)
103 11:03:16.526742 progress 30 % (30 MB)
104 11:03:16.820700 progress 35 % (35 MB)
105 11:03:16.991506 progress 40 % (41 MB)
106 11:03:17.194703 progress 45 % (46 MB)
107 11:03:17.499415 progress 50 % (51 MB)
108 11:03:17.792272 progress 55 % (56 MB)
109 11:03:18.108996 progress 60 % (61 MB)
110 11:03:18.433419 progress 65 % (66 MB)
111 11:03:18.751879 progress 70 % (71 MB)
112 11:03:19.111659 progress 75 % (76 MB)
113 11:03:19.416597 progress 80 % (82 MB)
114 11:03:19.737985 progress 85 % (87 MB)
115 11:03:20.034130 progress 90 % (92 MB)
116 11:03:20.340219 progress 95 % (97 MB)
117 11:03:20.662873 progress 100 % (102 MB)
118 11:03:20.668043 102 MB downloaded in 5.91 s (17.34 MB/s)
119 11:03:20.668201 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:03:20.668414 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:03:20.668491 start: 1.5 download-retry (timeout 00:09:54) [common]
123 11:03:20.668565 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 11:03:20.668693 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:03:20.668754 saving as /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/modules/modules.tar
126 11:03:20.668805 total size: 8607984 (8 MB)
127 11:03:20.668859 Using unxz to decompress xz
128 11:03:20.670092 progress 0 % (0 MB)
129 11:03:20.691256 progress 5 % (0 MB)
130 11:03:20.717366 progress 10 % (0 MB)
131 11:03:20.743282 progress 15 % (1 MB)
132 11:03:20.769108 progress 20 % (1 MB)
133 11:03:20.793602 progress 25 % (2 MB)
134 11:03:20.818013 progress 30 % (2 MB)
135 11:03:20.842781 progress 35 % (2 MB)
136 11:03:20.871218 progress 40 % (3 MB)
137 11:03:20.898248 progress 45 % (3 MB)
138 11:03:20.925030 progress 50 % (4 MB)
139 11:03:20.951302 progress 55 % (4 MB)
140 11:03:20.976499 progress 60 % (4 MB)
141 11:03:21.000856 progress 65 % (5 MB)
142 11:03:21.028201 progress 70 % (5 MB)
143 11:03:21.057689 progress 75 % (6 MB)
144 11:03:21.087311 progress 80 % (6 MB)
145 11:03:21.111985 progress 85 % (7 MB)
146 11:03:21.135893 progress 90 % (7 MB)
147 11:03:21.160060 progress 95 % (7 MB)
148 11:03:21.183138 progress 100 % (8 MB)
149 11:03:21.188795 8 MB downloaded in 0.52 s (15.79 MB/s)
150 11:03:21.189020 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:03:21.189355 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:03:21.189475 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 11:03:21.189594 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 11:03:23.399946 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786788/extract-nfsrootfs-j6owxqcc
156 11:03:23.400114 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:03:23.400205 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 11:03:23.400354 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z
159 11:03:23.400468 makedir: /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin
160 11:03:23.400557 makedir: /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/tests
161 11:03:23.400643 makedir: /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/results
162 11:03:23.400723 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-add-keys
163 11:03:23.400849 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-add-sources
164 11:03:23.400964 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-background-process-start
165 11:03:23.401077 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-background-process-stop
166 11:03:23.401199 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-common-functions
167 11:03:23.401314 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-echo-ipv4
168 11:03:23.401426 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-install-packages
169 11:03:23.401538 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-installed-packages
170 11:03:23.401648 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-os-build
171 11:03:23.401759 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-probe-channel
172 11:03:23.401870 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-probe-ip
173 11:03:23.401981 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-target-ip
174 11:03:23.402090 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-target-mac
175 11:03:23.402200 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-target-storage
176 11:03:23.402316 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-test-case
177 11:03:23.402431 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-test-event
178 11:03:23.402543 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-test-feedback
179 11:03:23.402652 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-test-raise
180 11:03:23.402762 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-test-reference
181 11:03:23.402872 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-test-runner
182 11:03:23.402982 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-test-set
183 11:03:23.403092 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-test-shell
184 11:03:23.403208 Updating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-install-packages (oe)
185 11:03:23.403346 Updating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/bin/lava-installed-packages (oe)
186 11:03:23.403462 Creating /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/environment
187 11:03:23.403554 LAVA metadata
188 11:03:23.403617 - LAVA_JOB_ID=14786788
189 11:03:23.403672 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:03:23.403762 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 11:03:23.403818 skipped lava-vland-overlay
192 11:03:23.403884 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:03:23.403955 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 11:03:23.404007 skipped lava-multinode-overlay
195 11:03:23.404070 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:03:23.404138 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 11:03:23.404225 Loading test definitions
198 11:03:23.404313 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 11:03:23.404374 Using /lava-14786788 at stage 0
200 11:03:23.404663 uuid=14786788_1.6.2.3.1 testdef=None
201 11:03:23.404743 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:03:23.404817 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 11:03:23.405258 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:03:23.405457 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 11:03:23.406082 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:03:23.406288 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 11:03:23.406844 runner path: /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/0/tests/0_dmesg test_uuid 14786788_1.6.2.3.1
210 11:03:23.406984 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:03:23.407165 Creating lava-test-runner.conf files
213 11:03:23.407221 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786788/lava-overlay-hsw3vh3z/lava-14786788/0 for stage 0
214 11:03:23.407299 - 0_dmesg
215 11:03:23.407388 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:03:23.407602 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 11:03:23.413875 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:03:23.413970 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 11:03:23.414047 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:03:23.414123 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:03:23.414199 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 11:03:23.571484 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:03:23.571626 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 11:03:23.571703 extracting modules file /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786788/extract-nfsrootfs-j6owxqcc
225 11:03:23.792439 extracting modules file /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786788/extract-overlay-ramdisk-np2w9ees/ramdisk
226 11:03:24.018430 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:03:24.018578 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 11:03:24.018655 [common] Applying overlay to NFS
229 11:03:24.018713 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786788/compress-overlay-gy91hyeb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786788/extract-nfsrootfs-j6owxqcc
230 11:03:24.025184 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:03:24.025297 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 11:03:24.025376 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:03:24.025452 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 11:03:24.025520 Building ramdisk /var/lib/lava/dispatcher/tmp/14786788/extract-overlay-ramdisk-np2w9ees/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786788/extract-overlay-ramdisk-np2w9ees/ramdisk
235 11:03:24.325524 >> 129845 blocks
236 11:03:26.454272 rename /var/lib/lava/dispatcher/tmp/14786788/extract-overlay-ramdisk-np2w9ees/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/ramdisk/ramdisk.cpio.gz
237 11:03:26.454468 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:03:26.454585 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 11:03:26.454692 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 11:03:26.454801 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/kernel/Image']
241 11:03:41.146843 Returned 0 in 14 seconds
242 11:03:41.147054 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/kernel/image.itb
243 11:03:41.682808 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:03:41.682934 output: Created: Wed Jul 10 12:03:41 2024
245 11:03:41.682996 output: Image 0 (kernel-1)
246 11:03:41.683048 output: Description:
247 11:03:41.683098 output: Created: Wed Jul 10 12:03:41 2024
248 11:03:41.683149 output: Type: Kernel Image
249 11:03:41.683197 output: Compression: lzma compressed
250 11:03:41.683247 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
251 11:03:41.683296 output: Architecture: AArch64
252 11:03:41.683342 output: OS: Linux
253 11:03:41.683390 output: Load Address: 0x00000000
254 11:03:41.683463 output: Entry Point: 0x00000000
255 11:03:41.683527 output: Hash algo: crc32
256 11:03:41.683576 output: Hash value: 9bb85fb9
257 11:03:41.683624 output: Image 1 (fdt-1)
258 11:03:41.683671 output: Description: mt8192-asurada-spherion-r0
259 11:03:41.683718 output: Created: Wed Jul 10 12:03:41 2024
260 11:03:41.683766 output: Type: Flat Device Tree
261 11:03:41.683813 output: Compression: uncompressed
262 11:03:41.683860 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 11:03:41.683907 output: Architecture: AArch64
264 11:03:41.683954 output: Hash algo: crc32
265 11:03:41.684001 output: Hash value: 0f8e4d2e
266 11:03:41.684048 output: Image 2 (ramdisk-1)
267 11:03:41.684132 output: Description: unavailable
268 11:03:41.684194 output: Created: Wed Jul 10 12:03:41 2024
269 11:03:41.684242 output: Type: RAMDisk Image
270 11:03:41.684289 output: Compression: uncompressed
271 11:03:41.684336 output: Data Size: 18709028 Bytes = 18270.54 KiB = 17.84 MiB
272 11:03:41.684383 output: Architecture: AArch64
273 11:03:41.684430 output: OS: Linux
274 11:03:41.684476 output: Load Address: unavailable
275 11:03:41.684522 output: Entry Point: unavailable
276 11:03:41.684568 output: Hash algo: crc32
277 11:03:41.684614 output: Hash value: bec60cc8
278 11:03:41.684660 output: Default Configuration: 'conf-1'
279 11:03:41.684706 output: Configuration 0 (conf-1)
280 11:03:41.684752 output: Description: mt8192-asurada-spherion-r0
281 11:03:41.684798 output: Kernel: kernel-1
282 11:03:41.684844 output: Init Ramdisk: ramdisk-1
283 11:03:41.684890 output: FDT: fdt-1
284 11:03:41.684937 output: Loadables: kernel-1
285 11:03:41.684983 output:
286 11:03:41.685080 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 11:03:41.685154 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 11:03:41.685228 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 11:03:41.685306 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
290 11:03:41.685363 No LXC device requested
291 11:03:41.685428 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:03:41.685496 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
293 11:03:41.685561 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:03:41.685614 Checking files for TFTP limit of 4294967296 bytes.
295 11:03:41.685974 end: 1 tftp-deploy (duration 00:00:28) [common]
296 11:03:41.686062 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:03:41.686140 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:03:41.686228 substitutions:
299 11:03:41.686286 - {DTB}: 14786788/tftp-deploy-nbkabym0/dtb/mt8192-asurada-spherion-r0.dtb
300 11:03:41.686339 - {INITRD}: 14786788/tftp-deploy-nbkabym0/ramdisk/ramdisk.cpio.gz
301 11:03:41.686389 - {KERNEL}: 14786788/tftp-deploy-nbkabym0/kernel/Image
302 11:03:41.686438 - {LAVA_MAC}: None
303 11:03:41.686487 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786788/extract-nfsrootfs-j6owxqcc
304 11:03:41.686536 - {NFS_SERVER_IP}: 192.168.201.1
305 11:03:41.686584 - {PRESEED_CONFIG}: None
306 11:03:41.686636 - {PRESEED_LOCAL}: None
307 11:03:41.686683 - {RAMDISK}: 14786788/tftp-deploy-nbkabym0/ramdisk/ramdisk.cpio.gz
308 11:03:41.686731 - {ROOT_PART}: None
309 11:03:41.686778 - {ROOT}: None
310 11:03:41.686825 - {SERVER_IP}: 192.168.201.1
311 11:03:41.686872 - {TEE}: None
312 11:03:41.686919 Parsed boot commands:
313 11:03:41.686965 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:03:41.687102 Parsed boot commands: tftpboot 192.168.201.1 14786788/tftp-deploy-nbkabym0/kernel/image.itb 14786788/tftp-deploy-nbkabym0/kernel/cmdline
315 11:03:41.687179 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:03:41.687251 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:03:41.687321 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:03:41.687391 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:03:41.687470 Not connected, no need to disconnect.
320 11:03:41.687550 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:03:41.687616 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:03:41.687668 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 11:03:41.690670 Setting prompt string to ['lava-test: # ']
324 11:03:41.690989 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:03:41.691082 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:03:41.691174 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:03:41.691267 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:03:41.691453 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=reboot']
329 11:03:50.860780 >> Command sent successfully.
330 11:03:50.864883 Returned 0 in 9 seconds
331 11:03:50.865031 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 11:03:50.865229 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 11:03:50.865314 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 11:03:50.865382 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:03:50.865434 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:03:50.865492 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:03:50.865817 [Enter `^Ec?' for help]
339 11:03:52.490640
340 11:03:52.490773 F0: 102B 0000
341 11:03:52.490837
342 11:03:52.494154 F3: 1001 0000 [0200]
343 11:03:52.494233
344 11:03:52.494291 F3: 1001 0000
345 11:03:52.494347
346 11:03:52.494399 F7: 102D 0000
347 11:03:52.494449
348 11:03:52.498022 F1: 0000 0000
349 11:03:52.498131
350 11:03:52.498188 V0: 0000 0000 [0001]
351 11:03:52.498242
352 11:03:52.498315 00: 0007 8000
353 11:03:52.501471
354 11:03:52.501546 01: 0000 0000
355 11:03:52.501608
356 11:03:52.501662 BP: 0C00 0209 [0000]
357 11:03:52.501713
358 11:03:52.505125 G0: 1182 0000
359 11:03:52.505248
360 11:03:52.505307 EC: 0000 0021 [4000]
361 11:03:52.505360
362 11:03:52.508522 S7: 0000 0000 [0000]
363 11:03:52.508597
364 11:03:52.508654 CC: 0000 0000 [0001]
365 11:03:52.508708
366 11:03:52.511921 T0: 0000 0040 [010F]
367 11:03:52.511998
368 11:03:52.512056 Jump to BL
369 11:03:52.512108
370 11:03:52.537155
371 11:03:52.537277
372 11:03:52.547868 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 11:03:52.551123 ARM64: Exception handlers installed.
374 11:03:52.551208 ARM64: Testing exception
375 11:03:52.554379 ARM64: Done test exception
376 11:03:52.561663 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 11:03:52.571383 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 11:03:52.577857 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 11:03:52.588563 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 11:03:52.595195 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 11:03:52.605694 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 11:03:52.615139 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 11:03:52.622121 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 11:03:52.640493 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 11:03:52.643658 WDT: Last reset was cold boot
386 11:03:52.646914 SPI1(PAD0) initialized at 2873684 Hz
387 11:03:52.650261 SPI5(PAD0) initialized at 992727 Hz
388 11:03:52.653581 VBOOT: Loading verstage.
389 11:03:52.660655 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 11:03:52.663646 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 11:03:52.667862 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 11:03:52.670102 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 11:03:52.678435 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 11:03:52.684567 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 11:03:52.695624 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
396 11:03:52.695714
397 11:03:52.695778
398 11:03:52.705591 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 11:03:52.708829 ARM64: Exception handlers installed.
400 11:03:52.711746 ARM64: Testing exception
401 11:03:52.715392 ARM64: Done test exception
402 11:03:52.718843 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 11:03:52.721938 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 11:03:52.736377 Probing TPM: . done!
405 11:03:52.736489 TPM ready after 0 ms
406 11:03:52.743586 Connected to device vid:did:rid of 1ae0:0028:00
407 11:03:52.749859 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
408 11:03:52.790058 Initialized TPM device CR50 revision 0
409 11:03:52.802210 tlcl_send_startup: Startup return code is 0
410 11:03:52.802307 TPM: setup succeeded
411 11:03:52.813800 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 11:03:52.822174 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 11:03:52.832450 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 11:03:52.841003 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 11:03:52.844564 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 11:03:52.848268 in-header: 03 07 00 00 08 00 00 00
417 11:03:52.852119 in-data: aa e4 47 04 13 02 00 00
418 11:03:52.855198 Chrome EC: UHEPI supported
419 11:03:52.861822 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 11:03:52.865052 in-header: 03 a9 00 00 08 00 00 00
421 11:03:52.868053 in-data: 84 60 60 08 00 00 00 00
422 11:03:52.868135 Phase 1
423 11:03:52.875294 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 11:03:52.878411 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 11:03:52.885182 VB2:vb2_check_recovery() Recovery was requested manually
426 11:03:52.891752 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 11:03:52.891832 Recovery requested (1009000e)
428 11:03:52.900486 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 11:03:52.905456 tlcl_extend: response is 0
430 11:03:52.913975 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 11:03:52.918899 tlcl_extend: response is 0
432 11:03:52.925729 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 11:03:52.946435 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
434 11:03:52.953435 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 11:03:52.953529
436 11:03:52.953588
437 11:03:52.963603 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 11:03:52.967262 ARM64: Exception handlers installed.
439 11:03:52.967364 ARM64: Testing exception
440 11:03:52.970874 ARM64: Done test exception
441 11:03:52.991868 pmic_efuse_setting: Set efuses in 11 msecs
442 11:03:52.995374 pmwrap_interface_init: Select PMIF_VLD_RDY
443 11:03:53.001652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 11:03:53.005052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 11:03:53.011574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 11:03:53.014973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 11:03:53.021768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 11:03:53.025075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 11:03:53.028313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 11:03:53.035076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 11:03:53.038294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 11:03:53.044784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 11:03:53.047746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 11:03:53.054779 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 11:03:53.057953 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 11:03:53.064706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 11:03:53.070968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 11:03:53.074549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 11:03:53.081342 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 11:03:53.087774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 11:03:53.090828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 11:03:53.097597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 11:03:53.104152 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 11:03:53.107382 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 11:03:53.114951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 11:03:53.121014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 11:03:53.124193 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 11:03:53.130849 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 11:03:53.137637 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 11:03:53.141122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 11:03:53.147978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 11:03:53.150867 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 11:03:53.157240 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 11:03:53.160636 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 11:03:53.167699 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 11:03:53.170565 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 11:03:53.174101 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 11:03:53.180831 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 11:03:53.187750 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 11:03:53.190794 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 11:03:53.194089 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 11:03:53.198171 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 11:03:53.205297 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 11:03:53.208729 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 11:03:53.211276 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 11:03:53.218059 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 11:03:53.221133 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 11:03:53.224707 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 11:03:53.231268 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 11:03:53.234737 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 11:03:53.237978 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 11:03:53.241109 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 11:03:53.247919 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 11:03:53.254315 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
495 11:03:53.264553 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 11:03:53.267734 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 11:03:53.274415 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 11:03:53.284564 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 11:03:53.287564 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 11:03:53.294563 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 11:03:53.297529 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:03:53.304603 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x30
503 11:03:53.311211 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 11:03:53.314458 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
505 11:03:53.317801 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 11:03:53.329005 [RTC]rtc_get_frequency_meter,154: input=15, output=834
507 11:03:53.338742 [RTC]rtc_get_frequency_meter,154: input=7, output=710
508 11:03:53.348066 [RTC]rtc_get_frequency_meter,154: input=11, output=772
509 11:03:53.357303 [RTC]rtc_get_frequency_meter,154: input=13, output=804
510 11:03:53.367167 [RTC]rtc_get_frequency_meter,154: input=12, output=788
511 11:03:53.376589 [RTC]rtc_get_frequency_meter,154: input=12, output=788
512 11:03:53.385956 [RTC]rtc_get_frequency_meter,154: input=13, output=804
513 11:03:53.389471 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
514 11:03:53.396372 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
515 11:03:53.399951 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 11:03:53.403264 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 11:03:53.409929 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 11:03:53.413761 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 11:03:53.416599 ADC[4]: Raw value=905988 ID=7
520 11:03:53.416695 ADC[3]: Raw value=213282 ID=1
521 11:03:53.420425 RAM Code: 0x71
522 11:03:53.423331 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 11:03:53.429926 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 11:03:53.436525 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 11:03:53.443127 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 11:03:53.446320 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 11:03:53.449650 in-header: 03 07 00 00 08 00 00 00
528 11:03:53.452727 in-data: aa e4 47 04 13 02 00 00
529 11:03:53.456185 Chrome EC: UHEPI supported
530 11:03:53.462725 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 11:03:53.466227 in-header: 03 a9 00 00 08 00 00 00
532 11:03:53.469557 in-data: 84 60 60 08 00 00 00 00
533 11:03:53.472882 MRC: failed to locate region type 0.
534 11:03:53.479368 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 11:03:53.482724 DRAM-K: Running full calibration
536 11:03:53.489162 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 11:03:53.489244 header.status = 0x0
538 11:03:53.492794 header.version = 0x6 (expected: 0x6)
539 11:03:53.496081 header.size = 0xd00 (expected: 0xd00)
540 11:03:53.499606 header.flags = 0x0
541 11:03:53.505960 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 11:03:53.522776 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
543 11:03:53.529835 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 11:03:53.532854 dram_init: ddr_geometry: 2
545 11:03:53.535782 [EMI] MDL number = 2
546 11:03:53.535856 [EMI] Get MDL freq = 0
547 11:03:53.539386 dram_init: ddr_type: 0
548 11:03:53.539498 is_discrete_lpddr4: 1
549 11:03:53.542914 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 11:03:53.542991
551 11:03:53.543049
552 11:03:53.545774 [Bian_co] ETT version 0.0.0.1
553 11:03:53.552636 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 11:03:53.552718
555 11:03:53.556056 dramc_set_vcore_voltage set vcore to 650000
556 11:03:53.559417 Read voltage for 800, 4
557 11:03:53.559528 Vio18 = 0
558 11:03:53.559587 Vcore = 650000
559 11:03:53.562198 Vdram = 0
560 11:03:53.562282 Vddq = 0
561 11:03:53.562378 Vmddr = 0
562 11:03:53.565904 dram_init: config_dvfs: 1
563 11:03:53.569059 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 11:03:53.575781 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 11:03:53.579347 [SwImpedanceCal] DRVP=8, DRVN=15, ODTN=9
566 11:03:53.582557 freq_region=0, Reg: DRVP=8, DRVN=15, ODTN=9
567 11:03:53.585713 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
568 11:03:53.589157 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
569 11:03:53.592330 MEM_TYPE=3, freq_sel=18
570 11:03:53.595730 sv_algorithm_assistance_LP4_1600
571 11:03:53.599328 ============ PULL DRAM RESETB DOWN ============
572 11:03:53.602724 ========== PULL DRAM RESETB DOWN end =========
573 11:03:53.609133 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 11:03:53.612384 ===================================
575 11:03:53.616185 LPDDR4 DRAM CONFIGURATION
576 11:03:53.616265 ===================================
577 11:03:53.620127 EX_ROW_EN[0] = 0x0
578 11:03:53.620205 EX_ROW_EN[1] = 0x0
579 11:03:53.623840 LP4Y_EN = 0x0
580 11:03:53.623917 WORK_FSP = 0x0
581 11:03:53.627339 WL = 0x2
582 11:03:53.627414 RL = 0x2
583 11:03:53.630580 BL = 0x2
584 11:03:53.630656 RPST = 0x0
585 11:03:53.634514 RD_PRE = 0x0
586 11:03:53.634602 WR_PRE = 0x1
587 11:03:53.638796 WR_PST = 0x0
588 11:03:53.638876 DBI_WR = 0x0
589 11:03:53.641558 DBI_RD = 0x0
590 11:03:53.641637 OTF = 0x1
591 11:03:53.645189 ===================================
592 11:03:53.648432 ===================================
593 11:03:53.651564 ANA top config
594 11:03:53.655128 ===================================
595 11:03:53.655221 DLL_ASYNC_EN = 0
596 11:03:53.658086 ALL_SLAVE_EN = 1
597 11:03:53.661475 NEW_RANK_MODE = 1
598 11:03:53.664808 DLL_IDLE_MODE = 1
599 11:03:53.664885 LP45_APHY_COMB_EN = 1
600 11:03:53.668174 TX_ODT_DIS = 1
601 11:03:53.671562 NEW_8X_MODE = 1
602 11:03:53.674785 ===================================
603 11:03:53.678428 ===================================
604 11:03:53.681286 data_rate = 1600
605 11:03:53.684547 CKR = 1
606 11:03:53.687971 DQ_P2S_RATIO = 8
607 11:03:53.691348 ===================================
608 11:03:53.691436 CA_P2S_RATIO = 8
609 11:03:53.694586 DQ_CA_OPEN = 0
610 11:03:53.697715 DQ_SEMI_OPEN = 0
611 11:03:53.701359 CA_SEMI_OPEN = 0
612 11:03:53.704489 CA_FULL_RATE = 0
613 11:03:53.707909 DQ_CKDIV4_EN = 1
614 11:03:53.707987 CA_CKDIV4_EN = 1
615 11:03:53.711170 CA_PREDIV_EN = 0
616 11:03:53.714698 PH8_DLY = 0
617 11:03:53.717940 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 11:03:53.721114 DQ_AAMCK_DIV = 4
619 11:03:53.724821 CA_AAMCK_DIV = 4
620 11:03:53.724899 CA_ADMCK_DIV = 4
621 11:03:53.727979 DQ_TRACK_CA_EN = 0
622 11:03:53.731332 CA_PICK = 800
623 11:03:53.734602 CA_MCKIO = 800
624 11:03:53.738076 MCKIO_SEMI = 0
625 11:03:53.741348 PLL_FREQ = 3068
626 11:03:53.744357 DQ_UI_PI_RATIO = 32
627 11:03:53.744433 CA_UI_PI_RATIO = 0
628 11:03:53.747970 ===================================
629 11:03:53.751732 ===================================
630 11:03:53.754743 memory_type:LPDDR4
631 11:03:53.758001 GP_NUM : 10
632 11:03:53.758079 SRAM_EN : 1
633 11:03:53.761457 MD32_EN : 0
634 11:03:53.764628 ===================================
635 11:03:53.768090 [ANA_INIT] >>>>>>>>>>>>>>
636 11:03:53.768165 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 11:03:53.774519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 11:03:53.777869 ===================================
639 11:03:53.777948 data_rate = 1600,PCW = 0X7600
640 11:03:53.781032 ===================================
641 11:03:53.784139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 11:03:53.791070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 11:03:53.797894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 11:03:53.801061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 11:03:53.804219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 11:03:53.808012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 11:03:53.810831 [ANA_INIT] flow start
648 11:03:53.810911 [ANA_INIT] PLL >>>>>>>>
649 11:03:53.814115 [ANA_INIT] PLL <<<<<<<<
650 11:03:53.817619 [ANA_INIT] MIDPI >>>>>>>>
651 11:03:53.817694 [ANA_INIT] MIDPI <<<<<<<<
652 11:03:53.821426 [ANA_INIT] DLL >>>>>>>>
653 11:03:53.824554 [ANA_INIT] flow end
654 11:03:53.827664 ============ LP4 DIFF to SE enter ============
655 11:03:53.830881 ============ LP4 DIFF to SE exit ============
656 11:03:53.834275 [ANA_INIT] <<<<<<<<<<<<<
657 11:03:53.837642 [Flow] Enable top DCM control >>>>>
658 11:03:53.840961 [Flow] Enable top DCM control <<<<<
659 11:03:53.844531 Enable DLL master slave shuffle
660 11:03:53.847463 ==============================================================
661 11:03:53.851411 Gating Mode config
662 11:03:53.857803 ==============================================================
663 11:03:53.857886 Config description:
664 11:03:53.868019 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 11:03:53.874118 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 11:03:53.880911 SELPH_MODE 0: By rank 1: By Phase
667 11:03:53.884344 ==============================================================
668 11:03:53.887544 GAT_TRACK_EN = 1
669 11:03:53.890923 RX_GATING_MODE = 2
670 11:03:53.894356 RX_GATING_TRACK_MODE = 2
671 11:03:53.897422 SELPH_MODE = 1
672 11:03:53.901092 PICG_EARLY_EN = 1
673 11:03:53.904252 VALID_LAT_VALUE = 1
674 11:03:53.907394 ==============================================================
675 11:03:53.910857 Enter into Gating configuration >>>>
676 11:03:53.914143 Exit from Gating configuration <<<<
677 11:03:53.917830 Enter into DVFS_PRE_config >>>>>
678 11:03:53.930844 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 11:03:53.933933 Exit from DVFS_PRE_config <<<<<
680 11:03:53.934011 Enter into PICG configuration >>>>
681 11:03:53.937552 Exit from PICG configuration <<<<
682 11:03:53.940810 [RX_INPUT] configuration >>>>>
683 11:03:53.944253 [RX_INPUT] configuration <<<<<
684 11:03:53.950983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 11:03:53.954394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 11:03:53.960552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 11:03:53.966858 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 11:03:53.973434 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 11:03:53.980664 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 11:03:53.983823 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 11:03:53.986882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 11:03:53.990454 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 11:03:53.996900 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 11:03:54.000336 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 11:03:54.003727 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 11:03:54.007017 ===================================
697 11:03:54.010288 LPDDR4 DRAM CONFIGURATION
698 11:03:54.013417 ===================================
699 11:03:54.016542 EX_ROW_EN[0] = 0x0
700 11:03:54.016618 EX_ROW_EN[1] = 0x0
701 11:03:54.019998 LP4Y_EN = 0x0
702 11:03:54.020073 WORK_FSP = 0x0
703 11:03:54.023387 WL = 0x2
704 11:03:54.023500 RL = 0x2
705 11:03:54.026931 BL = 0x2
706 11:03:54.027012 RPST = 0x0
707 11:03:54.030036 RD_PRE = 0x0
708 11:03:54.030111 WR_PRE = 0x1
709 11:03:54.033253 WR_PST = 0x0
710 11:03:54.033328 DBI_WR = 0x0
711 11:03:54.036590 DBI_RD = 0x0
712 11:03:54.036665 OTF = 0x1
713 11:03:54.039825 ===================================
714 11:03:54.046634 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 11:03:54.049904 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 11:03:54.053207 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 11:03:54.056736 ===================================
718 11:03:54.059981 LPDDR4 DRAM CONFIGURATION
719 11:03:54.063347 ===================================
720 11:03:54.066950 EX_ROW_EN[0] = 0x10
721 11:03:54.067025 EX_ROW_EN[1] = 0x0
722 11:03:54.069911 LP4Y_EN = 0x0
723 11:03:54.069985 WORK_FSP = 0x0
724 11:03:54.073285 WL = 0x2
725 11:03:54.073359 RL = 0x2
726 11:03:54.076717 BL = 0x2
727 11:03:54.076792 RPST = 0x0
728 11:03:54.080016 RD_PRE = 0x0
729 11:03:54.080091 WR_PRE = 0x1
730 11:03:54.083267 WR_PST = 0x0
731 11:03:54.083341 DBI_WR = 0x0
732 11:03:54.086401 DBI_RD = 0x0
733 11:03:54.086475 OTF = 0x1
734 11:03:54.089901 ===================================
735 11:03:54.096724 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 11:03:54.100849 nWR fixed to 40
737 11:03:54.104145 [ModeRegInit_LP4] CH0 RK0
738 11:03:54.104221 [ModeRegInit_LP4] CH0 RK1
739 11:03:54.107337 [ModeRegInit_LP4] CH1 RK0
740 11:03:54.110794 [ModeRegInit_LP4] CH1 RK1
741 11:03:54.110886 match AC timing 13
742 11:03:54.117434 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 11:03:54.120720 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 11:03:54.124201 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 11:03:54.130853 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 11:03:54.134112 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 11:03:54.137551 [EMI DOE] emi_dcm 0
748 11:03:54.140695 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 11:03:54.140771 ==
750 11:03:54.144103 Dram Type= 6, Freq= 0, CH_0, rank 0
751 11:03:54.147266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 11:03:54.147382 ==
753 11:03:54.153953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 11:03:54.160256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 11:03:54.168276 [CA 0] Center 37 (7~68) winsize 62
756 11:03:54.171676 [CA 1] Center 37 (6~68) winsize 63
757 11:03:54.175723 [CA 2] Center 34 (4~65) winsize 62
758 11:03:54.178606 [CA 3] Center 34 (4~65) winsize 62
759 11:03:54.181760 [CA 4] Center 33 (3~64) winsize 62
760 11:03:54.185214 [CA 5] Center 33 (3~64) winsize 62
761 11:03:54.185307
762 11:03:54.188471 [CmdBusTrainingLP45] Vref(ca) range 1: 34
763 11:03:54.188546
764 11:03:54.192018 [CATrainingPosCal] consider 1 rank data
765 11:03:54.195402 u2DelayCellTimex100 = 270/100 ps
766 11:03:54.199257 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 11:03:54.202530 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
768 11:03:54.205798 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
769 11:03:54.209204 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 11:03:54.215333 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
771 11:03:54.218931 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 11:03:54.219007
773 11:03:54.222211 CA PerBit enable=1, Macro0, CA PI delay=33
774 11:03:54.222287
775 11:03:54.225481 [CBTSetCACLKResult] CA Dly = 33
776 11:03:54.225568 CS Dly: 6 (0~37)
777 11:03:54.225626 ==
778 11:03:54.228608 Dram Type= 6, Freq= 0, CH_0, rank 1
779 11:03:54.235761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:03:54.235852 ==
781 11:03:54.238830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 11:03:54.245512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 11:03:54.254839 [CA 0] Center 37 (6~68) winsize 63
784 11:03:54.258095 [CA 1] Center 37 (7~68) winsize 62
785 11:03:54.261095 [CA 2] Center 34 (4~65) winsize 62
786 11:03:54.264585 [CA 3] Center 34 (4~65) winsize 62
787 11:03:54.268102 [CA 4] Center 33 (3~64) winsize 62
788 11:03:54.271561 [CA 5] Center 33 (3~64) winsize 62
789 11:03:54.271636
790 11:03:54.274555 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 11:03:54.274630
792 11:03:54.277837 [CATrainingPosCal] consider 2 rank data
793 11:03:54.281034 u2DelayCellTimex100 = 270/100 ps
794 11:03:54.284605 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 11:03:54.288192 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 11:03:54.294783 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
797 11:03:54.297587 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 11:03:54.301175 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
799 11:03:54.304669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 11:03:54.304767
801 11:03:54.307743 CA PerBit enable=1, Macro0, CA PI delay=33
802 11:03:54.307837
803 11:03:54.310841 [CBTSetCACLKResult] CA Dly = 33
804 11:03:54.310931 CS Dly: 6 (0~38)
805 11:03:54.311011
806 11:03:54.317818 ----->DramcWriteLeveling(PI) begin...
807 11:03:54.317923 ==
808 11:03:54.320963 Dram Type= 6, Freq= 0, CH_0, rank 0
809 11:03:54.324277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 11:03:54.324371 ==
811 11:03:54.327555 Write leveling (Byte 0): 31 => 31
812 11:03:54.330935 Write leveling (Byte 1): 29 => 29
813 11:03:54.334164 DramcWriteLeveling(PI) end<-----
814 11:03:54.334286
815 11:03:54.334382 ==
816 11:03:54.337612 Dram Type= 6, Freq= 0, CH_0, rank 0
817 11:03:54.340908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 11:03:54.341010 ==
819 11:03:54.344416 [Gating] SW mode calibration
820 11:03:54.350685 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 11:03:54.357432 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 11:03:54.361014 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 11:03:54.364315 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 11:03:54.371323 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 11:03:54.374333 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 11:03:54.377283 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:03:54.380714 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:03:54.387170 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:03:54.390984 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:03:54.394413 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:03:54.400799 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:03:54.403947 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:03:54.407355 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:03:54.414161 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 11:03:54.417348 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:03:54.420516 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:03:54.427028 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:03:54.430223 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:03:54.433634 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
840 11:03:54.440395 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
841 11:03:54.443645 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 11:03:54.446986 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:03:54.453934 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:03:54.457053 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:03:54.460250 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:03:54.467009 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:03:54.470305 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:03:54.473472 0 9 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
849 11:03:54.480137 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
850 11:03:54.483320 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 11:03:54.486831 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 11:03:54.493298 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 11:03:54.496869 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 11:03:54.500144 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 11:03:54.506574 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
856 11:03:54.510200 0 10 8 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 0)
857 11:03:54.513498 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
858 11:03:54.519779 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:03:54.523100 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:03:54.526538 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:03:54.533409 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:03:54.536623 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:03:54.540479 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:03:54.546557 0 11 8 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
865 11:03:54.549798 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
866 11:03:54.553562 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 11:03:54.556781 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:03:54.563400 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:03:54.566850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:03:54.569910 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 11:03:54.576478 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:03:54.579974 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 11:03:54.583393 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
874 11:03:54.589811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 11:03:54.593321 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:03:54.596618 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:03:54.603190 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:03:54.606869 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:03:54.610283 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:03:54.616508 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:03:54.620070 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:03:54.623062 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:03:54.630014 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:03:54.633073 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:03:54.636855 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 11:03:54.643094 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 11:03:54.646021 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 11:03:54.649464 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
889 11:03:54.656004 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 11:03:54.656085 Total UI for P1: 0, mck2ui 16
891 11:03:54.662886 best dqsien dly found for B0: ( 0, 14, 8)
892 11:03:54.662964 Total UI for P1: 0, mck2ui 16
893 11:03:54.669167 best dqsien dly found for B1: ( 0, 14, 8)
894 11:03:54.672883 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
895 11:03:54.675852 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
896 11:03:54.675929
897 11:03:54.679225 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
898 11:03:54.682445 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 11:03:54.686006 [Gating] SW calibration Done
900 11:03:54.686136 ==
901 11:03:54.689007 Dram Type= 6, Freq= 0, CH_0, rank 0
902 11:03:54.692722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 11:03:54.692800 ==
904 11:03:54.695691 RX Vref Scan: 0
905 11:03:54.695769
906 11:03:54.695827 RX Vref 0 -> 0, step: 1
907 11:03:54.695882
908 11:03:54.699066 RX Delay -130 -> 252, step: 16
909 11:03:54.702607 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
910 11:03:54.709220 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
911 11:03:54.712620 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
912 11:03:54.715820 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
913 11:03:54.719170 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
914 11:03:54.722390 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
915 11:03:54.728898 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
916 11:03:54.732199 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
917 11:03:54.735538 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
918 11:03:54.738939 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
919 11:03:54.742448 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
920 11:03:54.749185 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
921 11:03:54.752328 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
922 11:03:54.756034 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
923 11:03:54.759241 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
924 11:03:54.762494 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
925 11:03:54.765604 ==
926 11:03:54.765706 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:03:54.772064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:03:54.772150 ==
929 11:03:54.772210 DQS Delay:
930 11:03:54.775370 DQS0 = 0, DQS1 = 0
931 11:03:54.775489 DQM Delay:
932 11:03:54.778625 DQM0 = 86, DQM1 = 75
933 11:03:54.778701 DQ Delay:
934 11:03:54.782144 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
935 11:03:54.785858 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
936 11:03:54.788886 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
937 11:03:54.791888 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
938 11:03:54.791965
939 11:03:54.792024
940 11:03:54.792077 ==
941 11:03:54.795288 Dram Type= 6, Freq= 0, CH_0, rank 0
942 11:03:54.798726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
943 11:03:54.798826 ==
944 11:03:54.798940
945 11:03:54.799053
946 11:03:54.801946 TX Vref Scan disable
947 11:03:54.805621 == TX Byte 0 ==
948 11:03:54.808382 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
949 11:03:54.812194 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
950 11:03:54.815337 == TX Byte 1 ==
951 11:03:54.818472 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
952 11:03:54.821942 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
953 11:03:54.822022 ==
954 11:03:54.825172 Dram Type= 6, Freq= 0, CH_0, rank 0
955 11:03:54.831802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 11:03:54.831960 ==
957 11:03:54.843635 TX Vref=22, minBit 3, minWin=27, winSum=441
958 11:03:54.846795 TX Vref=24, minBit 5, minWin=27, winSum=444
959 11:03:54.849700 TX Vref=26, minBit 8, minWin=27, winSum=444
960 11:03:54.853079 TX Vref=28, minBit 10, minWin=27, winSum=451
961 11:03:54.856207 TX Vref=30, minBit 4, minWin=27, winSum=451
962 11:03:54.863196 TX Vref=32, minBit 11, minWin=26, winSum=443
963 11:03:54.866558 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 28
964 11:03:54.866675
965 11:03:54.869447 Final TX Range 1 Vref 28
966 11:03:54.869528
967 11:03:54.869608 ==
968 11:03:54.872811 Dram Type= 6, Freq= 0, CH_0, rank 0
969 11:03:54.879338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 11:03:54.879420 ==
971 11:03:54.879515
972 11:03:54.879606
973 11:03:54.879678 TX Vref Scan disable
974 11:03:54.883555 == TX Byte 0 ==
975 11:03:54.887003 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
976 11:03:54.893380 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
977 11:03:54.893463 == TX Byte 1 ==
978 11:03:54.896970 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
979 11:03:54.903307 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
980 11:03:54.903490
981 11:03:54.903576 [DATLAT]
982 11:03:54.903670 Freq=800, CH0 RK0
983 11:03:54.903782
984 11:03:54.906554 DATLAT Default: 0xa
985 11:03:54.906653 0, 0xFFFF, sum = 0
986 11:03:54.909751 1, 0xFFFF, sum = 0
987 11:03:54.912928 2, 0xFFFF, sum = 0
988 11:03:54.913045 3, 0xFFFF, sum = 0
989 11:03:54.916511 4, 0xFFFF, sum = 0
990 11:03:54.916626 5, 0xFFFF, sum = 0
991 11:03:54.920044 6, 0xFFFF, sum = 0
992 11:03:54.920172 7, 0xFFFF, sum = 0
993 11:03:54.922922 8, 0xFFFF, sum = 0
994 11:03:54.923066 9, 0x0, sum = 1
995 11:03:54.926675 10, 0x0, sum = 2
996 11:03:54.926818 11, 0x0, sum = 3
997 11:03:54.929682 12, 0x0, sum = 4
998 11:03:54.929844 best_step = 10
999 11:03:54.929969
1000 11:03:54.930085 ==
1001 11:03:54.933025 Dram Type= 6, Freq= 0, CH_0, rank 0
1002 11:03:54.936424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1003 11:03:54.936686 ==
1004 11:03:54.939938 RX Vref Scan: 1
1005 11:03:54.940132
1006 11:03:54.943280 Set Vref Range= 32 -> 127
1007 11:03:54.943462
1008 11:03:54.943595 RX Vref 32 -> 127, step: 1
1009 11:03:54.943714
1010 11:03:54.946741 RX Delay -111 -> 252, step: 8
1011 11:03:54.946903
1012 11:03:54.949825 Set Vref, RX VrefLevel [Byte0]: 32
1013 11:03:54.953040 [Byte1]: 32
1014 11:03:54.956240
1015 11:03:54.956413 Set Vref, RX VrefLevel [Byte0]: 33
1016 11:03:54.959560 [Byte1]: 33
1017 11:03:54.964224
1018 11:03:54.964316 Set Vref, RX VrefLevel [Byte0]: 34
1019 11:03:54.967017 [Byte1]: 34
1020 11:03:54.971827
1021 11:03:54.971922 Set Vref, RX VrefLevel [Byte0]: 35
1022 11:03:54.974943 [Byte1]: 35
1023 11:03:54.978971
1024 11:03:54.979048 Set Vref, RX VrefLevel [Byte0]: 36
1025 11:03:54.982495 [Byte1]: 36
1026 11:03:54.987552
1027 11:03:54.987640 Set Vref, RX VrefLevel [Byte0]: 37
1028 11:03:54.990198 [Byte1]: 37
1029 11:03:54.994686
1030 11:03:54.994784 Set Vref, RX VrefLevel [Byte0]: 38
1031 11:03:54.997808 [Byte1]: 38
1032 11:03:55.002031
1033 11:03:55.002115 Set Vref, RX VrefLevel [Byte0]: 39
1034 11:03:55.005475 [Byte1]: 39
1035 11:03:55.009902
1036 11:03:55.010012 Set Vref, RX VrefLevel [Byte0]: 40
1037 11:03:55.013106 [Byte1]: 40
1038 11:03:55.017289
1039 11:03:55.017383 Set Vref, RX VrefLevel [Byte0]: 41
1040 11:03:55.020625 [Byte1]: 41
1041 11:03:55.025548
1042 11:03:55.025633 Set Vref, RX VrefLevel [Byte0]: 42
1043 11:03:55.028565 [Byte1]: 42
1044 11:03:55.033005
1045 11:03:55.033127 Set Vref, RX VrefLevel [Byte0]: 43
1046 11:03:55.035885 [Byte1]: 43
1047 11:03:55.040452
1048 11:03:55.040538 Set Vref, RX VrefLevel [Byte0]: 44
1049 11:03:55.043789 [Byte1]: 44
1050 11:03:55.048096
1051 11:03:55.048179 Set Vref, RX VrefLevel [Byte0]: 45
1052 11:03:55.051236 [Byte1]: 45
1053 11:03:55.055874
1054 11:03:55.055998 Set Vref, RX VrefLevel [Byte0]: 46
1055 11:03:55.059061 [Byte1]: 46
1056 11:03:55.063627
1057 11:03:55.063758 Set Vref, RX VrefLevel [Byte0]: 47
1058 11:03:55.066453 [Byte1]: 47
1059 11:03:55.071018
1060 11:03:55.071150 Set Vref, RX VrefLevel [Byte0]: 48
1061 11:03:55.074393 [Byte1]: 48
1062 11:03:55.078457
1063 11:03:55.078575 Set Vref, RX VrefLevel [Byte0]: 49
1064 11:03:55.081668 [Byte1]: 49
1065 11:03:55.086394
1066 11:03:55.086539 Set Vref, RX VrefLevel [Byte0]: 50
1067 11:03:55.089819 [Byte1]: 50
1068 11:03:55.093851
1069 11:03:55.094000 Set Vref, RX VrefLevel [Byte0]: 51
1070 11:03:55.097612 [Byte1]: 51
1071 11:03:55.101761
1072 11:03:55.101840 Set Vref, RX VrefLevel [Byte0]: 52
1073 11:03:55.108140 [Byte1]: 52
1074 11:03:55.108219
1075 11:03:55.111055 Set Vref, RX VrefLevel [Byte0]: 53
1076 11:03:55.114595 [Byte1]: 53
1077 11:03:55.114747
1078 11:03:55.118179 Set Vref, RX VrefLevel [Byte0]: 54
1079 11:03:55.121685 [Byte1]: 54
1080 11:03:55.121842
1081 11:03:55.124567 Set Vref, RX VrefLevel [Byte0]: 55
1082 11:03:55.128014 [Byte1]: 55
1083 11:03:55.131932
1084 11:03:55.132052 Set Vref, RX VrefLevel [Byte0]: 56
1085 11:03:55.135206 [Byte1]: 56
1086 11:03:55.139783
1087 11:03:55.139887 Set Vref, RX VrefLevel [Byte0]: 57
1088 11:03:55.143264 [Byte1]: 57
1089 11:03:55.147377
1090 11:03:55.147527 Set Vref, RX VrefLevel [Byte0]: 58
1091 11:03:55.151000 [Byte1]: 58
1092 11:03:55.154915
1093 11:03:55.155030 Set Vref, RX VrefLevel [Byte0]: 59
1094 11:03:55.158310 [Byte1]: 59
1095 11:03:55.162651
1096 11:03:55.162809 Set Vref, RX VrefLevel [Byte0]: 60
1097 11:03:55.166083 [Byte1]: 60
1098 11:03:55.170607
1099 11:03:55.170691 Set Vref, RX VrefLevel [Byte0]: 61
1100 11:03:55.173809 [Byte1]: 61
1101 11:03:55.177797
1102 11:03:55.177876 Set Vref, RX VrefLevel [Byte0]: 62
1103 11:03:55.181570 [Byte1]: 62
1104 11:03:55.185410
1105 11:03:55.185488 Set Vref, RX VrefLevel [Byte0]: 63
1106 11:03:55.188861 [Byte1]: 63
1107 11:03:55.193624
1108 11:03:55.193704 Set Vref, RX VrefLevel [Byte0]: 64
1109 11:03:55.196427 [Byte1]: 64
1110 11:03:55.200930
1111 11:03:55.201014 Set Vref, RX VrefLevel [Byte0]: 65
1112 11:03:55.207242 [Byte1]: 65
1113 11:03:55.207332
1114 11:03:55.210808 Set Vref, RX VrefLevel [Byte0]: 66
1115 11:03:55.214300 [Byte1]: 66
1116 11:03:55.214409
1117 11:03:55.217203 Set Vref, RX VrefLevel [Byte0]: 67
1118 11:03:55.220899 [Byte1]: 67
1119 11:03:55.221018
1120 11:03:55.223960 Set Vref, RX VrefLevel [Byte0]: 68
1121 11:03:55.227378 [Byte1]: 68
1122 11:03:55.231491
1123 11:03:55.231666 Set Vref, RX VrefLevel [Byte0]: 69
1124 11:03:55.235063 [Byte1]: 69
1125 11:03:55.239383
1126 11:03:55.239618 Set Vref, RX VrefLevel [Byte0]: 70
1127 11:03:55.242496 [Byte1]: 70
1128 11:03:55.247126
1129 11:03:55.247298 Set Vref, RX VrefLevel [Byte0]: 71
1130 11:03:55.249928 [Byte1]: 71
1131 11:03:55.254576
1132 11:03:55.254739 Set Vref, RX VrefLevel [Byte0]: 72
1133 11:03:55.257720 [Byte1]: 72
1134 11:03:55.262123
1135 11:03:55.262249 Set Vref, RX VrefLevel [Byte0]: 73
1136 11:03:55.265370 [Byte1]: 73
1137 11:03:55.269938
1138 11:03:55.270017 Set Vref, RX VrefLevel [Byte0]: 74
1139 11:03:55.272841 [Byte1]: 74
1140 11:03:55.277334
1141 11:03:55.277412 Set Vref, RX VrefLevel [Byte0]: 75
1142 11:03:55.280698 [Byte1]: 75
1143 11:03:55.285348
1144 11:03:55.285426 Set Vref, RX VrefLevel [Byte0]: 76
1145 11:03:55.288097 [Byte1]: 76
1146 11:03:55.292652
1147 11:03:55.292789 Set Vref, RX VrefLevel [Byte0]: 77
1148 11:03:55.295939 [Byte1]: 77
1149 11:03:55.300636
1150 11:03:55.300726 Set Vref, RX VrefLevel [Byte0]: 78
1151 11:03:55.306746 [Byte1]: 78
1152 11:03:55.306844
1153 11:03:55.310483 Set Vref, RX VrefLevel [Byte0]: 79
1154 11:03:55.313918 [Byte1]: 79
1155 11:03:55.314037
1156 11:03:55.316719 Set Vref, RX VrefLevel [Byte0]: 80
1157 11:03:55.320257 [Byte1]: 80
1158 11:03:55.320387
1159 11:03:55.323941 Set Vref, RX VrefLevel [Byte0]: 81
1160 11:03:55.327189 [Byte1]: 81
1161 11:03:55.331140
1162 11:03:55.331305 Final RX Vref Byte 0 = 62 to rank0
1163 11:03:55.334149 Final RX Vref Byte 1 = 53 to rank0
1164 11:03:55.337787 Final RX Vref Byte 0 = 62 to rank1
1165 11:03:55.341123 Final RX Vref Byte 1 = 53 to rank1==
1166 11:03:55.344127 Dram Type= 6, Freq= 0, CH_0, rank 0
1167 11:03:55.351389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 11:03:55.351762 ==
1169 11:03:55.352184 DQS Delay:
1170 11:03:55.352500 DQS0 = 0, DQS1 = 0
1171 11:03:55.354299 DQM Delay:
1172 11:03:55.354634 DQM0 = 87, DQM1 = 76
1173 11:03:55.357835 DQ Delay:
1174 11:03:55.361215 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1175 11:03:55.364497 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1176 11:03:55.367584 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1177 11:03:55.370966 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1178 11:03:55.371305
1179 11:03:55.371725
1180 11:03:55.377799 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
1181 11:03:55.381006 CH0 RK0: MR19=606, MR18=4C2D
1182 11:03:55.387904 CH0_RK0: MR19=0x606, MR18=0x4C2D, DQSOSC=390, MR23=63, INC=97, DEC=64
1183 11:03:55.388261
1184 11:03:55.391115 ----->DramcWriteLeveling(PI) begin...
1185 11:03:55.391512 ==
1186 11:03:55.394110 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 11:03:55.397959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 11:03:55.398379 ==
1189 11:03:55.400829 Write leveling (Byte 0): 33 => 33
1190 11:03:55.404079 Write leveling (Byte 1): 32 => 32
1191 11:03:55.448325 DramcWriteLeveling(PI) end<-----
1192 11:03:55.448769
1193 11:03:55.449054 ==
1194 11:03:55.449311 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 11:03:55.449876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 11:03:55.450157 ==
1197 11:03:55.450400 [Gating] SW mode calibration
1198 11:03:55.450693 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1199 11:03:55.451099 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1200 11:03:55.451559 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1201 11:03:55.451833 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1202 11:03:55.452074 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1203 11:03:55.452384 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1204 11:03:55.454248 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:03:55.457752 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:03:55.460567 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:03:55.463910 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:03:55.470542 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:03:55.474050 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:03:55.477157 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:03:55.483855 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:03:55.487195 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:03:55.490918 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 11:03:55.497099 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:03:55.500620 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:03:55.503911 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:03:55.510422 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:03:55.513899 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:03:55.516841 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1220 11:03:55.524127 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:03:55.527047 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:03:55.530418 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:03:55.536666 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:03:55.540054 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:03:55.543573 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:03:55.550322 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1227 11:03:55.553360 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1228 11:03:55.556865 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 11:03:55.563196 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 11:03:55.566474 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 11:03:55.569853 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 11:03:55.573258 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 11:03:55.579930 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 11:03:55.583224 0 10 8 | B1->B0 | 3030 2929 | 0 0 | (1 1) (1 1)
1235 11:03:55.586612 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1236 11:03:55.593100 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:03:55.596513 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:03:55.600443 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:03:55.606515 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:03:55.609822 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:03:55.613182 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1242 11:03:55.619996 0 11 8 | B1->B0 | 2c2c 3e3e | 1 0 | (0 0) (0 0)
1243 11:03:55.622921 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1244 11:03:55.626365 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 11:03:55.632645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 11:03:55.636266 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 11:03:55.639582 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 11:03:55.646230 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 11:03:55.649416 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1250 11:03:55.652811 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1251 11:03:55.659490 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1252 11:03:55.662846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 11:03:55.666215 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 11:03:55.672782 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 11:03:55.676110 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 11:03:55.679627 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 11:03:55.686342 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 11:03:55.689825 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 11:03:55.692761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 11:03:55.699295 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 11:03:55.702624 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 11:03:55.706631 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 11:03:55.712753 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:03:55.716158 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:03:55.720001 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1266 11:03:55.726012 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1267 11:03:55.729627 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:03:55.732584 Total UI for P1: 0, mck2ui 16
1269 11:03:55.735970 best dqsien dly found for B0: ( 0, 14, 8)
1270 11:03:55.739494 Total UI for P1: 0, mck2ui 16
1271 11:03:55.742561 best dqsien dly found for B1: ( 0, 14, 6)
1272 11:03:55.745967 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1273 11:03:55.748916 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1274 11:03:55.748994
1275 11:03:55.752322 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1276 11:03:55.755382 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1277 11:03:55.758754 [Gating] SW calibration Done
1278 11:03:55.758831 ==
1279 11:03:55.762212 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 11:03:55.765877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 11:03:55.765951 ==
1282 11:03:55.769103 RX Vref Scan: 0
1283 11:03:55.769204
1284 11:03:55.772645 RX Vref 0 -> 0, step: 1
1285 11:03:55.772743
1286 11:03:55.772814 RX Delay -130 -> 252, step: 16
1287 11:03:55.778920 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1288 11:03:55.782340 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1289 11:03:55.785180 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1290 11:03:55.789052 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1291 11:03:55.792386 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1292 11:03:55.798567 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1293 11:03:55.802032 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1294 11:03:55.805262 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1295 11:03:55.808931 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1296 11:03:55.811872 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1297 11:03:55.818992 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1298 11:03:55.822027 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1299 11:03:55.825256 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1300 11:03:55.828454 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1301 11:03:55.835168 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1302 11:03:55.838548 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1303 11:03:55.838644 ==
1304 11:03:55.841536 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 11:03:55.845068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 11:03:55.845172 ==
1307 11:03:55.845253 DQS Delay:
1308 11:03:55.848574 DQS0 = 0, DQS1 = 0
1309 11:03:55.848687 DQM Delay:
1310 11:03:55.851995 DQM0 = 83, DQM1 = 78
1311 11:03:55.852108 DQ Delay:
1312 11:03:55.855412 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1313 11:03:55.858513 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1314 11:03:55.861945 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1315 11:03:55.865409 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1316 11:03:55.865570
1317 11:03:55.865694
1318 11:03:55.865807 ==
1319 11:03:55.868269 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 11:03:55.872032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 11:03:55.875357 ==
1322 11:03:55.875612
1323 11:03:55.875786
1324 11:03:55.875948 TX Vref Scan disable
1325 11:03:55.878520 == TX Byte 0 ==
1326 11:03:55.881759 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1327 11:03:55.885111 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1328 11:03:55.888313 == TX Byte 1 ==
1329 11:03:55.891735 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1330 11:03:55.895062 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1331 11:03:55.898332 ==
1332 11:03:55.902055 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 11:03:55.905103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 11:03:55.905468 ==
1335 11:03:55.917275 TX Vref=22, minBit 3, minWin=27, winSum=444
1336 11:03:55.920720 TX Vref=24, minBit 10, minWin=27, winSum=448
1337 11:03:55.924021 TX Vref=26, minBit 5, minWin=27, winSum=446
1338 11:03:55.927336 TX Vref=28, minBit 3, minWin=27, winSum=449
1339 11:03:55.930720 TX Vref=30, minBit 9, minWin=27, winSum=447
1340 11:03:55.937097 TX Vref=32, minBit 9, minWin=27, winSum=446
1341 11:03:55.940555 [TxChooseVref] Worse bit 3, Min win 27, Win sum 449, Final Vref 28
1342 11:03:55.940944
1343 11:03:55.943937 Final TX Range 1 Vref 28
1344 11:03:55.944368
1345 11:03:55.944677 ==
1346 11:03:55.947161 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 11:03:55.950896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 11:03:55.953484 ==
1349 11:03:55.953756
1350 11:03:55.953969
1351 11:03:55.954163 TX Vref Scan disable
1352 11:03:55.957374 == TX Byte 0 ==
1353 11:03:55.960674 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1354 11:03:55.967215 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1355 11:03:55.967382 == TX Byte 1 ==
1356 11:03:55.970787 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1357 11:03:55.973594 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1358 11:03:55.977364
1359 11:03:55.977483 [DATLAT]
1360 11:03:55.977585 Freq=800, CH0 RK1
1361 11:03:55.977668
1362 11:03:55.980196 DATLAT Default: 0xa
1363 11:03:55.980302 0, 0xFFFF, sum = 0
1364 11:03:55.983671 1, 0xFFFF, sum = 0
1365 11:03:55.983766 2, 0xFFFF, sum = 0
1366 11:03:55.987019 3, 0xFFFF, sum = 0
1367 11:03:55.987114 4, 0xFFFF, sum = 0
1368 11:03:55.990776 5, 0xFFFF, sum = 0
1369 11:03:55.993568 6, 0xFFFF, sum = 0
1370 11:03:55.993654 7, 0xFFFF, sum = 0
1371 11:03:55.996932 8, 0xFFFF, sum = 0
1372 11:03:55.997018 9, 0x0, sum = 1
1373 11:03:55.997085 10, 0x0, sum = 2
1374 11:03:56.000400 11, 0x0, sum = 3
1375 11:03:56.000486 12, 0x0, sum = 4
1376 11:03:56.003767 best_step = 10
1377 11:03:56.003842
1378 11:03:56.003901 ==
1379 11:03:56.006813 Dram Type= 6, Freq= 0, CH_0, rank 1
1380 11:03:56.010109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 11:03:56.010184 ==
1382 11:03:56.013482 RX Vref Scan: 0
1383 11:03:56.013558
1384 11:03:56.013616 RX Vref 0 -> 0, step: 1
1385 11:03:56.016935
1386 11:03:56.017010 RX Delay -95 -> 252, step: 8
1387 11:03:56.023878 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1388 11:03:56.026821 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1389 11:03:56.030283 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1390 11:03:56.033797 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1391 11:03:56.037060 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1392 11:03:56.043533 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1393 11:03:56.046922 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1394 11:03:56.050292 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1395 11:03:56.054098 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1396 11:03:56.057013 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1397 11:03:56.063812 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1398 11:03:56.067287 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1399 11:03:56.070726 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1400 11:03:56.073853 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1401 11:03:56.077332 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1402 11:03:56.083963 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1403 11:03:56.084452 ==
1404 11:03:56.087500 Dram Type= 6, Freq= 0, CH_0, rank 1
1405 11:03:56.090589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 11:03:56.091044 ==
1407 11:03:56.091486 DQS Delay:
1408 11:03:56.093744 DQS0 = 0, DQS1 = 0
1409 11:03:56.094167 DQM Delay:
1410 11:03:56.097321 DQM0 = 85, DQM1 = 76
1411 11:03:56.097765 DQ Delay:
1412 11:03:56.100691 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1413 11:03:56.104370 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1414 11:03:56.107698 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1415 11:03:56.111025 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1416 11:03:56.111378
1417 11:03:56.111683
1418 11:03:56.117175 [DQSOSCAuto] RK1, (LSB)MR18= 0x450b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
1419 11:03:56.120530 CH0 RK1: MR19=606, MR18=450B
1420 11:03:56.127518 CH0_RK1: MR19=0x606, MR18=0x450B, DQSOSC=392, MR23=63, INC=96, DEC=64
1421 11:03:56.130659 [RxdqsGatingPostProcess] freq 800
1422 11:03:56.137479 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1423 11:03:56.140504 Pre-setting of DQS Precalculation
1424 11:03:56.143757 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1425 11:03:56.144131 ==
1426 11:03:56.147135 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 11:03:56.150861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 11:03:56.151220 ==
1429 11:03:56.157039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1430 11:03:56.163481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1431 11:03:56.172458 [CA 0] Center 36 (6~67) winsize 62
1432 11:03:56.175862 [CA 1] Center 36 (6~67) winsize 62
1433 11:03:56.179097 [CA 2] Center 34 (4~65) winsize 62
1434 11:03:56.182559 [CA 3] Center 34 (3~65) winsize 63
1435 11:03:56.185883 [CA 4] Center 34 (4~65) winsize 62
1436 11:03:56.189399 [CA 5] Center 34 (3~65) winsize 63
1437 11:03:56.189787
1438 11:03:56.192276 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1439 11:03:56.192662
1440 11:03:56.195522 [CATrainingPosCal] consider 1 rank data
1441 11:03:56.198963 u2DelayCellTimex100 = 270/100 ps
1442 11:03:56.202308 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1443 11:03:56.205862 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1444 11:03:56.211663 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1445 11:03:56.215090 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1446 11:03:56.218700 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1447 11:03:56.221602 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1448 11:03:56.221683
1449 11:03:56.225357 CA PerBit enable=1, Macro0, CA PI delay=34
1450 11:03:56.225444
1451 11:03:56.228569 [CBTSetCACLKResult] CA Dly = 34
1452 11:03:56.228663 CS Dly: 5 (0~36)
1453 11:03:56.231922 ==
1454 11:03:56.235305 Dram Type= 6, Freq= 0, CH_1, rank 1
1455 11:03:56.238211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 11:03:56.238325 ==
1457 11:03:56.241575 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1458 11:03:56.248355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1459 11:03:56.258296 [CA 0] Center 36 (6~67) winsize 62
1460 11:03:56.261627 [CA 1] Center 37 (6~68) winsize 63
1461 11:03:56.264985 [CA 2] Center 34 (4~65) winsize 62
1462 11:03:56.268111 [CA 3] Center 34 (4~65) winsize 62
1463 11:03:56.271355 [CA 4] Center 34 (4~65) winsize 62
1464 11:03:56.275282 [CA 5] Center 33 (3~64) winsize 62
1465 11:03:56.275713
1466 11:03:56.278180 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1467 11:03:56.278536
1468 11:03:56.281699 [CATrainingPosCal] consider 2 rank data
1469 11:03:56.285188 u2DelayCellTimex100 = 270/100 ps
1470 11:03:56.288573 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1471 11:03:56.291841 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1472 11:03:56.298570 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1473 11:03:56.301734 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1474 11:03:56.304800 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1475 11:03:56.308559 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1476 11:03:56.308916
1477 11:03:56.311881 CA PerBit enable=1, Macro0, CA PI delay=33
1478 11:03:56.312239
1479 11:03:56.315309 [CBTSetCACLKResult] CA Dly = 33
1480 11:03:56.315690 CS Dly: 6 (0~38)
1481 11:03:56.315969
1482 11:03:56.318164 ----->DramcWriteLeveling(PI) begin...
1483 11:03:56.321607 ==
1484 11:03:56.321960 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 11:03:56.328407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1486 11:03:56.328762 ==
1487 11:03:56.332006 Write leveling (Byte 0): 28 => 28
1488 11:03:56.335290 Write leveling (Byte 1): 28 => 28
1489 11:03:56.338712 DramcWriteLeveling(PI) end<-----
1490 11:03:56.339063
1491 11:03:56.339337 ==
1492 11:03:56.342079 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 11:03:56.345249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 11:03:56.345615 ==
1495 11:03:56.348820 [Gating] SW mode calibration
1496 11:03:56.354919 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1497 11:03:56.358396 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1498 11:03:56.365020 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1499 11:03:56.368713 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1500 11:03:56.371595 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:03:56.378523 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:03:56.382101 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:03:56.385215 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:03:56.391963 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:03:56.395041 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:03:56.398440 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 11:03:56.404821 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:03:56.408669 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:03:56.411365 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:03:56.417885 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 11:03:56.421513 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:03:56.424757 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:03:56.431582 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:03:56.435035 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1515 11:03:56.438150 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1516 11:03:56.444466 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:03:56.448238 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:03:56.451079 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:03:56.458136 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:03:56.461422 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:03:56.464484 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:03:56.471529 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:03:56.474426 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:03:56.477812 0 9 8 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (0 0)
1525 11:03:56.484533 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 11:03:56.487957 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 11:03:56.491213 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 11:03:56.494741 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 11:03:56.501653 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 11:03:56.504626 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 11:03:56.507977 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (0 0) (0 1)
1532 11:03:56.514251 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1533 11:03:56.517713 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:03:56.521023 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:03:56.527389 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:03:56.530857 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:03:56.534399 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:03:56.541044 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:03:56.544382 0 11 4 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
1540 11:03:56.547750 0 11 8 | B1->B0 | 3939 3a3a | 1 0 | (0 0) (0 0)
1541 11:03:56.554490 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 11:03:56.557814 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 11:03:56.560587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 11:03:56.567494 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 11:03:56.571157 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 11:03:56.574309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 11:03:56.580672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 11:03:56.583936 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1549 11:03:56.586896 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 11:03:56.593586 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 11:03:56.596887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 11:03:56.600345 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 11:03:56.606760 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 11:03:56.609876 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 11:03:56.613370 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 11:03:56.620004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 11:03:56.623467 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 11:03:56.626890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 11:03:56.633578 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 11:03:56.636917 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:03:56.640023 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:03:56.646785 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:03:56.649902 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1564 11:03:56.653214 Total UI for P1: 0, mck2ui 16
1565 11:03:56.656631 best dqsien dly found for B0: ( 0, 14, 2)
1566 11:03:56.660167 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 11:03:56.663024 Total UI for P1: 0, mck2ui 16
1568 11:03:56.666441 best dqsien dly found for B1: ( 0, 14, 6)
1569 11:03:56.669683 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1570 11:03:56.673116 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1571 11:03:56.673192
1572 11:03:56.676194 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1573 11:03:56.683163 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1574 11:03:56.683251 [Gating] SW calibration Done
1575 11:03:56.683320 ==
1576 11:03:56.686336 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 11:03:56.692754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 11:03:56.692858 ==
1579 11:03:56.692939 RX Vref Scan: 0
1580 11:03:56.693014
1581 11:03:56.696419 RX Vref 0 -> 0, step: 1
1582 11:03:56.696522
1583 11:03:56.699402 RX Delay -130 -> 252, step: 16
1584 11:03:56.703068 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1585 11:03:56.706411 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1586 11:03:56.709491 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1587 11:03:56.716391 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1588 11:03:56.719986 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1589 11:03:56.723143 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1590 11:03:56.726135 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1591 11:03:56.729560 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1592 11:03:56.736311 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1593 11:03:56.739587 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1594 11:03:56.742944 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1595 11:03:56.746855 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1596 11:03:56.750230 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1597 11:03:56.756031 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1598 11:03:56.759569 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1599 11:03:56.762914 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1600 11:03:56.763307 ==
1601 11:03:56.766373 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 11:03:56.769777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 11:03:56.772617 ==
1604 11:03:56.773007 DQS Delay:
1605 11:03:56.773311 DQS0 = 0, DQS1 = 0
1606 11:03:56.775914 DQM Delay:
1607 11:03:56.776303 DQM0 = 89, DQM1 = 79
1608 11:03:56.779310 DQ Delay:
1609 11:03:56.782733 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1610 11:03:56.786182 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1611 11:03:56.789470 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1612 11:03:56.792943 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1613 11:03:56.793480
1614 11:03:56.793849
1615 11:03:56.794234 ==
1616 11:03:56.795901 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 11:03:56.799239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 11:03:56.799699 ==
1619 11:03:56.800020
1620 11:03:56.800307
1621 11:03:56.802462 TX Vref Scan disable
1622 11:03:56.802854 == TX Byte 0 ==
1623 11:03:56.809176 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1624 11:03:56.812319 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1625 11:03:56.812707 == TX Byte 1 ==
1626 11:03:56.819264 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1627 11:03:56.822302 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1628 11:03:56.822695 ==
1629 11:03:56.825836 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 11:03:56.828886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 11:03:56.829324 ==
1632 11:03:56.843029 TX Vref=22, minBit 15, minWin=26, winSum=442
1633 11:03:56.846483 TX Vref=24, minBit 8, minWin=26, winSum=445
1634 11:03:56.850201 TX Vref=26, minBit 9, minWin=27, winSum=449
1635 11:03:56.852703 TX Vref=28, minBit 10, minWin=27, winSum=449
1636 11:03:56.856448 TX Vref=30, minBit 10, minWin=27, winSum=450
1637 11:03:56.862922 TX Vref=32, minBit 8, minWin=27, winSum=447
1638 11:03:56.865879 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 30
1639 11:03:56.866045
1640 11:03:56.869395 Final TX Range 1 Vref 30
1641 11:03:56.869534
1642 11:03:56.869641 ==
1643 11:03:56.872504 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 11:03:56.875980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 11:03:56.879127 ==
1646 11:03:56.879231
1647 11:03:56.879311
1648 11:03:56.879385 TX Vref Scan disable
1649 11:03:56.882846 == TX Byte 0 ==
1650 11:03:56.886630 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1651 11:03:56.893087 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1652 11:03:56.893197 == TX Byte 1 ==
1653 11:03:56.895970 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1654 11:03:56.902997 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1655 11:03:56.903072
1656 11:03:56.903130 [DATLAT]
1657 11:03:56.903184 Freq=800, CH1 RK0
1658 11:03:56.903235
1659 11:03:56.906282 DATLAT Default: 0xa
1660 11:03:56.906356 0, 0xFFFF, sum = 0
1661 11:03:56.909694 1, 0xFFFF, sum = 0
1662 11:03:56.909770 2, 0xFFFF, sum = 0
1663 11:03:56.913032 3, 0xFFFF, sum = 0
1664 11:03:56.915999 4, 0xFFFF, sum = 0
1665 11:03:56.916076 5, 0xFFFF, sum = 0
1666 11:03:56.919269 6, 0xFFFF, sum = 0
1667 11:03:56.919345 7, 0xFFFF, sum = 0
1668 11:03:56.922416 8, 0xFFFF, sum = 0
1669 11:03:56.922492 9, 0x0, sum = 1
1670 11:03:56.925757 10, 0x0, sum = 2
1671 11:03:56.925833 11, 0x0, sum = 3
1672 11:03:56.929464 12, 0x0, sum = 4
1673 11:03:56.929547 best_step = 10
1674 11:03:56.929611
1675 11:03:56.929669 ==
1676 11:03:56.932796 Dram Type= 6, Freq= 0, CH_1, rank 0
1677 11:03:56.936039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1678 11:03:56.936128 ==
1679 11:03:56.939177 RX Vref Scan: 1
1680 11:03:56.939272
1681 11:03:56.942592 Set Vref Range= 32 -> 127
1682 11:03:56.942697
1683 11:03:56.942777 RX Vref 32 -> 127, step: 1
1684 11:03:56.942855
1685 11:03:56.946143 RX Delay -95 -> 252, step: 8
1686 11:03:56.946247
1687 11:03:56.949293 Set Vref, RX VrefLevel [Byte0]: 32
1688 11:03:56.952699 [Byte1]: 32
1689 11:03:56.955602
1690 11:03:56.955728 Set Vref, RX VrefLevel [Byte0]: 33
1691 11:03:56.958959 [Byte1]: 33
1692 11:03:56.963303
1693 11:03:56.963491 Set Vref, RX VrefLevel [Byte0]: 34
1694 11:03:56.966540 [Byte1]: 34
1695 11:03:56.971005
1696 11:03:56.971197 Set Vref, RX VrefLevel [Byte0]: 35
1697 11:03:56.974094 [Byte1]: 35
1698 11:03:56.978953
1699 11:03:56.979250 Set Vref, RX VrefLevel [Byte0]: 36
1700 11:03:56.982121 [Byte1]: 36
1701 11:03:56.986401
1702 11:03:56.986785 Set Vref, RX VrefLevel [Byte0]: 37
1703 11:03:56.989705 [Byte1]: 37
1704 11:03:56.993775
1705 11:03:56.994173 Set Vref, RX VrefLevel [Byte0]: 38
1706 11:03:56.997573 [Byte1]: 38
1707 11:03:57.001593
1708 11:03:57.002003 Set Vref, RX VrefLevel [Byte0]: 39
1709 11:03:57.008256 [Byte1]: 39
1710 11:03:57.008695
1711 11:03:57.011127 Set Vref, RX VrefLevel [Byte0]: 40
1712 11:03:57.014738 [Byte1]: 40
1713 11:03:57.015120
1714 11:03:57.018161 Set Vref, RX VrefLevel [Byte0]: 41
1715 11:03:57.021666 [Byte1]: 41
1716 11:03:57.022054
1717 11:03:57.024409 Set Vref, RX VrefLevel [Byte0]: 42
1718 11:03:57.027877 [Byte1]: 42
1719 11:03:57.031780
1720 11:03:57.032167 Set Vref, RX VrefLevel [Byte0]: 43
1721 11:03:57.035413 [Byte1]: 43
1722 11:03:57.039780
1723 11:03:57.040164 Set Vref, RX VrefLevel [Byte0]: 44
1724 11:03:57.043042 [Byte1]: 44
1725 11:03:57.046960
1726 11:03:57.047345 Set Vref, RX VrefLevel [Byte0]: 45
1727 11:03:57.050810 [Byte1]: 45
1728 11:03:57.054540
1729 11:03:57.054983 Set Vref, RX VrefLevel [Byte0]: 46
1730 11:03:57.057755 [Byte1]: 46
1731 11:03:57.062397
1732 11:03:57.062780 Set Vref, RX VrefLevel [Byte0]: 47
1733 11:03:57.065873 [Byte1]: 47
1734 11:03:57.070173
1735 11:03:57.070557 Set Vref, RX VrefLevel [Byte0]: 48
1736 11:03:57.073191 [Byte1]: 48
1737 11:03:57.077860
1738 11:03:57.078244 Set Vref, RX VrefLevel [Byte0]: 49
1739 11:03:57.080938 [Byte1]: 49
1740 11:03:57.085859
1741 11:03:57.086266 Set Vref, RX VrefLevel [Byte0]: 50
1742 11:03:57.088602 [Byte1]: 50
1743 11:03:57.092992
1744 11:03:57.093377 Set Vref, RX VrefLevel [Byte0]: 51
1745 11:03:57.095882 [Byte1]: 51
1746 11:03:57.100401
1747 11:03:57.100925 Set Vref, RX VrefLevel [Byte0]: 52
1748 11:03:57.106712 [Byte1]: 52
1749 11:03:57.107215
1750 11:03:57.110224 Set Vref, RX VrefLevel [Byte0]: 53
1751 11:03:57.113414 [Byte1]: 53
1752 11:03:57.113897
1753 11:03:57.116746 Set Vref, RX VrefLevel [Byte0]: 54
1754 11:03:57.120298 [Byte1]: 54
1755 11:03:57.120772
1756 11:03:57.123307 Set Vref, RX VrefLevel [Byte0]: 55
1757 11:03:57.126768 [Byte1]: 55
1758 11:03:57.130723
1759 11:03:57.131209 Set Vref, RX VrefLevel [Byte0]: 56
1760 11:03:57.134238 [Byte1]: 56
1761 11:03:57.138165
1762 11:03:57.138642 Set Vref, RX VrefLevel [Byte0]: 57
1763 11:03:57.141615 [Byte1]: 57
1764 11:03:57.145788
1765 11:03:57.146181 Set Vref, RX VrefLevel [Byte0]: 58
1766 11:03:57.149102 [Byte1]: 58
1767 11:03:57.153529
1768 11:03:57.153908 Set Vref, RX VrefLevel [Byte0]: 59
1769 11:03:57.156623 [Byte1]: 59
1770 11:03:57.161011
1771 11:03:57.161405 Set Vref, RX VrefLevel [Byte0]: 60
1772 11:03:57.164449 [Byte1]: 60
1773 11:03:57.168802
1774 11:03:57.169200 Set Vref, RX VrefLevel [Byte0]: 61
1775 11:03:57.171953 [Byte1]: 61
1776 11:03:57.176565
1777 11:03:57.177062 Set Vref, RX VrefLevel [Byte0]: 62
1778 11:03:57.179768 [Byte1]: 62
1779 11:03:57.183729
1780 11:03:57.184243 Set Vref, RX VrefLevel [Byte0]: 63
1781 11:03:57.187140 [Byte1]: 63
1782 11:03:57.191229
1783 11:03:57.191812 Set Vref, RX VrefLevel [Byte0]: 64
1784 11:03:57.195079 [Byte1]: 64
1785 11:03:57.199205
1786 11:03:57.199747 Set Vref, RX VrefLevel [Byte0]: 65
1787 11:03:57.202663 [Byte1]: 65
1788 11:03:57.206508
1789 11:03:57.206896 Set Vref, RX VrefLevel [Byte0]: 66
1790 11:03:57.209952 [Byte1]: 66
1791 11:03:57.214393
1792 11:03:57.214781 Set Vref, RX VrefLevel [Byte0]: 67
1793 11:03:57.217315 [Byte1]: 67
1794 11:03:57.221966
1795 11:03:57.222351 Set Vref, RX VrefLevel [Byte0]: 68
1796 11:03:57.225252 [Byte1]: 68
1797 11:03:57.229283
1798 11:03:57.229665 Set Vref, RX VrefLevel [Byte0]: 69
1799 11:03:57.232544 [Byte1]: 69
1800 11:03:57.237180
1801 11:03:57.237563 Set Vref, RX VrefLevel [Byte0]: 70
1802 11:03:57.240500 [Byte1]: 70
1803 11:03:57.244504
1804 11:03:57.245161 Set Vref, RX VrefLevel [Byte0]: 71
1805 11:03:57.247840 [Byte1]: 71
1806 11:03:57.252588
1807 11:03:57.252970 Set Vref, RX VrefLevel [Byte0]: 72
1808 11:03:57.255534 [Byte1]: 72
1809 11:03:57.259820
1810 11:03:57.260215 Set Vref, RX VrefLevel [Byte0]: 73
1811 11:03:57.263166 [Byte1]: 73
1812 11:03:57.267422
1813 11:03:57.267846 Final RX Vref Byte 0 = 55 to rank0
1814 11:03:57.270617 Final RX Vref Byte 1 = 63 to rank0
1815 11:03:57.274272 Final RX Vref Byte 0 = 55 to rank1
1816 11:03:57.277622 Final RX Vref Byte 1 = 63 to rank1==
1817 11:03:57.280792 Dram Type= 6, Freq= 0, CH_1, rank 0
1818 11:03:57.287545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 11:03:57.288130 ==
1820 11:03:57.288655 DQS Delay:
1821 11:03:57.289082 DQS0 = 0, DQS1 = 0
1822 11:03:57.290694 DQM Delay:
1823 11:03:57.291152 DQM0 = 86, DQM1 = 79
1824 11:03:57.294338 DQ Delay:
1825 11:03:57.297669 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1826 11:03:57.300880 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1827 11:03:57.301267 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1828 11:03:57.307187 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1829 11:03:57.307613
1830 11:03:57.307918
1831 11:03:57.314248 [DQSOSCAuto] RK0, (LSB)MR18= 0x321d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1832 11:03:57.317369 CH1 RK0: MR19=606, MR18=321D
1833 11:03:57.324185 CH1_RK0: MR19=0x606, MR18=0x321D, DQSOSC=397, MR23=63, INC=93, DEC=62
1834 11:03:57.324574
1835 11:03:57.327085 ----->DramcWriteLeveling(PI) begin...
1836 11:03:57.327517 ==
1837 11:03:57.330557 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 11:03:57.333667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 11:03:57.334056 ==
1840 11:03:57.337558 Write leveling (Byte 0): 25 => 25
1841 11:03:57.340523 Write leveling (Byte 1): 29 => 29
1842 11:03:57.343937 DramcWriteLeveling(PI) end<-----
1843 11:03:57.344347
1844 11:03:57.344645 ==
1845 11:03:57.346866 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 11:03:57.351089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 11:03:57.351523 ==
1848 11:03:57.354097 [Gating] SW mode calibration
1849 11:03:57.360463 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1850 11:03:57.367221 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1851 11:03:57.370118 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1852 11:03:57.373511 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1853 11:03:57.380498 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1854 11:03:57.383547 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:03:57.387082 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:03:57.393580 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:03:57.396827 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:03:57.400132 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:03:57.407547 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:03:57.410355 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:03:57.413854 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:03:57.420281 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:03:57.423741 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:03:57.427114 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:03:57.433713 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:03:57.436806 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:03:57.440457 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:03:57.446730 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1869 11:03:57.450395 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:03:57.453643 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:03:57.460069 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:03:57.463035 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:03:57.466537 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:03:57.473493 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:03:57.476850 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:03:57.480167 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:03:57.486405 0 9 8 | B1->B0 | 3232 2929 | 1 1 | (1 1) (1 1)
1878 11:03:57.490135 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1879 11:03:57.493307 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 11:03:57.499925 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 11:03:57.503760 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 11:03:57.506389 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 11:03:57.512822 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 11:03:57.516208 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (1 0) (1 0)
1885 11:03:57.519799 0 10 8 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
1886 11:03:57.522770 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:03:57.529598 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:03:57.532946 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:03:57.536471 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:03:57.543030 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:03:57.546206 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:03:57.549831 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1893 11:03:57.556274 0 11 8 | B1->B0 | 4545 3a39 | 0 1 | (0 0) (0 0)
1894 11:03:57.559807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 11:03:57.562940 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 11:03:57.569567 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 11:03:57.573028 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 11:03:57.575993 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 11:03:57.583030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 11:03:57.586508 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1901 11:03:57.589578 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1902 11:03:57.596045 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 11:03:57.599383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 11:03:57.602578 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 11:03:57.609322 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 11:03:57.612862 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 11:03:57.616185 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 11:03:57.623007 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 11:03:57.625761 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:03:57.629239 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 11:03:57.635930 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 11:03:57.639259 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 11:03:57.642582 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 11:03:57.649128 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 11:03:57.652234 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 11:03:57.655753 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1917 11:03:57.662064 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 11:03:57.662576 Total UI for P1: 0, mck2ui 16
1919 11:03:57.668586 best dqsien dly found for B0: ( 0, 14, 6)
1920 11:03:57.668974 Total UI for P1: 0, mck2ui 16
1921 11:03:57.675270 best dqsien dly found for B1: ( 0, 14, 4)
1922 11:03:57.678633 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1923 11:03:57.682111 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1924 11:03:57.682610
1925 11:03:57.685468 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1926 11:03:57.689050 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1927 11:03:57.691850 [Gating] SW calibration Done
1928 11:03:57.692233 ==
1929 11:03:57.695282 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 11:03:57.698106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 11:03:57.698495 ==
1932 11:03:57.701578 RX Vref Scan: 0
1933 11:03:57.701965
1934 11:03:57.702262 RX Vref 0 -> 0, step: 1
1935 11:03:57.702535
1936 11:03:57.704899 RX Delay -130 -> 252, step: 16
1937 11:03:57.708144 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1938 11:03:57.714646 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1939 11:03:57.718148 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1940 11:03:57.721626 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1941 11:03:57.725089 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1942 11:03:57.728312 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1943 11:03:57.735010 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1944 11:03:57.738315 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1945 11:03:57.741646 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1946 11:03:57.744557 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1947 11:03:57.748020 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1948 11:03:57.754989 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1949 11:03:57.758003 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1950 11:03:57.761543 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1951 11:03:57.764814 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1952 11:03:57.771223 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1953 11:03:57.771709 ==
1954 11:03:57.774697 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 11:03:57.778084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 11:03:57.778478 ==
1957 11:03:57.778781 DQS Delay:
1958 11:03:57.781192 DQS0 = 0, DQS1 = 0
1959 11:03:57.781623 DQM Delay:
1960 11:03:57.784170 DQM0 = 86, DQM1 = 78
1961 11:03:57.784720 DQ Delay:
1962 11:03:57.787378 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1963 11:03:57.791221 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1964 11:03:57.794216 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1965 11:03:57.797323 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1966 11:03:57.797714
1967 11:03:57.798013
1968 11:03:57.798288 ==
1969 11:03:57.800859 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 11:03:57.803977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 11:03:57.807951 ==
1972 11:03:57.808337
1973 11:03:57.808637
1974 11:03:57.809140 TX Vref Scan disable
1975 11:03:57.810969 == TX Byte 0 ==
1976 11:03:57.814109 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1977 11:03:57.817277 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1978 11:03:57.820644 == TX Byte 1 ==
1979 11:03:57.824307 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1980 11:03:57.827736 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1981 11:03:57.830521 ==
1982 11:03:57.834306 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 11:03:57.837464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 11:03:57.837887 ==
1985 11:03:57.849749 TX Vref=22, minBit 1, minWin=27, winSum=442
1986 11:03:57.852690 TX Vref=24, minBit 9, minWin=26, winSum=441
1987 11:03:57.856169 TX Vref=26, minBit 9, minWin=26, winSum=445
1988 11:03:57.859043 TX Vref=28, minBit 1, minWin=27, winSum=448
1989 11:03:57.862463 TX Vref=30, minBit 1, minWin=27, winSum=449
1990 11:03:57.869157 TX Vref=32, minBit 8, minWin=27, winSum=449
1991 11:03:57.872552 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1992 11:03:57.872628
1993 11:03:57.875906 Final TX Range 1 Vref 30
1994 11:03:57.875981
1995 11:03:57.876040 ==
1996 11:03:57.879635 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 11:03:57.882638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 11:03:57.885991 ==
1999 11:03:57.886077
2000 11:03:57.886144
2001 11:03:57.886205 TX Vref Scan disable
2002 11:03:57.889310 == TX Byte 0 ==
2003 11:03:57.892558 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2004 11:03:57.899592 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2005 11:03:57.899711 == TX Byte 1 ==
2006 11:03:57.903125 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2007 11:03:57.906192 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2008 11:03:57.909487
2009 11:03:57.909701 [DATLAT]
2010 11:03:57.909829 Freq=800, CH1 RK1
2011 11:03:57.909932
2012 11:03:57.913017 DATLAT Default: 0xa
2013 11:03:57.913175 0, 0xFFFF, sum = 0
2014 11:03:57.916525 1, 0xFFFF, sum = 0
2015 11:03:57.916688 2, 0xFFFF, sum = 0
2016 11:03:57.919803 3, 0xFFFF, sum = 0
2017 11:03:57.919991 4, 0xFFFF, sum = 0
2018 11:03:57.922964 5, 0xFFFF, sum = 0
2019 11:03:57.923189 6, 0xFFFF, sum = 0
2020 11:03:57.926106 7, 0xFFFF, sum = 0
2021 11:03:57.926331 8, 0xFFFF, sum = 0
2022 11:03:57.929907 9, 0x0, sum = 1
2023 11:03:57.930188 10, 0x0, sum = 2
2024 11:03:57.932899 11, 0x0, sum = 3
2025 11:03:57.933260 12, 0x0, sum = 4
2026 11:03:57.936502 best_step = 10
2027 11:03:57.936854
2028 11:03:57.937125 ==
2029 11:03:57.940023 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 11:03:57.943261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 11:03:57.943733 ==
2032 11:03:57.946778 RX Vref Scan: 0
2033 11:03:57.947164
2034 11:03:57.947505 RX Vref 0 -> 0, step: 1
2035 11:03:57.947797
2036 11:03:57.949573 RX Delay -95 -> 252, step: 8
2037 11:03:57.956303 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2038 11:03:57.959882 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2039 11:03:57.962675 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2040 11:03:57.965982 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2041 11:03:57.972445 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2042 11:03:57.975748 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2043 11:03:57.979205 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2044 11:03:57.982168 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2045 11:03:57.985967 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2046 11:03:57.991951 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2047 11:03:57.995361 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2048 11:03:57.999008 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2049 11:03:58.001949 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2050 11:03:58.005119 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2051 11:03:58.011723 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2052 11:03:58.015060 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2053 11:03:58.015137 ==
2054 11:03:58.018527 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 11:03:58.021811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 11:03:58.021887 ==
2057 11:03:58.025333 DQS Delay:
2058 11:03:58.025409 DQS0 = 0, DQS1 = 0
2059 11:03:58.028488 DQM Delay:
2060 11:03:58.028577 DQM0 = 87, DQM1 = 78
2061 11:03:58.028637 DQ Delay:
2062 11:03:58.031667 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2063 11:03:58.035014 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2064 11:03:58.038485 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2065 11:03:58.041796 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2066 11:03:58.041871
2067 11:03:58.041928
2068 11:03:58.051865 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2069 11:03:58.054990 CH1 RK1: MR19=606, MR18=1D15
2070 11:03:58.058076 CH1_RK1: MR19=0x606, MR18=0x1D15, DQSOSC=402, MR23=63, INC=91, DEC=60
2071 11:03:58.061567 [RxdqsGatingPostProcess] freq 800
2072 11:03:58.068396 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2073 11:03:58.071368 Pre-setting of DQS Precalculation
2074 11:03:58.074574 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2075 11:03:58.084481 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2076 11:03:58.091244 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2077 11:03:58.091343
2078 11:03:58.091433
2079 11:03:58.094826 [Calibration Summary] 1600 Mbps
2080 11:03:58.094902 CH 0, Rank 0
2081 11:03:58.098052 SW Impedance : PASS
2082 11:03:58.098128 DUTY Scan : NO K
2083 11:03:58.101369 ZQ Calibration : PASS
2084 11:03:58.104240 Jitter Meter : NO K
2085 11:03:58.104316 CBT Training : PASS
2086 11:03:58.107989 Write leveling : PASS
2087 11:03:58.110892 RX DQS gating : PASS
2088 11:03:58.110989 RX DQ/DQS(RDDQC) : PASS
2089 11:03:58.114525 TX DQ/DQS : PASS
2090 11:03:58.117838 RX DATLAT : PASS
2091 11:03:58.117915 RX DQ/DQS(Engine): PASS
2092 11:03:58.121118 TX OE : NO K
2093 11:03:58.121194 All Pass.
2094 11:03:58.121253
2095 11:03:58.124474 CH 0, Rank 1
2096 11:03:58.124550 SW Impedance : PASS
2097 11:03:58.127791 DUTY Scan : NO K
2098 11:03:58.130882 ZQ Calibration : PASS
2099 11:03:58.130958 Jitter Meter : NO K
2100 11:03:58.134216 CBT Training : PASS
2101 11:03:58.137469 Write leveling : PASS
2102 11:03:58.137568 RX DQS gating : PASS
2103 11:03:58.141090 RX DQ/DQS(RDDQC) : PASS
2104 11:03:58.144036 TX DQ/DQS : PASS
2105 11:03:58.144129 RX DATLAT : PASS
2106 11:03:58.147399 RX DQ/DQS(Engine): PASS
2107 11:03:58.147546 TX OE : NO K
2108 11:03:58.151087 All Pass.
2109 11:03:58.151177
2110 11:03:58.151259 CH 1, Rank 0
2111 11:03:58.153977 SW Impedance : PASS
2112 11:03:58.154065 DUTY Scan : NO K
2113 11:03:58.157430 ZQ Calibration : PASS
2114 11:03:58.160842 Jitter Meter : NO K
2115 11:03:58.160916 CBT Training : PASS
2116 11:03:58.164467 Write leveling : PASS
2117 11:03:58.167276 RX DQS gating : PASS
2118 11:03:58.167372 RX DQ/DQS(RDDQC) : PASS
2119 11:03:58.170807 TX DQ/DQS : PASS
2120 11:03:58.174350 RX DATLAT : PASS
2121 11:03:58.174443 RX DQ/DQS(Engine): PASS
2122 11:03:58.177263 TX OE : NO K
2123 11:03:58.177351 All Pass.
2124 11:03:58.177434
2125 11:03:58.180614 CH 1, Rank 1
2126 11:03:58.180701 SW Impedance : PASS
2127 11:03:58.184097 DUTY Scan : NO K
2128 11:03:58.187441 ZQ Calibration : PASS
2129 11:03:58.187531 Jitter Meter : NO K
2130 11:03:58.190963 CBT Training : PASS
2131 11:03:58.193828 Write leveling : PASS
2132 11:03:58.193904 RX DQS gating : PASS
2133 11:03:58.197235 RX DQ/DQS(RDDQC) : PASS
2134 11:03:58.200783 TX DQ/DQS : PASS
2135 11:03:58.200859 RX DATLAT : PASS
2136 11:03:58.204148 RX DQ/DQS(Engine): PASS
2137 11:03:58.204224 TX OE : NO K
2138 11:03:58.207597 All Pass.
2139 11:03:58.207672
2140 11:03:58.207730 DramC Write-DBI off
2141 11:03:58.210544 PER_BANK_REFRESH: Hybrid Mode
2142 11:03:58.213860 TX_TRACKING: ON
2143 11:03:58.217198 [GetDramInforAfterCalByMRR] Vendor 6.
2144 11:03:58.220919 [GetDramInforAfterCalByMRR] Revision 606.
2145 11:03:58.224251 [GetDramInforAfterCalByMRR] Revision 2 0.
2146 11:03:58.224328 MR0 0x3b3b
2147 11:03:58.224387 MR8 0x5151
2148 11:03:58.230306 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2149 11:03:58.230381
2150 11:03:58.230440 MR0 0x3b3b
2151 11:03:58.230493 MR8 0x5151
2152 11:03:58.233723 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2153 11:03:58.233799
2154 11:03:58.243641 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2155 11:03:58.247274 [FAST_K] Save calibration result to emmc
2156 11:03:58.250592 [FAST_K] Save calibration result to emmc
2157 11:03:58.253985 dram_init: config_dvfs: 1
2158 11:03:58.257294 dramc_set_vcore_voltage set vcore to 662500
2159 11:03:58.260178 Read voltage for 1200, 2
2160 11:03:58.260252 Vio18 = 0
2161 11:03:58.263765 Vcore = 662500
2162 11:03:58.263839 Vdram = 0
2163 11:03:58.263896 Vddq = 0
2164 11:03:58.263950 Vmddr = 0
2165 11:03:58.270174 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2166 11:03:58.277086 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2167 11:03:58.277161 MEM_TYPE=3, freq_sel=15
2168 11:03:58.280008 sv_algorithm_assistance_LP4_1600
2169 11:03:58.283446 ============ PULL DRAM RESETB DOWN ============
2170 11:03:58.289916 ========== PULL DRAM RESETB DOWN end =========
2171 11:03:58.293133 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2172 11:03:58.296964 ===================================
2173 11:03:58.300191 LPDDR4 DRAM CONFIGURATION
2174 11:03:58.303658 ===================================
2175 11:03:58.303733 EX_ROW_EN[0] = 0x0
2176 11:03:58.306842 EX_ROW_EN[1] = 0x0
2177 11:03:58.306916 LP4Y_EN = 0x0
2178 11:03:58.309804 WORK_FSP = 0x0
2179 11:03:58.309878 WL = 0x4
2180 11:03:58.313750 RL = 0x4
2181 11:03:58.313824 BL = 0x2
2182 11:03:58.316720 RPST = 0x0
2183 11:03:58.320309 RD_PRE = 0x0
2184 11:03:58.320384 WR_PRE = 0x1
2185 11:03:58.323267 WR_PST = 0x0
2186 11:03:58.323343 DBI_WR = 0x0
2187 11:03:58.326512 DBI_RD = 0x0
2188 11:03:58.326588 OTF = 0x1
2189 11:03:58.329905 ===================================
2190 11:03:58.333413 ===================================
2191 11:03:58.333489 ANA top config
2192 11:03:58.336819 ===================================
2193 11:03:58.340355 DLL_ASYNC_EN = 0
2194 11:03:58.343280 ALL_SLAVE_EN = 0
2195 11:03:58.346443 NEW_RANK_MODE = 1
2196 11:03:58.350002 DLL_IDLE_MODE = 1
2197 11:03:58.350083 LP45_APHY_COMB_EN = 1
2198 11:03:58.353213 TX_ODT_DIS = 1
2199 11:03:58.356569 NEW_8X_MODE = 1
2200 11:03:58.359797 ===================================
2201 11:03:58.363416 ===================================
2202 11:03:58.366754 data_rate = 2400
2203 11:03:58.370028 CKR = 1
2204 11:03:58.370140 DQ_P2S_RATIO = 8
2205 11:03:58.373117 ===================================
2206 11:03:58.376417 CA_P2S_RATIO = 8
2207 11:03:58.379657 DQ_CA_OPEN = 0
2208 11:03:58.383586 DQ_SEMI_OPEN = 0
2209 11:03:58.386386 CA_SEMI_OPEN = 0
2210 11:03:58.389848 CA_FULL_RATE = 0
2211 11:03:58.390033 DQ_CKDIV4_EN = 0
2212 11:03:58.393242 CA_CKDIV4_EN = 0
2213 11:03:58.396494 CA_PREDIV_EN = 0
2214 11:03:58.399925 PH8_DLY = 17
2215 11:03:58.403215 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2216 11:03:58.406932 DQ_AAMCK_DIV = 4
2217 11:03:58.407326 CA_AAMCK_DIV = 4
2218 11:03:58.410631 CA_ADMCK_DIV = 4
2219 11:03:58.413254 DQ_TRACK_CA_EN = 0
2220 11:03:58.416728 CA_PICK = 1200
2221 11:03:58.420125 CA_MCKIO = 1200
2222 11:03:58.423240 MCKIO_SEMI = 0
2223 11:03:58.426656 PLL_FREQ = 2366
2224 11:03:58.430010 DQ_UI_PI_RATIO = 32
2225 11:03:58.430397 CA_UI_PI_RATIO = 0
2226 11:03:58.433237 ===================================
2227 11:03:58.436795 ===================================
2228 11:03:58.440240 memory_type:LPDDR4
2229 11:03:58.443223 GP_NUM : 10
2230 11:03:58.443761 SRAM_EN : 1
2231 11:03:58.446747 MD32_EN : 0
2232 11:03:58.449998 ===================================
2233 11:03:58.453112 [ANA_INIT] >>>>>>>>>>>>>>
2234 11:03:58.453592 <<<<<< [CONFIGURE PHASE]: ANA_TX
2235 11:03:58.459915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2236 11:03:58.462858 ===================================
2237 11:03:58.463244 data_rate = 2400,PCW = 0X5b00
2238 11:03:58.466279 ===================================
2239 11:03:58.469554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2240 11:03:58.476353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2241 11:03:58.482924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2242 11:03:58.486339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2243 11:03:58.489835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2244 11:03:58.493000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2245 11:03:58.496008 [ANA_INIT] flow start
2246 11:03:58.496441 [ANA_INIT] PLL >>>>>>>>
2247 11:03:58.499723 [ANA_INIT] PLL <<<<<<<<
2248 11:03:58.502785 [ANA_INIT] MIDPI >>>>>>>>
2249 11:03:58.506266 [ANA_INIT] MIDPI <<<<<<<<
2250 11:03:58.506665 [ANA_INIT] DLL >>>>>>>>
2251 11:03:58.509658 [ANA_INIT] DLL <<<<<<<<
2252 11:03:58.510055 [ANA_INIT] flow end
2253 11:03:58.516096 ============ LP4 DIFF to SE enter ============
2254 11:03:58.519594 ============ LP4 DIFF to SE exit ============
2255 11:03:58.523077 [ANA_INIT] <<<<<<<<<<<<<
2256 11:03:58.526187 [Flow] Enable top DCM control >>>>>
2257 11:03:58.529686 [Flow] Enable top DCM control <<<<<
2258 11:03:58.532826 Enable DLL master slave shuffle
2259 11:03:58.536035 ==============================================================
2260 11:03:58.539466 Gating Mode config
2261 11:03:58.542740 ==============================================================
2262 11:03:58.546069 Config description:
2263 11:03:58.555680 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2264 11:03:58.562476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2265 11:03:58.566044 SELPH_MODE 0: By rank 1: By Phase
2266 11:03:58.572669 ==============================================================
2267 11:03:58.576399 GAT_TRACK_EN = 1
2268 11:03:58.579147 RX_GATING_MODE = 2
2269 11:03:58.582569 RX_GATING_TRACK_MODE = 2
2270 11:03:58.585970 SELPH_MODE = 1
2271 11:03:58.588813 PICG_EARLY_EN = 1
2272 11:03:58.589199 VALID_LAT_VALUE = 1
2273 11:03:58.595608 ==============================================================
2274 11:03:58.598909 Enter into Gating configuration >>>>
2275 11:03:58.602648 Exit from Gating configuration <<<<
2276 11:03:58.605603 Enter into DVFS_PRE_config >>>>>
2277 11:03:58.615612 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2278 11:03:58.619284 Exit from DVFS_PRE_config <<<<<
2279 11:03:58.622208 Enter into PICG configuration >>>>
2280 11:03:58.625253 Exit from PICG configuration <<<<
2281 11:03:58.629056 [RX_INPUT] configuration >>>>>
2282 11:03:58.631978 [RX_INPUT] configuration <<<<<
2283 11:03:58.638803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2284 11:03:58.642245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2285 11:03:58.648418 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2286 11:03:58.655707 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2287 11:03:58.661984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 11:03:58.668477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 11:03:58.671899 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2290 11:03:58.675228 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2291 11:03:58.678818 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2292 11:03:58.685151 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2293 11:03:58.688581 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2294 11:03:58.691972 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2295 11:03:58.694806 ===================================
2296 11:03:58.698281 LPDDR4 DRAM CONFIGURATION
2297 11:03:58.701817 ===================================
2298 11:03:58.702203 EX_ROW_EN[0] = 0x0
2299 11:03:58.705211 EX_ROW_EN[1] = 0x0
2300 11:03:58.708066 LP4Y_EN = 0x0
2301 11:03:58.708449 WORK_FSP = 0x0
2302 11:03:58.711736 WL = 0x4
2303 11:03:58.712194 RL = 0x4
2304 11:03:58.714904 BL = 0x2
2305 11:03:58.715287 RPST = 0x0
2306 11:03:58.718451 RD_PRE = 0x0
2307 11:03:58.718836 WR_PRE = 0x1
2308 11:03:58.722154 WR_PST = 0x0
2309 11:03:58.722539 DBI_WR = 0x0
2310 11:03:58.724888 DBI_RD = 0x0
2311 11:03:58.725455 OTF = 0x1
2312 11:03:58.728144 ===================================
2313 11:03:58.731486 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2314 11:03:58.738041 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2315 11:03:58.741596 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 11:03:58.744850 ===================================
2317 11:03:58.747967 LPDDR4 DRAM CONFIGURATION
2318 11:03:58.751816 ===================================
2319 11:03:58.752205 EX_ROW_EN[0] = 0x10
2320 11:03:58.754654 EX_ROW_EN[1] = 0x0
2321 11:03:58.755038 LP4Y_EN = 0x0
2322 11:03:58.758096 WORK_FSP = 0x0
2323 11:03:58.761600 WL = 0x4
2324 11:03:58.761989 RL = 0x4
2325 11:03:58.764828 BL = 0x2
2326 11:03:58.765212 RPST = 0x0
2327 11:03:58.768444 RD_PRE = 0x0
2328 11:03:58.768832 WR_PRE = 0x1
2329 11:03:58.771614 WR_PST = 0x0
2330 11:03:58.771999 DBI_WR = 0x0
2331 11:03:58.774953 DBI_RD = 0x0
2332 11:03:58.775337 OTF = 0x1
2333 11:03:58.778119 ===================================
2334 11:03:58.784950 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2335 11:03:58.785338 ==
2336 11:03:58.788276 Dram Type= 6, Freq= 0, CH_0, rank 0
2337 11:03:58.791203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2338 11:03:58.791623 ==
2339 11:03:58.794578 [Duty_Offset_Calibration]
2340 11:03:58.797842 B0:1 B1:-1 CA:0
2341 11:03:58.798220
2342 11:03:58.801275 [DutyScan_Calibration_Flow] k_type=0
2343 11:03:58.809596
2344 11:03:58.809984 ==CLK 0==
2345 11:03:58.812511 Final CLK duty delay cell = 0
2346 11:03:58.815922 [0] MAX Duty = 5094%(X100), DQS PI = 16
2347 11:03:58.819489 [0] MIN Duty = 4875%(X100), DQS PI = 8
2348 11:03:58.819894 [0] AVG Duty = 4984%(X100)
2349 11:03:58.822640
2350 11:03:58.825997 CH0 CLK Duty spec in!! Max-Min= 219%
2351 11:03:58.829425 [DutyScan_Calibration_Flow] ====Done====
2352 11:03:58.829809
2353 11:03:58.832141 [DutyScan_Calibration_Flow] k_type=1
2354 11:03:58.848006
2355 11:03:58.848461 ==DQS 0 ==
2356 11:03:58.851049 Final DQS duty delay cell = -4
2357 11:03:58.854853 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2358 11:03:58.857686 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2359 11:03:58.861109 [-4] AVG Duty = 4968%(X100)
2360 11:03:58.861491
2361 11:03:58.861819 ==DQS 1 ==
2362 11:03:58.864181 Final DQS duty delay cell = 0
2363 11:03:58.867613 [0] MAX Duty = 5124%(X100), DQS PI = 6
2364 11:03:58.871129 [0] MIN Duty = 5000%(X100), DQS PI = 22
2365 11:03:58.874367 [0] AVG Duty = 5062%(X100)
2366 11:03:58.874750
2367 11:03:58.877803 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2368 11:03:58.878187
2369 11:03:58.881376 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2370 11:03:58.884528 [DutyScan_Calibration_Flow] ====Done====
2371 11:03:58.884913
2372 11:03:58.887296 [DutyScan_Calibration_Flow] k_type=3
2373 11:03:58.905697
2374 11:03:58.906078 ==DQM 0 ==
2375 11:03:58.909005 Final DQM duty delay cell = 0
2376 11:03:58.912730 [0] MAX Duty = 5062%(X100), DQS PI = 22
2377 11:03:58.915457 [0] MIN Duty = 4876%(X100), DQS PI = 8
2378 11:03:58.916064 [0] AVG Duty = 4969%(X100)
2379 11:03:58.918987
2380 11:03:58.919367 ==DQM 1 ==
2381 11:03:58.922387 Final DQM duty delay cell = 4
2382 11:03:58.925284 [4] MAX Duty = 5156%(X100), DQS PI = 12
2383 11:03:58.928605 [4] MIN Duty = 4969%(X100), DQS PI = 24
2384 11:03:58.932027 [4] AVG Duty = 5062%(X100)
2385 11:03:58.932456
2386 11:03:58.935516 CH0 DQM 0 Duty spec in!! Max-Min= 186%
2387 11:03:58.936011
2388 11:03:58.938466 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2389 11:03:58.941825 [DutyScan_Calibration_Flow] ====Done====
2390 11:03:58.942210
2391 11:03:58.945161 [DutyScan_Calibration_Flow] k_type=2
2392 11:03:58.960898
2393 11:03:58.961279 ==DQ 0 ==
2394 11:03:58.964277 Final DQ duty delay cell = -4
2395 11:03:58.967675 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2396 11:03:58.971064 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2397 11:03:58.974577 [-4] AVG Duty = 4969%(X100)
2398 11:03:58.974965
2399 11:03:58.975265 ==DQ 1 ==
2400 11:03:58.978089 Final DQ duty delay cell = 0
2401 11:03:58.981193 [0] MAX Duty = 5125%(X100), DQS PI = 52
2402 11:03:58.984837 [0] MIN Duty = 4969%(X100), DQS PI = 40
2403 11:03:58.987882 [0] AVG Duty = 5047%(X100)
2404 11:03:58.988272
2405 11:03:58.990963 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2406 11:03:58.991353
2407 11:03:58.994216 CH0 DQ 1 Duty spec in!! Max-Min= 156%
2408 11:03:58.997741 [DutyScan_Calibration_Flow] ====Done====
2409 11:03:58.998130 ==
2410 11:03:59.001141 Dram Type= 6, Freq= 0, CH_1, rank 0
2411 11:03:59.004573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2412 11:03:59.004964 ==
2413 11:03:59.007374 [Duty_Offset_Calibration]
2414 11:03:59.007798 B0:-1 B1:1 CA:1
2415 11:03:59.008103
2416 11:03:59.010855 [DutyScan_Calibration_Flow] k_type=0
2417 11:03:59.021526
2418 11:03:59.021911 ==CLK 0==
2419 11:03:59.024994 Final CLK duty delay cell = 0
2420 11:03:59.028342 [0] MAX Duty = 5156%(X100), DQS PI = 22
2421 11:03:59.032085 [0] MIN Duty = 4969%(X100), DQS PI = 60
2422 11:03:59.035113 [0] AVG Duty = 5062%(X100)
2423 11:03:59.035521
2424 11:03:59.037800 CH1 CLK Duty spec in!! Max-Min= 187%
2425 11:03:59.041359 [DutyScan_Calibration_Flow] ====Done====
2426 11:03:59.041749
2427 11:03:59.044698 [DutyScan_Calibration_Flow] k_type=1
2428 11:03:59.060712
2429 11:03:59.061098 ==DQS 0 ==
2430 11:03:59.064058 Final DQS duty delay cell = 0
2431 11:03:59.067460 [0] MAX Duty = 5125%(X100), DQS PI = 48
2432 11:03:59.071013 [0] MIN Duty = 4875%(X100), DQS PI = 6
2433 11:03:59.071402 [0] AVG Duty = 5000%(X100)
2434 11:03:59.074353
2435 11:03:59.074736 ==DQS 1 ==
2436 11:03:59.077599 Final DQS duty delay cell = 0
2437 11:03:59.080662 [0] MAX Duty = 5094%(X100), DQS PI = 12
2438 11:03:59.084501 [0] MIN Duty = 4969%(X100), DQS PI = 0
2439 11:03:59.084892 [0] AVG Duty = 5031%(X100)
2440 11:03:59.087379
2441 11:03:59.090566 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2442 11:03:59.090954
2443 11:03:59.093916 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2444 11:03:59.097233 [DutyScan_Calibration_Flow] ====Done====
2445 11:03:59.097698
2446 11:03:59.100616 [DutyScan_Calibration_Flow] k_type=3
2447 11:03:59.116310
2448 11:03:59.116694 ==DQM 0 ==
2449 11:03:59.119708 Final DQM duty delay cell = -4
2450 11:03:59.122959 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2451 11:03:59.126372 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2452 11:03:59.129334 [-4] AVG Duty = 4937%(X100)
2453 11:03:59.129765
2454 11:03:59.130069 ==DQM 1 ==
2455 11:03:59.132800 Final DQM duty delay cell = 0
2456 11:03:59.136018 [0] MAX Duty = 5125%(X100), DQS PI = 2
2457 11:03:59.139498 [0] MIN Duty = 4969%(X100), DQS PI = 28
2458 11:03:59.142428 [0] AVG Duty = 5047%(X100)
2459 11:03:59.142860
2460 11:03:59.145769 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2461 11:03:59.146249
2462 11:03:59.149101 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2463 11:03:59.152148 [DutyScan_Calibration_Flow] ====Done====
2464 11:03:59.152668
2465 11:03:59.155415 [DutyScan_Calibration_Flow] k_type=2
2466 11:03:59.172873
2467 11:03:59.173256 ==DQ 0 ==
2468 11:03:59.176461 Final DQ duty delay cell = 0
2469 11:03:59.179990 [0] MAX Duty = 5156%(X100), DQS PI = 28
2470 11:03:59.183250 [0] MIN Duty = 4876%(X100), DQS PI = 8
2471 11:03:59.183686 [0] AVG Duty = 5016%(X100)
2472 11:03:59.183993
2473 11:03:59.186476 ==DQ 1 ==
2474 11:03:59.189801 Final DQ duty delay cell = 0
2475 11:03:59.192826 [0] MAX Duty = 5124%(X100), DQS PI = 10
2476 11:03:59.196436 [0] MIN Duty = 4969%(X100), DQS PI = 0
2477 11:03:59.196844 [0] AVG Duty = 5046%(X100)
2478 11:03:59.197239
2479 11:03:59.200301 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2480 11:03:59.200704
2481 11:03:59.203020 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2482 11:03:59.209755 [DutyScan_Calibration_Flow] ====Done====
2483 11:03:59.212813 nWR fixed to 30
2484 11:03:59.213206 [ModeRegInit_LP4] CH0 RK0
2485 11:03:59.216302 [ModeRegInit_LP4] CH0 RK1
2486 11:03:59.219828 [ModeRegInit_LP4] CH1 RK0
2487 11:03:59.220219 [ModeRegInit_LP4] CH1 RK1
2488 11:03:59.223067 match AC timing 7
2489 11:03:59.226000 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2490 11:03:59.229969 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2491 11:03:59.236090 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2492 11:03:59.239478 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2493 11:03:59.246280 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2494 11:03:59.246669 ==
2495 11:03:59.249841 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 11:03:59.252624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 11:03:59.253015 ==
2498 11:03:59.259391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 11:03:59.265998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 11:03:59.272756 [CA 0] Center 39 (9~70) winsize 62
2501 11:03:59.276628 [CA 1] Center 39 (9~69) winsize 61
2502 11:03:59.279950 [CA 2] Center 35 (5~66) winsize 62
2503 11:03:59.283222 [CA 3] Center 34 (4~65) winsize 62
2504 11:03:59.286111 [CA 4] Center 33 (4~63) winsize 60
2505 11:03:59.290075 [CA 5] Center 33 (3~63) winsize 61
2506 11:03:59.290472
2507 11:03:59.292857 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2508 11:03:59.293246
2509 11:03:59.296043 [CATrainingPosCal] consider 1 rank data
2510 11:03:59.299315 u2DelayCellTimex100 = 270/100 ps
2511 11:03:59.302724 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2512 11:03:59.306300 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2513 11:03:59.312747 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 11:03:59.316224 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2515 11:03:59.319498 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2516 11:03:59.322916 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2517 11:03:59.323303
2518 11:03:59.326616 CA PerBit enable=1, Macro0, CA PI delay=33
2519 11:03:59.327006
2520 11:03:59.329757 [CBTSetCACLKResult] CA Dly = 33
2521 11:03:59.330152 CS Dly: 8 (0~39)
2522 11:03:59.332972 ==
2523 11:03:59.333359 Dram Type= 6, Freq= 0, CH_0, rank 1
2524 11:03:59.339974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 11:03:59.340367 ==
2526 11:03:59.342589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 11:03:59.349374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2528 11:03:59.358900 [CA 0] Center 39 (8~70) winsize 63
2529 11:03:59.362282 [CA 1] Center 39 (9~70) winsize 62
2530 11:03:59.365335 [CA 2] Center 35 (5~66) winsize 62
2531 11:03:59.368947 [CA 3] Center 34 (4~65) winsize 62
2532 11:03:59.371743 [CA 4] Center 33 (3~63) winsize 61
2533 11:03:59.375092 [CA 5] Center 33 (3~63) winsize 61
2534 11:03:59.375512
2535 11:03:59.378511 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2536 11:03:59.378902
2537 11:03:59.381864 [CATrainingPosCal] consider 2 rank data
2538 11:03:59.385359 u2DelayCellTimex100 = 270/100 ps
2539 11:03:59.388749 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2540 11:03:59.395025 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2541 11:03:59.398531 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 11:03:59.402021 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2543 11:03:59.404878 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2544 11:03:59.408233 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2545 11:03:59.408619
2546 11:03:59.411691 CA PerBit enable=1, Macro0, CA PI delay=33
2547 11:03:59.412082
2548 11:03:59.415575 [CBTSetCACLKResult] CA Dly = 33
2549 11:03:59.415965 CS Dly: 8 (0~40)
2550 11:03:59.416266
2551 11:03:59.418612 ----->DramcWriteLeveling(PI) begin...
2552 11:03:59.421484 ==
2553 11:03:59.424896 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 11:03:59.428031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 11:03:59.428558 ==
2556 11:03:59.431871 Write leveling (Byte 0): 34 => 34
2557 11:03:59.435202 Write leveling (Byte 1): 29 => 29
2558 11:03:59.438097 DramcWriteLeveling(PI) end<-----
2559 11:03:59.438487
2560 11:03:59.438783 ==
2561 11:03:59.441880 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 11:03:59.445151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 11:03:59.445557 ==
2564 11:03:59.448180 [Gating] SW mode calibration
2565 11:03:59.454978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2566 11:03:59.461442 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2567 11:03:59.464863 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2568 11:03:59.468449 0 15 4 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
2569 11:03:59.474952 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 11:03:59.477995 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 11:03:59.481175 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 11:03:59.488125 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 11:03:59.491383 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2574 11:03:59.494428 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2575 11:03:59.497865 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2576 11:03:59.504565 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 11:03:59.508069 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 11:03:59.511599 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 11:03:59.518049 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 11:03:59.520969 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 11:03:59.524569 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2582 11:03:59.531022 1 0 28 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
2583 11:03:59.534221 1 1 0 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2584 11:03:59.537713 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2585 11:03:59.544636 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 11:03:59.548069 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 11:03:59.551324 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 11:03:59.557953 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 11:03:59.561156 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 11:03:59.564173 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2591 11:03:59.571036 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2592 11:03:59.574204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 11:03:59.577437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 11:03:59.584118 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 11:03:59.587714 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 11:03:59.590835 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 11:03:59.597438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 11:03:59.601242 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 11:03:59.603994 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 11:03:59.610807 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 11:03:59.614368 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 11:03:59.617946 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 11:03:59.623974 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 11:03:59.627652 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 11:03:59.631252 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2606 11:03:59.637182 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2607 11:03:59.640400 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2608 11:03:59.644123 Total UI for P1: 0, mck2ui 16
2609 11:03:59.647149 best dqsien dly found for B0: ( 1, 3, 26)
2610 11:03:59.650617 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2611 11:03:59.653650 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 11:03:59.657011 Total UI for P1: 0, mck2ui 16
2613 11:03:59.660261 best dqsien dly found for B1: ( 1, 4, 2)
2614 11:03:59.666680 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2615 11:03:59.670420 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2616 11:03:59.670849
2617 11:03:59.673560 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2618 11:03:59.677089 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2619 11:03:59.680070 [Gating] SW calibration Done
2620 11:03:59.680459 ==
2621 11:03:59.683511 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 11:03:59.686886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 11:03:59.687279 ==
2624 11:03:59.690396 RX Vref Scan: 0
2625 11:03:59.690785
2626 11:03:59.691092 RX Vref 0 -> 0, step: 1
2627 11:03:59.691374
2628 11:03:59.693330 RX Delay -40 -> 252, step: 8
2629 11:03:59.696570 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2630 11:03:59.703386 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2631 11:03:59.706895 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2632 11:03:59.710134 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2633 11:03:59.713485 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2634 11:03:59.716754 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2635 11:03:59.723111 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2636 11:03:59.726435 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2637 11:03:59.730028 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2638 11:03:59.733114 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2639 11:03:59.736440 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2640 11:03:59.739787 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2641 11:03:59.746778 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2642 11:03:59.750056 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2643 11:03:59.753463 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2644 11:03:59.756381 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2645 11:03:59.756864 ==
2646 11:03:59.759900 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 11:03:59.766712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 11:03:59.767106 ==
2649 11:03:59.767408 DQS Delay:
2650 11:03:59.769731 DQS0 = 0, DQS1 = 0
2651 11:03:59.770122 DQM Delay:
2652 11:03:59.772946 DQM0 = 119, DQM1 = 107
2653 11:03:59.773337 DQ Delay:
2654 11:03:59.776280 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2655 11:03:59.779497 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2656 11:03:59.782831 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2657 11:03:59.786276 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2658 11:03:59.786667
2659 11:03:59.786968
2660 11:03:59.787241 ==
2661 11:03:59.789790 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 11:03:59.793258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 11:03:59.796647 ==
2664 11:03:59.797036
2665 11:03:59.797334
2666 11:03:59.797612 TX Vref Scan disable
2667 11:03:59.799494 == TX Byte 0 ==
2668 11:03:59.803014 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2669 11:03:59.806087 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2670 11:03:59.809778 == TX Byte 1 ==
2671 11:03:59.812553 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2672 11:03:59.819792 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2673 11:03:59.820186 ==
2674 11:03:59.823068 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 11:03:59.826223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 11:03:59.826703 ==
2677 11:03:59.837537 TX Vref=22, minBit 6, minWin=25, winSum=416
2678 11:03:59.840722 TX Vref=24, minBit 14, minWin=25, winSum=423
2679 11:03:59.843996 TX Vref=26, minBit 0, minWin=26, winSum=427
2680 11:03:59.847973 TX Vref=28, minBit 13, minWin=26, winSum=435
2681 11:03:59.850869 TX Vref=30, minBit 10, minWin=26, winSum=435
2682 11:03:59.857795 TX Vref=32, minBit 4, minWin=26, winSum=432
2683 11:03:59.860753 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 28
2684 11:03:59.861211
2685 11:03:59.864294 Final TX Range 1 Vref 28
2686 11:03:59.864686
2687 11:03:59.864991 ==
2688 11:03:59.867230 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 11:03:59.870740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 11:03:59.874221 ==
2691 11:03:59.874625
2692 11:03:59.875034
2693 11:03:59.875324 TX Vref Scan disable
2694 11:03:59.877663 == TX Byte 0 ==
2695 11:03:59.881225 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2696 11:03:59.887525 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2697 11:03:59.887925 == TX Byte 1 ==
2698 11:03:59.891045 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2699 11:03:59.897646 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2700 11:03:59.898033
2701 11:03:59.898338 [DATLAT]
2702 11:03:59.898615 Freq=1200, CH0 RK0
2703 11:03:59.898881
2704 11:03:59.901217 DATLAT Default: 0xd
2705 11:03:59.901604 0, 0xFFFF, sum = 0
2706 11:03:59.904120 1, 0xFFFF, sum = 0
2707 11:03:59.907332 2, 0xFFFF, sum = 0
2708 11:03:59.907772 3, 0xFFFF, sum = 0
2709 11:03:59.910931 4, 0xFFFF, sum = 0
2710 11:03:59.911327 5, 0xFFFF, sum = 0
2711 11:03:59.914250 6, 0xFFFF, sum = 0
2712 11:03:59.914672 7, 0xFFFF, sum = 0
2713 11:03:59.917292 8, 0xFFFF, sum = 0
2714 11:03:59.917687 9, 0xFFFF, sum = 0
2715 11:03:59.920763 10, 0xFFFF, sum = 0
2716 11:03:59.921159 11, 0xFFFF, sum = 0
2717 11:03:59.924495 12, 0x0, sum = 1
2718 11:03:59.924909 13, 0x0, sum = 2
2719 11:03:59.927358 14, 0x0, sum = 3
2720 11:03:59.927804 15, 0x0, sum = 4
2721 11:03:59.930887 best_step = 13
2722 11:03:59.931302
2723 11:03:59.931708 ==
2724 11:03:59.933839 Dram Type= 6, Freq= 0, CH_0, rank 0
2725 11:03:59.937259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2726 11:03:59.937652 ==
2727 11:03:59.937952 RX Vref Scan: 1
2728 11:03:59.938232
2729 11:03:59.940700 Set Vref Range= 32 -> 127
2730 11:03:59.941146
2731 11:03:59.944073 RX Vref 32 -> 127, step: 1
2732 11:03:59.944463
2733 11:03:59.947228 RX Delay -21 -> 252, step: 4
2734 11:03:59.947716
2735 11:03:59.950889 Set Vref, RX VrefLevel [Byte0]: 32
2736 11:03:59.953914 [Byte1]: 32
2737 11:03:59.954303
2738 11:03:59.957379 Set Vref, RX VrefLevel [Byte0]: 33
2739 11:03:59.960354 [Byte1]: 33
2740 11:03:59.964308
2741 11:03:59.964691 Set Vref, RX VrefLevel [Byte0]: 34
2742 11:03:59.967386 [Byte1]: 34
2743 11:03:59.972214
2744 11:03:59.972747 Set Vref, RX VrefLevel [Byte0]: 35
2745 11:03:59.975135 [Byte1]: 35
2746 11:03:59.980194
2747 11:03:59.980732 Set Vref, RX VrefLevel [Byte0]: 36
2748 11:03:59.983227 [Byte1]: 36
2749 11:03:59.987949
2750 11:03:59.988432 Set Vref, RX VrefLevel [Byte0]: 37
2751 11:03:59.991135 [Byte1]: 37
2752 11:03:59.995961
2753 11:03:59.996455 Set Vref, RX VrefLevel [Byte0]: 38
2754 11:03:59.999069 [Byte1]: 38
2755 11:04:00.004153
2756 11:04:00.004661 Set Vref, RX VrefLevel [Byte0]: 39
2757 11:04:00.007056 [Byte1]: 39
2758 11:04:00.011868
2759 11:04:00.012254 Set Vref, RX VrefLevel [Byte0]: 40
2760 11:04:00.014763 [Byte1]: 40
2761 11:04:00.019868
2762 11:04:00.020362 Set Vref, RX VrefLevel [Byte0]: 41
2763 11:04:00.022825 [Byte1]: 41
2764 11:04:00.027704
2765 11:04:00.028188 Set Vref, RX VrefLevel [Byte0]: 42
2766 11:04:00.030638 [Byte1]: 42
2767 11:04:00.035463
2768 11:04:00.035857 Set Vref, RX VrefLevel [Byte0]: 43
2769 11:04:00.038640 [Byte1]: 43
2770 11:04:00.043664
2771 11:04:00.044053 Set Vref, RX VrefLevel [Byte0]: 44
2772 11:04:00.046546 [Byte1]: 44
2773 11:04:00.051663
2774 11:04:00.052212 Set Vref, RX VrefLevel [Byte0]: 45
2775 11:04:00.054448 [Byte1]: 45
2776 11:04:00.059409
2777 11:04:00.059939 Set Vref, RX VrefLevel [Byte0]: 46
2778 11:04:00.062664 [Byte1]: 46
2779 11:04:00.067031
2780 11:04:00.067604 Set Vref, RX VrefLevel [Byte0]: 47
2781 11:04:00.070360 [Byte1]: 47
2782 11:04:00.075737
2783 11:04:00.076223 Set Vref, RX VrefLevel [Byte0]: 48
2784 11:04:00.078751 [Byte1]: 48
2785 11:04:00.082877
2786 11:04:00.083363 Set Vref, RX VrefLevel [Byte0]: 49
2787 11:04:00.086489 [Byte1]: 49
2788 11:04:00.090834
2789 11:04:00.091330 Set Vref, RX VrefLevel [Byte0]: 50
2790 11:04:00.094143 [Byte1]: 50
2791 11:04:00.098803
2792 11:04:00.099293 Set Vref, RX VrefLevel [Byte0]: 51
2793 11:04:00.102283 [Byte1]: 51
2794 11:04:00.106639
2795 11:04:00.107155 Set Vref, RX VrefLevel [Byte0]: 52
2796 11:04:00.109902 [Byte1]: 52
2797 11:04:00.114871
2798 11:04:00.115282 Set Vref, RX VrefLevel [Byte0]: 53
2799 11:04:00.118238 [Byte1]: 53
2800 11:04:00.122674
2801 11:04:00.123057 Set Vref, RX VrefLevel [Byte0]: 54
2802 11:04:00.126126 [Byte1]: 54
2803 11:04:00.130545
2804 11:04:00.130930 Set Vref, RX VrefLevel [Byte0]: 55
2805 11:04:00.133921 [Byte1]: 55
2806 11:04:00.138775
2807 11:04:00.139161 Set Vref, RX VrefLevel [Byte0]: 56
2808 11:04:00.141657 [Byte1]: 56
2809 11:04:00.146473
2810 11:04:00.146858 Set Vref, RX VrefLevel [Byte0]: 57
2811 11:04:00.149441 [Byte1]: 57
2812 11:04:00.154722
2813 11:04:00.155106 Set Vref, RX VrefLevel [Byte0]: 58
2814 11:04:00.157971 [Byte1]: 58
2815 11:04:00.162454
2816 11:04:00.162838 Set Vref, RX VrefLevel [Byte0]: 59
2817 11:04:00.165355 [Byte1]: 59
2818 11:04:00.170246
2819 11:04:00.170633 Set Vref, RX VrefLevel [Byte0]: 60
2820 11:04:00.173314 [Byte1]: 60
2821 11:04:00.178129
2822 11:04:00.178514 Set Vref, RX VrefLevel [Byte0]: 61
2823 11:04:00.181247 [Byte1]: 61
2824 11:04:00.185779
2825 11:04:00.186163 Set Vref, RX VrefLevel [Byte0]: 62
2826 11:04:00.189668 [Byte1]: 62
2827 11:04:00.193748
2828 11:04:00.194131 Set Vref, RX VrefLevel [Byte0]: 63
2829 11:04:00.197284 [Byte1]: 63
2830 11:04:00.201974
2831 11:04:00.202356 Set Vref, RX VrefLevel [Byte0]: 64
2832 11:04:00.205341 [Byte1]: 64
2833 11:04:00.210053
2834 11:04:00.210437 Set Vref, RX VrefLevel [Byte0]: 65
2835 11:04:00.213155 [Byte1]: 65
2836 11:04:00.218046
2837 11:04:00.218430 Set Vref, RX VrefLevel [Byte0]: 66
2838 11:04:00.221065 [Byte1]: 66
2839 11:04:00.225758
2840 11:04:00.226140 Set Vref, RX VrefLevel [Byte0]: 67
2841 11:04:00.229048 [Byte1]: 67
2842 11:04:00.233909
2843 11:04:00.234292 Set Vref, RX VrefLevel [Byte0]: 68
2844 11:04:00.236698 [Byte1]: 68
2845 11:04:00.241408
2846 11:04:00.241789 Set Vref, RX VrefLevel [Byte0]: 69
2847 11:04:00.244883 [Byte1]: 69
2848 11:04:00.249475
2849 11:04:00.249859 Set Vref, RX VrefLevel [Byte0]: 70
2850 11:04:00.252793 [Byte1]: 70
2851 11:04:00.257106
2852 11:04:00.257491 Set Vref, RX VrefLevel [Byte0]: 71
2853 11:04:00.260900 [Byte1]: 71
2854 11:04:00.265348
2855 11:04:00.265737 Set Vref, RX VrefLevel [Byte0]: 72
2856 11:04:00.268862 [Byte1]: 72
2857 11:04:00.273402
2858 11:04:00.273804 Set Vref, RX VrefLevel [Byte0]: 73
2859 11:04:00.276330 [Byte1]: 73
2860 11:04:00.281322
2861 11:04:00.281707 Set Vref, RX VrefLevel [Byte0]: 74
2862 11:04:00.284259 [Byte1]: 74
2863 11:04:00.288955
2864 11:04:00.289340 Final RX Vref Byte 0 = 67 to rank0
2865 11:04:00.292471 Final RX Vref Byte 1 = 51 to rank0
2866 11:04:00.295750 Final RX Vref Byte 0 = 67 to rank1
2867 11:04:00.299504 Final RX Vref Byte 1 = 51 to rank1==
2868 11:04:00.302281 Dram Type= 6, Freq= 0, CH_0, rank 0
2869 11:04:00.309093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 11:04:00.309533 ==
2871 11:04:00.309838 DQS Delay:
2872 11:04:00.310175 DQS0 = 0, DQS1 = 0
2873 11:04:00.312320 DQM Delay:
2874 11:04:00.312708 DQM0 = 118, DQM1 = 107
2875 11:04:00.315480 DQ Delay:
2876 11:04:00.319041 DQ0 =116, DQ1 =118, DQ2 =116, DQ3 =116
2877 11:04:00.322442 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =124
2878 11:04:00.325891 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2879 11:04:00.328804 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2880 11:04:00.329192
2881 11:04:00.329489
2882 11:04:00.335691 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2883 11:04:00.339280 CH0 RK0: MR19=403, MR18=13FF
2884 11:04:00.345358 CH0_RK0: MR19=0x403, MR18=0x13FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2885 11:04:00.345746
2886 11:04:00.348905 ----->DramcWriteLeveling(PI) begin...
2887 11:04:00.349297 ==
2888 11:04:00.352330 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 11:04:00.355550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 11:04:00.359614 ==
2891 11:04:00.360010 Write leveling (Byte 0): 31 => 31
2892 11:04:00.362136 Write leveling (Byte 1): 31 => 31
2893 11:04:00.365528 DramcWriteLeveling(PI) end<-----
2894 11:04:00.366003
2895 11:04:00.366309 ==
2896 11:04:00.368589 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 11:04:00.375581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 11:04:00.376200 ==
2899 11:04:00.378643 [Gating] SW mode calibration
2900 11:04:00.385209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2901 11:04:00.388666 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2902 11:04:00.395111 0 15 0 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
2903 11:04:00.398411 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2904 11:04:00.401805 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 11:04:00.408321 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:04:00.411694 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:04:00.415176 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:04:00.421404 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 11:04:00.424923 0 15 28 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
2910 11:04:00.428355 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2911 11:04:00.431675 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 11:04:00.438458 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:04:00.441275 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:04:00.444757 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:04:00.451242 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:04:00.454774 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:04:00.461159 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
2918 11:04:00.464262 1 1 0 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
2919 11:04:00.468764 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 11:04:00.470821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:04:00.477690 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:04:00.481053 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:04:00.484343 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:04:00.491163 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2925 11:04:00.494071 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2926 11:04:00.497672 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2927 11:04:00.504681 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:04:00.507523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:04:00.511026 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:04:00.518013 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:04:00.521020 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:04:00.524200 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:04:00.530719 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:04:00.534162 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:04:00.537464 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:04:00.544181 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:04:00.547522 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:04:00.550928 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:04:00.557183 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:04:00.560487 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:04:00.563945 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2942 11:04:00.570629 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2943 11:04:00.570787 Total UI for P1: 0, mck2ui 16
2944 11:04:00.576976 best dqsien dly found for B0: ( 1, 3, 28)
2945 11:04:00.580639 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:04:00.583692 Total UI for P1: 0, mck2ui 16
2947 11:04:00.587274 best dqsien dly found for B1: ( 1, 4, 0)
2948 11:04:00.590072 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2949 11:04:00.593410 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2950 11:04:00.593488
2951 11:04:00.596694 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2952 11:04:00.600022 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2953 11:04:00.603206 [Gating] SW calibration Done
2954 11:04:00.603282 ==
2955 11:04:00.607007 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 11:04:00.609880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 11:04:00.613433 ==
2958 11:04:00.613508 RX Vref Scan: 0
2959 11:04:00.613566
2960 11:04:00.616894 RX Vref 0 -> 0, step: 1
2961 11:04:00.616970
2962 11:04:00.619971 RX Delay -40 -> 252, step: 8
2963 11:04:00.623178 iDelay=208, Bit 0, Center 115 (40 ~ 191) 152
2964 11:04:00.626432 iDelay=208, Bit 1, Center 123 (48 ~ 199) 152
2965 11:04:00.630216 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
2966 11:04:00.633371 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
2967 11:04:00.639892 iDelay=208, Bit 4, Center 123 (48 ~ 199) 152
2968 11:04:00.643056 iDelay=208, Bit 5, Center 111 (40 ~ 183) 144
2969 11:04:00.646543 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
2970 11:04:00.649535 iDelay=208, Bit 7, Center 127 (48 ~ 207) 160
2971 11:04:00.653149 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
2972 11:04:00.659663 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
2973 11:04:00.663003 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
2974 11:04:00.666173 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
2975 11:04:00.669505 iDelay=208, Bit 12, Center 111 (40 ~ 183) 144
2976 11:04:00.673120 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
2977 11:04:00.679720 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
2978 11:04:00.682885 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2979 11:04:00.683072 ==
2980 11:04:00.686152 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 11:04:00.689598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 11:04:00.689899 ==
2983 11:04:00.692734 DQS Delay:
2984 11:04:00.693025 DQS0 = 0, DQS1 = 0
2985 11:04:00.693289 DQM Delay:
2986 11:04:00.696147 DQM0 = 118, DQM1 = 108
2987 11:04:00.696438 DQ Delay:
2988 11:04:00.699287 DQ0 =115, DQ1 =123, DQ2 =111, DQ3 =111
2989 11:04:00.702751 DQ4 =123, DQ5 =111, DQ6 =123, DQ7 =127
2990 11:04:00.709429 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2991 11:04:00.712639 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =115
2992 11:04:00.712794
2993 11:04:00.712922
2994 11:04:00.713076 ==
2995 11:04:00.715921 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 11:04:00.719125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 11:04:00.719257 ==
2998 11:04:00.719358
2999 11:04:00.719469
3000 11:04:00.722597 TX Vref Scan disable
3001 11:04:00.725424 == TX Byte 0 ==
3002 11:04:00.728923 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3003 11:04:00.732477 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3004 11:04:00.735616 == TX Byte 1 ==
3005 11:04:00.739024 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3006 11:04:00.742264 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3007 11:04:00.742358 ==
3008 11:04:00.745570 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 11:04:00.749005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 11:04:00.752026 ==
3011 11:04:00.761749 TX Vref=22, minBit 1, minWin=25, winSum=420
3012 11:04:00.765007 TX Vref=24, minBit 4, minWin=25, winSum=423
3013 11:04:00.768619 TX Vref=26, minBit 1, minWin=26, winSum=429
3014 11:04:00.772004 TX Vref=28, minBit 1, minWin=25, winSum=428
3015 11:04:00.774979 TX Vref=30, minBit 1, minWin=26, winSum=431
3016 11:04:00.781796 TX Vref=32, minBit 4, minWin=26, winSum=427
3017 11:04:00.785118 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3018 11:04:00.785211
3019 11:04:00.788323 Final TX Range 1 Vref 30
3020 11:04:00.788416
3021 11:04:00.788500 ==
3022 11:04:00.791767 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 11:04:00.794782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 11:04:00.798548 ==
3025 11:04:00.798661
3026 11:04:00.798747
3027 11:04:00.798867 TX Vref Scan disable
3028 11:04:00.801906 == TX Byte 0 ==
3029 11:04:00.804888 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3030 11:04:00.811518 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3031 11:04:00.811620 == TX Byte 1 ==
3032 11:04:00.815260 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3033 11:04:00.821374 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3034 11:04:00.821469
3035 11:04:00.821542 [DATLAT]
3036 11:04:00.821609 Freq=1200, CH0 RK1
3037 11:04:00.821674
3038 11:04:00.824648 DATLAT Default: 0xd
3039 11:04:00.827932 0, 0xFFFF, sum = 0
3040 11:04:00.828010 1, 0xFFFF, sum = 0
3041 11:04:00.831331 2, 0xFFFF, sum = 0
3042 11:04:00.831423 3, 0xFFFF, sum = 0
3043 11:04:00.834324 4, 0xFFFF, sum = 0
3044 11:04:00.834401 5, 0xFFFF, sum = 0
3045 11:04:00.837851 6, 0xFFFF, sum = 0
3046 11:04:00.837929 7, 0xFFFF, sum = 0
3047 11:04:00.841208 8, 0xFFFF, sum = 0
3048 11:04:00.841286 9, 0xFFFF, sum = 0
3049 11:04:00.844847 10, 0xFFFF, sum = 0
3050 11:04:00.844931 11, 0xFFFF, sum = 0
3051 11:04:00.848157 12, 0x0, sum = 1
3052 11:04:00.848248 13, 0x0, sum = 2
3053 11:04:00.851554 14, 0x0, sum = 3
3054 11:04:00.851645 15, 0x0, sum = 4
3055 11:04:00.854523 best_step = 13
3056 11:04:00.854652
3057 11:04:00.854758 ==
3058 11:04:00.857861 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 11:04:00.861428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 11:04:00.861534 ==
3061 11:04:00.864859 RX Vref Scan: 0
3062 11:04:00.864975
3063 11:04:00.865063 RX Vref 0 -> 0, step: 1
3064 11:04:00.865147
3065 11:04:00.867562 RX Delay -21 -> 252, step: 4
3066 11:04:00.874259 iDelay=199, Bit 0, Center 112 (43 ~ 182) 140
3067 11:04:00.877830 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
3068 11:04:00.881122 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3069 11:04:00.884576 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3070 11:04:00.887465 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
3071 11:04:00.894679 iDelay=199, Bit 5, Center 112 (47 ~ 178) 132
3072 11:04:00.897414 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
3073 11:04:00.901148 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
3074 11:04:00.904462 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3075 11:04:00.907508 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3076 11:04:00.914382 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3077 11:04:00.917795 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3078 11:04:00.921179 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3079 11:04:00.923865 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3080 11:04:00.927367 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3081 11:04:00.933940 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3082 11:04:00.934330 ==
3083 11:04:00.937250 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 11:04:00.940723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 11:04:00.941110 ==
3086 11:04:00.941409 DQS Delay:
3087 11:04:00.944170 DQS0 = 0, DQS1 = 0
3088 11:04:00.944553 DQM Delay:
3089 11:04:00.946967 DQM0 = 116, DQM1 = 107
3090 11:04:00.947355 DQ Delay:
3091 11:04:00.950916 DQ0 =112, DQ1 =116, DQ2 =110, DQ3 =112
3092 11:04:00.954287 DQ4 =118, DQ5 =112, DQ6 =124, DQ7 =124
3093 11:04:00.957437 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3094 11:04:00.960337 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3095 11:04:00.963764
3096 11:04:00.964144
3097 11:04:00.970529 [DQSOSCAuto] RK1, (LSB)MR18= 0x11eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3098 11:04:00.973914 CH0 RK1: MR19=403, MR18=11EB
3099 11:04:00.980394 CH0_RK1: MR19=0x403, MR18=0x11EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3100 11:04:00.983391 [RxdqsGatingPostProcess] freq 1200
3101 11:04:00.987135 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 11:04:00.990535 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 11:04:00.993456 best DQS1 dly(2T, 0.5T) = (0, 12)
3104 11:04:00.996677 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 11:04:01.000167 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3106 11:04:01.003609 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 11:04:01.006710 best DQS1 dly(2T, 0.5T) = (0, 12)
3108 11:04:01.009782 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 11:04:01.013266 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3110 11:04:01.016767 Pre-setting of DQS Precalculation
3111 11:04:01.019893 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 11:04:01.020280 ==
3113 11:04:01.023474 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 11:04:01.029710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 11:04:01.030097 ==
3116 11:04:01.032954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 11:04:01.039457 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 11:04:01.048607 [CA 0] Center 37 (7~67) winsize 61
3119 11:04:01.051996 [CA 1] Center 37 (7~68) winsize 62
3120 11:04:01.055014 [CA 2] Center 34 (4~64) winsize 61
3121 11:04:01.057928 [CA 3] Center 33 (3~64) winsize 62
3122 11:04:01.061318 [CA 4] Center 34 (4~64) winsize 61
3123 11:04:01.064869 [CA 5] Center 33 (3~64) winsize 62
3124 11:04:01.065265
3125 11:04:01.067304 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3126 11:04:01.067382
3127 11:04:01.074055 [CATrainingPosCal] consider 1 rank data
3128 11:04:01.074163 u2DelayCellTimex100 = 270/100 ps
3129 11:04:01.080870 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3130 11:04:01.084110 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 11:04:01.087762 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 11:04:01.090659 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3133 11:04:01.094012 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 11:04:01.097335 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3135 11:04:01.097426
3136 11:04:01.100154 CA PerBit enable=1, Macro0, CA PI delay=33
3137 11:04:01.100230
3138 11:04:01.103398 [CBTSetCACLKResult] CA Dly = 33
3139 11:04:01.106725 CS Dly: 5 (0~36)
3140 11:04:01.106800 ==
3141 11:04:01.110451 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 11:04:01.113695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 11:04:01.113801 ==
3144 11:04:01.120213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 11:04:01.123285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3146 11:04:01.133193 [CA 0] Center 37 (7~67) winsize 61
3147 11:04:01.136673 [CA 1] Center 37 (7~68) winsize 62
3148 11:04:01.139883 [CA 2] Center 34 (4~65) winsize 62
3149 11:04:01.143123 [CA 3] Center 33 (3~64) winsize 62
3150 11:04:01.146400 [CA 4] Center 34 (4~64) winsize 61
3151 11:04:01.149659 [CA 5] Center 33 (3~64) winsize 62
3152 11:04:01.149736
3153 11:04:01.153480 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3154 11:04:01.153557
3155 11:04:01.156780 [CATrainingPosCal] consider 2 rank data
3156 11:04:01.160210 u2DelayCellTimex100 = 270/100 ps
3157 11:04:01.162998 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3158 11:04:01.169855 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3159 11:04:01.173195 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 11:04:01.176579 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3161 11:04:01.179689 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 11:04:01.183157 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3163 11:04:01.183234
3164 11:04:01.186208 CA PerBit enable=1, Macro0, CA PI delay=33
3165 11:04:01.186284
3166 11:04:01.189588 [CBTSetCACLKResult] CA Dly = 33
3167 11:04:01.192845 CS Dly: 7 (0~40)
3168 11:04:01.192921
3169 11:04:01.196182 ----->DramcWriteLeveling(PI) begin...
3170 11:04:01.196260 ==
3171 11:04:01.199292 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 11:04:01.202979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 11:04:01.203057 ==
3174 11:04:01.206035 Write leveling (Byte 0): 26 => 26
3175 11:04:01.209196 Write leveling (Byte 1): 27 => 27
3176 11:04:01.212924 DramcWriteLeveling(PI) end<-----
3177 11:04:01.213000
3178 11:04:01.213059 ==
3179 11:04:01.216160 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 11:04:01.219592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 11:04:01.219669 ==
3182 11:04:01.222402 [Gating] SW mode calibration
3183 11:04:01.229404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 11:04:01.235990 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 11:04:01.239528 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3186 11:04:01.242301 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 11:04:01.248992 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:04:01.252530 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:04:01.255959 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:04:01.262320 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 11:04:01.265632 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3192 11:04:01.268960 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
3193 11:04:01.275780 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 11:04:01.279242 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:04:01.282200 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:04:01.289254 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:04:01.292319 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:04:01.295765 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3199 11:04:01.302116 1 0 24 | B1->B0 | 2828 3a3a | 0 1 | (0 0) (0 0)
3200 11:04:01.305701 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 11:04:01.309033 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 11:04:01.315297 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:04:01.318951 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:04:01.321848 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:04:01.328643 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:04:01.331633 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:04:01.334921 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3208 11:04:01.341444 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3209 11:04:01.345186 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:04:01.348323 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:04:01.355105 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:04:01.358358 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:04:01.361817 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:04:01.368141 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:04:01.371126 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:04:01.374880 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:04:01.381413 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:04:01.384486 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:04:01.387948 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:04:01.394639 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:04:01.398172 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:04:01.401092 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:04:01.407757 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3224 11:04:01.410978 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 11:04:01.414086 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:04:01.417835 Total UI for P1: 0, mck2ui 16
3227 11:04:01.420785 best dqsien dly found for B0: ( 1, 3, 26)
3228 11:04:01.424071 Total UI for P1: 0, mck2ui 16
3229 11:04:01.427987 best dqsien dly found for B1: ( 1, 3, 28)
3230 11:04:01.431063 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3231 11:04:01.434193 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3232 11:04:01.437413
3233 11:04:01.440545 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3234 11:04:01.443894 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3235 11:04:01.447083 [Gating] SW calibration Done
3236 11:04:01.447616 ==
3237 11:04:01.450477 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 11:04:01.453933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 11:04:01.454332 ==
3240 11:04:01.454640 RX Vref Scan: 0
3241 11:04:01.457111
3242 11:04:01.457503 RX Vref 0 -> 0, step: 1
3243 11:04:01.457809
3244 11:04:01.460485 RX Delay -40 -> 252, step: 8
3245 11:04:01.464187 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3246 11:04:01.467278 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3247 11:04:01.473480 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3248 11:04:01.476988 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3249 11:04:01.479900 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3250 11:04:01.483415 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3251 11:04:01.489723 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3252 11:04:01.493165 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3253 11:04:01.496910 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3254 11:04:01.499930 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3255 11:04:01.503024 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3256 11:04:01.510049 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3257 11:04:01.512837 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3258 11:04:01.516232 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3259 11:04:01.519618 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3260 11:04:01.523036 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3261 11:04:01.526475 ==
3262 11:04:01.526984 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 11:04:01.532916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 11:04:01.533349 ==
3265 11:04:01.533652 DQS Delay:
3266 11:04:01.536363 DQS0 = 0, DQS1 = 0
3267 11:04:01.536749 DQM Delay:
3268 11:04:01.539215 DQM0 = 117, DQM1 = 109
3269 11:04:01.539651 DQ Delay:
3270 11:04:01.543039 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3271 11:04:01.546743 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3272 11:04:01.549670 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3273 11:04:01.552515 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =119
3274 11:04:01.552931
3275 11:04:01.553239
3276 11:04:01.553519 ==
3277 11:04:01.556045 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 11:04:01.562777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 11:04:01.563204 ==
3280 11:04:01.563568
3281 11:04:01.563856
3282 11:04:01.564125 TX Vref Scan disable
3283 11:04:01.566211 == TX Byte 0 ==
3284 11:04:01.569663 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3285 11:04:01.575895 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3286 11:04:01.576285 == TX Byte 1 ==
3287 11:04:01.579493 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 11:04:01.585781 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 11:04:01.586198 ==
3290 11:04:01.589043 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 11:04:01.592319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 11:04:01.592724 ==
3293 11:04:01.603666 TX Vref=22, minBit 10, minWin=24, winSum=415
3294 11:04:01.607095 TX Vref=24, minBit 10, minWin=25, winSum=421
3295 11:04:01.610673 TX Vref=26, minBit 8, minWin=25, winSum=421
3296 11:04:01.613507 TX Vref=28, minBit 9, minWin=25, winSum=430
3297 11:04:01.617043 TX Vref=30, minBit 9, minWin=26, winSum=431
3298 11:04:01.623399 TX Vref=32, minBit 9, minWin=25, winSum=428
3299 11:04:01.627019 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 30
3300 11:04:01.627406
3301 11:04:01.630510 Final TX Range 1 Vref 30
3302 11:04:01.630893
3303 11:04:01.631189 ==
3304 11:04:01.633362 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 11:04:01.640248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 11:04:01.640637 ==
3307 11:04:01.640945
3308 11:04:01.641325
3309 11:04:01.641601 TX Vref Scan disable
3310 11:04:01.643403 == TX Byte 0 ==
3311 11:04:01.646996 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3312 11:04:01.653523 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3313 11:04:01.653923 == TX Byte 1 ==
3314 11:04:01.657104 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 11:04:01.663325 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 11:04:01.663755
3317 11:04:01.664060 [DATLAT]
3318 11:04:01.664374 Freq=1200, CH1 RK0
3319 11:04:01.664648
3320 11:04:01.666525 DATLAT Default: 0xd
3321 11:04:01.669810 0, 0xFFFF, sum = 0
3322 11:04:01.670202 1, 0xFFFF, sum = 0
3323 11:04:01.673138 2, 0xFFFF, sum = 0
3324 11:04:01.673531 3, 0xFFFF, sum = 0
3325 11:04:01.676622 4, 0xFFFF, sum = 0
3326 11:04:01.677011 5, 0xFFFF, sum = 0
3327 11:04:01.680172 6, 0xFFFF, sum = 0
3328 11:04:01.680562 7, 0xFFFF, sum = 0
3329 11:04:01.683276 8, 0xFFFF, sum = 0
3330 11:04:01.683692 9, 0xFFFF, sum = 0
3331 11:04:01.686642 10, 0xFFFF, sum = 0
3332 11:04:01.687028 11, 0xFFFF, sum = 0
3333 11:04:01.689835 12, 0x0, sum = 1
3334 11:04:01.690248 13, 0x0, sum = 2
3335 11:04:01.693122 14, 0x0, sum = 3
3336 11:04:01.693513 15, 0x0, sum = 4
3337 11:04:01.696696 best_step = 13
3338 11:04:01.697079
3339 11:04:01.697371 ==
3340 11:04:01.699980 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 11:04:01.703040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 11:04:01.703454 ==
3343 11:04:01.703763 RX Vref Scan: 1
3344 11:04:01.706532
3345 11:04:01.706916 Set Vref Range= 32 -> 127
3346 11:04:01.707212
3347 11:04:01.709784 RX Vref 32 -> 127, step: 1
3348 11:04:01.710162
3349 11:04:01.713233 RX Delay -21 -> 252, step: 4
3350 11:04:01.713613
3351 11:04:01.716211 Set Vref, RX VrefLevel [Byte0]: 32
3352 11:04:01.719462 [Byte1]: 32
3353 11:04:01.719849
3354 11:04:01.722902 Set Vref, RX VrefLevel [Byte0]: 33
3355 11:04:01.726329 [Byte1]: 33
3356 11:04:01.730542
3357 11:04:01.730813 Set Vref, RX VrefLevel [Byte0]: 34
3358 11:04:01.733252 [Byte1]: 34
3359 11:04:01.737949
3360 11:04:01.738219 Set Vref, RX VrefLevel [Byte0]: 35
3361 11:04:01.741080 [Byte1]: 35
3362 11:04:01.746307
3363 11:04:01.746573 Set Vref, RX VrefLevel [Byte0]: 36
3364 11:04:01.749161 [Byte1]: 36
3365 11:04:01.753766
3366 11:04:01.754033 Set Vref, RX VrefLevel [Byte0]: 37
3367 11:04:01.757357 [Byte1]: 37
3368 11:04:01.762059
3369 11:04:01.762406 Set Vref, RX VrefLevel [Byte0]: 38
3370 11:04:01.765311 [Byte1]: 38
3371 11:04:01.769499
3372 11:04:01.769880 Set Vref, RX VrefLevel [Byte0]: 39
3373 11:04:01.773527 [Byte1]: 39
3374 11:04:01.777633
3375 11:04:01.778010 Set Vref, RX VrefLevel [Byte0]: 40
3376 11:04:01.780780 [Byte1]: 40
3377 11:04:01.785404
3378 11:04:01.785955 Set Vref, RX VrefLevel [Byte0]: 41
3379 11:04:01.788739 [Byte1]: 41
3380 11:04:01.793712
3381 11:04:01.794096 Set Vref, RX VrefLevel [Byte0]: 42
3382 11:04:01.797246 [Byte1]: 42
3383 11:04:01.801638
3384 11:04:01.802027 Set Vref, RX VrefLevel [Byte0]: 43
3385 11:04:01.804742 [Byte1]: 43
3386 11:04:01.809176
3387 11:04:01.809558 Set Vref, RX VrefLevel [Byte0]: 44
3388 11:04:01.812653 [Byte1]: 44
3389 11:04:01.817069
3390 11:04:01.817530 Set Vref, RX VrefLevel [Byte0]: 45
3391 11:04:01.820423 [Byte1]: 45
3392 11:04:01.825111
3393 11:04:01.825504 Set Vref, RX VrefLevel [Byte0]: 46
3394 11:04:01.828551 [Byte1]: 46
3395 11:04:01.833218
3396 11:04:01.833597 Set Vref, RX VrefLevel [Byte0]: 47
3397 11:04:01.836583 [Byte1]: 47
3398 11:04:01.840702
3399 11:04:01.841081 Set Vref, RX VrefLevel [Byte0]: 48
3400 11:04:01.844001 [Byte1]: 48
3401 11:04:01.848977
3402 11:04:01.849356 Set Vref, RX VrefLevel [Byte0]: 49
3403 11:04:01.852347 [Byte1]: 49
3404 11:04:01.856829
3405 11:04:01.857211 Set Vref, RX VrefLevel [Byte0]: 50
3406 11:04:01.860147 [Byte1]: 50
3407 11:04:01.864795
3408 11:04:01.865177 Set Vref, RX VrefLevel [Byte0]: 51
3409 11:04:01.867957 [Byte1]: 51
3410 11:04:01.872570
3411 11:04:01.872956 Set Vref, RX VrefLevel [Byte0]: 52
3412 11:04:01.875768 [Byte1]: 52
3413 11:04:01.880604
3414 11:04:01.881010 Set Vref, RX VrefLevel [Byte0]: 53
3415 11:04:01.883959 [Byte1]: 53
3416 11:04:01.888478
3417 11:04:01.888859 Set Vref, RX VrefLevel [Byte0]: 54
3418 11:04:01.891466 [Byte1]: 54
3419 11:04:01.896292
3420 11:04:01.896670 Set Vref, RX VrefLevel [Byte0]: 55
3421 11:04:01.899826 [Byte1]: 55
3422 11:04:01.904164
3423 11:04:01.904541 Set Vref, RX VrefLevel [Byte0]: 56
3424 11:04:01.907549 [Byte1]: 56
3425 11:04:01.912026
3426 11:04:01.912404 Set Vref, RX VrefLevel [Byte0]: 57
3427 11:04:01.915503 [Byte1]: 57
3428 11:04:01.920376
3429 11:04:01.920758 Set Vref, RX VrefLevel [Byte0]: 58
3430 11:04:01.923124 [Byte1]: 58
3431 11:04:01.928558
3432 11:04:01.928943 Set Vref, RX VrefLevel [Byte0]: 59
3433 11:04:01.931158 [Byte1]: 59
3434 11:04:01.935805
3435 11:04:01.936198 Set Vref, RX VrefLevel [Byte0]: 60
3436 11:04:01.939183 [Byte1]: 60
3437 11:04:01.943698
3438 11:04:01.944083 Set Vref, RX VrefLevel [Byte0]: 61
3439 11:04:01.947386 [Byte1]: 61
3440 11:04:01.951876
3441 11:04:01.952255 Set Vref, RX VrefLevel [Byte0]: 62
3442 11:04:01.955125 [Byte1]: 62
3443 11:04:01.959815
3444 11:04:01.960203 Set Vref, RX VrefLevel [Byte0]: 63
3445 11:04:01.962796 [Byte1]: 63
3446 11:04:01.968024
3447 11:04:01.968408 Set Vref, RX VrefLevel [Byte0]: 64
3448 11:04:01.970942 [Byte1]: 64
3449 11:04:01.975373
3450 11:04:01.975719 Set Vref, RX VrefLevel [Byte0]: 65
3451 11:04:01.978807 [Byte1]: 65
3452 11:04:01.983028
3453 11:04:01.983255 Set Vref, RX VrefLevel [Byte0]: 66
3454 11:04:01.986379 [Byte1]: 66
3455 11:04:01.991110
3456 11:04:01.991360 Final RX Vref Byte 0 = 50 to rank0
3457 11:04:01.994170 Final RX Vref Byte 1 = 61 to rank0
3458 11:04:01.997660 Final RX Vref Byte 0 = 50 to rank1
3459 11:04:02.000873 Final RX Vref Byte 1 = 61 to rank1==
3460 11:04:02.004039 Dram Type= 6, Freq= 0, CH_1, rank 0
3461 11:04:02.011115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 11:04:02.011301 ==
3463 11:04:02.011447 DQS Delay:
3464 11:04:02.011573 DQS0 = 0, DQS1 = 0
3465 11:04:02.014587 DQM Delay:
3466 11:04:02.014754 DQM0 = 115, DQM1 = 112
3467 11:04:02.017902 DQ Delay:
3468 11:04:02.020911 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3469 11:04:02.024338 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112
3470 11:04:02.027419 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3471 11:04:02.030861 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120
3472 11:04:02.031028
3473 11:04:02.031157
3474 11:04:02.040659 [DQSOSCAuto] RK0, (LSB)MR18= 0x7fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3475 11:04:02.040903 CH1 RK0: MR19=403, MR18=7FB
3476 11:04:02.047273 CH1_RK0: MR19=0x403, MR18=0x7FB, DQSOSC=407, MR23=63, INC=39, DEC=26
3477 11:04:02.047488
3478 11:04:02.050719 ----->DramcWriteLeveling(PI) begin...
3479 11:04:02.050918 ==
3480 11:04:02.054105 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 11:04:02.060420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 11:04:02.060587 ==
3483 11:04:02.063787 Write leveling (Byte 0): 25 => 25
3484 11:04:02.067357 Write leveling (Byte 1): 28 => 28
3485 11:04:02.067528 DramcWriteLeveling(PI) end<-----
3486 11:04:02.067642
3487 11:04:02.070304 ==
3488 11:04:02.073657 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 11:04:02.076789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 11:04:02.076896 ==
3491 11:04:02.080109 [Gating] SW mode calibration
3492 11:04:02.086753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3493 11:04:02.090030 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3494 11:04:02.096715 0 15 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3495 11:04:02.099645 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 11:04:02.103192 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 11:04:02.110154 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 11:04:02.113155 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 11:04:02.116388 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 11:04:02.123067 0 15 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
3501 11:04:02.126388 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3502 11:04:02.129809 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 11:04:02.136030 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 11:04:02.139377 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 11:04:02.143126 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 11:04:02.149733 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 11:04:02.153023 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 11:04:02.156036 1 0 24 | B1->B0 | 3535 2525 | 0 0 | (0 0) (0 0)
3509 11:04:02.162952 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3510 11:04:02.165766 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 11:04:02.169541 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 11:04:02.176103 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 11:04:02.179376 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 11:04:02.182635 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 11:04:02.189409 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 11:04:02.192480 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3517 11:04:02.195440 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3518 11:04:02.202254 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 11:04:02.205698 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 11:04:02.208555 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:04:02.215611 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:04:02.218605 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:04:02.222265 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:04:02.228734 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:04:02.232157 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:04:02.235088 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:04:02.241597 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:04:02.245082 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:04:02.248436 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 11:04:02.255369 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 11:04:02.258317 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:04:02.261681 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:04:02.268659 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3534 11:04:02.271802 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:04:02.274693 Total UI for P1: 0, mck2ui 16
3536 11:04:02.278321 best dqsien dly found for B0: ( 1, 3, 28)
3537 11:04:02.281487 Total UI for P1: 0, mck2ui 16
3538 11:04:02.285050 best dqsien dly found for B1: ( 1, 3, 28)
3539 11:04:02.288346 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3540 11:04:02.291731 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3541 11:04:02.292123
3542 11:04:02.295001 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3543 11:04:02.298518 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3544 11:04:02.301960 [Gating] SW calibration Done
3545 11:04:02.302353 ==
3546 11:04:02.304990 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 11:04:02.312106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 11:04:02.312507 ==
3549 11:04:02.312856 RX Vref Scan: 0
3550 11:04:02.313141
3551 11:04:02.314625 RX Vref 0 -> 0, step: 1
3552 11:04:02.315012
3553 11:04:02.317974 RX Delay -40 -> 252, step: 8
3554 11:04:02.321447 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3555 11:04:02.324952 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3556 11:04:02.328226 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3557 11:04:02.331348 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3558 11:04:02.338154 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3559 11:04:02.341197 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3560 11:04:02.344523 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3561 11:04:02.347973 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3562 11:04:02.350863 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3563 11:04:02.357839 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3564 11:04:02.360739 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3565 11:04:02.364204 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3566 11:04:02.367386 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3567 11:04:02.374239 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3568 11:04:02.377687 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3569 11:04:02.380704 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3570 11:04:02.381102 ==
3571 11:04:02.383879 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 11:04:02.387488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 11:04:02.387890 ==
3574 11:04:02.390990 DQS Delay:
3575 11:04:02.391384 DQS0 = 0, DQS1 = 0
3576 11:04:02.393854 DQM Delay:
3577 11:04:02.394295 DQM0 = 115, DQM1 = 110
3578 11:04:02.394625 DQ Delay:
3579 11:04:02.400905 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3580 11:04:02.404229 DQ4 =115, DQ5 =123, DQ6 =127, DQ7 =115
3581 11:04:02.407396 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3582 11:04:02.410971 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3583 11:04:02.411359
3584 11:04:02.411871
3585 11:04:02.412343 ==
3586 11:04:02.414252 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 11:04:02.417155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 11:04:02.417521 ==
3589 11:04:02.417816
3590 11:04:02.418091
3591 11:04:02.420641 TX Vref Scan disable
3592 11:04:02.423778 == TX Byte 0 ==
3593 11:04:02.427236 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 11:04:02.430536 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 11:04:02.433577 == TX Byte 1 ==
3596 11:04:02.436981 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3597 11:04:02.440255 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3598 11:04:02.440660 ==
3599 11:04:02.444052 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 11:04:02.447554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 11:04:02.449753 ==
3602 11:04:02.460205 TX Vref=22, minBit 8, minWin=25, winSum=417
3603 11:04:02.463169 TX Vref=24, minBit 8, minWin=25, winSum=428
3604 11:04:02.466346 TX Vref=26, minBit 8, minWin=26, winSum=431
3605 11:04:02.469661 TX Vref=28, minBit 8, minWin=26, winSum=430
3606 11:04:02.473209 TX Vref=30, minBit 8, minWin=26, winSum=432
3607 11:04:02.479750 TX Vref=32, minBit 8, minWin=26, winSum=432
3608 11:04:02.482804 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3609 11:04:02.482902
3610 11:04:02.486292 Final TX Range 1 Vref 30
3611 11:04:02.486368
3612 11:04:02.486426 ==
3613 11:04:02.489850 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 11:04:02.493027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 11:04:02.496436 ==
3616 11:04:02.496511
3617 11:04:02.496568
3618 11:04:02.496622 TX Vref Scan disable
3619 11:04:02.499769 == TX Byte 0 ==
3620 11:04:02.502992 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3621 11:04:02.509568 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3622 11:04:02.509682 == TX Byte 1 ==
3623 11:04:02.512862 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3624 11:04:02.519608 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3625 11:04:02.519711
3626 11:04:02.519789 [DATLAT]
3627 11:04:02.519861 Freq=1200, CH1 RK1
3628 11:04:02.519931
3629 11:04:02.522825 DATLAT Default: 0xd
3630 11:04:02.525889 0, 0xFFFF, sum = 0
3631 11:04:02.526002 1, 0xFFFF, sum = 0
3632 11:04:02.529107 2, 0xFFFF, sum = 0
3633 11:04:02.529273 3, 0xFFFF, sum = 0
3634 11:04:02.532825 4, 0xFFFF, sum = 0
3635 11:04:02.532982 5, 0xFFFF, sum = 0
3636 11:04:02.535815 6, 0xFFFF, sum = 0
3637 11:04:02.535956 7, 0xFFFF, sum = 0
3638 11:04:02.539495 8, 0xFFFF, sum = 0
3639 11:04:02.539662 9, 0xFFFF, sum = 0
3640 11:04:02.542593 10, 0xFFFF, sum = 0
3641 11:04:02.542780 11, 0xFFFF, sum = 0
3642 11:04:02.546097 12, 0x0, sum = 1
3643 11:04:02.546284 13, 0x0, sum = 2
3644 11:04:02.549119 14, 0x0, sum = 3
3645 11:04:02.549352 15, 0x0, sum = 4
3646 11:04:02.552749 best_step = 13
3647 11:04:02.553022
3648 11:04:02.553329 ==
3649 11:04:02.556187 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 11:04:02.559663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 11:04:02.560023 ==
3652 11:04:02.562519 RX Vref Scan: 0
3653 11:04:02.562910
3654 11:04:02.563212 RX Vref 0 -> 0, step: 1
3655 11:04:02.563534
3656 11:04:02.566068 RX Delay -13 -> 252, step: 4
3657 11:04:02.572668 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3658 11:04:02.576081 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3659 11:04:02.579062 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3660 11:04:02.582273 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3661 11:04:02.585909 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3662 11:04:02.592163 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3663 11:04:02.595892 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3664 11:04:02.599296 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3665 11:04:02.602456 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3666 11:04:02.605469 iDelay=199, Bit 9, Center 102 (39 ~ 166) 128
3667 11:04:02.612198 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3668 11:04:02.615456 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3669 11:04:02.618754 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3670 11:04:02.622184 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3671 11:04:02.628441 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3672 11:04:02.631898 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3673 11:04:02.632288 ==
3674 11:04:02.635519 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 11:04:02.638405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 11:04:02.638796 ==
3677 11:04:02.641917 DQS Delay:
3678 11:04:02.642302 DQS0 = 0, DQS1 = 0
3679 11:04:02.642600 DQM Delay:
3680 11:04:02.645198 DQM0 = 116, DQM1 = 110
3681 11:04:02.645586 DQ Delay:
3682 11:04:02.648604 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3683 11:04:02.651946 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3684 11:04:02.654946 DQ8 =100, DQ9 =102, DQ10 =110, DQ11 =104
3685 11:04:02.661669 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =120
3686 11:04:02.662113
3687 11:04:02.662465
3688 11:04:02.668344 [DQSOSCAuto] RK1, (LSB)MR18= 0xf9f4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 412 ps
3689 11:04:02.671950 CH1 RK1: MR19=303, MR18=F9F4
3690 11:04:02.678213 CH1_RK1: MR19=0x303, MR18=0xF9F4, DQSOSC=412, MR23=63, INC=38, DEC=25
3691 11:04:02.681467 [RxdqsGatingPostProcess] freq 1200
3692 11:04:02.685029 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3693 11:04:02.688522 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 11:04:02.691799 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 11:04:02.694619 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 11:04:02.697954 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 11:04:02.701279 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 11:04:02.704527 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 11:04:02.707513 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 11:04:02.710821 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 11:04:02.714301 Pre-setting of DQS Precalculation
3702 11:04:02.718125 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3703 11:04:02.727701 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3704 11:04:02.734481 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3705 11:04:02.734880
3706 11:04:02.735279
3707 11:04:02.737635 [Calibration Summary] 2400 Mbps
3708 11:04:02.738026 CH 0, Rank 0
3709 11:04:02.741137 SW Impedance : PASS
3710 11:04:02.743754 DUTY Scan : NO K
3711 11:04:02.744198 ZQ Calibration : PASS
3712 11:04:02.747685 Jitter Meter : NO K
3713 11:04:02.748149 CBT Training : PASS
3714 11:04:02.750413 Write leveling : PASS
3715 11:04:02.753841 RX DQS gating : PASS
3716 11:04:02.754290 RX DQ/DQS(RDDQC) : PASS
3717 11:04:02.757042 TX DQ/DQS : PASS
3718 11:04:02.760274 RX DATLAT : PASS
3719 11:04:02.760666 RX DQ/DQS(Engine): PASS
3720 11:04:02.763674 TX OE : NO K
3721 11:04:02.764066 All Pass.
3722 11:04:02.764445
3723 11:04:02.767086 CH 0, Rank 1
3724 11:04:02.767513 SW Impedance : PASS
3725 11:04:02.770686 DUTY Scan : NO K
3726 11:04:02.773880 ZQ Calibration : PASS
3727 11:04:02.774272 Jitter Meter : NO K
3728 11:04:02.777362 CBT Training : PASS
3729 11:04:02.780319 Write leveling : PASS
3730 11:04:02.780711 RX DQS gating : PASS
3731 11:04:02.783753 RX DQ/DQS(RDDQC) : PASS
3732 11:04:02.787194 TX DQ/DQS : PASS
3733 11:04:02.787633 RX DATLAT : PASS
3734 11:04:02.790011 RX DQ/DQS(Engine): PASS
3735 11:04:02.793431 TX OE : NO K
3736 11:04:02.793824 All Pass.
3737 11:04:02.794127
3738 11:04:02.794405 CH 1, Rank 0
3739 11:04:02.796926 SW Impedance : PASS
3740 11:04:02.800199 DUTY Scan : NO K
3741 11:04:02.800591 ZQ Calibration : PASS
3742 11:04:02.803255 Jitter Meter : NO K
3743 11:04:02.806645 CBT Training : PASS
3744 11:04:02.807038 Write leveling : PASS
3745 11:04:02.810260 RX DQS gating : PASS
3746 11:04:02.813672 RX DQ/DQS(RDDQC) : PASS
3747 11:04:02.814091 TX DQ/DQS : PASS
3748 11:04:02.816832 RX DATLAT : PASS
3749 11:04:02.817244 RX DQ/DQS(Engine): PASS
3750 11:04:02.819970 TX OE : NO K
3751 11:04:02.820368 All Pass.
3752 11:04:02.820757
3753 11:04:02.823094 CH 1, Rank 1
3754 11:04:02.826795 SW Impedance : PASS
3755 11:04:02.827222 DUTY Scan : NO K
3756 11:04:02.829884 ZQ Calibration : PASS
3757 11:04:02.830473 Jitter Meter : NO K
3758 11:04:02.833069 CBT Training : PASS
3759 11:04:02.836339 Write leveling : PASS
3760 11:04:02.836906 RX DQS gating : PASS
3761 11:04:02.839658 RX DQ/DQS(RDDQC) : PASS
3762 11:04:02.842970 TX DQ/DQS : PASS
3763 11:04:02.843553 RX DATLAT : PASS
3764 11:04:02.846444 RX DQ/DQS(Engine): PASS
3765 11:04:02.849522 TX OE : NO K
3766 11:04:02.850051 All Pass.
3767 11:04:02.850488
3768 11:04:02.852970 DramC Write-DBI off
3769 11:04:02.853435 PER_BANK_REFRESH: Hybrid Mode
3770 11:04:02.856090 TX_TRACKING: ON
3771 11:04:02.865662 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3772 11:04:02.869466 [FAST_K] Save calibration result to emmc
3773 11:04:02.872333 dramc_set_vcore_voltage set vcore to 650000
3774 11:04:02.872736 Read voltage for 600, 5
3775 11:04:02.875783 Vio18 = 0
3776 11:04:02.876184 Vcore = 650000
3777 11:04:02.876656 Vdram = 0
3778 11:04:02.879039 Vddq = 0
3779 11:04:02.879472 Vmddr = 0
3780 11:04:02.885660 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3781 11:04:02.889051 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3782 11:04:02.892334 MEM_TYPE=3, freq_sel=19
3783 11:04:02.895447 sv_algorithm_assistance_LP4_1600
3784 11:04:02.898861 ============ PULL DRAM RESETB DOWN ============
3785 11:04:02.902159 ========== PULL DRAM RESETB DOWN end =========
3786 11:04:02.908700 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3787 11:04:02.912269 ===================================
3788 11:04:02.912664 LPDDR4 DRAM CONFIGURATION
3789 11:04:02.915165 ===================================
3790 11:04:02.918684 EX_ROW_EN[0] = 0x0
3791 11:04:02.921703 EX_ROW_EN[1] = 0x0
3792 11:04:02.922141 LP4Y_EN = 0x0
3793 11:04:02.925428 WORK_FSP = 0x0
3794 11:04:02.925814 WL = 0x2
3795 11:04:02.928746 RL = 0x2
3796 11:04:02.929135 BL = 0x2
3797 11:04:02.931483 RPST = 0x0
3798 11:04:02.931875 RD_PRE = 0x0
3799 11:04:02.934818 WR_PRE = 0x1
3800 11:04:02.935417 WR_PST = 0x0
3801 11:04:02.938270 DBI_WR = 0x0
3802 11:04:02.938665 DBI_RD = 0x0
3803 11:04:02.941720 OTF = 0x1
3804 11:04:02.945152 ===================================
3805 11:04:02.948454 ===================================
3806 11:04:02.949052 ANA top config
3807 11:04:02.951388 ===================================
3808 11:04:02.954899 DLL_ASYNC_EN = 0
3809 11:04:02.957908 ALL_SLAVE_EN = 1
3810 11:04:02.961414 NEW_RANK_MODE = 1
3811 11:04:02.961806 DLL_IDLE_MODE = 1
3812 11:04:02.964995 LP45_APHY_COMB_EN = 1
3813 11:04:02.968340 TX_ODT_DIS = 1
3814 11:04:02.971360 NEW_8X_MODE = 1
3815 11:04:02.974686 ===================================
3816 11:04:02.978123 ===================================
3817 11:04:02.981509 data_rate = 1200
3818 11:04:02.984877 CKR = 1
3819 11:04:02.985374 DQ_P2S_RATIO = 8
3820 11:04:02.987771 ===================================
3821 11:04:02.991499 CA_P2S_RATIO = 8
3822 11:04:02.994479 DQ_CA_OPEN = 0
3823 11:04:02.997828 DQ_SEMI_OPEN = 0
3824 11:04:03.001075 CA_SEMI_OPEN = 0
3825 11:04:03.004549 CA_FULL_RATE = 0
3826 11:04:03.004938 DQ_CKDIV4_EN = 1
3827 11:04:03.007926 CA_CKDIV4_EN = 1
3828 11:04:03.010831 CA_PREDIV_EN = 0
3829 11:04:03.014337 PH8_DLY = 0
3830 11:04:03.017774 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3831 11:04:03.020880 DQ_AAMCK_DIV = 4
3832 11:04:03.021296 CA_AAMCK_DIV = 4
3833 11:04:03.024230 CA_ADMCK_DIV = 4
3834 11:04:03.027777 DQ_TRACK_CA_EN = 0
3835 11:04:03.030585 CA_PICK = 600
3836 11:04:03.033904 CA_MCKIO = 600
3837 11:04:03.037082 MCKIO_SEMI = 0
3838 11:04:03.040387 PLL_FREQ = 2288
3839 11:04:03.040774 DQ_UI_PI_RATIO = 32
3840 11:04:03.043928 CA_UI_PI_RATIO = 0
3841 11:04:03.047483 ===================================
3842 11:04:03.050867 ===================================
3843 11:04:03.054374 memory_type:LPDDR4
3844 11:04:03.057121 GP_NUM : 10
3845 11:04:03.057614 SRAM_EN : 1
3846 11:04:03.060517 MD32_EN : 0
3847 11:04:03.063875 ===================================
3848 11:04:03.067176 [ANA_INIT] >>>>>>>>>>>>>>
3849 11:04:03.067657 <<<<<< [CONFIGURE PHASE]: ANA_TX
3850 11:04:03.070446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3851 11:04:03.073960 ===================================
3852 11:04:03.077137 data_rate = 1200,PCW = 0X5800
3853 11:04:03.080214 ===================================
3854 11:04:03.083854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3855 11:04:03.090144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3856 11:04:03.096854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3857 11:04:03.100200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3858 11:04:03.103626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3859 11:04:03.106587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3860 11:04:03.109995 [ANA_INIT] flow start
3861 11:04:03.110387 [ANA_INIT] PLL >>>>>>>>
3862 11:04:03.113380 [ANA_INIT] PLL <<<<<<<<
3863 11:04:03.116804 [ANA_INIT] MIDPI >>>>>>>>
3864 11:04:03.119608 [ANA_INIT] MIDPI <<<<<<<<
3865 11:04:03.120003 [ANA_INIT] DLL >>>>>>>>
3866 11:04:03.123245 [ANA_INIT] flow end
3867 11:04:03.126197 ============ LP4 DIFF to SE enter ============
3868 11:04:03.129907 ============ LP4 DIFF to SE exit ============
3869 11:04:03.132903 [ANA_INIT] <<<<<<<<<<<<<
3870 11:04:03.136309 [Flow] Enable top DCM control >>>>>
3871 11:04:03.139584 [Flow] Enable top DCM control <<<<<
3872 11:04:03.142961 Enable DLL master slave shuffle
3873 11:04:03.149296 ==============================================================
3874 11:04:03.149695 Gating Mode config
3875 11:04:03.155881 ==============================================================
3876 11:04:03.156274 Config description:
3877 11:04:03.165737 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3878 11:04:03.173027 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3879 11:04:03.178943 SELPH_MODE 0: By rank 1: By Phase
3880 11:04:03.182222 ==============================================================
3881 11:04:03.185560 GAT_TRACK_EN = 1
3882 11:04:03.188886 RX_GATING_MODE = 2
3883 11:04:03.192303 RX_GATING_TRACK_MODE = 2
3884 11:04:03.195690 SELPH_MODE = 1
3885 11:04:03.199038 PICG_EARLY_EN = 1
3886 11:04:03.202172 VALID_LAT_VALUE = 1
3887 11:04:03.209043 ==============================================================
3888 11:04:03.212409 Enter into Gating configuration >>>>
3889 11:04:03.215363 Exit from Gating configuration <<<<
3890 11:04:03.218992 Enter into DVFS_PRE_config >>>>>
3891 11:04:03.228817 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3892 11:04:03.231834 Exit from DVFS_PRE_config <<<<<
3893 11:04:03.235286 Enter into PICG configuration >>>>
3894 11:04:03.238760 Exit from PICG configuration <<<<
3895 11:04:03.242193 [RX_INPUT] configuration >>>>>
3896 11:04:03.244959 [RX_INPUT] configuration <<<<<
3897 11:04:03.248458 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3898 11:04:03.255214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3899 11:04:03.261984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 11:04:03.265423 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 11:04:03.271770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 11:04:03.278392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 11:04:03.281451 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3904 11:04:03.287952 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3905 11:04:03.291361 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3906 11:04:03.294444 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3907 11:04:03.297877 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3908 11:04:03.304497 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 11:04:03.307779 ===================================
3910 11:04:03.308308 LPDDR4 DRAM CONFIGURATION
3911 11:04:03.311053 ===================================
3912 11:04:03.314690 EX_ROW_EN[0] = 0x0
3913 11:04:03.317798 EX_ROW_EN[1] = 0x0
3914 11:04:03.318297 LP4Y_EN = 0x0
3915 11:04:03.321094 WORK_FSP = 0x0
3916 11:04:03.321580 WL = 0x2
3917 11:04:03.324066 RL = 0x2
3918 11:04:03.324548 BL = 0x2
3919 11:04:03.327919 RPST = 0x0
3920 11:04:03.328402 RD_PRE = 0x0
3921 11:04:03.330621 WR_PRE = 0x1
3922 11:04:03.331099 WR_PST = 0x0
3923 11:04:03.334085 DBI_WR = 0x0
3924 11:04:03.334478 DBI_RD = 0x0
3925 11:04:03.337553 OTF = 0x1
3926 11:04:03.340931 ===================================
3927 11:04:03.343752 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3928 11:04:03.347239 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3929 11:04:03.353840 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 11:04:03.357109 ===================================
3931 11:04:03.357639 LPDDR4 DRAM CONFIGURATION
3932 11:04:03.360768 ===================================
3933 11:04:03.363532 EX_ROW_EN[0] = 0x10
3934 11:04:03.366887 EX_ROW_EN[1] = 0x0
3935 11:04:03.367482 LP4Y_EN = 0x0
3936 11:04:03.370174 WORK_FSP = 0x0
3937 11:04:03.370731 WL = 0x2
3938 11:04:03.373543 RL = 0x2
3939 11:04:03.374086 BL = 0x2
3940 11:04:03.376907 RPST = 0x0
3941 11:04:03.377447 RD_PRE = 0x0
3942 11:04:03.380295 WR_PRE = 0x1
3943 11:04:03.380792 WR_PST = 0x0
3944 11:04:03.383906 DBI_WR = 0x0
3945 11:04:03.384309 DBI_RD = 0x0
3946 11:04:03.386950 OTF = 0x1
3947 11:04:03.390066 ===================================
3948 11:04:03.396791 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3949 11:04:03.400159 nWR fixed to 30
3950 11:04:03.403475 [ModeRegInit_LP4] CH0 RK0
3951 11:04:03.404025 [ModeRegInit_LP4] CH0 RK1
3952 11:04:03.406758 [ModeRegInit_LP4] CH1 RK0
3953 11:04:03.410270 [ModeRegInit_LP4] CH1 RK1
3954 11:04:03.410756 match AC timing 17
3955 11:04:03.416970 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3956 11:04:03.420041 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3957 11:04:03.423239 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3958 11:04:03.429899 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3959 11:04:03.433508 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3960 11:04:03.434004 ==
3961 11:04:03.436685 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 11:04:03.439683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 11:04:03.440179 ==
3964 11:04:03.446669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 11:04:03.453463 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3966 11:04:03.456353 [CA 0] Center 36 (6~66) winsize 61
3967 11:04:03.459786 [CA 1] Center 36 (6~66) winsize 61
3968 11:04:03.463189 [CA 2] Center 34 (3~65) winsize 63
3969 11:04:03.466537 [CA 3] Center 34 (3~65) winsize 63
3970 11:04:03.469347 [CA 4] Center 33 (3~64) winsize 62
3971 11:04:03.472876 [CA 5] Center 33 (3~64) winsize 62
3972 11:04:03.473265
3973 11:04:03.476254 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3974 11:04:03.476642
3975 11:04:03.479855 [CATrainingPosCal] consider 1 rank data
3976 11:04:03.483081 u2DelayCellTimex100 = 270/100 ps
3977 11:04:03.485937 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3978 11:04:03.489757 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3979 11:04:03.492572 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3980 11:04:03.496247 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3981 11:04:03.502751 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 11:04:03.505833 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3983 11:04:03.506297
3984 11:04:03.509144 CA PerBit enable=1, Macro0, CA PI delay=33
3985 11:04:03.509600
3986 11:04:03.512856 [CBTSetCACLKResult] CA Dly = 33
3987 11:04:03.513290 CS Dly: 4 (0~35)
3988 11:04:03.513666 ==
3989 11:04:03.515732 Dram Type= 6, Freq= 0, CH_0, rank 1
3990 11:04:03.522566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 11:04:03.522953 ==
3992 11:04:03.526088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 11:04:03.532642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3994 11:04:03.535690 [CA 0] Center 36 (6~66) winsize 61
3995 11:04:03.538975 [CA 1] Center 36 (6~66) winsize 61
3996 11:04:03.542201 [CA 2] Center 34 (4~64) winsize 61
3997 11:04:03.545520 [CA 3] Center 34 (4~64) winsize 61
3998 11:04:03.548702 [CA 4] Center 33 (2~64) winsize 63
3999 11:04:03.552337 [CA 5] Center 33 (2~64) winsize 63
4000 11:04:03.552752
4001 11:04:03.555773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4002 11:04:03.556174
4003 11:04:03.559499 [CATrainingPosCal] consider 2 rank data
4004 11:04:03.562160 u2DelayCellTimex100 = 270/100 ps
4005 11:04:03.565685 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4006 11:04:03.568880 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4007 11:04:03.575602 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4008 11:04:03.578913 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4009 11:04:03.581710 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 11:04:03.585099 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4011 11:04:03.585604
4012 11:04:03.588778 CA PerBit enable=1, Macro0, CA PI delay=33
4013 11:04:03.589274
4014 11:04:03.592162 [CBTSetCACLKResult] CA Dly = 33
4015 11:04:03.592651 CS Dly: 5 (0~38)
4016 11:04:03.593141
4017 11:04:03.598338 ----->DramcWriteLeveling(PI) begin...
4018 11:04:03.598877 ==
4019 11:04:03.602083 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 11:04:03.605054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 11:04:03.605543 ==
4022 11:04:03.608400 Write leveling (Byte 0): 33 => 33
4023 11:04:03.611759 Write leveling (Byte 1): 29 => 29
4024 11:04:03.615247 DramcWriteLeveling(PI) end<-----
4025 11:04:03.615765
4026 11:04:03.616219 ==
4027 11:04:03.618372 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 11:04:03.621525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 11:04:03.622004 ==
4030 11:04:03.624589 [Gating] SW mode calibration
4031 11:04:03.631340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4032 11:04:03.638268 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4033 11:04:03.641084 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 11:04:03.644844 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 11:04:03.651017 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 11:04:03.654552 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4037 11:04:03.657454 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4038 11:04:03.664450 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 11:04:03.667719 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 11:04:03.671126 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 11:04:03.677775 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 11:04:03.681085 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 11:04:03.684088 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 11:04:03.691017 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 11:04:03.693965 0 10 16 | B1->B0 | 3737 4545 | 0 0 | (1 1) (0 0)
4046 11:04:03.697327 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 11:04:03.703977 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 11:04:03.707218 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 11:04:03.710393 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 11:04:03.717542 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 11:04:03.720172 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 11:04:03.723647 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4053 11:04:03.730499 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4054 11:04:03.734092 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:04:03.736894 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:04:03.743557 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:04:03.746680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:04:03.750514 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:04:03.756975 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:04:03.760108 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:04:03.763500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:04:03.770108 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:04:03.773125 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:04:03.776743 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:04:03.783398 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:04:03.786332 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:04:03.789987 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:04:03.796489 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:04:03.799811 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4070 11:04:03.803175 Total UI for P1: 0, mck2ui 16
4071 11:04:03.806708 best dqsien dly found for B0: ( 0, 13, 14)
4072 11:04:03.809677 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 11:04:03.813566 Total UI for P1: 0, mck2ui 16
4074 11:04:03.816208 best dqsien dly found for B1: ( 0, 13, 16)
4075 11:04:03.819763 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4076 11:04:03.822652 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4077 11:04:03.823044
4078 11:04:03.829204 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4079 11:04:03.833007 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4080 11:04:03.833401 [Gating] SW calibration Done
4081 11:04:03.836009 ==
4082 11:04:03.839235 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 11:04:03.842565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 11:04:03.842962 ==
4085 11:04:03.843264 RX Vref Scan: 0
4086 11:04:03.843596
4087 11:04:03.845982 RX Vref 0 -> 0, step: 1
4088 11:04:03.846371
4089 11:04:03.849085 RX Delay -230 -> 252, step: 16
4090 11:04:03.852777 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4091 11:04:03.855912 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4092 11:04:03.862585 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4093 11:04:03.865442 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4094 11:04:03.869037 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4095 11:04:03.872304 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4096 11:04:03.879097 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4097 11:04:03.882384 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4098 11:04:03.885693 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4099 11:04:03.889017 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4100 11:04:03.895170 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4101 11:04:03.898532 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4102 11:04:03.901902 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4103 11:04:03.905071 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4104 11:04:03.911860 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4105 11:04:03.915043 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4106 11:04:03.915538 ==
4107 11:04:03.918449 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 11:04:03.921656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 11:04:03.922053 ==
4110 11:04:03.925166 DQS Delay:
4111 11:04:03.925717 DQS0 = 0, DQS1 = 0
4112 11:04:03.926214 DQM Delay:
4113 11:04:03.928500 DQM0 = 42, DQM1 = 31
4114 11:04:03.928983 DQ Delay:
4115 11:04:03.931951 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4116 11:04:03.934889 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4117 11:04:03.938037 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4118 11:04:03.941288 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4119 11:04:03.941678
4120 11:04:03.941977
4121 11:04:03.942255 ==
4122 11:04:03.944520 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 11:04:03.951557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:04:03.951958 ==
4125 11:04:03.952264
4126 11:04:03.952543
4127 11:04:03.952810 TX Vref Scan disable
4128 11:04:03.955285 == TX Byte 0 ==
4129 11:04:03.958453 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4130 11:04:03.965094 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4131 11:04:03.965623 == TX Byte 1 ==
4132 11:04:03.968460 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4133 11:04:03.975016 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4134 11:04:03.975486 ==
4135 11:04:03.978291 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 11:04:03.981816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 11:04:03.982316 ==
4138 11:04:03.982781
4139 11:04:03.983235
4140 11:04:03.985217 TX Vref Scan disable
4141 11:04:03.987954 == TX Byte 0 ==
4142 11:04:03.991486 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4143 11:04:03.995577 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4144 11:04:03.997945 == TX Byte 1 ==
4145 11:04:04.001273 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4146 11:04:04.004990 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4147 11:04:04.005397
4148 11:04:04.005795 [DATLAT]
4149 11:04:04.008464 Freq=600, CH0 RK0
4150 11:04:04.008879
4151 11:04:04.011710 DATLAT Default: 0x9
4152 11:04:04.012234 0, 0xFFFF, sum = 0
4153 11:04:04.014974 1, 0xFFFF, sum = 0
4154 11:04:04.015369 2, 0xFFFF, sum = 0
4155 11:04:04.018234 3, 0xFFFF, sum = 0
4156 11:04:04.018687 4, 0xFFFF, sum = 0
4157 11:04:04.021544 5, 0xFFFF, sum = 0
4158 11:04:04.021951 6, 0xFFFF, sum = 0
4159 11:04:04.024826 7, 0xFFFF, sum = 0
4160 11:04:04.025421 8, 0x0, sum = 1
4161 11:04:04.028067 9, 0x0, sum = 2
4162 11:04:04.028597 10, 0x0, sum = 3
4163 11:04:04.031302 11, 0x0, sum = 4
4164 11:04:04.031868 best_step = 9
4165 11:04:04.032335
4166 11:04:04.032802 ==
4167 11:04:04.034289 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 11:04:04.037807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 11:04:04.038370 ==
4170 11:04:04.041166 RX Vref Scan: 1
4171 11:04:04.041571
4172 11:04:04.044541 RX Vref 0 -> 0, step: 1
4173 11:04:04.044940
4174 11:04:04.045351 RX Delay -195 -> 252, step: 8
4175 11:04:04.045725
4176 11:04:04.047899 Set Vref, RX VrefLevel [Byte0]: 67
4177 11:04:04.051010 [Byte1]: 51
4178 11:04:04.055933
4179 11:04:04.056338 Final RX Vref Byte 0 = 67 to rank0
4180 11:04:04.058847 Final RX Vref Byte 1 = 51 to rank0
4181 11:04:04.062500 Final RX Vref Byte 0 = 67 to rank1
4182 11:04:04.065876 Final RX Vref Byte 1 = 51 to rank1==
4183 11:04:04.069330 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 11:04:04.075533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 11:04:04.076009 ==
4186 11:04:04.076415 DQS Delay:
4187 11:04:04.076790 DQS0 = 0, DQS1 = 0
4188 11:04:04.078984 DQM Delay:
4189 11:04:04.079384 DQM0 = 44, DQM1 = 32
4190 11:04:04.082396 DQ Delay:
4191 11:04:04.085754 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4192 11:04:04.089088 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =52
4193 11:04:04.092683 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4194 11:04:04.095580 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4195 11:04:04.096054
4196 11:04:04.096451
4197 11:04:04.102365 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4198 11:04:04.105781 CH0 RK0: MR19=808, MR18=6F46
4199 11:04:04.112024 CH0_RK0: MR19=0x808, MR18=0x6F46, DQSOSC=389, MR23=63, INC=173, DEC=115
4200 11:04:04.112432
4201 11:04:04.115412 ----->DramcWriteLeveling(PI) begin...
4202 11:04:04.115851 ==
4203 11:04:04.118530 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 11:04:04.122251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 11:04:04.122729 ==
4206 11:04:04.124820 Write leveling (Byte 0): 31 => 31
4207 11:04:04.128523 Write leveling (Byte 1): 31 => 31
4208 11:04:04.131738 DramcWriteLeveling(PI) end<-----
4209 11:04:04.132162
4210 11:04:04.132512 ==
4211 11:04:04.135282 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 11:04:04.138459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 11:04:04.138892 ==
4214 11:04:04.142132 [Gating] SW mode calibration
4215 11:04:04.148317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4216 11:04:04.155503 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4217 11:04:04.158408 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 11:04:04.165296 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 11:04:04.168353 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 11:04:04.171562 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 1)
4221 11:04:04.177815 0 9 16 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
4222 11:04:04.181263 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 11:04:04.184932 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 11:04:04.190960 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:04:04.194787 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:04:04.197818 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 11:04:04.204407 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 11:04:04.207641 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4229 11:04:04.210599 0 10 16 | B1->B0 | 3636 4242 | 1 0 | (0 0) (0 0)
4230 11:04:04.217496 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:04:04.220959 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:04:04.224297 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:04:04.230710 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:04:04.233765 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 11:04:04.237274 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 11:04:04.244116 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 11:04:04.246885 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4238 11:04:04.250371 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:04:04.257100 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:04:04.260245 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:04:04.263808 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:04:04.270291 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:04:04.273225 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:04:04.276456 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:04:04.283407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:04:04.286776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:04:04.290210 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:04:04.296860 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:04:04.300243 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:04:04.303130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:04:04.309651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:04:04.313200 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4253 11:04:04.316404 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4254 11:04:04.323157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 11:04:04.323583 Total UI for P1: 0, mck2ui 16
4256 11:04:04.329592 best dqsien dly found for B0: ( 0, 13, 14)
4257 11:04:04.330007 Total UI for P1: 0, mck2ui 16
4258 11:04:04.336210 best dqsien dly found for B1: ( 0, 13, 18)
4259 11:04:04.339706 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4260 11:04:04.342703 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4261 11:04:04.343055
4262 11:04:04.345917 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4263 11:04:04.349384 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4264 11:04:04.352767 [Gating] SW calibration Done
4265 11:04:04.353203 ==
4266 11:04:04.355928 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 11:04:04.359565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 11:04:04.359955 ==
4269 11:04:04.362996 RX Vref Scan: 0
4270 11:04:04.363488
4271 11:04:04.363812 RX Vref 0 -> 0, step: 1
4272 11:04:04.366051
4273 11:04:04.366508 RX Delay -230 -> 252, step: 16
4274 11:04:04.372577 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4275 11:04:04.375858 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4276 11:04:04.379347 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4277 11:04:04.382367 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4278 11:04:04.389054 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4279 11:04:04.392415 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4280 11:04:04.395889 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4281 11:04:04.399107 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4282 11:04:04.402144 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4283 11:04:04.408771 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4284 11:04:04.411920 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4285 11:04:04.415631 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4286 11:04:04.418661 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4287 11:04:04.425037 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4288 11:04:04.428491 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4289 11:04:04.431903 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4290 11:04:04.432420 ==
4291 11:04:04.435283 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 11:04:04.441888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 11:04:04.442380 ==
4294 11:04:04.442714 DQS Delay:
4295 11:04:04.443025 DQS0 = 0, DQS1 = 0
4296 11:04:04.444985 DQM Delay:
4297 11:04:04.445469 DQM0 = 42, DQM1 = 33
4298 11:04:04.448663 DQ Delay:
4299 11:04:04.451548 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4300 11:04:04.455238 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4301 11:04:04.457992 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4302 11:04:04.461549 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4303 11:04:04.462073
4304 11:04:04.462409
4305 11:04:04.462717 ==
4306 11:04:04.464706 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 11:04:04.468282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 11:04:04.468713 ==
4309 11:04:04.469048
4310 11:04:04.469349
4311 11:04:04.471406 TX Vref Scan disable
4312 11:04:04.474500 == TX Byte 0 ==
4313 11:04:04.477893 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4314 11:04:04.481091 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4315 11:04:04.484439 == TX Byte 1 ==
4316 11:04:04.487948 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4317 11:04:04.491276 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4318 11:04:04.491877 ==
4319 11:04:04.494421 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 11:04:04.498088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 11:04:04.501131 ==
4322 11:04:04.501574
4323 11:04:04.502009
4324 11:04:04.502415 TX Vref Scan disable
4325 11:04:04.504658 == TX Byte 0 ==
4326 11:04:04.508203 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4327 11:04:04.514641 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4328 11:04:04.515146 == TX Byte 1 ==
4329 11:04:04.518157 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4330 11:04:04.524475 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4331 11:04:04.524925
4332 11:04:04.525361 [DATLAT]
4333 11:04:04.525772 Freq=600, CH0 RK1
4334 11:04:04.526187
4335 11:04:04.527966 DATLAT Default: 0x9
4336 11:04:04.528541 0, 0xFFFF, sum = 0
4337 11:04:04.531240 1, 0xFFFF, sum = 0
4338 11:04:04.534955 2, 0xFFFF, sum = 0
4339 11:04:04.535467 3, 0xFFFF, sum = 0
4340 11:04:04.537927 4, 0xFFFF, sum = 0
4341 11:04:04.538490 5, 0xFFFF, sum = 0
4342 11:04:04.541102 6, 0xFFFF, sum = 0
4343 11:04:04.541601 7, 0xFFFF, sum = 0
4344 11:04:04.544218 8, 0x0, sum = 1
4345 11:04:04.544722 9, 0x0, sum = 2
4346 11:04:04.545186 10, 0x0, sum = 3
4347 11:04:04.548156 11, 0x0, sum = 4
4348 11:04:04.548618 best_step = 9
4349 11:04:04.549019
4350 11:04:04.551112 ==
4351 11:04:04.551592 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 11:04:04.557230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 11:04:04.557567 ==
4354 11:04:04.557782 RX Vref Scan: 0
4355 11:04:04.557990
4356 11:04:04.560707 RX Vref 0 -> 0, step: 1
4357 11:04:04.561058
4358 11:04:04.564196 RX Delay -195 -> 252, step: 8
4359 11:04:04.570564 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4360 11:04:04.573876 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4361 11:04:04.577290 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4362 11:04:04.580483 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4363 11:04:04.583837 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4364 11:04:04.590762 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4365 11:04:04.593647 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4366 11:04:04.597338 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4367 11:04:04.600097 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4368 11:04:04.606979 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4369 11:04:04.610369 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4370 11:04:04.613787 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4371 11:04:04.617210 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4372 11:04:04.624250 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4373 11:04:04.627411 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4374 11:04:04.630528 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4375 11:04:04.630954 ==
4376 11:04:04.633638 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 11:04:04.637365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 11:04:04.637808 ==
4379 11:04:04.640320 DQS Delay:
4380 11:04:04.640746 DQS0 = 0, DQS1 = 0
4381 11:04:04.643732 DQM Delay:
4382 11:04:04.644124 DQM0 = 40, DQM1 = 37
4383 11:04:04.644423 DQ Delay:
4384 11:04:04.647266 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =36
4385 11:04:04.650480 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4386 11:04:04.653414 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4387 11:04:04.656683 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4388 11:04:04.657108
4389 11:04:04.660178
4390 11:04:04.666491 [DQSOSCAuto] RK1, (LSB)MR18= 0x6618, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4391 11:04:04.669731 CH0 RK1: MR19=808, MR18=6618
4392 11:04:04.676691 CH0_RK1: MR19=0x808, MR18=0x6618, DQSOSC=390, MR23=63, INC=172, DEC=114
4393 11:04:04.679890 [RxdqsGatingPostProcess] freq 600
4394 11:04:04.682962 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4395 11:04:04.686014 Pre-setting of DQS Precalculation
4396 11:04:04.692736 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4397 11:04:04.693352 ==
4398 11:04:04.695997 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 11:04:04.699268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 11:04:04.699731 ==
4401 11:04:04.706317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 11:04:04.709123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4403 11:04:04.713780 [CA 0] Center 35 (5~66) winsize 62
4404 11:04:04.716792 [CA 1] Center 35 (5~66) winsize 62
4405 11:04:04.720176 [CA 2] Center 34 (3~65) winsize 63
4406 11:04:04.723672 [CA 3] Center 33 (3~64) winsize 62
4407 11:04:04.726941 [CA 4] Center 34 (4~65) winsize 62
4408 11:04:04.730374 [CA 5] Center 33 (3~64) winsize 62
4409 11:04:04.730871
4410 11:04:04.733627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4411 11:04:04.734054
4412 11:04:04.737223 [CATrainingPosCal] consider 1 rank data
4413 11:04:04.740157 u2DelayCellTimex100 = 270/100 ps
4414 11:04:04.743808 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4415 11:04:04.750355 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 11:04:04.753176 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4417 11:04:04.756455 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 11:04:04.759855 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 11:04:04.763320 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 11:04:04.763892
4421 11:04:04.766207 CA PerBit enable=1, Macro0, CA PI delay=33
4422 11:04:04.766637
4423 11:04:04.769754 [CBTSetCACLKResult] CA Dly = 33
4424 11:04:04.773001 CS Dly: 5 (0~36)
4425 11:04:04.773652 ==
4426 11:04:04.775841 Dram Type= 6, Freq= 0, CH_1, rank 1
4427 11:04:04.779593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 11:04:04.780091 ==
4429 11:04:04.785816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4430 11:04:04.789386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4431 11:04:04.793939 [CA 0] Center 35 (5~66) winsize 62
4432 11:04:04.796974 [CA 1] Center 36 (6~66) winsize 61
4433 11:04:04.800299 [CA 2] Center 34 (4~65) winsize 62
4434 11:04:04.804163 [CA 3] Center 33 (3~64) winsize 62
4435 11:04:04.807200 [CA 4] Center 34 (3~65) winsize 63
4436 11:04:04.810277 [CA 5] Center 34 (3~65) winsize 63
4437 11:04:04.810753
4438 11:04:04.813742 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4439 11:04:04.814215
4440 11:04:04.817058 [CATrainingPosCal] consider 2 rank data
4441 11:04:04.820287 u2DelayCellTimex100 = 270/100 ps
4442 11:04:04.823614 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4443 11:04:04.829977 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4444 11:04:04.833108 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4445 11:04:04.836574 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4446 11:04:04.839819 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 11:04:04.843086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4448 11:04:04.843514
4449 11:04:04.846444 CA PerBit enable=1, Macro0, CA PI delay=33
4450 11:04:04.846833
4451 11:04:04.850138 [CBTSetCACLKResult] CA Dly = 33
4452 11:04:04.852984 CS Dly: 5 (0~36)
4453 11:04:04.853374
4454 11:04:04.856652 ----->DramcWriteLeveling(PI) begin...
4455 11:04:04.857053 ==
4456 11:04:04.859996 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 11:04:04.863322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 11:04:04.863844 ==
4459 11:04:04.866809 Write leveling (Byte 0): 29 => 29
4460 11:04:04.869885 Write leveling (Byte 1): 28 => 28
4461 11:04:04.872767 DramcWriteLeveling(PI) end<-----
4462 11:04:04.873200
4463 11:04:04.873532 ==
4464 11:04:04.876071 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 11:04:04.879992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 11:04:04.880509 ==
4467 11:04:04.882880 [Gating] SW mode calibration
4468 11:04:04.889749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4469 11:04:04.895971 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4470 11:04:04.899387 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 11:04:04.902751 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 11:04:04.909334 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 11:04:04.912518 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 1)
4474 11:04:04.916037 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4475 11:04:04.922977 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 11:04:04.926455 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 11:04:04.928971 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 11:04:04.935881 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 11:04:04.939251 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 11:04:04.942377 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4481 11:04:04.948960 0 10 12 | B1->B0 | 3232 4242 | 0 0 | (1 1) (1 1)
4482 11:04:04.952423 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4483 11:04:04.955279 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 11:04:04.962408 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 11:04:04.965771 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 11:04:04.968879 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 11:04:04.975491 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 11:04:04.978843 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 11:04:04.982004 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:04:04.988546 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:04:04.991925 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:04:04.995337 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:04:05.001660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:04:05.004801 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:04:05.008678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:04:05.014711 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:04:05.017998 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:04:05.021307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:04:05.027624 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:04:05.031926 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:04:05.034344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:04:05.041430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:04:05.045017 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:04:05.048085 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:04:05.054239 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4506 11:04:05.057592 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 11:04:05.060752 Total UI for P1: 0, mck2ui 16
4508 11:04:05.064335 best dqsien dly found for B0: ( 0, 13, 12)
4509 11:04:05.067773 Total UI for P1: 0, mck2ui 16
4510 11:04:05.071286 best dqsien dly found for B1: ( 0, 13, 12)
4511 11:04:05.074278 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4512 11:04:05.078028 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4513 11:04:05.078432
4514 11:04:05.080757 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4515 11:04:05.084141 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4516 11:04:05.087391 [Gating] SW calibration Done
4517 11:04:05.087839 ==
4518 11:04:05.090780 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 11:04:05.097179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 11:04:05.097656 ==
4521 11:04:05.098056 RX Vref Scan: 0
4522 11:04:05.098430
4523 11:04:05.100509 RX Vref 0 -> 0, step: 1
4524 11:04:05.100910
4525 11:04:05.104241 RX Delay -230 -> 252, step: 16
4526 11:04:05.107492 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4527 11:04:05.110708 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4528 11:04:05.114014 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4529 11:04:05.120716 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4530 11:04:05.123535 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4531 11:04:05.127141 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4532 11:04:05.130162 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4533 11:04:05.137132 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4534 11:04:05.140410 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4535 11:04:05.144019 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4536 11:04:05.147515 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4537 11:04:05.153738 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4538 11:04:05.156951 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4539 11:04:05.160285 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4540 11:04:05.163456 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4541 11:04:05.170044 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4542 11:04:05.170513 ==
4543 11:04:05.173454 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 11:04:05.176952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 11:04:05.177430 ==
4546 11:04:05.177737 DQS Delay:
4547 11:04:05.179757 DQS0 = 0, DQS1 = 0
4548 11:04:05.180145 DQM Delay:
4549 11:04:05.183277 DQM0 = 43, DQM1 = 34
4550 11:04:05.183743 DQ Delay:
4551 11:04:05.186632 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4552 11:04:05.190429 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4553 11:04:05.193320 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4554 11:04:05.196537 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4555 11:04:05.196966
4556 11:04:05.197294
4557 11:04:05.197593 ==
4558 11:04:05.200141 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 11:04:05.203223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 11:04:05.203792 ==
4561 11:04:05.204134
4562 11:04:05.204436
4563 11:04:05.206960 TX Vref Scan disable
4564 11:04:05.209667 == TX Byte 0 ==
4565 11:04:05.213207 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 11:04:05.216488 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 11:04:05.219486 == TX Byte 1 ==
4568 11:04:05.222861 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4569 11:04:05.226520 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4570 11:04:05.227032 ==
4571 11:04:05.229878 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 11:04:05.236211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 11:04:05.236740 ==
4574 11:04:05.237074
4575 11:04:05.237377
4576 11:04:05.237670 TX Vref Scan disable
4577 11:04:05.241043 == TX Byte 0 ==
4578 11:04:05.244013 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 11:04:05.251079 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 11:04:05.251657 == TX Byte 1 ==
4581 11:04:05.253911 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4582 11:04:05.260542 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4583 11:04:05.261007
4584 11:04:05.261443 [DATLAT]
4585 11:04:05.261852 Freq=600, CH1 RK0
4586 11:04:05.262254
4587 11:04:05.263792 DATLAT Default: 0x9
4588 11:04:05.267038 0, 0xFFFF, sum = 0
4589 11:04:05.267520 1, 0xFFFF, sum = 0
4590 11:04:05.270371 2, 0xFFFF, sum = 0
4591 11:04:05.270824 3, 0xFFFF, sum = 0
4592 11:04:05.273552 4, 0xFFFF, sum = 0
4593 11:04:05.274017 5, 0xFFFF, sum = 0
4594 11:04:05.276648 6, 0xFFFF, sum = 0
4595 11:04:05.277101 7, 0xFFFF, sum = 0
4596 11:04:05.280267 8, 0x0, sum = 1
4597 11:04:05.280734 9, 0x0, sum = 2
4598 11:04:05.283523 10, 0x0, sum = 3
4599 11:04:05.283976 11, 0x0, sum = 4
4600 11:04:05.284421 best_step = 9
4601 11:04:05.284838
4602 11:04:05.286866 ==
4603 11:04:05.290032 Dram Type= 6, Freq= 0, CH_1, rank 0
4604 11:04:05.293471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 11:04:05.293877 ==
4606 11:04:05.294275 RX Vref Scan: 1
4607 11:04:05.294649
4608 11:04:05.297140 RX Vref 0 -> 0, step: 1
4609 11:04:05.297631
4610 11:04:05.299930 RX Delay -195 -> 252, step: 8
4611 11:04:05.300319
4612 11:04:05.303255 Set Vref, RX VrefLevel [Byte0]: 50
4613 11:04:05.306665 [Byte1]: 61
4614 11:04:05.307069
4615 11:04:05.309920 Final RX Vref Byte 0 = 50 to rank0
4616 11:04:05.313553 Final RX Vref Byte 1 = 61 to rank0
4617 11:04:05.316474 Final RX Vref Byte 0 = 50 to rank1
4618 11:04:05.319898 Final RX Vref Byte 1 = 61 to rank1==
4619 11:04:05.323095 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 11:04:05.326569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 11:04:05.329967 ==
4622 11:04:05.330371 DQS Delay:
4623 11:04:05.330773 DQS0 = 0, DQS1 = 0
4624 11:04:05.332725 DQM Delay:
4625 11:04:05.333129 DQM0 = 45, DQM1 = 34
4626 11:04:05.336176 DQ Delay:
4627 11:04:05.339897 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4628 11:04:05.340371 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4629 11:04:05.343049 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4630 11:04:05.346370 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4631 11:04:05.349912
4632 11:04:05.350441
4633 11:04:05.356276 [DQSOSCAuto] RK0, (LSB)MR18= 0x5337, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4634 11:04:05.359582 CH1 RK0: MR19=808, MR18=5337
4635 11:04:05.366206 CH1_RK0: MR19=0x808, MR18=0x5337, DQSOSC=394, MR23=63, INC=168, DEC=112
4636 11:04:05.366645
4637 11:04:05.369322 ----->DramcWriteLeveling(PI) begin...
4638 11:04:05.369836 ==
4639 11:04:05.372508 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 11:04:05.376031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 11:04:05.376427 ==
4642 11:04:05.378822 Write leveling (Byte 0): 29 => 29
4643 11:04:05.382721 Write leveling (Byte 1): 32 => 32
4644 11:04:05.385888 DramcWriteLeveling(PI) end<-----
4645 11:04:05.386279
4646 11:04:05.386583 ==
4647 11:04:05.388913 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 11:04:05.392727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 11:04:05.393119 ==
4650 11:04:05.395570 [Gating] SW mode calibration
4651 11:04:05.402226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4652 11:04:05.408782 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4653 11:04:05.412269 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 11:04:05.419170 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 11:04:05.421989 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 11:04:05.425393 0 9 12 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (1 0)
4657 11:04:05.432161 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 11:04:05.435300 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 11:04:05.438735 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 11:04:05.445276 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 11:04:05.448851 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 11:04:05.451737 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 11:04:05.458628 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 11:04:05.462043 0 10 12 | B1->B0 | 3838 2e2e | 0 0 | (0 0) (0 0)
4665 11:04:05.465290 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 11:04:05.471933 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 11:04:05.474779 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 11:04:05.478389 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:04:05.484856 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 11:04:05.487978 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 11:04:05.491200 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 11:04:05.498729 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 11:04:05.501856 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:04:05.504478 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:04:05.511573 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:04:05.514760 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:04:05.518213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:04:05.524503 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:04:05.528064 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:04:05.531189 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:04:05.537765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:04:05.540848 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:04:05.544254 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:04:05.551059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:04:05.554386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:04:05.557397 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:04:05.563921 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:04:05.567223 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4689 11:04:05.570740 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:04:05.573679 Total UI for P1: 0, mck2ui 16
4691 11:04:05.577203 best dqsien dly found for B0: ( 0, 13, 12)
4692 11:04:05.580242 Total UI for P1: 0, mck2ui 16
4693 11:04:05.583920 best dqsien dly found for B1: ( 0, 13, 12)
4694 11:04:05.586954 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4695 11:04:05.590368 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4696 11:04:05.590949
4697 11:04:05.596811 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4698 11:04:05.600216 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4699 11:04:05.600616 [Gating] SW calibration Done
4700 11:04:05.603183 ==
4701 11:04:05.606715 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 11:04:05.609843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 11:04:05.610250 ==
4704 11:04:05.610655 RX Vref Scan: 0
4705 11:04:05.611026
4706 11:04:05.613442 RX Vref 0 -> 0, step: 1
4707 11:04:05.613828
4708 11:04:05.616765 RX Delay -230 -> 252, step: 16
4709 11:04:05.620253 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4710 11:04:05.623614 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4711 11:04:05.630114 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4712 11:04:05.633097 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4713 11:04:05.636687 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4714 11:04:05.639864 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4715 11:04:05.646482 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4716 11:04:05.649664 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4717 11:04:05.652918 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4718 11:04:05.656203 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4719 11:04:05.659464 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4720 11:04:05.666484 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4721 11:04:05.669854 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4722 11:04:05.672856 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4723 11:04:05.679403 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4724 11:04:05.682648 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4725 11:04:05.683057 ==
4726 11:04:05.685964 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 11:04:05.689404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 11:04:05.689796 ==
4729 11:04:05.692702 DQS Delay:
4730 11:04:05.693096 DQS0 = 0, DQS1 = 0
4731 11:04:05.693400 DQM Delay:
4732 11:04:05.696081 DQM0 = 40, DQM1 = 33
4733 11:04:05.696472 DQ Delay:
4734 11:04:05.699171 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4735 11:04:05.702879 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4736 11:04:05.706082 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4737 11:04:05.708805 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4738 11:04:05.709219
4739 11:04:05.709615
4740 11:04:05.709989 ==
4741 11:04:05.712193 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 11:04:05.719014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 11:04:05.719411 ==
4744 11:04:05.719769
4745 11:04:05.720050
4746 11:04:05.720315 TX Vref Scan disable
4747 11:04:05.722463 == TX Byte 0 ==
4748 11:04:05.725709 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4749 11:04:05.732423 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4750 11:04:05.732897 == TX Byte 1 ==
4751 11:04:05.735585 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4752 11:04:05.742001 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4753 11:04:05.742398 ==
4754 11:04:05.745217 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 11:04:05.749068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 11:04:05.749462 ==
4757 11:04:05.749762
4758 11:04:05.750042
4759 11:04:05.752028 TX Vref Scan disable
4760 11:04:05.755246 == TX Byte 0 ==
4761 11:04:05.758755 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4762 11:04:05.762141 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4763 11:04:05.765237 == TX Byte 1 ==
4764 11:04:05.768312 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4765 11:04:05.771613 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4766 11:04:05.772004
4767 11:04:05.775099 [DATLAT]
4768 11:04:05.775527 Freq=600, CH1 RK1
4769 11:04:05.775839
4770 11:04:05.778369 DATLAT Default: 0x9
4771 11:04:05.778757 0, 0xFFFF, sum = 0
4772 11:04:05.781560 1, 0xFFFF, sum = 0
4773 11:04:05.781957 2, 0xFFFF, sum = 0
4774 11:04:05.784657 3, 0xFFFF, sum = 0
4775 11:04:05.785057 4, 0xFFFF, sum = 0
4776 11:04:05.787998 5, 0xFFFF, sum = 0
4777 11:04:05.788395 6, 0xFFFF, sum = 0
4778 11:04:05.791505 7, 0xFFFF, sum = 0
4779 11:04:05.792087 8, 0x0, sum = 1
4780 11:04:05.794896 9, 0x0, sum = 2
4781 11:04:05.795524 10, 0x0, sum = 3
4782 11:04:05.797748 11, 0x0, sum = 4
4783 11:04:05.798321 best_step = 9
4784 11:04:05.798823
4785 11:04:05.799309 ==
4786 11:04:05.801267 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 11:04:05.804309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 11:04:05.808057 ==
4789 11:04:05.808629 RX Vref Scan: 0
4790 11:04:05.809161
4791 11:04:05.811386 RX Vref 0 -> 0, step: 1
4792 11:04:05.811814
4793 11:04:05.814491 RX Delay -195 -> 252, step: 8
4794 11:04:05.817891 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4795 11:04:05.824217 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4796 11:04:05.827920 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4797 11:04:05.831158 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4798 11:04:05.834128 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4799 11:04:05.838176 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4800 11:04:05.844276 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4801 11:04:05.847581 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4802 11:04:05.850761 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4803 11:04:05.854060 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4804 11:04:05.860661 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4805 11:04:05.863922 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4806 11:04:05.867418 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4807 11:04:05.870629 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4808 11:04:05.877258 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4809 11:04:05.880701 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4810 11:04:05.881165 ==
4811 11:04:05.884151 Dram Type= 6, Freq= 0, CH_1, rank 1
4812 11:04:05.886813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4813 11:04:05.887360 ==
4814 11:04:05.890498 DQS Delay:
4815 11:04:05.890885 DQS0 = 0, DQS1 = 0
4816 11:04:05.891182 DQM Delay:
4817 11:04:05.893650 DQM0 = 42, DQM1 = 34
4818 11:04:05.894035 DQ Delay:
4819 11:04:05.897018 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4820 11:04:05.900788 DQ4 =40, DQ5 =56, DQ6 =56, DQ7 =40
4821 11:04:05.903403 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4822 11:04:05.907293 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4823 11:04:05.907847
4824 11:04:05.908157
4825 11:04:05.916810 [DQSOSCAuto] RK1, (LSB)MR18= 0x3025, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4826 11:04:05.920005 CH1 RK1: MR19=808, MR18=3025
4827 11:04:05.923422 CH1_RK1: MR19=0x808, MR18=0x3025, DQSOSC=400, MR23=63, INC=163, DEC=109
4828 11:04:05.926264 [RxdqsGatingPostProcess] freq 600
4829 11:04:05.933383 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4830 11:04:05.936190 Pre-setting of DQS Precalculation
4831 11:04:05.939852 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4832 11:04:05.950176 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4833 11:04:05.956182 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4834 11:04:05.956775
4835 11:04:05.957103
4836 11:04:05.959820 [Calibration Summary] 1200 Mbps
4837 11:04:05.960224 CH 0, Rank 0
4838 11:04:05.962668 SW Impedance : PASS
4839 11:04:05.963060 DUTY Scan : NO K
4840 11:04:05.966348 ZQ Calibration : PASS
4841 11:04:05.969531 Jitter Meter : NO K
4842 11:04:05.970075 CBT Training : PASS
4843 11:04:05.972645 Write leveling : PASS
4844 11:04:05.976192 RX DQS gating : PASS
4845 11:04:05.976579 RX DQ/DQS(RDDQC) : PASS
4846 11:04:05.979345 TX DQ/DQS : PASS
4847 11:04:05.982919 RX DATLAT : PASS
4848 11:04:05.983337 RX DQ/DQS(Engine): PASS
4849 11:04:05.985772 TX OE : NO K
4850 11:04:05.986193 All Pass.
4851 11:04:05.986652
4852 11:04:05.989331 CH 0, Rank 1
4853 11:04:05.989655 SW Impedance : PASS
4854 11:04:05.992421 DUTY Scan : NO K
4855 11:04:05.995333 ZQ Calibration : PASS
4856 11:04:05.995451 Jitter Meter : NO K
4857 11:04:05.998892 CBT Training : PASS
4858 11:04:05.998965 Write leveling : PASS
4859 11:04:06.002444 RX DQS gating : PASS
4860 11:04:06.005314 RX DQ/DQS(RDDQC) : PASS
4861 11:04:06.005379 TX DQ/DQS : PASS
4862 11:04:06.008915 RX DATLAT : PASS
4863 11:04:06.012016 RX DQ/DQS(Engine): PASS
4864 11:04:06.012091 TX OE : NO K
4865 11:04:06.015798 All Pass.
4866 11:04:06.016180
4867 11:04:06.016536 CH 1, Rank 0
4868 11:04:06.019089 SW Impedance : PASS
4869 11:04:06.019514 DUTY Scan : NO K
4870 11:04:06.022328 ZQ Calibration : PASS
4871 11:04:06.026073 Jitter Meter : NO K
4872 11:04:06.026507 CBT Training : PASS
4873 11:04:06.028760 Write leveling : PASS
4874 11:04:06.032062 RX DQS gating : PASS
4875 11:04:06.032451 RX DQ/DQS(RDDQC) : PASS
4876 11:04:06.035584 TX DQ/DQS : PASS
4877 11:04:06.038965 RX DATLAT : PASS
4878 11:04:06.039351 RX DQ/DQS(Engine): PASS
4879 11:04:06.042068 TX OE : NO K
4880 11:04:06.042441 All Pass.
4881 11:04:06.042779
4882 11:04:06.045337 CH 1, Rank 1
4883 11:04:06.045719 SW Impedance : PASS
4884 11:04:06.048960 DUTY Scan : NO K
4885 11:04:06.051792 ZQ Calibration : PASS
4886 11:04:06.052370 Jitter Meter : NO K
4887 11:04:06.055535 CBT Training : PASS
4888 11:04:06.058908 Write leveling : PASS
4889 11:04:06.059292 RX DQS gating : PASS
4890 11:04:06.062045 RX DQ/DQS(RDDQC) : PASS
4891 11:04:06.065252 TX DQ/DQS : PASS
4892 11:04:06.065664 RX DATLAT : PASS
4893 11:04:06.068160 RX DQ/DQS(Engine): PASS
4894 11:04:06.068565 TX OE : NO K
4895 11:04:06.071757 All Pass.
4896 11:04:06.072182
4897 11:04:06.072573 DramC Write-DBI off
4898 11:04:06.075107 PER_BANK_REFRESH: Hybrid Mode
4899 11:04:06.078521 TX_TRACKING: ON
4900 11:04:06.084858 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4901 11:04:06.088746 [FAST_K] Save calibration result to emmc
4902 11:04:06.095379 dramc_set_vcore_voltage set vcore to 662500
4903 11:04:06.095881 Read voltage for 933, 3
4904 11:04:06.096272 Vio18 = 0
4905 11:04:06.098282 Vcore = 662500
4906 11:04:06.098825 Vdram = 0
4907 11:04:06.099324 Vddq = 0
4908 11:04:06.101700 Vmddr = 0
4909 11:04:06.104905 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4910 11:04:06.111736 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4911 11:04:06.114932 MEM_TYPE=3, freq_sel=17
4912 11:04:06.118073 sv_algorithm_assistance_LP4_1600
4913 11:04:06.121568 ============ PULL DRAM RESETB DOWN ============
4914 11:04:06.124494 ========== PULL DRAM RESETB DOWN end =========
4915 11:04:06.127911 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4916 11:04:06.131189 ===================================
4917 11:04:06.134311 LPDDR4 DRAM CONFIGURATION
4918 11:04:06.137666 ===================================
4919 11:04:06.141011 EX_ROW_EN[0] = 0x0
4920 11:04:06.141409 EX_ROW_EN[1] = 0x0
4921 11:04:06.144360 LP4Y_EN = 0x0
4922 11:04:06.144755 WORK_FSP = 0x0
4923 11:04:06.147367 WL = 0x3
4924 11:04:06.147810 RL = 0x3
4925 11:04:06.150728 BL = 0x2
4926 11:04:06.151162 RPST = 0x0
4927 11:04:06.154209 RD_PRE = 0x0
4928 11:04:06.157454 WR_PRE = 0x1
4929 11:04:06.157957 WR_PST = 0x0
4930 11:04:06.160807 DBI_WR = 0x0
4931 11:04:06.161204 DBI_RD = 0x0
4932 11:04:06.164112 OTF = 0x1
4933 11:04:06.167456 ===================================
4934 11:04:06.170874 ===================================
4935 11:04:06.171316 ANA top config
4936 11:04:06.174201 ===================================
4937 11:04:06.177345 DLL_ASYNC_EN = 0
4938 11:04:06.180542 ALL_SLAVE_EN = 1
4939 11:04:06.180938 NEW_RANK_MODE = 1
4940 11:04:06.183919 DLL_IDLE_MODE = 1
4941 11:04:06.187225 LP45_APHY_COMB_EN = 1
4942 11:04:06.190731 TX_ODT_DIS = 1
4943 11:04:06.191133 NEW_8X_MODE = 1
4944 11:04:06.193725 ===================================
4945 11:04:06.196813 ===================================
4946 11:04:06.200806 data_rate = 1866
4947 11:04:06.203526 CKR = 1
4948 11:04:06.207203 DQ_P2S_RATIO = 8
4949 11:04:06.210493 ===================================
4950 11:04:06.213346 CA_P2S_RATIO = 8
4951 11:04:06.216763 DQ_CA_OPEN = 0
4952 11:04:06.220320 DQ_SEMI_OPEN = 0
4953 11:04:06.220721 CA_SEMI_OPEN = 0
4954 11:04:06.223777 CA_FULL_RATE = 0
4955 11:04:06.226924 DQ_CKDIV4_EN = 1
4956 11:04:06.230520 CA_CKDIV4_EN = 1
4957 11:04:06.233417 CA_PREDIV_EN = 0
4958 11:04:06.237150 PH8_DLY = 0
4959 11:04:06.237539 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4960 11:04:06.240123 DQ_AAMCK_DIV = 4
4961 11:04:06.243346 CA_AAMCK_DIV = 4
4962 11:04:06.246233 CA_ADMCK_DIV = 4
4963 11:04:06.249862 DQ_TRACK_CA_EN = 0
4964 11:04:06.252814 CA_PICK = 933
4965 11:04:06.256384 CA_MCKIO = 933
4966 11:04:06.256923 MCKIO_SEMI = 0
4967 11:04:06.259832 PLL_FREQ = 3732
4968 11:04:06.263179 DQ_UI_PI_RATIO = 32
4969 11:04:06.266079 CA_UI_PI_RATIO = 0
4970 11:04:06.269551 ===================================
4971 11:04:06.273091 ===================================
4972 11:04:06.276019 memory_type:LPDDR4
4973 11:04:06.276413 GP_NUM : 10
4974 11:04:06.279725 SRAM_EN : 1
4975 11:04:06.282845 MD32_EN : 0
4976 11:04:06.285975 ===================================
4977 11:04:06.286461 [ANA_INIT] >>>>>>>>>>>>>>
4978 11:04:06.289231 <<<<<< [CONFIGURE PHASE]: ANA_TX
4979 11:04:06.293117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4980 11:04:06.296222 ===================================
4981 11:04:06.299078 data_rate = 1866,PCW = 0X8f00
4982 11:04:06.302503 ===================================
4983 11:04:06.305592 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4984 11:04:06.312375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4985 11:04:06.315865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4986 11:04:06.322132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4987 11:04:06.325325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4988 11:04:06.329046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4989 11:04:06.329577 [ANA_INIT] flow start
4990 11:04:06.332369 [ANA_INIT] PLL >>>>>>>>
4991 11:04:06.335699 [ANA_INIT] PLL <<<<<<<<
4992 11:04:06.339052 [ANA_INIT] MIDPI >>>>>>>>
4993 11:04:06.339456 [ANA_INIT] MIDPI <<<<<<<<
4994 11:04:06.341964 [ANA_INIT] DLL >>>>>>>>
4995 11:04:06.345285 [ANA_INIT] flow end
4996 11:04:06.348932 ============ LP4 DIFF to SE enter ============
4997 11:04:06.352057 ============ LP4 DIFF to SE exit ============
4998 11:04:06.355751 [ANA_INIT] <<<<<<<<<<<<<
4999 11:04:06.358373 [Flow] Enable top DCM control >>>>>
5000 11:04:06.361660 [Flow] Enable top DCM control <<<<<
5001 11:04:06.364871 Enable DLL master slave shuffle
5002 11:04:06.368473 ==============================================================
5003 11:04:06.371712 Gating Mode config
5004 11:04:06.378102 ==============================================================
5005 11:04:06.378590 Config description:
5006 11:04:06.388397 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5007 11:04:06.395106 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5008 11:04:06.401410 SELPH_MODE 0: By rank 1: By Phase
5009 11:04:06.405083 ==============================================================
5010 11:04:06.408209 GAT_TRACK_EN = 1
5011 11:04:06.411338 RX_GATING_MODE = 2
5012 11:04:06.414695 RX_GATING_TRACK_MODE = 2
5013 11:04:06.418206 SELPH_MODE = 1
5014 11:04:06.421411 PICG_EARLY_EN = 1
5015 11:04:06.424800 VALID_LAT_VALUE = 1
5016 11:04:06.427947 ==============================================================
5017 11:04:06.431115 Enter into Gating configuration >>>>
5018 11:04:06.434279 Exit from Gating configuration <<<<
5019 11:04:06.437779 Enter into DVFS_PRE_config >>>>>
5020 11:04:06.450829 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5021 11:04:06.453862 Exit from DVFS_PRE_config <<<<<
5022 11:04:06.457585 Enter into PICG configuration >>>>
5023 11:04:06.460767 Exit from PICG configuration <<<<
5024 11:04:06.461248 [RX_INPUT] configuration >>>>>
5025 11:04:06.464128 [RX_INPUT] configuration <<<<<
5026 11:04:06.470486 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5027 11:04:06.473872 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5028 11:04:06.480667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5029 11:04:06.487030 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5030 11:04:06.493759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 11:04:06.500168 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 11:04:06.503911 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5033 11:04:06.506862 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5034 11:04:06.513792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5035 11:04:06.516527 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5036 11:04:06.520076 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5037 11:04:06.526672 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5038 11:04:06.529784 ===================================
5039 11:04:06.530202 LPDDR4 DRAM CONFIGURATION
5040 11:04:06.533074 ===================================
5041 11:04:06.536501 EX_ROW_EN[0] = 0x0
5042 11:04:06.536959 EX_ROW_EN[1] = 0x0
5043 11:04:06.539768 LP4Y_EN = 0x0
5044 11:04:06.540212 WORK_FSP = 0x0
5045 11:04:06.543377 WL = 0x3
5046 11:04:06.546435 RL = 0x3
5047 11:04:06.547085 BL = 0x2
5048 11:04:06.549798 RPST = 0x0
5049 11:04:06.550190 RD_PRE = 0x0
5050 11:04:06.552686 WR_PRE = 0x1
5051 11:04:06.553111 WR_PST = 0x0
5052 11:04:06.556040 DBI_WR = 0x0
5053 11:04:06.556491 DBI_RD = 0x0
5054 11:04:06.559912 OTF = 0x1
5055 11:04:06.562944 ===================================
5056 11:04:06.566209 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5057 11:04:06.569642 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5058 11:04:06.576424 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5059 11:04:06.579528 ===================================
5060 11:04:06.579996 LPDDR4 DRAM CONFIGURATION
5061 11:04:06.582855 ===================================
5062 11:04:06.586124 EX_ROW_EN[0] = 0x10
5063 11:04:06.586516 EX_ROW_EN[1] = 0x0
5064 11:04:06.589426 LP4Y_EN = 0x0
5065 11:04:06.589818 WORK_FSP = 0x0
5066 11:04:06.592884 WL = 0x3
5067 11:04:06.593320 RL = 0x3
5068 11:04:06.596031 BL = 0x2
5069 11:04:06.599489 RPST = 0x0
5070 11:04:06.599930 RD_PRE = 0x0
5071 11:04:06.602941 WR_PRE = 0x1
5072 11:04:06.603348 WR_PST = 0x0
5073 11:04:06.606327 DBI_WR = 0x0
5074 11:04:06.606839 DBI_RD = 0x0
5075 11:04:06.609362 OTF = 0x1
5076 11:04:06.612879 ===================================
5077 11:04:06.615800 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5078 11:04:06.621704 nWR fixed to 30
5079 11:04:06.624823 [ModeRegInit_LP4] CH0 RK0
5080 11:04:06.625217 [ModeRegInit_LP4] CH0 RK1
5081 11:04:06.627917 [ModeRegInit_LP4] CH1 RK0
5082 11:04:06.631420 [ModeRegInit_LP4] CH1 RK1
5083 11:04:06.631991 match AC timing 9
5084 11:04:06.637860 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5085 11:04:06.641412 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5086 11:04:06.644627 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5087 11:04:06.651409 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5088 11:04:06.654391 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5089 11:04:06.654781 ==
5090 11:04:06.657685 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 11:04:06.661140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 11:04:06.661652 ==
5093 11:04:06.667788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 11:04:06.674065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5095 11:04:06.677712 [CA 0] Center 37 (7~68) winsize 62
5096 11:04:06.681051 [CA 1] Center 37 (7~68) winsize 62
5097 11:04:06.684092 [CA 2] Center 34 (4~65) winsize 62
5098 11:04:06.687506 [CA 3] Center 34 (4~65) winsize 62
5099 11:04:06.691017 [CA 4] Center 33 (3~64) winsize 62
5100 11:04:06.694363 [CA 5] Center 33 (3~63) winsize 61
5101 11:04:06.694887
5102 11:04:06.698222 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5103 11:04:06.698610
5104 11:04:06.700855 [CATrainingPosCal] consider 1 rank data
5105 11:04:06.704498 u2DelayCellTimex100 = 270/100 ps
5106 11:04:06.707218 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5107 11:04:06.710937 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5108 11:04:06.713727 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5109 11:04:06.717256 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5110 11:04:06.723719 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5111 11:04:06.727165 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5112 11:04:06.727600
5113 11:04:06.730036 CA PerBit enable=1, Macro0, CA PI delay=33
5114 11:04:06.730428
5115 11:04:06.733666 [CBTSetCACLKResult] CA Dly = 33
5116 11:04:06.734215 CS Dly: 7 (0~38)
5117 11:04:06.734748 ==
5118 11:04:06.736850 Dram Type= 6, Freq= 0, CH_0, rank 1
5119 11:04:06.743278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 11:04:06.743840 ==
5121 11:04:06.746368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5122 11:04:06.752977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5123 11:04:06.756538 [CA 0] Center 37 (7~68) winsize 62
5124 11:04:06.759864 [CA 1] Center 37 (7~68) winsize 62
5125 11:04:06.763009 [CA 2] Center 34 (4~65) winsize 62
5126 11:04:06.766229 [CA 3] Center 34 (4~65) winsize 62
5127 11:04:06.769560 [CA 4] Center 33 (3~64) winsize 62
5128 11:04:06.773275 [CA 5] Center 33 (3~63) winsize 61
5129 11:04:06.773731
5130 11:04:06.776281 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5131 11:04:06.776665
5132 11:04:06.779316 [CATrainingPosCal] consider 2 rank data
5133 11:04:06.782732 u2DelayCellTimex100 = 270/100 ps
5134 11:04:06.786202 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5135 11:04:06.793110 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5136 11:04:06.796368 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5137 11:04:06.799343 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5138 11:04:06.802834 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5139 11:04:06.806226 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5140 11:04:06.806645
5141 11:04:06.809554 CA PerBit enable=1, Macro0, CA PI delay=33
5142 11:04:06.809955
5143 11:04:06.812925 [CBTSetCACLKResult] CA Dly = 33
5144 11:04:06.815793 CS Dly: 7 (0~39)
5145 11:04:06.816182
5146 11:04:06.819213 ----->DramcWriteLeveling(PI) begin...
5147 11:04:06.819656 ==
5148 11:04:06.822712 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 11:04:06.825806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 11:04:06.826301 ==
5151 11:04:06.829180 Write leveling (Byte 0): 32 => 32
5152 11:04:06.832167 Write leveling (Byte 1): 28 => 28
5153 11:04:06.835464 DramcWriteLeveling(PI) end<-----
5154 11:04:06.835956
5155 11:04:06.836453 ==
5156 11:04:06.838863 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 11:04:06.842357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 11:04:06.842898 ==
5159 11:04:06.845866 [Gating] SW mode calibration
5160 11:04:06.851914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5161 11:04:06.858602 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5162 11:04:06.861885 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5163 11:04:06.868226 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5164 11:04:06.871839 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 11:04:06.875024 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 11:04:06.881604 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 11:04:06.884553 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 11:04:06.888263 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 11:04:06.894617 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5170 11:04:06.897897 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5171 11:04:06.901413 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 11:04:06.907982 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 11:04:06.911010 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 11:04:06.914487 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 11:04:06.921209 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 11:04:06.924376 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 11:04:06.927718 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5178 11:04:06.931166 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
5179 11:04:06.937568 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 11:04:06.941081 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 11:04:06.944177 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 11:04:06.950810 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 11:04:06.953918 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 11:04:06.957731 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 11:04:06.963998 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5186 11:04:06.967136 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5187 11:04:06.970929 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 11:04:06.977187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:04:06.980721 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:04:06.983669 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:04:06.990380 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:04:06.994082 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:04:06.997148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:04:07.003576 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:04:07.007387 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:04:07.010778 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:04:07.016850 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:04:07.020613 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:04:07.023598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:04:07.030313 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:04:07.033598 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:04:07.036934 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5203 11:04:07.040397 Total UI for P1: 0, mck2ui 16
5204 11:04:07.043310 best dqsien dly found for B0: ( 1, 2, 30)
5205 11:04:07.050245 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5206 11:04:07.053352 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 11:04:07.056781 Total UI for P1: 0, mck2ui 16
5208 11:04:07.059901 best dqsien dly found for B1: ( 1, 3, 2)
5209 11:04:07.063131 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5210 11:04:07.066345 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5211 11:04:07.066744
5212 11:04:07.069955 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5213 11:04:07.072961 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5214 11:04:07.076510 [Gating] SW calibration Done
5215 11:04:07.076912 ==
5216 11:04:07.080226 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 11:04:07.083279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 11:04:07.086386 ==
5219 11:04:07.086784 RX Vref Scan: 0
5220 11:04:07.087179
5221 11:04:07.089967 RX Vref 0 -> 0, step: 1
5222 11:04:07.090366
5223 11:04:07.093110 RX Delay -80 -> 252, step: 8
5224 11:04:07.096304 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5225 11:04:07.099741 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5226 11:04:07.102872 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5227 11:04:07.106288 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5228 11:04:07.109859 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5229 11:04:07.116105 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5230 11:04:07.119210 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5231 11:04:07.122600 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5232 11:04:07.125958 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5233 11:04:07.129575 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5234 11:04:07.135900 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5235 11:04:07.139160 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5236 11:04:07.142280 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5237 11:04:07.145563 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5238 11:04:07.149012 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5239 11:04:07.155987 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5240 11:04:07.156389 ==
5241 11:04:07.159021 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 11:04:07.162221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 11:04:07.162624 ==
5244 11:04:07.163023 DQS Delay:
5245 11:04:07.165747 DQS0 = 0, DQS1 = 0
5246 11:04:07.166144 DQM Delay:
5247 11:04:07.168898 DQM0 = 97, DQM1 = 86
5248 11:04:07.169382 DQ Delay:
5249 11:04:07.172209 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5250 11:04:07.175561 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5251 11:04:07.178830 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5252 11:04:07.182148 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5253 11:04:07.182548
5254 11:04:07.182937
5255 11:04:07.183306 ==
5256 11:04:07.185088 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 11:04:07.188786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 11:04:07.192075 ==
5259 11:04:07.192472
5260 11:04:07.192866
5261 11:04:07.193244 TX Vref Scan disable
5262 11:04:07.195261 == TX Byte 0 ==
5263 11:04:07.198311 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5264 11:04:07.201878 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5265 11:04:07.204885 == TX Byte 1 ==
5266 11:04:07.208086 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5267 11:04:07.211462 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5268 11:04:07.215083 ==
5269 11:04:07.218518 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 11:04:07.221323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 11:04:07.221726 ==
5272 11:04:07.222148
5273 11:04:07.222515
5274 11:04:07.225129 TX Vref Scan disable
5275 11:04:07.225526 == TX Byte 0 ==
5276 11:04:07.231562 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5277 11:04:07.234568 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5278 11:04:07.235128 == TX Byte 1 ==
5279 11:04:07.241471 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5280 11:04:07.244918 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5281 11:04:07.245304
5282 11:04:07.245603 [DATLAT]
5283 11:04:07.248083 Freq=933, CH0 RK0
5284 11:04:07.248587
5285 11:04:07.249024 DATLAT Default: 0xd
5286 11:04:07.251339 0, 0xFFFF, sum = 0
5287 11:04:07.251841 1, 0xFFFF, sum = 0
5288 11:04:07.254718 2, 0xFFFF, sum = 0
5289 11:04:07.257665 3, 0xFFFF, sum = 0
5290 11:04:07.258098 4, 0xFFFF, sum = 0
5291 11:04:07.260832 5, 0xFFFF, sum = 0
5292 11:04:07.261237 6, 0xFFFF, sum = 0
5293 11:04:07.264593 7, 0xFFFF, sum = 0
5294 11:04:07.265002 8, 0xFFFF, sum = 0
5295 11:04:07.267524 9, 0xFFFF, sum = 0
5296 11:04:07.267930 10, 0x0, sum = 1
5297 11:04:07.271067 11, 0x0, sum = 2
5298 11:04:07.271591 12, 0x0, sum = 3
5299 11:04:07.274616 13, 0x0, sum = 4
5300 11:04:07.275020 best_step = 11
5301 11:04:07.275533
5302 11:04:07.275910 ==
5303 11:04:07.277827 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 11:04:07.280815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 11:04:07.281294 ==
5306 11:04:07.284231 RX Vref Scan: 1
5307 11:04:07.284630
5308 11:04:07.287523 RX Vref 0 -> 0, step: 1
5309 11:04:07.287924
5310 11:04:07.288319 RX Delay -61 -> 252, step: 4
5311 11:04:07.288691
5312 11:04:07.290601 Set Vref, RX VrefLevel [Byte0]: 67
5313 11:04:07.294040 [Byte1]: 51
5314 11:04:07.298954
5315 11:04:07.299353 Final RX Vref Byte 0 = 67 to rank0
5316 11:04:07.301972 Final RX Vref Byte 1 = 51 to rank0
5317 11:04:07.305252 Final RX Vref Byte 0 = 67 to rank1
5318 11:04:07.308728 Final RX Vref Byte 1 = 51 to rank1==
5319 11:04:07.312214 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 11:04:07.318896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 11:04:07.319352 ==
5322 11:04:07.319796 DQS Delay:
5323 11:04:07.322235 DQS0 = 0, DQS1 = 0
5324 11:04:07.322632 DQM Delay:
5325 11:04:07.323028 DQM0 = 97, DQM1 = 84
5326 11:04:07.325053 DQ Delay:
5327 11:04:07.328733 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5328 11:04:07.331863 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =108
5329 11:04:07.335081 DQ8 =78, DQ9 =74, DQ10 =84, DQ11 =78
5330 11:04:07.338699 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =92
5331 11:04:07.339184
5332 11:04:07.339541
5333 11:04:07.345254 [DQSOSCAuto] RK0, (LSB)MR18= 0x3218, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 406 ps
5334 11:04:07.348550 CH0 RK0: MR19=505, MR18=3218
5335 11:04:07.354798 CH0_RK0: MR19=0x505, MR18=0x3218, DQSOSC=406, MR23=63, INC=65, DEC=43
5336 11:04:07.355194
5337 11:04:07.357978 ----->DramcWriteLeveling(PI) begin...
5338 11:04:07.358397 ==
5339 11:04:07.361586 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 11:04:07.364649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 11:04:07.365041 ==
5342 11:04:07.367919 Write leveling (Byte 0): 33 => 33
5343 11:04:07.371272 Write leveling (Byte 1): 27 => 27
5344 11:04:07.374815 DramcWriteLeveling(PI) end<-----
5345 11:04:07.375205
5346 11:04:07.375553 ==
5347 11:04:07.378126 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 11:04:07.384371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 11:04:07.384712 ==
5350 11:04:07.384926 [Gating] SW mode calibration
5351 11:04:07.394165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5352 11:04:07.397835 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5353 11:04:07.401069 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5354 11:04:07.407934 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 11:04:07.410668 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 11:04:07.414284 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 11:04:07.420551 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 11:04:07.423482 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 11:04:07.427190 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 11:04:07.433873 0 14 28 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (0 0)
5361 11:04:07.436856 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (0 1) (0 0)
5362 11:04:07.440291 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 11:04:07.447118 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 11:04:07.449912 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 11:04:07.453341 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 11:04:07.459734 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 11:04:07.463349 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 11:04:07.466539 0 15 28 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
5369 11:04:07.473347 1 0 0 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
5370 11:04:07.476731 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 11:04:07.479491 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:04:07.486228 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 11:04:07.490442 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 11:04:07.492805 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 11:04:07.499699 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5376 11:04:07.503076 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5377 11:04:07.506195 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5378 11:04:07.513044 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:04:07.516224 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:04:07.519731 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:04:07.526371 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:04:07.529210 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:04:07.532582 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:04:07.539362 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:04:07.542429 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:04:07.545961 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:04:07.552150 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:04:07.555810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:04:07.559151 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:04:07.565761 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:04:07.568689 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:04:07.571888 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5393 11:04:07.578792 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5394 11:04:07.582076 Total UI for P1: 0, mck2ui 16
5395 11:04:07.585365 best dqsien dly found for B0: ( 1, 2, 28)
5396 11:04:07.588528 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 11:04:07.591411 Total UI for P1: 0, mck2ui 16
5398 11:04:07.595021 best dqsien dly found for B1: ( 1, 3, 0)
5399 11:04:07.598300 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5400 11:04:07.601711 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5401 11:04:07.601787
5402 11:04:07.605331 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5403 11:04:07.608071 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5404 11:04:07.611462 [Gating] SW calibration Done
5405 11:04:07.611533 ==
5406 11:04:07.614867 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 11:04:07.621274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 11:04:07.621348 ==
5409 11:04:07.621406 RX Vref Scan: 0
5410 11:04:07.621459
5411 11:04:07.624837 RX Vref 0 -> 0, step: 1
5412 11:04:07.624929
5413 11:04:07.628193 RX Delay -80 -> 252, step: 8
5414 11:04:07.631066 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5415 11:04:07.634724 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5416 11:04:07.637880 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5417 11:04:07.641042 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5418 11:04:07.647559 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5419 11:04:07.650871 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5420 11:04:07.654285 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5421 11:04:07.657979 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5422 11:04:07.661146 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5423 11:04:07.664394 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5424 11:04:07.670969 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5425 11:04:07.674022 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5426 11:04:07.677239 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5427 11:04:07.680566 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5428 11:04:07.687568 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5429 11:04:07.690844 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5430 11:04:07.690954 ==
5431 11:04:07.693750 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 11:04:07.697186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 11:04:07.697314 ==
5434 11:04:07.697379 DQS Delay:
5435 11:04:07.700784 DQS0 = 0, DQS1 = 0
5436 11:04:07.700872 DQM Delay:
5437 11:04:07.703545 DQM0 = 97, DQM1 = 88
5438 11:04:07.703632 DQ Delay:
5439 11:04:07.706858 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5440 11:04:07.710311 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5441 11:04:07.713614 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5442 11:04:07.717208 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5443 11:04:07.717321
5444 11:04:07.717410
5445 11:04:07.717492 ==
5446 11:04:07.720042 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 11:04:07.726892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 11:04:07.727037 ==
5449 11:04:07.727147
5450 11:04:07.727248
5451 11:04:07.727343 TX Vref Scan disable
5452 11:04:07.730621 == TX Byte 0 ==
5453 11:04:07.733872 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5454 11:04:07.740125 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5455 11:04:07.740202 == TX Byte 1 ==
5456 11:04:07.743274 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5457 11:04:07.750202 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5458 11:04:07.750281 ==
5459 11:04:07.753347 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 11:04:07.756273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 11:04:07.756351 ==
5462 11:04:07.756410
5463 11:04:07.756465
5464 11:04:07.759940 TX Vref Scan disable
5465 11:04:07.763031 == TX Byte 0 ==
5466 11:04:07.766474 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5467 11:04:07.769741 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5468 11:04:07.772672 == TX Byte 1 ==
5469 11:04:07.776201 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5470 11:04:07.779804 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5471 11:04:07.779899
5472 11:04:07.779973 [DATLAT]
5473 11:04:07.782736 Freq=933, CH0 RK1
5474 11:04:07.782860
5475 11:04:07.786283 DATLAT Default: 0xb
5476 11:04:07.786430 0, 0xFFFF, sum = 0
5477 11:04:07.789213 1, 0xFFFF, sum = 0
5478 11:04:07.789353 2, 0xFFFF, sum = 0
5479 11:04:07.792706 3, 0xFFFF, sum = 0
5480 11:04:07.792865 4, 0xFFFF, sum = 0
5481 11:04:07.796451 5, 0xFFFF, sum = 0
5482 11:04:07.796600 6, 0xFFFF, sum = 0
5483 11:04:07.799640 7, 0xFFFF, sum = 0
5484 11:04:07.799846 8, 0xFFFF, sum = 0
5485 11:04:07.802808 9, 0xFFFF, sum = 0
5486 11:04:07.802987 10, 0x0, sum = 1
5487 11:04:07.805742 11, 0x0, sum = 2
5488 11:04:07.805974 12, 0x0, sum = 3
5489 11:04:07.809600 13, 0x0, sum = 4
5490 11:04:07.809840 best_step = 11
5491 11:04:07.810044
5492 11:04:07.810240 ==
5493 11:04:07.812913 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 11:04:07.816200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 11:04:07.819148 ==
5496 11:04:07.819332 RX Vref Scan: 0
5497 11:04:07.819549
5498 11:04:07.822393 RX Vref 0 -> 0, step: 1
5499 11:04:07.822643
5500 11:04:07.825984 RX Delay -61 -> 252, step: 4
5501 11:04:07.829164 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5502 11:04:07.832632 iDelay=199, Bit 1, Center 96 (-1 ~ 194) 196
5503 11:04:07.839158 iDelay=199, Bit 2, Center 90 (-5 ~ 186) 192
5504 11:04:07.842594 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5505 11:04:07.845721 iDelay=199, Bit 4, Center 96 (-1 ~ 194) 196
5506 11:04:07.849194 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5507 11:04:07.852342 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5508 11:04:07.855897 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5509 11:04:07.862504 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5510 11:04:07.866034 iDelay=199, Bit 9, Center 74 (-17 ~ 166) 184
5511 11:04:07.868831 iDelay=199, Bit 10, Center 86 (-9 ~ 182) 192
5512 11:04:07.872245 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5513 11:04:07.875662 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5514 11:04:07.882105 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5515 11:04:07.885464 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5516 11:04:07.888710 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5517 11:04:07.889071 ==
5518 11:04:07.892248 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 11:04:07.895325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 11:04:07.898456 ==
5521 11:04:07.898832 DQS Delay:
5522 11:04:07.899104 DQS0 = 0, DQS1 = 0
5523 11:04:07.901461 DQM Delay:
5524 11:04:07.901747 DQM0 = 95, DQM1 = 86
5525 11:04:07.905254 DQ Delay:
5526 11:04:07.908459 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =90
5527 11:04:07.911868 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5528 11:04:07.912220 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5529 11:04:07.918313 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5530 11:04:07.918664
5531 11:04:07.918933
5532 11:04:07.924680 [DQSOSCAuto] RK1, (LSB)MR18= 0x2dfd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 407 ps
5533 11:04:07.927752 CH0 RK1: MR19=504, MR18=2DFD
5534 11:04:07.935009 CH0_RK1: MR19=0x504, MR18=0x2DFD, DQSOSC=407, MR23=63, INC=65, DEC=43
5535 11:04:07.938192 [RxdqsGatingPostProcess] freq 933
5536 11:04:07.941491 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5537 11:04:07.944448 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 11:04:07.947893 best DQS1 dly(2T, 0.5T) = (0, 11)
5539 11:04:07.951297 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 11:04:07.954793 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5541 11:04:07.957804 best DQS0 dly(2T, 0.5T) = (0, 10)
5542 11:04:07.960931 best DQS1 dly(2T, 0.5T) = (0, 11)
5543 11:04:07.964364 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5544 11:04:07.967657 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5545 11:04:07.970777 Pre-setting of DQS Precalculation
5546 11:04:07.974393 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5547 11:04:07.977609 ==
5548 11:04:07.977962 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 11:04:07.984151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 11:04:07.984559 ==
5551 11:04:07.987477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 11:04:07.994260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5553 11:04:07.997716 [CA 0] Center 37 (7~67) winsize 61
5554 11:04:08.000891 [CA 1] Center 37 (6~68) winsize 63
5555 11:04:08.004665 [CA 2] Center 34 (4~65) winsize 62
5556 11:04:08.007709 [CA 3] Center 34 (4~64) winsize 61
5557 11:04:08.010906 [CA 4] Center 34 (4~64) winsize 61
5558 11:04:08.014634 [CA 5] Center 33 (3~64) winsize 62
5559 11:04:08.015174
5560 11:04:08.017877 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5561 11:04:08.018305
5562 11:04:08.020901 [CATrainingPosCal] consider 1 rank data
5563 11:04:08.024032 u2DelayCellTimex100 = 270/100 ps
5564 11:04:08.027724 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5565 11:04:08.034117 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5566 11:04:08.037416 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 11:04:08.040559 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 11:04:08.044024 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 11:04:08.047367 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 11:04:08.047848
5571 11:04:08.050532 CA PerBit enable=1, Macro0, CA PI delay=33
5572 11:04:08.050967
5573 11:04:08.053906 [CBTSetCACLKResult] CA Dly = 33
5574 11:04:08.056820 CS Dly: 6 (0~37)
5575 11:04:08.057250 ==
5576 11:04:08.060319 Dram Type= 6, Freq= 0, CH_1, rank 1
5577 11:04:08.063495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 11:04:08.064051 ==
5579 11:04:08.070363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 11:04:08.073761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5581 11:04:08.077682 [CA 0] Center 36 (6~67) winsize 62
5582 11:04:08.081071 [CA 1] Center 37 (7~67) winsize 61
5583 11:04:08.084255 [CA 2] Center 34 (4~65) winsize 62
5584 11:04:08.087342 [CA 3] Center 34 (3~65) winsize 63
5585 11:04:08.090917 [CA 4] Center 34 (3~65) winsize 63
5586 11:04:08.094091 [CA 5] Center 33 (3~64) winsize 62
5587 11:04:08.094487
5588 11:04:08.097261 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5589 11:04:08.097653
5590 11:04:08.100941 [CATrainingPosCal] consider 2 rank data
5591 11:04:08.103752 u2DelayCellTimex100 = 270/100 ps
5592 11:04:08.110596 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5593 11:04:08.113725 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5594 11:04:08.117215 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5595 11:04:08.120472 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5596 11:04:08.123525 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5597 11:04:08.127006 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 11:04:08.127399
5599 11:04:08.130232 CA PerBit enable=1, Macro0, CA PI delay=33
5600 11:04:08.130670
5601 11:04:08.133702 [CBTSetCACLKResult] CA Dly = 33
5602 11:04:08.136574 CS Dly: 7 (0~39)
5603 11:04:08.136964
5604 11:04:08.139923 ----->DramcWriteLeveling(PI) begin...
5605 11:04:08.140319 ==
5606 11:04:08.143608 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 11:04:08.146729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 11:04:08.147222 ==
5609 11:04:08.150131 Write leveling (Byte 0): 22 => 22
5610 11:04:08.153431 Write leveling (Byte 1): 26 => 26
5611 11:04:08.157203 DramcWriteLeveling(PI) end<-----
5612 11:04:08.157609
5613 11:04:08.157910 ==
5614 11:04:08.160228 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 11:04:08.163058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 11:04:08.163482 ==
5617 11:04:08.166780 [Gating] SW mode calibration
5618 11:04:08.172928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5619 11:04:08.179540 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5620 11:04:08.183088 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 11:04:08.189553 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 11:04:08.192941 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 11:04:08.196200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 11:04:08.202934 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 11:04:08.205788 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 11:04:08.209270 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5627 11:04:08.215587 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5628 11:04:08.219073 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 11:04:08.222093 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 11:04:08.228855 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 11:04:08.232093 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 11:04:08.235175 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 11:04:08.241873 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 11:04:08.245135 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5635 11:04:08.248454 0 15 28 | B1->B0 | 3838 3e3e | 0 1 | (0 0) (0 0)
5636 11:04:08.254878 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 11:04:08.258190 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 11:04:08.261809 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 11:04:08.268340 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 11:04:08.271472 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 11:04:08.274707 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 11:04:08.281420 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5643 11:04:08.285544 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5644 11:04:08.288273 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:04:08.294933 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:04:08.298214 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:04:08.301302 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:04:08.308002 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:04:08.311124 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:04:08.314284 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:04:08.321585 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:04:08.324358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:04:08.327996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:04:08.334482 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:04:08.337699 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:04:08.340611 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:04:08.347237 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5658 11:04:08.351065 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5659 11:04:08.353931 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 11:04:08.357227 Total UI for P1: 0, mck2ui 16
5661 11:04:08.360614 best dqsien dly found for B0: ( 1, 2, 22)
5662 11:04:08.363857 Total UI for P1: 0, mck2ui 16
5663 11:04:08.367254 best dqsien dly found for B1: ( 1, 2, 22)
5664 11:04:08.370980 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5665 11:04:08.373905 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5666 11:04:08.374385
5667 11:04:08.380846 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5668 11:04:08.383796 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5669 11:04:08.384306 [Gating] SW calibration Done
5670 11:04:08.386829 ==
5671 11:04:08.387258 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 11:04:08.393739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 11:04:08.394246 ==
5674 11:04:08.394582 RX Vref Scan: 0
5675 11:04:08.394893
5676 11:04:08.397136 RX Vref 0 -> 0, step: 1
5677 11:04:08.397654
5678 11:04:08.400299 RX Delay -80 -> 252, step: 8
5679 11:04:08.403807 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5680 11:04:08.406736 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5681 11:04:08.410264 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5682 11:04:08.416707 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5683 11:04:08.420297 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5684 11:04:08.423628 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5685 11:04:08.426737 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5686 11:04:08.430025 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5687 11:04:08.433454 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5688 11:04:08.440384 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5689 11:04:08.443098 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5690 11:04:08.446753 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5691 11:04:08.449741 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5692 11:04:08.453469 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5693 11:04:08.460101 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5694 11:04:08.463366 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5695 11:04:08.463905 ==
5696 11:04:08.466531 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:04:08.469695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:04:08.470084 ==
5699 11:04:08.473536 DQS Delay:
5700 11:04:08.473922 DQS0 = 0, DQS1 = 0
5701 11:04:08.474221 DQM Delay:
5702 11:04:08.476653 DQM0 = 102, DQM1 = 90
5703 11:04:08.477076 DQ Delay:
5704 11:04:08.479400 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5705 11:04:08.482867 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5706 11:04:08.486323 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5707 11:04:08.489892 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =103
5708 11:04:08.490421
5709 11:04:08.490760
5710 11:04:08.492626 ==
5711 11:04:08.493092 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 11:04:08.499250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 11:04:08.499811 ==
5714 11:04:08.500256
5715 11:04:08.500669
5716 11:04:08.502312 TX Vref Scan disable
5717 11:04:08.502701 == TX Byte 0 ==
5718 11:04:08.505773 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5719 11:04:08.512222 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5720 11:04:08.512613 == TX Byte 1 ==
5721 11:04:08.515591 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5722 11:04:08.522834 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5723 11:04:08.523299 ==
5724 11:04:08.525924 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 11:04:08.528891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 11:04:08.529299 ==
5727 11:04:08.529604
5728 11:04:08.529880
5729 11:04:08.532349 TX Vref Scan disable
5730 11:04:08.535767 == TX Byte 0 ==
5731 11:04:08.538757 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5732 11:04:08.541896 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5733 11:04:08.545666 == TX Byte 1 ==
5734 11:04:08.548964 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5735 11:04:08.551806 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5736 11:04:08.552195
5737 11:04:08.555632 [DATLAT]
5738 11:04:08.556161 Freq=933, CH1 RK0
5739 11:04:08.556616
5740 11:04:08.558361 DATLAT Default: 0xd
5741 11:04:08.558752 0, 0xFFFF, sum = 0
5742 11:04:08.561867 1, 0xFFFF, sum = 0
5743 11:04:08.562265 2, 0xFFFF, sum = 0
5744 11:04:08.565160 3, 0xFFFF, sum = 0
5745 11:04:08.565556 4, 0xFFFF, sum = 0
5746 11:04:08.568629 5, 0xFFFF, sum = 0
5747 11:04:08.569022 6, 0xFFFF, sum = 0
5748 11:04:08.571733 7, 0xFFFF, sum = 0
5749 11:04:08.572138 8, 0xFFFF, sum = 0
5750 11:04:08.574966 9, 0xFFFF, sum = 0
5751 11:04:08.575539 10, 0x0, sum = 1
5752 11:04:08.578145 11, 0x0, sum = 2
5753 11:04:08.578581 12, 0x0, sum = 3
5754 11:04:08.581681 13, 0x0, sum = 4
5755 11:04:08.582285 best_step = 11
5756 11:04:08.582723
5757 11:04:08.583138 ==
5758 11:04:08.585031 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 11:04:08.591569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 11:04:08.591967 ==
5761 11:04:08.592271 RX Vref Scan: 1
5762 11:04:08.592548
5763 11:04:08.594854 RX Vref 0 -> 0, step: 1
5764 11:04:08.595251
5765 11:04:08.598219 RX Delay -69 -> 252, step: 4
5766 11:04:08.598602
5767 11:04:08.601966 Set Vref, RX VrefLevel [Byte0]: 50
5768 11:04:08.604774 [Byte1]: 61
5769 11:04:08.605239
5770 11:04:08.608111 Final RX Vref Byte 0 = 50 to rank0
5771 11:04:08.611045 Final RX Vref Byte 1 = 61 to rank0
5772 11:04:08.614624 Final RX Vref Byte 0 = 50 to rank1
5773 11:04:08.618000 Final RX Vref Byte 1 = 61 to rank1==
5774 11:04:08.621020 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 11:04:08.624439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 11:04:08.624826 ==
5777 11:04:08.627580 DQS Delay:
5778 11:04:08.627963 DQS0 = 0, DQS1 = 0
5779 11:04:08.630919 DQM Delay:
5780 11:04:08.631315 DQM0 = 100, DQM1 = 94
5781 11:04:08.634068 DQ Delay:
5782 11:04:08.634450 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5783 11:04:08.637736 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =96
5784 11:04:08.641028 DQ8 =82, DQ9 =84, DQ10 =98, DQ11 =86
5785 11:04:08.647635 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5786 11:04:08.648194
5787 11:04:08.648744
5788 11:04:08.654284 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5789 11:04:08.657667 CH1 RK0: MR19=505, MR18=1B0B
5790 11:04:08.664059 CH1_RK0: MR19=0x505, MR18=0x1B0B, DQSOSC=413, MR23=63, INC=63, DEC=42
5791 11:04:08.664446
5792 11:04:08.667530 ----->DramcWriteLeveling(PI) begin...
5793 11:04:08.668077 ==
5794 11:04:08.670837 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 11:04:08.673895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 11:04:08.674284 ==
5797 11:04:08.677557 Write leveling (Byte 0): 23 => 23
5798 11:04:08.681035 Write leveling (Byte 1): 31 => 31
5799 11:04:08.684808 DramcWriteLeveling(PI) end<-----
5800 11:04:08.685190
5801 11:04:08.685485 ==
5802 11:04:08.687288 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 11:04:08.690643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 11:04:08.691032 ==
5805 11:04:08.694154 [Gating] SW mode calibration
5806 11:04:08.700489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5807 11:04:08.706806 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5808 11:04:08.710780 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
5809 11:04:08.716993 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 11:04:08.720237 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 11:04:08.723548 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 11:04:08.729945 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 11:04:08.733756 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 11:04:08.736832 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
5815 11:04:08.743307 0 14 28 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
5816 11:04:08.746440 0 15 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
5817 11:04:08.749697 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 11:04:08.756543 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 11:04:08.759789 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 11:04:08.762910 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 11:04:08.769486 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 11:04:08.772998 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5823 11:04:08.776455 0 15 28 | B1->B0 | 3d3d 2e2e | 0 0 | (0 0) (1 1)
5824 11:04:08.782837 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 11:04:08.786322 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 11:04:08.789537 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 11:04:08.797636 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 11:04:08.799869 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 11:04:08.802766 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 11:04:08.809447 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5831 11:04:08.813320 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5832 11:04:08.816134 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 11:04:08.822422 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:04:08.825963 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:04:08.829490 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:04:08.836009 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:04:08.839185 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:04:08.842592 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:04:08.845843 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:04:08.852313 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:04:08.855819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:04:08.859137 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:04:08.865886 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:04:08.869281 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:04:08.872127 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:04:08.878773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:04:08.882437 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5848 11:04:08.886141 Total UI for P1: 0, mck2ui 16
5849 11:04:08.888931 best dqsien dly found for B1: ( 1, 2, 26)
5850 11:04:08.892135 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5851 11:04:08.898556 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 11:04:08.901869 Total UI for P1: 0, mck2ui 16
5853 11:04:08.905402 best dqsien dly found for B0: ( 1, 2, 30)
5854 11:04:08.908775 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5855 11:04:08.911683 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5856 11:04:08.912310
5857 11:04:08.915563 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5858 11:04:08.918437 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5859 11:04:08.921709 [Gating] SW calibration Done
5860 11:04:08.922094 ==
5861 11:04:08.925015 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 11:04:08.928705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 11:04:08.929188 ==
5864 11:04:08.931865 RX Vref Scan: 0
5865 11:04:08.932247
5866 11:04:08.934923 RX Vref 0 -> 0, step: 1
5867 11:04:08.935400
5868 11:04:08.935748 RX Delay -80 -> 252, step: 8
5869 11:04:08.942443 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5870 11:04:08.945014 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5871 11:04:08.948453 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5872 11:04:08.951880 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5873 11:04:08.955123 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5874 11:04:08.958674 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5875 11:04:08.964978 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5876 11:04:08.968239 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5877 11:04:08.971792 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5878 11:04:08.974802 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5879 11:04:08.978308 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5880 11:04:08.984749 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5881 11:04:08.988165 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5882 11:04:08.991494 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5883 11:04:08.994700 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5884 11:04:08.997935 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5885 11:04:08.998377 ==
5886 11:04:09.001133 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 11:04:09.008055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 11:04:09.008478 ==
5889 11:04:09.008789 DQS Delay:
5890 11:04:09.011246 DQS0 = 0, DQS1 = 0
5891 11:04:09.011657 DQM Delay:
5892 11:04:09.014084 DQM0 = 99, DQM1 = 92
5893 11:04:09.014474 DQ Delay:
5894 11:04:09.017977 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5895 11:04:09.021313 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5896 11:04:09.024088 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5897 11:04:09.027399 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5898 11:04:09.027888
5899 11:04:09.028221
5900 11:04:09.028525 ==
5901 11:04:09.030637 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 11:04:09.034143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 11:04:09.034619 ==
5904 11:04:09.034926
5905 11:04:09.037241
5906 11:04:09.037671 TX Vref Scan disable
5907 11:04:09.040566 == TX Byte 0 ==
5908 11:04:09.044076 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5909 11:04:09.047665 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5910 11:04:09.051139 == TX Byte 1 ==
5911 11:04:09.053602 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5912 11:04:09.057273 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5913 11:04:09.057784 ==
5914 11:04:09.060270 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 11:04:09.067117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 11:04:09.067648 ==
5917 11:04:09.067985
5918 11:04:09.068313
5919 11:04:09.070362 TX Vref Scan disable
5920 11:04:09.070790 == TX Byte 0 ==
5921 11:04:09.077008 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5922 11:04:09.079843 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5923 11:04:09.080277 == TX Byte 1 ==
5924 11:04:09.086434 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5925 11:04:09.089793 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5926 11:04:09.090217
5927 11:04:09.090519 [DATLAT]
5928 11:04:09.093105 Freq=933, CH1 RK1
5929 11:04:09.093494
5930 11:04:09.093790 DATLAT Default: 0xb
5931 11:04:09.096756 0, 0xFFFF, sum = 0
5932 11:04:09.097230 1, 0xFFFF, sum = 0
5933 11:04:09.099999 2, 0xFFFF, sum = 0
5934 11:04:09.100394 3, 0xFFFF, sum = 0
5935 11:04:09.103576 4, 0xFFFF, sum = 0
5936 11:04:09.103970 5, 0xFFFF, sum = 0
5937 11:04:09.106798 6, 0xFFFF, sum = 0
5938 11:04:09.109653 7, 0xFFFF, sum = 0
5939 11:04:09.110044 8, 0xFFFF, sum = 0
5940 11:04:09.113073 9, 0xFFFF, sum = 0
5941 11:04:09.113464 10, 0x0, sum = 1
5942 11:04:09.116541 11, 0x0, sum = 2
5943 11:04:09.117012 12, 0x0, sum = 3
5944 11:04:09.117315 13, 0x0, sum = 4
5945 11:04:09.119559 best_step = 11
5946 11:04:09.119946
5947 11:04:09.120242 ==
5948 11:04:09.123499 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 11:04:09.126348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 11:04:09.126737 ==
5951 11:04:09.129540 RX Vref Scan: 0
5952 11:04:09.129923
5953 11:04:09.132585 RX Vref 0 -> 0, step: 1
5954 11:04:09.132966
5955 11:04:09.133263 RX Delay -61 -> 252, step: 4
5956 11:04:09.140485 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5957 11:04:09.143951 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5958 11:04:09.147354 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5959 11:04:09.150637 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5960 11:04:09.153748 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5961 11:04:09.160069 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5962 11:04:09.163225 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5963 11:04:09.166789 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5964 11:04:09.170259 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5965 11:04:09.173386 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5966 11:04:09.176483 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5967 11:04:09.183056 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5968 11:04:09.186973 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5969 11:04:09.189829 iDelay=207, Bit 13, Center 102 (15 ~ 190) 176
5970 11:04:09.192809 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
5971 11:04:09.199505 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
5972 11:04:09.199900 ==
5973 11:04:09.203028 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 11:04:09.206058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 11:04:09.206448 ==
5976 11:04:09.206748 DQS Delay:
5977 11:04:09.209533 DQS0 = 0, DQS1 = 0
5978 11:04:09.209922 DQM Delay:
5979 11:04:09.213007 DQM0 = 101, DQM1 = 94
5980 11:04:09.213392 DQ Delay:
5981 11:04:09.215898 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5982 11:04:09.219478 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
5983 11:04:09.222777 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5984 11:04:09.226174 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =104
5985 11:04:09.226685
5986 11:04:09.226990
5987 11:04:09.235728 [DQSOSCAuto] RK1, (LSB)MR18= 0xb04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
5988 11:04:09.239175 CH1 RK1: MR19=505, MR18=B04
5989 11:04:09.242125 CH1_RK1: MR19=0x505, MR18=0xB04, DQSOSC=418, MR23=63, INC=62, DEC=41
5990 11:04:09.245232 [RxdqsGatingPostProcess] freq 933
5991 11:04:09.252138 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5992 11:04:09.255550 best DQS0 dly(2T, 0.5T) = (0, 10)
5993 11:04:09.258301 best DQS1 dly(2T, 0.5T) = (0, 10)
5994 11:04:09.261854 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5995 11:04:09.265109 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5996 11:04:09.268572 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 11:04:09.271826 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 11:04:09.275344 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 11:04:09.278243 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 11:04:09.281895 Pre-setting of DQS Precalculation
6001 11:04:09.284749 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6002 11:04:09.291546 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6003 11:04:09.298347 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6004 11:04:09.298741
6005 11:04:09.299045
6006 11:04:09.301705 [Calibration Summary] 1866 Mbps
6007 11:04:09.304898 CH 0, Rank 0
6008 11:04:09.305284 SW Impedance : PASS
6009 11:04:09.308490 DUTY Scan : NO K
6010 11:04:09.311408 ZQ Calibration : PASS
6011 11:04:09.311853 Jitter Meter : NO K
6012 11:04:09.314598 CBT Training : PASS
6013 11:04:09.318283 Write leveling : PASS
6014 11:04:09.318786 RX DQS gating : PASS
6015 11:04:09.321781 RX DQ/DQS(RDDQC) : PASS
6016 11:04:09.324619 TX DQ/DQS : PASS
6017 11:04:09.325009 RX DATLAT : PASS
6018 11:04:09.328170 RX DQ/DQS(Engine): PASS
6019 11:04:09.331345 TX OE : NO K
6020 11:04:09.331766 All Pass.
6021 11:04:09.332088
6022 11:04:09.332369 CH 0, Rank 1
6023 11:04:09.334502 SW Impedance : PASS
6024 11:04:09.338227 DUTY Scan : NO K
6025 11:04:09.338614 ZQ Calibration : PASS
6026 11:04:09.341670 Jitter Meter : NO K
6027 11:04:09.342059 CBT Training : PASS
6028 11:04:09.344511 Write leveling : PASS
6029 11:04:09.347951 RX DQS gating : PASS
6030 11:04:09.348344 RX DQ/DQS(RDDQC) : PASS
6031 11:04:09.351230 TX DQ/DQS : PASS
6032 11:04:09.354879 RX DATLAT : PASS
6033 11:04:09.355347 RX DQ/DQS(Engine): PASS
6034 11:04:09.357849 TX OE : NO K
6035 11:04:09.358253 All Pass.
6036 11:04:09.358556
6037 11:04:09.360808 CH 1, Rank 0
6038 11:04:09.361200 SW Impedance : PASS
6039 11:04:09.364879 DUTY Scan : NO K
6040 11:04:09.367477 ZQ Calibration : PASS
6041 11:04:09.367899 Jitter Meter : NO K
6042 11:04:09.370832 CBT Training : PASS
6043 11:04:09.374819 Write leveling : PASS
6044 11:04:09.375367 RX DQS gating : PASS
6045 11:04:09.377747 RX DQ/DQS(RDDQC) : PASS
6046 11:04:09.381038 TX DQ/DQS : PASS
6047 11:04:09.381475 RX DATLAT : PASS
6048 11:04:09.384737 RX DQ/DQS(Engine): PASS
6049 11:04:09.387840 TX OE : NO K
6050 11:04:09.388354 All Pass.
6051 11:04:09.388690
6052 11:04:09.389055 CH 1, Rank 1
6053 11:04:09.390955 SW Impedance : PASS
6054 11:04:09.393912 DUTY Scan : NO K
6055 11:04:09.394346 ZQ Calibration : PASS
6056 11:04:09.397342 Jitter Meter : NO K
6057 11:04:09.400841 CBT Training : PASS
6058 11:04:09.401348 Write leveling : PASS
6059 11:04:09.403957 RX DQS gating : PASS
6060 11:04:09.407852 RX DQ/DQS(RDDQC) : PASS
6061 11:04:09.408379 TX DQ/DQS : PASS
6062 11:04:09.410772 RX DATLAT : PASS
6063 11:04:09.411397 RX DQ/DQS(Engine): PASS
6064 11:04:09.413634 TX OE : NO K
6065 11:04:09.414131 All Pass.
6066 11:04:09.414476
6067 11:04:09.417476 DramC Write-DBI off
6068 11:04:09.420804 PER_BANK_REFRESH: Hybrid Mode
6069 11:04:09.421310 TX_TRACKING: ON
6070 11:04:09.430430 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6071 11:04:09.433993 [FAST_K] Save calibration result to emmc
6072 11:04:09.437006 dramc_set_vcore_voltage set vcore to 650000
6073 11:04:09.440257 Read voltage for 400, 6
6074 11:04:09.440685 Vio18 = 0
6075 11:04:09.443579 Vcore = 650000
6076 11:04:09.443965 Vdram = 0
6077 11:04:09.444266 Vddq = 0
6078 11:04:09.444580 Vmddr = 0
6079 11:04:09.450714 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6080 11:04:09.456846 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6081 11:04:09.457312 MEM_TYPE=3, freq_sel=20
6082 11:04:09.460428 sv_algorithm_assistance_LP4_800
6083 11:04:09.463553 ============ PULL DRAM RESETB DOWN ============
6084 11:04:09.470404 ========== PULL DRAM RESETB DOWN end =========
6085 11:04:09.473904 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6086 11:04:09.476401 ===================================
6087 11:04:09.479630 LPDDR4 DRAM CONFIGURATION
6088 11:04:09.483253 ===================================
6089 11:04:09.483921 EX_ROW_EN[0] = 0x0
6090 11:04:09.486148 EX_ROW_EN[1] = 0x0
6091 11:04:09.489835 LP4Y_EN = 0x0
6092 11:04:09.490298 WORK_FSP = 0x0
6093 11:04:09.493090 WL = 0x2
6094 11:04:09.493525 RL = 0x2
6095 11:04:09.496196 BL = 0x2
6096 11:04:09.496588 RPST = 0x0
6097 11:04:09.499614 RD_PRE = 0x0
6098 11:04:09.500006 WR_PRE = 0x1
6099 11:04:09.503301 WR_PST = 0x0
6100 11:04:09.503830 DBI_WR = 0x0
6101 11:04:09.506709 DBI_RD = 0x0
6102 11:04:09.507174 OTF = 0x1
6103 11:04:09.509295 ===================================
6104 11:04:09.512669 ===================================
6105 11:04:09.515910 ANA top config
6106 11:04:09.519495 ===================================
6107 11:04:09.519882 DLL_ASYNC_EN = 0
6108 11:04:09.523000 ALL_SLAVE_EN = 1
6109 11:04:09.526608 NEW_RANK_MODE = 1
6110 11:04:09.529106 DLL_IDLE_MODE = 1
6111 11:04:09.533119 LP45_APHY_COMB_EN = 1
6112 11:04:09.533622 TX_ODT_DIS = 1
6113 11:04:09.536156 NEW_8X_MODE = 1
6114 11:04:09.539591 ===================================
6115 11:04:09.542807 ===================================
6116 11:04:09.545741 data_rate = 800
6117 11:04:09.549409 CKR = 1
6118 11:04:09.553176 DQ_P2S_RATIO = 4
6119 11:04:09.555968 ===================================
6120 11:04:09.558779 CA_P2S_RATIO = 4
6121 11:04:09.559273 DQ_CA_OPEN = 0
6122 11:04:09.562327 DQ_SEMI_OPEN = 1
6123 11:04:09.565560 CA_SEMI_OPEN = 1
6124 11:04:09.568774 CA_FULL_RATE = 0
6125 11:04:09.572494 DQ_CKDIV4_EN = 0
6126 11:04:09.575383 CA_CKDIV4_EN = 1
6127 11:04:09.575856 CA_PREDIV_EN = 0
6128 11:04:09.578943 PH8_DLY = 0
6129 11:04:09.581774 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6130 11:04:09.585616 DQ_AAMCK_DIV = 0
6131 11:04:09.588573 CA_AAMCK_DIV = 0
6132 11:04:09.592413 CA_ADMCK_DIV = 4
6133 11:04:09.592920 DQ_TRACK_CA_EN = 0
6134 11:04:09.595622 CA_PICK = 800
6135 11:04:09.598417 CA_MCKIO = 400
6136 11:04:09.602544 MCKIO_SEMI = 400
6137 11:04:09.605354 PLL_FREQ = 3016
6138 11:04:09.608465 DQ_UI_PI_RATIO = 32
6139 11:04:09.611880 CA_UI_PI_RATIO = 32
6140 11:04:09.615310 ===================================
6141 11:04:09.619060 ===================================
6142 11:04:09.619601 memory_type:LPDDR4
6143 11:04:09.621697 GP_NUM : 10
6144 11:04:09.625005 SRAM_EN : 1
6145 11:04:09.625513 MD32_EN : 0
6146 11:04:09.628373 ===================================
6147 11:04:09.631749 [ANA_INIT] >>>>>>>>>>>>>>
6148 11:04:09.634697 <<<<<< [CONFIGURE PHASE]: ANA_TX
6149 11:04:09.638467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6150 11:04:09.641624 ===================================
6151 11:04:09.645109 data_rate = 800,PCW = 0X7400
6152 11:04:09.648185 ===================================
6153 11:04:09.651270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6154 11:04:09.654674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6155 11:04:09.667816 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 11:04:09.671107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6157 11:04:09.674353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6158 11:04:09.677632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6159 11:04:09.680833 [ANA_INIT] flow start
6160 11:04:09.684432 [ANA_INIT] PLL >>>>>>>>
6161 11:04:09.684907 [ANA_INIT] PLL <<<<<<<<
6162 11:04:09.687522 [ANA_INIT] MIDPI >>>>>>>>
6163 11:04:09.691172 [ANA_INIT] MIDPI <<<<<<<<
6164 11:04:09.691615 [ANA_INIT] DLL >>>>>>>>
6165 11:04:09.694254 [ANA_INIT] flow end
6166 11:04:09.697330 ============ LP4 DIFF to SE enter ============
6167 11:04:09.704193 ============ LP4 DIFF to SE exit ============
6168 11:04:09.704593 [ANA_INIT] <<<<<<<<<<<<<
6169 11:04:09.707507 [Flow] Enable top DCM control >>>>>
6170 11:04:09.710595 [Flow] Enable top DCM control <<<<<
6171 11:04:09.713935 Enable DLL master slave shuffle
6172 11:04:09.720422 ==============================================================
6173 11:04:09.720812 Gating Mode config
6174 11:04:09.727160 ==============================================================
6175 11:04:09.730553 Config description:
6176 11:04:09.740430 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6177 11:04:09.747145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6178 11:04:09.749917 SELPH_MODE 0: By rank 1: By Phase
6179 11:04:09.756366 ==============================================================
6180 11:04:09.759890 GAT_TRACK_EN = 0
6181 11:04:09.763110 RX_GATING_MODE = 2
6182 11:04:09.763557 RX_GATING_TRACK_MODE = 2
6183 11:04:09.766498 SELPH_MODE = 1
6184 11:04:09.769799 PICG_EARLY_EN = 1
6185 11:04:09.773215 VALID_LAT_VALUE = 1
6186 11:04:09.779382 ==============================================================
6187 11:04:09.783082 Enter into Gating configuration >>>>
6188 11:04:09.786127 Exit from Gating configuration <<<<
6189 11:04:09.789704 Enter into DVFS_PRE_config >>>>>
6190 11:04:09.799500 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6191 11:04:09.803286 Exit from DVFS_PRE_config <<<<<
6192 11:04:09.806023 Enter into PICG configuration >>>>
6193 11:04:09.809427 Exit from PICG configuration <<<<
6194 11:04:09.812553 [RX_INPUT] configuration >>>>>
6195 11:04:09.815908 [RX_INPUT] configuration <<<<<
6196 11:04:09.819173 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6197 11:04:09.825889 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6198 11:04:09.832447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 11:04:09.839037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 11:04:09.845283 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 11:04:09.848761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 11:04:09.855598 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6203 11:04:09.859223 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6204 11:04:09.862211 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6205 11:04:09.865594 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6206 11:04:09.872108 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6207 11:04:09.875471 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 11:04:09.879083 ===================================
6209 11:04:09.881758 LPDDR4 DRAM CONFIGURATION
6210 11:04:09.885146 ===================================
6211 11:04:09.885572 EX_ROW_EN[0] = 0x0
6212 11:04:09.888278 EX_ROW_EN[1] = 0x0
6213 11:04:09.888666 LP4Y_EN = 0x0
6214 11:04:09.891628 WORK_FSP = 0x0
6215 11:04:09.892020 WL = 0x2
6216 11:04:09.894930 RL = 0x2
6217 11:04:09.898356 BL = 0x2
6218 11:04:09.898748 RPST = 0x0
6219 11:04:09.902007 RD_PRE = 0x0
6220 11:04:09.902397 WR_PRE = 0x1
6221 11:04:09.905236 WR_PST = 0x0
6222 11:04:09.905657 DBI_WR = 0x0
6223 11:04:09.908749 DBI_RD = 0x0
6224 11:04:09.909136 OTF = 0x1
6225 11:04:09.911554 ===================================
6226 11:04:09.914981 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6227 11:04:09.921320 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6228 11:04:09.924863 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 11:04:09.928580 ===================================
6230 11:04:09.931708 LPDDR4 DRAM CONFIGURATION
6231 11:04:09.934618 ===================================
6232 11:04:09.935109 EX_ROW_EN[0] = 0x10
6233 11:04:09.938354 EX_ROW_EN[1] = 0x0
6234 11:04:09.938776 LP4Y_EN = 0x0
6235 11:04:09.941256 WORK_FSP = 0x0
6236 11:04:09.941785 WL = 0x2
6237 11:04:09.944816 RL = 0x2
6238 11:04:09.945346 BL = 0x2
6239 11:04:09.948299 RPST = 0x0
6240 11:04:09.951036 RD_PRE = 0x0
6241 11:04:09.951628 WR_PRE = 0x1
6242 11:04:09.954458 WR_PST = 0x0
6243 11:04:09.954889 DBI_WR = 0x0
6244 11:04:09.958094 DBI_RD = 0x0
6245 11:04:09.958498 OTF = 0x1
6246 11:04:09.960896 ===================================
6247 11:04:09.967659 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6248 11:04:09.971728 nWR fixed to 30
6249 11:04:09.974903 [ModeRegInit_LP4] CH0 RK0
6250 11:04:09.975303 [ModeRegInit_LP4] CH0 RK1
6251 11:04:09.978053 [ModeRegInit_LP4] CH1 RK0
6252 11:04:09.981650 [ModeRegInit_LP4] CH1 RK1
6253 11:04:09.982142 match AC timing 19
6254 11:04:09.988441 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6255 11:04:09.991243 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6256 11:04:09.994539 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6257 11:04:10.001669 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6258 11:04:10.004879 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6259 11:04:10.005254 ==
6260 11:04:10.008400 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 11:04:10.011948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 11:04:10.012373 ==
6263 11:04:10.018213 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 11:04:10.024593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6265 11:04:10.028081 [CA 0] Center 36 (8~64) winsize 57
6266 11:04:10.031134 [CA 1] Center 36 (8~64) winsize 57
6267 11:04:10.034178 [CA 2] Center 36 (8~64) winsize 57
6268 11:04:10.037829 [CA 3] Center 36 (8~64) winsize 57
6269 11:04:10.041069 [CA 4] Center 36 (8~64) winsize 57
6270 11:04:10.044301 [CA 5] Center 36 (8~64) winsize 57
6271 11:04:10.044705
6272 11:04:10.047545 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6273 11:04:10.047933
6274 11:04:10.051133 [CATrainingPosCal] consider 1 rank data
6275 11:04:10.053955 u2DelayCellTimex100 = 270/100 ps
6276 11:04:10.057371 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:04:10.060603 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 11:04:10.064190 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 11:04:10.066984 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:04:10.070359 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 11:04:10.073810 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 11:04:10.074308
6283 11:04:10.079979 CA PerBit enable=1, Macro0, CA PI delay=36
6284 11:04:10.080488
6285 11:04:10.083597 [CBTSetCACLKResult] CA Dly = 36
6286 11:04:10.084045 CS Dly: 1 (0~32)
6287 11:04:10.084351 ==
6288 11:04:10.087075 Dram Type= 6, Freq= 0, CH_0, rank 1
6289 11:04:10.089944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 11:04:10.090334 ==
6291 11:04:10.096697 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6292 11:04:10.103299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6293 11:04:10.106518 [CA 0] Center 36 (8~64) winsize 57
6294 11:04:10.110036 [CA 1] Center 36 (8~64) winsize 57
6295 11:04:10.113337 [CA 2] Center 36 (8~64) winsize 57
6296 11:04:10.116449 [CA 3] Center 36 (8~64) winsize 57
6297 11:04:10.119767 [CA 4] Center 36 (8~64) winsize 57
6298 11:04:10.120205 [CA 5] Center 36 (8~64) winsize 57
6299 11:04:10.123563
6300 11:04:10.126239 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6301 11:04:10.126736
6302 11:04:10.129590 [CATrainingPosCal] consider 2 rank data
6303 11:04:10.133352 u2DelayCellTimex100 = 270/100 ps
6304 11:04:10.136271 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:04:10.139483 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:04:10.142936 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:04:10.146290 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:04:10.149422 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 11:04:10.152782 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 11:04:10.153053
6311 11:04:10.155963 CA PerBit enable=1, Macro0, CA PI delay=36
6312 11:04:10.158805
6313 11:04:10.159089 [CBTSetCACLKResult] CA Dly = 36
6314 11:04:10.162485 CS Dly: 1 (0~32)
6315 11:04:10.162782
6316 11:04:10.165604 ----->DramcWriteLeveling(PI) begin...
6317 11:04:10.165871 ==
6318 11:04:10.168945 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 11:04:10.172157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 11:04:10.172436 ==
6321 11:04:10.175643 Write leveling (Byte 0): 40 => 8
6322 11:04:10.178880 Write leveling (Byte 1): 32 => 0
6323 11:04:10.182252 DramcWriteLeveling(PI) end<-----
6324 11:04:10.182324
6325 11:04:10.182387 ==
6326 11:04:10.185392 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 11:04:10.188518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 11:04:10.192095 ==
6329 11:04:10.192196 [Gating] SW mode calibration
6330 11:04:10.198451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6331 11:04:10.205455 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6332 11:04:10.208722 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6333 11:04:10.215169 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 11:04:10.218080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 11:04:10.221329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 11:04:10.228175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 11:04:10.231280 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 11:04:10.234813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 11:04:10.241070 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 11:04:10.244745 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 11:04:10.247668 Total UI for P1: 0, mck2ui 16
6342 11:04:10.251266 best dqsien dly found for B0: ( 0, 14, 24)
6343 11:04:10.254339 Total UI for P1: 0, mck2ui 16
6344 11:04:10.257918 best dqsien dly found for B1: ( 0, 14, 24)
6345 11:04:10.261043 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6346 11:04:10.264400 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6347 11:04:10.264501
6348 11:04:10.268024 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6349 11:04:10.271180 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 11:04:10.274240 [Gating] SW calibration Done
6351 11:04:10.274334 ==
6352 11:04:10.277368 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 11:04:10.284173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 11:04:10.284271 ==
6355 11:04:10.284357 RX Vref Scan: 0
6356 11:04:10.284440
6357 11:04:10.287840 RX Vref 0 -> 0, step: 1
6358 11:04:10.287908
6359 11:04:10.290652 RX Delay -410 -> 252, step: 16
6360 11:04:10.294464 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6361 11:04:10.297385 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6362 11:04:10.304056 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6363 11:04:10.307366 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6364 11:04:10.310927 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6365 11:04:10.313850 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6366 11:04:10.320347 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6367 11:04:10.323829 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6368 11:04:10.327252 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6369 11:04:10.330220 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6370 11:04:10.336906 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6371 11:04:10.340345 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6372 11:04:10.343565 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6373 11:04:10.349953 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6374 11:04:10.353683 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6375 11:04:10.356601 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6376 11:04:10.356695 ==
6377 11:04:10.360129 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 11:04:10.363030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 11:04:10.363125 ==
6380 11:04:10.366819 DQS Delay:
6381 11:04:10.366911 DQS0 = 43, DQS1 = 59
6382 11:04:10.370278 DQM Delay:
6383 11:04:10.370370 DQM0 = 10, DQM1 = 11
6384 11:04:10.372990 DQ Delay:
6385 11:04:10.373085 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6386 11:04:10.376503 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6387 11:04:10.379617 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6388 11:04:10.382772 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6389 11:04:10.382854
6390 11:04:10.382913
6391 11:04:10.382967 ==
6392 11:04:10.386114 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 11:04:10.393049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 11:04:10.393125 ==
6395 11:04:10.393184
6396 11:04:10.393244
6397 11:04:10.396431 TX Vref Scan disable
6398 11:04:10.396494 == TX Byte 0 ==
6399 11:04:10.399689 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 11:04:10.406049 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 11:04:10.406120 == TX Byte 1 ==
6402 11:04:10.409469 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6403 11:04:10.415967 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6404 11:04:10.416044 ==
6405 11:04:10.419320 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 11:04:10.422884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 11:04:10.422960 ==
6408 11:04:10.423018
6409 11:04:10.423072
6410 11:04:10.426056 TX Vref Scan disable
6411 11:04:10.426131 == TX Byte 0 ==
6412 11:04:10.429442 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 11:04:10.436286 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 11:04:10.436362 == TX Byte 1 ==
6415 11:04:10.439002 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6416 11:04:10.445712 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6417 11:04:10.445788
6418 11:04:10.445846 [DATLAT]
6419 11:04:10.445900 Freq=400, CH0 RK0
6420 11:04:10.449153
6421 11:04:10.449228 DATLAT Default: 0xf
6422 11:04:10.452626 0, 0xFFFF, sum = 0
6423 11:04:10.452709 1, 0xFFFF, sum = 0
6424 11:04:10.455948 2, 0xFFFF, sum = 0
6425 11:04:10.456048 3, 0xFFFF, sum = 0
6426 11:04:10.458939 4, 0xFFFF, sum = 0
6427 11:04:10.459033 5, 0xFFFF, sum = 0
6428 11:04:10.462818 6, 0xFFFF, sum = 0
6429 11:04:10.462884 7, 0xFFFF, sum = 0
6430 11:04:10.465515 8, 0xFFFF, sum = 0
6431 11:04:10.465580 9, 0xFFFF, sum = 0
6432 11:04:10.469107 10, 0xFFFF, sum = 0
6433 11:04:10.469174 11, 0xFFFF, sum = 0
6434 11:04:10.472253 12, 0xFFFF, sum = 0
6435 11:04:10.472318 13, 0x0, sum = 1
6436 11:04:10.475612 14, 0x0, sum = 2
6437 11:04:10.475688 15, 0x0, sum = 3
6438 11:04:10.478441 16, 0x0, sum = 4
6439 11:04:10.478528 best_step = 14
6440 11:04:10.478586
6441 11:04:10.478640 ==
6442 11:04:10.481850 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 11:04:10.488379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 11:04:10.488455 ==
6445 11:04:10.488514 RX Vref Scan: 1
6446 11:04:10.488568
6447 11:04:10.491853 RX Vref 0 -> 0, step: 1
6448 11:04:10.491927
6449 11:04:10.495171 RX Delay -359 -> 252, step: 8
6450 11:04:10.495246
6451 11:04:10.498673 Set Vref, RX VrefLevel [Byte0]: 67
6452 11:04:10.501461 [Byte1]: 51
6453 11:04:10.505272
6454 11:04:10.505347 Final RX Vref Byte 0 = 67 to rank0
6455 11:04:10.508813 Final RX Vref Byte 1 = 51 to rank0
6456 11:04:10.511971 Final RX Vref Byte 0 = 67 to rank1
6457 11:04:10.515004 Final RX Vref Byte 1 = 51 to rank1==
6458 11:04:10.518212 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 11:04:10.525071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 11:04:10.525157 ==
6461 11:04:10.525221 DQS Delay:
6462 11:04:10.527974 DQS0 = 48, DQS1 = 60
6463 11:04:10.528044 DQM Delay:
6464 11:04:10.531433 DQM0 = 10, DQM1 = 11
6465 11:04:10.531556 DQ Delay:
6466 11:04:10.534763 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6467 11:04:10.538329 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6468 11:04:10.538431 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6469 11:04:10.544717 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6470 11:04:10.544786
6471 11:04:10.544841
6472 11:04:10.551443 [DQSOSCAuto] RK0, (LSB)MR18= 0xc487, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6473 11:04:10.554358 CH0 RK0: MR19=C0C, MR18=C487
6474 11:04:10.561318 CH0_RK0: MR19=0xC0C, MR18=0xC487, DQSOSC=385, MR23=63, INC=398, DEC=265
6475 11:04:10.561394 ==
6476 11:04:10.564476 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 11:04:10.567790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 11:04:10.567869 ==
6479 11:04:10.571355 [Gating] SW mode calibration
6480 11:04:10.577747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6481 11:04:10.584289 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6482 11:04:10.587623 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 11:04:10.590971 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 11:04:10.597300 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 11:04:10.600613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 11:04:10.604133 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 11:04:10.610967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 11:04:10.614022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 11:04:10.617156 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 11:04:10.623654 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 11:04:10.627199 Total UI for P1: 0, mck2ui 16
6492 11:04:10.630300 best dqsien dly found for B0: ( 0, 14, 24)
6493 11:04:10.630385 Total UI for P1: 0, mck2ui 16
6494 11:04:10.636840 best dqsien dly found for B1: ( 0, 14, 24)
6495 11:04:10.640296 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6496 11:04:10.643595 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6497 11:04:10.643677
6498 11:04:10.646856 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6499 11:04:10.650304 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 11:04:10.653581 [Gating] SW calibration Done
6501 11:04:10.653676 ==
6502 11:04:10.656516 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 11:04:10.659862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 11:04:10.659936 ==
6505 11:04:10.663183 RX Vref Scan: 0
6506 11:04:10.663274
6507 11:04:10.666467 RX Vref 0 -> 0, step: 1
6508 11:04:10.666557
6509 11:04:10.666628 RX Delay -410 -> 252, step: 16
6510 11:04:10.673380 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6511 11:04:10.676453 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6512 11:04:10.680266 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6513 11:04:10.683658 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6514 11:04:10.689850 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6515 11:04:10.692955 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6516 11:04:10.696807 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6517 11:04:10.703312 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6518 11:04:10.706292 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6519 11:04:10.709877 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6520 11:04:10.712967 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6521 11:04:10.719574 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6522 11:04:10.722842 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6523 11:04:10.726014 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6524 11:04:10.729715 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6525 11:04:10.736121 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6526 11:04:10.736193 ==
6527 11:04:10.739127 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 11:04:10.742504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 11:04:10.742596 ==
6530 11:04:10.742680 DQS Delay:
6531 11:04:10.745910 DQS0 = 43, DQS1 = 59
6532 11:04:10.745998 DQM Delay:
6533 11:04:10.749225 DQM0 = 10, DQM1 = 16
6534 11:04:10.749313 DQ Delay:
6535 11:04:10.752458 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6536 11:04:10.755886 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6537 11:04:10.759337 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6538 11:04:10.762341 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6539 11:04:10.762436
6540 11:04:10.762524
6541 11:04:10.762604 ==
6542 11:04:10.765864 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 11:04:10.769363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 11:04:10.769433 ==
6545 11:04:10.769489
6546 11:04:10.772233
6547 11:04:10.772321 TX Vref Scan disable
6548 11:04:10.775580 == TX Byte 0 ==
6549 11:04:10.778951 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6550 11:04:10.782209 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6551 11:04:10.785638 == TX Byte 1 ==
6552 11:04:10.788861 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6553 11:04:10.792241 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6554 11:04:10.792332 ==
6555 11:04:10.795575 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 11:04:10.801684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 11:04:10.801757 ==
6558 11:04:10.801815
6559 11:04:10.801872
6560 11:04:10.801925 TX Vref Scan disable
6561 11:04:10.805178 == TX Byte 0 ==
6562 11:04:10.808510 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6563 11:04:10.811879 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6564 11:04:10.814870 == TX Byte 1 ==
6565 11:04:10.818462 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6566 11:04:10.821613 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6567 11:04:10.821705
6568 11:04:10.824922 [DATLAT]
6569 11:04:10.825028 Freq=400, CH0 RK1
6570 11:04:10.825121
6571 11:04:10.828282 DATLAT Default: 0xe
6572 11:04:10.828350 0, 0xFFFF, sum = 0
6573 11:04:10.831639 1, 0xFFFF, sum = 0
6574 11:04:10.831711 2, 0xFFFF, sum = 0
6575 11:04:10.834715 3, 0xFFFF, sum = 0
6576 11:04:10.834782 4, 0xFFFF, sum = 0
6577 11:04:10.838244 5, 0xFFFF, sum = 0
6578 11:04:10.838313 6, 0xFFFF, sum = 0
6579 11:04:10.841216 7, 0xFFFF, sum = 0
6580 11:04:10.841283 8, 0xFFFF, sum = 0
6581 11:04:10.844813 9, 0xFFFF, sum = 0
6582 11:04:10.847877 10, 0xFFFF, sum = 0
6583 11:04:10.847946 11, 0xFFFF, sum = 0
6584 11:04:10.851385 12, 0xFFFF, sum = 0
6585 11:04:10.851504 13, 0x0, sum = 1
6586 11:04:10.854597 14, 0x0, sum = 2
6587 11:04:10.854662 15, 0x0, sum = 3
6588 11:04:10.857897 16, 0x0, sum = 4
6589 11:04:10.857992 best_step = 14
6590 11:04:10.858084
6591 11:04:10.858168 ==
6592 11:04:10.861013 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 11:04:10.864515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 11:04:10.864616 ==
6595 11:04:10.868083 RX Vref Scan: 0
6596 11:04:10.868181
6597 11:04:10.870970 RX Vref 0 -> 0, step: 1
6598 11:04:10.871061
6599 11:04:10.871143 RX Delay -359 -> 252, step: 8
6600 11:04:10.879679 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6601 11:04:10.883433 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6602 11:04:10.886461 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6603 11:04:10.889827 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6604 11:04:10.896662 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6605 11:04:10.900095 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6606 11:04:10.903354 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6607 11:04:10.906387 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6608 11:04:10.913002 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6609 11:04:10.916654 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6610 11:04:10.919442 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6611 11:04:10.926029 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6612 11:04:10.929495 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6613 11:04:10.932727 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6614 11:04:10.935908 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6615 11:04:10.942576 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6616 11:04:10.942667 ==
6617 11:04:10.946003 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 11:04:10.949527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 11:04:10.949622 ==
6620 11:04:10.949707 DQS Delay:
6621 11:04:10.953070 DQS0 = 44, DQS1 = 60
6622 11:04:10.953177 DQM Delay:
6623 11:04:10.955625 DQM0 = 7, DQM1 = 14
6624 11:04:10.955710 DQ Delay:
6625 11:04:10.959234 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =0
6626 11:04:10.962379 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6627 11:04:10.965784 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6628 11:04:10.969237 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =20
6629 11:04:10.969331
6630 11:04:10.969415
6631 11:04:10.975377 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe4a, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6632 11:04:10.978866 CH0 RK1: MR19=C0C, MR18=BE4A
6633 11:04:10.985675 CH0_RK1: MR19=0xC0C, MR18=0xBE4A, DQSOSC=386, MR23=63, INC=396, DEC=264
6634 11:04:10.989040 [RxdqsGatingPostProcess] freq 400
6635 11:04:10.995361 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6636 11:04:10.999020 best DQS0 dly(2T, 0.5T) = (0, 10)
6637 11:04:11.001806 best DQS1 dly(2T, 0.5T) = (0, 10)
6638 11:04:11.005295 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6639 11:04:11.005387 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6640 11:04:11.008650 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 11:04:11.012321 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 11:04:11.015520 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 11:04:11.018520 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 11:04:11.021942 Pre-setting of DQS Precalculation
6645 11:04:11.028418 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6646 11:04:11.028515 ==
6647 11:04:11.031900 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 11:04:11.034776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 11:04:11.034847 ==
6650 11:04:11.041980 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 11:04:11.048312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6652 11:04:11.051442 [CA 0] Center 36 (8~64) winsize 57
6653 11:04:11.051533 [CA 1] Center 36 (8~64) winsize 57
6654 11:04:11.054826 [CA 2] Center 36 (8~64) winsize 57
6655 11:04:11.058099 [CA 3] Center 36 (8~64) winsize 57
6656 11:04:11.061483 [CA 4] Center 36 (8~64) winsize 57
6657 11:04:11.064911 [CA 5] Center 36 (8~64) winsize 57
6658 11:04:11.065048
6659 11:04:11.068013 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6660 11:04:11.068144
6661 11:04:11.074656 [CATrainingPosCal] consider 1 rank data
6662 11:04:11.074818 u2DelayCellTimex100 = 270/100 ps
6663 11:04:11.081530 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:04:11.084648 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 11:04:11.087992 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 11:04:11.091316 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:04:11.094478 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 11:04:11.097949 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 11:04:11.098043
6670 11:04:11.101313 CA PerBit enable=1, Macro0, CA PI delay=36
6671 11:04:11.101405
6672 11:04:11.104559 [CBTSetCACLKResult] CA Dly = 36
6673 11:04:11.107527 CS Dly: 1 (0~32)
6674 11:04:11.107595 ==
6675 11:04:11.111030 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 11:04:11.114773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 11:04:11.114841 ==
6678 11:04:11.121263 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6679 11:04:11.124178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6680 11:04:11.127726 [CA 0] Center 36 (8~64) winsize 57
6681 11:04:11.130760 [CA 1] Center 36 (8~64) winsize 57
6682 11:04:11.134009 [CA 2] Center 36 (8~64) winsize 57
6683 11:04:11.137332 [CA 3] Center 36 (8~64) winsize 57
6684 11:04:11.141088 [CA 4] Center 36 (8~64) winsize 57
6685 11:04:11.144006 [CA 5] Center 36 (8~64) winsize 57
6686 11:04:11.144091
6687 11:04:11.147121 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6688 11:04:11.147220
6689 11:04:11.150562 [CATrainingPosCal] consider 2 rank data
6690 11:04:11.154119 u2DelayCellTimex100 = 270/100 ps
6691 11:04:11.156996 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:04:11.160404 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:04:11.166944 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:04:11.170558 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:04:11.173473 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 11:04:11.177131 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 11:04:11.177222
6698 11:04:11.180288 CA PerBit enable=1, Macro0, CA PI delay=36
6699 11:04:11.180355
6700 11:04:11.183284 [CBTSetCACLKResult] CA Dly = 36
6701 11:04:11.183387 CS Dly: 1 (0~32)
6702 11:04:11.183485
6703 11:04:11.190269 ----->DramcWriteLeveling(PI) begin...
6704 11:04:11.190361 ==
6705 11:04:11.193569 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 11:04:11.196678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 11:04:11.196745 ==
6708 11:04:11.199995 Write leveling (Byte 0): 40 => 8
6709 11:04:11.203355 Write leveling (Byte 1): 32 => 0
6710 11:04:11.206653 DramcWriteLeveling(PI) end<-----
6711 11:04:11.206734
6712 11:04:11.206791 ==
6713 11:04:11.209981 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 11:04:11.213361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 11:04:11.213452 ==
6716 11:04:11.216623 [Gating] SW mode calibration
6717 11:04:11.222994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6718 11:04:11.230088 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6719 11:04:11.232916 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6720 11:04:11.236546 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 11:04:11.243347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 11:04:11.246173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 11:04:11.250157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 11:04:11.256017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 11:04:11.259307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 11:04:11.263097 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 11:04:11.269431 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 11:04:11.269528 Total UI for P1: 0, mck2ui 16
6729 11:04:11.275852 best dqsien dly found for B0: ( 0, 14, 24)
6730 11:04:11.275954 Total UI for P1: 0, mck2ui 16
6731 11:04:11.279142 best dqsien dly found for B1: ( 0, 14, 24)
6732 11:04:11.285963 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6733 11:04:11.289372 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6734 11:04:11.289455
6735 11:04:11.292413 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6736 11:04:11.295732 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 11:04:11.298802 [Gating] SW calibration Done
6738 11:04:11.298879 ==
6739 11:04:11.302178 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 11:04:11.305437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 11:04:11.305513 ==
6742 11:04:11.308871 RX Vref Scan: 0
6743 11:04:11.308947
6744 11:04:11.309007 RX Vref 0 -> 0, step: 1
6745 11:04:11.309063
6746 11:04:11.312216 RX Delay -410 -> 252, step: 16
6747 11:04:11.319120 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6748 11:04:11.322102 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6749 11:04:11.325633 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6750 11:04:11.328812 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6751 11:04:11.335824 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6752 11:04:11.338773 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6753 11:04:11.342239 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6754 11:04:11.345757 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6755 11:04:11.351701 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6756 11:04:11.355101 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6757 11:04:11.358395 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6758 11:04:11.361643 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6759 11:04:11.368607 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6760 11:04:11.371689 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6761 11:04:11.375112 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6762 11:04:11.382040 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6763 11:04:11.382117 ==
6764 11:04:11.384906 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 11:04:11.388431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 11:04:11.388508 ==
6767 11:04:11.388569 DQS Delay:
6768 11:04:11.391845 DQS0 = 43, DQS1 = 51
6769 11:04:11.391968 DQM Delay:
6770 11:04:11.394997 DQM0 = 12, DQM1 = 14
6771 11:04:11.395072 DQ Delay:
6772 11:04:11.398305 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6773 11:04:11.401651 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6774 11:04:11.404750 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6775 11:04:11.407675 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6776 11:04:11.407752
6777 11:04:11.407810
6778 11:04:11.407865 ==
6779 11:04:11.411385 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 11:04:11.414876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 11:04:11.414952 ==
6782 11:04:11.415011
6783 11:04:11.415066
6784 11:04:11.418037 TX Vref Scan disable
6785 11:04:11.418117 == TX Byte 0 ==
6786 11:04:11.424710 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 11:04:11.427766 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 11:04:11.427835 == TX Byte 1 ==
6789 11:04:11.434648 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6790 11:04:11.437942 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6791 11:04:11.438011 ==
6792 11:04:11.440966 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 11:04:11.444357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 11:04:11.444449 ==
6795 11:04:11.444532
6796 11:04:11.447760
6797 11:04:11.447847 TX Vref Scan disable
6798 11:04:11.451309 == TX Byte 0 ==
6799 11:04:11.454005 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 11:04:11.457376 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 11:04:11.460600 == TX Byte 1 ==
6802 11:04:11.463822 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6803 11:04:11.467046 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6804 11:04:11.467136
6805 11:04:11.470962 [DATLAT]
6806 11:04:11.471054 Freq=400, CH1 RK0
6807 11:04:11.471137
6808 11:04:11.474152 DATLAT Default: 0xf
6809 11:04:11.474243 0, 0xFFFF, sum = 0
6810 11:04:11.477289 1, 0xFFFF, sum = 0
6811 11:04:11.477384 2, 0xFFFF, sum = 0
6812 11:04:11.480704 3, 0xFFFF, sum = 0
6813 11:04:11.480800 4, 0xFFFF, sum = 0
6814 11:04:11.483593 5, 0xFFFF, sum = 0
6815 11:04:11.483681 6, 0xFFFF, sum = 0
6816 11:04:11.486835 7, 0xFFFF, sum = 0
6817 11:04:11.486926 8, 0xFFFF, sum = 0
6818 11:04:11.490158 9, 0xFFFF, sum = 0
6819 11:04:11.490247 10, 0xFFFF, sum = 0
6820 11:04:11.493497 11, 0xFFFF, sum = 0
6821 11:04:11.493588 12, 0xFFFF, sum = 0
6822 11:04:11.496925 13, 0x0, sum = 1
6823 11:04:11.497023 14, 0x0, sum = 2
6824 11:04:11.500244 15, 0x0, sum = 3
6825 11:04:11.500337 16, 0x0, sum = 4
6826 11:04:11.503717 best_step = 14
6827 11:04:11.503794
6828 11:04:11.503849 ==
6829 11:04:11.506835 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 11:04:11.510407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 11:04:11.510489 ==
6832 11:04:11.513276 RX Vref Scan: 1
6833 11:04:11.513365
6834 11:04:11.513447 RX Vref 0 -> 0, step: 1
6835 11:04:11.513525
6836 11:04:11.516933 RX Delay -343 -> 252, step: 8
6837 11:04:11.517024
6838 11:04:11.520405 Set Vref, RX VrefLevel [Byte0]: 50
6839 11:04:11.523330 [Byte1]: 61
6840 11:04:11.528271
6841 11:04:11.528367 Final RX Vref Byte 0 = 50 to rank0
6842 11:04:11.531375 Final RX Vref Byte 1 = 61 to rank0
6843 11:04:11.534546 Final RX Vref Byte 0 = 50 to rank1
6844 11:04:11.537996 Final RX Vref Byte 1 = 61 to rank1==
6845 11:04:11.541269 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 11:04:11.548105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 11:04:11.548202 ==
6848 11:04:11.548287 DQS Delay:
6849 11:04:11.551040 DQS0 = 44, DQS1 = 56
6850 11:04:11.551130 DQM Delay:
6851 11:04:11.551215 DQM0 = 7, DQM1 = 11
6852 11:04:11.554459 DQ Delay:
6853 11:04:11.558025 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6854 11:04:11.558116 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6855 11:04:11.560929 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6856 11:04:11.564619 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6857 11:04:11.567620
6858 11:04:11.567718
6859 11:04:11.574199 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f74, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 389 ps
6860 11:04:11.577633 CH1 RK0: MR19=C0C, MR18=9F74
6861 11:04:11.584333 CH1_RK0: MR19=0xC0C, MR18=0x9F74, DQSOSC=389, MR23=63, INC=390, DEC=260
6862 11:04:11.584431 ==
6863 11:04:11.587302 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 11:04:11.590760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 11:04:11.590828 ==
6866 11:04:11.594312 [Gating] SW mode calibration
6867 11:04:11.600728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6868 11:04:11.607705 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6869 11:04:11.610588 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6870 11:04:11.613954 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 11:04:11.620773 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 11:04:11.623713 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 11:04:11.627203 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 11:04:11.633878 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 11:04:11.636825 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 11:04:11.640470 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 11:04:11.647319 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 11:04:11.647413 Total UI for P1: 0, mck2ui 16
6879 11:04:11.653647 best dqsien dly found for B0: ( 0, 14, 24)
6880 11:04:11.653740 Total UI for P1: 0, mck2ui 16
6881 11:04:11.660060 best dqsien dly found for B1: ( 0, 14, 24)
6882 11:04:11.663622 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6883 11:04:11.666726 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6884 11:04:11.666795
6885 11:04:11.670119 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6886 11:04:11.673339 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 11:04:11.677000 [Gating] SW calibration Done
6888 11:04:11.677096 ==
6889 11:04:11.680144 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 11:04:11.683295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 11:04:11.683392 ==
6892 11:04:11.686743 RX Vref Scan: 0
6893 11:04:11.686829
6894 11:04:11.686911 RX Vref 0 -> 0, step: 1
6895 11:04:11.686991
6896 11:04:11.689982 RX Delay -410 -> 252, step: 16
6897 11:04:11.696769 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6898 11:04:11.699993 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6899 11:04:11.703199 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6900 11:04:11.706758 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6901 11:04:11.712914 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6902 11:04:11.716234 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6903 11:04:11.719507 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6904 11:04:11.722843 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6905 11:04:11.729932 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6906 11:04:11.732769 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6907 11:04:11.736495 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6908 11:04:11.739500 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6909 11:04:11.746387 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6910 11:04:11.749435 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6911 11:04:11.752921 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6912 11:04:11.759257 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6913 11:04:11.759352 ==
6914 11:04:11.762786 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 11:04:11.765797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 11:04:11.765894 ==
6917 11:04:11.765979 DQS Delay:
6918 11:04:11.769009 DQS0 = 51, DQS1 = 59
6919 11:04:11.769096 DQM Delay:
6920 11:04:11.772290 DQM0 = 19, DQM1 = 22
6921 11:04:11.772384 DQ Delay:
6922 11:04:11.775551 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6923 11:04:11.778880 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6924 11:04:11.782357 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6925 11:04:11.785817 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6926 11:04:11.785907
6927 11:04:11.785990
6928 11:04:11.786070 ==
6929 11:04:11.788759 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 11:04:11.792340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 11:04:11.795655 ==
6932 11:04:11.795720
6933 11:04:11.795774
6934 11:04:11.795825 TX Vref Scan disable
6935 11:04:11.798911 == TX Byte 0 ==
6936 11:04:11.802205 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6937 11:04:11.805604 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6938 11:04:11.809046 == TX Byte 1 ==
6939 11:04:11.812018 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6940 11:04:11.815279 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6941 11:04:11.815379 ==
6942 11:04:11.818637 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 11:04:11.825015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 11:04:11.825109 ==
6945 11:04:11.825195
6946 11:04:11.825275
6947 11:04:11.825350 TX Vref Scan disable
6948 11:04:11.828541 == TX Byte 0 ==
6949 11:04:11.832009 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6950 11:04:11.834932 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6951 11:04:11.838537 == TX Byte 1 ==
6952 11:04:11.841959 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6953 11:04:11.844839 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6954 11:04:11.844923
6955 11:04:11.848310 [DATLAT]
6956 11:04:11.848394 Freq=400, CH1 RK1
6957 11:04:11.848476
6958 11:04:11.851760 DATLAT Default: 0xe
6959 11:04:11.851852 0, 0xFFFF, sum = 0
6960 11:04:11.854691 1, 0xFFFF, sum = 0
6961 11:04:11.854787 2, 0xFFFF, sum = 0
6962 11:04:11.857940 3, 0xFFFF, sum = 0
6963 11:04:11.858031 4, 0xFFFF, sum = 0
6964 11:04:11.861253 5, 0xFFFF, sum = 0
6965 11:04:11.861342 6, 0xFFFF, sum = 0
6966 11:04:11.864745 7, 0xFFFF, sum = 0
6967 11:04:11.868512 8, 0xFFFF, sum = 0
6968 11:04:11.868598 9, 0xFFFF, sum = 0
6969 11:04:11.871058 10, 0xFFFF, sum = 0
6970 11:04:11.871148 11, 0xFFFF, sum = 0
6971 11:04:11.874967 12, 0xFFFF, sum = 0
6972 11:04:11.875064 13, 0x0, sum = 1
6973 11:04:11.878067 14, 0x0, sum = 2
6974 11:04:11.878170 15, 0x0, sum = 3
6975 11:04:11.880966 16, 0x0, sum = 4
6976 11:04:11.881051 best_step = 14
6977 11:04:11.881108
6978 11:04:11.881162 ==
6979 11:04:11.884239 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 11:04:11.887631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 11:04:11.887697 ==
6982 11:04:11.891239 RX Vref Scan: 0
6983 11:04:11.891331
6984 11:04:11.894289 RX Vref 0 -> 0, step: 1
6985 11:04:11.894377
6986 11:04:11.894460 RX Delay -359 -> 252, step: 8
6987 11:04:11.903762 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6988 11:04:11.906815 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6989 11:04:11.910216 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6990 11:04:11.916920 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6991 11:04:11.919803 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6992 11:04:11.923381 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6993 11:04:11.926301 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6994 11:04:11.933044 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6995 11:04:11.936544 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
6996 11:04:11.939947 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6997 11:04:11.942822 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6998 11:04:11.949643 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
6999 11:04:11.953096 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7000 11:04:11.956458 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7001 11:04:11.959603 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7002 11:04:11.966348 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7003 11:04:11.966444 ==
7004 11:04:11.969609 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 11:04:11.972865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 11:04:11.972955 ==
7007 11:04:11.973038 DQS Delay:
7008 11:04:11.976060 DQS0 = 44, DQS1 = 60
7009 11:04:11.976156 DQM Delay:
7010 11:04:11.979629 DQM0 = 7, DQM1 = 14
7011 11:04:11.979710 DQ Delay:
7012 11:04:11.982498 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
7013 11:04:11.985826 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7014 11:04:11.989117 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7015 11:04:11.992501 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7016 11:04:11.992592
7017 11:04:11.992676
7018 11:04:11.999327 [DQSOSCAuto] RK1, (LSB)MR18= 0x7564, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7019 11:04:12.002355 CH1 RK1: MR19=C0C, MR18=7564
7020 11:04:12.008974 CH1_RK1: MR19=0xC0C, MR18=0x7564, DQSOSC=395, MR23=63, INC=378, DEC=252
7021 11:04:12.012375 [RxdqsGatingPostProcess] freq 400
7022 11:04:12.019147 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7023 11:04:12.022072 best DQS0 dly(2T, 0.5T) = (0, 10)
7024 11:04:12.025465 best DQS1 dly(2T, 0.5T) = (0, 10)
7025 11:04:12.029128 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7026 11:04:12.031925 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7027 11:04:12.032013 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 11:04:12.035247 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 11:04:12.038660 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 11:04:12.042123 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 11:04:12.045465 Pre-setting of DQS Precalculation
7032 11:04:12.051771 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7033 11:04:12.058392 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7034 11:04:12.064950 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7035 11:04:12.065022
7036 11:04:12.065083
7037 11:04:12.068127 [Calibration Summary] 800 Mbps
7038 11:04:12.068220 CH 0, Rank 0
7039 11:04:12.071616 SW Impedance : PASS
7040 11:04:12.074980 DUTY Scan : NO K
7041 11:04:12.075070 ZQ Calibration : PASS
7042 11:04:12.078018 Jitter Meter : NO K
7043 11:04:12.081413 CBT Training : PASS
7044 11:04:12.081503 Write leveling : PASS
7045 11:04:12.084824 RX DQS gating : PASS
7046 11:04:12.088144 RX DQ/DQS(RDDQC) : PASS
7047 11:04:12.088233 TX DQ/DQS : PASS
7048 11:04:12.091345 RX DATLAT : PASS
7049 11:04:12.094630 RX DQ/DQS(Engine): PASS
7050 11:04:12.094720 TX OE : NO K
7051 11:04:12.098305 All Pass.
7052 11:04:12.098395
7053 11:04:12.098475 CH 0, Rank 1
7054 11:04:12.101448 SW Impedance : PASS
7055 11:04:12.101537 DUTY Scan : NO K
7056 11:04:12.104977 ZQ Calibration : PASS
7057 11:04:12.108214 Jitter Meter : NO K
7058 11:04:12.108281 CBT Training : PASS
7059 11:04:12.111219 Write leveling : NO K
7060 11:04:12.114592 RX DQS gating : PASS
7061 11:04:12.114682 RX DQ/DQS(RDDQC) : PASS
7062 11:04:12.118040 TX DQ/DQS : PASS
7063 11:04:12.118127 RX DATLAT : PASS
7064 11:04:12.121186 RX DQ/DQS(Engine): PASS
7065 11:04:12.124537 TX OE : NO K
7066 11:04:12.124625 All Pass.
7067 11:04:12.124706
7068 11:04:12.127794 CH 1, Rank 0
7069 11:04:12.127862 SW Impedance : PASS
7070 11:04:12.131000 DUTY Scan : NO K
7071 11:04:12.131087 ZQ Calibration : PASS
7072 11:04:12.134397 Jitter Meter : NO K
7073 11:04:12.137957 CBT Training : PASS
7074 11:04:12.138045 Write leveling : PASS
7075 11:04:12.141028 RX DQS gating : PASS
7076 11:04:12.144293 RX DQ/DQS(RDDQC) : PASS
7077 11:04:12.144384 TX DQ/DQS : PASS
7078 11:04:12.147692 RX DATLAT : PASS
7079 11:04:12.150881 RX DQ/DQS(Engine): PASS
7080 11:04:12.150972 TX OE : NO K
7081 11:04:12.154361 All Pass.
7082 11:04:12.154451
7083 11:04:12.154531 CH 1, Rank 1
7084 11:04:12.157641 SW Impedance : PASS
7085 11:04:12.157731 DUTY Scan : NO K
7086 11:04:12.161211 ZQ Calibration : PASS
7087 11:04:12.164436 Jitter Meter : NO K
7088 11:04:12.164498 CBT Training : PASS
7089 11:04:12.167729 Write leveling : NO K
7090 11:04:12.171083 RX DQS gating : PASS
7091 11:04:12.171176 RX DQ/DQS(RDDQC) : PASS
7092 11:04:12.174478 TX DQ/DQS : PASS
7093 11:04:12.174568 RX DATLAT : PASS
7094 11:04:12.177444 RX DQ/DQS(Engine): PASS
7095 11:04:12.180702 TX OE : NO K
7096 11:04:12.180795 All Pass.
7097 11:04:12.180878
7098 11:04:12.184277 DramC Write-DBI off
7099 11:04:12.187690 PER_BANK_REFRESH: Hybrid Mode
7100 11:04:12.187757 TX_TRACKING: ON
7101 11:04:12.197164 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7102 11:04:12.200561 [FAST_K] Save calibration result to emmc
7103 11:04:12.203895 dramc_set_vcore_voltage set vcore to 725000
7104 11:04:12.207557 Read voltage for 1600, 0
7105 11:04:12.207625 Vio18 = 0
7106 11:04:12.207681 Vcore = 725000
7107 11:04:12.210379 Vdram = 0
7108 11:04:12.210466 Vddq = 0
7109 11:04:12.210549 Vmddr = 0
7110 11:04:12.217185 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7111 11:04:12.220342 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7112 11:04:12.223813 MEM_TYPE=3, freq_sel=13
7113 11:04:12.226998 sv_algorithm_assistance_LP4_3733
7114 11:04:12.230382 ============ PULL DRAM RESETB DOWN ============
7115 11:04:12.233793 ========== PULL DRAM RESETB DOWN end =========
7116 11:04:12.240099 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7117 11:04:12.243515 ===================================
7118 11:04:12.246946 LPDDR4 DRAM CONFIGURATION
7119 11:04:12.247037 ===================================
7120 11:04:12.250307 EX_ROW_EN[0] = 0x0
7121 11:04:12.253454 EX_ROW_EN[1] = 0x0
7122 11:04:12.253543 LP4Y_EN = 0x0
7123 11:04:12.256771 WORK_FSP = 0x1
7124 11:04:12.256861 WL = 0x5
7125 11:04:12.260194 RL = 0x5
7126 11:04:12.260260 BL = 0x2
7127 11:04:12.263741 RPST = 0x0
7128 11:04:12.263809 RD_PRE = 0x0
7129 11:04:12.267639 WR_PRE = 0x1
7130 11:04:12.267705 WR_PST = 0x1
7131 11:04:12.270210 DBI_WR = 0x0
7132 11:04:12.270298 DBI_RD = 0x0
7133 11:04:12.273538 OTF = 0x1
7134 11:04:12.276374 ===================================
7135 11:04:12.279664 ===================================
7136 11:04:12.279754 ANA top config
7137 11:04:12.283309 ===================================
7138 11:04:12.286202 DLL_ASYNC_EN = 0
7139 11:04:12.289809 ALL_SLAVE_EN = 0
7140 11:04:12.292702 NEW_RANK_MODE = 1
7141 11:04:12.296258 DLL_IDLE_MODE = 1
7142 11:04:12.296324 LP45_APHY_COMB_EN = 1
7143 11:04:12.299510 TX_ODT_DIS = 0
7144 11:04:12.303050 NEW_8X_MODE = 1
7145 11:04:12.306090 ===================================
7146 11:04:12.309573 ===================================
7147 11:04:12.312929 data_rate = 3200
7148 11:04:12.315924 CKR = 1
7149 11:04:12.316015 DQ_P2S_RATIO = 8
7150 11:04:12.319510 ===================================
7151 11:04:12.322877 CA_P2S_RATIO = 8
7152 11:04:12.326152 DQ_CA_OPEN = 0
7153 11:04:12.329394 DQ_SEMI_OPEN = 0
7154 11:04:12.332651 CA_SEMI_OPEN = 0
7155 11:04:12.335952 CA_FULL_RATE = 0
7156 11:04:12.336023 DQ_CKDIV4_EN = 0
7157 11:04:12.339460 CA_CKDIV4_EN = 0
7158 11:04:12.342892 CA_PREDIV_EN = 0
7159 11:04:12.345792 PH8_DLY = 12
7160 11:04:12.349284 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7161 11:04:12.352207 DQ_AAMCK_DIV = 4
7162 11:04:12.352296 CA_AAMCK_DIV = 4
7163 11:04:12.355766 CA_ADMCK_DIV = 4
7164 11:04:12.359214 DQ_TRACK_CA_EN = 0
7165 11:04:12.362226 CA_PICK = 1600
7166 11:04:12.365524 CA_MCKIO = 1600
7167 11:04:12.368721 MCKIO_SEMI = 0
7168 11:04:12.372043 PLL_FREQ = 3068
7169 11:04:12.375325 DQ_UI_PI_RATIO = 32
7170 11:04:12.375413 CA_UI_PI_RATIO = 0
7171 11:04:12.379308 ===================================
7172 11:04:12.382559 ===================================
7173 11:04:12.385734 memory_type:LPDDR4
7174 11:04:12.388572 GP_NUM : 10
7175 11:04:12.388661 SRAM_EN : 1
7176 11:04:12.392231 MD32_EN : 0
7177 11:04:12.394999 ===================================
7178 11:04:12.398541 [ANA_INIT] >>>>>>>>>>>>>>
7179 11:04:12.402069 <<<<<< [CONFIGURE PHASE]: ANA_TX
7180 11:04:12.405068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7181 11:04:12.408603 ===================================
7182 11:04:12.408694 data_rate = 3200,PCW = 0X7600
7183 11:04:12.411503 ===================================
7184 11:04:12.418387 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7185 11:04:12.421469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7186 11:04:12.428515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 11:04:12.431689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7188 11:04:12.434890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7189 11:04:12.437998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7190 11:04:12.441806 [ANA_INIT] flow start
7191 11:04:12.445248 [ANA_INIT] PLL >>>>>>>>
7192 11:04:12.445341 [ANA_INIT] PLL <<<<<<<<
7193 11:04:12.448120 [ANA_INIT] MIDPI >>>>>>>>
7194 11:04:12.451608 [ANA_INIT] MIDPI <<<<<<<<
7195 11:04:12.451675 [ANA_INIT] DLL >>>>>>>>
7196 11:04:12.455077 [ANA_INIT] DLL <<<<<<<<
7197 11:04:12.457900 [ANA_INIT] flow end
7198 11:04:12.461223 ============ LP4 DIFF to SE enter ============
7199 11:04:12.464686 ============ LP4 DIFF to SE exit ============
7200 11:04:12.468065 [ANA_INIT] <<<<<<<<<<<<<
7201 11:04:12.471379 [Flow] Enable top DCM control >>>>>
7202 11:04:12.474836 [Flow] Enable top DCM control <<<<<
7203 11:04:12.477640 Enable DLL master slave shuffle
7204 11:04:12.481253 ==============================================================
7205 11:04:12.484779 Gating Mode config
7206 11:04:12.490955 ==============================================================
7207 11:04:12.491046 Config description:
7208 11:04:12.500928 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7209 11:04:12.507930 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7210 11:04:12.514200 SELPH_MODE 0: By rank 1: By Phase
7211 11:04:12.517668 ==============================================================
7212 11:04:12.521046 GAT_TRACK_EN = 1
7213 11:04:12.524321 RX_GATING_MODE = 2
7214 11:04:12.527527 RX_GATING_TRACK_MODE = 2
7215 11:04:12.531037 SELPH_MODE = 1
7216 11:04:12.533769 PICG_EARLY_EN = 1
7217 11:04:12.537411 VALID_LAT_VALUE = 1
7218 11:04:12.540576 ==============================================================
7219 11:04:12.543674 Enter into Gating configuration >>>>
7220 11:04:12.547329 Exit from Gating configuration <<<<
7221 11:04:12.550522 Enter into DVFS_PRE_config >>>>>
7222 11:04:12.563729 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7223 11:04:12.566679 Exit from DVFS_PRE_config <<<<<
7224 11:04:12.570639 Enter into PICG configuration >>>>
7225 11:04:12.573922 Exit from PICG configuration <<<<
7226 11:04:12.574014 [RX_INPUT] configuration >>>>>
7227 11:04:12.577046 [RX_INPUT] configuration <<<<<
7228 11:04:12.583477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7229 11:04:12.587035 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7230 11:04:12.593459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 11:04:12.599905 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 11:04:12.606790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 11:04:12.613370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 11:04:12.616613 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7235 11:04:12.619868 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7236 11:04:12.626505 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7237 11:04:12.629784 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7238 11:04:12.633360 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7239 11:04:12.639534 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 11:04:12.642646 ===================================
7241 11:04:12.642711 LPDDR4 DRAM CONFIGURATION
7242 11:04:12.646243 ===================================
7243 11:04:12.649429 EX_ROW_EN[0] = 0x0
7244 11:04:12.649519 EX_ROW_EN[1] = 0x0
7245 11:04:12.652768 LP4Y_EN = 0x0
7246 11:04:12.652834 WORK_FSP = 0x1
7247 11:04:12.656038 WL = 0x5
7248 11:04:12.656122 RL = 0x5
7249 11:04:12.659844 BL = 0x2
7250 11:04:12.659907 RPST = 0x0
7251 11:04:12.662652 RD_PRE = 0x0
7252 11:04:12.666045 WR_PRE = 0x1
7253 11:04:12.666132 WR_PST = 0x1
7254 11:04:12.669663 DBI_WR = 0x0
7255 11:04:12.669748 DBI_RD = 0x0
7256 11:04:12.672704 OTF = 0x1
7257 11:04:12.676227 ===================================
7258 11:04:12.679127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7259 11:04:12.682505 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7260 11:04:12.685717 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 11:04:12.689280 ===================================
7262 11:04:12.692411 LPDDR4 DRAM CONFIGURATION
7263 11:04:12.695798 ===================================
7264 11:04:12.698955 EX_ROW_EN[0] = 0x10
7265 11:04:12.699085 EX_ROW_EN[1] = 0x0
7266 11:04:12.702452 LP4Y_EN = 0x0
7267 11:04:12.702538 WORK_FSP = 0x1
7268 11:04:12.705833 WL = 0x5
7269 11:04:12.708636 RL = 0x5
7270 11:04:12.708720 BL = 0x2
7271 11:04:12.712097 RPST = 0x0
7272 11:04:12.712158 RD_PRE = 0x0
7273 11:04:12.715265 WR_PRE = 0x1
7274 11:04:12.715347 WR_PST = 0x1
7275 11:04:12.719177 DBI_WR = 0x0
7276 11:04:12.719261 DBI_RD = 0x0
7277 11:04:12.722405 OTF = 0x1
7278 11:04:12.725711 ===================================
7279 11:04:12.731965 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7280 11:04:12.732028 ==
7281 11:04:12.735071 Dram Type= 6, Freq= 0, CH_0, rank 0
7282 11:04:12.738707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 11:04:12.738796 ==
7284 11:04:12.742308 [Duty_Offset_Calibration]
7285 11:04:12.742394 B0:1 B1:-1 CA:0
7286 11:04:12.742474
7287 11:04:12.745253 [DutyScan_Calibration_Flow] k_type=0
7288 11:04:12.755715
7289 11:04:12.755808 ==CLK 0==
7290 11:04:12.759008 Final CLK duty delay cell = 0
7291 11:04:12.762291 [0] MAX Duty = 5124%(X100), DQS PI = 22
7292 11:04:12.765350 [0] MIN Duty = 4907%(X100), DQS PI = 4
7293 11:04:12.765442 [0] AVG Duty = 5015%(X100)
7294 11:04:12.768713
7295 11:04:12.772204 CH0 CLK Duty spec in!! Max-Min= 217%
7296 11:04:12.775616 [DutyScan_Calibration_Flow] ====Done====
7297 11:04:12.775705
7298 11:04:12.778503 [DutyScan_Calibration_Flow] k_type=1
7299 11:04:12.794717
7300 11:04:12.794811 ==DQS 0 ==
7301 11:04:12.798285 Final DQS duty delay cell = -4
7302 11:04:12.801084 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7303 11:04:12.804465 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7304 11:04:12.808109 [-4] AVG Duty = 4922%(X100)
7305 11:04:12.808170
7306 11:04:12.808224 ==DQS 1 ==
7307 11:04:12.811288 Final DQS duty delay cell = 0
7308 11:04:12.814474 [0] MAX Duty = 5156%(X100), DQS PI = 2
7309 11:04:12.817528 [0] MIN Duty = 5000%(X100), DQS PI = 20
7310 11:04:12.821002 [0] AVG Duty = 5078%(X100)
7311 11:04:12.821078
7312 11:04:12.824443 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7313 11:04:12.824502
7314 11:04:12.828057 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7315 11:04:12.830862 [DutyScan_Calibration_Flow] ====Done====
7316 11:04:12.830920
7317 11:04:12.834286 [DutyScan_Calibration_Flow] k_type=3
7318 11:04:12.852310
7319 11:04:12.852409 ==DQM 0 ==
7320 11:04:12.855602 Final DQM duty delay cell = 0
7321 11:04:12.858739 [0] MAX Duty = 5124%(X100), DQS PI = 24
7322 11:04:12.862207 [0] MIN Duty = 4875%(X100), DQS PI = 10
7323 11:04:12.865160 [0] AVG Duty = 4999%(X100)
7324 11:04:12.865247
7325 11:04:12.865360 ==DQM 1 ==
7326 11:04:12.868755 Final DQM duty delay cell = 0
7327 11:04:12.871969 [0] MAX Duty = 5000%(X100), DQS PI = 10
7328 11:04:12.875450 [0] MIN Duty = 4782%(X100), DQS PI = 20
7329 11:04:12.878723 [0] AVG Duty = 4891%(X100)
7330 11:04:12.878790
7331 11:04:12.882280 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7332 11:04:12.882369
7333 11:04:12.885055 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7334 11:04:12.888567 [DutyScan_Calibration_Flow] ====Done====
7335 11:04:12.888652
7336 11:04:12.891797 [DutyScan_Calibration_Flow] k_type=2
7337 11:04:12.908765
7338 11:04:12.908832 ==DQ 0 ==
7339 11:04:12.911585 Final DQ duty delay cell = -4
7340 11:04:12.915031 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7341 11:04:12.918356 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7342 11:04:12.922034 [-4] AVG Duty = 4953%(X100)
7343 11:04:12.922122
7344 11:04:12.922202 ==DQ 1 ==
7345 11:04:12.925379 Final DQ duty delay cell = 0
7346 11:04:12.928274 [0] MAX Duty = 5125%(X100), DQS PI = 2
7347 11:04:12.931564 [0] MIN Duty = 5000%(X100), DQS PI = 36
7348 11:04:12.934883 [0] AVG Duty = 5062%(X100)
7349 11:04:12.934973
7350 11:04:12.938021 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7351 11:04:12.938114
7352 11:04:12.941539 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7353 11:04:12.944975 [DutyScan_Calibration_Flow] ====Done====
7354 11:04:12.945063 ==
7355 11:04:12.948282 Dram Type= 6, Freq= 0, CH_1, rank 0
7356 11:04:12.951779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7357 11:04:12.951871 ==
7358 11:04:12.955084 [Duty_Offset_Calibration]
7359 11:04:12.955170 B0:-1 B1:1 CA:2
7360 11:04:12.955254
7361 11:04:12.957729 [DutyScan_Calibration_Flow] k_type=0
7362 11:04:12.968995
7363 11:04:12.969085 ==CLK 0==
7364 11:04:12.972392 Final CLK duty delay cell = 0
7365 11:04:12.975418 [0] MAX Duty = 5187%(X100), DQS PI = 22
7366 11:04:12.978703 [0] MIN Duty = 4969%(X100), DQS PI = 0
7367 11:04:12.982157 [0] AVG Duty = 5078%(X100)
7368 11:04:12.982249
7369 11:04:12.985274 CH1 CLK Duty spec in!! Max-Min= 218%
7370 11:04:12.988975 [DutyScan_Calibration_Flow] ====Done====
7371 11:04:12.989040
7372 11:04:12.991695 [DutyScan_Calibration_Flow] k_type=1
7373 11:04:13.008563
7374 11:04:13.008651 ==DQS 0 ==
7375 11:04:13.012109 Final DQS duty delay cell = 0
7376 11:04:13.015345 [0] MAX Duty = 5124%(X100), DQS PI = 18
7377 11:04:13.018884 [0] MIN Duty = 4907%(X100), DQS PI = 8
7378 11:04:13.021732 [0] AVG Duty = 5015%(X100)
7379 11:04:13.021798
7380 11:04:13.021852 ==DQS 1 ==
7381 11:04:13.025401 Final DQS duty delay cell = 0
7382 11:04:13.028489 [0] MAX Duty = 5093%(X100), DQS PI = 26
7383 11:04:13.031958 [0] MIN Duty = 4969%(X100), DQS PI = 56
7384 11:04:13.035106 [0] AVG Duty = 5031%(X100)
7385 11:04:13.035191
7386 11:04:13.038496 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7387 11:04:13.038559
7388 11:04:13.041659 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7389 11:04:13.044970 [DutyScan_Calibration_Flow] ====Done====
7390 11:04:13.045059
7391 11:04:13.048441 [DutyScan_Calibration_Flow] k_type=3
7392 11:04:13.065644
7393 11:04:13.065736 ==DQM 0 ==
7394 11:04:13.069115 Final DQM duty delay cell = 0
7395 11:04:13.072343 [0] MAX Duty = 5218%(X100), DQS PI = 18
7396 11:04:13.075857 [0] MIN Duty = 5031%(X100), DQS PI = 6
7397 11:04:13.075946 [0] AVG Duty = 5124%(X100)
7398 11:04:13.079148
7399 11:04:13.079237 ==DQM 1 ==
7400 11:04:13.082238 Final DQM duty delay cell = 0
7401 11:04:13.085482 [0] MAX Duty = 5156%(X100), DQS PI = 4
7402 11:04:13.088995 [0] MIN Duty = 4938%(X100), DQS PI = 34
7403 11:04:13.091936 [0] AVG Duty = 5047%(X100)
7404 11:04:13.092007
7405 11:04:13.095028 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7406 11:04:13.095113
7407 11:04:13.098779 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7408 11:04:13.101649 [DutyScan_Calibration_Flow] ====Done====
7409 11:04:13.101736
7410 11:04:13.105060 [DutyScan_Calibration_Flow] k_type=2
7411 11:04:13.122428
7412 11:04:13.122519 ==DQ 0 ==
7413 11:04:13.125967 Final DQ duty delay cell = 0
7414 11:04:13.129099 [0] MAX Duty = 5156%(X100), DQS PI = 30
7415 11:04:13.132102 [0] MIN Duty = 4906%(X100), DQS PI = 8
7416 11:04:13.132166 [0] AVG Duty = 5031%(X100)
7417 11:04:13.135701
7418 11:04:13.135786 ==DQ 1 ==
7419 11:04:13.139148 Final DQ duty delay cell = 0
7420 11:04:13.142327 [0] MAX Duty = 5156%(X100), DQS PI = 8
7421 11:04:13.145552 [0] MIN Duty = 4969%(X100), DQS PI = 32
7422 11:04:13.145641 [0] AVG Duty = 5062%(X100)
7423 11:04:13.145722
7424 11:04:13.148535 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7425 11:04:13.152020
7426 11:04:13.155252 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7427 11:04:13.158662 [DutyScan_Calibration_Flow] ====Done====
7428 11:04:13.161788 nWR fixed to 30
7429 11:04:13.161880 [ModeRegInit_LP4] CH0 RK0
7430 11:04:13.165049 [ModeRegInit_LP4] CH0 RK1
7431 11:04:13.168585 [ModeRegInit_LP4] CH1 RK0
7432 11:04:13.171738 [ModeRegInit_LP4] CH1 RK1
7433 11:04:13.171830 match AC timing 5
7434 11:04:13.178398 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7435 11:04:13.182025 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7436 11:04:13.185291 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7437 11:04:13.191821 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7438 11:04:13.195748 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7439 11:04:13.195824 [MiockJmeterHQA]
7440 11:04:13.195908
7441 11:04:13.197862 [DramcMiockJmeter] u1RxGatingPI = 0
7442 11:04:13.201855 0 : 4366, 4140
7443 11:04:13.201946 4 : 4252, 4027
7444 11:04:13.204881 8 : 4363, 4138
7445 11:04:13.204946 12 : 4368, 4140
7446 11:04:13.208287 16 : 4252, 4027
7447 11:04:13.208374 20 : 4258, 4029
7448 11:04:13.208458 24 : 4252, 4027
7449 11:04:13.211408 28 : 4252, 4027
7450 11:04:13.211508 32 : 4253, 4027
7451 11:04:13.214453 36 : 4257, 4032
7452 11:04:13.214519 40 : 4363, 4138
7453 11:04:13.218408 44 : 4253, 4026
7454 11:04:13.218506 48 : 4253, 4027
7455 11:04:13.218566 52 : 4252, 4027
7456 11:04:13.221351 56 : 4257, 4031
7457 11:04:13.221443 60 : 4253, 4027
7458 11:04:13.224811 64 : 4361, 4137
7459 11:04:13.224914 68 : 4363, 4137
7460 11:04:13.228038 72 : 4250, 4026
7461 11:04:13.228132 76 : 4252, 4030
7462 11:04:13.231554 80 : 4250, 4027
7463 11:04:13.231622 84 : 4250, 4027
7464 11:04:13.231705 88 : 4252, 4029
7465 11:04:13.234519 92 : 4360, 686
7466 11:04:13.234584 96 : 4252, 0
7467 11:04:13.237944 100 : 4250, 0
7468 11:04:13.238039 104 : 4250, 0
7469 11:04:13.238134 108 : 4250, 0
7470 11:04:13.241323 112 : 4250, 0
7471 11:04:13.241420 116 : 4250, 0
7472 11:04:13.244588 120 : 4250, 0
7473 11:04:13.244681 124 : 4253, 0
7474 11:04:13.244766 128 : 4249, 0
7475 11:04:13.247534 132 : 4250, 0
7476 11:04:13.247600 136 : 4253, 0
7477 11:04:13.251023 140 : 4250, 0
7478 11:04:13.251113 144 : 4250, 0
7479 11:04:13.251197 148 : 4360, 0
7480 11:04:13.254558 152 : 4250, 0
7481 11:04:13.254620 156 : 4250, 0
7482 11:04:13.254673 160 : 4250, 0
7483 11:04:13.257775 164 : 4250, 0
7484 11:04:13.257836 168 : 4250, 0
7485 11:04:13.260951 172 : 4250, 0
7486 11:04:13.261012 176 : 4253, 0
7487 11:04:13.261064 180 : 4250, 0
7488 11:04:13.264366 184 : 4250, 0
7489 11:04:13.264453 188 : 4253, 0
7490 11:04:13.267717 192 : 4250, 0
7491 11:04:13.267783 196 : 4361, 0
7492 11:04:13.267836 200 : 4363, 0
7493 11:04:13.270922 204 : 4361, 0
7494 11:04:13.270983 208 : 4250, 0
7495 11:04:13.274089 212 : 4255, 0
7496 11:04:13.274176 216 : 4250, 0
7497 11:04:13.274257 220 : 4250, 0
7498 11:04:13.277979 224 : 4255, 66
7499 11:04:13.278096 228 : 4255, 3240
7500 11:04:13.281848 232 : 4252, 4030
7501 11:04:13.281916 236 : 4250, 4027
7502 11:04:13.284321 240 : 4250, 4026
7503 11:04:13.284387 244 : 4363, 4137
7504 11:04:13.287685 248 : 4250, 4027
7505 11:04:13.287792 252 : 4255, 4029
7506 11:04:13.290891 256 : 4361, 4137
7507 11:04:13.290975 260 : 4250, 4027
7508 11:04:13.291059 264 : 4250, 4027
7509 11:04:13.293778 268 : 4363, 4137
7510 11:04:13.293879 272 : 4361, 4137
7511 11:04:13.297480 276 : 4250, 4027
7512 11:04:13.297571 280 : 4252, 4027
7513 11:04:13.301187 284 : 4250, 4027
7514 11:04:13.301280 288 : 4252, 4029
7515 11:04:13.303828 292 : 4249, 4027
7516 11:04:13.303929 296 : 4250, 4027
7517 11:04:13.307303 300 : 4250, 4027
7518 11:04:13.307395 304 : 4252, 4029
7519 11:04:13.310706 308 : 4360, 4138
7520 11:04:13.310801 312 : 4360, 4138
7521 11:04:13.313818 316 : 4247, 4024
7522 11:04:13.313955 320 : 4366, 4142
7523 11:04:13.314041 324 : 4250, 4027
7524 11:04:13.317124 328 : 4250, 4027
7525 11:04:13.317217 332 : 4250, 4027
7526 11:04:13.320627 336 : 4255, 3822
7527 11:04:13.320726 340 : 4250, 1790
7528 11:04:13.320815
7529 11:04:13.324069 MIOCK jitter meter ch=0
7530 11:04:13.324157
7531 11:04:13.326917 1T = (340-92) = 248 dly cells
7532 11:04:13.333929 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7533 11:04:13.334025 ==
7534 11:04:13.336890 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 11:04:13.340310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 11:04:13.340403 ==
7537 11:04:13.346957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 11:04:13.350359 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 11:04:13.353200 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 11:04:13.360045 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 11:04:13.369449 [CA 0] Center 43 (12~74) winsize 63
7542 11:04:13.372259 [CA 1] Center 42 (12~73) winsize 62
7543 11:04:13.375577 [CA 2] Center 38 (9~68) winsize 60
7544 11:04:13.379092 [CA 3] Center 38 (8~68) winsize 61
7545 11:04:13.382370 [CA 4] Center 36 (7~66) winsize 60
7546 11:04:13.385445 [CA 5] Center 35 (6~65) winsize 60
7547 11:04:13.385536
7548 11:04:13.388888 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7549 11:04:13.388979
7550 11:04:13.395510 [CATrainingPosCal] consider 1 rank data
7551 11:04:13.395598 u2DelayCellTimex100 = 262/100 ps
7552 11:04:13.402203 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7553 11:04:13.405598 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7554 11:04:13.408747 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7555 11:04:13.411969 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7556 11:04:13.415692 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7557 11:04:13.418607 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7558 11:04:13.418696
7559 11:04:13.421809 CA PerBit enable=1, Macro0, CA PI delay=35
7560 11:04:13.421887
7561 11:04:13.425433 [CBTSetCACLKResult] CA Dly = 35
7562 11:04:13.428934 CS Dly: 12 (0~43)
7563 11:04:13.431767 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 11:04:13.435459 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 11:04:13.435559 ==
7566 11:04:13.438508 Dram Type= 6, Freq= 0, CH_0, rank 1
7567 11:04:13.445113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 11:04:13.445178 ==
7569 11:04:13.448376 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7570 11:04:13.455272 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7571 11:04:13.458574 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7572 11:04:13.464926 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7573 11:04:13.472959 [CA 0] Center 42 (12~73) winsize 62
7574 11:04:13.475865 [CA 1] Center 43 (13~73) winsize 61
7575 11:04:13.479512 [CA 2] Center 37 (8~67) winsize 60
7576 11:04:13.482727 [CA 3] Center 37 (7~67) winsize 61
7577 11:04:13.485617 [CA 4] Center 36 (6~66) winsize 61
7578 11:04:13.489172 [CA 5] Center 35 (5~66) winsize 62
7579 11:04:13.489262
7580 11:04:13.492317 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7581 11:04:13.492409
7582 11:04:13.495683 [CATrainingPosCal] consider 2 rank data
7583 11:04:13.499123 u2DelayCellTimex100 = 262/100 ps
7584 11:04:13.505770 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7585 11:04:13.508862 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7586 11:04:13.512438 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7587 11:04:13.515932 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7588 11:04:13.519531 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7589 11:04:13.522227 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7590 11:04:13.522355
7591 11:04:13.525592 CA PerBit enable=1, Macro0, CA PI delay=35
7592 11:04:13.525762
7593 11:04:13.528523 [CBTSetCACLKResult] CA Dly = 35
7594 11:04:13.531886 CS Dly: 12 (0~44)
7595 11:04:13.535262 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7596 11:04:13.538293 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7597 11:04:13.538391
7598 11:04:13.541823 ----->DramcWriteLeveling(PI) begin...
7599 11:04:13.545035 ==
7600 11:04:13.545132 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 11:04:13.551382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 11:04:13.551478 ==
7603 11:04:13.554855 Write leveling (Byte 0): 36 => 36
7604 11:04:13.558276 Write leveling (Byte 1): 28 => 28
7605 11:04:13.561537 DramcWriteLeveling(PI) end<-----
7606 11:04:13.561625
7607 11:04:13.561707 ==
7608 11:04:13.565325 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 11:04:13.568362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 11:04:13.568429 ==
7611 11:04:13.571401 [Gating] SW mode calibration
7612 11:04:13.578342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7613 11:04:13.584798 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7614 11:04:13.587633 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 11:04:13.591104 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 11:04:13.597928 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 11:04:13.600774 1 4 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7618 11:04:13.604409 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7619 11:04:13.611705 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7620 11:04:13.614552 1 4 24 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
7621 11:04:13.617306 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 11:04:13.624561 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 11:04:13.627476 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 11:04:13.630972 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 11:04:13.637336 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7626 11:04:13.640820 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7627 11:04:13.643611 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7628 11:04:13.650504 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7629 11:04:13.653803 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 11:04:13.657034 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 11:04:13.663604 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 11:04:13.666830 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 11:04:13.670670 1 6 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7634 11:04:13.676557 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7635 11:04:13.680388 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7636 11:04:13.683311 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7637 11:04:13.690152 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 11:04:13.692961 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 11:04:13.696856 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 11:04:13.703560 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7641 11:04:13.706271 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7642 11:04:13.709692 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7643 11:04:13.716538 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7644 11:04:13.719870 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7645 11:04:13.723166 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 11:04:13.729806 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 11:04:13.733220 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 11:04:13.736344 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 11:04:13.742694 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 11:04:13.746013 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:04:13.749557 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:04:13.755745 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:04:13.759046 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:04:13.762646 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:04:13.768909 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:04:13.772138 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7657 11:04:13.775464 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 11:04:13.782136 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 11:04:13.782233 Total UI for P1: 0, mck2ui 16
7660 11:04:13.789200 best dqsien dly found for B0: ( 1, 9, 10)
7661 11:04:13.791839 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7662 11:04:13.795285 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7663 11:04:13.801736 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 11:04:13.801830 Total UI for P1: 0, mck2ui 16
7665 11:04:13.808319 best dqsien dly found for B1: ( 1, 9, 20)
7666 11:04:13.811701 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7667 11:04:13.815200 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7668 11:04:13.815288
7669 11:04:13.818587 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7670 11:04:13.821468 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7671 11:04:13.825012 [Gating] SW calibration Done
7672 11:04:13.825102 ==
7673 11:04:13.828371 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 11:04:13.831408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 11:04:13.831519 ==
7676 11:04:13.835163 RX Vref Scan: 0
7677 11:04:13.835251
7678 11:04:13.835333 RX Vref 0 -> 0, step: 1
7679 11:04:13.835411
7680 11:04:13.838299 RX Delay 0 -> 252, step: 8
7681 11:04:13.841520 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7682 11:04:13.848549 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7683 11:04:13.851414 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7684 11:04:13.854569 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7685 11:04:13.858139 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7686 11:04:13.860943 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7687 11:04:13.867846 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7688 11:04:13.871188 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7689 11:04:13.874443 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7690 11:04:13.877869 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7691 11:04:13.881246 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7692 11:04:13.887920 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7693 11:04:13.891001 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7694 11:04:13.894403 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7695 11:04:13.897794 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7696 11:04:13.904284 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7697 11:04:13.904361 ==
7698 11:04:13.907448 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 11:04:13.910777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 11:04:13.910852 ==
7701 11:04:13.910910 DQS Delay:
7702 11:04:13.914115 DQS0 = 0, DQS1 = 0
7703 11:04:13.914214 DQM Delay:
7704 11:04:13.917485 DQM0 = 134, DQM1 = 126
7705 11:04:13.917574 DQ Delay:
7706 11:04:13.920565 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7707 11:04:13.923998 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7708 11:04:13.926950 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7709 11:04:13.933841 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7710 11:04:13.933933
7711 11:04:13.934015
7712 11:04:13.934094 ==
7713 11:04:13.936753 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 11:04:13.940396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 11:04:13.940488 ==
7716 11:04:13.940572
7717 11:04:13.940652
7718 11:04:13.943372 TX Vref Scan disable
7719 11:04:13.943460 == TX Byte 0 ==
7720 11:04:13.949823 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7721 11:04:13.953456 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7722 11:04:13.953522 == TX Byte 1 ==
7723 11:04:13.960337 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7724 11:04:13.963640 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7725 11:04:13.963708 ==
7726 11:04:13.966595 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 11:04:13.969892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 11:04:13.969958 ==
7729 11:04:13.984214
7730 11:04:13.987706 TX Vref early break, caculate TX vref
7731 11:04:13.990672 TX Vref=16, minBit 4, minWin=22, winSum=370
7732 11:04:13.994018 TX Vref=18, minBit 1, minWin=23, winSum=383
7733 11:04:13.997458 TX Vref=20, minBit 1, minWin=23, winSum=391
7734 11:04:14.000689 TX Vref=22, minBit 3, minWin=24, winSum=401
7735 11:04:14.004388 TX Vref=24, minBit 3, minWin=24, winSum=410
7736 11:04:14.011121 TX Vref=26, minBit 4, minWin=24, winSum=415
7737 11:04:14.013867 TX Vref=28, minBit 4, minWin=24, winSum=418
7738 11:04:14.017351 TX Vref=30, minBit 1, minWin=24, winSum=410
7739 11:04:14.020871 TX Vref=32, minBit 0, minWin=24, winSum=403
7740 11:04:14.023750 TX Vref=34, minBit 4, minWin=23, winSum=391
7741 11:04:14.030093 [TxChooseVref] Worse bit 4, Min win 24, Win sum 418, Final Vref 28
7742 11:04:14.030187
7743 11:04:14.033495 Final TX Range 0 Vref 28
7744 11:04:14.033560
7745 11:04:14.033615 ==
7746 11:04:14.036789 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 11:04:14.040169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 11:04:14.040233 ==
7749 11:04:14.040286
7750 11:04:14.040336
7751 11:04:14.043458 TX Vref Scan disable
7752 11:04:14.049934 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7753 11:04:14.050025 == TX Byte 0 ==
7754 11:04:14.053361 u2DelayCellOfst[0]=14 cells (4 PI)
7755 11:04:14.056885 u2DelayCellOfst[1]=18 cells (5 PI)
7756 11:04:14.059681 u2DelayCellOfst[2]=14 cells (4 PI)
7757 11:04:14.063276 u2DelayCellOfst[3]=14 cells (4 PI)
7758 11:04:14.066897 u2DelayCellOfst[4]=11 cells (3 PI)
7759 11:04:14.069699 u2DelayCellOfst[5]=0 cells (0 PI)
7760 11:04:14.073240 u2DelayCellOfst[6]=18 cells (5 PI)
7761 11:04:14.076325 u2DelayCellOfst[7]=22 cells (6 PI)
7762 11:04:14.079904 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7763 11:04:14.082854 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7764 11:04:14.086378 == TX Byte 1 ==
7765 11:04:14.089762 u2DelayCellOfst[8]=0 cells (0 PI)
7766 11:04:14.092550 u2DelayCellOfst[9]=0 cells (0 PI)
7767 11:04:14.096003 u2DelayCellOfst[10]=3 cells (1 PI)
7768 11:04:14.099401 u2DelayCellOfst[11]=0 cells (0 PI)
7769 11:04:14.102874 u2DelayCellOfst[12]=11 cells (3 PI)
7770 11:04:14.106292 u2DelayCellOfst[13]=11 cells (3 PI)
7771 11:04:14.106378 u2DelayCellOfst[14]=14 cells (4 PI)
7772 11:04:14.109388 u2DelayCellOfst[15]=11 cells (3 PI)
7773 11:04:14.115620 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7774 11:04:14.119189 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7775 11:04:14.122537 DramC Write-DBI on
7776 11:04:14.122603 ==
7777 11:04:14.125740 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 11:04:14.129494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 11:04:14.129586 ==
7780 11:04:14.129667
7781 11:04:14.129746
7782 11:04:14.132316 TX Vref Scan disable
7783 11:04:14.132399 == TX Byte 0 ==
7784 11:04:14.139107 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7785 11:04:14.139191 == TX Byte 1 ==
7786 11:04:14.142594 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7787 11:04:14.145623 DramC Write-DBI off
7788 11:04:14.145683
7789 11:04:14.145738 [DATLAT]
7790 11:04:14.148697 Freq=1600, CH0 RK0
7791 11:04:14.148758
7792 11:04:14.148809 DATLAT Default: 0xf
7793 11:04:14.151946 0, 0xFFFF, sum = 0
7794 11:04:14.155316 1, 0xFFFF, sum = 0
7795 11:04:14.155400 2, 0xFFFF, sum = 0
7796 11:04:14.158833 3, 0xFFFF, sum = 0
7797 11:04:14.158917 4, 0xFFFF, sum = 0
7798 11:04:14.162190 5, 0xFFFF, sum = 0
7799 11:04:14.162275 6, 0xFFFF, sum = 0
7800 11:04:14.165029 7, 0xFFFF, sum = 0
7801 11:04:14.165114 8, 0xFFFF, sum = 0
7802 11:04:14.168399 9, 0xFFFF, sum = 0
7803 11:04:14.168483 10, 0xFFFF, sum = 0
7804 11:04:14.171789 11, 0xFFFF, sum = 0
7805 11:04:14.171851 12, 0xFFFF, sum = 0
7806 11:04:14.174850 13, 0xFFFF, sum = 0
7807 11:04:14.174937 14, 0x0, sum = 1
7808 11:04:14.178352 15, 0x0, sum = 2
7809 11:04:14.178413 16, 0x0, sum = 3
7810 11:04:14.181694 17, 0x0, sum = 4
7811 11:04:14.181785 best_step = 15
7812 11:04:14.181865
7813 11:04:14.181946 ==
7814 11:04:14.185074 Dram Type= 6, Freq= 0, CH_0, rank 0
7815 11:04:14.191393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7816 11:04:14.191491 ==
7817 11:04:14.191547 RX Vref Scan: 1
7818 11:04:14.191599
7819 11:04:14.194725 Set Vref Range= 24 -> 127
7820 11:04:14.194790
7821 11:04:14.198074 RX Vref 24 -> 127, step: 1
7822 11:04:14.198161
7823 11:04:14.201948 RX Delay 19 -> 252, step: 4
7824 11:04:14.202032
7825 11:04:14.204896 Set Vref, RX VrefLevel [Byte0]: 24
7826 11:04:14.207720 [Byte1]: 24
7827 11:04:14.207787
7828 11:04:14.211351 Set Vref, RX VrefLevel [Byte0]: 25
7829 11:04:14.214670 [Byte1]: 25
7830 11:04:14.214731
7831 11:04:14.218106 Set Vref, RX VrefLevel [Byte0]: 26
7832 11:04:14.221098 [Byte1]: 26
7833 11:04:14.221185
7834 11:04:14.224741 Set Vref, RX VrefLevel [Byte0]: 27
7835 11:04:14.228172 [Byte1]: 27
7836 11:04:14.231699
7837 11:04:14.231762 Set Vref, RX VrefLevel [Byte0]: 28
7838 11:04:14.235514 [Byte1]: 28
7839 11:04:14.239301
7840 11:04:14.239405 Set Vref, RX VrefLevel [Byte0]: 29
7841 11:04:14.242816 [Byte1]: 29
7842 11:04:14.247122
7843 11:04:14.247258 Set Vref, RX VrefLevel [Byte0]: 30
7844 11:04:14.250022 [Byte1]: 30
7845 11:04:14.254556
7846 11:04:14.254625 Set Vref, RX VrefLevel [Byte0]: 31
7847 11:04:14.258021 [Byte1]: 31
7848 11:04:14.262236
7849 11:04:14.262328 Set Vref, RX VrefLevel [Byte0]: 32
7850 11:04:14.265416 [Byte1]: 32
7851 11:04:14.269878
7852 11:04:14.269964 Set Vref, RX VrefLevel [Byte0]: 33
7853 11:04:14.272719 [Byte1]: 33
7854 11:04:14.277301
7855 11:04:14.277387 Set Vref, RX VrefLevel [Byte0]: 34
7856 11:04:14.280338 [Byte1]: 34
7857 11:04:14.284860
7858 11:04:14.284959 Set Vref, RX VrefLevel [Byte0]: 35
7859 11:04:14.287818 [Byte1]: 35
7860 11:04:14.292242
7861 11:04:14.292308 Set Vref, RX VrefLevel [Byte0]: 36
7862 11:04:14.295546 [Byte1]: 36
7863 11:04:14.300044
7864 11:04:14.300113 Set Vref, RX VrefLevel [Byte0]: 37
7865 11:04:14.303612 [Byte1]: 37
7866 11:04:14.307609
7867 11:04:14.307713 Set Vref, RX VrefLevel [Byte0]: 38
7868 11:04:14.310533 [Byte1]: 38
7869 11:04:14.314895
7870 11:04:14.314961 Set Vref, RX VrefLevel [Byte0]: 39
7871 11:04:14.318213 [Byte1]: 39
7872 11:04:14.322612
7873 11:04:14.322673 Set Vref, RX VrefLevel [Byte0]: 40
7874 11:04:14.326186 [Byte1]: 40
7875 11:04:14.330062
7876 11:04:14.330147 Set Vref, RX VrefLevel [Byte0]: 41
7877 11:04:14.333606 [Byte1]: 41
7878 11:04:14.337546
7879 11:04:14.337611 Set Vref, RX VrefLevel [Byte0]: 42
7880 11:04:14.341223 [Byte1]: 42
7881 11:04:14.345283
7882 11:04:14.345371 Set Vref, RX VrefLevel [Byte0]: 43
7883 11:04:14.348547 [Byte1]: 43
7884 11:04:14.353875
7885 11:04:14.353968 Set Vref, RX VrefLevel [Byte0]: 44
7886 11:04:14.356393 [Byte1]: 44
7887 11:04:14.360856
7888 11:04:14.360931 Set Vref, RX VrefLevel [Byte0]: 45
7889 11:04:14.364060 [Byte1]: 45
7890 11:04:14.368098
7891 11:04:14.368172 Set Vref, RX VrefLevel [Byte0]: 46
7892 11:04:14.371580 [Byte1]: 46
7893 11:04:14.375468
7894 11:04:14.375544 Set Vref, RX VrefLevel [Byte0]: 47
7895 11:04:14.378892 [Byte1]: 47
7896 11:04:14.383491
7897 11:04:14.383567 Set Vref, RX VrefLevel [Byte0]: 48
7898 11:04:14.386387 [Byte1]: 48
7899 11:04:14.390771
7900 11:04:14.390846 Set Vref, RX VrefLevel [Byte0]: 49
7901 11:04:14.394228 [Byte1]: 49
7902 11:04:14.398375
7903 11:04:14.398450 Set Vref, RX VrefLevel [Byte0]: 50
7904 11:04:14.401677 [Byte1]: 50
7905 11:04:14.405928
7906 11:04:14.406026 Set Vref, RX VrefLevel [Byte0]: 51
7907 11:04:14.408884 [Byte1]: 51
7908 11:04:14.413479
7909 11:04:14.413554 Set Vref, RX VrefLevel [Byte0]: 52
7910 11:04:14.416920 [Byte1]: 52
7911 11:04:14.420866
7912 11:04:14.420942 Set Vref, RX VrefLevel [Byte0]: 53
7913 11:04:14.424465 [Byte1]: 53
7914 11:04:14.428637
7915 11:04:14.428711 Set Vref, RX VrefLevel [Byte0]: 54
7916 11:04:14.431734 [Byte1]: 54
7917 11:04:14.436304
7918 11:04:14.439747 Set Vref, RX VrefLevel [Byte0]: 55
7919 11:04:14.442867 [Byte1]: 55
7920 11:04:14.442943
7921 11:04:14.446067 Set Vref, RX VrefLevel [Byte0]: 56
7922 11:04:14.449090 [Byte1]: 56
7923 11:04:14.449166
7924 11:04:14.452531 Set Vref, RX VrefLevel [Byte0]: 57
7925 11:04:14.455893 [Byte1]: 57
7926 11:04:14.455968
7927 11:04:14.459324 Set Vref, RX VrefLevel [Byte0]: 58
7928 11:04:14.462351 [Byte1]: 58
7929 11:04:14.466592
7930 11:04:14.466668 Set Vref, RX VrefLevel [Byte0]: 59
7931 11:04:14.469767 [Byte1]: 59
7932 11:04:14.474281
7933 11:04:14.474352 Set Vref, RX VrefLevel [Byte0]: 60
7934 11:04:14.477300 [Byte1]: 60
7935 11:04:14.481682
7936 11:04:14.481757 Set Vref, RX VrefLevel [Byte0]: 61
7937 11:04:14.485191 [Byte1]: 61
7938 11:04:14.489227
7939 11:04:14.489302 Set Vref, RX VrefLevel [Byte0]: 62
7940 11:04:14.492444 [Byte1]: 62
7941 11:04:14.496823
7942 11:04:14.496891 Set Vref, RX VrefLevel [Byte0]: 63
7943 11:04:14.500166 [Byte1]: 63
7944 11:04:14.504131
7945 11:04:14.504210 Set Vref, RX VrefLevel [Byte0]: 64
7946 11:04:14.507496 [Byte1]: 64
7947 11:04:14.511910
7948 11:04:14.511984 Set Vref, RX VrefLevel [Byte0]: 65
7949 11:04:14.515567 [Byte1]: 65
7950 11:04:14.519278
7951 11:04:14.519378 Set Vref, RX VrefLevel [Byte0]: 66
7952 11:04:14.522837 [Byte1]: 66
7953 11:04:14.526929
7954 11:04:14.527027 Set Vref, RX VrefLevel [Byte0]: 67
7955 11:04:14.530660 [Byte1]: 67
7956 11:04:14.535234
7957 11:04:14.535327 Set Vref, RX VrefLevel [Byte0]: 68
7958 11:04:14.537908 [Byte1]: 68
7959 11:04:14.542082
7960 11:04:14.542173 Set Vref, RX VrefLevel [Byte0]: 69
7961 11:04:14.545386 [Byte1]: 69
7962 11:04:14.549901
7963 11:04:14.549989 Set Vref, RX VrefLevel [Byte0]: 70
7964 11:04:14.553309 [Byte1]: 70
7965 11:04:14.557409
7966 11:04:14.557495 Set Vref, RX VrefLevel [Byte0]: 71
7967 11:04:14.560845 [Byte1]: 71
7968 11:04:14.564997
7969 11:04:14.565059 Set Vref, RX VrefLevel [Byte0]: 72
7970 11:04:14.571178 [Byte1]: 72
7971 11:04:14.571247
7972 11:04:14.574558 Set Vref, RX VrefLevel [Byte0]: 73
7973 11:04:14.577977 [Byte1]: 73
7974 11:04:14.578067
7975 11:04:14.581326 Set Vref, RX VrefLevel [Byte0]: 74
7976 11:04:14.584778 [Byte1]: 74
7977 11:04:14.584868
7978 11:04:14.587713 Set Vref, RX VrefLevel [Byte0]: 75
7979 11:04:14.590884 [Byte1]: 75
7980 11:04:14.595118
7981 11:04:14.595204 Set Vref, RX VrefLevel [Byte0]: 76
7982 11:04:14.598321 [Byte1]: 76
7983 11:04:14.602809
7984 11:04:14.602895 Set Vref, RX VrefLevel [Byte0]: 77
7985 11:04:14.606300 [Byte1]: 77
7986 11:04:14.610380
7987 11:04:14.610470 Set Vref, RX VrefLevel [Byte0]: 78
7988 11:04:14.613836 [Byte1]: 78
7989 11:04:14.617936
7990 11:04:14.618021 Set Vref, RX VrefLevel [Byte0]: 79
7991 11:04:14.621245 [Byte1]: 79
7992 11:04:14.625803
7993 11:04:14.625891 Set Vref, RX VrefLevel [Byte0]: 80
7994 11:04:14.628599 [Byte1]: 80
7995 11:04:14.632801
7996 11:04:14.632861 Final RX Vref Byte 0 = 68 to rank0
7997 11:04:14.636227 Final RX Vref Byte 1 = 58 to rank0
7998 11:04:14.639580 Final RX Vref Byte 0 = 68 to rank1
7999 11:04:14.643120 Final RX Vref Byte 1 = 58 to rank1==
8000 11:04:14.645999 Dram Type= 6, Freq= 0, CH_0, rank 0
8001 11:04:14.652987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 11:04:14.653074 ==
8003 11:04:14.653159 DQS Delay:
8004 11:04:14.656611 DQS0 = 0, DQS1 = 0
8005 11:04:14.656706 DQM Delay:
8006 11:04:14.656793 DQM0 = 133, DQM1 = 122
8007 11:04:14.659455 DQ Delay:
8008 11:04:14.662916 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8009 11:04:14.666220 DQ4 =132, DQ5 =120, DQ6 =140, DQ7 =142
8010 11:04:14.669482 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8011 11:04:14.673082 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =128
8012 11:04:14.673158
8013 11:04:14.673216
8014 11:04:14.673268
8015 11:04:14.676379 [DramC_TX_OE_Calibration] TA2
8016 11:04:14.679361 Original DQ_B0 (3 6) =30, OEN = 27
8017 11:04:14.682332 Original DQ_B1 (3 6) =30, OEN = 27
8018 11:04:14.685697 24, 0x0, End_B0=24 End_B1=24
8019 11:04:14.689023 25, 0x0, End_B0=25 End_B1=25
8020 11:04:14.689100 26, 0x0, End_B0=26 End_B1=26
8021 11:04:14.692423 27, 0x0, End_B0=27 End_B1=27
8022 11:04:14.695415 28, 0x0, End_B0=28 End_B1=28
8023 11:04:14.699237 29, 0x0, End_B0=29 End_B1=29
8024 11:04:14.699328 30, 0x0, End_B0=30 End_B1=30
8025 11:04:14.702215 31, 0x4141, End_B0=30 End_B1=30
8026 11:04:14.705470 Byte0 end_step=30 best_step=27
8027 11:04:14.708965 Byte1 end_step=30 best_step=27
8028 11:04:14.712293 Byte0 TX OE(2T, 0.5T) = (3, 3)
8029 11:04:14.715799 Byte1 TX OE(2T, 0.5T) = (3, 3)
8030 11:04:14.715875
8031 11:04:14.715932
8032 11:04:14.722267 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8033 11:04:14.725708 CH0 RK0: MR19=303, MR18=2112
8034 11:04:14.732448 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8035 11:04:14.732547
8036 11:04:14.735318 ----->DramcWriteLeveling(PI) begin...
8037 11:04:14.735407 ==
8038 11:04:14.738714 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 11:04:14.742120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 11:04:14.742196 ==
8041 11:04:14.745498 Write leveling (Byte 0): 37 => 37
8042 11:04:14.748522 Write leveling (Byte 1): 27 => 27
8043 11:04:14.752103 DramcWriteLeveling(PI) end<-----
8044 11:04:14.752205
8045 11:04:14.752289 ==
8046 11:04:14.755629 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 11:04:14.758248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 11:04:14.761729 ==
8049 11:04:14.761828 [Gating] SW mode calibration
8050 11:04:14.771948 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8051 11:04:14.775050 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8052 11:04:14.778401 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 11:04:14.784943 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 11:04:14.788305 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 11:04:14.791560 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8056 11:04:14.797903 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8057 11:04:14.801711 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8058 11:04:14.804680 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 11:04:14.811562 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 11:04:14.814714 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:04:14.818150 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:04:14.824721 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8063 11:04:14.827674 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
8064 11:04:14.831021 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 1)
8065 11:04:14.837885 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8066 11:04:14.841183 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 11:04:14.844174 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 11:04:14.850717 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 11:04:14.854326 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:04:14.857274 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:04:14.863991 1 6 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8072 11:04:14.867486 1 6 16 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8073 11:04:14.870433 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8074 11:04:14.877382 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8075 11:04:14.880708 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:04:14.884044 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:04:14.890435 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:04:14.893870 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8079 11:04:14.897474 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 11:04:14.903611 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 11:04:14.906922 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8082 11:04:14.910291 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:04:14.917107 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:04:14.919938 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:04:14.923665 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:04:14.929937 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:04:14.933305 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:04:14.936837 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:04:14.942969 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:04:14.946400 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:04:14.949687 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:04:14.956735 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:04:14.959619 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:04:14.962820 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:04:14.969349 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8096 11:04:14.973065 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8097 11:04:14.975967 Total UI for P1: 0, mck2ui 16
8098 11:04:14.979652 best dqsien dly found for B0: ( 1, 9, 12)
8099 11:04:14.982467 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8100 11:04:14.989261 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 11:04:14.989338 Total UI for P1: 0, mck2ui 16
8102 11:04:14.996029 best dqsien dly found for B1: ( 1, 9, 18)
8103 11:04:14.999380 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8104 11:04:15.002499 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8105 11:04:15.002575
8106 11:04:15.005776 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8107 11:04:15.009146 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8108 11:04:15.012003 [Gating] SW calibration Done
8109 11:04:15.012079 ==
8110 11:04:15.015368 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 11:04:15.019052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 11:04:15.019129 ==
8113 11:04:15.021931 RX Vref Scan: 0
8114 11:04:15.022028
8115 11:04:15.025727 RX Vref 0 -> 0, step: 1
8116 11:04:15.025802
8117 11:04:15.025884 RX Delay 0 -> 252, step: 8
8118 11:04:15.031915 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8119 11:04:15.035369 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8120 11:04:15.038929 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8121 11:04:15.041757 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8122 11:04:15.045235 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8123 11:04:15.052111 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8124 11:04:15.054937 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8125 11:04:15.058378 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8126 11:04:15.061849 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8127 11:04:15.065141 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8128 11:04:15.071312 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8129 11:04:15.075097 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8130 11:04:15.078268 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8131 11:04:15.081543 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8132 11:04:15.087943 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8133 11:04:15.090940 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8134 11:04:15.091016 ==
8135 11:04:15.094384 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 11:04:15.097879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 11:04:15.097971 ==
8138 11:04:15.101283 DQS Delay:
8139 11:04:15.101350 DQS0 = 0, DQS1 = 0
8140 11:04:15.101405 DQM Delay:
8141 11:04:15.104557 DQM0 = 133, DQM1 = 127
8142 11:04:15.104621 DQ Delay:
8143 11:04:15.107744 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8144 11:04:15.110917 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8145 11:04:15.114428 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8146 11:04:15.121040 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8147 11:04:15.121110
8148 11:04:15.121166
8149 11:04:15.121219 ==
8150 11:04:15.124343 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 11:04:15.127761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 11:04:15.127830 ==
8153 11:04:15.127886
8154 11:04:15.127942
8155 11:04:15.131354 TX Vref Scan disable
8156 11:04:15.131420 == TX Byte 0 ==
8157 11:04:15.137539 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8158 11:04:15.140990 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8159 11:04:15.144444 == TX Byte 1 ==
8160 11:04:15.147251 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8161 11:04:15.150747 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8162 11:04:15.150814 ==
8163 11:04:15.154444 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 11:04:15.157662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 11:04:15.160427 ==
8166 11:04:15.172854
8167 11:04:15.175686 TX Vref early break, caculate TX vref
8168 11:04:15.179176 TX Vref=16, minBit 0, minWin=23, winSum=379
8169 11:04:15.182745 TX Vref=18, minBit 0, minWin=23, winSum=384
8170 11:04:15.185603 TX Vref=20, minBit 5, minWin=23, winSum=395
8171 11:04:15.189305 TX Vref=22, minBit 3, minWin=24, winSum=403
8172 11:04:15.192148 TX Vref=24, minBit 3, minWin=24, winSum=409
8173 11:04:15.198553 TX Vref=26, minBit 0, minWin=25, winSum=415
8174 11:04:15.201929 TX Vref=28, minBit 0, minWin=25, winSum=412
8175 11:04:15.205176 TX Vref=30, minBit 3, minWin=24, winSum=405
8176 11:04:15.208621 TX Vref=32, minBit 0, minWin=24, winSum=395
8177 11:04:15.211959 TX Vref=34, minBit 1, minWin=23, winSum=385
8178 11:04:15.218819 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 26
8179 11:04:15.218896
8180 11:04:15.221830 Final TX Range 0 Vref 26
8181 11:04:15.221906
8182 11:04:15.221964 ==
8183 11:04:15.225209 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 11:04:15.228378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 11:04:15.228454 ==
8186 11:04:15.228571
8187 11:04:15.228704
8188 11:04:15.231760 TX Vref Scan disable
8189 11:04:15.238353 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8190 11:04:15.238446 == TX Byte 0 ==
8191 11:04:15.241788 u2DelayCellOfst[0]=11 cells (3 PI)
8192 11:04:15.244940 u2DelayCellOfst[1]=14 cells (4 PI)
8193 11:04:15.247998 u2DelayCellOfst[2]=11 cells (3 PI)
8194 11:04:15.251375 u2DelayCellOfst[3]=11 cells (3 PI)
8195 11:04:15.255114 u2DelayCellOfst[4]=7 cells (2 PI)
8196 11:04:15.257991 u2DelayCellOfst[5]=0 cells (0 PI)
8197 11:04:15.261258 u2DelayCellOfst[6]=14 cells (4 PI)
8198 11:04:15.264610 u2DelayCellOfst[7]=18 cells (5 PI)
8199 11:04:15.268200 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8200 11:04:15.271535 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8201 11:04:15.274474 == TX Byte 1 ==
8202 11:04:15.277861 u2DelayCellOfst[8]=0 cells (0 PI)
8203 11:04:15.281411 u2DelayCellOfst[9]=0 cells (0 PI)
8204 11:04:15.284416 u2DelayCellOfst[10]=7 cells (2 PI)
8205 11:04:15.288129 u2DelayCellOfst[11]=3 cells (1 PI)
8206 11:04:15.288223 u2DelayCellOfst[12]=11 cells (3 PI)
8207 11:04:15.290915 u2DelayCellOfst[13]=11 cells (3 PI)
8208 11:04:15.294268 u2DelayCellOfst[14]=14 cells (4 PI)
8209 11:04:15.297771 u2DelayCellOfst[15]=11 cells (3 PI)
8210 11:04:15.304084 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8211 11:04:15.307409 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8212 11:04:15.307536 DramC Write-DBI on
8213 11:04:15.310956 ==
8214 11:04:15.313940 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 11:04:15.317444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 11:04:15.317511 ==
8217 11:04:15.317566
8218 11:04:15.317617
8219 11:04:15.320585 TX Vref Scan disable
8220 11:04:15.320676 == TX Byte 0 ==
8221 11:04:15.327180 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8222 11:04:15.327250 == TX Byte 1 ==
8223 11:04:15.330704 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8224 11:04:15.334072 DramC Write-DBI off
8225 11:04:15.334161
8226 11:04:15.334241 [DATLAT]
8227 11:04:15.337010 Freq=1600, CH0 RK1
8228 11:04:15.337072
8229 11:04:15.337124 DATLAT Default: 0xf
8230 11:04:15.340511 0, 0xFFFF, sum = 0
8231 11:04:15.340591 1, 0xFFFF, sum = 0
8232 11:04:15.343587 2, 0xFFFF, sum = 0
8233 11:04:15.347235 3, 0xFFFF, sum = 0
8234 11:04:15.347347 4, 0xFFFF, sum = 0
8235 11:04:15.350106 5, 0xFFFF, sum = 0
8236 11:04:15.350189 6, 0xFFFF, sum = 0
8237 11:04:15.353476 7, 0xFFFF, sum = 0
8238 11:04:15.353583 8, 0xFFFF, sum = 0
8239 11:04:15.357043 9, 0xFFFF, sum = 0
8240 11:04:15.357124 10, 0xFFFF, sum = 0
8241 11:04:15.360180 11, 0xFFFF, sum = 0
8242 11:04:15.360286 12, 0xFFFF, sum = 0
8243 11:04:15.363393 13, 0xFFFF, sum = 0
8244 11:04:15.363528 14, 0x0, sum = 1
8245 11:04:15.366664 15, 0x0, sum = 2
8246 11:04:15.366743 16, 0x0, sum = 3
8247 11:04:15.370312 17, 0x0, sum = 4
8248 11:04:15.370388 best_step = 15
8249 11:04:15.370468
8250 11:04:15.370546 ==
8251 11:04:15.373779 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 11:04:15.380325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 11:04:15.380406 ==
8254 11:04:15.380489 RX Vref Scan: 0
8255 11:04:15.380589
8256 11:04:15.383218 RX Vref 0 -> 0, step: 1
8257 11:04:15.383303
8258 11:04:15.386577 RX Delay 11 -> 252, step: 4
8259 11:04:15.389764 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8260 11:04:15.393009 iDelay=191, Bit 1, Center 134 (79 ~ 190) 112
8261 11:04:15.396455 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8262 11:04:15.403179 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8263 11:04:15.406497 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8264 11:04:15.410062 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8265 11:04:15.413198 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8266 11:04:15.416126 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8267 11:04:15.422777 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8268 11:04:15.426150 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8269 11:04:15.429437 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8270 11:04:15.432366 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8271 11:04:15.439395 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8272 11:04:15.442835 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8273 11:04:15.446198 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8274 11:04:15.448961 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8275 11:04:15.449030 ==
8276 11:04:15.452474 Dram Type= 6, Freq= 0, CH_0, rank 1
8277 11:04:15.458947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 11:04:15.459023 ==
8279 11:04:15.459082 DQS Delay:
8280 11:04:15.459135 DQS0 = 0, DQS1 = 0
8281 11:04:15.462539 DQM Delay:
8282 11:04:15.462615 DQM0 = 129, DQM1 = 125
8283 11:04:15.465552 DQ Delay:
8284 11:04:15.469108 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =126
8285 11:04:15.472519 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
8286 11:04:15.475699 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8287 11:04:15.479167 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8288 11:04:15.479242
8289 11:04:15.479299
8290 11:04:15.479352
8291 11:04:15.482557 [DramC_TX_OE_Calibration] TA2
8292 11:04:15.485504 Original DQ_B0 (3 6) =30, OEN = 27
8293 11:04:15.488824 Original DQ_B1 (3 6) =30, OEN = 27
8294 11:04:15.492331 24, 0x0, End_B0=24 End_B1=24
8295 11:04:15.492421 25, 0x0, End_B0=25 End_B1=25
8296 11:04:15.495651 26, 0x0, End_B0=26 End_B1=26
8297 11:04:15.499045 27, 0x0, End_B0=27 End_B1=27
8298 11:04:15.501999 28, 0x0, End_B0=28 End_B1=28
8299 11:04:15.505507 29, 0x0, End_B0=29 End_B1=29
8300 11:04:15.505600 30, 0x0, End_B0=30 End_B1=30
8301 11:04:15.508741 31, 0x4141, End_B0=30 End_B1=30
8302 11:04:15.512029 Byte0 end_step=30 best_step=27
8303 11:04:15.515533 Byte1 end_step=30 best_step=27
8304 11:04:15.518781 Byte0 TX OE(2T, 0.5T) = (3, 3)
8305 11:04:15.521742 Byte1 TX OE(2T, 0.5T) = (3, 3)
8306 11:04:15.521829
8307 11:04:15.521909
8308 11:04:15.528644 [DQSOSCAuto] RK1, (LSB)MR18= 0x2003, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8309 11:04:15.531546 CH0 RK1: MR19=303, MR18=2003
8310 11:04:15.538199 CH0_RK1: MR19=0x303, MR18=0x2003, DQSOSC=393, MR23=63, INC=23, DEC=15
8311 11:04:15.541736 [RxdqsGatingPostProcess] freq 1600
8312 11:04:15.544789 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8313 11:04:15.548250 best DQS0 dly(2T, 0.5T) = (1, 1)
8314 11:04:15.551640 best DQS1 dly(2T, 0.5T) = (1, 1)
8315 11:04:15.554693 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8316 11:04:15.558387 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8317 11:04:15.561321 best DQS0 dly(2T, 0.5T) = (1, 1)
8318 11:04:15.564789 best DQS1 dly(2T, 0.5T) = (1, 1)
8319 11:04:15.568249 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8320 11:04:15.571240 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8321 11:04:15.574751 Pre-setting of DQS Precalculation
8322 11:04:15.578150 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8323 11:04:15.578219 ==
8324 11:04:15.581045 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 11:04:15.588791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 11:04:15.588872 ==
8327 11:04:15.591166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 11:04:15.597742 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 11:04:15.601284 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 11:04:15.607462 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 11:04:15.615118 [CA 0] Center 42 (13~72) winsize 60
8332 11:04:15.618708 [CA 1] Center 42 (13~72) winsize 60
8333 11:04:15.621664 [CA 2] Center 38 (9~67) winsize 59
8334 11:04:15.625307 [CA 3] Center 37 (8~66) winsize 59
8335 11:04:15.628541 [CA 4] Center 37 (8~67) winsize 60
8336 11:04:15.631921 [CA 5] Center 37 (8~67) winsize 60
8337 11:04:15.631996
8338 11:04:15.634807 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8339 11:04:15.634895
8340 11:04:15.638261 [CATrainingPosCal] consider 1 rank data
8341 11:04:15.641679 u2DelayCellTimex100 = 262/100 ps
8342 11:04:15.648126 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8343 11:04:15.651266 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8344 11:04:15.654562 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8345 11:04:15.657878 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8346 11:04:15.661062 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8347 11:04:15.664584 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8348 11:04:15.664653
8349 11:04:15.667727 CA PerBit enable=1, Macro0, CA PI delay=37
8350 11:04:15.667795
8351 11:04:15.671022 [CBTSetCACLKResult] CA Dly = 37
8352 11:04:15.674554 CS Dly: 9 (0~40)
8353 11:04:15.677973 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 11:04:15.680795 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 11:04:15.680860 ==
8356 11:04:15.684218 Dram Type= 6, Freq= 0, CH_1, rank 1
8357 11:04:15.690843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 11:04:15.690913 ==
8359 11:04:15.693921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8360 11:04:15.700958 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8361 11:04:15.704177 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8362 11:04:15.710815 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8363 11:04:15.718092 [CA 0] Center 42 (13~72) winsize 60
8364 11:04:15.721812 [CA 1] Center 42 (13~72) winsize 60
8365 11:04:15.725206 [CA 2] Center 38 (9~67) winsize 59
8366 11:04:15.728036 [CA 3] Center 37 (7~67) winsize 61
8367 11:04:15.731705 [CA 4] Center 37 (8~67) winsize 60
8368 11:04:15.735241 [CA 5] Center 37 (8~67) winsize 60
8369 11:04:15.735334
8370 11:04:15.738092 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8371 11:04:15.738156
8372 11:04:15.741761 [CATrainingPosCal] consider 2 rank data
8373 11:04:15.744600 u2DelayCellTimex100 = 262/100 ps
8374 11:04:15.751258 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8375 11:04:15.754589 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8376 11:04:15.757894 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8377 11:04:15.760988 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8378 11:04:15.764460 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8379 11:04:15.767913 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8380 11:04:15.767989
8381 11:04:15.770996 CA PerBit enable=1, Macro0, CA PI delay=37
8382 11:04:15.771070
8383 11:04:15.774383 [CBTSetCACLKResult] CA Dly = 37
8384 11:04:15.777760 CS Dly: 11 (0~44)
8385 11:04:15.781233 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8386 11:04:15.784692 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8387 11:04:15.784767
8388 11:04:15.787641 ----->DramcWriteLeveling(PI) begin...
8389 11:04:15.787718 ==
8390 11:04:15.791009 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 11:04:15.797607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 11:04:15.797682 ==
8393 11:04:15.801155 Write leveling (Byte 0): 24 => 24
8394 11:04:15.804098 Write leveling (Byte 1): 26 => 26
8395 11:04:15.804173 DramcWriteLeveling(PI) end<-----
8396 11:04:15.807331
8397 11:04:15.807410 ==
8398 11:04:15.810689 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 11:04:15.813998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 11:04:15.814065 ==
8401 11:04:15.817773 [Gating] SW mode calibration
8402 11:04:15.823924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8403 11:04:15.827556 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8404 11:04:15.834000 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 11:04:15.836945 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:04:15.840158 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:04:15.847061 1 4 12 | B1->B0 | 3030 3131 | 1 1 | (1 1) (1 1)
8408 11:04:15.850067 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 11:04:15.853745 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 11:04:15.860075 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 11:04:15.863393 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 11:04:15.866527 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 11:04:15.873603 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 11:04:15.876767 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8415 11:04:15.880362 1 5 12 | B1->B0 | 3030 2323 | 1 0 | (0 0) (1 0)
8416 11:04:15.886385 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8417 11:04:15.889929 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 11:04:15.896585 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 11:04:15.899403 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:04:15.902728 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:04:15.906570 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:04:15.912768 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8423 11:04:15.916032 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8424 11:04:15.919594 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 11:04:15.926182 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 11:04:15.929609 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 11:04:15.933196 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 11:04:15.939308 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 11:04:15.942740 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:04:15.946039 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:04:15.952352 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8432 11:04:15.955827 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8433 11:04:15.959101 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 11:04:15.965564 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 11:04:15.969289 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:04:15.972260 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:04:15.978816 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:04:15.982163 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:04:15.985550 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:04:15.992162 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:04:15.995135 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:04:15.998284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:04:16.004914 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:04:16.008319 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:04:16.014952 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:04:16.018379 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8447 11:04:16.021828 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8448 11:04:16.027920 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 11:04:16.027999 Total UI for P1: 0, mck2ui 16
8450 11:04:16.031295 best dqsien dly found for B0: ( 1, 9, 10)
8451 11:04:16.034730 Total UI for P1: 0, mck2ui 16
8452 11:04:16.038136 best dqsien dly found for B1: ( 1, 9, 12)
8453 11:04:16.044762 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8454 11:04:16.047997 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8455 11:04:16.048065
8456 11:04:16.051370 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8457 11:04:16.054236 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8458 11:04:16.057383 [Gating] SW calibration Done
8459 11:04:16.057452 ==
8460 11:04:16.060775 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 11:04:16.064232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 11:04:16.064296 ==
8463 11:04:16.067474 RX Vref Scan: 0
8464 11:04:16.067583
8465 11:04:16.067637 RX Vref 0 -> 0, step: 1
8466 11:04:16.067688
8467 11:04:16.070908 RX Delay 0 -> 252, step: 8
8468 11:04:16.074050 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8469 11:04:16.080581 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8470 11:04:16.083943 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8471 11:04:16.087255 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8472 11:04:16.090747 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8473 11:04:16.094149 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8474 11:04:16.100939 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8475 11:04:16.103798 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8476 11:04:16.107380 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8477 11:04:16.110712 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8478 11:04:16.113738 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8479 11:04:16.120494 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8480 11:04:16.123919 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8481 11:04:16.126731 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8482 11:04:16.130500 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8483 11:04:16.136878 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8484 11:04:16.136950 ==
8485 11:04:16.140255 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 11:04:16.143522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 11:04:16.143588 ==
8488 11:04:16.143643 DQS Delay:
8489 11:04:16.147053 DQS0 = 0, DQS1 = 0
8490 11:04:16.147114 DQM Delay:
8491 11:04:16.149979 DQM0 = 138, DQM1 = 129
8492 11:04:16.150044 DQ Delay:
8493 11:04:16.153065 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8494 11:04:16.156376 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8495 11:04:16.159820 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8496 11:04:16.163355 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8497 11:04:16.166321
8498 11:04:16.166420
8499 11:04:16.166510 ==
8500 11:04:16.169843 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 11:04:16.172723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 11:04:16.172791 ==
8503 11:04:16.172846
8504 11:04:16.172898
8505 11:04:16.176339 TX Vref Scan disable
8506 11:04:16.176417 == TX Byte 0 ==
8507 11:04:16.183080 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8508 11:04:16.186593 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8509 11:04:16.186685 == TX Byte 1 ==
8510 11:04:16.192627 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8511 11:04:16.196265 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8512 11:04:16.196332 ==
8513 11:04:16.199291 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 11:04:16.202948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 11:04:16.203045 ==
8516 11:04:16.217417
8517 11:04:16.220236 TX Vref early break, caculate TX vref
8518 11:04:16.223520 TX Vref=16, minBit 5, minWin=22, winSum=380
8519 11:04:16.227217 TX Vref=18, minBit 0, minWin=23, winSum=385
8520 11:04:16.229998 TX Vref=20, minBit 0, minWin=24, winSum=401
8521 11:04:16.233454 TX Vref=22, minBit 5, minWin=23, winSum=406
8522 11:04:16.236768 TX Vref=24, minBit 6, minWin=24, winSum=417
8523 11:04:16.243380 TX Vref=26, minBit 0, minWin=25, winSum=420
8524 11:04:16.246728 TX Vref=28, minBit 0, minWin=25, winSum=421
8525 11:04:16.250332 TX Vref=30, minBit 1, minWin=25, winSum=413
8526 11:04:16.253758 TX Vref=32, minBit 0, minWin=24, winSum=405
8527 11:04:16.256865 TX Vref=34, minBit 1, minWin=24, winSum=400
8528 11:04:16.260317 TX Vref=36, minBit 1, minWin=23, winSum=386
8529 11:04:16.266548 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8530 11:04:16.266623
8531 11:04:16.269974 Final TX Range 0 Vref 28
8532 11:04:16.270070
8533 11:04:16.270151 ==
8534 11:04:16.273446 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 11:04:16.276895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 11:04:16.276965 ==
8537 11:04:16.277021
8538 11:04:16.279940
8539 11:04:16.280004 TX Vref Scan disable
8540 11:04:16.286380 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8541 11:04:16.286450 == TX Byte 0 ==
8542 11:04:16.289918 u2DelayCellOfst[0]=18 cells (5 PI)
8543 11:04:16.293140 u2DelayCellOfst[1]=11 cells (3 PI)
8544 11:04:16.296538 u2DelayCellOfst[2]=0 cells (0 PI)
8545 11:04:16.299828 u2DelayCellOfst[3]=3 cells (1 PI)
8546 11:04:16.303073 u2DelayCellOfst[4]=7 cells (2 PI)
8547 11:04:16.306301 u2DelayCellOfst[5]=18 cells (5 PI)
8548 11:04:16.309480 u2DelayCellOfst[6]=18 cells (5 PI)
8549 11:04:16.312973 u2DelayCellOfst[7]=7 cells (2 PI)
8550 11:04:16.316357 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8551 11:04:16.319256 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8552 11:04:16.322716 == TX Byte 1 ==
8553 11:04:16.326222 u2DelayCellOfst[8]=0 cells (0 PI)
8554 11:04:16.329501 u2DelayCellOfst[9]=3 cells (1 PI)
8555 11:04:16.332184 u2DelayCellOfst[10]=11 cells (3 PI)
8556 11:04:16.335759 u2DelayCellOfst[11]=3 cells (1 PI)
8557 11:04:16.338905 u2DelayCellOfst[12]=14 cells (4 PI)
8558 11:04:16.342309 u2DelayCellOfst[13]=18 cells (5 PI)
8559 11:04:16.345536 u2DelayCellOfst[14]=18 cells (5 PI)
8560 11:04:16.345637 u2DelayCellOfst[15]=18 cells (5 PI)
8561 11:04:16.352447 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8562 11:04:16.355439 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8563 11:04:16.358991 DramC Write-DBI on
8564 11:04:16.359088 ==
8565 11:04:16.362096 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 11:04:16.365597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 11:04:16.365666 ==
8568 11:04:16.365722
8569 11:04:16.365775
8570 11:04:16.368918 TX Vref Scan disable
8571 11:04:16.369022 == TX Byte 0 ==
8572 11:04:16.375266 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8573 11:04:16.375360 == TX Byte 1 ==
8574 11:04:16.378914 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8575 11:04:16.381822 DramC Write-DBI off
8576 11:04:16.381921
8577 11:04:16.382004 [DATLAT]
8578 11:04:16.385417 Freq=1600, CH1 RK0
8579 11:04:16.385508
8580 11:04:16.385589 DATLAT Default: 0xf
8581 11:04:16.388541 0, 0xFFFF, sum = 0
8582 11:04:16.388644 1, 0xFFFF, sum = 0
8583 11:04:16.392087 2, 0xFFFF, sum = 0
8584 11:04:16.394989 3, 0xFFFF, sum = 0
8585 11:04:16.395080 4, 0xFFFF, sum = 0
8586 11:04:16.398293 5, 0xFFFF, sum = 0
8587 11:04:16.398384 6, 0xFFFF, sum = 0
8588 11:04:16.401713 7, 0xFFFF, sum = 0
8589 11:04:16.401810 8, 0xFFFF, sum = 0
8590 11:04:16.404783 9, 0xFFFF, sum = 0
8591 11:04:16.404873 10, 0xFFFF, sum = 0
8592 11:04:16.408419 11, 0xFFFF, sum = 0
8593 11:04:16.408521 12, 0xFFFF, sum = 0
8594 11:04:16.411656 13, 0xFFFF, sum = 0
8595 11:04:16.411750 14, 0x0, sum = 1
8596 11:04:16.415132 15, 0x0, sum = 2
8597 11:04:16.415223 16, 0x0, sum = 3
8598 11:04:16.418328 17, 0x0, sum = 4
8599 11:04:16.418418 best_step = 15
8600 11:04:16.418497
8601 11:04:16.418575 ==
8602 11:04:16.421615 Dram Type= 6, Freq= 0, CH_1, rank 0
8603 11:04:16.428391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8604 11:04:16.428464 ==
8605 11:04:16.428523 RX Vref Scan: 1
8606 11:04:16.428576
8607 11:04:16.431413 Set Vref Range= 24 -> 127
8608 11:04:16.431519
8609 11:04:16.434752 RX Vref 24 -> 127, step: 1
8610 11:04:16.434810
8611 11:04:16.434860 RX Delay 11 -> 252, step: 4
8612 11:04:16.437829
8613 11:04:16.437891 Set Vref, RX VrefLevel [Byte0]: 24
8614 11:04:16.441199 [Byte1]: 24
8615 11:04:16.445617
8616 11:04:16.445707 Set Vref, RX VrefLevel [Byte0]: 25
8617 11:04:16.448410 [Byte1]: 25
8618 11:04:16.452813
8619 11:04:16.452882 Set Vref, RX VrefLevel [Byte0]: 26
8620 11:04:16.456048 [Byte1]: 26
8621 11:04:16.460492
8622 11:04:16.460581 Set Vref, RX VrefLevel [Byte0]: 27
8623 11:04:16.464405 [Byte1]: 27
8624 11:04:16.468472
8625 11:04:16.468541 Set Vref, RX VrefLevel [Byte0]: 28
8626 11:04:16.471392 [Byte1]: 28
8627 11:04:16.475554
8628 11:04:16.475621 Set Vref, RX VrefLevel [Byte0]: 29
8629 11:04:16.479558 [Byte1]: 29
8630 11:04:16.483242
8631 11:04:16.483318 Set Vref, RX VrefLevel [Byte0]: 30
8632 11:04:16.486670 [Byte1]: 30
8633 11:04:16.491300
8634 11:04:16.491390 Set Vref, RX VrefLevel [Byte0]: 31
8635 11:04:16.494092 [Byte1]: 31
8636 11:04:16.498757
8637 11:04:16.498833 Set Vref, RX VrefLevel [Byte0]: 32
8638 11:04:16.501943 [Byte1]: 32
8639 11:04:16.506278
8640 11:04:16.506353 Set Vref, RX VrefLevel [Byte0]: 33
8641 11:04:16.509775 [Byte1]: 33
8642 11:04:16.513706
8643 11:04:16.513782 Set Vref, RX VrefLevel [Byte0]: 34
8644 11:04:16.520575 [Byte1]: 34
8645 11:04:16.520651
8646 11:04:16.523793 Set Vref, RX VrefLevel [Byte0]: 35
8647 11:04:16.526932 [Byte1]: 35
8648 11:04:16.527000
8649 11:04:16.530283 Set Vref, RX VrefLevel [Byte0]: 36
8650 11:04:16.533337 [Byte1]: 36
8651 11:04:16.536618
8652 11:04:16.536683 Set Vref, RX VrefLevel [Byte0]: 37
8653 11:04:16.540446 [Byte1]: 37
8654 11:04:16.544567
8655 11:04:16.544632 Set Vref, RX VrefLevel [Byte0]: 38
8656 11:04:16.547341 [Byte1]: 38
8657 11:04:16.551963
8658 11:04:16.552030 Set Vref, RX VrefLevel [Byte0]: 39
8659 11:04:16.555106 [Byte1]: 39
8660 11:04:16.559498
8661 11:04:16.559590 Set Vref, RX VrefLevel [Byte0]: 40
8662 11:04:16.562981 [Byte1]: 40
8663 11:04:16.567275
8664 11:04:16.567366 Set Vref, RX VrefLevel [Byte0]: 41
8665 11:04:16.570761 [Byte1]: 41
8666 11:04:16.574904
8667 11:04:16.574971 Set Vref, RX VrefLevel [Byte0]: 42
8668 11:04:16.578250 [Byte1]: 42
8669 11:04:16.582359
8670 11:04:16.582422 Set Vref, RX VrefLevel [Byte0]: 43
8671 11:04:16.585528 [Byte1]: 43
8672 11:04:16.590237
8673 11:04:16.590303 Set Vref, RX VrefLevel [Byte0]: 44
8674 11:04:16.593228 [Byte1]: 44
8675 11:04:16.597884
8676 11:04:16.597959 Set Vref, RX VrefLevel [Byte0]: 45
8677 11:04:16.600942 [Byte1]: 45
8678 11:04:16.605574
8679 11:04:16.605650 Set Vref, RX VrefLevel [Byte0]: 46
8680 11:04:16.608801 [Byte1]: 46
8681 11:04:16.612695
8682 11:04:16.612771 Set Vref, RX VrefLevel [Byte0]: 47
8683 11:04:16.619419 [Byte1]: 47
8684 11:04:16.619532
8685 11:04:16.622378 Set Vref, RX VrefLevel [Byte0]: 48
8686 11:04:16.625797 [Byte1]: 48
8687 11:04:16.625872
8688 11:04:16.629248 Set Vref, RX VrefLevel [Byte0]: 49
8689 11:04:16.632503 [Byte1]: 49
8690 11:04:16.635560
8691 11:04:16.635635 Set Vref, RX VrefLevel [Byte0]: 50
8692 11:04:16.638774 [Byte1]: 50
8693 11:04:16.643389
8694 11:04:16.643501 Set Vref, RX VrefLevel [Byte0]: 51
8695 11:04:16.646558 [Byte1]: 51
8696 11:04:16.651118
8697 11:04:16.651194 Set Vref, RX VrefLevel [Byte0]: 52
8698 11:04:16.653944 [Byte1]: 52
8699 11:04:16.658752
8700 11:04:16.658828 Set Vref, RX VrefLevel [Byte0]: 53
8701 11:04:16.662041 [Byte1]: 53
8702 11:04:16.665901
8703 11:04:16.665977 Set Vref, RX VrefLevel [Byte0]: 54
8704 11:04:16.669546 [Byte1]: 54
8705 11:04:16.673580
8706 11:04:16.673655 Set Vref, RX VrefLevel [Byte0]: 55
8707 11:04:16.677028 [Byte1]: 55
8708 11:04:16.681671
8709 11:04:16.681746 Set Vref, RX VrefLevel [Byte0]: 56
8710 11:04:16.684457 [Byte1]: 56
8711 11:04:16.689014
8712 11:04:16.689090 Set Vref, RX VrefLevel [Byte0]: 57
8713 11:04:16.692297 [Byte1]: 57
8714 11:04:16.696869
8715 11:04:16.696944 Set Vref, RX VrefLevel [Byte0]: 58
8716 11:04:16.700152 [Byte1]: 58
8717 11:04:16.704032
8718 11:04:16.704107 Set Vref, RX VrefLevel [Byte0]: 59
8719 11:04:16.707696 [Byte1]: 59
8720 11:04:16.711763
8721 11:04:16.711839 Set Vref, RX VrefLevel [Byte0]: 60
8722 11:04:16.718342 [Byte1]: 60
8723 11:04:16.718418
8724 11:04:16.721535 Set Vref, RX VrefLevel [Byte0]: 61
8725 11:04:16.724789 [Byte1]: 61
8726 11:04:16.724864
8727 11:04:16.728432 Set Vref, RX VrefLevel [Byte0]: 62
8728 11:04:16.731395 [Byte1]: 62
8729 11:04:16.734924
8730 11:04:16.734999 Set Vref, RX VrefLevel [Byte0]: 63
8731 11:04:16.738274 [Byte1]: 63
8732 11:04:16.742121
8733 11:04:16.742213 Set Vref, RX VrefLevel [Byte0]: 64
8734 11:04:16.745939 [Byte1]: 64
8735 11:04:16.749844
8736 11:04:16.749919 Set Vref, RX VrefLevel [Byte0]: 65
8737 11:04:16.753230 [Byte1]: 65
8738 11:04:16.757831
8739 11:04:16.757906 Set Vref, RX VrefLevel [Byte0]: 66
8740 11:04:16.760851 [Byte1]: 66
8741 11:04:16.764903
8742 11:04:16.764979 Set Vref, RX VrefLevel [Byte0]: 67
8743 11:04:16.768421 [Byte1]: 67
8744 11:04:16.772547
8745 11:04:16.772623 Set Vref, RX VrefLevel [Byte0]: 68
8746 11:04:16.775850 [Byte1]: 68
8747 11:04:16.780204
8748 11:04:16.780279 Set Vref, RX VrefLevel [Byte0]: 69
8749 11:04:16.783387 [Byte1]: 69
8750 11:04:16.787867
8751 11:04:16.787943 Set Vref, RX VrefLevel [Byte0]: 70
8752 11:04:16.791002 [Byte1]: 70
8753 11:04:16.795628
8754 11:04:16.795703 Set Vref, RX VrefLevel [Byte0]: 71
8755 11:04:16.798727 [Byte1]: 71
8756 11:04:16.803201
8757 11:04:16.803308 Set Vref, RX VrefLevel [Byte0]: 72
8758 11:04:16.806369 [Byte1]: 72
8759 11:04:16.810928
8760 11:04:16.811019 Set Vref, RX VrefLevel [Byte0]: 73
8761 11:04:16.817200 [Byte1]: 73
8762 11:04:16.817265
8763 11:04:16.820284 Final RX Vref Byte 0 = 53 to rank0
8764 11:04:16.823718 Final RX Vref Byte 1 = 56 to rank0
8765 11:04:16.826958 Final RX Vref Byte 0 = 53 to rank1
8766 11:04:16.830383 Final RX Vref Byte 1 = 56 to rank1==
8767 11:04:16.833879 Dram Type= 6, Freq= 0, CH_1, rank 0
8768 11:04:16.836887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 11:04:16.836948 ==
8770 11:04:16.837001 DQS Delay:
8771 11:04:16.840165 DQS0 = 0, DQS1 = 0
8772 11:04:16.840224 DQM Delay:
8773 11:04:16.843574 DQM0 = 134, DQM1 = 129
8774 11:04:16.843659 DQ Delay:
8775 11:04:16.847032 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8776 11:04:16.850271 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8777 11:04:16.853474 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =118
8778 11:04:16.856573 DQ12 =134, DQ13 =138, DQ14 =138, DQ15 =138
8779 11:04:16.859769
8780 11:04:16.859857
8781 11:04:16.859944
8782 11:04:16.860023 [DramC_TX_OE_Calibration] TA2
8783 11:04:16.863538 Original DQ_B0 (3 6) =30, OEN = 27
8784 11:04:16.866778 Original DQ_B1 (3 6) =30, OEN = 27
8785 11:04:16.870064 24, 0x0, End_B0=24 End_B1=24
8786 11:04:16.873074 25, 0x0, End_B0=25 End_B1=25
8787 11:04:16.876576 26, 0x0, End_B0=26 End_B1=26
8788 11:04:16.876644 27, 0x0, End_B0=27 End_B1=27
8789 11:04:16.879838 28, 0x0, End_B0=28 End_B1=28
8790 11:04:16.882962 29, 0x0, End_B0=29 End_B1=29
8791 11:04:16.886293 30, 0x0, End_B0=30 End_B1=30
8792 11:04:16.889835 31, 0x5151, End_B0=30 End_B1=30
8793 11:04:16.893174 Byte0 end_step=30 best_step=27
8794 11:04:16.893281 Byte1 end_step=30 best_step=27
8795 11:04:16.896353 Byte0 TX OE(2T, 0.5T) = (3, 3)
8796 11:04:16.899376 Byte1 TX OE(2T, 0.5T) = (3, 3)
8797 11:04:16.899498
8798 11:04:16.899555
8799 11:04:16.909473 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
8800 11:04:16.909546 CH1 RK0: MR19=303, MR18=1C11
8801 11:04:16.915951 CH1_RK0: MR19=0x303, MR18=0x1C11, DQSOSC=395, MR23=63, INC=23, DEC=15
8802 11:04:16.916021
8803 11:04:16.919391 ----->DramcWriteLeveling(PI) begin...
8804 11:04:16.919535 ==
8805 11:04:16.922840 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 11:04:16.929405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 11:04:16.929500 ==
8808 11:04:16.932845 Write leveling (Byte 0): 25 => 25
8809 11:04:16.935720 Write leveling (Byte 1): 27 => 27
8810 11:04:16.935806 DramcWriteLeveling(PI) end<-----
8811 11:04:16.939202
8812 11:04:16.939291 ==
8813 11:04:16.942616 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 11:04:16.946323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 11:04:16.946427 ==
8816 11:04:16.948862 [Gating] SW mode calibration
8817 11:04:16.955623 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8818 11:04:16.958738 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8819 11:04:16.965516 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 11:04:16.968974 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 11:04:16.972343 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8822 11:04:16.978856 1 4 12 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8823 11:04:16.982077 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8824 11:04:16.985463 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 11:04:16.992411 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 11:04:16.995323 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 11:04:16.998661 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 11:04:17.005436 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 11:04:17.008457 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8830 11:04:17.011913 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8831 11:04:17.018776 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 11:04:17.021861 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:04:17.025103 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:04:17.031580 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:04:17.035086 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:04:17.038434 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 11:04:17.044780 1 6 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8838 11:04:17.048538 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8839 11:04:17.051363 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 11:04:17.057871 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 11:04:17.061599 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:04:17.065073 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:04:17.071393 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 11:04:17.074818 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 11:04:17.078145 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8846 11:04:17.084724 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8847 11:04:17.088054 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8848 11:04:17.091327 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:04:17.097472 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:04:17.100949 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:04:17.104386 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:04:17.111100 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:04:17.114031 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:04:17.117507 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:04:17.124404 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:04:17.127227 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:04:17.130538 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:04:17.137569 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:04:17.140627 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:04:17.144104 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:04:17.150486 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8862 11:04:17.154026 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8863 11:04:17.157365 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 11:04:17.160729 Total UI for P1: 0, mck2ui 16
8865 11:04:17.163557 best dqsien dly found for B0: ( 1, 9, 10)
8866 11:04:17.167040 Total UI for P1: 0, mck2ui 16
8867 11:04:17.170409 best dqsien dly found for B1: ( 1, 9, 10)
8868 11:04:17.173678 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8869 11:04:17.177000 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8870 11:04:17.177076
8871 11:04:17.183538 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8872 11:04:17.187010 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8873 11:04:17.190310 [Gating] SW calibration Done
8874 11:04:17.190382 ==
8875 11:04:17.193327 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 11:04:17.196958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 11:04:17.197031 ==
8878 11:04:17.197087 RX Vref Scan: 0
8879 11:04:17.200086
8880 11:04:17.200157 RX Vref 0 -> 0, step: 1
8881 11:04:17.200213
8882 11:04:17.203036 RX Delay 0 -> 252, step: 8
8883 11:04:17.206729 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8884 11:04:17.209821 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8885 11:04:17.216260 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8886 11:04:17.220037 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8887 11:04:17.222893 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8888 11:04:17.226603 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8889 11:04:17.230237 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8890 11:04:17.236300 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8891 11:04:17.239758 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8892 11:04:17.243010 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8893 11:04:17.246144 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8894 11:04:17.249680 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8895 11:04:17.255885 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8896 11:04:17.259259 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8897 11:04:17.262672 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8898 11:04:17.266021 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8899 11:04:17.266089 ==
8900 11:04:17.269538 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 11:04:17.275771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 11:04:17.275840 ==
8903 11:04:17.275897 DQS Delay:
8904 11:04:17.279098 DQS0 = 0, DQS1 = 0
8905 11:04:17.279192 DQM Delay:
8906 11:04:17.282238 DQM0 = 136, DQM1 = 129
8907 11:04:17.282333 DQ Delay:
8908 11:04:17.285911 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8909 11:04:17.288896 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8910 11:04:17.292187 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8911 11:04:17.295557 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8912 11:04:17.295623
8913 11:04:17.295678
8914 11:04:17.295730 ==
8915 11:04:17.299076 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 11:04:17.305219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 11:04:17.305293 ==
8918 11:04:17.305377
8919 11:04:17.305463
8920 11:04:17.305540 TX Vref Scan disable
8921 11:04:17.309159 == TX Byte 0 ==
8922 11:04:17.312649 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8923 11:04:17.319007 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8924 11:04:17.319084 == TX Byte 1 ==
8925 11:04:17.321945 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8926 11:04:17.328988 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 11:04:17.329081 ==
8928 11:04:17.331866 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 11:04:17.335038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 11:04:17.335133 ==
8931 11:04:17.347946
8932 11:04:17.351207 TX Vref early break, caculate TX vref
8933 11:04:17.354806 TX Vref=16, minBit 0, minWin=23, winSum=388
8934 11:04:17.357885 TX Vref=18, minBit 0, minWin=24, winSum=399
8935 11:04:17.360947 TX Vref=20, minBit 8, minWin=24, winSum=408
8936 11:04:17.364547 TX Vref=22, minBit 8, minWin=24, winSum=410
8937 11:04:17.367916 TX Vref=24, minBit 0, minWin=26, winSum=421
8938 11:04:17.374181 TX Vref=26, minBit 0, minWin=26, winSum=429
8939 11:04:17.377569 TX Vref=28, minBit 0, minWin=25, winSum=428
8940 11:04:17.381044 TX Vref=30, minBit 0, minWin=25, winSum=420
8941 11:04:17.384408 TX Vref=32, minBit 0, minWin=24, winSum=415
8942 11:04:17.387734 TX Vref=34, minBit 0, minWin=23, winSum=401
8943 11:04:17.394264 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8944 11:04:17.394340
8945 11:04:17.397744 Final TX Range 0 Vref 26
8946 11:04:17.397820
8947 11:04:17.397878 ==
8948 11:04:17.400588 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 11:04:17.404200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 11:04:17.404273 ==
8951 11:04:17.404333
8952 11:04:17.404386
8953 11:04:17.407600 TX Vref Scan disable
8954 11:04:17.413921 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8955 11:04:17.413994 == TX Byte 0 ==
8956 11:04:17.417361 u2DelayCellOfst[0]=18 cells (5 PI)
8957 11:04:17.420641 u2DelayCellOfst[1]=11 cells (3 PI)
8958 11:04:17.424006 u2DelayCellOfst[2]=0 cells (0 PI)
8959 11:04:17.427339 u2DelayCellOfst[3]=7 cells (2 PI)
8960 11:04:17.430353 u2DelayCellOfst[4]=7 cells (2 PI)
8961 11:04:17.434035 u2DelayCellOfst[5]=22 cells (6 PI)
8962 11:04:17.436980 u2DelayCellOfst[6]=22 cells (6 PI)
8963 11:04:17.440317 u2DelayCellOfst[7]=7 cells (2 PI)
8964 11:04:17.443641 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8965 11:04:17.447208 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8966 11:04:17.450587 == TX Byte 1 ==
8967 11:04:17.453443 u2DelayCellOfst[8]=0 cells (0 PI)
8968 11:04:17.453508 u2DelayCellOfst[9]=7 cells (2 PI)
8969 11:04:17.456983 u2DelayCellOfst[10]=14 cells (4 PI)
8970 11:04:17.460343 u2DelayCellOfst[11]=3 cells (1 PI)
8971 11:04:17.463413 u2DelayCellOfst[12]=18 cells (5 PI)
8972 11:04:17.466765 u2DelayCellOfst[13]=18 cells (5 PI)
8973 11:04:17.469989 u2DelayCellOfst[14]=18 cells (5 PI)
8974 11:04:17.473343 u2DelayCellOfst[15]=18 cells (5 PI)
8975 11:04:17.480126 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8976 11:04:17.483121 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8977 11:04:17.483192 DramC Write-DBI on
8978 11:04:17.483248 ==
8979 11:04:17.486478 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 11:04:17.493559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 11:04:17.493636 ==
8982 11:04:17.493695
8983 11:04:17.493748
8984 11:04:17.493799 TX Vref Scan disable
8985 11:04:17.497680 == TX Byte 0 ==
8986 11:04:17.500820 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8987 11:04:17.504073 == TX Byte 1 ==
8988 11:04:17.507404 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8989 11:04:17.510289 DramC Write-DBI off
8990 11:04:17.510351
8991 11:04:17.510405 [DATLAT]
8992 11:04:17.510462 Freq=1600, CH1 RK1
8993 11:04:17.510513
8994 11:04:17.513802 DATLAT Default: 0xf
8995 11:04:17.517119 0, 0xFFFF, sum = 0
8996 11:04:17.517181 1, 0xFFFF, sum = 0
8997 11:04:17.520521 2, 0xFFFF, sum = 0
8998 11:04:17.520592 3, 0xFFFF, sum = 0
8999 11:04:17.523416 4, 0xFFFF, sum = 0
9000 11:04:17.523491 5, 0xFFFF, sum = 0
9001 11:04:17.527282 6, 0xFFFF, sum = 0
9002 11:04:17.527391 7, 0xFFFF, sum = 0
9003 11:04:17.530118 8, 0xFFFF, sum = 0
9004 11:04:17.530224 9, 0xFFFF, sum = 0
9005 11:04:17.533613 10, 0xFFFF, sum = 0
9006 11:04:17.533685 11, 0xFFFF, sum = 0
9007 11:04:17.536621 12, 0xFFFF, sum = 0
9008 11:04:17.536694 13, 0xFFFF, sum = 0
9009 11:04:17.539953 14, 0x0, sum = 1
9010 11:04:17.540018 15, 0x0, sum = 2
9011 11:04:17.543302 16, 0x0, sum = 3
9012 11:04:17.543400 17, 0x0, sum = 4
9013 11:04:17.546862 best_step = 15
9014 11:04:17.546961
9015 11:04:17.547054 ==
9016 11:04:17.550406 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 11:04:17.553646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 11:04:17.553724 ==
9019 11:04:17.556493 RX Vref Scan: 0
9020 11:04:17.556560
9021 11:04:17.556615 RX Vref 0 -> 0, step: 1
9022 11:04:17.556675
9023 11:04:17.560024 RX Delay 11 -> 252, step: 4
9024 11:04:17.566223 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9025 11:04:17.569679 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9026 11:04:17.573001 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9027 11:04:17.576277 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9028 11:04:17.579477 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9029 11:04:17.586166 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9030 11:04:17.589429 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9031 11:04:17.592809 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9032 11:04:17.596100 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9033 11:04:17.599637 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9034 11:04:17.605800 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9035 11:04:17.609571 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9036 11:04:17.612549 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9037 11:04:17.616041 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9038 11:04:17.622444 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9039 11:04:17.625583 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9040 11:04:17.625660 ==
9041 11:04:17.629124 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 11:04:17.632479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 11:04:17.632549 ==
9044 11:04:17.636015 DQS Delay:
9045 11:04:17.636094 DQS0 = 0, DQS1 = 0
9046 11:04:17.636152 DQM Delay:
9047 11:04:17.639132 DQM0 = 134, DQM1 = 126
9048 11:04:17.639251 DQ Delay:
9049 11:04:17.642075 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9050 11:04:17.645646 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9051 11:04:17.649119 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9052 11:04:17.655795 DQ12 =138, DQ13 =134, DQ14 =134, DQ15 =138
9053 11:04:17.655864
9054 11:04:17.655933
9055 11:04:17.655986
9056 11:04:17.658820 [DramC_TX_OE_Calibration] TA2
9057 11:04:17.658972 Original DQ_B0 (3 6) =30, OEN = 27
9058 11:04:17.661963 Original DQ_B1 (3 6) =30, OEN = 27
9059 11:04:17.665566 24, 0x0, End_B0=24 End_B1=24
9060 11:04:17.668716 25, 0x0, End_B0=25 End_B1=25
9061 11:04:17.672023 26, 0x0, End_B0=26 End_B1=26
9062 11:04:17.675686 27, 0x0, End_B0=27 End_B1=27
9063 11:04:17.675763 28, 0x0, End_B0=28 End_B1=28
9064 11:04:17.678493 29, 0x0, End_B0=29 End_B1=29
9065 11:04:17.681816 30, 0x0, End_B0=30 End_B1=30
9066 11:04:17.685450 31, 0x4141, End_B0=30 End_B1=30
9067 11:04:17.689015 Byte0 end_step=30 best_step=27
9068 11:04:17.689092 Byte1 end_step=30 best_step=27
9069 11:04:17.691929 Byte0 TX OE(2T, 0.5T) = (3, 3)
9070 11:04:17.695195 Byte1 TX OE(2T, 0.5T) = (3, 3)
9071 11:04:17.695307
9072 11:04:17.695396
9073 11:04:17.705213 [DQSOSCAuto] RK1, (LSB)MR18= 0x100b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
9074 11:04:17.705286 CH1 RK1: MR19=303, MR18=100B
9075 11:04:17.711602 CH1_RK1: MR19=0x303, MR18=0x100B, DQSOSC=401, MR23=63, INC=22, DEC=15
9076 11:04:17.714998 [RxdqsGatingPostProcess] freq 1600
9077 11:04:17.721485 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9078 11:04:17.725387 best DQS0 dly(2T, 0.5T) = (1, 1)
9079 11:04:17.728652 best DQS1 dly(2T, 0.5T) = (1, 1)
9080 11:04:17.731583 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9081 11:04:17.734826 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9082 11:04:17.738254 best DQS0 dly(2T, 0.5T) = (1, 1)
9083 11:04:17.738319 best DQS1 dly(2T, 0.5T) = (1, 1)
9084 11:04:17.741265 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9085 11:04:17.744646 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9086 11:04:17.748017 Pre-setting of DQS Precalculation
9087 11:04:17.754661 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9088 11:04:17.761743 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9089 11:04:17.768098 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9090 11:04:17.768171
9091 11:04:17.768236
9092 11:04:17.771334 [Calibration Summary] 3200 Mbps
9093 11:04:17.774256 CH 0, Rank 0
9094 11:04:17.774322 SW Impedance : PASS
9095 11:04:17.777562 DUTY Scan : NO K
9096 11:04:17.781205 ZQ Calibration : PASS
9097 11:04:17.781298 Jitter Meter : NO K
9098 11:04:17.784554 CBT Training : PASS
9099 11:04:17.784622 Write leveling : PASS
9100 11:04:17.787415 RX DQS gating : PASS
9101 11:04:17.790599 RX DQ/DQS(RDDQC) : PASS
9102 11:04:17.790675 TX DQ/DQS : PASS
9103 11:04:17.794364 RX DATLAT : PASS
9104 11:04:17.797482 RX DQ/DQS(Engine): PASS
9105 11:04:17.797582 TX OE : PASS
9106 11:04:17.800930 All Pass.
9107 11:04:17.801026
9108 11:04:17.801119 CH 0, Rank 1
9109 11:04:17.804076 SW Impedance : PASS
9110 11:04:17.804147 DUTY Scan : NO K
9111 11:04:17.807273 ZQ Calibration : PASS
9112 11:04:17.810600 Jitter Meter : NO K
9113 11:04:17.810674 CBT Training : PASS
9114 11:04:17.814322 Write leveling : PASS
9115 11:04:17.817304 RX DQS gating : PASS
9116 11:04:17.817372 RX DQ/DQS(RDDQC) : PASS
9117 11:04:17.820612 TX DQ/DQS : PASS
9118 11:04:17.823982 RX DATLAT : PASS
9119 11:04:17.824050 RX DQ/DQS(Engine): PASS
9120 11:04:17.827213 TX OE : PASS
9121 11:04:17.827303 All Pass.
9122 11:04:17.827392
9123 11:04:17.830807 CH 1, Rank 0
9124 11:04:17.830879 SW Impedance : PASS
9125 11:04:17.833842 DUTY Scan : NO K
9126 11:04:17.837452 ZQ Calibration : PASS
9127 11:04:17.837519 Jitter Meter : NO K
9128 11:04:17.840756 CBT Training : PASS
9129 11:04:17.844208 Write leveling : PASS
9130 11:04:17.844283 RX DQS gating : PASS
9131 11:04:17.847316 RX DQ/DQS(RDDQC) : PASS
9132 11:04:17.847411 TX DQ/DQS : PASS
9133 11:04:17.850070 RX DATLAT : PASS
9134 11:04:17.853949 RX DQ/DQS(Engine): PASS
9135 11:04:17.854020 TX OE : PASS
9136 11:04:17.856753 All Pass.
9137 11:04:17.856815
9138 11:04:17.856869 CH 1, Rank 1
9139 11:04:17.860161 SW Impedance : PASS
9140 11:04:17.860239 DUTY Scan : NO K
9141 11:04:17.863852 ZQ Calibration : PASS
9142 11:04:17.866783 Jitter Meter : NO K
9143 11:04:17.866870 CBT Training : PASS
9144 11:04:17.870491 Write leveling : PASS
9145 11:04:17.873640 RX DQS gating : PASS
9146 11:04:17.873731 RX DQ/DQS(RDDQC) : PASS
9147 11:04:17.876980 TX DQ/DQS : PASS
9148 11:04:17.880307 RX DATLAT : PASS
9149 11:04:17.880413 RX DQ/DQS(Engine): PASS
9150 11:04:17.883150 TX OE : PASS
9151 11:04:17.883240 All Pass.
9152 11:04:17.883326
9153 11:04:17.886446 DramC Write-DBI on
9154 11:04:17.889834 PER_BANK_REFRESH: Hybrid Mode
9155 11:04:17.889915 TX_TRACKING: ON
9156 11:04:17.899789 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9157 11:04:17.906542 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9158 11:04:17.912943 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9159 11:04:17.919849 [FAST_K] Save calibration result to emmc
9160 11:04:17.919921 sync common calibartion params.
9161 11:04:17.923522 sync cbt_mode0:1, 1:1
9162 11:04:17.926087 dram_init: ddr_geometry: 2
9163 11:04:17.926155 dram_init: ddr_geometry: 2
9164 11:04:17.929574 dram_init: ddr_geometry: 2
9165 11:04:17.933362 0:dram_rank_size:100000000
9166 11:04:17.936014 1:dram_rank_size:100000000
9167 11:04:17.939717 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9168 11:04:17.943003 DFS_SHUFFLE_HW_MODE: ON
9169 11:04:17.946268 dramc_set_vcore_voltage set vcore to 725000
9170 11:04:17.949513 Read voltage for 1600, 0
9171 11:04:17.949591 Vio18 = 0
9172 11:04:17.952680 Vcore = 725000
9173 11:04:17.952748 Vdram = 0
9174 11:04:17.952802 Vddq = 0
9175 11:04:17.952853 Vmddr = 0
9176 11:04:17.956203 switch to 3200 Mbps bootup
9177 11:04:17.959510 [DramcRunTimeConfig]
9178 11:04:17.959620 PHYPLL
9179 11:04:17.962388 DPM_CONTROL_AFTERK: ON
9180 11:04:17.962485 PER_BANK_REFRESH: ON
9181 11:04:17.965952 REFRESH_OVERHEAD_REDUCTION: ON
9182 11:04:17.969268 CMD_PICG_NEW_MODE: OFF
9183 11:04:17.969338 XRTWTW_NEW_MODE: ON
9184 11:04:17.972769 XRTRTR_NEW_MODE: ON
9185 11:04:17.972836 TX_TRACKING: ON
9186 11:04:17.976070 RDSEL_TRACKING: OFF
9187 11:04:17.976167 DQS Precalculation for DVFS: ON
9188 11:04:17.979376 RX_TRACKING: OFF
9189 11:04:17.979519 HW_GATING DBG: ON
9190 11:04:17.982427 ZQCS_ENABLE_LP4: ON
9191 11:04:17.985992 RX_PICG_NEW_MODE: ON
9192 11:04:17.986085 TX_PICG_NEW_MODE: ON
9193 11:04:17.988953 ENABLE_RX_DCM_DPHY: ON
9194 11:04:17.992435 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9195 11:04:17.992508 DUMMY_READ_FOR_TRACKING: OFF
9196 11:04:17.995797 !!! SPM_CONTROL_AFTERK: OFF
9197 11:04:17.999070 !!! SPM could not control APHY
9198 11:04:18.002477 IMPEDANCE_TRACKING: ON
9199 11:04:18.002569 TEMP_SENSOR: ON
9200 11:04:18.005729 HW_SAVE_FOR_SR: OFF
9201 11:04:18.009235 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9202 11:04:18.012551 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9203 11:04:18.012622 Read ODT Tracking: ON
9204 11:04:18.015633 Refresh Rate DeBounce: ON
9205 11:04:18.018799 DFS_NO_QUEUE_FLUSH: ON
9206 11:04:18.022825 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9207 11:04:18.022899 ENABLE_DFS_RUNTIME_MRW: OFF
9208 11:04:18.025706 DDR_RESERVE_NEW_MODE: ON
9209 11:04:18.028849 MR_CBT_SWITCH_FREQ: ON
9210 11:04:18.028992 =========================
9211 11:04:18.048936 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9212 11:04:18.052291 dram_init: ddr_geometry: 2
9213 11:04:18.070726 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9214 11:04:18.073498 dram_init: dram init end (result: 0)
9215 11:04:18.080054 DRAM-K: Full calibration passed in 24586 msecs
9216 11:04:18.083857 MRC: failed to locate region type 0.
9217 11:04:18.083923 DRAM rank0 size:0x100000000,
9218 11:04:18.087007 DRAM rank1 size=0x100000000
9219 11:04:18.096657 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9220 11:04:18.103547 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9221 11:04:18.110457 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9222 11:04:18.119855 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9223 11:04:18.119964 DRAM rank0 size:0x100000000,
9224 11:04:18.123112 DRAM rank1 size=0x100000000
9225 11:04:18.123204 CBMEM:
9226 11:04:18.126529 IMD: root @ 0xfffff000 254 entries.
9227 11:04:18.129900 IMD: root @ 0xffffec00 62 entries.
9228 11:04:18.132936 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9229 11:04:18.140021 WARNING: RO_VPD is uninitialized or empty.
9230 11:04:18.142926 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9231 11:04:18.150416 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9232 11:04:18.163110 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9233 11:04:18.174908 BS: romstage times (exec / console): total (unknown) / 24086 ms
9234 11:04:18.174983
9235 11:04:18.175041
9236 11:04:18.184384 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9237 11:04:18.187913 ARM64: Exception handlers installed.
9238 11:04:18.191369 ARM64: Testing exception
9239 11:04:18.194351 ARM64: Done test exception
9240 11:04:18.194412 Enumerating buses...
9241 11:04:18.197871 Show all devs... Before device enumeration.
9242 11:04:18.200823 Root Device: enabled 1
9243 11:04:18.204214 CPU_CLUSTER: 0: enabled 1
9244 11:04:18.204274 CPU: 00: enabled 1
9245 11:04:18.207338 Compare with tree...
9246 11:04:18.207421 Root Device: enabled 1
9247 11:04:18.211015 CPU_CLUSTER: 0: enabled 1
9248 11:04:18.213805 CPU: 00: enabled 1
9249 11:04:18.213895 Root Device scanning...
9250 11:04:18.217252 scan_static_bus for Root Device
9251 11:04:18.220610 CPU_CLUSTER: 0 enabled
9252 11:04:18.224061 scan_static_bus for Root Device done
9253 11:04:18.227088 scan_bus: bus Root Device finished in 8 msecs
9254 11:04:18.227153 done
9255 11:04:18.234307 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9256 11:04:18.237235 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9257 11:04:18.243549 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9258 11:04:18.249991 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9259 11:04:18.250119 Allocating resources...
9260 11:04:18.253375 Reading resources...
9261 11:04:18.256948 Root Device read_resources bus 0 link: 0
9262 11:04:18.259787 DRAM rank0 size:0x100000000,
9263 11:04:18.259874 DRAM rank1 size=0x100000000
9264 11:04:18.266792 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9265 11:04:18.266858 CPU: 00 missing read_resources
9266 11:04:18.273374 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9267 11:04:18.276651 Root Device read_resources bus 0 link: 0 done
9268 11:04:18.280012 Done reading resources.
9269 11:04:18.283093 Show resources in subtree (Root Device)...After reading.
9270 11:04:18.286608 Root Device child on link 0 CPU_CLUSTER: 0
9271 11:04:18.289507 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 11:04:18.299624 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 11:04:18.299704 CPU: 00
9274 11:04:18.305934 Root Device assign_resources, bus 0 link: 0
9275 11:04:18.309293 CPU_CLUSTER: 0 missing set_resources
9276 11:04:18.312710 Root Device assign_resources, bus 0 link: 0 done
9277 11:04:18.316222 Done setting resources.
9278 11:04:18.319248 Show resources in subtree (Root Device)...After assigning values.
9279 11:04:18.322432 Root Device child on link 0 CPU_CLUSTER: 0
9280 11:04:18.329387 CPU_CLUSTER: 0 child on link 0 CPU: 00
9281 11:04:18.335942 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9282 11:04:18.339152 CPU: 00
9283 11:04:18.339230 Done allocating resources.
9284 11:04:18.345962 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9285 11:04:18.346040 Enabling resources...
9286 11:04:18.348889 done.
9287 11:04:18.352161 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9288 11:04:18.355363 Initializing devices...
9289 11:04:18.355467 Root Device init
9290 11:04:18.358944 init hardware done!
9291 11:04:18.359039 0x00000018: ctrlr->caps
9292 11:04:18.362255 52.000 MHz: ctrlr->f_max
9293 11:04:18.365604 0.400 MHz: ctrlr->f_min
9294 11:04:18.368973 0x40ff8080: ctrlr->voltages
9295 11:04:18.369070 sclk: 390625
9296 11:04:18.369155 Bus Width = 1
9297 11:04:18.372300 sclk: 390625
9298 11:04:18.372390 Bus Width = 1
9299 11:04:18.375227 Early init status = 3
9300 11:04:18.378802 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9301 11:04:18.382799 in-header: 03 fc 00 00 01 00 00 00
9302 11:04:18.386497 in-data: 00
9303 11:04:18.389299 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9304 11:04:18.395294 in-header: 03 fd 00 00 00 00 00 00
9305 11:04:18.398419 in-data:
9306 11:04:18.401343 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9307 11:04:18.405958 in-header: 03 fc 00 00 01 00 00 00
9308 11:04:18.409170 in-data: 00
9309 11:04:18.412561 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9310 11:04:18.418043 in-header: 03 fd 00 00 00 00 00 00
9311 11:04:18.421844 in-data:
9312 11:04:18.424770 [SSUSB] Setting up USB HOST controller...
9313 11:04:18.428648 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9314 11:04:18.431255 [SSUSB] phy power-on done.
9315 11:04:18.435019 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9316 11:04:18.441416 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9317 11:04:18.444739 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9318 11:04:18.451265 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9319 11:04:18.457760 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9320 11:04:18.464382 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9321 11:04:18.471086 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9322 11:04:18.477431 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9323 11:04:18.480933 SPM: binary array size = 0x9dc
9324 11:04:18.484111 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9325 11:04:18.490588 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9326 11:04:18.497064 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9327 11:04:18.504026 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9328 11:04:18.506987 configure_display: Starting display init
9329 11:04:18.541609 anx7625_power_on_init: Init interface.
9330 11:04:18.544806 anx7625_disable_pd_protocol: Disabled PD feature.
9331 11:04:18.547866 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9332 11:04:18.575874 anx7625_start_dp_work: Secure OCM version=00
9333 11:04:18.579275 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9334 11:04:18.593985 sp_tx_get_edid_block: EDID Block = 1
9335 11:04:18.696495 Extracted contents:
9336 11:04:18.700081 header: 00 ff ff ff ff ff ff 00
9337 11:04:18.703509 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9338 11:04:18.706364 version: 01 04
9339 11:04:18.709848 basic params: 95 1f 11 78 0a
9340 11:04:18.713213 chroma info: 76 90 94 55 54 90 27 21 50 54
9341 11:04:18.716257 established: 00 00 00
9342 11:04:18.723316 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9343 11:04:18.726329 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9344 11:04:18.732743 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9345 11:04:18.739764 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9346 11:04:18.746164 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9347 11:04:18.749585 extensions: 00
9348 11:04:18.749687 checksum: fb
9349 11:04:18.749774
9350 11:04:18.755738 Manufacturer: IVO Model 57d Serial Number 0
9351 11:04:18.755837 Made week 0 of 2020
9352 11:04:18.759997 EDID version: 1.4
9353 11:04:18.760071 Digital display
9354 11:04:18.762617 6 bits per primary color channel
9355 11:04:18.766047 DisplayPort interface
9356 11:04:18.766138 Maximum image size: 31 cm x 17 cm
9357 11:04:18.769334 Gamma: 220%
9358 11:04:18.769432 Check DPMS levels
9359 11:04:18.775870 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9360 11:04:18.779329 First detailed timing is preferred timing
9361 11:04:18.779424 Established timings supported:
9362 11:04:18.782366 Standard timings supported:
9363 11:04:18.785475 Detailed timings
9364 11:04:18.788713 Hex of detail: 383680a07038204018303c0035ae10000019
9365 11:04:18.795674 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9366 11:04:18.798734 0780 0798 07c8 0820 hborder 0
9367 11:04:18.802266 0438 043b 0447 0458 vborder 0
9368 11:04:18.805205 -hsync -vsync
9369 11:04:18.805295 Did detailed timing
9370 11:04:18.811887 Hex of detail: 000000000000000000000000000000000000
9371 11:04:18.815260 Manufacturer-specified data, tag 0
9372 11:04:18.818517 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9373 11:04:18.821581 ASCII string: InfoVision
9374 11:04:18.824916 Hex of detail: 000000fe00523134304e574635205248200a
9375 11:04:18.828158 ASCII string: R140NWF5 RH
9376 11:04:18.828254 Checksum
9377 11:04:18.832338 Checksum: 0xfb (valid)
9378 11:04:18.834795 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9379 11:04:18.838190 DSI data_rate: 832800000 bps
9380 11:04:18.844768 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9381 11:04:18.848294 anx7625_parse_edid: pixelclock(138800).
9382 11:04:18.851533 hactive(1920), hsync(48), hfp(24), hbp(88)
9383 11:04:18.854846 vactive(1080), vsync(12), vfp(3), vbp(17)
9384 11:04:18.858315 anx7625_dsi_config: config dsi.
9385 11:04:18.864515 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9386 11:04:18.878708 anx7625_dsi_config: success to config DSI
9387 11:04:18.881841 anx7625_dp_start: MIPI phy setup OK.
9388 11:04:18.885572 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9389 11:04:18.888585 mtk_ddp_mode_set invalid vrefresh 60
9390 11:04:18.891674 main_disp_path_setup
9391 11:04:18.891769 ovl_layer_smi_id_en
9392 11:04:18.895093 ovl_layer_smi_id_en
9393 11:04:18.895206 ccorr_config
9394 11:04:18.895296 aal_config
9395 11:04:18.898650 gamma_config
9396 11:04:18.898749 postmask_config
9397 11:04:18.901737 dither_config
9398 11:04:18.904867 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9399 11:04:18.911753 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9400 11:04:18.915062 Root Device init finished in 555 msecs
9401 11:04:18.917874 CPU_CLUSTER: 0 init
9402 11:04:18.924682 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9403 11:04:18.931300 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9404 11:04:18.931400 APU_MBOX 0x190000b0 = 0x10001
9405 11:04:18.934345 APU_MBOX 0x190001b0 = 0x10001
9406 11:04:18.937989 APU_MBOX 0x190005b0 = 0x10001
9407 11:04:18.941173 APU_MBOX 0x190006b0 = 0x10001
9408 11:04:18.947886 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9409 11:04:18.957420 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9410 11:04:18.969784 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9411 11:04:18.976689 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9412 11:04:18.988453 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9413 11:04:18.997581 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9414 11:04:19.000860 CPU_CLUSTER: 0 init finished in 81 msecs
9415 11:04:19.004114 Devices initialized
9416 11:04:19.007612 Show all devs... After init.
9417 11:04:19.007710 Root Device: enabled 1
9418 11:04:19.010820 CPU_CLUSTER: 0: enabled 1
9419 11:04:19.013723 CPU: 00: enabled 1
9420 11:04:19.017004 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9421 11:04:19.020455 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9422 11:04:19.023429 ELOG: NV offset 0x57f000 size 0x1000
9423 11:04:19.030624 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9424 11:04:19.037238 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9425 11:04:19.040146 ELOG: Event(17) added with size 13 at 2024-07-10 11:04:19 UTC
9426 11:04:19.047262 out: cmd=0x121: 03 db 21 01 00 00 00 00
9427 11:04:19.050349 in-header: 03 61 00 00 2c 00 00 00
9428 11:04:19.060047 in-data: dc 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9429 11:04:19.066793 ELOG: Event(A1) added with size 10 at 2024-07-10 11:04:19 UTC
9430 11:04:19.073293 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9431 11:04:19.079864 ELOG: Event(A0) added with size 9 at 2024-07-10 11:04:19 UTC
9432 11:04:19.083072 elog_add_boot_reason: Logged dev mode boot
9433 11:04:19.089546 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9434 11:04:19.089647 Finalize devices...
9435 11:04:19.093472 Devices finalized
9436 11:04:19.096373 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9437 11:04:19.099606 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9438 11:04:19.102915 in-header: 03 07 00 00 08 00 00 00
9439 11:04:19.106381 in-data: aa e4 47 04 13 02 00 00
9440 11:04:19.109628 Chrome EC: UHEPI supported
9441 11:04:19.116058 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9442 11:04:19.119355 in-header: 03 a9 00 00 08 00 00 00
9443 11:04:19.122810 in-data: 84 60 60 08 00 00 00 00
9444 11:04:19.129311 ELOG: Event(91) added with size 10 at 2024-07-10 11:04:19 UTC
9445 11:04:19.132563 Chrome EC: clear events_b mask to 0x0000000020004000
9446 11:04:19.139577 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9447 11:04:19.142948 in-header: 03 fd 00 00 00 00 00 00
9448 11:04:19.143046 in-data:
9449 11:04:19.149614 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9450 11:04:19.152808 Writing coreboot table at 0xffe64000
9451 11:04:19.156083 0. 000000000010a000-0000000000113fff: RAMSTAGE
9452 11:04:19.159507 1. 0000000040000000-00000000400fffff: RAM
9453 11:04:19.165914 2. 0000000040100000-000000004032afff: RAMSTAGE
9454 11:04:19.169228 3. 000000004032b000-00000000545fffff: RAM
9455 11:04:19.172743 4. 0000000054600000-000000005465ffff: BL31
9456 11:04:19.176032 5. 0000000054660000-00000000ffe63fff: RAM
9457 11:04:19.182719 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9458 11:04:19.185596 7. 0000000100000000-000000023fffffff: RAM
9459 11:04:19.189273 Passing 5 GPIOs to payload:
9460 11:04:19.192256 NAME | PORT | POLARITY | VALUE
9461 11:04:19.199046 EC in RW | 0x000000aa | low | undefined
9462 11:04:19.202378 EC interrupt | 0x00000005 | low | undefined
9463 11:04:19.205533 TPM interrupt | 0x000000ab | high | undefined
9464 11:04:19.212128 SD card detect | 0x00000011 | high | undefined
9465 11:04:19.215451 speaker enable | 0x00000093 | high | undefined
9466 11:04:19.219150 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9467 11:04:19.222130 in-header: 03 f9 00 00 02 00 00 00
9468 11:04:19.225506 in-data: 02 00
9469 11:04:19.228501 ADC[4]: Raw value=903031 ID=7
9470 11:04:19.228604 ADC[3]: Raw value=213282 ID=1
9471 11:04:19.231959 RAM Code: 0x71
9472 11:04:19.235439 ADC[6]: Raw value=75036 ID=0
9473 11:04:19.235519 ADC[5]: Raw value=213282 ID=1
9474 11:04:19.238845 SKU Code: 0x1
9475 11:04:19.244900 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b2f4
9476 11:04:19.244968 coreboot table: 964 bytes.
9477 11:04:19.248428 IMD ROOT 0. 0xfffff000 0x00001000
9478 11:04:19.251550 IMD SMALL 1. 0xffffe000 0x00001000
9479 11:04:19.255288 RO MCACHE 2. 0xffffc000 0x00001104
9480 11:04:19.258192 CONSOLE 3. 0xfff7c000 0x00080000
9481 11:04:19.261385 FMAP 4. 0xfff7b000 0x00000452
9482 11:04:19.264718 TIME STAMP 5. 0xfff7a000 0x00000910
9483 11:04:19.268221 VBOOT WORK 6. 0xfff66000 0x00014000
9484 11:04:19.271422 RAMOOPS 7. 0xffe66000 0x00100000
9485 11:04:19.274702 COREBOOT 8. 0xffe64000 0x00002000
9486 11:04:19.278194 IMD small region:
9487 11:04:19.281634 IMD ROOT 0. 0xffffec00 0x00000400
9488 11:04:19.284363 VPD 1. 0xffffeb80 0x0000006c
9489 11:04:19.288182 MMC STATUS 2. 0xffffeb60 0x00000004
9490 11:04:19.294217 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9491 11:04:19.300829 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9492 11:04:19.339292 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9493 11:04:19.342772 Checking segment from ROM address 0x40100000
9494 11:04:19.346417 Checking segment from ROM address 0x4010001c
9495 11:04:19.352530 Loading segment from ROM address 0x40100000
9496 11:04:19.352632 code (compression=0)
9497 11:04:19.362204 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9498 11:04:19.369054 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9499 11:04:19.369157 it's not compressed!
9500 11:04:19.375754 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9501 11:04:19.382023 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9502 11:04:19.399908 Loading segment from ROM address 0x4010001c
9503 11:04:19.400011 Entry Point 0x80000000
9504 11:04:19.402640 Loaded segments
9505 11:04:19.406528 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9506 11:04:19.412746 Jumping to boot code at 0x80000000(0xffe64000)
9507 11:04:19.419371 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9508 11:04:19.426229 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9509 11:04:19.434171 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9510 11:04:19.437504 Checking segment from ROM address 0x40100000
9511 11:04:19.440628 Checking segment from ROM address 0x4010001c
9512 11:04:19.447041 Loading segment from ROM address 0x40100000
9513 11:04:19.447140 code (compression=1)
9514 11:04:19.453747 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9515 11:04:19.463739 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9516 11:04:19.463844 using LZMA
9517 11:04:19.472424 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9518 11:04:19.479135 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9519 11:04:19.482177 Loading segment from ROM address 0x4010001c
9520 11:04:19.485411 Entry Point 0x54601000
9521 11:04:19.485505 Loaded segments
9522 11:04:19.488689 NOTICE: MT8192 bl31_setup
9523 11:04:19.496117 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9524 11:04:19.499607 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9525 11:04:19.502826 WARNING: region 0:
9526 11:04:19.505643 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 11:04:19.505737 WARNING: region 1:
9528 11:04:19.512672 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9529 11:04:19.515986 WARNING: region 2:
9530 11:04:19.519285 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9531 11:04:19.522270 WARNING: region 3:
9532 11:04:19.529413 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9533 11:04:19.529513 WARNING: region 4:
9534 11:04:19.535422 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 11:04:19.535536 WARNING: region 5:
9536 11:04:19.538855 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 11:04:19.542181 WARNING: region 6:
9538 11:04:19.545592 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 11:04:19.548872 WARNING: region 7:
9540 11:04:19.552064 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 11:04:19.558751 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9542 11:04:19.562390 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9543 11:04:19.568421 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9544 11:04:19.571743 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9545 11:04:19.574897 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9546 11:04:19.581644 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9547 11:04:19.584891 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9548 11:04:19.588300 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9549 11:04:19.594828 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9550 11:04:19.598340 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9551 11:04:19.604893 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9552 11:04:19.608171 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9553 11:04:19.611595 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9554 11:04:19.617743 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9555 11:04:19.621050 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9556 11:04:19.628003 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9557 11:04:19.630976 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9558 11:04:19.634561 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9559 11:04:19.641044 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9560 11:04:19.644426 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9561 11:04:19.650926 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9562 11:04:19.653874 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9563 11:04:19.657085 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9564 11:04:19.663637 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9565 11:04:19.667320 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9566 11:04:19.673438 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9567 11:04:19.677311 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9568 11:04:19.680279 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9569 11:04:19.686957 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9570 11:04:19.690077 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9571 11:04:19.696629 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9572 11:04:19.699757 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9573 11:04:19.703124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9574 11:04:19.709785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9575 11:04:19.713255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9576 11:04:19.716558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9577 11:04:19.719506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9578 11:04:19.726297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9579 11:04:19.729498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9580 11:04:19.732987 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9581 11:04:19.736110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9582 11:04:19.742837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9583 11:04:19.746212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9584 11:04:19.749418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9585 11:04:19.755712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9586 11:04:19.759643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9587 11:04:19.762657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9588 11:04:19.766464 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9589 11:04:19.772589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9590 11:04:19.776098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9591 11:04:19.782624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9592 11:04:19.785904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9593 11:04:19.792320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9594 11:04:19.795813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9595 11:04:19.799045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9596 11:04:19.805693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9597 11:04:19.808857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9598 11:04:19.815526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9599 11:04:19.818856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9600 11:04:19.825441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9601 11:04:19.828646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9602 11:04:19.835414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9603 11:04:19.838408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9604 11:04:19.845334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9605 11:04:19.848227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9606 11:04:19.851545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9607 11:04:19.858521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9608 11:04:19.861811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9609 11:04:19.868232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9610 11:04:19.871414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9611 11:04:19.877882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9612 11:04:19.881305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9613 11:04:19.884645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9614 11:04:19.891040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9615 11:04:19.894446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9616 11:04:19.901310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9617 11:04:19.904315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9618 11:04:19.911334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9619 11:04:19.914209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9620 11:04:19.920990 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9621 11:04:19.924617 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9622 11:04:19.930956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9623 11:04:19.933972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9624 11:04:19.937230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9625 11:04:19.944032 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9626 11:04:19.947513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9627 11:04:19.954025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9628 11:04:19.957468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9629 11:04:19.963932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9630 11:04:19.967035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9631 11:04:19.970367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9632 11:04:19.977088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9633 11:04:19.980400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9634 11:04:19.986780 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9635 11:04:19.990253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9636 11:04:19.997087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9637 11:04:20.000414 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9638 11:04:20.003348 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9639 11:04:20.009964 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9640 11:04:20.013305 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9641 11:04:20.016890 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9642 11:04:20.020299 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9643 11:04:20.026780 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9644 11:04:20.029727 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9645 11:04:20.036412 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9646 11:04:20.040100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9647 11:04:20.046693 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9648 11:04:20.049503 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9649 11:04:20.053030 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9650 11:04:20.059884 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9651 11:04:20.062830 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9652 11:04:20.069697 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9653 11:04:20.073130 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9654 11:04:20.076074 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9655 11:04:20.083026 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9656 11:04:20.085918 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9657 11:04:20.089375 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9658 11:04:20.095746 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9659 11:04:20.099045 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9660 11:04:20.102658 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9661 11:04:20.109000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9662 11:04:20.112395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9663 11:04:20.116066 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9664 11:04:20.118853 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9665 11:04:20.125467 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9666 11:04:20.128848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9667 11:04:20.135337 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9668 11:04:20.138711 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9669 11:04:20.142308 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9670 11:04:20.148520 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9671 11:04:20.151981 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9672 11:04:20.158382 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9673 11:04:20.162199 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9674 11:04:20.165088 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9675 11:04:20.171678 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9676 11:04:20.175055 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9677 11:04:20.181711 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9678 11:04:20.185407 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9679 11:04:20.188242 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9680 11:04:20.195033 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9681 11:04:20.198282 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9682 11:04:20.204721 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9683 11:04:20.208238 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9684 11:04:20.211209 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9685 11:04:20.217843 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9686 11:04:20.221336 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9687 11:04:20.227647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9688 11:04:20.231025 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9689 11:04:20.234291 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9690 11:04:20.240982 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9691 11:04:20.244241 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9692 11:04:20.251235 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9693 11:04:20.254288 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9694 11:04:20.257503 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9695 11:04:20.264291 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9696 11:04:20.267634 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9697 11:04:20.274086 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9698 11:04:20.277376 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9699 11:04:20.280745 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9700 11:04:20.287306 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9701 11:04:20.290489 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9702 11:04:20.297060 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9703 11:04:20.300417 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9704 11:04:20.303934 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9705 11:04:20.310053 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9706 11:04:20.313508 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9707 11:04:20.320512 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9708 11:04:20.323710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9709 11:04:20.326878 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9710 11:04:20.333215 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9711 11:04:20.336820 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9712 11:04:20.343314 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9713 11:04:20.346985 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9714 11:04:20.349604 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9715 11:04:20.356182 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9716 11:04:20.359812 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9717 11:04:20.366019 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9718 11:04:20.369389 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9719 11:04:20.372675 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9720 11:04:20.379518 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9721 11:04:20.383239 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9722 11:04:20.389617 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9723 11:04:20.392941 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9724 11:04:20.395738 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9725 11:04:20.402454 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9726 11:04:20.405805 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9727 11:04:20.412096 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9728 11:04:20.415686 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9729 11:04:20.422163 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9730 11:04:20.425424 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9731 11:04:20.429095 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9732 11:04:20.435331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9733 11:04:20.439057 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9734 11:04:20.444958 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9735 11:04:20.448873 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9736 11:04:20.455399 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9737 11:04:20.458772 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9738 11:04:20.461888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9739 11:04:20.468460 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9740 11:04:20.471409 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9741 11:04:20.478057 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9742 11:04:20.481749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9743 11:04:20.484845 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9744 11:04:20.491185 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9745 11:04:20.494857 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9746 11:04:20.501022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9747 11:04:20.504330 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9748 11:04:20.511055 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9749 11:04:20.514489 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9750 11:04:20.520802 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9751 11:04:20.524180 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9752 11:04:20.527591 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9753 11:04:20.533939 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9754 11:04:20.537637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9755 11:04:20.543930 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9756 11:04:20.547552 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9757 11:04:20.553977 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9758 11:04:20.556916 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9759 11:04:20.560204 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9760 11:04:20.567239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9761 11:04:20.570607 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9762 11:04:20.576761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9763 11:04:20.579869 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9764 11:04:20.586603 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9765 11:04:20.590238 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9766 11:04:20.593445 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9767 11:04:20.600498 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9768 11:04:20.603171 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9769 11:04:20.609975 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9770 11:04:20.613405 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9771 11:04:20.616586 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9772 11:04:20.619680 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9773 11:04:20.626671 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9774 11:04:20.629644 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9775 11:04:20.633060 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9776 11:04:20.639463 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9777 11:04:20.642844 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9778 11:04:20.646308 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9779 11:04:20.653195 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9780 11:04:20.656392 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9781 11:04:20.659512 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9782 11:04:20.666149 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9783 11:04:20.669416 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9784 11:04:20.672996 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9785 11:04:20.679060 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9786 11:04:20.682607 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9787 11:04:20.688982 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9788 11:04:20.692565 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9789 11:04:20.695658 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9790 11:04:20.702237 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9791 11:04:20.705917 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9792 11:04:20.712243 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9793 11:04:20.715654 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9794 11:04:20.718720 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9795 11:04:20.725507 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9796 11:04:20.728544 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9797 11:04:20.732188 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9798 11:04:20.738620 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9799 11:04:20.741573 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9800 11:04:20.748278 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9801 11:04:20.751572 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9802 11:04:20.755249 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9803 11:04:20.761538 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9804 11:04:20.764949 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9805 11:04:20.768405 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9806 11:04:20.774702 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9807 11:04:20.778211 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9808 11:04:20.784880 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9809 11:04:20.788004 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9810 11:04:20.790882 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9811 11:04:20.794319 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9812 11:04:20.800685 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9813 11:04:20.804037 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9814 11:04:20.807866 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9815 11:04:20.811102 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9816 11:04:20.817467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9817 11:04:20.820816 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9818 11:04:20.824284 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9819 11:04:20.827664 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9820 11:04:20.834202 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9821 11:04:20.837332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9822 11:04:20.840933 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9823 11:04:20.847195 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9824 11:04:20.850599 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9825 11:04:20.856983 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9826 11:04:20.860218 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9827 11:04:20.863647 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9828 11:04:20.870409 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9829 11:04:20.873464 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9830 11:04:20.879765 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9831 11:04:20.883037 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9832 11:04:20.886797 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9833 11:04:20.893324 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9834 11:04:20.896455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9835 11:04:20.903178 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9836 11:04:20.906600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9837 11:04:20.913052 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9838 11:04:20.916387 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9839 11:04:20.919615 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9840 11:04:20.926055 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9841 11:04:20.929310 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9842 11:04:20.936296 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9843 11:04:20.939299 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9844 11:04:20.945760 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9845 11:04:20.948989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9846 11:04:20.952592 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9847 11:04:20.959088 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9848 11:04:20.962303 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9849 11:04:20.969392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9850 11:04:20.972059 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9851 11:04:20.978880 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9852 11:04:20.982435 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9853 11:04:20.985666 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9854 11:04:20.991866 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9855 11:04:20.995341 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9856 11:04:21.001891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9857 11:04:21.005236 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9858 11:04:21.008197 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9859 11:04:21.015069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9860 11:04:21.018134 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9861 11:04:21.024859 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9862 11:04:21.028113 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9863 11:04:21.034605 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9864 11:04:21.038260 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9865 11:04:21.041308 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9866 11:04:21.048072 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9867 11:04:21.051317 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9868 11:04:21.057525 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9869 11:04:21.061413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9870 11:04:21.064499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9871 11:04:21.071129 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9872 11:04:21.074483 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9873 11:04:21.080740 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9874 11:04:21.084106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9875 11:04:21.090878 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9876 11:04:21.094191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9877 11:04:21.097600 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9878 11:04:21.103977 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9879 11:04:21.107549 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9880 11:04:21.113917 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9881 11:04:21.116882 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9882 11:04:21.123410 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9883 11:04:21.127285 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9884 11:04:21.130303 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9885 11:04:21.136673 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9886 11:04:21.140422 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9887 11:04:21.146531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9888 11:04:21.149954 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9889 11:04:21.153335 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9890 11:04:21.160194 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9891 11:04:21.163271 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9892 11:04:21.169753 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9893 11:04:21.173571 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9894 11:04:21.176400 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9895 11:04:21.182949 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9896 11:04:21.186292 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9897 11:04:21.192923 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9898 11:04:21.196305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9899 11:04:21.203049 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9900 11:04:21.206054 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9901 11:04:21.213060 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9902 11:04:21.215819 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9903 11:04:21.219046 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9904 11:04:21.226021 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9905 11:04:21.229376 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9906 11:04:21.235401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9907 11:04:21.238820 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9908 11:04:21.245940 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9909 11:04:21.248783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9910 11:04:21.255558 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9911 11:04:21.258691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9912 11:04:21.265245 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9913 11:04:21.268785 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9914 11:04:21.271901 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9915 11:04:21.278375 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9916 11:04:21.282216 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9917 11:04:21.288785 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9918 11:04:21.291708 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9919 11:04:21.298126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9920 11:04:21.302000 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9921 11:04:21.308146 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9922 11:04:21.311648 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9923 11:04:21.314708 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9924 11:04:21.321490 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9925 11:04:21.324626 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9926 11:04:21.331160 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9927 11:04:21.334300 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9928 11:04:21.341125 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9929 11:04:21.344636 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9930 11:04:21.351096 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9931 11:04:21.354306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9932 11:04:21.357494 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9933 11:04:21.364537 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9934 11:04:21.368082 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9935 11:04:21.374389 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9936 11:04:21.377483 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9937 11:04:21.384348 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9938 11:04:21.387571 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9939 11:04:21.394263 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9940 11:04:21.397033 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9941 11:04:21.400792 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9942 11:04:21.407465 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9943 11:04:21.410474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9944 11:04:21.417059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9945 11:04:21.420511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9946 11:04:21.426896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9947 11:04:21.429849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9948 11:04:21.436705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9949 11:04:21.440173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9950 11:04:21.446425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9951 11:04:21.449706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9952 11:04:21.456508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9953 11:04:21.459681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9954 11:04:21.463052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9955 11:04:21.469521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9956 11:04:21.472762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9957 11:04:21.479352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9958 11:04:21.482830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9959 11:04:21.489604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9960 11:04:21.492619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9961 11:04:21.499267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9962 11:04:21.502916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9963 11:04:21.509387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9964 11:04:21.512239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9965 11:04:21.519242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9966 11:04:21.525766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9967 11:04:21.528661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9968 11:04:21.535418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9969 11:04:21.538769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9970 11:04:21.545953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9971 11:04:21.548568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9972 11:04:21.555308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9973 11:04:21.558649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9974 11:04:21.564957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9975 11:04:21.568459 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9976 11:04:21.571715 INFO: [APUAPC] vio 0
9977 11:04:21.575097 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9978 11:04:21.581549 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9979 11:04:21.581623 INFO: [APUAPC] D0_APC_0: 0x400510
9980 11:04:21.584885 INFO: [APUAPC] D0_APC_1: 0x0
9981 11:04:21.588175 INFO: [APUAPC] D0_APC_2: 0x1540
9982 11:04:21.591251 INFO: [APUAPC] D0_APC_3: 0x0
9983 11:04:21.594401 INFO: [APUAPC] D1_APC_0: 0xffffffff
9984 11:04:21.597803 INFO: [APUAPC] D1_APC_1: 0xffffffff
9985 11:04:21.601071 INFO: [APUAPC] D1_APC_2: 0x3fffff
9986 11:04:21.604524 INFO: [APUAPC] D1_APC_3: 0x0
9987 11:04:21.608067 INFO: [APUAPC] D2_APC_0: 0xffffffff
9988 11:04:21.610995 INFO: [APUAPC] D2_APC_1: 0xffffffff
9989 11:04:21.614557 INFO: [APUAPC] D2_APC_2: 0x3fffff
9990 11:04:21.617871 INFO: [APUAPC] D2_APC_3: 0x0
9991 11:04:21.621474 INFO: [APUAPC] D3_APC_0: 0xffffffff
9992 11:04:21.624480 INFO: [APUAPC] D3_APC_1: 0xffffffff
9993 11:04:21.627977 INFO: [APUAPC] D3_APC_2: 0x3fffff
9994 11:04:21.631222 INFO: [APUAPC] D3_APC_3: 0x0
9995 11:04:21.634495 INFO: [APUAPC] D4_APC_0: 0xffffffff
9996 11:04:21.637474 INFO: [APUAPC] D4_APC_1: 0xffffffff
9997 11:04:21.640927 INFO: [APUAPC] D4_APC_2: 0x3fffff
9998 11:04:21.644210 INFO: [APUAPC] D4_APC_3: 0x0
9999 11:04:21.647510 INFO: [APUAPC] D5_APC_0: 0xffffffff
10000 11:04:21.650483 INFO: [APUAPC] D5_APC_1: 0xffffffff
10001 11:04:21.653780 INFO: [APUAPC] D5_APC_2: 0x3fffff
10002 11:04:21.657283 INFO: [APUAPC] D5_APC_3: 0x0
10003 11:04:21.660687 INFO: [APUAPC] D6_APC_0: 0xffffffff
10004 11:04:21.663996 INFO: [APUAPC] D6_APC_1: 0xffffffff
10005 11:04:21.667442 INFO: [APUAPC] D6_APC_2: 0x3fffff
10006 11:04:21.670460 INFO: [APUAPC] D6_APC_3: 0x0
10007 11:04:21.673546 INFO: [APUAPC] D7_APC_0: 0xffffffff
10008 11:04:21.676739 INFO: [APUAPC] D7_APC_1: 0xffffffff
10009 11:04:21.680058 INFO: [APUAPC] D7_APC_2: 0x3fffff
10010 11:04:21.683758 INFO: [APUAPC] D7_APC_3: 0x0
10011 11:04:21.687004 INFO: [APUAPC] D8_APC_0: 0xffffffff
10012 11:04:21.689985 INFO: [APUAPC] D8_APC_1: 0xffffffff
10013 11:04:21.693155 INFO: [APUAPC] D8_APC_2: 0x3fffff
10014 11:04:21.696593 INFO: [APUAPC] D8_APC_3: 0x0
10015 11:04:21.699966 INFO: [APUAPC] D9_APC_0: 0xffffffff
10016 11:04:21.703297 INFO: [APUAPC] D9_APC_1: 0xffffffff
10017 11:04:21.706696 INFO: [APUAPC] D9_APC_2: 0x3fffff
10018 11:04:21.710284 INFO: [APUAPC] D9_APC_3: 0x0
10019 11:04:21.713528 INFO: [APUAPC] D10_APC_0: 0xffffffff
10020 11:04:21.716896 INFO: [APUAPC] D10_APC_1: 0xffffffff
10021 11:04:21.720274 INFO: [APUAPC] D10_APC_2: 0x3fffff
10022 11:04:21.723410 INFO: [APUAPC] D10_APC_3: 0x0
10023 11:04:21.726518 INFO: [APUAPC] D11_APC_0: 0xffffffff
10024 11:04:21.729661 INFO: [APUAPC] D11_APC_1: 0xffffffff
10025 11:04:21.733601 INFO: [APUAPC] D11_APC_2: 0x3fffff
10026 11:04:21.736526 INFO: [APUAPC] D11_APC_3: 0x0
10027 11:04:21.739734 INFO: [APUAPC] D12_APC_0: 0xffffffff
10028 11:04:21.743258 INFO: [APUAPC] D12_APC_1: 0xffffffff
10029 11:04:21.746282 INFO: [APUAPC] D12_APC_2: 0x3fffff
10030 11:04:21.749556 INFO: [APUAPC] D12_APC_3: 0x0
10031 11:04:21.752889 INFO: [APUAPC] D13_APC_0: 0xffffffff
10032 11:04:21.756099 INFO: [APUAPC] D13_APC_1: 0xffffffff
10033 11:04:21.759829 INFO: [APUAPC] D13_APC_2: 0x3fffff
10034 11:04:21.763199 INFO: [APUAPC] D13_APC_3: 0x0
10035 11:04:21.766503 INFO: [APUAPC] D14_APC_0: 0xffffffff
10036 11:04:21.769341 INFO: [APUAPC] D14_APC_1: 0xffffffff
10037 11:04:21.772861 INFO: [APUAPC] D14_APC_2: 0x3fffff
10038 11:04:21.776067 INFO: [APUAPC] D14_APC_3: 0x0
10039 11:04:21.779549 INFO: [APUAPC] D15_APC_0: 0xffffffff
10040 11:04:21.782713 INFO: [APUAPC] D15_APC_1: 0xffffffff
10041 11:04:21.786064 INFO: [APUAPC] D15_APC_2: 0x3fffff
10042 11:04:21.789547 INFO: [APUAPC] D15_APC_3: 0x0
10043 11:04:21.792467 INFO: [APUAPC] APC_CON: 0x4
10044 11:04:21.796250 INFO: [NOCDAPC] D0_APC_0: 0x0
10045 11:04:21.799474 INFO: [NOCDAPC] D0_APC_1: 0x0
10046 11:04:21.799567 INFO: [NOCDAPC] D1_APC_0: 0x0
10047 11:04:21.802750 INFO: [NOCDAPC] D1_APC_1: 0xfff
10048 11:04:21.805766 INFO: [NOCDAPC] D2_APC_0: 0x0
10049 11:04:21.809712 INFO: [NOCDAPC] D2_APC_1: 0xfff
10050 11:04:21.812894 INFO: [NOCDAPC] D3_APC_0: 0x0
10051 11:04:21.815854 INFO: [NOCDAPC] D3_APC_1: 0xfff
10052 11:04:21.819325 INFO: [NOCDAPC] D4_APC_0: 0x0
10053 11:04:21.822227 INFO: [NOCDAPC] D4_APC_1: 0xfff
10054 11:04:21.826360 INFO: [NOCDAPC] D5_APC_0: 0x0
10055 11:04:21.829186 INFO: [NOCDAPC] D5_APC_1: 0xfff
10056 11:04:21.832280 INFO: [NOCDAPC] D6_APC_0: 0x0
10057 11:04:21.835308 INFO: [NOCDAPC] D6_APC_1: 0xfff
10058 11:04:21.835407 INFO: [NOCDAPC] D7_APC_0: 0x0
10059 11:04:21.839201 INFO: [NOCDAPC] D7_APC_1: 0xfff
10060 11:04:21.842422 INFO: [NOCDAPC] D8_APC_0: 0x0
10061 11:04:21.845504 INFO: [NOCDAPC] D8_APC_1: 0xfff
10062 11:04:21.848950 INFO: [NOCDAPC] D9_APC_0: 0x0
10063 11:04:21.851874 INFO: [NOCDAPC] D9_APC_1: 0xfff
10064 11:04:21.855267 INFO: [NOCDAPC] D10_APC_0: 0x0
10065 11:04:21.858866 INFO: [NOCDAPC] D10_APC_1: 0xfff
10066 11:04:21.861842 INFO: [NOCDAPC] D11_APC_0: 0x0
10067 11:04:21.865110 INFO: [NOCDAPC] D11_APC_1: 0xfff
10068 11:04:21.868640 INFO: [NOCDAPC] D12_APC_0: 0x0
10069 11:04:21.871929 INFO: [NOCDAPC] D12_APC_1: 0xfff
10070 11:04:21.875485 INFO: [NOCDAPC] D13_APC_0: 0x0
10071 11:04:21.878324 INFO: [NOCDAPC] D13_APC_1: 0xfff
10072 11:04:21.878418 INFO: [NOCDAPC] D14_APC_0: 0x0
10073 11:04:21.881881 INFO: [NOCDAPC] D14_APC_1: 0xfff
10074 11:04:21.885275 INFO: [NOCDAPC] D15_APC_0: 0x0
10075 11:04:21.888422 INFO: [NOCDAPC] D15_APC_1: 0xfff
10076 11:04:21.891678 INFO: [NOCDAPC] APC_CON: 0x4
10077 11:04:21.894814 INFO: [APUAPC] set_apusys_apc done
10078 11:04:21.897983 INFO: [DEVAPC] devapc_init done
10079 11:04:21.901381 INFO: GICv3 without legacy support detected.
10080 11:04:21.908050 INFO: ARM GICv3 driver initialized in EL3
10081 11:04:21.911678 INFO: Maximum SPI INTID supported: 639
10082 11:04:21.914554 INFO: BL31: Initializing runtime services
10083 11:04:21.921449 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10084 11:04:21.921553 INFO: SPM: enable CPC mode
10085 11:04:21.927876 INFO: mcdi ready for mcusys-off-idle and system suspend
10086 11:04:21.931215 INFO: BL31: Preparing for EL3 exit to normal world
10087 11:04:21.937652 INFO: Entry point address = 0x80000000
10088 11:04:21.937752 INFO: SPSR = 0x8
10089 11:04:21.944075
10090 11:04:21.944168
10091 11:04:21.944256
10092 11:04:21.947495 Starting depthcharge on Spherion...
10093 11:04:21.947561
10094 11:04:21.947616 Wipe memory regions:
10095 11:04:21.947669
10096 11:04:21.948459 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10097 11:04:21.948578 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10098 11:04:21.948677 Setting prompt string to ['asurada:']
10099 11:04:21.948770 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10100 11:04:21.950629 [0x00000040000000, 0x00000054600000)
10101 11:04:22.073464
10102 11:04:22.073598 [0x00000054660000, 0x00000080000000)
10103 11:04:22.333485
10104 11:04:22.333630 [0x000000821a7280, 0x000000ffe64000)
10105 11:04:23.078642
10106 11:04:23.078785 [0x00000100000000, 0x00000240000000)
10107 11:04:24.968576
10108 11:04:24.972319 Initializing XHCI USB controller at 0x11200000.
10109 11:04:26.010358
10110 11:04:26.013532 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10111 11:04:26.013611
10112 11:04:26.013669
10113 11:04:26.013930 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10114 11:04:26.014032 Sending line: 'tftpboot 192.168.201.1 14786788/tftp-deploy-nbkabym0/kernel/image.itb 14786788/tftp-deploy-nbkabym0/kernel/cmdline '
10116 11:04:26.114472 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10117 11:04:26.114578 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10118 11:04:26.118915 asurada: tftpboot 192.168.201.1 14786788/tftp-deploy-nbkabym0/kernel/image.ittp-deploy-nbkabym0/kernel/cmdline
10119 11:04:26.119012
10120 11:04:26.119097 Waiting for link
10121 11:04:26.276758
10122 11:04:26.276899 R8152: Initializing
10123 11:04:26.276986
10124 11:04:26.280096 Version 6 (ocp_data = 5c30)
10125 11:04:26.280205
10126 11:04:26.283419 R8152: Done initializing
10127 11:04:26.283534
10128 11:04:26.283616 Adding net device
10129 11:04:28.251046
10130 11:04:28.251181 done.
10131 11:04:28.251284
10132 11:04:28.251367 MAC: 00:e0:4c:68:02:81
10133 11:04:28.251472
10134 11:04:28.254536 Sending DHCP discover... done.
10135 11:04:28.254622
10136 11:04:28.257458 Waiting for reply... done.
10137 11:04:28.257547
10138 11:04:28.260942 Sending DHCP request... done.
10139 11:04:28.261031
10140 11:04:28.265801 Waiting for reply... done.
10141 11:04:28.265886
10142 11:04:28.265969 My ip is 192.168.201.14
10143 11:04:28.266047
10144 11:04:28.269033 The DHCP server ip is 192.168.201.1
10145 11:04:28.269124
10146 11:04:28.275611 TFTP server IP predefined by user: 192.168.201.1
10147 11:04:28.275706
10148 11:04:28.282115 Bootfile predefined by user: 14786788/tftp-deploy-nbkabym0/kernel/image.itb
10149 11:04:28.282223
10150 11:04:28.285533 Sending tftp read request... done.
10151 11:04:28.285625
10152 11:04:28.289237 Waiting for the transfer...
10153 11:04:28.289327
10154 11:04:28.813841 00000000 ################################################################
10155 11:04:28.814044
10156 11:04:29.334372 00080000 ################################################################
10157 11:04:29.334493
10158 11:04:29.857933 00100000 ################################################################
10159 11:04:29.858061
10160 11:04:30.381345 00180000 ################################################################
10161 11:04:30.381478
10162 11:04:30.903919 00200000 ################################################################
10163 11:04:30.904069
10164 11:04:31.446552 00280000 ################################################################
10165 11:04:31.446665
10166 11:04:31.986420 00300000 ################################################################
10167 11:04:31.986541
10168 11:04:32.526612 00380000 ################################################################
10169 11:04:32.526735
10170 11:04:33.047556 00400000 ################################################################
10171 11:04:33.047674
10172 11:04:33.568425 00480000 ################################################################
10173 11:04:33.568549
10174 11:04:34.113141 00500000 ################################################################
10175 11:04:34.113270
10176 11:04:34.648838 00580000 ################################################################
10177 11:04:34.648975
10178 11:04:35.201319 00600000 ################################################################
10179 11:04:35.201442
10180 11:04:35.742014 00680000 ################################################################
10181 11:04:35.742166
10182 11:04:36.282249 00700000 ################################################################
10183 11:04:36.282356
10184 11:04:36.845835 00780000 ################################################################
10185 11:04:36.845945
10186 11:04:37.397133 00800000 ################################################################
10187 11:04:37.397244
10188 11:04:37.929668 00880000 ################################################################
10189 11:04:37.929780
10190 11:04:38.475766 00900000 ################################################################
10191 11:04:38.475879
10192 11:04:39.012598 00980000 ################################################################
10193 11:04:39.012712
10194 11:04:39.566761 00a00000 ################################################################
10195 11:04:39.566867
10196 11:04:40.103955 00a80000 ################################################################
10197 11:04:40.104073
10198 11:04:40.645487 00b00000 ################################################################
10199 11:04:40.645614
10200 11:04:41.209570 00b80000 ################################################################
10201 11:04:41.209690
10202 11:04:41.773094 00c00000 ################################################################
10203 11:04:41.773226
10204 11:04:42.345657 00c80000 ################################################################
10205 11:04:42.345776
10206 11:04:42.919447 00d00000 ################################################################
10207 11:04:42.919577
10208 11:04:43.559687 00d80000 ################################################################
10209 11:04:43.560276
10210 11:04:44.254818 00e00000 ################################################################
10211 11:04:44.255290
10212 11:04:44.962802 00e80000 ################################################################
10213 11:04:44.963278
10214 11:04:45.627334 00f00000 ################################################################
10215 11:04:45.627476
10216 11:04:46.203714 00f80000 ################################################################
10217 11:04:46.203830
10218 11:04:46.771930 01000000 ################################################################
10219 11:04:46.772055
10220 11:04:47.408247 01080000 ################################################################
10221 11:04:47.408716
10222 11:04:48.096285 01100000 ################################################################
10223 11:04:48.096781
10224 11:04:48.725634 01180000 ################################################################
10225 11:04:48.725763
10226 11:04:49.354690 01200000 ################################################################
10227 11:04:49.354831
10228 11:04:49.897747 01280000 ################################################################
10229 11:04:49.898271
10230 11:04:50.601387 01300000 ################################################################
10231 11:04:50.601974
10232 11:04:51.292849 01380000 ################################################################
10233 11:04:51.293584
10234 11:04:51.963634 01400000 ################################################################
10235 11:04:51.964105
10236 11:04:52.538544 01480000 ################################################################
10237 11:04:52.538671
10238 11:04:53.180992 01500000 ################################################################
10239 11:04:53.181443
10240 11:04:53.860802 01580000 ################################################################
10241 11:04:53.861283
10242 11:04:54.576635 01600000 ################################################################
10243 11:04:54.577183
10244 11:04:55.269281 01680000 ################################################################
10245 11:04:55.269962
10246 11:04:55.940064 01700000 ################################################################
10247 11:04:55.940558
10248 11:04:56.563349 01780000 ################################################################
10249 11:04:56.563679
10250 11:04:57.186910 01800000 ################################################################
10251 11:04:57.187022
10252 11:04:57.768946 01880000 ################################################################
10253 11:04:57.769070
10254 11:04:58.405575 01900000 ################################################################
10255 11:04:58.406257
10256 11:04:59.061243 01980000 ################################################################
10257 11:04:59.061368
10258 11:04:59.718893 01a00000 ################################################################
10259 11:04:59.719473
10260 11:05:00.371725 01a80000 ################################################################
10261 11:05:00.372208
10262 11:05:00.971145 01b00000 ################################################################
10263 11:05:00.971257
10264 11:05:01.638500 01b80000 ################################################################
10265 11:05:01.639024
10266 11:05:02.193590 01c00000 ################################################################
10267 11:05:02.193717
10268 11:05:02.753598 01c80000 ################################################################
10269 11:05:02.754012
10270 11:05:03.330256 01d00000 ################################################################
10271 11:05:03.330814
10272 11:05:03.946784 01d80000 ################################################################
10273 11:05:03.946928
10274 11:05:04.484639 01e00000 ################################################### done.
10275 11:05:04.485105
10276 11:05:04.488085 The bootfile was 31874570 bytes long.
10277 11:05:04.488750
10278 11:05:04.491893 Sending tftp read request... done.
10279 11:05:04.492479
10280 11:05:04.496865 Waiting for the transfer...
10281 11:05:04.497267
10282 11:05:04.497566 00000000 # done.
10283 11:05:04.497852
10284 11:05:04.503352 Command line loaded dynamically from TFTP file: 14786788/tftp-deploy-nbkabym0/kernel/cmdline
10285 11:05:04.506413
10286 11:05:04.526703 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786788/extract-nfsrootfs-j6owxqcc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10287 11:05:04.527134
10288 11:05:04.529621 Loading FIT.
10289 11:05:04.530007
10290 11:05:04.530304 Image ramdisk-1 has 18709028 bytes.
10291 11:05:04.533020
10292 11:05:04.533404 Image fdt-1 has 47258 bytes.
10293 11:05:04.533706
10294 11:05:04.536636 Image kernel-1 has 13116259 bytes.
10295 11:05:04.537025
10296 11:05:04.546579 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10297 11:05:04.546973
10298 11:05:04.562789 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10299 11:05:04.563212
10300 11:05:04.569631 Choosing best match conf-1 for compat google,spherion-rev2.
10301 11:05:04.573219
10302 11:05:04.577505 Connected to device vid:did:rid of 1ae0:0028:00
10303 11:05:04.584530
10304 11:05:04.588009 tpm_get_response: command 0x17b, return code 0x0
10305 11:05:04.588413
10306 11:05:04.591299 ec_init: CrosEC protocol v3 supported (256, 248)
10307 11:05:04.595568
10308 11:05:04.598388 tpm_cleanup: add release locality here.
10309 11:05:04.598780
10310 11:05:04.599077 Shutting down all USB controllers.
10311 11:05:04.601906
10312 11:05:04.602378 Removing current net device
10313 11:05:04.602686
10314 11:05:04.608443 Exiting depthcharge with code 4 at timestamp: 72066624
10315 11:05:04.608891
10316 11:05:04.611555 LZMA decompressing kernel-1 to 0x821a6718
10317 11:05:04.611950
10318 11:05:04.615131 LZMA decompressing kernel-1 to 0x40000000
10319 11:05:06.230394
10320 11:05:06.230948 jumping to kernel
10321 11:05:06.232680 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10322 11:05:06.233270 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10323 11:05:06.233632 Setting prompt string to ['Linux version [0-9]']
10324 11:05:06.233947 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10325 11:05:06.234289 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10326 11:05:06.311193
10327 11:05:06.314404 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10328 11:05:06.318418 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10329 11:05:06.318925 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10330 11:05:06.319270 Setting prompt string to []
10331 11:05:06.319688 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10332 11:05:06.320061 Using line separator: #'\n'#
10333 11:05:06.320345 No login prompt set.
10334 11:05:06.320901 Parsing kernel messages
10335 11:05:06.321185 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10336 11:05:06.321714 [login-action] Waiting for messages, (timeout 00:03:35)
10337 11:05:06.322026 Waiting using forced prompt support (timeout 00:01:48)
10338 11:05:06.337397 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10339 11:05:06.340700 [ 0.000000] random: crng init done
10340 11:05:06.343855 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10341 11:05:06.347138 [ 0.000000] efi: UEFI not found.
10342 11:05:06.357351 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10343 11:05:06.363629 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10344 11:05:06.373745 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10345 11:05:06.384038 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10346 11:05:06.390112 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10347 11:05:06.396670 [ 0.000000] printk: bootconsole [mtk8250] enabled
10348 11:05:06.403408 [ 0.000000] NUMA: No NUMA configuration found
10349 11:05:06.410285 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10350 11:05:06.413549 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10351 11:05:06.416416 [ 0.000000] Zone ranges:
10352 11:05:06.423131 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10353 11:05:06.426589 [ 0.000000] DMA32 empty
10354 11:05:06.433227 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10355 11:05:06.436178 [ 0.000000] Movable zone start for each node
10356 11:05:06.439725 [ 0.000000] Early memory node ranges
10357 11:05:06.445991 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10358 11:05:06.452820 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10359 11:05:06.459091 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10360 11:05:06.465671 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10361 11:05:06.472357 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10362 11:05:06.479500 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10363 11:05:06.535534 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10364 11:05:06.541882 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10365 11:05:06.548842 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10366 11:05:06.552107 [ 0.000000] psci: probing for conduit method from DT.
10367 11:05:06.558490 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10368 11:05:06.561594 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10369 11:05:06.568160 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10370 11:05:06.571692 [ 0.000000] psci: SMC Calling Convention v1.2
10371 11:05:06.578172 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10372 11:05:06.581443 [ 0.000000] Detected VIPT I-cache on CPU0
10373 11:05:06.588476 [ 0.000000] CPU features: detected: GIC system register CPU interface
10374 11:05:06.594847 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10375 11:05:06.601511 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10376 11:05:06.607886 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10377 11:05:06.617798 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10378 11:05:06.624553 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10379 11:05:06.627533 [ 0.000000] alternatives: applying boot alternatives
10380 11:05:06.634153 [ 0.000000] Fallback order for Node 0: 0
10381 11:05:06.640702 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10382 11:05:06.644200 [ 0.000000] Policy zone: Normal
10383 11:05:06.667875 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786788/extract-nfsrootfs-j6owxqcc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10384 11:05:06.677634 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10385 11:05:06.688234 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10386 11:05:06.698326 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10387 11:05:06.704592 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10388 11:05:06.708082 <6>[ 0.000000] software IO TLB: area num 8.
10389 11:05:06.765490 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10390 11:05:06.915235 <6>[ 0.000000] Memory: 7945788K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406980K reserved, 32768K cma-reserved)
10391 11:05:06.921600 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10392 11:05:06.927977 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10393 11:05:06.931544 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10394 11:05:06.938248 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10395 11:05:06.944565 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10396 11:05:06.948229 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10397 11:05:06.958017 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10398 11:05:06.964332 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10399 11:05:06.970805 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10400 11:05:06.977705 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10401 11:05:06.981229 <6>[ 0.000000] GICv3: 608 SPIs implemented
10402 11:05:06.984454 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10403 11:05:06.990650 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10404 11:05:06.994439 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10405 11:05:07.000931 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10406 11:05:07.014030 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10407 11:05:07.027101 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10408 11:05:07.033473 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10409 11:05:07.042371 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10410 11:05:07.054684 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10411 11:05:07.061155 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10412 11:05:07.068018 <6>[ 0.009226] Console: colour dummy device 80x25
10413 11:05:07.077759 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10414 11:05:07.084760 <6>[ 0.024465] pid_max: default: 32768 minimum: 301
10415 11:05:07.087753 <6>[ 0.029338] LSM: Security Framework initializing
10416 11:05:07.097674 <6>[ 0.034306] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10417 11:05:07.104193 <6>[ 0.042167] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 11:05:07.113945 <6>[ 0.051591] cblist_init_generic: Setting adjustable number of callback queues.
10419 11:05:07.120464 <6>[ 0.059031] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 11:05:07.126976 <6>[ 0.065370] cblist_init_generic: Setting adjustable number of callback queues.
10421 11:05:07.134119 <6>[ 0.072842] cblist_init_generic: Setting shift to 3 and lim to 1.
10422 11:05:07.136925 <6>[ 0.079271] rcu: Hierarchical SRCU implementation.
10423 11:05:07.144076 <6>[ 0.084286] rcu: Max phase no-delay instances is 1000.
10424 11:05:07.150064 <6>[ 0.091320] EFI services will not be available.
10425 11:05:07.153668 <6>[ 0.096251] smp: Bringing up secondary CPUs ...
10426 11:05:07.162501 <6>[ 0.101333] Detected VIPT I-cache on CPU1
10427 11:05:07.168852 <6>[ 0.101405] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10428 11:05:07.175745 <6>[ 0.101435] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10429 11:05:07.178859 <6>[ 0.101782] Detected VIPT I-cache on CPU2
10430 11:05:07.188536 <6>[ 0.101834] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10431 11:05:07.195225 <6>[ 0.101852] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10432 11:05:07.198737 <6>[ 0.102119] Detected VIPT I-cache on CPU3
10433 11:05:07.205421 <6>[ 0.102167] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10434 11:05:07.212709 <6>[ 0.102181] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10435 11:05:07.218486 <6>[ 0.102487] CPU features: detected: Spectre-v4
10436 11:05:07.222090 <6>[ 0.102493] CPU features: detected: Spectre-BHB
10437 11:05:07.225165 <6>[ 0.102499] Detected PIPT I-cache on CPU4
10438 11:05:07.231488 <6>[ 0.102561] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10439 11:05:07.238205 <6>[ 0.102578] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10440 11:05:07.244858 <6>[ 0.102871] Detected PIPT I-cache on CPU5
10441 11:05:07.251319 <6>[ 0.102934] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10442 11:05:07.258272 <6>[ 0.102949] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10443 11:05:07.260907 <6>[ 0.103229] Detected PIPT I-cache on CPU6
10444 11:05:07.271327 <6>[ 0.103294] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10445 11:05:07.277628 <6>[ 0.103309] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10446 11:05:07.281203 <6>[ 0.103604] Detected PIPT I-cache on CPU7
10447 11:05:07.287734 <6>[ 0.103669] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10448 11:05:07.294331 <6>[ 0.103684] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10449 11:05:07.297353 <6>[ 0.103732] smp: Brought up 1 node, 8 CPUs
10450 11:05:07.303999 <6>[ 0.245110] SMP: Total of 8 processors activated.
10451 11:05:07.310743 <6>[ 0.250031] CPU features: detected: 32-bit EL0 Support
10452 11:05:07.317451 <6>[ 0.255394] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10453 11:05:07.324363 <6>[ 0.264250] CPU features: detected: Common not Private translations
10454 11:05:07.330422 <6>[ 0.270766] CPU features: detected: CRC32 instructions
10455 11:05:07.337270 <6>[ 0.276151] CPU features: detected: RCpc load-acquire (LDAPR)
10456 11:05:07.340024 <6>[ 0.282111] CPU features: detected: LSE atomic instructions
10457 11:05:07.346915 <6>[ 0.287928] CPU features: detected: Privileged Access Never
10458 11:05:07.353230 <6>[ 0.293744] CPU features: detected: RAS Extension Support
10459 11:05:07.360165 <6>[ 0.299352] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10460 11:05:07.363521 <6>[ 0.306616] CPU: All CPU(s) started at EL2
10461 11:05:07.369765 <6>[ 0.310933] alternatives: applying system-wide alternatives
10462 11:05:07.380618 <6>[ 0.321804] devtmpfs: initialized
10463 11:05:07.395672 <6>[ 0.330572] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10464 11:05:07.402134 <6>[ 0.340533] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10465 11:05:07.409263 <6>[ 0.348790] pinctrl core: initialized pinctrl subsystem
10466 11:05:07.412072 <6>[ 0.355461] DMI not present or invalid.
10467 11:05:07.418748 <6>[ 0.359873] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10468 11:05:07.428872 <6>[ 0.366765] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10469 11:05:07.435482 <6>[ 0.374355] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10470 11:05:07.445208 <6>[ 0.382586] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10471 11:05:07.451900 <6>[ 0.390832] audit: initializing netlink subsys (disabled)
10472 11:05:07.458545 <5>[ 0.396526] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10473 11:05:07.464704 <6>[ 0.397247] thermal_sys: Registered thermal governor 'step_wise'
10474 11:05:07.471641 <6>[ 0.404494] thermal_sys: Registered thermal governor 'power_allocator'
10475 11:05:07.474903 <6>[ 0.410745] cpuidle: using governor menu
10476 11:05:07.481332 <6>[ 0.421703] NET: Registered PF_QIPCRTR protocol family
10477 11:05:07.487855 <6>[ 0.427221] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10478 11:05:07.494609 <6>[ 0.434323] ASID allocator initialised with 32768 entries
10479 11:05:07.497822 <6>[ 0.440906] Serial: AMBA PL011 UART driver
10480 11:05:07.508907 <4>[ 0.450268] Trying to register duplicate clock ID: 134
10481 11:05:07.566984 <6>[ 0.511566] KASLR enabled
10482 11:05:07.581199 <6>[ 0.519179] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10483 11:05:07.588042 <6>[ 0.526192] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10484 11:05:07.594459 <6>[ 0.532680] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10485 11:05:07.600824 <6>[ 0.539686] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10486 11:05:07.607706 <6>[ 0.546172] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10487 11:05:07.614031 <6>[ 0.553175] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10488 11:05:07.620550 <6>[ 0.559663] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10489 11:05:07.627001 <6>[ 0.566666] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10490 11:05:07.630784 <6>[ 0.574123] ACPI: Interpreter disabled.
10491 11:05:07.639453 <6>[ 0.580558] iommu: Default domain type: Translated
10492 11:05:07.646086 <6>[ 0.585706] iommu: DMA domain TLB invalidation policy: strict mode
10493 11:05:07.649336 <5>[ 0.592358] SCSI subsystem initialized
10494 11:05:07.656133 <6>[ 0.596603] usbcore: registered new interface driver usbfs
10495 11:05:07.662554 <6>[ 0.602333] usbcore: registered new interface driver hub
10496 11:05:07.666076 <6>[ 0.607886] usbcore: registered new device driver usb
10497 11:05:07.672875 <6>[ 0.614003] pps_core: LinuxPPS API ver. 1 registered
10498 11:05:07.682853 <6>[ 0.619193] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10499 11:05:07.686081 <6>[ 0.628533] PTP clock support registered
10500 11:05:07.689252 <6>[ 0.632776] EDAC MC: Ver: 3.0.0
10501 11:05:07.696550 <6>[ 0.637969] FPGA manager framework
10502 11:05:07.703401 <6>[ 0.641647] Advanced Linux Sound Architecture Driver Initialized.
10503 11:05:07.706401 <6>[ 0.648435] vgaarb: loaded
10504 11:05:07.712854 <6>[ 0.651608] clocksource: Switched to clocksource arch_sys_counter
10505 11:05:07.716726 <5>[ 0.658050] VFS: Disk quotas dquot_6.6.0
10506 11:05:07.723071 <6>[ 0.662232] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10507 11:05:07.726230 <6>[ 0.669426] pnp: PnP ACPI: disabled
10508 11:05:07.734855 <6>[ 0.676100] NET: Registered PF_INET protocol family
10509 11:05:07.744577 <6>[ 0.681695] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10510 11:05:07.756138 <6>[ 0.694013] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10511 11:05:07.765924 <6>[ 0.702822] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10512 11:05:07.772254 <6>[ 0.710789] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10513 11:05:07.782189 <6>[ 0.719490] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10514 11:05:07.788933 <6>[ 0.729245] TCP: Hash tables configured (established 65536 bind 65536)
10515 11:05:07.795656 <6>[ 0.736118] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10516 11:05:07.805415 <6>[ 0.743314] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10517 11:05:07.811809 <6>[ 0.751015] NET: Registered PF_UNIX/PF_LOCAL protocol family
10518 11:05:07.818549 <6>[ 0.757162] RPC: Registered named UNIX socket transport module.
10519 11:05:07.821781 <6>[ 0.763317] RPC: Registered udp transport module.
10520 11:05:07.828437 <6>[ 0.768250] RPC: Registered tcp transport module.
10521 11:05:07.834927 <6>[ 0.773182] RPC: Registered tcp NFSv4.1 backchannel transport module.
10522 11:05:07.838553 <6>[ 0.779847] PCI: CLS 0 bytes, default 64
10523 11:05:07.841690 <6>[ 0.784170] Unpacking initramfs...
10524 11:05:07.861774 <6>[ 0.800042] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10525 11:05:07.871777 <6>[ 0.808672] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10526 11:05:07.875098 <6>[ 0.817480] kvm [1]: IPA Size Limit: 40 bits
10527 11:05:07.881847 <6>[ 0.822008] kvm [1]: GICv3: no GICV resource entry
10528 11:05:07.884987 <6>[ 0.827026] kvm [1]: disabling GICv2 emulation
10529 11:05:07.891755 <6>[ 0.831725] kvm [1]: GIC system register CPU interface enabled
10530 11:05:07.894684 <6>[ 0.837886] kvm [1]: vgic interrupt IRQ18
10531 11:05:07.902082 <6>[ 0.842244] kvm [1]: VHE mode initialized successfully
10532 11:05:07.908226 <5>[ 0.848716] Initialise system trusted keyrings
10533 11:05:07.914782 <6>[ 0.853500] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10534 11:05:07.922160 <6>[ 0.863472] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10535 11:05:07.928868 <5>[ 0.869830] NFS: Registering the id_resolver key type
10536 11:05:07.932217 <5>[ 0.875130] Key type id_resolver registered
10537 11:05:07.938676 <5>[ 0.879546] Key type id_legacy registered
10538 11:05:07.945297 <6>[ 0.883819] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10539 11:05:07.951657 <6>[ 0.890742] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10540 11:05:07.958748 <6>[ 0.898441] 9p: Installing v9fs 9p2000 file system support
10541 11:05:07.995957 <5>[ 0.937291] Key type asymmetric registered
10542 11:05:07.999548 <5>[ 0.941620] Asymmetric key parser 'x509' registered
10543 11:05:08.009016 <6>[ 0.946754] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10544 11:05:08.012360 <6>[ 0.954370] io scheduler mq-deadline registered
10545 11:05:08.015865 <6>[ 0.959128] io scheduler kyber registered
10546 11:05:08.035597 <6>[ 0.976139] EINJ: ACPI disabled.
10547 11:05:08.067162 <4>[ 1.001931] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10548 11:05:08.076804 <4>[ 1.012548] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 11:05:08.092257 <6>[ 1.033550] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10550 11:05:08.100215 <6>[ 1.041519] printk: console [ttyS0] disabled
10551 11:05:08.128222 <6>[ 1.066163] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10552 11:05:08.134877 <6>[ 1.075635] printk: console [ttyS0] enabled
10553 11:05:08.138321 <6>[ 1.075635] printk: console [ttyS0] enabled
10554 11:05:08.144376 <6>[ 1.084529] printk: bootconsole [mtk8250] disabled
10555 11:05:08.148142 <6>[ 1.084529] printk: bootconsole [mtk8250] disabled
10556 11:05:08.154774 <6>[ 1.095563] SuperH (H)SCI(F) driver initialized
10557 11:05:08.157953 <6>[ 1.100842] msm_serial: driver initialized
10558 11:05:08.171732 <6>[ 1.109745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10559 11:05:08.181803 <6>[ 1.118292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10560 11:05:08.188159 <6>[ 1.126834] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10561 11:05:08.198116 <6>[ 1.135460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10562 11:05:08.208078 <6>[ 1.144166] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10563 11:05:08.214643 <6>[ 1.152879] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10564 11:05:08.224654 <6>[ 1.161425] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10565 11:05:08.231087 <6>[ 1.170227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10566 11:05:08.240918 <6>[ 1.178768] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10567 11:05:08.253302 <6>[ 1.194437] loop: module loaded
10568 11:05:08.259552 <6>[ 1.200333] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10569 11:05:08.282277 <4>[ 1.223511] mtk-pmic-keys: Failed to locate of_node [id: -1]
10570 11:05:08.289150 <6>[ 1.230299] megasas: 07.719.03.00-rc1
10571 11:05:08.298940 <6>[ 1.239941] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10572 11:05:08.306085 <6>[ 1.246982] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10573 11:05:08.321996 <6>[ 1.263350] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10574 11:05:08.381244 <6>[ 1.316150] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10575 11:05:08.664274 <6>[ 1.606368] Freeing initrd memory: 18268K
10576 11:05:08.676050 <6>[ 1.617927] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10577 11:05:08.687418 <6>[ 1.628939] tun: Universal TUN/TAP device driver, 1.6
10578 11:05:08.690525 <6>[ 1.635007] thunder_xcv, ver 1.0
10579 11:05:08.693935 <6>[ 1.638512] thunder_bgx, ver 1.0
10580 11:05:08.696923 <6>[ 1.642008] nicpf, ver 1.0
10581 11:05:08.707288 <6>[ 1.646029] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10582 11:05:08.711071 <6>[ 1.653505] hns3: Copyright (c) 2017 Huawei Corporation.
10583 11:05:08.717670 <6>[ 1.659094] hclge is initializing
10584 11:05:08.720966 <6>[ 1.662669] e1000: Intel(R) PRO/1000 Network Driver
10585 11:05:08.727807 <6>[ 1.667799] e1000: Copyright (c) 1999-2006 Intel Corporation.
10586 11:05:08.730690 <6>[ 1.673812] e1000e: Intel(R) PRO/1000 Network Driver
10587 11:05:08.737338 <6>[ 1.679027] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10588 11:05:08.744030 <6>[ 1.685212] igb: Intel(R) Gigabit Ethernet Network Driver
10589 11:05:08.750830 <6>[ 1.690861] igb: Copyright (c) 2007-2014 Intel Corporation.
10590 11:05:08.757200 <6>[ 1.696698] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10591 11:05:08.763920 <6>[ 1.703215] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10592 11:05:08.767209 <6>[ 1.709677] sky2: driver version 1.30
10593 11:05:08.773986 <6>[ 1.714615] usbcore: registered new device driver r8152-cfgselector
10594 11:05:08.780427 <6>[ 1.721150] usbcore: registered new interface driver r8152
10595 11:05:08.787563 <6>[ 1.726966] VFIO - User Level meta-driver version: 0.3
10596 11:05:08.793652 <6>[ 1.735185] usbcore: registered new interface driver usb-storage
10597 11:05:08.800159 <6>[ 1.741635] usbcore: registered new device driver onboard-usb-hub
10598 11:05:08.808850 <6>[ 1.750825] mt6397-rtc mt6359-rtc: registered as rtc0
10599 11:05:08.819024 <6>[ 1.756293] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:05:08 UTC (1720609508)
10600 11:05:08.822465 <6>[ 1.765856] i2c_dev: i2c /dev entries driver
10601 11:05:08.835913 <4>[ 1.777925] cpu cpu0: supply cpu not found, using dummy regulator
10602 11:05:08.842734 <4>[ 1.784353] cpu cpu1: supply cpu not found, using dummy regulator
10603 11:05:08.849831 <4>[ 1.790755] cpu cpu2: supply cpu not found, using dummy regulator
10604 11:05:08.856070 <4>[ 1.797156] cpu cpu3: supply cpu not found, using dummy regulator
10605 11:05:08.862804 <4>[ 1.803556] cpu cpu4: supply cpu not found, using dummy regulator
10606 11:05:08.869302 <4>[ 1.809972] cpu cpu5: supply cpu not found, using dummy regulator
10607 11:05:08.875917 <4>[ 1.816369] cpu cpu6: supply cpu not found, using dummy regulator
10608 11:05:08.882514 <4>[ 1.822760] cpu cpu7: supply cpu not found, using dummy regulator
10609 11:05:08.901683 <6>[ 1.843386] cpu cpu0: EM: created perf domain
10610 11:05:08.905112 <6>[ 1.848314] cpu cpu4: EM: created perf domain
10611 11:05:08.912734 <6>[ 1.853925] sdhci: Secure Digital Host Controller Interface driver
10612 11:05:08.919201 <6>[ 1.860357] sdhci: Copyright(c) Pierre Ossman
10613 11:05:08.925461 <6>[ 1.865307] Synopsys Designware Multimedia Card Interface Driver
10614 11:05:08.932401 <6>[ 1.871945] sdhci-pltfm: SDHCI platform and OF driver helper
10615 11:05:08.935469 <6>[ 1.872045] mmc0: CQHCI version 5.10
10616 11:05:08.942422 <6>[ 1.882233] ledtrig-cpu: registered to indicate activity on CPUs
10617 11:05:08.948838 <6>[ 1.889218] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10618 11:05:08.955592 <6>[ 1.896284] usbcore: registered new interface driver usbhid
10619 11:05:08.959071 <6>[ 1.902105] usbhid: USB HID core driver
10620 11:05:08.965480 <6>[ 1.906284] spi_master spi0: will run message pump with realtime priority
10621 11:05:09.011127 <6>[ 1.945633] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10622 11:05:09.029872 <6>[ 1.961064] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10623 11:05:09.032864 <6>[ 1.973790] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10624 11:05:09.040077 <6>[ 1.981446] cros-ec-spi spi0.0: Chrome EC device registered
10625 11:05:09.047047 <6>[ 1.987426] mmc0: Command Queue Engine enabled
10626 11:05:09.053463 <6>[ 1.992160] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10627 11:05:09.056786 <6>[ 1.999677] mmcblk0: mmc0:0001 DA4128 116 GiB
10628 11:05:09.066806 <6>[ 2.008376] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10629 11:05:09.074109 <6>[ 2.015668] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10630 11:05:09.084211 <6>[ 2.020268] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10631 11:05:09.087729 <6>[ 2.021580] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10632 11:05:09.094404 <6>[ 2.031650] NET: Registered PF_PACKET protocol family
10633 11:05:09.101166 <6>[ 2.036097] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10634 11:05:09.103950 <6>[ 2.040822] 9pnet: Installing 9P2000 support
10635 11:05:09.111117 <5>[ 2.051811] Key type dns_resolver registered
10636 11:05:09.113793 <6>[ 2.056737] registered taskstats version 1
10637 11:05:09.120577 <5>[ 2.061115] Loading compiled-in X.509 certificates
10638 11:05:09.148523 <4>[ 2.083156] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 11:05:09.158026 <4>[ 2.093890] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10640 11:05:09.172888 <6>[ 2.114372] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10641 11:05:09.180001 <6>[ 2.121612] xhci-mtk 11200000.usb: xHCI Host Controller
10642 11:05:09.187002 <6>[ 2.127142] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10643 11:05:09.197183 <6>[ 2.135006] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10644 11:05:09.203819 <6>[ 2.144444] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10645 11:05:09.210267 <6>[ 2.150635] xhci-mtk 11200000.usb: xHCI Host Controller
10646 11:05:09.217004 <6>[ 2.156141] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10647 11:05:09.223539 <6>[ 2.163798] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10648 11:05:09.230303 <6>[ 2.171664] hub 1-0:1.0: USB hub found
10649 11:05:09.233891 <6>[ 2.175693] hub 1-0:1.0: 1 port detected
10650 11:05:09.243323 <6>[ 2.179986] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10651 11:05:09.247116 <6>[ 2.188718] hub 2-0:1.0: USB hub found
10652 11:05:09.250323 <6>[ 2.192739] hub 2-0:1.0: 1 port detected
10653 11:05:09.258218 <6>[ 2.199432] mtk-msdc 11f70000.mmc: Got CD GPIO
10654 11:05:09.272277 <6>[ 2.210517] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10655 11:05:09.282460 <6>[ 2.218932] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10656 11:05:09.288739 <6>[ 2.227277] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10657 11:05:09.298923 <6>[ 2.235633] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10658 11:05:09.305563 <6>[ 2.243974] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10659 11:05:09.315491 <6>[ 2.252313] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10660 11:05:09.321787 <6>[ 2.260652] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10661 11:05:09.331726 <6>[ 2.268991] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10662 11:05:09.338727 <6>[ 2.277331] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10663 11:05:09.348323 <6>[ 2.285670] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10664 11:05:09.355045 <6>[ 2.294008] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10665 11:05:09.365096 <6>[ 2.302359] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10666 11:05:09.371779 <6>[ 2.310697] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10667 11:05:09.381637 <6>[ 2.319035] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10668 11:05:09.388128 <6>[ 2.327374] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10669 11:05:09.394661 <6>[ 2.336054] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10670 11:05:09.401594 <6>[ 2.343244] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10671 11:05:09.408596 <6>[ 2.350014] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10672 11:05:09.418471 <6>[ 2.356822] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10673 11:05:09.425222 <6>[ 2.363775] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10674 11:05:09.431593 <6>[ 2.370635] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10675 11:05:09.441584 <6>[ 2.379769] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10676 11:05:09.451701 <6>[ 2.388890] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10677 11:05:09.461669 <6>[ 2.398186] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10678 11:05:09.471470 <6>[ 2.407656] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10679 11:05:09.480979 <6>[ 2.417127] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10680 11:05:09.488109 <6>[ 2.426246] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10681 11:05:09.498040 <6>[ 2.435714] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10682 11:05:09.507787 <6>[ 2.444835] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10683 11:05:09.517370 <6>[ 2.454150] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10684 11:05:09.527643 <6>[ 2.464312] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10685 11:05:09.537762 <6>[ 2.475833] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10686 11:05:09.545227 <6>[ 2.486794] Trying to probe devices needed for running init ...
10687 11:05:09.555373 <3>[ 2.493911] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10688 11:05:09.653621 <6>[ 2.591895] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10689 11:05:09.808981 <6>[ 2.749805] hub 1-1:1.0: USB hub found
10690 11:05:09.811564 <6>[ 2.754322] hub 1-1:1.0: 4 ports detected
10691 11:05:09.823597 <6>[ 2.764914] hub 1-1:1.0: USB hub found
10692 11:05:09.826651 <6>[ 2.769366] hub 1-1:1.0: 4 ports detected
10693 11:05:09.933955 <6>[ 2.872259] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10694 11:05:09.961069 <6>[ 2.902699] hub 2-1:1.0: USB hub found
10695 11:05:09.964402 <6>[ 2.907286] hub 2-1:1.0: 3 ports detected
10696 11:05:09.977173 <6>[ 2.918386] hub 2-1:1.0: USB hub found
10697 11:05:09.979928 <6>[ 2.922776] hub 2-1:1.0: 3 ports detected
10698 11:05:10.150023 <6>[ 3.087977] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10699 11:05:10.282458 <6>[ 3.224033] hub 1-1.4:1.0: USB hub found
10700 11:05:10.285408 <6>[ 3.228685] hub 1-1.4:1.0: 2 ports detected
10701 11:05:10.297739 <6>[ 3.239486] hub 1-1.4:1.0: USB hub found
10702 11:05:10.301259 <6>[ 3.244061] hub 1-1.4:1.0: 2 ports detected
10703 11:05:10.361140 <6>[ 3.300048] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10704 11:05:10.469794 <6>[ 3.408601] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10705 11:05:10.507194 <4>[ 3.445755] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10706 11:05:10.516690 <4>[ 3.454856] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10707 11:05:10.555893 <6>[ 3.497728] r8152 2-1.3:1.0 eth0: v1.12.13
10708 11:05:10.597213 <6>[ 3.536025] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10709 11:05:10.792991 <6>[ 3.731930] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10710 11:05:12.224071 <6>[ 5.166026] r8152 2-1.3:1.0 eth0: carrier on
10711 11:05:14.397387 <5>[ 5.195924] Sending DHCP requests .., OK
10712 11:05:14.403872 <6>[ 7.343923] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10713 11:05:14.407392 <6>[ 7.352210] IP-Config: Complete:
10714 11:05:14.420375 <6>[ 7.355711] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10715 11:05:14.426628 <6>[ 7.366423] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10716 11:05:14.436949 <6>[ 7.375040] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10717 11:05:14.439684 <6>[ 7.375050] nameserver0=192.168.201.1
10718 11:05:14.443239 <6>[ 7.387224] clk: Disabling unused clocks
10719 11:05:14.447028 <6>[ 7.393054] ALSA device list:
10720 11:05:14.453671 <6>[ 7.396296] No soundcards found.
10721 11:05:14.461458 <6>[ 7.403757] Freeing unused kernel memory: 8512K
10722 11:05:14.464539 <6>[ 7.408659] Run /init as init process
10723 11:05:14.474561 Loading, please wait...
10724 11:05:14.500918 Starting systemd-udevd version 252.22-1~deb12u1
10725 11:05:14.750732 <6>[ 7.689705] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10726 11:05:14.761121 <6>[ 7.699268] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10727 11:05:14.770618 <6>[ 7.708192] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10728 11:05:14.789563 <4>[ 7.728103] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10729 11:05:14.796005 <6>[ 7.733964] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10730 11:05:14.803239 <4>[ 7.735765] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10731 11:05:14.813253 <3>[ 7.751921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 11:05:14.820064 <3>[ 7.760075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 11:05:14.829772 <4>[ 7.760421] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10734 11:05:14.836259 <4>[ 7.760421] Fallback method does not support PEC.
10735 11:05:14.842744 <3>[ 7.768159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 11:05:14.849461 <6>[ 7.773434] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10737 11:05:14.859161 <6>[ 7.777389] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10738 11:05:14.862485 <6>[ 7.785175] mc: Linux media interface: v0.10
10739 11:05:14.872144 <3>[ 7.785803] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 11:05:14.878903 <3>[ 7.785818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 11:05:14.885627 <3>[ 7.785821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 11:05:14.895281 <3>[ 7.785828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 11:05:14.901929 <3>[ 7.785832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 11:05:14.909080 <6>[ 7.790068] remoteproc remoteproc0: scp is available
10745 11:05:14.915292 <3>[ 7.792590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:05:14.925434 <3>[ 7.796280] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 11:05:14.932118 <3>[ 7.796310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 11:05:14.941622 <3>[ 7.796320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 11:05:14.948283 <3>[ 7.806171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 11:05:14.955089 <6>[ 7.810037] remoteproc remoteproc0: powering up scp
10751 11:05:14.961815 <6>[ 7.810057] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10752 11:05:14.971352 <6>[ 7.810063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10753 11:05:14.977910 <4>[ 7.810249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10754 11:05:14.987841 <6>[ 7.810903] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10755 11:05:14.994778 <6>[ 7.810907] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10756 11:05:15.004535 <6>[ 7.811973] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10757 11:05:15.011431 <6>[ 7.811987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10758 11:05:15.017668 <6>[ 7.811992] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10759 11:05:15.027379 <6>[ 7.812000] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10760 11:05:15.034169 <3>[ 7.818138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 11:05:15.044265 <6>[ 7.826171] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10762 11:05:15.050851 <6>[ 7.826198] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10763 11:05:15.057980 <6>[ 7.840918] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10764 11:05:15.064295 <3>[ 7.842579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 11:05:15.074479 <3>[ 7.849367] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10766 11:05:15.081382 <6>[ 7.850743] pci_bus 0000:00: root bus resource [bus 00-ff]
10767 11:05:15.087712 <3>[ 7.856778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 11:05:15.098004 <6>[ 7.864394] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10769 11:05:15.104458 <6>[ 7.864430] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10770 11:05:15.114336 <6>[ 7.864441] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10771 11:05:15.121757 <6>[ 7.864509] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10772 11:05:15.127814 <6>[ 7.864528] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10773 11:05:15.134502 <6>[ 7.864605] pci 0000:00:00.0: supports D1 D2
10774 11:05:15.141072 <6>[ 7.864606] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10775 11:05:15.147754 <6>[ 7.865684] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10776 11:05:15.154521 <6>[ 7.865797] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10777 11:05:15.160659 <6>[ 7.865822] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10778 11:05:15.170705 <6>[ 7.865838] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10779 11:05:15.177816 <6>[ 7.865853] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10780 11:05:15.180550 <6>[ 7.865959] pci 0000:01:00.0: supports D1 D2
10781 11:05:15.187374 <6>[ 7.865960] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10782 11:05:15.196980 <3>[ 7.872051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 11:05:15.203768 <3>[ 7.872559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 11:05:15.210679 <6>[ 7.875672] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10785 11:05:15.220272 <6>[ 7.875710] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10786 11:05:15.227264 <6>[ 7.875714] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10787 11:05:15.236582 <6>[ 7.875725] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10788 11:05:15.243382 <6>[ 7.875738] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10789 11:05:15.249851 <6>[ 7.875751] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10790 11:05:15.256159 <6>[ 7.875763] pci 0000:00:00.0: PCI bridge to [bus 01]
10791 11:05:15.262550 <6>[ 7.875767] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10792 11:05:15.269187 <6>[ 7.875896] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10793 11:05:15.276106 <6>[ 7.876393] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10794 11:05:15.282923 <6>[ 7.876602] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10795 11:05:15.292604 <6>[ 7.881996] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10796 11:05:15.302386 <6>[ 7.883373] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10797 11:05:15.308709 <6>[ 7.952040] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10798 11:05:15.315995 <6>[ 7.958295] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10799 11:05:15.322126 <6>[ 7.975771] videodev: Linux video capture interface: v2.00
10800 11:05:15.332086 <6>[ 7.977940] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10801 11:05:15.338625 <6>[ 7.981387] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10802 11:05:15.345604 <6>[ 7.983328] remoteproc remoteproc0: remote processor scp is now up
10803 11:05:15.348454 <6>[ 8.005793] Bluetooth: Core ver 2.22
10804 11:05:15.358490 <5>[ 8.014769] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10805 11:05:15.361605 <6>[ 8.021194] NET: Registered PF_BLUETOOTH protocol family
10806 11:05:15.368386 <6>[ 8.021197] Bluetooth: HCI device and connection manager initialized
10807 11:05:15.375384 <6>[ 8.021217] Bluetooth: HCI socket layer initialized
10808 11:05:15.378229 <6>[ 8.021221] Bluetooth: L2CAP socket layer initialized
10809 11:05:15.384866 <6>[ 8.021246] Bluetooth: SCO socket layer initialized
10810 11:05:15.391362 <6>[ 8.063181] usbcore: registered new interface driver btusb
10811 11:05:15.401212 <4>[ 8.063562] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10812 11:05:15.408252 <3>[ 8.063570] Bluetooth: hci0: Failed to load firmware file (-2)
10813 11:05:15.411327 <3>[ 8.063573] Bluetooth: hci0: Failed to set up firmware (-2)
10814 11:05:15.424388 <4>[ 8.063575] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10815 11:05:15.430904 <3>[ 8.069316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10816 11:05:15.437798 <6>[ 8.069656] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10817 11:05:15.451037 <6>[ 8.070795] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10818 11:05:15.457315 <6>[ 8.070968] usbcore: registered new interface driver uvcvideo
10819 11:05:15.463945 <6>[ 8.077797] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10820 11:05:15.470700 <5>[ 8.084741] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10821 11:05:15.480563 <5>[ 8.418581] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10822 11:05:15.487162 <4>[ 8.427003] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10823 11:05:15.493389 <6>[ 8.435912] cfg80211: failed to load regulatory.db
10824 11:05:15.534340 <6>[ 8.473452] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10825 11:05:15.540629 <6>[ 8.480954] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10826 11:05:15.564921 <6>[ 8.507754] mt7921e 0000:01:00.0: ASIC revision: 79610010
10827 11:05:15.667950 <6>[ 8.607245] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10828 11:05:15.671261 <6>[ 8.607245]
10829 11:05:15.674510 Begin: Loading essential drivers ... done.
10830 11:05:15.677889 Begin: Running /scripts/init-premount ... done.
10831 11:05:15.684170 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10832 11:05:15.694134 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10833 11:05:15.698083 Device /sys/class/net/eth0 found
10834 11:05:15.698159 done.
10835 11:05:15.704205 Begin: Waiting up to 180 secs for any network device to become available ... done.
10836 11:05:15.741721 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10837 11:05:15.748127 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10838 11:05:15.754603 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10839 11:05:15.760983 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10840 11:05:15.767614 host : mt8192-asurada-spherion-r0-cbg-9
10841 11:05:15.774185 domain : lava-rack
10842 11:05:15.777789 rootserver: 192.168.201.1 rootpath:
10843 11:05:15.777867 filename :
10844 11:05:15.796177 done.
10845 11:05:15.805409 Begin: Running /scripts/nfs-bottom ... done.
10846 11:05:15.824860 Begin: Running /scripts/init-bottom ... done.
10847 11:05:15.934799 <6>[ 8.874136] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10848 11:05:17.209290 <6>[ 10.151962] NET: Registered PF_INET6 protocol family
10849 11:05:17.216686 <6>[ 10.159644] Segment Routing with IPv6
10850 11:05:17.220173 <6>[ 10.163653] In-situ OAM (IOAM) with IPv6
10851 11:05:17.402211 <30>[ 10.318068] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10852 11:05:17.408858 <30>[ 10.351212] systemd[1]: Detected architecture arm64.
10853 11:05:17.418378
10854 11:05:17.422046 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10855 11:05:17.422185
10856 11:05:17.447310 <30>[ 10.390026] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10857 11:05:18.630729 <30>[ 11.570255] systemd[1]: Queued start job for default target graphical.target.
10858 11:05:18.674732 <30>[ 11.614076] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10859 11:05:18.680625 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10860 11:05:18.702543 <30>[ 11.642159] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10861 11:05:18.712549 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10862 11:05:18.730533 <30>[ 11.670024] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10863 11:05:18.740370 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10864 11:05:18.758566 <30>[ 11.698220] systemd[1]: Created slice user.slice - User and Session Slice.
10865 11:05:18.765258 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10866 11:05:18.788721 <30>[ 11.724867] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10867 11:05:18.798848 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10868 11:05:18.820810 <30>[ 11.756833] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10869 11:05:18.827342 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10870 11:05:18.854581 <30>[ 11.784253] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10871 11:05:18.864466 <30>[ 11.804145] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10872 11:05:18.870902 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10873 11:05:18.888062 <30>[ 11.827947] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10874 11:05:18.895118 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10875 11:05:18.912039 <30>[ 11.852013] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10876 11:05:18.921814 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10877 11:05:18.937570 <30>[ 11.880530] systemd[1]: Reached target paths.target - Path Units.
10878 11:05:18.947235 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10879 11:05:18.964826 <30>[ 11.904389] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10880 11:05:18.971149 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10881 11:05:18.985053 <30>[ 11.927926] systemd[1]: Reached target slices.target - Slice Units.
10882 11:05:18.995100 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10883 11:05:19.009122 <30>[ 11.952321] systemd[1]: Reached target swap.target - Swaps.
10884 11:05:19.015949 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10885 11:05:19.036814 <30>[ 11.976454] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10886 11:05:19.046371 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10887 11:05:19.065549 <30>[ 12.004974] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10888 11:05:19.075196 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10889 11:05:19.094949 <30>[ 12.034515] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10890 11:05:19.104732 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10891 11:05:19.121586 <30>[ 12.061375] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10892 11:05:19.131625 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10893 11:05:19.149177 <30>[ 12.088655] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10894 11:05:19.155856 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10895 11:05:19.173118 <30>[ 12.113069] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10896 11:05:19.182972 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10897 11:05:19.203260 <30>[ 12.142969] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10898 11:05:19.213206 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10899 11:05:19.228557 <30>[ 12.168494] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10900 11:05:19.238405 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10901 11:05:19.280195 <30>[ 12.219984] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10902 11:05:19.287088 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10903 11:05:19.309243 <30>[ 12.248919] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10904 11:05:19.315821 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10905 11:05:19.341705 <30>[ 12.281424] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10906 11:05:19.348132 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10907 11:05:19.374963 <30>[ 12.308272] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10908 11:05:19.404720 <30>[ 12.344620] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10909 11:05:19.414843 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10910 11:05:19.438376 <30>[ 12.378181] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10911 11:05:19.444810 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10912 11:05:19.469990 <30>[ 12.409947] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10913 11:05:19.476657 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10914 11:05:19.502228 <30>[ 12.442252] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10915 11:05:19.512720 Startin<6>[ 12.451694] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10916 11:05:19.518742 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10917 11:05:19.572902 <30>[ 12.512802] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10918 11:05:19.583149 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10919 11:05:19.603727 <30>[ 12.543380] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10920 11:05:19.610249 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10921 11:05:19.632742 <30>[ 12.572708] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10922 11:05:19.639312 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10923 11:05:19.662856 <6>[ 12.606184] fuse: init (API version 7.37)
10924 11:05:19.692939 <30>[ 12.632524] systemd[1]: Starting systemd-journald.service - Journal Service...
10925 11:05:19.699063 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10926 11:05:19.724579 <30>[ 12.664541] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10927 11:05:19.731139 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10928 11:05:19.760737 <30>[ 12.696971] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10929 11:05:19.766845 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10930 11:05:19.817188 <30>[ 12.756770] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10931 11:05:19.826911 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10932 11:05:19.849863 <30>[ 12.789760] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10933 11:05:19.856789 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10934 11:05:19.881059 <30>[ 12.821093] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10935 11:05:19.887682 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10936 11:05:19.908753 <30>[ 12.848412] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10937 11:05:19.922241 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 12.862106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 11:05:19.925566 X Message Queue File System.
10939 11:05:19.945079 <30>[ 12.884837] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10940 11:05:19.952087 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10941 11:05:19.961740 <3>[ 12.901670] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 11:05:19.973258 <30>[ 12.912949] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10943 11:05:19.983169 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10944 11:05:19.997711 <3>[ 12.937415] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 11:05:20.010220 <30>[ 12.950095] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10946 11:05:20.020073 <30>[ 12.958374] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10947 11:05:20.026497 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10948 11:05:20.045255 <3>[ 12.985046] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 11:05:20.055538 <30>[ 12.995507] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10950 11:05:20.062693 <30>[ 13.003254] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10951 11:05:20.079474 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Mo<3>[ 13.017611] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:05:20.079620 dule dm_mod.
10953 11:05:20.094838 <30>[ 13.037594] systemd[1]: modprobe@drm.service: Deactivated successfully.
10954 11:05:20.105090 <30>[ 13.045070] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10955 11:05:20.114761 <3>[ 13.049866] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 11:05:20.121365 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10957 11:05:20.141301 <30>[ 13.081013] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10958 11:05:20.148250 <3>[ 13.083858] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:05:20.157918 <30>[ 13.089494] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10960 11:05:20.167942 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10961 11:05:20.180174 <3>[ 13.119845] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:05:20.190961 <30>[ 13.130916] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10963 11:05:20.197270 <30>[ 13.138872] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10964 11:05:20.207919 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10965 11:05:20.214315 <3>[ 13.154022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 11:05:20.226277 <30>[ 13.165687] systemd[1]: modprobe@loop.service: Deactivated successfully.
10967 11:05:20.232503 <30>[ 13.174004] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10968 11:05:20.245581 [[0;32m OK [0m] Finished [0;1;39mmodprobe@l<3>[ 13.185907] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 11:05:20.252491 oop.service[0m - Load Kernel Module loop.
10970 11:05:20.270980 <30>[ 13.209800] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10971 11:05:20.287111 [[0;32m OK [<4>[ 13.219164] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10972 11:05:20.294116 0m] Finished [0<3>[ 13.235092] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10973 11:05:20.301017 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10974 11:05:20.325296 <30>[ 13.261317] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10975 11:05:20.332206 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10976 11:05:20.353020 <30>[ 13.292642] systemd[1]: Started systemd-journald.service - Journal Service.
10977 11:05:20.359617 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10978 11:05:20.381696 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10979 11:05:20.402155 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10980 11:05:20.423907 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10981 11:05:20.468933 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10982 11:05:20.487090 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10983 11:05:20.511801 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10984 11:05:20.537127 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10985 11:05:20.575778 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10986 11:05:20.598538 <46>[ 13.538258] systemd-journald[310]: Received client request to flush runtime journal.
10987 11:05:20.605110 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10988 11:05:20.643042 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10989 11:05:20.661185 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10990 11:05:20.682091 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10991 11:05:20.702208 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10992 11:05:21.710813 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10993 11:05:21.757063 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10994 11:05:22.009839 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10995 11:05:22.139725 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10996 11:05:22.161441 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10997 11:05:22.184555 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10998 11:05:22.229407 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10999 11:05:22.255379 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11000 11:05:22.504653 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11001 11:05:22.562682 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11002 11:05:22.620048 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11003 11:05:22.912971 <6>[ 15.856478] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11004 11:05:22.930630 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11005 11:05:22.982805 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11006 11:05:23.007194 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11007 11:05:23.064692 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11008 11:05:23.140201 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11009 11:05:23.171750 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11010 11:05:23.194640 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11011 11:05:23.237077 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11012 11:05:23.262063 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11013 11:05:23.281010 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11014 11:05:23.308448 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11015 11:05:23.352987 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11016 11:05:23.390244 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11017 11:05:23.408607 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11018 11:05:23.432267 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11019 11:05:23.452243 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11020 11:05:23.481163 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11021 11:05:23.530513 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11022 11:05:23.548499 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11023 11:05:23.568558 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11024 11:05:23.588662 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11025 11:05:23.604664 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11026 11:05:23.628008 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11027 11:05:23.644459 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11028 11:05:23.660766 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11029 11:05:23.710224 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11030 11:05:23.811380 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11031 11:05:23.919213 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11032 11:05:23.955094 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11033 11:05:23.975146 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11034 11:05:24.013360 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11035 11:05:24.035546 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11036 11:05:24.118036 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11037 11:05:24.165377 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11038 11:05:24.185230 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11039 11:05:24.206525 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11040 11:05:24.265649 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11041 11:05:24.292562 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11042 11:05:24.313153 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11043 11:05:24.380581 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11044 11:05:24.467813 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11045 11:05:24.553790
11046 11:05:24.557167 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11047 11:05:24.557703
11048 11:05:24.560043 debian-bookworm-arm64 login: root (automatic login)
11049 11:05:24.560544
11050 11:05:24.861046 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11051 11:05:24.861538
11052 11:05:24.867554 The programs included with the Debian GNU/Linux system are free software;
11053 11:05:24.874466 the exact distribution terms for each program are described in the
11054 11:05:24.877162 individual files in /usr/share/doc/*/copyright.
11055 11:05:24.877579
11056 11:05:24.883922 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11057 11:05:24.887235 permitted by applicable law.
11058 11:05:25.030223 Matched prompt #10: / #
11060 11:05:25.031197 Setting prompt string to ['/ #']
11061 11:05:25.031628 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11063 11:05:25.032531 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11064 11:05:25.032921 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
11065 11:05:25.033221 Setting prompt string to ['/ #']
11066 11:05:25.033495 Forcing a shell prompt, looking for ['/ #']
11067 11:05:25.033782 Sending line: ''
11069 11:05:25.084753 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11070 11:05:25.085123 Waiting using forced prompt support (timeout 00:02:30)
11071 11:05:25.089731 / #
11072 11:05:25.090462 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11073 11:05:25.090928 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
11074 11:05:25.091277 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786788/extract-nfsrootfs-j6owxqcc'"
11076 11:05:25.198049 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786788/extract-nfsrootfs-j6owxqcc'
11077 11:05:25.198661 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11079 11:05:25.305526 / # export NFS_SERVER_IP='192.168.201.1'
11080 11:05:25.306281 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11081 11:05:25.306738 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11082 11:05:25.307165 end: 2 depthcharge-action (duration 00:01:44) [common]
11083 11:05:25.307634 start: 3 lava-test-retry (timeout 00:01:00) [common]
11084 11:05:25.308047 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11085 11:05:25.308400 Using namespace: common
11086 11:05:25.308738 Sending line: '#'
11088 11:05:25.409934 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11089 11:05:25.415173 / # #
11090 11:05:25.415946 Using /lava-14786788
11091 11:05:25.416299 Sending line: 'export SHELL=/bin/sh'
11093 11:05:25.522540 / # export SHELL=/bin/sh
11094 11:05:25.523156 Sending line: '. /lava-14786788/environment'
11096 11:05:25.629910 / # . /lava-14786788/environment
11097 11:05:25.636961 Sending line: '/lava-14786788/bin/lava-test-runner /lava-14786788/0'
11099 11:05:25.738276 Test shell timeout: 10s (minimum of the action and connection timeout)
11100 11:05:25.744102 / # /lava-14786788/bin/lava-test-runner /lava-14786788/0
11101 11:05:26.043153 + export TESTRUN_ID=0_dmesg
11102 11:05:26.046150 + cd /lava-14786788/0/tests/0_dmesg
11103 11:05:26.049923 + cat uuid
11104 11:05:26.070319 + UUID=14786788_<8>[ 19.010366] <LAVA_SIGNAL_STARTRUN 0_dmesg 14786788_1.6.2.3.1>
11105 11:05:26.070715 1.6.2.3.1
11106 11:05:26.071181 + set +x
11107 11:05:26.071793 Received signal: <STARTRUN> 0_dmesg 14786788_1.6.2.3.1
11108 11:05:26.072144 Starting test lava.0_dmesg (14786788_1.6.2.3.1)
11109 11:05:26.072523 Skipping test definition patterns.
11110 11:05:26.076630 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11111 11:05:26.214713 <8>[ 19.154698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11112 11:05:26.215410 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11114 11:05:26.315935 <8>[ 19.255810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11115 11:05:26.316596 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11117 11:05:26.414510 <8>[ 19.355273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11118 11:05:26.414803 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11120 11:05:26.418045 + set +x
11121 11:05:26.421560 Received signal: <ENDRUN> 0_dmesg 14786788_1.6.2.3.1
11122 11:05:26.421732 Ending use of test pattern.
11123 11:05:26.421820 Ending test lava.0_dmesg (14786788_1.6.2.3.1), duration 0.35
11125 11:05:26.424699 <8>[ 19.365128] <LAVA_SIGNAL_ENDRUN 0_dmesg 14786788_1.6.2.3.1>
11126 11:05:26.428196 <LAVA_TEST_RUNNER EXIT>
11127 11:05:26.428525 ok: lava_test_shell seems to have completed
11128 11:05:26.428721 crit: pass
alert: pass
emerg: pass
11129 11:05:26.428852 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11130 11:05:26.428976 end: 3 lava-test-retry (duration 00:00:01) [common]
11131 11:05:26.429103 start: 4 finalize (timeout 00:07:48) [common]
11132 11:05:26.429239 start: 4.1 power-off (timeout 00:00:30) [common]
11133 11:05:26.429434 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11134 11:05:28.545493 >> Command sent successfully.
11135 11:05:28.548680 Returned 0 in 2 seconds
11136 11:05:28.548812 end: 4.1 power-off (duration 00:00:02) [common]
11138 11:05:28.549006 start: 4.2 read-feedback (timeout 00:07:46) [common]
11139 11:05:28.549141 Listened to connection for namespace 'common' for up to 1s
11140 11:05:29.550333 Finalising connection for namespace 'common'
11141 11:05:29.550850 Disconnecting from shell: Finalise
11142 11:05:29.551167 / #
11143 11:05:29.651963 end: 4.2 read-feedback (duration 00:00:01) [common]
11144 11:05:29.652550 end: 4 finalize (duration 00:00:03) [common]
11145 11:05:29.653128 Cleaning after the job
11146 11:05:29.653670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/ramdisk
11147 11:05:29.662967 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/kernel
11148 11:05:29.697369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/dtb
11149 11:05:29.697780 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/nfsrootfs
11150 11:05:29.761030 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786788/tftp-deploy-nbkabym0/modules
11151 11:05:29.766503 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786788
11152 11:05:30.077090 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786788
11153 11:05:30.077253 Job finished correctly