Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:06:03.944562 lava-dispatcher, installed at version: 2024.05
2 11:06:03.944754 start: 0 validate
3 11:06:03.944875 Start time: 2024-07-10 11:06:03.944869+00:00 (UTC)
4 11:06:03.945004 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:06:03.945162 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:06:04.214291 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:06:04.214448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:06:04.481712 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:06:04.482512 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:06:04.754168 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:06:04.754749 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:06:05.031210 validate duration: 1.09
14 11:06:05.032426 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:06:05.032935 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:06:05.033442 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:06:05.034214 Not decompressing ramdisk as can be used compressed.
18 11:06:05.034739 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 11:06:05.035107 saving as /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/ramdisk/rootfs.cpio.gz
20 11:06:05.035452 total size: 47897469 (45 MB)
21 11:06:05.040841 progress 0 % (0 MB)
22 11:06:05.077108 progress 5 % (2 MB)
23 11:06:05.092420 progress 10 % (4 MB)
24 11:06:05.104353 progress 15 % (6 MB)
25 11:06:05.116014 progress 20 % (9 MB)
26 11:06:05.127512 progress 25 % (11 MB)
27 11:06:05.139152 progress 30 % (13 MB)
28 11:06:05.150716 progress 35 % (16 MB)
29 11:06:05.162680 progress 40 % (18 MB)
30 11:06:05.174429 progress 45 % (20 MB)
31 11:06:05.186084 progress 50 % (22 MB)
32 11:06:05.197987 progress 55 % (25 MB)
33 11:06:05.209786 progress 60 % (27 MB)
34 11:06:05.221428 progress 65 % (29 MB)
35 11:06:05.233059 progress 70 % (32 MB)
36 11:06:05.244850 progress 75 % (34 MB)
37 11:06:05.256464 progress 80 % (36 MB)
38 11:06:05.268082 progress 85 % (38 MB)
39 11:06:05.280136 progress 90 % (41 MB)
40 11:06:05.291997 progress 95 % (43 MB)
41 11:06:05.303540 progress 100 % (45 MB)
42 11:06:05.303772 45 MB downloaded in 0.27 s (170.23 MB/s)
43 11:06:05.303931 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:06:05.304146 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:06:05.304226 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:06:05.304301 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:06:05.304433 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:06:05.304494 saving as /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/kernel/Image
50 11:06:05.304546 total size: 54813184 (52 MB)
51 11:06:05.304598 No compression specified
52 11:06:05.305718 progress 0 % (0 MB)
53 11:06:05.318990 progress 5 % (2 MB)
54 11:06:05.332649 progress 10 % (5 MB)
55 11:06:05.345894 progress 15 % (7 MB)
56 11:06:05.359352 progress 20 % (10 MB)
57 11:06:05.372883 progress 25 % (13 MB)
58 11:06:05.386318 progress 30 % (15 MB)
59 11:06:05.400022 progress 35 % (18 MB)
60 11:06:05.413484 progress 40 % (20 MB)
61 11:06:05.426731 progress 45 % (23 MB)
62 11:06:05.440236 progress 50 % (26 MB)
63 11:06:05.453684 progress 55 % (28 MB)
64 11:06:05.466821 progress 60 % (31 MB)
65 11:06:05.480020 progress 65 % (34 MB)
66 11:06:05.493468 progress 70 % (36 MB)
67 11:06:05.506787 progress 75 % (39 MB)
68 11:06:05.520084 progress 80 % (41 MB)
69 11:06:05.533361 progress 85 % (44 MB)
70 11:06:05.546581 progress 90 % (47 MB)
71 11:06:05.559793 progress 95 % (49 MB)
72 11:06:05.572843 progress 100 % (52 MB)
73 11:06:05.573073 52 MB downloaded in 0.27 s (194.67 MB/s)
74 11:06:05.573219 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:06:05.573467 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:06:05.573547 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:06:05.573622 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:06:05.573746 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:06:05.573806 saving as /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/dtb/mt8192-asurada-spherion-r0.dtb
81 11:06:05.573857 total size: 47258 (0 MB)
82 11:06:05.573909 No compression specified
83 11:06:05.574902 progress 69 % (0 MB)
84 11:06:05.575154 progress 100 % (0 MB)
85 11:06:05.575295 0 MB downloaded in 0.00 s (31.40 MB/s)
86 11:06:05.575404 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:06:05.575600 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:06:05.575676 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:06:05.575749 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:06:05.575852 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:06:05.575911 saving as /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/modules/modules.tar
93 11:06:05.575963 total size: 8607984 (8 MB)
94 11:06:05.576016 Using unxz to decompress xz
95 11:06:05.577315 progress 0 % (0 MB)
96 11:06:05.597546 progress 5 % (0 MB)
97 11:06:05.621325 progress 10 % (0 MB)
98 11:06:05.644940 progress 15 % (1 MB)
99 11:06:05.668710 progress 20 % (1 MB)
100 11:06:05.691859 progress 25 % (2 MB)
101 11:06:05.715235 progress 30 % (2 MB)
102 11:06:05.738341 progress 35 % (2 MB)
103 11:06:05.764579 progress 40 % (3 MB)
104 11:06:05.789312 progress 45 % (3 MB)
105 11:06:05.814056 progress 50 % (4 MB)
106 11:06:05.839104 progress 55 % (4 MB)
107 11:06:05.863555 progress 60 % (4 MB)
108 11:06:05.886480 progress 65 % (5 MB)
109 11:06:05.911253 progress 70 % (5 MB)
110 11:06:05.937625 progress 75 % (6 MB)
111 11:06:05.964531 progress 80 % (6 MB)
112 11:06:05.987514 progress 85 % (7 MB)
113 11:06:06.010179 progress 90 % (7 MB)
114 11:06:06.033184 progress 95 % (7 MB)
115 11:06:06.055417 progress 100 % (8 MB)
116 11:06:06.060584 8 MB downloaded in 0.48 s (16.94 MB/s)
117 11:06:06.060741 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:06:06.060951 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:06:06.061030 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:06:06.061106 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:06:06.061179 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:06:06.061280 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:06:06.061459 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0
125 11:06:06.061575 makedir: /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin
126 11:06:06.061664 makedir: /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/tests
127 11:06:06.061749 makedir: /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/results
128 11:06:06.061834 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-add-keys
129 11:06:06.061961 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-add-sources
130 11:06:06.062074 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-background-process-start
131 11:06:06.062189 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-background-process-stop
132 11:06:06.062313 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-common-functions
133 11:06:06.062427 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-echo-ipv4
134 11:06:06.062542 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-install-packages
135 11:06:06.062667 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-installed-packages
136 11:06:06.062778 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-os-build
137 11:06:06.062888 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-probe-channel
138 11:06:06.062996 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-probe-ip
139 11:06:06.063103 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-target-ip
140 11:06:06.063210 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-target-mac
141 11:06:06.063316 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-target-storage
142 11:06:06.063430 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-test-case
143 11:06:06.063538 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-test-event
144 11:06:06.063647 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-test-feedback
145 11:06:06.063754 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-test-raise
146 11:06:06.063866 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-test-reference
147 11:06:06.063988 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-test-runner
148 11:06:06.064097 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-test-set
149 11:06:06.064205 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-test-shell
150 11:06:06.064313 Updating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-install-packages (oe)
151 11:06:06.064448 Updating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/bin/lava-installed-packages (oe)
152 11:06:06.064554 Creating /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/environment
153 11:06:06.064639 LAVA metadata
154 11:06:06.064699 - LAVA_JOB_ID=14786845
155 11:06:06.064753 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:06:06.064839 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:06:06.064896 skipped lava-vland-overlay
158 11:06:06.064961 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:06:06.065029 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:06:06.065081 skipped lava-multinode-overlay
161 11:06:06.065143 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:06:06.065210 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:06:06.065320 Loading test definitions
164 11:06:06.065395 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:06:06.065455 Using /lava-14786845 at stage 0
166 11:06:06.065738 uuid=14786845_1.5.2.3.1 testdef=None
167 11:06:06.065824 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:06:06.065899 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:06:06.066323 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:06:06.066523 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:06:06.067070 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:06:06.067273 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:06:06.067812 runner path: /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/0/tests/0_igt-gpu-panfrost test_uuid 14786845_1.5.2.3.1
176 11:06:06.067969 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:06:06.068196 Creating lava-test-runner.conf files
179 11:06:06.068252 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786845/lava-overlay-95hxbcy0/lava-14786845/0 for stage 0
180 11:06:06.068331 - 0_igt-gpu-panfrost
181 11:06:06.068417 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:06:06.068491 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:06:06.074727 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:06:06.074822 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:06:06.074899 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:06:06.074975 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:06:06.075049 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:06:07.605177 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 11:06:07.605331 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 11:06:07.605410 extracting modules file /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786845/extract-overlay-ramdisk-mhw_bpq9/ramdisk
191 11:06:07.831143 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:06:07.831270 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:06:07.831346 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786845/compress-overlay-t_z3u06y/overlay-1.5.2.4.tar.gz to ramdisk
194 11:06:07.831405 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786845/compress-overlay-t_z3u06y/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786845/extract-overlay-ramdisk-mhw_bpq9/ramdisk
195 11:06:07.837795 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:06:07.837892 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:06:07.837992 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:06:07.838105 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:06:07.838169 Building ramdisk /var/lib/lava/dispatcher/tmp/14786845/extract-overlay-ramdisk-mhw_bpq9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786845/extract-overlay-ramdisk-mhw_bpq9/ramdisk
200 11:06:08.842902 >> 465428 blocks
201 11:06:15.142446 rename /var/lib/lava/dispatcher/tmp/14786845/extract-overlay-ramdisk-mhw_bpq9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/ramdisk/ramdisk.cpio.gz
202 11:06:15.142619 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:06:15.142706 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 11:06:15.142784 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 11:06:15.142863 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/kernel/Image']
206 11:06:29.534511 Returned 0 in 14 seconds
207 11:06:29.534677 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/kernel/image.itb
208 11:06:30.395078 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:06:30.395209 output: Created: Wed Jul 10 12:06:30 2024
210 11:06:30.395270 output: Image 0 (kernel-1)
211 11:06:30.395325 output: Description:
212 11:06:30.395376 output: Created: Wed Jul 10 12:06:30 2024
213 11:06:30.395428 output: Type: Kernel Image
214 11:06:30.395477 output: Compression: lzma compressed
215 11:06:30.395529 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
216 11:06:30.395579 output: Architecture: AArch64
217 11:06:30.395627 output: OS: Linux
218 11:06:30.395686 output: Load Address: 0x00000000
219 11:06:30.395765 output: Entry Point: 0x00000000
220 11:06:30.395813 output: Hash algo: crc32
221 11:06:30.395862 output: Hash value: 9bb85fb9
222 11:06:30.395911 output: Image 1 (fdt-1)
223 11:06:30.395959 output: Description: mt8192-asurada-spherion-r0
224 11:06:30.396008 output: Created: Wed Jul 10 12:06:30 2024
225 11:06:30.396056 output: Type: Flat Device Tree
226 11:06:30.396104 output: Compression: uncompressed
227 11:06:30.396152 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:06:30.396200 output: Architecture: AArch64
229 11:06:30.396249 output: Hash algo: crc32
230 11:06:30.396296 output: Hash value: 0f8e4d2e
231 11:06:30.396343 output: Image 2 (ramdisk-1)
232 11:06:30.396390 output: Description: unavailable
233 11:06:30.396437 output: Created: Wed Jul 10 12:06:30 2024
234 11:06:30.396484 output: Type: RAMDisk Image
235 11:06:30.396532 output: Compression: uncompressed
236 11:06:30.396579 output: Data Size: 60979880 Bytes = 59550.66 KiB = 58.15 MiB
237 11:06:30.396627 output: Architecture: AArch64
238 11:06:30.396675 output: OS: Linux
239 11:06:30.396722 output: Load Address: unavailable
240 11:06:30.396769 output: Entry Point: unavailable
241 11:06:30.396816 output: Hash algo: crc32
242 11:06:30.396863 output: Hash value: 5086688d
243 11:06:30.396911 output: Default Configuration: 'conf-1'
244 11:06:30.396958 output: Configuration 0 (conf-1)
245 11:06:30.397005 output: Description: mt8192-asurada-spherion-r0
246 11:06:30.397051 output: Kernel: kernel-1
247 11:06:30.397098 output: Init Ramdisk: ramdisk-1
248 11:06:30.397145 output: FDT: fdt-1
249 11:06:30.397193 output: Loadables: kernel-1
250 11:06:30.397252 output:
251 11:06:30.397357 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 11:06:30.397431 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 11:06:30.397504 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 11:06:30.397578 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 11:06:30.397635 No LXC device requested
256 11:06:30.397703 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:06:30.397773 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 11:06:30.397840 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:06:30.397895 Checking files for TFTP limit of 4294967296 bytes.
260 11:06:30.398259 end: 1 tftp-deploy (duration 00:00:25) [common]
261 11:06:30.398347 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:06:30.398425 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:06:30.398512 substitutions:
264 11:06:30.398572 - {DTB}: 14786845/tftp-deploy-xcyw_x31/dtb/mt8192-asurada-spherion-r0.dtb
265 11:06:30.398628 - {INITRD}: 14786845/tftp-deploy-xcyw_x31/ramdisk/ramdisk.cpio.gz
266 11:06:30.398680 - {KERNEL}: 14786845/tftp-deploy-xcyw_x31/kernel/Image
267 11:06:30.398731 - {LAVA_MAC}: None
268 11:06:30.398781 - {PRESEED_CONFIG}: None
269 11:06:30.398830 - {PRESEED_LOCAL}: None
270 11:06:30.398879 - {RAMDISK}: 14786845/tftp-deploy-xcyw_x31/ramdisk/ramdisk.cpio.gz
271 11:06:30.398933 - {ROOT_PART}: None
272 11:06:30.398982 - {ROOT}: None
273 11:06:30.399032 - {SERVER_IP}: 192.168.201.1
274 11:06:30.399080 - {TEE}: None
275 11:06:30.399129 Parsed boot commands:
276 11:06:30.399176 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:06:30.399314 Parsed boot commands: tftpboot 192.168.201.1 14786845/tftp-deploy-xcyw_x31/kernel/image.itb 14786845/tftp-deploy-xcyw_x31/kernel/cmdline
278 11:06:30.399392 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:06:30.399466 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:06:30.399537 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:06:30.399607 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:06:30.399662 Not connected, no need to disconnect.
283 11:06:30.399726 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:06:30.399793 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:06:30.399854 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:06:30.402757 Setting prompt string to ['lava-test: # ']
287 11:06:30.403058 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:06:30.403148 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:06:30.403231 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:06:30.403307 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:06:30.403519 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
292 11:06:39.642233 >> Command sent successfully.
293 11:06:39.656821 Returned 0 in 9 seconds
294 11:06:39.657518 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:06:39.658675 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:06:39.659078 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:06:39.659416 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:06:39.659690 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:06:39.659992 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:06:39.661605 [Enter `^Ec?' for help]
302 11:06:40.879759
303 11:06:40.880274
304 11:06:40.880613 F0: 102B 0000
305 11:06:40.880931
306 11:06:40.881279 F3: 1001 0000 [0200]
307 11:06:40.882659
308 11:06:40.883086 F3: 1001 0000
309 11:06:40.883460
310 11:06:40.883808 F7: 102D 0000
311 11:06:40.884114
312 11:06:40.886188 F1: 0000 0000
313 11:06:40.886625
314 11:06:40.886968 V0: 0000 0000 [0001]
315 11:06:40.887276
316 11:06:40.889425 00: 0007 8000
317 11:06:40.889851
318 11:06:40.890172 01: 0000 0000
319 11:06:40.890485
320 11:06:40.893155 BP: 0C00 0209 [0000]
321 11:06:40.893720
322 11:06:40.894050 G0: 1182 0000
323 11:06:40.894351
324 11:06:40.896162 EC: 0000 0021 [4000]
325 11:06:40.896657
326 11:06:40.896980 S7: 0000 0000 [0000]
327 11:06:40.897447
328 11:06:40.899285 CC: 0000 0000 [0001]
329 11:06:40.899888
330 11:06:40.900362 T0: 0000 0040 [010F]
331 11:06:40.900813
332 11:06:40.902432 Jump to BL
333 11:06:40.902807
334 11:06:40.926350
335 11:06:40.926831
336 11:06:40.936389 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:06:40.939473 ARM64: Exception handlers installed.
338 11:06:40.940071 ARM64: Testing exception
339 11:06:40.943042 ARM64: Done test exception
340 11:06:40.949753 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:06:40.960051 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:06:40.966688 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:06:40.977387 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:06:40.984027 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:06:40.994124 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:06:41.003900 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:06:41.010673 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:06:41.029594 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:06:41.032666 WDT: Last reset was cold boot
350 11:06:41.036219 SPI1(PAD0) initialized at 2873684 Hz
351 11:06:41.039444 SPI5(PAD0) initialized at 992727 Hz
352 11:06:41.042842 VBOOT: Loading verstage.
353 11:06:41.049618 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:06:41.052721 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:06:41.056249 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:06:41.059593 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:06:41.066964 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:06:41.073336 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:06:41.084362 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 11:06:41.084866
361 11:06:41.085279
362 11:06:41.094296 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:06:41.097782 ARM64: Exception handlers installed.
364 11:06:41.101061 ARM64: Testing exception
365 11:06:41.101604 ARM64: Done test exception
366 11:06:41.107868 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:06:41.110893 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:06:41.125706 Probing TPM: . done!
369 11:06:41.126379 TPM ready after 0 ms
370 11:06:41.132453 Connected to device vid:did:rid of 1ae0:0028:00
371 11:06:41.138700 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
372 11:06:41.142423 Initialized TPM device CR50 revision 0
373 11:06:41.188718 tlcl_send_startup: Startup return code is 0
374 11:06:41.189222 TPM: setup succeeded
375 11:06:41.200161 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:06:41.208655 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:06:41.218902 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:06:41.228193 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:06:41.231284 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:06:41.234715 in-header: 03 07 00 00 08 00 00 00
381 11:06:41.237594 in-data: aa e4 47 04 13 02 00 00
382 11:06:41.241368 Chrome EC: UHEPI supported
383 11:06:41.247595 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:06:41.250905 in-header: 03 a9 00 00 08 00 00 00
385 11:06:41.255791 in-data: 84 60 60 08 00 00 00 00
386 11:06:41.256364 Phase 1
387 11:06:41.261044 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:06:41.264531 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:06:41.271041 VB2:vb2_check_recovery() Recovery was requested manually
390 11:06:41.278084 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:06:41.278640 Recovery requested (1009000e)
392 11:06:41.286887 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:06:41.292129 tlcl_extend: response is 0
394 11:06:41.300273 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:06:41.305651 tlcl_extend: response is 0
396 11:06:41.312333 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:06:41.332561 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:06:41.339229 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:06:41.339673
400 11:06:41.339995
401 11:06:41.349550 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:06:41.352956 ARM64: Exception handlers installed.
403 11:06:41.355942 ARM64: Testing exception
404 11:06:41.356418 ARM64: Done test exception
405 11:06:41.378145 pmic_efuse_setting: Set efuses in 11 msecs
406 11:06:41.381526 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:06:41.388606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:06:41.392286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:06:41.398431 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:06:41.401703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:06:41.405181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:06:41.412026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:06:41.414921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:06:41.422167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:06:41.425327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:06:41.431669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:06:41.435296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:06:41.438668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:06:41.445290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:06:41.451900 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:06:41.455324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:06:41.461876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:06:41.468693 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:06:41.471911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:06:41.478534 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:06:41.485543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:06:41.488576 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:06:41.495166 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:06:41.502360 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:06:41.505494 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:06:41.512320 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:06:41.518626 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:06:41.521831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:06:41.528828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:06:41.532012 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:06:41.538468 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:06:41.541786 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:06:41.548527 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:06:41.551920 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:06:41.558699 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:06:41.562237 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:06:41.568744 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:06:41.571889 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:06:41.578536 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:06:41.582373 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:06:41.586029 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:06:41.589313 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:06:41.596066 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:06:41.599443 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:06:41.602766 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:06:41.609368 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:06:41.612566 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:06:41.616047 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:06:41.619249 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:06:41.626000 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:06:41.629528 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:06:41.632507 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:06:41.642551 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:06:41.649395 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:06:41.652494 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:06:41.662870 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:06:41.669331 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:06:41.676225 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:06:41.679307 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:06:41.682697 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:06:41.691153 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 11:06:41.697594 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:06:41.700959 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:06:41.704576 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:06:41.715397 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 11:06:41.725275 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 11:06:41.734861 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 11:06:41.744106 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 11:06:41.753885 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 11:06:41.763378 [RTC]rtc_get_frequency_meter,154: input=16, output=789
476 11:06:41.772788 [RTC]rtc_get_frequency_meter,154: input=17, output=809
477 11:06:41.775927 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:06:41.783293 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:06:41.786230 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:06:41.789812 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 11:06:41.796849 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:06:41.799980 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 11:06:41.802993 ADC[4]: Raw value=670432 ID=5
484 11:06:41.803463 ADC[3]: Raw value=212549 ID=1
485 11:06:41.806352 RAM Code: 0x51
486 11:06:41.809469 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:06:41.816944 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:06:41.822779 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 11:06:41.829525 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 11:06:41.832777 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:06:41.836099 in-header: 03 07 00 00 08 00 00 00
492 11:06:41.839459 in-data: aa e4 47 04 13 02 00 00
493 11:06:41.843021 Chrome EC: UHEPI supported
494 11:06:41.849638 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:06:41.852958 in-header: 03 a9 00 00 08 00 00 00
496 11:06:41.856326 in-data: 84 60 60 08 00 00 00 00
497 11:06:41.859536 MRC: failed to locate region type 0.
498 11:06:41.866133 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:06:41.869893 DRAM-K: Running full calibration
500 11:06:41.873118 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 11:06:41.876565 header.status = 0x0
502 11:06:41.879525 header.version = 0x6 (expected: 0x6)
503 11:06:41.882818 header.size = 0xd00 (expected: 0xd00)
504 11:06:41.883235 header.flags = 0x0
505 11:06:41.890006 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:06:41.908353 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 11:06:41.914560 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:06:41.918521 dram_init: ddr_geometry: 0
509 11:06:41.921398 [EMI] MDL number = 0
510 11:06:41.921836 [EMI] Get MDL freq = 0
511 11:06:41.924771 dram_init: ddr_type: 0
512 11:06:41.925349 is_discrete_lpddr4: 1
513 11:06:41.928034 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:06:41.928458
515 11:06:41.928789
516 11:06:41.931190 [Bian_co] ETT version 0.0.0.1
517 11:06:41.938155 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 11:06:41.938650
519 11:06:41.941309 dramc_set_vcore_voltage set vcore to 650000
520 11:06:41.944630 Read voltage for 800, 4
521 11:06:41.945160 Vio18 = 0
522 11:06:41.945503 Vcore = 650000
523 11:06:41.947555 Vdram = 0
524 11:06:41.947848 Vddq = 0
525 11:06:41.948078 Vmddr = 0
526 11:06:41.951414 dram_init: config_dvfs: 1
527 11:06:41.954413 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:06:41.960981 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:06:41.964140 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:06:41.967512 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:06:41.970388 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:06:41.977190 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:06:41.977312 MEM_TYPE=3, freq_sel=18
534 11:06:41.980915 sv_algorithm_assistance_LP4_1600
535 11:06:41.983900 ============ PULL DRAM RESETB DOWN ============
536 11:06:41.990481 ========== PULL DRAM RESETB DOWN end =========
537 11:06:41.993775 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:06:41.997358 ===================================
539 11:06:42.000397 LPDDR4 DRAM CONFIGURATION
540 11:06:42.003650 ===================================
541 11:06:42.003731 EX_ROW_EN[0] = 0x0
542 11:06:42.007086 EX_ROW_EN[1] = 0x0
543 11:06:42.007165 LP4Y_EN = 0x0
544 11:06:42.010445 WORK_FSP = 0x0
545 11:06:42.010525 WL = 0x2
546 11:06:42.013886 RL = 0x2
547 11:06:42.013966 BL = 0x2
548 11:06:42.017030 RPST = 0x0
549 11:06:42.017129 RD_PRE = 0x0
550 11:06:42.020507 WR_PRE = 0x1
551 11:06:42.023735 WR_PST = 0x0
552 11:06:42.023814 DBI_WR = 0x0
553 11:06:42.026929 DBI_RD = 0x0
554 11:06:42.027006 OTF = 0x1
555 11:06:42.030572 ===================================
556 11:06:42.033769 ===================================
557 11:06:42.033848 ANA top config
558 11:06:42.037064 ===================================
559 11:06:42.040131 DLL_ASYNC_EN = 0
560 11:06:42.043504 ALL_SLAVE_EN = 1
561 11:06:42.047059 NEW_RANK_MODE = 1
562 11:06:42.050089 DLL_IDLE_MODE = 1
563 11:06:42.050184 LP45_APHY_COMB_EN = 1
564 11:06:42.053779 TX_ODT_DIS = 1
565 11:06:42.056912 NEW_8X_MODE = 1
566 11:06:42.060270 ===================================
567 11:06:42.063634 ===================================
568 11:06:42.066831 data_rate = 1600
569 11:06:42.070647 CKR = 1
570 11:06:42.070739 DQ_P2S_RATIO = 8
571 11:06:42.073366 ===================================
572 11:06:42.076683 CA_P2S_RATIO = 8
573 11:06:42.080063 DQ_CA_OPEN = 0
574 11:06:42.083590 DQ_SEMI_OPEN = 0
575 11:06:42.086827 CA_SEMI_OPEN = 0
576 11:06:42.089875 CA_FULL_RATE = 0
577 11:06:42.089952 DQ_CKDIV4_EN = 1
578 11:06:42.093370 CA_CKDIV4_EN = 1
579 11:06:42.096804 CA_PREDIV_EN = 0
580 11:06:42.100090 PH8_DLY = 0
581 11:06:42.103191 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:06:42.107075 DQ_AAMCK_DIV = 4
583 11:06:42.107174 CA_AAMCK_DIV = 4
584 11:06:42.109940 CA_ADMCK_DIV = 4
585 11:06:42.113911 DQ_TRACK_CA_EN = 0
586 11:06:42.116777 CA_PICK = 800
587 11:06:42.120064 CA_MCKIO = 800
588 11:06:42.123343 MCKIO_SEMI = 0
589 11:06:42.126832 PLL_FREQ = 3068
590 11:06:42.126916 DQ_UI_PI_RATIO = 32
591 11:06:42.130208 CA_UI_PI_RATIO = 0
592 11:06:42.133323 ===================================
593 11:06:42.136698 ===================================
594 11:06:42.140412 memory_type:LPDDR4
595 11:06:42.143637 GP_NUM : 10
596 11:06:42.143742 SRAM_EN : 1
597 11:06:42.146785 MD32_EN : 0
598 11:06:42.150291 ===================================
599 11:06:42.150419 [ANA_INIT] >>>>>>>>>>>>>>
600 11:06:42.153648 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:06:42.156840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:06:42.160645 ===================================
603 11:06:42.163911 data_rate = 1600,PCW = 0X7600
604 11:06:42.167276 ===================================
605 11:06:42.170100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:06:42.176889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:06:42.180494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:06:42.186828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:06:42.190195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:06:42.193542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:06:42.193701 [ANA_INIT] flow start
612 11:06:42.197094 [ANA_INIT] PLL >>>>>>>>
613 11:06:42.200464 [ANA_INIT] PLL <<<<<<<<
614 11:06:42.203903 [ANA_INIT] MIDPI >>>>>>>>
615 11:06:42.204063 [ANA_INIT] MIDPI <<<<<<<<
616 11:06:42.206904 [ANA_INIT] DLL >>>>>>>>
617 11:06:42.207062 [ANA_INIT] flow end
618 11:06:42.213968 ============ LP4 DIFF to SE enter ============
619 11:06:42.217108 ============ LP4 DIFF to SE exit ============
620 11:06:42.220588 [ANA_INIT] <<<<<<<<<<<<<
621 11:06:42.223597 [Flow] Enable top DCM control >>>>>
622 11:06:42.227113 [Flow] Enable top DCM control <<<<<
623 11:06:42.230312 Enable DLL master slave shuffle
624 11:06:42.233621 ==============================================================
625 11:06:42.237071 Gating Mode config
626 11:06:42.240408 ==============================================================
627 11:06:42.243738 Config description:
628 11:06:42.253751 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:06:42.260188 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:06:42.263698 SELPH_MODE 0: By rank 1: By Phase
631 11:06:42.270458 ==============================================================
632 11:06:42.273803 GAT_TRACK_EN = 1
633 11:06:42.276991 RX_GATING_MODE = 2
634 11:06:42.280156 RX_GATING_TRACK_MODE = 2
635 11:06:42.283700 SELPH_MODE = 1
636 11:06:42.283803 PICG_EARLY_EN = 1
637 11:06:42.287016 VALID_LAT_VALUE = 1
638 11:06:42.293608 ==============================================================
639 11:06:42.296828 Enter into Gating configuration >>>>
640 11:06:42.300327 Exit from Gating configuration <<<<
641 11:06:42.303880 Enter into DVFS_PRE_config >>>>>
642 11:06:42.313514 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:06:42.316894 Exit from DVFS_PRE_config <<<<<
644 11:06:42.320514 Enter into PICG configuration >>>>
645 11:06:42.323574 Exit from PICG configuration <<<<
646 11:06:42.327148 [RX_INPUT] configuration >>>>>
647 11:06:42.330347 [RX_INPUT] configuration <<<<<
648 11:06:42.333715 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:06:42.340114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:06:42.347071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:06:42.353650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:06:42.360388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:06:42.363694 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:06:42.370298 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:06:42.373466 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:06:42.376762 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:06:42.379983 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:06:42.383588 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:06:42.390305 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:06:42.393695 ===================================
661 11:06:42.396961 LPDDR4 DRAM CONFIGURATION
662 11:06:42.400445 ===================================
663 11:06:42.400573 EX_ROW_EN[0] = 0x0
664 11:06:42.404045 EX_ROW_EN[1] = 0x0
665 11:06:42.404156 LP4Y_EN = 0x0
666 11:06:42.407383 WORK_FSP = 0x0
667 11:06:42.407506 WL = 0x2
668 11:06:42.410701 RL = 0x2
669 11:06:42.410839 BL = 0x2
670 11:06:42.413521 RPST = 0x0
671 11:06:42.413659 RD_PRE = 0x0
672 11:06:42.416873 WR_PRE = 0x1
673 11:06:42.417030 WR_PST = 0x0
674 11:06:42.420673 DBI_WR = 0x0
675 11:06:42.420920 DBI_RD = 0x0
676 11:06:42.423709 OTF = 0x1
677 11:06:42.427251 ===================================
678 11:06:42.430767 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:06:42.434088 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:06:42.440648 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:06:42.444183 ===================================
682 11:06:42.444605 LPDDR4 DRAM CONFIGURATION
683 11:06:42.447128 ===================================
684 11:06:42.450691 EX_ROW_EN[0] = 0x10
685 11:06:42.454086 EX_ROW_EN[1] = 0x0
686 11:06:42.454587 LP4Y_EN = 0x0
687 11:06:42.457413 WORK_FSP = 0x0
688 11:06:42.457838 WL = 0x2
689 11:06:42.460649 RL = 0x2
690 11:06:42.461069 BL = 0x2
691 11:06:42.464299 RPST = 0x0
692 11:06:42.464815 RD_PRE = 0x0
693 11:06:42.467144 WR_PRE = 0x1
694 11:06:42.467563 WR_PST = 0x0
695 11:06:42.470766 DBI_WR = 0x0
696 11:06:42.471269 DBI_RD = 0x0
697 11:06:42.473957 OTF = 0x1
698 11:06:42.477445 ===================================
699 11:06:42.483754 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:06:42.487408 nWR fixed to 40
701 11:06:42.487845 [ModeRegInit_LP4] CH0 RK0
702 11:06:42.490540 [ModeRegInit_LP4] CH0 RK1
703 11:06:42.493796 [ModeRegInit_LP4] CH1 RK0
704 11:06:42.496971 [ModeRegInit_LP4] CH1 RK1
705 11:06:42.497430 match AC timing 12
706 11:06:42.503619 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 11:06:42.506777 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:06:42.510423 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:06:42.516713 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:06:42.520542 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:06:42.521044 [EMI DOE] emi_dcm 0
712 11:06:42.526969 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:06:42.527476 ==
714 11:06:42.530443 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:06:42.533678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 11:06:42.534117 ==
717 11:06:42.540273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:06:42.543590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:06:42.553721 [CA 0] Center 37 (7~68) winsize 62
720 11:06:42.557098 [CA 1] Center 37 (7~68) winsize 62
721 11:06:42.560516 [CA 2] Center 35 (5~66) winsize 62
722 11:06:42.563729 [CA 3] Center 35 (4~66) winsize 63
723 11:06:42.567175 [CA 4] Center 34 (3~65) winsize 63
724 11:06:42.570784 [CA 5] Center 34 (3~65) winsize 63
725 11:06:42.571288
726 11:06:42.573842 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:06:42.574269
728 11:06:42.577540 [CATrainingPosCal] consider 1 rank data
729 11:06:42.581340 u2DelayCellTimex100 = 270/100 ps
730 11:06:42.584626 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 11:06:42.588346 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 11:06:42.591359 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 11:06:42.594611 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 11:06:42.601369 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
735 11:06:42.604357 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
736 11:06:42.604800
737 11:06:42.607791 CA PerBit enable=1, Macro0, CA PI delay=34
738 11:06:42.608325
739 11:06:42.611225 [CBTSetCACLKResult] CA Dly = 34
740 11:06:42.611646 CS Dly: 6 (0~37)
741 11:06:42.611971 ==
742 11:06:42.614479 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:06:42.617877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 11:06:42.621128 ==
745 11:06:42.624499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:06:42.631232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:06:42.639596 [CA 0] Center 37 (6~68) winsize 63
748 11:06:42.642988 [CA 1] Center 37 (6~68) winsize 63
749 11:06:42.646245 [CA 2] Center 35 (4~66) winsize 63
750 11:06:42.649932 [CA 3] Center 34 (4~65) winsize 62
751 11:06:42.653252 [CA 4] Center 33 (2~64) winsize 63
752 11:06:42.656607 [CA 5] Center 33 (3~64) winsize 62
753 11:06:42.657110
754 11:06:42.659485 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:06:42.659907
756 11:06:42.663166 [CATrainingPosCal] consider 2 rank data
757 11:06:42.666556 u2DelayCellTimex100 = 270/100 ps
758 11:06:42.669609 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:06:42.673144 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:06:42.679748 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:06:42.683084 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:06:42.686169 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 11:06:42.689934 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:06:42.690325
765 11:06:42.692933 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:06:42.693349
767 11:06:42.696618 [CBTSetCACLKResult] CA Dly = 33
768 11:06:42.697117 CS Dly: 6 (0~38)
769 11:06:42.697484
770 11:06:42.699800 ----->DramcWriteLeveling(PI) begin...
771 11:06:42.702863 ==
772 11:06:42.703247 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:06:42.709747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 11:06:42.710200 ==
775 11:06:42.712861 Write leveling (Byte 0): 27 => 27
776 11:06:42.716408 Write leveling (Byte 1): 27 => 27
777 11:06:42.719879 DramcWriteLeveling(PI) end<-----
778 11:06:42.720259
779 11:06:42.720556 ==
780 11:06:42.723135 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:06:42.726458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 11:06:42.726951 ==
783 11:06:42.729695 [Gating] SW mode calibration
784 11:06:42.736801 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:06:42.739727 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:06:42.746821 0 6 0 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
787 11:06:42.749834 0 6 4 | B1->B0 | 2a2a 2424 | 1 0 | (1 0) (1 0)
788 11:06:42.753065 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:06:42.759652 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:06:42.763232 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:06:42.766542 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:06:42.773182 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:06:42.776196 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:06:42.779631 0 7 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
795 11:06:42.786041 0 7 4 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
796 11:06:42.789492 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:06:42.792623 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:06:42.799505 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:06:42.802585 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:06:42.805916 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:06:42.809264 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 11:06:42.816019 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 11:06:42.819624 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 11:06:42.822820 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:06:42.829503 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:06:42.832821 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:06:42.836124 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:06:42.842770 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:06:42.846198 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:06:42.849677 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:06:42.856393 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:06:42.859557 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:06:42.863116 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:06:42.869527 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:06:42.873045 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:06:42.876507 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:06:42.882806 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 11:06:42.886536 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 11:06:42.889787 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 11:06:42.893100 Total UI for P1: 0, mck2ui 16
821 11:06:42.896164 best dqsien dly found for B0: ( 0, 10, 0)
822 11:06:42.899499 Total UI for P1: 0, mck2ui 16
823 11:06:42.903287 best dqsien dly found for B1: ( 0, 10, 0)
824 11:06:42.906569 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 11:06:42.909692 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 11:06:42.910132
827 11:06:42.913373 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 11:06:42.919636 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 11:06:42.920074 [Gating] SW calibration Done
830 11:06:42.920405 ==
831 11:06:42.923495 Dram Type= 6, Freq= 0, CH_0, rank 0
832 11:06:42.929714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 11:06:42.930395 ==
834 11:06:42.930942 RX Vref Scan: 0
835 11:06:42.931468
836 11:06:42.932745 RX Vref 0 -> 0, step: 1
837 11:06:42.933288
838 11:06:42.936158 RX Delay -130 -> 252, step: 16
839 11:06:42.939654 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 11:06:42.942786 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 11:06:42.946152 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 11:06:42.952722 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 11:06:42.956530 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
844 11:06:42.959557 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 11:06:42.963170 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 11:06:42.966195 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 11:06:42.972683 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 11:06:42.975850 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
849 11:06:42.979287 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 11:06:42.982980 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 11:06:42.986157 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 11:06:42.992966 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 11:06:42.996308 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 11:06:42.999710 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 11:06:43.000227 ==
856 11:06:43.002924 Dram Type= 6, Freq= 0, CH_0, rank 0
857 11:06:43.006364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 11:06:43.006940 ==
859 11:06:43.009309 DQS Delay:
860 11:06:43.009853 DQS0 = 0, DQS1 = 0
861 11:06:43.012651 DQM Delay:
862 11:06:43.013024 DQM0 = 81, DQM1 = 75
863 11:06:43.013367 DQ Delay:
864 11:06:43.016168 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 11:06:43.019427 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
866 11:06:43.022781 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
867 11:06:43.026112 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 11:06:43.026521
869 11:06:43.026816
870 11:06:43.029656 ==
871 11:06:43.030034 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:06:43.035963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 11:06:43.036359 ==
874 11:06:43.036656
875 11:06:43.036925
876 11:06:43.039331 TX Vref Scan disable
877 11:06:43.039710 == TX Byte 0 ==
878 11:06:43.042596 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
879 11:06:43.049274 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
880 11:06:43.049667 == TX Byte 1 ==
881 11:06:43.052828 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
882 11:06:43.059613 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
883 11:06:43.059991 ==
884 11:06:43.063190 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:06:43.066068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 11:06:43.066451 ==
887 11:06:43.079039 TX Vref=22, minBit 2, minWin=27, winSum=441
888 11:06:43.081903 TX Vref=24, minBit 2, minWin=27, winSum=445
889 11:06:43.085600 TX Vref=26, minBit 4, minWin=27, winSum=450
890 11:06:43.088670 TX Vref=28, minBit 1, minWin=28, winSum=455
891 11:06:43.092609 TX Vref=30, minBit 1, minWin=28, winSum=454
892 11:06:43.095822 TX Vref=32, minBit 0, minWin=28, winSum=453
893 11:06:43.102241 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 28
894 11:06:43.102662
895 11:06:43.105399 Final TX Range 1 Vref 28
896 11:06:43.105839
897 11:06:43.106165 ==
898 11:06:43.109126 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:06:43.112336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 11:06:43.112787 ==
901 11:06:43.113111
902 11:06:43.113497
903 11:06:43.115725 TX Vref Scan disable
904 11:06:43.118994 == TX Byte 0 ==
905 11:06:43.122047 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
906 11:06:43.125548 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
907 11:06:43.129024 == TX Byte 1 ==
908 11:06:43.132096 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
909 11:06:43.135408 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
910 11:06:43.135819
911 11:06:43.138836 [DATLAT]
912 11:06:43.139215 Freq=800, CH0 RK0
913 11:06:43.139511
914 11:06:43.142235 DATLAT Default: 0xa
915 11:06:43.142616 0, 0xFFFF, sum = 0
916 11:06:43.145288 1, 0xFFFF, sum = 0
917 11:06:43.145747 2, 0xFFFF, sum = 0
918 11:06:43.148984 3, 0xFFFF, sum = 0
919 11:06:43.149641 4, 0xFFFF, sum = 0
920 11:06:43.152039 5, 0xFFFF, sum = 0
921 11:06:43.152619 6, 0xFFFF, sum = 0
922 11:06:43.155369 7, 0xFFFF, sum = 0
923 11:06:43.155756 8, 0x0, sum = 1
924 11:06:43.158909 9, 0x0, sum = 2
925 11:06:43.159299 10, 0x0, sum = 3
926 11:06:43.162119 11, 0x0, sum = 4
927 11:06:43.162506 best_step = 9
928 11:06:43.162800
929 11:06:43.163070 ==
930 11:06:43.165719 Dram Type= 6, Freq= 0, CH_0, rank 0
931 11:06:43.169517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 11:06:43.172301 ==
933 11:06:43.172770 RX Vref Scan: 1
934 11:06:43.173066
935 11:06:43.175729 Set Vref Range= 32 -> 127
936 11:06:43.176109
937 11:06:43.178961 RX Vref 32 -> 127, step: 1
938 11:06:43.179386
939 11:06:43.179769 RX Delay -95 -> 252, step: 8
940 11:06:43.180061
941 11:06:43.182051 Set Vref, RX VrefLevel [Byte0]: 32
942 11:06:43.185318 [Byte1]: 32
943 11:06:43.189281
944 11:06:43.189665 Set Vref, RX VrefLevel [Byte0]: 33
945 11:06:43.192920 [Byte1]: 33
946 11:06:43.196913
947 11:06:43.197389 Set Vref, RX VrefLevel [Byte0]: 34
948 11:06:43.200380 [Byte1]: 34
949 11:06:43.204628
950 11:06:43.205203 Set Vref, RX VrefLevel [Byte0]: 35
951 11:06:43.208318 [Byte1]: 35
952 11:06:43.212429
953 11:06:43.212852 Set Vref, RX VrefLevel [Byte0]: 36
954 11:06:43.215531 [Byte1]: 36
955 11:06:43.220141
956 11:06:43.220562 Set Vref, RX VrefLevel [Byte0]: 37
957 11:06:43.223263 [Byte1]: 37
958 11:06:43.227736
959 11:06:43.228156 Set Vref, RX VrefLevel [Byte0]: 38
960 11:06:43.230955 [Byte1]: 38
961 11:06:43.235063
962 11:06:43.235481 Set Vref, RX VrefLevel [Byte0]: 39
963 11:06:43.238188 [Byte1]: 39
964 11:06:43.242590
965 11:06:43.243007 Set Vref, RX VrefLevel [Byte0]: 40
966 11:06:43.246154 [Byte1]: 40
967 11:06:43.250146
968 11:06:43.250605 Set Vref, RX VrefLevel [Byte0]: 41
969 11:06:43.253377 [Byte1]: 41
970 11:06:43.257800
971 11:06:43.258244 Set Vref, RX VrefLevel [Byte0]: 42
972 11:06:43.261177 [Byte1]: 42
973 11:06:43.265436
974 11:06:43.265884 Set Vref, RX VrefLevel [Byte0]: 43
975 11:06:43.268737 [Byte1]: 43
976 11:06:43.272948
977 11:06:43.273647 Set Vref, RX VrefLevel [Byte0]: 44
978 11:06:43.276668 [Byte1]: 44
979 11:06:43.280873
980 11:06:43.281280 Set Vref, RX VrefLevel [Byte0]: 45
981 11:06:43.284006 [Byte1]: 45
982 11:06:43.288073
983 11:06:43.288454 Set Vref, RX VrefLevel [Byte0]: 46
984 11:06:43.291839 [Byte1]: 46
985 11:06:43.295684
986 11:06:43.296061 Set Vref, RX VrefLevel [Byte0]: 47
987 11:06:43.298999 [Byte1]: 47
988 11:06:43.303526
989 11:06:43.303906 Set Vref, RX VrefLevel [Byte0]: 48
990 11:06:43.306484 [Byte1]: 48
991 11:06:43.311251
992 11:06:43.311706 Set Vref, RX VrefLevel [Byte0]: 49
993 11:06:43.314313 [Byte1]: 49
994 11:06:43.318538
995 11:06:43.319012 Set Vref, RX VrefLevel [Byte0]: 50
996 11:06:43.321685 [Byte1]: 50
997 11:06:43.326180
998 11:06:43.326639 Set Vref, RX VrefLevel [Byte0]: 51
999 11:06:43.329830 [Byte1]: 51
1000 11:06:43.333626
1001 11:06:43.334050 Set Vref, RX VrefLevel [Byte0]: 52
1002 11:06:43.336850 [Byte1]: 52
1003 11:06:43.341188
1004 11:06:43.341610 Set Vref, RX VrefLevel [Byte0]: 53
1005 11:06:43.344432 [Byte1]: 53
1006 11:06:43.348922
1007 11:06:43.349449 Set Vref, RX VrefLevel [Byte0]: 54
1008 11:06:43.352045 [Byte1]: 54
1009 11:06:43.356524
1010 11:06:43.356899 Set Vref, RX VrefLevel [Byte0]: 55
1011 11:06:43.359825 [Byte1]: 55
1012 11:06:43.364109
1013 11:06:43.364506 Set Vref, RX VrefLevel [Byte0]: 56
1014 11:06:43.367816 [Byte1]: 56
1015 11:06:43.371766
1016 11:06:43.372346 Set Vref, RX VrefLevel [Byte0]: 57
1017 11:06:43.375480 [Byte1]: 57
1018 11:06:43.379334
1019 11:06:43.379752 Set Vref, RX VrefLevel [Byte0]: 58
1020 11:06:43.382691 [Byte1]: 58
1021 11:06:43.387080
1022 11:06:43.387509 Set Vref, RX VrefLevel [Byte0]: 59
1023 11:06:43.390189 [Byte1]: 59
1024 11:06:43.394643
1025 11:06:43.395067 Set Vref, RX VrefLevel [Byte0]: 60
1026 11:06:43.397896 [Byte1]: 60
1027 11:06:43.402430
1028 11:06:43.402809 Set Vref, RX VrefLevel [Byte0]: 61
1029 11:06:43.405474 [Byte1]: 61
1030 11:06:43.409779
1031 11:06:43.410164 Set Vref, RX VrefLevel [Byte0]: 62
1032 11:06:43.412930 [Byte1]: 62
1033 11:06:43.417715
1034 11:06:43.418182 Set Vref, RX VrefLevel [Byte0]: 63
1035 11:06:43.420583 [Byte1]: 63
1036 11:06:43.425024
1037 11:06:43.425582 Set Vref, RX VrefLevel [Byte0]: 64
1038 11:06:43.428139 [Byte1]: 64
1039 11:06:43.432423
1040 11:06:43.432847 Set Vref, RX VrefLevel [Byte0]: 65
1041 11:06:43.435827 [Byte1]: 65
1042 11:06:43.440258
1043 11:06:43.440727 Set Vref, RX VrefLevel [Byte0]: 66
1044 11:06:43.443651 [Byte1]: 66
1045 11:06:43.447659
1046 11:06:43.448081 Set Vref, RX VrefLevel [Byte0]: 67
1047 11:06:43.451214 [Byte1]: 67
1048 11:06:43.455094
1049 11:06:43.455598 Set Vref, RX VrefLevel [Byte0]: 68
1050 11:06:43.458627 [Byte1]: 68
1051 11:06:43.462691
1052 11:06:43.463114 Set Vref, RX VrefLevel [Byte0]: 69
1053 11:06:43.466568 [Byte1]: 69
1054 11:06:43.470500
1055 11:06:43.470995 Set Vref, RX VrefLevel [Byte0]: 70
1056 11:06:43.474153 [Byte1]: 70
1057 11:06:43.478013
1058 11:06:43.478512 Set Vref, RX VrefLevel [Byte0]: 71
1059 11:06:43.481477 [Byte1]: 71
1060 11:06:43.485749
1061 11:06:43.486171 Set Vref, RX VrefLevel [Byte0]: 72
1062 11:06:43.488884 [Byte1]: 72
1063 11:06:43.493508
1064 11:06:43.494002 Set Vref, RX VrefLevel [Byte0]: 73
1065 11:06:43.496522 [Byte1]: 73
1066 11:06:43.501461
1067 11:06:43.502009 Set Vref, RX VrefLevel [Byte0]: 74
1068 11:06:43.504203 [Byte1]: 74
1069 11:06:43.508848
1070 11:06:43.509382 Set Vref, RX VrefLevel [Byte0]: 75
1071 11:06:43.512122 [Byte1]: 75
1072 11:06:43.516075
1073 11:06:43.516502 Final RX Vref Byte 0 = 51 to rank0
1074 11:06:43.519574 Final RX Vref Byte 1 = 56 to rank0
1075 11:06:43.522741 Final RX Vref Byte 0 = 51 to rank1
1076 11:06:43.526096 Final RX Vref Byte 1 = 56 to rank1==
1077 11:06:43.529450 Dram Type= 6, Freq= 0, CH_0, rank 0
1078 11:06:43.536473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1079 11:06:43.536964 ==
1080 11:06:43.537329 DQS Delay:
1081 11:06:43.537642 DQS0 = 0, DQS1 = 0
1082 11:06:43.539543 DQM Delay:
1083 11:06:43.540035 DQM0 = 83, DQM1 = 73
1084 11:06:43.542794 DQ Delay:
1085 11:06:43.546298 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1086 11:06:43.549278 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1087 11:06:43.549707 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1088 11:06:43.556040 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1089 11:06:43.556529
1090 11:06:43.556859
1091 11:06:43.562346 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1092 11:06:43.566176 CH0 RK0: MR19=606, MR18=3737
1093 11:06:43.572734 CH0_RK0: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1094 11:06:43.573279
1095 11:06:43.575962 ----->DramcWriteLeveling(PI) begin...
1096 11:06:43.576475 ==
1097 11:06:43.579394 Dram Type= 6, Freq= 0, CH_0, rank 1
1098 11:06:43.582533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1099 11:06:43.583034 ==
1100 11:06:43.585810 Write leveling (Byte 0): 33 => 33
1101 11:06:43.589166 Write leveling (Byte 1): 28 => 28
1102 11:06:43.592224 DramcWriteLeveling(PI) end<-----
1103 11:06:43.592643
1104 11:06:43.592968 ==
1105 11:06:43.595616 Dram Type= 6, Freq= 0, CH_0, rank 1
1106 11:06:43.598770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1107 11:06:43.598937 ==
1108 11:06:43.602037 [Gating] SW mode calibration
1109 11:06:43.609095 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1110 11:06:43.615396 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1111 11:06:43.618976 0 6 0 | B1->B0 | 3131 3030 | 1 0 | (1 1) (0 0)
1112 11:06:43.622066 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1113 11:06:43.628881 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 11:06:43.632612 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 11:06:43.635652 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 11:06:43.642023 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 11:06:43.645397 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 11:06:43.648844 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 11:06:43.655441 0 7 0 | B1->B0 | 2e2e 2e2e | 0 0 | (1 1) (1 1)
1120 11:06:43.658609 0 7 4 | B1->B0 | 4343 4444 | 0 0 | (1 1) (0 0)
1121 11:06:43.662016 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 11:06:43.669289 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 11:06:43.672164 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 11:06:43.675494 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 11:06:43.682068 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 11:06:43.685543 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 11:06:43.688469 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1128 11:06:43.695387 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1129 11:06:43.698662 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 11:06:43.702152 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 11:06:43.708909 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 11:06:43.712442 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 11:06:43.715512 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 11:06:43.718573 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 11:06:43.725694 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 11:06:43.728876 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 11:06:43.732429 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 11:06:43.738873 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 11:06:43.742330 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 11:06:43.745585 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 11:06:43.752256 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 11:06:43.755745 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 11:06:43.758914 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1144 11:06:43.766033 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1145 11:06:43.766597 Total UI for P1: 0, mck2ui 16
1146 11:06:43.772711 best dqsien dly found for B1: ( 0, 10, 0)
1147 11:06:43.775812 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1148 11:06:43.778925 Total UI for P1: 0, mck2ui 16
1149 11:06:43.782432 best dqsien dly found for B0: ( 0, 10, 2)
1150 11:06:43.785368 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1151 11:06:43.789617 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1152 11:06:43.790121
1153 11:06:43.792318 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1154 11:06:43.795697 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1155 11:06:43.798777 [Gating] SW calibration Done
1156 11:06:43.799200 ==
1157 11:06:43.842930 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 11:06:43.843481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1159 11:06:43.843824 ==
1160 11:06:43.844131 RX Vref Scan: 0
1161 11:06:43.844426
1162 11:06:43.844712 RX Vref 0 -> 0, step: 1
1163 11:06:43.844995
1164 11:06:43.845320 RX Delay -130 -> 252, step: 16
1165 11:06:43.845951 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1166 11:06:43.846262 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1167 11:06:43.846547 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1168 11:06:43.846823 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1169 11:06:43.847100 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1170 11:06:43.847376 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1171 11:06:43.847651 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1172 11:06:43.866930 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1173 11:06:43.867491 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1174 11:06:43.867869 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1175 11:06:43.868179 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1176 11:06:43.868795 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1177 11:06:43.869140 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1178 11:06:43.870264 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1179 11:06:43.873857 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1180 11:06:43.877641 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1181 11:06:43.878141 ==
1182 11:06:43.880769 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 11:06:43.887405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1184 11:06:43.887915 ==
1185 11:06:43.888246 DQS Delay:
1186 11:06:43.888549 DQS0 = 0, DQS1 = 0
1187 11:06:43.890532 DQM Delay:
1188 11:06:43.890949 DQM0 = 84, DQM1 = 74
1189 11:06:43.894197 DQ Delay:
1190 11:06:43.897351 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1191 11:06:43.897850 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1192 11:06:43.900617 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =61
1193 11:06:43.903677 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1194 11:06:43.907635
1195 11:06:43.908129
1196 11:06:43.908450 ==
1197 11:06:43.910980 Dram Type= 6, Freq= 0, CH_0, rank 1
1198 11:06:43.913658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1199 11:06:43.914177 ==
1200 11:06:43.914515
1201 11:06:43.914831
1202 11:06:43.917035 TX Vref Scan disable
1203 11:06:43.917586 == TX Byte 0 ==
1204 11:06:43.923692 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1205 11:06:43.927109 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1206 11:06:43.927531 == TX Byte 1 ==
1207 11:06:43.934282 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1208 11:06:43.937151 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1209 11:06:43.937699 ==
1210 11:06:43.940787 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 11:06:43.943807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1212 11:06:43.944302 ==
1213 11:06:43.958380 TX Vref=22, minBit 13, minWin=27, winSum=449
1214 11:06:43.961475 TX Vref=24, minBit 0, minWin=28, winSum=452
1215 11:06:43.964587 TX Vref=26, minBit 1, minWin=28, winSum=457
1216 11:06:43.968064 TX Vref=28, minBit 0, minWin=28, winSum=454
1217 11:06:43.971727 TX Vref=30, minBit 0, minWin=28, winSum=455
1218 11:06:43.975805 TX Vref=32, minBit 0, minWin=28, winSum=456
1219 11:06:43.981531 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
1220 11:06:43.982030
1221 11:06:43.984867 Final TX Range 1 Vref 26
1222 11:06:43.985399
1223 11:06:43.985726 ==
1224 11:06:43.988096 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 11:06:43.991248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1226 11:06:43.991675 ==
1227 11:06:43.992001
1228 11:06:43.994772
1229 11:06:43.995279 TX Vref Scan disable
1230 11:06:43.998215 == TX Byte 0 ==
1231 11:06:44.001131 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1232 11:06:44.007965 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1233 11:06:44.008449 == TX Byte 1 ==
1234 11:06:44.011909 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1235 11:06:44.014758 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1236 11:06:44.018426
1237 11:06:44.018921 [DATLAT]
1238 11:06:44.019249 Freq=800, CH0 RK1
1239 11:06:44.019553
1240 11:06:44.021648 DATLAT Default: 0x9
1241 11:06:44.022158 0, 0xFFFF, sum = 0
1242 11:06:44.024844 1, 0xFFFF, sum = 0
1243 11:06:44.025304 2, 0xFFFF, sum = 0
1244 11:06:44.028465 3, 0xFFFF, sum = 0
1245 11:06:44.028969 4, 0xFFFF, sum = 0
1246 11:06:44.031620 5, 0xFFFF, sum = 0
1247 11:06:44.032042 6, 0xFFFF, sum = 0
1248 11:06:44.034809 7, 0xFFFF, sum = 0
1249 11:06:44.035325 8, 0x0, sum = 1
1250 11:06:44.038474 9, 0x0, sum = 2
1251 11:06:44.038897 10, 0x0, sum = 3
1252 11:06:44.041487 11, 0x0, sum = 4
1253 11:06:44.041986 best_step = 9
1254 11:06:44.042311
1255 11:06:44.042611 ==
1256 11:06:44.044536 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 11:06:44.051478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1258 11:06:44.051982 ==
1259 11:06:44.052312 RX Vref Scan: 0
1260 11:06:44.052654
1261 11:06:44.054769 RX Vref 0 -> 0, step: 1
1262 11:06:44.055188
1263 11:06:44.058093 RX Delay -111 -> 252, step: 8
1264 11:06:44.061607 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1265 11:06:44.064807 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1266 11:06:44.071364 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1267 11:06:44.074609 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1268 11:06:44.078412 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1269 11:06:44.081364 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1270 11:06:44.084942 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1271 11:06:44.088019 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1272 11:06:44.095106 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1273 11:06:44.097780 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1274 11:06:44.101437 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1275 11:06:44.104893 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1276 11:06:44.111839 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1277 11:06:44.114645 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1278 11:06:44.117767 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1279 11:06:44.121802 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1280 11:06:44.122305 ==
1281 11:06:44.124842 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 11:06:44.128310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1283 11:06:44.131384 ==
1284 11:06:44.131881 DQS Delay:
1285 11:06:44.132212 DQS0 = 0, DQS1 = 0
1286 11:06:44.134490 DQM Delay:
1287 11:06:44.134912 DQM0 = 86, DQM1 = 74
1288 11:06:44.138134 DQ Delay:
1289 11:06:44.138699 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1290 11:06:44.141637 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1291 11:06:44.144709 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1292 11:06:44.148414 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1293 11:06:44.148937
1294 11:06:44.149313
1295 11:06:44.158131 [DQSOSCAuto] RK1, (LSB)MR18= 0x4949, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1296 11:06:44.161758 CH0 RK1: MR19=606, MR18=4949
1297 11:06:44.168322 CH0_RK1: MR19=0x606, MR18=0x4949, DQSOSC=391, MR23=63, INC=96, DEC=64
1298 11:06:44.168852 [RxdqsGatingPostProcess] freq 800
1299 11:06:44.174602 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1300 11:06:44.177933 Pre-setting of DQS Precalculation
1301 11:06:44.181518 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1302 11:06:44.184887 ==
1303 11:06:44.185438 Dram Type= 6, Freq= 0, CH_1, rank 0
1304 11:06:44.191231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1305 11:06:44.191668 ==
1306 11:06:44.194771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1307 11:06:44.201222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1308 11:06:44.210995 [CA 0] Center 37 (6~68) winsize 63
1309 11:06:44.213825 [CA 1] Center 37 (6~68) winsize 63
1310 11:06:44.217733 [CA 2] Center 34 (4~65) winsize 62
1311 11:06:44.220764 [CA 3] Center 34 (4~65) winsize 62
1312 11:06:44.223911 [CA 4] Center 33 (3~64) winsize 62
1313 11:06:44.227331 [CA 5] Center 33 (3~64) winsize 62
1314 11:06:44.227631
1315 11:06:44.230685 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1316 11:06:44.231054
1317 11:06:44.234154 [CATrainingPosCal] consider 1 rank data
1318 11:06:44.237684 u2DelayCellTimex100 = 270/100 ps
1319 11:06:44.240723 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1320 11:06:44.243986 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1321 11:06:44.250822 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1322 11:06:44.254134 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1323 11:06:44.257701 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1324 11:06:44.260919 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1325 11:06:44.261453
1326 11:06:44.264352 CA PerBit enable=1, Macro0, CA PI delay=33
1327 11:06:44.264870
1328 11:06:44.267841 [CBTSetCACLKResult] CA Dly = 33
1329 11:06:44.268364 CS Dly: 4 (0~35)
1330 11:06:44.268688 ==
1331 11:06:44.270875 Dram Type= 6, Freq= 0, CH_1, rank 1
1332 11:06:44.277637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1333 11:06:44.278202 ==
1334 11:06:44.280907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1335 11:06:44.287561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1336 11:06:44.296936 [CA 0] Center 37 (6~68) winsize 63
1337 11:06:44.299814 [CA 1] Center 37 (6~68) winsize 63
1338 11:06:44.303142 [CA 2] Center 34 (4~65) winsize 62
1339 11:06:44.306641 [CA 3] Center 34 (4~65) winsize 62
1340 11:06:44.310672 [CA 4] Center 33 (3~64) winsize 62
1341 11:06:44.313426 [CA 5] Center 33 (3~64) winsize 62
1342 11:06:44.313926
1343 11:06:44.317061 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1344 11:06:44.317602
1345 11:06:44.320358 [CATrainingPosCal] consider 2 rank data
1346 11:06:44.323746 u2DelayCellTimex100 = 270/100 ps
1347 11:06:44.326589 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1348 11:06:44.330063 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1349 11:06:44.336735 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1350 11:06:44.340304 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1351 11:06:44.343602 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1352 11:06:44.346758 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1353 11:06:44.347195
1354 11:06:44.350108 CA PerBit enable=1, Macro0, CA PI delay=33
1355 11:06:44.350609
1356 11:06:44.353263 [CBTSetCACLKResult] CA Dly = 33
1357 11:06:44.353762 CS Dly: 4 (0~36)
1358 11:06:44.354089
1359 11:06:44.356955 ----->DramcWriteLeveling(PI) begin...
1360 11:06:44.360245 ==
1361 11:06:44.360745 Dram Type= 6, Freq= 0, CH_1, rank 0
1362 11:06:44.366889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1363 11:06:44.367388 ==
1364 11:06:44.369995 Write leveling (Byte 0): 26 => 26
1365 11:06:44.373193 Write leveling (Byte 1): 22 => 22
1366 11:06:44.373654 DramcWriteLeveling(PI) end<-----
1367 11:06:44.376636
1368 11:06:44.377052 ==
1369 11:06:44.379893 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 11:06:44.383365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1371 11:06:44.383822 ==
1372 11:06:44.386826 [Gating] SW mode calibration
1373 11:06:44.393442 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1374 11:06:44.396662 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1375 11:06:44.403421 0 6 0 | B1->B0 | 3232 2929 | 1 0 | (0 0) (0 0)
1376 11:06:44.406769 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 11:06:44.410114 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 11:06:44.416672 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 11:06:44.420207 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 11:06:44.423163 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 11:06:44.430123 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 11:06:44.433261 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1383 11:06:44.436517 0 7 0 | B1->B0 | 2d2d 4343 | 0 0 | (0 0) (0 0)
1384 11:06:44.443360 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1385 11:06:44.446827 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 11:06:44.450018 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 11:06:44.456473 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 11:06:44.460064 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 11:06:44.463443 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 11:06:44.466376 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1391 11:06:44.473310 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 11:06:44.476540 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 11:06:44.480085 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 11:06:44.486852 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 11:06:44.490038 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 11:06:44.493309 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 11:06:44.499810 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 11:06:44.503166 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 11:06:44.506674 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 11:06:44.513335 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 11:06:44.516334 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 11:06:44.520463 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 11:06:44.526567 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 11:06:44.529839 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 11:06:44.532957 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 11:06:44.540102 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1407 11:06:44.543373 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1408 11:06:44.546399 Total UI for P1: 0, mck2ui 16
1409 11:06:44.549959 best dqsien dly found for B0: ( 0, 9, 28)
1410 11:06:44.553276 Total UI for P1: 0, mck2ui 16
1411 11:06:44.556720 best dqsien dly found for B1: ( 0, 9, 30)
1412 11:06:44.560022 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1413 11:06:44.563210 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1414 11:06:44.563804
1415 11:06:44.566919 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1416 11:06:44.569791 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1417 11:06:44.573205 [Gating] SW calibration Done
1418 11:06:44.573662 ==
1419 11:06:44.576811 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 11:06:44.580249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1421 11:06:44.580760 ==
1422 11:06:44.583607 RX Vref Scan: 0
1423 11:06:44.584141
1424 11:06:44.586606 RX Vref 0 -> 0, step: 1
1425 11:06:44.587104
1426 11:06:44.589796 RX Delay -130 -> 252, step: 16
1427 11:06:44.593331 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1428 11:06:44.596795 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1429 11:06:44.599863 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1430 11:06:44.603389 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1431 11:06:44.606742 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1432 11:06:44.613520 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1433 11:06:44.616715 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1434 11:06:44.620270 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1435 11:06:44.623252 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1436 11:06:44.626305 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1437 11:06:44.633145 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1438 11:06:44.636623 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1439 11:06:44.640048 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1440 11:06:44.643471 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1441 11:06:44.646413 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1442 11:06:44.653336 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1443 11:06:44.653835 ==
1444 11:06:44.656429 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 11:06:44.660006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1446 11:06:44.660525 ==
1447 11:06:44.660865 DQS Delay:
1448 11:06:44.663244 DQS0 = 0, DQS1 = 0
1449 11:06:44.663668 DQM Delay:
1450 11:06:44.666453 DQM0 = 81, DQM1 = 70
1451 11:06:44.666878 DQ Delay:
1452 11:06:44.669932 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1453 11:06:44.673278 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1454 11:06:44.676593 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1455 11:06:44.679937 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1456 11:06:44.680439
1457 11:06:44.680769
1458 11:06:44.681073 ==
1459 11:06:44.682998 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 11:06:44.686781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1461 11:06:44.687284 ==
1462 11:06:44.689762
1463 11:06:44.690183
1464 11:06:44.690662 TX Vref Scan disable
1465 11:06:44.693440 == TX Byte 0 ==
1466 11:06:44.697577 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1467 11:06:44.700503 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1468 11:06:44.703323 == TX Byte 1 ==
1469 11:06:44.706984 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1470 11:06:44.709917 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1471 11:06:44.710345 ==
1472 11:06:44.713627 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 11:06:44.719980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1474 11:06:44.720567 ==
1475 11:06:44.732522 TX Vref=22, minBit 3, minWin=27, winSum=449
1476 11:06:44.735908 TX Vref=24, minBit 0, minWin=28, winSum=451
1477 11:06:44.739231 TX Vref=26, minBit 0, minWin=28, winSum=453
1478 11:06:44.742052 TX Vref=28, minBit 0, minWin=28, winSum=457
1479 11:06:44.745424 TX Vref=30, minBit 0, minWin=28, winSum=459
1480 11:06:44.748894 TX Vref=32, minBit 1, minWin=28, winSum=460
1481 11:06:44.755361 [TxChooseVref] Worse bit 1, Min win 28, Win sum 460, Final Vref 32
1482 11:06:44.755848
1483 11:06:44.759073 Final TX Range 1 Vref 32
1484 11:06:44.759569
1485 11:06:44.759903 ==
1486 11:06:44.761996 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 11:06:44.765404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1488 11:06:44.765915 ==
1489 11:06:44.768561
1490 11:06:44.768978
1491 11:06:44.769348 TX Vref Scan disable
1492 11:06:44.772306 == TX Byte 0 ==
1493 11:06:44.775460 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1494 11:06:44.782029 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1495 11:06:44.782500 == TX Byte 1 ==
1496 11:06:44.785374 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1497 11:06:44.791671 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1498 11:06:44.792159
1499 11:06:44.792496 [DATLAT]
1500 11:06:44.792986 Freq=800, CH1 RK0
1501 11:06:44.793473
1502 11:06:44.795368 DATLAT Default: 0xa
1503 11:06:44.795792 0, 0xFFFF, sum = 0
1504 11:06:44.798671 1, 0xFFFF, sum = 0
1505 11:06:44.799101 2, 0xFFFF, sum = 0
1506 11:06:44.801820 3, 0xFFFF, sum = 0
1507 11:06:44.805069 4, 0xFFFF, sum = 0
1508 11:06:44.805535 5, 0xFFFF, sum = 0
1509 11:06:44.808484 6, 0xFFFF, sum = 0
1510 11:06:44.809003 7, 0xFFFF, sum = 0
1511 11:06:44.812163 8, 0x0, sum = 1
1512 11:06:44.812666 9, 0x0, sum = 2
1513 11:06:44.813011 10, 0x0, sum = 3
1514 11:06:44.815348 11, 0x0, sum = 4
1515 11:06:44.815932 best_step = 9
1516 11:06:44.816336
1517 11:06:44.816689 ==
1518 11:06:44.818601 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 11:06:44.825865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 11:06:44.826366 ==
1521 11:06:44.826704 RX Vref Scan: 1
1522 11:06:44.827016
1523 11:06:44.828611 Set Vref Range= 32 -> 127
1524 11:06:44.829035
1525 11:06:44.831835 RX Vref 32 -> 127, step: 1
1526 11:06:44.832256
1527 11:06:44.835567 RX Delay -111 -> 252, step: 8
1528 11:06:44.836064
1529 11:06:44.838537 Set Vref, RX VrefLevel [Byte0]: 32
1530 11:06:44.838966 [Byte1]: 32
1531 11:06:44.843679
1532 11:06:44.844174 Set Vref, RX VrefLevel [Byte0]: 33
1533 11:06:44.846356 [Byte1]: 33
1534 11:06:44.850834
1535 11:06:44.851329 Set Vref, RX VrefLevel [Byte0]: 34
1536 11:06:44.854490 [Byte1]: 34
1537 11:06:44.858831
1538 11:06:44.859346 Set Vref, RX VrefLevel [Byte0]: 35
1539 11:06:44.862050 [Byte1]: 35
1540 11:06:44.866253
1541 11:06:44.866750 Set Vref, RX VrefLevel [Byte0]: 36
1542 11:06:44.869425 [Byte1]: 36
1543 11:06:44.874060
1544 11:06:44.874557 Set Vref, RX VrefLevel [Byte0]: 37
1545 11:06:44.877180 [Byte1]: 37
1546 11:06:44.881625
1547 11:06:44.882120 Set Vref, RX VrefLevel [Byte0]: 38
1548 11:06:44.884580 [Byte1]: 38
1549 11:06:44.888960
1550 11:06:44.889516 Set Vref, RX VrefLevel [Byte0]: 39
1551 11:06:44.892576 [Byte1]: 39
1552 11:06:44.896640
1553 11:06:44.897194 Set Vref, RX VrefLevel [Byte0]: 40
1554 11:06:44.899914 [Byte1]: 40
1555 11:06:44.904164
1556 11:06:44.904638 Set Vref, RX VrefLevel [Byte0]: 41
1557 11:06:44.907967 [Byte1]: 41
1558 11:06:44.912106
1559 11:06:44.912607 Set Vref, RX VrefLevel [Byte0]: 42
1560 11:06:44.915249 [Byte1]: 42
1561 11:06:44.919375
1562 11:06:44.919798 Set Vref, RX VrefLevel [Byte0]: 43
1563 11:06:44.922828 [Byte1]: 43
1564 11:06:44.927015
1565 11:06:44.927486 Set Vref, RX VrefLevel [Byte0]: 44
1566 11:06:44.930449 [Byte1]: 44
1567 11:06:44.934769
1568 11:06:44.935191 Set Vref, RX VrefLevel [Byte0]: 45
1569 11:06:44.937962 [Byte1]: 45
1570 11:06:44.942802
1571 11:06:44.943314 Set Vref, RX VrefLevel [Byte0]: 46
1572 11:06:44.945855 [Byte1]: 46
1573 11:06:44.950027
1574 11:06:44.950525 Set Vref, RX VrefLevel [Byte0]: 47
1575 11:06:44.953413 [Byte1]: 47
1576 11:06:44.957926
1577 11:06:44.958422 Set Vref, RX VrefLevel [Byte0]: 48
1578 11:06:44.961217 [Byte1]: 48
1579 11:06:44.965419
1580 11:06:44.965926 Set Vref, RX VrefLevel [Byte0]: 49
1581 11:06:44.968866 [Byte1]: 49
1582 11:06:44.973165
1583 11:06:44.973713 Set Vref, RX VrefLevel [Byte0]: 50
1584 11:06:44.976495 [Byte1]: 50
1585 11:06:44.980775
1586 11:06:44.981338 Set Vref, RX VrefLevel [Byte0]: 51
1587 11:06:44.984195 [Byte1]: 51
1588 11:06:44.988424
1589 11:06:44.988904 Set Vref, RX VrefLevel [Byte0]: 52
1590 11:06:44.991644 [Byte1]: 52
1591 11:06:44.995711
1592 11:06:44.996134 Set Vref, RX VrefLevel [Byte0]: 53
1593 11:06:44.999289 [Byte1]: 53
1594 11:06:45.003473
1595 11:06:45.003897 Set Vref, RX VrefLevel [Byte0]: 54
1596 11:06:45.007069 [Byte1]: 54
1597 11:06:45.011363
1598 11:06:45.011859 Set Vref, RX VrefLevel [Byte0]: 55
1599 11:06:45.014354 [Byte1]: 55
1600 11:06:45.019093
1601 11:06:45.019594 Set Vref, RX VrefLevel [Byte0]: 56
1602 11:06:45.022223 [Byte1]: 56
1603 11:06:45.026926
1604 11:06:45.027420 Set Vref, RX VrefLevel [Byte0]: 57
1605 11:06:45.029746 [Byte1]: 57
1606 11:06:45.034335
1607 11:06:45.034828 Set Vref, RX VrefLevel [Byte0]: 58
1608 11:06:45.037710 [Byte1]: 58
1609 11:06:45.042243
1610 11:06:45.042853 Set Vref, RX VrefLevel [Byte0]: 59
1611 11:06:45.045111 [Byte1]: 59
1612 11:06:45.049814
1613 11:06:45.050307 Set Vref, RX VrefLevel [Byte0]: 60
1614 11:06:45.052810 [Byte1]: 60
1615 11:06:45.057584
1616 11:06:45.058158 Set Vref, RX VrefLevel [Byte0]: 61
1617 11:06:45.060711 [Byte1]: 61
1618 11:06:45.064862
1619 11:06:45.065403 Set Vref, RX VrefLevel [Byte0]: 62
1620 11:06:45.068394 [Byte1]: 62
1621 11:06:45.072827
1622 11:06:45.073370 Set Vref, RX VrefLevel [Byte0]: 63
1623 11:06:45.075938 [Byte1]: 63
1624 11:06:45.080232
1625 11:06:45.080734 Set Vref, RX VrefLevel [Byte0]: 64
1626 11:06:45.083755 [Byte1]: 64
1627 11:06:45.088053
1628 11:06:45.088553 Set Vref, RX VrefLevel [Byte0]: 65
1629 11:06:45.090959 [Byte1]: 65
1630 11:06:45.095440
1631 11:06:45.095935 Set Vref, RX VrefLevel [Byte0]: 66
1632 11:06:45.098383 [Byte1]: 66
1633 11:06:45.102966
1634 11:06:45.103386 Set Vref, RX VrefLevel [Byte0]: 67
1635 11:06:45.106690 [Byte1]: 67
1636 11:06:45.110827
1637 11:06:45.111250 Set Vref, RX VrefLevel [Byte0]: 68
1638 11:06:45.113921 [Byte1]: 68
1639 11:06:45.118310
1640 11:06:45.118802 Set Vref, RX VrefLevel [Byte0]: 69
1641 11:06:45.121371 [Byte1]: 69
1642 11:06:45.125769
1643 11:06:45.126344 Set Vref, RX VrefLevel [Byte0]: 70
1644 11:06:45.129124 [Byte1]: 70
1645 11:06:45.134087
1646 11:06:45.134580 Set Vref, RX VrefLevel [Byte0]: 71
1647 11:06:45.136738 [Byte1]: 71
1648 11:06:45.141218
1649 11:06:45.141746 Set Vref, RX VrefLevel [Byte0]: 72
1650 11:06:45.144238 [Byte1]: 72
1651 11:06:45.149084
1652 11:06:45.149671 Set Vref, RX VrefLevel [Byte0]: 73
1653 11:06:45.152222 [Byte1]: 73
1654 11:06:45.156611
1655 11:06:45.157145 Set Vref, RX VrefLevel [Byte0]: 74
1656 11:06:45.159773 [Byte1]: 74
1657 11:06:45.164206
1658 11:06:45.164625 Set Vref, RX VrefLevel [Byte0]: 75
1659 11:06:45.167603 [Byte1]: 75
1660 11:06:45.172243
1661 11:06:45.172791 Set Vref, RX VrefLevel [Byte0]: 76
1662 11:06:45.175104 [Byte1]: 76
1663 11:06:45.179476
1664 11:06:45.179971 Final RX Vref Byte 0 = 60 to rank0
1665 11:06:45.182980 Final RX Vref Byte 1 = 55 to rank0
1666 11:06:45.186100 Final RX Vref Byte 0 = 60 to rank1
1667 11:06:45.189389 Final RX Vref Byte 1 = 55 to rank1==
1668 11:06:45.193021 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 11:06:45.199756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1670 11:06:45.200241 ==
1671 11:06:45.200607 DQS Delay:
1672 11:06:45.200911 DQS0 = 0, DQS1 = 0
1673 11:06:45.202694 DQM Delay:
1674 11:06:45.203109 DQM0 = 81, DQM1 = 74
1675 11:06:45.206024 DQ Delay:
1676 11:06:45.209734 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1677 11:06:45.210248 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1678 11:06:45.213208 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1679 11:06:45.216063 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
1680 11:06:45.219677
1681 11:06:45.220169
1682 11:06:45.226251 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a5a, (MSB)MR19= 0x606, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
1683 11:06:45.229966 CH1 RK0: MR19=606, MR18=5A5A
1684 11:06:45.236303 CH1_RK0: MR19=0x606, MR18=0x5A5A, DQSOSC=387, MR23=63, INC=98, DEC=65
1685 11:06:45.236814
1686 11:06:45.240117 ----->DramcWriteLeveling(PI) begin...
1687 11:06:45.240542 ==
1688 11:06:45.242926 Dram Type= 6, Freq= 0, CH_1, rank 1
1689 11:06:45.246126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1690 11:06:45.246550 ==
1691 11:06:45.249679 Write leveling (Byte 0): 26 => 26
1692 11:06:45.252935 Write leveling (Byte 1): 25 => 25
1693 11:06:45.256389 DramcWriteLeveling(PI) end<-----
1694 11:06:45.256881
1695 11:06:45.257219 ==
1696 11:06:45.259774 Dram Type= 6, Freq= 0, CH_1, rank 1
1697 11:06:45.263799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1698 11:06:45.264298 ==
1699 11:06:45.266486 [Gating] SW mode calibration
1700 11:06:45.273294 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1701 11:06:45.279719 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1702 11:06:45.283249 0 6 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
1703 11:06:45.286253 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 11:06:45.293146 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1705 11:06:45.296336 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1706 11:06:45.299560 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 11:06:45.306393 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 11:06:45.309762 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 11:06:45.312797 0 6 28 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (0 0)
1710 11:06:45.316652 0 7 0 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
1711 11:06:45.323102 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 11:06:45.326313 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 11:06:45.330356 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1714 11:06:45.336550 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 11:06:45.339720 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 11:06:45.343135 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1717 11:06:45.349516 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1718 11:06:45.352976 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 11:06:45.356355 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 11:06:45.363283 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 11:06:45.366175 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 11:06:45.369923 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 11:06:45.376317 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 11:06:45.379625 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 11:06:45.383257 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 11:06:45.389613 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 11:06:45.393206 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 11:06:45.395923 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 11:06:45.402734 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 11:06:45.406015 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 11:06:45.409602 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 11:06:45.416317 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 11:06:45.419697 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1734 11:06:45.422810 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1735 11:06:45.426269 Total UI for P1: 0, mck2ui 16
1736 11:06:45.429319 best dqsien dly found for B0: ( 0, 9, 28)
1737 11:06:45.432945 Total UI for P1: 0, mck2ui 16
1738 11:06:45.436612 best dqsien dly found for B1: ( 0, 9, 28)
1739 11:06:45.439715 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1740 11:06:45.443278 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1741 11:06:45.443772
1742 11:06:45.446116 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1743 11:06:45.453382 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1744 11:06:45.453889 [Gating] SW calibration Done
1745 11:06:45.454222 ==
1746 11:06:45.455926 Dram Type= 6, Freq= 0, CH_1, rank 1
1747 11:06:45.462880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1748 11:06:45.463387 ==
1749 11:06:45.463721 RX Vref Scan: 0
1750 11:06:45.464024
1751 11:06:45.466105 RX Vref 0 -> 0, step: 1
1752 11:06:45.466524
1753 11:06:45.469896 RX Delay -130 -> 252, step: 16
1754 11:06:45.473279 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1755 11:06:45.476012 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1756 11:06:45.479204 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1757 11:06:45.485972 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1758 11:06:45.489329 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1759 11:06:45.492789 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1760 11:06:45.496103 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1761 11:06:45.498981 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1762 11:06:45.505958 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1763 11:06:45.509071 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1764 11:06:45.512680 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1765 11:06:45.516056 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1766 11:06:45.520166 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1767 11:06:45.526011 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1768 11:06:45.529189 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1769 11:06:45.532516 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1770 11:06:45.533016 ==
1771 11:06:45.536020 Dram Type= 6, Freq= 0, CH_1, rank 1
1772 11:06:45.539041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1773 11:06:45.539467 ==
1774 11:06:45.542787 DQS Delay:
1775 11:06:45.543281 DQS0 = 0, DQS1 = 0
1776 11:06:45.545577 DQM Delay:
1777 11:06:45.546002 DQM0 = 85, DQM1 = 72
1778 11:06:45.546332 DQ Delay:
1779 11:06:45.549197 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1780 11:06:45.552484 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1781 11:06:45.555984 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1782 11:06:45.559528 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1783 11:06:45.560027
1784 11:06:45.560355
1785 11:06:45.562413 ==
1786 11:06:45.565839 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 11:06:45.569818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1788 11:06:45.570321 ==
1789 11:06:45.570651
1790 11:06:45.570954
1791 11:06:45.572257 TX Vref Scan disable
1792 11:06:45.572679 == TX Byte 0 ==
1793 11:06:45.575748 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1794 11:06:45.582268 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1795 11:06:45.582741 == TX Byte 1 ==
1796 11:06:45.585751 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1797 11:06:45.592859 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1798 11:06:45.593416 ==
1799 11:06:45.595852 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 11:06:45.598987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1801 11:06:45.599417 ==
1802 11:06:45.612411 TX Vref=22, minBit 0, minWin=27, winSum=449
1803 11:06:45.615639 TX Vref=24, minBit 0, minWin=28, winSum=454
1804 11:06:45.618882 TX Vref=26, minBit 2, minWin=28, winSum=458
1805 11:06:45.622425 TX Vref=28, minBit 0, minWin=28, winSum=457
1806 11:06:45.625383 TX Vref=30, minBit 0, minWin=28, winSum=457
1807 11:06:45.629597 TX Vref=32, minBit 0, minWin=28, winSum=454
1808 11:06:45.636079 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 26
1809 11:06:45.636570
1810 11:06:45.638877 Final TX Range 1 Vref 26
1811 11:06:45.639260
1812 11:06:45.639556 ==
1813 11:06:45.642261 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 11:06:45.645535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1815 11:06:45.645919 ==
1816 11:06:45.646217
1817 11:06:45.649087
1818 11:06:45.649514 TX Vref Scan disable
1819 11:06:45.652254 == TX Byte 0 ==
1820 11:06:45.656005 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1821 11:06:45.659149 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1822 11:06:45.662324 == TX Byte 1 ==
1823 11:06:45.666044 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1824 11:06:45.669050 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1825 11:06:45.669486
1826 11:06:45.672669 [DATLAT]
1827 11:06:45.673042 Freq=800, CH1 RK1
1828 11:06:45.673395
1829 11:06:45.675557 DATLAT Default: 0x9
1830 11:06:45.675931 0, 0xFFFF, sum = 0
1831 11:06:45.678987 1, 0xFFFF, sum = 0
1832 11:06:45.679586 2, 0xFFFF, sum = 0
1833 11:06:45.682175 3, 0xFFFF, sum = 0
1834 11:06:45.682557 4, 0xFFFF, sum = 0
1835 11:06:45.685983 5, 0xFFFF, sum = 0
1836 11:06:45.686446 6, 0xFFFF, sum = 0
1837 11:06:45.688798 7, 0xFFFF, sum = 0
1838 11:06:45.689181 8, 0x0, sum = 1
1839 11:06:45.692590 9, 0x0, sum = 2
1840 11:06:45.692973 10, 0x0, sum = 3
1841 11:06:45.695954 11, 0x0, sum = 4
1842 11:06:45.696384 best_step = 9
1843 11:06:45.696680
1844 11:06:45.696952 ==
1845 11:06:45.698796 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 11:06:45.705628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1847 11:06:45.706017 ==
1848 11:06:45.706367 RX Vref Scan: 0
1849 11:06:45.706662
1850 11:06:45.708950 RX Vref 0 -> 0, step: 1
1851 11:06:45.709358
1852 11:06:45.712154 RX Delay -111 -> 252, step: 8
1853 11:06:45.715412 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1854 11:06:45.718864 iDelay=217, Bit 1, Center 80 (-39 ~ 200) 240
1855 11:06:45.725609 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1856 11:06:45.729062 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1857 11:06:45.732154 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1858 11:06:45.736021 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1859 11:06:45.738968 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1860 11:06:45.742213 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1861 11:06:45.748828 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1862 11:06:45.752154 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1863 11:06:45.755550 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1864 11:06:45.758890 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1865 11:06:45.765349 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1866 11:06:45.768658 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1867 11:06:45.772023 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1868 11:06:45.775640 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1869 11:06:45.776135 ==
1870 11:06:45.778737 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 11:06:45.782196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1872 11:06:45.785422 ==
1873 11:06:45.785845 DQS Delay:
1874 11:06:45.786173 DQS0 = 0, DQS1 = 0
1875 11:06:45.789075 DQM Delay:
1876 11:06:45.789596 DQM0 = 84, DQM1 = 74
1877 11:06:45.792243 DQ Delay:
1878 11:06:45.792731 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =80
1879 11:06:45.795508 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1880 11:06:45.798928 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1881 11:06:45.802306 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1882 11:06:45.802726
1883 11:06:45.803054
1884 11:06:45.812414 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1885 11:06:45.815514 CH1 RK1: MR19=606, MR18=4242
1886 11:06:45.822888 CH1_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1887 11:06:45.823405 [RxdqsGatingPostProcess] freq 800
1888 11:06:45.828904 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1889 11:06:45.832361 Pre-setting of DQS Precalculation
1890 11:06:45.835416 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1891 11:06:45.845820 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1892 11:06:45.852523 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1893 11:06:45.853030
1894 11:06:45.853420
1895 11:06:45.855533 [Calibration Summary] 1600 Mbps
1896 11:06:45.856035 CH 0, Rank 0
1897 11:06:45.858982 SW Impedance : PASS
1898 11:06:45.859479 DUTY Scan : NO K
1899 11:06:45.862463 ZQ Calibration : PASS
1900 11:06:45.865321 Jitter Meter : NO K
1901 11:06:45.865747 CBT Training : PASS
1902 11:06:45.868946 Write leveling : PASS
1903 11:06:45.872463 RX DQS gating : PASS
1904 11:06:45.872959 RX DQ/DQS(RDDQC) : PASS
1905 11:06:45.875590 TX DQ/DQS : PASS
1906 11:06:45.878838 RX DATLAT : PASS
1907 11:06:45.879336 RX DQ/DQS(Engine): PASS
1908 11:06:45.882264 TX OE : NO K
1909 11:06:45.882683 All Pass.
1910 11:06:45.883008
1911 11:06:45.885625 CH 0, Rank 1
1912 11:06:45.886124 SW Impedance : PASS
1913 11:06:45.889170 DUTY Scan : NO K
1914 11:06:45.889704 ZQ Calibration : PASS
1915 11:06:45.892293 Jitter Meter : NO K
1916 11:06:45.895621 CBT Training : PASS
1917 11:06:45.896123 Write leveling : PASS
1918 11:06:45.898766 RX DQS gating : PASS
1919 11:06:45.902138 RX DQ/DQS(RDDQC) : PASS
1920 11:06:45.902558 TX DQ/DQS : PASS
1921 11:06:45.905724 RX DATLAT : PASS
1922 11:06:45.908949 RX DQ/DQS(Engine): PASS
1923 11:06:45.909513 TX OE : NO K
1924 11:06:45.912031 All Pass.
1925 11:06:45.912451
1926 11:06:45.912775 CH 1, Rank 0
1927 11:06:45.915404 SW Impedance : PASS
1928 11:06:45.915881 DUTY Scan : NO K
1929 11:06:45.918649 ZQ Calibration : PASS
1930 11:06:45.922385 Jitter Meter : NO K
1931 11:06:45.922880 CBT Training : PASS
1932 11:06:45.925654 Write leveling : PASS
1933 11:06:45.928462 RX DQS gating : PASS
1934 11:06:45.928886 RX DQ/DQS(RDDQC) : PASS
1935 11:06:45.931839 TX DQ/DQS : PASS
1936 11:06:45.932267 RX DATLAT : PASS
1937 11:06:45.935767 RX DQ/DQS(Engine): PASS
1938 11:06:45.938673 TX OE : NO K
1939 11:06:45.939100 All Pass.
1940 11:06:45.939428
1941 11:06:45.939735 CH 1, Rank 1
1942 11:06:45.942112 SW Impedance : PASS
1943 11:06:45.945497 DUTY Scan : NO K
1944 11:06:45.945994 ZQ Calibration : PASS
1945 11:06:45.948969 Jitter Meter : NO K
1946 11:06:45.952209 CBT Training : PASS
1947 11:06:45.952711 Write leveling : PASS
1948 11:06:45.955351 RX DQS gating : PASS
1949 11:06:45.958551 RX DQ/DQS(RDDQC) : PASS
1950 11:06:45.958976 TX DQ/DQS : PASS
1951 11:06:45.961779 RX DATLAT : PASS
1952 11:06:45.965371 RX DQ/DQS(Engine): PASS
1953 11:06:45.965795 TX OE : NO K
1954 11:06:45.968495 All Pass.
1955 11:06:45.968913
1956 11:06:45.969269 DramC Write-DBI off
1957 11:06:45.972343 PER_BANK_REFRESH: Hybrid Mode
1958 11:06:45.972761 TX_TRACKING: ON
1959 11:06:45.975401 [GetDramInforAfterCalByMRR] Vendor 6.
1960 11:06:45.981638 [GetDramInforAfterCalByMRR] Revision 606.
1961 11:06:45.984878 [GetDramInforAfterCalByMRR] Revision 2 0.
1962 11:06:45.985285 MR0 0x3939
1963 11:06:45.985586 MR8 0x1111
1964 11:06:45.988265 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1965 11:06:45.988642
1966 11:06:45.991823 MR0 0x3939
1967 11:06:45.992200 MR8 0x1111
1968 11:06:45.995048 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1969 11:06:45.995426
1970 11:06:46.004808 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1971 11:06:46.008296 [FAST_K] Save calibration result to emmc
1972 11:06:46.011740 [FAST_K] Save calibration result to emmc
1973 11:06:46.014923 dram_init: config_dvfs: 1
1974 11:06:46.018318 dramc_set_vcore_voltage set vcore to 662500
1975 11:06:46.021827 Read voltage for 1200, 2
1976 11:06:46.022287 Vio18 = 0
1977 11:06:46.022583 Vcore = 662500
1978 11:06:46.024939 Vdram = 0
1979 11:06:46.025362 Vddq = 0
1980 11:06:46.025660 Vmddr = 0
1981 11:06:46.031794 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1982 11:06:46.035034 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1983 11:06:46.038270 MEM_TYPE=3, freq_sel=15
1984 11:06:46.041589 sv_algorithm_assistance_LP4_1600
1985 11:06:46.045035 ============ PULL DRAM RESETB DOWN ============
1986 11:06:46.048104 ========== PULL DRAM RESETB DOWN end =========
1987 11:06:46.055024 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1988 11:06:46.058917 ===================================
1989 11:06:46.059371 LPDDR4 DRAM CONFIGURATION
1990 11:06:46.062161 ===================================
1991 11:06:46.065458 EX_ROW_EN[0] = 0x0
1992 11:06:46.068587 EX_ROW_EN[1] = 0x0
1993 11:06:46.069075 LP4Y_EN = 0x0
1994 11:06:46.071741 WORK_FSP = 0x0
1995 11:06:46.072227 WL = 0x4
1996 11:06:46.075026 RL = 0x4
1997 11:06:46.075450 BL = 0x2
1998 11:06:46.078259 RPST = 0x0
1999 11:06:46.078749 RD_PRE = 0x0
2000 11:06:46.081921 WR_PRE = 0x1
2001 11:06:46.082409 WR_PST = 0x0
2002 11:06:46.085265 DBI_WR = 0x0
2003 11:06:46.085766 DBI_RD = 0x0
2004 11:06:46.088636 OTF = 0x1
2005 11:06:46.091683 ===================================
2006 11:06:46.095433 ===================================
2007 11:06:46.095926 ANA top config
2008 11:06:46.098170 ===================================
2009 11:06:46.101975 DLL_ASYNC_EN = 0
2010 11:06:46.105372 ALL_SLAVE_EN = 0
2011 11:06:46.105868 NEW_RANK_MODE = 1
2012 11:06:46.108194 DLL_IDLE_MODE = 1
2013 11:06:46.111467 LP45_APHY_COMB_EN = 1
2014 11:06:46.114830 TX_ODT_DIS = 1
2015 11:06:46.118883 NEW_8X_MODE = 1
2016 11:06:46.121502 ===================================
2017 11:06:46.125398 ===================================
2018 11:06:46.125909 data_rate = 2400
2019 11:06:46.128692 CKR = 1
2020 11:06:46.131882 DQ_P2S_RATIO = 8
2021 11:06:46.135134 ===================================
2022 11:06:46.138647 CA_P2S_RATIO = 8
2023 11:06:46.141588 DQ_CA_OPEN = 0
2024 11:06:46.145033 DQ_SEMI_OPEN = 0
2025 11:06:46.145569 CA_SEMI_OPEN = 0
2026 11:06:46.148354 CA_FULL_RATE = 0
2027 11:06:46.151464 DQ_CKDIV4_EN = 0
2028 11:06:46.155030 CA_CKDIV4_EN = 0
2029 11:06:46.158421 CA_PREDIV_EN = 0
2030 11:06:46.161611 PH8_DLY = 17
2031 11:06:46.162067 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2032 11:06:46.165214 DQ_AAMCK_DIV = 4
2033 11:06:46.169011 CA_AAMCK_DIV = 4
2034 11:06:46.171439 CA_ADMCK_DIV = 4
2035 11:06:46.175302 DQ_TRACK_CA_EN = 0
2036 11:06:46.178257 CA_PICK = 1200
2037 11:06:46.181620 CA_MCKIO = 1200
2038 11:06:46.182045 MCKIO_SEMI = 0
2039 11:06:46.185676 PLL_FREQ = 2366
2040 11:06:46.188339 DQ_UI_PI_RATIO = 32
2041 11:06:46.192336 CA_UI_PI_RATIO = 0
2042 11:06:46.195428 ===================================
2043 11:06:46.198555 ===================================
2044 11:06:46.201938 memory_type:LPDDR4
2045 11:06:46.202369 GP_NUM : 10
2046 11:06:46.205386 SRAM_EN : 1
2047 11:06:46.205874 MD32_EN : 0
2048 11:06:46.208503 ===================================
2049 11:06:46.211706 [ANA_INIT] >>>>>>>>>>>>>>
2050 11:06:46.214971 <<<<<< [CONFIGURE PHASE]: ANA_TX
2051 11:06:46.218394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2052 11:06:46.221740 ===================================
2053 11:06:46.225288 data_rate = 2400,PCW = 0X5b00
2054 11:06:46.228388 ===================================
2055 11:06:46.231685 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2056 11:06:46.234898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2057 11:06:46.241933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2058 11:06:46.245199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2059 11:06:46.251642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2060 11:06:46.255384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2061 11:06:46.255807 [ANA_INIT] flow start
2062 11:06:46.258535 [ANA_INIT] PLL >>>>>>>>
2063 11:06:46.262011 [ANA_INIT] PLL <<<<<<<<
2064 11:06:46.262530 [ANA_INIT] MIDPI >>>>>>>>
2065 11:06:46.265092 [ANA_INIT] MIDPI <<<<<<<<
2066 11:06:46.268867 [ANA_INIT] DLL >>>>>>>>
2067 11:06:46.269337 [ANA_INIT] DLL <<<<<<<<
2068 11:06:46.271696 [ANA_INIT] flow end
2069 11:06:46.275385 ============ LP4 DIFF to SE enter ============
2070 11:06:46.278524 ============ LP4 DIFF to SE exit ============
2071 11:06:46.282130 [ANA_INIT] <<<<<<<<<<<<<
2072 11:06:46.284978 [Flow] Enable top DCM control >>>>>
2073 11:06:46.288668 [Flow] Enable top DCM control <<<<<
2074 11:06:46.291980 Enable DLL master slave shuffle
2075 11:06:46.298623 ==============================================================
2076 11:06:46.299140 Gating Mode config
2077 11:06:46.305160 ==============================================================
2078 11:06:46.305625 Config description:
2079 11:06:46.315911 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2080 11:06:46.321880 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2081 11:06:46.328948 SELPH_MODE 0: By rank 1: By Phase
2082 11:06:46.331869 ==============================================================
2083 11:06:46.335189 GAT_TRACK_EN = 1
2084 11:06:46.338730 RX_GATING_MODE = 2
2085 11:06:46.342089 RX_GATING_TRACK_MODE = 2
2086 11:06:46.345421 SELPH_MODE = 1
2087 11:06:46.348460 PICG_EARLY_EN = 1
2088 11:06:46.351670 VALID_LAT_VALUE = 1
2089 11:06:46.354872 ==============================================================
2090 11:06:46.358628 Enter into Gating configuration >>>>
2091 11:06:46.361946 Exit from Gating configuration <<<<
2092 11:06:46.365019 Enter into DVFS_PRE_config >>>>>
2093 11:06:46.378541 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2094 11:06:46.381550 Exit from DVFS_PRE_config <<<<<
2095 11:06:46.385296 Enter into PICG configuration >>>>
2096 11:06:46.385794 Exit from PICG configuration <<<<
2097 11:06:46.388533 [RX_INPUT] configuration >>>>>
2098 11:06:46.392389 [RX_INPUT] configuration <<<<<
2099 11:06:46.398599 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2100 11:06:46.401594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2101 11:06:46.408382 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2102 11:06:46.415337 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2103 11:06:46.421691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2104 11:06:46.428215 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2105 11:06:46.431500 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2106 11:06:46.435249 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2107 11:06:46.438174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2108 11:06:46.445039 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2109 11:06:46.448209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2110 11:06:46.451564 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2111 11:06:46.455138 ===================================
2112 11:06:46.458379 LPDDR4 DRAM CONFIGURATION
2113 11:06:46.461966 ===================================
2114 11:06:46.464995 EX_ROW_EN[0] = 0x0
2115 11:06:46.465553 EX_ROW_EN[1] = 0x0
2116 11:06:46.468459 LP4Y_EN = 0x0
2117 11:06:46.468951 WORK_FSP = 0x0
2118 11:06:46.471594 WL = 0x4
2119 11:06:46.472013 RL = 0x4
2120 11:06:46.474635 BL = 0x2
2121 11:06:46.475132 RPST = 0x0
2122 11:06:46.478321 RD_PRE = 0x0
2123 11:06:46.478869 WR_PRE = 0x1
2124 11:06:46.481321 WR_PST = 0x0
2125 11:06:46.481746 DBI_WR = 0x0
2126 11:06:46.484922 DBI_RD = 0x0
2127 11:06:46.485416 OTF = 0x1
2128 11:06:46.488027 ===================================
2129 11:06:46.491459 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2130 11:06:46.498019 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2131 11:06:46.501602 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 11:06:46.504769 ===================================
2133 11:06:46.508030 LPDDR4 DRAM CONFIGURATION
2134 11:06:46.511481 ===================================
2135 11:06:46.511937 EX_ROW_EN[0] = 0x10
2136 11:06:46.514973 EX_ROW_EN[1] = 0x0
2137 11:06:46.517890 LP4Y_EN = 0x0
2138 11:06:46.518267 WORK_FSP = 0x0
2139 11:06:46.521637 WL = 0x4
2140 11:06:46.522112 RL = 0x4
2141 11:06:46.525205 BL = 0x2
2142 11:06:46.525747 RPST = 0x0
2143 11:06:46.528315 RD_PRE = 0x0
2144 11:06:46.528769 WR_PRE = 0x1
2145 11:06:46.531336 WR_PST = 0x0
2146 11:06:46.531714 DBI_WR = 0x0
2147 11:06:46.534743 DBI_RD = 0x0
2148 11:06:46.535121 OTF = 0x1
2149 11:06:46.538559 ===================================
2150 11:06:46.545207 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2151 11:06:46.545748 ==
2152 11:06:46.548457 Dram Type= 6, Freq= 0, CH_0, rank 0
2153 11:06:46.551661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2154 11:06:46.552087 ==
2155 11:06:46.554766 [Duty_Offset_Calibration]
2156 11:06:46.558219 B0:0 B1:2 CA:1
2157 11:06:46.558639
2158 11:06:46.561588 [DutyScan_Calibration_Flow] k_type=0
2159 11:06:46.569650
2160 11:06:46.570154 ==CLK 0==
2161 11:06:46.573122 Final CLK duty delay cell = 0
2162 11:06:46.576599 [0] MAX Duty = 5093%(X100), DQS PI = 12
2163 11:06:46.580562 [0] MIN Duty = 4938%(X100), DQS PI = 52
2164 11:06:46.581355 [0] AVG Duty = 5015%(X100)
2165 11:06:46.581746
2166 11:06:46.582875 CH0 CLK Duty spec in!! Max-Min= 155%
2167 11:06:46.589684 [DutyScan_Calibration_Flow] ====Done====
2168 11:06:46.590179
2169 11:06:46.592693 [DutyScan_Calibration_Flow] k_type=1
2170 11:06:46.608881
2171 11:06:46.609426 ==DQS 0 ==
2172 11:06:46.612349 Final DQS duty delay cell = 0
2173 11:06:46.615720 [0] MAX Duty = 5125%(X100), DQS PI = 30
2174 11:06:46.618779 [0] MIN Duty = 5031%(X100), DQS PI = 6
2175 11:06:46.619203 [0] AVG Duty = 5078%(X100)
2176 11:06:46.622456
2177 11:06:46.622954 ==DQS 1 ==
2178 11:06:46.625445 Final DQS duty delay cell = 0
2179 11:06:46.628714 [0] MAX Duty = 5031%(X100), DQS PI = 54
2180 11:06:46.631950 [0] MIN Duty = 4906%(X100), DQS PI = 14
2181 11:06:46.632374 [0] AVG Duty = 4968%(X100)
2182 11:06:46.635599
2183 11:06:46.639515 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2184 11:06:46.640009
2185 11:06:46.641955 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2186 11:06:46.645478 [DutyScan_Calibration_Flow] ====Done====
2187 11:06:46.645979
2188 11:06:46.648812 [DutyScan_Calibration_Flow] k_type=3
2189 11:06:46.666097
2190 11:06:46.666590 ==DQM 0 ==
2191 11:06:46.669755 Final DQM duty delay cell = 0
2192 11:06:46.672634 [0] MAX Duty = 5156%(X100), DQS PI = 22
2193 11:06:46.676136 [0] MIN Duty = 4969%(X100), DQS PI = 40
2194 11:06:46.676680 [0] AVG Duty = 5062%(X100)
2195 11:06:46.679354
2196 11:06:46.679905 ==DQM 1 ==
2197 11:06:46.682588 Final DQM duty delay cell = 4
2198 11:06:46.685933 [4] MAX Duty = 5187%(X100), DQS PI = 54
2199 11:06:46.689332 [4] MIN Duty = 5000%(X100), DQS PI = 18
2200 11:06:46.692545 [4] AVG Duty = 5093%(X100)
2201 11:06:46.692969
2202 11:06:46.696039 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2203 11:06:46.696543
2204 11:06:46.699166 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2205 11:06:46.702948 [DutyScan_Calibration_Flow] ====Done====
2206 11:06:46.703440
2207 11:06:46.706255 [DutyScan_Calibration_Flow] k_type=2
2208 11:06:46.721177
2209 11:06:46.721727 ==DQ 0 ==
2210 11:06:46.724508 Final DQ duty delay cell = -4
2211 11:06:46.727650 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2212 11:06:46.730834 [-4] MIN Duty = 4813%(X100), DQS PI = 6
2213 11:06:46.734123 [-4] AVG Duty = 4937%(X100)
2214 11:06:46.734547
2215 11:06:46.734874 ==DQ 1 ==
2216 11:06:46.737488 Final DQ duty delay cell = -4
2217 11:06:46.741329 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2218 11:06:46.744262 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2219 11:06:46.747527 [-4] AVG Duty = 4984%(X100)
2220 11:06:46.747950
2221 11:06:46.750733 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2222 11:06:46.751161
2223 11:06:46.754129 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2224 11:06:46.757525 [DutyScan_Calibration_Flow] ====Done====
2225 11:06:46.757955 ==
2226 11:06:46.760754 Dram Type= 6, Freq= 0, CH_1, rank 0
2227 11:06:46.764216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2228 11:06:46.764728 ==
2229 11:06:46.767929 [Duty_Offset_Calibration]
2230 11:06:46.768708 B0:0 B1:5 CA:-5
2231 11:06:46.769181
2232 11:06:46.770620 [DutyScan_Calibration_Flow] k_type=0
2233 11:06:46.781377
2234 11:06:46.781908 ==CLK 0==
2235 11:06:46.784629 Final CLK duty delay cell = 0
2236 11:06:46.787724 [0] MAX Duty = 5094%(X100), DQS PI = 24
2237 11:06:46.791463 [0] MIN Duty = 4876%(X100), DQS PI = 48
2238 11:06:46.792051 [0] AVG Duty = 4985%(X100)
2239 11:06:46.794501
2240 11:06:46.797905 CH1 CLK Duty spec in!! Max-Min= 218%
2241 11:06:46.801601 [DutyScan_Calibration_Flow] ====Done====
2242 11:06:46.802027
2243 11:06:46.804542 [DutyScan_Calibration_Flow] k_type=1
2244 11:06:46.819821
2245 11:06:46.820272 ==DQS 0 ==
2246 11:06:46.823313 Final DQS duty delay cell = 0
2247 11:06:46.826697 [0] MAX Duty = 5125%(X100), DQS PI = 14
2248 11:06:46.830009 [0] MIN Duty = 4875%(X100), DQS PI = 40
2249 11:06:46.833132 [0] AVG Duty = 5000%(X100)
2250 11:06:46.833703
2251 11:06:46.834254 ==DQS 1 ==
2252 11:06:46.836703 Final DQS duty delay cell = -4
2253 11:06:46.840386 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2254 11:06:46.843599 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2255 11:06:46.846722 [-4] AVG Duty = 4953%(X100)
2256 11:06:46.847515
2257 11:06:46.849944 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2258 11:06:46.850329
2259 11:06:46.853423 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2260 11:06:46.856601 [DutyScan_Calibration_Flow] ====Done====
2261 11:06:46.856986
2262 11:06:46.859834 [DutyScan_Calibration_Flow] k_type=3
2263 11:06:46.875126
2264 11:06:46.875539 ==DQM 0 ==
2265 11:06:46.878351 Final DQM duty delay cell = -4
2266 11:06:46.881568 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2267 11:06:46.885046 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2268 11:06:46.888319 [-4] AVG Duty = 4953%(X100)
2269 11:06:46.888705
2270 11:06:46.889002 ==DQM 1 ==
2271 11:06:46.892080 Final DQM duty delay cell = -4
2272 11:06:46.894946 [-4] MAX Duty = 5094%(X100), DQS PI = 22
2273 11:06:46.898885 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2274 11:06:46.901589 [-4] AVG Duty = 5000%(X100)
2275 11:06:46.901972
2276 11:06:46.905371 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2277 11:06:46.905795
2278 11:06:46.908608 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2279 11:06:46.911936 [DutyScan_Calibration_Flow] ====Done====
2280 11:06:46.912314
2281 11:06:46.914986 [DutyScan_Calibration_Flow] k_type=2
2282 11:06:46.932190
2283 11:06:46.932611 ==DQ 0 ==
2284 11:06:46.935569 Final DQ duty delay cell = 0
2285 11:06:46.938749 [0] MAX Duty = 5062%(X100), DQS PI = 0
2286 11:06:46.942039 [0] MIN Duty = 4938%(X100), DQS PI = 44
2287 11:06:46.942424 [0] AVG Duty = 5000%(X100)
2288 11:06:46.942722
2289 11:06:46.946105 ==DQ 1 ==
2290 11:06:46.948786 Final DQ duty delay cell = 0
2291 11:06:46.952655 [0] MAX Duty = 5031%(X100), DQS PI = 8
2292 11:06:46.956014 [0] MIN Duty = 4907%(X100), DQS PI = 0
2293 11:06:46.956459 [0] AVG Duty = 4969%(X100)
2294 11:06:46.956792
2295 11:06:46.959060 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2296 11:06:46.959477
2297 11:06:46.962495 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2298 11:06:46.969063 [DutyScan_Calibration_Flow] ====Done====
2299 11:06:46.972252 nWR fixed to 30
2300 11:06:46.972737 [ModeRegInit_LP4] CH0 RK0
2301 11:06:46.975832 [ModeRegInit_LP4] CH0 RK1
2302 11:06:46.979176 [ModeRegInit_LP4] CH1 RK0
2303 11:06:46.979695 [ModeRegInit_LP4] CH1 RK1
2304 11:06:46.982456 match AC timing 6
2305 11:06:46.985412 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2306 11:06:46.989309 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2307 11:06:46.995693 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2308 11:06:46.998833 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2309 11:06:47.005471 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2310 11:06:47.005879 ==
2311 11:06:47.009153 Dram Type= 6, Freq= 0, CH_0, rank 0
2312 11:06:47.012372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2313 11:06:47.012724 ==
2314 11:06:47.019168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2315 11:06:47.022663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2316 11:06:47.031712 [CA 0] Center 39 (9~70) winsize 62
2317 11:06:47.035123 [CA 1] Center 39 (8~70) winsize 63
2318 11:06:47.039070 [CA 2] Center 36 (5~67) winsize 63
2319 11:06:47.042046 [CA 3] Center 35 (4~66) winsize 63
2320 11:06:47.045358 [CA 4] Center 34 (3~65) winsize 63
2321 11:06:47.048931 [CA 5] Center 33 (3~64) winsize 62
2322 11:06:47.049505
2323 11:06:47.052217 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2324 11:06:47.052659
2325 11:06:47.055849 [CATrainingPosCal] consider 1 rank data
2326 11:06:47.058798 u2DelayCellTimex100 = 270/100 ps
2327 11:06:47.062131 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2328 11:06:47.065604 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2329 11:06:47.072385 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2330 11:06:47.075363 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2331 11:06:47.079229 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2332 11:06:47.082063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2333 11:06:47.082485
2334 11:06:47.085621 CA PerBit enable=1, Macro0, CA PI delay=33
2335 11:06:47.086141
2336 11:06:47.088881 [CBTSetCACLKResult] CA Dly = 33
2337 11:06:47.089371 CS Dly: 7 (0~38)
2338 11:06:47.089768 ==
2339 11:06:47.092120 Dram Type= 6, Freq= 0, CH_0, rank 1
2340 11:06:47.099036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2341 11:06:47.099658 ==
2342 11:06:47.102079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2343 11:06:47.108741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2344 11:06:47.117367 [CA 0] Center 39 (8~70) winsize 63
2345 11:06:47.120577 [CA 1] Center 39 (8~70) winsize 63
2346 11:06:47.124045 [CA 2] Center 36 (5~67) winsize 63
2347 11:06:47.127262 [CA 3] Center 35 (4~66) winsize 63
2348 11:06:47.130560 [CA 4] Center 33 (3~64) winsize 62
2349 11:06:47.134027 [CA 5] Center 33 (3~64) winsize 62
2350 11:06:47.134442
2351 11:06:47.137437 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2352 11:06:47.138002
2353 11:06:47.140593 [CATrainingPosCal] consider 2 rank data
2354 11:06:47.144145 u2DelayCellTimex100 = 270/100 ps
2355 11:06:47.147176 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2356 11:06:47.150591 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2357 11:06:47.157621 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2358 11:06:47.161435 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2359 11:06:47.163983 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2360 11:06:47.167621 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2361 11:06:47.168157
2362 11:06:47.170679 CA PerBit enable=1, Macro0, CA PI delay=33
2363 11:06:47.171094
2364 11:06:47.174206 [CBTSetCACLKResult] CA Dly = 33
2365 11:06:47.174700 CS Dly: 7 (0~39)
2366 11:06:47.175024
2367 11:06:47.177322 ----->DramcWriteLeveling(PI) begin...
2368 11:06:47.180786 ==
2369 11:06:47.184166 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 11:06:47.187350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2371 11:06:47.187800 ==
2372 11:06:47.190630 Write leveling (Byte 0): 28 => 28
2373 11:06:47.193916 Write leveling (Byte 1): 28 => 28
2374 11:06:47.197368 DramcWriteLeveling(PI) end<-----
2375 11:06:47.197791
2376 11:06:47.198113 ==
2377 11:06:47.200502 Dram Type= 6, Freq= 0, CH_0, rank 0
2378 11:06:47.203904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2379 11:06:47.204322 ==
2380 11:06:47.207129 [Gating] SW mode calibration
2381 11:06:47.214090 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2382 11:06:47.217398 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2383 11:06:47.224049 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2384 11:06:47.227857 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2385 11:06:47.230997 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2386 11:06:47.237292 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2387 11:06:47.240402 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2388 11:06:47.243737 0 11 20 | B1->B0 | 2c2c 2828 | 1 0 | (1 0) (1 0)
2389 11:06:47.250728 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 11:06:47.253843 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 11:06:47.257213 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2392 11:06:47.264199 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 11:06:47.267303 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2394 11:06:47.270270 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 11:06:47.276986 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2396 11:06:47.280610 0 12 20 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
2397 11:06:47.283630 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 11:06:47.290417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 11:06:47.293704 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 11:06:47.297286 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 11:06:47.303721 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 11:06:47.307275 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 11:06:47.310579 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 11:06:47.316982 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2405 11:06:47.320505 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 11:06:47.324195 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 11:06:47.330530 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 11:06:47.333920 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 11:06:47.337991 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 11:06:47.340831 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 11:06:47.347431 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 11:06:47.350359 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 11:06:47.353746 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 11:06:47.360466 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 11:06:47.364186 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 11:06:47.367391 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 11:06:47.373940 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 11:06:47.377023 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 11:06:47.380950 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2420 11:06:47.387147 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2421 11:06:47.390419 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2422 11:06:47.393846 Total UI for P1: 0, mck2ui 16
2423 11:06:47.397122 best dqsien dly found for B0: ( 0, 15, 18)
2424 11:06:47.400446 Total UI for P1: 0, mck2ui 16
2425 11:06:47.404053 best dqsien dly found for B1: ( 0, 15, 20)
2426 11:06:47.407271 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2427 11:06:47.410391 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2428 11:06:47.410773
2429 11:06:47.413849 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2430 11:06:47.417221 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2431 11:06:47.420786 [Gating] SW calibration Done
2432 11:06:47.421278 ==
2433 11:06:47.424275 Dram Type= 6, Freq= 0, CH_0, rank 0
2434 11:06:47.427607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2435 11:06:47.428111 ==
2436 11:06:47.430770 RX Vref Scan: 0
2437 11:06:47.431275
2438 11:06:47.433930 RX Vref 0 -> 0, step: 1
2439 11:06:47.434436
2440 11:06:47.434769 RX Delay -40 -> 252, step: 8
2441 11:06:47.440600 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2442 11:06:47.444218 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2443 11:06:47.447588 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2444 11:06:47.450746 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2445 11:06:47.454069 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2446 11:06:47.460666 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2447 11:06:47.464395 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2448 11:06:47.467405 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2449 11:06:47.470962 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2450 11:06:47.474263 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2451 11:06:47.477816 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2452 11:06:47.484416 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2453 11:06:47.487407 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2454 11:06:47.491118 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2455 11:06:47.494081 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2456 11:06:47.500878 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2457 11:06:47.501409 ==
2458 11:06:47.504618 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 11:06:47.508043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2460 11:06:47.508574 ==
2461 11:06:47.509011 DQS Delay:
2462 11:06:47.511027 DQS0 = 0, DQS1 = 0
2463 11:06:47.511457 DQM Delay:
2464 11:06:47.514524 DQM0 = 115, DQM1 = 105
2465 11:06:47.514953 DQ Delay:
2466 11:06:47.517842 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2467 11:06:47.520859 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2468 11:06:47.524547 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2469 11:06:47.527917 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =111
2470 11:06:47.528424
2471 11:06:47.528858
2472 11:06:47.529293 ==
2473 11:06:47.531254 Dram Type= 6, Freq= 0, CH_0, rank 0
2474 11:06:47.537841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2475 11:06:47.538315 ==
2476 11:06:47.538745
2477 11:06:47.539149
2478 11:06:47.539540 TX Vref Scan disable
2479 11:06:47.541150 == TX Byte 0 ==
2480 11:06:47.544513 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2481 11:06:47.547906 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2482 11:06:47.551109 == TX Byte 1 ==
2483 11:06:47.554196 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2484 11:06:47.560940 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2485 11:06:47.561421 ==
2486 11:06:47.564224 Dram Type= 6, Freq= 0, CH_0, rank 0
2487 11:06:47.567609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2488 11:06:47.568047 ==
2489 11:06:47.578984 TX Vref=22, minBit 10, minWin=25, winSum=418
2490 11:06:47.582277 TX Vref=24, minBit 4, minWin=26, winSum=429
2491 11:06:47.585515 TX Vref=26, minBit 8, minWin=26, winSum=432
2492 11:06:47.589000 TX Vref=28, minBit 8, minWin=26, winSum=439
2493 11:06:47.592229 TX Vref=30, minBit 9, minWin=26, winSum=439
2494 11:06:47.599435 TX Vref=32, minBit 10, minWin=26, winSum=439
2495 11:06:47.602930 [TxChooseVref] Worse bit 8, Min win 26, Win sum 439, Final Vref 28
2496 11:06:47.603440
2497 11:06:47.605842 Final TX Range 1 Vref 28
2498 11:06:47.606360
2499 11:06:47.606687 ==
2500 11:06:47.608513 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 11:06:47.612151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2502 11:06:47.612654 ==
2503 11:06:47.615683
2504 11:06:47.616173
2505 11:06:47.616500 TX Vref Scan disable
2506 11:06:47.618939 == TX Byte 0 ==
2507 11:06:47.622149 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2508 11:06:47.625847 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2509 11:06:47.629040 == TX Byte 1 ==
2510 11:06:47.632189 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2511 11:06:47.635536 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2512 11:06:47.635962
2513 11:06:47.638516 [DATLAT]
2514 11:06:47.638932 Freq=1200, CH0 RK0
2515 11:06:47.639259
2516 11:06:47.642285 DATLAT Default: 0xd
2517 11:06:47.642706 0, 0xFFFF, sum = 0
2518 11:06:47.645661 1, 0xFFFF, sum = 0
2519 11:06:47.646191 2, 0xFFFF, sum = 0
2520 11:06:47.649206 3, 0xFFFF, sum = 0
2521 11:06:47.649756 4, 0xFFFF, sum = 0
2522 11:06:47.652101 5, 0xFFFF, sum = 0
2523 11:06:47.652527 6, 0xFFFF, sum = 0
2524 11:06:47.655570 7, 0xFFFF, sum = 0
2525 11:06:47.655995 8, 0xFFFF, sum = 0
2526 11:06:47.658815 9, 0xFFFF, sum = 0
2527 11:06:47.662070 10, 0xFFFF, sum = 0
2528 11:06:47.662569 11, 0x0, sum = 1
2529 11:06:47.662908 12, 0x0, sum = 2
2530 11:06:47.665357 13, 0x0, sum = 3
2531 11:06:47.665856 14, 0x0, sum = 4
2532 11:06:47.669329 best_step = 12
2533 11:06:47.669833
2534 11:06:47.670217 ==
2535 11:06:47.672130 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 11:06:47.675359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2537 11:06:47.675782 ==
2538 11:06:47.678945 RX Vref Scan: 1
2539 11:06:47.679446
2540 11:06:47.679769 Set Vref Range= 32 -> 127
2541 11:06:47.681930
2542 11:06:47.682348 RX Vref 32 -> 127, step: 1
2543 11:06:47.682676
2544 11:06:47.685661 RX Delay -21 -> 252, step: 4
2545 11:06:47.686164
2546 11:06:47.688813 Set Vref, RX VrefLevel [Byte0]: 32
2547 11:06:47.692062 [Byte1]: 32
2548 11:06:47.695346
2549 11:06:47.695844 Set Vref, RX VrefLevel [Byte0]: 33
2550 11:06:47.698652 [Byte1]: 33
2551 11:06:47.703361
2552 11:06:47.703779 Set Vref, RX VrefLevel [Byte0]: 34
2553 11:06:47.706365 [Byte1]: 34
2554 11:06:47.711349
2555 11:06:47.711765 Set Vref, RX VrefLevel [Byte0]: 35
2556 11:06:47.714503 [Byte1]: 35
2557 11:06:47.719179
2558 11:06:47.719670 Set Vref, RX VrefLevel [Byte0]: 36
2559 11:06:47.722400 [Byte1]: 36
2560 11:06:47.727406
2561 11:06:47.727897 Set Vref, RX VrefLevel [Byte0]: 37
2562 11:06:47.730677 [Byte1]: 37
2563 11:06:47.735043
2564 11:06:47.735543 Set Vref, RX VrefLevel [Byte0]: 38
2565 11:06:47.738160 [Byte1]: 38
2566 11:06:47.742635
2567 11:06:47.743051 Set Vref, RX VrefLevel [Byte0]: 39
2568 11:06:47.746087 [Byte1]: 39
2569 11:06:47.750880
2570 11:06:47.751381 Set Vref, RX VrefLevel [Byte0]: 40
2571 11:06:47.754325 [Byte1]: 40
2572 11:06:47.758503
2573 11:06:47.758966 Set Vref, RX VrefLevel [Byte0]: 41
2574 11:06:47.761815 [Byte1]: 41
2575 11:06:47.766597
2576 11:06:47.767016 Set Vref, RX VrefLevel [Byte0]: 42
2577 11:06:47.769966 [Byte1]: 42
2578 11:06:47.774360
2579 11:06:47.774778 Set Vref, RX VrefLevel [Byte0]: 43
2580 11:06:47.777965 [Byte1]: 43
2581 11:06:47.782263
2582 11:06:47.782720 Set Vref, RX VrefLevel [Byte0]: 44
2583 11:06:47.785654 [Byte1]: 44
2584 11:06:47.790144
2585 11:06:47.790589 Set Vref, RX VrefLevel [Byte0]: 45
2586 11:06:47.793747 [Byte1]: 45
2587 11:06:47.798261
2588 11:06:47.798724 Set Vref, RX VrefLevel [Byte0]: 46
2589 11:06:47.801310 [Byte1]: 46
2590 11:06:47.806370
2591 11:06:47.806812 Set Vref, RX VrefLevel [Byte0]: 47
2592 11:06:47.809604 [Byte1]: 47
2593 11:06:47.814096
2594 11:06:47.814607 Set Vref, RX VrefLevel [Byte0]: 48
2595 11:06:47.817321 [Byte1]: 48
2596 11:06:47.822191
2597 11:06:47.822609 Set Vref, RX VrefLevel [Byte0]: 49
2598 11:06:47.825199 [Byte1]: 49
2599 11:06:47.829908
2600 11:06:47.830281 Set Vref, RX VrefLevel [Byte0]: 50
2601 11:06:47.833110 [Byte1]: 50
2602 11:06:47.837624
2603 11:06:47.838005 Set Vref, RX VrefLevel [Byte0]: 51
2604 11:06:47.841425 [Byte1]: 51
2605 11:06:47.845743
2606 11:06:47.846205 Set Vref, RX VrefLevel [Byte0]: 52
2607 11:06:47.848962 [Byte1]: 52
2608 11:06:47.854020
2609 11:06:47.854535 Set Vref, RX VrefLevel [Byte0]: 53
2610 11:06:47.857112 [Byte1]: 53
2611 11:06:47.861661
2612 11:06:47.862092 Set Vref, RX VrefLevel [Byte0]: 54
2613 11:06:47.865206 [Byte1]: 54
2614 11:06:47.869355
2615 11:06:47.869930 Set Vref, RX VrefLevel [Byte0]: 55
2616 11:06:47.872784 [Byte1]: 55
2617 11:06:47.877746
2618 11:06:47.878123 Set Vref, RX VrefLevel [Byte0]: 56
2619 11:06:47.880692 [Byte1]: 56
2620 11:06:47.885581
2621 11:06:47.885958 Set Vref, RX VrefLevel [Byte0]: 57
2622 11:06:47.888804 [Byte1]: 57
2623 11:06:47.893518
2624 11:06:47.893908 Set Vref, RX VrefLevel [Byte0]: 58
2625 11:06:47.896522 [Byte1]: 58
2626 11:06:47.901644
2627 11:06:47.902026 Set Vref, RX VrefLevel [Byte0]: 59
2628 11:06:47.904641 [Byte1]: 59
2629 11:06:47.909189
2630 11:06:47.909619 Set Vref, RX VrefLevel [Byte0]: 60
2631 11:06:47.912494 [Byte1]: 60
2632 11:06:47.916977
2633 11:06:47.917389 Set Vref, RX VrefLevel [Byte0]: 61
2634 11:06:47.920166 [Byte1]: 61
2635 11:06:47.924773
2636 11:06:47.925149 Set Vref, RX VrefLevel [Byte0]: 62
2637 11:06:47.928433 [Byte1]: 62
2638 11:06:47.933099
2639 11:06:47.933658 Set Vref, RX VrefLevel [Byte0]: 63
2640 11:06:47.936207 [Byte1]: 63
2641 11:06:47.940712
2642 11:06:47.941130 Set Vref, RX VrefLevel [Byte0]: 64
2643 11:06:47.944098 [Byte1]: 64
2644 11:06:47.948813
2645 11:06:47.949540 Set Vref, RX VrefLevel [Byte0]: 65
2646 11:06:47.951926 [Byte1]: 65
2647 11:06:47.956555
2648 11:06:47.956947 Final RX Vref Byte 0 = 51 to rank0
2649 11:06:47.959842 Final RX Vref Byte 1 = 45 to rank0
2650 11:06:47.963412 Final RX Vref Byte 0 = 51 to rank1
2651 11:06:47.966590 Final RX Vref Byte 1 = 45 to rank1==
2652 11:06:47.969893 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 11:06:47.976644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2654 11:06:47.977031 ==
2655 11:06:47.977373 DQS Delay:
2656 11:06:47.977660 DQS0 = 0, DQS1 = 0
2657 11:06:47.979973 DQM Delay:
2658 11:06:47.980355 DQM0 = 114, DQM1 = 104
2659 11:06:47.983570 DQ Delay:
2660 11:06:47.986626 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =110
2661 11:06:47.989843 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2662 11:06:47.993102 DQ8 =94, DQ9 =84, DQ10 =106, DQ11 =96
2663 11:06:47.996594 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2664 11:06:47.996980
2665 11:06:47.997323
2666 11:06:48.003509 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2667 11:06:48.006416 CH0 RK0: MR19=404, MR18=D0D
2668 11:06:48.013361 CH0_RK0: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2669 11:06:48.013812
2670 11:06:48.016634 ----->DramcWriteLeveling(PI) begin...
2671 11:06:48.017065 ==
2672 11:06:48.019995 Dram Type= 6, Freq= 0, CH_0, rank 1
2673 11:06:48.023231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2674 11:06:48.023622 ==
2675 11:06:48.026376 Write leveling (Byte 0): 28 => 28
2676 11:06:48.030121 Write leveling (Byte 1): 26 => 26
2677 11:06:48.033768 DramcWriteLeveling(PI) end<-----
2678 11:06:48.034153
2679 11:06:48.034452 ==
2680 11:06:48.036969 Dram Type= 6, Freq= 0, CH_0, rank 1
2681 11:06:48.040068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2682 11:06:48.043457 ==
2683 11:06:48.043854 [Gating] SW mode calibration
2684 11:06:48.050046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2685 11:06:48.056740 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2686 11:06:48.060119 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2687 11:06:48.066475 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2688 11:06:48.070017 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2689 11:06:48.073321 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2690 11:06:48.079873 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2691 11:06:48.083264 0 11 20 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
2692 11:06:48.086584 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 11:06:48.093439 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2694 11:06:48.096505 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2695 11:06:48.100560 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2696 11:06:48.107206 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 11:06:48.109924 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 11:06:48.113285 0 12 16 | B1->B0 | 2828 3939 | 0 0 | (0 0) (0 0)
2699 11:06:48.116779 0 12 20 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
2700 11:06:48.123344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 11:06:48.126708 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2702 11:06:48.129920 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2703 11:06:48.136861 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2704 11:06:48.140128 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 11:06:48.143381 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 11:06:48.150323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2707 11:06:48.153302 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 11:06:48.157056 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 11:06:48.163475 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 11:06:48.167017 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 11:06:48.170423 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 11:06:48.177008 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 11:06:48.180245 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 11:06:48.183473 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 11:06:48.190364 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 11:06:48.193399 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 11:06:48.197281 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 11:06:48.200283 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 11:06:48.206732 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 11:06:48.210063 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 11:06:48.213686 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 11:06:48.220273 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2723 11:06:48.223991 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2724 11:06:48.226694 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2725 11:06:48.230212 Total UI for P1: 0, mck2ui 16
2726 11:06:48.233528 best dqsien dly found for B0: ( 0, 15, 18)
2727 11:06:48.236706 Total UI for P1: 0, mck2ui 16
2728 11:06:48.240182 best dqsien dly found for B1: ( 0, 15, 20)
2729 11:06:48.243624 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2730 11:06:48.247081 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2731 11:06:48.247466
2732 11:06:48.253196 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2733 11:06:48.256709 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2734 11:06:48.260082 [Gating] SW calibration Done
2735 11:06:48.260466 ==
2736 11:06:48.263498 Dram Type= 6, Freq= 0, CH_0, rank 1
2737 11:06:48.266705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2738 11:06:48.267093 ==
2739 11:06:48.267394 RX Vref Scan: 0
2740 11:06:48.267673
2741 11:06:48.270018 RX Vref 0 -> 0, step: 1
2742 11:06:48.270401
2743 11:06:48.273350 RX Delay -40 -> 252, step: 8
2744 11:06:48.277074 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2745 11:06:48.280336 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2746 11:06:48.286866 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2747 11:06:48.290119 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2748 11:06:48.293482 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2749 11:06:48.296590 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2750 11:06:48.299986 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2751 11:06:48.303413 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2752 11:06:48.310305 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2753 11:06:48.313114 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2754 11:06:48.316686 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2755 11:06:48.320098 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2756 11:06:48.323263 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2757 11:06:48.329989 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2758 11:06:48.333722 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2759 11:06:48.336902 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2760 11:06:48.337390 ==
2761 11:06:48.340103 Dram Type= 6, Freq= 0, CH_0, rank 1
2762 11:06:48.343651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2763 11:06:48.344112 ==
2764 11:06:48.346610 DQS Delay:
2765 11:06:48.346996 DQS0 = 0, DQS1 = 0
2766 11:06:48.350260 DQM Delay:
2767 11:06:48.350697 DQM0 = 115, DQM1 = 107
2768 11:06:48.350994 DQ Delay:
2769 11:06:48.356859 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =107
2770 11:06:48.360337 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2771 11:06:48.363531 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2772 11:06:48.367746 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2773 11:06:48.368129
2774 11:06:48.368425
2775 11:06:48.368819 ==
2776 11:06:48.370235 Dram Type= 6, Freq= 0, CH_0, rank 1
2777 11:06:48.373463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2778 11:06:48.373878 ==
2779 11:06:48.374183
2780 11:06:48.374457
2781 11:06:48.376904 TX Vref Scan disable
2782 11:06:48.380707 == TX Byte 0 ==
2783 11:06:48.383495 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2784 11:06:48.387035 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2785 11:06:48.389890 == TX Byte 1 ==
2786 11:06:48.393693 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2787 11:06:48.397298 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2788 11:06:48.397775 ==
2789 11:06:48.400522 Dram Type= 6, Freq= 0, CH_0, rank 1
2790 11:06:48.403724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2791 11:06:48.404210 ==
2792 11:06:48.416882 TX Vref=22, minBit 8, minWin=25, winSum=417
2793 11:06:48.419834 TX Vref=24, minBit 9, minWin=25, winSum=425
2794 11:06:48.423336 TX Vref=26, minBit 1, minWin=26, winSum=430
2795 11:06:48.427016 TX Vref=28, minBit 9, minWin=26, winSum=432
2796 11:06:48.430179 TX Vref=30, minBit 9, minWin=26, winSum=432
2797 11:06:48.433926 TX Vref=32, minBit 10, minWin=25, winSum=434
2798 11:06:48.440258 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
2799 11:06:48.440687
2800 11:06:48.443813 Final TX Range 1 Vref 28
2801 11:06:48.444319
2802 11:06:48.444651 ==
2803 11:06:48.446693 Dram Type= 6, Freq= 0, CH_0, rank 1
2804 11:06:48.450188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2805 11:06:48.450617 ==
2806 11:06:48.450946
2807 11:06:48.451247
2808 11:06:48.453348 TX Vref Scan disable
2809 11:06:48.456996 == TX Byte 0 ==
2810 11:06:48.460298 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2811 11:06:48.463421 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2812 11:06:48.466573 == TX Byte 1 ==
2813 11:06:48.470315 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2814 11:06:48.473343 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2815 11:06:48.473812
2816 11:06:48.477093 [DATLAT]
2817 11:06:48.477660 Freq=1200, CH0 RK1
2818 11:06:48.478004
2819 11:06:48.480238 DATLAT Default: 0xc
2820 11:06:48.480740 0, 0xFFFF, sum = 0
2821 11:06:48.483761 1, 0xFFFF, sum = 0
2822 11:06:48.484271 2, 0xFFFF, sum = 0
2823 11:06:48.486957 3, 0xFFFF, sum = 0
2824 11:06:48.487468 4, 0xFFFF, sum = 0
2825 11:06:48.490283 5, 0xFFFF, sum = 0
2826 11:06:48.490709 6, 0xFFFF, sum = 0
2827 11:06:48.493399 7, 0xFFFF, sum = 0
2828 11:06:48.493827 8, 0xFFFF, sum = 0
2829 11:06:48.496756 9, 0xFFFF, sum = 0
2830 11:06:48.499944 10, 0xFFFF, sum = 0
2831 11:06:48.500381 11, 0x0, sum = 1
2832 11:06:48.500721 12, 0x0, sum = 2
2833 11:06:48.503192 13, 0x0, sum = 3
2834 11:06:48.503623 14, 0x0, sum = 4
2835 11:06:48.506573 best_step = 12
2836 11:06:48.506996
2837 11:06:48.507360 ==
2838 11:06:48.510024 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 11:06:48.513475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2840 11:06:48.513907 ==
2841 11:06:48.516570 RX Vref Scan: 0
2842 11:06:48.516993
2843 11:06:48.517371 RX Vref 0 -> 0, step: 1
2844 11:06:48.517689
2845 11:06:48.519973 RX Delay -21 -> 252, step: 4
2846 11:06:48.526955 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2847 11:06:48.530488 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2848 11:06:48.533815 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2849 11:06:48.537283 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2850 11:06:48.540437 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2851 11:06:48.547254 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2852 11:06:48.550276 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2853 11:06:48.553993 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2854 11:06:48.557142 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2855 11:06:48.560606 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2856 11:06:48.566974 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2857 11:06:48.570230 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2858 11:06:48.573931 iDelay=199, Bit 12, Center 110 (47 ~ 174) 128
2859 11:06:48.577083 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2860 11:06:48.580503 iDelay=199, Bit 14, Center 116 (55 ~ 178) 124
2861 11:06:48.586989 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2862 11:06:48.587443 ==
2863 11:06:48.590301 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 11:06:48.593974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2865 11:06:48.594409 ==
2866 11:06:48.594713 DQS Delay:
2867 11:06:48.597045 DQS0 = 0, DQS1 = 0
2868 11:06:48.597471 DQM Delay:
2869 11:06:48.600296 DQM0 = 115, DQM1 = 105
2870 11:06:48.600679 DQ Delay:
2871 11:06:48.603654 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2872 11:06:48.607139 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2873 11:06:48.610363 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2874 11:06:48.613789 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
2875 11:06:48.614176
2876 11:06:48.614475
2877 11:06:48.623650 [DQSOSCAuto] RK1, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
2878 11:06:48.626990 CH0 RK1: MR19=404, MR18=1818
2879 11:06:48.630763 CH0_RK1: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
2880 11:06:48.633641 [RxdqsGatingPostProcess] freq 1200
2881 11:06:48.640453 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2882 11:06:48.644031 Pre-setting of DQS Precalculation
2883 11:06:48.646893 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2884 11:06:48.647280 ==
2885 11:06:48.650134 Dram Type= 6, Freq= 0, CH_1, rank 0
2886 11:06:48.657209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2887 11:06:48.657713 ==
2888 11:06:48.660421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2889 11:06:48.667036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2890 11:06:48.675477 [CA 0] Center 37 (7~68) winsize 62
2891 11:06:48.679026 [CA 1] Center 37 (7~68) winsize 62
2892 11:06:48.682164 [CA 2] Center 34 (4~65) winsize 62
2893 11:06:48.685503 [CA 3] Center 33 (3~64) winsize 62
2894 11:06:48.688554 [CA 4] Center 32 (2~63) winsize 62
2895 11:06:48.692361 [CA 5] Center 32 (2~63) winsize 62
2896 11:06:48.692591
2897 11:06:48.695551 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2898 11:06:48.695794
2899 11:06:48.698844 [CATrainingPosCal] consider 1 rank data
2900 11:06:48.701872 u2DelayCellTimex100 = 270/100 ps
2901 11:06:48.705453 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2902 11:06:48.708586 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2903 11:06:48.715187 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2904 11:06:48.718563 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2905 11:06:48.722068 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2906 11:06:48.725381 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2907 11:06:48.725683
2908 11:06:48.728669 CA PerBit enable=1, Macro0, CA PI delay=32
2909 11:06:48.728965
2910 11:06:48.731937 [CBTSetCACLKResult] CA Dly = 32
2911 11:06:48.732234 CS Dly: 5 (0~36)
2912 11:06:48.732532 ==
2913 11:06:48.735217 Dram Type= 6, Freq= 0, CH_1, rank 1
2914 11:06:48.742237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2915 11:06:48.742592 ==
2916 11:06:48.745456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2917 11:06:48.752172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2918 11:06:48.760745 [CA 0] Center 37 (6~68) winsize 63
2919 11:06:48.764040 [CA 1] Center 37 (7~68) winsize 62
2920 11:06:48.767255 [CA 2] Center 34 (3~65) winsize 63
2921 11:06:48.770769 [CA 3] Center 33 (3~64) winsize 62
2922 11:06:48.774466 [CA 4] Center 32 (2~63) winsize 62
2923 11:06:48.777508 [CA 5] Center 32 (1~63) winsize 63
2924 11:06:48.777936
2925 11:06:48.781028 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2926 11:06:48.781554
2927 11:06:48.784044 [CATrainingPosCal] consider 2 rank data
2928 11:06:48.787672 u2DelayCellTimex100 = 270/100 ps
2929 11:06:48.790580 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2930 11:06:48.797297 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2931 11:06:48.800869 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2932 11:06:48.803799 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2933 11:06:48.807300 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2934 11:06:48.810517 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2935 11:06:48.810947
2936 11:06:48.813867 CA PerBit enable=1, Macro0, CA PI delay=32
2937 11:06:48.814323
2938 11:06:48.817810 [CBTSetCACLKResult] CA Dly = 32
2939 11:06:48.818308 CS Dly: 6 (0~38)
2940 11:06:48.818739
2941 11:06:48.820498 ----->DramcWriteLeveling(PI) begin...
2942 11:06:48.823584 ==
2943 11:06:48.827273 Dram Type= 6, Freq= 0, CH_1, rank 0
2944 11:06:48.830358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2945 11:06:48.830789 ==
2946 11:06:48.833773 Write leveling (Byte 0): 21 => 21
2947 11:06:48.837296 Write leveling (Byte 1): 21 => 21
2948 11:06:48.840447 DramcWriteLeveling(PI) end<-----
2949 11:06:48.840873
2950 11:06:48.841395 ==
2951 11:06:48.843617 Dram Type= 6, Freq= 0, CH_1, rank 0
2952 11:06:48.847004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2953 11:06:48.847469 ==
2954 11:06:48.850649 [Gating] SW mode calibration
2955 11:06:48.857032 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2956 11:06:48.863728 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2957 11:06:48.866934 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 11:06:48.870622 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 11:06:48.876860 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2960 11:06:48.880215 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2961 11:06:48.883484 0 11 16 | B1->B0 | 3131 2424 | 0 0 | (0 0) (1 0)
2962 11:06:48.887339 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2963 11:06:48.893821 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 11:06:48.897292 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 11:06:48.900523 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 11:06:48.907254 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 11:06:48.910562 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 11:06:48.913714 0 12 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2969 11:06:48.920679 0 12 16 | B1->B0 | 3232 4444 | 1 0 | (0 0) (0 0)
2970 11:06:48.924228 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 11:06:48.927358 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 11:06:48.934051 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 11:06:48.937607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 11:06:48.940350 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 11:06:48.946988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 11:06:48.950522 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 11:06:48.954078 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2978 11:06:48.960536 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2979 11:06:48.964117 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:06:48.967207 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:06:48.970656 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:06:48.977267 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:06:48.980486 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 11:06:48.983944 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 11:06:48.990486 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 11:06:48.993668 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 11:06:48.997153 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 11:06:49.003845 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 11:06:49.007243 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 11:06:49.010441 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 11:06:49.017076 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 11:06:49.020392 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2993 11:06:49.023727 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2994 11:06:49.026852 Total UI for P1: 0, mck2ui 16
2995 11:06:49.030362 best dqsien dly found for B0: ( 0, 15, 12)
2996 11:06:49.036813 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2997 11:06:49.040805 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2998 11:06:49.043728 Total UI for P1: 0, mck2ui 16
2999 11:06:49.047022 best dqsien dly found for B1: ( 0, 15, 18)
3000 11:06:49.050503 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3001 11:06:49.053715 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3002 11:06:49.054142
3003 11:06:49.056834 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3004 11:06:49.060386 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3005 11:06:49.063697 [Gating] SW calibration Done
3006 11:06:49.064083 ==
3007 11:06:49.066847 Dram Type= 6, Freq= 0, CH_1, rank 0
3008 11:06:49.070401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3009 11:06:49.073447 ==
3010 11:06:49.073832 RX Vref Scan: 0
3011 11:06:49.074129
3012 11:06:49.077072 RX Vref 0 -> 0, step: 1
3013 11:06:49.077506
3014 11:06:49.080165 RX Delay -40 -> 252, step: 8
3015 11:06:49.083750 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3016 11:06:49.086952 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3017 11:06:49.090490 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3018 11:06:49.093663 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3019 11:06:49.100219 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3020 11:06:49.103614 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3021 11:06:49.107049 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3022 11:06:49.110089 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3023 11:06:49.113492 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3024 11:06:49.117176 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3025 11:06:49.123354 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3026 11:06:49.126892 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3027 11:06:49.130068 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3028 11:06:49.133646 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3029 11:06:49.137010 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3030 11:06:49.143563 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3031 11:06:49.143989 ==
3032 11:06:49.147014 Dram Type= 6, Freq= 0, CH_1, rank 0
3033 11:06:49.150389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3034 11:06:49.150780 ==
3035 11:06:49.151078 DQS Delay:
3036 11:06:49.153730 DQS0 = 0, DQS1 = 0
3037 11:06:49.154189 DQM Delay:
3038 11:06:49.157148 DQM0 = 116, DQM1 = 109
3039 11:06:49.157678 DQ Delay:
3040 11:06:49.160320 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3041 11:06:49.163595 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3042 11:06:49.167250 DQ8 =91, DQ9 =99, DQ10 =107, DQ11 =99
3043 11:06:49.170245 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3044 11:06:49.170636
3045 11:06:49.170940
3046 11:06:49.173642 ==
3047 11:06:49.174031 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 11:06:49.180455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3049 11:06:49.180884 ==
3050 11:06:49.181193
3051 11:06:49.181523
3052 11:06:49.184004 TX Vref Scan disable
3053 11:06:49.184462 == TX Byte 0 ==
3054 11:06:49.187412 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3055 11:06:49.193828 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3056 11:06:49.194289 == TX Byte 1 ==
3057 11:06:49.197355 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3058 11:06:49.203684 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3059 11:06:49.204133 ==
3060 11:06:49.207591 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 11:06:49.210533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3062 11:06:49.210922 ==
3063 11:06:49.221726 TX Vref=22, minBit 9, minWin=24, winSum=411
3064 11:06:49.225217 TX Vref=24, minBit 9, minWin=25, winSum=418
3065 11:06:49.228410 TX Vref=26, minBit 0, minWin=26, winSum=424
3066 11:06:49.231557 TX Vref=28, minBit 5, minWin=26, winSum=430
3067 11:06:49.235398 TX Vref=30, minBit 9, minWin=25, winSum=431
3068 11:06:49.238367 TX Vref=32, minBit 3, minWin=26, winSum=426
3069 11:06:49.245158 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
3070 11:06:49.245602
3071 11:06:49.248445 Final TX Range 1 Vref 28
3072 11:06:49.248845
3073 11:06:49.249267 ==
3074 11:06:49.251736 Dram Type= 6, Freq= 0, CH_1, rank 0
3075 11:06:49.255299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3076 11:06:49.255701 ==
3077 11:06:49.256096
3078 11:06:49.256464
3079 11:06:49.258259 TX Vref Scan disable
3080 11:06:49.261882 == TX Byte 0 ==
3081 11:06:49.265368 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3082 11:06:49.268648 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3083 11:06:49.272057 == TX Byte 1 ==
3084 11:06:49.275692 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3085 11:06:49.278353 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3086 11:06:49.278750
3087 11:06:49.281957 [DATLAT]
3088 11:06:49.282353 Freq=1200, CH1 RK0
3089 11:06:49.282753
3090 11:06:49.285211 DATLAT Default: 0xd
3091 11:06:49.285650 0, 0xFFFF, sum = 0
3092 11:06:49.288456 1, 0xFFFF, sum = 0
3093 11:06:49.289104 2, 0xFFFF, sum = 0
3094 11:06:49.291885 3, 0xFFFF, sum = 0
3095 11:06:49.292343 4, 0xFFFF, sum = 0
3096 11:06:49.295236 5, 0xFFFF, sum = 0
3097 11:06:49.295662 6, 0xFFFF, sum = 0
3098 11:06:49.298434 7, 0xFFFF, sum = 0
3099 11:06:49.298862 8, 0xFFFF, sum = 0
3100 11:06:49.302059 9, 0xFFFF, sum = 0
3101 11:06:49.305076 10, 0xFFFF, sum = 0
3102 11:06:49.305657 11, 0x0, sum = 1
3103 11:06:49.306132 12, 0x0, sum = 2
3104 11:06:49.308211 13, 0x0, sum = 3
3105 11:06:49.308603 14, 0x0, sum = 4
3106 11:06:49.311699 best_step = 12
3107 11:06:49.312083
3108 11:06:49.312380 ==
3109 11:06:49.315092 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 11:06:49.318437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3111 11:06:49.318824 ==
3112 11:06:49.321610 RX Vref Scan: 1
3113 11:06:49.322126
3114 11:06:49.322578 Set Vref Range= 32 -> 127
3115 11:06:49.322994
3116 11:06:49.324901 RX Vref 32 -> 127, step: 1
3117 11:06:49.325332
3118 11:06:49.328411 RX Delay -21 -> 252, step: 4
3119 11:06:49.328924
3120 11:06:49.331636 Set Vref, RX VrefLevel [Byte0]: 32
3121 11:06:49.335335 [Byte1]: 32
3122 11:06:49.335720
3123 11:06:49.338170 Set Vref, RX VrefLevel [Byte0]: 33
3124 11:06:49.341563 [Byte1]: 33
3125 11:06:49.345839
3126 11:06:49.346226 Set Vref, RX VrefLevel [Byte0]: 34
3127 11:06:49.349359 [Byte1]: 34
3128 11:06:49.354101
3129 11:06:49.354484 Set Vref, RX VrefLevel [Byte0]: 35
3130 11:06:49.357204 [Byte1]: 35
3131 11:06:49.361885
3132 11:06:49.362266 Set Vref, RX VrefLevel [Byte0]: 36
3133 11:06:49.365111 [Byte1]: 36
3134 11:06:49.369937
3135 11:06:49.370350 Set Vref, RX VrefLevel [Byte0]: 37
3136 11:06:49.373000 [Byte1]: 37
3137 11:06:49.377580
3138 11:06:49.378004 Set Vref, RX VrefLevel [Byte0]: 38
3139 11:06:49.381128 [Byte1]: 38
3140 11:06:49.385416
3141 11:06:49.389145 Set Vref, RX VrefLevel [Byte0]: 39
3142 11:06:49.392381 [Byte1]: 39
3143 11:06:49.392778
3144 11:06:49.395588 Set Vref, RX VrefLevel [Byte0]: 40
3145 11:06:49.398964 [Byte1]: 40
3146 11:06:49.399361
3147 11:06:49.402006 Set Vref, RX VrefLevel [Byte0]: 41
3148 11:06:49.405258 [Byte1]: 41
3149 11:06:49.409274
3150 11:06:49.409671 Set Vref, RX VrefLevel [Byte0]: 42
3151 11:06:49.412596 [Byte1]: 42
3152 11:06:49.417406
3153 11:06:49.417801 Set Vref, RX VrefLevel [Byte0]: 43
3154 11:06:49.420705 [Byte1]: 43
3155 11:06:49.425410
3156 11:06:49.425910 Set Vref, RX VrefLevel [Byte0]: 44
3157 11:06:49.428868 [Byte1]: 44
3158 11:06:49.433288
3159 11:06:49.433735 Set Vref, RX VrefLevel [Byte0]: 45
3160 11:06:49.436451 [Byte1]: 45
3161 11:06:49.441417
3162 11:06:49.441841 Set Vref, RX VrefLevel [Byte0]: 46
3163 11:06:49.444334 [Byte1]: 46
3164 11:06:49.449001
3165 11:06:49.449458 Set Vref, RX VrefLevel [Byte0]: 47
3166 11:06:49.452003 [Byte1]: 47
3167 11:06:49.456564
3168 11:06:49.456982 Set Vref, RX VrefLevel [Byte0]: 48
3169 11:06:49.460117 [Byte1]: 48
3170 11:06:49.464496
3171 11:06:49.464999 Set Vref, RX VrefLevel [Byte0]: 49
3172 11:06:49.468008 [Byte1]: 49
3173 11:06:49.472923
3174 11:06:49.473466 Set Vref, RX VrefLevel [Byte0]: 50
3175 11:06:49.476291 [Byte1]: 50
3176 11:06:49.480713
3177 11:06:49.481265 Set Vref, RX VrefLevel [Byte0]: 51
3178 11:06:49.484129 [Byte1]: 51
3179 11:06:49.489150
3180 11:06:49.489715 Set Vref, RX VrefLevel [Byte0]: 52
3181 11:06:49.492423 [Byte1]: 52
3182 11:06:49.496674
3183 11:06:49.497181 Set Vref, RX VrefLevel [Byte0]: 53
3184 11:06:49.500156 [Byte1]: 53
3185 11:06:49.504448
3186 11:06:49.504952 Set Vref, RX VrefLevel [Byte0]: 54
3187 11:06:49.507460 [Byte1]: 54
3188 11:06:49.512230
3189 11:06:49.512671 Set Vref, RX VrefLevel [Byte0]: 55
3190 11:06:49.515531 [Byte1]: 55
3191 11:06:49.520293
3192 11:06:49.520730 Set Vref, RX VrefLevel [Byte0]: 56
3193 11:06:49.524021 [Byte1]: 56
3194 11:06:49.528513
3195 11:06:49.528991 Set Vref, RX VrefLevel [Byte0]: 57
3196 11:06:49.531464 [Byte1]: 57
3197 11:06:49.536458
3198 11:06:49.536973 Set Vref, RX VrefLevel [Byte0]: 58
3199 11:06:49.539498 [Byte1]: 58
3200 11:06:49.543991
3201 11:06:49.544449 Set Vref, RX VrefLevel [Byte0]: 59
3202 11:06:49.547198 [Byte1]: 59
3203 11:06:49.552231
3204 11:06:49.552669 Set Vref, RX VrefLevel [Byte0]: 60
3205 11:06:49.555766 [Byte1]: 60
3206 11:06:49.559902
3207 11:06:49.560380 Set Vref, RX VrefLevel [Byte0]: 61
3208 11:06:49.563205 [Byte1]: 61
3209 11:06:49.568004
3210 11:06:49.568534 Set Vref, RX VrefLevel [Byte0]: 62
3211 11:06:49.571097 [Byte1]: 62
3212 11:06:49.576063
3213 11:06:49.576568 Set Vref, RX VrefLevel [Byte0]: 63
3214 11:06:49.579087 [Byte1]: 63
3215 11:06:49.583588
3216 11:06:49.584028 Set Vref, RX VrefLevel [Byte0]: 64
3217 11:06:49.586950 [Byte1]: 64
3218 11:06:49.591648
3219 11:06:49.592163 Set Vref, RX VrefLevel [Byte0]: 65
3220 11:06:49.595409 [Byte1]: 65
3221 11:06:49.599787
3222 11:06:49.600307 Set Vref, RX VrefLevel [Byte0]: 66
3223 11:06:49.602791 [Byte1]: 66
3224 11:06:49.607282
3225 11:06:49.607753 Final RX Vref Byte 0 = 52 to rank0
3226 11:06:49.610684 Final RX Vref Byte 1 = 48 to rank0
3227 11:06:49.613993 Final RX Vref Byte 0 = 52 to rank1
3228 11:06:49.617140 Final RX Vref Byte 1 = 48 to rank1==
3229 11:06:49.620786 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 11:06:49.627434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3231 11:06:49.627935 ==
3232 11:06:49.628272 DQS Delay:
3233 11:06:49.630994 DQS0 = 0, DQS1 = 0
3234 11:06:49.631493 DQM Delay:
3235 11:06:49.631826 DQM0 = 115, DQM1 = 105
3236 11:06:49.633624 DQ Delay:
3237 11:06:49.637251 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3238 11:06:49.640657 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3239 11:06:49.643814 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3240 11:06:49.646869 DQ12 =112, DQ13 =114, DQ14 =114, DQ15 =114
3241 11:06:49.647292
3242 11:06:49.647619
3243 11:06:49.657028 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3244 11:06:49.657603 CH1 RK0: MR19=404, MR18=1717
3245 11:06:49.663492 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3246 11:06:49.663958
3247 11:06:49.667208 ----->DramcWriteLeveling(PI) begin...
3248 11:06:49.667747 ==
3249 11:06:49.670491 Dram Type= 6, Freq= 0, CH_1, rank 1
3250 11:06:49.676790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3251 11:06:49.677298 ==
3252 11:06:49.680325 Write leveling (Byte 0): 20 => 20
3253 11:06:49.680749 Write leveling (Byte 1): 20 => 20
3254 11:06:49.683814 DramcWriteLeveling(PI) end<-----
3255 11:06:49.684468
3256 11:06:49.686861 ==
3257 11:06:49.687363 Dram Type= 6, Freq= 0, CH_1, rank 1
3258 11:06:49.693284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3259 11:06:49.693730 ==
3260 11:06:49.696937 [Gating] SW mode calibration
3261 11:06:49.703038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3262 11:06:49.706577 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3263 11:06:49.712845 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3264 11:06:49.716692 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3265 11:06:49.719888 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3266 11:06:49.726380 0 11 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3267 11:06:49.729564 0 11 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
3268 11:06:49.732765 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 11:06:49.739708 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 11:06:49.743271 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3271 11:06:49.746376 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 11:06:49.752922 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3273 11:06:49.756331 0 12 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3274 11:06:49.759565 0 12 12 | B1->B0 | 2424 3e3e | 0 0 | (0 0) (0 0)
3275 11:06:49.766560 0 12 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3276 11:06:49.769315 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 11:06:49.772926 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 11:06:49.779626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 11:06:49.782806 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 11:06:49.786399 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 11:06:49.792982 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 11:06:49.796183 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3283 11:06:49.799468 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3284 11:06:49.803021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 11:06:49.809353 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 11:06:49.812910 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 11:06:49.816010 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 11:06:49.822634 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 11:06:49.825885 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 11:06:49.829813 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 11:06:49.835908 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 11:06:49.839315 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 11:06:49.842592 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 11:06:49.849102 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 11:06:49.852627 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 11:06:49.856299 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 11:06:49.862550 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 11:06:49.865969 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3299 11:06:49.869286 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3300 11:06:49.872566 Total UI for P1: 0, mck2ui 16
3301 11:06:49.875848 best dqsien dly found for B0: ( 0, 15, 12)
3302 11:06:49.882681 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3303 11:06:49.883153 Total UI for P1: 0, mck2ui 16
3304 11:06:49.889108 best dqsien dly found for B1: ( 0, 15, 16)
3305 11:06:49.892236 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3306 11:06:49.895763 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3307 11:06:49.896182
3308 11:06:49.898878 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3309 11:06:49.902189 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3310 11:06:49.905612 [Gating] SW calibration Done
3311 11:06:49.906033 ==
3312 11:06:49.908649 Dram Type= 6, Freq= 0, CH_1, rank 1
3313 11:06:49.912014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3314 11:06:49.912283 ==
3315 11:06:49.915211 RX Vref Scan: 0
3316 11:06:49.915479
3317 11:06:49.915687 RX Vref 0 -> 0, step: 1
3318 11:06:49.918386
3319 11:06:49.918587 RX Delay -40 -> 252, step: 8
3320 11:06:49.924905 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3321 11:06:49.928308 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3322 11:06:49.931622 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3323 11:06:49.935343 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3324 11:06:49.938702 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3325 11:06:49.945519 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3326 11:06:49.948733 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3327 11:06:49.951925 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3328 11:06:49.955365 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3329 11:06:49.958505 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3330 11:06:49.961957 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3331 11:06:49.968380 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3332 11:06:49.972023 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3333 11:06:49.974958 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3334 11:06:49.978380 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3335 11:06:49.985355 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3336 11:06:49.985818 ==
3337 11:06:49.988346 Dram Type= 6, Freq= 0, CH_1, rank 1
3338 11:06:49.991609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3339 11:06:49.992050 ==
3340 11:06:49.992375 DQS Delay:
3341 11:06:49.995338 DQS0 = 0, DQS1 = 0
3342 11:06:49.995802 DQM Delay:
3343 11:06:49.998468 DQM0 = 114, DQM1 = 105
3344 11:06:49.998931 DQ Delay:
3345 11:06:50.001652 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =107
3346 11:06:50.004753 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =107
3347 11:06:50.007977 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
3348 11:06:50.011590 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3349 11:06:50.012009
3350 11:06:50.012335
3351 11:06:50.012633 ==
3352 11:06:50.014907 Dram Type= 6, Freq= 0, CH_1, rank 1
3353 11:06:50.021371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3354 11:06:50.021795 ==
3355 11:06:50.022119
3356 11:06:50.022415
3357 11:06:50.022700 TX Vref Scan disable
3358 11:06:50.025190 == TX Byte 0 ==
3359 11:06:50.028418 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3360 11:06:50.031928 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3361 11:06:50.035131 == TX Byte 1 ==
3362 11:06:50.038736 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3363 11:06:50.041943 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3364 11:06:50.045392 ==
3365 11:06:50.048352 Dram Type= 6, Freq= 0, CH_1, rank 1
3366 11:06:50.052212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3367 11:06:50.052630 ==
3368 11:06:50.063007 TX Vref=22, minBit 3, minWin=25, winSum=421
3369 11:06:50.066089 TX Vref=24, minBit 9, minWin=25, winSum=427
3370 11:06:50.069380 TX Vref=26, minBit 9, minWin=25, winSum=425
3371 11:06:50.072666 TX Vref=28, minBit 9, minWin=26, winSum=432
3372 11:06:50.076024 TX Vref=30, minBit 9, minWin=26, winSum=431
3373 11:06:50.082343 TX Vref=32, minBit 9, minWin=26, winSum=432
3374 11:06:50.085782 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3375 11:06:50.086319
3376 11:06:50.089131 Final TX Range 1 Vref 28
3377 11:06:50.089704
3378 11:06:50.090176 ==
3379 11:06:50.092509 Dram Type= 6, Freq= 0, CH_1, rank 1
3380 11:06:50.095884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3381 11:06:50.098898 ==
3382 11:06:50.099364
3383 11:06:50.099769
3384 11:06:50.100154 TX Vref Scan disable
3385 11:06:50.102208 == TX Byte 0 ==
3386 11:06:50.105659 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3387 11:06:50.108845 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3388 11:06:50.112160 == TX Byte 1 ==
3389 11:06:50.115411 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3390 11:06:50.122011 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3391 11:06:50.122216
3392 11:06:50.122375 [DATLAT]
3393 11:06:50.122522 Freq=1200, CH1 RK1
3394 11:06:50.122665
3395 11:06:50.125747 DATLAT Default: 0xc
3396 11:06:50.126048 0, 0xFFFF, sum = 0
3397 11:06:50.128932 1, 0xFFFF, sum = 0
3398 11:06:50.132317 2, 0xFFFF, sum = 0
3399 11:06:50.132523 3, 0xFFFF, sum = 0
3400 11:06:50.135223 4, 0xFFFF, sum = 0
3401 11:06:50.135431 5, 0xFFFF, sum = 0
3402 11:06:50.138685 6, 0xFFFF, sum = 0
3403 11:06:50.138947 7, 0xFFFF, sum = 0
3404 11:06:50.142074 8, 0xFFFF, sum = 0
3405 11:06:50.142282 9, 0xFFFF, sum = 0
3406 11:06:50.145181 10, 0xFFFF, sum = 0
3407 11:06:50.145413 11, 0x0, sum = 1
3408 11:06:50.148557 12, 0x0, sum = 2
3409 11:06:50.148765 13, 0x0, sum = 3
3410 11:06:50.151882 14, 0x0, sum = 4
3411 11:06:50.152138 best_step = 12
3412 11:06:50.152334
3413 11:06:50.152512 ==
3414 11:06:50.155394 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 11:06:50.158881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3416 11:06:50.159260 ==
3417 11:06:50.162311 RX Vref Scan: 0
3418 11:06:50.162809
3419 11:06:50.165565 RX Vref 0 -> 0, step: 1
3420 11:06:50.165986
3421 11:06:50.166313 RX Delay -29 -> 252, step: 4
3422 11:06:50.173125 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3423 11:06:50.176277 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3424 11:06:50.179776 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3425 11:06:50.183120 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3426 11:06:50.186319 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3427 11:06:50.193698 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3428 11:06:50.196233 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3429 11:06:50.199605 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3430 11:06:50.202652 iDelay=195, Bit 8, Center 86 (19 ~ 154) 136
3431 11:06:50.206203 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3432 11:06:50.212745 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3433 11:06:50.216337 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3434 11:06:50.219416 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3435 11:06:50.223023 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3436 11:06:50.225952 iDelay=195, Bit 14, Center 112 (43 ~ 182) 140
3437 11:06:50.232653 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3438 11:06:50.233121 ==
3439 11:06:50.235991 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 11:06:50.239372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3441 11:06:50.239801 ==
3442 11:06:50.240133 DQS Delay:
3443 11:06:50.242721 DQS0 = 0, DQS1 = 0
3444 11:06:50.243143 DQM Delay:
3445 11:06:50.245836 DQM0 = 113, DQM1 = 103
3446 11:06:50.246262 DQ Delay:
3447 11:06:50.249368 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =110
3448 11:06:50.253359 DQ4 =112, DQ5 =124, DQ6 =120, DQ7 =112
3449 11:06:50.256008 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =96
3450 11:06:50.259150 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3451 11:06:50.259617
3452 11:06:50.259950
3453 11:06:50.269596 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3454 11:06:50.272886 CH1 RK1: MR19=404, MR18=909
3455 11:06:50.276294 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3456 11:06:50.279378 [RxdqsGatingPostProcess] freq 1200
3457 11:06:50.286553 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3458 11:06:50.289351 Pre-setting of DQS Precalculation
3459 11:06:50.292934 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3460 11:06:50.302681 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3461 11:06:50.309528 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3462 11:06:50.310020
3463 11:06:50.310353
3464 11:06:50.312510 [Calibration Summary] 2400 Mbps
3465 11:06:50.312934 CH 0, Rank 0
3466 11:06:50.315749 SW Impedance : PASS
3467 11:06:50.316175 DUTY Scan : NO K
3468 11:06:50.318924 ZQ Calibration : PASS
3469 11:06:50.322307 Jitter Meter : NO K
3470 11:06:50.322729 CBT Training : PASS
3471 11:06:50.325562 Write leveling : PASS
3472 11:06:50.328738 RX DQS gating : PASS
3473 11:06:50.329156 RX DQ/DQS(RDDQC) : PASS
3474 11:06:50.332361 TX DQ/DQS : PASS
3475 11:06:50.335703 RX DATLAT : PASS
3476 11:06:50.336208 RX DQ/DQS(Engine): PASS
3477 11:06:50.338987 TX OE : NO K
3478 11:06:50.339411 All Pass.
3479 11:06:50.339736
3480 11:06:50.342303 CH 0, Rank 1
3481 11:06:50.342727 SW Impedance : PASS
3482 11:06:50.345733 DUTY Scan : NO K
3483 11:06:50.349014 ZQ Calibration : PASS
3484 11:06:50.349477 Jitter Meter : NO K
3485 11:06:50.352269 CBT Training : PASS
3486 11:06:50.355685 Write leveling : PASS
3487 11:06:50.356166 RX DQS gating : PASS
3488 11:06:50.358954 RX DQ/DQS(RDDQC) : PASS
3489 11:06:50.359450 TX DQ/DQS : PASS
3490 11:06:50.362141 RX DATLAT : PASS
3491 11:06:50.365342 RX DQ/DQS(Engine): PASS
3492 11:06:50.365767 TX OE : NO K
3493 11:06:50.368976 All Pass.
3494 11:06:50.369523
3495 11:06:50.369856 CH 1, Rank 0
3496 11:06:50.372633 SW Impedance : PASS
3497 11:06:50.373132 DUTY Scan : NO K
3498 11:06:50.375345 ZQ Calibration : PASS
3499 11:06:50.378563 Jitter Meter : NO K
3500 11:06:50.378979 CBT Training : PASS
3501 11:06:50.382175 Write leveling : PASS
3502 11:06:50.385501 RX DQS gating : PASS
3503 11:06:50.386006 RX DQ/DQS(RDDQC) : PASS
3504 11:06:50.389350 TX DQ/DQS : PASS
3505 11:06:50.392104 RX DATLAT : PASS
3506 11:06:50.392640 RX DQ/DQS(Engine): PASS
3507 11:06:50.395543 TX OE : NO K
3508 11:06:50.396039 All Pass.
3509 11:06:50.396369
3510 11:06:50.398810 CH 1, Rank 1
3511 11:06:50.399310 SW Impedance : PASS
3512 11:06:50.401772 DUTY Scan : NO K
3513 11:06:50.405209 ZQ Calibration : PASS
3514 11:06:50.405650 Jitter Meter : NO K
3515 11:06:50.408571 CBT Training : PASS
3516 11:06:50.411770 Write leveling : PASS
3517 11:06:50.412189 RX DQS gating : PASS
3518 11:06:50.415059 RX DQ/DQS(RDDQC) : PASS
3519 11:06:50.415478 TX DQ/DQS : PASS
3520 11:06:50.418452 RX DATLAT : PASS
3521 11:06:50.421753 RX DQ/DQS(Engine): PASS
3522 11:06:50.422168 TX OE : NO K
3523 11:06:50.425030 All Pass.
3524 11:06:50.425501
3525 11:06:50.425830 DramC Write-DBI off
3526 11:06:50.428396 PER_BANK_REFRESH: Hybrid Mode
3527 11:06:50.431598 TX_TRACKING: ON
3528 11:06:50.438180 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3529 11:06:50.441766 [FAST_K] Save calibration result to emmc
3530 11:06:50.448313 dramc_set_vcore_voltage set vcore to 650000
3531 11:06:50.448791 Read voltage for 600, 5
3532 11:06:50.449125 Vio18 = 0
3533 11:06:50.451306 Vcore = 650000
3534 11:06:50.451798 Vdram = 0
3535 11:06:50.452139 Vddq = 0
3536 11:06:50.455012 Vmddr = 0
3537 11:06:50.458371 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3538 11:06:50.464773 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3539 11:06:50.468265 MEM_TYPE=3, freq_sel=19
3540 11:06:50.468789 sv_algorithm_assistance_LP4_1600
3541 11:06:50.474724 ============ PULL DRAM RESETB DOWN ============
3542 11:06:50.478190 ========== PULL DRAM RESETB DOWN end =========
3543 11:06:50.481536 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3544 11:06:50.484696 ===================================
3545 11:06:50.488028 LPDDR4 DRAM CONFIGURATION
3546 11:06:50.491820 ===================================
3547 11:06:50.494740 EX_ROW_EN[0] = 0x0
3548 11:06:50.495223 EX_ROW_EN[1] = 0x0
3549 11:06:50.498098 LP4Y_EN = 0x0
3550 11:06:50.498555 WORK_FSP = 0x0
3551 11:06:50.501261 WL = 0x2
3552 11:06:50.501718 RL = 0x2
3553 11:06:50.505038 BL = 0x2
3554 11:06:50.505524 RPST = 0x0
3555 11:06:50.508052 RD_PRE = 0x0
3556 11:06:50.508742 WR_PRE = 0x1
3557 11:06:50.511268 WR_PST = 0x0
3558 11:06:50.511677 DBI_WR = 0x0
3559 11:06:50.514599 DBI_RD = 0x0
3560 11:06:50.515044 OTF = 0x1
3561 11:06:50.517946 ===================================
3562 11:06:50.521485 ===================================
3563 11:06:50.524627 ANA top config
3564 11:06:50.528360 ===================================
3565 11:06:50.531256 DLL_ASYNC_EN = 0
3566 11:06:50.531649 ALL_SLAVE_EN = 1
3567 11:06:50.534621 NEW_RANK_MODE = 1
3568 11:06:50.537906 DLL_IDLE_MODE = 1
3569 11:06:50.541112 LP45_APHY_COMB_EN = 1
3570 11:06:50.541556 TX_ODT_DIS = 1
3571 11:06:50.544559 NEW_8X_MODE = 1
3572 11:06:50.547981 ===================================
3573 11:06:50.550968 ===================================
3574 11:06:50.554859 data_rate = 1200
3575 11:06:50.557732 CKR = 1
3576 11:06:50.561094 DQ_P2S_RATIO = 8
3577 11:06:50.564541 ===================================
3578 11:06:50.567924 CA_P2S_RATIO = 8
3579 11:06:50.568308 DQ_CA_OPEN = 0
3580 11:06:50.571314 DQ_SEMI_OPEN = 0
3581 11:06:50.574542 CA_SEMI_OPEN = 0
3582 11:06:50.578122 CA_FULL_RATE = 0
3583 11:06:50.581365 DQ_CKDIV4_EN = 1
3584 11:06:50.584415 CA_CKDIV4_EN = 1
3585 11:06:50.584802 CA_PREDIV_EN = 0
3586 11:06:50.587764 PH8_DLY = 0
3587 11:06:50.591259 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3588 11:06:50.594709 DQ_AAMCK_DIV = 4
3589 11:06:50.597769 CA_AAMCK_DIV = 4
3590 11:06:50.598154 CA_ADMCK_DIV = 4
3591 11:06:50.601057 DQ_TRACK_CA_EN = 0
3592 11:06:50.604982 CA_PICK = 600
3593 11:06:50.607495 CA_MCKIO = 600
3594 11:06:50.611022 MCKIO_SEMI = 0
3595 11:06:50.614304 PLL_FREQ = 2288
3596 11:06:50.617401 DQ_UI_PI_RATIO = 32
3597 11:06:50.620956 CA_UI_PI_RATIO = 0
3598 11:06:50.624356 ===================================
3599 11:06:50.627589 ===================================
3600 11:06:50.627988 memory_type:LPDDR4
3601 11:06:50.630737 GP_NUM : 10
3602 11:06:50.634060 SRAM_EN : 1
3603 11:06:50.634446 MD32_EN : 0
3604 11:06:50.637321 ===================================
3605 11:06:50.640527 [ANA_INIT] >>>>>>>>>>>>>>
3606 11:06:50.643845 <<<<<< [CONFIGURE PHASE]: ANA_TX
3607 11:06:50.647264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3608 11:06:50.650781 ===================================
3609 11:06:50.654017 data_rate = 1200,PCW = 0X5800
3610 11:06:50.657532 ===================================
3611 11:06:50.660570 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3612 11:06:50.663658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3613 11:06:50.670482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3614 11:06:50.673488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3615 11:06:50.676996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3616 11:06:50.680520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3617 11:06:50.683680 [ANA_INIT] flow start
3618 11:06:50.686974 [ANA_INIT] PLL >>>>>>>>
3619 11:06:50.687465 [ANA_INIT] PLL <<<<<<<<
3620 11:06:50.690396 [ANA_INIT] MIDPI >>>>>>>>
3621 11:06:50.693712 [ANA_INIT] MIDPI <<<<<<<<
3622 11:06:50.696887 [ANA_INIT] DLL >>>>>>>>
3623 11:06:50.697365 [ANA_INIT] flow end
3624 11:06:50.700163 ============ LP4 DIFF to SE enter ============
3625 11:06:50.706905 ============ LP4 DIFF to SE exit ============
3626 11:06:50.707335 [ANA_INIT] <<<<<<<<<<<<<
3627 11:06:50.710102 [Flow] Enable top DCM control >>>>>
3628 11:06:50.713365 [Flow] Enable top DCM control <<<<<
3629 11:06:50.716646 Enable DLL master slave shuffle
3630 11:06:50.723352 ==============================================================
3631 11:06:50.723781 Gating Mode config
3632 11:06:50.729895 ==============================================================
3633 11:06:50.733703 Config description:
3634 11:06:50.743328 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3635 11:06:50.749881 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3636 11:06:50.753258 SELPH_MODE 0: By rank 1: By Phase
3637 11:06:50.760002 ==============================================================
3638 11:06:50.763283 GAT_TRACK_EN = 1
3639 11:06:50.763764 RX_GATING_MODE = 2
3640 11:06:50.766947 RX_GATING_TRACK_MODE = 2
3641 11:06:50.769956 SELPH_MODE = 1
3642 11:06:50.773339 PICG_EARLY_EN = 1
3643 11:06:50.776391 VALID_LAT_VALUE = 1
3644 11:06:50.782921 ==============================================================
3645 11:06:50.786482 Enter into Gating configuration >>>>
3646 11:06:50.789632 Exit from Gating configuration <<<<
3647 11:06:50.792980 Enter into DVFS_PRE_config >>>>>
3648 11:06:50.803246 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3649 11:06:50.806155 Exit from DVFS_PRE_config <<<<<
3650 11:06:50.809785 Enter into PICG configuration >>>>
3651 11:06:50.812991 Exit from PICG configuration <<<<
3652 11:06:50.816080 [RX_INPUT] configuration >>>>>
3653 11:06:50.819745 [RX_INPUT] configuration <<<<<
3654 11:06:50.823022 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3655 11:06:50.829852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3656 11:06:50.836036 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3657 11:06:50.842456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3658 11:06:50.845820 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3659 11:06:50.852229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3660 11:06:50.855932 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3661 11:06:50.862215 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3662 11:06:50.865976 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3663 11:06:50.868988 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3664 11:06:50.872040 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3665 11:06:50.878786 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3666 11:06:50.882572 ===================================
3667 11:06:50.882674 LPDDR4 DRAM CONFIGURATION
3668 11:06:50.885604 ===================================
3669 11:06:50.889558 EX_ROW_EN[0] = 0x0
3670 11:06:50.892345 EX_ROW_EN[1] = 0x0
3671 11:06:50.892461 LP4Y_EN = 0x0
3672 11:06:50.895939 WORK_FSP = 0x0
3673 11:06:50.896062 WL = 0x2
3674 11:06:50.898846 RL = 0x2
3675 11:06:50.898964 BL = 0x2
3676 11:06:50.902153 RPST = 0x0
3677 11:06:50.902263 RD_PRE = 0x0
3678 11:06:50.905381 WR_PRE = 0x1
3679 11:06:50.905505 WR_PST = 0x0
3680 11:06:50.908690 DBI_WR = 0x0
3681 11:06:50.908815 DBI_RD = 0x0
3682 11:06:50.912285 OTF = 0x1
3683 11:06:50.915230 ===================================
3684 11:06:50.919157 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3685 11:06:50.921979 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3686 11:06:50.928895 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3687 11:06:50.931882 ===================================
3688 11:06:50.932042 LPDDR4 DRAM CONFIGURATION
3689 11:06:50.935324 ===================================
3690 11:06:50.939031 EX_ROW_EN[0] = 0x10
3691 11:06:50.941735 EX_ROW_EN[1] = 0x0
3692 11:06:50.941874 LP4Y_EN = 0x0
3693 11:06:50.945198 WORK_FSP = 0x0
3694 11:06:50.945357 WL = 0x2
3695 11:06:50.948634 RL = 0x2
3696 11:06:50.948848 BL = 0x2
3697 11:06:50.952294 RPST = 0x0
3698 11:06:50.952723 RD_PRE = 0x0
3699 11:06:50.955561 WR_PRE = 0x1
3700 11:06:50.956047 WR_PST = 0x0
3701 11:06:50.959150 DBI_WR = 0x0
3702 11:06:50.959575 DBI_RD = 0x0
3703 11:06:50.962446 OTF = 0x1
3704 11:06:50.965357 ===================================
3705 11:06:50.972256 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3706 11:06:50.975744 nWR fixed to 30
3707 11:06:50.976224 [ModeRegInit_LP4] CH0 RK0
3708 11:06:50.979116 [ModeRegInit_LP4] CH0 RK1
3709 11:06:50.982563 [ModeRegInit_LP4] CH1 RK0
3710 11:06:50.982990 [ModeRegInit_LP4] CH1 RK1
3711 11:06:50.985530 match AC timing 16
3712 11:06:50.989124 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3713 11:06:50.992115 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3714 11:06:50.998741 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3715 11:06:51.002266 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3716 11:06:51.008925 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3717 11:06:51.009377 ==
3718 11:06:51.012187 Dram Type= 6, Freq= 0, CH_0, rank 0
3719 11:06:51.015470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3720 11:06:51.015942 ==
3721 11:06:51.022383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3722 11:06:51.025759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3723 11:06:51.029983 [CA 0] Center 35 (5~66) winsize 62
3724 11:06:51.033307 [CA 1] Center 35 (5~66) winsize 62
3725 11:06:51.036641 [CA 2] Center 34 (4~65) winsize 62
3726 11:06:51.039881 [CA 3] Center 34 (4~65) winsize 62
3727 11:06:51.043005 [CA 4] Center 33 (3~64) winsize 62
3728 11:06:51.046617 [CA 5] Center 33 (2~64) winsize 63
3729 11:06:51.047090
3730 11:06:51.049754 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3731 11:06:51.050228
3732 11:06:51.053320 [CATrainingPosCal] consider 1 rank data
3733 11:06:51.056312 u2DelayCellTimex100 = 270/100 ps
3734 11:06:51.060025 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3735 11:06:51.066676 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3736 11:06:51.070245 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3737 11:06:51.073363 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3738 11:06:51.076360 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3739 11:06:51.079864 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3740 11:06:51.080290
3741 11:06:51.083256 CA PerBit enable=1, Macro0, CA PI delay=33
3742 11:06:51.083731
3743 11:06:51.086316 [CBTSetCACLKResult] CA Dly = 33
3744 11:06:51.086743 CS Dly: 5 (0~36)
3745 11:06:51.089764 ==
3746 11:06:51.090206 Dram Type= 6, Freq= 0, CH_0, rank 1
3747 11:06:51.096344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3748 11:06:51.096842 ==
3749 11:06:51.099814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3750 11:06:51.106351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3751 11:06:51.109920 [CA 0] Center 35 (5~66) winsize 62
3752 11:06:51.113296 [CA 1] Center 35 (5~66) winsize 62
3753 11:06:51.116387 [CA 2] Center 34 (4~65) winsize 62
3754 11:06:51.119669 [CA 3] Center 34 (3~65) winsize 63
3755 11:06:51.122968 [CA 4] Center 33 (3~64) winsize 62
3756 11:06:51.126611 [CA 5] Center 33 (3~64) winsize 62
3757 11:06:51.127037
3758 11:06:51.130015 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3759 11:06:51.130438
3760 11:06:51.133293 [CATrainingPosCal] consider 2 rank data
3761 11:06:51.136521 u2DelayCellTimex100 = 270/100 ps
3762 11:06:51.139743 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3763 11:06:51.146606 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3764 11:06:51.149924 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3765 11:06:51.153199 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3766 11:06:51.156394 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3767 11:06:51.159595 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3768 11:06:51.160064
3769 11:06:51.163044 CA PerBit enable=1, Macro0, CA PI delay=33
3770 11:06:51.163558
3771 11:06:51.166427 [CBTSetCACLKResult] CA Dly = 33
3772 11:06:51.169690 CS Dly: 5 (0~36)
3773 11:06:51.170237
3774 11:06:51.172623 ----->DramcWriteLeveling(PI) begin...
3775 11:06:51.173191 ==
3776 11:06:51.176170 Dram Type= 6, Freq= 0, CH_0, rank 0
3777 11:06:51.179755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3778 11:06:51.180312 ==
3779 11:06:51.183019 Write leveling (Byte 0): 31 => 31
3780 11:06:51.186498 Write leveling (Byte 1): 30 => 30
3781 11:06:51.189545 DramcWriteLeveling(PI) end<-----
3782 11:06:51.190093
3783 11:06:51.190431 ==
3784 11:06:51.192685 Dram Type= 6, Freq= 0, CH_0, rank 0
3785 11:06:51.196370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3786 11:06:51.197033 ==
3787 11:06:51.199555 [Gating] SW mode calibration
3788 11:06:51.206060 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3789 11:06:51.212581 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3790 11:06:51.216154 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3791 11:06:51.219264 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3792 11:06:51.226076 0 5 8 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (0 0)
3793 11:06:51.229133 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3794 11:06:51.233013 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 11:06:51.239287 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 11:06:51.242675 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 11:06:51.245948 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 11:06:51.252541 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 11:06:51.255881 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3800 11:06:51.259148 0 6 8 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
3801 11:06:51.265625 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 11:06:51.268923 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 11:06:51.272975 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 11:06:51.275633 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 11:06:51.282410 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3806 11:06:51.285882 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 11:06:51.288972 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 11:06:51.295904 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3809 11:06:51.298980 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3810 11:06:51.302241 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 11:06:51.309081 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 11:06:51.312177 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 11:06:51.315488 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 11:06:51.322352 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 11:06:51.325427 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 11:06:51.329095 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 11:06:51.335435 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 11:06:51.338505 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 11:06:51.342080 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 11:06:51.348735 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 11:06:51.352426 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 11:06:51.355236 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 11:06:51.362096 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 11:06:51.365481 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3825 11:06:51.368928 Total UI for P1: 0, mck2ui 16
3826 11:06:51.372103 best dqsien dly found for B0: ( 0, 9, 6)
3827 11:06:51.375153 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3828 11:06:51.378811 Total UI for P1: 0, mck2ui 16
3829 11:06:51.381874 best dqsien dly found for B1: ( 0, 9, 8)
3830 11:06:51.385633 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3831 11:06:51.388588 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3832 11:06:51.389088
3833 11:06:51.392216 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3834 11:06:51.398842 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3835 11:06:51.399347 [Gating] SW calibration Done
3836 11:06:51.399681 ==
3837 11:06:51.401907 Dram Type= 6, Freq= 0, CH_0, rank 0
3838 11:06:51.408828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3839 11:06:51.409382 ==
3840 11:06:51.409725 RX Vref Scan: 0
3841 11:06:51.410152
3842 11:06:51.411803 RX Vref 0 -> 0, step: 1
3843 11:06:51.412224
3844 11:06:51.415021 RX Delay -230 -> 252, step: 16
3845 11:06:51.418444 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3846 11:06:51.421702 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3847 11:06:51.428093 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3848 11:06:51.431587 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3849 11:06:51.435157 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3850 11:06:51.438228 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3851 11:06:51.441407 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3852 11:06:51.448292 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3853 11:06:51.451850 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3854 11:06:51.454838 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3855 11:06:51.458173 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3856 11:06:51.465180 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3857 11:06:51.467785 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3858 11:06:51.471171 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3859 11:06:51.474883 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3860 11:06:51.481856 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3861 11:06:51.482327 ==
3862 11:06:51.484752 Dram Type= 6, Freq= 0, CH_0, rank 0
3863 11:06:51.487820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3864 11:06:51.488246 ==
3865 11:06:51.488581 DQS Delay:
3866 11:06:51.491207 DQS0 = 0, DQS1 = 0
3867 11:06:51.491626 DQM Delay:
3868 11:06:51.494344 DQM0 = 38, DQM1 = 33
3869 11:06:51.494763 DQ Delay:
3870 11:06:51.497716 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3871 11:06:51.501398 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3872 11:06:51.505353 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3873 11:06:51.507796 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3874 11:06:51.508221
3875 11:06:51.508550
3876 11:06:51.508890 ==
3877 11:06:51.511482 Dram Type= 6, Freq= 0, CH_0, rank 0
3878 11:06:51.514352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3879 11:06:51.514781 ==
3880 11:06:51.515116
3881 11:06:51.517691
3882 11:06:51.518113 TX Vref Scan disable
3883 11:06:51.521085 == TX Byte 0 ==
3884 11:06:51.524474 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3885 11:06:51.527611 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3886 11:06:51.531327 == TX Byte 1 ==
3887 11:06:51.534604 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3888 11:06:51.537965 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3889 11:06:51.538394 ==
3890 11:06:51.541138 Dram Type= 6, Freq= 0, CH_0, rank 0
3891 11:06:51.547739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3892 11:06:51.548169 ==
3893 11:06:51.548497
3894 11:06:51.548802
3895 11:06:51.549090 TX Vref Scan disable
3896 11:06:51.552345 == TX Byte 0 ==
3897 11:06:51.555426 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3898 11:06:51.558891 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3899 11:06:51.562081 == TX Byte 1 ==
3900 11:06:51.565766 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3901 11:06:51.568927 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3902 11:06:51.572206
3903 11:06:51.572676 [DATLAT]
3904 11:06:51.573013 Freq=600, CH0 RK0
3905 11:06:51.573379
3906 11:06:51.575719 DATLAT Default: 0x9
3907 11:06:51.576159 0, 0xFFFF, sum = 0
3908 11:06:51.578792 1, 0xFFFF, sum = 0
3909 11:06:51.579247 2, 0xFFFF, sum = 0
3910 11:06:51.581968 3, 0xFFFF, sum = 0
3911 11:06:51.582397 4, 0xFFFF, sum = 0
3912 11:06:51.585536 5, 0xFFFF, sum = 0
3913 11:06:51.585964 6, 0xFFFF, sum = 0
3914 11:06:51.589106 7, 0x0, sum = 1
3915 11:06:51.589656 8, 0x0, sum = 2
3916 11:06:51.592468 9, 0x0, sum = 3
3917 11:06:51.592967 10, 0x0, sum = 4
3918 11:06:51.595423 best_step = 8
3919 11:06:51.595841
3920 11:06:51.596164 ==
3921 11:06:51.598934 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 11:06:51.602134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3923 11:06:51.602634 ==
3924 11:06:51.605327 RX Vref Scan: 1
3925 11:06:51.605748
3926 11:06:51.606074 RX Vref 0 -> 0, step: 1
3927 11:06:51.606376
3928 11:06:51.608580 RX Delay -195 -> 252, step: 8
3929 11:06:51.609005
3930 11:06:51.612455 Set Vref, RX VrefLevel [Byte0]: 51
3931 11:06:51.615370 [Byte1]: 45
3932 11:06:51.619099
3933 11:06:51.619520 Final RX Vref Byte 0 = 51 to rank0
3934 11:06:51.622432 Final RX Vref Byte 1 = 45 to rank0
3935 11:06:51.625885 Final RX Vref Byte 0 = 51 to rank1
3936 11:06:51.629054 Final RX Vref Byte 1 = 45 to rank1==
3937 11:06:51.632413 Dram Type= 6, Freq= 0, CH_0, rank 0
3938 11:06:51.639150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3939 11:06:51.639625 ==
3940 11:06:51.639957 DQS Delay:
3941 11:06:51.640260 DQS0 = 0, DQS1 = 0
3942 11:06:51.642237 DQM Delay:
3943 11:06:51.642660 DQM0 = 39, DQM1 = 31
3944 11:06:51.645474 DQ Delay:
3945 11:06:51.649159 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =36
3946 11:06:51.652429 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3947 11:06:51.655617 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
3948 11:06:51.658724 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
3949 11:06:51.659155
3950 11:06:51.659492
3951 11:06:51.665914 [DQSOSCAuto] RK0, (LSB)MR18= 0x5757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3952 11:06:51.668985 CH0 RK0: MR19=808, MR18=5757
3953 11:06:51.675856 CH0_RK0: MR19=0x808, MR18=0x5757, DQSOSC=393, MR23=63, INC=169, DEC=113
3954 11:06:51.676387
3955 11:06:51.678904 ----->DramcWriteLeveling(PI) begin...
3956 11:06:51.679363 ==
3957 11:06:51.682246 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 11:06:51.685385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3959 11:06:51.686082 ==
3960 11:06:51.688718 Write leveling (Byte 0): 28 => 28
3961 11:06:51.691942 Write leveling (Byte 1): 28 => 28
3962 11:06:51.695476 DramcWriteLeveling(PI) end<-----
3963 11:06:51.695955
3964 11:06:51.696304 ==
3965 11:06:51.698679 Dram Type= 6, Freq= 0, CH_0, rank 1
3966 11:06:51.701950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3967 11:06:51.702389 ==
3968 11:06:51.705335 [Gating] SW mode calibration
3969 11:06:51.712151 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3970 11:06:51.718470 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3971 11:06:51.721986 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 11:06:51.728662 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 11:06:51.732573 0 5 8 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
3974 11:06:51.735090 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3975 11:06:51.741945 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 11:06:51.745378 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 11:06:51.748334 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 11:06:51.754824 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 11:06:51.758639 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 11:06:51.761546 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:06:51.765708 0 6 8 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 0)
3982 11:06:51.771496 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3983 11:06:51.775332 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 11:06:51.778081 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 11:06:51.784683 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 11:06:51.788569 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 11:06:51.791536 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 11:06:51.798140 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:06:51.801546 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3990 11:06:51.804707 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3991 11:06:51.811601 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:06:51.814617 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:06:51.817966 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:06:51.824454 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:06:51.827827 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:06:51.831171 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:06:51.837792 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:06:51.841404 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:06:51.845094 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:06:51.851437 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:06:51.854486 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:06:51.857612 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:06:51.864387 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:06:51.867853 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:06:51.870890 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4006 11:06:51.874596 Total UI for P1: 0, mck2ui 16
4007 11:06:51.877667 best dqsien dly found for B1: ( 0, 9, 6)
4008 11:06:51.884488 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4009 11:06:51.884976 Total UI for P1: 0, mck2ui 16
4010 11:06:51.887839 best dqsien dly found for B0: ( 0, 9, 8)
4011 11:06:51.894194 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4012 11:06:51.897506 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4013 11:06:51.897941
4014 11:06:51.900902 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4015 11:06:51.904538 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4016 11:06:51.908002 [Gating] SW calibration Done
4017 11:06:51.908518 ==
4018 11:06:51.910989 Dram Type= 6, Freq= 0, CH_0, rank 1
4019 11:06:51.914184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4020 11:06:51.914635 ==
4021 11:06:51.917627 RX Vref Scan: 0
4022 11:06:51.918061
4023 11:06:51.918490 RX Vref 0 -> 0, step: 1
4024 11:06:51.918896
4025 11:06:51.921114 RX Delay -230 -> 252, step: 16
4026 11:06:51.924499 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4027 11:06:51.931147 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4028 11:06:51.934447 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4029 11:06:51.937906 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4030 11:06:51.940753 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4031 11:06:51.944352 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4032 11:06:51.951153 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4033 11:06:51.954087 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4034 11:06:51.957345 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4035 11:06:51.960806 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4036 11:06:51.967823 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4037 11:06:51.970835 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4038 11:06:51.974463 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4039 11:06:51.977618 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4040 11:06:51.984314 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4041 11:06:51.987215 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4042 11:06:51.987639 ==
4043 11:06:51.990937 Dram Type= 6, Freq= 0, CH_0, rank 1
4044 11:06:51.994311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4045 11:06:51.994812 ==
4046 11:06:51.997766 DQS Delay:
4047 11:06:51.998269 DQS0 = 0, DQS1 = 0
4048 11:06:51.998603 DQM Delay:
4049 11:06:52.001000 DQM0 = 40, DQM1 = 31
4050 11:06:52.001613 DQ Delay:
4051 11:06:52.004123 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4052 11:06:52.007648 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4053 11:06:52.010450 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4054 11:06:52.013790 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4055 11:06:52.014214
4056 11:06:52.014647
4057 11:06:52.014955 ==
4058 11:06:52.017282 Dram Type= 6, Freq= 0, CH_0, rank 1
4059 11:06:52.023567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4060 11:06:52.023999 ==
4061 11:06:52.024408
4062 11:06:52.024735
4063 11:06:52.025030 TX Vref Scan disable
4064 11:06:52.027138 == TX Byte 0 ==
4065 11:06:52.030400 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4066 11:06:52.037061 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4067 11:06:52.037558 == TX Byte 1 ==
4068 11:06:52.040500 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4069 11:06:52.047283 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4070 11:06:52.047774 ==
4071 11:06:52.050680 Dram Type= 6, Freq= 0, CH_0, rank 1
4072 11:06:52.053940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4073 11:06:52.054448 ==
4074 11:06:52.054780
4075 11:06:52.055082
4076 11:06:52.057214 TX Vref Scan disable
4077 11:06:52.060277 == TX Byte 0 ==
4078 11:06:52.063488 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4079 11:06:52.066854 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4080 11:06:52.070145 == TX Byte 1 ==
4081 11:06:52.073741 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4082 11:06:52.076950 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4083 11:06:52.077396
4084 11:06:52.077794 [DATLAT]
4085 11:06:52.080098 Freq=600, CH0 RK1
4086 11:06:52.080520
4087 11:06:52.080966 DATLAT Default: 0x8
4088 11:06:52.084105 0, 0xFFFF, sum = 0
4089 11:06:52.087026 1, 0xFFFF, sum = 0
4090 11:06:52.087547 2, 0xFFFF, sum = 0
4091 11:06:52.090453 3, 0xFFFF, sum = 0
4092 11:06:52.091050 4, 0xFFFF, sum = 0
4093 11:06:52.093596 5, 0xFFFF, sum = 0
4094 11:06:52.094023 6, 0xFFFF, sum = 0
4095 11:06:52.097044 7, 0x0, sum = 1
4096 11:06:52.097511 8, 0x0, sum = 2
4097 11:06:52.097848 9, 0x0, sum = 3
4098 11:06:52.100132 10, 0x0, sum = 4
4099 11:06:52.100679 best_step = 8
4100 11:06:52.101011
4101 11:06:52.101367 ==
4102 11:06:52.103297 Dram Type= 6, Freq= 0, CH_0, rank 1
4103 11:06:52.110338 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4104 11:06:52.110849 ==
4105 11:06:52.111182 RX Vref Scan: 0
4106 11:06:52.111487
4107 11:06:52.113748 RX Vref 0 -> 0, step: 1
4108 11:06:52.114195
4109 11:06:52.116441 RX Delay -195 -> 252, step: 8
4110 11:06:52.119821 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4111 11:06:52.126403 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4112 11:06:52.129795 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4113 11:06:52.133488 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4114 11:06:52.136749 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4115 11:06:52.143383 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4116 11:06:52.146936 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4117 11:06:52.149919 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4118 11:06:52.153772 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4119 11:06:52.156472 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4120 11:06:52.163153 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4121 11:06:52.166390 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4122 11:06:52.169844 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4123 11:06:52.173365 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4124 11:06:52.179654 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4125 11:06:52.182976 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4126 11:06:52.183397 ==
4127 11:06:52.186821 Dram Type= 6, Freq= 0, CH_0, rank 1
4128 11:06:52.190135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4129 11:06:52.190633 ==
4130 11:06:52.193010 DQS Delay:
4131 11:06:52.193477 DQS0 = 0, DQS1 = 0
4132 11:06:52.193807 DQM Delay:
4133 11:06:52.196462 DQM0 = 42, DQM1 = 31
4134 11:06:52.196991 DQ Delay:
4135 11:06:52.199543 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4136 11:06:52.202673 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4137 11:06:52.205901 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4138 11:06:52.209658 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4139 11:06:52.210082
4140 11:06:52.210411
4141 11:06:52.219634 [DQSOSCAuto] RK1, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4142 11:06:52.222753 CH0 RK1: MR19=808, MR18=7474
4143 11:06:52.226104 CH0_RK1: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4144 11:06:52.229366 [RxdqsGatingPostProcess] freq 600
4145 11:06:52.235903 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4146 11:06:52.239313 Pre-setting of DQS Precalculation
4147 11:06:52.242537 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4148 11:06:52.242970 ==
4149 11:06:52.245795 Dram Type= 6, Freq= 0, CH_1, rank 0
4150 11:06:52.252984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4151 11:06:52.253556 ==
4152 11:06:52.255905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4153 11:06:52.262476 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4154 11:06:52.266046 [CA 0] Center 36 (5~67) winsize 63
4155 11:06:52.269161 [CA 1] Center 35 (5~66) winsize 62
4156 11:06:52.272389 [CA 2] Center 33 (3~64) winsize 62
4157 11:06:52.276224 [CA 3] Center 33 (3~64) winsize 62
4158 11:06:52.279129 [CA 4] Center 33 (2~64) winsize 63
4159 11:06:52.282439 [CA 5] Center 32 (2~63) winsize 62
4160 11:06:52.282859
4161 11:06:52.286065 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4162 11:06:52.286646
4163 11:06:52.289305 [CATrainingPosCal] consider 1 rank data
4164 11:06:52.292958 u2DelayCellTimex100 = 270/100 ps
4165 11:06:52.296244 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
4166 11:06:52.302489 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4167 11:06:52.305572 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4168 11:06:52.309418 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4169 11:06:52.312872 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4170 11:06:52.315637 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4171 11:06:52.316056
4172 11:06:52.319154 CA PerBit enable=1, Macro0, CA PI delay=32
4173 11:06:52.319580
4174 11:06:52.322269 [CBTSetCACLKResult] CA Dly = 32
4175 11:06:52.322694 CS Dly: 4 (0~35)
4176 11:06:52.325524 ==
4177 11:06:52.328957 Dram Type= 6, Freq= 0, CH_1, rank 1
4178 11:06:52.332268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4179 11:06:52.332692 ==
4180 11:06:52.335484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4181 11:06:52.342246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4182 11:06:52.345939 [CA 0] Center 34 (4~65) winsize 62
4183 11:06:52.349929 [CA 1] Center 34 (4~65) winsize 62
4184 11:06:52.352584 [CA 2] Center 33 (3~64) winsize 62
4185 11:06:52.356056 [CA 3] Center 33 (3~64) winsize 62
4186 11:06:52.359810 [CA 4] Center 32 (2~63) winsize 62
4187 11:06:52.362467 [CA 5] Center 32 (2~63) winsize 62
4188 11:06:52.362892
4189 11:06:52.366333 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4190 11:06:52.366757
4191 11:06:52.369419 [CATrainingPosCal] consider 2 rank data
4192 11:06:52.373005 u2DelayCellTimex100 = 270/100 ps
4193 11:06:52.376490 CA0 delay=35 (5~65),Diff = 3 PI (28 cell)
4194 11:06:52.379355 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4195 11:06:52.386280 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4196 11:06:52.389380 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4197 11:06:52.393120 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4198 11:06:52.396088 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4199 11:06:52.396563
4200 11:06:52.399244 CA PerBit enable=1, Macro0, CA PI delay=32
4201 11:06:52.399754
4202 11:06:52.402738 [CBTSetCACLKResult] CA Dly = 32
4203 11:06:52.403216 CS Dly: 4 (0~36)
4204 11:06:52.403554
4205 11:06:52.405921 ----->DramcWriteLeveling(PI) begin...
4206 11:06:52.409583 ==
4207 11:06:52.412680 Dram Type= 6, Freq= 0, CH_1, rank 0
4208 11:06:52.416144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4209 11:06:52.416575 ==
4210 11:06:52.419422 Write leveling (Byte 0): 27 => 27
4211 11:06:52.422668 Write leveling (Byte 1): 26 => 26
4212 11:06:52.425786 DramcWriteLeveling(PI) end<-----
4213 11:06:52.426209
4214 11:06:52.426535 ==
4215 11:06:52.429066 Dram Type= 6, Freq= 0, CH_1, rank 0
4216 11:06:52.432763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4217 11:06:52.433186 ==
4218 11:06:52.436212 [Gating] SW mode calibration
4219 11:06:52.442627 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 11:06:52.446070 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4221 11:06:52.453056 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 11:06:52.456069 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4223 11:06:52.459348 0 5 8 | B1->B0 | 3030 2525 | 1 0 | (0 0) (0 0)
4224 11:06:52.465872 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:06:52.469451 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:06:52.473282 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 11:06:52.479271 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 11:06:52.482452 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 11:06:52.485726 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 11:06:52.492473 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4231 11:06:52.496105 0 6 8 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
4232 11:06:52.499232 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:06:52.505625 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:06:52.508928 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 11:06:52.512376 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 11:06:52.519298 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 11:06:52.522273 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4238 11:06:52.525837 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 11:06:52.532449 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:06:52.535935 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:06:52.539146 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:06:52.546127 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:06:52.549282 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:06:52.552639 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:06:52.555625 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:06:52.562293 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:06:52.565535 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:06:52.568715 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:06:52.575342 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:06:52.579035 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:06:52.582287 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:06:52.589004 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:06:52.592217 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:06:52.595331 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4255 11:06:52.602467 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4256 11:06:52.605364 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:06:52.608773 Total UI for P1: 0, mck2ui 16
4258 11:06:52.612090 best dqsien dly found for B0: ( 0, 9, 6)
4259 11:06:52.615217 Total UI for P1: 0, mck2ui 16
4260 11:06:52.618564 best dqsien dly found for B1: ( 0, 9, 8)
4261 11:06:52.621912 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4262 11:06:52.625094 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4263 11:06:52.625635
4264 11:06:52.628397 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4265 11:06:52.632135 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4266 11:06:52.635178 [Gating] SW calibration Done
4267 11:06:52.635555 ==
4268 11:06:52.638676 Dram Type= 6, Freq= 0, CH_1, rank 0
4269 11:06:52.641836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4270 11:06:52.645265 ==
4271 11:06:52.645668 RX Vref Scan: 0
4272 11:06:52.646057
4273 11:06:52.648416 RX Vref 0 -> 0, step: 1
4274 11:06:52.648809
4275 11:06:52.651738 RX Delay -230 -> 252, step: 16
4276 11:06:52.654931 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4277 11:06:52.658548 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4278 11:06:52.661352 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4279 11:06:52.668100 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4280 11:06:52.671556 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4281 11:06:52.674811 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4282 11:06:52.678062 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4283 11:06:52.681215 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4284 11:06:52.687489 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4285 11:06:52.691277 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4286 11:06:52.694721 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4287 11:06:52.697479 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4288 11:06:52.704142 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4289 11:06:52.707672 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4290 11:06:52.711041 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4291 11:06:52.714178 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4292 11:06:52.717654 ==
4293 11:06:52.717779 Dram Type= 6, Freq= 0, CH_1, rank 0
4294 11:06:52.724111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4295 11:06:52.724238 ==
4296 11:06:52.724335 DQS Delay:
4297 11:06:52.727553 DQS0 = 0, DQS1 = 0
4298 11:06:52.727687 DQM Delay:
4299 11:06:52.730712 DQM0 = 39, DQM1 = 33
4300 11:06:52.730828 DQ Delay:
4301 11:06:52.734014 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4302 11:06:52.737279 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4303 11:06:52.740512 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4304 11:06:52.743763 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4305 11:06:52.743877
4306 11:06:52.743966
4307 11:06:52.744048 ==
4308 11:06:52.747234 Dram Type= 6, Freq= 0, CH_1, rank 0
4309 11:06:52.750634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4310 11:06:52.750762 ==
4311 11:06:52.750861
4312 11:06:52.750953
4313 11:06:52.753817 TX Vref Scan disable
4314 11:06:52.757022 == TX Byte 0 ==
4315 11:06:52.760440 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4316 11:06:52.763915 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4317 11:06:52.767370 == TX Byte 1 ==
4318 11:06:52.770781 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4319 11:06:52.774207 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4320 11:06:52.774498 ==
4321 11:06:52.777371 Dram Type= 6, Freq= 0, CH_1, rank 0
4322 11:06:52.781041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4323 11:06:52.784290 ==
4324 11:06:52.784758
4325 11:06:52.785081
4326 11:06:52.785423 TX Vref Scan disable
4327 11:06:52.788029 == TX Byte 0 ==
4328 11:06:52.791467 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4329 11:06:52.798610 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4330 11:06:52.799039 == TX Byte 1 ==
4331 11:06:52.801301 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4332 11:06:52.807954 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4333 11:06:52.808372
4334 11:06:52.808717 [DATLAT]
4335 11:06:52.809032 Freq=600, CH1 RK0
4336 11:06:52.809379
4337 11:06:52.811304 DATLAT Default: 0x9
4338 11:06:52.811716 0, 0xFFFF, sum = 0
4339 11:06:52.814727 1, 0xFFFF, sum = 0
4340 11:06:52.815162 2, 0xFFFF, sum = 0
4341 11:06:52.817976 3, 0xFFFF, sum = 0
4342 11:06:52.821335 4, 0xFFFF, sum = 0
4343 11:06:52.821761 5, 0xFFFF, sum = 0
4344 11:06:52.824899 6, 0xFFFF, sum = 0
4345 11:06:52.825350 7, 0x0, sum = 1
4346 11:06:52.825680 8, 0x0, sum = 2
4347 11:06:52.827801 9, 0x0, sum = 3
4348 11:06:52.828229 10, 0x0, sum = 4
4349 11:06:52.831857 best_step = 8
4350 11:06:52.832270
4351 11:06:52.832587 ==
4352 11:06:52.834423 Dram Type= 6, Freq= 0, CH_1, rank 0
4353 11:06:52.837820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4354 11:06:52.838286 ==
4355 11:06:52.841189 RX Vref Scan: 1
4356 11:06:52.841658
4357 11:06:52.841978 RX Vref 0 -> 0, step: 1
4358 11:06:52.842278
4359 11:06:52.844620 RX Delay -195 -> 252, step: 8
4360 11:06:52.845041
4361 11:06:52.847725 Set Vref, RX VrefLevel [Byte0]: 52
4362 11:06:52.851293 [Byte1]: 48
4363 11:06:52.855172
4364 11:06:52.855585 Final RX Vref Byte 0 = 52 to rank0
4365 11:06:52.858542 Final RX Vref Byte 1 = 48 to rank0
4366 11:06:52.861595 Final RX Vref Byte 0 = 52 to rank1
4367 11:06:52.865035 Final RX Vref Byte 1 = 48 to rank1==
4368 11:06:52.868661 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 11:06:52.875226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4370 11:06:52.875708 ==
4371 11:06:52.876033 DQS Delay:
4372 11:06:52.878572 DQS0 = 0, DQS1 = 0
4373 11:06:52.878988 DQM Delay:
4374 11:06:52.879308 DQM0 = 38, DQM1 = 30
4375 11:06:52.881598 DQ Delay:
4376 11:06:52.885150 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4377 11:06:52.888300 DQ4 =36, DQ5 =52, DQ6 =44, DQ7 =36
4378 11:06:52.891634 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4379 11:06:52.894698 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4380 11:06:52.895112
4381 11:06:52.895433
4382 11:06:52.901457 [DQSOSCAuto] RK0, (LSB)MR18= 0x7c7c, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4383 11:06:52.904550 CH1 RK0: MR19=808, MR18=7C7C
4384 11:06:52.911657 CH1_RK0: MR19=0x808, MR18=0x7C7C, DQSOSC=386, MR23=63, INC=176, DEC=117
4385 11:06:52.912118
4386 11:06:52.914779 ----->DramcWriteLeveling(PI) begin...
4387 11:06:52.915203 ==
4388 11:06:52.918075 Dram Type= 6, Freq= 0, CH_1, rank 1
4389 11:06:52.921344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4390 11:06:52.921793 ==
4391 11:06:52.924964 Write leveling (Byte 0): 27 => 27
4392 11:06:52.927780 Write leveling (Byte 1): 27 => 27
4393 11:06:52.931159 DramcWriteLeveling(PI) end<-----
4394 11:06:52.931610
4395 11:06:52.931974 ==
4396 11:06:52.934372 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 11:06:52.938025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4398 11:06:52.938466 ==
4399 11:06:52.941301 [Gating] SW mode calibration
4400 11:06:52.947942 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4401 11:06:52.954279 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4402 11:06:52.957750 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 11:06:52.964404 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4404 11:06:52.967752 0 5 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 0)
4405 11:06:52.971114 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 11:06:52.977596 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 11:06:52.980753 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 11:06:52.984205 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 11:06:52.990957 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 11:06:52.994216 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 11:06:52.997800 0 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4412 11:06:53.004566 0 6 8 | B1->B0 | 3231 4646 | 1 0 | (0 0) (0 0)
4413 11:06:53.007561 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 11:06:53.011143 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 11:06:53.014299 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 11:06:53.020776 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 11:06:53.024484 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 11:06:53.027646 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 11:06:53.034454 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 11:06:53.037508 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4421 11:06:53.040627 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:06:53.047292 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:06:53.050472 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:06:53.053744 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 11:06:53.060304 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 11:06:53.063627 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 11:06:53.067138 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 11:06:53.073753 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 11:06:53.076976 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:06:53.080319 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:06:53.086935 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:06:53.090122 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:06:53.093862 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:06:53.100241 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:06:53.103944 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4436 11:06:53.107153 Total UI for P1: 0, mck2ui 16
4437 11:06:53.110384 best dqsien dly found for B0: ( 0, 9, 2)
4438 11:06:53.113781 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 11:06:53.117031 Total UI for P1: 0, mck2ui 16
4440 11:06:53.120498 best dqsien dly found for B1: ( 0, 9, 6)
4441 11:06:53.123703 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4442 11:06:53.126835 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4443 11:06:53.127267
4444 11:06:53.130206 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4445 11:06:53.136758 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4446 11:06:53.137340 [Gating] SW calibration Done
4447 11:06:53.140496 ==
4448 11:06:53.140927 Dram Type= 6, Freq= 0, CH_1, rank 1
4449 11:06:53.147075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4450 11:06:53.147530 ==
4451 11:06:53.147828 RX Vref Scan: 0
4452 11:06:53.148101
4453 11:06:53.149951 RX Vref 0 -> 0, step: 1
4454 11:06:53.150337
4455 11:06:53.153363 RX Delay -230 -> 252, step: 16
4456 11:06:53.156890 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4457 11:06:53.160271 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4458 11:06:53.166703 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4459 11:06:53.170212 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4460 11:06:53.173469 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4461 11:06:53.176924 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4462 11:06:53.179841 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4463 11:06:53.186685 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4464 11:06:53.189897 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4465 11:06:53.193349 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4466 11:06:53.196804 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4467 11:06:53.203710 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4468 11:06:53.206925 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4469 11:06:53.209969 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4470 11:06:53.213075 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4471 11:06:53.219626 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4472 11:06:53.220093 ==
4473 11:06:53.223561 Dram Type= 6, Freq= 0, CH_1, rank 1
4474 11:06:53.226516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4475 11:06:53.226946 ==
4476 11:06:53.227272 DQS Delay:
4477 11:06:53.230064 DQS0 = 0, DQS1 = 0
4478 11:06:53.230505 DQM Delay:
4479 11:06:53.233469 DQM0 = 42, DQM1 = 34
4480 11:06:53.233920 DQ Delay:
4481 11:06:53.236731 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4482 11:06:53.239802 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4483 11:06:53.243139 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4484 11:06:53.246555 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4485 11:06:53.247059
4486 11:06:53.247381
4487 11:06:53.247660 ==
4488 11:06:53.249853 Dram Type= 6, Freq= 0, CH_1, rank 1
4489 11:06:53.252994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4490 11:06:53.253509 ==
4491 11:06:53.253843
4492 11:06:53.254123
4493 11:06:53.256190 TX Vref Scan disable
4494 11:06:53.259449 == TX Byte 0 ==
4495 11:06:53.262988 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4496 11:06:53.266397 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4497 11:06:53.269744 == TX Byte 1 ==
4498 11:06:53.272755 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4499 11:06:53.276093 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4500 11:06:53.276471 ==
4501 11:06:53.279248 Dram Type= 6, Freq= 0, CH_1, rank 1
4502 11:06:53.285985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4503 11:06:53.286308 ==
4504 11:06:53.286523
4505 11:06:53.286719
4506 11:06:53.286921 TX Vref Scan disable
4507 11:06:53.290613 == TX Byte 0 ==
4508 11:06:53.294423 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4509 11:06:53.301060 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4510 11:06:53.301448 == TX Byte 1 ==
4511 11:06:53.303835 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4512 11:06:53.310687 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4513 11:06:53.311135
4514 11:06:53.311479 [DATLAT]
4515 11:06:53.311784 Freq=600, CH1 RK1
4516 11:06:53.312081
4517 11:06:53.313909 DATLAT Default: 0x8
4518 11:06:53.314337 0, 0xFFFF, sum = 0
4519 11:06:53.317154 1, 0xFFFF, sum = 0
4520 11:06:53.320157 2, 0xFFFF, sum = 0
4521 11:06:53.320587 3, 0xFFFF, sum = 0
4522 11:06:53.323620 4, 0xFFFF, sum = 0
4523 11:06:53.324050 5, 0xFFFF, sum = 0
4524 11:06:53.326818 6, 0xFFFF, sum = 0
4525 11:06:53.327244 7, 0x0, sum = 1
4526 11:06:53.327578 8, 0x0, sum = 2
4527 11:06:53.330327 9, 0x0, sum = 3
4528 11:06:53.330753 10, 0x0, sum = 4
4529 11:06:53.333492 best_step = 8
4530 11:06:53.333917
4531 11:06:53.334245 ==
4532 11:06:53.336758 Dram Type= 6, Freq= 0, CH_1, rank 1
4533 11:06:53.340748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4534 11:06:53.341298 ==
4535 11:06:53.343718 RX Vref Scan: 0
4536 11:06:53.344235
4537 11:06:53.344574 RX Vref 0 -> 0, step: 1
4538 11:06:53.344881
4539 11:06:53.346707 RX Delay -195 -> 252, step: 8
4540 11:06:53.354227 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4541 11:06:53.357845 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4542 11:06:53.360937 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4543 11:06:53.364245 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4544 11:06:53.370930 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4545 11:06:53.374045 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4546 11:06:53.377789 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4547 11:06:53.380704 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4548 11:06:53.384330 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4549 11:06:53.390760 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4550 11:06:53.394117 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4551 11:06:53.397963 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4552 11:06:53.400900 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4553 11:06:53.407545 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4554 11:06:53.410714 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4555 11:06:53.413857 iDelay=205, Bit 15, Center 36 (-115 ~ 188) 304
4556 11:06:53.414287 ==
4557 11:06:53.417313 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 11:06:53.423787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4559 11:06:53.424250 ==
4560 11:06:53.424702 DQS Delay:
4561 11:06:53.425113 DQS0 = 0, DQS1 = 0
4562 11:06:53.427001 DQM Delay:
4563 11:06:53.427460 DQM0 = 37, DQM1 = 29
4564 11:06:53.430548 DQ Delay:
4565 11:06:53.433752 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4566 11:06:53.434191 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4567 11:06:53.437434 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4568 11:06:53.443870 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =36
4569 11:06:53.444433
4570 11:06:53.444870
4571 11:06:53.450649 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4572 11:06:53.453564 CH1 RK1: MR19=808, MR18=6161
4573 11:06:53.460409 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4574 11:06:53.463921 [RxdqsGatingPostProcess] freq 600
4575 11:06:53.467070 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4576 11:06:53.470530 Pre-setting of DQS Precalculation
4577 11:06:53.476926 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4578 11:06:53.483451 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4579 11:06:53.489920 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4580 11:06:53.490408
4581 11:06:53.490741
4582 11:06:53.493354 [Calibration Summary] 1200 Mbps
4583 11:06:53.493922 CH 0, Rank 0
4584 11:06:53.497012 SW Impedance : PASS
4585 11:06:53.500224 DUTY Scan : NO K
4586 11:06:53.500730 ZQ Calibration : PASS
4587 11:06:53.503712 Jitter Meter : NO K
4588 11:06:53.506609 CBT Training : PASS
4589 11:06:53.507036 Write leveling : PASS
4590 11:06:53.509758 RX DQS gating : PASS
4591 11:06:53.513085 RX DQ/DQS(RDDQC) : PASS
4592 11:06:53.513549 TX DQ/DQS : PASS
4593 11:06:53.516491 RX DATLAT : PASS
4594 11:06:53.516916 RX DQ/DQS(Engine): PASS
4595 11:06:53.519734 TX OE : NO K
4596 11:06:53.520193 All Pass.
4597 11:06:53.520531
4598 11:06:53.523312 CH 0, Rank 1
4599 11:06:53.523818 SW Impedance : PASS
4600 11:06:53.526873 DUTY Scan : NO K
4601 11:06:53.529734 ZQ Calibration : PASS
4602 11:06:53.530157 Jitter Meter : NO K
4603 11:06:53.533060 CBT Training : PASS
4604 11:06:53.536445 Write leveling : PASS
4605 11:06:53.536870 RX DQS gating : PASS
4606 11:06:53.540315 RX DQ/DQS(RDDQC) : PASS
4607 11:06:53.543078 TX DQ/DQS : PASS
4608 11:06:53.543501 RX DATLAT : PASS
4609 11:06:53.546624 RX DQ/DQS(Engine): PASS
4610 11:06:53.549901 TX OE : NO K
4611 11:06:53.550391 All Pass.
4612 11:06:53.550728
4613 11:06:53.551036 CH 1, Rank 0
4614 11:06:53.553131 SW Impedance : PASS
4615 11:06:53.556249 DUTY Scan : NO K
4616 11:06:53.556738 ZQ Calibration : PASS
4617 11:06:53.559628 Jitter Meter : NO K
4618 11:06:53.562935 CBT Training : PASS
4619 11:06:53.563361 Write leveling : PASS
4620 11:06:53.565999 RX DQS gating : PASS
4621 11:06:53.569732 RX DQ/DQS(RDDQC) : PASS
4622 11:06:53.570158 TX DQ/DQS : PASS
4623 11:06:53.573303 RX DATLAT : PASS
4624 11:06:53.576649 RX DQ/DQS(Engine): PASS
4625 11:06:53.577074 TX OE : NO K
4626 11:06:53.577447 All Pass.
4627 11:06:53.577755
4628 11:06:53.579429 CH 1, Rank 1
4629 11:06:53.579856 SW Impedance : PASS
4630 11:06:53.582826 DUTY Scan : NO K
4631 11:06:53.586444 ZQ Calibration : PASS
4632 11:06:53.586921 Jitter Meter : NO K
4633 11:06:53.589597 CBT Training : PASS
4634 11:06:53.592632 Write leveling : PASS
4635 11:06:53.593058 RX DQS gating : PASS
4636 11:06:53.595863 RX DQ/DQS(RDDQC) : PASS
4637 11:06:53.599304 TX DQ/DQS : PASS
4638 11:06:53.599702 RX DATLAT : PASS
4639 11:06:53.603061 RX DQ/DQS(Engine): PASS
4640 11:06:53.606039 TX OE : NO K
4641 11:06:53.606460 All Pass.
4642 11:06:53.606786
4643 11:06:53.609474 DramC Write-DBI off
4644 11:06:53.610119 PER_BANK_REFRESH: Hybrid Mode
4645 11:06:53.612643 TX_TRACKING: ON
4646 11:06:53.619442 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4647 11:06:53.622662 [FAST_K] Save calibration result to emmc
4648 11:06:53.629496 dramc_set_vcore_voltage set vcore to 662500
4649 11:06:53.629961 Read voltage for 933, 3
4650 11:06:53.632638 Vio18 = 0
4651 11:06:53.633072 Vcore = 662500
4652 11:06:53.633496 Vdram = 0
4653 11:06:53.635817 Vddq = 0
4654 11:06:53.636251 Vmddr = 0
4655 11:06:53.639194 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4656 11:06:53.646364 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4657 11:06:53.649464 MEM_TYPE=3, freq_sel=17
4658 11:06:53.652480 sv_algorithm_assistance_LP4_1600
4659 11:06:53.656304 ============ PULL DRAM RESETB DOWN ============
4660 11:06:53.659678 ========== PULL DRAM RESETB DOWN end =========
4661 11:06:53.662445 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4662 11:06:53.665910 ===================================
4663 11:06:53.669353 LPDDR4 DRAM CONFIGURATION
4664 11:06:53.672364 ===================================
4665 11:06:53.675786 EX_ROW_EN[0] = 0x0
4666 11:06:53.676259 EX_ROW_EN[1] = 0x0
4667 11:06:53.680839 LP4Y_EN = 0x0
4668 11:06:53.681329 WORK_FSP = 0x0
4669 11:06:53.682603 WL = 0x3
4670 11:06:53.682767 RL = 0x3
4671 11:06:53.685592 BL = 0x2
4672 11:06:53.685757 RPST = 0x0
4673 11:06:53.688916 RD_PRE = 0x0
4674 11:06:53.689081 WR_PRE = 0x1
4675 11:06:53.691979 WR_PST = 0x0
4676 11:06:53.692143 DBI_WR = 0x0
4677 11:06:53.695724 DBI_RD = 0x0
4678 11:06:53.695954 OTF = 0x1
4679 11:06:53.699136 ===================================
4680 11:06:53.702655 ===================================
4681 11:06:53.705321 ANA top config
4682 11:06:53.709091 ===================================
4683 11:06:53.712499 DLL_ASYNC_EN = 0
4684 11:06:53.712959 ALL_SLAVE_EN = 1
4685 11:06:53.715456 NEW_RANK_MODE = 1
4686 11:06:53.719093 DLL_IDLE_MODE = 1
4687 11:06:53.722336 LP45_APHY_COMB_EN = 1
4688 11:06:53.725472 TX_ODT_DIS = 1
4689 11:06:53.725899 NEW_8X_MODE = 1
4690 11:06:53.728708 ===================================
4691 11:06:53.732449 ===================================
4692 11:06:53.735598 data_rate = 1866
4693 11:06:53.739556 CKR = 1
4694 11:06:53.742351 DQ_P2S_RATIO = 8
4695 11:06:53.745283 ===================================
4696 11:06:53.748931 CA_P2S_RATIO = 8
4697 11:06:53.752194 DQ_CA_OPEN = 0
4698 11:06:53.752695 DQ_SEMI_OPEN = 0
4699 11:06:53.755862 CA_SEMI_OPEN = 0
4700 11:06:53.759001 CA_FULL_RATE = 0
4701 11:06:53.762309 DQ_CKDIV4_EN = 1
4702 11:06:53.765622 CA_CKDIV4_EN = 1
4703 11:06:53.768769 CA_PREDIV_EN = 0
4704 11:06:53.769213 PH8_DLY = 0
4705 11:06:53.772374 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4706 11:06:53.775757 DQ_AAMCK_DIV = 4
4707 11:06:53.778788 CA_AAMCK_DIV = 4
4708 11:06:53.782036 CA_ADMCK_DIV = 4
4709 11:06:53.785830 DQ_TRACK_CA_EN = 0
4710 11:06:53.786260 CA_PICK = 933
4711 11:06:53.788712 CA_MCKIO = 933
4712 11:06:53.792143 MCKIO_SEMI = 0
4713 11:06:53.795159 PLL_FREQ = 3732
4714 11:06:53.798910 DQ_UI_PI_RATIO = 32
4715 11:06:53.801886 CA_UI_PI_RATIO = 0
4716 11:06:53.805367 ===================================
4717 11:06:53.808361 ===================================
4718 11:06:53.811696 memory_type:LPDDR4
4719 11:06:53.812117 GP_NUM : 10
4720 11:06:53.814974 SRAM_EN : 1
4721 11:06:53.815401 MD32_EN : 0
4722 11:06:53.818115 ===================================
4723 11:06:53.821585 [ANA_INIT] >>>>>>>>>>>>>>
4724 11:06:53.825099 <<<<<< [CONFIGURE PHASE]: ANA_TX
4725 11:06:53.828127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4726 11:06:53.832174 ===================================
4727 11:06:53.834803 data_rate = 1866,PCW = 0X8f00
4728 11:06:53.838104 ===================================
4729 11:06:53.841758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4730 11:06:53.845124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4731 11:06:53.851333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4732 11:06:53.857928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4733 11:06:53.861522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4734 11:06:53.864330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4735 11:06:53.864756 [ANA_INIT] flow start
4736 11:06:53.867881 [ANA_INIT] PLL >>>>>>>>
4737 11:06:53.871242 [ANA_INIT] PLL <<<<<<<<
4738 11:06:53.871667 [ANA_INIT] MIDPI >>>>>>>>
4739 11:06:53.874462 [ANA_INIT] MIDPI <<<<<<<<
4740 11:06:53.878076 [ANA_INIT] DLL >>>>>>>>
4741 11:06:53.878503 [ANA_INIT] flow end
4742 11:06:53.884447 ============ LP4 DIFF to SE enter ============
4743 11:06:53.887799 ============ LP4 DIFF to SE exit ============
4744 11:06:53.888228 [ANA_INIT] <<<<<<<<<<<<<
4745 11:06:53.890962 [Flow] Enable top DCM control >>>>>
4746 11:06:53.894389 [Flow] Enable top DCM control <<<<<
4747 11:06:53.897687 Enable DLL master slave shuffle
4748 11:06:53.904556 ==============================================================
4749 11:06:53.907732 Gating Mode config
4750 11:06:53.911101 ==============================================================
4751 11:06:53.914465 Config description:
4752 11:06:53.924316 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4753 11:06:53.930872 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4754 11:06:53.934437 SELPH_MODE 0: By rank 1: By Phase
4755 11:06:53.941464 ==============================================================
4756 11:06:53.944293 GAT_TRACK_EN = 1
4757 11:06:53.947766 RX_GATING_MODE = 2
4758 11:06:53.951073 RX_GATING_TRACK_MODE = 2
4759 11:06:53.951504 SELPH_MODE = 1
4760 11:06:53.954529 PICG_EARLY_EN = 1
4761 11:06:53.957451 VALID_LAT_VALUE = 1
4762 11:06:53.964592 ==============================================================
4763 11:06:53.967521 Enter into Gating configuration >>>>
4764 11:06:53.971236 Exit from Gating configuration <<<<
4765 11:06:53.974220 Enter into DVFS_PRE_config >>>>>
4766 11:06:53.984330 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4767 11:06:53.987403 Exit from DVFS_PRE_config <<<<<
4768 11:06:53.990889 Enter into PICG configuration >>>>
4769 11:06:53.993856 Exit from PICG configuration <<<<
4770 11:06:53.997600 [RX_INPUT] configuration >>>>>
4771 11:06:54.000638 [RX_INPUT] configuration <<<<<
4772 11:06:54.003865 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4773 11:06:54.011072 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4774 11:06:54.017470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4775 11:06:54.024274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4776 11:06:54.027277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4777 11:06:54.033872 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4778 11:06:54.040294 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4779 11:06:54.044280 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4780 11:06:54.047073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4781 11:06:54.050513 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4782 11:06:54.053972 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4783 11:06:54.060648 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4784 11:06:54.063813 ===================================
4785 11:06:54.066936 LPDDR4 DRAM CONFIGURATION
4786 11:06:54.070273 ===================================
4787 11:06:54.070700 EX_ROW_EN[0] = 0x0
4788 11:06:54.073598 EX_ROW_EN[1] = 0x0
4789 11:06:54.074030 LP4Y_EN = 0x0
4790 11:06:54.077017 WORK_FSP = 0x0
4791 11:06:54.077590 WL = 0x3
4792 11:06:54.080534 RL = 0x3
4793 11:06:54.081044 BL = 0x2
4794 11:06:54.084130 RPST = 0x0
4795 11:06:54.084636 RD_PRE = 0x0
4796 11:06:54.086849 WR_PRE = 0x1
4797 11:06:54.087276 WR_PST = 0x0
4798 11:06:54.090133 DBI_WR = 0x0
4799 11:06:54.090559 DBI_RD = 0x0
4800 11:06:54.093509 OTF = 0x1
4801 11:06:54.097307 ===================================
4802 11:06:54.100425 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4803 11:06:54.103311 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4804 11:06:54.110169 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4805 11:06:54.113687 ===================================
4806 11:06:54.114190 LPDDR4 DRAM CONFIGURATION
4807 11:06:54.116678 ===================================
4808 11:06:54.120162 EX_ROW_EN[0] = 0x10
4809 11:06:54.123477 EX_ROW_EN[1] = 0x0
4810 11:06:54.123903 LP4Y_EN = 0x0
4811 11:06:54.126565 WORK_FSP = 0x0
4812 11:06:54.127109 WL = 0x3
4813 11:06:54.130057 RL = 0x3
4814 11:06:54.130523 BL = 0x2
4815 11:06:54.133500 RPST = 0x0
4816 11:06:54.133917 RD_PRE = 0x0
4817 11:06:54.137214 WR_PRE = 0x1
4818 11:06:54.137947 WR_PST = 0x0
4819 11:06:54.140465 DBI_WR = 0x0
4820 11:06:54.141107 DBI_RD = 0x0
4821 11:06:54.143122 OTF = 0x1
4822 11:06:54.146779 ===================================
4823 11:06:54.153399 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4824 11:06:54.156345 nWR fixed to 30
4825 11:06:54.159989 [ModeRegInit_LP4] CH0 RK0
4826 11:06:54.160502 [ModeRegInit_LP4] CH0 RK1
4827 11:06:54.163575 [ModeRegInit_LP4] CH1 RK0
4828 11:06:54.166394 [ModeRegInit_LP4] CH1 RK1
4829 11:06:54.166815 match AC timing 8
4830 11:06:54.173520 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4831 11:06:54.176361 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4832 11:06:54.179654 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4833 11:06:54.186204 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4834 11:06:54.189700 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4835 11:06:54.190183 ==
4836 11:06:54.193080 Dram Type= 6, Freq= 0, CH_0, rank 0
4837 11:06:54.196016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4838 11:06:54.196440 ==
4839 11:06:54.202665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4840 11:06:54.209189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4841 11:06:54.212774 [CA 0] Center 38 (8~69) winsize 62
4842 11:06:54.216281 [CA 1] Center 38 (8~69) winsize 62
4843 11:06:54.218957 [CA 2] Center 36 (6~67) winsize 62
4844 11:06:54.222481 [CA 3] Center 36 (6~66) winsize 61
4845 11:06:54.225824 [CA 4] Center 34 (4~65) winsize 62
4846 11:06:54.229303 [CA 5] Center 34 (4~65) winsize 62
4847 11:06:54.229814
4848 11:06:54.232529 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4849 11:06:54.232964
4850 11:06:54.235990 [CATrainingPosCal] consider 1 rank data
4851 11:06:54.238966 u2DelayCellTimex100 = 270/100 ps
4852 11:06:54.242733 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4853 11:06:54.245893 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4854 11:06:54.249126 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4855 11:06:54.252414 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4856 11:06:54.255611 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4857 11:06:54.262315 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4858 11:06:54.262742
4859 11:06:54.265693 CA PerBit enable=1, Macro0, CA PI delay=34
4860 11:06:54.266121
4861 11:06:54.268843 [CBTSetCACLKResult] CA Dly = 34
4862 11:06:54.269494 CS Dly: 7 (0~38)
4863 11:06:54.269848 ==
4864 11:06:54.272431 Dram Type= 6, Freq= 0, CH_0, rank 1
4865 11:06:54.275440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4866 11:06:54.279140 ==
4867 11:06:54.282246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4868 11:06:54.288664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4869 11:06:54.292052 [CA 0] Center 38 (8~69) winsize 62
4870 11:06:54.295456 [CA 1] Center 38 (8~69) winsize 62
4871 11:06:54.298508 [CA 2] Center 36 (5~67) winsize 63
4872 11:06:54.302084 [CA 3] Center 35 (5~66) winsize 62
4873 11:06:54.305873 [CA 4] Center 34 (4~65) winsize 62
4874 11:06:54.308851 [CA 5] Center 34 (4~65) winsize 62
4875 11:06:54.309300
4876 11:06:54.312091 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4877 11:06:54.312515
4878 11:06:54.315092 [CATrainingPosCal] consider 2 rank data
4879 11:06:54.318929 u2DelayCellTimex100 = 270/100 ps
4880 11:06:54.321797 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4881 11:06:54.325092 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4882 11:06:54.328416 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4883 11:06:54.334929 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4884 11:06:54.338129 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4885 11:06:54.341574 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4886 11:06:54.341962
4887 11:06:54.345179 CA PerBit enable=1, Macro0, CA PI delay=34
4888 11:06:54.345747
4889 11:06:54.348206 [CBTSetCACLKResult] CA Dly = 34
4890 11:06:54.348593 CS Dly: 7 (0~39)
4891 11:06:54.348891
4892 11:06:54.351647 ----->DramcWriteLeveling(PI) begin...
4893 11:06:54.352056 ==
4894 11:06:54.354790 Dram Type= 6, Freq= 0, CH_0, rank 0
4895 11:06:54.361705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4896 11:06:54.362097 ==
4897 11:06:54.364704 Write leveling (Byte 0): 27 => 27
4898 11:06:54.368264 Write leveling (Byte 1): 27 => 27
4899 11:06:54.371773 DramcWriteLeveling(PI) end<-----
4900 11:06:54.372226
4901 11:06:54.372653 ==
4902 11:06:54.374876 Dram Type= 6, Freq= 0, CH_0, rank 0
4903 11:06:54.378025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4904 11:06:54.378410 ==
4905 11:06:54.381485 [Gating] SW mode calibration
4906 11:06:54.388110 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4907 11:06:54.391219 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4908 11:06:54.398113 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4909 11:06:54.401526 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 11:06:54.405108 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 11:06:54.411110 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4912 11:06:54.414773 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4913 11:06:54.417793 0 10 20 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 0)
4914 11:06:54.424416 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4915 11:06:54.427777 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 11:06:54.431089 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 11:06:54.437883 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 11:06:54.440892 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 11:06:54.444414 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 11:06:54.451434 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 11:06:54.454278 0 11 20 | B1->B0 | 2525 3130 | 0 1 | (1 1) (0 0)
4922 11:06:54.457840 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4923 11:06:54.464035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 11:06:54.467545 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 11:06:54.470750 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 11:06:54.477445 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 11:06:54.480743 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 11:06:54.484611 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 11:06:54.490826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4930 11:06:54.494337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 11:06:54.497513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 11:06:54.504060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 11:06:54.507450 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 11:06:54.510488 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 11:06:54.517408 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 11:06:54.520788 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 11:06:54.523750 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 11:06:54.530840 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 11:06:54.534170 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 11:06:54.537015 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 11:06:54.543623 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 11:06:54.547142 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 11:06:54.550298 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 11:06:54.557023 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 11:06:54.560426 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4946 11:06:54.563389 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4947 11:06:54.570255 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4948 11:06:54.570733 Total UI for P1: 0, mck2ui 16
4949 11:06:54.573851 best dqsien dly found for B0: ( 0, 14, 22)
4950 11:06:54.577006 Total UI for P1: 0, mck2ui 16
4951 11:06:54.580594 best dqsien dly found for B1: ( 0, 14, 22)
4952 11:06:54.586782 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4953 11:06:54.589959 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4954 11:06:54.590377
4955 11:06:54.593329 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4956 11:06:54.597059 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4957 11:06:54.600376 [Gating] SW calibration Done
4958 11:06:54.600875 ==
4959 11:06:54.603937 Dram Type= 6, Freq= 0, CH_0, rank 0
4960 11:06:54.607198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4961 11:06:54.607671 ==
4962 11:06:54.610263 RX Vref Scan: 0
4963 11:06:54.610748
4964 11:06:54.611077 RX Vref 0 -> 0, step: 1
4965 11:06:54.611384
4966 11:06:54.613823 RX Delay -80 -> 252, step: 8
4967 11:06:54.616721 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4968 11:06:54.623530 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
4969 11:06:54.626600 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4970 11:06:54.630682 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4971 11:06:54.633539 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4972 11:06:54.636446 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4973 11:06:54.639794 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4974 11:06:54.646432 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4975 11:06:54.649645 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4976 11:06:54.653109 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4977 11:06:54.656677 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4978 11:06:54.659650 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
4979 11:06:54.666418 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4980 11:06:54.669757 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4981 11:06:54.673480 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4982 11:06:54.676274 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4983 11:06:54.676717 ==
4984 11:06:54.679513 Dram Type= 6, Freq= 0, CH_0, rank 0
4985 11:06:54.682975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4986 11:06:54.686188 ==
4987 11:06:54.686609 DQS Delay:
4988 11:06:54.686939 DQS0 = 0, DQS1 = 0
4989 11:06:54.689968 DQM Delay:
4990 11:06:54.690390 DQM0 = 95, DQM1 = 85
4991 11:06:54.692860 DQ Delay:
4992 11:06:54.693447 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91
4993 11:06:54.696269 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
4994 11:06:54.700070 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =83
4995 11:06:54.703147 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
4996 11:06:54.706098
4997 11:06:54.706512
4998 11:06:54.706834 ==
4999 11:06:54.709509 Dram Type= 6, Freq= 0, CH_0, rank 0
5000 11:06:54.712768 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5001 11:06:54.713192 ==
5002 11:06:54.713570
5003 11:06:54.713874
5004 11:06:54.716081 TX Vref Scan disable
5005 11:06:54.716497 == TX Byte 0 ==
5006 11:06:54.723122 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5007 11:06:54.726025 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5008 11:06:54.726449 == TX Byte 1 ==
5009 11:06:54.732681 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5010 11:06:54.736032 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5011 11:06:54.736543 ==
5012 11:06:54.739316 Dram Type= 6, Freq= 0, CH_0, rank 0
5013 11:06:54.742624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5014 11:06:54.743093 ==
5015 11:06:54.743423
5016 11:06:54.743721
5017 11:06:54.745819 TX Vref Scan disable
5018 11:06:54.749398 == TX Byte 0 ==
5019 11:06:54.752989 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5020 11:06:54.756096 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5021 11:06:54.759502 == TX Byte 1 ==
5022 11:06:54.762736 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5023 11:06:54.765835 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5024 11:06:54.766255
5025 11:06:54.769756 [DATLAT]
5026 11:06:54.770330 Freq=933, CH0 RK0
5027 11:06:54.770670
5028 11:06:54.772530 DATLAT Default: 0xd
5029 11:06:54.772946 0, 0xFFFF, sum = 0
5030 11:06:54.775852 1, 0xFFFF, sum = 0
5031 11:06:54.776280 2, 0xFFFF, sum = 0
5032 11:06:54.779796 3, 0xFFFF, sum = 0
5033 11:06:54.780316 4, 0xFFFF, sum = 0
5034 11:06:54.782672 5, 0xFFFF, sum = 0
5035 11:06:54.783101 6, 0xFFFF, sum = 0
5036 11:06:54.785750 7, 0xFFFF, sum = 0
5037 11:06:54.786178 8, 0xFFFF, sum = 0
5038 11:06:54.789138 9, 0xFFFF, sum = 0
5039 11:06:54.789597 10, 0x0, sum = 1
5040 11:06:54.792382 11, 0x0, sum = 2
5041 11:06:54.792810 12, 0x0, sum = 3
5042 11:06:54.795797 13, 0x0, sum = 4
5043 11:06:54.796227 best_step = 11
5044 11:06:54.796553
5045 11:06:54.796851 ==
5046 11:06:54.799432 Dram Type= 6, Freq= 0, CH_0, rank 0
5047 11:06:54.802725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5048 11:06:54.805742 ==
5049 11:06:54.806165 RX Vref Scan: 1
5050 11:06:54.806487
5051 11:06:54.808903 RX Vref 0 -> 0, step: 1
5052 11:06:54.809351
5053 11:06:54.812389 RX Delay -69 -> 252, step: 4
5054 11:06:54.812807
5055 11:06:54.815789 Set Vref, RX VrefLevel [Byte0]: 51
5056 11:06:54.819170 [Byte1]: 45
5057 11:06:54.819589
5058 11:06:54.822280 Final RX Vref Byte 0 = 51 to rank0
5059 11:06:54.825530 Final RX Vref Byte 1 = 45 to rank0
5060 11:06:54.828885 Final RX Vref Byte 0 = 51 to rank1
5061 11:06:54.832860 Final RX Vref Byte 1 = 45 to rank1==
5062 11:06:54.835538 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 11:06:54.839034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5064 11:06:54.839459 ==
5065 11:06:54.842346 DQS Delay:
5066 11:06:54.842764 DQS0 = 0, DQS1 = 0
5067 11:06:54.843087 DQM Delay:
5068 11:06:54.845558 DQM0 = 96, DQM1 = 86
5069 11:06:54.845978 DQ Delay:
5070 11:06:54.848962 DQ0 =92, DQ1 =96, DQ2 =94, DQ3 =92
5071 11:06:54.852383 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =104
5072 11:06:54.855837 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5073 11:06:54.859007 DQ12 =96, DQ13 =90, DQ14 =96, DQ15 =98
5074 11:06:54.859609
5075 11:06:54.859958
5076 11:06:54.868817 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5077 11:06:54.872280 CH0 RK0: MR19=505, MR18=2828
5078 11:06:54.875506 CH0_RK0: MR19=0x505, MR18=0x2828, DQSOSC=409, MR23=63, INC=64, DEC=43
5079 11:06:54.875957
5080 11:06:54.879076 ----->DramcWriteLeveling(PI) begin...
5081 11:06:54.882490 ==
5082 11:06:54.885452 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 11:06:54.888961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5084 11:06:54.889479 ==
5085 11:06:54.892314 Write leveling (Byte 0): 29 => 29
5086 11:06:54.895475 Write leveling (Byte 1): 27 => 27
5087 11:06:54.898665 DramcWriteLeveling(PI) end<-----
5088 11:06:54.899086
5089 11:06:54.899413 ==
5090 11:06:54.902532 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 11:06:54.905557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5092 11:06:54.905985 ==
5093 11:06:54.908738 [Gating] SW mode calibration
5094 11:06:54.915463 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5095 11:06:54.922175 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5096 11:06:54.925364 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 11:06:54.928642 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 11:06:54.931875 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 11:06:54.938694 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 11:06:54.941755 0 10 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
5101 11:06:54.945014 0 10 20 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (1 0)
5102 11:06:54.951706 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5103 11:06:54.955058 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 11:06:54.958228 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 11:06:54.965001 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 11:06:54.968605 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 11:06:54.971524 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 11:06:54.978677 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 11:06:54.981783 0 11 20 | B1->B0 | 2c2c 3837 | 0 1 | (0 0) (0 0)
5110 11:06:54.984884 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5111 11:06:54.991964 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 11:06:54.994797 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 11:06:54.998153 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 11:06:55.004934 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 11:06:55.008192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 11:06:55.011749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 11:06:55.018007 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5118 11:06:55.021441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:06:55.024872 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:06:55.031563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 11:06:55.034617 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 11:06:55.038350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 11:06:55.044768 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 11:06:55.048101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 11:06:55.051375 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:06:55.057800 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:06:55.061053 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:06:55.064626 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:06:55.070930 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:06:55.074543 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:06:55.077781 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:06:55.084672 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:06:55.087760 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5134 11:06:55.091357 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5135 11:06:55.098104 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 11:06:55.098580 Total UI for P1: 0, mck2ui 16
5137 11:06:55.104611 best dqsien dly found for B0: ( 0, 14, 22)
5138 11:06:55.105122 Total UI for P1: 0, mck2ui 16
5139 11:06:55.107677 best dqsien dly found for B1: ( 0, 14, 22)
5140 11:06:55.114534 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5141 11:06:55.117410 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5142 11:06:55.117844
5143 11:06:55.120640 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5144 11:06:55.124080 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5145 11:06:55.127228 [Gating] SW calibration Done
5146 11:06:55.127649 ==
5147 11:06:55.130527 Dram Type= 6, Freq= 0, CH_0, rank 1
5148 11:06:55.134151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5149 11:06:55.134654 ==
5150 11:06:55.137424 RX Vref Scan: 0
5151 11:06:55.137868
5152 11:06:55.138386 RX Vref 0 -> 0, step: 1
5153 11:06:55.138728
5154 11:06:55.140741 RX Delay -80 -> 252, step: 8
5155 11:06:55.144102 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5156 11:06:55.150623 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5157 11:06:55.154174 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5158 11:06:55.157503 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5159 11:06:55.160399 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5160 11:06:55.163814 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5161 11:06:55.167738 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5162 11:06:55.173869 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5163 11:06:55.177356 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5164 11:06:55.180247 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5165 11:06:55.183985 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5166 11:06:55.187594 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5167 11:06:55.194158 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5168 11:06:55.197221 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5169 11:06:55.200532 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5170 11:06:55.203604 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5171 11:06:55.204024 ==
5172 11:06:55.206919 Dram Type= 6, Freq= 0, CH_0, rank 1
5173 11:06:55.210469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5174 11:06:55.210973 ==
5175 11:06:55.213684 DQS Delay:
5176 11:06:55.214205 DQS0 = 0, DQS1 = 0
5177 11:06:55.216996 DQM Delay:
5178 11:06:55.217544 DQM0 = 96, DQM1 = 83
5179 11:06:55.217918 DQ Delay:
5180 11:06:55.220225 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5181 11:06:55.223724 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5182 11:06:55.226879 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5183 11:06:55.230238 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5184 11:06:55.230661
5185 11:06:55.233813
5186 11:06:55.234321 ==
5187 11:06:55.236928 Dram Type= 6, Freq= 0, CH_0, rank 1
5188 11:06:55.240075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5189 11:06:55.240551 ==
5190 11:06:55.240882
5191 11:06:55.241186
5192 11:06:55.243476 TX Vref Scan disable
5193 11:06:55.243895 == TX Byte 0 ==
5194 11:06:55.250136 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5195 11:06:55.253118 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5196 11:06:55.253604 == TX Byte 1 ==
5197 11:06:55.259887 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5198 11:06:55.263174 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5199 11:06:55.263611 ==
5200 11:06:55.266683 Dram Type= 6, Freq= 0, CH_0, rank 1
5201 11:06:55.269945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5202 11:06:55.270371 ==
5203 11:06:55.270703
5204 11:06:55.271011
5205 11:06:55.273179 TX Vref Scan disable
5206 11:06:55.276785 == TX Byte 0 ==
5207 11:06:55.280274 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5208 11:06:55.283546 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5209 11:06:55.286449 == TX Byte 1 ==
5210 11:06:55.289947 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5211 11:06:55.293620 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5212 11:06:55.294102
5213 11:06:55.296745 [DATLAT]
5214 11:06:55.297222 Freq=933, CH0 RK1
5215 11:06:55.297595
5216 11:06:55.300053 DATLAT Default: 0xb
5217 11:06:55.300532 0, 0xFFFF, sum = 0
5218 11:06:55.303309 1, 0xFFFF, sum = 0
5219 11:06:55.303809 2, 0xFFFF, sum = 0
5220 11:06:55.306631 3, 0xFFFF, sum = 0
5221 11:06:55.307058 4, 0xFFFF, sum = 0
5222 11:06:55.310180 5, 0xFFFF, sum = 0
5223 11:06:55.310666 6, 0xFFFF, sum = 0
5224 11:06:55.313367 7, 0xFFFF, sum = 0
5225 11:06:55.313875 8, 0xFFFF, sum = 0
5226 11:06:55.316845 9, 0xFFFF, sum = 0
5227 11:06:55.317372 10, 0x0, sum = 1
5228 11:06:55.319946 11, 0x0, sum = 2
5229 11:06:55.320373 12, 0x0, sum = 3
5230 11:06:55.323008 13, 0x0, sum = 4
5231 11:06:55.323474 best_step = 11
5232 11:06:55.323825
5233 11:06:55.324129 ==
5234 11:06:55.326333 Dram Type= 6, Freq= 0, CH_0, rank 1
5235 11:06:55.333367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5236 11:06:55.333860 ==
5237 11:06:55.334193 RX Vref Scan: 0
5238 11:06:55.334497
5239 11:06:55.336625 RX Vref 0 -> 0, step: 1
5240 11:06:55.337121
5241 11:06:55.339756 RX Delay -69 -> 252, step: 4
5242 11:06:55.343096 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5243 11:06:55.346294 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5244 11:06:55.353214 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5245 11:06:55.356494 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5246 11:06:55.359772 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5247 11:06:55.363082 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5248 11:06:55.366209 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5249 11:06:55.369812 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5250 11:06:55.376084 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5251 11:06:55.379185 iDelay=203, Bit 9, Center 74 (-13 ~ 162) 176
5252 11:06:55.382448 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5253 11:06:55.385918 iDelay=203, Bit 11, Center 76 (-9 ~ 162) 172
5254 11:06:55.389455 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5255 11:06:55.396037 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5256 11:06:55.399198 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5257 11:06:55.402613 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5258 11:06:55.403114 ==
5259 11:06:55.405851 Dram Type= 6, Freq= 0, CH_0, rank 1
5260 11:06:55.409268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5261 11:06:55.409794 ==
5262 11:06:55.412544 DQS Delay:
5263 11:06:55.413051 DQS0 = 0, DQS1 = 0
5264 11:06:55.415876 DQM Delay:
5265 11:06:55.416370 DQM0 = 97, DQM1 = 86
5266 11:06:55.416699 DQ Delay:
5267 11:06:55.418948 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5268 11:06:55.422296 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =108
5269 11:06:55.425408 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =76
5270 11:06:55.428617 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =96
5271 11:06:55.429119
5272 11:06:55.429513
5273 11:06:55.438749 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d2d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5274 11:06:55.442048 CH0 RK1: MR19=505, MR18=2D2D
5275 11:06:55.448734 CH0_RK1: MR19=0x505, MR18=0x2D2D, DQSOSC=407, MR23=63, INC=65, DEC=43
5276 11:06:55.451884 [RxdqsGatingPostProcess] freq 933
5277 11:06:55.455229 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5278 11:06:55.458469 Pre-setting of DQS Precalculation
5279 11:06:55.465338 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5280 11:06:55.465768 ==
5281 11:06:55.468212 Dram Type= 6, Freq= 0, CH_1, rank 0
5282 11:06:55.471689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5283 11:06:55.472274 ==
5284 11:06:55.478476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5285 11:06:55.481447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5286 11:06:55.486040 [CA 0] Center 37 (7~68) winsize 62
5287 11:06:55.488837 [CA 1] Center 37 (6~68) winsize 63
5288 11:06:55.492299 [CA 2] Center 34 (4~65) winsize 62
5289 11:06:55.495645 [CA 3] Center 34 (4~65) winsize 62
5290 11:06:55.498876 [CA 4] Center 33 (2~64) winsize 63
5291 11:06:55.502238 [CA 5] Center 33 (2~64) winsize 63
5292 11:06:55.502618
5293 11:06:55.505471 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5294 11:06:55.505953
5295 11:06:55.508796 [CATrainingPosCal] consider 1 rank data
5296 11:06:55.512150 u2DelayCellTimex100 = 270/100 ps
5297 11:06:55.515282 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5298 11:06:55.522321 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5299 11:06:55.525331 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5300 11:06:55.528697 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5301 11:06:55.532152 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5302 11:06:55.535329 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5303 11:06:55.535710
5304 11:06:55.538551 CA PerBit enable=1, Macro0, CA PI delay=33
5305 11:06:55.538928
5306 11:06:55.542007 [CBTSetCACLKResult] CA Dly = 33
5307 11:06:55.542389 CS Dly: 5 (0~36)
5308 11:06:55.545138 ==
5309 11:06:55.549176 Dram Type= 6, Freq= 0, CH_1, rank 1
5310 11:06:55.552344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5311 11:06:55.552722 ==
5312 11:06:55.555006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5313 11:06:55.562616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5314 11:06:55.565322 [CA 0] Center 37 (6~68) winsize 63
5315 11:06:55.568671 [CA 1] Center 37 (6~68) winsize 63
5316 11:06:55.571837 [CA 2] Center 34 (4~65) winsize 62
5317 11:06:55.575107 [CA 3] Center 34 (4~65) winsize 62
5318 11:06:55.579120 [CA 4] Center 33 (2~64) winsize 63
5319 11:06:55.581766 [CA 5] Center 33 (2~64) winsize 63
5320 11:06:55.581970
5321 11:06:55.585260 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5322 11:06:55.585464
5323 11:06:55.588621 [CATrainingPosCal] consider 2 rank data
5324 11:06:55.592013 u2DelayCellTimex100 = 270/100 ps
5325 11:06:55.595308 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5326 11:06:55.598847 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5327 11:06:55.605290 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5328 11:06:55.608685 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5329 11:06:55.612049 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5330 11:06:55.615459 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5331 11:06:55.615845
5332 11:06:55.618759 CA PerBit enable=1, Macro0, CA PI delay=33
5333 11:06:55.619161
5334 11:06:55.621837 [CBTSetCACLKResult] CA Dly = 33
5335 11:06:55.622217 CS Dly: 5 (0~37)
5336 11:06:55.622511
5337 11:06:55.625413 ----->DramcWriteLeveling(PI) begin...
5338 11:06:55.628863 ==
5339 11:06:55.632170 Dram Type= 6, Freq= 0, CH_1, rank 0
5340 11:06:55.635074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5341 11:06:55.635497 ==
5342 11:06:55.638742 Write leveling (Byte 0): 24 => 24
5343 11:06:55.641907 Write leveling (Byte 1): 25 => 25
5344 11:06:55.645263 DramcWriteLeveling(PI) end<-----
5345 11:06:55.645737
5346 11:06:55.646068 ==
5347 11:06:55.648438 Dram Type= 6, Freq= 0, CH_1, rank 0
5348 11:06:55.651959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5349 11:06:55.652428 ==
5350 11:06:55.654896 [Gating] SW mode calibration
5351 11:06:55.661804 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5352 11:06:55.668312 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5353 11:06:55.671656 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 11:06:55.674862 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 11:06:55.681624 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 11:06:55.684934 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 11:06:55.688313 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
5358 11:06:55.695021 0 10 20 | B1->B0 | 3030 2323 | 1 0 | (0 1) (0 0)
5359 11:06:55.697999 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 11:06:55.701548 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 11:06:55.707938 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 11:06:55.711499 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 11:06:55.714653 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 11:06:55.721203 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 11:06:55.724854 0 11 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5366 11:06:55.728372 0 11 20 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
5367 11:06:55.731440 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5368 11:06:55.738028 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 11:06:55.741557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 11:06:55.744879 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 11:06:55.751093 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:06:55.754419 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 11:06:55.757979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5374 11:06:55.764590 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:06:55.767684 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:06:55.771050 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:06:55.778046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:06:55.781148 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:06:55.784714 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:06:55.790901 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:06:55.794555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:06:55.797724 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:06:55.804559 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:06:55.807870 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:06:55.811226 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:06:55.817947 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:06:55.820817 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:06:55.824844 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:06:55.831012 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5390 11:06:55.834420 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5391 11:06:55.837382 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 11:06:55.841074 Total UI for P1: 0, mck2ui 16
5393 11:06:55.844239 best dqsien dly found for B0: ( 0, 14, 18)
5394 11:06:55.847499 Total UI for P1: 0, mck2ui 16
5395 11:06:55.850732 best dqsien dly found for B1: ( 0, 14, 20)
5396 11:06:55.854493 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5397 11:06:55.857666 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5398 11:06:55.858192
5399 11:06:55.863914 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5400 11:06:55.867210 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5401 11:06:55.867639 [Gating] SW calibration Done
5402 11:06:55.870889 ==
5403 11:06:55.874060 Dram Type= 6, Freq= 0, CH_1, rank 0
5404 11:06:55.877922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5405 11:06:55.878452 ==
5406 11:06:55.878790 RX Vref Scan: 0
5407 11:06:55.879097
5408 11:06:55.880351 RX Vref 0 -> 0, step: 1
5409 11:06:55.880779
5410 11:06:55.883790 RX Delay -80 -> 252, step: 8
5411 11:06:55.887358 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5412 11:06:55.890616 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5413 11:06:55.894016 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5414 11:06:55.900529 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5415 11:06:55.903888 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5416 11:06:55.907124 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5417 11:06:55.910709 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5418 11:06:55.913701 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5419 11:06:55.917051 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5420 11:06:55.923496 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5421 11:06:55.926765 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5422 11:06:55.930097 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5423 11:06:55.933809 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5424 11:06:55.936841 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5425 11:06:55.943727 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5426 11:06:55.946755 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5427 11:06:55.947183 ==
5428 11:06:55.950034 Dram Type= 6, Freq= 0, CH_1, rank 0
5429 11:06:55.953696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5430 11:06:55.954203 ==
5431 11:06:55.956706 DQS Delay:
5432 11:06:55.957130 DQS0 = 0, DQS1 = 0
5433 11:06:55.957499 DQM Delay:
5434 11:06:55.959907 DQM0 = 95, DQM1 = 86
5435 11:06:55.960332 DQ Delay:
5436 11:06:55.963803 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5437 11:06:55.966770 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5438 11:06:55.970019 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5439 11:06:55.973346 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5440 11:06:55.973822
5441 11:06:55.974154
5442 11:06:55.974456 ==
5443 11:06:55.976665 Dram Type= 6, Freq= 0, CH_1, rank 0
5444 11:06:55.983300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5445 11:06:55.983725 ==
5446 11:06:55.984105
5447 11:06:55.984611
5448 11:06:55.984930 TX Vref Scan disable
5449 11:06:55.986947 == TX Byte 0 ==
5450 11:06:55.990381 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5451 11:06:55.996671 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5452 11:06:55.997144 == TX Byte 1 ==
5453 11:06:56.000440 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5454 11:06:56.006838 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5455 11:06:56.007265 ==
5456 11:06:56.010151 Dram Type= 6, Freq= 0, CH_1, rank 0
5457 11:06:56.013219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5458 11:06:56.013675 ==
5459 11:06:56.014019
5460 11:06:56.014319
5461 11:06:56.016515 TX Vref Scan disable
5462 11:06:56.016934 == TX Byte 0 ==
5463 11:06:56.023141 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5464 11:06:56.026811 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5465 11:06:56.027236 == TX Byte 1 ==
5466 11:06:56.033412 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5467 11:06:56.036589 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5468 11:06:56.037013
5469 11:06:56.037384 [DATLAT]
5470 11:06:56.039861 Freq=933, CH1 RK0
5471 11:06:56.040322
5472 11:06:56.040650 DATLAT Default: 0xd
5473 11:06:56.043714 0, 0xFFFF, sum = 0
5474 11:06:56.044274 1, 0xFFFF, sum = 0
5475 11:06:56.046704 2, 0xFFFF, sum = 0
5476 11:06:56.047138 3, 0xFFFF, sum = 0
5477 11:06:56.049962 4, 0xFFFF, sum = 0
5478 11:06:56.050395 5, 0xFFFF, sum = 0
5479 11:06:56.053459 6, 0xFFFF, sum = 0
5480 11:06:56.056657 7, 0xFFFF, sum = 0
5481 11:06:56.057089 8, 0xFFFF, sum = 0
5482 11:06:56.060740 9, 0xFFFF, sum = 0
5483 11:06:56.061305 10, 0x0, sum = 1
5484 11:06:56.061660 11, 0x0, sum = 2
5485 11:06:56.063235 12, 0x0, sum = 3
5486 11:06:56.063667 13, 0x0, sum = 4
5487 11:06:56.066581 best_step = 11
5488 11:06:56.067018
5489 11:06:56.067341 ==
5490 11:06:56.069850 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 11:06:56.073214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5492 11:06:56.073721 ==
5493 11:06:56.076666 RX Vref Scan: 1
5494 11:06:56.077087
5495 11:06:56.077450 RX Vref 0 -> 0, step: 1
5496 11:06:56.077760
5497 11:06:56.079665 RX Delay -69 -> 252, step: 4
5498 11:06:56.080088
5499 11:06:56.083002 Set Vref, RX VrefLevel [Byte0]: 52
5500 11:06:56.086746 [Byte1]: 48
5501 11:06:56.090805
5502 11:06:56.091231 Final RX Vref Byte 0 = 52 to rank0
5503 11:06:56.093928 Final RX Vref Byte 1 = 48 to rank0
5504 11:06:56.097321 Final RX Vref Byte 0 = 52 to rank1
5505 11:06:56.101034 Final RX Vref Byte 1 = 48 to rank1==
5506 11:06:56.104054 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 11:06:56.110875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5508 11:06:56.111392 ==
5509 11:06:56.111729 DQS Delay:
5510 11:06:56.113923 DQS0 = 0, DQS1 = 0
5511 11:06:56.114348 DQM Delay:
5512 11:06:56.114677 DQM0 = 94, DQM1 = 88
5513 11:06:56.117081 DQ Delay:
5514 11:06:56.120776 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =90
5515 11:06:56.123940 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5516 11:06:56.127064 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5517 11:06:56.130294 DQ12 =94, DQ13 =100, DQ14 =96, DQ15 =98
5518 11:06:56.130718
5519 11:06:56.131050
5520 11:06:56.136833 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5521 11:06:56.140171 CH1 RK0: MR19=505, MR18=3737
5522 11:06:56.147303 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5523 11:06:56.147771
5524 11:06:56.150758 ----->DramcWriteLeveling(PI) begin...
5525 11:06:56.151194 ==
5526 11:06:56.153343 Dram Type= 6, Freq= 0, CH_1, rank 1
5527 11:06:56.156795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5528 11:06:56.157253 ==
5529 11:06:56.160433 Write leveling (Byte 0): 26 => 26
5530 11:06:56.163762 Write leveling (Byte 1): 25 => 25
5531 11:06:56.166729 DramcWriteLeveling(PI) end<-----
5532 11:06:56.167154
5533 11:06:56.167484 ==
5534 11:06:56.170157 Dram Type= 6, Freq= 0, CH_1, rank 1
5535 11:06:56.173695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5536 11:06:56.176740 ==
5537 11:06:56.177339 [Gating] SW mode calibration
5538 11:06:56.183329 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5539 11:06:56.190396 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5540 11:06:56.193357 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 11:06:56.199997 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 11:06:56.203396 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 11:06:56.206537 0 10 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5544 11:06:56.213588 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
5545 11:06:56.217070 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5546 11:06:56.219665 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 11:06:56.226518 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 11:06:56.229811 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 11:06:56.233449 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 11:06:56.239912 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 11:06:56.243514 0 11 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5552 11:06:56.246787 0 11 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
5553 11:06:56.253329 0 11 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5554 11:06:56.256184 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 11:06:56.260013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 11:06:56.266544 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 11:06:56.269601 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 11:06:56.273023 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 11:06:56.279389 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5560 11:06:56.282777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5561 11:06:56.285945 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 11:06:56.292611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:06:56.295893 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:06:56.299349 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:06:56.302796 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:06:56.309042 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 11:06:56.313020 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 11:06:56.316194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 11:06:56.322487 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 11:06:56.325854 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 11:06:56.329424 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 11:06:56.335912 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 11:06:56.339389 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 11:06:56.342580 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 11:06:56.349347 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5576 11:06:56.352687 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 11:06:56.355927 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5578 11:06:56.362373 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:06:56.365685 Total UI for P1: 0, mck2ui 16
5580 11:06:56.369152 best dqsien dly found for B0: ( 0, 14, 20)
5581 11:06:56.369604 Total UI for P1: 0, mck2ui 16
5582 11:06:56.376259 best dqsien dly found for B1: ( 0, 14, 20)
5583 11:06:56.378994 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5584 11:06:56.382350 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5585 11:06:56.382791
5586 11:06:56.385628 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5587 11:06:56.389171 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5588 11:06:56.392037 [Gating] SW calibration Done
5589 11:06:56.392617 ==
5590 11:06:56.396154 Dram Type= 6, Freq= 0, CH_1, rank 1
5591 11:06:56.398891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5592 11:06:56.399315 ==
5593 11:06:56.402229 RX Vref Scan: 0
5594 11:06:56.402739
5595 11:06:56.403070 RX Vref 0 -> 0, step: 1
5596 11:06:56.403372
5597 11:06:56.405710 RX Delay -80 -> 252, step: 8
5598 11:06:56.412155 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5599 11:06:56.415842 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5600 11:06:56.419214 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5601 11:06:56.422413 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5602 11:06:56.425462 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5603 11:06:56.429547 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5604 11:06:56.435481 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5605 11:06:56.438933 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5606 11:06:56.442077 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5607 11:06:56.445624 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5608 11:06:56.448978 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5609 11:06:56.452088 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5610 11:06:56.458679 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5611 11:06:56.462245 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5612 11:06:56.465393 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5613 11:06:56.468763 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5614 11:06:56.469186 ==
5615 11:06:56.472056 Dram Type= 6, Freq= 0, CH_1, rank 1
5616 11:06:56.475478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5617 11:06:56.478884 ==
5618 11:06:56.479307 DQS Delay:
5619 11:06:56.479635 DQS0 = 0, DQS1 = 0
5620 11:06:56.481921 DQM Delay:
5621 11:06:56.482342 DQM0 = 95, DQM1 = 85
5622 11:06:56.485292 DQ Delay:
5623 11:06:56.488585 DQ0 =103, DQ1 =87, DQ2 =87, DQ3 =91
5624 11:06:56.491725 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5625 11:06:56.495615 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5626 11:06:56.498835 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5627 11:06:56.499344
5628 11:06:56.499775
5629 11:06:56.500217 ==
5630 11:06:56.501720 Dram Type= 6, Freq= 0, CH_1, rank 1
5631 11:06:56.504789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5632 11:06:56.505213 ==
5633 11:06:56.505572
5634 11:06:56.505872
5635 11:06:56.508280 TX Vref Scan disable
5636 11:06:56.508702 == TX Byte 0 ==
5637 11:06:56.515029 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5638 11:06:56.518401 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5639 11:06:56.518909 == TX Byte 1 ==
5640 11:06:56.525035 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5641 11:06:56.528125 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5642 11:06:56.528546 ==
5643 11:06:56.531479 Dram Type= 6, Freq= 0, CH_1, rank 1
5644 11:06:56.534754 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5645 11:06:56.535184 ==
5646 11:06:56.535519
5647 11:06:56.538227
5648 11:06:56.538649 TX Vref Scan disable
5649 11:06:56.541540 == TX Byte 0 ==
5650 11:06:56.544830 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5651 11:06:56.548420 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5652 11:06:56.551443 == TX Byte 1 ==
5653 11:06:56.554844 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5654 11:06:56.561189 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5655 11:06:56.561699
5656 11:06:56.562034 [DATLAT]
5657 11:06:56.562342 Freq=933, CH1 RK1
5658 11:06:56.562636
5659 11:06:56.564544 DATLAT Default: 0xb
5660 11:06:56.564969 0, 0xFFFF, sum = 0
5661 11:06:56.567833 1, 0xFFFF, sum = 0
5662 11:06:56.568264 2, 0xFFFF, sum = 0
5663 11:06:56.571686 3, 0xFFFF, sum = 0
5664 11:06:56.572259 4, 0xFFFF, sum = 0
5665 11:06:56.574724 5, 0xFFFF, sum = 0
5666 11:06:56.577836 6, 0xFFFF, sum = 0
5667 11:06:56.578284 7, 0xFFFF, sum = 0
5668 11:06:56.581104 8, 0xFFFF, sum = 0
5669 11:06:56.581595 9, 0xFFFF, sum = 0
5670 11:06:56.584524 10, 0x0, sum = 1
5671 11:06:56.584953 11, 0x0, sum = 2
5672 11:06:56.585359 12, 0x0, sum = 3
5673 11:06:56.588123 13, 0x0, sum = 4
5674 11:06:56.588555 best_step = 11
5675 11:06:56.588888
5676 11:06:56.591511 ==
5677 11:06:56.591988 Dram Type= 6, Freq= 0, CH_1, rank 1
5678 11:06:56.597758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5679 11:06:56.598263 ==
5680 11:06:56.598602 RX Vref Scan: 0
5681 11:06:56.598912
5682 11:06:56.601462 RX Vref 0 -> 0, step: 1
5683 11:06:56.602003
5684 11:06:56.605102 RX Delay -77 -> 252, step: 4
5685 11:06:56.607933 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5686 11:06:56.614488 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5687 11:06:56.617781 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5688 11:06:56.621218 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5689 11:06:56.624638 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5690 11:06:56.628000 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5691 11:06:56.631294 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5692 11:06:56.637945 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5693 11:06:56.641351 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5694 11:06:56.644402 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5695 11:06:56.647972 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5696 11:06:56.650846 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5697 11:06:56.657524 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5698 11:06:56.660885 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5699 11:06:56.664128 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5700 11:06:56.667517 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5701 11:06:56.667883 ==
5702 11:06:56.670691 Dram Type= 6, Freq= 0, CH_1, rank 1
5703 11:06:56.674227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5704 11:06:56.674449 ==
5705 11:06:56.677421 DQS Delay:
5706 11:06:56.677864 DQS0 = 0, DQS1 = 0
5707 11:06:56.680637 DQM Delay:
5708 11:06:56.681165 DQM0 = 95, DQM1 = 87
5709 11:06:56.681542 DQ Delay:
5710 11:06:56.684308 DQ0 =94, DQ1 =90, DQ2 =88, DQ3 =92
5711 11:06:56.687578 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =94
5712 11:06:56.690617 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =80
5713 11:06:56.694099 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5714 11:06:56.697397
5715 11:06:56.697781
5716 11:06:56.703971 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5717 11:06:56.707100 CH1 RK1: MR19=505, MR18=2929
5718 11:06:56.713751 CH1_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5719 11:06:56.717211 [RxdqsGatingPostProcess] freq 933
5720 11:06:56.720637 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5721 11:06:56.724000 Pre-setting of DQS Precalculation
5722 11:06:56.730398 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5723 11:06:56.737201 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5724 11:06:56.744056 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5725 11:06:56.744487
5726 11:06:56.744785
5727 11:06:56.747055 [Calibration Summary] 1866 Mbps
5728 11:06:56.747440 CH 0, Rank 0
5729 11:06:56.750230 SW Impedance : PASS
5730 11:06:56.753991 DUTY Scan : NO K
5731 11:06:56.754376 ZQ Calibration : PASS
5732 11:06:56.756983 Jitter Meter : NO K
5733 11:06:56.760324 CBT Training : PASS
5734 11:06:56.760706 Write leveling : PASS
5735 11:06:56.763760 RX DQS gating : PASS
5736 11:06:56.764220 RX DQ/DQS(RDDQC) : PASS
5737 11:06:56.767156 TX DQ/DQS : PASS
5738 11:06:56.770840 RX DATLAT : PASS
5739 11:06:56.771303 RX DQ/DQS(Engine): PASS
5740 11:06:56.773516 TX OE : NO K
5741 11:06:56.773902 All Pass.
5742 11:06:56.774198
5743 11:06:56.777063 CH 0, Rank 1
5744 11:06:56.777575 SW Impedance : PASS
5745 11:06:56.780468 DUTY Scan : NO K
5746 11:06:56.783385 ZQ Calibration : PASS
5747 11:06:56.783777 Jitter Meter : NO K
5748 11:06:56.786951 CBT Training : PASS
5749 11:06:56.790564 Write leveling : PASS
5750 11:06:56.790942 RX DQS gating : PASS
5751 11:06:56.793405 RX DQ/DQS(RDDQC) : PASS
5752 11:06:56.796943 TX DQ/DQS : PASS
5753 11:06:56.797372 RX DATLAT : PASS
5754 11:06:56.800016 RX DQ/DQS(Engine): PASS
5755 11:06:56.803470 TX OE : NO K
5756 11:06:56.803869 All Pass.
5757 11:06:56.804267
5758 11:06:56.804640 CH 1, Rank 0
5759 11:06:56.806427 SW Impedance : PASS
5760 11:06:56.809930 DUTY Scan : NO K
5761 11:06:56.810330 ZQ Calibration : PASS
5762 11:06:56.813296 Jitter Meter : NO K
5763 11:06:56.816592 CBT Training : PASS
5764 11:06:56.816985 Write leveling : PASS
5765 11:06:56.819935 RX DQS gating : PASS
5766 11:06:56.820368 RX DQ/DQS(RDDQC) : PASS
5767 11:06:56.823626 TX DQ/DQS : PASS
5768 11:06:56.826832 RX DATLAT : PASS
5769 11:06:56.827323 RX DQ/DQS(Engine): PASS
5770 11:06:56.829723 TX OE : NO K
5771 11:06:56.830107 All Pass.
5772 11:06:56.830402
5773 11:06:56.833179 CH 1, Rank 1
5774 11:06:56.833596 SW Impedance : PASS
5775 11:06:56.836579 DUTY Scan : NO K
5776 11:06:56.839634 ZQ Calibration : PASS
5777 11:06:56.840019 Jitter Meter : NO K
5778 11:06:56.843094 CBT Training : PASS
5779 11:06:56.846899 Write leveling : PASS
5780 11:06:56.847412 RX DQS gating : PASS
5781 11:06:56.849587 RX DQ/DQS(RDDQC) : PASS
5782 11:06:56.853062 TX DQ/DQS : PASS
5783 11:06:56.853541 RX DATLAT : PASS
5784 11:06:56.856194 RX DQ/DQS(Engine): PASS
5785 11:06:56.859755 TX OE : NO K
5786 11:06:56.860181 All Pass.
5787 11:06:56.860510
5788 11:06:56.860809 DramC Write-DBI off
5789 11:06:56.863203 PER_BANK_REFRESH: Hybrid Mode
5790 11:06:56.866393 TX_TRACKING: ON
5791 11:06:56.872817 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5792 11:06:56.880066 [FAST_K] Save calibration result to emmc
5793 11:06:56.883004 dramc_set_vcore_voltage set vcore to 650000
5794 11:06:56.883435 Read voltage for 400, 6
5795 11:06:56.886106 Vio18 = 0
5796 11:06:56.886530 Vcore = 650000
5797 11:06:56.886860 Vdram = 0
5798 11:06:56.889362 Vddq = 0
5799 11:06:56.889887 Vmddr = 0
5800 11:06:56.892660 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5801 11:06:56.899388 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5802 11:06:56.903134 MEM_TYPE=3, freq_sel=20
5803 11:06:56.906137 sv_algorithm_assistance_LP4_800
5804 11:06:56.909885 ============ PULL DRAM RESETB DOWN ============
5805 11:06:56.912774 ========== PULL DRAM RESETB DOWN end =========
5806 11:06:56.916169 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5807 11:06:56.922235 ===================================
5808 11:06:56.922780 LPDDR4 DRAM CONFIGURATION
5809 11:06:56.926115 ===================================
5810 11:06:56.928957 EX_ROW_EN[0] = 0x0
5811 11:06:56.929512 EX_ROW_EN[1] = 0x0
5812 11:06:56.932346 LP4Y_EN = 0x0
5813 11:06:56.932773 WORK_FSP = 0x0
5814 11:06:56.935633 WL = 0x2
5815 11:06:56.936136 RL = 0x2
5816 11:06:56.939182 BL = 0x2
5817 11:06:56.939625 RPST = 0x0
5818 11:06:56.942630 RD_PRE = 0x0
5819 11:06:56.945863 WR_PRE = 0x1
5820 11:06:56.946289 WR_PST = 0x0
5821 11:06:56.949280 DBI_WR = 0x0
5822 11:06:56.949840 DBI_RD = 0x0
5823 11:06:56.952032 OTF = 0x1
5824 11:06:56.955692 ===================================
5825 11:06:56.958639 ===================================
5826 11:06:56.959114 ANA top config
5827 11:06:56.961999 ===================================
5828 11:06:56.965487 DLL_ASYNC_EN = 0
5829 11:06:56.968576 ALL_SLAVE_EN = 1
5830 11:06:56.969000 NEW_RANK_MODE = 1
5831 11:06:56.972168 DLL_IDLE_MODE = 1
5832 11:06:56.975375 LP45_APHY_COMB_EN = 1
5833 11:06:56.978774 TX_ODT_DIS = 1
5834 11:06:56.982244 NEW_8X_MODE = 1
5835 11:06:56.982762 ===================================
5836 11:06:56.988535 ===================================
5837 11:06:56.989052 data_rate = 800
5838 11:06:56.991953 CKR = 1
5839 11:06:56.994956 DQ_P2S_RATIO = 4
5840 11:06:56.998509 ===================================
5841 11:06:57.001907 CA_P2S_RATIO = 4
5842 11:06:57.005747 DQ_CA_OPEN = 0
5843 11:06:57.008319 DQ_SEMI_OPEN = 1
5844 11:06:57.008830 CA_SEMI_OPEN = 1
5845 11:06:57.011896 CA_FULL_RATE = 0
5846 11:06:57.015220 DQ_CKDIV4_EN = 0
5847 11:06:57.018313 CA_CKDIV4_EN = 1
5848 11:06:57.021661 CA_PREDIV_EN = 0
5849 11:06:57.024833 PH8_DLY = 0
5850 11:06:57.025293 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5851 11:06:57.028216 DQ_AAMCK_DIV = 0
5852 11:06:57.031477 CA_AAMCK_DIV = 0
5853 11:06:57.035065 CA_ADMCK_DIV = 4
5854 11:06:57.038265 DQ_TRACK_CA_EN = 0
5855 11:06:57.041401 CA_PICK = 800
5856 11:06:57.045403 CA_MCKIO = 400
5857 11:06:57.045944 MCKIO_SEMI = 400
5858 11:06:57.048127 PLL_FREQ = 3016
5859 11:06:57.051213 DQ_UI_PI_RATIO = 32
5860 11:06:57.054284 CA_UI_PI_RATIO = 32
5861 11:06:57.057719 ===================================
5862 11:06:57.061337 ===================================
5863 11:06:57.064591 memory_type:LPDDR4
5864 11:06:57.065175 GP_NUM : 10
5865 11:06:57.067693 SRAM_EN : 1
5866 11:06:57.071064 MD32_EN : 0
5867 11:06:57.074326 ===================================
5868 11:06:57.074750 [ANA_INIT] >>>>>>>>>>>>>>
5869 11:06:57.077553 <<<<<< [CONFIGURE PHASE]: ANA_TX
5870 11:06:57.081129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5871 11:06:57.084189 ===================================
5872 11:06:57.088348 data_rate = 800,PCW = 0X7400
5873 11:06:57.090914 ===================================
5874 11:06:57.094750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5875 11:06:57.100977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5876 11:06:57.110640 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5877 11:06:57.117704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5878 11:06:57.120686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5879 11:06:57.124430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5880 11:06:57.124912 [ANA_INIT] flow start
5881 11:06:57.127424 [ANA_INIT] PLL >>>>>>>>
5882 11:06:57.130574 [ANA_INIT] PLL <<<<<<<<
5883 11:06:57.131010 [ANA_INIT] MIDPI >>>>>>>>
5884 11:06:57.134148 [ANA_INIT] MIDPI <<<<<<<<
5885 11:06:57.136923 [ANA_INIT] DLL >>>>>>>>
5886 11:06:57.137467 [ANA_INIT] flow end
5887 11:06:57.144117 ============ LP4 DIFF to SE enter ============
5888 11:06:57.147124 ============ LP4 DIFF to SE exit ============
5889 11:06:57.150330 [ANA_INIT] <<<<<<<<<<<<<
5890 11:06:57.153719 [Flow] Enable top DCM control >>>>>
5891 11:06:57.157211 [Flow] Enable top DCM control <<<<<
5892 11:06:57.157772 Enable DLL master slave shuffle
5893 11:06:57.163571 ==============================================================
5894 11:06:57.167083 Gating Mode config
5895 11:06:57.170563 ==============================================================
5896 11:06:57.173626 Config description:
5897 11:06:57.183375 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5898 11:06:57.190283 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5899 11:06:57.193365 SELPH_MODE 0: By rank 1: By Phase
5900 11:06:57.200235 ==============================================================
5901 11:06:57.203662 GAT_TRACK_EN = 0
5902 11:06:57.206800 RX_GATING_MODE = 2
5903 11:06:57.210172 RX_GATING_TRACK_MODE = 2
5904 11:06:57.213406 SELPH_MODE = 1
5905 11:06:57.213877 PICG_EARLY_EN = 1
5906 11:06:57.216849 VALID_LAT_VALUE = 1
5907 11:06:57.223883 ==============================================================
5908 11:06:57.226960 Enter into Gating configuration >>>>
5909 11:06:57.229916 Exit from Gating configuration <<<<
5910 11:06:57.233499 Enter into DVFS_PRE_config >>>>>
5911 11:06:57.243478 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5912 11:06:57.246771 Exit from DVFS_PRE_config <<<<<
5913 11:06:57.250456 Enter into PICG configuration >>>>
5914 11:06:57.253452 Exit from PICG configuration <<<<
5915 11:06:57.256890 [RX_INPUT] configuration >>>>>
5916 11:06:57.259851 [RX_INPUT] configuration <<<<<
5917 11:06:57.263368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5918 11:06:57.269838 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5919 11:06:57.276662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5920 11:06:57.283068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5921 11:06:57.289844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5922 11:06:57.293048 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5923 11:06:57.299942 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5924 11:06:57.303486 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5925 11:06:57.306457 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5926 11:06:57.309914 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5927 11:06:57.317448 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5928 11:06:57.320085 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5929 11:06:57.322779 ===================================
5930 11:06:57.326307 LPDDR4 DRAM CONFIGURATION
5931 11:06:57.329720 ===================================
5932 11:06:57.330305 EX_ROW_EN[0] = 0x0
5933 11:06:57.332760 EX_ROW_EN[1] = 0x0
5934 11:06:57.333375 LP4Y_EN = 0x0
5935 11:06:57.336364 WORK_FSP = 0x0
5936 11:06:57.336960 WL = 0x2
5937 11:06:57.339896 RL = 0x2
5938 11:06:57.340472 BL = 0x2
5939 11:06:57.343017 RPST = 0x0
5940 11:06:57.343438 RD_PRE = 0x0
5941 11:06:57.346214 WR_PRE = 0x1
5942 11:06:57.349400 WR_PST = 0x0
5943 11:06:57.349822 DBI_WR = 0x0
5944 11:06:57.353127 DBI_RD = 0x0
5945 11:06:57.353646 OTF = 0x1
5946 11:06:57.355960 ===================================
5947 11:06:57.359300 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5948 11:06:57.366084 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5949 11:06:57.369467 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5950 11:06:57.372810 ===================================
5951 11:06:57.375987 LPDDR4 DRAM CONFIGURATION
5952 11:06:57.379040 ===================================
5953 11:06:57.379462 EX_ROW_EN[0] = 0x10
5954 11:06:57.382488 EX_ROW_EN[1] = 0x0
5955 11:06:57.382910 LP4Y_EN = 0x0
5956 11:06:57.386081 WORK_FSP = 0x0
5957 11:06:57.386508 WL = 0x2
5958 11:06:57.389754 RL = 0x2
5959 11:06:57.390331 BL = 0x2
5960 11:06:57.392352 RPST = 0x0
5961 11:06:57.392774 RD_PRE = 0x0
5962 11:06:57.395886 WR_PRE = 0x1
5963 11:06:57.396308 WR_PST = 0x0
5964 11:06:57.399179 DBI_WR = 0x0
5965 11:06:57.402812 DBI_RD = 0x0
5966 11:06:57.403288 OTF = 0x1
5967 11:06:57.405989 ===================================
5968 11:06:57.412519 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5969 11:06:57.416032 nWR fixed to 30
5970 11:06:57.419581 [ModeRegInit_LP4] CH0 RK0
5971 11:06:57.420081 [ModeRegInit_LP4] CH0 RK1
5972 11:06:57.422414 [ModeRegInit_LP4] CH1 RK0
5973 11:06:57.425714 [ModeRegInit_LP4] CH1 RK1
5974 11:06:57.426138 match AC timing 18
5975 11:06:57.432698 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5976 11:06:57.435976 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5977 11:06:57.438894 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5978 11:06:57.446268 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5979 11:06:57.449148 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5980 11:06:57.449704 ==
5981 11:06:57.452311 Dram Type= 6, Freq= 0, CH_0, rank 0
5982 11:06:57.455459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5983 11:06:57.456030 ==
5984 11:06:57.462814 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5985 11:06:57.469179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5986 11:06:57.472191 [CA 0] Center 36 (8~64) winsize 57
5987 11:06:57.475608 [CA 1] Center 36 (8~64) winsize 57
5988 11:06:57.478931 [CA 2] Center 36 (8~64) winsize 57
5989 11:06:57.482354 [CA 3] Center 36 (8~64) winsize 57
5990 11:06:57.482863 [CA 4] Center 36 (8~64) winsize 57
5991 11:06:57.485435 [CA 5] Center 36 (8~64) winsize 57
5992 11:06:57.485861
5993 11:06:57.491924 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5994 11:06:57.492468
5995 11:06:57.495189 [CATrainingPosCal] consider 1 rank data
5996 11:06:57.498848 u2DelayCellTimex100 = 270/100 ps
5997 11:06:57.502537 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 11:06:57.505626 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5999 11:06:57.508579 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6000 11:06:57.511761 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 11:06:57.515426 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6002 11:06:57.518865 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6003 11:06:57.519381
6004 11:06:57.521727 CA PerBit enable=1, Macro0, CA PI delay=36
6005 11:06:57.522156
6006 11:06:57.525107 [CBTSetCACLKResult] CA Dly = 36
6007 11:06:57.528367 CS Dly: 1 (0~32)
6008 11:06:57.528790 ==
6009 11:06:57.531996 Dram Type= 6, Freq= 0, CH_0, rank 1
6010 11:06:57.534916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6011 11:06:57.535395 ==
6012 11:06:57.541631 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6013 11:06:57.548416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6014 11:06:57.551648 [CA 0] Center 36 (8~64) winsize 57
6015 11:06:57.552079 [CA 1] Center 36 (8~64) winsize 57
6016 11:06:57.554971 [CA 2] Center 36 (8~64) winsize 57
6017 11:06:57.558141 [CA 3] Center 36 (8~64) winsize 57
6018 11:06:57.561478 [CA 4] Center 36 (8~64) winsize 57
6019 11:06:57.564948 [CA 5] Center 36 (8~64) winsize 57
6020 11:06:57.565421
6021 11:06:57.568559 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6022 11:06:57.568984
6023 11:06:57.571550 [CATrainingPosCal] consider 2 rank data
6024 11:06:57.574890 u2DelayCellTimex100 = 270/100 ps
6025 11:06:57.578170 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 11:06:57.584945 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 11:06:57.588170 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 11:06:57.591660 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 11:06:57.594663 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 11:06:57.598076 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 11:06:57.598496
6032 11:06:57.601689 CA PerBit enable=1, Macro0, CA PI delay=36
6033 11:06:57.602111
6034 11:06:57.605058 [CBTSetCACLKResult] CA Dly = 36
6035 11:06:57.605587 CS Dly: 1 (0~32)
6036 11:06:57.608303
6037 11:06:57.611278 ----->DramcWriteLeveling(PI) begin...
6038 11:06:57.611661 ==
6039 11:06:57.614667 Dram Type= 6, Freq= 0, CH_0, rank 0
6040 11:06:57.617906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6041 11:06:57.618334 ==
6042 11:06:57.621383 Write leveling (Byte 0): 32 => 0
6043 11:06:57.624565 Write leveling (Byte 1): 32 => 0
6044 11:06:57.627811 DramcWriteLeveling(PI) end<-----
6045 11:06:57.628231
6046 11:06:57.628556 ==
6047 11:06:57.631225 Dram Type= 6, Freq= 0, CH_0, rank 0
6048 11:06:57.634552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6049 11:06:57.635028 ==
6050 11:06:57.638026 [Gating] SW mode calibration
6051 11:06:57.644935 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6052 11:06:57.651370 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6053 11:06:57.654697 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6054 11:06:57.658018 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6055 11:06:57.664350 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6056 11:06:57.667634 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6057 11:06:57.670928 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6058 11:06:57.674279 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6059 11:06:57.681035 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6060 11:06:57.684386 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6061 11:06:57.687562 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6062 11:06:57.691388 Total UI for P1: 0, mck2ui 16
6063 11:06:57.694139 best dqsien dly found for B0: ( 0, 10, 16)
6064 11:06:57.697545 Total UI for P1: 0, mck2ui 16
6065 11:06:57.700709 best dqsien dly found for B1: ( 0, 10, 24)
6066 11:06:57.704243 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6067 11:06:57.710756 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6068 11:06:57.711195
6069 11:06:57.714559 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6070 11:06:57.717630 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6071 11:06:57.720542 [Gating] SW calibration Done
6072 11:06:57.720964 ==
6073 11:06:57.723817 Dram Type= 6, Freq= 0, CH_0, rank 0
6074 11:06:57.727106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6075 11:06:57.727534 ==
6076 11:06:57.730694 RX Vref Scan: 0
6077 11:06:57.731115
6078 11:06:57.731440 RX Vref 0 -> 0, step: 1
6079 11:06:57.731741
6080 11:06:57.734105 RX Delay -410 -> 252, step: 16
6081 11:06:57.737547 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6082 11:06:57.743931 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6083 11:06:57.747146 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6084 11:06:57.750777 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6085 11:06:57.754236 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6086 11:06:57.760731 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6087 11:06:57.763758 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6088 11:06:57.767560 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6089 11:06:57.770450 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6090 11:06:57.777368 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6091 11:06:57.780161 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6092 11:06:57.783733 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6093 11:06:57.790503 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6094 11:06:57.793819 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6095 11:06:57.796912 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6096 11:06:57.800645 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6097 11:06:57.803780 ==
6098 11:06:57.804263 Dram Type= 6, Freq= 0, CH_0, rank 0
6099 11:06:57.810258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6100 11:06:57.810723 ==
6101 11:06:57.811219 DQS Delay:
6102 11:06:57.813979 DQS0 = 43, DQS1 = 59
6103 11:06:57.814557 DQM Delay:
6104 11:06:57.817318 DQM0 = 5, DQM1 = 13
6105 11:06:57.817982 DQ Delay:
6106 11:06:57.820332 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6107 11:06:57.823484 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6108 11:06:57.823936 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6109 11:06:57.827128 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6110 11:06:57.829861
6111 11:06:57.830300
6112 11:06:57.830662 ==
6113 11:06:57.833318 Dram Type= 6, Freq= 0, CH_0, rank 0
6114 11:06:57.836744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6115 11:06:57.837384 ==
6116 11:06:57.837867
6117 11:06:57.838397
6118 11:06:57.839942 TX Vref Scan disable
6119 11:06:57.840439 == TX Byte 0 ==
6120 11:06:57.843170 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6121 11:06:57.850043 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6122 11:06:57.850508 == TX Byte 1 ==
6123 11:06:57.853127 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6124 11:06:57.859906 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6125 11:06:57.860364 ==
6126 11:06:57.864128 Dram Type= 6, Freq= 0, CH_0, rank 0
6127 11:06:57.866628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6128 11:06:57.867070 ==
6129 11:06:57.867561
6130 11:06:57.867966
6131 11:06:57.869697 TX Vref Scan disable
6132 11:06:57.870186 == TX Byte 0 ==
6133 11:06:57.876339 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6134 11:06:57.879697 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6135 11:06:57.880135 == TX Byte 1 ==
6136 11:06:57.886425 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6137 11:06:57.889660 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6138 11:06:57.890085
6139 11:06:57.890412 [DATLAT]
6140 11:06:57.892999 Freq=400, CH0 RK0
6141 11:06:57.893597
6142 11:06:57.893934 DATLAT Default: 0xf
6143 11:06:57.896810 0, 0xFFFF, sum = 0
6144 11:06:57.897467 1, 0xFFFF, sum = 0
6145 11:06:57.899721 2, 0xFFFF, sum = 0
6146 11:06:57.900279 3, 0xFFFF, sum = 0
6147 11:06:57.903038 4, 0xFFFF, sum = 0
6148 11:06:57.903468 5, 0xFFFF, sum = 0
6149 11:06:57.906232 6, 0xFFFF, sum = 0
6150 11:06:57.909687 7, 0xFFFF, sum = 0
6151 11:06:57.910173 8, 0xFFFF, sum = 0
6152 11:06:57.912822 9, 0xFFFF, sum = 0
6153 11:06:57.913555 10, 0xFFFF, sum = 0
6154 11:06:57.916171 11, 0xFFFF, sum = 0
6155 11:06:57.916782 12, 0x0, sum = 1
6156 11:06:57.919506 13, 0x0, sum = 2
6157 11:06:57.919948 14, 0x0, sum = 3
6158 11:06:57.922961 15, 0x0, sum = 4
6159 11:06:57.923461 best_step = 13
6160 11:06:57.923943
6161 11:06:57.924349 ==
6162 11:06:57.925985 Dram Type= 6, Freq= 0, CH_0, rank 0
6163 11:06:57.929809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6164 11:06:57.930272 ==
6165 11:06:57.932811 RX Vref Scan: 1
6166 11:06:57.933276
6167 11:06:57.936042 RX Vref 0 -> 0, step: 1
6168 11:06:57.936529
6169 11:06:57.937033 RX Delay -359 -> 252, step: 8
6170 11:06:57.937521
6171 11:06:57.939533 Set Vref, RX VrefLevel [Byte0]: 51
6172 11:06:57.942648 [Byte1]: 45
6173 11:06:57.947843
6174 11:06:57.948265 Final RX Vref Byte 0 = 51 to rank0
6175 11:06:57.951242 Final RX Vref Byte 1 = 45 to rank0
6176 11:06:57.954494 Final RX Vref Byte 0 = 51 to rank1
6177 11:06:57.957870 Final RX Vref Byte 1 = 45 to rank1==
6178 11:06:57.961678 Dram Type= 6, Freq= 0, CH_0, rank 0
6179 11:06:57.968259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6180 11:06:57.968663 ==
6181 11:06:57.968993 DQS Delay:
6182 11:06:57.971102 DQS0 = 52, DQS1 = 68
6183 11:06:57.971393 DQM Delay:
6184 11:06:57.971620 DQM0 = 9, DQM1 = 17
6185 11:06:57.974411 DQ Delay:
6186 11:06:57.974700 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6187 11:06:57.977624 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6188 11:06:57.981372 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6189 11:06:57.984841 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6190 11:06:57.985129
6191 11:06:57.985448
6192 11:06:57.994705 [DQSOSCAuto] RK0, (LSB)MR18= 0xb8b8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6193 11:06:57.997591 CH0 RK0: MR19=C0C, MR18=B8B8
6194 11:06:58.004382 CH0_RK0: MR19=0xC0C, MR18=0xB8B8, DQSOSC=386, MR23=63, INC=396, DEC=264
6195 11:06:58.004765 ==
6196 11:06:58.007831 Dram Type= 6, Freq= 0, CH_0, rank 1
6197 11:06:58.011645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6198 11:06:58.012062 ==
6199 11:06:58.014265 [Gating] SW mode calibration
6200 11:06:58.021117 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6201 11:06:58.024535 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6202 11:06:58.031159 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6203 11:06:58.034325 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6204 11:06:58.037733 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6205 11:06:58.044344 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6206 11:06:58.047579 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6207 11:06:58.050999 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6208 11:06:58.057594 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6209 11:06:58.061048 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6210 11:06:58.064171 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6211 11:06:58.067434 Total UI for P1: 0, mck2ui 16
6212 11:06:58.071035 best dqsien dly found for B0: ( 0, 10, 16)
6213 11:06:58.074420 Total UI for P1: 0, mck2ui 16
6214 11:06:58.077321 best dqsien dly found for B1: ( 0, 10, 16)
6215 11:06:58.080656 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6216 11:06:58.084240 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6217 11:06:58.087631
6218 11:06:58.090710 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6219 11:06:58.094264 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6220 11:06:58.097557 [Gating] SW calibration Done
6221 11:06:58.097936 ==
6222 11:06:58.100858 Dram Type= 6, Freq= 0, CH_0, rank 1
6223 11:06:58.104666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6224 11:06:58.105114 ==
6225 11:06:58.105695 RX Vref Scan: 0
6226 11:06:58.107648
6227 11:06:58.108132 RX Vref 0 -> 0, step: 1
6228 11:06:58.108439
6229 11:06:58.110597 RX Delay -410 -> 252, step: 16
6230 11:06:58.114008 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6231 11:06:58.120774 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6232 11:06:58.124487 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6233 11:06:58.128066 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6234 11:06:58.130340 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6235 11:06:58.137584 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6236 11:06:58.140574 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6237 11:06:58.144414 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6238 11:06:58.147419 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6239 11:06:58.153935 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6240 11:06:58.157104 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6241 11:06:58.160503 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6242 11:06:58.163755 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6243 11:06:58.170584 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6244 11:06:58.173676 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6245 11:06:58.177015 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6246 11:06:58.177453 ==
6247 11:06:58.180390 Dram Type= 6, Freq= 0, CH_0, rank 1
6248 11:06:58.187155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6249 11:06:58.187669 ==
6250 11:06:58.188008 DQS Delay:
6251 11:06:58.190383 DQS0 = 51, DQS1 = 59
6252 11:06:58.190854 DQM Delay:
6253 11:06:58.191192 DQM0 = 14, DQM1 = 16
6254 11:06:58.193859 DQ Delay:
6255 11:06:58.196906 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6256 11:06:58.197363 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6257 11:06:58.200761 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6258 11:06:58.203813 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6259 11:06:58.204319
6260 11:06:58.207414
6261 11:06:58.207909 ==
6262 11:06:58.210473 Dram Type= 6, Freq= 0, CH_0, rank 1
6263 11:06:58.214086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6264 11:06:58.214588 ==
6265 11:06:58.214915
6266 11:06:58.215215
6267 11:06:58.217188 TX Vref Scan disable
6268 11:06:58.217723 == TX Byte 0 ==
6269 11:06:58.220707 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6270 11:06:58.226972 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6271 11:06:58.227400 == TX Byte 1 ==
6272 11:06:58.230180 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6273 11:06:58.237054 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6274 11:06:58.237599 ==
6275 11:06:58.240647 Dram Type= 6, Freq= 0, CH_0, rank 1
6276 11:06:58.243438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6277 11:06:58.243865 ==
6278 11:06:58.244193
6279 11:06:58.244511
6280 11:06:58.247412 TX Vref Scan disable
6281 11:06:58.247916 == TX Byte 0 ==
6282 11:06:58.250522 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6283 11:06:58.257467 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6284 11:06:58.257975 == TX Byte 1 ==
6285 11:06:58.260279 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6286 11:06:58.266923 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6287 11:06:58.267478
6288 11:06:58.267816 [DATLAT]
6289 11:06:58.268123 Freq=400, CH0 RK1
6290 11:06:58.268419
6291 11:06:58.269992 DATLAT Default: 0xd
6292 11:06:58.270416 0, 0xFFFF, sum = 0
6293 11:06:58.273508 1, 0xFFFF, sum = 0
6294 11:06:58.277000 2, 0xFFFF, sum = 0
6295 11:06:58.277560 3, 0xFFFF, sum = 0
6296 11:06:58.280101 4, 0xFFFF, sum = 0
6297 11:06:58.280529 5, 0xFFFF, sum = 0
6298 11:06:58.283648 6, 0xFFFF, sum = 0
6299 11:06:58.284158 7, 0xFFFF, sum = 0
6300 11:06:58.286954 8, 0xFFFF, sum = 0
6301 11:06:58.287656 9, 0xFFFF, sum = 0
6302 11:06:58.290374 10, 0xFFFF, sum = 0
6303 11:06:58.290807 11, 0xFFFF, sum = 0
6304 11:06:58.293259 12, 0x0, sum = 1
6305 11:06:58.293691 13, 0x0, sum = 2
6306 11:06:58.296749 14, 0x0, sum = 3
6307 11:06:58.297176 15, 0x0, sum = 4
6308 11:06:58.300189 best_step = 13
6309 11:06:58.300605
6310 11:06:58.300924 ==
6311 11:06:58.303442 Dram Type= 6, Freq= 0, CH_0, rank 1
6312 11:06:58.306664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6313 11:06:58.307086 ==
6314 11:06:58.307409 RX Vref Scan: 0
6315 11:06:58.309897
6316 11:06:58.310313 RX Vref 0 -> 0, step: 1
6317 11:06:58.310637
6318 11:06:58.313104 RX Delay -359 -> 252, step: 8
6319 11:06:58.320695 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6320 11:06:58.323552 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6321 11:06:58.327010 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6322 11:06:58.330443 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6323 11:06:58.336914 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6324 11:06:58.340283 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6325 11:06:58.343485 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6326 11:06:58.350485 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6327 11:06:58.353765 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6328 11:06:58.357385 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6329 11:06:58.360284 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6330 11:06:58.366996 iDelay=217, Bit 11, Center -60 (-295 ~ 176) 472
6331 11:06:58.370366 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6332 11:06:58.373819 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6333 11:06:58.376870 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6334 11:06:58.383715 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6335 11:06:58.384095 ==
6336 11:06:58.386748 Dram Type= 6, Freq= 0, CH_0, rank 1
6337 11:06:58.390301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6338 11:06:58.390688 ==
6339 11:06:58.390982 DQS Delay:
6340 11:06:58.393638 DQS0 = 52, DQS1 = 64
6341 11:06:58.394014 DQM Delay:
6342 11:06:58.396962 DQM0 = 11, DQM1 = 13
6343 11:06:58.397406 DQ Delay:
6344 11:06:58.400191 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6345 11:06:58.403586 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6346 11:06:58.406994 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6347 11:06:58.410087 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6348 11:06:58.410542
6349 11:06:58.410839
6350 11:06:58.416627 [DQSOSCAuto] RK1, (LSB)MR18= 0xc4c4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6351 11:06:58.420387 CH0 RK1: MR19=C0C, MR18=C4C4
6352 11:06:58.426652 CH0_RK1: MR19=0xC0C, MR18=0xC4C4, DQSOSC=385, MR23=63, INC=398, DEC=265
6353 11:06:58.430017 [RxdqsGatingPostProcess] freq 400
6354 11:06:58.437196 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6355 11:06:58.437663 Pre-setting of DQS Precalculation
6356 11:06:58.443078 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6357 11:06:58.443532 ==
6358 11:06:58.446862 Dram Type= 6, Freq= 0, CH_1, rank 0
6359 11:06:58.450365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6360 11:06:58.450831 ==
6361 11:06:58.456701 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6362 11:06:58.463193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6363 11:06:58.466475 [CA 0] Center 36 (8~64) winsize 57
6364 11:06:58.469846 [CA 1] Center 36 (8~64) winsize 57
6365 11:06:58.473151 [CA 2] Center 36 (8~64) winsize 57
6366 11:06:58.476580 [CA 3] Center 36 (8~64) winsize 57
6367 11:06:58.477041 [CA 4] Center 36 (8~64) winsize 57
6368 11:06:58.479742 [CA 5] Center 36 (8~64) winsize 57
6369 11:06:58.480249
6370 11:06:58.486623 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6371 11:06:58.487128
6372 11:06:58.489919 [CATrainingPosCal] consider 1 rank data
6373 11:06:58.493095 u2DelayCellTimex100 = 270/100 ps
6374 11:06:58.496562 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 11:06:58.500018 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 11:06:58.503306 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 11:06:58.506102 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 11:06:58.509835 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 11:06:58.513058 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6380 11:06:58.513638
6381 11:06:58.516352 CA PerBit enable=1, Macro0, CA PI delay=36
6382 11:06:58.516843
6383 11:06:58.519529 [CBTSetCACLKResult] CA Dly = 36
6384 11:06:58.523066 CS Dly: 1 (0~32)
6385 11:06:58.523571 ==
6386 11:06:58.526221 Dram Type= 6, Freq= 0, CH_1, rank 1
6387 11:06:58.529574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6388 11:06:58.529996 ==
6389 11:06:58.536144 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6390 11:06:58.542800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6391 11:06:58.543239 [CA 0] Center 36 (8~64) winsize 57
6392 11:06:58.546355 [CA 1] Center 36 (8~64) winsize 57
6393 11:06:58.549339 [CA 2] Center 36 (8~64) winsize 57
6394 11:06:58.552929 [CA 3] Center 36 (8~64) winsize 57
6395 11:06:58.556108 [CA 4] Center 36 (8~64) winsize 57
6396 11:06:58.559405 [CA 5] Center 36 (8~64) winsize 57
6397 11:06:58.559836
6398 11:06:58.562893 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6399 11:06:58.563316
6400 11:06:58.566254 [CATrainingPosCal] consider 2 rank data
6401 11:06:58.569353 u2DelayCellTimex100 = 270/100 ps
6402 11:06:58.572927 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 11:06:58.579163 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 11:06:58.582951 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 11:06:58.585926 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 11:06:58.589221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 11:06:58.592871 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 11:06:58.593341
6409 11:06:58.596018 CA PerBit enable=1, Macro0, CA PI delay=36
6410 11:06:58.596484
6411 11:06:58.599349 [CBTSetCACLKResult] CA Dly = 36
6412 11:06:58.599884 CS Dly: 1 (0~32)
6413 11:06:58.602830
6414 11:06:58.605864 ----->DramcWriteLeveling(PI) begin...
6415 11:06:58.606298 ==
6416 11:06:58.609479 Dram Type= 6, Freq= 0, CH_1, rank 0
6417 11:06:58.613087 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6418 11:06:58.613640 ==
6419 11:06:58.615830 Write leveling (Byte 0): 32 => 0
6420 11:06:58.619400 Write leveling (Byte 1): 32 => 0
6421 11:06:58.622265 DramcWriteLeveling(PI) end<-----
6422 11:06:58.622695
6423 11:06:58.623023 ==
6424 11:06:58.625598 Dram Type= 6, Freq= 0, CH_1, rank 0
6425 11:06:58.629379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6426 11:06:58.629865 ==
6427 11:06:58.632356 [Gating] SW mode calibration
6428 11:06:58.638861 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 11:06:58.645632 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6430 11:06:58.649358 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 11:06:58.652571 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 11:06:58.655747 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 11:06:58.662299 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6434 11:06:58.665552 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 11:06:58.668935 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 11:06:58.675822 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 11:06:58.678891 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6438 11:06:58.682173 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 11:06:58.685680 Total UI for P1: 0, mck2ui 16
6440 11:06:58.688801 best dqsien dly found for B0: ( 0, 10, 16)
6441 11:06:58.692180 Total UI for P1: 0, mck2ui 16
6442 11:06:58.695301 best dqsien dly found for B1: ( 0, 10, 16)
6443 11:06:58.698482 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6444 11:06:58.702070 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6445 11:06:58.705218
6446 11:06:58.709293 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6447 11:06:58.712063 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6448 11:06:58.715496 [Gating] SW calibration Done
6449 11:06:58.715925 ==
6450 11:06:58.718933 Dram Type= 6, Freq= 0, CH_1, rank 0
6451 11:06:58.722097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6452 11:06:58.722529 ==
6453 11:06:58.725054 RX Vref Scan: 0
6454 11:06:58.725522
6455 11:06:58.725854 RX Vref 0 -> 0, step: 1
6456 11:06:58.726161
6457 11:06:58.728443 RX Delay -410 -> 252, step: 16
6458 11:06:58.731676 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6459 11:06:58.738512 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6460 11:06:58.741629 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6461 11:06:58.745357 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6462 11:06:58.748455 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6463 11:06:58.754769 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6464 11:06:58.758595 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6465 11:06:58.761553 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6466 11:06:58.765073 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6467 11:06:58.771706 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6468 11:06:58.774881 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6469 11:06:58.778445 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6470 11:06:58.781876 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6471 11:06:58.788438 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6472 11:06:58.791587 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6473 11:06:58.795379 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6474 11:06:58.795798 ==
6475 11:06:58.798393 Dram Type= 6, Freq= 0, CH_1, rank 0
6476 11:06:58.805072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6477 11:06:58.805527 ==
6478 11:06:58.805856 DQS Delay:
6479 11:06:58.808536 DQS0 = 43, DQS1 = 59
6480 11:06:58.808954 DQM Delay:
6481 11:06:58.809319 DQM0 = 6, DQM1 = 14
6482 11:06:58.811863 DQ Delay:
6483 11:06:58.815226 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6484 11:06:58.815648 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6485 11:06:58.818275 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6486 11:06:58.821968 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =32
6487 11:06:58.822437
6488 11:06:58.822780
6489 11:06:58.824892 ==
6490 11:06:58.825375 Dram Type= 6, Freq= 0, CH_1, rank 0
6491 11:06:58.831714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6492 11:06:58.832211 ==
6493 11:06:58.832547
6494 11:06:58.832852
6495 11:06:58.834874 TX Vref Scan disable
6496 11:06:58.835314 == TX Byte 0 ==
6497 11:06:58.838099 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6498 11:06:58.844586 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6499 11:06:58.844970 == TX Byte 1 ==
6500 11:06:58.848077 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6501 11:06:58.854517 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6502 11:06:58.854941 ==
6503 11:06:58.858015 Dram Type= 6, Freq= 0, CH_1, rank 0
6504 11:06:58.861808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6505 11:06:58.862237 ==
6506 11:06:58.862547
6507 11:06:58.862820
6508 11:06:58.864449 TX Vref Scan disable
6509 11:06:58.864827 == TX Byte 0 ==
6510 11:06:58.871150 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6511 11:06:58.874443 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6512 11:06:58.874826 == TX Byte 1 ==
6513 11:06:58.880955 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6514 11:06:58.884399 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6515 11:06:58.884844
6516 11:06:58.885141 [DATLAT]
6517 11:06:58.887753 Freq=400, CH1 RK0
6518 11:06:58.888178
6519 11:06:58.888472 DATLAT Default: 0xf
6520 11:06:58.891243 0, 0xFFFF, sum = 0
6521 11:06:58.891632 1, 0xFFFF, sum = 0
6522 11:06:58.894376 2, 0xFFFF, sum = 0
6523 11:06:58.894760 3, 0xFFFF, sum = 0
6524 11:06:58.898060 4, 0xFFFF, sum = 0
6525 11:06:58.898499 5, 0xFFFF, sum = 0
6526 11:06:58.900826 6, 0xFFFF, sum = 0
6527 11:06:58.901211 7, 0xFFFF, sum = 0
6528 11:06:58.904345 8, 0xFFFF, sum = 0
6529 11:06:58.904810 9, 0xFFFF, sum = 0
6530 11:06:58.907614 10, 0xFFFF, sum = 0
6531 11:06:58.911178 11, 0xFFFF, sum = 0
6532 11:06:58.911619 12, 0x0, sum = 1
6533 11:06:58.911923 13, 0x0, sum = 2
6534 11:06:58.914471 14, 0x0, sum = 3
6535 11:06:58.914854 15, 0x0, sum = 4
6536 11:06:58.917798 best_step = 13
6537 11:06:58.918177
6538 11:06:58.918469 ==
6539 11:06:58.921328 Dram Type= 6, Freq= 0, CH_1, rank 0
6540 11:06:58.924328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6541 11:06:58.924807 ==
6542 11:06:58.927629 RX Vref Scan: 1
6543 11:06:58.928004
6544 11:06:58.928342 RX Vref 0 -> 0, step: 1
6545 11:06:58.928673
6546 11:06:58.930928 RX Delay -359 -> 252, step: 8
6547 11:06:58.931307
6548 11:06:58.934291 Set Vref, RX VrefLevel [Byte0]: 52
6549 11:06:58.937375 [Byte1]: 48
6550 11:06:58.942630
6551 11:06:58.943116 Final RX Vref Byte 0 = 52 to rank0
6552 11:06:58.945861 Final RX Vref Byte 1 = 48 to rank0
6553 11:06:58.949344 Final RX Vref Byte 0 = 52 to rank1
6554 11:06:58.952357 Final RX Vref Byte 1 = 48 to rank1==
6555 11:06:58.955793 Dram Type= 6, Freq= 0, CH_1, rank 0
6556 11:06:58.962562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6557 11:06:58.963000 ==
6558 11:06:58.963528 DQS Delay:
6559 11:06:58.965726 DQS0 = 48, DQS1 = 68
6560 11:06:58.966106 DQM Delay:
6561 11:06:58.966404 DQM0 = 8, DQM1 = 20
6562 11:06:58.969174 DQ Delay:
6563 11:06:58.972499 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6564 11:06:58.972882 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6565 11:06:58.975654 DQ8 =0, DQ9 =12, DQ10 =24, DQ11 =12
6566 11:06:58.979394 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =28
6567 11:06:58.979778
6568 11:06:58.982575
6569 11:06:58.989402 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5e5, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6570 11:06:58.992375 CH1 RK0: MR19=C0C, MR18=E5E5
6571 11:06:58.998922 CH1_RK0: MR19=0xC0C, MR18=0xE5E5, DQSOSC=381, MR23=63, INC=406, DEC=271
6572 11:06:58.999328 ==
6573 11:06:59.002166 Dram Type= 6, Freq= 0, CH_1, rank 1
6574 11:06:59.005577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6575 11:06:59.005973 ==
6576 11:06:59.008598 [Gating] SW mode calibration
6577 11:06:59.015323 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6578 11:06:59.022279 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6579 11:06:59.025500 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6580 11:06:59.028783 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6581 11:06:59.035526 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6582 11:06:59.038622 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6583 11:06:59.042086 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6584 11:06:59.045700 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6585 11:06:59.052160 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6586 11:06:59.055389 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6587 11:06:59.058655 Total UI for P1: 0, mck2ui 16
6588 11:06:59.062025 best dqsien dly found for B0: ( 0, 10, 8)
6589 11:06:59.065157 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6590 11:06:59.068618 Total UI for P1: 0, mck2ui 16
6591 11:06:59.071907 best dqsien dly found for B1: ( 0, 10, 16)
6592 11:06:59.075348 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6593 11:06:59.081621 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6594 11:06:59.082057
6595 11:06:59.085384 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6596 11:06:59.088679 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6597 11:06:59.091758 [Gating] SW calibration Done
6598 11:06:59.092180 ==
6599 11:06:59.095134 Dram Type= 6, Freq= 0, CH_1, rank 1
6600 11:06:59.098774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6601 11:06:59.099209 ==
6602 11:06:59.101838 RX Vref Scan: 0
6603 11:06:59.102380
6604 11:06:59.102903 RX Vref 0 -> 0, step: 1
6605 11:06:59.103240
6606 11:06:59.104849 RX Delay -410 -> 252, step: 16
6607 11:06:59.108503 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6608 11:06:59.115088 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6609 11:06:59.118357 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6610 11:06:59.121703 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6611 11:06:59.125081 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6612 11:06:59.131571 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6613 11:06:59.134860 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6614 11:06:59.137873 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6615 11:06:59.141503 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6616 11:06:59.148111 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6617 11:06:59.151835 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6618 11:06:59.154772 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6619 11:06:59.157891 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6620 11:06:59.164985 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6621 11:06:59.168767 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6622 11:06:59.171701 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6623 11:06:59.172121 ==
6624 11:06:59.174992 Dram Type= 6, Freq= 0, CH_1, rank 1
6625 11:06:59.181605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6626 11:06:59.182073 ==
6627 11:06:59.182398 DQS Delay:
6628 11:06:59.185031 DQS0 = 43, DQS1 = 59
6629 11:06:59.185550 DQM Delay:
6630 11:06:59.185880 DQM0 = 9, DQM1 = 18
6631 11:06:59.188350 DQ Delay:
6632 11:06:59.191528 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6633 11:06:59.191949 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6634 11:06:59.194917 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6635 11:06:59.198322 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6636 11:06:59.198743
6637 11:06:59.199072
6638 11:06:59.201377 ==
6639 11:06:59.204745 Dram Type= 6, Freq= 0, CH_1, rank 1
6640 11:06:59.208286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6641 11:06:59.208837 ==
6642 11:06:59.209173
6643 11:06:59.209519
6644 11:06:59.212073 TX Vref Scan disable
6645 11:06:59.212651 == TX Byte 0 ==
6646 11:06:59.214731 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6647 11:06:59.218095 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6648 11:06:59.221327 == TX Byte 1 ==
6649 11:06:59.225187 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6650 11:06:59.228351 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6651 11:06:59.231318 ==
6652 11:06:59.234692 Dram Type= 6, Freq= 0, CH_1, rank 1
6653 11:06:59.237875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6654 11:06:59.238357 ==
6655 11:06:59.238689
6656 11:06:59.239165
6657 11:06:59.241255 TX Vref Scan disable
6658 11:06:59.241685 == TX Byte 0 ==
6659 11:06:59.244670 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6660 11:06:59.251005 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6661 11:06:59.251428 == TX Byte 1 ==
6662 11:06:59.254302 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6663 11:06:59.261159 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6664 11:06:59.261581
6665 11:06:59.261878 [DATLAT]
6666 11:06:59.262149 Freq=400, CH1 RK1
6667 11:06:59.262414
6668 11:06:59.264318 DATLAT Default: 0xd
6669 11:06:59.264701 0, 0xFFFF, sum = 0
6670 11:06:59.267725 1, 0xFFFF, sum = 0
6671 11:06:59.270977 2, 0xFFFF, sum = 0
6672 11:06:59.271360 3, 0xFFFF, sum = 0
6673 11:06:59.274599 4, 0xFFFF, sum = 0
6674 11:06:59.274984 5, 0xFFFF, sum = 0
6675 11:06:59.277540 6, 0xFFFF, sum = 0
6676 11:06:59.277927 7, 0xFFFF, sum = 0
6677 11:06:59.281294 8, 0xFFFF, sum = 0
6678 11:06:59.281721 9, 0xFFFF, sum = 0
6679 11:06:59.284201 10, 0xFFFF, sum = 0
6680 11:06:59.284585 11, 0xFFFF, sum = 0
6681 11:06:59.287525 12, 0x0, sum = 1
6682 11:06:59.288075 13, 0x0, sum = 2
6683 11:06:59.290868 14, 0x0, sum = 3
6684 11:06:59.291254 15, 0x0, sum = 4
6685 11:06:59.291551 best_step = 13
6686 11:06:59.294183
6687 11:06:59.294557 ==
6688 11:06:59.297492 Dram Type= 6, Freq= 0, CH_1, rank 1
6689 11:06:59.300680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6690 11:06:59.301057 ==
6691 11:06:59.301396 RX Vref Scan: 0
6692 11:06:59.301672
6693 11:06:59.304091 RX Vref 0 -> 0, step: 1
6694 11:06:59.304469
6695 11:06:59.307535 RX Delay -359 -> 252, step: 8
6696 11:06:59.315151 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6697 11:06:59.318226 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6698 11:06:59.321435 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6699 11:06:59.324823 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6700 11:06:59.332049 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6701 11:06:59.334735 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6702 11:06:59.338188 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6703 11:06:59.341353 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6704 11:06:59.348045 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6705 11:06:59.351226 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6706 11:06:59.354718 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6707 11:06:59.357839 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6708 11:06:59.364671 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6709 11:06:59.367963 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6710 11:06:59.371385 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6711 11:06:59.378229 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6712 11:06:59.378628 ==
6713 11:06:59.381672 Dram Type= 6, Freq= 0, CH_1, rank 1
6714 11:06:59.384434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6715 11:06:59.384822 ==
6716 11:06:59.385121 DQS Delay:
6717 11:06:59.387978 DQS0 = 48, DQS1 = 64
6718 11:06:59.388362 DQM Delay:
6719 11:06:59.391671 DQM0 = 9, DQM1 = 15
6720 11:06:59.392151 DQ Delay:
6721 11:06:59.394405 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6722 11:06:59.397776 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6723 11:06:59.401357 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6724 11:06:59.404458 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6725 11:06:59.404846
6726 11:06:59.405140
6727 11:06:59.411364 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6728 11:06:59.414236 CH1 RK1: MR19=C0C, MR18=B0B0
6729 11:06:59.421323 CH1_RK1: MR19=0xC0C, MR18=0xB0B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6730 11:06:59.424255 [RxdqsGatingPostProcess] freq 400
6731 11:06:59.428184 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6732 11:06:59.431017 Pre-setting of DQS Precalculation
6733 11:06:59.437665 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6734 11:06:59.444045 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6735 11:06:59.451099 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6736 11:06:59.451538
6737 11:06:59.451834
6738 11:06:59.454171 [Calibration Summary] 800 Mbps
6739 11:06:59.457787 CH 0, Rank 0
6740 11:06:59.458168 SW Impedance : PASS
6741 11:06:59.460991 DUTY Scan : NO K
6742 11:06:59.461435 ZQ Calibration : PASS
6743 11:06:59.464223 Jitter Meter : NO K
6744 11:06:59.467601 CBT Training : PASS
6745 11:06:59.467984 Write leveling : PASS
6746 11:06:59.470757 RX DQS gating : PASS
6747 11:06:59.474369 RX DQ/DQS(RDDQC) : PASS
6748 11:06:59.474756 TX DQ/DQS : PASS
6749 11:06:59.477573 RX DATLAT : PASS
6750 11:06:59.480788 RX DQ/DQS(Engine): PASS
6751 11:06:59.481171 TX OE : NO K
6752 11:06:59.484137 All Pass.
6753 11:06:59.484516
6754 11:06:59.484808 CH 0, Rank 1
6755 11:06:59.487496 SW Impedance : PASS
6756 11:06:59.487881 DUTY Scan : NO K
6757 11:06:59.491176 ZQ Calibration : PASS
6758 11:06:59.494307 Jitter Meter : NO K
6759 11:06:59.494696 CBT Training : PASS
6760 11:06:59.497339 Write leveling : NO K
6761 11:06:59.500772 RX DQS gating : PASS
6762 11:06:59.501155 RX DQ/DQS(RDDQC) : PASS
6763 11:06:59.503983 TX DQ/DQS : PASS
6764 11:06:59.504351 RX DATLAT : PASS
6765 11:06:59.507369 RX DQ/DQS(Engine): PASS
6766 11:06:59.510616 TX OE : NO K
6767 11:06:59.511001 All Pass.
6768 11:06:59.511297
6769 11:06:59.511573 CH 1, Rank 0
6770 11:06:59.513889 SW Impedance : PASS
6771 11:06:59.517617 DUTY Scan : NO K
6772 11:06:59.518053 ZQ Calibration : PASS
6773 11:06:59.520579 Jitter Meter : NO K
6774 11:06:59.523966 CBT Training : PASS
6775 11:06:59.524425 Write leveling : PASS
6776 11:06:59.527183 RX DQS gating : PASS
6777 11:06:59.530444 RX DQ/DQS(RDDQC) : PASS
6778 11:06:59.530828 TX DQ/DQS : PASS
6779 11:06:59.534077 RX DATLAT : PASS
6780 11:06:59.537325 RX DQ/DQS(Engine): PASS
6781 11:06:59.537704 TX OE : NO K
6782 11:06:59.540699 All Pass.
6783 11:06:59.541081
6784 11:06:59.541430 CH 1, Rank 1
6785 11:06:59.544194 SW Impedance : PASS
6786 11:06:59.544621 DUTY Scan : NO K
6787 11:06:59.547030 ZQ Calibration : PASS
6788 11:06:59.550413 Jitter Meter : NO K
6789 11:06:59.550885 CBT Training : PASS
6790 11:06:59.553806 Write leveling : NO K
6791 11:06:59.557001 RX DQS gating : PASS
6792 11:06:59.557521 RX DQ/DQS(RDDQC) : PASS
6793 11:06:59.560187 TX DQ/DQS : PASS
6794 11:06:59.560797 RX DATLAT : PASS
6795 11:06:59.563822 RX DQ/DQS(Engine): PASS
6796 11:06:59.567197 TX OE : NO K
6797 11:06:59.567586 All Pass.
6798 11:06:59.567882
6799 11:06:59.570395 DramC Write-DBI off
6800 11:06:59.573682 PER_BANK_REFRESH: Hybrid Mode
6801 11:06:59.574213 TX_TRACKING: ON
6802 11:06:59.583552 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6803 11:06:59.586751 [FAST_K] Save calibration result to emmc
6804 11:06:59.590121 dramc_set_vcore_voltage set vcore to 725000
6805 11:06:59.593515 Read voltage for 1600, 0
6806 11:06:59.593904 Vio18 = 0
6807 11:06:59.594204 Vcore = 725000
6808 11:06:59.596895 Vdram = 0
6809 11:06:59.597417 Vddq = 0
6810 11:06:59.597724 Vmddr = 0
6811 11:06:59.603514 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6812 11:06:59.606740 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6813 11:06:59.610168 MEM_TYPE=3, freq_sel=13
6814 11:06:59.613869 sv_algorithm_assistance_LP4_3733
6815 11:06:59.616747 ============ PULL DRAM RESETB DOWN ============
6816 11:06:59.620078 ========== PULL DRAM RESETB DOWN end =========
6817 11:06:59.626532 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6818 11:06:59.629778 ===================================
6819 11:06:59.630228 LPDDR4 DRAM CONFIGURATION
6820 11:06:59.633413 ===================================
6821 11:06:59.636552 EX_ROW_EN[0] = 0x0
6822 11:06:59.640040 EX_ROW_EN[1] = 0x0
6823 11:06:59.640502 LP4Y_EN = 0x0
6824 11:06:59.643374 WORK_FSP = 0x1
6825 11:06:59.643868 WL = 0x5
6826 11:06:59.646645 RL = 0x5
6827 11:06:59.647080 BL = 0x2
6828 11:06:59.650433 RPST = 0x0
6829 11:06:59.650898 RD_PRE = 0x0
6830 11:06:59.653350 WR_PRE = 0x1
6831 11:06:59.653817 WR_PST = 0x1
6832 11:06:59.656682 DBI_WR = 0x0
6833 11:06:59.657083 DBI_RD = 0x0
6834 11:06:59.660011 OTF = 0x1
6835 11:06:59.663439 ===================================
6836 11:06:59.666417 ===================================
6837 11:06:59.666836 ANA top config
6838 11:06:59.669739 ===================================
6839 11:06:59.673359 DLL_ASYNC_EN = 0
6840 11:06:59.676424 ALL_SLAVE_EN = 0
6841 11:06:59.679570 NEW_RANK_MODE = 1
6842 11:06:59.679989 DLL_IDLE_MODE = 1
6843 11:06:59.682968 LP45_APHY_COMB_EN = 1
6844 11:06:59.686413 TX_ODT_DIS = 0
6845 11:06:59.690074 NEW_8X_MODE = 1
6846 11:06:59.693388 ===================================
6847 11:06:59.696242 ===================================
6848 11:06:59.699513 data_rate = 3200
6849 11:06:59.699728 CKR = 1
6850 11:06:59.702509 DQ_P2S_RATIO = 8
6851 11:06:59.706175 ===================================
6852 11:06:59.709438 CA_P2S_RATIO = 8
6853 11:06:59.712831 DQ_CA_OPEN = 0
6854 11:06:59.716023 DQ_SEMI_OPEN = 0
6855 11:06:59.719461 CA_SEMI_OPEN = 0
6856 11:06:59.719753 CA_FULL_RATE = 0
6857 11:06:59.722768 DQ_CKDIV4_EN = 0
6858 11:06:59.726257 CA_CKDIV4_EN = 0
6859 11:06:59.729686 CA_PREDIV_EN = 0
6860 11:06:59.733350 PH8_DLY = 12
6861 11:06:59.733691 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6862 11:06:59.736549 DQ_AAMCK_DIV = 4
6863 11:06:59.739652 CA_AAMCK_DIV = 4
6864 11:06:59.742866 CA_ADMCK_DIV = 4
6865 11:06:59.746197 DQ_TRACK_CA_EN = 0
6866 11:06:59.749746 CA_PICK = 1600
6867 11:06:59.752998 CA_MCKIO = 1600
6868 11:06:59.753632 MCKIO_SEMI = 0
6869 11:06:59.756319 PLL_FREQ = 3068
6870 11:06:59.759627 DQ_UI_PI_RATIO = 32
6871 11:06:59.763165 CA_UI_PI_RATIO = 0
6872 11:06:59.766241 ===================================
6873 11:06:59.769366 ===================================
6874 11:06:59.772930 memory_type:LPDDR4
6875 11:06:59.773569 GP_NUM : 10
6876 11:06:59.776036 SRAM_EN : 1
6877 11:06:59.779593 MD32_EN : 0
6878 11:06:59.782885 ===================================
6879 11:06:59.783481 [ANA_INIT] >>>>>>>>>>>>>>
6880 11:06:59.785871 <<<<<< [CONFIGURE PHASE]: ANA_TX
6881 11:06:59.789409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6882 11:06:59.792766 ===================================
6883 11:06:59.796051 data_rate = 3200,PCW = 0X7600
6884 11:06:59.798918 ===================================
6885 11:06:59.802353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6886 11:06:59.809126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6887 11:06:59.812398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6888 11:06:59.819246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6889 11:06:59.823270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6890 11:06:59.825514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6891 11:06:59.829198 [ANA_INIT] flow start
6892 11:06:59.829655 [ANA_INIT] PLL >>>>>>>>
6893 11:06:59.832308 [ANA_INIT] PLL <<<<<<<<
6894 11:06:59.836024 [ANA_INIT] MIDPI >>>>>>>>
6895 11:06:59.836526 [ANA_INIT] MIDPI <<<<<<<<
6896 11:06:59.838999 [ANA_INIT] DLL >>>>>>>>
6897 11:06:59.842386 [ANA_INIT] DLL <<<<<<<<
6898 11:06:59.842811 [ANA_INIT] flow end
6899 11:06:59.845923 ============ LP4 DIFF to SE enter ============
6900 11:06:59.852264 ============ LP4 DIFF to SE exit ============
6901 11:06:59.852738 [ANA_INIT] <<<<<<<<<<<<<
6902 11:06:59.855393 [Flow] Enable top DCM control >>>>>
6903 11:06:59.858852 [Flow] Enable top DCM control <<<<<
6904 11:06:59.862007 Enable DLL master slave shuffle
6905 11:06:59.868611 ==============================================================
6906 11:06:59.871912 Gating Mode config
6907 11:06:59.875370 ==============================================================
6908 11:06:59.878498 Config description:
6909 11:06:59.888865 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6910 11:06:59.895458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6911 11:06:59.898430 SELPH_MODE 0: By rank 1: By Phase
6912 11:06:59.905042 ==============================================================
6913 11:06:59.908560 GAT_TRACK_EN = 1
6914 11:06:59.912200 RX_GATING_MODE = 2
6915 11:06:59.915256 RX_GATING_TRACK_MODE = 2
6916 11:06:59.915685 SELPH_MODE = 1
6917 11:06:59.918336 PICG_EARLY_EN = 1
6918 11:06:59.922406 VALID_LAT_VALUE = 1
6919 11:06:59.928550 ==============================================================
6920 11:06:59.932054 Enter into Gating configuration >>>>
6921 11:06:59.935215 Exit from Gating configuration <<<<
6922 11:06:59.938439 Enter into DVFS_PRE_config >>>>>
6923 11:06:59.948470 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6924 11:06:59.951891 Exit from DVFS_PRE_config <<<<<
6925 11:06:59.955019 Enter into PICG configuration >>>>
6926 11:06:59.958313 Exit from PICG configuration <<<<
6927 11:06:59.961799 [RX_INPUT] configuration >>>>>
6928 11:06:59.964887 [RX_INPUT] configuration <<<<<
6929 11:06:59.968137 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6930 11:06:59.974871 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6931 11:06:59.981396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6932 11:06:59.988153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6933 11:06:59.991441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6934 11:06:59.998039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6935 11:07:00.004663 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6936 11:07:00.007953 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6937 11:07:00.011341 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6938 11:07:00.014781 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6939 11:07:00.017869 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6940 11:07:00.024340 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6941 11:07:00.028004 ===================================
6942 11:07:00.031126 LPDDR4 DRAM CONFIGURATION
6943 11:07:00.034628 ===================================
6944 11:07:00.035071 EX_ROW_EN[0] = 0x0
6945 11:07:00.037976 EX_ROW_EN[1] = 0x0
6946 11:07:00.038414 LP4Y_EN = 0x0
6947 11:07:00.040950 WORK_FSP = 0x1
6948 11:07:00.041439 WL = 0x5
6949 11:07:00.044283 RL = 0x5
6950 11:07:00.044718 BL = 0x2
6951 11:07:00.047981 RPST = 0x0
6952 11:07:00.048421 RD_PRE = 0x0
6953 11:07:00.051091 WR_PRE = 0x1
6954 11:07:00.051583 WR_PST = 0x1
6955 11:07:00.054313 DBI_WR = 0x0
6956 11:07:00.054754 DBI_RD = 0x0
6957 11:07:00.057733 OTF = 0x1
6958 11:07:00.060792 ===================================
6959 11:07:00.064560 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6960 11:07:00.067746 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6961 11:07:00.074405 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6962 11:07:00.077754 ===================================
6963 11:07:00.078266 LPDDR4 DRAM CONFIGURATION
6964 11:07:00.080799 ===================================
6965 11:07:00.084033 EX_ROW_EN[0] = 0x10
6966 11:07:00.087625 EX_ROW_EN[1] = 0x0
6967 11:07:00.088064 LP4Y_EN = 0x0
6968 11:07:00.090665 WORK_FSP = 0x1
6969 11:07:00.091093 WL = 0x5
6970 11:07:00.094010 RL = 0x5
6971 11:07:00.094436 BL = 0x2
6972 11:07:00.097500 RPST = 0x0
6973 11:07:00.097934 RD_PRE = 0x0
6974 11:07:00.100835 WR_PRE = 0x1
6975 11:07:00.101494 WR_PST = 0x1
6976 11:07:00.104364 DBI_WR = 0x0
6977 11:07:00.104789 DBI_RD = 0x0
6978 11:07:00.107464 OTF = 0x1
6979 11:07:00.111213 ===================================
6980 11:07:00.117764 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6981 11:07:00.118362 ==
6982 11:07:00.120793 Dram Type= 6, Freq= 0, CH_0, rank 0
6983 11:07:00.123965 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6984 11:07:00.124550 ==
6985 11:07:00.127197 [Duty_Offset_Calibration]
6986 11:07:00.127654 B0:0 B1:2 CA:1
6987 11:07:00.127985
6988 11:07:00.130632 [DutyScan_Calibration_Flow] k_type=0
6989 11:07:00.141805
6990 11:07:00.142281 ==CLK 0==
6991 11:07:00.145103 Final CLK duty delay cell = 0
6992 11:07:00.148274 [0] MAX Duty = 5156%(X100), DQS PI = 22
6993 11:07:00.151656 [0] MIN Duty = 4938%(X100), DQS PI = 50
6994 11:07:00.152134 [0] AVG Duty = 5047%(X100)
6995 11:07:00.155110
6996 11:07:00.158182 CH0 CLK Duty spec in!! Max-Min= 218%
6997 11:07:00.161643 [DutyScan_Calibration_Flow] ====Done====
6998 11:07:00.162120
6999 11:07:00.164694 [DutyScan_Calibration_Flow] k_type=1
7000 11:07:00.181361
7001 11:07:00.181833 ==DQS 0 ==
7002 11:07:00.184977 Final DQS duty delay cell = 0
7003 11:07:00.188454 [0] MAX Duty = 5156%(X100), DQS PI = 34
7004 11:07:00.191821 [0] MIN Duty = 5000%(X100), DQS PI = 10
7005 11:07:00.195081 [0] AVG Duty = 5078%(X100)
7006 11:07:00.195507
7007 11:07:00.195834 ==DQS 1 ==
7008 11:07:00.198091 Final DQS duty delay cell = 0
7009 11:07:00.201390 [0] MAX Duty = 5031%(X100), DQS PI = 46
7010 11:07:00.204969 [0] MIN Duty = 4876%(X100), DQS PI = 16
7011 11:07:00.208074 [0] AVG Duty = 4953%(X100)
7012 11:07:00.208651
7013 11:07:00.211475 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7014 11:07:00.212097
7015 11:07:00.214992 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7016 11:07:00.218729 [DutyScan_Calibration_Flow] ====Done====
7017 11:07:00.219130
7018 11:07:00.221661 [DutyScan_Calibration_Flow] k_type=3
7019 11:07:00.238955
7020 11:07:00.239539 ==DQM 0 ==
7021 11:07:00.241898 Final DQM duty delay cell = 0
7022 11:07:00.245646 [0] MAX Duty = 5187%(X100), DQS PI = 24
7023 11:07:00.248910 [0] MIN Duty = 4907%(X100), DQS PI = 42
7024 11:07:00.252081 [0] AVG Duty = 5047%(X100)
7025 11:07:00.252665
7026 11:07:00.253197 ==DQM 1 ==
7027 11:07:00.255176 Final DQM duty delay cell = 0
7028 11:07:00.258697 [0] MAX Duty = 5031%(X100), DQS PI = 52
7029 11:07:00.261838 [0] MIN Duty = 4782%(X100), DQS PI = 14
7030 11:07:00.265270 [0] AVG Duty = 4906%(X100)
7031 11:07:00.265866
7032 11:07:00.268537 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7033 11:07:00.269118
7034 11:07:00.272115 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7035 11:07:00.275370 [DutyScan_Calibration_Flow] ====Done====
7036 11:07:00.275917
7037 11:07:00.278454 [DutyScan_Calibration_Flow] k_type=2
7038 11:07:00.295184
7039 11:07:00.295779 ==DQ 0 ==
7040 11:07:00.298547 Final DQ duty delay cell = 0
7041 11:07:00.301765 [0] MAX Duty = 5187%(X100), DQS PI = 18
7042 11:07:00.305130 [0] MIN Duty = 4938%(X100), DQS PI = 56
7043 11:07:00.305743 [0] AVG Duty = 5062%(X100)
7044 11:07:00.308374
7045 11:07:00.308953 ==DQ 1 ==
7046 11:07:00.311938 Final DQ duty delay cell = -4
7047 11:07:00.315148 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7048 11:07:00.318383 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7049 11:07:00.321733 [-4] AVG Duty = 4953%(X100)
7050 11:07:00.322253
7051 11:07:00.325120 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7052 11:07:00.325744
7053 11:07:00.328502 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7054 11:07:00.331772 [DutyScan_Calibration_Flow] ====Done====
7055 11:07:00.332233 ==
7056 11:07:00.334930 Dram Type= 6, Freq= 0, CH_1, rank 0
7057 11:07:00.338396 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7058 11:07:00.338978 ==
7059 11:07:00.341373 [Duty_Offset_Calibration]
7060 11:07:00.341901 B0:0 B1:4 CA:-5
7061 11:07:00.342400
7062 11:07:00.344698 [DutyScan_Calibration_Flow] k_type=0
7063 11:07:00.355826
7064 11:07:00.356304 ==CLK 0==
7065 11:07:00.359218 Final CLK duty delay cell = 0
7066 11:07:00.362532 [0] MAX Duty = 5156%(X100), DQS PI = 22
7067 11:07:00.366018 [0] MIN Duty = 4906%(X100), DQS PI = 50
7068 11:07:00.369330 [0] AVG Duty = 5031%(X100)
7069 11:07:00.369763
7070 11:07:00.372842 CH1 CLK Duty spec in!! Max-Min= 250%
7071 11:07:00.375900 [DutyScan_Calibration_Flow] ====Done====
7072 11:07:00.376327
7073 11:07:00.379038 [DutyScan_Calibration_Flow] k_type=1
7074 11:07:00.394755
7075 11:07:00.395215 ==DQS 0 ==
7076 11:07:00.397897 Final DQS duty delay cell = 0
7077 11:07:00.401276 [0] MAX Duty = 5156%(X100), DQS PI = 20
7078 11:07:00.404897 [0] MIN Duty = 4876%(X100), DQS PI = 42
7079 11:07:00.408410 [0] AVG Duty = 5016%(X100)
7080 11:07:00.408920
7081 11:07:00.409287 ==DQS 1 ==
7082 11:07:00.411153 Final DQS duty delay cell = -4
7083 11:07:00.414602 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7084 11:07:00.417794 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7085 11:07:00.421415 [-4] AVG Duty = 4922%(X100)
7086 11:07:00.421855
7087 11:07:00.424607 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7088 11:07:00.425140
7089 11:07:00.427615 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7090 11:07:00.431306 [DutyScan_Calibration_Flow] ====Done====
7091 11:07:00.431746
7092 11:07:00.434410 [DutyScan_Calibration_Flow] k_type=3
7093 11:07:00.450360
7094 11:07:00.451051 ==DQM 0 ==
7095 11:07:00.453680 Final DQM duty delay cell = -4
7096 11:07:00.456899 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7097 11:07:00.460428 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7098 11:07:00.463685 [-4] AVG Duty = 4922%(X100)
7099 11:07:00.464114
7100 11:07:00.464412 ==DQM 1 ==
7101 11:07:00.467083 Final DQM duty delay cell = -4
7102 11:07:00.470311 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7103 11:07:00.473677 [-4] MIN Duty = 4907%(X100), DQS PI = 32
7104 11:07:00.476648 [-4] AVG Duty = 4984%(X100)
7105 11:07:00.477146
7106 11:07:00.480553 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7107 11:07:00.480939
7108 11:07:00.483361 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7109 11:07:00.486584 [DutyScan_Calibration_Flow] ====Done====
7110 11:07:00.486964
7111 11:07:00.490482 [DutyScan_Calibration_Flow] k_type=2
7112 11:07:00.507890
7113 11:07:00.508271 ==DQ 0 ==
7114 11:07:00.511616 Final DQ duty delay cell = 0
7115 11:07:00.514710 [0] MAX Duty = 5093%(X100), DQS PI = 34
7116 11:07:00.517932 [0] MIN Duty = 4969%(X100), DQS PI = 46
7117 11:07:00.518333 [0] AVG Duty = 5031%(X100)
7118 11:07:00.518729
7119 11:07:00.521320 ==DQ 1 ==
7120 11:07:00.524973 Final DQ duty delay cell = 0
7121 11:07:00.528084 [0] MAX Duty = 5031%(X100), DQS PI = 2
7122 11:07:00.531405 [0] MIN Duty = 4876%(X100), DQS PI = 26
7123 11:07:00.531790 [0] AVG Duty = 4953%(X100)
7124 11:07:00.532170
7125 11:07:00.534731 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7126 11:07:00.535112
7127 11:07:00.541530 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7128 11:07:00.544332 [DutyScan_Calibration_Flow] ====Done====
7129 11:07:00.548588 nWR fixed to 30
7130 11:07:00.549013 [ModeRegInit_LP4] CH0 RK0
7131 11:07:00.551278 [ModeRegInit_LP4] CH0 RK1
7132 11:07:00.554938 [ModeRegInit_LP4] CH1 RK0
7133 11:07:00.555473 [ModeRegInit_LP4] CH1 RK1
7134 11:07:00.558190 match AC timing 4
7135 11:07:00.561591 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7136 11:07:00.564600 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7137 11:07:00.571630 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7138 11:07:00.574694 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7139 11:07:00.581041 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7140 11:07:00.581481 [MiockJmeterHQA]
7141 11:07:00.581789
7142 11:07:00.584504 [DramcMiockJmeter] u1RxGatingPI = 0
7143 11:07:00.587662 0 : 4255, 4030
7144 11:07:00.588054 4 : 4252, 4027
7145 11:07:00.588357 8 : 4255, 4029
7146 11:07:00.591486 12 : 4253, 4026
7147 11:07:00.591951 16 : 4252, 4027
7148 11:07:00.594670 20 : 4365, 4140
7149 11:07:00.595114 24 : 4253, 4027
7150 11:07:00.597627 28 : 4253, 4026
7151 11:07:00.598013 32 : 4252, 4027
7152 11:07:00.601138 36 : 4255, 4029
7153 11:07:00.601747 40 : 4253, 4026
7154 11:07:00.602268 44 : 4252, 4027
7155 11:07:00.604523 48 : 4366, 4139
7156 11:07:00.604909 52 : 4252, 4027
7157 11:07:00.607766 56 : 4255, 4029
7158 11:07:00.608154 60 : 4250, 4027
7159 11:07:00.611378 64 : 4363, 4140
7160 11:07:00.611857 68 : 4250, 4027
7161 11:07:00.614135 72 : 4360, 4138
7162 11:07:00.614524 76 : 4252, 4030
7163 11:07:00.614834 80 : 4250, 4027
7164 11:07:00.617867 84 : 4250, 4027
7165 11:07:00.618255 88 : 4252, 4029
7166 11:07:00.621448 92 : 4360, 4138
7167 11:07:00.621916 96 : 4250, 4027
7168 11:07:00.624647 100 : 4361, 1347
7169 11:07:00.625110 104 : 4252, 0
7170 11:07:00.625452 108 : 4249, 0
7171 11:07:00.627390 112 : 4361, 0
7172 11:07:00.627776 116 : 4250, 0
7173 11:07:00.631079 120 : 4360, 0
7174 11:07:00.631465 124 : 4250, 0
7175 11:07:00.631767 128 : 4361, 0
7176 11:07:00.634164 132 : 4250, 0
7177 11:07:00.634566 136 : 4361, 0
7178 11:07:00.637673 140 : 4250, 0
7179 11:07:00.638061 144 : 4250, 0
7180 11:07:00.638364 148 : 4252, 0
7181 11:07:00.640716 152 : 4252, 0
7182 11:07:00.641102 156 : 4250, 0
7183 11:07:00.641554 160 : 4252, 0
7184 11:07:00.644022 164 : 4250, 0
7185 11:07:00.644409 168 : 4253, 0
7186 11:07:00.647373 172 : 4250, 0
7187 11:07:00.647761 176 : 4252, 0
7188 11:07:00.648062 180 : 4250, 0
7189 11:07:00.650654 184 : 4250, 0
7190 11:07:00.651037 188 : 4363, 0
7191 11:07:00.654360 192 : 4250, 0
7192 11:07:00.654752 196 : 4250, 0
7193 11:07:00.655055 200 : 4252, 0
7194 11:07:00.657164 204 : 4361, 0
7195 11:07:00.657587 208 : 4250, 0
7196 11:07:00.660494 212 : 4250, 0
7197 11:07:00.660923 216 : 4250, 0
7198 11:07:00.661266 220 : 4361, 892
7199 11:07:00.663945 224 : 4250, 4019
7200 11:07:00.664378 228 : 4250, 4027
7201 11:07:00.667267 232 : 4252, 4029
7202 11:07:00.667654 236 : 4250, 4027
7203 11:07:00.670387 240 : 4250, 4027
7204 11:07:00.670774 244 : 4252, 4029
7205 11:07:00.674025 248 : 4250, 4027
7206 11:07:00.674421 252 : 4361, 4137
7207 11:07:00.677173 256 : 4361, 4138
7208 11:07:00.677607 260 : 4250, 4027
7209 11:07:00.680581 264 : 4363, 4140
7210 11:07:00.680965 268 : 4360, 4138
7211 11:07:00.681426 272 : 4250, 4027
7212 11:07:00.683782 276 : 4250, 4027
7213 11:07:00.684170 280 : 4252, 4029
7214 11:07:00.686958 284 : 4250, 4026
7215 11:07:00.687347 288 : 4250, 4027
7216 11:07:00.690437 292 : 4250, 4027
7217 11:07:00.690825 296 : 4252, 4029
7218 11:07:00.693917 300 : 4250, 4026
7219 11:07:00.694354 304 : 4361, 4137
7220 11:07:00.697274 308 : 4361, 4138
7221 11:07:00.697707 312 : 4250, 4027
7222 11:07:00.700200 316 : 4363, 4140
7223 11:07:00.700586 320 : 4360, 4138
7224 11:07:00.703767 324 : 4250, 4027
7225 11:07:00.704161 328 : 4250, 4027
7226 11:07:00.706952 332 : 4252, 4029
7227 11:07:00.707412 336 : 4250, 3638
7228 11:07:00.707731 340 : 4250, 1496
7229 11:07:00.710254
7230 11:07:00.710690 MIOCK jitter meter ch=0
7231 11:07:00.710983
7232 11:07:00.714341 1T = (340-100) = 240 dly cells
7233 11:07:00.720130 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7234 11:07:00.720521 ==
7235 11:07:00.723499 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 11:07:00.727034 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7237 11:07:00.727494 ==
7238 11:07:00.733571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7239 11:07:00.736711 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7240 11:07:00.740134 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7241 11:07:00.746765 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7242 11:07:00.755472 [CA 0] Center 42 (12~73) winsize 62
7243 11:07:00.758589 [CA 1] Center 42 (12~73) winsize 62
7244 11:07:00.761877 [CA 2] Center 39 (9~69) winsize 61
7245 11:07:00.765283 [CA 3] Center 38 (9~68) winsize 60
7246 11:07:00.768747 [CA 4] Center 36 (6~67) winsize 62
7247 11:07:00.772411 [CA 5] Center 36 (6~66) winsize 61
7248 11:07:00.772821
7249 11:07:00.775382 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7250 11:07:00.775778
7251 11:07:00.778513 [CATrainingPosCal] consider 1 rank data
7252 11:07:00.782162 u2DelayCellTimex100 = 271/100 ps
7253 11:07:00.785167 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7254 11:07:00.792306 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7255 11:07:00.795247 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7256 11:07:00.798704 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7257 11:07:00.801658 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7258 11:07:00.805198 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7259 11:07:00.805626
7260 11:07:00.808588 CA PerBit enable=1, Macro0, CA PI delay=36
7261 11:07:00.808982
7262 11:07:00.811641 [CBTSetCACLKResult] CA Dly = 36
7263 11:07:00.815256 CS Dly: 10 (0~41)
7264 11:07:00.818140 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7265 11:07:00.821487 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7266 11:07:00.821882 ==
7267 11:07:00.824846 Dram Type= 6, Freq= 0, CH_0, rank 1
7268 11:07:00.828153 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7269 11:07:00.831530 ==
7270 11:07:00.834930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7271 11:07:00.838153 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7272 11:07:00.844933 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7273 11:07:00.848133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7274 11:07:00.858170 [CA 0] Center 42 (12~73) winsize 62
7275 11:07:00.861295 [CA 1] Center 41 (11~72) winsize 62
7276 11:07:00.864629 [CA 2] Center 38 (9~68) winsize 60
7277 11:07:00.868195 [CA 3] Center 37 (7~67) winsize 61
7278 11:07:00.871260 [CA 4] Center 35 (5~65) winsize 61
7279 11:07:00.874510 [CA 5] Center 35 (5~66) winsize 62
7280 11:07:00.874936
7281 11:07:00.877688 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7282 11:07:00.878215
7283 11:07:00.881115 [CATrainingPosCal] consider 2 rank data
7284 11:07:00.884598 u2DelayCellTimex100 = 271/100 ps
7285 11:07:00.887816 CA0 delay=42 (12~73),Diff = 7 PI (25 cell)
7286 11:07:00.894286 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7287 11:07:00.897775 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7288 11:07:00.900962 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7289 11:07:00.904668 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7290 11:07:00.907553 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
7291 11:07:00.907993
7292 11:07:00.911196 CA PerBit enable=1, Macro0, CA PI delay=35
7293 11:07:00.911801
7294 11:07:00.914161 [CBTSetCACLKResult] CA Dly = 35
7295 11:07:00.917971 CS Dly: 11 (0~43)
7296 11:07:00.920906 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7297 11:07:00.924160 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7298 11:07:00.924806
7299 11:07:00.927473 ----->DramcWriteLeveling(PI) begin...
7300 11:07:00.927901 ==
7301 11:07:00.930590 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 11:07:00.937775 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7303 11:07:00.938219 ==
7304 11:07:00.940906 Write leveling (Byte 0): 28 => 28
7305 11:07:00.941354 Write leveling (Byte 1): 26 => 26
7306 11:07:00.943953 DramcWriteLeveling(PI) end<-----
7307 11:07:00.944371
7308 11:07:00.947291 ==
7309 11:07:00.947712 Dram Type= 6, Freq= 0, CH_0, rank 0
7310 11:07:00.954168 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7311 11:07:00.954593 ==
7312 11:07:00.957336 [Gating] SW mode calibration
7313 11:07:00.963637 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7314 11:07:00.967275 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7315 11:07:00.973748 0 12 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7316 11:07:00.977103 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7317 11:07:00.980590 0 12 8 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
7318 11:07:00.987218 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7319 11:07:00.990357 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7320 11:07:00.994181 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7321 11:07:01.000583 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7322 11:07:01.004332 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7323 11:07:01.007052 0 13 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
7324 11:07:01.013952 0 13 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
7325 11:07:01.017202 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7326 11:07:01.020785 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7327 11:07:01.027316 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7328 11:07:01.030798 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7329 11:07:01.033851 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7330 11:07:01.040384 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7331 11:07:01.043826 0 14 0 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7332 11:07:01.046814 0 14 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7333 11:07:01.053990 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7334 11:07:01.057330 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 11:07:01.060498 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7336 11:07:01.063720 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 11:07:01.070496 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7338 11:07:01.073707 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7339 11:07:01.076717 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7340 11:07:01.083573 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7341 11:07:01.086872 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7342 11:07:01.089973 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 11:07:01.096639 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 11:07:01.100185 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 11:07:01.103331 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 11:07:01.109951 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 11:07:01.113829 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 11:07:01.116924 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 11:07:01.123061 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 11:07:01.126328 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 11:07:01.129838 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 11:07:01.136311 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 11:07:01.139695 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 11:07:01.143389 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7355 11:07:01.149850 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7356 11:07:01.153696 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7357 11:07:01.156363 Total UI for P1: 0, mck2ui 16
7358 11:07:01.159710 best dqsien dly found for B0: ( 1, 0, 30)
7359 11:07:01.163324 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7360 11:07:01.169734 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7361 11:07:01.170161 Total UI for P1: 0, mck2ui 16
7362 11:07:01.176861 best dqsien dly found for B1: ( 1, 1, 6)
7363 11:07:01.180068 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7364 11:07:01.183227 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7365 11:07:01.183653
7366 11:07:01.186451 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7367 11:07:01.189860 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7368 11:07:01.193336 [Gating] SW calibration Done
7369 11:07:01.193852 ==
7370 11:07:01.196468 Dram Type= 6, Freq= 0, CH_0, rank 0
7371 11:07:01.200058 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7372 11:07:01.200534 ==
7373 11:07:01.203016 RX Vref Scan: 0
7374 11:07:01.203449
7375 11:07:01.203776 RX Vref 0 -> 0, step: 1
7376 11:07:01.204083
7377 11:07:01.206195 RX Delay 0 -> 252, step: 8
7378 11:07:01.209760 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7379 11:07:01.213290 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7380 11:07:01.219495 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7381 11:07:01.222770 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7382 11:07:01.226546 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7383 11:07:01.229616 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7384 11:07:01.233069 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7385 11:07:01.240014 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7386 11:07:01.242922 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7387 11:07:01.246223 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7388 11:07:01.249865 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7389 11:07:01.252839 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7390 11:07:01.259467 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7391 11:07:01.262670 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7392 11:07:01.266567 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7393 11:07:01.269500 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7394 11:07:01.269927 ==
7395 11:07:01.272782 Dram Type= 6, Freq= 0, CH_0, rank 0
7396 11:07:01.279097 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7397 11:07:01.279530 ==
7398 11:07:01.279862 DQS Delay:
7399 11:07:01.282829 DQS0 = 0, DQS1 = 0
7400 11:07:01.283338 DQM Delay:
7401 11:07:01.286044 DQM0 = 129, DQM1 = 122
7402 11:07:01.286544 DQ Delay:
7403 11:07:01.289329 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7404 11:07:01.292389 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7405 11:07:01.296071 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7406 11:07:01.299240 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7407 11:07:01.299744
7408 11:07:01.300079
7409 11:07:01.300385 ==
7410 11:07:01.302325 Dram Type= 6, Freq= 0, CH_0, rank 0
7411 11:07:01.309302 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7412 11:07:01.309820 ==
7413 11:07:01.310155
7414 11:07:01.310457
7415 11:07:01.310753 TX Vref Scan disable
7416 11:07:01.312382 == TX Byte 0 ==
7417 11:07:01.315902 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7418 11:07:01.322041 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7419 11:07:01.322510 == TX Byte 1 ==
7420 11:07:01.325914 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7421 11:07:01.332106 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7422 11:07:01.332593 ==
7423 11:07:01.335432 Dram Type= 6, Freq= 0, CH_0, rank 0
7424 11:07:01.339461 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7425 11:07:01.339974 ==
7426 11:07:01.351277
7427 11:07:01.354586 TX Vref early break, caculate TX vref
7428 11:07:01.357879 TX Vref=16, minBit 8, minWin=21, winSum=375
7429 11:07:01.361389 TX Vref=18, minBit 9, minWin=22, winSum=381
7430 11:07:01.364566 TX Vref=20, minBit 8, minWin=22, winSum=390
7431 11:07:01.368216 TX Vref=22, minBit 8, minWin=23, winSum=395
7432 11:07:01.371244 TX Vref=24, minBit 8, minWin=24, winSum=403
7433 11:07:01.378055 TX Vref=26, minBit 10, minWin=24, winSum=413
7434 11:07:01.380865 TX Vref=28, minBit 8, minWin=25, winSum=415
7435 11:07:01.384692 TX Vref=30, minBit 6, minWin=24, winSum=411
7436 11:07:01.387755 TX Vref=32, minBit 7, minWin=24, winSum=405
7437 11:07:01.391347 TX Vref=34, minBit 8, minWin=23, winSum=390
7438 11:07:01.397736 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 28
7439 11:07:01.398261
7440 11:07:01.400889 Final TX Range 0 Vref 28
7441 11:07:01.401434
7442 11:07:01.401772 ==
7443 11:07:01.403966 Dram Type= 6, Freq= 0, CH_0, rank 0
7444 11:07:01.407462 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7445 11:07:01.407892 ==
7446 11:07:01.408221
7447 11:07:01.408525
7448 11:07:01.411240 TX Vref Scan disable
7449 11:07:01.417407 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7450 11:07:01.417900 == TX Byte 0 ==
7451 11:07:01.420922 u2DelayCellOfst[0]=14 cells (4 PI)
7452 11:07:01.424362 u2DelayCellOfst[1]=21 cells (6 PI)
7453 11:07:01.427243 u2DelayCellOfst[2]=18 cells (5 PI)
7454 11:07:01.430769 u2DelayCellOfst[3]=14 cells (4 PI)
7455 11:07:01.433898 u2DelayCellOfst[4]=10 cells (3 PI)
7456 11:07:01.437726 u2DelayCellOfst[5]=0 cells (0 PI)
7457 11:07:01.440853 u2DelayCellOfst[6]=21 cells (6 PI)
7458 11:07:01.443867 u2DelayCellOfst[7]=18 cells (5 PI)
7459 11:07:01.447149 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7460 11:07:01.450491 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7461 11:07:01.453890 == TX Byte 1 ==
7462 11:07:01.457326 u2DelayCellOfst[8]=3 cells (1 PI)
7463 11:07:01.457833 u2DelayCellOfst[9]=0 cells (0 PI)
7464 11:07:01.460625 u2DelayCellOfst[10]=10 cells (3 PI)
7465 11:07:01.463897 u2DelayCellOfst[11]=3 cells (1 PI)
7466 11:07:01.467091 u2DelayCellOfst[12]=14 cells (4 PI)
7467 11:07:01.470957 u2DelayCellOfst[13]=14 cells (4 PI)
7468 11:07:01.473816 u2DelayCellOfst[14]=18 cells (5 PI)
7469 11:07:01.476995 u2DelayCellOfst[15]=18 cells (5 PI)
7470 11:07:01.480627 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7471 11:07:01.486963 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7472 11:07:01.487429 DramC Write-DBI on
7473 11:07:01.487761 ==
7474 11:07:01.490346 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 11:07:01.497088 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7476 11:07:01.497684 ==
7477 11:07:01.498030
7478 11:07:01.498337
7479 11:07:01.498636 TX Vref Scan disable
7480 11:07:01.500921 == TX Byte 0 ==
7481 11:07:01.504099 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7482 11:07:01.507363 == TX Byte 1 ==
7483 11:07:01.510787 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7484 11:07:01.514218 DramC Write-DBI off
7485 11:07:01.514713
7486 11:07:01.515048 [DATLAT]
7487 11:07:01.515356 Freq=1600, CH0 RK0
7488 11:07:01.515655
7489 11:07:01.517571 DATLAT Default: 0xf
7490 11:07:01.518081 0, 0xFFFF, sum = 0
7491 11:07:01.520476 1, 0xFFFF, sum = 0
7492 11:07:01.523878 2, 0xFFFF, sum = 0
7493 11:07:01.524310 3, 0xFFFF, sum = 0
7494 11:07:01.527437 4, 0xFFFF, sum = 0
7495 11:07:01.527923 5, 0xFFFF, sum = 0
7496 11:07:01.530497 6, 0xFFFF, sum = 0
7497 11:07:01.530935 7, 0xFFFF, sum = 0
7498 11:07:01.533802 8, 0xFFFF, sum = 0
7499 11:07:01.534238 9, 0xFFFF, sum = 0
7500 11:07:01.537035 10, 0xFFFF, sum = 0
7501 11:07:01.537516 11, 0xFFFF, sum = 0
7502 11:07:01.541049 12, 0xFFF, sum = 0
7503 11:07:01.541549 13, 0x0, sum = 1
7504 11:07:01.543813 14, 0x0, sum = 2
7505 11:07:01.544282 15, 0x0, sum = 3
7506 11:07:01.547127 16, 0x0, sum = 4
7507 11:07:01.547561 best_step = 14
7508 11:07:01.547889
7509 11:07:01.548190 ==
7510 11:07:01.550463 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 11:07:01.553967 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7512 11:07:01.557115 ==
7513 11:07:01.557656 RX Vref Scan: 1
7514 11:07:01.557987
7515 11:07:01.560514 Set Vref Range= 24 -> 127
7516 11:07:01.560937
7517 11:07:01.563698 RX Vref 24 -> 127, step: 1
7518 11:07:01.564204
7519 11:07:01.564535 RX Delay 11 -> 252, step: 4
7520 11:07:01.564840
7521 11:07:01.566976 Set Vref, RX VrefLevel [Byte0]: 24
7522 11:07:01.570462 [Byte1]: 24
7523 11:07:01.574224
7524 11:07:01.574651 Set Vref, RX VrefLevel [Byte0]: 25
7525 11:07:01.577708 [Byte1]: 25
7526 11:07:01.581913
7527 11:07:01.582335 Set Vref, RX VrefLevel [Byte0]: 26
7528 11:07:01.584933 [Byte1]: 26
7529 11:07:01.589084
7530 11:07:01.589690 Set Vref, RX VrefLevel [Byte0]: 27
7531 11:07:01.592590 [Byte1]: 27
7532 11:07:01.596709
7533 11:07:01.597131 Set Vref, RX VrefLevel [Byte0]: 28
7534 11:07:01.599962 [Byte1]: 28
7535 11:07:01.604388
7536 11:07:01.604821 Set Vref, RX VrefLevel [Byte0]: 29
7537 11:07:01.607676 [Byte1]: 29
7538 11:07:01.612059
7539 11:07:01.612851 Set Vref, RX VrefLevel [Byte0]: 30
7540 11:07:01.615035 [Byte1]: 30
7541 11:07:01.619695
7542 11:07:01.620112 Set Vref, RX VrefLevel [Byte0]: 31
7543 11:07:01.622991 [Byte1]: 31
7544 11:07:01.627354
7545 11:07:01.627806 Set Vref, RX VrefLevel [Byte0]: 32
7546 11:07:01.630504 [Byte1]: 32
7547 11:07:01.634721
7548 11:07:01.635156 Set Vref, RX VrefLevel [Byte0]: 33
7549 11:07:01.637949 [Byte1]: 33
7550 11:07:01.642300
7551 11:07:01.645806 Set Vref, RX VrefLevel [Byte0]: 34
7552 11:07:01.646226 [Byte1]: 34
7553 11:07:01.650126
7554 11:07:01.650586 Set Vref, RX VrefLevel [Byte0]: 35
7555 11:07:01.653976 [Byte1]: 35
7556 11:07:01.657662
7557 11:07:01.658036 Set Vref, RX VrefLevel [Byte0]: 36
7558 11:07:01.660974 [Byte1]: 36
7559 11:07:01.665110
7560 11:07:01.665574 Set Vref, RX VrefLevel [Byte0]: 37
7561 11:07:01.668637 [Byte1]: 37
7562 11:07:01.672859
7563 11:07:01.673386 Set Vref, RX VrefLevel [Byte0]: 38
7564 11:07:01.676220 [Byte1]: 38
7565 11:07:01.680461
7566 11:07:01.680929 Set Vref, RX VrefLevel [Byte0]: 39
7567 11:07:01.683921 [Byte1]: 39
7568 11:07:01.688075
7569 11:07:01.688515 Set Vref, RX VrefLevel [Byte0]: 40
7570 11:07:01.691608 [Byte1]: 40
7571 11:07:01.696014
7572 11:07:01.696526 Set Vref, RX VrefLevel [Byte0]: 41
7573 11:07:01.698855 [Byte1]: 41
7574 11:07:01.703357
7575 11:07:01.703869 Set Vref, RX VrefLevel [Byte0]: 42
7576 11:07:01.706858 [Byte1]: 42
7577 11:07:01.710905
7578 11:07:01.711329 Set Vref, RX VrefLevel [Byte0]: 43
7579 11:07:01.714413 [Byte1]: 43
7580 11:07:01.718500
7581 11:07:01.718917 Set Vref, RX VrefLevel [Byte0]: 44
7582 11:07:01.721894 [Byte1]: 44
7583 11:07:01.726159
7584 11:07:01.726601 Set Vref, RX VrefLevel [Byte0]: 45
7585 11:07:01.729558 [Byte1]: 45
7586 11:07:01.733810
7587 11:07:01.734184 Set Vref, RX VrefLevel [Byte0]: 46
7588 11:07:01.737149 [Byte1]: 46
7589 11:07:01.741423
7590 11:07:01.741818 Set Vref, RX VrefLevel [Byte0]: 47
7591 11:07:01.744764 [Byte1]: 47
7592 11:07:01.748873
7593 11:07:01.749293 Set Vref, RX VrefLevel [Byte0]: 48
7594 11:07:01.752657 [Byte1]: 48
7595 11:07:01.756656
7596 11:07:01.757039 Set Vref, RX VrefLevel [Byte0]: 49
7597 11:07:01.760167 [Byte1]: 49
7598 11:07:01.764473
7599 11:07:01.764959 Set Vref, RX VrefLevel [Byte0]: 50
7600 11:07:01.767699 [Byte1]: 50
7601 11:07:01.771924
7602 11:07:01.772381 Set Vref, RX VrefLevel [Byte0]: 51
7603 11:07:01.775407 [Byte1]: 51
7604 11:07:01.779600
7605 11:07:01.780176 Set Vref, RX VrefLevel [Byte0]: 52
7606 11:07:01.782752 [Byte1]: 52
7607 11:07:01.786948
7608 11:07:01.787375 Set Vref, RX VrefLevel [Byte0]: 53
7609 11:07:01.790411 [Byte1]: 53
7610 11:07:01.795029
7611 11:07:01.795529 Set Vref, RX VrefLevel [Byte0]: 54
7612 11:07:01.798246 [Byte1]: 54
7613 11:07:01.802418
7614 11:07:01.802836 Set Vref, RX VrefLevel [Byte0]: 55
7615 11:07:01.805924 [Byte1]: 55
7616 11:07:01.809873
7617 11:07:01.810289 Set Vref, RX VrefLevel [Byte0]: 56
7618 11:07:01.813311 [Byte1]: 56
7619 11:07:01.817751
7620 11:07:01.818268 Set Vref, RX VrefLevel [Byte0]: 57
7621 11:07:01.820899 [Byte1]: 57
7622 11:07:01.825384
7623 11:07:01.825891 Set Vref, RX VrefLevel [Byte0]: 58
7624 11:07:01.828475 [Byte1]: 58
7625 11:07:01.833121
7626 11:07:01.833759 Set Vref, RX VrefLevel [Byte0]: 59
7627 11:07:01.836064 [Byte1]: 59
7628 11:07:01.840235
7629 11:07:01.843785 Set Vref, RX VrefLevel [Byte0]: 60
7630 11:07:01.846930 [Byte1]: 60
7631 11:07:01.847447
7632 11:07:01.850322 Set Vref, RX VrefLevel [Byte0]: 61
7633 11:07:01.853640 [Byte1]: 61
7634 11:07:01.854131
7635 11:07:01.857158 Set Vref, RX VrefLevel [Byte0]: 62
7636 11:07:01.860734 [Byte1]: 62
7637 11:07:01.861296
7638 11:07:01.863810 Set Vref, RX VrefLevel [Byte0]: 63
7639 11:07:01.866975 [Byte1]: 63
7640 11:07:01.871011
7641 11:07:01.871675 Set Vref, RX VrefLevel [Byte0]: 64
7642 11:07:01.874338 [Byte1]: 64
7643 11:07:01.878685
7644 11:07:01.879178 Set Vref, RX VrefLevel [Byte0]: 65
7645 11:07:01.881734 [Byte1]: 65
7646 11:07:01.886531
7647 11:07:01.887215 Set Vref, RX VrefLevel [Byte0]: 66
7648 11:07:01.889719 [Byte1]: 66
7649 11:07:01.893791
7650 11:07:01.894296 Set Vref, RX VrefLevel [Byte0]: 67
7651 11:07:01.897336 [Byte1]: 67
7652 11:07:01.901480
7653 11:07:01.901970 Set Vref, RX VrefLevel [Byte0]: 68
7654 11:07:01.904832 [Byte1]: 68
7655 11:07:01.908939
7656 11:07:01.909489 Set Vref, RX VrefLevel [Byte0]: 69
7657 11:07:01.912063 [Byte1]: 69
7658 11:07:01.916639
7659 11:07:01.917129 Set Vref, RX VrefLevel [Byte0]: 70
7660 11:07:01.920041 [Byte1]: 70
7661 11:07:01.924420
7662 11:07:01.924914 Final RX Vref Byte 0 = 54 to rank0
7663 11:07:01.927574 Final RX Vref Byte 1 = 56 to rank0
7664 11:07:01.930623 Final RX Vref Byte 0 = 54 to rank1
7665 11:07:01.933939 Final RX Vref Byte 1 = 56 to rank1==
7666 11:07:01.937679 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 11:07:01.944491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7668 11:07:01.944994 ==
7669 11:07:01.945370 DQS Delay:
7670 11:07:01.945689 DQS0 = 0, DQS1 = 0
7671 11:07:01.947475 DQM Delay:
7672 11:07:01.947889 DQM0 = 126, DQM1 = 120
7673 11:07:01.950968 DQ Delay:
7674 11:07:01.954225 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7675 11:07:01.957621 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7676 11:07:01.961116 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7677 11:07:01.963999 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7678 11:07:01.964671
7679 11:07:01.965181
7680 11:07:01.965564
7681 11:07:01.967490 [DramC_TX_OE_Calibration] TA2
7682 11:07:01.970526 Original DQ_B0 (3 6) =30, OEN = 27
7683 11:07:01.973689 Original DQ_B1 (3 6) =30, OEN = 27
7684 11:07:01.977061 24, 0x0, End_B0=24 End_B1=24
7685 11:07:01.977610 25, 0x0, End_B0=25 End_B1=25
7686 11:07:01.980439 26, 0x0, End_B0=26 End_B1=26
7687 11:07:01.983855 27, 0x0, End_B0=27 End_B1=27
7688 11:07:01.987311 28, 0x0, End_B0=28 End_B1=28
7689 11:07:01.990403 29, 0x0, End_B0=29 End_B1=29
7690 11:07:01.990831 30, 0x0, End_B0=30 End_B1=30
7691 11:07:01.993622 31, 0x4141, End_B0=30 End_B1=30
7692 11:07:01.997031 Byte0 end_step=30 best_step=27
7693 11:07:02.000746 Byte1 end_step=30 best_step=27
7694 11:07:02.003711 Byte0 TX OE(2T, 0.5T) = (3, 3)
7695 11:07:02.007087 Byte1 TX OE(2T, 0.5T) = (3, 3)
7696 11:07:02.007676
7697 11:07:02.008175
7698 11:07:02.013637 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7699 11:07:02.016954 CH0 RK0: MR19=303, MR18=1E1E
7700 11:07:02.024114 CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7701 11:07:02.024601
7702 11:07:02.027096 ----->DramcWriteLeveling(PI) begin...
7703 11:07:02.027522 ==
7704 11:07:02.030129 Dram Type= 6, Freq= 0, CH_0, rank 1
7705 11:07:02.033828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7706 11:07:02.034251 ==
7707 11:07:02.036926 Write leveling (Byte 0): 28 => 28
7708 11:07:02.040145 Write leveling (Byte 1): 27 => 27
7709 11:07:02.043749 DramcWriteLeveling(PI) end<-----
7710 11:07:02.044260
7711 11:07:02.044588 ==
7712 11:07:02.047139 Dram Type= 6, Freq= 0, CH_0, rank 1
7713 11:07:02.050253 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7714 11:07:02.050678 ==
7715 11:07:02.053348 [Gating] SW mode calibration
7716 11:07:02.060380 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7717 11:07:02.067164 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7718 11:07:02.070075 0 12 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7719 11:07:02.073250 0 12 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
7720 11:07:02.080246 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7721 11:07:02.083273 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7722 11:07:02.086791 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7723 11:07:02.093106 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7724 11:07:02.096416 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7725 11:07:02.100309 0 12 28 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
7726 11:07:02.106728 0 13 0 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)
7727 11:07:02.110233 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
7728 11:07:02.113423 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7729 11:07:02.120127 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 11:07:02.123268 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7731 11:07:02.126422 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7732 11:07:02.133760 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7733 11:07:02.136750 0 13 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7734 11:07:02.139721 0 14 0 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7735 11:07:02.146348 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7736 11:07:02.149725 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7737 11:07:02.153049 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 11:07:02.160407 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7739 11:07:02.163058 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 11:07:02.166668 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7741 11:07:02.173152 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7742 11:07:02.176478 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7743 11:07:02.179631 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7744 11:07:02.186260 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 11:07:02.189510 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 11:07:02.193516 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 11:07:02.199672 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 11:07:02.202608 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 11:07:02.206067 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 11:07:02.212672 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 11:07:02.216189 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 11:07:02.219272 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 11:07:02.225854 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 11:07:02.229027 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 11:07:02.232440 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 11:07:02.239096 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7757 11:07:02.242371 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7758 11:07:02.245866 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7759 11:07:02.249277 Total UI for P1: 0, mck2ui 16
7760 11:07:02.252593 best dqsien dly found for B0: ( 1, 0, 26)
7761 11:07:02.255842 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7762 11:07:02.262315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7763 11:07:02.265479 Total UI for P1: 0, mck2ui 16
7764 11:07:02.268873 best dqsien dly found for B1: ( 1, 1, 2)
7765 11:07:02.272757 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
7766 11:07:02.275747 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7767 11:07:02.276213
7768 11:07:02.279232 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
7769 11:07:02.282094 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7770 11:07:02.285290 [Gating] SW calibration Done
7771 11:07:02.285729 ==
7772 11:07:02.289104 Dram Type= 6, Freq= 0, CH_0, rank 1
7773 11:07:02.292192 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7774 11:07:02.292620 ==
7775 11:07:02.295503 RX Vref Scan: 0
7776 11:07:02.295943
7777 11:07:02.298682 RX Vref 0 -> 0, step: 1
7778 11:07:02.299098
7779 11:07:02.299427 RX Delay 0 -> 252, step: 8
7780 11:07:02.305551 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7781 11:07:02.309314 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7782 11:07:02.312155 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7783 11:07:02.315357 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7784 11:07:02.318709 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7785 11:07:02.325103 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7786 11:07:02.328892 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7787 11:07:02.332591 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7788 11:07:02.335499 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
7789 11:07:02.338316 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7790 11:07:02.345382 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7791 11:07:02.348678 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7792 11:07:02.352391 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7793 11:07:02.355240 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7794 11:07:02.358613 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7795 11:07:02.365114 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7796 11:07:02.365591 ==
7797 11:07:02.368512 Dram Type= 6, Freq= 0, CH_0, rank 1
7798 11:07:02.371714 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7799 11:07:02.372135 ==
7800 11:07:02.372462 DQS Delay:
7801 11:07:02.374896 DQS0 = 0, DQS1 = 0
7802 11:07:02.375315 DQM Delay:
7803 11:07:02.378576 DQM0 = 130, DQM1 = 123
7804 11:07:02.378997 DQ Delay:
7805 11:07:02.382172 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7806 11:07:02.385015 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7807 11:07:02.388517 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
7808 11:07:02.392486 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7809 11:07:02.392996
7810 11:07:02.393410
7811 11:07:02.395201 ==
7812 11:07:02.398417 Dram Type= 6, Freq= 0, CH_0, rank 1
7813 11:07:02.401747 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7814 11:07:02.402173 ==
7815 11:07:02.402507
7816 11:07:02.402812
7817 11:07:02.405137 TX Vref Scan disable
7818 11:07:02.405592 == TX Byte 0 ==
7819 11:07:02.408675 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7820 11:07:02.415243 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7821 11:07:02.415670 == TX Byte 1 ==
7822 11:07:02.418206 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7823 11:07:02.424737 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7824 11:07:02.425160 ==
7825 11:07:02.428109 Dram Type= 6, Freq= 0, CH_0, rank 1
7826 11:07:02.431605 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7827 11:07:02.432108 ==
7828 11:07:02.444520
7829 11:07:02.447663 TX Vref early break, caculate TX vref
7830 11:07:02.450802 TX Vref=16, minBit 10, minWin=22, winSum=374
7831 11:07:02.454681 TX Vref=18, minBit 8, minWin=23, winSum=384
7832 11:07:02.457723 TX Vref=20, minBit 8, minWin=23, winSum=393
7833 11:07:02.461817 TX Vref=22, minBit 1, minWin=23, winSum=399
7834 11:07:02.464103 TX Vref=24, minBit 8, minWin=24, winSum=409
7835 11:07:02.471366 TX Vref=26, minBit 8, minWin=24, winSum=412
7836 11:07:02.474696 TX Vref=28, minBit 8, minWin=24, winSum=417
7837 11:07:02.477851 TX Vref=30, minBit 1, minWin=25, winSum=415
7838 11:07:02.480962 TX Vref=32, minBit 8, minWin=24, winSum=406
7839 11:07:02.484350 TX Vref=34, minBit 8, minWin=23, winSum=392
7840 11:07:02.490785 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 30
7841 11:07:02.491260
7842 11:07:02.494394 Final TX Range 0 Vref 30
7843 11:07:02.494873
7844 11:07:02.495199 ==
7845 11:07:02.497744 Dram Type= 6, Freq= 0, CH_0, rank 1
7846 11:07:02.500808 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7847 11:07:02.501320 ==
7848 11:07:02.501656
7849 11:07:02.501959
7850 11:07:02.504080 TX Vref Scan disable
7851 11:07:02.510668 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7852 11:07:02.511095 == TX Byte 0 ==
7853 11:07:02.514185 u2DelayCellOfst[0]=14 cells (4 PI)
7854 11:07:02.517296 u2DelayCellOfst[1]=18 cells (5 PI)
7855 11:07:02.521185 u2DelayCellOfst[2]=14 cells (4 PI)
7856 11:07:02.524043 u2DelayCellOfst[3]=14 cells (4 PI)
7857 11:07:02.527461 u2DelayCellOfst[4]=7 cells (2 PI)
7858 11:07:02.530616 u2DelayCellOfst[5]=0 cells (0 PI)
7859 11:07:02.534006 u2DelayCellOfst[6]=18 cells (5 PI)
7860 11:07:02.537555 u2DelayCellOfst[7]=18 cells (5 PI)
7861 11:07:02.540557 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7862 11:07:02.544385 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7863 11:07:02.547191 == TX Byte 1 ==
7864 11:07:02.547610 u2DelayCellOfst[8]=0 cells (0 PI)
7865 11:07:02.550596 u2DelayCellOfst[9]=0 cells (0 PI)
7866 11:07:02.554252 u2DelayCellOfst[10]=10 cells (3 PI)
7867 11:07:02.557435 u2DelayCellOfst[11]=3 cells (1 PI)
7868 11:07:02.560499 u2DelayCellOfst[12]=14 cells (4 PI)
7869 11:07:02.563738 u2DelayCellOfst[13]=14 cells (4 PI)
7870 11:07:02.567121 u2DelayCellOfst[14]=14 cells (4 PI)
7871 11:07:02.570545 u2DelayCellOfst[15]=14 cells (4 PI)
7872 11:07:02.573722 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7873 11:07:02.580318 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7874 11:07:02.580782 DramC Write-DBI on
7875 11:07:02.581107 ==
7876 11:07:02.583561 Dram Type= 6, Freq= 0, CH_0, rank 1
7877 11:07:02.587461 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7878 11:07:02.590146 ==
7879 11:07:02.590563
7880 11:07:02.590885
7881 11:07:02.591184 TX Vref Scan disable
7882 11:07:02.593881 == TX Byte 0 ==
7883 11:07:02.597083 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7884 11:07:02.600461 == TX Byte 1 ==
7885 11:07:02.604044 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7886 11:07:02.607274 DramC Write-DBI off
7887 11:07:02.607695
7888 11:07:02.608022 [DATLAT]
7889 11:07:02.608327 Freq=1600, CH0 RK1
7890 11:07:02.608616
7891 11:07:02.610614 DATLAT Default: 0xe
7892 11:07:02.611032 0, 0xFFFF, sum = 0
7893 11:07:02.613845 1, 0xFFFF, sum = 0
7894 11:07:02.616889 2, 0xFFFF, sum = 0
7895 11:07:02.617362 3, 0xFFFF, sum = 0
7896 11:07:02.620660 4, 0xFFFF, sum = 0
7897 11:07:02.621174 5, 0xFFFF, sum = 0
7898 11:07:02.623774 6, 0xFFFF, sum = 0
7899 11:07:02.624203 7, 0xFFFF, sum = 0
7900 11:07:02.626856 8, 0xFFFF, sum = 0
7901 11:07:02.627282 9, 0xFFFF, sum = 0
7902 11:07:02.630357 10, 0xFFFF, sum = 0
7903 11:07:02.630862 11, 0xFFFF, sum = 0
7904 11:07:02.633766 12, 0x8FFF, sum = 0
7905 11:07:02.634195 13, 0x0, sum = 1
7906 11:07:02.636836 14, 0x0, sum = 2
7907 11:07:02.637407 15, 0x0, sum = 3
7908 11:07:02.640307 16, 0x0, sum = 4
7909 11:07:02.640832 best_step = 14
7910 11:07:02.641161
7911 11:07:02.641509 ==
7912 11:07:02.643450 Dram Type= 6, Freq= 0, CH_0, rank 1
7913 11:07:02.650300 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7914 11:07:02.650799 ==
7915 11:07:02.651125 RX Vref Scan: 0
7916 11:07:02.651424
7917 11:07:02.653333 RX Vref 0 -> 0, step: 1
7918 11:07:02.653752
7919 11:07:02.656732 RX Delay 3 -> 252, step: 4
7920 11:07:02.660147 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7921 11:07:02.663368 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7922 11:07:02.666652 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7923 11:07:02.673283 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7924 11:07:02.676621 iDelay=195, Bit 4, Center 128 (71 ~ 186) 116
7925 11:07:02.679802 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7926 11:07:02.683063 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7927 11:07:02.686281 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7928 11:07:02.693310 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
7929 11:07:02.696281 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7930 11:07:02.699645 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7931 11:07:02.702886 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7932 11:07:02.706186 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7933 11:07:02.712704 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7934 11:07:02.716012 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
7935 11:07:02.719483 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7936 11:07:02.719956 ==
7937 11:07:02.722782 Dram Type= 6, Freq= 0, CH_0, rank 1
7938 11:07:02.726133 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7939 11:07:02.729439 ==
7940 11:07:02.729856 DQS Delay:
7941 11:07:02.730181 DQS0 = 0, DQS1 = 0
7942 11:07:02.732615 DQM Delay:
7943 11:07:02.733035 DQM0 = 127, DQM1 = 119
7944 11:07:02.736076 DQ Delay:
7945 11:07:02.739402 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
7946 11:07:02.742723 DQ4 =128, DQ5 =118, DQ6 =136, DQ7 =138
7947 11:07:02.746334 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
7948 11:07:02.749572 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =130
7949 11:07:02.749996
7950 11:07:02.750320
7951 11:07:02.750621
7952 11:07:02.752583 [DramC_TX_OE_Calibration] TA2
7953 11:07:02.755828 Original DQ_B0 (3 6) =30, OEN = 27
7954 11:07:02.759619 Original DQ_B1 (3 6) =30, OEN = 27
7955 11:07:02.760127 24, 0x0, End_B0=24 End_B1=24
7956 11:07:02.762890 25, 0x0, End_B0=25 End_B1=25
7957 11:07:02.766205 26, 0x0, End_B0=26 End_B1=26
7958 11:07:02.769614 27, 0x0, End_B0=27 End_B1=27
7959 11:07:02.772993 28, 0x0, End_B0=28 End_B1=28
7960 11:07:02.773688 29, 0x0, End_B0=29 End_B1=29
7961 11:07:02.775864 30, 0x0, End_B0=30 End_B1=30
7962 11:07:02.779513 31, 0x4141, End_B0=30 End_B1=30
7963 11:07:02.782879 Byte0 end_step=30 best_step=27
7964 11:07:02.785697 Byte1 end_step=30 best_step=27
7965 11:07:02.789729 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 11:07:02.790243 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 11:07:02.790578
7968 11:07:02.790883
7969 11:07:02.799335 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7970 11:07:02.802359 CH0 RK1: MR19=303, MR18=2323
7971 11:07:02.809313 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7972 11:07:02.809762 [RxdqsGatingPostProcess] freq 1600
7973 11:07:02.815699 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7974 11:07:02.818945 Pre-setting of DQS Precalculation
7975 11:07:02.825824 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7976 11:07:02.826298 ==
7977 11:07:02.829071 Dram Type= 6, Freq= 0, CH_1, rank 0
7978 11:07:02.832246 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7979 11:07:02.832677 ==
7980 11:07:02.838736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7981 11:07:02.842226 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7982 11:07:02.845672 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7983 11:07:02.852135 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7984 11:07:02.859722 [CA 0] Center 40 (10~71) winsize 62
7985 11:07:02.862934 [CA 1] Center 40 (10~70) winsize 61
7986 11:07:02.866414 [CA 2] Center 36 (6~66) winsize 61
7987 11:07:02.869936 [CA 3] Center 35 (6~65) winsize 60
7988 11:07:02.873071 [CA 4] Center 33 (4~63) winsize 60
7989 11:07:02.876329 [CA 5] Center 33 (4~63) winsize 60
7990 11:07:02.876868
7991 11:07:02.879734 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7992 11:07:02.880118
7993 11:07:02.882734 [CATrainingPosCal] consider 1 rank data
7994 11:07:02.886525 u2DelayCellTimex100 = 271/100 ps
7995 11:07:02.889276 CA0 delay=40 (10~71),Diff = 7 PI (25 cell)
7996 11:07:02.896694 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
7997 11:07:02.899850 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
7998 11:07:02.902693 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
7999 11:07:02.906060 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8000 11:07:02.909361 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8001 11:07:02.910053
8002 11:07:02.912810 CA PerBit enable=1, Macro0, CA PI delay=33
8003 11:07:02.913532
8004 11:07:02.916089 [CBTSetCACLKResult] CA Dly = 33
8005 11:07:02.919285 CS Dly: 8 (0~39)
8006 11:07:02.922652 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8007 11:07:02.925957 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8008 11:07:02.926626 ==
8009 11:07:02.929401 Dram Type= 6, Freq= 0, CH_1, rank 1
8010 11:07:02.932611 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8011 11:07:02.935769 ==
8012 11:07:02.939562 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8013 11:07:02.942358 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8014 11:07:02.949077 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8015 11:07:02.952231 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8016 11:07:02.961621 [CA 0] Center 40 (10~70) winsize 61
8017 11:07:02.965175 [CA 1] Center 39 (9~70) winsize 62
8018 11:07:02.968351 [CA 2] Center 35 (6~65) winsize 60
8019 11:07:02.971584 [CA 3] Center 35 (6~64) winsize 59
8020 11:07:02.975242 [CA 4] Center 32 (3~62) winsize 60
8021 11:07:02.978497 [CA 5] Center 33 (4~62) winsize 59
8022 11:07:02.978572
8023 11:07:02.981623 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8024 11:07:02.981699
8025 11:07:02.985136 [CATrainingPosCal] consider 2 rank data
8026 11:07:02.988703 u2DelayCellTimex100 = 271/100 ps
8027 11:07:02.991633 CA0 delay=40 (10~70),Diff = 7 PI (25 cell)
8028 11:07:02.998431 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8029 11:07:03.001843 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8030 11:07:03.004865 CA3 delay=35 (6~64),Diff = 2 PI (7 cell)
8031 11:07:03.008404 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8032 11:07:03.011547 CA5 delay=33 (4~62),Diff = 0 PI (0 cell)
8033 11:07:03.011638
8034 11:07:03.015013 CA PerBit enable=1, Macro0, CA PI delay=33
8035 11:07:03.015103
8036 11:07:03.018218 [CBTSetCACLKResult] CA Dly = 33
8037 11:07:03.018314 CS Dly: 9 (0~41)
8038 11:07:03.024712 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8039 11:07:03.028559 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8040 11:07:03.028646
8041 11:07:03.031909 ----->DramcWriteLeveling(PI) begin...
8042 11:07:03.032001 ==
8043 11:07:03.035091 Dram Type= 6, Freq= 0, CH_1, rank 0
8044 11:07:03.038107 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8045 11:07:03.038194 ==
8046 11:07:03.041593 Write leveling (Byte 0): 22 => 22
8047 11:07:03.044918 Write leveling (Byte 1): 21 => 21
8048 11:07:03.048252 DramcWriteLeveling(PI) end<-----
8049 11:07:03.048353
8050 11:07:03.048430 ==
8051 11:07:03.051529 Dram Type= 6, Freq= 0, CH_1, rank 0
8052 11:07:03.058542 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8053 11:07:03.058728 ==
8054 11:07:03.058833 [Gating] SW mode calibration
8055 11:07:03.068493 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8056 11:07:03.071606 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8057 11:07:03.075790 0 12 0 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
8058 11:07:03.081595 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 11:07:03.085128 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 11:07:03.088526 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:07:03.095188 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:07:03.098538 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:07:03.101747 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8064 11:07:03.108121 0 12 28 | B1->B0 | 3434 2828 | 1 1 | (1 1) (0 1)
8065 11:07:03.111530 0 13 0 | B1->B0 | 3131 2424 | 1 0 | (1 0) (1 0)
8066 11:07:03.115128 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 11:07:03.121714 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 11:07:03.124833 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 11:07:03.128420 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:07:03.135045 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:07:03.138031 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:07:03.141445 0 13 28 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8073 11:07:03.148431 0 14 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
8074 11:07:03.151449 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 11:07:03.154870 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:07:03.161359 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:07:03.164911 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:07:03.167910 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:07:03.174897 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 11:07:03.178853 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8081 11:07:03.181348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8082 11:07:03.187813 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8083 11:07:03.191268 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:07:03.195094 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:07:03.198420 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:07:03.205273 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:07:03.208325 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:07:03.211747 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:07:03.218267 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:07:03.221563 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:07:03.224901 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:07:03.231664 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:07:03.234537 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:07:03.238346 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:07:03.244532 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8096 11:07:03.247850 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8097 11:07:03.250879 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8098 11:07:03.254444 Total UI for P1: 0, mck2ui 16
8099 11:07:03.257725 best dqsien dly found for B0: ( 1, 0, 26)
8100 11:07:03.264508 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8101 11:07:03.267555 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 11:07:03.271172 Total UI for P1: 0, mck2ui 16
8103 11:07:03.274354 best dqsien dly found for B1: ( 1, 1, 4)
8104 11:07:03.278293 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8105 11:07:03.280954 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8106 11:07:03.281421
8107 11:07:03.284212 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8108 11:07:03.287484 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8109 11:07:03.290969 [Gating] SW calibration Done
8110 11:07:03.291397 ==
8111 11:07:03.294248 Dram Type= 6, Freq= 0, CH_1, rank 0
8112 11:07:03.297558 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8113 11:07:03.301005 ==
8114 11:07:03.301542 RX Vref Scan: 0
8115 11:07:03.301877
8116 11:07:03.304195 RX Vref 0 -> 0, step: 1
8117 11:07:03.304615
8118 11:07:03.307649 RX Delay 0 -> 252, step: 8
8119 11:07:03.310631 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8120 11:07:03.314242 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8121 11:07:03.317270 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8122 11:07:03.320614 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8123 11:07:03.327614 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8124 11:07:03.330589 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8125 11:07:03.334547 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8126 11:07:03.337440 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8127 11:07:03.341060 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8128 11:07:03.344286 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8129 11:07:03.350580 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8130 11:07:03.353888 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8131 11:07:03.357386 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8132 11:07:03.360885 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8133 11:07:03.367409 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8134 11:07:03.370942 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8135 11:07:03.371434 ==
8136 11:07:03.373661 Dram Type= 6, Freq= 0, CH_1, rank 0
8137 11:07:03.377440 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8138 11:07:03.377871 ==
8139 11:07:03.380166 DQS Delay:
8140 11:07:03.380656 DQS0 = 0, DQS1 = 0
8141 11:07:03.380990 DQM Delay:
8142 11:07:03.383600 DQM0 = 130, DQM1 = 125
8143 11:07:03.384020 DQ Delay:
8144 11:07:03.387005 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8145 11:07:03.390300 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8146 11:07:03.393900 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8147 11:07:03.400616 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8148 11:07:03.401131
8149 11:07:03.401539
8150 11:07:03.401854 ==
8151 11:07:03.403679 Dram Type= 6, Freq= 0, CH_1, rank 0
8152 11:07:03.407160 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8153 11:07:03.407586 ==
8154 11:07:03.407918
8155 11:07:03.408221
8156 11:07:03.410632 TX Vref Scan disable
8157 11:07:03.411131 == TX Byte 0 ==
8158 11:07:03.416935 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8159 11:07:03.420377 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8160 11:07:03.420802 == TX Byte 1 ==
8161 11:07:03.427149 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8162 11:07:03.429991 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8163 11:07:03.430420 ==
8164 11:07:03.433950 Dram Type= 6, Freq= 0, CH_1, rank 0
8165 11:07:03.436535 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8166 11:07:03.436970 ==
8167 11:07:03.451058
8168 11:07:03.454521 TX Vref early break, caculate TX vref
8169 11:07:03.457972 TX Vref=16, minBit 0, minWin=21, winSum=367
8170 11:07:03.461130 TX Vref=18, minBit 1, minWin=22, winSum=376
8171 11:07:03.464654 TX Vref=20, minBit 1, minWin=23, winSum=388
8172 11:07:03.467528 TX Vref=22, minBit 1, minWin=23, winSum=398
8173 11:07:03.471106 TX Vref=24, minBit 0, minWin=24, winSum=401
8174 11:07:03.477674 TX Vref=26, minBit 0, minWin=24, winSum=412
8175 11:07:03.481508 TX Vref=28, minBit 0, minWin=25, winSum=411
8176 11:07:03.484346 TX Vref=30, minBit 1, minWin=24, winSum=408
8177 11:07:03.487811 TX Vref=32, minBit 3, minWin=23, winSum=397
8178 11:07:03.490798 TX Vref=34, minBit 3, minWin=23, winSum=391
8179 11:07:03.494667 TX Vref=36, minBit 3, minWin=22, winSum=378
8180 11:07:03.501264 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 28
8181 11:07:03.501772
8182 11:07:03.504470 Final TX Range 0 Vref 28
8183 11:07:03.504893
8184 11:07:03.505220 ==
8185 11:07:03.507996 Dram Type= 6, Freq= 0, CH_1, rank 0
8186 11:07:03.511065 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8187 11:07:03.511681 ==
8188 11:07:03.512147
8189 11:07:03.512468
8190 11:07:03.514445 TX Vref Scan disable
8191 11:07:03.521081 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8192 11:07:03.521543 == TX Byte 0 ==
8193 11:07:03.524248 u2DelayCellOfst[0]=18 cells (5 PI)
8194 11:07:03.528550 u2DelayCellOfst[1]=10 cells (3 PI)
8195 11:07:03.531489 u2DelayCellOfst[2]=0 cells (0 PI)
8196 11:07:03.533905 u2DelayCellOfst[3]=7 cells (2 PI)
8197 11:07:03.537307 u2DelayCellOfst[4]=10 cells (3 PI)
8198 11:07:03.541123 u2DelayCellOfst[5]=18 cells (5 PI)
8199 11:07:03.544625 u2DelayCellOfst[6]=18 cells (5 PI)
8200 11:07:03.547730 u2DelayCellOfst[7]=7 cells (2 PI)
8201 11:07:03.550973 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8202 11:07:03.554037 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8203 11:07:03.557652 == TX Byte 1 ==
8204 11:07:03.560948 u2DelayCellOfst[8]=0 cells (0 PI)
8205 11:07:03.561489 u2DelayCellOfst[9]=7 cells (2 PI)
8206 11:07:03.564647 u2DelayCellOfst[10]=10 cells (3 PI)
8207 11:07:03.568138 u2DelayCellOfst[11]=3 cells (1 PI)
8208 11:07:03.570870 u2DelayCellOfst[12]=18 cells (5 PI)
8209 11:07:03.574170 u2DelayCellOfst[13]=18 cells (5 PI)
8210 11:07:03.577648 u2DelayCellOfst[14]=18 cells (5 PI)
8211 11:07:03.580562 u2DelayCellOfst[15]=18 cells (5 PI)
8212 11:07:03.584022 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8213 11:07:03.590469 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8214 11:07:03.590900 DramC Write-DBI on
8215 11:07:03.591232 ==
8216 11:07:03.593965 Dram Type= 6, Freq= 0, CH_1, rank 0
8217 11:07:03.600656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8218 11:07:03.601162 ==
8219 11:07:03.601537
8220 11:07:03.601840
8221 11:07:03.602129 TX Vref Scan disable
8222 11:07:03.604188 == TX Byte 0 ==
8223 11:07:03.607603 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8224 11:07:03.611078 == TX Byte 1 ==
8225 11:07:03.614382 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8226 11:07:03.617302 DramC Write-DBI off
8227 11:07:03.617733
8228 11:07:03.618192 [DATLAT]
8229 11:07:03.618638 Freq=1600, CH1 RK0
8230 11:07:03.618954
8231 11:07:03.620913 DATLAT Default: 0xf
8232 11:07:03.621366 0, 0xFFFF, sum = 0
8233 11:07:03.624670 1, 0xFFFF, sum = 0
8234 11:07:03.625214 2, 0xFFFF, sum = 0
8235 11:07:03.627717 3, 0xFFFF, sum = 0
8236 11:07:03.628359 4, 0xFFFF, sum = 0
8237 11:07:03.631020 5, 0xFFFF, sum = 0
8238 11:07:03.634765 6, 0xFFFF, sum = 0
8239 11:07:03.635274 7, 0xFFFF, sum = 0
8240 11:07:03.637523 8, 0xFFFF, sum = 0
8241 11:07:03.637973 9, 0xFFFF, sum = 0
8242 11:07:03.641021 10, 0xFFFF, sum = 0
8243 11:07:03.641518 11, 0xFFFF, sum = 0
8244 11:07:03.643970 12, 0xFFF, sum = 0
8245 11:07:03.644404 13, 0x0, sum = 1
8246 11:07:03.647577 14, 0x0, sum = 2
8247 11:07:03.648085 15, 0x0, sum = 3
8248 11:07:03.650885 16, 0x0, sum = 4
8249 11:07:03.651392 best_step = 14
8250 11:07:03.651725
8251 11:07:03.652031 ==
8252 11:07:03.654163 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 11:07:03.657589 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8254 11:07:03.658088 ==
8255 11:07:03.661009 RX Vref Scan: 1
8256 11:07:03.661622
8257 11:07:03.664140 Set Vref Range= 24 -> 127
8258 11:07:03.664637
8259 11:07:03.664965 RX Vref 24 -> 127, step: 1
8260 11:07:03.667421
8261 11:07:03.667962 RX Delay 3 -> 252, step: 4
8262 11:07:03.668311
8263 11:07:03.670664 Set Vref, RX VrefLevel [Byte0]: 24
8264 11:07:03.674140 [Byte1]: 24
8265 11:07:03.677962
8266 11:07:03.678460 Set Vref, RX VrefLevel [Byte0]: 25
8267 11:07:03.680543 [Byte1]: 25
8268 11:07:03.684961
8269 11:07:03.685191 Set Vref, RX VrefLevel [Byte0]: 26
8270 11:07:03.688216 [Byte1]: 26
8271 11:07:03.692672
8272 11:07:03.692903 Set Vref, RX VrefLevel [Byte0]: 27
8273 11:07:03.696056 [Byte1]: 27
8274 11:07:03.700472
8275 11:07:03.700704 Set Vref, RX VrefLevel [Byte0]: 28
8276 11:07:03.703818 [Byte1]: 28
8277 11:07:03.707744
8278 11:07:03.707981 Set Vref, RX VrefLevel [Byte0]: 29
8279 11:07:03.711119 [Byte1]: 29
8280 11:07:03.715412
8281 11:07:03.715659 Set Vref, RX VrefLevel [Byte0]: 30
8282 11:07:03.718873 [Byte1]: 30
8283 11:07:03.723744
8284 11:07:03.724118 Set Vref, RX VrefLevel [Byte0]: 31
8285 11:07:03.726689 [Byte1]: 31
8286 11:07:03.731131
8287 11:07:03.731630 Set Vref, RX VrefLevel [Byte0]: 32
8288 11:07:03.734165 [Byte1]: 32
8289 11:07:03.738825
8290 11:07:03.739275 Set Vref, RX VrefLevel [Byte0]: 33
8291 11:07:03.742016 [Byte1]: 33
8292 11:07:03.746421
8293 11:07:03.746839 Set Vref, RX VrefLevel [Byte0]: 34
8294 11:07:03.749737 [Byte1]: 34
8295 11:07:03.754088
8296 11:07:03.754522 Set Vref, RX VrefLevel [Byte0]: 35
8297 11:07:03.757508 [Byte1]: 35
8298 11:07:03.761967
8299 11:07:03.762470 Set Vref, RX VrefLevel [Byte0]: 36
8300 11:07:03.764841 [Byte1]: 36
8301 11:07:03.769530
8302 11:07:03.770026 Set Vref, RX VrefLevel [Byte0]: 37
8303 11:07:03.772535 [Byte1]: 37
8304 11:07:03.776666
8305 11:07:03.777082 Set Vref, RX VrefLevel [Byte0]: 38
8306 11:07:03.780010 [Byte1]: 38
8307 11:07:03.784565
8308 11:07:03.784981 Set Vref, RX VrefLevel [Byte0]: 39
8309 11:07:03.787667 [Byte1]: 39
8310 11:07:03.792123
8311 11:07:03.792541 Set Vref, RX VrefLevel [Byte0]: 40
8312 11:07:03.795778 [Byte1]: 40
8313 11:07:03.800087
8314 11:07:03.800585 Set Vref, RX VrefLevel [Byte0]: 41
8315 11:07:03.803358 [Byte1]: 41
8316 11:07:03.807713
8317 11:07:03.808203 Set Vref, RX VrefLevel [Byte0]: 42
8318 11:07:03.810800 [Byte1]: 42
8319 11:07:03.815327
8320 11:07:03.815828 Set Vref, RX VrefLevel [Byte0]: 43
8321 11:07:03.818259 [Byte1]: 43
8322 11:07:03.823007
8323 11:07:03.823495 Set Vref, RX VrefLevel [Byte0]: 44
8324 11:07:03.826041 [Byte1]: 44
8325 11:07:03.830475
8326 11:07:03.830963 Set Vref, RX VrefLevel [Byte0]: 45
8327 11:07:03.833785 [Byte1]: 45
8328 11:07:03.838152
8329 11:07:03.838571 Set Vref, RX VrefLevel [Byte0]: 46
8330 11:07:03.841643 [Byte1]: 46
8331 11:07:03.845933
8332 11:07:03.846351 Set Vref, RX VrefLevel [Byte0]: 47
8333 11:07:03.849291 [Byte1]: 47
8334 11:07:03.853690
8335 11:07:03.854105 Set Vref, RX VrefLevel [Byte0]: 48
8336 11:07:03.857118 [Byte1]: 48
8337 11:07:03.861149
8338 11:07:03.861692 Set Vref, RX VrefLevel [Byte0]: 49
8339 11:07:03.864905 [Byte1]: 49
8340 11:07:03.869124
8341 11:07:03.869655 Set Vref, RX VrefLevel [Byte0]: 50
8342 11:07:03.872073 [Byte1]: 50
8343 11:07:03.876802
8344 11:07:03.877322 Set Vref, RX VrefLevel [Byte0]: 51
8345 11:07:03.879963 [Byte1]: 51
8346 11:07:03.884392
8347 11:07:03.884895 Set Vref, RX VrefLevel [Byte0]: 52
8348 11:07:03.887355 [Byte1]: 52
8349 11:07:03.891638
8350 11:07:03.892053 Set Vref, RX VrefLevel [Byte0]: 53
8351 11:07:03.894802 [Byte1]: 53
8352 11:07:03.899473
8353 11:07:03.899971 Set Vref, RX VrefLevel [Byte0]: 54
8354 11:07:03.902737 [Byte1]: 54
8355 11:07:03.907416
8356 11:07:03.907907 Set Vref, RX VrefLevel [Byte0]: 55
8357 11:07:03.910363 [Byte1]: 55
8358 11:07:03.914625
8359 11:07:03.915145 Set Vref, RX VrefLevel [Byte0]: 56
8360 11:07:03.918619 [Byte1]: 56
8361 11:07:03.922379
8362 11:07:03.922800 Set Vref, RX VrefLevel [Byte0]: 57
8363 11:07:03.926071 [Byte1]: 57
8364 11:07:03.930234
8365 11:07:03.930722 Set Vref, RX VrefLevel [Byte0]: 58
8366 11:07:03.933841 [Byte1]: 58
8367 11:07:03.937472
8368 11:07:03.937894 Set Vref, RX VrefLevel [Byte0]: 59
8369 11:07:03.940924 [Byte1]: 59
8370 11:07:03.945551
8371 11:07:03.945966 Set Vref, RX VrefLevel [Byte0]: 60
8372 11:07:03.948976 [Byte1]: 60
8373 11:07:03.953039
8374 11:07:03.953577 Set Vref, RX VrefLevel [Byte0]: 61
8375 11:07:03.956404 [Byte1]: 61
8376 11:07:03.960827
8377 11:07:03.961275 Set Vref, RX VrefLevel [Byte0]: 62
8378 11:07:03.963756 [Byte1]: 62
8379 11:07:03.968276
8380 11:07:03.968697 Set Vref, RX VrefLevel [Byte0]: 63
8381 11:07:03.971444 [Byte1]: 63
8382 11:07:03.976120
8383 11:07:03.976553 Set Vref, RX VrefLevel [Byte0]: 64
8384 11:07:03.979205 [Byte1]: 64
8385 11:07:03.983765
8386 11:07:03.984191 Set Vref, RX VrefLevel [Byte0]: 65
8387 11:07:03.986677 [Byte1]: 65
8388 11:07:03.991296
8389 11:07:03.991775 Set Vref, RX VrefLevel [Byte0]: 66
8390 11:07:03.994396 [Byte1]: 66
8391 11:07:03.998832
8392 11:07:03.999253 Set Vref, RX VrefLevel [Byte0]: 67
8393 11:07:04.002123 [Byte1]: 67
8394 11:07:04.006822
8395 11:07:04.007247 Set Vref, RX VrefLevel [Byte0]: 68
8396 11:07:04.009786 [Byte1]: 68
8397 11:07:04.014046
8398 11:07:04.014468 Set Vref, RX VrefLevel [Byte0]: 69
8399 11:07:04.017457 [Byte1]: 69
8400 11:07:04.022027
8401 11:07:04.022453 Set Vref, RX VrefLevel [Byte0]: 70
8402 11:07:04.024822 [Byte1]: 70
8403 11:07:04.029630
8404 11:07:04.030139 Set Vref, RX VrefLevel [Byte0]: 71
8405 11:07:04.033173 [Byte1]: 71
8406 11:07:04.037141
8407 11:07:04.037708 Set Vref, RX VrefLevel [Byte0]: 72
8408 11:07:04.040291 [Byte1]: 72
8409 11:07:04.044541
8410 11:07:04.044966 Set Vref, RX VrefLevel [Byte0]: 73
8411 11:07:04.048165 [Byte1]: 73
8412 11:07:04.052251
8413 11:07:04.052677 Set Vref, RX VrefLevel [Byte0]: 74
8414 11:07:04.055589 [Byte1]: 74
8415 11:07:04.059918
8416 11:07:04.060340 Set Vref, RX VrefLevel [Byte0]: 75
8417 11:07:04.063569 [Byte1]: 75
8418 11:07:04.067656
8419 11:07:04.068076 Final RX Vref Byte 0 = 63 to rank0
8420 11:07:04.071334 Final RX Vref Byte 1 = 53 to rank0
8421 11:07:04.074631 Final RX Vref Byte 0 = 63 to rank1
8422 11:07:04.077429 Final RX Vref Byte 1 = 53 to rank1==
8423 11:07:04.081347 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 11:07:04.087633 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8425 11:07:04.088064 ==
8426 11:07:04.088393 DQS Delay:
8427 11:07:04.088795 DQS0 = 0, DQS1 = 0
8428 11:07:04.091362 DQM Delay:
8429 11:07:04.091978 DQM0 = 128, DQM1 = 124
8430 11:07:04.094247 DQ Delay:
8431 11:07:04.097459 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8432 11:07:04.100759 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =124
8433 11:07:04.104230 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8434 11:07:04.107329 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8435 11:07:04.107748
8436 11:07:04.108072
8437 11:07:04.108370
8438 11:07:04.110949 [DramC_TX_OE_Calibration] TA2
8439 11:07:04.114312 Original DQ_B0 (3 6) =30, OEN = 27
8440 11:07:04.117179 Original DQ_B1 (3 6) =30, OEN = 27
8441 11:07:04.120459 24, 0x0, End_B0=24 End_B1=24
8442 11:07:04.120912 25, 0x0, End_B0=25 End_B1=25
8443 11:07:04.123909 26, 0x0, End_B0=26 End_B1=26
8444 11:07:04.126989 27, 0x0, End_B0=27 End_B1=27
8445 11:07:04.130327 28, 0x0, End_B0=28 End_B1=28
8446 11:07:04.134099 29, 0x0, End_B0=29 End_B1=29
8447 11:07:04.134678 30, 0x0, End_B0=30 End_B1=30
8448 11:07:04.136931 31, 0x4141, End_B0=30 End_B1=30
8449 11:07:04.140259 Byte0 end_step=30 best_step=27
8450 11:07:04.144154 Byte1 end_step=30 best_step=27
8451 11:07:04.147188 Byte0 TX OE(2T, 0.5T) = (3, 3)
8452 11:07:04.150331 Byte1 TX OE(2T, 0.5T) = (3, 3)
8453 11:07:04.150755
8454 11:07:04.151078
8455 11:07:04.156998 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8456 11:07:04.160337 CH1 RK0: MR19=303, MR18=2828
8457 11:07:04.166828 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8458 11:07:04.167252
8459 11:07:04.170414 ----->DramcWriteLeveling(PI) begin...
8460 11:07:04.170841 ==
8461 11:07:04.173432 Dram Type= 6, Freq= 0, CH_1, rank 1
8462 11:07:04.176803 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8463 11:07:04.177261 ==
8464 11:07:04.179960 Write leveling (Byte 0): 22 => 22
8465 11:07:04.183599 Write leveling (Byte 1): 21 => 21
8466 11:07:04.186721 DramcWriteLeveling(PI) end<-----
8467 11:07:04.187102
8468 11:07:04.187399 ==
8469 11:07:04.190192 Dram Type= 6, Freq= 0, CH_1, rank 1
8470 11:07:04.193525 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8471 11:07:04.193911 ==
8472 11:07:04.196989 [Gating] SW mode calibration
8473 11:07:04.203284 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8474 11:07:04.210236 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8475 11:07:04.213067 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 11:07:04.219837 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 11:07:04.223181 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 11:07:04.226662 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 11:07:04.233126 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 11:07:04.236751 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8481 11:07:04.240103 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8482 11:07:04.246760 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8483 11:07:04.249570 0 13 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8484 11:07:04.253381 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 11:07:04.259773 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 11:07:04.263330 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 11:07:04.266454 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 11:07:04.269514 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 11:07:04.276445 0 13 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8490 11:07:04.279561 0 13 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8491 11:07:04.282976 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 11:07:04.289872 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 11:07:04.293015 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 11:07:04.297002 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 11:07:04.303189 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 11:07:04.306097 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 11:07:04.309460 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8498 11:07:04.316285 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8499 11:07:04.320031 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8500 11:07:04.322749 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8501 11:07:04.329599 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 11:07:04.333124 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 11:07:04.336205 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 11:07:04.343333 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 11:07:04.346180 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 11:07:04.349592 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 11:07:04.355933 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 11:07:04.359612 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 11:07:04.362542 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 11:07:04.369158 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 11:07:04.372749 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 11:07:04.376048 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8513 11:07:04.382577 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8514 11:07:04.385938 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8515 11:07:04.388895 Total UI for P1: 0, mck2ui 16
8516 11:07:04.392418 best dqsien dly found for B0: ( 1, 0, 22)
8517 11:07:04.395750 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8518 11:07:04.399015 Total UI for P1: 0, mck2ui 16
8519 11:07:04.402085 best dqsien dly found for B1: ( 1, 0, 28)
8520 11:07:04.405759 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8521 11:07:04.409063 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8522 11:07:04.409630
8523 11:07:04.415351 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8524 11:07:04.418845 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8525 11:07:04.419347 [Gating] SW calibration Done
8526 11:07:04.422376 ==
8527 11:07:04.425343 Dram Type= 6, Freq= 0, CH_1, rank 1
8528 11:07:04.428810 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8529 11:07:04.429261 ==
8530 11:07:04.429596 RX Vref Scan: 0
8531 11:07:04.429899
8532 11:07:04.432059 RX Vref 0 -> 0, step: 1
8533 11:07:04.432548
8534 11:07:04.435588 RX Delay 0 -> 252, step: 8
8535 11:07:04.438634 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8536 11:07:04.442140 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8537 11:07:04.445585 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8538 11:07:04.452355 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8539 11:07:04.455135 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8540 11:07:04.458705 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8541 11:07:04.462154 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8542 11:07:04.465426 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8543 11:07:04.472081 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8544 11:07:04.475706 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8545 11:07:04.478451 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8546 11:07:04.482166 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8547 11:07:04.485291 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8548 11:07:04.492471 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8549 11:07:04.495646 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8550 11:07:04.498650 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8551 11:07:04.499148 ==
8552 11:07:04.501957 Dram Type= 6, Freq= 0, CH_1, rank 1
8553 11:07:04.505133 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8554 11:07:04.505683 ==
8555 11:07:04.508656 DQS Delay:
8556 11:07:04.509150 DQS0 = 0, DQS1 = 0
8557 11:07:04.511977 DQM Delay:
8558 11:07:04.512471 DQM0 = 131, DQM1 = 125
8559 11:07:04.514862 DQ Delay:
8560 11:07:04.518278 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8561 11:07:04.521736 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8562 11:07:04.524858 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8563 11:07:04.528752 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =131
8564 11:07:04.529288
8565 11:07:04.529631
8566 11:07:04.529935 ==
8567 11:07:04.532030 Dram Type= 6, Freq= 0, CH_1, rank 1
8568 11:07:04.535191 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8569 11:07:04.535691 ==
8570 11:07:04.536024
8571 11:07:04.536326
8572 11:07:04.538433 TX Vref Scan disable
8573 11:07:04.541856 == TX Byte 0 ==
8574 11:07:04.545355 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8575 11:07:04.548123 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8576 11:07:04.551597 == TX Byte 1 ==
8577 11:07:04.554729 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8578 11:07:04.557986 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8579 11:07:04.558411 ==
8580 11:07:04.561642 Dram Type= 6, Freq= 0, CH_1, rank 1
8581 11:07:04.568290 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8582 11:07:04.568792 ==
8583 11:07:04.579215
8584 11:07:04.582345 TX Vref early break, caculate TX vref
8585 11:07:04.586168 TX Vref=16, minBit 0, minWin=22, winSum=380
8586 11:07:04.589189 TX Vref=18, minBit 0, minWin=23, winSum=389
8587 11:07:04.592264 TX Vref=20, minBit 0, minWin=24, winSum=398
8588 11:07:04.596323 TX Vref=22, minBit 3, minWin=24, winSum=407
8589 11:07:04.599436 TX Vref=24, minBit 0, minWin=25, winSum=413
8590 11:07:04.605829 TX Vref=26, minBit 0, minWin=25, winSum=423
8591 11:07:04.609346 TX Vref=28, minBit 0, minWin=25, winSum=420
8592 11:07:04.612694 TX Vref=30, minBit 0, minWin=24, winSum=416
8593 11:07:04.615931 TX Vref=32, minBit 0, minWin=23, winSum=406
8594 11:07:04.619048 TX Vref=34, minBit 0, minWin=22, winSum=395
8595 11:07:04.625618 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8596 11:07:04.626119
8597 11:07:04.629422 Final TX Range 0 Vref 26
8598 11:07:04.629922
8599 11:07:04.630253 ==
8600 11:07:04.632385 Dram Type= 6, Freq= 0, CH_1, rank 1
8601 11:07:04.635839 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8602 11:07:04.636346 ==
8603 11:07:04.636679
8604 11:07:04.636981
8605 11:07:04.639129 TX Vref Scan disable
8606 11:07:04.645899 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8607 11:07:04.646402 == TX Byte 0 ==
8608 11:07:04.649315 u2DelayCellOfst[0]=18 cells (5 PI)
8609 11:07:04.652491 u2DelayCellOfst[1]=10 cells (3 PI)
8610 11:07:04.655386 u2DelayCellOfst[2]=0 cells (0 PI)
8611 11:07:04.658878 u2DelayCellOfst[3]=10 cells (3 PI)
8612 11:07:04.662218 u2DelayCellOfst[4]=10 cells (3 PI)
8613 11:07:04.665714 u2DelayCellOfst[5]=18 cells (5 PI)
8614 11:07:04.669117 u2DelayCellOfst[6]=18 cells (5 PI)
8615 11:07:04.669645 u2DelayCellOfst[7]=7 cells (2 PI)
8616 11:07:04.675671 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8617 11:07:04.678980 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8618 11:07:04.679488 == TX Byte 1 ==
8619 11:07:04.682456 u2DelayCellOfst[8]=0 cells (0 PI)
8620 11:07:04.685250 u2DelayCellOfst[9]=3 cells (1 PI)
8621 11:07:04.688972 u2DelayCellOfst[10]=10 cells (3 PI)
8622 11:07:04.692061 u2DelayCellOfst[11]=3 cells (1 PI)
8623 11:07:04.695196 u2DelayCellOfst[12]=14 cells (4 PI)
8624 11:07:04.698865 u2DelayCellOfst[13]=18 cells (5 PI)
8625 11:07:04.702260 u2DelayCellOfst[14]=18 cells (5 PI)
8626 11:07:04.705371 u2DelayCellOfst[15]=18 cells (5 PI)
8627 11:07:04.708782 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8628 11:07:04.715323 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8629 11:07:04.715825 DramC Write-DBI on
8630 11:07:04.716159 ==
8631 11:07:04.718511 Dram Type= 6, Freq= 0, CH_1, rank 1
8632 11:07:04.722191 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8633 11:07:04.725330 ==
8634 11:07:04.725838
8635 11:07:04.726166
8636 11:07:04.726472 TX Vref Scan disable
8637 11:07:04.728482 == TX Byte 0 ==
8638 11:07:04.731878 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8639 11:07:04.735650 == TX Byte 1 ==
8640 11:07:04.738371 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8641 11:07:04.741917 DramC Write-DBI off
8642 11:07:04.742414
8643 11:07:04.742740 [DATLAT]
8644 11:07:04.743044 Freq=1600, CH1 RK1
8645 11:07:04.743336
8646 11:07:04.745346 DATLAT Default: 0xe
8647 11:07:04.745771 0, 0xFFFF, sum = 0
8648 11:07:04.748857 1, 0xFFFF, sum = 0
8649 11:07:04.751776 2, 0xFFFF, sum = 0
8650 11:07:04.752340 3, 0xFFFF, sum = 0
8651 11:07:04.755152 4, 0xFFFF, sum = 0
8652 11:07:04.755582 5, 0xFFFF, sum = 0
8653 11:07:04.758461 6, 0xFFFF, sum = 0
8654 11:07:04.758986 7, 0xFFFF, sum = 0
8655 11:07:04.761558 8, 0xFFFF, sum = 0
8656 11:07:04.761991 9, 0xFFFF, sum = 0
8657 11:07:04.765307 10, 0xFFFF, sum = 0
8658 11:07:04.765819 11, 0xFFFF, sum = 0
8659 11:07:04.768762 12, 0xF7F, sum = 0
8660 11:07:04.769298 13, 0x0, sum = 1
8661 11:07:04.771803 14, 0x0, sum = 2
8662 11:07:04.772307 15, 0x0, sum = 3
8663 11:07:04.775431 16, 0x0, sum = 4
8664 11:07:04.775934 best_step = 14
8665 11:07:04.776264
8666 11:07:04.776570 ==
8667 11:07:04.778440 Dram Type= 6, Freq= 0, CH_1, rank 1
8668 11:07:04.781723 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8669 11:07:04.782149 ==
8670 11:07:04.784662 RX Vref Scan: 0
8671 11:07:04.785080
8672 11:07:04.788550 RX Vref 0 -> 0, step: 1
8673 11:07:04.789044
8674 11:07:04.789513 RX Delay 3 -> 252, step: 4
8675 11:07:04.795272 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8676 11:07:04.798973 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8677 11:07:04.802034 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8678 11:07:04.805911 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8679 11:07:04.808485 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8680 11:07:04.815668 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8681 11:07:04.818583 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8682 11:07:04.822338 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8683 11:07:04.825318 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8684 11:07:04.828445 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8685 11:07:04.835468 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8686 11:07:04.838609 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8687 11:07:04.842164 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8688 11:07:04.845491 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8689 11:07:04.852421 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8690 11:07:04.854992 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8691 11:07:04.855418 ==
8692 11:07:04.858626 Dram Type= 6, Freq= 0, CH_1, rank 1
8693 11:07:04.862123 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8694 11:07:04.862623 ==
8695 11:07:04.862951 DQS Delay:
8696 11:07:04.865016 DQS0 = 0, DQS1 = 0
8697 11:07:04.865549 DQM Delay:
8698 11:07:04.869042 DQM0 = 126, DQM1 = 122
8699 11:07:04.869595 DQ Delay:
8700 11:07:04.872149 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8701 11:07:04.876011 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8702 11:07:04.879167 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8703 11:07:04.882071 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8704 11:07:04.884956
8705 11:07:04.885431
8706 11:07:04.885763
8707 11:07:04.886065 [DramC_TX_OE_Calibration] TA2
8708 11:07:04.888544 Original DQ_B0 (3 6) =30, OEN = 27
8709 11:07:04.892298 Original DQ_B1 (3 6) =30, OEN = 27
8710 11:07:04.895113 24, 0x0, End_B0=24 End_B1=24
8711 11:07:04.898385 25, 0x0, End_B0=25 End_B1=25
8712 11:07:04.901790 26, 0x0, End_B0=26 End_B1=26
8713 11:07:04.902299 27, 0x0, End_B0=27 End_B1=27
8714 11:07:04.905032 28, 0x0, End_B0=28 End_B1=28
8715 11:07:04.908164 29, 0x0, End_B0=29 End_B1=29
8716 11:07:04.911495 30, 0x0, End_B0=30 End_B1=30
8717 11:07:04.915172 31, 0x4141, End_B0=30 End_B1=30
8718 11:07:04.918308 Byte0 end_step=30 best_step=27
8719 11:07:04.918729 Byte1 end_step=30 best_step=27
8720 11:07:04.921699 Byte0 TX OE(2T, 0.5T) = (3, 3)
8721 11:07:04.925105 Byte1 TX OE(2T, 0.5T) = (3, 3)
8722 11:07:04.925572
8723 11:07:04.925899
8724 11:07:04.935101 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8725 11:07:04.935600 CH1 RK1: MR19=303, MR18=1F1F
8726 11:07:04.941693 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8727 11:07:04.945099 [RxdqsGatingPostProcess] freq 1600
8728 11:07:04.951441 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8729 11:07:04.954665 Pre-setting of DQS Precalculation
8730 11:07:04.957918 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8731 11:07:04.964995 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8732 11:07:04.974737 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8733 11:07:04.975236
8734 11:07:04.975561
8735 11:07:04.977889 [Calibration Summary] 3200 Mbps
8736 11:07:04.978325 CH 0, Rank 0
8737 11:07:04.981135 SW Impedance : PASS
8738 11:07:04.981604 DUTY Scan : NO K
8739 11:07:04.985166 ZQ Calibration : PASS
8740 11:07:04.987729 Jitter Meter : NO K
8741 11:07:04.987893 CBT Training : PASS
8742 11:07:04.991115 Write leveling : PASS
8743 11:07:04.991536 RX DQS gating : PASS
8744 11:07:04.994529 RX DQ/DQS(RDDQC) : PASS
8745 11:07:04.997723 TX DQ/DQS : PASS
8746 11:07:04.998147 RX DATLAT : PASS
8747 11:07:05.001058 RX DQ/DQS(Engine): PASS
8748 11:07:05.005165 TX OE : PASS
8749 11:07:05.005697 All Pass.
8750 11:07:05.006026
8751 11:07:05.006326 CH 0, Rank 1
8752 11:07:05.007690 SW Impedance : PASS
8753 11:07:05.011137 DUTY Scan : NO K
8754 11:07:05.011561 ZQ Calibration : PASS
8755 11:07:05.014783 Jitter Meter : NO K
8756 11:07:05.018094 CBT Training : PASS
8757 11:07:05.018594 Write leveling : PASS
8758 11:07:05.021318 RX DQS gating : PASS
8759 11:07:05.024439 RX DQ/DQS(RDDQC) : PASS
8760 11:07:05.024858 TX DQ/DQS : PASS
8761 11:07:05.027735 RX DATLAT : PASS
8762 11:07:05.030913 RX DQ/DQS(Engine): PASS
8763 11:07:05.031422 TX OE : PASS
8764 11:07:05.031845 All Pass.
8765 11:07:05.034369
8766 11:07:05.034961 CH 1, Rank 0
8767 11:07:05.038079 SW Impedance : PASS
8768 11:07:05.038599 DUTY Scan : NO K
8769 11:07:05.041141 ZQ Calibration : PASS
8770 11:07:05.041698 Jitter Meter : NO K
8771 11:07:05.044290 CBT Training : PASS
8772 11:07:05.047747 Write leveling : PASS
8773 11:07:05.048257 RX DQS gating : PASS
8774 11:07:05.050806 RX DQ/DQS(RDDQC) : PASS
8775 11:07:05.054419 TX DQ/DQS : PASS
8776 11:07:05.054846 RX DATLAT : PASS
8777 11:07:05.057722 RX DQ/DQS(Engine): PASS
8778 11:07:05.060999 TX OE : PASS
8779 11:07:05.061517 All Pass.
8780 11:07:05.061932
8781 11:07:05.062240 CH 1, Rank 1
8782 11:07:05.064415 SW Impedance : PASS
8783 11:07:05.067450 DUTY Scan : NO K
8784 11:07:05.067832 ZQ Calibration : PASS
8785 11:07:05.070925 Jitter Meter : NO K
8786 11:07:05.073793 CBT Training : PASS
8787 11:07:05.074174 Write leveling : PASS
8788 11:07:05.077011 RX DQS gating : PASS
8789 11:07:05.080516 RX DQ/DQS(RDDQC) : PASS
8790 11:07:05.080893 TX DQ/DQS : PASS
8791 11:07:05.083906 RX DATLAT : PASS
8792 11:07:05.087163 RX DQ/DQS(Engine): PASS
8793 11:07:05.087623 TX OE : PASS
8794 11:07:05.090303 All Pass.
8795 11:07:05.090695
8796 11:07:05.090988 DramC Write-DBI on
8797 11:07:05.093565 PER_BANK_REFRESH: Hybrid Mode
8798 11:07:05.094137 TX_TRACKING: ON
8799 11:07:05.103749 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8800 11:07:05.110402 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8801 11:07:05.120312 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8802 11:07:05.123521 [FAST_K] Save calibration result to emmc
8803 11:07:05.126958 sync common calibartion params.
8804 11:07:05.127337 sync cbt_mode0:0, 1:0
8805 11:07:05.130186 dram_init: ddr_geometry: 0
8806 11:07:05.133726 dram_init: ddr_geometry: 0
8807 11:07:05.134105 dram_init: ddr_geometry: 0
8808 11:07:05.137491 0:dram_rank_size:80000000
8809 11:07:05.140149 1:dram_rank_size:80000000
8810 11:07:05.143479 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8811 11:07:05.147013 DFS_SHUFFLE_HW_MODE: ON
8812 11:07:05.149923 dramc_set_vcore_voltage set vcore to 725000
8813 11:07:05.153360 Read voltage for 1600, 0
8814 11:07:05.153760 Vio18 = 0
8815 11:07:05.157481 Vcore = 725000
8816 11:07:05.157859 Vdram = 0
8817 11:07:05.158150 Vddq = 0
8818 11:07:05.158422 Vmddr = 0
8819 11:07:05.159901 switch to 3200 Mbps bootup
8820 11:07:05.163494 [DramcRunTimeConfig]
8821 11:07:05.163875 PHYPLL
8822 11:07:05.166538 DPM_CONTROL_AFTERK: ON
8823 11:07:05.166920 PER_BANK_REFRESH: ON
8824 11:07:05.169970 REFRESH_OVERHEAD_REDUCTION: ON
8825 11:07:05.173562 CMD_PICG_NEW_MODE: OFF
8826 11:07:05.173940 XRTWTW_NEW_MODE: ON
8827 11:07:05.176422 XRTRTR_NEW_MODE: ON
8828 11:07:05.176803 TX_TRACKING: ON
8829 11:07:05.179775 RDSEL_TRACKING: OFF
8830 11:07:05.183348 DQS Precalculation for DVFS: ON
8831 11:07:05.183772 RX_TRACKING: OFF
8832 11:07:05.184076 HW_GATING DBG: ON
8833 11:07:05.186443 ZQCS_ENABLE_LP4: ON
8834 11:07:05.190253 RX_PICG_NEW_MODE: ON
8835 11:07:05.190637 TX_PICG_NEW_MODE: ON
8836 11:07:05.193321 ENABLE_RX_DCM_DPHY: ON
8837 11:07:05.196548 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8838 11:07:05.199851 DUMMY_READ_FOR_TRACKING: OFF
8839 11:07:05.200229 !!! SPM_CONTROL_AFTERK: OFF
8840 11:07:05.202969 !!! SPM could not control APHY
8841 11:07:05.206620 IMPEDANCE_TRACKING: ON
8842 11:07:05.207052 TEMP_SENSOR: ON
8843 11:07:05.210116 HW_SAVE_FOR_SR: OFF
8844 11:07:05.213155 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8845 11:07:05.216372 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8846 11:07:05.216753 Read ODT Tracking: ON
8847 11:07:05.219835 Refresh Rate DeBounce: ON
8848 11:07:05.223108 DFS_NO_QUEUE_FLUSH: ON
8849 11:07:05.226505 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8850 11:07:05.226884 ENABLE_DFS_RUNTIME_MRW: OFF
8851 11:07:05.229657 DDR_RESERVE_NEW_MODE: ON
8852 11:07:05.232839 MR_CBT_SWITCH_FREQ: ON
8853 11:07:05.233216 =========================
8854 11:07:05.252992 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8855 11:07:05.256115 dram_init: ddr_geometry: 0
8856 11:07:05.274189 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8857 11:07:05.277504 dram_init: dram init end (result: 0)
8858 11:07:05.284071 DRAM-K: Full calibration passed in 23404 msecs
8859 11:07:05.287498 MRC: failed to locate region type 0.
8860 11:07:05.287880 DRAM rank0 size:0x80000000,
8861 11:07:05.290742 DRAM rank1 size=0x80000000
8862 11:07:05.300138 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8863 11:07:05.306884 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8864 11:07:05.313206 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8865 11:07:05.320210 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8866 11:07:05.323181 DRAM rank0 size:0x80000000,
8867 11:07:05.326779 DRAM rank1 size=0x80000000
8868 11:07:05.326853 CBMEM:
8869 11:07:05.330212 IMD: root @ 0xfffff000 254 entries.
8870 11:07:05.333340 IMD: root @ 0xffffec00 62 entries.
8871 11:07:05.336650 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8872 11:07:05.339717 WARNING: RO_VPD is uninitialized or empty.
8873 11:07:05.346327 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8874 11:07:05.353508 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8875 11:07:05.366239 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8876 11:07:05.377694 BS: romstage times (exec / console): total (unknown) / 22948 ms
8877 11:07:05.377769
8878 11:07:05.377827
8879 11:07:05.387427 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8880 11:07:05.390710 ARM64: Exception handlers installed.
8881 11:07:05.394106 ARM64: Testing exception
8882 11:07:05.397299 ARM64: Done test exception
8883 11:07:05.397373 Enumerating buses...
8884 11:07:05.401008 Show all devs... Before device enumeration.
8885 11:07:05.404294 Root Device: enabled 1
8886 11:07:05.407402 CPU_CLUSTER: 0: enabled 1
8887 11:07:05.407476 CPU: 00: enabled 1
8888 11:07:05.410803 Compare with tree...
8889 11:07:05.410878 Root Device: enabled 1
8890 11:07:05.414147 CPU_CLUSTER: 0: enabled 1
8891 11:07:05.417535 CPU: 00: enabled 1
8892 11:07:05.417610 Root Device scanning...
8893 11:07:05.420917 scan_static_bus for Root Device
8894 11:07:05.424101 CPU_CLUSTER: 0 enabled
8895 11:07:05.427446 scan_static_bus for Root Device done
8896 11:07:05.431061 scan_bus: bus Root Device finished in 8 msecs
8897 11:07:05.431136 done
8898 11:07:05.437172 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8899 11:07:05.440689 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8900 11:07:05.447470 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8901 11:07:05.450637 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8902 11:07:05.453892 Allocating resources...
8903 11:07:05.457152 Reading resources...
8904 11:07:05.460676 Root Device read_resources bus 0 link: 0
8905 11:07:05.460752 DRAM rank0 size:0x80000000,
8906 11:07:05.464008 DRAM rank1 size=0x80000000
8907 11:07:05.467094 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8908 11:07:05.470732 CPU: 00 missing read_resources
8909 11:07:05.473855 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8910 11:07:05.480442 Root Device read_resources bus 0 link: 0 done
8911 11:07:05.480518 Done reading resources.
8912 11:07:05.487030 Show resources in subtree (Root Device)...After reading.
8913 11:07:05.490541 Root Device child on link 0 CPU_CLUSTER: 0
8914 11:07:05.493646 CPU_CLUSTER: 0 child on link 0 CPU: 00
8915 11:07:05.503778 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8916 11:07:05.503855 CPU: 00
8917 11:07:05.506943 Root Device assign_resources, bus 0 link: 0
8918 11:07:05.510003 CPU_CLUSTER: 0 missing set_resources
8919 11:07:05.513376 Root Device assign_resources, bus 0 link: 0 done
8920 11:07:05.517153 Done setting resources.
8921 11:07:05.523481 Show resources in subtree (Root Device)...After assigning values.
8922 11:07:05.526566 Root Device child on link 0 CPU_CLUSTER: 0
8923 11:07:05.529860 CPU_CLUSTER: 0 child on link 0 CPU: 00
8924 11:07:05.540089 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8925 11:07:05.540165 CPU: 00
8926 11:07:05.543258 Done allocating resources.
8927 11:07:05.546691 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8928 11:07:05.550100 Enabling resources...
8929 11:07:05.550174 done.
8930 11:07:05.556650 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8931 11:07:05.556725 Initializing devices...
8932 11:07:05.559912 Root Device init
8933 11:07:05.559987 init hardware done!
8934 11:07:05.563395 0x00000018: ctrlr->caps
8935 11:07:05.566621 52.000 MHz: ctrlr->f_max
8936 11:07:05.566697 0.400 MHz: ctrlr->f_min
8937 11:07:05.570347 0x40ff8080: ctrlr->voltages
8938 11:07:05.570423 sclk: 390625
8939 11:07:05.573699 Bus Width = 1
8940 11:07:05.573774 sclk: 390625
8941 11:07:05.576758 Bus Width = 1
8942 11:07:05.576832 Early init status = 3
8943 11:07:05.583204 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8944 11:07:05.586763 in-header: 03 fc 00 00 01 00 00 00
8945 11:07:05.586837 in-data: 00
8946 11:07:05.593017 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8947 11:07:05.596728 in-header: 03 fd 00 00 00 00 00 00
8948 11:07:05.599864 in-data:
8949 11:07:05.603266 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8950 11:07:05.606237 in-header: 03 fc 00 00 01 00 00 00
8951 11:07:05.609768 in-data: 00
8952 11:07:05.613104 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8953 11:07:05.617678 in-header: 03 fd 00 00 00 00 00 00
8954 11:07:05.620982 in-data:
8955 11:07:05.624066 [SSUSB] Setting up USB HOST controller...
8956 11:07:05.627488 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8957 11:07:05.630787 [SSUSB] phy power-on done.
8958 11:07:05.634181 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8959 11:07:05.641046 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8960 11:07:05.644287 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8961 11:07:05.650720 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8962 11:07:05.657603 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8963 11:07:05.664019 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8964 11:07:05.670689 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8965 11:07:05.677176 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
8966 11:07:05.680917 SPM: binary array size = 0x9dc
8967 11:07:05.684243 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8968 11:07:05.690747 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8969 11:07:05.697406 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8970 11:07:05.700707 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8971 11:07:05.707128 configure_display: Starting display init
8972 11:07:05.740661 anx7625_power_on_init: Init interface.
8973 11:07:05.744264 anx7625_disable_pd_protocol: Disabled PD feature.
8974 11:07:05.747896 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8975 11:07:05.775137 anx7625_start_dp_work: Secure OCM version=00
8976 11:07:05.778474 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8977 11:07:05.793367 sp_tx_get_edid_block: EDID Block = 1
8978 11:07:05.896254 Extracted contents:
8979 11:07:05.899128 header: 00 ff ff ff ff ff ff 00
8980 11:07:05.902493 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8981 11:07:05.906026 version: 01 04
8982 11:07:05.909050 basic params: 95 1f 11 78 0a
8983 11:07:05.912700 chroma info: 76 90 94 55 54 90 27 21 50 54
8984 11:07:05.915638 established: 00 00 00
8985 11:07:05.922707 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8986 11:07:05.925757 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8987 11:07:05.932591 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8988 11:07:05.939361 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8989 11:07:05.945524 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8990 11:07:05.948819 extensions: 00
8991 11:07:05.948894 checksum: fb
8992 11:07:05.948952
8993 11:07:05.952242 Manufacturer: IVO Model 57d Serial Number 0
8994 11:07:05.955730 Made week 0 of 2020
8995 11:07:05.955805 EDID version: 1.4
8996 11:07:05.959354 Digital display
8997 11:07:05.962343 6 bits per primary color channel
8998 11:07:05.962418 DisplayPort interface
8999 11:07:05.965730 Maximum image size: 31 cm x 17 cm
9000 11:07:05.968892 Gamma: 220%
9001 11:07:05.968966 Check DPMS levels
9002 11:07:05.972388 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9003 11:07:05.975526 First detailed timing is preferred timing
9004 11:07:05.979049 Established timings supported:
9005 11:07:05.982194 Standard timings supported:
9006 11:07:05.982268 Detailed timings
9007 11:07:05.988851 Hex of detail: 383680a07038204018303c0035ae10000019
9008 11:07:05.992171 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9009 11:07:05.999156 0780 0798 07c8 0820 hborder 0
9010 11:07:06.002465 0438 043b 0447 0458 vborder 0
9011 11:07:06.002540 -hsync -vsync
9012 11:07:06.005607 Did detailed timing
9013 11:07:06.009112 Hex of detail: 000000000000000000000000000000000000
9014 11:07:06.012275 Manufacturer-specified data, tag 0
9015 11:07:06.019100 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9016 11:07:06.019176 ASCII string: InfoVision
9017 11:07:06.025563 Hex of detail: 000000fe00523134304e574635205248200a
9018 11:07:06.028878 ASCII string: R140NWF5 RH
9019 11:07:06.028952 Checksum
9020 11:07:06.029009 Checksum: 0xfb (valid)
9021 11:07:06.035709 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9022 11:07:06.038769 DSI data_rate: 832800000 bps
9023 11:07:06.042138 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9024 11:07:06.045979 anx7625_parse_edid: pixelclock(138800).
9025 11:07:06.052013 hactive(1920), hsync(48), hfp(24), hbp(88)
9026 11:07:06.055519 vactive(1080), vsync(12), vfp(3), vbp(17)
9027 11:07:06.058898 anx7625_dsi_config: config dsi.
9028 11:07:06.065317 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9029 11:07:06.077738 anx7625_dsi_config: success to config DSI
9030 11:07:06.081671 anx7625_dp_start: MIPI phy setup OK.
9031 11:07:06.084539 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9032 11:07:06.087999 mtk_ddp_mode_set invalid vrefresh 60
9033 11:07:06.091241 main_disp_path_setup
9034 11:07:06.091315 ovl_layer_smi_id_en
9035 11:07:06.094460 ovl_layer_smi_id_en
9036 11:07:06.094534 ccorr_config
9037 11:07:06.094591 aal_config
9038 11:07:06.097655 gamma_config
9039 11:07:06.097730 postmask_config
9040 11:07:06.101447 dither_config
9041 11:07:06.104445 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9042 11:07:06.111383 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9043 11:07:06.114549 Root Device init finished in 551 msecs
9044 11:07:06.114623 CPU_CLUSTER: 0 init
9045 11:07:06.124396 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9046 11:07:06.127710 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9047 11:07:06.131204 APU_MBOX 0x190000b0 = 0x10001
9048 11:07:06.134569 APU_MBOX 0x190001b0 = 0x10001
9049 11:07:06.137786 APU_MBOX 0x190005b0 = 0x10001
9050 11:07:06.141554 APU_MBOX 0x190006b0 = 0x10001
9051 11:07:06.144456 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9052 11:07:06.157104 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9053 11:07:06.170018 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9054 11:07:06.176168 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9055 11:07:06.187534 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9056 11:07:06.197108 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9057 11:07:06.200188 CPU_CLUSTER: 0 init finished in 81 msecs
9058 11:07:06.203165 Devices initialized
9059 11:07:06.206588 Show all devs... After init.
9060 11:07:06.206663 Root Device: enabled 1
9061 11:07:06.209997 CPU_CLUSTER: 0: enabled 1
9062 11:07:06.213189 CPU: 00: enabled 1
9063 11:07:06.216447 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9064 11:07:06.219936 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9065 11:07:06.223241 ELOG: NV offset 0x57f000 size 0x1000
9066 11:07:06.229964 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9067 11:07:06.236707 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9068 11:07:06.239917 ELOG: Event(17) added with size 13 at 2024-07-10 11:07:06 UTC
9069 11:07:06.243117 out: cmd=0x121: 03 db 21 01 00 00 00 00
9070 11:07:06.246716 in-header: 03 30 00 00 2c 00 00 00
9071 11:07:06.259890 in-data: 12 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9072 11:07:06.266832 ELOG: Event(A1) added with size 10 at 2024-07-10 11:07:06 UTC
9073 11:07:06.273317 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9074 11:07:06.276611 ELOG: Event(A0) added with size 9 at 2024-07-10 11:07:06 UTC
9075 11:07:06.283586 elog_add_boot_reason: Logged dev mode boot
9076 11:07:06.286562 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9077 11:07:06.289981 Finalize devices...
9078 11:07:06.290057 Devices finalized
9079 11:07:06.296647 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9080 11:07:06.299902 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9081 11:07:06.303335 in-header: 03 07 00 00 08 00 00 00
9082 11:07:06.306781 in-data: aa e4 47 04 13 02 00 00
9083 11:07:06.306856 Chrome EC: UHEPI supported
9084 11:07:06.313346 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9085 11:07:06.316958 in-header: 03 a9 00 00 08 00 00 00
9086 11:07:06.319958 in-data: 84 60 60 08 00 00 00 00
9087 11:07:06.326760 ELOG: Event(91) added with size 10 at 2024-07-10 11:07:06 UTC
9088 11:07:06.330032 Chrome EC: clear events_b mask to 0x0000000020004000
9089 11:07:06.337085 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9090 11:07:06.341799 in-header: 03 fd 00 00 00 00 00 00
9091 11:07:06.344957 in-data:
9092 11:07:06.348564 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9093 11:07:06.351695 Writing coreboot table at 0xffe64000
9094 11:07:06.355101 0. 000000000010a000-0000000000113fff: RAMSTAGE
9095 11:07:06.362406 1. 0000000040000000-00000000400fffff: RAM
9096 11:07:06.364837 2. 0000000040100000-000000004032afff: RAMSTAGE
9097 11:07:06.368861 3. 000000004032b000-00000000545fffff: RAM
9098 11:07:06.371710 4. 0000000054600000-000000005465ffff: BL31
9099 11:07:06.375137 5. 0000000054660000-00000000ffe63fff: RAM
9100 11:07:06.381779 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9101 11:07:06.384833 7. 0000000100000000-000000013fffffff: RAM
9102 11:07:06.388688 Passing 5 GPIOs to payload:
9103 11:07:06.391749 NAME | PORT | POLARITY | VALUE
9104 11:07:06.398147 EC in RW | 0x000000aa | low | undefined
9105 11:07:06.401643 EC interrupt | 0x00000005 | low | undefined
9106 11:07:06.404926 TPM interrupt | 0x000000ab | high | undefined
9107 11:07:06.411709 SD card detect | 0x00000011 | high | undefined
9108 11:07:06.414803 speaker enable | 0x00000093 | high | undefined
9109 11:07:06.418501 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9110 11:07:06.421669 in-header: 03 f8 00 00 02 00 00 00
9111 11:07:06.424588 in-data: 03 00
9112 11:07:06.428192 ADC[4]: Raw value=668222 ID=5
9113 11:07:06.428267 ADC[3]: Raw value=212549 ID=1
9114 11:07:06.431190 RAM Code: 0x51
9115 11:07:06.434535 ADC[6]: Raw value=74778 ID=0
9116 11:07:06.434609 ADC[5]: Raw value=211444 ID=1
9117 11:07:06.438423 SKU Code: 0x1
9118 11:07:06.444617 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum fb58
9119 11:07:06.444696 coreboot table: 964 bytes.
9120 11:07:06.447753 IMD ROOT 0. 0xfffff000 0x00001000
9121 11:07:06.451205 IMD SMALL 1. 0xffffe000 0x00001000
9122 11:07:06.454620 RO MCACHE 2. 0xffffc000 0x00001104
9123 11:07:06.457972 CONSOLE 3. 0xfff7c000 0x00080000
9124 11:07:06.461159 FMAP 4. 0xfff7b000 0x00000452
9125 11:07:06.464532 TIME STAMP 5. 0xfff7a000 0x00000910
9126 11:07:06.467797 VBOOT WORK 6. 0xfff66000 0x00014000
9127 11:07:06.471484 RAMOOPS 7. 0xffe66000 0x00100000
9128 11:07:06.474748 COREBOOT 8. 0xffe64000 0x00002000
9129 11:07:06.477704 IMD small region:
9130 11:07:06.481106 IMD ROOT 0. 0xffffec00 0x00000400
9131 11:07:06.484340 VPD 1. 0xffffeb80 0x0000006c
9132 11:07:06.487516 MMC STATUS 2. 0xffffeb60 0x00000004
9133 11:07:06.490930 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9134 11:07:06.497887 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9135 11:07:06.538536 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9136 11:07:06.541887 Checking segment from ROM address 0x40100000
9137 11:07:06.545124 Checking segment from ROM address 0x4010001c
9138 11:07:06.552344 Loading segment from ROM address 0x40100000
9139 11:07:06.552419 code (compression=0)
9140 11:07:06.558706 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9141 11:07:06.568708 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9142 11:07:06.568783 it's not compressed!
9143 11:07:06.575499 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9144 11:07:06.579111 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9145 11:07:06.599476 Loading segment from ROM address 0x4010001c
9146 11:07:06.599555 Entry Point 0x80000000
9147 11:07:06.602532 Loaded segments
9148 11:07:06.605465 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9149 11:07:06.612219 Jumping to boot code at 0x80000000(0xffe64000)
9150 11:07:06.619320 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9151 11:07:06.625677 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9152 11:07:06.633677 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9153 11:07:06.636722 Checking segment from ROM address 0x40100000
9154 11:07:06.640160 Checking segment from ROM address 0x4010001c
9155 11:07:06.646640 Loading segment from ROM address 0x40100000
9156 11:07:06.646738 code (compression=1)
9157 11:07:06.653367 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9158 11:07:06.663282 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9159 11:07:06.663359 using LZMA
9160 11:07:06.672024 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9161 11:07:06.678605 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9162 11:07:06.681758 Loading segment from ROM address 0x4010001c
9163 11:07:06.681833 Entry Point 0x54601000
9164 11:07:06.684979 Loaded segments
9165 11:07:06.688313 NOTICE: MT8192 bl31_setup
9166 11:07:06.695224 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9167 11:07:06.698646 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9168 11:07:06.701873 WARNING: region 0:
9169 11:07:06.705712 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9170 11:07:06.705787 WARNING: region 1:
9171 11:07:06.712361 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9172 11:07:06.715257 WARNING: region 2:
9173 11:07:06.719027 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9174 11:07:06.722126 WARNING: region 3:
9175 11:07:06.725153 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9176 11:07:06.728637 WARNING: region 4:
9177 11:07:06.735283 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9178 11:07:06.735358 WARNING: region 5:
9179 11:07:06.738742 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 11:07:06.741891 WARNING: region 6:
9181 11:07:06.745426 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9182 11:07:06.748457 WARNING: region 7:
9183 11:07:06.751812 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9184 11:07:06.758309 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9185 11:07:06.761957 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9186 11:07:06.765459 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9187 11:07:06.771786 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9188 11:07:06.775221 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9189 11:07:06.778542 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9190 11:07:06.785140 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9191 11:07:06.788400 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9192 11:07:06.794996 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9193 11:07:06.798628 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9194 11:07:06.801773 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9195 11:07:06.808676 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9196 11:07:06.811846 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9197 11:07:06.815132 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9198 11:07:06.821863 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9199 11:07:06.824983 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9200 11:07:06.831783 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9201 11:07:06.835162 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9202 11:07:06.838545 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9203 11:07:06.844934 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9204 11:07:06.848573 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9205 11:07:06.851939 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9206 11:07:06.858673 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9207 11:07:06.861539 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9208 11:07:06.868502 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9209 11:07:06.872007 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9210 11:07:06.875196 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9211 11:07:06.881554 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9212 11:07:06.884771 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9213 11:07:06.891923 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9214 11:07:06.894931 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9215 11:07:06.898186 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9216 11:07:06.905025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9217 11:07:06.908643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9218 11:07:06.911704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9219 11:07:06.915128 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9220 11:07:06.921471 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9221 11:07:06.924912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9222 11:07:06.928190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9223 11:07:06.931718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9224 11:07:06.938243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9225 11:07:06.941385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9226 11:07:06.944916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9227 11:07:06.947978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9228 11:07:06.954585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9229 11:07:06.958054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9230 11:07:06.961483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9231 11:07:06.968192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9232 11:07:06.971366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9233 11:07:06.974615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9234 11:07:06.981612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9235 11:07:06.984654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9236 11:07:06.991338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9237 11:07:06.994653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9238 11:07:06.998270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9239 11:07:07.004473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9240 11:07:07.007867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9241 11:07:07.014709 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9242 11:07:07.017883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9243 11:07:07.024535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9244 11:07:07.027923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9245 11:07:07.034590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9246 11:07:07.038111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9247 11:07:07.041364 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9248 11:07:07.047966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9249 11:07:07.051252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9250 11:07:07.057928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9251 11:07:07.060952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9252 11:07:07.068167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9253 11:07:07.071305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9254 11:07:07.074535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9255 11:07:07.081046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9256 11:07:07.084354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9257 11:07:07.091173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9258 11:07:07.094453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9259 11:07:07.101072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9260 11:07:07.104270 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9261 11:07:07.110797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9262 11:07:07.114815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9263 11:07:07.117921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9264 11:07:07.124224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9265 11:07:07.127611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9266 11:07:07.134137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9267 11:07:07.137538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9268 11:07:07.144078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9269 11:07:07.147606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9270 11:07:07.151140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9271 11:07:07.157324 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9272 11:07:07.160993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9273 11:07:07.167435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9274 11:07:07.171091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9275 11:07:07.177652 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9276 11:07:07.180860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9277 11:07:07.184290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9278 11:07:07.190674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9279 11:07:07.194096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9280 11:07:07.201008 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9281 11:07:07.204204 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9282 11:07:07.207517 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9283 11:07:07.210745 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9284 11:07:07.217571 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9285 11:07:07.220559 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9286 11:07:07.224297 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9287 11:07:07.230616 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9288 11:07:07.233899 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9289 11:07:07.240435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9290 11:07:07.244134 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9291 11:07:07.247138 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9292 11:07:07.253910 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9293 11:07:07.257131 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9294 11:07:07.263662 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9295 11:07:07.267050 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9296 11:07:07.274285 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9297 11:07:07.277088 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9298 11:07:07.280313 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9299 11:07:07.286978 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9300 11:07:07.290252 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9301 11:07:07.293538 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9302 11:07:07.300158 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9303 11:07:07.303356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9304 11:07:07.306756 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9305 11:07:07.309996 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9306 11:07:07.316694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9307 11:07:07.319892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9308 11:07:07.323308 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9309 11:07:07.330052 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9310 11:07:07.333495 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9311 11:07:07.337261 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9312 11:07:07.343651 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9313 11:07:07.346934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9314 11:07:07.353604 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9315 11:07:07.356716 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9316 11:07:07.359972 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9317 11:07:07.366948 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9318 11:07:07.369997 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9319 11:07:07.376786 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9320 11:07:07.379983 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9321 11:07:07.383571 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9322 11:07:07.390025 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9323 11:07:07.393140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9324 11:07:07.396783 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9325 11:07:07.403106 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9326 11:07:07.406641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9327 11:07:07.413189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9328 11:07:07.416434 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9329 11:07:07.419861 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9330 11:07:07.426500 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9331 11:07:07.430050 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9332 11:07:07.436943 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9333 11:07:07.439977 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9334 11:07:07.443619 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9335 11:07:07.449864 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9336 11:07:07.453618 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9337 11:07:07.456636 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9338 11:07:07.464142 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9339 11:07:07.466733 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9340 11:07:07.473168 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9341 11:07:07.476612 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9342 11:07:07.479910 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9343 11:07:07.486597 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9344 11:07:07.489937 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9345 11:07:07.496565 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9346 11:07:07.499965 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9347 11:07:07.503275 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9348 11:07:07.509722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9349 11:07:07.513166 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9350 11:07:07.516753 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9351 11:07:07.523097 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9352 11:07:07.526522 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9353 11:07:07.533120 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9354 11:07:07.536600 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9355 11:07:07.539906 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9356 11:07:07.546309 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9357 11:07:07.549810 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9358 11:07:07.556201 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9359 11:07:07.559659 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9360 11:07:07.563057 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9361 11:07:07.569874 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9362 11:07:07.573015 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9363 11:07:07.576464 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9364 11:07:07.583171 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9365 11:07:07.586207 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9366 11:07:07.592918 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9367 11:07:07.596376 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9368 11:07:07.603214 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9369 11:07:07.606208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9370 11:07:07.609431 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9371 11:07:07.616296 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9372 11:07:07.619748 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9373 11:07:07.626174 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9374 11:07:07.629634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9375 11:07:07.632845 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9376 11:07:07.639893 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9377 11:07:07.642908 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9378 11:07:07.649554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9379 11:07:07.653019 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9380 11:07:07.656146 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9381 11:07:07.662890 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9382 11:07:07.666186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9383 11:07:07.673160 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9384 11:07:07.676194 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9385 11:07:07.679316 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9386 11:07:07.686070 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9387 11:07:07.689481 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9388 11:07:07.696411 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9389 11:07:07.699625 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9390 11:07:07.706471 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9391 11:07:07.709497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9392 11:07:07.712740 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9393 11:07:07.719396 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9394 11:07:07.722884 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9395 11:07:07.729488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9396 11:07:07.733101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9397 11:07:07.735904 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9398 11:07:07.742621 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9399 11:07:07.746122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9400 11:07:07.752957 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9401 11:07:07.756017 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9402 11:07:07.759279 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9403 11:07:07.766305 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9404 11:07:07.769373 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9405 11:07:07.776027 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9406 11:07:07.779451 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9407 11:07:07.785887 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9408 11:07:07.789381 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9409 11:07:07.792736 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9410 11:07:07.799336 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9411 11:07:07.802866 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9412 11:07:07.809189 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9413 11:07:07.812810 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9414 11:07:07.815934 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9415 11:07:07.819182 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9416 11:07:07.822624 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9417 11:07:07.829061 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9418 11:07:07.832844 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9419 11:07:07.835742 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9420 11:07:07.842320 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9421 11:07:07.845719 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9422 11:07:07.852135 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9423 11:07:07.855820 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9424 11:07:07.859047 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9425 11:07:07.865594 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9426 11:07:07.869064 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9427 11:07:07.872480 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9428 11:07:07.879046 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9429 11:07:07.882119 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9430 11:07:07.889380 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9431 11:07:07.892465 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9432 11:07:07.896169 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9433 11:07:07.899061 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9434 11:07:07.905697 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9435 11:07:07.909023 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9436 11:07:07.915797 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9437 11:07:07.919039 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9438 11:07:07.922056 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9439 11:07:07.928824 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9440 11:07:07.932392 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9441 11:07:07.938813 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9442 11:07:07.942170 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9443 11:07:07.945406 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9444 11:07:07.952158 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9445 11:07:07.955262 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9446 11:07:07.959119 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9447 11:07:07.965755 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9448 11:07:07.969304 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9449 11:07:07.972475 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9450 11:07:07.978940 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9451 11:07:07.982004 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9452 11:07:07.985376 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9453 11:07:07.992361 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9454 11:07:07.995321 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9455 11:07:07.998531 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9456 11:07:08.001960 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9457 11:07:08.005165 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9458 11:07:08.011860 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9459 11:07:08.015537 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9460 11:07:08.019162 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9461 11:07:08.025356 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9462 11:07:08.028540 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9463 11:07:08.031682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9464 11:07:08.035439 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9465 11:07:08.041964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9466 11:07:08.045064 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9467 11:07:08.048500 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9468 11:07:08.054979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9469 11:07:08.058565 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9470 11:07:08.065015 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9471 11:07:08.068539 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9472 11:07:08.075175 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9473 11:07:08.078502 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9474 11:07:08.081581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9475 11:07:08.088373 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9476 11:07:08.091588 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9477 11:07:08.098131 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9478 11:07:08.101493 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9479 11:07:08.104949 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9480 11:07:08.111428 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9481 11:07:08.114827 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9482 11:07:08.121658 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9483 11:07:08.124939 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9484 11:07:08.128262 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9485 11:07:08.134659 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9486 11:07:08.138365 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9487 11:07:08.144925 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9488 11:07:08.148265 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9489 11:07:08.151695 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9490 11:07:08.158047 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9491 11:07:08.161707 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9492 11:07:08.168062 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9493 11:07:08.171803 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9494 11:07:08.174808 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9495 11:07:08.181787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9496 11:07:08.184751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9497 11:07:08.191378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9498 11:07:08.194716 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9499 11:07:08.198353 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9500 11:07:08.204963 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9501 11:07:08.208227 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9502 11:07:08.214754 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9503 11:07:08.218061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9504 11:07:08.225364 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9505 11:07:08.227928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9506 11:07:08.231255 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9507 11:07:08.238156 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9508 11:07:08.241379 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9509 11:07:08.248361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9510 11:07:08.251483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9511 11:07:08.254808 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9512 11:07:08.261462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9513 11:07:08.264608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9514 11:07:08.268041 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9515 11:07:08.274561 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9516 11:07:08.277825 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9517 11:07:08.284703 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9518 11:07:08.288226 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9519 11:07:08.294344 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9520 11:07:08.297949 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9521 11:07:08.301222 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9522 11:07:08.307872 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9523 11:07:08.310925 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9524 11:07:08.317681 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9525 11:07:08.321380 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9526 11:07:08.324382 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9527 11:07:08.331014 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9528 11:07:08.334372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9529 11:07:08.341489 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9530 11:07:08.344242 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9531 11:07:08.348041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9532 11:07:08.354353 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9533 11:07:08.358026 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9534 11:07:08.364451 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9535 11:07:08.367592 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9536 11:07:08.374514 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9537 11:07:08.378158 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9538 11:07:08.381061 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9539 11:07:08.387817 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9540 11:07:08.391122 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9541 11:07:08.397764 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9542 11:07:08.401036 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9543 11:07:08.404289 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9544 11:07:08.411186 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9545 11:07:08.414427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9546 11:07:08.420879 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9547 11:07:08.424443 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9548 11:07:08.431117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9549 11:07:08.434298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9550 11:07:08.440881 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9551 11:07:08.444357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9552 11:07:08.447432 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9553 11:07:08.454102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9554 11:07:08.457401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9555 11:07:08.464317 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9556 11:07:08.467430 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9557 11:07:08.474494 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9558 11:07:08.477450 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9559 11:07:08.480704 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9560 11:07:08.487263 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9561 11:07:08.490941 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9562 11:07:08.497401 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9563 11:07:08.500580 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9564 11:07:08.507148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9565 11:07:08.510558 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9566 11:07:08.513809 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9567 11:07:08.520563 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9568 11:07:08.523915 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9569 11:07:08.530791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9570 11:07:08.533842 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9571 11:07:08.540676 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9572 11:07:08.543615 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9573 11:07:08.547046 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9574 11:07:08.553949 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9575 11:07:08.557296 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9576 11:07:08.563611 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9577 11:07:08.566915 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9578 11:07:08.573894 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9579 11:07:08.577068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9580 11:07:08.580346 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9581 11:07:08.586995 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9582 11:07:08.590213 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9583 11:07:08.597154 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9584 11:07:08.600401 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9585 11:07:08.607000 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9586 11:07:08.610299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9587 11:07:08.613639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9588 11:07:08.620223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9589 11:07:08.623526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9590 11:07:08.630266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9591 11:07:08.633402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9592 11:07:08.640433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9593 11:07:08.643576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9594 11:07:08.650398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9595 11:07:08.653723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9596 11:07:08.660038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9597 11:07:08.663765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9598 11:07:08.670202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9599 11:07:08.673509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9600 11:07:08.680122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9601 11:07:08.683712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9602 11:07:08.690357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9603 11:07:08.693408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9604 11:07:08.696842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9605 11:07:08.703561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9606 11:07:08.706735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9607 11:07:08.713286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9608 11:07:08.716872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9609 11:07:08.723684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9610 11:07:08.726605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9611 11:07:08.733463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9612 11:07:08.736502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9613 11:07:08.743317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9614 11:07:08.746794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9615 11:07:08.753341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9616 11:07:08.756558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9617 11:07:08.763428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9618 11:07:08.766617 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9619 11:07:08.769945 INFO: [APUAPC] vio 0
9620 11:07:08.773360 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9621 11:07:08.779874 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9622 11:07:08.782845 INFO: [APUAPC] D0_APC_0: 0x400510
9623 11:07:08.786329 INFO: [APUAPC] D0_APC_1: 0x0
9624 11:07:08.789557 INFO: [APUAPC] D0_APC_2: 0x1540
9625 11:07:08.789632 INFO: [APUAPC] D0_APC_3: 0x0
9626 11:07:08.792904 INFO: [APUAPC] D1_APC_0: 0xffffffff
9627 11:07:08.796413 INFO: [APUAPC] D1_APC_1: 0xffffffff
9628 11:07:08.799924 INFO: [APUAPC] D1_APC_2: 0x3fffff
9629 11:07:08.803049 INFO: [APUAPC] D1_APC_3: 0x0
9630 11:07:08.806524 INFO: [APUAPC] D2_APC_0: 0xffffffff
9631 11:07:08.810064 INFO: [APUAPC] D2_APC_1: 0xffffffff
9632 11:07:08.812952 INFO: [APUAPC] D2_APC_2: 0x3fffff
9633 11:07:08.816657 INFO: [APUAPC] D2_APC_3: 0x0
9634 11:07:08.819786 INFO: [APUAPC] D3_APC_0: 0xffffffff
9635 11:07:08.822715 INFO: [APUAPC] D3_APC_1: 0xffffffff
9636 11:07:08.826282 INFO: [APUAPC] D3_APC_2: 0x3fffff
9637 11:07:08.829764 INFO: [APUAPC] D3_APC_3: 0x0
9638 11:07:08.833556 INFO: [APUAPC] D4_APC_0: 0xffffffff
9639 11:07:08.836203 INFO: [APUAPC] D4_APC_1: 0xffffffff
9640 11:07:08.839827 INFO: [APUAPC] D4_APC_2: 0x3fffff
9641 11:07:08.842998 INFO: [APUAPC] D4_APC_3: 0x0
9642 11:07:08.846388 INFO: [APUAPC] D5_APC_0: 0xffffffff
9643 11:07:08.849594 INFO: [APUAPC] D5_APC_1: 0xffffffff
9644 11:07:08.853049 INFO: [APUAPC] D5_APC_2: 0x3fffff
9645 11:07:08.856336 INFO: [APUAPC] D5_APC_3: 0x0
9646 11:07:08.859381 INFO: [APUAPC] D6_APC_0: 0xffffffff
9647 11:07:08.863029 INFO: [APUAPC] D6_APC_1: 0xffffffff
9648 11:07:08.866421 INFO: [APUAPC] D6_APC_2: 0x3fffff
9649 11:07:08.869566 INFO: [APUAPC] D6_APC_3: 0x0
9650 11:07:08.873030 INFO: [APUAPC] D7_APC_0: 0xffffffff
9651 11:07:08.876024 INFO: [APUAPC] D7_APC_1: 0xffffffff
9652 11:07:08.879451 INFO: [APUAPC] D7_APC_2: 0x3fffff
9653 11:07:08.882525 INFO: [APUAPC] D7_APC_3: 0x0
9654 11:07:08.886002 INFO: [APUAPC] D8_APC_0: 0xffffffff
9655 11:07:08.889377 INFO: [APUAPC] D8_APC_1: 0xffffffff
9656 11:07:08.892557 INFO: [APUAPC] D8_APC_2: 0x3fffff
9657 11:07:08.895932 INFO: [APUAPC] D8_APC_3: 0x0
9658 11:07:08.899056 INFO: [APUAPC] D9_APC_0: 0xffffffff
9659 11:07:08.902435 INFO: [APUAPC] D9_APC_1: 0xffffffff
9660 11:07:08.905882 INFO: [APUAPC] D9_APC_2: 0x3fffff
9661 11:07:08.909412 INFO: [APUAPC] D9_APC_3: 0x0
9662 11:07:08.912728 INFO: [APUAPC] D10_APC_0: 0xffffffff
9663 11:07:08.915764 INFO: [APUAPC] D10_APC_1: 0xffffffff
9664 11:07:08.919026 INFO: [APUAPC] D10_APC_2: 0x3fffff
9665 11:07:08.922327 INFO: [APUAPC] D10_APC_3: 0x0
9666 11:07:08.925855 INFO: [APUAPC] D11_APC_0: 0xffffffff
9667 11:07:08.928964 INFO: [APUAPC] D11_APC_1: 0xffffffff
9668 11:07:08.932433 INFO: [APUAPC] D11_APC_2: 0x3fffff
9669 11:07:08.935797 INFO: [APUAPC] D11_APC_3: 0x0
9670 11:07:08.938859 INFO: [APUAPC] D12_APC_0: 0xffffffff
9671 11:07:08.942313 INFO: [APUAPC] D12_APC_1: 0xffffffff
9672 11:07:08.945956 INFO: [APUAPC] D12_APC_2: 0x3fffff
9673 11:07:08.948791 INFO: [APUAPC] D12_APC_3: 0x0
9674 11:07:08.952174 INFO: [APUAPC] D13_APC_0: 0xffffffff
9675 11:07:08.955542 INFO: [APUAPC] D13_APC_1: 0xffffffff
9676 11:07:08.958846 INFO: [APUAPC] D13_APC_2: 0x3fffff
9677 11:07:08.962106 INFO: [APUAPC] D13_APC_3: 0x0
9678 11:07:08.965406 INFO: [APUAPC] D14_APC_0: 0xffffffff
9679 11:07:08.968775 INFO: [APUAPC] D14_APC_1: 0xffffffff
9680 11:07:08.972455 INFO: [APUAPC] D14_APC_2: 0x3fffff
9681 11:07:08.975736 INFO: [APUAPC] D14_APC_3: 0x0
9682 11:07:08.978916 INFO: [APUAPC] D15_APC_0: 0xffffffff
9683 11:07:08.981937 INFO: [APUAPC] D15_APC_1: 0xffffffff
9684 11:07:08.985239 INFO: [APUAPC] D15_APC_2: 0x3fffff
9685 11:07:08.988626 INFO: [APUAPC] D15_APC_3: 0x0
9686 11:07:08.991832 INFO: [APUAPC] APC_CON: 0x4
9687 11:07:08.995621 INFO: [NOCDAPC] D0_APC_0: 0x0
9688 11:07:08.995686 INFO: [NOCDAPC] D0_APC_1: 0x0
9689 11:07:08.998739 INFO: [NOCDAPC] D1_APC_0: 0x0
9690 11:07:09.002047 INFO: [NOCDAPC] D1_APC_1: 0xfff
9691 11:07:09.005605 INFO: [NOCDAPC] D2_APC_0: 0x0
9692 11:07:09.008704 INFO: [NOCDAPC] D2_APC_1: 0xfff
9693 11:07:09.011901 INFO: [NOCDAPC] D3_APC_0: 0x0
9694 11:07:09.015051 INFO: [NOCDAPC] D3_APC_1: 0xfff
9695 11:07:09.018529 INFO: [NOCDAPC] D4_APC_0: 0x0
9696 11:07:09.022336 INFO: [NOCDAPC] D4_APC_1: 0xfff
9697 11:07:09.025097 INFO: [NOCDAPC] D5_APC_0: 0x0
9698 11:07:09.028586 INFO: [NOCDAPC] D5_APC_1: 0xfff
9699 11:07:09.028656 INFO: [NOCDAPC] D6_APC_0: 0x0
9700 11:07:09.031842 INFO: [NOCDAPC] D6_APC_1: 0xfff
9701 11:07:09.035223 INFO: [NOCDAPC] D7_APC_0: 0x0
9702 11:07:09.038483 INFO: [NOCDAPC] D7_APC_1: 0xfff
9703 11:07:09.042291 INFO: [NOCDAPC] D8_APC_0: 0x0
9704 11:07:09.044943 INFO: [NOCDAPC] D8_APC_1: 0xfff
9705 11:07:09.048318 INFO: [NOCDAPC] D9_APC_0: 0x0
9706 11:07:09.051592 INFO: [NOCDAPC] D9_APC_1: 0xfff
9707 11:07:09.054926 INFO: [NOCDAPC] D10_APC_0: 0x0
9708 11:07:09.058300 INFO: [NOCDAPC] D10_APC_1: 0xfff
9709 11:07:09.061797 INFO: [NOCDAPC] D11_APC_0: 0x0
9710 11:07:09.064986 INFO: [NOCDAPC] D11_APC_1: 0xfff
9711 11:07:09.065056 INFO: [NOCDAPC] D12_APC_0: 0x0
9712 11:07:09.068155 INFO: [NOCDAPC] D12_APC_1: 0xfff
9713 11:07:09.071725 INFO: [NOCDAPC] D13_APC_0: 0x0
9714 11:07:09.074887 INFO: [NOCDAPC] D13_APC_1: 0xfff
9715 11:07:09.078123 INFO: [NOCDAPC] D14_APC_0: 0x0
9716 11:07:09.081941 INFO: [NOCDAPC] D14_APC_1: 0xfff
9717 11:07:09.084727 INFO: [NOCDAPC] D15_APC_0: 0x0
9718 11:07:09.087996 INFO: [NOCDAPC] D15_APC_1: 0xfff
9719 11:07:09.091469 INFO: [NOCDAPC] APC_CON: 0x4
9720 11:07:09.094674 INFO: [APUAPC] set_apusys_apc done
9721 11:07:09.097889 INFO: [DEVAPC] devapc_init done
9722 11:07:09.101462 INFO: GICv3 without legacy support detected.
9723 11:07:09.104461 INFO: ARM GICv3 driver initialized in EL3
9724 11:07:09.108003 INFO: Maximum SPI INTID supported: 639
9725 11:07:09.114576 INFO: BL31: Initializing runtime services
9726 11:07:09.117927 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9727 11:07:09.121113 INFO: SPM: enable CPC mode
9728 11:07:09.127865 INFO: mcdi ready for mcusys-off-idle and system suspend
9729 11:07:09.131681 INFO: BL31: Preparing for EL3 exit to normal world
9730 11:07:09.134559 INFO: Entry point address = 0x80000000
9731 11:07:09.137817 INFO: SPSR = 0x8
9732 11:07:09.143265
9733 11:07:09.143333
9734 11:07:09.143390
9735 11:07:09.146863 Starting depthcharge on Spherion...
9736 11:07:09.146924
9737 11:07:09.146978 Wipe memory regions:
9738 11:07:09.147032
9739 11:07:09.147667 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9740 11:07:09.147759 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9741 11:07:09.147834 Setting prompt string to ['asurada:']
9742 11:07:09.147898 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9743 11:07:09.149677 [0x00000040000000, 0x00000054600000)
9744 11:07:09.272280
9745 11:07:09.272381 [0x00000054660000, 0x00000080000000)
9746 11:07:09.532721
9747 11:07:09.532835 [0x000000821a7280, 0x000000ffe64000)
9748 11:07:10.277630
9749 11:07:10.277758 [0x00000100000000, 0x00000140000000)
9750 11:07:10.658780
9751 11:07:10.661804 Initializing XHCI USB controller at 0x11200000.
9752 11:07:11.700272
9753 11:07:11.703475 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9754 11:07:11.703552
9755 11:07:11.703611
9756 11:07:11.703869 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9757 11:07:11.703940 Sending line: 'tftpboot 192.168.201.1 14786845/tftp-deploy-xcyw_x31/kernel/image.itb 14786845/tftp-deploy-xcyw_x31/kernel/cmdline '
9759 11:07:11.804342 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9760 11:07:11.804418 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:19)
9761 11:07:11.808312 asurada: tftpboot 192.168.201.1 14786845/tftp-deploy-xcyw_x31/kernel/image.ittp-deploy-xcyw_x31/kernel/cmdline
9762 11:07:11.808389
9763 11:07:11.808447 Waiting for link
9764 11:07:11.966994
9765 11:07:11.967102 R8152: Initializing
9766 11:07:11.967163
9767 11:07:11.970208 Version 9 (ocp_data = 6010)
9768 11:07:11.970283
9769 11:07:11.973316 R8152: Done initializing
9770 11:07:11.973392
9771 11:07:11.973450 Adding net device
9772 11:07:13.946033
9773 11:07:13.946532 done.
9774 11:07:13.946863
9775 11:07:13.947169 MAC: 00:e0:4c:68:03:bd
9776 11:07:13.947542
9777 11:07:13.949723 Sending DHCP discover... done.
9778 11:07:13.950143
9779 11:07:13.952880 Waiting for reply... done.
9780 11:07:13.953307
9781 11:07:13.955841 Sending DHCP request... done.
9782 11:07:13.956286
9783 11:07:13.961423 Waiting for reply... done.
9784 11:07:13.961589
9785 11:07:13.961719 My ip is 192.168.201.16
9786 11:07:13.961838
9787 11:07:13.964998 The DHCP server ip is 192.168.201.1
9788 11:07:13.965163
9789 11:07:13.971386 TFTP server IP predefined by user: 192.168.201.1
9790 11:07:13.971552
9791 11:07:13.978176 Bootfile predefined by user: 14786845/tftp-deploy-xcyw_x31/kernel/image.itb
9792 11:07:13.978341
9793 11:07:13.981399 Sending tftp read request... done.
9794 11:07:13.981566
9795 11:07:13.985959 Waiting for the transfer...
9796 11:07:13.986123
9797 11:07:14.238979 00000000 ################################################################
9798 11:07:14.239104
9799 11:07:14.492408 00080000 ################################################################
9800 11:07:14.492544
9801 11:07:14.740554 00100000 ################################################################
9802 11:07:14.740683
9803 11:07:14.990494 00180000 ################################################################
9804 11:07:14.990620
9805 11:07:15.239831 00200000 ################################################################
9806 11:07:15.239951
9807 11:07:15.490253 00280000 ################################################################
9808 11:07:15.490385
9809 11:07:15.745373 00300000 ################################################################
9810 11:07:15.745496
9811 11:07:15.996708 00380000 ################################################################
9812 11:07:15.996822
9813 11:07:16.244607 00400000 ################################################################
9814 11:07:16.244716
9815 11:07:16.503099 00480000 ################################################################
9816 11:07:16.503217
9817 11:07:16.753904 00500000 ################################################################
9818 11:07:16.754048
9819 11:07:17.003814 00580000 ################################################################
9820 11:07:17.003951
9821 11:07:17.254327 00600000 ################################################################
9822 11:07:17.254459
9823 11:07:17.500488 00680000 ################################################################
9824 11:07:17.500639
9825 11:07:17.757042 00700000 ################################################################
9826 11:07:17.757199
9827 11:07:18.007330 00780000 ################################################################
9828 11:07:18.007482
9829 11:07:18.257386 00800000 ################################################################
9830 11:07:18.257506
9831 11:07:18.506368 00880000 ################################################################
9832 11:07:18.506511
9833 11:07:18.755212 00900000 ################################################################
9834 11:07:18.755338
9835 11:07:19.002925 00980000 ################################################################
9836 11:07:19.003050
9837 11:07:19.252333 00a00000 ################################################################
9838 11:07:19.252469
9839 11:07:19.501466 00a80000 ################################################################
9840 11:07:19.501627
9841 11:07:19.752420 00b00000 ################################################################
9842 11:07:19.752539
9843 11:07:20.005518 00b80000 ################################################################
9844 11:07:20.005656
9845 11:07:20.252864 00c00000 ################################################################
9846 11:07:20.252982
9847 11:07:20.502806 00c80000 ################################################################
9848 11:07:20.502921
9849 11:07:20.773950 00d00000 ################################################################
9850 11:07:20.774063
9851 11:07:21.026797 00d80000 ################################################################
9852 11:07:21.026916
9853 11:07:21.276495 00e00000 ################################################################
9854 11:07:21.276609
9855 11:07:21.525145 00e80000 ################################################################
9856 11:07:21.525294
9857 11:07:21.776226 00f00000 ################################################################
9858 11:07:21.776339
9859 11:07:22.027740 00f80000 ################################################################
9860 11:07:22.027854
9861 11:07:22.275199 01000000 ################################################################
9862 11:07:22.275323
9863 11:07:22.524271 01080000 ################################################################
9864 11:07:22.524517
9865 11:07:22.772281 01100000 ################################################################
9866 11:07:22.772404
9867 11:07:23.017955 01180000 ################################################################
9868 11:07:23.018078
9869 11:07:23.264196 01200000 ################################################################
9870 11:07:23.264319
9871 11:07:23.517787 01280000 ################################################################
9872 11:07:23.517902
9873 11:07:23.779699 01300000 ################################################################
9874 11:07:23.779825
9875 11:07:24.034279 01380000 ################################################################
9876 11:07:24.034401
9877 11:07:24.288585 01400000 ################################################################
9878 11:07:24.288720
9879 11:07:24.534662 01480000 ################################################################
9880 11:07:24.534779
9881 11:07:24.781564 01500000 ################################################################
9882 11:07:24.781708
9883 11:07:25.047476 01580000 ################################################################
9884 11:07:25.047616
9885 11:07:25.303304 01600000 ################################################################
9886 11:07:25.303439
9887 11:07:25.576302 01680000 ################################################################
9888 11:07:25.576434
9889 11:07:25.826073 01700000 ################################################################
9890 11:07:25.826184
9891 11:07:26.075365 01780000 ################################################################
9892 11:07:26.075484
9893 11:07:26.328199 01800000 ################################################################
9894 11:07:26.328313
9895 11:07:26.574046 01880000 ################################################################
9896 11:07:26.574172
9897 11:07:26.834798 01900000 ################################################################
9898 11:07:26.834925
9899 11:07:27.114918 01980000 ################################################################
9900 11:07:27.115071
9901 11:07:27.384596 01a00000 ################################################################
9902 11:07:27.384730
9903 11:07:27.637738 01a80000 ################################################################
9904 11:07:27.637864
9905 11:07:27.883319 01b00000 ################################################################
9906 11:07:27.883442
9907 11:07:28.131683 01b80000 ################################################################
9908 11:07:28.131827
9909 11:07:28.397918 01c00000 ################################################################
9910 11:07:28.398038
9911 11:07:28.649255 01c80000 ################################################################
9912 11:07:28.649392
9913 11:07:28.895820 01d00000 ################################################################
9914 11:07:28.895964
9915 11:07:29.154500 01d80000 ################################################################
9916 11:07:29.154612
9917 11:07:29.419885 01e00000 ################################################################
9918 11:07:29.420004
9919 11:07:29.683007 01e80000 ################################################################
9920 11:07:29.683148
9921 11:07:29.944564 01f00000 ################################################################
9922 11:07:29.944675
9923 11:07:30.200849 01f80000 ################################################################
9924 11:07:30.200969
9925 11:07:30.480389 02000000 ################################################################
9926 11:07:30.480517
9927 11:07:30.758887 02080000 ################################################################
9928 11:07:30.759000
9929 11:07:31.014887 02100000 ################################################################
9930 11:07:31.015043
9931 11:07:31.264167 02180000 ################################################################
9932 11:07:31.264291
9933 11:07:31.512147 02200000 ################################################################
9934 11:07:31.512273
9935 11:07:31.764081 02280000 ################################################################
9936 11:07:31.764205
9937 11:07:32.023396 02300000 ################################################################
9938 11:07:32.023523
9939 11:07:32.298832 02380000 ################################################################
9940 11:07:32.298991
9941 11:07:32.554480 02400000 ################################################################
9942 11:07:32.554605
9943 11:07:32.811192 02480000 ################################################################
9944 11:07:32.811315
9945 11:07:33.067897 02500000 ################################################################
9946 11:07:33.068019
9947 11:07:33.324902 02580000 ################################################################
9948 11:07:33.325049
9949 11:07:33.571163 02600000 ################################################################
9950 11:07:33.571290
9951 11:07:33.816596 02680000 ################################################################
9952 11:07:33.816720
9953 11:07:34.061770 02700000 ################################################################
9954 11:07:34.061883
9955 11:07:34.308686 02780000 ################################################################
9956 11:07:34.308807
9957 11:07:34.558090 02800000 ################################################################
9958 11:07:34.558226
9959 11:07:34.808342 02880000 ################################################################
9960 11:07:34.808465
9961 11:07:35.066090 02900000 ################################################################
9962 11:07:35.066230
9963 11:07:35.345043 02980000 ################################################################
9964 11:07:35.345181
9965 11:07:35.604153 02a00000 ################################################################
9966 11:07:35.604263
9967 11:07:35.858970 02a80000 ################################################################
9968 11:07:35.859088
9969 11:07:36.108224 02b00000 ################################################################
9970 11:07:36.108341
9971 11:07:36.368834 02b80000 ################################################################
9972 11:07:36.368952
9973 11:07:36.633768 02c00000 ################################################################
9974 11:07:36.633880
9975 11:07:36.892668 02c80000 ################################################################
9976 11:07:36.892796
9977 11:07:37.171179 02d00000 ################################################################
9978 11:07:37.171304
9979 11:07:37.446410 02d80000 ################################################################
9980 11:07:37.446524
9981 11:07:37.729798 02e00000 ################################################################
9982 11:07:37.729936
9983 11:07:38.001762 02e80000 ################################################################
9984 11:07:38.001877
9985 11:07:38.253551 02f00000 ################################################################
9986 11:07:38.253679
9987 11:07:38.528405 02f80000 ################################################################
9988 11:07:38.528533
9989 11:07:38.785015 03000000 ################################################################
9990 11:07:38.785141
9991 11:07:39.055295 03080000 ################################################################
9992 11:07:39.055422
9993 11:07:39.317638 03100000 ################################################################
9994 11:07:39.317760
9995 11:07:39.584031 03180000 ################################################################
9996 11:07:39.584159
9997 11:07:39.838224 03200000 ################################################################
9998 11:07:39.838352
9999 11:07:40.093101 03280000 ################################################################
10000 11:07:40.093265
10001 11:07:40.344127 03300000 ################################################################
10002 11:07:40.344251
10003 11:07:40.590641 03380000 ################################################################
10004 11:07:40.590838
10005 11:07:40.847919 03400000 ################################################################
10006 11:07:40.848043
10007 11:07:41.094455 03480000 ################################################################
10008 11:07:41.094575
10009 11:07:41.339543 03500000 ################################################################
10010 11:07:41.339655
10011 11:07:41.586390 03580000 ################################################################
10012 11:07:41.586502
10013 11:07:41.833824 03600000 ################################################################
10014 11:07:41.833936
10015 11:07:42.084500 03680000 ################################################################
10016 11:07:42.084638
10017 11:07:42.367988 03700000 ################################################################
10018 11:07:42.368101
10019 11:07:42.656572 03780000 ################################################################
10020 11:07:42.656709
10021 11:07:42.935663 03800000 ################################################################
10022 11:07:42.935775
10023 11:07:43.190737 03880000 ################################################################
10024 11:07:43.190873
10025 11:07:43.447271 03900000 ################################################################
10026 11:07:43.447412
10027 11:07:43.696365 03980000 ################################################################
10028 11:07:43.696525
10029 11:07:43.947186 03a00000 ################################################################
10030 11:07:43.947332
10031 11:07:44.225377 03a80000 ################################################################
10032 11:07:44.225495
10033 11:07:44.509965 03b00000 ################################################################
10034 11:07:44.510084
10035 11:07:44.807953 03b80000 ################################################################
10036 11:07:44.808072
10037 11:07:45.107245 03c00000 ################################################################
10038 11:07:45.107366
10039 11:07:45.405887 03c80000 ################################################################
10040 11:07:45.406006
10041 11:07:45.694312 03d00000 ################################################################
10042 11:07:45.694434
10043 11:07:45.960573 03d80000 ################################################################
10044 11:07:45.960683
10045 11:07:46.220252 03e00000 ################################################################
10046 11:07:46.220363
10047 11:07:46.478838 03e80000 ################################################################
10048 11:07:46.478948
10049 11:07:46.731650 03f00000 ################################################################
10050 11:07:46.731761
10051 11:07:47.004144 03f80000 ################################################################
10052 11:07:47.004257
10053 11:07:47.264969 04000000 ################################################################
10054 11:07:47.265106
10055 11:07:47.516749 04080000 ################################################################
10056 11:07:47.516857
10057 11:07:47.793569 04100000 ################################################################
10058 11:07:47.793681
10059 11:07:48.049987 04180000 ################################################################
10060 11:07:48.050110
10061 11:07:48.308861 04200000 ################################################################
10062 11:07:48.308987
10063 11:07:48.559243 04280000 ################################################################
10064 11:07:48.559358
10065 11:07:48.810302 04300000 ################################################################
10066 11:07:48.810418
10067 11:07:49.060725 04380000 ################################################################
10068 11:07:49.060863
10069 11:07:49.311054 04400000 ################################################################
10070 11:07:49.311239
10071 11:07:49.561730 04480000 ################################################################
10072 11:07:49.561866
10073 11:07:49.842280 04500000 ################################################################
10074 11:07:49.842392
10075 11:07:50.129709 04580000 ################################################################
10076 11:07:50.129824
10077 11:07:50.398788 04600000 ################################################################
10078 11:07:50.398901
10079 11:07:50.518921 04680000 ########################### done.
10080 11:07:50.519029
10081 11:07:50.522501 The bootfile was 74145422 bytes long.
10082 11:07:50.522584
10083 11:07:50.526109 Sending tftp read request... done.
10084 11:07:50.526518
10085 11:07:50.526905 Waiting for the transfer...
10086 11:07:50.527193
10087 11:07:50.529306 00000000 # done.
10088 11:07:50.529706
10089 11:07:50.535869 Command line loaded dynamically from TFTP file: 14786845/tftp-deploy-xcyw_x31/kernel/cmdline
10090 11:07:50.536267
10091 11:07:50.549007 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10092 11:07:50.549469
10093 11:07:50.552496 Loading FIT.
10094 11:07:50.552882
10095 11:07:50.555919 Image ramdisk-1 has 60979880 bytes.
10096 11:07:50.556307
10097 11:07:50.556607 Image fdt-1 has 47258 bytes.
10098 11:07:50.559489
10099 11:07:50.559946 Image kernel-1 has 13116259 bytes.
10100 11:07:50.560251
10101 11:07:50.569220 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10102 11:07:50.569640
10103 11:07:50.585390 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10104 11:07:50.588751
10105 11:07:50.592145 Choosing best match conf-1 for compat google,spherion-rev3.
10106 11:07:50.596425
10107 11:07:50.601581 Connected to device vid:did:rid of 1ae0:0028:00
10108 11:07:50.609207
10109 11:07:50.612648 tpm_get_response: command 0x17b, return code 0x0
10110 11:07:50.613032
10111 11:07:50.615982 ec_init: CrosEC protocol v3 supported (256, 248)
10112 11:07:50.620348
10113 11:07:50.623510 tpm_cleanup: add release locality here.
10114 11:07:50.623894
10115 11:07:50.624186 Shutting down all USB controllers.
10116 11:07:50.627406
10117 11:07:50.627786 Removing current net device
10118 11:07:50.628080
10119 11:07:50.633583 Exiting depthcharge with code 4 at timestamp: 69703618
10120 11:07:50.633969
10121 11:07:50.637187 LZMA decompressing kernel-1 to 0x821a6718
10122 11:07:50.637715
10123 11:07:50.640063 LZMA decompressing kernel-1 to 0x40000000
10124 11:07:52.255583
10125 11:07:52.256073 jumping to kernel
10126 11:07:52.258321 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10127 11:07:52.258827 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10128 11:07:52.259195 Setting prompt string to ['Linux version [0-9]']
10129 11:07:52.259537 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10130 11:07:52.259881 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10131 11:07:52.306089
10132 11:07:52.309785 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10133 11:07:52.313196 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10134 11:07:52.313539 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10135 11:07:52.313750 Setting prompt string to []
10136 11:07:52.314003 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10137 11:07:52.314220 Using line separator: #'\n'#
10138 11:07:52.314420 No login prompt set.
10139 11:07:52.314669 Parsing kernel messages
10140 11:07:52.314826 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10141 11:07:52.315093 [login-action] Waiting for messages, (timeout 00:03:38)
10142 11:07:52.315258 Waiting using forced prompt support (timeout 00:01:49)
10143 11:07:52.332807 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10144 11:07:52.336200 [ 0.000000] random: crng init done
10145 11:07:52.339753 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10146 11:07:52.342435 [ 0.000000] efi: UEFI not found.
10147 11:07:52.352616 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10148 11:07:52.359556 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10149 11:07:52.369674 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10150 11:07:52.379187 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10151 11:07:52.385906 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10152 11:07:52.388845 [ 0.000000] printk: bootconsole [mtk8250] enabled
10153 11:07:52.397613 [ 0.000000] NUMA: No NUMA configuration found
10154 11:07:52.404071 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10155 11:07:52.410307 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10156 11:07:52.410737 [ 0.000000] Zone ranges:
10157 11:07:52.416986 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10158 11:07:52.420725 [ 0.000000] DMA32 empty
10159 11:07:52.427124 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10160 11:07:52.430045 [ 0.000000] Movable zone start for each node
10161 11:07:52.433467 [ 0.000000] Early memory node ranges
10162 11:07:52.440088 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10163 11:07:52.446935 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10164 11:07:52.453602 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10165 11:07:52.459970 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10166 11:07:52.466867 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10167 11:07:52.473166 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10168 11:07:52.504854 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10169 11:07:52.510884 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10170 11:07:52.517960 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10171 11:07:52.521008 [ 0.000000] psci: probing for conduit method from DT.
10172 11:07:52.527745 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10173 11:07:52.530967 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10174 11:07:52.538001 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10175 11:07:52.540653 [ 0.000000] psci: SMC Calling Convention v1.2
10176 11:07:52.547651 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10177 11:07:52.550622 [ 0.000000] Detected VIPT I-cache on CPU0
10178 11:07:52.557362 [ 0.000000] CPU features: detected: GIC system register CPU interface
10179 11:07:52.563994 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10180 11:07:52.570328 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10181 11:07:52.576954 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10182 11:07:52.583644 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10183 11:07:52.593847 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10184 11:07:52.596919 [ 0.000000] alternatives: applying boot alternatives
10185 11:07:52.603176 [ 0.000000] Fallback order for Node 0: 0
10186 11:07:52.609927 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10187 11:07:52.613331 [ 0.000000] Policy zone: Normal
10188 11:07:52.626729 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10189 11:07:52.636685 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10190 11:07:52.647393 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10191 11:07:52.656925 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10192 11:07:52.663280 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10193 11:07:52.666610 <6>[ 0.000000] software IO TLB: area num 8.
10194 11:07:52.723224 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10195 11:07:52.804255 <6>[ 0.000000] Memory: 3790092K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 368372K reserved, 32768K cma-reserved)
10196 11:07:52.810581 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10197 11:07:52.817587 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10198 11:07:52.820530 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10199 11:07:52.827368 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10200 11:07:52.833562 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10201 11:07:52.837030 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10202 11:07:52.847295 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10203 11:07:52.853782 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10204 11:07:52.860530 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10205 11:07:52.866981 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10206 11:07:52.870001 <6>[ 0.000000] GICv3: 608 SPIs implemented
10207 11:07:52.873316 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10208 11:07:52.879709 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10209 11:07:52.883160 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10210 11:07:52.889760 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10211 11:07:52.902845 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10212 11:07:52.916228 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10213 11:07:52.922729 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10214 11:07:52.930817 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10215 11:07:52.943769 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10216 11:07:52.950196 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10217 11:07:52.956723 <6>[ 0.009169] Console: colour dummy device 80x25
10218 11:07:52.966849 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10219 11:07:52.973627 <6>[ 0.024340] pid_max: default: 32768 minimum: 301
10220 11:07:52.976607 <6>[ 0.029212] LSM: Security Framework initializing
10221 11:07:52.983392 <6>[ 0.034125] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10222 11:07:52.993391 <6>[ 0.041780] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10223 11:07:53.000152 <6>[ 0.051019] cblist_init_generic: Setting adjustable number of callback queues.
10224 11:07:53.006557 <6>[ 0.058461] cblist_init_generic: Setting shift to 3 and lim to 1.
10225 11:07:53.016749 <6>[ 0.064800] cblist_init_generic: Setting adjustable number of callback queues.
10226 11:07:53.019803 <6>[ 0.072273] cblist_init_generic: Setting shift to 3 and lim to 1.
10227 11:07:53.026607 <6>[ 0.078712] rcu: Hierarchical SRCU implementation.
10228 11:07:53.033173 <6>[ 0.083758] rcu: Max phase no-delay instances is 1000.
10229 11:07:53.040040 <6>[ 0.090772] EFI services will not be available.
10230 11:07:53.042710 <6>[ 0.095730] smp: Bringing up secondary CPUs ...
10231 11:07:53.050822 <6>[ 0.100783] Detected VIPT I-cache on CPU1
10232 11:07:53.057334 <6>[ 0.100854] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10233 11:07:53.064019 <6>[ 0.100883] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10234 11:07:53.067221 <6>[ 0.101227] Detected VIPT I-cache on CPU2
10235 11:07:53.077380 <6>[ 0.101283] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10236 11:07:53.084030 <6>[ 0.101299] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10237 11:07:53.087593 <6>[ 0.101560] Detected VIPT I-cache on CPU3
10238 11:07:53.093824 <6>[ 0.101611] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10239 11:07:53.100446 <6>[ 0.101625] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10240 11:07:53.103671 <6>[ 0.101930] CPU features: detected: Spectre-v4
10241 11:07:53.110182 <6>[ 0.101936] CPU features: detected: Spectre-BHB
10242 11:07:53.113583 <6>[ 0.101942] Detected PIPT I-cache on CPU4
10243 11:07:53.120190 <6>[ 0.102002] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10244 11:07:53.127168 <6>[ 0.102020] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10245 11:07:53.133338 <6>[ 0.102309] Detected PIPT I-cache on CPU5
10246 11:07:53.140163 <6>[ 0.102370] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10247 11:07:53.146419 <6>[ 0.102386] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10248 11:07:53.149966 <6>[ 0.102667] Detected PIPT I-cache on CPU6
10249 11:07:53.156612 <6>[ 0.102730] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10250 11:07:53.166549 <6>[ 0.102746] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10251 11:07:53.169667 <6>[ 0.103047] Detected PIPT I-cache on CPU7
10252 11:07:53.176499 <6>[ 0.103113] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10253 11:07:53.182669 <6>[ 0.103129] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10254 11:07:53.185863 <6>[ 0.103177] smp: Brought up 1 node, 8 CPUs
10255 11:07:53.192558 <6>[ 0.244516] SMP: Total of 8 processors activated.
10256 11:07:53.195992 <6>[ 0.249438] CPU features: detected: 32-bit EL0 Support
10257 11:07:53.205716 <6>[ 0.254800] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10258 11:07:53.212588 <6>[ 0.263601] CPU features: detected: Common not Private translations
10259 11:07:53.219134 <6>[ 0.270077] CPU features: detected: CRC32 instructions
10260 11:07:53.222391 <6>[ 0.275462] CPU features: detected: RCpc load-acquire (LDAPR)
10261 11:07:53.229786 <6>[ 0.281421] CPU features: detected: LSE atomic instructions
10262 11:07:53.235886 <6>[ 0.287203] CPU features: detected: Privileged Access Never
10263 11:07:53.242330 <6>[ 0.292983] CPU features: detected: RAS Extension Support
10264 11:07:53.249055 <6>[ 0.298591] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10265 11:07:53.252117 <6>[ 0.305854] CPU: All CPU(s) started at EL2
10266 11:07:53.258982 <6>[ 0.310197] alternatives: applying system-wide alternatives
10267 11:07:53.267764 <6>[ 0.320184] devtmpfs: initialized
10268 11:07:53.282836 <6>[ 0.328322] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10269 11:07:53.289375 <6>[ 0.338286] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10270 11:07:53.296174 <6>[ 0.346530] pinctrl core: initialized pinctrl subsystem
10271 11:07:53.299067 <6>[ 0.353201] DMI not present or invalid.
10272 11:07:53.305635 <6>[ 0.357602] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10273 11:07:53.315544 <6>[ 0.364466] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10274 11:07:53.322382 <6>[ 0.371912] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10275 11:07:53.331919 <6>[ 0.380003] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10276 11:07:53.335926 <6>[ 0.388155] audit: initializing netlink subsys (disabled)
10277 11:07:53.345541 <5>[ 0.393852] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10278 11:07:53.352068 <6>[ 0.394550] thermal_sys: Registered thermal governor 'step_wise'
10279 11:07:53.358995 <6>[ 0.401816] thermal_sys: Registered thermal governor 'power_allocator'
10280 11:07:53.361847 <6>[ 0.408067] cpuidle: using governor menu
10281 11:07:53.368719 <6>[ 0.419025] NET: Registered PF_QIPCRTR protocol family
10282 11:07:53.375096 <6>[ 0.424524] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10283 11:07:53.381842 <6>[ 0.431628] ASID allocator initialised with 32768 entries
10284 11:07:53.384788 <6>[ 0.438186] Serial: AMBA PL011 UART driver
10285 11:07:53.395363 <4>[ 0.447514] Trying to register duplicate clock ID: 134
10286 11:07:53.452820 <6>[ 0.508747] KASLR enabled
10287 11:07:53.467359 <6>[ 0.516425] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10288 11:07:53.473805 <6>[ 0.523436] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10289 11:07:53.480067 <6>[ 0.529924] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10290 11:07:53.486996 <6>[ 0.536931] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10291 11:07:53.494179 <6>[ 0.543417] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10292 11:07:53.500372 <6>[ 0.550423] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10293 11:07:53.506835 <6>[ 0.556911] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10294 11:07:53.513775 <6>[ 0.563917] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10295 11:07:53.517297 <6>[ 0.571424] ACPI: Interpreter disabled.
10296 11:07:53.525975 <6>[ 0.577855] iommu: Default domain type: Translated
10297 11:07:53.532381 <6>[ 0.582969] iommu: DMA domain TLB invalidation policy: strict mode
10298 11:07:53.535726 <5>[ 0.589619] SCSI subsystem initialized
10299 11:07:53.542186 <6>[ 0.593781] usbcore: registered new interface driver usbfs
10300 11:07:53.548761 <6>[ 0.599512] usbcore: registered new interface driver hub
10301 11:07:53.552017 <6>[ 0.605062] usbcore: registered new device driver usb
10302 11:07:53.558965 <6>[ 0.611167] pps_core: LinuxPPS API ver. 1 registered
10303 11:07:53.568620 <6>[ 0.616361] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10304 11:07:53.572449 <6>[ 0.625710] PTP clock support registered
10305 11:07:53.575381 <6>[ 0.629953] EDAC MC: Ver: 3.0.0
10306 11:07:53.582944 <6>[ 0.635113] FPGA manager framework
10307 11:07:53.589445 <6>[ 0.638800] Advanced Linux Sound Architecture Driver Initialized.
10308 11:07:53.592566 <6>[ 0.645594] vgaarb: loaded
10309 11:07:53.599557 <6>[ 0.648754] clocksource: Switched to clocksource arch_sys_counter
10310 11:07:53.602447 <5>[ 0.655193] VFS: Disk quotas dquot_6.6.0
10311 11:07:53.609541 <6>[ 0.659379] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10312 11:07:53.612532 <6>[ 0.666564] pnp: PnP ACPI: disabled
10313 11:07:53.621024 <6>[ 0.673289] NET: Registered PF_INET protocol family
10314 11:07:53.627345 <6>[ 0.678683] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10315 11:07:53.639822 <6>[ 0.688699] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10316 11:07:53.650063 <6>[ 0.697484] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10317 11:07:53.656372 <6>[ 0.705452] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10318 11:07:53.662912 <6>[ 0.713850] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10319 11:07:53.673837 <6>[ 0.722507] TCP: Hash tables configured (established 32768 bind 32768)
10320 11:07:53.679908 <6>[ 0.729350] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10321 11:07:53.686933 <6>[ 0.736371] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10322 11:07:53.693432 <6>[ 0.743884] NET: Registered PF_UNIX/PF_LOCAL protocol family
10323 11:07:53.699941 <6>[ 0.750043] RPC: Registered named UNIX socket transport module.
10324 11:07:53.703215 <6>[ 0.756198] RPC: Registered udp transport module.
10325 11:07:53.710200 <6>[ 0.761133] RPC: Registered tcp transport module.
10326 11:07:53.716477 <6>[ 0.766064] RPC: Registered tcp NFSv4.1 backchannel transport module.
10327 11:07:53.719843 <6>[ 0.772734] PCI: CLS 0 bytes, default 64
10328 11:07:53.722894 <6>[ 0.777047] Unpacking initramfs...
10329 11:07:53.732779 <6>[ 0.781104] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10330 11:07:53.739554 <6>[ 0.789783] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10331 11:07:53.746312 <6>[ 0.798623] kvm [1]: IPA Size Limit: 40 bits
10332 11:07:53.750135 <6>[ 0.803137] kvm [1]: GICv3: no GICV resource entry
10333 11:07:53.756654 <6>[ 0.808156] kvm [1]: disabling GICv2 emulation
10334 11:07:53.762758 <6>[ 0.812847] kvm [1]: GIC system register CPU interface enabled
10335 11:07:53.766211 <6>[ 0.819020] kvm [1]: vgic interrupt IRQ18
10336 11:07:53.772753 <6>[ 0.823384] kvm [1]: VHE mode initialized successfully
10337 11:07:53.775818 <5>[ 0.829739] Initialise system trusted keyrings
10338 11:07:53.782638 <6>[ 0.834548] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10339 11:07:53.792340 <6>[ 0.844500] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10340 11:07:53.799107 <5>[ 0.850887] NFS: Registering the id_resolver key type
10341 11:07:53.801898 <5>[ 0.856188] Key type id_resolver registered
10342 11:07:53.808881 <5>[ 0.860603] Key type id_legacy registered
10343 11:07:53.815647 <6>[ 0.864879] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10344 11:07:53.822403 <6>[ 0.871798] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10345 11:07:53.828568 <6>[ 0.879510] 9p: Installing v9fs 9p2000 file system support
10346 11:07:53.865552 <5>[ 0.917473] Key type asymmetric registered
10347 11:07:53.868601 <5>[ 0.921807] Asymmetric key parser 'x509' registered
10348 11:07:53.878705 <6>[ 0.926952] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10349 11:07:53.881684 <6>[ 0.934568] io scheduler mq-deadline registered
10350 11:07:53.885009 <6>[ 0.939332] io scheduler kyber registered
10351 11:07:53.904165 <6>[ 0.956642] EINJ: ACPI disabled.
10352 11:07:53.937793 <4>[ 0.983053] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10353 11:07:53.947515 <4>[ 0.993680] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10354 11:07:53.962822 <6>[ 1.014897] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10355 11:07:53.970763 <6>[ 1.022905] printk: console [ttyS0] disabled
10356 11:07:53.998985 <6>[ 1.047546] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10357 11:07:54.005423 <6>[ 1.057019] printk: console [ttyS0] enabled
10358 11:07:54.008382 <6>[ 1.057019] printk: console [ttyS0] enabled
10359 11:07:54.015175 <6>[ 1.065923] printk: bootconsole [mtk8250] disabled
10360 11:07:54.018568 <6>[ 1.065923] printk: bootconsole [mtk8250] disabled
10361 11:07:54.025567 <6>[ 1.077260] SuperH (H)SCI(F) driver initialized
10362 11:07:54.028981 <6>[ 1.082568] msm_serial: driver initialized
10363 11:07:54.042509 <6>[ 1.091557] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10364 11:07:54.052819 <6>[ 1.100104] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10365 11:07:54.059743 <6>[ 1.108649] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10366 11:07:54.069268 <6>[ 1.117277] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10367 11:07:54.076036 <6>[ 1.125983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10368 11:07:54.085600 <6>[ 1.134697] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10369 11:07:54.095470 <6>[ 1.143237] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10370 11:07:54.102306 <6>[ 1.152053] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10371 11:07:54.112133 <6>[ 1.160596] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10372 11:07:54.124499 <6>[ 1.176521] loop: module loaded
10373 11:07:54.130933 <6>[ 1.182593] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10374 11:07:54.153325 <4>[ 1.205517] mtk-pmic-keys: Failed to locate of_node [id: -1]
10375 11:07:54.160620 <6>[ 1.212527] megasas: 07.719.03.00-rc1
10376 11:07:54.170013 <6>[ 1.222189] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10377 11:07:54.176537 <6>[ 1.228134] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10378 11:07:54.193045 <6>[ 1.244828] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10379 11:07:54.248812 <6>[ 1.294447] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10380 11:07:56.460140 <6>[ 3.512667] Freeing initrd memory: 59548K
10381 11:07:56.471539 <6>[ 3.524429] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10382 11:07:56.482918 <6>[ 3.535437] tun: Universal TUN/TAP device driver, 1.6
10383 11:07:56.486088 <6>[ 3.541540] thunder_xcv, ver 1.0
10384 11:07:56.489498 <6>[ 3.545047] thunder_bgx, ver 1.0
10385 11:07:56.493071 <6>[ 3.548536] nicpf, ver 1.0
10386 11:07:56.503388 <6>[ 3.552577] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10387 11:07:56.506644 <6>[ 3.560053] hns3: Copyright (c) 2017 Huawei Corporation.
10388 11:07:56.513103 <6>[ 3.565642] hclge is initializing
10389 11:07:56.516322 <6>[ 3.569224] e1000: Intel(R) PRO/1000 Network Driver
10390 11:07:56.523270 <6>[ 3.574353] e1000: Copyright (c) 1999-2006 Intel Corporation.
10391 11:07:56.526531 <6>[ 3.580364] e1000e: Intel(R) PRO/1000 Network Driver
10392 11:07:56.532854 <6>[ 3.585580] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10393 11:07:56.540057 <6>[ 3.591768] igb: Intel(R) Gigabit Ethernet Network Driver
10394 11:07:56.546365 <6>[ 3.597418] igb: Copyright (c) 2007-2014 Intel Corporation.
10395 11:07:56.553174 <6>[ 3.603254] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10396 11:07:56.559817 <6>[ 3.609773] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10397 11:07:56.562748 <6>[ 3.616239] sky2: driver version 1.30
10398 11:07:56.569574 <6>[ 3.621189] usbcore: registered new device driver r8152-cfgselector
10399 11:07:56.576074 <6>[ 3.627723] usbcore: registered new interface driver r8152
10400 11:07:56.582374 <6>[ 3.633543] VFIO - User Level meta-driver version: 0.3
10401 11:07:56.589204 <6>[ 3.641789] usbcore: registered new interface driver usb-storage
10402 11:07:56.595671 <6>[ 3.648233] usbcore: registered new device driver onboard-usb-hub
10403 11:07:56.604768 <6>[ 3.657385] mt6397-rtc mt6359-rtc: registered as rtc0
10404 11:07:56.615154 <6>[ 3.662848] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:07:56 UTC (1720609676)
10405 11:07:56.617947 <6>[ 3.672423] i2c_dev: i2c /dev entries driver
10406 11:07:56.631800 <4>[ 3.684511] cpu cpu0: supply cpu not found, using dummy regulator
10407 11:07:56.638742 <4>[ 3.690974] cpu cpu1: supply cpu not found, using dummy regulator
10408 11:07:56.644986 <4>[ 3.697383] cpu cpu2: supply cpu not found, using dummy regulator
10409 11:07:56.651806 <4>[ 3.703780] cpu cpu3: supply cpu not found, using dummy regulator
10410 11:07:56.658477 <4>[ 3.710176] cpu cpu4: supply cpu not found, using dummy regulator
10411 11:07:56.665092 <4>[ 3.716569] cpu cpu5: supply cpu not found, using dummy regulator
10412 11:07:56.671542 <4>[ 3.722986] cpu cpu6: supply cpu not found, using dummy regulator
10413 11:07:56.677897 <4>[ 3.729387] cpu cpu7: supply cpu not found, using dummy regulator
10414 11:07:56.697590 <6>[ 3.749994] cpu cpu0: EM: created perf domain
10415 11:07:56.700610 <6>[ 3.754900] cpu cpu4: EM: created perf domain
10416 11:07:56.708017 <6>[ 3.760475] sdhci: Secure Digital Host Controller Interface driver
10417 11:07:56.714418 <6>[ 3.766906] sdhci: Copyright(c) Pierre Ossman
10418 11:07:56.721661 <6>[ 3.771824] Synopsys Designware Multimedia Card Interface Driver
10419 11:07:56.727520 <6>[ 3.778425] sdhci-pltfm: SDHCI platform and OF driver helper
10420 11:07:56.730902 <6>[ 3.778455] mmc0: CQHCI version 5.10
10421 11:07:56.738149 <6>[ 3.788381] ledtrig-cpu: registered to indicate activity on CPUs
10422 11:07:56.744147 <6>[ 3.795338] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10423 11:07:56.750690 <6>[ 3.802366] usbcore: registered new interface driver usbhid
10424 11:07:56.753797 <6>[ 3.808188] usbhid: USB HID core driver
10425 11:07:56.760476 <6>[ 3.812376] spi_master spi0: will run message pump with realtime priority
10426 11:07:56.803057 <6>[ 3.849176] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10427 11:07:56.821467 <6>[ 3.864389] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10428 11:07:56.824658 <6>[ 3.877327] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10429 11:07:56.831831 <6>[ 3.884572] cros-ec-spi spi0.0: Chrome EC device registered
10430 11:07:56.838752 <6>[ 3.890579] mmc0: Command Queue Engine enabled
10431 11:07:56.845052 <6>[ 3.895305] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10432 11:07:56.848544 <6>[ 3.902814] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10433 11:07:56.858948 <6>[ 3.911659] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10434 11:07:56.866804 <6>[ 3.919163] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10435 11:07:56.876723 <6>[ 3.923106] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10436 11:07:56.880239 <6>[ 3.925088] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10437 11:07:56.886202 <6>[ 3.934707] NET: Registered PF_PACKET protocol family
10438 11:07:56.893000 <6>[ 3.939564] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10439 11:07:56.896297 <6>[ 3.944301] 9pnet: Installing 9P2000 support
10440 11:07:56.902743 <5>[ 3.955289] Key type dns_resolver registered
10441 11:07:56.906359 <6>[ 3.960207] registered taskstats version 1
10442 11:07:56.912992 <5>[ 3.964591] Loading compiled-in X.509 certificates
10443 11:07:56.940935 <4>[ 3.986549] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10444 11:07:56.950464 <4>[ 3.997273] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10445 11:07:56.964721 <6>[ 4.017400] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10446 11:07:56.972017 <6>[ 4.024351] xhci-mtk 11200000.usb: xHCI Host Controller
10447 11:07:56.978266 <6>[ 4.029879] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10448 11:07:56.988518 <6>[ 4.037736] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10449 11:07:56.994843 <6>[ 4.047168] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10450 11:07:57.001775 <6>[ 4.053333] xhci-mtk 11200000.usb: xHCI Host Controller
10451 11:07:57.008196 <6>[ 4.058823] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10452 11:07:57.014695 <6>[ 4.066477] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10453 11:07:57.021633 <6>[ 4.074253] hub 1-0:1.0: USB hub found
10454 11:07:57.024652 <6>[ 4.078279] hub 1-0:1.0: 1 port detected
10455 11:07:57.034896 <6>[ 4.082572] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10456 11:07:57.037875 <6>[ 4.091286] hub 2-0:1.0: USB hub found
10457 11:07:57.041347 <6>[ 4.095316] hub 2-0:1.0: 1 port detected
10458 11:07:57.050093 <6>[ 4.102593] mtk-msdc 11f70000.mmc: Got CD GPIO
10459 11:07:57.067476 <6>[ 4.116696] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10460 11:07:57.077338 <6>[ 4.125073] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10461 11:07:57.084072 <6>[ 4.133413] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10462 11:07:57.093812 <6>[ 4.141750] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10463 11:07:57.100422 <6>[ 4.150090] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10464 11:07:57.110186 <6>[ 4.158430] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10465 11:07:57.116872 <6>[ 4.166768] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10466 11:07:57.126880 <6>[ 4.175107] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10467 11:07:57.133650 <6>[ 4.183445] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10468 11:07:57.143039 <6>[ 4.191783] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10469 11:07:57.150228 <6>[ 4.200121] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10470 11:07:57.160546 <6>[ 4.208468] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10471 11:07:57.166714 <6>[ 4.216808] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10472 11:07:57.176536 <6>[ 4.225146] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10473 11:07:57.183257 <6>[ 4.233490] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10474 11:07:57.189911 <6>[ 4.242147] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10475 11:07:57.196437 <6>[ 4.249253] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10476 11:07:57.203145 <6>[ 4.256035] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10477 11:07:57.213405 <6>[ 4.262771] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10478 11:07:57.220167 <6>[ 4.269715] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10479 11:07:57.226559 <6>[ 4.276566] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10480 11:07:57.236665 <6>[ 4.285699] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10481 11:07:57.246324 <6>[ 4.294818] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10482 11:07:57.257125 <6>[ 4.304113] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10483 11:07:57.265976 <6>[ 4.313580] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10484 11:07:57.276247 <6>[ 4.323047] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10485 11:07:57.282545 <6>[ 4.332166] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10486 11:07:57.292425 <6>[ 4.341632] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10487 11:07:57.302563 <6>[ 4.350755] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10488 11:07:57.312380 <6>[ 4.360052] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10489 11:07:57.322173 <6>[ 4.370212] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10490 11:07:57.332469 <6>[ 4.382252] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10491 11:07:57.455337 <6>[ 4.505029] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10492 11:07:57.610407 <6>[ 4.662826] hub 1-1:1.0: USB hub found
10493 11:07:57.613425 <6>[ 4.667351] hub 1-1:1.0: 4 ports detected
10494 11:07:57.625360 <6>[ 4.677982] hub 1-1:1.0: USB hub found
10495 11:07:57.628555 <6>[ 4.682302] hub 1-1:1.0: 4 ports detected
10496 11:07:57.735904 <6>[ 4.785264] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10497 11:07:57.761307 <6>[ 4.814022] hub 2-1:1.0: USB hub found
10498 11:07:57.764876 <6>[ 4.818471] hub 2-1:1.0: 3 ports detected
10499 11:07:57.775304 <6>[ 4.828146] hub 2-1:1.0: USB hub found
10500 11:07:57.778688 <6>[ 4.832545] hub 2-1:1.0: 3 ports detected
10501 11:07:57.951233 <6>[ 5.001021] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10502 11:07:58.084162 <6>[ 5.136712] hub 1-1.4:1.0: USB hub found
10503 11:07:58.087319 <6>[ 5.141378] hub 1-1.4:1.0: 2 ports detected
10504 11:07:58.099588 <6>[ 5.152580] hub 1-1.4:1.0: USB hub found
10505 11:07:58.102802 <6>[ 5.157184] hub 1-1.4:1.0: 2 ports detected
10506 11:07:58.163470 <6>[ 5.213199] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10507 11:07:58.272098 <6>[ 5.321701] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10508 11:07:58.307881 <4>[ 5.357314] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10509 11:07:58.317471 <4>[ 5.366458] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10510 11:07:58.361828 <6>[ 5.414638] r8152 2-1.3:1.0 eth0: v1.12.13
10511 11:07:58.399423 <6>[ 5.449006] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10512 11:07:58.595408 <6>[ 5.645029] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10513 11:07:59.969742 <6>[ 7.022792] r8152 2-1.3:1.0 eth0: carrier on
10514 11:08:02.375142 <5>[ 7.044871] Sending DHCP requests .., OK
10515 11:08:02.381975 <6>[ 9.433210] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10516 11:08:02.385752 <6>[ 9.441501] IP-Config: Complete:
10517 11:08:02.399406 <6>[ 9.444998] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10518 11:08:02.405479 <6>[ 9.455715] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10519 11:08:02.411973 <6>[ 9.464337] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10520 11:08:02.418968 <6>[ 9.464346] nameserver0=192.168.201.1
10521 11:08:02.422074 <6>[ 9.476532] clk: Disabling unused clocks
10522 11:08:02.425393 <6>[ 9.482067] ALSA device list:
10523 11:08:02.432177 <6>[ 9.485321] No soundcards found.
10524 11:08:02.439514 <6>[ 9.492668] Freeing unused kernel memory: 8512K
10525 11:08:02.442767 <6>[ 9.497555] Run /init as init process
10526 11:08:02.473009 <6>[ 9.526157] NET: Registered PF_INET6 protocol family
10527 11:08:02.479731 <6>[ 9.532804] Segment Routing with IPv6
10528 11:08:02.482811 <6>[ 9.536764] In-situ OAM (IOAM) with IPv6
10529 11:08:02.522274 <30>[ 9.549010] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10530 11:08:02.529144 <30>[ 9.582044] systemd[1]: Detected architecture arm64.
10531 11:08:02.529710
10532 11:08:02.535288 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10533 11:08:02.535773
10534 11:08:02.547840 <30>[ 9.601066] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10535 11:08:02.671130 <30>[ 9.721189] systemd[1]: Queued start job for default target graphical.target.
10536 11:08:02.709094 <30>[ 9.758939] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10537 11:08:02.715977 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10538 11:08:02.739784 <30>[ 9.789775] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10539 11:08:02.749685 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10540 11:08:02.769174 <30>[ 9.819169] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10541 11:08:02.780037 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10542 11:08:02.796584 <30>[ 9.846325] systemd[1]: Created slice user.slice - User and Session Slice.
10543 11:08:02.802938 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10544 11:08:02.826574 <30>[ 9.873276] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10545 11:08:02.833192 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10546 11:08:02.854748 <30>[ 9.901662] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10547 11:08:02.861213 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10548 11:08:02.888715 <30>[ 9.929162] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10549 11:08:02.898770 <30>[ 9.948986] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10550 11:08:02.905359 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10551 11:08:02.923621 <30>[ 9.973501] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10552 11:08:02.933146 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10553 11:08:02.951086 <30>[ 10.001223] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10554 11:08:02.961006 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10555 11:08:02.980036 <30>[ 10.033252] systemd[1]: Reached target paths.target - Path Units.
10556 11:08:02.989616 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10557 11:08:03.007410 <30>[ 10.057518] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10558 11:08:03.014152 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10559 11:08:03.027790 <30>[ 10.081045] systemd[1]: Reached target slices.target - Slice Units.
10560 11:08:03.037484 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10561 11:08:03.052481 <30>[ 10.105535] systemd[1]: Reached target swap.target - Swaps.
10562 11:08:03.059057 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10563 11:08:03.079279 <30>[ 10.129549] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10564 11:08:03.089186 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10565 11:08:03.107332 <30>[ 10.157499] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10566 11:08:03.117404 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10567 11:08:03.136798 <30>[ 10.187075] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10568 11:08:03.146680 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10569 11:08:03.163559 <30>[ 10.213738] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10570 11:08:03.173474 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10571 11:08:03.191473 <30>[ 10.241656] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10572 11:08:03.198125 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10573 11:08:03.216090 <30>[ 10.265701] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10574 11:08:03.225462 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10575 11:08:03.243305 <30>[ 10.293625] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10576 11:08:03.253700 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10577 11:08:03.303286 <30>[ 10.353320] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10578 11:08:03.309592 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10579 11:08:03.329346 <30>[ 10.379126] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10580 11:08:03.335686 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10581 11:08:03.357477 <30>[ 10.407164] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10582 11:08:03.363947 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10583 11:08:03.389878 <30>[ 10.433446] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10584 11:08:03.402153 <30>[ 10.452222] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10585 11:08:03.412110 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10586 11:08:03.430031 <30>[ 10.480157] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10587 11:08:03.436807 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10588 11:08:03.459239 <30>[ 10.509076] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10589 11:08:03.469169 Startin<6>[ 10.518428] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10590 11:08:03.475378 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10591 11:08:03.500319 <30>[ 10.550334] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10592 11:08:03.506888 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10593 11:08:03.563555 <30>[ 10.613696] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10594 11:08:03.573377 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10595 11:08:03.600101 <30>[ 10.650353] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10596 11:08:03.607119 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10597 11:08:03.636080 <30>[ 10.686000] systemd[1]: Starting systemd-journald.service - Journal Service...
10598 11:08:03.642391 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10599 11:08:03.661370 <30>[ 10.711735] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10600 11:08:03.668371 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10601 11:08:03.693356 <30>[ 10.740105] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10602 11:08:03.699867 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10603 11:08:03.723263 <30>[ 10.773585] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10604 11:08:03.733455 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10605 11:08:03.760814 <30>[ 10.810779] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10606 11:08:03.767288 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10607 11:08:03.791990 <30>[ 10.841975] systemd[1]: Started systemd-journald.service - Journal Service.
10608 11:08:03.798490 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10609 11:08:03.822526 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10610 11:08:03.840201 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10611 11:08:03.860575 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10612 11:08:03.881691 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10613 11:08:03.902254 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10614 11:08:03.922489 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10615 11:08:03.940821 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10616 11:08:03.960699 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10617 11:08:03.982886 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10618 11:08:04.000725 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10619 11:08:04.024975 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10620 11:08:04.049514 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10621 11:08:04.056112 See 'systemctl status systemd-remount-fs.service' for details.
10622 11:08:04.065937 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10623 11:08:04.086169 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10624 11:08:04.123303 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10625 11:08:04.142038 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10626 11:08:04.169792 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed..<46>[ 11.219731] systemd-journald[196]: Received client request to flush runtime journal.
10627 11:08:04.170319 .
10628 11:08:04.196000 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10629 11:08:04.219691 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10630 11:08:04.245040 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10631 11:08:04.264703 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10632 11:08:04.284531 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10633 11:08:04.303902 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10634 11:08:04.324063 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10635 11:08:04.380489 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10636 11:08:04.405764 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10637 11:08:04.423696 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10638 11:08:04.443532 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10639 11:08:04.491905 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10640 11:08:04.516914 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10641 11:08:04.543394 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10642 11:08:04.562722 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10643 11:08:04.602118 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10644 11:08:04.741329 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10645 11:08:04.766189 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10646 11:08:04.806181 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10647 11:08:04.832513 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10648 11:08:04.867760 <6>[ 11.918152] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10649 11:08:04.874750 <6>[ 11.926244] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10650 11:08:04.887957 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slic<6>[ 11.938927] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10651 11:08:04.897930 e /system/system<6>[ 11.940276] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10652 11:08:04.898450 d-backlight.
10653 11:08:04.904282 <6>[ 11.943079] remoteproc remoteproc0: scp is available
10654 11:08:04.910752 <6>[ 11.943150] remoteproc remoteproc0: powering up scp
10655 11:08:04.917586 <6>[ 11.943155] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10656 11:08:04.923982 <6>[ 11.943171] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10657 11:08:04.933943 <6>[ 11.947305] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10658 11:08:04.940915 <6>[ 11.956571] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10659 11:08:04.950668 <4>[ 11.956810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10660 11:08:04.957071 <6>[ 11.963302] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10661 11:08:04.966847 <6>[ 11.969120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10662 11:08:04.973801 <3>[ 11.978616] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 11:08:04.983611 <6>[ 11.982574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10664 11:08:04.990039 <6>[ 11.982735] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10665 11:08:05.000453 <3>[ 11.992198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 11:08:05.006525 <6>[ 11.999171] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10667 11:08:05.013154 <3>[ 12.008455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 11:08:05.023139 <6>[ 12.016977] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10669 11:08:05.033131 <6>[ 12.016999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10670 11:08:05.039893 <4>[ 12.049441] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10671 11:08:05.046457 <6>[ 12.068707] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10672 11:08:05.056351 <6>[ 12.073164] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10673 11:08:05.062896 <6>[ 12.073177] remoteproc remoteproc0: remote processor scp is now up
10674 11:08:05.069086 <4>[ 12.081832] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10675 11:08:05.075971 <3>[ 12.081890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 11:08:05.086133 <3>[ 12.081902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 11:08:05.092639 <3>[ 12.081906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 11:08:05.102438 <3>[ 12.081910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 11:08:05.109009 <3>[ 12.081913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 11:08:05.115365 <3>[ 12.081933] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 11:08:05.125373 <3>[ 12.081961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 11:08:05.132215 <3>[ 12.081964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 11:08:05.141644 <3>[ 12.081966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 11:08:05.144905 <6>[ 12.090863] mc: Linux media interface: v0.10
10685 11:08:05.154815 <3>[ 12.091917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 11:08:05.162067 <3>[ 12.091944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 11:08:05.171637 <3>[ 12.091952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 11:08:05.177943 <3>[ 12.091966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 11:08:05.184750 <3>[ 12.091976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 11:08:05.194406 <3>[ 12.092055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 11:08:05.201147 <6>[ 12.166057] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10692 11:08:05.211477 <6>[ 12.233539] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10693 11:08:05.218344 <6>[ 12.240813] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10694 11:08:05.228460 <4>[ 12.248780] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10695 11:08:05.231801 <4>[ 12.248780] Fallback method does not support PEC.
10696 11:08:05.238064 <6>[ 12.253879] pci_bus 0000:00: root bus resource [bus 00-ff]
10697 11:08:05.248577 <3>[ 12.275166] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10698 11:08:05.255045 <6>[ 12.277817] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10699 11:08:05.261882 <6>[ 12.304699] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10700 11:08:05.272182 <6>[ 12.305638] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10701 11:08:05.282081 <6>[ 12.305774] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10702 11:08:05.291586 <3>[ 12.319854] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10703 11:08:05.298384 <6>[ 12.322024] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10704 11:08:05.308599 [[0;32m OK [<6>[ 12.356963] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10705 11:08:05.311942 0m] Reached targ<6>[ 12.365447] pci 0000:00:00.0: supports D1 D2
10706 11:08:05.322116 et [0;1;39mtime<3>[ 12.367407] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 11:08:05.328692 <6>[ 12.371411] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10708 11:08:05.335396 -set.target[0m <6>[ 12.383911] videodev: Linux video capture interface: v2.00
10709 11:08:05.346034 <6>[ 12.395178] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10710 11:08:05.355872 - System Time Se<3>[ 12.399320] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10711 11:08:05.362598 <6>[ 12.403988] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10712 11:08:05.369187 <6>[ 12.416345] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10713 11:08:05.378692 <6>[ 12.420144] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10714 11:08:05.379179 t.
10715 11:08:05.385283 <6>[ 12.431023] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10716 11:08:05.392055 <6>[ 12.435867] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10717 11:08:05.398704 <6>[ 12.436526] Bluetooth: Core ver 2.22
10718 11:08:05.402023 <6>[ 12.436591] NET: Registered PF_BLUETOOTH protocol family
10719 11:08:05.408593 <6>[ 12.436593] Bluetooth: HCI device and connection manager initialized
10720 11:08:05.415108 <6>[ 12.436617] Bluetooth: HCI socket layer initialized
10721 11:08:05.418403 <6>[ 12.436621] Bluetooth: L2CAP socket layer initialized
10722 11:08:05.424880 <6>[ 12.436630] Bluetooth: SCO socket layer initialized
10723 11:08:05.431533 <6>[ 12.453926] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10724 11:08:05.438388 <6>[ 12.455858] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10725 11:08:05.451557 <6>[ 12.463315] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10726 11:08:05.455111 <6>[ 12.468121] pci 0000:01:00.0: supports D1 D2
10727 11:08:05.461358 <6>[ 12.473317] usbcore: registered new interface driver uvcvideo
10728 11:08:05.468171 <6>[ 12.478445] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10729 11:08:05.474801 <6>[ 12.479576] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10730 11:08:05.481307 <6>[ 12.484604] usbcore: registered new interface driver btusb
10731 11:08:05.491102 <4>[ 12.486132] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10732 11:08:05.497556 <3>[ 12.486162] Bluetooth: hci0: Failed to load firmware file (-2)
10733 11:08:05.504566 <3>[ 12.486173] Bluetooth: hci0: Failed to set up firmware (-2)
10734 11:08:05.514266 <4>[ 12.486186] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10735 11:08:05.521286 <6>[ 12.492866] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10736 11:08:05.531138 <6>[ 12.580078] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10737 11:08:05.537706 <6>[ 12.588362] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10738 11:08:05.544422 <6>[ 12.596428] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10739 11:08:05.553962 <6>[ 12.596442] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10740 11:08:05.561142 <6>[ 12.596455] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10741 11:08:05.567551 <6>[ 12.596467] pci 0000:00:00.0: PCI bridge to [bus 01]
10742 11:08:05.573885 <6>[ 12.596472] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10743 11:08:05.580759 <6>[ 12.596655] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10744 11:08:05.590642 Startin<6>[ 12.640594] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10745 11:08:05.596963 g [0;1;39msyste<6>[ 12.648256] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10746 11:08:05.600742 md-backlight…ess of leds:white:kbd_backlight...
10747 11:08:05.615706 <5>[ 12.666009] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10748 11:08:05.629810 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness <3>[ 12.680842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10749 11:08:05.636393 <5>[ 12.688932] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10750 11:08:05.646922 of leds:white:kb<5>[ 12.696872] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10751 11:08:05.650320 d_backlight.
10752 11:08:05.657120 <4>[ 12.706423] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10753 11:08:05.667019 <3>[ 12.708492] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10754 11:08:05.670277 <6>[ 12.716520] cfg80211: failed to load regulatory.db
10755 11:08:05.681389 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10756 11:08:05.703719 [[0;32m OK [<3>[ 12.751333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10757 11:08:05.713439 0m] Reached target [0;1;39msysi<6>[ 12.762656] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10758 11:08:05.720375 nit.target[0m -<6>[ 12.770937] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10759 11:08:05.723340 System Initialization.
10760 11:08:05.735858 <3>[ 12.785712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10761 11:08:05.745608 [[0;32m OK [0m] Started [0;1;39mfstrim.time<6>[ 12.798651] mt7921e 0000:01:00.0: ASIC revision: 79610010
10762 11:08:05.752043 r[0m - Discard unused blocks once a week.
10763 11:08:05.767026 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10764 11:08:05.782363 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10765 11:08:05.799510 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10766 11:08:05.818312 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10767 11:08:05.834202 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10768 11:08:05.848682 <6>[ 12.899078] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10769 11:08:05.852381 <6>[ 12.899078]
10770 11:08:05.858500 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10771 11:08:05.881970 <3>[ 12.931795] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10772 11:08:05.910227 <3>[ 12.960591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10773 11:08:05.917005 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10774 11:08:05.946251 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10775 11:08:05.970753 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10776 11:08:05.988459 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10777 11:08:06.022920 <46>[ 13.059481] systemd-journald[196]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1538 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
10778 11:08:06.036150 <46>[ 13.059515] systemd-journald[196]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
10779 11:08:06.046369 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10780 11:08:06.107442 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10781 11:08:06.118909 <6>[ 13.169407] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10782 11:08:06.134174 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10783 11:08:06.150488 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10784 11:08:06.202315 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10785 11:08:06.222468 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10786 11:08:06.241679 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10787 11:08:06.259764 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10788 11:08:06.277315 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10789 11:08:06.321352 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10790 11:08:06.353511 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10791 11:08:06.388066
10792 11:08:06.391117 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10793 11:08:06.391615
10794 11:08:06.394399 debian-bookworm-arm64 login: root (automatic login)
10795 11:08:06.394893
10796 11:08:06.409657 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
10797 11:08:06.410251
10798 11:08:06.416470 The programs included with the Debian GNU/Linux system are free software;
10799 11:08:06.422853 the exact distribution terms for each program are described in the
10800 11:08:06.426158 individual files in /usr/share/doc/*/copyright.
10801 11:08:06.426662
10802 11:08:06.432769 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10803 11:08:06.435925 permitted by applicable law.
10804 11:08:06.437473 Matched prompt #10: / #
10806 11:08:06.438521 Setting prompt string to ['/ #']
10807 11:08:06.438969 end: 2.2.5.1 login-action (duration 00:00:14) [common]
10809 11:08:06.439947 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
10810 11:08:06.440465 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10811 11:08:06.440802 Setting prompt string to ['/ #']
10812 11:08:06.441097 Forcing a shell prompt, looking for ['/ #']
10813 11:08:06.441443 Sending line: ''
10815 11:08:06.492798 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10816 11:08:06.493206 Waiting using forced prompt support (timeout 00:02:30)
10817 11:08:06.498398 / #
10818 11:08:06.499257 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10819 11:08:06.499745 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10820 11:08:06.500229 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10821 11:08:06.500653 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
10822 11:08:06.501168 end: 2 depthcharge-action (duration 00:01:36) [common]
10823 11:08:06.501763 start: 3 lava-test-retry (timeout 00:07:59) [common]
10824 11:08:06.502299 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
10825 11:08:06.502740 Using namespace: common
10826 11:08:06.503183 Sending line: '#'
10828 11:08:06.604757 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10829 11:08:06.610293 / # #
10830 11:08:06.611396 Using /lava-14786845
10831 11:08:06.611798 Sending line: 'export SHELL=/bin/sh'
10833 11:08:06.719215 / # export SHELL=/bin/sh
10834 11:08:06.719959 Sending line: '. /lava-14786845/environment'
10836 11:08:06.827861 / # . /lava-14786845/environment
10837 11:08:06.828763 Sending line: '/lava-14786845/bin/lava-test-runner /lava-14786845/0'
10839 11:08:06.930218 Test shell timeout: 10s (minimum of the action and connection timeout)
10840 11:08:06.936062 / # /lava-14786845/bin/lava-test-runner /lava-14786845/0
10841 11:08:06.968891 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 14.021692] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14786845_1.5.2.3.1>
10842 11:08:06.969741 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14786845_1.5.2.3.1
10843 11:08:06.970114 Starting test lava.0_igt-gpu-panfrost (14786845_1.5.2.3.1)
10844 11:08:06.970504 Skipping test definition patterns.
10845 11:08:06.972418 nfrost
10846 11:08:06.975432 + cd /lava-14786845/0/tests/0_igt-gpu-panfrost
10847 11:08:06.975861 + cat uuid
10848 11:08:06.982093 + UUID=14786<6>[ 14.035516] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10849 11:08:06.985641 845_1.5.2.3.1
10850 11:08:06.986147 + set +x
10851 11:08:06.995489 + IGT_FORCE_DRIVER=panfrost /usr/bin/ig<8>[ 14.047456] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10852 11:08:06.996250 Received signal: <TESTSET> START panfrost_gem_new
10853 11:08:06.996618 Starting test_set panfrost_gem_new
10854 11:08:07.002153 t-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
10855 11:08:07.023004 <14>[ 14.076617] [IGT] panfrost_gem_new: executing
10856 11:08:07.032917 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.085293] [IGT] panfrost_gem_new: exiting, ret=77
10857 11:08:07.033464 .96-cip24 aarch64)
10858 11:08:07.039444 Using IGT_SRANDOM=1720609686 for randomisation
10859 11:08:07.046159 Test require<8>[ 14.097878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10860 11:08:07.046931 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10862 11:08:07.052591 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
10863 11:08:07.056436 Test requirement: !(fd<0)
10864 11:08:07.062602 No known gpu found for chipset flags 0x32 (panfrost)
10865 11:08:07.065664 Last errno: 2, No such file or directory
10866 11:08:07.068576 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
10867 11:08:07.081883 <14>[ 14.135765] [IGT] panfrost_gem_new: executing
10868 11:08:07.091921 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.144358] [IGT] panfrost_gem_new: exiting, ret=77
10869 11:08:07.092429 .96-cip24 aarch64)
10870 11:08:07.098631 Using IGT_SRANDOM=1720609686 for randomisation
10871 11:08:07.105137 Test requirement not met in <8>[ 14.157450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10872 11:08:07.106005 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10874 11:08:07.111630 function drm_open_driver, file ../lib/drmtest.c:694:
10875 11:08:07.115014 Test requirement: !(fd<0)
10876 11:08:07.118118 No known gpu found for chipset flags 0x32 (panfrost)
10877 11:08:07.125076 Last errno: 2, No such fi<14>[ 14.178854] [IGT] panfrost_gem_new: executing
10878 11:08:07.128317 le or directory
10879 11:08:07.135091 [1mSubtest gem<14>[ 14.186068] [IGT] panfrost_gem_new: exiting, ret=77
10880 11:08:07.135594 -new-0: SKIP (0.000s)[0m
10881 11:08:07.148073 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-c<8>[ 14.198760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10882 11:08:07.148586 ip24 aarch64)
10883 11:08:07.149186 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10885 11:08:07.154935 Using IGT_SRANDOM<8>[ 14.208310] <LAVA_SIGNAL_TESTSET STOP>
10886 11:08:07.155697 Received signal: <TESTSET> STOP
10887 11:08:07.156061 Closing test_set panfrost_gem_new
10888 11:08:07.157973 =1720609687 for randomisation
10889 11:08:07.165197 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10890 11:08:07.167983 Test requirement: !(fd<0)
10891 11:08:07.177770 No known gpu found for chipset flags 0x32 (panfrost)<8>[ 14.228388] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10892 11:08:07.178274
10893 11:08:07.178865 Received signal: <TESTSET> START panfrost_get_param
10894 11:08:07.179265 Starting test_set panfrost_get_param
10895 11:08:07.181018 Last errno: 2, No such file or directory
10896 11:08:07.184447 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
10897 11:08:07.194314 <14>[ 14.248045] [IGT] panfrost_get_param: executing
10898 11:08:07.204050 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.254944] [IGT] panfrost_get_param: exiting, ret=77
10899 11:08:07.204551 h64) (Linux: 6.1.96-cip24 aarch64)
10900 11:08:07.217378 Using IGT_SRANDOM=1720609687 for randomisati<8>[ 14.267229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10901 11:08:07.217901 on
10902 11:08:07.218496 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10904 11:08:07.224024 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10905 11:08:07.227448 Test requirement: !(fd<0)
10906 11:08:07.230478 No known gpu found for chipset flags 0x32 (panfrost)
10907 11:08:07.234175 Last errno: 2, No such file or directory
10908 11:08:07.236776 [1mSubtest base-params: SKIP (0.000s)[0m
10909 11:08:07.251377 <14>[ 14.305060] [IGT] panfrost_get_param: executing
10910 11:08:07.261205 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.313429] [IGT] panfrost_get_param: exiting, ret=77
10911 11:08:07.264512 .96-cip24 aarch64)
10912 11:08:07.267820 Using IGT_SRANDOM=1720609687 for randomisation
10913 11:08:07.274132 Test require<8>[ 14.325554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10914 11:08:07.274867 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10916 11:08:07.281010 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
10917 11:08:07.284129 Test requirement: !(fd<0)
10918 11:08:07.287589 No known gpu found for chipset flags 0x32 (panfrost)
10919 11:08:07.294423 Last errn<14>[ 14.347020] [IGT] panfrost_get_param: executing
10920 11:08:07.297683 o: 2, No such file or directory
10921 11:08:07.301064 <14>[ 14.354614] [IGT] panfrost_get_param: exiting, ret=77
10922 11:08:07.301571
10923 11:08:07.307829 [1mSubtest get-bad-param: SKIP (0.000s)[0m
10924 11:08:07.317554 IGT-Version: 1.28-ga44ebfe (aarch<8>[ 14.367039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10925 11:08:07.318313 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10927 11:08:07.324239 64) (Linux: 6.1.96-cip24 aarch64<8>[ 14.376942] <LAVA_SIGNAL_TESTSET STOP>
10928 11:08:07.324749 )
10929 11:08:07.325364 Received signal: <TESTSET> STOP
10930 11:08:07.325705 Closing test_set panfrost_get_param
10931 11:08:07.327113 Using IGT_SRANDOM=1720609687 for randomisation
10932 11:08:07.333936 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10933 11:08:07.337174 Test requirement: !(fd<0)
10934 11:08:07.340383 No known gpu found for chipset flags 0x32 (panfrost)
10935 11:08:07.346813 Last errno: 2, No such file or directory
10936 11:08:07.350091 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
10937 11:08:07.353932 <8>[ 14.408783] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10938 11:08:07.354684 Received signal: <TESTSET> START panfrost_prime
10939 11:08:07.355040 Starting test_set panfrost_prime
10940 11:08:07.383251 <14>[ 14.436349] [IGT] panfrost_prime: executing
10941 11:08:07.392509 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.444288] [IGT] panfrost_prime: exiting, ret=77
10942 11:08:07.392736 .96-cip24 aarch64)
10943 11:08:07.399143 Using IGT_SRANDOM=1720609687 for randomisation
10944 11:08:07.405377 Test require<8>[ 14.456282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10945 11:08:07.405804 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10947 11:08:07.412395 ment not met in function drm_ope<8>[ 14.466917] <LAVA_SIGNAL_TESTSET STOP>
10948 11:08:07.412820 Received signal: <TESTSET> STOP
10949 11:08:07.412963 Closing test_set panfrost_prime
10950 11:08:07.415172 n_driver, file ../lib/drmtest.c:694:
10951 11:08:07.418590 Test requirement: !(fd<0)
10952 11:08:07.421926 No known gpu found for chipset flags 0x32 (panfrost)
10953 11:08:07.425630 Last errno: 2, No such file or directory
10954 11:08:07.435427 [1mSubtest gem-prime-import: SKIP (0.000s)[0m<8>[ 14.488421] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10955 11:08:07.435894
10956 11:08:07.436439 Received signal: <TESTSET> START panfrost_submit
10957 11:08:07.436747 Starting test_set panfrost_submit
10958 11:08:07.452889 <14>[ 14.506854] [IGT] panfrost_submit: executing
10959 11:08:07.459719 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.513460] [IGT] panfrost_submit: exiting, ret=77
10960 11:08:07.462871 h64) (Linux: 6.1.96-cip24 aarch64)
10961 11:08:07.473361 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10963 11:08:07.475984 Using IGT_SRANDOM=1720609687 for randomisati<8>[ 14.525249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10964 11:08:07.476414 on
10965 11:08:07.482642 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10966 11:08:07.483194 Test requirement: !(fd<0)
10967 11:08:07.489274 No known gpu found for chipset flags 0x32 (panfrost)
10968 11:08:07.495721 Last errn<14>[ 14.547325] [IGT] panfrost_submit: executing
10969 11:08:07.496221 o: 2, No such file or directory
10970 11:08:07.502549 <14>[ 14.555157] [IGT] panfrost_submit: exiting, ret=77
10971 11:08:07.503081
10972 11:08:07.505788 [1mSubtest pan-submit: SKIP (0.000s)[0m
10973 11:08:07.515893 IGT-Version: 1.28-ga<8>[ 14.566360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10974 11:08:07.516656 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10976 11:08:07.519177 44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10977 11:08:07.525447 Using IGT_SRANDOM=1720609687 for randomisation
10978 11:08:07.532337 Test requirement not met in function drm_open_dr<14>[ 14.586915] [IGT] panfrost_submit: executing
10979 11:08:07.541838 iver, file ../lib/drmtest.c:694:<14>[ 14.593767] [IGT] panfrost_submit: exiting, ret=77
10980 11:08:07.542327
10981 11:08:07.542654 Test requirement: !(fd<0)
10982 11:08:07.555343 No known gpu found for chipset flag<8>[ 14.605213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10983 11:08:07.555860 s 0x32 (panfrost)
10984 11:08:07.556441 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10986 11:08:07.558482 Last errno: 2, No such file or directory
10987 11:08:07.565612 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
10988 11:08:07.571823 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 14.627158] [IGT] panfrost_submit: executing
10989 11:08:07.574937 6.1.96-cip24 aarch64)
10990 11:08:07.582001 Using IG<14>[ 14.634332] [IGT] panfrost_submit: exiting, ret=77
10991 11:08:07.585423 T_SRANDOM=1720609687 for randomisation
10992 11:08:07.595041 Test requirement not met<8>[ 14.645138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10993 11:08:07.595852 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10995 11:08:07.602030 in function drm_open_driver, file ../lib/drmtest.c:694:
10996 11:08:07.602525 Test requirement: !(fd<0)
10997 11:08:07.608456 No known gpu found for chipset flags 0x32 (panfrost)
10998 11:08:07.611445 Last <14>[ 14.666946] [IGT] panfrost_submit: executing
10999 11:08:07.621608 errno: 2, No such file or direct<14>[ 14.673472] [IGT] panfrost_submit: exiting, ret=77
11000 11:08:07.622217 ory
11001 11:08:07.628097 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11002 11:08:07.638060 IGT-Version: <8>[ 14.685572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11003 11:08:07.638799 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11005 11:08:07.641377 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11006 11:08:07.644744 Using IGT_SRANDOM=1720609687 for randomisation
11007 11:08:07.654423 Test requirement not met in function drm_open_driver, fil<14>[ 14.708169] [IGT] panfrost_submit: executing
11008 11:08:07.657964 e ../lib/drmtest.c:694:
11009 11:08:07.664303 Test re<14>[ 14.715763] [IGT] panfrost_submit: exiting, ret=77
11010 11:08:07.664798 quirement: !(fd<0)
11011 11:08:07.671129 No known gpu found for chipset flags 0x32 (panfrost)
11012 11:08:07.677302 Last e<8>[ 14.727811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11013 11:08:07.677990 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11015 11:08:07.680951 rrno: 2, No such file or directory
11016 11:08:07.687660 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11017 11:08:07.697470 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aa<14>[ 14.751097] [IGT] panfrost_submit: executing
11018 11:08:07.697964 rch64)
11019 11:08:07.703991 Using IGT_SRANDOM=172060<14>[ 14.757864] [IGT] panfrost_submit: exiting, ret=77
11020 11:08:07.707011 9687 for randomisation
11021 11:08:07.717192 Test requirement not met in function drm<8>[ 14.769108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11022 11:08:07.717952 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11024 11:08:07.720133 _open_driver, file ../lib/drmtest.c:694:
11025 11:08:07.723890 Test requirement: !(fd<0)
11026 11:08:07.726923 No known gpu found for chipset flags 0x32 (panfrost)
11027 11:08:07.736744 Last errno: 2, No such file or direct<14>[ 14.788909] [IGT] panfrost_submit: executing
11028 11:08:07.737266 ory
11029 11:08:07.743489 [1mSubtest pan-submit-erro<14>[ 14.796939] [IGT] panfrost_submit: exiting, ret=77
11030 11:08:07.746813 r-bad-requirements: SKIP (0.000s)[0m
11031 11:08:07.757391 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11033 11:08:07.760345 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 14.808362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11034 11:08:07.760851 ux: 6.1.96-cip24 aarch64)
11035 11:08:07.766555 Using IGT_SRANDOM=1720609687 for randomisation
11036 11:08:07.773301 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11037 11:08:07.776639 Tes<14>[ 14.830694] [IGT] panfrost_submit: executing
11038 11:08:07.779649 t requirement: !(fd<0)
11039 11:08:07.786304 No known<14>[ 14.838038] [IGT] panfrost_submit: exiting, ret=77
11040 11:08:07.789705 gpu found for chipset flags 0x32 (panfrost)
11041 11:08:07.799776 Last errno: 2, No such file or dir<8>[ 14.850046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11042 11:08:07.800277 ectory
11043 11:08:07.800859 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11045 11:08:07.805943 [1mSubtest pan-submit-e<8>[ 14.860629] <LAVA_SIGNAL_TESTSET STOP>
11046 11:08:07.806607 Received signal: <TESTSET> STOP
11047 11:08:07.806957 Closing test_set panfrost_submit
11048 11:08:07.815938 rror-bad-out-syn<8>[ 14.866528] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14786845_1.5.2.3.1>
11049 11:08:07.816502 c: SKIP (0.000s)[0m
11050 11:08:07.817141 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14786845_1.5.2.3.1
11051 11:08:07.817696 Ending use of test pattern.
11052 11:08:07.818083 Ending test lava.0_igt-gpu-panfrost (14786845_1.5.2.3.1), duration 0.85
11054 11:08:07.822921 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11055 11:08:07.825911 Using IGT_SRANDOM=1720609687 for randomisation
11056 11:08:07.832431 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11057 11:08:07.835798 Test requirement: !(fd<0)
11058 11:08:07.842361 No known gpu found for chipset flags 0x32 (panfrost)
11059 11:08:07.846090 Last errno: 2, No such file or directory
11060 11:08:07.849028 [1mSubtest pan-reset: SKIP (0.000s)[0m
11061 11:08:07.856034 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11062 11:08:07.859037 Using IGT_SRANDOM=1720609687 for randomisation
11063 11:08:07.866071 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11064 11:08:07.868859 Test requirement: !(fd<0)
11065 11:08:07.872748 No known gpu found for chipset flags 0x32 (panfrost)
11066 11:08:07.875579 Last errno: 2, No such file or directory
11067 11:08:07.881901 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11068 11:08:07.885366 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11069 11:08:07.891926 Using IGT_SRANDOM=1720609687 for randomisation
11070 11:08:07.898428 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11071 11:08:07.902060 Test requirement: !(fd<0)
11072 11:08:07.905002 No known gpu found for chipset flags 0x32 (panfrost)
11073 11:08:07.908786 Last errno: 2, No such file or directory
11074 11:08:07.915779 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11075 11:08:07.916158 + set +x
11076 11:08:07.916404 <LAVA_TEST_RUNNER EXIT>
11077 11:08:07.916854 ok: lava_test_shell seems to have completed
11078 11:08:07.917964 gem-new-4096:
set: panfrost_gem_new
result: skip
gem-new-0:
set: panfrost_gem_new
result: skip
gem-new-zeroed:
set: panfrost_gem_new
result: skip
base-params:
set: panfrost_get_param
result: skip
get-bad-param:
set: panfrost_get_param
result: skip
get-bad-padding:
set: panfrost_get_param
result: skip
gem-prime-import:
set: panfrost_prime
result: skip
pan-submit:
set: panfrost_submit
result: skip
pan-submit-error-no-jc:
set: panfrost_submit
result: skip
pan-submit-error-bad-in-syncs:
set: panfrost_submit
result: skip
pan-submit-error-bad-bo-handles:
set: panfrost_submit
result: skip
pan-submit-error-bad-requirements:
set: panfrost_submit
result: skip
pan-submit-error-bad-out-sync:
set: panfrost_submit
result: skip
pan-reset:
set: panfrost_submit
result: skip
pan-submit-and-close:
set: panfrost_submit
result: skip
pan-unhandled-pagefault:
set: panfrost_submit
result: skip
11079 11:08:07.918367 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11080 11:08:07.918754 end: 3 lava-test-retry (duration 00:00:01) [common]
11081 11:08:07.919075 start: 4 finalize (timeout 00:07:57) [common]
11082 11:08:07.919387 start: 4.1 power-off (timeout 00:00:30) [common]
11083 11:08:07.919848 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11084 11:08:10.033874 >> Command sent successfully.
11085 11:08:10.047904 Returned 0 in 2 seconds
11086 11:08:10.048492 end: 4.1 power-off (duration 00:00:02) [common]
11088 11:08:10.049538 start: 4.2 read-feedback (timeout 00:07:55) [common]
11089 11:08:10.050229 Listened to connection for namespace 'common' for up to 1s
11090 11:08:10.050994 Listened to connection for namespace 'common' for up to 1s
11091 11:08:11.051398 Finalising connection for namespace 'common'
11092 11:08:11.051959 Disconnecting from shell: Finalise
11093 11:08:11.052313 / #
11094 11:08:11.153181 end: 4.2 read-feedback (duration 00:00:01) [common]
11095 11:08:11.153865 end: 4 finalize (duration 00:00:03) [common]
11096 11:08:11.154486 Cleaning after the job
11097 11:08:11.154986 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/ramdisk
11098 11:08:11.186206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/kernel
11099 11:08:11.213422 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/dtb
11100 11:08:11.213656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786845/tftp-deploy-xcyw_x31/modules
11101 11:08:11.220193 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786845
11102 11:08:11.329390 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786845
11103 11:08:11.329540 Job finished correctly