Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:02:03.976462 lava-dispatcher, installed at version: 2024.05
2 11:02:03.976651 start: 0 validate
3 11:02:03.976769 Start time: 2024-07-10 11:02:03.976763+00:00 (UTC)
4 11:02:03.976903 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:03.977058 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:02:04.244371 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:04.244533 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:02:04.512726 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:02:04.513516 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:02:51.033766 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:02:51.034352 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:02:51.570447 validate duration: 47.59
14 11:02:51.571557 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:02:51.572021 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:02:51.572433 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:02:51.573141 Not decompressing ramdisk as can be used compressed.
18 11:02:51.573603 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 11:02:51.573918 saving as /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/ramdisk/rootfs.cpio.gz
20 11:02:51.574329 total size: 47897469 (45 MB)
21 11:02:55.443760 progress 0 % (0 MB)
22 11:02:55.494970 progress 5 % (2 MB)
23 11:02:55.513410 progress 10 % (4 MB)
24 11:02:55.526182 progress 15 % (6 MB)
25 11:02:55.537661 progress 20 % (9 MB)
26 11:02:55.549078 progress 25 % (11 MB)
27 11:02:55.560448 progress 30 % (13 MB)
28 11:02:55.572125 progress 35 % (16 MB)
29 11:02:55.583750 progress 40 % (18 MB)
30 11:02:55.595188 progress 45 % (20 MB)
31 11:02:55.606833 progress 50 % (22 MB)
32 11:02:55.618245 progress 55 % (25 MB)
33 11:02:55.629822 progress 60 % (27 MB)
34 11:02:55.641747 progress 65 % (29 MB)
35 11:02:55.653393 progress 70 % (32 MB)
36 11:02:55.664892 progress 75 % (34 MB)
37 11:02:55.676381 progress 80 % (36 MB)
38 11:02:55.687951 progress 85 % (38 MB)
39 11:02:55.699339 progress 90 % (41 MB)
40 11:02:55.710744 progress 95 % (43 MB)
41 11:02:55.722167 progress 100 % (45 MB)
42 11:02:55.722369 45 MB downloaded in 4.15 s (11.01 MB/s)
43 11:02:55.722521 end: 1.1.1 http-download (duration 00:00:04) [common]
45 11:02:55.722733 end: 1.1 download-retry (duration 00:00:04) [common]
46 11:02:55.722811 start: 1.2 download-retry (timeout 00:09:56) [common]
47 11:02:55.722886 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 11:02:55.723019 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:02:55.723079 saving as /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/kernel/Image
50 11:02:55.723132 total size: 54813184 (52 MB)
51 11:02:55.723185 No compression specified
52 11:02:55.724182 progress 0 % (0 MB)
53 11:02:55.737325 progress 5 % (2 MB)
54 11:02:55.750400 progress 10 % (5 MB)
55 11:02:55.763606 progress 15 % (7 MB)
56 11:02:55.776770 progress 20 % (10 MB)
57 11:02:55.790102 progress 25 % (13 MB)
58 11:02:55.803163 progress 30 % (15 MB)
59 11:02:55.816372 progress 35 % (18 MB)
60 11:02:55.829472 progress 40 % (20 MB)
61 11:02:55.842610 progress 45 % (23 MB)
62 11:02:55.855519 progress 50 % (26 MB)
63 11:02:55.868731 progress 55 % (28 MB)
64 11:02:55.881822 progress 60 % (31 MB)
65 11:02:55.895963 progress 65 % (34 MB)
66 11:02:55.910038 progress 70 % (36 MB)
67 11:02:55.924424 progress 75 % (39 MB)
68 11:02:55.938939 progress 80 % (41 MB)
69 11:02:55.953293 progress 85 % (44 MB)
70 11:02:55.967402 progress 90 % (47 MB)
71 11:02:55.981702 progress 95 % (49 MB)
72 11:02:55.995448 progress 100 % (52 MB)
73 11:02:55.995720 52 MB downloaded in 0.27 s (191.77 MB/s)
74 11:02:55.995888 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:02:55.996124 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:02:55.996219 start: 1.3 download-retry (timeout 00:09:56) [common]
78 11:02:55.996308 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 11:02:55.996450 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:02:55.996515 saving as /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/dtb/mt8192-asurada-spherion-r0.dtb
81 11:02:55.996600 total size: 47258 (0 MB)
82 11:02:55.996686 No compression specified
83 11:02:55.998232 progress 69 % (0 MB)
84 11:02:55.998514 progress 100 % (0 MB)
85 11:02:55.998669 0 MB downloaded in 0.00 s (21.80 MB/s)
86 11:02:55.998851 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:02:55.999080 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:02:55.999169 start: 1.4 download-retry (timeout 00:09:56) [common]
90 11:02:55.999258 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 11:02:55.999441 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:02:55.999545 saving as /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/modules/modules.tar
93 11:02:55.999632 total size: 8607984 (8 MB)
94 11:02:55.999721 Using unxz to decompress xz
95 11:02:56.001512 progress 0 % (0 MB)
96 11:02:56.022030 progress 5 % (0 MB)
97 11:02:56.046763 progress 10 % (0 MB)
98 11:02:56.072358 progress 15 % (1 MB)
99 11:02:56.097109 progress 20 % (1 MB)
100 11:02:56.122168 progress 25 % (2 MB)
101 11:02:56.145894 progress 30 % (2 MB)
102 11:02:56.169270 progress 35 % (2 MB)
103 11:02:56.195145 progress 40 % (3 MB)
104 11:02:56.219277 progress 45 % (3 MB)
105 11:02:56.243280 progress 50 % (4 MB)
106 11:02:56.268090 progress 55 % (4 MB)
107 11:02:56.291951 progress 60 % (4 MB)
108 11:02:56.315002 progress 65 % (5 MB)
109 11:02:56.339687 progress 70 % (5 MB)
110 11:02:56.366279 progress 75 % (6 MB)
111 11:02:56.393386 progress 80 % (6 MB)
112 11:02:56.416948 progress 85 % (7 MB)
113 11:02:56.439690 progress 90 % (7 MB)
114 11:02:56.462411 progress 95 % (7 MB)
115 11:02:56.484674 progress 100 % (8 MB)
116 11:02:56.489999 8 MB downloaded in 0.49 s (16.74 MB/s)
117 11:02:56.490221 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:02:56.490463 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:02:56.490542 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 11:02:56.490618 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 11:02:56.490691 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:02:56.490762 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 11:02:56.490927 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6
125 11:02:56.491044 makedir: /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin
126 11:02:56.491132 makedir: /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/tests
127 11:02:56.491219 makedir: /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/results
128 11:02:56.491301 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-add-keys
129 11:02:56.491426 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-add-sources
130 11:02:56.491540 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-background-process-start
131 11:02:56.491654 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-background-process-stop
132 11:02:56.491777 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-common-functions
133 11:02:56.491888 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-echo-ipv4
134 11:02:56.491999 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-install-packages
135 11:02:56.492107 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-installed-packages
136 11:02:56.492214 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-os-build
137 11:02:56.492322 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-probe-channel
138 11:02:56.492429 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-probe-ip
139 11:02:56.492537 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-target-ip
140 11:02:56.492643 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-target-mac
141 11:02:56.492749 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-target-storage
142 11:02:56.492859 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-test-case
143 11:02:56.492967 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-test-event
144 11:02:56.493074 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-test-feedback
145 11:02:56.493180 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-test-raise
146 11:02:56.493333 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-test-reference
147 11:02:56.493442 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-test-runner
148 11:02:56.493550 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-test-set
149 11:02:56.493658 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-test-shell
150 11:02:56.493767 Updating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-install-packages (oe)
151 11:02:56.493900 Updating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/bin/lava-installed-packages (oe)
152 11:02:56.494006 Creating /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/environment
153 11:02:56.494092 LAVA metadata
154 11:02:56.494152 - LAVA_JOB_ID=14786812
155 11:02:56.494206 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:02:56.494291 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 11:02:56.494348 skipped lava-vland-overlay
158 11:02:56.494413 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:02:56.494482 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 11:02:56.494533 skipped lava-multinode-overlay
161 11:02:56.494594 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:02:56.494660 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 11:02:56.494720 Loading test definitions
164 11:02:56.494793 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 11:02:56.494848 Using /lava-14786812 at stage 0
166 11:02:56.495145 uuid=14786812_1.5.2.3.1 testdef=None
167 11:02:56.495224 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:02:56.495296 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 11:02:56.495854 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:02:56.496048 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 11:02:56.496596 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:02:56.496795 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 11:02:56.497367 runner path: /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/0/tests/0_igt-kms-mediatek test_uuid 14786812_1.5.2.3.1
176 11:02:56.497506 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:02:56.497689 Creating lava-test-runner.conf files
179 11:02:56.497745 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786812/lava-overlay-rr9f0qk6/lava-14786812/0 for stage 0
180 11:02:56.497822 - 0_igt-kms-mediatek
181 11:02:56.497906 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:02:56.498002 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 11:02:56.504099 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:02:56.504196 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 11:02:56.504272 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:02:56.504347 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:02:56.504420 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 11:02:58.085189 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 11:02:58.085380 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
190 11:02:58.085453 extracting modules file /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786812/extract-overlay-ramdisk-ssl7w2mb/ramdisk
191 11:02:58.309561 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:02:58.309701 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
193 11:02:58.309778 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786812/compress-overlay-8s52kr0c/overlay-1.5.2.4.tar.gz to ramdisk
194 11:02:58.309837 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786812/compress-overlay-8s52kr0c/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786812/extract-overlay-ramdisk-ssl7w2mb/ramdisk
195 11:02:58.316166 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:02:58.316263 start: 1.5.6 configure-preseed-file (timeout 00:09:53) [common]
197 11:02:58.316345 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:02:58.316421 start: 1.5.7 compress-ramdisk (timeout 00:09:53) [common]
199 11:02:58.316484 Building ramdisk /var/lib/lava/dispatcher/tmp/14786812/extract-overlay-ramdisk-ssl7w2mb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786812/extract-overlay-ramdisk-ssl7w2mb/ramdisk
200 11:02:59.326678 >> 465428 blocks
201 11:03:05.940835 rename /var/lib/lava/dispatcher/tmp/14786812/extract-overlay-ramdisk-ssl7w2mb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/ramdisk/ramdisk.cpio.gz
202 11:03:05.941085 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 11:03:05.941282 start: 1.5.8 prepare-kernel (timeout 00:09:46) [common]
204 11:03:05.941425 start: 1.5.8.1 prepare-fit (timeout 00:09:46) [common]
205 11:03:05.941562 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/kernel/Image']
206 11:03:20.113982 Returned 0 in 14 seconds
207 11:03:20.114150 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/kernel/image.itb
208 11:03:20.968759 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:03:20.968886 output: Created: Wed Jul 10 12:03:20 2024
210 11:03:20.968949 output: Image 0 (kernel-1)
211 11:03:20.969002 output: Description:
212 11:03:20.969054 output: Created: Wed Jul 10 12:03:20 2024
213 11:03:20.969106 output: Type: Kernel Image
214 11:03:20.969155 output: Compression: lzma compressed
215 11:03:20.969207 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
216 11:03:20.969285 output: Architecture: AArch64
217 11:03:20.969347 output: OS: Linux
218 11:03:20.969395 output: Load Address: 0x00000000
219 11:03:20.969442 output: Entry Point: 0x00000000
220 11:03:20.969489 output: Hash algo: crc32
221 11:03:20.969536 output: Hash value: 9bb85fb9
222 11:03:20.969584 output: Image 1 (fdt-1)
223 11:03:20.969632 output: Description: mt8192-asurada-spherion-r0
224 11:03:20.969679 output: Created: Wed Jul 10 12:03:20 2024
225 11:03:20.969727 output: Type: Flat Device Tree
226 11:03:20.969774 output: Compression: uncompressed
227 11:03:20.969821 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:03:20.969868 output: Architecture: AArch64
229 11:03:20.969916 output: Hash algo: crc32
230 11:03:20.969963 output: Hash value: 0f8e4d2e
231 11:03:20.970010 output: Image 2 (ramdisk-1)
232 11:03:20.970055 output: Description: unavailable
233 11:03:20.970101 output: Created: Wed Jul 10 12:03:20 2024
234 11:03:20.970158 output: Type: RAMDisk Image
235 11:03:20.970208 output: Compression: uncompressed
236 11:03:20.970256 output: Data Size: 60974499 Bytes = 59545.41 KiB = 58.15 MiB
237 11:03:20.970303 output: Architecture: AArch64
238 11:03:20.970350 output: OS: Linux
239 11:03:20.970396 output: Load Address: unavailable
240 11:03:20.970443 output: Entry Point: unavailable
241 11:03:20.970490 output: Hash algo: crc32
242 11:03:20.970536 output: Hash value: 50b38dfe
243 11:03:20.970583 output: Default Configuration: 'conf-1'
244 11:03:20.970630 output: Configuration 0 (conf-1)
245 11:03:20.970676 output: Description: mt8192-asurada-spherion-r0
246 11:03:20.970723 output: Kernel: kernel-1
247 11:03:20.970769 output: Init Ramdisk: ramdisk-1
248 11:03:20.970816 output: FDT: fdt-1
249 11:03:20.970862 output: Loadables: kernel-1
250 11:03:20.970909 output:
251 11:03:20.971010 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 11:03:20.971083 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 11:03:20.971157 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 11:03:20.971229 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
255 11:03:20.971285 No LXC device requested
256 11:03:20.971353 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:03:20.971423 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
258 11:03:20.971491 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:03:20.971548 Checking files for TFTP limit of 4294967296 bytes.
260 11:03:20.971912 end: 1 tftp-deploy (duration 00:00:29) [common]
261 11:03:20.971999 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:03:20.972075 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:03:20.972161 substitutions:
264 11:03:20.972220 - {DTB}: 14786812/tftp-deploy-mulcmt2h/dtb/mt8192-asurada-spherion-r0.dtb
265 11:03:20.972274 - {INITRD}: 14786812/tftp-deploy-mulcmt2h/ramdisk/ramdisk.cpio.gz
266 11:03:20.972325 - {KERNEL}: 14786812/tftp-deploy-mulcmt2h/kernel/Image
267 11:03:20.972376 - {LAVA_MAC}: None
268 11:03:20.972425 - {PRESEED_CONFIG}: None
269 11:03:20.972475 - {PRESEED_LOCAL}: None
270 11:03:20.972524 - {RAMDISK}: 14786812/tftp-deploy-mulcmt2h/ramdisk/ramdisk.cpio.gz
271 11:03:20.972577 - {ROOT_PART}: None
272 11:03:20.972626 - {ROOT}: None
273 11:03:20.972675 - {SERVER_IP}: 192.168.201.1
274 11:03:20.972723 - {TEE}: None
275 11:03:20.972770 Parsed boot commands:
276 11:03:20.972817 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:03:20.973006 Parsed boot commands: tftpboot 192.168.201.1 14786812/tftp-deploy-mulcmt2h/kernel/image.itb 14786812/tftp-deploy-mulcmt2h/kernel/cmdline
278 11:03:20.973085 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:03:20.973158 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:03:20.973240 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:03:20.973346 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:03:20.973400 Not connected, no need to disconnect.
283 11:03:20.973465 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:03:20.973531 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:03:20.973585 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:03:20.976432 Setting prompt string to ['lava-test: # ']
287 11:03:20.976730 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:03:20.976820 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:03:20.976903 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:03:20.976995 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:03:20.977169 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
292 11:03:30.107630 >> Command sent successfully.
293 11:03:30.110918 Returned 0 in 9 seconds
294 11:03:30.111115 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:03:30.111440 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:03:30.111562 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:03:30.111668 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:03:30.111754 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:03:30.111854 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:03:30.112349 [Enter `^Ec?' for help]
302 11:03:31.288949 capacity change from 0 to 194784
303 11:03:31.289086 F0: 102B 0000
304 11:03:31.289174
305 11:03:31.292219 F3: 1001 0000 [0200]
306 11:03:31.292323
307 11:03:31.292408 F3: 1001 0000
308 11:03:31.292487
309 11:03:31.292544 F7: 102D 0000
310 11:03:31.292613
311 11:03:31.295924 F1: 0000 0000
312 11:03:31.295998
313 11:03:31.296054 V0: 0000 0000 [0001]
314 11:03:31.296107
315 11:03:31.298902 00: 0007 8000
316 11:03:31.298977
317 11:03:31.299033 01: 0000 0000
318 11:03:31.299086
319 11:03:31.302181 BP: 0C00 0209 [0000]
320 11:03:31.302276
321 11:03:31.302358 G0: 1182 0000
322 11:03:31.302436
323 11:03:31.305532 EC: 0000 0021 [4000]
324 11:03:31.305605
325 11:03:31.305662 S7: 0000 0000 [0000]
326 11:03:31.305716
327 11:03:31.308938 CC: 0000 0000 [0001]
328 11:03:31.309091
329 11:03:31.309177 T0: 0000 0040 [010F]
330 11:03:31.309300
331 11:03:31.312556 Jump to BL
332 11:03:31.312630
333 11:03:31.335751
334 11:03:31.335854
335 11:03:31.345875 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 11:03:31.349106 ARM64: Exception handlers installed.
337 11:03:31.349201 ARM64: Testing exception
338 11:03:31.352440 ARM64: Done test exception
339 11:03:31.359364 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 11:03:31.369015 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 11:03:31.375862 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 11:03:31.386678 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 11:03:31.393233 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 11:03:31.403604 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 11:03:31.413574 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 11:03:31.420489 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 11:03:31.438587 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 11:03:31.442023 WDT: Last reset was cold boot
349 11:03:31.445461 SPI1(PAD0) initialized at 2873684 Hz
350 11:03:31.448618 SPI5(PAD0) initialized at 992727 Hz
351 11:03:31.451816 VBOOT: Loading verstage.
352 11:03:31.458727 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 11:03:31.462062 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 11:03:31.465145 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 11:03:31.468557 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 11:03:31.476210 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 11:03:31.482804 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 11:03:31.493464 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 11:03:31.493561
360 11:03:31.493646
361 11:03:31.503740 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 11:03:31.507195 ARM64: Exception handlers installed.
363 11:03:31.510255 ARM64: Testing exception
364 11:03:31.510361 ARM64: Done test exception
365 11:03:31.517201 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 11:03:31.520519 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 11:03:31.535001 Probing TPM: . done!
368 11:03:31.535108 TPM ready after 0 ms
369 11:03:31.541387 Connected to device vid:did:rid of 1ae0:0028:00
370 11:03:31.548538 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
371 11:03:31.551999 Initialized TPM device CR50 revision 0
372 11:03:31.597672 tlcl_send_startup: Startup return code is 0
373 11:03:31.597786 TPM: setup succeeded
374 11:03:31.609673 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 11:03:31.618569 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 11:03:31.628319 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 11:03:31.637130 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:03:31.640645 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 11:03:31.643685 in-header: 03 07 00 00 08 00 00 00
380 11:03:31.647009 in-data: aa e4 47 04 13 02 00 00
381 11:03:31.650506 Chrome EC: UHEPI supported
382 11:03:31.657287 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 11:03:31.660490 in-header: 03 a9 00 00 08 00 00 00
384 11:03:31.663593 in-data: 84 60 60 08 00 00 00 00
385 11:03:31.663677 Phase 1
386 11:03:31.670301 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 11:03:31.673595 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 11:03:31.680340 VB2:vb2_check_recovery() Recovery was requested manually
389 11:03:31.686958 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 11:03:31.687049 Recovery requested (1009000e)
391 11:03:31.695881 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 11:03:31.701191 tlcl_extend: response is 0
393 11:03:31.711061 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 11:03:31.714977 tlcl_extend: response is 0
395 11:03:31.721389 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 11:03:31.742181 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 11:03:31.748797 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 11:03:31.748896
399 11:03:31.748955
400 11:03:31.759012 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 11:03:31.762316 ARM64: Exception handlers installed.
402 11:03:31.765781 ARM64: Testing exception
403 11:03:31.765861 ARM64: Done test exception
404 11:03:31.787656 pmic_efuse_setting: Set efuses in 11 msecs
405 11:03:31.791337 pmwrap_interface_init: Select PMIF_VLD_RDY
406 11:03:31.797704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 11:03:31.801023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 11:03:31.807946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 11:03:31.811092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 11:03:31.817654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 11:03:31.821101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 11:03:31.824531 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 11:03:31.830874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 11:03:31.834348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 11:03:31.840989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 11:03:31.844780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 11:03:31.847727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 11:03:31.854278 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 11:03:31.860955 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 11:03:31.864337 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 11:03:31.871098 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 11:03:31.877684 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 11:03:31.881170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 11:03:31.888087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 11:03:31.894279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 11:03:31.901119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 11:03:31.904196 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 11:03:31.911154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 11:03:31.917602 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 11:03:31.920825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 11:03:31.927569 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 11:03:31.930922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 11:03:31.937677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 11:03:31.941001 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 11:03:31.947374 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 11:03:31.950863 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 11:03:31.957777 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 11:03:31.960991 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 11:03:31.967398 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 11:03:31.970904 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 11:03:31.977580 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 11:03:31.980935 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 11:03:31.987504 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 11:03:31.991207 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 11:03:31.994688 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 11:03:32.001437 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 11:03:32.004797 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 11:03:32.008172 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 11:03:32.014886 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 11:03:32.018029 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 11:03:32.021192 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 11:03:32.024776 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 11:03:32.031627 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 11:03:32.034820 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 11:03:32.037955 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 11:03:32.041444 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 11:03:32.051461 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 11:03:32.058420 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 11:03:32.064909 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 11:03:32.071422 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 11:03:32.081662 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 11:03:32.084974 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 11:03:32.087915 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 11:03:32.094773 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:03:32.101088 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0x0
466 11:03:32.107722 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
467 11:03:32.111212 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 11:03:32.114362 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 11:03:32.124784 [RTC]rtc_get_frequency_meter,154: input=15, output=764
470 11:03:32.134414 [RTC]rtc_get_frequency_meter,154: input=23, output=950
471 11:03:32.143731 [RTC]rtc_get_frequency_meter,154: input=19, output=857
472 11:03:32.153166 [RTC]rtc_get_frequency_meter,154: input=17, output=811
473 11:03:32.162984 [RTC]rtc_get_frequency_meter,154: input=16, output=787
474 11:03:32.172962 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 11:03:32.181981 [RTC]rtc_get_frequency_meter,154: input=17, output=810
476 11:03:32.185171 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 11:03:32.192255 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 11:03:32.195839 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 11:03:32.198995 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 11:03:32.205708 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 11:03:32.209055 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 11:03:32.212528 ADC[4]: Raw value=670800 ID=5
483 11:03:32.212610 ADC[3]: Raw value=212917 ID=1
484 11:03:32.215957 RAM Code: 0x51
485 11:03:32.219237 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 11:03:32.226172 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 11:03:32.232485 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 11:03:32.239174 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 11:03:32.242575 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 11:03:32.245952 in-header: 03 07 00 00 08 00 00 00
491 11:03:32.249195 in-data: aa e4 47 04 13 02 00 00
492 11:03:32.252661 Chrome EC: UHEPI supported
493 11:03:32.259164 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 11:03:32.262595 in-header: 03 a9 00 00 08 00 00 00
495 11:03:32.265822 in-data: 84 60 60 08 00 00 00 00
496 11:03:32.269263 MRC: failed to locate region type 0.
497 11:03:32.276222 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 11:03:32.276303 DRAM-K: Running full calibration
499 11:03:32.282859 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 11:03:32.286089 header.status = 0x0
501 11:03:32.289109 header.version = 0x6 (expected: 0x6)
502 11:03:32.292627 header.size = 0xd00 (expected: 0xd00)
503 11:03:32.292706 header.flags = 0x0
504 11:03:32.299129 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 11:03:32.317646 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 11:03:32.324496 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 11:03:32.327844 dram_init: ddr_geometry: 0
508 11:03:32.327922 [EMI] MDL number = 0
509 11:03:32.331344 [EMI] Get MDL freq = 0
510 11:03:32.334754 dram_init: ddr_type: 0
511 11:03:32.334836 is_discrete_lpddr4: 1
512 11:03:32.338019 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 11:03:32.338091
514 11:03:32.338147
515 11:03:32.341467 [Bian_co] ETT version 0.0.0.1
516 11:03:32.347981 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 11:03:32.348062
518 11:03:32.351077 dramc_set_vcore_voltage set vcore to 650000
519 11:03:32.351185 Read voltage for 800, 4
520 11:03:32.354560 Vio18 = 0
521 11:03:32.354637 Vcore = 650000
522 11:03:32.354695 Vdram = 0
523 11:03:32.357879 Vddq = 0
524 11:03:32.357955 Vmddr = 0
525 11:03:32.361464 dram_init: config_dvfs: 1
526 11:03:32.364671 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 11:03:32.371422 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 11:03:32.374385 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 11:03:32.378000 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 11:03:32.381383 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 11:03:32.384691 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 11:03:32.387999 MEM_TYPE=3, freq_sel=18
533 11:03:32.391034 sv_algorithm_assistance_LP4_1600
534 11:03:32.394551 ============ PULL DRAM RESETB DOWN ============
535 11:03:32.397766 ========== PULL DRAM RESETB DOWN end =========
536 11:03:32.404721 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 11:03:32.407862 ===================================
538 11:03:32.407971 LPDDR4 DRAM CONFIGURATION
539 11:03:32.411185 ===================================
540 11:03:32.414378 EX_ROW_EN[0] = 0x0
541 11:03:32.417980 EX_ROW_EN[1] = 0x0
542 11:03:32.418066 LP4Y_EN = 0x0
543 11:03:32.421132 WORK_FSP = 0x0
544 11:03:32.421216 WL = 0x2
545 11:03:32.424837 RL = 0x2
546 11:03:32.424967 BL = 0x2
547 11:03:32.427869 RPST = 0x0
548 11:03:32.427966 RD_PRE = 0x0
549 11:03:32.431324 WR_PRE = 0x1
550 11:03:32.431404 WR_PST = 0x0
551 11:03:32.434553 DBI_WR = 0x0
552 11:03:32.434649 DBI_RD = 0x0
553 11:03:32.437701 OTF = 0x1
554 11:03:32.441131 ===================================
555 11:03:32.444755 ===================================
556 11:03:32.444852 ANA top config
557 11:03:32.448019 ===================================
558 11:03:32.451264 DLL_ASYNC_EN = 0
559 11:03:32.454401 ALL_SLAVE_EN = 1
560 11:03:32.454510 NEW_RANK_MODE = 1
561 11:03:32.457817 DLL_IDLE_MODE = 1
562 11:03:32.461288 LP45_APHY_COMB_EN = 1
563 11:03:32.464766 TX_ODT_DIS = 1
564 11:03:32.467657 NEW_8X_MODE = 1
565 11:03:32.471144 ===================================
566 11:03:32.474611 ===================================
567 11:03:32.474692 data_rate = 1600
568 11:03:32.477690 CKR = 1
569 11:03:32.481326 DQ_P2S_RATIO = 8
570 11:03:32.484505 ===================================
571 11:03:32.487843 CA_P2S_RATIO = 8
572 11:03:32.491132 DQ_CA_OPEN = 0
573 11:03:32.494280 DQ_SEMI_OPEN = 0
574 11:03:32.494361 CA_SEMI_OPEN = 0
575 11:03:32.497734 CA_FULL_RATE = 0
576 11:03:32.501009 DQ_CKDIV4_EN = 1
577 11:03:32.504473 CA_CKDIV4_EN = 1
578 11:03:32.507621 CA_PREDIV_EN = 0
579 11:03:32.511016 PH8_DLY = 0
580 11:03:32.511100 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 11:03:32.514361 DQ_AAMCK_DIV = 4
582 11:03:32.517636 CA_AAMCK_DIV = 4
583 11:03:32.521332 CA_ADMCK_DIV = 4
584 11:03:32.524356 DQ_TRACK_CA_EN = 0
585 11:03:32.527908 CA_PICK = 800
586 11:03:32.527986 CA_MCKIO = 800
587 11:03:32.530939 MCKIO_SEMI = 0
588 11:03:32.534468 PLL_FREQ = 3068
589 11:03:32.537681 DQ_UI_PI_RATIO = 32
590 11:03:32.540964 CA_UI_PI_RATIO = 0
591 11:03:32.544256 ===================================
592 11:03:32.547850 ===================================
593 11:03:32.551008 memory_type:LPDDR4
594 11:03:32.551087 GP_NUM : 10
595 11:03:32.554280 SRAM_EN : 1
596 11:03:32.554358 MD32_EN : 0
597 11:03:32.557741 ===================================
598 11:03:32.560863 [ANA_INIT] >>>>>>>>>>>>>>
599 11:03:32.564263 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 11:03:32.567524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 11:03:32.571266 ===================================
602 11:03:32.574655 data_rate = 1600,PCW = 0X7600
603 11:03:32.577892 ===================================
604 11:03:32.580845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 11:03:32.584253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 11:03:32.590998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:03:32.597793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 11:03:32.600995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 11:03:32.604273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:03:32.604378 [ANA_INIT] flow start
611 11:03:32.607410 [ANA_INIT] PLL >>>>>>>>
612 11:03:32.611190 [ANA_INIT] PLL <<<<<<<<
613 11:03:32.611291 [ANA_INIT] MIDPI >>>>>>>>
614 11:03:32.614336 [ANA_INIT] MIDPI <<<<<<<<
615 11:03:32.617563 [ANA_INIT] DLL >>>>>>>>
616 11:03:32.617662 [ANA_INIT] flow end
617 11:03:32.620764 ============ LP4 DIFF to SE enter ============
618 11:03:32.627869 ============ LP4 DIFF to SE exit ============
619 11:03:32.627958 [ANA_INIT] <<<<<<<<<<<<<
620 11:03:32.630927 [Flow] Enable top DCM control >>>>>
621 11:03:32.634223 [Flow] Enable top DCM control <<<<<
622 11:03:32.637569 Enable DLL master slave shuffle
623 11:03:32.644051 ==============================================================
624 11:03:32.644156 Gating Mode config
625 11:03:32.650898 ==============================================================
626 11:03:32.654555 Config description:
627 11:03:32.664334 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 11:03:32.671159 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 11:03:32.674443 SELPH_MODE 0: By rank 1: By Phase
630 11:03:32.681001 ==============================================================
631 11:03:32.684656 GAT_TRACK_EN = 1
632 11:03:32.684745 RX_GATING_MODE = 2
633 11:03:32.687897 RX_GATING_TRACK_MODE = 2
634 11:03:32.691231 SELPH_MODE = 1
635 11:03:32.694668 PICG_EARLY_EN = 1
636 11:03:32.697830 VALID_LAT_VALUE = 1
637 11:03:32.704754 ==============================================================
638 11:03:32.707739 Enter into Gating configuration >>>>
639 11:03:32.711227 Exit from Gating configuration <<<<
640 11:03:32.714405 Enter into DVFS_PRE_config >>>>>
641 11:03:32.724776 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 11:03:32.727731 Exit from DVFS_PRE_config <<<<<
643 11:03:32.730846 Enter into PICG configuration >>>>
644 11:03:32.734487 Exit from PICG configuration <<<<
645 11:03:32.737527 [RX_INPUT] configuration >>>>>
646 11:03:32.737605 [RX_INPUT] configuration <<<<<
647 11:03:32.744127 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 11:03:32.750754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 11:03:32.757586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 11:03:32.760872 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 11:03:32.767459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 11:03:32.773997 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 11:03:32.777344 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 11:03:32.780824 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 11:03:32.787281 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 11:03:32.790808 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 11:03:32.793991 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 11:03:32.800843 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 11:03:32.804148 ===================================
660 11:03:32.804260 LPDDR4 DRAM CONFIGURATION
661 11:03:32.807594 ===================================
662 11:03:32.810691 EX_ROW_EN[0] = 0x0
663 11:03:32.813957 EX_ROW_EN[1] = 0x0
664 11:03:32.814034 LP4Y_EN = 0x0
665 11:03:32.817149 WORK_FSP = 0x0
666 11:03:32.817284 WL = 0x2
667 11:03:32.820760 RL = 0x2
668 11:03:32.820834 BL = 0x2
669 11:03:32.823867 RPST = 0x0
670 11:03:32.823943 RD_PRE = 0x0
671 11:03:32.827357 WR_PRE = 0x1
672 11:03:32.827465 WR_PST = 0x0
673 11:03:32.830610 DBI_WR = 0x0
674 11:03:32.830685 DBI_RD = 0x0
675 11:03:32.834143 OTF = 0x1
676 11:03:32.837143 ===================================
677 11:03:32.840618 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 11:03:32.844192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 11:03:32.850547 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 11:03:32.850630 ===================================
681 11:03:32.853929 LPDDR4 DRAM CONFIGURATION
682 11:03:32.857124 ===================================
683 11:03:32.860589 EX_ROW_EN[0] = 0x10
684 11:03:32.860667 EX_ROW_EN[1] = 0x0
685 11:03:32.863790 LP4Y_EN = 0x0
686 11:03:32.863866 WORK_FSP = 0x0
687 11:03:32.867317 WL = 0x2
688 11:03:32.867395 RL = 0x2
689 11:03:32.870627 BL = 0x2
690 11:03:32.870705 RPST = 0x0
691 11:03:32.873842 RD_PRE = 0x0
692 11:03:32.877505 WR_PRE = 0x1
693 11:03:32.877583 WR_PST = 0x0
694 11:03:32.880671 DBI_WR = 0x0
695 11:03:32.880749 DBI_RD = 0x0
696 11:03:32.884120 OTF = 0x1
697 11:03:32.887235 ===================================
698 11:03:32.890687 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 11:03:32.895731 nWR fixed to 40
700 11:03:32.899327 [ModeRegInit_LP4] CH0 RK0
701 11:03:32.899408 [ModeRegInit_LP4] CH0 RK1
702 11:03:32.902567 [ModeRegInit_LP4] CH1 RK0
703 11:03:32.906011 [ModeRegInit_LP4] CH1 RK1
704 11:03:32.906090 match AC timing 12
705 11:03:32.913003 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 11:03:32.916202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 11:03:32.919382 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 11:03:32.926367 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 11:03:32.929437 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 11:03:32.929543 [EMI DOE] emi_dcm 0
711 11:03:32.935849 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 11:03:32.935954 ==
713 11:03:32.939312 Dram Type= 6, Freq= 0, CH_0, rank 0
714 11:03:32.942376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 11:03:32.942454 ==
716 11:03:32.949118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 11:03:32.955698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 11:03:32.963181 [CA 0] Center 37 (7~68) winsize 62
719 11:03:32.966484 [CA 1] Center 37 (7~68) winsize 62
720 11:03:32.969793 [CA 2] Center 35 (5~66) winsize 62
721 11:03:32.973099 [CA 3] Center 35 (5~66) winsize 62
722 11:03:32.976553 [CA 4] Center 34 (4~65) winsize 62
723 11:03:32.980222 [CA 5] Center 33 (3~64) winsize 62
724 11:03:32.980300
725 11:03:32.983149 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 11:03:32.983233
727 11:03:32.986665 [CATrainingPosCal] consider 1 rank data
728 11:03:32.990111 u2DelayCellTimex100 = 270/100 ps
729 11:03:32.993784 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 11:03:32.997143 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:03:33.000668 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 11:03:33.004090 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
733 11:03:33.010741 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:03:33.014014 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 11:03:33.014092
736 11:03:33.017350 CA PerBit enable=1, Macro0, CA PI delay=33
737 11:03:33.017425
738 11:03:33.020723 [CBTSetCACLKResult] CA Dly = 33
739 11:03:33.020798 CS Dly: 5 (0~36)
740 11:03:33.020856 ==
741 11:03:33.024119 Dram Type= 6, Freq= 0, CH_0, rank 1
742 11:03:33.027393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 11:03:33.030683 ==
744 11:03:33.034003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 11:03:33.040508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 11:03:33.049120 [CA 0] Center 37 (7~68) winsize 62
747 11:03:33.052434 [CA 1] Center 37 (6~68) winsize 63
748 11:03:33.055896 [CA 2] Center 35 (4~66) winsize 63
749 11:03:33.059298 [CA 3] Center 34 (4~65) winsize 62
750 11:03:33.062663 [CA 4] Center 33 (3~64) winsize 62
751 11:03:33.065908 [CA 5] Center 33 (3~64) winsize 62
752 11:03:33.065986
753 11:03:33.069188 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 11:03:33.069324
755 11:03:33.072443 [CATrainingPosCal] consider 2 rank data
756 11:03:33.075656 u2DelayCellTimex100 = 270/100 ps
757 11:03:33.079138 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 11:03:33.082398 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:03:33.089004 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 11:03:33.092339 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
761 11:03:33.095933 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
762 11:03:33.099340 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 11:03:33.099414
764 11:03:33.102351 CA PerBit enable=1, Macro0, CA PI delay=33
765 11:03:33.102470
766 11:03:33.105813 [CBTSetCACLKResult] CA Dly = 33
767 11:03:33.105889 CS Dly: 6 (0~38)
768 11:03:33.105946
769 11:03:33.109428 ----->DramcWriteLeveling(PI) begin...
770 11:03:33.112504 ==
771 11:03:33.115967 Dram Type= 6, Freq= 0, CH_0, rank 0
772 11:03:33.119134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 11:03:33.119209 ==
774 11:03:33.122617 Write leveling (Byte 0): 29 => 29
775 11:03:33.125997 Write leveling (Byte 1): 29 => 29
776 11:03:33.129185 DramcWriteLeveling(PI) end<-----
777 11:03:33.129327
778 11:03:33.129421 ==
779 11:03:33.132388 Dram Type= 6, Freq= 0, CH_0, rank 0
780 11:03:33.135669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 11:03:33.135743 ==
782 11:03:33.139293 [Gating] SW mode calibration
783 11:03:33.145982 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 11:03:33.149131 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 11:03:33.155775 0 6 0 | B1->B0 | 3232 3333 | 1 1 | (1 0) (1 0)
786 11:03:33.159026 0 6 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
787 11:03:33.162804 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:03:33.169201 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:03:33.172630 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:03:33.175913 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:03:33.182571 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:03:33.185901 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:03:33.189391 0 7 0 | B1->B0 | 2424 2525 | 1 1 | (0 0) (0 0)
794 11:03:33.196145 0 7 4 | B1->B0 | 3a3a 4141 | 1 0 | (0 0) (0 0)
795 11:03:33.199053 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 11:03:33.202754 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:03:33.209048 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:03:33.212660 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:03:33.215761 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:03:33.222666 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:03:33.225910 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 11:03:33.229368 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
803 11:03:33.235719 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 11:03:33.239066 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:03:33.242465 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:03:33.246000 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:03:33.252446 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:03:33.255637 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:03:33.259152 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:03:33.265799 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:03:33.269396 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:03:33.272684 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:03:33.279151 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:03:33.282415 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:03:33.285762 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:03:33.292700 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:03:33.295747 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
818 11:03:33.299128 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
819 11:03:33.302801 Total UI for P1: 0, mck2ui 16
820 11:03:33.306054 best dqsien dly found for B1: ( 0, 10, 2)
821 11:03:33.309375 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
822 11:03:33.312773 Total UI for P1: 0, mck2ui 16
823 11:03:33.315994 best dqsien dly found for B0: ( 0, 10, 2)
824 11:03:33.319453 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 11:03:33.326221 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
826 11:03:33.326299
827 11:03:33.329496 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 11:03:33.333008 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 11:03:33.336376 [Gating] SW calibration Done
830 11:03:33.336475 ==
831 11:03:33.339692 Dram Type= 6, Freq= 0, CH_0, rank 0
832 11:03:33.342825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 11:03:33.342903 ==
834 11:03:33.342995 RX Vref Scan: 0
835 11:03:33.346606
836 11:03:33.346682 RX Vref 0 -> 0, step: 1
837 11:03:33.346757
838 11:03:33.349563 RX Delay -130 -> 252, step: 16
839 11:03:33.352740 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
840 11:03:33.356066 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 11:03:33.362855 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
842 11:03:33.366341 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 11:03:33.369546 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 11:03:33.372900 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 11:03:33.376268 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 11:03:33.382797 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 11:03:33.386028 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 11:03:33.389660 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 11:03:33.392773 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 11:03:33.396013 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 11:03:33.402680 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
852 11:03:33.405968 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
853 11:03:33.409384 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 11:03:33.412622 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 11:03:33.412698 ==
856 11:03:33.416079 Dram Type= 6, Freq= 0, CH_0, rank 0
857 11:03:33.422632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 11:03:33.422712 ==
859 11:03:33.422787 DQS Delay:
860 11:03:33.422857 DQS0 = 0, DQS1 = 0
861 11:03:33.426037 DQM Delay:
862 11:03:33.426114 DQM0 = 84, DQM1 = 72
863 11:03:33.429569 DQ Delay:
864 11:03:33.433063 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
865 11:03:33.433139 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 11:03:33.436100 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 11:03:33.442838 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
868 11:03:33.442917
869 11:03:33.442993
870 11:03:33.443063 ==
871 11:03:33.446002 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:03:33.449392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 11:03:33.449495 ==
874 11:03:33.449586
875 11:03:33.449679
876 11:03:33.452967 TX Vref Scan disable
877 11:03:33.453065 == TX Byte 0 ==
878 11:03:33.459383 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
879 11:03:33.463113 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
880 11:03:33.463191 == TX Byte 1 ==
881 11:03:33.469608 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
882 11:03:33.473158 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
883 11:03:33.473262 ==
884 11:03:33.476348 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:03:33.479787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 11:03:33.479871 ==
887 11:03:33.492655 TX Vref=22, minBit 2, minWin=27, winSum=445
888 11:03:33.496184 TX Vref=24, minBit 2, minWin=27, winSum=446
889 11:03:33.499556 TX Vref=26, minBit 5, minWin=27, winSum=451
890 11:03:33.503195 TX Vref=28, minBit 4, minWin=27, winSum=451
891 11:03:33.506103 TX Vref=30, minBit 4, minWin=27, winSum=455
892 11:03:33.509671 TX Vref=32, minBit 0, minWin=27, winSum=452
893 11:03:33.516233 [TxChooseVref] Worse bit 4, Min win 27, Win sum 455, Final Vref 30
894 11:03:33.516329
895 11:03:33.519405 Final TX Range 1 Vref 30
896 11:03:33.519483
897 11:03:33.519541 ==
898 11:03:33.522634 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:03:33.526027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 11:03:33.526106 ==
901 11:03:33.526165
902 11:03:33.529432
903 11:03:33.529508 TX Vref Scan disable
904 11:03:33.532564 == TX Byte 0 ==
905 11:03:33.536064 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
906 11:03:33.539461 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
907 11:03:33.542804 == TX Byte 1 ==
908 11:03:33.546098 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
909 11:03:33.549470 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
910 11:03:33.552805
911 11:03:33.552888 [DATLAT]
912 11:03:33.552947 Freq=800, CH0 RK0
913 11:03:33.553004
914 11:03:33.556072 DATLAT Default: 0xa
915 11:03:33.556146 0, 0xFFFF, sum = 0
916 11:03:33.559205 1, 0xFFFF, sum = 0
917 11:03:33.559283 2, 0xFFFF, sum = 0
918 11:03:33.562708 3, 0xFFFF, sum = 0
919 11:03:33.562817 4, 0xFFFF, sum = 0
920 11:03:33.566414 5, 0xFFFF, sum = 0
921 11:03:33.569291 6, 0xFFFF, sum = 0
922 11:03:33.569368 7, 0xFFFF, sum = 0
923 11:03:33.569428 8, 0x0, sum = 1
924 11:03:33.572586 9, 0x0, sum = 2
925 11:03:33.572663 10, 0x0, sum = 3
926 11:03:33.575929 11, 0x0, sum = 4
927 11:03:33.576005 best_step = 9
928 11:03:33.576062
929 11:03:33.576114 ==
930 11:03:33.579303 Dram Type= 6, Freq= 0, CH_0, rank 0
931 11:03:33.586001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 11:03:33.586077 ==
933 11:03:33.586135 RX Vref Scan: 1
934 11:03:33.586188
935 11:03:33.589387 Set Vref Range= 32 -> 127
936 11:03:33.589496
937 11:03:33.592755 RX Vref 32 -> 127, step: 1
938 11:03:33.592853
939 11:03:33.592938 RX Delay -111 -> 252, step: 8
940 11:03:33.596555
941 11:03:33.596631 Set Vref, RX VrefLevel [Byte0]: 32
942 11:03:33.599314 [Byte1]: 32
943 11:03:33.603743
944 11:03:33.603820 Set Vref, RX VrefLevel [Byte0]: 33
945 11:03:33.606952 [Byte1]: 33
946 11:03:33.611601
947 11:03:33.611684 Set Vref, RX VrefLevel [Byte0]: 34
948 11:03:33.614744 [Byte1]: 34
949 11:03:33.619080
950 11:03:33.619157 Set Vref, RX VrefLevel [Byte0]: 35
951 11:03:33.622442 [Byte1]: 35
952 11:03:33.626504
953 11:03:33.626578 Set Vref, RX VrefLevel [Byte0]: 36
954 11:03:33.629988 [Byte1]: 36
955 11:03:33.634187
956 11:03:33.634262 Set Vref, RX VrefLevel [Byte0]: 37
957 11:03:33.637513 [Byte1]: 37
958 11:03:33.642131
959 11:03:33.642238 Set Vref, RX VrefLevel [Byte0]: 38
960 11:03:33.645167 [Byte1]: 38
961 11:03:33.649612
962 11:03:33.649693 Set Vref, RX VrefLevel [Byte0]: 39
963 11:03:33.652755 [Byte1]: 39
964 11:03:33.657100
965 11:03:33.657191 Set Vref, RX VrefLevel [Byte0]: 40
966 11:03:33.660694 [Byte1]: 40
967 11:03:33.664723
968 11:03:33.664798 Set Vref, RX VrefLevel [Byte0]: 41
969 11:03:33.668412 [Byte1]: 41
970 11:03:33.672879
971 11:03:33.672954 Set Vref, RX VrefLevel [Byte0]: 42
972 11:03:33.675910 [Byte1]: 42
973 11:03:33.680068
974 11:03:33.680146 Set Vref, RX VrefLevel [Byte0]: 43
975 11:03:33.683502 [Byte1]: 43
976 11:03:33.688019
977 11:03:33.688094 Set Vref, RX VrefLevel [Byte0]: 44
978 11:03:33.691277 [Byte1]: 44
979 11:03:33.695311
980 11:03:33.695385 Set Vref, RX VrefLevel [Byte0]: 45
981 11:03:33.698732 [Byte1]: 45
982 11:03:33.702954
983 11:03:33.706490 Set Vref, RX VrefLevel [Byte0]: 46
984 11:03:33.709761 [Byte1]: 46
985 11:03:33.709836
986 11:03:33.712857 Set Vref, RX VrefLevel [Byte0]: 47
987 11:03:33.716138 [Byte1]: 47
988 11:03:33.716218
989 11:03:33.719608 Set Vref, RX VrefLevel [Byte0]: 48
990 11:03:33.722977 [Byte1]: 48
991 11:03:33.723052
992 11:03:33.726373 Set Vref, RX VrefLevel [Byte0]: 49
993 11:03:33.729625 [Byte1]: 49
994 11:03:33.733619
995 11:03:33.733694 Set Vref, RX VrefLevel [Byte0]: 50
996 11:03:33.736865 [Byte1]: 50
997 11:03:33.741464
998 11:03:33.741539 Set Vref, RX VrefLevel [Byte0]: 51
999 11:03:33.744518 [Byte1]: 51
1000 11:03:33.748836
1001 11:03:33.748910 Set Vref, RX VrefLevel [Byte0]: 52
1002 11:03:33.752188 [Byte1]: 52
1003 11:03:33.756767
1004 11:03:33.756843 Set Vref, RX VrefLevel [Byte0]: 53
1005 11:03:33.760012 [Byte1]: 53
1006 11:03:33.764486
1007 11:03:33.764560 Set Vref, RX VrefLevel [Byte0]: 54
1008 11:03:33.767774 [Byte1]: 54
1009 11:03:33.771991
1010 11:03:33.772066 Set Vref, RX VrefLevel [Byte0]: 55
1011 11:03:33.775160 [Byte1]: 55
1012 11:03:33.779541
1013 11:03:33.779615 Set Vref, RX VrefLevel [Byte0]: 56
1014 11:03:33.782775 [Byte1]: 56
1015 11:03:33.787191
1016 11:03:33.787266 Set Vref, RX VrefLevel [Byte0]: 57
1017 11:03:33.790391 [Byte1]: 57
1018 11:03:33.794633
1019 11:03:33.794707 Set Vref, RX VrefLevel [Byte0]: 58
1020 11:03:33.798029 [Byte1]: 58
1021 11:03:33.802665
1022 11:03:33.802741 Set Vref, RX VrefLevel [Byte0]: 59
1023 11:03:33.805684 [Byte1]: 59
1024 11:03:33.810078
1025 11:03:33.810174 Set Vref, RX VrefLevel [Byte0]: 60
1026 11:03:33.813267 [Byte1]: 60
1027 11:03:33.817938
1028 11:03:33.818016 Set Vref, RX VrefLevel [Byte0]: 61
1029 11:03:33.820949 [Byte1]: 61
1030 11:03:33.825710
1031 11:03:33.825787 Set Vref, RX VrefLevel [Byte0]: 62
1032 11:03:33.828633 [Byte1]: 62
1033 11:03:33.833165
1034 11:03:33.833281 Set Vref, RX VrefLevel [Byte0]: 63
1035 11:03:33.836206 [Byte1]: 63
1036 11:03:33.841121
1037 11:03:33.841200 Set Vref, RX VrefLevel [Byte0]: 64
1038 11:03:33.844060 [Byte1]: 64
1039 11:03:33.848172
1040 11:03:33.848251 Set Vref, RX VrefLevel [Byte0]: 65
1041 11:03:33.851612 [Byte1]: 65
1042 11:03:33.856073
1043 11:03:33.856153 Set Vref, RX VrefLevel [Byte0]: 66
1044 11:03:33.859183 [Byte1]: 66
1045 11:03:33.863702
1046 11:03:33.863779 Set Vref, RX VrefLevel [Byte0]: 67
1047 11:03:33.867089 [Byte1]: 67
1048 11:03:33.871242
1049 11:03:33.871319 Set Vref, RX VrefLevel [Byte0]: 68
1050 11:03:33.874644 [Byte1]: 68
1051 11:03:33.879177
1052 11:03:33.879252 Set Vref, RX VrefLevel [Byte0]: 69
1053 11:03:33.882251 [Byte1]: 69
1054 11:03:33.886501
1055 11:03:33.886577 Set Vref, RX VrefLevel [Byte0]: 70
1056 11:03:33.889857 [Byte1]: 70
1057 11:03:33.894010
1058 11:03:33.894085 Set Vref, RX VrefLevel [Byte0]: 71
1059 11:03:33.897541 [Byte1]: 71
1060 11:03:33.902065
1061 11:03:33.902142 Set Vref, RX VrefLevel [Byte0]: 72
1062 11:03:33.905123 [Byte1]: 72
1063 11:03:33.909393
1064 11:03:33.909470 Set Vref, RX VrefLevel [Byte0]: 73
1065 11:03:33.912707 [Byte1]: 73
1066 11:03:33.916996
1067 11:03:33.917072 Set Vref, RX VrefLevel [Byte0]: 74
1068 11:03:33.920296 [Byte1]: 74
1069 11:03:33.924759
1070 11:03:33.924835 Set Vref, RX VrefLevel [Byte0]: 75
1071 11:03:33.928048 [Byte1]: 75
1072 11:03:33.932645
1073 11:03:33.932722 Final RX Vref Byte 0 = 52 to rank0
1074 11:03:33.935597 Final RX Vref Byte 1 = 56 to rank0
1075 11:03:33.938879 Final RX Vref Byte 0 = 52 to rank1
1076 11:03:33.942371 Final RX Vref Byte 1 = 56 to rank1==
1077 11:03:33.945840 Dram Type= 6, Freq= 0, CH_0, rank 0
1078 11:03:33.952629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1079 11:03:33.952709 ==
1080 11:03:33.952768 DQS Delay:
1081 11:03:33.952822 DQS0 = 0, DQS1 = 0
1082 11:03:33.955654 DQM Delay:
1083 11:03:33.955729 DQM0 = 84, DQM1 = 73
1084 11:03:33.959258 DQ Delay:
1085 11:03:33.962383 DQ0 =80, DQ1 =84, DQ2 =84, DQ3 =80
1086 11:03:33.962459 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1087 11:03:33.965980 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1088 11:03:33.969189 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1089 11:03:33.972292
1090 11:03:33.972366
1091 11:03:33.979209 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1092 11:03:33.982449 CH0 RK0: MR19=606, MR18=3F3F
1093 11:03:33.989264 CH0_RK0: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1094 11:03:33.989348
1095 11:03:33.992554 ----->DramcWriteLeveling(PI) begin...
1096 11:03:33.992633 ==
1097 11:03:33.995844 Dram Type= 6, Freq= 0, CH_0, rank 1
1098 11:03:33.999802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1099 11:03:33.999879 ==
1100 11:03:34.002631 Write leveling (Byte 0): 31 => 31
1101 11:03:34.005985 Write leveling (Byte 1): 31 => 31
1102 11:03:34.009214 DramcWriteLeveling(PI) end<-----
1103 11:03:34.009330
1104 11:03:34.009388 ==
1105 11:03:34.012515 Dram Type= 6, Freq= 0, CH_0, rank 1
1106 11:03:34.016055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1107 11:03:34.016132 ==
1108 11:03:34.019274 [Gating] SW mode calibration
1109 11:03:34.025705 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1110 11:03:34.032461 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1111 11:03:34.035847 0 6 0 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
1112 11:03:34.039158 0 6 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1113 11:03:34.045902 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 11:03:34.049235 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 11:03:34.052634 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 11:03:34.059523 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 11:03:34.062639 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 11:03:34.065721 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 11:03:34.072305 0 7 0 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
1120 11:03:34.075706 0 7 4 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1121 11:03:34.079101 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 11:03:34.082323 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 11:03:34.089194 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 11:03:34.092700 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 11:03:34.095746 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 11:03:34.102637 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 11:03:34.105944 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1128 11:03:34.109150 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1129 11:03:34.116120 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 11:03:34.119162 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 11:03:34.122693 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 11:03:34.129343 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 11:03:34.132359 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 11:03:34.135922 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 11:03:34.142366 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 11:03:34.145591 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 11:03:34.149069 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 11:03:34.155611 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 11:03:34.159298 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 11:03:34.162387 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 11:03:34.169126 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 11:03:34.172559 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 11:03:34.175692 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 11:03:34.179162 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1145 11:03:34.182395 Total UI for P1: 0, mck2ui 16
1146 11:03:34.185816 best dqsien dly found for B0: ( 0, 10, 2)
1147 11:03:34.189208 Total UI for P1: 0, mck2ui 16
1148 11:03:34.192666 best dqsien dly found for B1: ( 0, 10, 2)
1149 11:03:34.196322 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1150 11:03:34.199580 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1151 11:03:34.199656
1152 11:03:34.205959 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1153 11:03:34.209212 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1154 11:03:34.253590 [Gating] SW calibration Done
1155 11:03:34.253717 ==
1156 11:03:34.253777 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 11:03:34.254022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1158 11:03:34.254083 ==
1159 11:03:34.254135 RX Vref Scan: 0
1160 11:03:34.254186
1161 11:03:34.254235 RX Vref 0 -> 0, step: 1
1162 11:03:34.254283
1163 11:03:34.254332 RX Delay -130 -> 252, step: 16
1164 11:03:34.254381 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1165 11:03:34.254441 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1166 11:03:34.254496 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1167 11:03:34.254554 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1168 11:03:34.254615 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1169 11:03:34.254847 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1170 11:03:34.254902 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1171 11:03:34.277182 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1172 11:03:34.277502 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1173 11:03:34.277567 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1174 11:03:34.277897 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1175 11:03:34.278153 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1176 11:03:34.280924 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1177 11:03:34.281001 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1178 11:03:34.284423 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1179 11:03:34.290912 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1180 11:03:34.290989 ==
1181 11:03:34.294063 Dram Type= 6, Freq= 0, CH_0, rank 1
1182 11:03:34.297357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1183 11:03:34.297434 ==
1184 11:03:34.297493 DQS Delay:
1185 11:03:34.301149 DQS0 = 0, DQS1 = 0
1186 11:03:34.301250 DQM Delay:
1187 11:03:34.304089 DQM0 = 82, DQM1 = 74
1188 11:03:34.304164 DQ Delay:
1189 11:03:34.307324 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1190 11:03:34.310733 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1191 11:03:34.313987 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1192 11:03:34.317415 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1193 11:03:34.317491
1194 11:03:34.317549
1195 11:03:34.317604 ==
1196 11:03:34.320778 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 11:03:34.324048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1198 11:03:34.327313 ==
1199 11:03:34.327389
1200 11:03:34.327447
1201 11:03:34.327500 TX Vref Scan disable
1202 11:03:34.330687 == TX Byte 0 ==
1203 11:03:34.333879 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1204 11:03:34.337453 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1205 11:03:34.340705 == TX Byte 1 ==
1206 11:03:34.343861 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1207 11:03:34.347161 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1208 11:03:34.350698 ==
1209 11:03:34.350775 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 11:03:34.357074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1211 11:03:34.357155 ==
1212 11:03:34.369243 TX Vref=22, minBit 1, minWin=27, winSum=447
1213 11:03:34.372562 TX Vref=24, minBit 0, minWin=28, winSum=453
1214 11:03:34.375720 TX Vref=26, minBit 2, minWin=28, winSum=455
1215 11:03:34.379192 TX Vref=28, minBit 0, minWin=28, winSum=454
1216 11:03:34.382458 TX Vref=30, minBit 4, minWin=28, winSum=458
1217 11:03:34.386009 TX Vref=32, minBit 0, minWin=28, winSum=457
1218 11:03:34.392671 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 30
1219 11:03:34.392750
1220 11:03:34.396182 Final TX Range 1 Vref 30
1221 11:03:34.396258
1222 11:03:34.396316 ==
1223 11:03:34.399161 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 11:03:34.402481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1225 11:03:34.402558 ==
1226 11:03:34.402616
1227 11:03:34.405605
1228 11:03:34.405680 TX Vref Scan disable
1229 11:03:34.409126 == TX Byte 0 ==
1230 11:03:34.412400 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1231 11:03:34.415843 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1232 11:03:34.419489 == TX Byte 1 ==
1233 11:03:34.422567 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1234 11:03:34.426003 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1235 11:03:34.426080
1236 11:03:34.429442 [DATLAT]
1237 11:03:34.429521 Freq=800, CH0 RK1
1238 11:03:34.429580
1239 11:03:34.432649 DATLAT Default: 0x9
1240 11:03:34.432725 0, 0xFFFF, sum = 0
1241 11:03:34.435991 1, 0xFFFF, sum = 0
1242 11:03:34.436068 2, 0xFFFF, sum = 0
1243 11:03:34.439285 3, 0xFFFF, sum = 0
1244 11:03:34.439361 4, 0xFFFF, sum = 0
1245 11:03:34.442514 5, 0xFFFF, sum = 0
1246 11:03:34.442591 6, 0xFFFF, sum = 0
1247 11:03:34.445985 7, 0xFFFF, sum = 0
1248 11:03:34.446061 8, 0x0, sum = 1
1249 11:03:34.449127 9, 0x0, sum = 2
1250 11:03:34.449203 10, 0x0, sum = 3
1251 11:03:34.452385 11, 0x0, sum = 4
1252 11:03:34.452462 best_step = 9
1253 11:03:34.452520
1254 11:03:34.452572 ==
1255 11:03:34.455620 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 11:03:34.462448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1257 11:03:34.462534 ==
1258 11:03:34.462592 RX Vref Scan: 0
1259 11:03:34.462678
1260 11:03:34.465849 RX Vref 0 -> 0, step: 1
1261 11:03:34.465925
1262 11:03:34.469422 RX Delay -111 -> 252, step: 8
1263 11:03:34.472419 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1264 11:03:34.475983 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1265 11:03:34.482415 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1266 11:03:34.485740 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1267 11:03:34.489126 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1268 11:03:34.492398 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1269 11:03:34.495695 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1270 11:03:34.499434 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1271 11:03:34.505679 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1272 11:03:34.509082 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1273 11:03:34.512412 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1274 11:03:34.515880 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1275 11:03:34.519208 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1276 11:03:34.526023 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1277 11:03:34.529352 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1278 11:03:34.532694 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1279 11:03:34.532771 ==
1280 11:03:34.536026 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 11:03:34.539220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1282 11:03:34.539299 ==
1283 11:03:34.542943 DQS Delay:
1284 11:03:34.543020 DQS0 = 0, DQS1 = 0
1285 11:03:34.545891 DQM Delay:
1286 11:03:34.545968 DQM0 = 87, DQM1 = 74
1287 11:03:34.546027 DQ Delay:
1288 11:03:34.549421 DQ0 =84, DQ1 =88, DQ2 =88, DQ3 =84
1289 11:03:34.552587 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1290 11:03:34.555821 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1291 11:03:34.559404 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1292 11:03:34.559481
1293 11:03:34.559539
1294 11:03:34.569237 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f4f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1295 11:03:34.572685 CH0 RK1: MR19=606, MR18=4F4F
1296 11:03:34.576060 CH0_RK1: MR19=0x606, MR18=0x4F4F, DQSOSC=390, MR23=63, INC=97, DEC=64
1297 11:03:34.579582 [RxdqsGatingPostProcess] freq 800
1298 11:03:34.585932 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1299 11:03:34.589371 Pre-setting of DQS Precalculation
1300 11:03:34.592601 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1301 11:03:34.592678 ==
1302 11:03:34.595948 Dram Type= 6, Freq= 0, CH_1, rank 0
1303 11:03:34.602650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1304 11:03:34.602737 ==
1305 11:03:34.605886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1306 11:03:34.612503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1307 11:03:34.621654 [CA 0] Center 36 (6~67) winsize 62
1308 11:03:34.625420 [CA 1] Center 36 (5~67) winsize 63
1309 11:03:34.628605 [CA 2] Center 34 (4~65) winsize 62
1310 11:03:34.631954 [CA 3] Center 34 (3~65) winsize 63
1311 11:03:34.635169 [CA 4] Center 33 (2~64) winsize 63
1312 11:03:34.638703 [CA 5] Center 33 (3~64) winsize 62
1313 11:03:34.638778
1314 11:03:34.642055 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1315 11:03:34.642129
1316 11:03:34.645516 [CATrainingPosCal] consider 1 rank data
1317 11:03:34.648499 u2DelayCellTimex100 = 270/100 ps
1318 11:03:34.651872 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1319 11:03:34.655530 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1320 11:03:34.661960 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1321 11:03:34.665557 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1322 11:03:34.668707 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1323 11:03:34.672009 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1324 11:03:34.672086
1325 11:03:34.675153 CA PerBit enable=1, Macro0, CA PI delay=33
1326 11:03:34.675227
1327 11:03:34.678512 [CBTSetCACLKResult] CA Dly = 33
1328 11:03:34.678586 CS Dly: 4 (0~35)
1329 11:03:34.678644 ==
1330 11:03:34.682089 Dram Type= 6, Freq= 0, CH_1, rank 1
1331 11:03:34.688530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1332 11:03:34.688606 ==
1333 11:03:34.692048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1334 11:03:34.698846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1335 11:03:34.707515 [CA 0] Center 36 (5~67) winsize 63
1336 11:03:34.710751 [CA 1] Center 36 (5~67) winsize 63
1337 11:03:34.714013 [CA 2] Center 34 (4~65) winsize 62
1338 11:03:34.717410 [CA 3] Center 33 (3~64) winsize 62
1339 11:03:34.720836 [CA 4] Center 33 (3~64) winsize 62
1340 11:03:34.724198 [CA 5] Center 32 (2~63) winsize 62
1341 11:03:34.724273
1342 11:03:34.727825 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1343 11:03:34.727908
1344 11:03:34.731284 [CATrainingPosCal] consider 2 rank data
1345 11:03:34.734150 u2DelayCellTimex100 = 270/100 ps
1346 11:03:34.738033 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1347 11:03:34.741159 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1348 11:03:34.747487 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1349 11:03:34.751191 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1350 11:03:34.754243 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1351 11:03:34.757594 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1352 11:03:34.757676
1353 11:03:34.760917 CA PerBit enable=1, Macro0, CA PI delay=33
1354 11:03:34.760993
1355 11:03:34.764534 [CBTSetCACLKResult] CA Dly = 33
1356 11:03:34.764643 CS Dly: 4 (0~36)
1357 11:03:34.764734
1358 11:03:34.767748 ----->DramcWriteLeveling(PI) begin...
1359 11:03:34.767827 ==
1360 11:03:34.771066 Dram Type= 6, Freq= 0, CH_1, rank 0
1361 11:03:34.777870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1362 11:03:34.777950 ==
1363 11:03:34.780955 Write leveling (Byte 0): 25 => 25
1364 11:03:34.784150 Write leveling (Byte 1): 25 => 25
1365 11:03:34.784226 DramcWriteLeveling(PI) end<-----
1366 11:03:34.787476
1367 11:03:34.787552 ==
1368 11:03:34.790794 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 11:03:34.794169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1370 11:03:34.794246 ==
1371 11:03:34.797683 [Gating] SW mode calibration
1372 11:03:34.804206 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1373 11:03:34.807618 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1374 11:03:34.814292 0 6 0 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 0)
1375 11:03:34.817544 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 11:03:34.820976 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 11:03:34.827732 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 11:03:34.831040 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 11:03:34.834322 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 11:03:34.840995 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 11:03:34.844207 0 6 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1382 11:03:34.848257 0 7 0 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
1383 11:03:34.854533 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1384 11:03:34.857780 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 11:03:34.861134 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 11:03:34.864406 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 11:03:34.871038 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 11:03:34.874743 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 11:03:34.877945 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 11:03:34.884798 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1391 11:03:34.888003 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 11:03:34.891167 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 11:03:34.897642 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 11:03:34.901074 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 11:03:34.904485 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 11:03:34.911119 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 11:03:34.914325 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 11:03:34.917886 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 11:03:34.924439 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 11:03:34.927758 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 11:03:34.931179 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 11:03:34.937785 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 11:03:34.941152 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 11:03:34.944405 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 11:03:34.951150 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 11:03:34.954684 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1407 11:03:34.957712 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1408 11:03:34.961181 Total UI for P1: 0, mck2ui 16
1409 11:03:34.964579 best dqsien dly found for B0: ( 0, 10, 0)
1410 11:03:34.967834 Total UI for P1: 0, mck2ui 16
1411 11:03:34.971351 best dqsien dly found for B1: ( 0, 10, 0)
1412 11:03:34.974633 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1413 11:03:34.977885 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1414 11:03:34.977991
1415 11:03:34.981172 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1416 11:03:34.984552 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1417 11:03:34.988480 [Gating] SW calibration Done
1418 11:03:34.988609 ==
1419 11:03:34.991126 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 11:03:34.997882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1421 11:03:34.998045 ==
1422 11:03:34.998121 RX Vref Scan: 0
1423 11:03:34.998176
1424 11:03:35.001160 RX Vref 0 -> 0, step: 1
1425 11:03:35.001289
1426 11:03:35.004420 RX Delay -130 -> 252, step: 16
1427 11:03:35.007820 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1428 11:03:35.011141 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1429 11:03:35.014507 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1430 11:03:35.017839 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1431 11:03:35.024713 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1432 11:03:35.027941 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1433 11:03:35.031564 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1434 11:03:35.034853 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1435 11:03:35.037849 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1436 11:03:35.044495 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1437 11:03:35.048036 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1438 11:03:35.051174 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1439 11:03:35.054709 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1440 11:03:35.058274 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1441 11:03:35.064805 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1442 11:03:35.068238 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1443 11:03:35.068316 ==
1444 11:03:35.071171 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 11:03:35.074502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1446 11:03:35.074578 ==
1447 11:03:35.077843 DQS Delay:
1448 11:03:35.077917 DQS0 = 0, DQS1 = 0
1449 11:03:35.077975 DQM Delay:
1450 11:03:35.081427 DQM0 = 84, DQM1 = 74
1451 11:03:35.081502 DQ Delay:
1452 11:03:35.084719 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1453 11:03:35.087815 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =85
1454 11:03:35.091232 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1455 11:03:35.094968 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1456 11:03:35.095045
1457 11:03:35.095103
1458 11:03:35.095156 ==
1459 11:03:35.097756 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 11:03:35.104771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1461 11:03:35.104851 ==
1462 11:03:35.104909
1463 11:03:35.104962
1464 11:03:35.105012 TX Vref Scan disable
1465 11:03:35.107738 == TX Byte 0 ==
1466 11:03:35.111426 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1467 11:03:35.114631 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1468 11:03:35.118019 == TX Byte 1 ==
1469 11:03:35.121371 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1470 11:03:35.124782 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1471 11:03:35.127946 ==
1472 11:03:35.131433 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 11:03:35.134460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1474 11:03:35.134537 ==
1475 11:03:35.146642 TX Vref=22, minBit 3, minWin=27, winSum=444
1476 11:03:35.149941 TX Vref=24, minBit 3, minWin=27, winSum=447
1477 11:03:35.153094 TX Vref=26, minBit 0, minWin=28, winSum=453
1478 11:03:35.156571 TX Vref=28, minBit 0, minWin=28, winSum=455
1479 11:03:35.160015 TX Vref=30, minBit 3, minWin=28, winSum=457
1480 11:03:35.163279 TX Vref=32, minBit 0, minWin=28, winSum=451
1481 11:03:35.170148 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30
1482 11:03:35.170228
1483 11:03:35.173552 Final TX Range 1 Vref 30
1484 11:03:35.173667
1485 11:03:35.173767 ==
1486 11:03:35.176910 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 11:03:35.180140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1488 11:03:35.180216 ==
1489 11:03:35.180274
1490 11:03:35.180327
1491 11:03:35.183392 TX Vref Scan disable
1492 11:03:35.186978 == TX Byte 0 ==
1493 11:03:35.190114 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1494 11:03:35.193320 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1495 11:03:35.196535 == TX Byte 1 ==
1496 11:03:35.200059 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1497 11:03:35.203515 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1498 11:03:35.203593
1499 11:03:35.206732 [DATLAT]
1500 11:03:35.206809 Freq=800, CH1 RK0
1501 11:03:35.206869
1502 11:03:35.210017 DATLAT Default: 0xa
1503 11:03:35.210096 0, 0xFFFF, sum = 0
1504 11:03:35.213424 1, 0xFFFF, sum = 0
1505 11:03:35.213501 2, 0xFFFF, sum = 0
1506 11:03:35.216681 3, 0xFFFF, sum = 0
1507 11:03:35.216758 4, 0xFFFF, sum = 0
1508 11:03:35.220106 5, 0xFFFF, sum = 0
1509 11:03:35.220183 6, 0xFFFF, sum = 0
1510 11:03:35.223283 7, 0xFFFF, sum = 0
1511 11:03:35.223359 8, 0x0, sum = 1
1512 11:03:35.226749 9, 0x0, sum = 2
1513 11:03:35.226828 10, 0x0, sum = 3
1514 11:03:35.230018 11, 0x0, sum = 4
1515 11:03:35.230094 best_step = 9
1516 11:03:35.230152
1517 11:03:35.230206 ==
1518 11:03:35.233361 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 11:03:35.236726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 11:03:35.240250 ==
1521 11:03:35.240326 RX Vref Scan: 1
1522 11:03:35.240385
1523 11:03:35.243490 Set Vref Range= 32 -> 127
1524 11:03:35.243566
1525 11:03:35.246866 RX Vref 32 -> 127, step: 1
1526 11:03:35.246942
1527 11:03:35.247001 RX Delay -111 -> 252, step: 8
1528 11:03:35.247055
1529 11:03:35.250032 Set Vref, RX VrefLevel [Byte0]: 32
1530 11:03:35.253344 [Byte1]: 32
1531 11:03:35.257462
1532 11:03:35.257541 Set Vref, RX VrefLevel [Byte0]: 33
1533 11:03:35.260797 [Byte1]: 33
1534 11:03:35.265099
1535 11:03:35.265177 Set Vref, RX VrefLevel [Byte0]: 34
1536 11:03:35.268277 [Byte1]: 34
1537 11:03:35.273060
1538 11:03:35.273137 Set Vref, RX VrefLevel [Byte0]: 35
1539 11:03:35.276184 [Byte1]: 35
1540 11:03:35.280364
1541 11:03:35.280440 Set Vref, RX VrefLevel [Byte0]: 36
1542 11:03:35.283643 [Byte1]: 36
1543 11:03:35.287996
1544 11:03:35.288073 Set Vref, RX VrefLevel [Byte0]: 37
1545 11:03:35.291159 [Byte1]: 37
1546 11:03:35.295790
1547 11:03:35.295867 Set Vref, RX VrefLevel [Byte0]: 38
1548 11:03:35.298748 [Byte1]: 38
1549 11:03:35.303307
1550 11:03:35.303383 Set Vref, RX VrefLevel [Byte0]: 39
1551 11:03:35.306674 [Byte1]: 39
1552 11:03:35.310968
1553 11:03:35.311046 Set Vref, RX VrefLevel [Byte0]: 40
1554 11:03:35.314207 [Byte1]: 40
1555 11:03:35.318424
1556 11:03:35.318503 Set Vref, RX VrefLevel [Byte0]: 41
1557 11:03:35.321885 [Byte1]: 41
1558 11:03:35.326274
1559 11:03:35.326349 Set Vref, RX VrefLevel [Byte0]: 42
1560 11:03:35.329512 [Byte1]: 42
1561 11:03:35.334001
1562 11:03:35.334078 Set Vref, RX VrefLevel [Byte0]: 43
1563 11:03:35.337215 [Byte1]: 43
1564 11:03:35.341447
1565 11:03:35.341529 Set Vref, RX VrefLevel [Byte0]: 44
1566 11:03:35.344855 [Byte1]: 44
1567 11:03:35.349115
1568 11:03:35.349217 Set Vref, RX VrefLevel [Byte0]: 45
1569 11:03:35.352330 [Byte1]: 45
1570 11:03:35.356873
1571 11:03:35.356949 Set Vref, RX VrefLevel [Byte0]: 46
1572 11:03:35.360367 [Byte1]: 46
1573 11:03:35.364409
1574 11:03:35.364486 Set Vref, RX VrefLevel [Byte0]: 47
1575 11:03:35.367844 [Byte1]: 47
1576 11:03:35.372065
1577 11:03:35.372142 Set Vref, RX VrefLevel [Byte0]: 48
1578 11:03:35.375497 [Byte1]: 48
1579 11:03:35.379947
1580 11:03:35.380027 Set Vref, RX VrefLevel [Byte0]: 49
1581 11:03:35.383078 [Byte1]: 49
1582 11:03:35.387668
1583 11:03:35.387743 Set Vref, RX VrefLevel [Byte0]: 50
1584 11:03:35.390657 [Byte1]: 50
1585 11:03:35.395003
1586 11:03:35.395078 Set Vref, RX VrefLevel [Byte0]: 51
1587 11:03:35.398324 [Byte1]: 51
1588 11:03:35.402728
1589 11:03:35.402807 Set Vref, RX VrefLevel [Byte0]: 52
1590 11:03:35.406058 [Byte1]: 52
1591 11:03:35.410435
1592 11:03:35.410510 Set Vref, RX VrefLevel [Byte0]: 53
1593 11:03:35.413783 [Byte1]: 53
1594 11:03:35.417968
1595 11:03:35.418048 Set Vref, RX VrefLevel [Byte0]: 54
1596 11:03:35.421353 [Byte1]: 54
1597 11:03:35.425657
1598 11:03:35.425733 Set Vref, RX VrefLevel [Byte0]: 55
1599 11:03:35.429339 [Byte1]: 55
1600 11:03:35.433125
1601 11:03:35.433234 Set Vref, RX VrefLevel [Byte0]: 56
1602 11:03:35.436790 [Byte1]: 56
1603 11:03:35.441063
1604 11:03:35.441138 Set Vref, RX VrefLevel [Byte0]: 57
1605 11:03:35.444612 [Byte1]: 57
1606 11:03:35.448703
1607 11:03:35.448806 Set Vref, RX VrefLevel [Byte0]: 58
1608 11:03:35.452071 [Byte1]: 58
1609 11:03:35.456610
1610 11:03:35.456678 Set Vref, RX VrefLevel [Byte0]: 59
1611 11:03:35.459727 [Byte1]: 59
1612 11:03:35.463937
1613 11:03:35.464011 Set Vref, RX VrefLevel [Byte0]: 60
1614 11:03:35.467476 [Byte1]: 60
1615 11:03:35.471656
1616 11:03:35.471750 Set Vref, RX VrefLevel [Byte0]: 61
1617 11:03:35.475211 [Byte1]: 61
1618 11:03:35.479007
1619 11:03:35.479100 Set Vref, RX VrefLevel [Byte0]: 62
1620 11:03:35.482313 [Byte1]: 62
1621 11:03:35.486857
1622 11:03:35.486952 Set Vref, RX VrefLevel [Byte0]: 63
1623 11:03:35.490215 [Byte1]: 63
1624 11:03:35.494366
1625 11:03:35.494463 Set Vref, RX VrefLevel [Byte0]: 64
1626 11:03:35.497875 [Byte1]: 64
1627 11:03:35.502185
1628 11:03:35.502278 Set Vref, RX VrefLevel [Byte0]: 65
1629 11:03:35.505352 [Byte1]: 65
1630 11:03:35.509773
1631 11:03:35.509848 Set Vref, RX VrefLevel [Byte0]: 66
1632 11:03:35.512900 [Byte1]: 66
1633 11:03:35.517348
1634 11:03:35.517423 Set Vref, RX VrefLevel [Byte0]: 67
1635 11:03:35.520916 [Byte1]: 67
1636 11:03:35.525050
1637 11:03:35.525125 Set Vref, RX VrefLevel [Byte0]: 68
1638 11:03:35.528310 [Byte1]: 68
1639 11:03:35.532642
1640 11:03:35.532717 Set Vref, RX VrefLevel [Byte0]: 69
1641 11:03:35.536253 [Byte1]: 69
1642 11:03:35.540697
1643 11:03:35.540772 Set Vref, RX VrefLevel [Byte0]: 70
1644 11:03:35.544145 [Byte1]: 70
1645 11:03:35.548061
1646 11:03:35.548157 Set Vref, RX VrefLevel [Byte0]: 71
1647 11:03:35.551078 [Byte1]: 71
1648 11:03:35.555819
1649 11:03:35.555894 Set Vref, RX VrefLevel [Byte0]: 72
1650 11:03:35.559140 [Byte1]: 72
1651 11:03:35.563577
1652 11:03:35.563652 Set Vref, RX VrefLevel [Byte0]: 73
1653 11:03:35.566586 [Byte1]: 73
1654 11:03:35.571087
1655 11:03:35.571189 Set Vref, RX VrefLevel [Byte0]: 74
1656 11:03:35.574339 [Byte1]: 74
1657 11:03:35.578562
1658 11:03:35.578661 Final RX Vref Byte 0 = 58 to rank0
1659 11:03:35.581874 Final RX Vref Byte 1 = 53 to rank0
1660 11:03:35.585180 Final RX Vref Byte 0 = 58 to rank1
1661 11:03:35.588637 Final RX Vref Byte 1 = 53 to rank1==
1662 11:03:35.591870 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 11:03:35.595278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1664 11:03:35.598529 ==
1665 11:03:35.598621 DQS Delay:
1666 11:03:35.598704 DQS0 = 0, DQS1 = 0
1667 11:03:35.601960 DQM Delay:
1668 11:03:35.602052 DQM0 = 79, DQM1 = 71
1669 11:03:35.605441 DQ Delay:
1670 11:03:35.608849 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1671 11:03:35.608997 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1672 11:03:35.612318 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1673 11:03:35.615489 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1674 11:03:35.615564
1675 11:03:35.618592
1676 11:03:35.625474 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1677 11:03:35.628664 CH1 RK0: MR19=606, MR18=5454
1678 11:03:35.635548 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1679 11:03:35.635661
1680 11:03:35.639068 ----->DramcWriteLeveling(PI) begin...
1681 11:03:35.639145 ==
1682 11:03:35.641902 Dram Type= 6, Freq= 0, CH_1, rank 1
1683 11:03:35.645697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1684 11:03:35.645774 ==
1685 11:03:35.648794 Write leveling (Byte 0): 26 => 26
1686 11:03:35.652020 Write leveling (Byte 1): 27 => 27
1687 11:03:35.655576 DramcWriteLeveling(PI) end<-----
1688 11:03:35.655650
1689 11:03:35.655709 ==
1690 11:03:35.658863 Dram Type= 6, Freq= 0, CH_1, rank 1
1691 11:03:35.662481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1692 11:03:35.662576 ==
1693 11:03:35.665579 [Gating] SW mode calibration
1694 11:03:35.672158 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1695 11:03:35.678803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1696 11:03:35.682124 0 6 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
1697 11:03:35.685620 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 11:03:35.692468 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 11:03:35.695421 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 11:03:35.698848 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 11:03:35.702153 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 11:03:35.708826 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 11:03:35.712403 0 6 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1704 11:03:35.715527 0 7 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1705 11:03:35.722326 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 11:03:35.725500 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 11:03:35.728829 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 11:03:35.735443 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 11:03:35.738764 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 11:03:35.742337 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 11:03:35.749117 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 11:03:35.752349 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1713 11:03:35.755532 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 11:03:35.762204 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 11:03:35.765669 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 11:03:35.768906 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 11:03:35.775691 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 11:03:35.778942 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 11:03:35.782312 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 11:03:35.789235 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 11:03:35.792378 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 11:03:35.795497 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 11:03:35.802185 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 11:03:35.805474 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 11:03:35.809291 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 11:03:35.812147 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 11:03:35.818853 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1728 11:03:35.822301 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1729 11:03:35.825620 Total UI for P1: 0, mck2ui 16
1730 11:03:35.828990 best dqsien dly found for B0: ( 0, 9, 28)
1731 11:03:35.832338 Total UI for P1: 0, mck2ui 16
1732 11:03:35.835380 best dqsien dly found for B1: ( 0, 9, 30)
1733 11:03:35.838745 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1734 11:03:35.842246 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1735 11:03:35.842347
1736 11:03:35.846582 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1737 11:03:35.851997 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1738 11:03:35.852143 [Gating] SW calibration Done
1739 11:03:35.852204 ==
1740 11:03:35.855584 Dram Type= 6, Freq= 0, CH_1, rank 1
1741 11:03:35.862424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1742 11:03:35.862544 ==
1743 11:03:35.862604 RX Vref Scan: 0
1744 11:03:35.862659
1745 11:03:35.865604 RX Vref 0 -> 0, step: 1
1746 11:03:35.865683
1747 11:03:35.868908 RX Delay -130 -> 252, step: 16
1748 11:03:35.872307 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1749 11:03:35.875610 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1750 11:03:35.878937 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1751 11:03:35.882127 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1752 11:03:35.889001 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1753 11:03:35.892123 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1754 11:03:35.895645 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1755 11:03:35.899091 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1756 11:03:35.902177 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1757 11:03:35.908989 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1758 11:03:35.911999 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1759 11:03:35.915739 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1760 11:03:35.918683 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1761 11:03:35.922017 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1762 11:03:35.928813 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1763 11:03:35.932098 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1764 11:03:35.932239 ==
1765 11:03:35.935564 Dram Type= 6, Freq= 0, CH_1, rank 1
1766 11:03:35.938680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1767 11:03:35.938819 ==
1768 11:03:35.942068 DQS Delay:
1769 11:03:35.942205 DQS0 = 0, DQS1 = 0
1770 11:03:35.942330 DQM Delay:
1771 11:03:35.945251 DQM0 = 80, DQM1 = 70
1772 11:03:35.945399 DQ Delay:
1773 11:03:35.948867 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1774 11:03:35.952046 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1775 11:03:35.955356 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1776 11:03:35.958908 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1777 11:03:35.959048
1778 11:03:35.959174
1779 11:03:35.959295 ==
1780 11:03:35.961909 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 11:03:35.968578 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1782 11:03:35.968721 ==
1783 11:03:35.968847
1784 11:03:35.968968
1785 11:03:35.969085 TX Vref Scan disable
1786 11:03:35.972513 == TX Byte 0 ==
1787 11:03:35.975751 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1788 11:03:35.979295 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1789 11:03:35.982472 == TX Byte 1 ==
1790 11:03:35.985806 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1791 11:03:35.989037 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1792 11:03:35.992293 ==
1793 11:03:35.995783 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 11:03:35.999027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1795 11:03:35.999168 ==
1796 11:03:36.011317 TX Vref=22, minBit 10, minWin=27, winSum=451
1797 11:03:36.014815 TX Vref=24, minBit 5, minWin=28, winSum=455
1798 11:03:36.017837 TX Vref=26, minBit 5, minWin=28, winSum=458
1799 11:03:36.021430 TX Vref=28, minBit 6, minWin=28, winSum=455
1800 11:03:36.024565 TX Vref=30, minBit 9, minWin=27, winSum=457
1801 11:03:36.027965 TX Vref=32, minBit 8, minWin=28, winSum=458
1802 11:03:36.034913 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 26
1803 11:03:36.034993
1804 11:03:36.038039 Final TX Range 1 Vref 26
1805 11:03:36.038137
1806 11:03:36.038223 ==
1807 11:03:36.041187 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 11:03:36.045007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1809 11:03:36.045082 ==
1810 11:03:36.045156
1811 11:03:36.047943
1812 11:03:36.048016 TX Vref Scan disable
1813 11:03:36.051325 == TX Byte 0 ==
1814 11:03:36.054778 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1815 11:03:36.057980 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1816 11:03:36.061448 == TX Byte 1 ==
1817 11:03:36.064661 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1818 11:03:36.068022 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1819 11:03:36.071193
1820 11:03:36.071267 [DATLAT]
1821 11:03:36.071324 Freq=800, CH1 RK1
1822 11:03:36.071377
1823 11:03:36.074585 DATLAT Default: 0x9
1824 11:03:36.074683 0, 0xFFFF, sum = 0
1825 11:03:36.077819 1, 0xFFFF, sum = 0
1826 11:03:36.077912 2, 0xFFFF, sum = 0
1827 11:03:36.081399 3, 0xFFFF, sum = 0
1828 11:03:36.081474 4, 0xFFFF, sum = 0
1829 11:03:36.084596 5, 0xFFFF, sum = 0
1830 11:03:36.084671 6, 0xFFFF, sum = 0
1831 11:03:36.087719 7, 0xFFFF, sum = 0
1832 11:03:36.087793 8, 0x0, sum = 1
1833 11:03:36.091259 9, 0x0, sum = 2
1834 11:03:36.091336 10, 0x0, sum = 3
1835 11:03:36.094716 11, 0x0, sum = 4
1836 11:03:36.094790 best_step = 9
1837 11:03:36.094848
1838 11:03:36.094900 ==
1839 11:03:36.097792 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 11:03:36.104656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1841 11:03:36.104732 ==
1842 11:03:36.104790 RX Vref Scan: 0
1843 11:03:36.104845
1844 11:03:36.107752 RX Vref 0 -> 0, step: 1
1845 11:03:36.107825
1846 11:03:36.111349 RX Delay -111 -> 252, step: 8
1847 11:03:36.114878 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1848 11:03:36.117906 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1849 11:03:36.121423 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1850 11:03:36.127880 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1851 11:03:36.131146 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1852 11:03:36.134373 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1853 11:03:36.137815 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1854 11:03:36.141059 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1855 11:03:36.147733 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1856 11:03:36.151337 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1857 11:03:36.154445 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1858 11:03:36.157900 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1859 11:03:36.161141 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1860 11:03:36.167827 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1861 11:03:36.171126 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1862 11:03:36.174466 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1863 11:03:36.174541 ==
1864 11:03:36.177882 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 11:03:36.181070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1866 11:03:36.184536 ==
1867 11:03:36.184635 DQS Delay:
1868 11:03:36.184694 DQS0 = 0, DQS1 = 0
1869 11:03:36.188003 DQM Delay:
1870 11:03:36.188079 DQM0 = 82, DQM1 = 71
1871 11:03:36.191208 DQ Delay:
1872 11:03:36.191287 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1873 11:03:36.194412 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1874 11:03:36.197725 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1875 11:03:36.200959 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
1876 11:03:36.201080
1877 11:03:36.201170
1878 11:03:36.211249 [DQSOSCAuto] RK1, (LSB)MR18= 0x4343, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1879 11:03:36.214552 CH1 RK1: MR19=606, MR18=4343
1880 11:03:36.221192 CH1_RK1: MR19=0x606, MR18=0x4343, DQSOSC=393, MR23=63, INC=95, DEC=63
1881 11:03:36.221349 [RxdqsGatingPostProcess] freq 800
1882 11:03:36.227901 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1883 11:03:36.231242 Pre-setting of DQS Precalculation
1884 11:03:36.234452 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1885 11:03:36.244888 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1886 11:03:36.251336 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1887 11:03:36.251433
1888 11:03:36.251529
1889 11:03:36.254543 [Calibration Summary] 1600 Mbps
1890 11:03:36.254640 CH 0, Rank 0
1891 11:03:36.257878 SW Impedance : PASS
1892 11:03:36.257982 DUTY Scan : NO K
1893 11:03:36.261219 ZQ Calibration : PASS
1894 11:03:36.264614 Jitter Meter : NO K
1895 11:03:36.264728 CBT Training : PASS
1896 11:03:36.267707 Write leveling : PASS
1897 11:03:36.271050 RX DQS gating : PASS
1898 11:03:36.271250 RX DQ/DQS(RDDQC) : PASS
1899 11:03:36.274585 TX DQ/DQS : PASS
1900 11:03:36.277862 RX DATLAT : PASS
1901 11:03:36.278023 RX DQ/DQS(Engine): PASS
1902 11:03:36.281080 TX OE : NO K
1903 11:03:36.281260 All Pass.
1904 11:03:36.281422
1905 11:03:36.284600 CH 0, Rank 1
1906 11:03:36.284761 SW Impedance : PASS
1907 11:03:36.287809 DUTY Scan : NO K
1908 11:03:36.287971 ZQ Calibration : PASS
1909 11:03:36.291092 Jitter Meter : NO K
1910 11:03:36.294771 CBT Training : PASS
1911 11:03:36.294939 Write leveling : PASS
1912 11:03:36.297887 RX DQS gating : PASS
1913 11:03:36.301239 RX DQ/DQS(RDDQC) : PASS
1914 11:03:36.301374 TX DQ/DQS : PASS
1915 11:03:36.304586 RX DATLAT : PASS
1916 11:03:36.307878 RX DQ/DQS(Engine): PASS
1917 11:03:36.307993 TX OE : NO K
1918 11:03:36.310950 All Pass.
1919 11:03:36.311085
1920 11:03:36.311197 CH 1, Rank 0
1921 11:03:36.314659 SW Impedance : PASS
1922 11:03:36.314761 DUTY Scan : NO K
1923 11:03:36.317715 ZQ Calibration : PASS
1924 11:03:36.321172 Jitter Meter : NO K
1925 11:03:36.321291 CBT Training : PASS
1926 11:03:36.324740 Write leveling : PASS
1927 11:03:36.324851 RX DQS gating : PASS
1928 11:03:36.327833 RX DQ/DQS(RDDQC) : PASS
1929 11:03:36.331245 TX DQ/DQS : PASS
1930 11:03:36.331355 RX DATLAT : PASS
1931 11:03:36.334668 RX DQ/DQS(Engine): PASS
1932 11:03:36.338009 TX OE : NO K
1933 11:03:36.338091 All Pass.
1934 11:03:36.338150
1935 11:03:36.338203 CH 1, Rank 1
1936 11:03:36.341159 SW Impedance : PASS
1937 11:03:36.345080 DUTY Scan : NO K
1938 11:03:36.345168 ZQ Calibration : PASS
1939 11:03:36.348065 Jitter Meter : NO K
1940 11:03:36.351348 CBT Training : PASS
1941 11:03:36.351428 Write leveling : PASS
1942 11:03:36.355137 RX DQS gating : PASS
1943 11:03:36.358018 RX DQ/DQS(RDDQC) : PASS
1944 11:03:36.358119 TX DQ/DQS : PASS
1945 11:03:36.361383 RX DATLAT : PASS
1946 11:03:36.361461 RX DQ/DQS(Engine): PASS
1947 11:03:36.364606 TX OE : NO K
1948 11:03:36.364681 All Pass.
1949 11:03:36.364754
1950 11:03:36.368153 DramC Write-DBI off
1951 11:03:36.371445 PER_BANK_REFRESH: Hybrid Mode
1952 11:03:36.371519 TX_TRACKING: ON
1953 11:03:36.374703 [GetDramInforAfterCalByMRR] Vendor 6.
1954 11:03:36.378043 [GetDramInforAfterCalByMRR] Revision 606.
1955 11:03:36.381314 [GetDramInforAfterCalByMRR] Revision 2 0.
1956 11:03:36.385045 MR0 0x3939
1957 11:03:36.385122 MR8 0x1111
1958 11:03:36.387793 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1959 11:03:36.387858
1960 11:03:36.391556 MR0 0x3939
1961 11:03:36.391629 MR8 0x1111
1962 11:03:36.394656 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1963 11:03:36.394722
1964 11:03:36.405018 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1965 11:03:36.408238 [FAST_K] Save calibration result to emmc
1966 11:03:36.411426 [FAST_K] Save calibration result to emmc
1967 11:03:36.414911 dram_init: config_dvfs: 1
1968 11:03:36.418142 dramc_set_vcore_voltage set vcore to 662500
1969 11:03:36.418256 Read voltage for 1200, 2
1970 11:03:36.421414 Vio18 = 0
1971 11:03:36.421492 Vcore = 662500
1972 11:03:36.421556 Vdram = 0
1973 11:03:36.424677 Vddq = 0
1974 11:03:36.424785 Vmddr = 0
1975 11:03:36.428099 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1976 11:03:36.434892 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1977 11:03:36.437967 MEM_TYPE=3, freq_sel=15
1978 11:03:36.441943 sv_algorithm_assistance_LP4_1600
1979 11:03:36.444736 ============ PULL DRAM RESETB DOWN ============
1980 11:03:36.447926 ========== PULL DRAM RESETB DOWN end =========
1981 11:03:36.451686 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1982 11:03:36.454901 ===================================
1983 11:03:36.458149 LPDDR4 DRAM CONFIGURATION
1984 11:03:36.461373 ===================================
1985 11:03:36.465107 EX_ROW_EN[0] = 0x0
1986 11:03:36.465207 EX_ROW_EN[1] = 0x0
1987 11:03:36.468152 LP4Y_EN = 0x0
1988 11:03:36.468246 WORK_FSP = 0x0
1989 11:03:36.472043 WL = 0x4
1990 11:03:36.472122 RL = 0x4
1991 11:03:36.474849 BL = 0x2
1992 11:03:36.474947 RPST = 0x0
1993 11:03:36.478117 RD_PRE = 0x0
1994 11:03:36.478192 WR_PRE = 0x1
1995 11:03:36.481895 WR_PST = 0x0
1996 11:03:36.481969 DBI_WR = 0x0
1997 11:03:36.484709 DBI_RD = 0x0
1998 11:03:36.484783 OTF = 0x1
1999 11:03:36.488136 ===================================
2000 11:03:36.491592 ===================================
2001 11:03:36.495019 ANA top config
2002 11:03:36.498283 ===================================
2003 11:03:36.501935 DLL_ASYNC_EN = 0
2004 11:03:36.502024 ALL_SLAVE_EN = 0
2005 11:03:36.505182 NEW_RANK_MODE = 1
2006 11:03:36.508165 DLL_IDLE_MODE = 1
2007 11:03:36.511693 LP45_APHY_COMB_EN = 1
2008 11:03:36.514924 TX_ODT_DIS = 1
2009 11:03:36.514998 NEW_8X_MODE = 1
2010 11:03:36.518152 ===================================
2011 11:03:36.521587 ===================================
2012 11:03:36.525382 data_rate = 2400
2013 11:03:36.528080 CKR = 1
2014 11:03:36.531254 DQ_P2S_RATIO = 8
2015 11:03:36.535367 ===================================
2016 11:03:36.538119 CA_P2S_RATIO = 8
2017 11:03:36.538212 DQ_CA_OPEN = 0
2018 11:03:36.541660 DQ_SEMI_OPEN = 0
2019 11:03:36.544850 CA_SEMI_OPEN = 0
2020 11:03:36.548164 CA_FULL_RATE = 0
2021 11:03:36.551496 DQ_CKDIV4_EN = 0
2022 11:03:36.555047 CA_CKDIV4_EN = 0
2023 11:03:36.555109 CA_PREDIV_EN = 0
2024 11:03:36.558917 PH8_DLY = 17
2025 11:03:36.561452 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2026 11:03:36.565343 DQ_AAMCK_DIV = 4
2027 11:03:36.568225 CA_AAMCK_DIV = 4
2028 11:03:36.571705 CA_ADMCK_DIV = 4
2029 11:03:36.571766 DQ_TRACK_CA_EN = 0
2030 11:03:36.574810 CA_PICK = 1200
2031 11:03:36.578470 CA_MCKIO = 1200
2032 11:03:36.581532 MCKIO_SEMI = 0
2033 11:03:36.585089 PLL_FREQ = 2366
2034 11:03:36.588752 DQ_UI_PI_RATIO = 32
2035 11:03:36.591968 CA_UI_PI_RATIO = 0
2036 11:03:36.595169 ===================================
2037 11:03:36.598617 ===================================
2038 11:03:36.598679 memory_type:LPDDR4
2039 11:03:36.601845 GP_NUM : 10
2040 11:03:36.601908 SRAM_EN : 1
2041 11:03:36.605142 MD32_EN : 0
2042 11:03:36.608611 ===================================
2043 11:03:36.611702 [ANA_INIT] >>>>>>>>>>>>>>
2044 11:03:36.615022 <<<<<< [CONFIGURE PHASE]: ANA_TX
2045 11:03:36.618422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2046 11:03:36.621899 ===================================
2047 11:03:36.621969 data_rate = 2400,PCW = 0X5b00
2048 11:03:36.625058 ===================================
2049 11:03:36.631946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2050 11:03:36.635250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2051 11:03:36.641636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2052 11:03:36.645212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2053 11:03:36.648754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2054 11:03:36.652284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2055 11:03:36.655099 [ANA_INIT] flow start
2056 11:03:36.658178 [ANA_INIT] PLL >>>>>>>>
2057 11:03:36.658253 [ANA_INIT] PLL <<<<<<<<
2058 11:03:36.662106 [ANA_INIT] MIDPI >>>>>>>>
2059 11:03:36.664949 [ANA_INIT] MIDPI <<<<<<<<
2060 11:03:36.665025 [ANA_INIT] DLL >>>>>>>>
2061 11:03:36.668477 [ANA_INIT] DLL <<<<<<<<
2062 11:03:36.671794 [ANA_INIT] flow end
2063 11:03:36.674996 ============ LP4 DIFF to SE enter ============
2064 11:03:36.678548 ============ LP4 DIFF to SE exit ============
2065 11:03:36.681896 [ANA_INIT] <<<<<<<<<<<<<
2066 11:03:36.685143 [Flow] Enable top DCM control >>>>>
2067 11:03:36.688240 [Flow] Enable top DCM control <<<<<
2068 11:03:36.691697 Enable DLL master slave shuffle
2069 11:03:36.695068 ==============================================================
2070 11:03:36.698432 Gating Mode config
2071 11:03:36.701846 ==============================================================
2072 11:03:36.705305 Config description:
2073 11:03:36.715184 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2074 11:03:36.721859 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2075 11:03:36.724929 SELPH_MODE 0: By rank 1: By Phase
2076 11:03:36.731689 ==============================================================
2077 11:03:36.735120 GAT_TRACK_EN = 1
2078 11:03:36.738615 RX_GATING_MODE = 2
2079 11:03:36.741438 RX_GATING_TRACK_MODE = 2
2080 11:03:36.745005 SELPH_MODE = 1
2081 11:03:36.748499 PICG_EARLY_EN = 1
2082 11:03:36.748574 VALID_LAT_VALUE = 1
2083 11:03:36.755062 ==============================================================
2084 11:03:36.758203 Enter into Gating configuration >>>>
2085 11:03:36.761573 Exit from Gating configuration <<<<
2086 11:03:36.764942 Enter into DVFS_PRE_config >>>>>
2087 11:03:36.775154 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2088 11:03:36.778308 Exit from DVFS_PRE_config <<<<<
2089 11:03:36.781602 Enter into PICG configuration >>>>
2090 11:03:36.784593 Exit from PICG configuration <<<<
2091 11:03:36.788237 [RX_INPUT] configuration >>>>>
2092 11:03:36.791186 [RX_INPUT] configuration <<<<<
2093 11:03:36.798425 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2094 11:03:36.801130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2095 11:03:36.808035 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2096 11:03:36.814675 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2097 11:03:36.821129 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2098 11:03:36.827892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2099 11:03:36.831438 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2100 11:03:36.834527 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2101 11:03:36.838012 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2102 11:03:36.844881 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2103 11:03:36.847720 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2104 11:03:36.851514 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2105 11:03:36.854726 ===================================
2106 11:03:36.857800 LPDDR4 DRAM CONFIGURATION
2107 11:03:36.861145 ===================================
2108 11:03:36.861283 EX_ROW_EN[0] = 0x0
2109 11:03:36.864749 EX_ROW_EN[1] = 0x0
2110 11:03:36.864824 LP4Y_EN = 0x0
2111 11:03:36.868200 WORK_FSP = 0x0
2112 11:03:36.868274 WL = 0x4
2113 11:03:36.871777 RL = 0x4
2114 11:03:36.871853 BL = 0x2
2115 11:03:36.874381 RPST = 0x0
2116 11:03:36.878039 RD_PRE = 0x0
2117 11:03:36.878114 WR_PRE = 0x1
2118 11:03:36.881555 WR_PST = 0x0
2119 11:03:36.881629 DBI_WR = 0x0
2120 11:03:36.884802 DBI_RD = 0x0
2121 11:03:36.884877 OTF = 0x1
2122 11:03:36.887824 ===================================
2123 11:03:36.890989 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2124 11:03:36.894365 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2125 11:03:36.901148 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 11:03:36.904568 ===================================
2127 11:03:36.907785 LPDDR4 DRAM CONFIGURATION
2128 11:03:36.911304 ===================================
2129 11:03:36.911380 EX_ROW_EN[0] = 0x10
2130 11:03:36.914725 EX_ROW_EN[1] = 0x0
2131 11:03:36.914800 LP4Y_EN = 0x0
2132 11:03:36.918276 WORK_FSP = 0x0
2133 11:03:36.918351 WL = 0x4
2134 11:03:36.921071 RL = 0x4
2135 11:03:36.921146 BL = 0x2
2136 11:03:36.925057 RPST = 0x0
2137 11:03:36.925156 RD_PRE = 0x0
2138 11:03:36.927682 WR_PRE = 0x1
2139 11:03:36.927756 WR_PST = 0x0
2140 11:03:36.931521 DBI_WR = 0x0
2141 11:03:36.931596 DBI_RD = 0x0
2142 11:03:36.934696 OTF = 0x1
2143 11:03:36.937844 ===================================
2144 11:03:36.944445 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2145 11:03:36.944522 ==
2146 11:03:36.947686 Dram Type= 6, Freq= 0, CH_0, rank 0
2147 11:03:36.951386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2148 11:03:36.951463 ==
2149 11:03:36.954807 [Duty_Offset_Calibration]
2150 11:03:36.954882 B0:0 B1:2 CA:1
2151 11:03:36.954941
2152 11:03:36.957780 [DutyScan_Calibration_Flow] k_type=0
2153 11:03:36.968238
2154 11:03:36.968339 ==CLK 0==
2155 11:03:36.971758 Final CLK duty delay cell = 0
2156 11:03:36.975329 [0] MAX Duty = 5093%(X100), DQS PI = 12
2157 11:03:36.978466 [0] MIN Duty = 4938%(X100), DQS PI = 54
2158 11:03:36.978542 [0] AVG Duty = 5015%(X100)
2159 11:03:36.981992
2160 11:03:36.982066 CH0 CLK Duty spec in!! Max-Min= 155%
2161 11:03:36.988576 [DutyScan_Calibration_Flow] ====Done====
2162 11:03:36.988709
2163 11:03:36.991938 [DutyScan_Calibration_Flow] k_type=1
2164 11:03:37.008105
2165 11:03:37.008189 ==DQS 0 ==
2166 11:03:37.011140 Final DQS duty delay cell = 0
2167 11:03:37.014782 [0] MAX Duty = 5125%(X100), DQS PI = 32
2168 11:03:37.017796 [0] MIN Duty = 5031%(X100), DQS PI = 6
2169 11:03:37.017873 [0] AVG Duty = 5078%(X100)
2170 11:03:37.021201
2171 11:03:37.021320 ==DQS 1 ==
2172 11:03:37.024644 Final DQS duty delay cell = 0
2173 11:03:37.027867 [0] MAX Duty = 5062%(X100), DQS PI = 58
2174 11:03:37.031063 [0] MIN Duty = 4906%(X100), DQS PI = 14
2175 11:03:37.031139 [0] AVG Duty = 4984%(X100)
2176 11:03:37.034664
2177 11:03:37.037706 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2178 11:03:37.037781
2179 11:03:37.040960 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2180 11:03:37.044275 [DutyScan_Calibration_Flow] ====Done====
2181 11:03:37.044374
2182 11:03:37.047715 [DutyScan_Calibration_Flow] k_type=3
2183 11:03:37.064852
2184 11:03:37.064936 ==DQM 0 ==
2185 11:03:37.068065 Final DQM duty delay cell = 0
2186 11:03:37.071551 [0] MAX Duty = 5156%(X100), DQS PI = 22
2187 11:03:37.075070 [0] MIN Duty = 4969%(X100), DQS PI = 40
2188 11:03:37.078192 [0] AVG Duty = 5062%(X100)
2189 11:03:37.078267
2190 11:03:37.078326 ==DQM 1 ==
2191 11:03:37.081582 Final DQM duty delay cell = 4
2192 11:03:37.085039 [4] MAX Duty = 5187%(X100), DQS PI = 54
2193 11:03:37.088303 [4] MIN Duty = 5000%(X100), DQS PI = 18
2194 11:03:37.091616 [4] AVG Duty = 5093%(X100)
2195 11:03:37.091688
2196 11:03:37.095141 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2197 11:03:37.095211
2198 11:03:37.098315 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2199 11:03:37.101403 [DutyScan_Calibration_Flow] ====Done====
2200 11:03:37.101478
2201 11:03:37.104680 [DutyScan_Calibration_Flow] k_type=2
2202 11:03:37.120184
2203 11:03:37.120284 ==DQ 0 ==
2204 11:03:37.123428 Final DQ duty delay cell = -4
2205 11:03:37.126719 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2206 11:03:37.130020 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2207 11:03:37.133526 [-4] AVG Duty = 4937%(X100)
2208 11:03:37.133616
2209 11:03:37.133673 ==DQ 1 ==
2210 11:03:37.136833 Final DQ duty delay cell = -4
2211 11:03:37.140369 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2212 11:03:37.143746 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2213 11:03:37.146547 [-4] AVG Duty = 4984%(X100)
2214 11:03:37.146621
2215 11:03:37.149809 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2216 11:03:37.149883
2217 11:03:37.153415 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2218 11:03:37.156490 [DutyScan_Calibration_Flow] ====Done====
2219 11:03:37.156564 ==
2220 11:03:37.159931 Dram Type= 6, Freq= 0, CH_1, rank 0
2221 11:03:37.163492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2222 11:03:37.163569 ==
2223 11:03:37.166718 [Duty_Offset_Calibration]
2224 11:03:37.166924 B0:0 B1:5 CA:-5
2225 11:03:37.167062
2226 11:03:37.169786 [DutyScan_Calibration_Flow] k_type=0
2227 11:03:37.180655
2228 11:03:37.180771 ==CLK 0==
2229 11:03:37.184126 Final CLK duty delay cell = 0
2230 11:03:37.186892 [0] MAX Duty = 5094%(X100), DQS PI = 24
2231 11:03:37.190433 [0] MIN Duty = 4844%(X100), DQS PI = 46
2232 11:03:37.190529 [0] AVG Duty = 4969%(X100)
2233 11:03:37.193489
2234 11:03:37.197105 CH1 CLK Duty spec in!! Max-Min= 250%
2235 11:03:37.200294 [DutyScan_Calibration_Flow] ====Done====
2236 11:03:37.200370
2237 11:03:37.204157 [DutyScan_Calibration_Flow] k_type=1
2238 11:03:37.219029
2239 11:03:37.219135 ==DQS 0 ==
2240 11:03:37.222779 Final DQS duty delay cell = 0
2241 11:03:37.225653 [0] MAX Duty = 5125%(X100), DQS PI = 14
2242 11:03:37.229116 [0] MIN Duty = 4875%(X100), DQS PI = 40
2243 11:03:37.231948 [0] AVG Duty = 5000%(X100)
2244 11:03:37.232039
2245 11:03:37.232125 ==DQS 1 ==
2246 11:03:37.236027 Final DQS duty delay cell = -4
2247 11:03:37.238796 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2248 11:03:37.242231 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2249 11:03:37.245501 [-4] AVG Duty = 4953%(X100)
2250 11:03:37.245581
2251 11:03:37.248614 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2252 11:03:37.248703
2253 11:03:37.251916 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2254 11:03:37.256357 [DutyScan_Calibration_Flow] ====Done====
2255 11:03:37.256430
2256 11:03:37.258726 [DutyScan_Calibration_Flow] k_type=3
2257 11:03:37.274257
2258 11:03:37.274333 ==DQM 0 ==
2259 11:03:37.277574 Final DQM duty delay cell = -4
2260 11:03:37.280970 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2261 11:03:37.284221 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2262 11:03:37.287501 [-4] AVG Duty = 4953%(X100)
2263 11:03:37.287575
2264 11:03:37.287633 ==DQM 1 ==
2265 11:03:37.290696 Final DQM duty delay cell = -4
2266 11:03:37.294148 [-4] MAX Duty = 5094%(X100), DQS PI = 22
2267 11:03:37.297293 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2268 11:03:37.300632 [-4] AVG Duty = 5000%(X100)
2269 11:03:37.300706
2270 11:03:37.304229 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2271 11:03:37.304303
2272 11:03:37.307461 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2273 11:03:37.310869 [DutyScan_Calibration_Flow] ====Done====
2274 11:03:37.310958
2275 11:03:37.313761 [DutyScan_Calibration_Flow] k_type=2
2276 11:03:37.331591
2277 11:03:37.331669 ==DQ 0 ==
2278 11:03:37.334910 Final DQ duty delay cell = 0
2279 11:03:37.338099 [0] MAX Duty = 5062%(X100), DQS PI = 0
2280 11:03:37.341670 [0] MIN Duty = 4938%(X100), DQS PI = 44
2281 11:03:37.341745 [0] AVG Duty = 5000%(X100)
2282 11:03:37.341803
2283 11:03:37.344468 ==DQ 1 ==
2284 11:03:37.348123 Final DQ duty delay cell = 0
2285 11:03:37.351254 [0] MAX Duty = 5000%(X100), DQS PI = 8
2286 11:03:37.354863 [0] MIN Duty = 4875%(X100), DQS PI = 62
2287 11:03:37.354939 [0] AVG Duty = 4937%(X100)
2288 11:03:37.354997
2289 11:03:37.358066 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2290 11:03:37.358141
2291 11:03:37.361414 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2292 11:03:37.367849 [DutyScan_Calibration_Flow] ====Done====
2293 11:03:37.371276 nWR fixed to 30
2294 11:03:37.371365 [ModeRegInit_LP4] CH0 RK0
2295 11:03:37.374661 [ModeRegInit_LP4] CH0 RK1
2296 11:03:37.378130 [ModeRegInit_LP4] CH1 RK0
2297 11:03:37.378206 [ModeRegInit_LP4] CH1 RK1
2298 11:03:37.381094 match AC timing 6
2299 11:03:37.384540 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2300 11:03:37.387898 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2301 11:03:37.394654 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2302 11:03:37.397726 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2303 11:03:37.404501 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2304 11:03:37.404605 ==
2305 11:03:37.408041 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 11:03:37.411144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2307 11:03:37.411237 ==
2308 11:03:37.418034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2309 11:03:37.421329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2310 11:03:37.431073 [CA 0] Center 39 (9~70) winsize 62
2311 11:03:37.434308 [CA 1] Center 39 (8~70) winsize 63
2312 11:03:37.438241 [CA 2] Center 36 (5~67) winsize 63
2313 11:03:37.440950 [CA 3] Center 35 (5~66) winsize 62
2314 11:03:37.444713 [CA 4] Center 34 (3~65) winsize 63
2315 11:03:37.447753 [CA 5] Center 33 (3~64) winsize 62
2316 11:03:37.447849
2317 11:03:37.451153 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2318 11:03:37.451242
2319 11:03:37.454373 [CATrainingPosCal] consider 1 rank data
2320 11:03:37.457961 u2DelayCellTimex100 = 270/100 ps
2321 11:03:37.461187 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2322 11:03:37.464955 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2323 11:03:37.471269 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2324 11:03:37.474438 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2325 11:03:37.477537 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2326 11:03:37.481166 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2327 11:03:37.481274
2328 11:03:37.484316 CA PerBit enable=1, Macro0, CA PI delay=33
2329 11:03:37.484388
2330 11:03:37.487686 [CBTSetCACLKResult] CA Dly = 33
2331 11:03:37.487758 CS Dly: 7 (0~38)
2332 11:03:37.491044 ==
2333 11:03:37.491116 Dram Type= 6, Freq= 0, CH_0, rank 1
2334 11:03:37.497822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2335 11:03:37.497895 ==
2336 11:03:37.501442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2337 11:03:37.507595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2338 11:03:37.516754 [CA 0] Center 39 (8~70) winsize 63
2339 11:03:37.520054 [CA 1] Center 39 (8~70) winsize 63
2340 11:03:37.522989 [CA 2] Center 35 (5~66) winsize 62
2341 11:03:37.526307 [CA 3] Center 35 (4~66) winsize 63
2342 11:03:37.530008 [CA 4] Center 33 (3~64) winsize 62
2343 11:03:37.533572 [CA 5] Center 33 (3~64) winsize 62
2344 11:03:37.533645
2345 11:03:37.536475 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2346 11:03:37.536548
2347 11:03:37.539791 [CATrainingPosCal] consider 2 rank data
2348 11:03:37.543263 u2DelayCellTimex100 = 270/100 ps
2349 11:03:37.546528 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2350 11:03:37.549723 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2351 11:03:37.556752 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2352 11:03:37.560203 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2353 11:03:37.563650 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2354 11:03:37.566602 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2355 11:03:37.566676
2356 11:03:37.570025 CA PerBit enable=1, Macro0, CA PI delay=33
2357 11:03:37.570098
2358 11:03:37.573089 [CBTSetCACLKResult] CA Dly = 33
2359 11:03:37.573186 CS Dly: 7 (0~39)
2360 11:03:37.573291
2361 11:03:37.576671 ----->DramcWriteLeveling(PI) begin...
2362 11:03:37.580158 ==
2363 11:03:37.580232 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 11:03:37.586484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2365 11:03:37.586558 ==
2366 11:03:37.590169 Write leveling (Byte 0): 27 => 27
2367 11:03:37.593406 Write leveling (Byte 1): 27 => 27
2368 11:03:37.593480 DramcWriteLeveling(PI) end<-----
2369 11:03:37.596494
2370 11:03:37.596566 ==
2371 11:03:37.600240 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 11:03:37.603050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2373 11:03:37.603124 ==
2374 11:03:37.606613 [Gating] SW mode calibration
2375 11:03:37.613446 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2376 11:03:37.616505 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2377 11:03:37.623210 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2378 11:03:37.626445 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 11:03:37.629724 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 11:03:37.636608 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2381 11:03:37.640408 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2382 11:03:37.643671 0 11 20 | B1->B0 | 2d2d 2929 | 1 0 | (1 0) (0 0)
2383 11:03:37.649878 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 11:03:37.653147 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 11:03:37.656420 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 11:03:37.663500 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 11:03:37.666749 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 11:03:37.670225 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 11:03:37.676675 0 12 16 | B1->B0 | 2424 2b2a | 0 1 | (0 0) (0 0)
2390 11:03:37.680418 0 12 20 | B1->B0 | 3d3d 4343 | 0 0 | (1 1) (0 0)
2391 11:03:37.683465 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 11:03:37.689773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 11:03:37.693114 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 11:03:37.696621 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 11:03:37.699726 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 11:03:37.706672 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 11:03:37.709961 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2398 11:03:37.713675 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2399 11:03:37.720166 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2400 11:03:37.723980 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 11:03:37.726779 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 11:03:37.733292 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 11:03:37.736742 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 11:03:37.740117 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 11:03:37.746727 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 11:03:37.750277 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 11:03:37.753543 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 11:03:37.760387 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 11:03:37.763673 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 11:03:37.766889 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 11:03:37.770330 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 11:03:37.776922 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 11:03:37.780231 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 11:03:37.783587 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2415 11:03:37.790019 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2416 11:03:37.793423 Total UI for P1: 0, mck2ui 16
2417 11:03:37.797481 best dqsien dly found for B0: ( 0, 15, 20)
2418 11:03:37.797555 Total UI for P1: 0, mck2ui 16
2419 11:03:37.803862 best dqsien dly found for B1: ( 0, 15, 20)
2420 11:03:37.806811 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2421 11:03:37.810728 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2422 11:03:37.810801
2423 11:03:37.813562 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2424 11:03:37.816885 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2425 11:03:37.820366 [Gating] SW calibration Done
2426 11:03:37.820441 ==
2427 11:03:37.823795 Dram Type= 6, Freq= 0, CH_0, rank 0
2428 11:03:37.827342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2429 11:03:37.827417 ==
2430 11:03:37.831230 RX Vref Scan: 0
2431 11:03:37.831304
2432 11:03:37.831361 RX Vref 0 -> 0, step: 1
2433 11:03:37.831415
2434 11:03:37.834544 RX Delay -40 -> 252, step: 8
2435 11:03:37.837091 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2436 11:03:37.843889 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2437 11:03:37.847102 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2438 11:03:37.850077 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2439 11:03:37.853779 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2440 11:03:37.856916 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2441 11:03:37.863933 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2442 11:03:37.866892 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2443 11:03:37.870120 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2444 11:03:37.873871 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2445 11:03:37.876793 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2446 11:03:37.883735 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2447 11:03:37.886767 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2448 11:03:37.890344 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2449 11:03:37.893412 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2450 11:03:37.896981 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2451 11:03:37.900044 ==
2452 11:03:37.900142 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 11:03:37.907267 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2454 11:03:37.907342 ==
2455 11:03:37.907400 DQS Delay:
2456 11:03:37.910515 DQS0 = 0, DQS1 = 0
2457 11:03:37.910588 DQM Delay:
2458 11:03:37.913662 DQM0 = 115, DQM1 = 105
2459 11:03:37.913736 DQ Delay:
2460 11:03:37.916919 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2461 11:03:37.920340 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2462 11:03:37.923459 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2463 11:03:37.927325 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =111
2464 11:03:37.927399
2465 11:03:37.927456
2466 11:03:37.927508 ==
2467 11:03:37.930680 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 11:03:37.934147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2469 11:03:37.937142 ==
2470 11:03:37.937263
2471 11:03:37.937336
2472 11:03:37.937389 TX Vref Scan disable
2473 11:03:37.940146 == TX Byte 0 ==
2474 11:03:37.943597 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2475 11:03:37.947114 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2476 11:03:37.950253 == TX Byte 1 ==
2477 11:03:37.954236 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2478 11:03:37.957063 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2479 11:03:37.957160 ==
2480 11:03:37.960830 Dram Type= 6, Freq= 0, CH_0, rank 0
2481 11:03:37.967711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2482 11:03:37.967787 ==
2483 11:03:37.977813 TX Vref=22, minBit 10, minWin=25, winSum=417
2484 11:03:37.981162 TX Vref=24, minBit 8, minWin=25, winSum=424
2485 11:03:37.984674 TX Vref=26, minBit 8, minWin=26, winSum=432
2486 11:03:37.988154 TX Vref=28, minBit 8, minWin=26, winSum=432
2487 11:03:37.991307 TX Vref=30, minBit 10, minWin=26, winSum=436
2488 11:03:37.997651 TX Vref=32, minBit 10, minWin=26, winSum=436
2489 11:03:38.001130 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 30
2490 11:03:38.001251
2491 11:03:38.004408 Final TX Range 1 Vref 30
2492 11:03:38.004498
2493 11:03:38.004569 ==
2494 11:03:38.007411 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 11:03:38.011034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2496 11:03:38.014352 ==
2497 11:03:38.014425
2498 11:03:38.014482
2499 11:03:38.014534 TX Vref Scan disable
2500 11:03:38.017690 == TX Byte 0 ==
2501 11:03:38.021128 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2502 11:03:38.024368 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2503 11:03:38.027483 == TX Byte 1 ==
2504 11:03:38.031182 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2505 11:03:38.034704 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2506 11:03:38.038084
2507 11:03:38.038158 [DATLAT]
2508 11:03:38.038218 Freq=1200, CH0 RK0
2509 11:03:38.038271
2510 11:03:38.041024 DATLAT Default: 0xd
2511 11:03:38.041098 0, 0xFFFF, sum = 0
2512 11:03:38.044260 1, 0xFFFF, sum = 0
2513 11:03:38.044335 2, 0xFFFF, sum = 0
2514 11:03:38.047805 3, 0xFFFF, sum = 0
2515 11:03:38.047880 4, 0xFFFF, sum = 0
2516 11:03:38.051243 5, 0xFFFF, sum = 0
2517 11:03:38.054414 6, 0xFFFF, sum = 0
2518 11:03:38.054489 7, 0xFFFF, sum = 0
2519 11:03:38.057584 8, 0xFFFF, sum = 0
2520 11:03:38.057659 9, 0xFFFF, sum = 0
2521 11:03:38.060791 10, 0xFFFF, sum = 0
2522 11:03:38.060869 11, 0x0, sum = 1
2523 11:03:38.064560 12, 0x0, sum = 2
2524 11:03:38.064636 13, 0x0, sum = 3
2525 11:03:38.064693 14, 0x0, sum = 4
2526 11:03:38.068193 best_step = 12
2527 11:03:38.068267
2528 11:03:38.068323 ==
2529 11:03:38.070765 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 11:03:38.074100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2531 11:03:38.074174 ==
2532 11:03:38.077551 RX Vref Scan: 1
2533 11:03:38.077624
2534 11:03:38.081189 Set Vref Range= 32 -> 127
2535 11:03:38.081310
2536 11:03:38.081368 RX Vref 32 -> 127, step: 1
2537 11:03:38.081421
2538 11:03:38.084389 RX Delay -21 -> 252, step: 4
2539 11:03:38.084463
2540 11:03:38.087665 Set Vref, RX VrefLevel [Byte0]: 32
2541 11:03:38.091011 [Byte1]: 32
2542 11:03:38.094453
2543 11:03:38.094527 Set Vref, RX VrefLevel [Byte0]: 33
2544 11:03:38.097753 [Byte1]: 33
2545 11:03:38.102307
2546 11:03:38.102383 Set Vref, RX VrefLevel [Byte0]: 34
2547 11:03:38.105613 [Byte1]: 34
2548 11:03:38.110391
2549 11:03:38.110464 Set Vref, RX VrefLevel [Byte0]: 35
2550 11:03:38.113665 [Byte1]: 35
2551 11:03:38.118035
2552 11:03:38.118133 Set Vref, RX VrefLevel [Byte0]: 36
2553 11:03:38.121469 [Byte1]: 36
2554 11:03:38.126059
2555 11:03:38.126132 Set Vref, RX VrefLevel [Byte0]: 37
2556 11:03:38.129545 [Byte1]: 37
2557 11:03:38.133782
2558 11:03:38.133858 Set Vref, RX VrefLevel [Byte0]: 38
2559 11:03:38.137532 [Byte1]: 38
2560 11:03:38.142176
2561 11:03:38.142250 Set Vref, RX VrefLevel [Byte0]: 39
2562 11:03:38.145356 [Byte1]: 39
2563 11:03:38.150137
2564 11:03:38.150210 Set Vref, RX VrefLevel [Byte0]: 40
2565 11:03:38.153622 [Byte1]: 40
2566 11:03:38.157834
2567 11:03:38.157907 Set Vref, RX VrefLevel [Byte0]: 41
2568 11:03:38.161128 [Byte1]: 41
2569 11:03:38.165732
2570 11:03:38.165805 Set Vref, RX VrefLevel [Byte0]: 42
2571 11:03:38.169437 [Byte1]: 42
2572 11:03:38.174007
2573 11:03:38.174080 Set Vref, RX VrefLevel [Byte0]: 43
2574 11:03:38.177201 [Byte1]: 43
2575 11:03:38.181438
2576 11:03:38.181512 Set Vref, RX VrefLevel [Byte0]: 44
2577 11:03:38.206557 [Byte1]: 44
2578 11:03:38.206666
2579 11:03:38.206733 Set Vref, RX VrefLevel [Byte0]: 45
2580 11:03:38.206790 [Byte1]: 45
2581 11:03:38.206841
2582 11:03:38.206891 Set Vref, RX VrefLevel [Byte0]: 46
2583 11:03:38.206940 [Byte1]: 46
2584 11:03:38.206989
2585 11:03:38.207044 Set Vref, RX VrefLevel [Byte0]: 47
2586 11:03:38.208562 [Byte1]: 47
2587 11:03:38.213157
2588 11:03:38.213275 Set Vref, RX VrefLevel [Byte0]: 48
2589 11:03:38.216500 [Byte1]: 48
2590 11:03:38.221069
2591 11:03:38.221153 Set Vref, RX VrefLevel [Byte0]: 49
2592 11:03:38.225024 [Byte1]: 49
2593 11:03:38.229391
2594 11:03:38.229465 Set Vref, RX VrefLevel [Byte0]: 50
2595 11:03:38.232195 [Byte1]: 50
2596 11:03:38.236824
2597 11:03:38.236920 Set Vref, RX VrefLevel [Byte0]: 51
2598 11:03:38.240763 [Byte1]: 51
2599 11:03:38.244735
2600 11:03:38.244802 Set Vref, RX VrefLevel [Byte0]: 52
2601 11:03:38.248036 [Byte1]: 52
2602 11:03:38.252998
2603 11:03:38.253067 Set Vref, RX VrefLevel [Byte0]: 53
2604 11:03:38.256302 [Byte1]: 53
2605 11:03:38.260836
2606 11:03:38.260913 Set Vref, RX VrefLevel [Byte0]: 54
2607 11:03:38.263793 [Byte1]: 54
2608 11:03:38.268929
2609 11:03:38.269000 Set Vref, RX VrefLevel [Byte0]: 55
2610 11:03:38.271950 [Byte1]: 55
2611 11:03:38.277023
2612 11:03:38.277108 Set Vref, RX VrefLevel [Byte0]: 56
2613 11:03:38.280022 [Byte1]: 56
2614 11:03:38.284343
2615 11:03:38.284405 Set Vref, RX VrefLevel [Byte0]: 57
2616 11:03:38.287558 [Byte1]: 57
2617 11:03:38.292307
2618 11:03:38.292373 Set Vref, RX VrefLevel [Byte0]: 58
2619 11:03:38.295619 [Byte1]: 58
2620 11:03:38.300594
2621 11:03:38.300716 Set Vref, RX VrefLevel [Byte0]: 59
2622 11:03:38.303403 [Byte1]: 59
2623 11:03:38.308329
2624 11:03:38.308401 Set Vref, RX VrefLevel [Byte0]: 60
2625 11:03:38.311750 [Byte1]: 60
2626 11:03:38.316093
2627 11:03:38.316164 Set Vref, RX VrefLevel [Byte0]: 61
2628 11:03:38.319521 [Byte1]: 61
2629 11:03:38.323985
2630 11:03:38.324052 Set Vref, RX VrefLevel [Byte0]: 62
2631 11:03:38.327250 [Byte1]: 62
2632 11:03:38.331947
2633 11:03:38.332089 Set Vref, RX VrefLevel [Byte0]: 63
2634 11:03:38.335510 [Byte1]: 63
2635 11:03:38.339756
2636 11:03:38.339830 Set Vref, RX VrefLevel [Byte0]: 64
2637 11:03:38.343099 [Byte1]: 64
2638 11:03:38.347822
2639 11:03:38.347929 Final RX Vref Byte 0 = 50 to rank0
2640 11:03:38.351111 Final RX Vref Byte 1 = 52 to rank0
2641 11:03:38.354399 Final RX Vref Byte 0 = 50 to rank1
2642 11:03:38.358556 Final RX Vref Byte 1 = 52 to rank1==
2643 11:03:38.361356 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 11:03:38.367561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2645 11:03:38.367672 ==
2646 11:03:38.367758 DQS Delay:
2647 11:03:38.367848 DQS0 = 0, DQS1 = 0
2648 11:03:38.371263 DQM Delay:
2649 11:03:38.371382 DQM0 = 114, DQM1 = 106
2650 11:03:38.374352 DQ Delay:
2651 11:03:38.377699 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =110
2652 11:03:38.381112 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2653 11:03:38.384683 DQ8 =96, DQ9 =88, DQ10 =106, DQ11 =100
2654 11:03:38.387844 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =118
2655 11:03:38.387935
2656 11:03:38.388019
2657 11:03:38.394387 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2658 11:03:38.397731 CH0 RK0: MR19=404, MR18=A0A
2659 11:03:38.404302 CH0_RK0: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
2660 11:03:38.404412
2661 11:03:38.407587 ----->DramcWriteLeveling(PI) begin...
2662 11:03:38.407663 ==
2663 11:03:38.411435 Dram Type= 6, Freq= 0, CH_0, rank 1
2664 11:03:38.414358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2665 11:03:38.414434 ==
2666 11:03:38.417446 Write leveling (Byte 0): 29 => 29
2667 11:03:38.421150 Write leveling (Byte 1): 26 => 26
2668 11:03:38.424177 DramcWriteLeveling(PI) end<-----
2669 11:03:38.424254
2670 11:03:38.424313 ==
2671 11:03:38.427750 Dram Type= 6, Freq= 0, CH_0, rank 1
2672 11:03:38.434299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2673 11:03:38.434376 ==
2674 11:03:38.434436 [Gating] SW mode calibration
2675 11:03:38.444043 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2676 11:03:38.447483 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2677 11:03:38.454118 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2678 11:03:38.457393 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2679 11:03:38.461012 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2680 11:03:38.463900 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2681 11:03:38.470595 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 1)
2682 11:03:38.473846 0 11 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2683 11:03:38.477069 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2684 11:03:38.484042 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2685 11:03:38.487107 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2686 11:03:38.490460 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2687 11:03:38.497246 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 11:03:38.500706 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2689 11:03:38.504334 0 12 16 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2690 11:03:38.510758 0 12 20 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
2691 11:03:38.513809 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2692 11:03:38.517320 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2693 11:03:38.523642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2694 11:03:38.527085 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2695 11:03:38.530482 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 11:03:38.537166 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 11:03:38.540734 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 11:03:38.544068 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2699 11:03:38.550693 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2700 11:03:38.554068 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2701 11:03:38.557128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2702 11:03:38.560482 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2703 11:03:38.567203 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2704 11:03:38.570370 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 11:03:38.573739 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 11:03:38.580358 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 11:03:38.583920 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 11:03:38.587228 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 11:03:38.593897 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 11:03:38.596916 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 11:03:38.600595 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 11:03:38.607060 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 11:03:38.610706 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2714 11:03:38.613804 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2715 11:03:38.617059 Total UI for P1: 0, mck2ui 16
2716 11:03:38.620356 best dqsien dly found for B0: ( 0, 15, 16)
2717 11:03:38.627483 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2718 11:03:38.627573 Total UI for P1: 0, mck2ui 16
2719 11:03:38.633859 best dqsien dly found for B1: ( 0, 15, 18)
2720 11:03:38.637238 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2721 11:03:38.640830 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2722 11:03:38.640921
2723 11:03:38.643709 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2724 11:03:38.647233 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2725 11:03:38.650737 [Gating] SW calibration Done
2726 11:03:38.650847 ==
2727 11:03:38.654448 Dram Type= 6, Freq= 0, CH_0, rank 1
2728 11:03:38.657216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2729 11:03:38.657347 ==
2730 11:03:38.660523 RX Vref Scan: 0
2731 11:03:38.660599
2732 11:03:38.660689 RX Vref 0 -> 0, step: 1
2733 11:03:38.660778
2734 11:03:38.663962 RX Delay -40 -> 252, step: 8
2735 11:03:38.667279 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2736 11:03:38.673693 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2737 11:03:38.677467 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2738 11:03:38.680623 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2739 11:03:38.683763 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2740 11:03:38.687176 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2741 11:03:38.693956 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2742 11:03:38.697640 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2743 11:03:38.700541 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2744 11:03:38.704195 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2745 11:03:38.707547 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2746 11:03:38.710772 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2747 11:03:38.717148 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2748 11:03:38.720977 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2749 11:03:38.724237 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2750 11:03:38.727470 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2751 11:03:38.727595 ==
2752 11:03:38.730809 Dram Type= 6, Freq= 0, CH_0, rank 1
2753 11:03:38.737710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2754 11:03:38.737808 ==
2755 11:03:38.737891 DQS Delay:
2756 11:03:38.737970 DQS0 = 0, DQS1 = 0
2757 11:03:38.740807 DQM Delay:
2758 11:03:38.740913 DQM0 = 115, DQM1 = 104
2759 11:03:38.744017 DQ Delay:
2760 11:03:38.747479 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =111
2761 11:03:38.751140 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2762 11:03:38.754012 DQ8 =91, DQ9 =95, DQ10 =103, DQ11 =99
2763 11:03:38.757644 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2764 11:03:38.757752
2765 11:03:38.757818
2766 11:03:38.757873 ==
2767 11:03:38.760795 Dram Type= 6, Freq= 0, CH_0, rank 1
2768 11:03:38.764618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2769 11:03:38.764700 ==
2770 11:03:38.764760
2771 11:03:38.764815
2772 11:03:38.767822 TX Vref Scan disable
2773 11:03:38.770929 == TX Byte 0 ==
2774 11:03:38.774218 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2775 11:03:38.777734 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2776 11:03:38.781021 == TX Byte 1 ==
2777 11:03:38.784343 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2778 11:03:38.787492 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2779 11:03:38.787573 ==
2780 11:03:38.790956 Dram Type= 6, Freq= 0, CH_0, rank 1
2781 11:03:38.797430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2782 11:03:38.797538 ==
2783 11:03:38.807950 TX Vref=22, minBit 8, minWin=25, winSum=415
2784 11:03:38.811267 TX Vref=24, minBit 12, minWin=25, winSum=426
2785 11:03:38.814477 TX Vref=26, minBit 9, minWin=26, winSum=431
2786 11:03:38.818146 TX Vref=28, minBit 10, minWin=26, winSum=435
2787 11:03:38.821310 TX Vref=30, minBit 10, minWin=25, winSum=432
2788 11:03:38.827939 TX Vref=32, minBit 10, minWin=25, winSum=431
2789 11:03:38.831194 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2790 11:03:38.831305
2791 11:03:38.834688 Final TX Range 1 Vref 28
2792 11:03:38.834771
2793 11:03:38.834831 ==
2794 11:03:38.838099 Dram Type= 6, Freq= 0, CH_0, rank 1
2795 11:03:38.841556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2796 11:03:38.844526 ==
2797 11:03:38.844594
2798 11:03:38.844650
2799 11:03:38.844704 TX Vref Scan disable
2800 11:03:38.848554 == TX Byte 0 ==
2801 11:03:38.851295 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2802 11:03:38.855270 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2803 11:03:38.858369 == TX Byte 1 ==
2804 11:03:38.861507 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2805 11:03:38.868308 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2806 11:03:38.868412
2807 11:03:38.868499 [DATLAT]
2808 11:03:38.868581 Freq=1200, CH0 RK1
2809 11:03:38.868661
2810 11:03:38.871388 DATLAT Default: 0xc
2811 11:03:38.871504 0, 0xFFFF, sum = 0
2812 11:03:38.875050 1, 0xFFFF, sum = 0
2813 11:03:38.878385 2, 0xFFFF, sum = 0
2814 11:03:38.878489 3, 0xFFFF, sum = 0
2815 11:03:38.881198 4, 0xFFFF, sum = 0
2816 11:03:38.881281 5, 0xFFFF, sum = 0
2817 11:03:38.885035 6, 0xFFFF, sum = 0
2818 11:03:38.885136 7, 0xFFFF, sum = 0
2819 11:03:38.887864 8, 0xFFFF, sum = 0
2820 11:03:38.887991 9, 0xFFFF, sum = 0
2821 11:03:38.891381 10, 0xFFFF, sum = 0
2822 11:03:38.891458 11, 0x0, sum = 1
2823 11:03:38.894480 12, 0x0, sum = 2
2824 11:03:38.894582 13, 0x0, sum = 3
2825 11:03:38.897992 14, 0x0, sum = 4
2826 11:03:38.898069 best_step = 12
2827 11:03:38.898128
2828 11:03:38.898182 ==
2829 11:03:38.901486 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 11:03:38.904560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2831 11:03:38.904638 ==
2832 11:03:38.907895 RX Vref Scan: 0
2833 11:03:38.907994
2834 11:03:38.911152 RX Vref 0 -> 0, step: 1
2835 11:03:38.911227
2836 11:03:38.911287 RX Delay -21 -> 252, step: 4
2837 11:03:38.918629 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2838 11:03:38.922416 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2839 11:03:38.925165 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2840 11:03:38.928390 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2841 11:03:38.931983 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2842 11:03:38.938765 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2843 11:03:38.941873 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2844 11:03:38.945279 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2845 11:03:38.948354 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2846 11:03:38.951801 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2847 11:03:38.958528 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2848 11:03:38.962211 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2849 11:03:38.965270 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2850 11:03:38.968576 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2851 11:03:38.972039 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2852 11:03:38.978879 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
2853 11:03:38.978961 ==
2854 11:03:38.982052 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 11:03:38.985217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2856 11:03:38.985316 ==
2857 11:03:38.985376 DQS Delay:
2858 11:03:38.988649 DQS0 = 0, DQS1 = 0
2859 11:03:38.988730 DQM Delay:
2860 11:03:38.991829 DQM0 = 114, DQM1 = 106
2861 11:03:38.991905 DQ Delay:
2862 11:03:38.995356 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2863 11:03:38.998578 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2864 11:03:39.001986 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2865 11:03:39.005283 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2866 11:03:39.005366
2867 11:03:39.005426
2868 11:03:39.015490 [DQSOSCAuto] RK1, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2869 11:03:39.018469 CH0 RK1: MR19=404, MR18=1414
2870 11:03:39.021961 CH0_RK1: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
2871 11:03:39.025310 [RxdqsGatingPostProcess] freq 1200
2872 11:03:39.031968 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2873 11:03:39.035083 Pre-setting of DQS Precalculation
2874 11:03:39.038760 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2875 11:03:39.038855 ==
2876 11:03:39.041930 Dram Type= 6, Freq= 0, CH_1, rank 0
2877 11:03:39.048679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2878 11:03:39.048751 ==
2879 11:03:39.052183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2880 11:03:39.058934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2881 11:03:39.067436 [CA 0] Center 37 (7~68) winsize 62
2882 11:03:39.070436 [CA 1] Center 37 (7~68) winsize 62
2883 11:03:39.073901 [CA 2] Center 34 (4~65) winsize 62
2884 11:03:39.076976 [CA 3] Center 33 (3~64) winsize 62
2885 11:03:39.080556 [CA 4] Center 32 (2~63) winsize 62
2886 11:03:39.084067 [CA 5] Center 32 (2~63) winsize 62
2887 11:03:39.084195
2888 11:03:39.087217 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2889 11:03:39.087292
2890 11:03:39.090332 [CATrainingPosCal] consider 1 rank data
2891 11:03:39.093811 u2DelayCellTimex100 = 270/100 ps
2892 11:03:39.097056 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2893 11:03:39.100273 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2894 11:03:39.107496 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2895 11:03:39.110504 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2896 11:03:39.114004 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2897 11:03:39.117177 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2898 11:03:39.117277
2899 11:03:39.120463 CA PerBit enable=1, Macro0, CA PI delay=32
2900 11:03:39.120538
2901 11:03:39.123756 [CBTSetCACLKResult] CA Dly = 32
2902 11:03:39.123831 CS Dly: 5 (0~36)
2903 11:03:39.123889 ==
2904 11:03:39.127438 Dram Type= 6, Freq= 0, CH_1, rank 1
2905 11:03:39.133943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2906 11:03:39.134020 ==
2907 11:03:39.137204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2908 11:03:39.143547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2909 11:03:39.152458 [CA 0] Center 37 (7~68) winsize 62
2910 11:03:39.156064 [CA 1] Center 37 (7~68) winsize 62
2911 11:03:39.159147 [CA 2] Center 34 (3~65) winsize 63
2912 11:03:39.162335 [CA 3] Center 33 (3~64) winsize 62
2913 11:03:39.165719 [CA 4] Center 32 (2~63) winsize 62
2914 11:03:39.168945 [CA 5] Center 31 (1~62) winsize 62
2915 11:03:39.169020
2916 11:03:39.172610 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2917 11:03:39.172685
2918 11:03:39.176048 [CATrainingPosCal] consider 2 rank data
2919 11:03:39.179233 u2DelayCellTimex100 = 270/100 ps
2920 11:03:39.182721 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2921 11:03:39.185841 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2922 11:03:39.192571 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2923 11:03:39.195672 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2924 11:03:39.198874 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2925 11:03:39.202674 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2926 11:03:39.202748
2927 11:03:39.206089 CA PerBit enable=1, Macro0, CA PI delay=32
2928 11:03:39.206185
2929 11:03:39.209146 [CBTSetCACLKResult] CA Dly = 32
2930 11:03:39.209283 CS Dly: 6 (0~38)
2931 11:03:39.209431
2932 11:03:39.212412 ----->DramcWriteLeveling(PI) begin...
2933 11:03:39.216110 ==
2934 11:03:39.216183 Dram Type= 6, Freq= 0, CH_1, rank 0
2935 11:03:39.222522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2936 11:03:39.222597 ==
2937 11:03:39.226263 Write leveling (Byte 0): 20 => 20
2938 11:03:39.229157 Write leveling (Byte 1): 21 => 21
2939 11:03:39.232478 DramcWriteLeveling(PI) end<-----
2940 11:03:39.232579
2941 11:03:39.232664 ==
2942 11:03:39.235931 Dram Type= 6, Freq= 0, CH_1, rank 0
2943 11:03:39.239013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2944 11:03:39.239079 ==
2945 11:03:39.242845 [Gating] SW mode calibration
2946 11:03:39.249010 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2947 11:03:39.252599 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2948 11:03:39.259567 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 11:03:39.262627 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 11:03:39.265812 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2951 11:03:39.272478 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2952 11:03:39.276087 0 11 16 | B1->B0 | 3434 2525 | 0 0 | (0 1) (0 1)
2953 11:03:39.279075 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2954 11:03:39.285843 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 11:03:39.289128 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 11:03:39.292229 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 11:03:39.298769 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 11:03:39.302132 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 11:03:39.305815 0 12 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2960 11:03:39.312414 0 12 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2961 11:03:39.315534 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 11:03:39.318962 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 11:03:39.325779 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 11:03:39.329578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 11:03:39.332558 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 11:03:39.335852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:03:39.342370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 11:03:39.345972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2969 11:03:39.349360 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2970 11:03:39.356123 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 11:03:39.359905 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 11:03:39.362540 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 11:03:39.369646 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 11:03:39.372834 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 11:03:39.376280 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 11:03:39.382571 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:03:39.385928 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:03:39.389519 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:03:39.396119 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:03:39.399375 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:03:39.402839 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:03:39.409375 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:03:39.412430 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2984 11:03:39.415987 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2985 11:03:39.419564 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2986 11:03:39.422600 Total UI for P1: 0, mck2ui 16
2987 11:03:39.425676 best dqsien dly found for B0: ( 0, 15, 14)
2988 11:03:39.432480 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 11:03:39.435813 Total UI for P1: 0, mck2ui 16
2990 11:03:39.439560 best dqsien dly found for B1: ( 0, 15, 18)
2991 11:03:39.442376 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2992 11:03:39.446090 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2993 11:03:39.446166
2994 11:03:39.449206 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
2995 11:03:39.452741 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2996 11:03:39.456417 [Gating] SW calibration Done
2997 11:03:39.456491 ==
2998 11:03:39.459300 Dram Type= 6, Freq= 0, CH_1, rank 0
2999 11:03:39.462641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3000 11:03:39.462715 ==
3001 11:03:39.465986 RX Vref Scan: 0
3002 11:03:39.466060
3003 11:03:39.466118 RX Vref 0 -> 0, step: 1
3004 11:03:39.469940
3005 11:03:39.470013 RX Delay -40 -> 252, step: 8
3006 11:03:39.476499 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3007 11:03:39.479404 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3008 11:03:39.482936 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3009 11:03:39.485985 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3010 11:03:39.489625 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3011 11:03:39.492829 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3012 11:03:39.499562 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3013 11:03:39.502648 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3014 11:03:39.506356 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3015 11:03:39.509553 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3016 11:03:39.512836 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3017 11:03:39.519479 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3018 11:03:39.523043 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3019 11:03:39.525854 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3020 11:03:39.529120 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3021 11:03:39.532549 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3022 11:03:39.536232 ==
3023 11:03:39.539477 Dram Type= 6, Freq= 0, CH_1, rank 0
3024 11:03:39.542549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3025 11:03:39.542654 ==
3026 11:03:39.542790 DQS Delay:
3027 11:03:39.546364 DQS0 = 0, DQS1 = 0
3028 11:03:39.546437 DQM Delay:
3029 11:03:39.549115 DQM0 = 116, DQM1 = 108
3030 11:03:39.549204 DQ Delay:
3031 11:03:39.552783 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3032 11:03:39.555730 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3033 11:03:39.559380 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3034 11:03:39.562322 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3035 11:03:39.562396
3036 11:03:39.562453
3037 11:03:39.562505 ==
3038 11:03:39.565907 Dram Type= 6, Freq= 0, CH_1, rank 0
3039 11:03:39.572610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3040 11:03:39.572685 ==
3041 11:03:39.572741
3042 11:03:39.572793
3043 11:03:39.572843 TX Vref Scan disable
3044 11:03:39.575840 == TX Byte 0 ==
3045 11:03:39.579326 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3046 11:03:39.582773 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3047 11:03:39.586092 == TX Byte 1 ==
3048 11:03:39.589335 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3049 11:03:39.592941 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3050 11:03:39.596326 ==
3051 11:03:39.599359 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 11:03:39.602377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3053 11:03:39.602443 ==
3054 11:03:39.613356 TX Vref=22, minBit 0, minWin=25, winSum=413
3055 11:03:39.616797 TX Vref=24, minBit 1, minWin=25, winSum=416
3056 11:03:39.620637 TX Vref=26, minBit 11, minWin=25, winSum=424
3057 11:03:39.623463 TX Vref=28, minBit 3, minWin=26, winSum=427
3058 11:03:39.626951 TX Vref=30, minBit 1, minWin=26, winSum=430
3059 11:03:39.630506 TX Vref=32, minBit 3, minWin=26, winSum=428
3060 11:03:39.637063 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3061 11:03:39.637154
3062 11:03:39.640333 Final TX Range 1 Vref 30
3063 11:03:39.640399
3064 11:03:39.640453 ==
3065 11:03:39.644014 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 11:03:39.646840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3067 11:03:39.646904 ==
3068 11:03:39.646957
3069 11:03:39.650071
3070 11:03:39.650136 TX Vref Scan disable
3071 11:03:39.653611 == TX Byte 0 ==
3072 11:03:39.656902 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3073 11:03:39.660326 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3074 11:03:39.663681 == TX Byte 1 ==
3075 11:03:39.666915 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3076 11:03:39.670599 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3077 11:03:39.670668
3078 11:03:39.673541 [DATLAT]
3079 11:03:39.673629 Freq=1200, CH1 RK0
3080 11:03:39.673699
3081 11:03:39.676964 DATLAT Default: 0xd
3082 11:03:39.677033 0, 0xFFFF, sum = 0
3083 11:03:39.680401 1, 0xFFFF, sum = 0
3084 11:03:39.680468 2, 0xFFFF, sum = 0
3085 11:03:39.683451 3, 0xFFFF, sum = 0
3086 11:03:39.683521 4, 0xFFFF, sum = 0
3087 11:03:39.686765 5, 0xFFFF, sum = 0
3088 11:03:39.686857 6, 0xFFFF, sum = 0
3089 11:03:39.689975 7, 0xFFFF, sum = 0
3090 11:03:39.693199 8, 0xFFFF, sum = 0
3091 11:03:39.693313 9, 0xFFFF, sum = 0
3092 11:03:39.696517 10, 0xFFFF, sum = 0
3093 11:03:39.696593 11, 0x0, sum = 1
3094 11:03:39.700238 12, 0x0, sum = 2
3095 11:03:39.700313 13, 0x0, sum = 3
3096 11:03:39.700372 14, 0x0, sum = 4
3097 11:03:39.703433 best_step = 12
3098 11:03:39.703507
3099 11:03:39.703564 ==
3100 11:03:39.706882 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 11:03:39.709961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3102 11:03:39.710036 ==
3103 11:03:39.713575 RX Vref Scan: 1
3104 11:03:39.713650
3105 11:03:39.716797 Set Vref Range= 32 -> 127
3106 11:03:39.716871
3107 11:03:39.716928 RX Vref 32 -> 127, step: 1
3108 11:03:39.716981
3109 11:03:39.719923 RX Delay -29 -> 252, step: 4
3110 11:03:39.720020
3111 11:03:39.723602 Set Vref, RX VrefLevel [Byte0]: 32
3112 11:03:39.727161 [Byte1]: 32
3113 11:03:39.730084
3114 11:03:39.730198 Set Vref, RX VrefLevel [Byte0]: 33
3115 11:03:39.733177 [Byte1]: 33
3116 11:03:39.737892
3117 11:03:39.737967 Set Vref, RX VrefLevel [Byte0]: 34
3118 11:03:39.741156 [Byte1]: 34
3119 11:03:39.746360
3120 11:03:39.746433 Set Vref, RX VrefLevel [Byte0]: 35
3121 11:03:39.749682 [Byte1]: 35
3122 11:03:39.753848
3123 11:03:39.753922 Set Vref, RX VrefLevel [Byte0]: 36
3124 11:03:39.757669 [Byte1]: 36
3125 11:03:39.762022
3126 11:03:39.762112 Set Vref, RX VrefLevel [Byte0]: 37
3127 11:03:39.765330 [Byte1]: 37
3128 11:03:39.769774
3129 11:03:39.769848 Set Vref, RX VrefLevel [Byte0]: 38
3130 11:03:39.773210 [Byte1]: 38
3131 11:03:39.778020
3132 11:03:39.778125 Set Vref, RX VrefLevel [Byte0]: 39
3133 11:03:39.781000 [Byte1]: 39
3134 11:03:39.785568
3135 11:03:39.785642 Set Vref, RX VrefLevel [Byte0]: 40
3136 11:03:39.788915 [Byte1]: 40
3137 11:03:39.793663
3138 11:03:39.793737 Set Vref, RX VrefLevel [Byte0]: 41
3139 11:03:39.797158 [Byte1]: 41
3140 11:03:39.801786
3141 11:03:39.801860 Set Vref, RX VrefLevel [Byte0]: 42
3142 11:03:39.804967 [Byte1]: 42
3143 11:03:39.809633
3144 11:03:39.809706 Set Vref, RX VrefLevel [Byte0]: 43
3145 11:03:39.813074 [Byte1]: 43
3146 11:03:39.817769
3147 11:03:39.817843 Set Vref, RX VrefLevel [Byte0]: 44
3148 11:03:39.821156 [Byte1]: 44
3149 11:03:39.825339
3150 11:03:39.825413 Set Vref, RX VrefLevel [Byte0]: 45
3151 11:03:39.828646 [Byte1]: 45
3152 11:03:39.833833
3153 11:03:39.833907 Set Vref, RX VrefLevel [Byte0]: 46
3154 11:03:39.836908 [Byte1]: 46
3155 11:03:39.841374
3156 11:03:39.841448 Set Vref, RX VrefLevel [Byte0]: 47
3157 11:03:39.844977 [Byte1]: 47
3158 11:03:39.849245
3159 11:03:39.849333 Set Vref, RX VrefLevel [Byte0]: 48
3160 11:03:39.852785 [Byte1]: 48
3161 11:03:39.857455
3162 11:03:39.857528 Set Vref, RX VrefLevel [Byte0]: 49
3163 11:03:39.860795 [Byte1]: 49
3164 11:03:39.865520
3165 11:03:39.865594 Set Vref, RX VrefLevel [Byte0]: 50
3166 11:03:39.868817 [Byte1]: 50
3167 11:03:39.873158
3168 11:03:39.873252 Set Vref, RX VrefLevel [Byte0]: 51
3169 11:03:39.876573 [Byte1]: 51
3170 11:03:39.881137
3171 11:03:39.881210 Set Vref, RX VrefLevel [Byte0]: 52
3172 11:03:39.884948 [Byte1]: 52
3173 11:03:39.889498
3174 11:03:39.889572 Set Vref, RX VrefLevel [Byte0]: 53
3175 11:03:39.892509 [Byte1]: 53
3176 11:03:39.897483
3177 11:03:39.897556 Set Vref, RX VrefLevel [Byte0]: 54
3178 11:03:39.900367 [Byte1]: 54
3179 11:03:39.905098
3180 11:03:39.905193 Set Vref, RX VrefLevel [Byte0]: 55
3181 11:03:39.908416 [Byte1]: 55
3182 11:03:39.913120
3183 11:03:39.913214 Set Vref, RX VrefLevel [Byte0]: 56
3184 11:03:39.916230 [Byte1]: 56
3185 11:03:39.921114
3186 11:03:39.921207 Set Vref, RX VrefLevel [Byte0]: 57
3187 11:03:39.924166 [Byte1]: 57
3188 11:03:39.928869
3189 11:03:39.928937 Set Vref, RX VrefLevel [Byte0]: 58
3190 11:03:39.932230 [Byte1]: 58
3191 11:03:39.936766
3192 11:03:39.936857 Set Vref, RX VrefLevel [Byte0]: 59
3193 11:03:39.940044 [Byte1]: 59
3194 11:03:39.944923
3195 11:03:39.945018 Set Vref, RX VrefLevel [Byte0]: 60
3196 11:03:39.947991 [Byte1]: 60
3197 11:03:39.952925
3198 11:03:39.953021 Set Vref, RX VrefLevel [Byte0]: 61
3199 11:03:39.956237 [Byte1]: 61
3200 11:03:39.960753
3201 11:03:39.960820 Set Vref, RX VrefLevel [Byte0]: 62
3202 11:03:39.963838 [Byte1]: 62
3203 11:03:39.968850
3204 11:03:39.968919 Set Vref, RX VrefLevel [Byte0]: 63
3205 11:03:39.971900 [Byte1]: 63
3206 11:03:39.976929
3207 11:03:39.977029 Set Vref, RX VrefLevel [Byte0]: 64
3208 11:03:39.979954 [Byte1]: 64
3209 11:03:39.984670
3210 11:03:39.984760 Set Vref, RX VrefLevel [Byte0]: 65
3211 11:03:39.987997 [Byte1]: 65
3212 11:03:39.992767
3213 11:03:39.992835 Set Vref, RX VrefLevel [Byte0]: 66
3214 11:03:39.995985 [Byte1]: 66
3215 11:03:40.000417
3216 11:03:40.000508 Final RX Vref Byte 0 = 53 to rank0
3217 11:03:40.003709 Final RX Vref Byte 1 = 48 to rank0
3218 11:03:40.007337 Final RX Vref Byte 0 = 53 to rank1
3219 11:03:40.010284 Final RX Vref Byte 1 = 48 to rank1==
3220 11:03:40.013664 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 11:03:40.020306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3222 11:03:40.020397 ==
3223 11:03:40.020455 DQS Delay:
3224 11:03:40.020509 DQS0 = 0, DQS1 = 0
3225 11:03:40.023946 DQM Delay:
3226 11:03:40.024020 DQM0 = 115, DQM1 = 104
3227 11:03:40.027044 DQ Delay:
3228 11:03:40.030334 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3229 11:03:40.034092 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3230 11:03:40.037155 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3231 11:03:40.040316 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =112
3232 11:03:40.040390
3233 11:03:40.040463
3234 11:03:40.050192 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3235 11:03:40.050299 CH1 RK0: MR19=404, MR18=1919
3236 11:03:40.056689 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3237 11:03:40.056764
3238 11:03:40.060112 ----->DramcWriteLeveling(PI) begin...
3239 11:03:40.060188 ==
3240 11:03:40.063246 Dram Type= 6, Freq= 0, CH_1, rank 1
3241 11:03:40.070107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3242 11:03:40.070198 ==
3243 11:03:40.073413 Write leveling (Byte 0): 21 => 21
3244 11:03:40.073482 Write leveling (Byte 1): 21 => 21
3245 11:03:40.077106 DramcWriteLeveling(PI) end<-----
3246 11:03:40.077181
3247 11:03:40.080103 ==
3248 11:03:40.080178 Dram Type= 6, Freq= 0, CH_1, rank 1
3249 11:03:40.086433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3250 11:03:40.086508 ==
3251 11:03:40.089992 [Gating] SW mode calibration
3252 11:03:40.096511 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3253 11:03:40.099685 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3254 11:03:40.106361 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3255 11:03:40.109485 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3256 11:03:40.112766 0 11 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3257 11:03:40.119780 0 11 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
3258 11:03:40.122668 0 11 16 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3259 11:03:40.126044 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3260 11:03:40.132715 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3261 11:03:40.135845 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3262 11:03:40.139465 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3263 11:03:40.146299 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3264 11:03:40.149262 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3265 11:03:40.152629 0 12 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
3266 11:03:40.159610 0 12 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
3267 11:03:40.162736 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3268 11:03:40.165911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 11:03:40.172493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 11:03:40.175825 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 11:03:40.178977 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 11:03:40.185532 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 11:03:40.188952 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3274 11:03:40.192313 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3275 11:03:40.198872 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 11:03:40.202130 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 11:03:40.205903 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 11:03:40.212130 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 11:03:40.215459 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 11:03:40.219244 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 11:03:40.225958 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 11:03:40.228630 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 11:03:40.232128 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 11:03:40.238603 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 11:03:40.242227 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 11:03:40.245150 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 11:03:40.248714 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 11:03:40.255102 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 11:03:40.258621 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3290 11:03:40.261888 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3291 11:03:40.268408 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3292 11:03:40.272075 Total UI for P1: 0, mck2ui 16
3293 11:03:40.274959 best dqsien dly found for B0: ( 0, 15, 14)
3294 11:03:40.278357 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3295 11:03:40.281955 Total UI for P1: 0, mck2ui 16
3296 11:03:40.285015 best dqsien dly found for B1: ( 0, 15, 18)
3297 11:03:40.288527 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3298 11:03:40.291785 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3299 11:03:40.291860
3300 11:03:40.294897 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3301 11:03:40.301991 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3302 11:03:40.302066 [Gating] SW calibration Done
3303 11:03:40.302123 ==
3304 11:03:40.304805 Dram Type= 6, Freq= 0, CH_1, rank 1
3305 11:03:40.311368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3306 11:03:40.311443 ==
3307 11:03:40.311505 RX Vref Scan: 0
3308 11:03:40.311559
3309 11:03:40.314509 RX Vref 0 -> 0, step: 1
3310 11:03:40.314577
3311 11:03:40.317879 RX Delay -40 -> 252, step: 8
3312 11:03:40.321376 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3313 11:03:40.324804 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3314 11:03:40.327805 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3315 11:03:40.334297 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3316 11:03:40.337726 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3317 11:03:40.340852 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3318 11:03:40.344166 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3319 11:03:40.347639 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3320 11:03:40.354071 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3321 11:03:40.357766 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3322 11:03:40.360718 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3323 11:03:40.364032 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3324 11:03:40.367702 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3325 11:03:40.373913 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3326 11:03:40.377322 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3327 11:03:40.380717 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3328 11:03:40.380819 ==
3329 11:03:40.384241 Dram Type= 6, Freq= 0, CH_1, rank 1
3330 11:03:40.387442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3331 11:03:40.390790 ==
3332 11:03:40.390880 DQS Delay:
3333 11:03:40.390950 DQS0 = 0, DQS1 = 0
3334 11:03:40.394149 DQM Delay:
3335 11:03:40.394222 DQM0 = 115, DQM1 = 105
3336 11:03:40.397261 DQ Delay:
3337 11:03:40.400697 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3338 11:03:40.403718 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3339 11:03:40.407305 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3340 11:03:40.410528 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3341 11:03:40.410601
3342 11:03:40.410657
3343 11:03:40.410708 ==
3344 11:03:40.413878 Dram Type= 6, Freq= 0, CH_1, rank 1
3345 11:03:40.417017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3346 11:03:40.417090 ==
3347 11:03:40.417145
3348 11:03:40.417196
3349 11:03:40.420896 TX Vref Scan disable
3350 11:03:40.423539 == TX Byte 0 ==
3351 11:03:40.426670 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3352 11:03:40.430264 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3353 11:03:40.433592 == TX Byte 1 ==
3354 11:03:40.436712 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3355 11:03:40.440141 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3356 11:03:40.440215 ==
3357 11:03:40.443261 Dram Type= 6, Freq= 0, CH_1, rank 1
3358 11:03:40.449854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3359 11:03:40.449928 ==
3360 11:03:40.460772 TX Vref=22, minBit 4, minWin=25, winSum=423
3361 11:03:40.463922 TX Vref=24, minBit 3, minWin=26, winSum=427
3362 11:03:40.467381 TX Vref=26, minBit 3, minWin=26, winSum=431
3363 11:03:40.470306 TX Vref=28, minBit 9, minWin=25, winSum=428
3364 11:03:40.473896 TX Vref=30, minBit 8, minWin=26, winSum=432
3365 11:03:40.480286 TX Vref=32, minBit 9, minWin=26, winSum=432
3366 11:03:40.484025 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3367 11:03:40.484123
3368 11:03:40.486867 Final TX Range 1 Vref 30
3369 11:03:40.486963
3370 11:03:40.487046 ==
3371 11:03:40.490484 Dram Type= 6, Freq= 0, CH_1, rank 1
3372 11:03:40.493576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3373 11:03:40.493644 ==
3374 11:03:40.497085
3375 11:03:40.497171
3376 11:03:40.497282 TX Vref Scan disable
3377 11:03:40.500180 == TX Byte 0 ==
3378 11:03:40.503580 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3379 11:03:40.507605 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3380 11:03:40.509929 == TX Byte 1 ==
3381 11:03:40.514014 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3382 11:03:40.516815 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3383 11:03:40.520138
3384 11:03:40.520227 [DATLAT]
3385 11:03:40.520308 Freq=1200, CH1 RK1
3386 11:03:40.520395
3387 11:03:40.523490 DATLAT Default: 0xc
3388 11:03:40.523594 0, 0xFFFF, sum = 0
3389 11:03:40.526673 1, 0xFFFF, sum = 0
3390 11:03:40.526740 2, 0xFFFF, sum = 0
3391 11:03:40.530122 3, 0xFFFF, sum = 0
3392 11:03:40.530187 4, 0xFFFF, sum = 0
3393 11:03:40.533739 5, 0xFFFF, sum = 0
3394 11:03:40.536732 6, 0xFFFF, sum = 0
3395 11:03:40.536797 7, 0xFFFF, sum = 0
3396 11:03:40.540053 8, 0xFFFF, sum = 0
3397 11:03:40.540142 9, 0xFFFF, sum = 0
3398 11:03:40.543531 10, 0xFFFF, sum = 0
3399 11:03:40.543615 11, 0x0, sum = 1
3400 11:03:40.546769 12, 0x0, sum = 2
3401 11:03:40.546834 13, 0x0, sum = 3
3402 11:03:40.549864 14, 0x0, sum = 4
3403 11:03:40.549927 best_step = 12
3404 11:03:40.549978
3405 11:03:40.550028 ==
3406 11:03:40.553335 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 11:03:40.556647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3408 11:03:40.556713 ==
3409 11:03:40.560115 RX Vref Scan: 0
3410 11:03:40.560189
3411 11:03:40.563131 RX Vref 0 -> 0, step: 1
3412 11:03:40.563249
3413 11:03:40.563312 RX Delay -29 -> 252, step: 4
3414 11:03:40.570775 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3415 11:03:40.573774 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3416 11:03:40.577128 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3417 11:03:40.580767 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3418 11:03:40.583926 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3419 11:03:40.590787 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3420 11:03:40.593907 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3421 11:03:40.596903 iDelay=199, Bit 7, Center 112 (39 ~ 186) 148
3422 11:03:40.600463 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3423 11:03:40.603684 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3424 11:03:40.610257 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3425 11:03:40.613774 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3426 11:03:40.617179 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3427 11:03:40.620468 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3428 11:03:40.624090 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3429 11:03:40.630213 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3430 11:03:40.630293 ==
3431 11:03:40.633372 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 11:03:40.636926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3433 11:03:40.637003 ==
3434 11:03:40.637111 DQS Delay:
3435 11:03:40.640020 DQS0 = 0, DQS1 = 0
3436 11:03:40.640097 DQM Delay:
3437 11:03:40.643364 DQM0 = 114, DQM1 = 103
3438 11:03:40.643441 DQ Delay:
3439 11:03:40.646964 DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112
3440 11:03:40.650676 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3441 11:03:40.653197 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3442 11:03:40.656558 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =110
3443 11:03:40.656668
3444 11:03:40.660278
3445 11:03:40.666544 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3446 11:03:40.670281 CH1 RK1: MR19=404, MR18=D0D
3447 11:03:40.673245 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3448 11:03:40.676661 [RxdqsGatingPostProcess] freq 1200
3449 11:03:40.683371 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3450 11:03:40.686518 Pre-setting of DQS Precalculation
3451 11:03:40.689884 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3452 11:03:40.700158 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3453 11:03:40.706788 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3454 11:03:40.706872
3455 11:03:40.706935
3456 11:03:40.710096 [Calibration Summary] 2400 Mbps
3457 11:03:40.710173 CH 0, Rank 0
3458 11:03:40.713586 SW Impedance : PASS
3459 11:03:40.713664 DUTY Scan : NO K
3460 11:03:40.716490 ZQ Calibration : PASS
3461 11:03:40.720207 Jitter Meter : NO K
3462 11:03:40.720342 CBT Training : PASS
3463 11:03:40.723371 Write leveling : PASS
3464 11:03:40.726679 RX DQS gating : PASS
3465 11:03:40.726756 RX DQ/DQS(RDDQC) : PASS
3466 11:03:40.730036 TX DQ/DQS : PASS
3467 11:03:40.733233 RX DATLAT : PASS
3468 11:03:40.733326 RX DQ/DQS(Engine): PASS
3469 11:03:40.736650 TX OE : NO K
3470 11:03:40.736727 All Pass.
3471 11:03:40.736803
3472 11:03:40.739918 CH 0, Rank 1
3473 11:03:40.740007 SW Impedance : PASS
3474 11:03:40.743012 DUTY Scan : NO K
3475 11:03:40.746585 ZQ Calibration : PASS
3476 11:03:40.746663 Jitter Meter : NO K
3477 11:03:40.749683 CBT Training : PASS
3478 11:03:40.753051 Write leveling : PASS
3479 11:03:40.753128 RX DQS gating : PASS
3480 11:03:40.756808 RX DQ/DQS(RDDQC) : PASS
3481 11:03:40.756885 TX DQ/DQS : PASS
3482 11:03:40.759787 RX DATLAT : PASS
3483 11:03:40.763288 RX DQ/DQS(Engine): PASS
3484 11:03:40.763364 TX OE : NO K
3485 11:03:40.766256 All Pass.
3486 11:03:40.766332
3487 11:03:40.766425 CH 1, Rank 0
3488 11:03:40.769602 SW Impedance : PASS
3489 11:03:40.769679 DUTY Scan : NO K
3490 11:03:40.772915 ZQ Calibration : PASS
3491 11:03:40.776163 Jitter Meter : NO K
3492 11:03:40.776240 CBT Training : PASS
3493 11:03:40.779469 Write leveling : PASS
3494 11:03:40.782838 RX DQS gating : PASS
3495 11:03:40.782916 RX DQ/DQS(RDDQC) : PASS
3496 11:03:40.786067 TX DQ/DQS : PASS
3497 11:03:40.789532 RX DATLAT : PASS
3498 11:03:40.789630 RX DQ/DQS(Engine): PASS
3499 11:03:40.793332 TX OE : NO K
3500 11:03:40.793495 All Pass.
3501 11:03:40.793638
3502 11:03:40.796108 CH 1, Rank 1
3503 11:03:40.796181 SW Impedance : PASS
3504 11:03:40.799468 DUTY Scan : NO K
3505 11:03:40.802975 ZQ Calibration : PASS
3506 11:03:40.803048 Jitter Meter : NO K
3507 11:03:40.806276 CBT Training : PASS
3508 11:03:40.809548 Write leveling : PASS
3509 11:03:40.809688 RX DQS gating : PASS
3510 11:03:40.812507 RX DQ/DQS(RDDQC) : PASS
3511 11:03:40.816275 TX DQ/DQS : PASS
3512 11:03:40.816349 RX DATLAT : PASS
3513 11:03:40.819250 RX DQ/DQS(Engine): PASS
3514 11:03:40.819324 TX OE : NO K
3515 11:03:40.822628 All Pass.
3516 11:03:40.822718
3517 11:03:40.822775 DramC Write-DBI off
3518 11:03:40.825747 PER_BANK_REFRESH: Hybrid Mode
3519 11:03:40.829537 TX_TRACKING: ON
3520 11:03:40.835830 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3521 11:03:40.839271 [FAST_K] Save calibration result to emmc
3522 11:03:40.843022 dramc_set_vcore_voltage set vcore to 650000
3523 11:03:40.845992 Read voltage for 600, 5
3524 11:03:40.846066 Vio18 = 0
3525 11:03:40.849288 Vcore = 650000
3526 11:03:40.849362 Vdram = 0
3527 11:03:40.849420 Vddq = 0
3528 11:03:40.852820 Vmddr = 0
3529 11:03:40.856120 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3530 11:03:40.862688 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3531 11:03:40.862762 MEM_TYPE=3, freq_sel=19
3532 11:03:40.866037 sv_algorithm_assistance_LP4_1600
3533 11:03:40.872603 ============ PULL DRAM RESETB DOWN ============
3534 11:03:40.875991 ========== PULL DRAM RESETB DOWN end =========
3535 11:03:40.879302 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3536 11:03:40.882510 ===================================
3537 11:03:40.886061 LPDDR4 DRAM CONFIGURATION
3538 11:03:40.889639 ===================================
3539 11:03:40.892361 EX_ROW_EN[0] = 0x0
3540 11:03:40.892438 EX_ROW_EN[1] = 0x0
3541 11:03:40.895855 LP4Y_EN = 0x0
3542 11:03:40.895932 WORK_FSP = 0x0
3543 11:03:40.899328 WL = 0x2
3544 11:03:40.899406 RL = 0x2
3545 11:03:40.902693 BL = 0x2
3546 11:03:40.902770 RPST = 0x0
3547 11:03:40.906475 RD_PRE = 0x0
3548 11:03:40.906552 WR_PRE = 0x1
3549 11:03:40.909168 WR_PST = 0x0
3550 11:03:40.909286 DBI_WR = 0x0
3551 11:03:40.912221 DBI_RD = 0x0
3552 11:03:40.912298 OTF = 0x1
3553 11:03:40.915572 ===================================
3554 11:03:40.919073 ===================================
3555 11:03:40.922423 ANA top config
3556 11:03:40.925676 ===================================
3557 11:03:40.928737 DLL_ASYNC_EN = 0
3558 11:03:40.928814 ALL_SLAVE_EN = 1
3559 11:03:40.932217 NEW_RANK_MODE = 1
3560 11:03:40.935578 DLL_IDLE_MODE = 1
3561 11:03:40.938923 LP45_APHY_COMB_EN = 1
3562 11:03:40.939000 TX_ODT_DIS = 1
3563 11:03:40.942325 NEW_8X_MODE = 1
3564 11:03:40.945660 ===================================
3565 11:03:40.948941 ===================================
3566 11:03:40.952887 data_rate = 1200
3567 11:03:40.955547 CKR = 1
3568 11:03:40.959019 DQ_P2S_RATIO = 8
3569 11:03:40.962216 ===================================
3570 11:03:40.965468 CA_P2S_RATIO = 8
3571 11:03:40.965545 DQ_CA_OPEN = 0
3572 11:03:40.968630 DQ_SEMI_OPEN = 0
3573 11:03:40.972564 CA_SEMI_OPEN = 0
3574 11:03:40.975543 CA_FULL_RATE = 0
3575 11:03:40.978760 DQ_CKDIV4_EN = 1
3576 11:03:40.982294 CA_CKDIV4_EN = 1
3577 11:03:40.982370 CA_PREDIV_EN = 0
3578 11:03:40.985383 PH8_DLY = 0
3579 11:03:40.988510 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3580 11:03:40.991902 DQ_AAMCK_DIV = 4
3581 11:03:40.995593 CA_AAMCK_DIV = 4
3582 11:03:40.998807 CA_ADMCK_DIV = 4
3583 11:03:40.998885 DQ_TRACK_CA_EN = 0
3584 11:03:41.002089 CA_PICK = 600
3585 11:03:41.005200 CA_MCKIO = 600
3586 11:03:41.008579 MCKIO_SEMI = 0
3587 11:03:41.011857 PLL_FREQ = 2288
3588 11:03:41.015454 DQ_UI_PI_RATIO = 32
3589 11:03:41.018387 CA_UI_PI_RATIO = 0
3590 11:03:41.021748 ===================================
3591 11:03:41.024896 ===================================
3592 11:03:41.024973 memory_type:LPDDR4
3593 11:03:41.028302 GP_NUM : 10
3594 11:03:41.031971 SRAM_EN : 1
3595 11:03:41.032048 MD32_EN : 0
3596 11:03:41.035004 ===================================
3597 11:03:41.038595 [ANA_INIT] >>>>>>>>>>>>>>
3598 11:03:41.041534 <<<<<< [CONFIGURE PHASE]: ANA_TX
3599 11:03:41.044852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3600 11:03:41.048211 ===================================
3601 11:03:41.051580 data_rate = 1200,PCW = 0X5800
3602 11:03:41.054874 ===================================
3603 11:03:41.058531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3604 11:03:41.061841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3605 11:03:41.067943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3606 11:03:41.071742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3607 11:03:41.074564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3608 11:03:41.077952 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3609 11:03:41.081340 [ANA_INIT] flow start
3610 11:03:41.084728 [ANA_INIT] PLL >>>>>>>>
3611 11:03:41.084805 [ANA_INIT] PLL <<<<<<<<
3612 11:03:41.087783 [ANA_INIT] MIDPI >>>>>>>>
3613 11:03:41.091220 [ANA_INIT] MIDPI <<<<<<<<
3614 11:03:41.094245 [ANA_INIT] DLL >>>>>>>>
3615 11:03:41.094322 [ANA_INIT] flow end
3616 11:03:41.097531 ============ LP4 DIFF to SE enter ============
3617 11:03:41.104472 ============ LP4 DIFF to SE exit ============
3618 11:03:41.104549 [ANA_INIT] <<<<<<<<<<<<<
3619 11:03:41.107810 [Flow] Enable top DCM control >>>>>
3620 11:03:41.111182 [Flow] Enable top DCM control <<<<<
3621 11:03:41.114893 Enable DLL master slave shuffle
3622 11:03:41.120869 ==============================================================
3623 11:03:41.120948 Gating Mode config
3624 11:03:41.127785 ==============================================================
3625 11:03:41.130932 Config description:
3626 11:03:41.140851 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3627 11:03:41.147619 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3628 11:03:41.150689 SELPH_MODE 0: By rank 1: By Phase
3629 11:03:41.157501 ==============================================================
3630 11:03:41.161089 GAT_TRACK_EN = 1
3631 11:03:41.161166 RX_GATING_MODE = 2
3632 11:03:41.164176 RX_GATING_TRACK_MODE = 2
3633 11:03:41.167263 SELPH_MODE = 1
3634 11:03:41.170606 PICG_EARLY_EN = 1
3635 11:03:41.173977 VALID_LAT_VALUE = 1
3636 11:03:41.180588 ==============================================================
3637 11:03:41.183697 Enter into Gating configuration >>>>
3638 11:03:41.187280 Exit from Gating configuration <<<<
3639 11:03:41.190811 Enter into DVFS_PRE_config >>>>>
3640 11:03:41.200728 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3641 11:03:41.203690 Exit from DVFS_PRE_config <<<<<
3642 11:03:41.207007 Enter into PICG configuration >>>>
3643 11:03:41.210297 Exit from PICG configuration <<<<
3644 11:03:41.213741 [RX_INPUT] configuration >>>>>
3645 11:03:41.216893 [RX_INPUT] configuration <<<<<
3646 11:03:41.220289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3647 11:03:41.227456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3648 11:03:41.234197 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3649 11:03:41.240391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3650 11:03:41.243671 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3651 11:03:41.250422 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3652 11:03:41.253499 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3653 11:03:41.260480 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3654 11:03:41.263920 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3655 11:03:41.266926 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3656 11:03:41.270338 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3657 11:03:41.276746 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3658 11:03:41.280063 ===================================
3659 11:03:41.280160 LPDDR4 DRAM CONFIGURATION
3660 11:03:41.283283 ===================================
3661 11:03:41.286816 EX_ROW_EN[0] = 0x0
3662 11:03:41.290227 EX_ROW_EN[1] = 0x0
3663 11:03:41.290305 LP4Y_EN = 0x0
3664 11:03:41.293661 WORK_FSP = 0x0
3665 11:03:41.293740 WL = 0x2
3666 11:03:41.296570 RL = 0x2
3667 11:03:41.296647 BL = 0x2
3668 11:03:41.299849 RPST = 0x0
3669 11:03:41.299942 RD_PRE = 0x0
3670 11:03:41.303074 WR_PRE = 0x1
3671 11:03:41.303151 WR_PST = 0x0
3672 11:03:41.306437 DBI_WR = 0x0
3673 11:03:41.306514 DBI_RD = 0x0
3674 11:03:41.309870 OTF = 0x1
3675 11:03:41.313199 ===================================
3676 11:03:41.316425 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3677 11:03:41.319560 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3678 11:03:41.326210 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3679 11:03:41.329937 ===================================
3680 11:03:41.330015 LPDDR4 DRAM CONFIGURATION
3681 11:03:41.334009 ===================================
3682 11:03:41.336333 EX_ROW_EN[0] = 0x10
3683 11:03:41.339509 EX_ROW_EN[1] = 0x0
3684 11:03:41.339586 LP4Y_EN = 0x0
3685 11:03:41.342877 WORK_FSP = 0x0
3686 11:03:41.342954 WL = 0x2
3687 11:03:41.346274 RL = 0x2
3688 11:03:41.346351 BL = 0x2
3689 11:03:41.349270 RPST = 0x0
3690 11:03:41.349346 RD_PRE = 0x0
3691 11:03:41.352792 WR_PRE = 0x1
3692 11:03:41.352900 WR_PST = 0x0
3693 11:03:41.356054 DBI_WR = 0x0
3694 11:03:41.356131 DBI_RD = 0x0
3695 11:03:41.359294 OTF = 0x1
3696 11:03:41.362814 ===================================
3697 11:03:41.369733 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3698 11:03:41.372865 nWR fixed to 30
3699 11:03:41.372944 [ModeRegInit_LP4] CH0 RK0
3700 11:03:41.376253 [ModeRegInit_LP4] CH0 RK1
3701 11:03:41.379420 [ModeRegInit_LP4] CH1 RK0
3702 11:03:41.382796 [ModeRegInit_LP4] CH1 RK1
3703 11:03:41.382869 match AC timing 16
3704 11:03:41.389375 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3705 11:03:41.392820 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3706 11:03:41.395765 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3707 11:03:41.402991 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3708 11:03:41.406006 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3709 11:03:41.406085 ==
3710 11:03:41.409559 Dram Type= 6, Freq= 0, CH_0, rank 0
3711 11:03:41.412537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3712 11:03:41.412615 ==
3713 11:03:41.419287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3714 11:03:41.425625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3715 11:03:41.429171 [CA 0] Center 35 (5~66) winsize 62
3716 11:03:41.432428 [CA 1] Center 35 (5~66) winsize 62
3717 11:03:41.436064 [CA 2] Center 34 (4~65) winsize 62
3718 11:03:41.439148 [CA 3] Center 34 (4~65) winsize 62
3719 11:03:41.442262 [CA 4] Center 33 (3~64) winsize 62
3720 11:03:41.445636 [CA 5] Center 33 (3~64) winsize 62
3721 11:03:41.445714
3722 11:03:41.449203 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3723 11:03:41.449305
3724 11:03:41.452205 [CATrainingPosCal] consider 1 rank data
3725 11:03:41.455688 u2DelayCellTimex100 = 270/100 ps
3726 11:03:41.458991 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3727 11:03:41.462319 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3728 11:03:41.465835 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3729 11:03:41.469146 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3730 11:03:41.472479 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3731 11:03:41.475441 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3732 11:03:41.475534
3733 11:03:41.482205 CA PerBit enable=1, Macro0, CA PI delay=33
3734 11:03:41.482283
3735 11:03:41.482360 [CBTSetCACLKResult] CA Dly = 33
3736 11:03:41.485746 CS Dly: 5 (0~36)
3737 11:03:41.485822 ==
3738 11:03:41.489032 Dram Type= 6, Freq= 0, CH_0, rank 1
3739 11:03:41.492216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3740 11:03:41.492294 ==
3741 11:03:41.498991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3742 11:03:41.505704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3743 11:03:41.508737 [CA 0] Center 35 (5~66) winsize 62
3744 11:03:41.512309 [CA 1] Center 35 (5~66) winsize 62
3745 11:03:41.515637 [CA 2] Center 34 (4~65) winsize 62
3746 11:03:41.518757 [CA 3] Center 34 (4~65) winsize 62
3747 11:03:41.521887 [CA 4] Center 33 (3~64) winsize 62
3748 11:03:41.525424 [CA 5] Center 33 (3~64) winsize 62
3749 11:03:41.525502
3750 11:03:41.528869 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3751 11:03:41.528986
3752 11:03:41.531979 [CATrainingPosCal] consider 2 rank data
3753 11:03:41.535130 u2DelayCellTimex100 = 270/100 ps
3754 11:03:41.538842 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3755 11:03:41.541985 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3756 11:03:41.545087 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3757 11:03:41.548581 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3758 11:03:41.551953 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3759 11:03:41.555317 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3760 11:03:41.558744
3761 11:03:41.562050 CA PerBit enable=1, Macro0, CA PI delay=33
3762 11:03:41.562123
3763 11:03:41.565121 [CBTSetCACLKResult] CA Dly = 33
3764 11:03:41.565218 CS Dly: 5 (0~36)
3765 11:03:41.565328
3766 11:03:41.568792 ----->DramcWriteLeveling(PI) begin...
3767 11:03:41.568867 ==
3768 11:03:41.572138 Dram Type= 6, Freq= 0, CH_0, rank 0
3769 11:03:41.575253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3770 11:03:41.578476 ==
3771 11:03:41.578550 Write leveling (Byte 0): 32 => 32
3772 11:03:41.582023 Write leveling (Byte 1): 29 => 29
3773 11:03:41.585418 DramcWriteLeveling(PI) end<-----
3774 11:03:41.585492
3775 11:03:41.585552 ==
3776 11:03:41.588627 Dram Type= 6, Freq= 0, CH_0, rank 0
3777 11:03:41.595225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3778 11:03:41.595300 ==
3779 11:03:41.595387 [Gating] SW mode calibration
3780 11:03:41.605498 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3781 11:03:41.608893 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3782 11:03:41.612080 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3783 11:03:41.619051 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3784 11:03:41.621958 0 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3785 11:03:41.625152 0 5 12 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
3786 11:03:41.632096 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3787 11:03:41.635058 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3788 11:03:41.638892 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3789 11:03:41.645408 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3790 11:03:41.648950 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3791 11:03:41.651673 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 11:03:41.658353 0 6 8 | B1->B0 | 3030 3333 | 0 0 | (1 1) (0 0)
3793 11:03:41.661728 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3794 11:03:41.665257 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3795 11:03:41.671449 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3796 11:03:41.674910 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3797 11:03:41.678423 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3798 11:03:41.684751 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 11:03:41.688296 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3800 11:03:41.691426 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3801 11:03:41.697960 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3802 11:03:41.701339 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3803 11:03:41.704802 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3804 11:03:41.711422 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3805 11:03:41.714889 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 11:03:41.718079 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 11:03:41.724570 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 11:03:41.727914 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 11:03:41.731253 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 11:03:41.737817 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 11:03:41.741131 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 11:03:41.744816 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 11:03:41.751344 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 11:03:41.754640 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 11:03:41.757908 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 11:03:41.761052 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3817 11:03:41.764535 Total UI for P1: 0, mck2ui 16
3818 11:03:41.768081 best dqsien dly found for B0: ( 0, 9, 6)
3819 11:03:41.774390 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3820 11:03:41.777906 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3821 11:03:41.781381 Total UI for P1: 0, mck2ui 16
3822 11:03:41.784504 best dqsien dly found for B1: ( 0, 9, 10)
3823 11:03:41.788027 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3824 11:03:41.791097 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3825 11:03:41.791188
3826 11:03:41.794373 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3827 11:03:41.797799 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3828 11:03:41.800820 [Gating] SW calibration Done
3829 11:03:41.800909 ==
3830 11:03:41.804328 Dram Type= 6, Freq= 0, CH_0, rank 0
3831 11:03:41.810985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3832 11:03:41.811150 ==
3833 11:03:41.811237 RX Vref Scan: 0
3834 11:03:41.811350
3835 11:03:41.814538 RX Vref 0 -> 0, step: 1
3836 11:03:41.814626
3837 11:03:41.817559 RX Delay -230 -> 252, step: 16
3838 11:03:41.820697 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3839 11:03:41.823969 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3840 11:03:41.827544 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3841 11:03:41.834082 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
3842 11:03:41.837611 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3843 11:03:41.841239 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
3844 11:03:41.844198 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3845 11:03:41.850809 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3846 11:03:41.854234 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3847 11:03:41.857552 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3848 11:03:41.860712 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
3849 11:03:41.864206 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3850 11:03:41.870422 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3851 11:03:41.873979 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3852 11:03:41.877173 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3853 11:03:41.880373 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3854 11:03:41.883559 ==
3855 11:03:41.887138 Dram Type= 6, Freq= 0, CH_0, rank 0
3856 11:03:41.890384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3857 11:03:41.890452 ==
3858 11:03:41.890510 DQS Delay:
3859 11:03:41.893902 DQS0 = 0, DQS1 = 0
3860 11:03:41.893964 DQM Delay:
3861 11:03:41.897111 DQM0 = 43, DQM1 = 34
3862 11:03:41.897195 DQ Delay:
3863 11:03:41.900395 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
3864 11:03:41.903655 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3865 11:03:41.907372 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
3866 11:03:41.910220 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3867 11:03:41.910307
3868 11:03:41.910387
3869 11:03:41.910465 ==
3870 11:03:41.913651 Dram Type= 6, Freq= 0, CH_0, rank 0
3871 11:03:41.916990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3872 11:03:41.917074 ==
3873 11:03:41.917153
3874 11:03:41.917237
3875 11:03:41.920416 TX Vref Scan disable
3876 11:03:41.923617 == TX Byte 0 ==
3877 11:03:41.927093 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3878 11:03:41.930200 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3879 11:03:41.933767 == TX Byte 1 ==
3880 11:03:41.937028 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3881 11:03:41.940329 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3882 11:03:41.940412 ==
3883 11:03:41.943794 Dram Type= 6, Freq= 0, CH_0, rank 0
3884 11:03:41.950270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3885 11:03:41.950341 ==
3886 11:03:41.950396
3887 11:03:41.950447
3888 11:03:41.950497 TX Vref Scan disable
3889 11:03:41.954274 == TX Byte 0 ==
3890 11:03:41.957973 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3891 11:03:41.964356 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3892 11:03:41.964444 == TX Byte 1 ==
3893 11:03:41.967559 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3894 11:03:41.974413 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3895 11:03:41.974482
3896 11:03:41.974542 [DATLAT]
3897 11:03:41.974595 Freq=600, CH0 RK0
3898 11:03:41.974646
3899 11:03:41.977632 DATLAT Default: 0x9
3900 11:03:41.980587 0, 0xFFFF, sum = 0
3901 11:03:41.980677 1, 0xFFFF, sum = 0
3902 11:03:41.984398 2, 0xFFFF, sum = 0
3903 11:03:41.984487 3, 0xFFFF, sum = 0
3904 11:03:41.987302 4, 0xFFFF, sum = 0
3905 11:03:41.987390 5, 0xFFFF, sum = 0
3906 11:03:41.990604 6, 0xFFFF, sum = 0
3907 11:03:41.990667 7, 0x0, sum = 1
3908 11:03:41.994045 8, 0x0, sum = 2
3909 11:03:41.994108 9, 0x0, sum = 3
3910 11:03:41.994162 10, 0x0, sum = 4
3911 11:03:41.997600 best_step = 8
3912 11:03:41.997661
3913 11:03:41.997711 ==
3914 11:03:42.000444 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 11:03:42.004001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3916 11:03:42.004088 ==
3917 11:03:42.007070 RX Vref Scan: 1
3918 11:03:42.007132
3919 11:03:42.007188 RX Vref 0 -> 0, step: 1
3920 11:03:42.007239
3921 11:03:42.010398 RX Delay -195 -> 252, step: 8
3922 11:03:42.010461
3923 11:03:42.013954 Set Vref, RX VrefLevel [Byte0]: 50
3924 11:03:42.017070 [Byte1]: 52
3925 11:03:42.021350
3926 11:03:42.021441 Final RX Vref Byte 0 = 50 to rank0
3927 11:03:42.024777 Final RX Vref Byte 1 = 52 to rank0
3928 11:03:42.028145 Final RX Vref Byte 0 = 50 to rank1
3929 11:03:42.031666 Final RX Vref Byte 1 = 52 to rank1==
3930 11:03:42.034583 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 11:03:42.041285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3932 11:03:42.041353 ==
3933 11:03:42.041409 DQS Delay:
3934 11:03:42.041465 DQS0 = 0, DQS1 = 0
3935 11:03:42.044744 DQM Delay:
3936 11:03:42.044815 DQM0 = 40, DQM1 = 30
3937 11:03:42.047772 DQ Delay:
3938 11:03:42.051326 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3939 11:03:42.054564 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
3940 11:03:42.057707 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
3941 11:03:42.060968 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3942 11:03:42.061037
3943 11:03:42.061092
3944 11:03:42.067771 [DQSOSCAuto] RK0, (LSB)MR18= 0x5757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3945 11:03:42.071285 CH0 RK0: MR19=808, MR18=5757
3946 11:03:42.077941 CH0_RK0: MR19=0x808, MR18=0x5757, DQSOSC=393, MR23=63, INC=169, DEC=113
3947 11:03:42.078013
3948 11:03:42.081007 ----->DramcWriteLeveling(PI) begin...
3949 11:03:42.081099 ==
3950 11:03:42.084355 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 11:03:42.087629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3952 11:03:42.087720 ==
3953 11:03:42.090893 Write leveling (Byte 0): 32 => 32
3954 11:03:42.094502 Write leveling (Byte 1): 32 => 32
3955 11:03:42.097888 DramcWriteLeveling(PI) end<-----
3956 11:03:42.097949
3957 11:03:42.098003 ==
3958 11:03:42.101366 Dram Type= 6, Freq= 0, CH_0, rank 1
3959 11:03:42.104310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3960 11:03:42.104370 ==
3961 11:03:42.107897 [Gating] SW mode calibration
3962 11:03:42.114453 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3963 11:03:42.121320 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3964 11:03:42.124331 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 11:03:42.127912 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 11:03:42.134909 0 5 8 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 0)
3967 11:03:42.137878 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3968 11:03:42.141315 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 11:03:42.148048 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 11:03:42.151415 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 11:03:42.154475 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 11:03:42.161018 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 11:03:42.164321 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 11:03:42.168191 0 6 8 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
3975 11:03:42.174279 0 6 12 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
3976 11:03:42.177938 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 11:03:42.181020 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 11:03:42.187988 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 11:03:42.190940 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 11:03:42.194317 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 11:03:42.200996 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 11:03:42.204251 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3983 11:03:42.207650 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3984 11:03:42.214493 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 11:03:42.217612 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 11:03:42.220655 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 11:03:42.227453 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 11:03:42.230587 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 11:03:42.233941 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 11:03:42.240927 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 11:03:42.243992 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:03:42.247605 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:03:42.250820 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:03:42.257726 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:03:42.260822 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:03:42.264089 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:03:42.270663 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:03:42.274325 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3999 11:03:42.277573 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 11:03:42.280639 Total UI for P1: 0, mck2ui 16
4001 11:03:42.283963 best dqsien dly found for B0: ( 0, 9, 8)
4002 11:03:42.287511 Total UI for P1: 0, mck2ui 16
4003 11:03:42.290730 best dqsien dly found for B1: ( 0, 9, 8)
4004 11:03:42.294449 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4005 11:03:42.297052 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4006 11:03:42.297148
4007 11:03:42.304155 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4008 11:03:42.307114 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4009 11:03:42.310591 [Gating] SW calibration Done
4010 11:03:42.310668 ==
4011 11:03:42.314210 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 11:03:42.317181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4013 11:03:42.317311 ==
4014 11:03:42.317414 RX Vref Scan: 0
4015 11:03:42.317500
4016 11:03:42.320376 RX Vref 0 -> 0, step: 1
4017 11:03:42.320474
4018 11:03:42.323799 RX Delay -230 -> 252, step: 16
4019 11:03:42.326928 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4020 11:03:42.330443 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4021 11:03:42.337025 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4022 11:03:42.340275 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4023 11:03:42.343360 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4024 11:03:42.347011 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4025 11:03:42.353550 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4026 11:03:42.357129 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4027 11:03:42.360483 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4028 11:03:42.363403 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4029 11:03:42.366844 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4030 11:03:42.373631 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4031 11:03:42.377140 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4032 11:03:42.380272 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4033 11:03:42.383808 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4034 11:03:42.390047 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4035 11:03:42.390140 ==
4036 11:03:42.393460 Dram Type= 6, Freq= 0, CH_0, rank 1
4037 11:03:42.396764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4038 11:03:42.396839 ==
4039 11:03:42.396924 DQS Delay:
4040 11:03:42.400323 DQS0 = 0, DQS1 = 0
4041 11:03:42.400401 DQM Delay:
4042 11:03:42.403181 DQM0 = 41, DQM1 = 32
4043 11:03:42.403258 DQ Delay:
4044 11:03:42.406649 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =33
4045 11:03:42.409998 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4046 11:03:42.413720 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4047 11:03:42.416749 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4048 11:03:42.416826
4049 11:03:42.416903
4050 11:03:42.416975 ==
4051 11:03:42.419806 Dram Type= 6, Freq= 0, CH_0, rank 1
4052 11:03:42.423161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4053 11:03:42.423260 ==
4054 11:03:42.426427
4055 11:03:42.426505
4056 11:03:42.426581 TX Vref Scan disable
4057 11:03:42.430253 == TX Byte 0 ==
4058 11:03:42.433115 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4059 11:03:42.436448 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4060 11:03:42.439931 == TX Byte 1 ==
4061 11:03:42.443214 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4062 11:03:42.446493 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4063 11:03:42.449720 ==
4064 11:03:42.452805 Dram Type= 6, Freq= 0, CH_0, rank 1
4065 11:03:42.455975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4066 11:03:42.456050 ==
4067 11:03:42.456110
4068 11:03:42.456163
4069 11:03:42.459478 TX Vref Scan disable
4070 11:03:42.459552 == TX Byte 0 ==
4071 11:03:42.465882 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4072 11:03:42.469556 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4073 11:03:42.469632 == TX Byte 1 ==
4074 11:03:42.475994 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 11:03:42.479737 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 11:03:42.479812
4077 11:03:42.479870 [DATLAT]
4078 11:03:42.482800 Freq=600, CH0 RK1
4079 11:03:42.482875
4080 11:03:42.482933 DATLAT Default: 0x8
4081 11:03:42.486167 0, 0xFFFF, sum = 0
4082 11:03:42.486243 1, 0xFFFF, sum = 0
4083 11:03:42.489419 2, 0xFFFF, sum = 0
4084 11:03:42.492639 3, 0xFFFF, sum = 0
4085 11:03:42.492714 4, 0xFFFF, sum = 0
4086 11:03:42.495902 5, 0xFFFF, sum = 0
4087 11:03:42.495977 6, 0xFFFF, sum = 0
4088 11:03:42.499324 7, 0x0, sum = 1
4089 11:03:42.499400 8, 0x0, sum = 2
4090 11:03:42.499459 9, 0x0, sum = 3
4091 11:03:42.502710 10, 0x0, sum = 4
4092 11:03:42.502786 best_step = 8
4093 11:03:42.502845
4094 11:03:42.502899 ==
4095 11:03:42.505991 Dram Type= 6, Freq= 0, CH_0, rank 1
4096 11:03:42.512311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4097 11:03:42.512387 ==
4098 11:03:42.512445 RX Vref Scan: 0
4099 11:03:42.512499
4100 11:03:42.515998 RX Vref 0 -> 0, step: 1
4101 11:03:42.516088
4102 11:03:42.518854 RX Delay -195 -> 252, step: 8
4103 11:03:42.522296 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4104 11:03:42.528751 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4105 11:03:42.532744 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4106 11:03:42.535667 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4107 11:03:42.538863 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4108 11:03:42.545542 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4109 11:03:42.548976 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4110 11:03:42.552748 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4111 11:03:42.555932 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4112 11:03:42.559023 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4113 11:03:42.565207 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4114 11:03:42.569060 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4115 11:03:42.571831 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4116 11:03:42.575420 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4117 11:03:42.581982 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4118 11:03:42.585138 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4119 11:03:42.585235 ==
4120 11:03:42.588419 Dram Type= 6, Freq= 0, CH_0, rank 1
4121 11:03:42.592045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4122 11:03:42.592121 ==
4123 11:03:42.595136 DQS Delay:
4124 11:03:42.595211 DQS0 = 0, DQS1 = 0
4125 11:03:42.595270 DQM Delay:
4126 11:03:42.598559 DQM0 = 40, DQM1 = 32
4127 11:03:42.598633 DQ Delay:
4128 11:03:42.601550 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4129 11:03:42.604908 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4130 11:03:42.608447 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4131 11:03:42.611731 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =44
4132 11:03:42.611805
4133 11:03:42.611863
4134 11:03:42.621515 [DQSOSCAuto] RK1, (LSB)MR18= 0x7575, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4135 11:03:42.624723 CH0 RK1: MR19=808, MR18=7575
4136 11:03:42.631419 CH0_RK1: MR19=0x808, MR18=0x7575, DQSOSC=387, MR23=63, INC=175, DEC=116
4137 11:03:42.631499 [RxdqsGatingPostProcess] freq 600
4138 11:03:42.638173 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4139 11:03:42.641385 Pre-setting of DQS Precalculation
4140 11:03:42.644769 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4141 11:03:42.647967 ==
4142 11:03:42.648042 Dram Type= 6, Freq= 0, CH_1, rank 0
4143 11:03:42.654618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4144 11:03:42.654694 ==
4145 11:03:42.657740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4146 11:03:42.664359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4147 11:03:42.668040 [CA 0] Center 35 (5~66) winsize 62
4148 11:03:42.671555 [CA 1] Center 35 (5~65) winsize 61
4149 11:03:42.675053 [CA 2] Center 33 (3~64) winsize 62
4150 11:03:42.678060 [CA 3] Center 33 (3~64) winsize 62
4151 11:03:42.681381 [CA 4] Center 33 (2~64) winsize 63
4152 11:03:42.685153 [CA 5] Center 33 (2~64) winsize 63
4153 11:03:42.685274
4154 11:03:42.687896 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4155 11:03:42.687970
4156 11:03:42.691290 [CATrainingPosCal] consider 1 rank data
4157 11:03:42.694619 u2DelayCellTimex100 = 270/100 ps
4158 11:03:42.697986 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4159 11:03:42.704693 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4160 11:03:42.708183 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4161 11:03:42.711498 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4162 11:03:42.714419 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4163 11:03:42.718195 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4164 11:03:42.718270
4165 11:03:42.721216 CA PerBit enable=1, Macro0, CA PI delay=33
4166 11:03:42.721350
4167 11:03:42.724393 [CBTSetCACLKResult] CA Dly = 33
4168 11:03:42.724468 CS Dly: 4 (0~35)
4169 11:03:42.727673 ==
4170 11:03:42.731131 Dram Type= 6, Freq= 0, CH_1, rank 1
4171 11:03:42.734438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4172 11:03:42.734514 ==
4173 11:03:42.737878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4174 11:03:42.744431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4175 11:03:42.748516 [CA 0] Center 35 (5~66) winsize 62
4176 11:03:42.751369 [CA 1] Center 34 (4~65) winsize 62
4177 11:03:42.754864 [CA 2] Center 33 (3~64) winsize 62
4178 11:03:42.758899 [CA 3] Center 33 (3~64) winsize 62
4179 11:03:42.761604 [CA 4] Center 32 (2~63) winsize 62
4180 11:03:42.764709 [CA 5] Center 32 (2~63) winsize 62
4181 11:03:42.764784
4182 11:03:42.768380 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4183 11:03:42.768460
4184 11:03:42.771365 [CATrainingPosCal] consider 2 rank data
4185 11:03:42.774960 u2DelayCellTimex100 = 270/100 ps
4186 11:03:42.778213 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4187 11:03:42.781662 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4188 11:03:42.788597 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4189 11:03:42.791931 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4190 11:03:42.795175 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4191 11:03:42.798270 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4192 11:03:42.798344
4193 11:03:42.801340 CA PerBit enable=1, Macro0, CA PI delay=32
4194 11:03:42.801440
4195 11:03:42.804637 [CBTSetCACLKResult] CA Dly = 32
4196 11:03:42.804734 CS Dly: 3 (0~34)
4197 11:03:42.804817
4198 11:03:42.808169 ----->DramcWriteLeveling(PI) begin...
4199 11:03:42.811764 ==
4200 11:03:42.815168 Dram Type= 6, Freq= 0, CH_1, rank 0
4201 11:03:42.817928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4202 11:03:42.818004 ==
4203 11:03:42.821251 Write leveling (Byte 0): 29 => 29
4204 11:03:42.824574 Write leveling (Byte 1): 29 => 29
4205 11:03:42.828013 DramcWriteLeveling(PI) end<-----
4206 11:03:42.828088
4207 11:03:42.828146 ==
4208 11:03:42.831463 Dram Type= 6, Freq= 0, CH_1, rank 0
4209 11:03:42.834510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4210 11:03:42.834582 ==
4211 11:03:42.837885 [Gating] SW mode calibration
4212 11:03:42.844620 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4213 11:03:42.851052 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4214 11:03:42.854746 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4215 11:03:42.857896 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
4216 11:03:42.861326 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4217 11:03:42.868317 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 11:03:42.871431 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 11:03:42.874435 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 11:03:42.880996 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:03:42.884361 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:03:42.887916 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 11:03:42.894577 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4224 11:03:42.897859 0 6 8 | B1->B0 | 3636 4141 | 0 0 | (0 0) (0 0)
4225 11:03:42.901037 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4226 11:03:42.907619 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 11:03:42.911187 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 11:03:42.914525 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:03:42.921064 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:03:42.924433 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:03:42.927762 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:03:42.934341 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4233 11:03:42.937461 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 11:03:42.941193 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 11:03:42.947528 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 11:03:42.950680 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:03:42.954183 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:03:42.960646 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:03:42.963981 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:03:42.967245 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:03:42.974606 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:03:42.977285 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:03:42.980804 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:03:42.987223 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:03:42.990559 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:03:42.994512 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4247 11:03:43.000629 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:03:43.003652 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 11:03:43.007290 Total UI for P1: 0, mck2ui 16
4250 11:03:43.010380 best dqsien dly found for B0: ( 0, 9, 6)
4251 11:03:43.014021 Total UI for P1: 0, mck2ui 16
4252 11:03:43.017142 best dqsien dly found for B1: ( 0, 9, 6)
4253 11:03:43.020318 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4254 11:03:43.023531 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4255 11:03:43.023626
4256 11:03:43.027069 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4257 11:03:43.030157 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4258 11:03:43.033592 [Gating] SW calibration Done
4259 11:03:43.033690 ==
4260 11:03:43.037158 Dram Type= 6, Freq= 0, CH_1, rank 0
4261 11:03:43.040435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4262 11:03:43.040511 ==
4263 11:03:43.043609 RX Vref Scan: 0
4264 11:03:43.043683
4265 11:03:43.047048 RX Vref 0 -> 0, step: 1
4266 11:03:43.047122
4267 11:03:43.047179 RX Delay -230 -> 252, step: 16
4268 11:03:43.053545 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4269 11:03:43.056849 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4270 11:03:43.060436 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4271 11:03:43.063280 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4272 11:03:43.070104 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4273 11:03:43.073910 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4274 11:03:43.076631 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4275 11:03:43.080055 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4276 11:03:43.083513 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4277 11:03:43.089951 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4278 11:03:43.093549 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4279 11:03:43.096803 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4280 11:03:43.099891 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4281 11:03:43.106816 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4282 11:03:43.109976 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4283 11:03:43.113521 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4284 11:03:43.113596 ==
4285 11:03:43.116634 Dram Type= 6, Freq= 0, CH_1, rank 0
4286 11:03:43.119935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4287 11:03:43.123251 ==
4288 11:03:43.123327 DQS Delay:
4289 11:03:43.123386 DQS0 = 0, DQS1 = 0
4290 11:03:43.126539 DQM Delay:
4291 11:03:43.126620 DQM0 = 39, DQM1 = 34
4292 11:03:43.130198 DQ Delay:
4293 11:03:43.130273 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4294 11:03:43.133639 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4295 11:03:43.136885 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4296 11:03:43.140283 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4297 11:03:43.140358
4298 11:03:43.140415
4299 11:03:43.143486 ==
4300 11:03:43.147286 Dram Type= 6, Freq= 0, CH_1, rank 0
4301 11:03:43.150194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4302 11:03:43.150268 ==
4303 11:03:43.150326
4304 11:03:43.150386
4305 11:03:43.153328 TX Vref Scan disable
4306 11:03:43.153422 == TX Byte 0 ==
4307 11:03:43.156896 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4308 11:03:43.163527 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4309 11:03:43.163617 == TX Byte 1 ==
4310 11:03:43.169912 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4311 11:03:43.173422 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4312 11:03:43.173512 ==
4313 11:03:43.176671 Dram Type= 6, Freq= 0, CH_1, rank 0
4314 11:03:43.180092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4315 11:03:43.180157 ==
4316 11:03:43.180210
4317 11:03:43.180260
4318 11:03:43.183502 TX Vref Scan disable
4319 11:03:43.187064 == TX Byte 0 ==
4320 11:03:43.189847 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4321 11:03:43.193528 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4322 11:03:43.196524 == TX Byte 1 ==
4323 11:03:43.199998 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4324 11:03:43.203478 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4325 11:03:43.203566
4326 11:03:43.206781 [DATLAT]
4327 11:03:43.206872 Freq=600, CH1 RK0
4328 11:03:43.206956
4329 11:03:43.209792 DATLAT Default: 0x9
4330 11:03:43.209855 0, 0xFFFF, sum = 0
4331 11:03:43.213129 1, 0xFFFF, sum = 0
4332 11:03:43.213204 2, 0xFFFF, sum = 0
4333 11:03:43.216474 3, 0xFFFF, sum = 0
4334 11:03:43.216549 4, 0xFFFF, sum = 0
4335 11:03:43.219999 5, 0xFFFF, sum = 0
4336 11:03:43.220076 6, 0xFFFF, sum = 0
4337 11:03:43.223026 7, 0x0, sum = 1
4338 11:03:43.223101 8, 0x0, sum = 2
4339 11:03:43.226428 9, 0x0, sum = 3
4340 11:03:43.226527 10, 0x0, sum = 4
4341 11:03:43.229670 best_step = 8
4342 11:03:43.229744
4343 11:03:43.229800 ==
4344 11:03:43.233047 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 11:03:43.236398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4346 11:03:43.236473 ==
4347 11:03:43.236529 RX Vref Scan: 1
4348 11:03:43.239547
4349 11:03:43.239620 RX Vref 0 -> 0, step: 1
4350 11:03:43.239677
4351 11:03:43.242991 RX Delay -195 -> 252, step: 8
4352 11:03:43.243065
4353 11:03:43.246099 Set Vref, RX VrefLevel [Byte0]: 53
4354 11:03:43.249404 [Byte1]: 48
4355 11:03:43.253040
4356 11:03:43.253114 Final RX Vref Byte 0 = 53 to rank0
4357 11:03:43.256388 Final RX Vref Byte 1 = 48 to rank0
4358 11:03:43.259608 Final RX Vref Byte 0 = 53 to rank1
4359 11:03:43.262973 Final RX Vref Byte 1 = 48 to rank1==
4360 11:03:43.266185 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 11:03:43.272682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4362 11:03:43.272784 ==
4363 11:03:43.272868 DQS Delay:
4364 11:03:43.272924 DQS0 = 0, DQS1 = 0
4365 11:03:43.276172 DQM Delay:
4366 11:03:43.276246 DQM0 = 37, DQM1 = 31
4367 11:03:43.279663 DQ Delay:
4368 11:03:43.282973 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4369 11:03:43.286397 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4370 11:03:43.289180 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4371 11:03:43.292684 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4372 11:03:43.292818
4373 11:03:43.292909
4374 11:03:43.299216 [DQSOSCAuto] RK0, (LSB)MR18= 0x7d7d, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4375 11:03:43.302663 CH1 RK0: MR19=808, MR18=7D7D
4376 11:03:43.309182 CH1_RK0: MR19=0x808, MR18=0x7D7D, DQSOSC=386, MR23=63, INC=176, DEC=117
4377 11:03:43.309288
4378 11:03:43.312884 ----->DramcWriteLeveling(PI) begin...
4379 11:03:43.312979 ==
4380 11:03:43.315949 Dram Type= 6, Freq= 0, CH_1, rank 1
4381 11:03:43.319183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4382 11:03:43.319259 ==
4383 11:03:43.322509 Write leveling (Byte 0): 27 => 27
4384 11:03:43.325934 Write leveling (Byte 1): 27 => 27
4385 11:03:43.329105 DramcWriteLeveling(PI) end<-----
4386 11:03:43.329181
4387 11:03:43.329264 ==
4388 11:03:43.332341 Dram Type= 6, Freq= 0, CH_1, rank 1
4389 11:03:43.336028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4390 11:03:43.336150 ==
4391 11:03:43.339240 [Gating] SW mode calibration
4392 11:03:43.345529 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4393 11:03:43.352224 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4394 11:03:43.355555 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4395 11:03:43.362229 0 5 4 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
4396 11:03:43.365603 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4397 11:03:43.368729 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 11:03:43.375477 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 11:03:43.378726 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 11:03:43.382310 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 11:03:43.388752 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 11:03:43.392105 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 11:03:43.395575 0 6 4 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
4404 11:03:43.402244 0 6 8 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4405 11:03:43.405204 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 11:03:43.408999 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 11:03:43.415222 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 11:03:43.419149 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 11:03:43.421993 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 11:03:43.425159 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 11:03:43.431761 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 11:03:43.434884 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 11:03:43.439033 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 11:03:43.445191 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 11:03:43.448295 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 11:03:43.451729 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 11:03:43.458142 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 11:03:43.461512 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 11:03:43.465039 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 11:03:43.471732 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 11:03:43.474732 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:03:43.478247 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:03:43.484822 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:03:43.488109 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 11:03:43.491482 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 11:03:43.498483 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 11:03:43.501398 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4428 11:03:43.504457 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4429 11:03:43.507906 Total UI for P1: 0, mck2ui 16
4430 11:03:43.511442 best dqsien dly found for B0: ( 0, 9, 4)
4431 11:03:43.517918 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:03:43.518021 Total UI for P1: 0, mck2ui 16
4433 11:03:43.524830 best dqsien dly found for B1: ( 0, 9, 10)
4434 11:03:43.527694 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4435 11:03:43.531431 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4436 11:03:43.531507
4437 11:03:43.534668 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4438 11:03:43.538220 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4439 11:03:43.541153 [Gating] SW calibration Done
4440 11:03:43.541274 ==
4441 11:03:43.544636 Dram Type= 6, Freq= 0, CH_1, rank 1
4442 11:03:43.548120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4443 11:03:43.548196 ==
4444 11:03:43.550912 RX Vref Scan: 0
4445 11:03:43.550987
4446 11:03:43.551045 RX Vref 0 -> 0, step: 1
4447 11:03:43.551099
4448 11:03:43.554641 RX Delay -230 -> 252, step: 16
4449 11:03:43.561115 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4450 11:03:43.564908 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4451 11:03:43.567778 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4452 11:03:43.571586 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4453 11:03:43.574248 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4454 11:03:43.581183 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4455 11:03:43.584659 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4456 11:03:43.587763 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4457 11:03:43.591046 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4458 11:03:43.594449 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4459 11:03:43.601168 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4460 11:03:43.604300 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4461 11:03:43.607689 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4462 11:03:43.611052 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4463 11:03:43.617605 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4464 11:03:43.621212 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4465 11:03:43.621329 ==
4466 11:03:43.624401 Dram Type= 6, Freq= 0, CH_1, rank 1
4467 11:03:43.627832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4468 11:03:43.627908 ==
4469 11:03:43.631239 DQS Delay:
4470 11:03:43.631314 DQS0 = 0, DQS1 = 0
4471 11:03:43.634329 DQM Delay:
4472 11:03:43.634404 DQM0 = 40, DQM1 = 33
4473 11:03:43.634462 DQ Delay:
4474 11:03:43.637627 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4475 11:03:43.641055 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4476 11:03:43.644119 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4477 11:03:43.647479 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4478 11:03:43.647572
4479 11:03:43.647657
4480 11:03:43.647737 ==
4481 11:03:43.650968 Dram Type= 6, Freq= 0, CH_1, rank 1
4482 11:03:43.657656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4483 11:03:43.657728 ==
4484 11:03:43.657785
4485 11:03:43.657841
4486 11:03:43.660481 TX Vref Scan disable
4487 11:03:43.660578 == TX Byte 0 ==
4488 11:03:43.663970 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4489 11:03:43.670722 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4490 11:03:43.670825 == TX Byte 1 ==
4491 11:03:43.674280 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4492 11:03:43.680398 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4493 11:03:43.680490 ==
4494 11:03:43.683995 Dram Type= 6, Freq= 0, CH_1, rank 1
4495 11:03:43.687129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4496 11:03:43.687196 ==
4497 11:03:43.687259
4498 11:03:43.687321
4499 11:03:43.690593 TX Vref Scan disable
4500 11:03:43.693971 == TX Byte 0 ==
4501 11:03:43.697114 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4502 11:03:43.700907 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4503 11:03:43.703778 == TX Byte 1 ==
4504 11:03:43.707114 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4505 11:03:43.710542 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4506 11:03:43.710611
4507 11:03:43.713692 [DATLAT]
4508 11:03:43.713758 Freq=600, CH1 RK1
4509 11:03:43.713814
4510 11:03:43.716866 DATLAT Default: 0x8
4511 11:03:43.716968 0, 0xFFFF, sum = 0
4512 11:03:43.720289 1, 0xFFFF, sum = 0
4513 11:03:43.720353 2, 0xFFFF, sum = 0
4514 11:03:43.723700 3, 0xFFFF, sum = 0
4515 11:03:43.723799 4, 0xFFFF, sum = 0
4516 11:03:43.726883 5, 0xFFFF, sum = 0
4517 11:03:43.726960 6, 0xFFFF, sum = 0
4518 11:03:43.730463 7, 0x0, sum = 1
4519 11:03:43.730554 8, 0x0, sum = 2
4520 11:03:43.733856 9, 0x0, sum = 3
4521 11:03:43.733920 10, 0x0, sum = 4
4522 11:03:43.733979 best_step = 8
4523 11:03:43.736854
4524 11:03:43.736946 ==
4525 11:03:43.740520 Dram Type= 6, Freq= 0, CH_1, rank 1
4526 11:03:43.743445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4527 11:03:43.743540 ==
4528 11:03:43.743619 RX Vref Scan: 0
4529 11:03:43.743697
4530 11:03:43.747026 RX Vref 0 -> 0, step: 1
4531 11:03:43.747092
4532 11:03:43.750265 RX Delay -195 -> 252, step: 8
4533 11:03:43.756887 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4534 11:03:43.760132 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4535 11:03:43.763858 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4536 11:03:43.766880 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4537 11:03:43.770161 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4538 11:03:43.777009 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4539 11:03:43.780227 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4540 11:03:43.783632 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4541 11:03:43.786904 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4542 11:03:43.793720 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4543 11:03:43.797060 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4544 11:03:43.799922 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4545 11:03:43.803631 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4546 11:03:43.809971 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4547 11:03:43.813361 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4548 11:03:43.816750 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4549 11:03:43.816841 ==
4550 11:03:43.819825 Dram Type= 6, Freq= 0, CH_1, rank 1
4551 11:03:43.823155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4552 11:03:43.826268 ==
4553 11:03:43.826335 DQS Delay:
4554 11:03:43.826391 DQS0 = 0, DQS1 = 0
4555 11:03:43.829801 DQM Delay:
4556 11:03:43.829865 DQM0 = 37, DQM1 = 30
4557 11:03:43.833119 DQ Delay:
4558 11:03:43.833205 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4559 11:03:43.836251 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4560 11:03:43.839573 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4561 11:03:43.843219 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4562 11:03:43.843306
4563 11:03:43.846068
4564 11:03:43.852924 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4565 11:03:43.856351 CH1 RK1: MR19=808, MR18=5E5E
4566 11:03:43.862960 CH1_RK1: MR19=0x808, MR18=0x5E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4567 11:03:43.866500 [RxdqsGatingPostProcess] freq 600
4568 11:03:43.869617 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4569 11:03:43.872782 Pre-setting of DQS Precalculation
4570 11:03:43.879614 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4571 11:03:43.886299 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4572 11:03:43.892613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4573 11:03:43.892746
4574 11:03:43.892842
4575 11:03:43.896407 [Calibration Summary] 1200 Mbps
4576 11:03:43.896495 CH 0, Rank 0
4577 11:03:43.899434 SW Impedance : PASS
4578 11:03:43.902738 DUTY Scan : NO K
4579 11:03:43.902807 ZQ Calibration : PASS
4580 11:03:43.906336 Jitter Meter : NO K
4581 11:03:43.906424 CBT Training : PASS
4582 11:03:43.909308 Write leveling : PASS
4583 11:03:43.912575 RX DQS gating : PASS
4584 11:03:43.912643 RX DQ/DQS(RDDQC) : PASS
4585 11:03:43.915864 TX DQ/DQS : PASS
4586 11:03:43.919495 RX DATLAT : PASS
4587 11:03:43.919586 RX DQ/DQS(Engine): PASS
4588 11:03:43.922615 TX OE : NO K
4589 11:03:43.922710 All Pass.
4590 11:03:43.922794
4591 11:03:43.926124 CH 0, Rank 1
4592 11:03:43.926191 SW Impedance : PASS
4593 11:03:43.929413 DUTY Scan : NO K
4594 11:03:43.932569 ZQ Calibration : PASS
4595 11:03:43.932630 Jitter Meter : NO K
4596 11:03:43.936156 CBT Training : PASS
4597 11:03:43.939412 Write leveling : PASS
4598 11:03:43.939476 RX DQS gating : PASS
4599 11:03:43.942852 RX DQ/DQS(RDDQC) : PASS
4600 11:03:43.945665 TX DQ/DQS : PASS
4601 11:03:43.945755 RX DATLAT : PASS
4602 11:03:43.948812 RX DQ/DQS(Engine): PASS
4603 11:03:43.952187 TX OE : NO K
4604 11:03:43.952256 All Pass.
4605 11:03:43.952312
4606 11:03:43.952363 CH 1, Rank 0
4607 11:03:43.955461 SW Impedance : PASS
4608 11:03:43.959116 DUTY Scan : NO K
4609 11:03:43.959180 ZQ Calibration : PASS
4610 11:03:43.962401 Jitter Meter : NO K
4611 11:03:43.962464 CBT Training : PASS
4612 11:03:43.965674 Write leveling : PASS
4613 11:03:43.968804 RX DQS gating : PASS
4614 11:03:43.968869 RX DQ/DQS(RDDQC) : PASS
4615 11:03:43.972169 TX DQ/DQS : PASS
4616 11:03:43.975452 RX DATLAT : PASS
4617 11:03:43.975543 RX DQ/DQS(Engine): PASS
4618 11:03:43.978813 TX OE : NO K
4619 11:03:43.978903 All Pass.
4620 11:03:43.978982
4621 11:03:43.982197 CH 1, Rank 1
4622 11:03:43.982283 SW Impedance : PASS
4623 11:03:43.985609 DUTY Scan : NO K
4624 11:03:43.988932 ZQ Calibration : PASS
4625 11:03:43.988998 Jitter Meter : NO K
4626 11:03:43.991993 CBT Training : PASS
4627 11:03:43.995351 Write leveling : PASS
4628 11:03:43.995441 RX DQS gating : PASS
4629 11:03:43.998664 RX DQ/DQS(RDDQC) : PASS
4630 11:03:44.002471 TX DQ/DQS : PASS
4631 11:03:44.002568 RX DATLAT : PASS
4632 11:03:44.005563 RX DQ/DQS(Engine): PASS
4633 11:03:44.008674 TX OE : NO K
4634 11:03:44.008768 All Pass.
4635 11:03:44.008851
4636 11:03:44.008935 DramC Write-DBI off
4637 11:03:44.012306 PER_BANK_REFRESH: Hybrid Mode
4638 11:03:44.015658 TX_TRACKING: ON
4639 11:03:44.022036 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4640 11:03:44.025098 [FAST_K] Save calibration result to emmc
4641 11:03:44.032104 dramc_set_vcore_voltage set vcore to 662500
4642 11:03:44.032208 Read voltage for 933, 3
4643 11:03:44.035258 Vio18 = 0
4644 11:03:44.035353 Vcore = 662500
4645 11:03:44.035438 Vdram = 0
4646 11:03:44.035522 Vddq = 0
4647 11:03:44.038736 Vmddr = 0
4648 11:03:44.041740 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4649 11:03:44.048626 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4650 11:03:44.051946 MEM_TYPE=3, freq_sel=17
4651 11:03:44.052038 sv_algorithm_assistance_LP4_1600
4652 11:03:44.058652 ============ PULL DRAM RESETB DOWN ============
4653 11:03:44.061618 ========== PULL DRAM RESETB DOWN end =========
4654 11:03:44.065215 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4655 11:03:44.068471 ===================================
4656 11:03:44.072013 LPDDR4 DRAM CONFIGURATION
4657 11:03:44.075323 ===================================
4658 11:03:44.078418 EX_ROW_EN[0] = 0x0
4659 11:03:44.078506 EX_ROW_EN[1] = 0x0
4660 11:03:44.082046 LP4Y_EN = 0x0
4661 11:03:44.082106 WORK_FSP = 0x0
4662 11:03:44.084878 WL = 0x3
4663 11:03:44.084963 RL = 0x3
4664 11:03:44.088438 BL = 0x2
4665 11:03:44.088502 RPST = 0x0
4666 11:03:44.091698 RD_PRE = 0x0
4667 11:03:44.091786 WR_PRE = 0x1
4668 11:03:44.095239 WR_PST = 0x0
4669 11:03:44.095323 DBI_WR = 0x0
4670 11:03:44.098475 DBI_RD = 0x0
4671 11:03:44.098535 OTF = 0x1
4672 11:03:44.101649 ===================================
4673 11:03:44.104774 ===================================
4674 11:03:44.108603 ANA top config
4675 11:03:44.111213 ===================================
4676 11:03:44.114959 DLL_ASYNC_EN = 0
4677 11:03:44.115034 ALL_SLAVE_EN = 1
4678 11:03:44.118183 NEW_RANK_MODE = 1
4679 11:03:44.121696 DLL_IDLE_MODE = 1
4680 11:03:44.124899 LP45_APHY_COMB_EN = 1
4681 11:03:44.128233 TX_ODT_DIS = 1
4682 11:03:44.128328 NEW_8X_MODE = 1
4683 11:03:44.131775 ===================================
4684 11:03:44.134756 ===================================
4685 11:03:44.138169 data_rate = 1866
4686 11:03:44.141571 CKR = 1
4687 11:03:44.144750 DQ_P2S_RATIO = 8
4688 11:03:44.148146 ===================================
4689 11:03:44.151761 CA_P2S_RATIO = 8
4690 11:03:44.151855 DQ_CA_OPEN = 0
4691 11:03:44.154759 DQ_SEMI_OPEN = 0
4692 11:03:44.158252 CA_SEMI_OPEN = 0
4693 11:03:44.161478 CA_FULL_RATE = 0
4694 11:03:44.165192 DQ_CKDIV4_EN = 1
4695 11:03:44.168233 CA_CKDIV4_EN = 1
4696 11:03:44.168299 CA_PREDIV_EN = 0
4697 11:03:44.171784 PH8_DLY = 0
4698 11:03:44.175002 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4699 11:03:44.178479 DQ_AAMCK_DIV = 4
4700 11:03:44.181737 CA_AAMCK_DIV = 4
4701 11:03:44.184762 CA_ADMCK_DIV = 4
4702 11:03:44.184852 DQ_TRACK_CA_EN = 0
4703 11:03:44.188293 CA_PICK = 933
4704 11:03:44.191511 CA_MCKIO = 933
4705 11:03:44.194934 MCKIO_SEMI = 0
4706 11:03:44.197883 PLL_FREQ = 3732
4707 11:03:44.201181 DQ_UI_PI_RATIO = 32
4708 11:03:44.204739 CA_UI_PI_RATIO = 0
4709 11:03:44.208213 ===================================
4710 11:03:44.211619 ===================================
4711 11:03:44.211716 memory_type:LPDDR4
4712 11:03:44.214592 GP_NUM : 10
4713 11:03:44.217889 SRAM_EN : 1
4714 11:03:44.217982 MD32_EN : 0
4715 11:03:44.221412 ===================================
4716 11:03:44.224692 [ANA_INIT] >>>>>>>>>>>>>>
4717 11:03:44.227842 <<<<<< [CONFIGURE PHASE]: ANA_TX
4718 11:03:44.231177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4719 11:03:44.234605 ===================================
4720 11:03:44.238013 data_rate = 1866,PCW = 0X8f00
4721 11:03:44.241496 ===================================
4722 11:03:44.244478 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4723 11:03:44.247779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4724 11:03:44.254602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4725 11:03:44.257742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4726 11:03:44.261076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4727 11:03:44.264717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4728 11:03:44.268073 [ANA_INIT] flow start
4729 11:03:44.271347 [ANA_INIT] PLL >>>>>>>>
4730 11:03:44.271453 [ANA_INIT] PLL <<<<<<<<
4731 11:03:44.274427 [ANA_INIT] MIDPI >>>>>>>>
4732 11:03:44.277569 [ANA_INIT] MIDPI <<<<<<<<
4733 11:03:44.277663 [ANA_INIT] DLL >>>>>>>>
4734 11:03:44.281155 [ANA_INIT] flow end
4735 11:03:44.284392 ============ LP4 DIFF to SE enter ============
4736 11:03:44.291080 ============ LP4 DIFF to SE exit ============
4737 11:03:44.291174 [ANA_INIT] <<<<<<<<<<<<<
4738 11:03:44.294305 [Flow] Enable top DCM control >>>>>
4739 11:03:44.297792 [Flow] Enable top DCM control <<<<<
4740 11:03:44.300944 Enable DLL master slave shuffle
4741 11:03:44.307681 ==============================================================
4742 11:03:44.307755 Gating Mode config
4743 11:03:44.314424 ==============================================================
4744 11:03:44.317757 Config description:
4745 11:03:44.324095 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4746 11:03:44.330962 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4747 11:03:44.337494 SELPH_MODE 0: By rank 1: By Phase
4748 11:03:44.344231 ==============================================================
4749 11:03:44.344331 GAT_TRACK_EN = 1
4750 11:03:44.347552 RX_GATING_MODE = 2
4751 11:03:44.350524 RX_GATING_TRACK_MODE = 2
4752 11:03:44.354074 SELPH_MODE = 1
4753 11:03:44.357121 PICG_EARLY_EN = 1
4754 11:03:44.360690 VALID_LAT_VALUE = 1
4755 11:03:44.367457 ==============================================================
4756 11:03:44.370585 Enter into Gating configuration >>>>
4757 11:03:44.374056 Exit from Gating configuration <<<<
4758 11:03:44.377148 Enter into DVFS_PRE_config >>>>>
4759 11:03:44.386973 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4760 11:03:44.390446 Exit from DVFS_PRE_config <<<<<
4761 11:03:44.394066 Enter into PICG configuration >>>>
4762 11:03:44.396956 Exit from PICG configuration <<<<
4763 11:03:44.400215 [RX_INPUT] configuration >>>>>
4764 11:03:44.403743 [RX_INPUT] configuration <<<<<
4765 11:03:44.406832 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4766 11:03:44.413667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4767 11:03:44.420345 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4768 11:03:44.423522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4769 11:03:44.430178 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4770 11:03:44.437118 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4771 11:03:44.440495 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4772 11:03:44.443418 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4773 11:03:44.450454 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4774 11:03:44.453162 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4775 11:03:44.456979 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4776 11:03:44.463334 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4777 11:03:44.466499 ===================================
4778 11:03:44.466572 LPDDR4 DRAM CONFIGURATION
4779 11:03:44.470056 ===================================
4780 11:03:44.473364 EX_ROW_EN[0] = 0x0
4781 11:03:44.476560 EX_ROW_EN[1] = 0x0
4782 11:03:44.476633 LP4Y_EN = 0x0
4783 11:03:44.479976 WORK_FSP = 0x0
4784 11:03:44.480057 WL = 0x3
4785 11:03:44.483382 RL = 0x3
4786 11:03:44.483471 BL = 0x2
4787 11:03:44.486603 RPST = 0x0
4788 11:03:44.486676 RD_PRE = 0x0
4789 11:03:44.489813 WR_PRE = 0x1
4790 11:03:44.489887 WR_PST = 0x0
4791 11:03:44.493137 DBI_WR = 0x0
4792 11:03:44.493211 DBI_RD = 0x0
4793 11:03:44.496738 OTF = 0x1
4794 11:03:44.499981 ===================================
4795 11:03:44.503455 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4796 11:03:44.507027 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4797 11:03:44.513264 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4798 11:03:44.516594 ===================================
4799 11:03:44.516658 LPDDR4 DRAM CONFIGURATION
4800 11:03:44.520147 ===================================
4801 11:03:44.523465 EX_ROW_EN[0] = 0x10
4802 11:03:44.523563 EX_ROW_EN[1] = 0x0
4803 11:03:44.526948 LP4Y_EN = 0x0
4804 11:03:44.527039 WORK_FSP = 0x0
4805 11:03:44.529930 WL = 0x3
4806 11:03:44.529997 RL = 0x3
4807 11:03:44.533123 BL = 0x2
4808 11:03:44.536939 RPST = 0x0
4809 11:03:44.537027 RD_PRE = 0x0
4810 11:03:44.540050 WR_PRE = 0x1
4811 11:03:44.540118 WR_PST = 0x0
4812 11:03:44.543328 DBI_WR = 0x0
4813 11:03:44.543417 DBI_RD = 0x0
4814 11:03:44.546505 OTF = 0x1
4815 11:03:44.550097 ===================================
4816 11:03:44.553379 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4817 11:03:44.558562 nWR fixed to 30
4818 11:03:44.562006 [ModeRegInit_LP4] CH0 RK0
4819 11:03:44.562080 [ModeRegInit_LP4] CH0 RK1
4820 11:03:44.565072 [ModeRegInit_LP4] CH1 RK0
4821 11:03:44.568375 [ModeRegInit_LP4] CH1 RK1
4822 11:03:44.568446 match AC timing 8
4823 11:03:44.575238 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4824 11:03:44.578839 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4825 11:03:44.581710 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4826 11:03:44.588552 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4827 11:03:44.591982 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4828 11:03:44.592107 ==
4829 11:03:44.595015 Dram Type= 6, Freq= 0, CH_0, rank 0
4830 11:03:44.598210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4831 11:03:44.598281 ==
4832 11:03:44.604975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4833 11:03:44.611715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4834 11:03:44.614859 [CA 0] Center 38 (8~69) winsize 62
4835 11:03:44.618335 [CA 1] Center 38 (8~69) winsize 62
4836 11:03:44.621714 [CA 2] Center 36 (5~67) winsize 63
4837 11:03:44.624798 [CA 3] Center 35 (5~66) winsize 62
4838 11:03:44.628216 [CA 4] Center 34 (4~65) winsize 62
4839 11:03:44.631993 [CA 5] Center 34 (4~64) winsize 61
4840 11:03:44.632089
4841 11:03:44.634868 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4842 11:03:44.634962
4843 11:03:44.638834 [CATrainingPosCal] consider 1 rank data
4844 11:03:44.642072 u2DelayCellTimex100 = 270/100 ps
4845 11:03:44.645031 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4846 11:03:44.648484 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4847 11:03:44.651599 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4848 11:03:44.655543 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4849 11:03:44.658331 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4850 11:03:44.661792 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4851 11:03:44.664816
4852 11:03:44.668225 CA PerBit enable=1, Macro0, CA PI delay=34
4853 11:03:44.668319
4854 11:03:44.671606 [CBTSetCACLKResult] CA Dly = 34
4855 11:03:44.671703 CS Dly: 7 (0~38)
4856 11:03:44.671787 ==
4857 11:03:44.674872 Dram Type= 6, Freq= 0, CH_0, rank 1
4858 11:03:44.677964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4859 11:03:44.678039 ==
4860 11:03:44.684723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4861 11:03:44.691443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4862 11:03:44.694746 [CA 0] Center 38 (8~69) winsize 62
4863 11:03:44.698076 [CA 1] Center 38 (7~69) winsize 63
4864 11:03:44.701117 [CA 2] Center 36 (6~67) winsize 62
4865 11:03:44.704548 [CA 3] Center 35 (5~66) winsize 62
4866 11:03:44.707849 [CA 4] Center 34 (4~64) winsize 61
4867 11:03:44.711803 [CA 5] Center 34 (4~65) winsize 62
4868 11:03:44.711895
4869 11:03:44.714405 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4870 11:03:44.714473
4871 11:03:44.717656 [CATrainingPosCal] consider 2 rank data
4872 11:03:44.721115 u2DelayCellTimex100 = 270/100 ps
4873 11:03:44.724377 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4874 11:03:44.727730 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4875 11:03:44.731052 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4876 11:03:44.734422 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4877 11:03:44.737638 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4878 11:03:44.744415 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4879 11:03:44.744485
4880 11:03:44.747747 CA PerBit enable=1, Macro0, CA PI delay=34
4881 11:03:44.747840
4882 11:03:44.751358 [CBTSetCACLKResult] CA Dly = 34
4883 11:03:44.751452 CS Dly: 7 (0~39)
4884 11:03:44.751536
4885 11:03:44.754167 ----->DramcWriteLeveling(PI) begin...
4886 11:03:44.754251 ==
4887 11:03:44.757799 Dram Type= 6, Freq= 0, CH_0, rank 0
4888 11:03:44.764057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4889 11:03:44.764133 ==
4890 11:03:44.767763 Write leveling (Byte 0): 27 => 27
4891 11:03:44.767832 Write leveling (Byte 1): 27 => 27
4892 11:03:44.771107 DramcWriteLeveling(PI) end<-----
4893 11:03:44.771175
4894 11:03:44.774669 ==
4895 11:03:44.774734 Dram Type= 6, Freq= 0, CH_0, rank 0
4896 11:03:44.780910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4897 11:03:44.781002 ==
4898 11:03:44.784245 [Gating] SW mode calibration
4899 11:03:44.790816 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4900 11:03:44.794245 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4901 11:03:44.800557 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4902 11:03:44.804015 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4903 11:03:44.807234 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4904 11:03:44.813938 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4905 11:03:44.817095 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4906 11:03:44.820734 0 10 20 | B1->B0 | 3232 2f2f | 0 1 | (0 1) (0 0)
4907 11:03:44.827022 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4908 11:03:44.830197 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4909 11:03:44.833964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4910 11:03:44.841025 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4911 11:03:44.843807 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4912 11:03:44.847162 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4913 11:03:44.853693 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4914 11:03:44.857481 0 11 20 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
4915 11:03:44.860339 0 11 24 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4916 11:03:44.867273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4917 11:03:44.870102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4918 11:03:44.873990 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4919 11:03:44.877086 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4920 11:03:44.884093 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4921 11:03:44.887109 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4922 11:03:44.890463 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4923 11:03:44.897136 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4924 11:03:44.900121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4925 11:03:44.903370 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4926 11:03:44.910220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4927 11:03:44.913401 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 11:03:44.916691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 11:03:44.923518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 11:03:44.926780 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 11:03:44.930314 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 11:03:44.936631 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 11:03:44.940190 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 11:03:44.943222 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 11:03:44.949934 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 11:03:44.953412 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 11:03:44.956866 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 11:03:44.963440 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 11:03:44.966280 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4940 11:03:44.970035 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4941 11:03:44.973315 Total UI for P1: 0, mck2ui 16
4942 11:03:44.976735 best dqsien dly found for B0: ( 0, 14, 24)
4943 11:03:44.980243 Total UI for P1: 0, mck2ui 16
4944 11:03:44.983468 best dqsien dly found for B1: ( 0, 14, 24)
4945 11:03:44.986945 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
4946 11:03:44.989871 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
4947 11:03:44.989945
4948 11:03:44.996488 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 24)
4949 11:03:45.000134 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
4950 11:03:45.003184 [Gating] SW calibration Done
4951 11:03:45.003258 ==
4952 11:03:45.006221 Dram Type= 6, Freq= 0, CH_0, rank 0
4953 11:03:45.009801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4954 11:03:45.009876 ==
4955 11:03:45.009934 RX Vref Scan: 0
4956 11:03:45.010012
4957 11:03:45.012806 RX Vref 0 -> 0, step: 1
4958 11:03:45.012880
4959 11:03:45.016390 RX Delay -80 -> 252, step: 8
4960 11:03:45.020102 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4961 11:03:45.023092 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4962 11:03:45.026462 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4963 11:03:45.032719 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4964 11:03:45.036224 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4965 11:03:45.039661 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4966 11:03:45.042917 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4967 11:03:45.045942 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4968 11:03:45.052580 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4969 11:03:45.055856 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4970 11:03:45.059264 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4971 11:03:45.062665 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
4972 11:03:45.065962 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4973 11:03:45.069290 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4974 11:03:45.075897 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4975 11:03:45.079375 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4976 11:03:45.079450 ==
4977 11:03:45.082335 Dram Type= 6, Freq= 0, CH_0, rank 0
4978 11:03:45.085831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4979 11:03:45.085907 ==
4980 11:03:45.089138 DQS Delay:
4981 11:03:45.089213 DQS0 = 0, DQS1 = 0
4982 11:03:45.089312 DQM Delay:
4983 11:03:45.092505 DQM0 = 95, DQM1 = 85
4984 11:03:45.092579 DQ Delay:
4985 11:03:45.095717 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4986 11:03:45.098856 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
4987 11:03:45.102322 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
4988 11:03:45.105525 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4989 11:03:45.105599
4990 11:03:45.105657
4991 11:03:45.105709 ==
4992 11:03:45.109248 Dram Type= 6, Freq= 0, CH_0, rank 0
4993 11:03:45.115752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4994 11:03:45.115828 ==
4995 11:03:45.115886
4996 11:03:45.115939
4997 11:03:45.115989 TX Vref Scan disable
4998 11:03:45.119327 == TX Byte 0 ==
4999 11:03:45.122310 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5000 11:03:45.129430 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5001 11:03:45.129506 == TX Byte 1 ==
5002 11:03:45.132419 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5003 11:03:45.138958 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5004 11:03:45.139036 ==
5005 11:03:45.142473 Dram Type= 6, Freq= 0, CH_0, rank 0
5006 11:03:45.145706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5007 11:03:45.145781 ==
5008 11:03:45.145840
5009 11:03:45.145893
5010 11:03:45.149049 TX Vref Scan disable
5011 11:03:45.149124 == TX Byte 0 ==
5012 11:03:45.155620 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5013 11:03:45.159092 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5014 11:03:45.159167 == TX Byte 1 ==
5015 11:03:45.165783 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5016 11:03:45.168938 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5017 11:03:45.169012
5018 11:03:45.169070 [DATLAT]
5019 11:03:45.172274 Freq=933, CH0 RK0
5020 11:03:45.172382
5021 11:03:45.172477 DATLAT Default: 0xd
5022 11:03:45.175612 0, 0xFFFF, sum = 0
5023 11:03:45.175688 1, 0xFFFF, sum = 0
5024 11:03:45.178779 2, 0xFFFF, sum = 0
5025 11:03:45.178856 3, 0xFFFF, sum = 0
5026 11:03:45.182403 4, 0xFFFF, sum = 0
5027 11:03:45.185485 5, 0xFFFF, sum = 0
5028 11:03:45.185563 6, 0xFFFF, sum = 0
5029 11:03:45.188790 7, 0xFFFF, sum = 0
5030 11:03:45.188865 8, 0xFFFF, sum = 0
5031 11:03:45.192131 9, 0xFFFF, sum = 0
5032 11:03:45.192206 10, 0x0, sum = 1
5033 11:03:45.195708 11, 0x0, sum = 2
5034 11:03:45.195784 12, 0x0, sum = 3
5035 11:03:45.195844 13, 0x0, sum = 4
5036 11:03:45.199152 best_step = 11
5037 11:03:45.199226
5038 11:03:45.199283 ==
5039 11:03:45.202042 Dram Type= 6, Freq= 0, CH_0, rank 0
5040 11:03:45.205525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5041 11:03:45.205599 ==
5042 11:03:45.208919 RX Vref Scan: 1
5043 11:03:45.208992
5044 11:03:45.209050 RX Vref 0 -> 0, step: 1
5045 11:03:45.212174
5046 11:03:45.212241 RX Delay -69 -> 252, step: 4
5047 11:03:45.212300
5048 11:03:45.215543 Set Vref, RX VrefLevel [Byte0]: 50
5049 11:03:45.219067 [Byte1]: 52
5050 11:03:45.223483
5051 11:03:45.223557 Final RX Vref Byte 0 = 50 to rank0
5052 11:03:45.226527 Final RX Vref Byte 1 = 52 to rank0
5053 11:03:45.229922 Final RX Vref Byte 0 = 50 to rank1
5054 11:03:45.233260 Final RX Vref Byte 1 = 52 to rank1==
5055 11:03:45.236214 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 11:03:45.242948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 11:03:45.243040 ==
5058 11:03:45.243113 DQS Delay:
5059 11:03:45.246076 DQS0 = 0, DQS1 = 0
5060 11:03:45.246149 DQM Delay:
5061 11:03:45.246206 DQM0 = 97, DQM1 = 87
5062 11:03:45.249515 DQ Delay:
5063 11:03:45.253405 DQ0 =92, DQ1 =98, DQ2 =98, DQ3 =92
5064 11:03:45.256409 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5065 11:03:45.259720 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5066 11:03:45.262954 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5067 11:03:45.263046
5068 11:03:45.263134
5069 11:03:45.269255 [DQSOSCAuto] RK0, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5070 11:03:45.272663 CH0 RK0: MR19=505, MR18=2020
5071 11:03:45.279277 CH0_RK0: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5072 11:03:45.279353
5073 11:03:45.282854 ----->DramcWriteLeveling(PI) begin...
5074 11:03:45.282947 ==
5075 11:03:45.286207 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 11:03:45.289616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5077 11:03:45.289695 ==
5078 11:03:45.292654 Write leveling (Byte 0): 29 => 29
5079 11:03:45.296413 Write leveling (Byte 1): 28 => 28
5080 11:03:45.299348 DramcWriteLeveling(PI) end<-----
5081 11:03:45.299423
5082 11:03:45.299481 ==
5083 11:03:45.302497 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 11:03:45.305964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5085 11:03:45.306040 ==
5086 11:03:45.309185 [Gating] SW mode calibration
5087 11:03:45.316013 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5088 11:03:45.322681 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5089 11:03:45.325895 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 11:03:45.332671 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 11:03:45.336149 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 11:03:45.339355 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 11:03:45.345861 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 11:03:45.349333 0 10 20 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 0)
5095 11:03:45.352411 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
5096 11:03:45.359231 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 11:03:45.362403 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 11:03:45.365556 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 11:03:45.369101 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 11:03:45.375983 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 11:03:45.379276 0 11 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5102 11:03:45.382124 0 11 20 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (1 1)
5103 11:03:45.389110 0 11 24 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
5104 11:03:45.392129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 11:03:45.395334 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 11:03:45.402142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 11:03:45.405522 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 11:03:45.409156 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 11:03:45.415640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 11:03:45.418758 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5111 11:03:45.422020 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5112 11:03:45.428921 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 11:03:45.431951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 11:03:45.435565 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 11:03:45.442131 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 11:03:45.445579 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 11:03:45.448738 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 11:03:45.455303 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:03:45.459041 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:03:45.461800 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 11:03:45.468636 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 11:03:45.471815 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 11:03:45.475233 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 11:03:45.481816 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 11:03:45.485168 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:03:45.488587 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5127 11:03:45.495100 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:03:45.495176 Total UI for P1: 0, mck2ui 16
5129 11:03:45.501991 best dqsien dly found for B0: ( 0, 14, 20)
5130 11:03:45.502106 Total UI for P1: 0, mck2ui 16
5131 11:03:45.508432 best dqsien dly found for B1: ( 0, 14, 20)
5132 11:03:45.511725 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5133 11:03:45.515465 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5134 11:03:45.515541
5135 11:03:45.518561 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5136 11:03:45.521893 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5137 11:03:45.525075 [Gating] SW calibration Done
5138 11:03:45.525152 ==
5139 11:03:45.528363 Dram Type= 6, Freq= 0, CH_0, rank 1
5140 11:03:45.531661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5141 11:03:45.531737 ==
5142 11:03:45.534841 RX Vref Scan: 0
5143 11:03:45.534916
5144 11:03:45.534974 RX Vref 0 -> 0, step: 1
5145 11:03:45.535028
5146 11:03:45.538490 RX Delay -80 -> 252, step: 8
5147 11:03:45.541437 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5148 11:03:45.548411 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5149 11:03:45.551716 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5150 11:03:45.554636 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5151 11:03:45.558326 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5152 11:03:45.561814 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5153 11:03:45.564969 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5154 11:03:45.571403 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5155 11:03:45.575549 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5156 11:03:45.578198 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5157 11:03:45.581441 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5158 11:03:45.585004 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5159 11:03:45.591600 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5160 11:03:45.594527 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5161 11:03:45.597960 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5162 11:03:45.601192 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5163 11:03:45.601311 ==
5164 11:03:45.604419 Dram Type= 6, Freq= 0, CH_0, rank 1
5165 11:03:45.607789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5166 11:03:45.607857 ==
5167 11:03:45.611129 DQS Delay:
5168 11:03:45.611190 DQS0 = 0, DQS1 = 0
5169 11:03:45.614520 DQM Delay:
5170 11:03:45.614592 DQM0 = 95, DQM1 = 86
5171 11:03:45.614651 DQ Delay:
5172 11:03:45.617996 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5173 11:03:45.621058 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5174 11:03:45.624963 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5175 11:03:45.628147 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5176 11:03:45.628219
5177 11:03:45.628275
5178 11:03:45.631019 ==
5179 11:03:45.634452 Dram Type= 6, Freq= 0, CH_0, rank 1
5180 11:03:45.638097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5181 11:03:45.638171 ==
5182 11:03:45.638228
5183 11:03:45.638279
5184 11:03:45.641017 TX Vref Scan disable
5185 11:03:45.641082 == TX Byte 0 ==
5186 11:03:45.644312 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5187 11:03:45.651043 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5188 11:03:45.651119 == TX Byte 1 ==
5189 11:03:45.654366 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5190 11:03:45.660806 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5191 11:03:45.660873 ==
5192 11:03:45.664096 Dram Type= 6, Freq= 0, CH_0, rank 1
5193 11:03:45.667561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5194 11:03:45.667630 ==
5195 11:03:45.667688
5196 11:03:45.667740
5197 11:03:45.670675 TX Vref Scan disable
5198 11:03:45.674055 == TX Byte 0 ==
5199 11:03:45.677701 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5200 11:03:45.680728 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5201 11:03:45.684347 == TX Byte 1 ==
5202 11:03:45.687747 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5203 11:03:45.690909 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5204 11:03:45.690983
5205 11:03:45.694004 [DATLAT]
5206 11:03:45.694078 Freq=933, CH0 RK1
5207 11:03:45.694136
5208 11:03:45.697827 DATLAT Default: 0xb
5209 11:03:45.697902 0, 0xFFFF, sum = 0
5210 11:03:45.700641 1, 0xFFFF, sum = 0
5211 11:03:45.700716 2, 0xFFFF, sum = 0
5212 11:03:45.704605 3, 0xFFFF, sum = 0
5213 11:03:45.704680 4, 0xFFFF, sum = 0
5214 11:03:45.707396 5, 0xFFFF, sum = 0
5215 11:03:45.707471 6, 0xFFFF, sum = 0
5216 11:03:45.710985 7, 0xFFFF, sum = 0
5217 11:03:45.711060 8, 0xFFFF, sum = 0
5218 11:03:45.714043 9, 0xFFFF, sum = 0
5219 11:03:45.714116 10, 0x0, sum = 1
5220 11:03:45.717379 11, 0x0, sum = 2
5221 11:03:45.717454 12, 0x0, sum = 3
5222 11:03:45.721086 13, 0x0, sum = 4
5223 11:03:45.721162 best_step = 11
5224 11:03:45.721220
5225 11:03:45.721316 ==
5226 11:03:45.723935 Dram Type= 6, Freq= 0, CH_0, rank 1
5227 11:03:45.727479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5228 11:03:45.730718 ==
5229 11:03:45.730792 RX Vref Scan: 0
5230 11:03:45.730849
5231 11:03:45.734677 RX Vref 0 -> 0, step: 1
5232 11:03:45.734751
5233 11:03:45.737417 RX Delay -77 -> 252, step: 4
5234 11:03:45.740909 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5235 11:03:45.743883 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5236 11:03:45.747320 iDelay=203, Bit 2, Center 94 (-1 ~ 190) 192
5237 11:03:45.754119 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5238 11:03:45.757163 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5239 11:03:45.760912 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5240 11:03:45.763882 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5241 11:03:45.767274 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5242 11:03:45.774187 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5243 11:03:45.777560 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5244 11:03:45.780561 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5245 11:03:45.783868 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5246 11:03:45.787083 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5247 11:03:45.790540 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5248 11:03:45.797158 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5249 11:03:45.800441 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5250 11:03:45.800515 ==
5251 11:03:45.803987 Dram Type= 6, Freq= 0, CH_0, rank 1
5252 11:03:45.807295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5253 11:03:45.807369 ==
5254 11:03:45.810651 DQS Delay:
5255 11:03:45.810725 DQS0 = 0, DQS1 = 0
5256 11:03:45.810782 DQM Delay:
5257 11:03:45.813704 DQM0 = 97, DQM1 = 86
5258 11:03:45.813778 DQ Delay:
5259 11:03:45.817075 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5260 11:03:45.820428 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =108
5261 11:03:45.823699 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5262 11:03:45.826865 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5263 11:03:45.826939
5264 11:03:45.826996
5265 11:03:45.837564 [DQSOSCAuto] RK1, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5266 11:03:45.837639 CH0 RK1: MR19=505, MR18=3434
5267 11:03:45.843434 CH0_RK1: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5268 11:03:45.846834 [RxdqsGatingPostProcess] freq 933
5269 11:03:45.853420 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5270 11:03:45.856852 Pre-setting of DQS Precalculation
5271 11:03:45.859978 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5272 11:03:45.860056 ==
5273 11:03:45.863408 Dram Type= 6, Freq= 0, CH_1, rank 0
5274 11:03:45.870005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5275 11:03:45.870080 ==
5276 11:03:45.873331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5277 11:03:45.879926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5278 11:03:45.883340 [CA 0] Center 37 (7~68) winsize 62
5279 11:03:45.886908 [CA 1] Center 37 (6~68) winsize 63
5280 11:03:45.889961 [CA 2] Center 34 (4~65) winsize 62
5281 11:03:45.893190 [CA 3] Center 34 (4~65) winsize 62
5282 11:03:45.896598 [CA 4] Center 32 (2~63) winsize 62
5283 11:03:45.900070 [CA 5] Center 33 (3~64) winsize 62
5284 11:03:45.900144
5285 11:03:45.903078 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5286 11:03:45.903152
5287 11:03:45.906264 [CATrainingPosCal] consider 1 rank data
5288 11:03:45.909790 u2DelayCellTimex100 = 270/100 ps
5289 11:03:45.912786 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5290 11:03:45.919513 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5291 11:03:45.922701 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5292 11:03:45.925978 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5293 11:03:45.929272 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5294 11:03:45.933001 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5295 11:03:45.933076
5296 11:03:45.936237 CA PerBit enable=1, Macro0, CA PI delay=32
5297 11:03:45.936311
5298 11:03:45.939407 [CBTSetCACLKResult] CA Dly = 32
5299 11:03:45.942432 CS Dly: 5 (0~36)
5300 11:03:45.942505 ==
5301 11:03:45.946343 Dram Type= 6, Freq= 0, CH_1, rank 1
5302 11:03:45.949686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5303 11:03:45.949762 ==
5304 11:03:45.955939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5305 11:03:45.959036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5306 11:03:45.963312 [CA 0] Center 37 (6~68) winsize 63
5307 11:03:45.966830 [CA 1] Center 37 (6~68) winsize 63
5308 11:03:45.969821 [CA 2] Center 34 (4~65) winsize 62
5309 11:03:45.973179 [CA 3] Center 34 (4~64) winsize 61
5310 11:03:45.976565 [CA 4] Center 33 (2~64) winsize 63
5311 11:03:45.979622 [CA 5] Center 33 (3~64) winsize 62
5312 11:03:45.979696
5313 11:03:45.982945 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5314 11:03:45.983019
5315 11:03:45.986233 [CATrainingPosCal] consider 2 rank data
5316 11:03:45.990236 u2DelayCellTimex100 = 270/100 ps
5317 11:03:45.992884 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5318 11:03:45.996543 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5319 11:03:46.003361 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5320 11:03:46.006351 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5321 11:03:46.009699 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5322 11:03:46.013272 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5323 11:03:46.013346
5324 11:03:46.016482 CA PerBit enable=1, Macro0, CA PI delay=32
5325 11:03:46.016555
5326 11:03:46.019997 [CBTSetCACLKResult] CA Dly = 32
5327 11:03:46.020070 CS Dly: 5 (0~37)
5328 11:03:46.023100
5329 11:03:46.026398 ----->DramcWriteLeveling(PI) begin...
5330 11:03:46.026473 ==
5331 11:03:46.030338 Dram Type= 6, Freq= 0, CH_1, rank 0
5332 11:03:46.033044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5333 11:03:46.033112 ==
5334 11:03:46.036090 Write leveling (Byte 0): 24 => 24
5335 11:03:46.039480 Write leveling (Byte 1): 24 => 24
5336 11:03:46.042726 DramcWriteLeveling(PI) end<-----
5337 11:03:46.042799
5338 11:03:46.042855 ==
5339 11:03:46.045895 Dram Type= 6, Freq= 0, CH_1, rank 0
5340 11:03:46.049364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5341 11:03:46.049447 ==
5342 11:03:46.052701 [Gating] SW mode calibration
5343 11:03:46.059178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5344 11:03:46.066068 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5345 11:03:46.069376 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 11:03:46.072985 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 11:03:46.079533 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 11:03:46.082570 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 11:03:46.085804 0 10 16 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
5350 11:03:46.092493 0 10 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
5351 11:03:46.095987 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5352 11:03:46.099169 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 11:03:46.105663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 11:03:46.109190 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 11:03:46.112322 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 11:03:46.119270 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 11:03:46.122651 0 11 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5358 11:03:46.125522 0 11 20 | B1->B0 | 2828 4343 | 0 0 | (0 0) (0 0)
5359 11:03:46.132370 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5360 11:03:46.136099 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 11:03:46.138875 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 11:03:46.145731 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 11:03:46.149118 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 11:03:46.152123 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 11:03:46.155514 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5366 11:03:46.162024 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 11:03:46.165388 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 11:03:46.168751 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 11:03:46.175588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 11:03:46.178714 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 11:03:46.182175 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 11:03:46.188815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:03:46.192028 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:03:46.195336 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:03:46.201898 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:03:46.205119 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:03:46.208354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:03:46.215452 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:03:46.218606 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:03:46.221790 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5381 11:03:46.228309 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5382 11:03:46.231653 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 11:03:46.234769 Total UI for P1: 0, mck2ui 16
5384 11:03:46.238237 best dqsien dly found for B0: ( 0, 14, 14)
5385 11:03:46.241686 Total UI for P1: 0, mck2ui 16
5386 11:03:46.245101 best dqsien dly found for B1: ( 0, 14, 18)
5387 11:03:46.248159 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5388 11:03:46.251402 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5389 11:03:46.251477
5390 11:03:46.254852 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5391 11:03:46.258118 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5392 11:03:46.261265 [Gating] SW calibration Done
5393 11:03:46.261354 ==
5394 11:03:46.265174 Dram Type= 6, Freq= 0, CH_1, rank 0
5395 11:03:46.271635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5396 11:03:46.271711 ==
5397 11:03:46.271770 RX Vref Scan: 0
5398 11:03:46.271825
5399 11:03:46.274596 RX Vref 0 -> 0, step: 1
5400 11:03:46.274671
5401 11:03:46.277956 RX Delay -80 -> 252, step: 8
5402 11:03:46.281192 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5403 11:03:46.284820 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5404 11:03:46.288353 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5405 11:03:46.291417 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5406 11:03:46.297858 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5407 11:03:46.301182 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5408 11:03:46.304568 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5409 11:03:46.308021 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5410 11:03:46.311506 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5411 11:03:46.314783 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5412 11:03:46.321554 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5413 11:03:46.324690 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5414 11:03:46.327890 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5415 11:03:46.331736 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5416 11:03:46.334819 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5417 11:03:46.341197 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5418 11:03:46.341336 ==
5419 11:03:46.344769 Dram Type= 6, Freq= 0, CH_1, rank 0
5420 11:03:46.348089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5421 11:03:46.348168 ==
5422 11:03:46.348226 DQS Delay:
5423 11:03:46.351703 DQS0 = 0, DQS1 = 0
5424 11:03:46.351777 DQM Delay:
5425 11:03:46.354400 DQM0 = 94, DQM1 = 86
5426 11:03:46.354474 DQ Delay:
5427 11:03:46.357681 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5428 11:03:46.361577 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5429 11:03:46.364250 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5430 11:03:46.367646 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =95
5431 11:03:46.367719
5432 11:03:46.367786
5433 11:03:46.367842 ==
5434 11:03:46.371168 Dram Type= 6, Freq= 0, CH_1, rank 0
5435 11:03:46.374236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5436 11:03:46.378052 ==
5437 11:03:46.378125
5438 11:03:46.378181
5439 11:03:46.378233 TX Vref Scan disable
5440 11:03:46.381222 == TX Byte 0 ==
5441 11:03:46.384529 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5442 11:03:46.387541 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5443 11:03:46.391175 == TX Byte 1 ==
5444 11:03:46.394156 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5445 11:03:46.397790 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5446 11:03:46.400927 ==
5447 11:03:46.400999 Dram Type= 6, Freq= 0, CH_1, rank 0
5448 11:03:46.407760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5449 11:03:46.407834 ==
5450 11:03:46.407891
5451 11:03:46.407943
5452 11:03:46.410626 TX Vref Scan disable
5453 11:03:46.410699 == TX Byte 0 ==
5454 11:03:46.417582 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5455 11:03:46.420712 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5456 11:03:46.420785 == TX Byte 1 ==
5457 11:03:46.427531 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5458 11:03:46.430870 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5459 11:03:46.430945
5460 11:03:46.431003 [DATLAT]
5461 11:03:46.434147 Freq=933, CH1 RK0
5462 11:03:46.434221
5463 11:03:46.434278 DATLAT Default: 0xd
5464 11:03:46.437553 0, 0xFFFF, sum = 0
5465 11:03:46.437639 1, 0xFFFF, sum = 0
5466 11:03:46.440601 2, 0xFFFF, sum = 0
5467 11:03:46.440676 3, 0xFFFF, sum = 0
5468 11:03:46.444042 4, 0xFFFF, sum = 0
5469 11:03:46.444117 5, 0xFFFF, sum = 0
5470 11:03:46.447088 6, 0xFFFF, sum = 0
5471 11:03:46.447164 7, 0xFFFF, sum = 0
5472 11:03:46.450777 8, 0xFFFF, sum = 0
5473 11:03:46.450868 9, 0xFFFF, sum = 0
5474 11:03:46.454004 10, 0x0, sum = 1
5475 11:03:46.454079 11, 0x0, sum = 2
5476 11:03:46.457369 12, 0x0, sum = 3
5477 11:03:46.457448 13, 0x0, sum = 4
5478 11:03:46.460637 best_step = 11
5479 11:03:46.460711
5480 11:03:46.460768 ==
5481 11:03:46.463922 Dram Type= 6, Freq= 0, CH_1, rank 0
5482 11:03:46.466921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5483 11:03:46.466991 ==
5484 11:03:46.470621 RX Vref Scan: 1
5485 11:03:46.470712
5486 11:03:46.470793 RX Vref 0 -> 0, step: 1
5487 11:03:46.470872
5488 11:03:46.474017 RX Delay -69 -> 252, step: 4
5489 11:03:46.474091
5490 11:03:46.477403 Set Vref, RX VrefLevel [Byte0]: 53
5491 11:03:46.480491 [Byte1]: 48
5492 11:03:46.484575
5493 11:03:46.484679 Final RX Vref Byte 0 = 53 to rank0
5494 11:03:46.487575 Final RX Vref Byte 1 = 48 to rank0
5495 11:03:46.490959 Final RX Vref Byte 0 = 53 to rank1
5496 11:03:46.494684 Final RX Vref Byte 1 = 48 to rank1==
5497 11:03:46.498113 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 11:03:46.504403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5499 11:03:46.504480 ==
5500 11:03:46.504538 DQS Delay:
5501 11:03:46.507930 DQS0 = 0, DQS1 = 0
5502 11:03:46.508029 DQM Delay:
5503 11:03:46.508119 DQM0 = 94, DQM1 = 87
5504 11:03:46.510772 DQ Delay:
5505 11:03:46.514441 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5506 11:03:46.517739 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5507 11:03:46.521103 DQ8 =70, DQ9 =76, DQ10 =88, DQ11 =80
5508 11:03:46.524445 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5509 11:03:46.524520
5510 11:03:46.524578
5511 11:03:46.530718 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5512 11:03:46.534296 CH1 RK0: MR19=505, MR18=3535
5513 11:03:46.540547 CH1_RK0: MR19=0x505, MR18=0x3535, DQSOSC=405, MR23=63, INC=66, DEC=44
5514 11:03:46.540623
5515 11:03:46.544292 ----->DramcWriteLeveling(PI) begin...
5516 11:03:46.544368 ==
5517 11:03:46.547400 Dram Type= 6, Freq= 0, CH_1, rank 1
5518 11:03:46.550658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5519 11:03:46.550734 ==
5520 11:03:46.554076 Write leveling (Byte 0): 25 => 25
5521 11:03:46.557481 Write leveling (Byte 1): 25 => 25
5522 11:03:46.560766 DramcWriteLeveling(PI) end<-----
5523 11:03:46.560865
5524 11:03:46.560949 ==
5525 11:03:46.563964 Dram Type= 6, Freq= 0, CH_1, rank 1
5526 11:03:46.567043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5527 11:03:46.570333 ==
5528 11:03:46.570432 [Gating] SW mode calibration
5529 11:03:46.577258 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5530 11:03:46.584126 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5531 11:03:46.587144 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5532 11:03:46.593811 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5533 11:03:46.597243 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5534 11:03:46.600323 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5535 11:03:46.607114 0 10 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
5536 11:03:46.610086 0 10 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5537 11:03:46.613532 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5538 11:03:46.620364 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5539 11:03:46.623626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5540 11:03:46.627194 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 11:03:46.633621 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5542 11:03:46.637136 0 11 12 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
5543 11:03:46.640387 0 11 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5544 11:03:46.647031 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
5545 11:03:46.650159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5546 11:03:46.653605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5547 11:03:46.656977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 11:03:46.663596 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 11:03:46.666931 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 11:03:46.669841 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5551 11:03:46.676491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5552 11:03:46.680109 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5553 11:03:46.683266 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5554 11:03:46.689833 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5555 11:03:46.693129 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 11:03:46.696544 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 11:03:46.703293 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 11:03:46.706117 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 11:03:46.709935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 11:03:46.716581 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 11:03:46.719845 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 11:03:46.723100 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:03:46.729356 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:03:46.733158 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:03:46.736209 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:03:46.743141 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5567 11:03:46.746022 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5568 11:03:46.749783 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 11:03:46.752922 Total UI for P1: 0, mck2ui 16
5570 11:03:46.756074 best dqsien dly found for B0: ( 0, 14, 14)
5571 11:03:46.759504 Total UI for P1: 0, mck2ui 16
5572 11:03:46.762895 best dqsien dly found for B1: ( 0, 14, 16)
5573 11:03:46.766335 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5574 11:03:46.769274 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5575 11:03:46.772647
5576 11:03:46.776438 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5577 11:03:46.779355 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5578 11:03:46.782852 [Gating] SW calibration Done
5579 11:03:46.782926 ==
5580 11:03:46.785857 Dram Type= 6, Freq= 0, CH_1, rank 1
5581 11:03:46.789076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5582 11:03:46.789150 ==
5583 11:03:46.789207 RX Vref Scan: 0
5584 11:03:46.789310
5585 11:03:46.792475 RX Vref 0 -> 0, step: 1
5586 11:03:46.792548
5587 11:03:46.795905 RX Delay -80 -> 252, step: 8
5588 11:03:46.798962 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5589 11:03:46.802304 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5590 11:03:46.808995 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5591 11:03:46.812178 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5592 11:03:46.815606 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5593 11:03:46.818869 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5594 11:03:46.822364 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5595 11:03:46.825551 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5596 11:03:46.831970 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5597 11:03:46.835884 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5598 11:03:46.838663 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5599 11:03:46.841959 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5600 11:03:46.845721 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5601 11:03:46.851844 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5602 11:03:46.855164 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5603 11:03:46.858650 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5604 11:03:46.858725 ==
5605 11:03:46.862076 Dram Type= 6, Freq= 0, CH_1, rank 1
5606 11:03:46.865084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5607 11:03:46.865158 ==
5608 11:03:46.868652 DQS Delay:
5609 11:03:46.868732 DQS0 = 0, DQS1 = 0
5610 11:03:46.871747 DQM Delay:
5611 11:03:46.871844 DQM0 = 95, DQM1 = 86
5612 11:03:46.871928 DQ Delay:
5613 11:03:46.875093 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91
5614 11:03:46.878329 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5615 11:03:46.881796 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5616 11:03:46.884685 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5617 11:03:46.884774
5618 11:03:46.884856
5619 11:03:46.888101 ==
5620 11:03:46.891634 Dram Type= 6, Freq= 0, CH_1, rank 1
5621 11:03:46.894606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5622 11:03:46.894697 ==
5623 11:03:46.894780
5624 11:03:46.894858
5625 11:03:46.897965 TX Vref Scan disable
5626 11:03:46.898057 == TX Byte 0 ==
5627 11:03:46.901558 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5628 11:03:46.907881 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5629 11:03:46.907961 == TX Byte 1 ==
5630 11:03:46.911617 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5631 11:03:46.918147 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5632 11:03:46.918219 ==
5633 11:03:46.921554 Dram Type= 6, Freq= 0, CH_1, rank 1
5634 11:03:46.925078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5635 11:03:46.925152 ==
5636 11:03:46.925259
5637 11:03:46.925354
5638 11:03:46.927987 TX Vref Scan disable
5639 11:03:46.931311 == TX Byte 0 ==
5640 11:03:46.934724 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5641 11:03:46.937926 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5642 11:03:46.941094 == TX Byte 1 ==
5643 11:03:46.944195 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5644 11:03:46.947760 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5645 11:03:46.947851
5646 11:03:46.951129 [DATLAT]
5647 11:03:46.951220 Freq=933, CH1 RK1
5648 11:03:46.951304
5649 11:03:46.954492 DATLAT Default: 0xb
5650 11:03:46.954560 0, 0xFFFF, sum = 0
5651 11:03:46.957552 1, 0xFFFF, sum = 0
5652 11:03:46.957618 2, 0xFFFF, sum = 0
5653 11:03:46.961099 3, 0xFFFF, sum = 0
5654 11:03:46.961196 4, 0xFFFF, sum = 0
5655 11:03:46.964068 5, 0xFFFF, sum = 0
5656 11:03:46.964138 6, 0xFFFF, sum = 0
5657 11:03:46.967386 7, 0xFFFF, sum = 0
5658 11:03:46.967447 8, 0xFFFF, sum = 0
5659 11:03:46.971078 9, 0xFFFF, sum = 0
5660 11:03:46.971174 10, 0x0, sum = 1
5661 11:03:46.973956 11, 0x0, sum = 2
5662 11:03:46.974051 12, 0x0, sum = 3
5663 11:03:46.977654 13, 0x0, sum = 4
5664 11:03:46.977747 best_step = 11
5665 11:03:46.977827
5666 11:03:46.977905 ==
5667 11:03:46.980594 Dram Type= 6, Freq= 0, CH_1, rank 1
5668 11:03:46.987316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5669 11:03:46.987402 ==
5670 11:03:46.987482 RX Vref Scan: 0
5671 11:03:46.987558
5672 11:03:46.990961 RX Vref 0 -> 0, step: 1
5673 11:03:46.991047
5674 11:03:46.993990 RX Delay -77 -> 252, step: 4
5675 11:03:46.997504 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5676 11:03:47.000446 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5677 11:03:47.007457 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5678 11:03:47.010595 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5679 11:03:47.013860 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5680 11:03:47.017389 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5681 11:03:47.020678 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5682 11:03:47.023842 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5683 11:03:47.030784 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5684 11:03:47.033773 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5685 11:03:47.036896 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5686 11:03:47.040186 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5687 11:03:47.043813 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5688 11:03:47.050443 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5689 11:03:47.053940 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5690 11:03:47.057130 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5691 11:03:47.057233 ==
5692 11:03:47.060359 Dram Type= 6, Freq= 0, CH_1, rank 1
5693 11:03:47.063560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5694 11:03:47.063635 ==
5695 11:03:47.067028 DQS Delay:
5696 11:03:47.067105 DQS0 = 0, DQS1 = 0
5697 11:03:47.070042 DQM Delay:
5698 11:03:47.070108 DQM0 = 96, DQM1 = 87
5699 11:03:47.070163 DQ Delay:
5700 11:03:47.073558 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =94
5701 11:03:47.076589 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =96
5702 11:03:47.080171 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =78
5703 11:03:47.083470 DQ12 =96, DQ13 =98, DQ14 =94, DQ15 =96
5704 11:03:47.083559
5705 11:03:47.083642
5706 11:03:47.093140 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5707 11:03:47.096441 CH1 RK1: MR19=505, MR18=2A2A
5708 11:03:47.103115 CH1_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5709 11:03:47.103212 [RxdqsGatingPostProcess] freq 933
5710 11:03:47.110046 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5711 11:03:47.113211 Pre-setting of DQS Precalculation
5712 11:03:47.119633 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5713 11:03:47.126603 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5714 11:03:47.132794 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5715 11:03:47.132891
5716 11:03:47.132975
5717 11:03:47.136486 [Calibration Summary] 1866 Mbps
5718 11:03:47.136551 CH 0, Rank 0
5719 11:03:47.139575 SW Impedance : PASS
5720 11:03:47.142640 DUTY Scan : NO K
5721 11:03:47.142730 ZQ Calibration : PASS
5722 11:03:47.146010 Jitter Meter : NO K
5723 11:03:47.146102 CBT Training : PASS
5724 11:03:47.149513 Write leveling : PASS
5725 11:03:47.152828 RX DQS gating : PASS
5726 11:03:47.152898 RX DQ/DQS(RDDQC) : PASS
5727 11:03:47.156124 TX DQ/DQS : PASS
5728 11:03:47.159144 RX DATLAT : PASS
5729 11:03:47.159237 RX DQ/DQS(Engine): PASS
5730 11:03:47.162573 TX OE : NO K
5731 11:03:47.162641 All Pass.
5732 11:03:47.162696
5733 11:03:47.165761 CH 0, Rank 1
5734 11:03:47.165829 SW Impedance : PASS
5735 11:03:47.169287 DUTY Scan : NO K
5736 11:03:47.172536 ZQ Calibration : PASS
5737 11:03:47.172628 Jitter Meter : NO K
5738 11:03:47.176400 CBT Training : PASS
5739 11:03:47.179122 Write leveling : PASS
5740 11:03:47.179186 RX DQS gating : PASS
5741 11:03:47.182596 RX DQ/DQS(RDDQC) : PASS
5742 11:03:47.185620 TX DQ/DQS : PASS
5743 11:03:47.185714 RX DATLAT : PASS
5744 11:03:47.188858 RX DQ/DQS(Engine): PASS
5745 11:03:47.192511 TX OE : NO K
5746 11:03:47.192579 All Pass.
5747 11:03:47.192634
5748 11:03:47.192689 CH 1, Rank 0
5749 11:03:47.195619 SW Impedance : PASS
5750 11:03:47.198834 DUTY Scan : NO K
5751 11:03:47.198903 ZQ Calibration : PASS
5752 11:03:47.202250 Jitter Meter : NO K
5753 11:03:47.205646 CBT Training : PASS
5754 11:03:47.205707 Write leveling : PASS
5755 11:03:47.208712 RX DQS gating : PASS
5756 11:03:47.208771 RX DQ/DQS(RDDQC) : PASS
5757 11:03:47.212274 TX DQ/DQS : PASS
5758 11:03:47.215756 RX DATLAT : PASS
5759 11:03:47.215827 RX DQ/DQS(Engine): PASS
5760 11:03:47.218989 TX OE : NO K
5761 11:03:47.219081 All Pass.
5762 11:03:47.219163
5763 11:03:47.222193 CH 1, Rank 1
5764 11:03:47.222278 SW Impedance : PASS
5765 11:03:47.225969 DUTY Scan : NO K
5766 11:03:47.228594 ZQ Calibration : PASS
5767 11:03:47.228665 Jitter Meter : NO K
5768 11:03:47.231998 CBT Training : PASS
5769 11:03:47.235489 Write leveling : PASS
5770 11:03:47.235579 RX DQS gating : PASS
5771 11:03:47.239060 RX DQ/DQS(RDDQC) : PASS
5772 11:03:47.242404 TX DQ/DQS : PASS
5773 11:03:47.242491 RX DATLAT : PASS
5774 11:03:47.245494 RX DQ/DQS(Engine): PASS
5775 11:03:47.248659 TX OE : NO K
5776 11:03:47.248748 All Pass.
5777 11:03:47.248830
5778 11:03:47.248910 DramC Write-DBI off
5779 11:03:47.251991 PER_BANK_REFRESH: Hybrid Mode
5780 11:03:47.255474 TX_TRACKING: ON
5781 11:03:47.261988 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5782 11:03:47.268631 [FAST_K] Save calibration result to emmc
5783 11:03:47.271913 dramc_set_vcore_voltage set vcore to 650000
5784 11:03:47.272010 Read voltage for 400, 6
5785 11:03:47.274948 Vio18 = 0
5786 11:03:47.275039 Vcore = 650000
5787 11:03:47.275123 Vdram = 0
5788 11:03:47.278606 Vddq = 0
5789 11:03:47.278676 Vmddr = 0
5790 11:03:47.281622 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5791 11:03:47.288523 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5792 11:03:47.291515 MEM_TYPE=3, freq_sel=20
5793 11:03:47.295077 sv_algorithm_assistance_LP4_800
5794 11:03:47.298218 ============ PULL DRAM RESETB DOWN ============
5795 11:03:47.301573 ========== PULL DRAM RESETB DOWN end =========
5796 11:03:47.304879 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5797 11:03:47.308347 ===================================
5798 11:03:47.311421 LPDDR4 DRAM CONFIGURATION
5799 11:03:47.315063 ===================================
5800 11:03:47.318187 EX_ROW_EN[0] = 0x0
5801 11:03:47.318253 EX_ROW_EN[1] = 0x0
5802 11:03:47.321592 LP4Y_EN = 0x0
5803 11:03:47.321662 WORK_FSP = 0x0
5804 11:03:47.324799 WL = 0x2
5805 11:03:47.324891 RL = 0x2
5806 11:03:47.328249 BL = 0x2
5807 11:03:47.331457 RPST = 0x0
5808 11:03:47.331550 RD_PRE = 0x0
5809 11:03:47.334893 WR_PRE = 0x1
5810 11:03:47.334963 WR_PST = 0x0
5811 11:03:47.338148 DBI_WR = 0x0
5812 11:03:47.338211 DBI_RD = 0x0
5813 11:03:47.341570 OTF = 0x1
5814 11:03:47.344481 ===================================
5815 11:03:47.348333 ===================================
5816 11:03:47.348415 ANA top config
5817 11:03:47.351350 ===================================
5818 11:03:47.354338 DLL_ASYNC_EN = 0
5819 11:03:47.357880 ALL_SLAVE_EN = 1
5820 11:03:47.357973 NEW_RANK_MODE = 1
5821 11:03:47.360792 DLL_IDLE_MODE = 1
5822 11:03:47.364211 LP45_APHY_COMB_EN = 1
5823 11:03:47.367860 TX_ODT_DIS = 1
5824 11:03:47.370764 NEW_8X_MODE = 1
5825 11:03:47.374224 ===================================
5826 11:03:47.374324 ===================================
5827 11:03:47.377933 data_rate = 800
5828 11:03:47.380816 CKR = 1
5829 11:03:47.384389 DQ_P2S_RATIO = 4
5830 11:03:47.387287 ===================================
5831 11:03:47.390721 CA_P2S_RATIO = 4
5832 11:03:47.393924 DQ_CA_OPEN = 0
5833 11:03:47.397560 DQ_SEMI_OPEN = 1
5834 11:03:47.397628 CA_SEMI_OPEN = 1
5835 11:03:47.400472 CA_FULL_RATE = 0
5836 11:03:47.403704 DQ_CKDIV4_EN = 0
5837 11:03:47.407313 CA_CKDIV4_EN = 1
5838 11:03:47.410600 CA_PREDIV_EN = 0
5839 11:03:47.413847 PH8_DLY = 0
5840 11:03:47.413940 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5841 11:03:47.417188 DQ_AAMCK_DIV = 0
5842 11:03:47.420575 CA_AAMCK_DIV = 0
5843 11:03:47.423751 CA_ADMCK_DIV = 4
5844 11:03:47.427266 DQ_TRACK_CA_EN = 0
5845 11:03:47.430774 CA_PICK = 800
5846 11:03:47.433536 CA_MCKIO = 400
5847 11:03:47.433598 MCKIO_SEMI = 400
5848 11:03:47.436760 PLL_FREQ = 3016
5849 11:03:47.440424 DQ_UI_PI_RATIO = 32
5850 11:03:47.443706 CA_UI_PI_RATIO = 32
5851 11:03:47.446708 ===================================
5852 11:03:47.450301 ===================================
5853 11:03:47.453759 memory_type:LPDDR4
5854 11:03:47.453819 GP_NUM : 10
5855 11:03:47.456953 SRAM_EN : 1
5856 11:03:47.459860 MD32_EN : 0
5857 11:03:47.464042 ===================================
5858 11:03:47.464128 [ANA_INIT] >>>>>>>>>>>>>>
5859 11:03:47.466798 <<<<<< [CONFIGURE PHASE]: ANA_TX
5860 11:03:47.470027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5861 11:03:47.473631 ===================================
5862 11:03:47.476888 data_rate = 800,PCW = 0X7400
5863 11:03:47.479834 ===================================
5864 11:03:47.483382 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5865 11:03:47.490000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5866 11:03:47.499624 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5867 11:03:47.506235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5868 11:03:47.509641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5869 11:03:47.512869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5870 11:03:47.512960 [ANA_INIT] flow start
5871 11:03:47.516209 [ANA_INIT] PLL >>>>>>>>
5872 11:03:47.519807 [ANA_INIT] PLL <<<<<<<<
5873 11:03:47.519895 [ANA_INIT] MIDPI >>>>>>>>
5874 11:03:47.523481 [ANA_INIT] MIDPI <<<<<<<<
5875 11:03:47.526094 [ANA_INIT] DLL >>>>>>>>
5876 11:03:47.526183 [ANA_INIT] flow end
5877 11:03:47.532740 ============ LP4 DIFF to SE enter ============
5878 11:03:47.536022 ============ LP4 DIFF to SE exit ============
5879 11:03:47.539366 [ANA_INIT] <<<<<<<<<<<<<
5880 11:03:47.542818 [Flow] Enable top DCM control >>>>>
5881 11:03:47.546100 [Flow] Enable top DCM control <<<<<
5882 11:03:47.546190 Enable DLL master slave shuffle
5883 11:03:47.552464 ==============================================================
5884 11:03:47.556256 Gating Mode config
5885 11:03:47.559162 ==============================================================
5886 11:03:47.562799 Config description:
5887 11:03:47.572513 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5888 11:03:47.579061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5889 11:03:47.582372 SELPH_MODE 0: By rank 1: By Phase
5890 11:03:47.588907 ==============================================================
5891 11:03:47.592253 GAT_TRACK_EN = 0
5892 11:03:47.595898 RX_GATING_MODE = 2
5893 11:03:47.599087 RX_GATING_TRACK_MODE = 2
5894 11:03:47.602316 SELPH_MODE = 1
5895 11:03:47.605241 PICG_EARLY_EN = 1
5896 11:03:47.605320 VALID_LAT_VALUE = 1
5897 11:03:47.612266 ==============================================================
5898 11:03:47.615305 Enter into Gating configuration >>>>
5899 11:03:47.619094 Exit from Gating configuration <<<<
5900 11:03:47.622370 Enter into DVFS_PRE_config >>>>>
5901 11:03:47.631710 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5902 11:03:47.635056 Exit from DVFS_PRE_config <<<<<
5903 11:03:47.638374 Enter into PICG configuration >>>>
5904 11:03:47.641836 Exit from PICG configuration <<<<
5905 11:03:47.645040 [RX_INPUT] configuration >>>>>
5906 11:03:47.648579 [RX_INPUT] configuration <<<<<
5907 11:03:47.654974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5908 11:03:47.658584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5909 11:03:47.664804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5910 11:03:47.671655 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5911 11:03:47.678324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5912 11:03:47.685132 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5913 11:03:47.688833 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5914 11:03:47.691458 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5915 11:03:47.695318 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5916 11:03:47.701558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5917 11:03:47.704794 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5918 11:03:47.708639 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5919 11:03:47.711572 ===================================
5920 11:03:47.714709 LPDDR4 DRAM CONFIGURATION
5921 11:03:47.718323 ===================================
5922 11:03:47.718417 EX_ROW_EN[0] = 0x0
5923 11:03:47.721979 EX_ROW_EN[1] = 0x0
5924 11:03:47.724521 LP4Y_EN = 0x0
5925 11:03:47.724592 WORK_FSP = 0x0
5926 11:03:47.728057 WL = 0x2
5927 11:03:47.728151 RL = 0x2
5928 11:03:47.731376 BL = 0x2
5929 11:03:47.731472 RPST = 0x0
5930 11:03:47.734983 RD_PRE = 0x0
5931 11:03:47.735081 WR_PRE = 0x1
5932 11:03:47.738320 WR_PST = 0x0
5933 11:03:47.738412 DBI_WR = 0x0
5934 11:03:47.741039 DBI_RD = 0x0
5935 11:03:47.741127 OTF = 0x1
5936 11:03:47.744359 ===================================
5937 11:03:47.747695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5938 11:03:47.754676 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5939 11:03:47.757551 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5940 11:03:47.761112 ===================================
5941 11:03:47.764244 LPDDR4 DRAM CONFIGURATION
5942 11:03:47.767629 ===================================
5943 11:03:47.767727 EX_ROW_EN[0] = 0x10
5944 11:03:47.770645 EX_ROW_EN[1] = 0x0
5945 11:03:47.774140 LP4Y_EN = 0x0
5946 11:03:47.774230 WORK_FSP = 0x0
5947 11:03:47.777527 WL = 0x2
5948 11:03:47.777600 RL = 0x2
5949 11:03:47.780716 BL = 0x2
5950 11:03:47.780807 RPST = 0x0
5951 11:03:47.784292 RD_PRE = 0x0
5952 11:03:47.784385 WR_PRE = 0x1
5953 11:03:47.787391 WR_PST = 0x0
5954 11:03:47.787467 DBI_WR = 0x0
5955 11:03:47.790660 DBI_RD = 0x0
5956 11:03:47.790736 OTF = 0x1
5957 11:03:47.794067 ===================================
5958 11:03:47.800429 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5959 11:03:47.805192 nWR fixed to 30
5960 11:03:47.808063 [ModeRegInit_LP4] CH0 RK0
5961 11:03:47.808138 [ModeRegInit_LP4] CH0 RK1
5962 11:03:47.811726 [ModeRegInit_LP4] CH1 RK0
5963 11:03:47.815428 [ModeRegInit_LP4] CH1 RK1
5964 11:03:47.815504 match AC timing 18
5965 11:03:47.821575 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5966 11:03:47.825222 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5967 11:03:47.828340 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5968 11:03:47.834680 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5969 11:03:47.838113 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5970 11:03:47.838187 ==
5971 11:03:47.841976 Dram Type= 6, Freq= 0, CH_0, rank 0
5972 11:03:47.844720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5973 11:03:47.844796 ==
5974 11:03:47.851519 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5975 11:03:47.858421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5976 11:03:47.861494 [CA 0] Center 36 (8~64) winsize 57
5977 11:03:47.864586 [CA 1] Center 36 (8~64) winsize 57
5978 11:03:47.867898 [CA 2] Center 36 (8~64) winsize 57
5979 11:03:47.867973 [CA 3] Center 36 (8~64) winsize 57
5980 11:03:47.871195 [CA 4] Center 36 (8~64) winsize 57
5981 11:03:47.874485 [CA 5] Center 36 (8~64) winsize 57
5982 11:03:47.874560
5983 11:03:47.881317 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5984 11:03:47.881396
5985 11:03:47.884646 [CATrainingPosCal] consider 1 rank data
5986 11:03:47.887747 u2DelayCellTimex100 = 270/100 ps
5987 11:03:47.891252 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5988 11:03:47.894671 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5989 11:03:47.897560 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5990 11:03:47.901106 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5991 11:03:47.904592 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5992 11:03:47.907738 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5993 11:03:47.907813
5994 11:03:47.910880 CA PerBit enable=1, Macro0, CA PI delay=36
5995 11:03:47.910979
5996 11:03:47.914328 [CBTSetCACLKResult] CA Dly = 36
5997 11:03:47.917755 CS Dly: 1 (0~32)
5998 11:03:47.917830 ==
5999 11:03:47.921319 Dram Type= 6, Freq= 0, CH_0, rank 1
6000 11:03:47.924234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6001 11:03:47.924326 ==
6002 11:03:47.930984 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6003 11:03:47.934432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6004 11:03:47.937455 [CA 0] Center 36 (8~64) winsize 57
6005 11:03:47.940900 [CA 1] Center 36 (8~64) winsize 57
6006 11:03:47.943950 [CA 2] Center 36 (8~64) winsize 57
6007 11:03:47.947736 [CA 3] Center 36 (8~64) winsize 57
6008 11:03:47.950672 [CA 4] Center 36 (8~64) winsize 57
6009 11:03:47.954234 [CA 5] Center 36 (8~64) winsize 57
6010 11:03:47.954313
6011 11:03:47.957157 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6012 11:03:47.957256
6013 11:03:47.960907 [CATrainingPosCal] consider 2 rank data
6014 11:03:47.964356 u2DelayCellTimex100 = 270/100 ps
6015 11:03:47.967589 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6016 11:03:47.970712 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6017 11:03:47.977594 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6018 11:03:47.980784 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6019 11:03:47.984114 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 11:03:47.987373 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 11:03:47.987448
6022 11:03:47.990567 CA PerBit enable=1, Macro0, CA PI delay=36
6023 11:03:47.990643
6024 11:03:47.994118 [CBTSetCACLKResult] CA Dly = 36
6025 11:03:47.994192 CS Dly: 1 (0~32)
6026 11:03:47.994251
6027 11:03:47.997179 ----->DramcWriteLeveling(PI) begin...
6028 11:03:48.000512 ==
6029 11:03:48.000588 Dram Type= 6, Freq= 0, CH_0, rank 0
6030 11:03:48.007351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6031 11:03:48.007426 ==
6032 11:03:48.010863 Write leveling (Byte 0): 32 => 0
6033 11:03:48.014161 Write leveling (Byte 1): 32 => 0
6034 11:03:48.014236 DramcWriteLeveling(PI) end<-----
6035 11:03:48.017502
6036 11:03:48.017575 ==
6037 11:03:48.020401 Dram Type= 6, Freq= 0, CH_0, rank 0
6038 11:03:48.023963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6039 11:03:48.024038 ==
6040 11:03:48.027326 [Gating] SW mode calibration
6041 11:03:48.033731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6042 11:03:48.037448 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6043 11:03:48.043616 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6044 11:03:48.047352 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6045 11:03:48.050401 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6046 11:03:48.057001 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6047 11:03:48.060399 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6048 11:03:48.063639 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6049 11:03:48.070360 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6050 11:03:48.073753 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6051 11:03:48.077132 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6052 11:03:48.080732 Total UI for P1: 0, mck2ui 16
6053 11:03:48.083667 best dqsien dly found for B0: ( 0, 10, 16)
6054 11:03:48.086899 Total UI for P1: 0, mck2ui 16
6055 11:03:48.090216 best dqsien dly found for B1: ( 0, 10, 24)
6056 11:03:48.093939 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6057 11:03:48.097062 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6058 11:03:48.097128
6059 11:03:48.103488 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6060 11:03:48.106860 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6061 11:03:48.110274 [Gating] SW calibration Done
6062 11:03:48.110344 ==
6063 11:03:48.113800 Dram Type= 6, Freq= 0, CH_0, rank 0
6064 11:03:48.116703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6065 11:03:48.116767 ==
6066 11:03:48.116828 RX Vref Scan: 0
6067 11:03:48.116879
6068 11:03:48.120485 RX Vref 0 -> 0, step: 1
6069 11:03:48.120548
6070 11:03:48.123624 RX Delay -410 -> 252, step: 16
6071 11:03:48.126952 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6072 11:03:48.133353 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6073 11:03:48.136477 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6074 11:03:48.140114 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6075 11:03:48.143051 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6076 11:03:48.149998 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6077 11:03:48.153378 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6078 11:03:48.156958 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6079 11:03:48.159959 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6080 11:03:48.166485 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6081 11:03:48.169597 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6082 11:03:48.173451 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6083 11:03:48.176887 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6084 11:03:48.183175 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6085 11:03:48.186386 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6086 11:03:48.190061 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6087 11:03:48.190128 ==
6088 11:03:48.193161 Dram Type= 6, Freq= 0, CH_0, rank 0
6089 11:03:48.199829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6090 11:03:48.199906 ==
6091 11:03:48.199964 DQS Delay:
6092 11:03:48.200018 DQS0 = 59, DQS1 = 59
6093 11:03:48.202965 DQM Delay:
6094 11:03:48.203041 DQM0 = 19, DQM1 = 12
6095 11:03:48.206290 DQ Delay:
6096 11:03:48.209576 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6097 11:03:48.212878 DQ4 =24, DQ5 =0, DQ6 =32, DQ7 =32
6098 11:03:48.212953 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6099 11:03:48.216220 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6100 11:03:48.216320
6101 11:03:48.219811
6102 11:03:48.219885 ==
6103 11:03:48.223119 Dram Type= 6, Freq= 0, CH_0, rank 0
6104 11:03:48.226252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6105 11:03:48.226326 ==
6106 11:03:48.226384
6107 11:03:48.226438
6108 11:03:48.229610 TX Vref Scan disable
6109 11:03:48.229687 == TX Byte 0 ==
6110 11:03:48.232900 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6111 11:03:48.239790 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6112 11:03:48.239865 == TX Byte 1 ==
6113 11:03:48.243019 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6114 11:03:48.249795 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6115 11:03:48.249870 ==
6116 11:03:48.252989 Dram Type= 6, Freq= 0, CH_0, rank 0
6117 11:03:48.256211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6118 11:03:48.256286 ==
6119 11:03:48.256344
6120 11:03:48.256396
6121 11:03:48.259668 TX Vref Scan disable
6122 11:03:48.259768 == TX Byte 0 ==
6123 11:03:48.266233 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6124 11:03:48.269416 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6125 11:03:48.269492 == TX Byte 1 ==
6126 11:03:48.275965 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6127 11:03:48.279349 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6128 11:03:48.279448
6129 11:03:48.279533 [DATLAT]
6130 11:03:48.282907 Freq=400, CH0 RK0
6131 11:03:48.282981
6132 11:03:48.283039 DATLAT Default: 0xf
6133 11:03:48.286540 0, 0xFFFF, sum = 0
6134 11:03:48.286616 1, 0xFFFF, sum = 0
6135 11:03:48.289695 2, 0xFFFF, sum = 0
6136 11:03:48.289771 3, 0xFFFF, sum = 0
6137 11:03:48.292922 4, 0xFFFF, sum = 0
6138 11:03:48.293025 5, 0xFFFF, sum = 0
6139 11:03:48.296267 6, 0xFFFF, sum = 0
6140 11:03:48.296361 7, 0xFFFF, sum = 0
6141 11:03:48.299570 8, 0xFFFF, sum = 0
6142 11:03:48.299642 9, 0xFFFF, sum = 0
6143 11:03:48.302678 10, 0xFFFF, sum = 0
6144 11:03:48.306423 11, 0xFFFF, sum = 0
6145 11:03:48.306526 12, 0x0, sum = 1
6146 11:03:48.306618 13, 0x0, sum = 2
6147 11:03:48.309731 14, 0x0, sum = 3
6148 11:03:48.309807 15, 0x0, sum = 4
6149 11:03:48.312981 best_step = 13
6150 11:03:48.313055
6151 11:03:48.313113 ==
6152 11:03:48.316340 Dram Type= 6, Freq= 0, CH_0, rank 0
6153 11:03:48.319358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6154 11:03:48.319433 ==
6155 11:03:48.322838 RX Vref Scan: 1
6156 11:03:48.322913
6157 11:03:48.322971 RX Vref 0 -> 0, step: 1
6158 11:03:48.323025
6159 11:03:48.325835 RX Delay -359 -> 252, step: 8
6160 11:03:48.325910
6161 11:03:48.329572 Set Vref, RX VrefLevel [Byte0]: 50
6162 11:03:48.332565 [Byte1]: 52
6163 11:03:48.337704
6164 11:03:48.337778 Final RX Vref Byte 0 = 50 to rank0
6165 11:03:48.340921 Final RX Vref Byte 1 = 52 to rank0
6166 11:03:48.344685 Final RX Vref Byte 0 = 50 to rank1
6167 11:03:48.347545 Final RX Vref Byte 1 = 52 to rank1==
6168 11:03:48.350921 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 11:03:48.357448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 11:03:48.357524 ==
6171 11:03:48.357583 DQS Delay:
6172 11:03:48.360900 DQS0 = 52, DQS1 = 68
6173 11:03:48.360974 DQM Delay:
6174 11:03:48.361032 DQM0 = 9, DQM1 = 17
6175 11:03:48.364414 DQ Delay:
6176 11:03:48.367707 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6177 11:03:48.367782 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6178 11:03:48.371311 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6179 11:03:48.374103 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28
6180 11:03:48.374177
6181 11:03:48.374238
6182 11:03:48.383922 [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6183 11:03:48.387464 CH0 RK0: MR19=C0C, MR18=ADAD
6184 11:03:48.394036 CH0_RK0: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6185 11:03:48.394116 ==
6186 11:03:48.397497 Dram Type= 6, Freq= 0, CH_0, rank 1
6187 11:03:48.400789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6188 11:03:48.400863 ==
6189 11:03:48.404094 [Gating] SW mode calibration
6190 11:03:48.410900 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6191 11:03:48.413822 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6192 11:03:48.420364 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6193 11:03:48.423639 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6194 11:03:48.427104 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6195 11:03:48.433627 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6196 11:03:48.437033 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6197 11:03:48.440327 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6198 11:03:48.446923 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6199 11:03:48.450805 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6200 11:03:48.453819 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6201 11:03:48.456837 Total UI for P1: 0, mck2ui 16
6202 11:03:48.460002 best dqsien dly found for B0: ( 0, 10, 16)
6203 11:03:48.463330 Total UI for P1: 0, mck2ui 16
6204 11:03:48.467053 best dqsien dly found for B1: ( 0, 10, 16)
6205 11:03:48.470349 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6206 11:03:48.476649 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6207 11:03:48.476724
6208 11:03:48.480292 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6209 11:03:48.483256 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6210 11:03:48.487014 [Gating] SW calibration Done
6211 11:03:48.487090 ==
6212 11:03:48.490039 Dram Type= 6, Freq= 0, CH_0, rank 1
6213 11:03:48.493277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6214 11:03:48.493352 ==
6215 11:03:48.496718 RX Vref Scan: 0
6216 11:03:48.496792
6217 11:03:48.496851 RX Vref 0 -> 0, step: 1
6218 11:03:48.496907
6219 11:03:48.500234 RX Delay -410 -> 252, step: 16
6220 11:03:48.503523 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6221 11:03:48.509843 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6222 11:03:48.513089 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6223 11:03:48.516496 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6224 11:03:48.519901 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6225 11:03:48.526215 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6226 11:03:48.529652 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6227 11:03:48.533259 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6228 11:03:48.536265 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6229 11:03:48.542952 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6230 11:03:48.546239 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6231 11:03:48.549678 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6232 11:03:48.556745 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6233 11:03:48.560194 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6234 11:03:48.562950 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6235 11:03:48.566308 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6236 11:03:48.566372 ==
6237 11:03:48.569410 Dram Type= 6, Freq= 0, CH_0, rank 1
6238 11:03:48.576344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6239 11:03:48.576421 ==
6240 11:03:48.576480 DQS Delay:
6241 11:03:48.579542 DQS0 = 51, DQS1 = 59
6242 11:03:48.579606 DQM Delay:
6243 11:03:48.582950 DQM0 = 13, DQM1 = 13
6244 11:03:48.583012 DQ Delay:
6245 11:03:48.586072 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6246 11:03:48.589401 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6247 11:03:48.589464 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6248 11:03:48.596019 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6249 11:03:48.596084
6250 11:03:48.596141
6251 11:03:48.596193 ==
6252 11:03:48.599416 Dram Type= 6, Freq= 0, CH_0, rank 1
6253 11:03:48.602785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6254 11:03:48.602849 ==
6255 11:03:48.602902
6256 11:03:48.602955
6257 11:03:48.606198 TX Vref Scan disable
6258 11:03:48.606262 == TX Byte 0 ==
6259 11:03:48.609229 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6260 11:03:48.615791 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6261 11:03:48.615861 == TX Byte 1 ==
6262 11:03:48.619307 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6263 11:03:48.626003 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6264 11:03:48.626075 ==
6265 11:03:48.629301 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 11:03:48.632554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6267 11:03:48.632696 ==
6268 11:03:48.632830
6269 11:03:48.632913
6270 11:03:48.636059 TX Vref Scan disable
6271 11:03:48.636134 == TX Byte 0 ==
6272 11:03:48.642476 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6273 11:03:48.645966 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6274 11:03:48.646041 == TX Byte 1 ==
6275 11:03:48.649012 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6276 11:03:48.655727 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6277 11:03:48.655828
6278 11:03:48.655911 [DATLAT]
6279 11:03:48.659263 Freq=400, CH0 RK1
6280 11:03:48.659337
6281 11:03:48.659396 DATLAT Default: 0xd
6282 11:03:48.662335 0, 0xFFFF, sum = 0
6283 11:03:48.662412 1, 0xFFFF, sum = 0
6284 11:03:48.666225 2, 0xFFFF, sum = 0
6285 11:03:48.666301 3, 0xFFFF, sum = 0
6286 11:03:48.669169 4, 0xFFFF, sum = 0
6287 11:03:48.669294 5, 0xFFFF, sum = 0
6288 11:03:48.672732 6, 0xFFFF, sum = 0
6289 11:03:48.672808 7, 0xFFFF, sum = 0
6290 11:03:48.675941 8, 0xFFFF, sum = 0
6291 11:03:48.676017 9, 0xFFFF, sum = 0
6292 11:03:48.679116 10, 0xFFFF, sum = 0
6293 11:03:48.679218 11, 0xFFFF, sum = 0
6294 11:03:48.682299 12, 0x0, sum = 1
6295 11:03:48.682375 13, 0x0, sum = 2
6296 11:03:48.685739 14, 0x0, sum = 3
6297 11:03:48.685815 15, 0x0, sum = 4
6298 11:03:48.688777 best_step = 13
6299 11:03:48.688865
6300 11:03:48.688922 ==
6301 11:03:48.692357 Dram Type= 6, Freq= 0, CH_0, rank 1
6302 11:03:48.695636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6303 11:03:48.695719 ==
6304 11:03:48.699302 RX Vref Scan: 0
6305 11:03:48.699375
6306 11:03:48.699434 RX Vref 0 -> 0, step: 1
6307 11:03:48.699487
6308 11:03:48.701985 RX Delay -359 -> 252, step: 8
6309 11:03:48.710368 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6310 11:03:48.713731 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6311 11:03:48.716871 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6312 11:03:48.720291 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6313 11:03:48.726711 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6314 11:03:48.729880 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6315 11:03:48.733691 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6316 11:03:48.737056 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6317 11:03:48.743633 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6318 11:03:48.746611 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6319 11:03:48.750236 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6320 11:03:48.753338 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6321 11:03:48.760123 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6322 11:03:48.763291 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6323 11:03:48.767055 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6324 11:03:48.773254 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6325 11:03:48.773342 ==
6326 11:03:48.776521 Dram Type= 6, Freq= 0, CH_0, rank 1
6327 11:03:48.779741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6328 11:03:48.779816 ==
6329 11:03:48.779874 DQS Delay:
6330 11:03:48.783346 DQS0 = 52, DQS1 = 64
6331 11:03:48.783420 DQM Delay:
6332 11:03:48.786477 DQM0 = 11, DQM1 = 14
6333 11:03:48.786551 DQ Delay:
6334 11:03:48.790194 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6335 11:03:48.793092 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6336 11:03:48.796578 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6337 11:03:48.799879 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6338 11:03:48.799954
6339 11:03:48.800011
6340 11:03:48.806414 [DQSOSCAuto] RK1, (LSB)MR18= 0xcbcb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6341 11:03:48.809661 CH0 RK1: MR19=C0C, MR18=CBCB
6342 11:03:48.816508 CH0_RK1: MR19=0xC0C, MR18=0xCBCB, DQSOSC=384, MR23=63, INC=400, DEC=267
6343 11:03:48.819797 [RxdqsGatingPostProcess] freq 400
6344 11:03:48.826490 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6345 11:03:48.826567 Pre-setting of DQS Precalculation
6346 11:03:48.833294 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6347 11:03:48.833386 ==
6348 11:03:48.836402 Dram Type= 6, Freq= 0, CH_1, rank 0
6349 11:03:48.839683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6350 11:03:48.839774 ==
6351 11:03:48.846237 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6352 11:03:48.853117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6353 11:03:48.856345 [CA 0] Center 36 (8~64) winsize 57
6354 11:03:48.859753 [CA 1] Center 36 (8~64) winsize 57
6355 11:03:48.862912 [CA 2] Center 36 (8~64) winsize 57
6356 11:03:48.863025 [CA 3] Center 36 (8~64) winsize 57
6357 11:03:48.866392 [CA 4] Center 36 (8~64) winsize 57
6358 11:03:48.869485 [CA 5] Center 36 (8~64) winsize 57
6359 11:03:48.869552
6360 11:03:48.873346 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6361 11:03:48.873411
6362 11:03:48.879695 [CATrainingPosCal] consider 1 rank data
6363 11:03:48.879766 u2DelayCellTimex100 = 270/100 ps
6364 11:03:48.886515 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 11:03:48.889729 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 11:03:48.893066 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 11:03:48.896148 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 11:03:48.899690 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 11:03:48.903016 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 11:03:48.903107
6371 11:03:48.906337 CA PerBit enable=1, Macro0, CA PI delay=36
6372 11:03:48.906412
6373 11:03:48.909820 [CBTSetCACLKResult] CA Dly = 36
6374 11:03:48.913281 CS Dly: 1 (0~32)
6375 11:03:48.913356 ==
6376 11:03:48.916541 Dram Type= 6, Freq= 0, CH_1, rank 1
6377 11:03:48.919876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6378 11:03:48.919951 ==
6379 11:03:48.926370 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6380 11:03:48.929605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6381 11:03:48.933094 [CA 0] Center 36 (8~64) winsize 57
6382 11:03:48.936109 [CA 1] Center 36 (8~64) winsize 57
6383 11:03:48.939868 [CA 2] Center 36 (8~64) winsize 57
6384 11:03:48.942802 [CA 3] Center 36 (8~64) winsize 57
6385 11:03:48.946540 [CA 4] Center 36 (8~64) winsize 57
6386 11:03:48.949483 [CA 5] Center 36 (8~64) winsize 57
6387 11:03:48.949558
6388 11:03:48.953348 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6389 11:03:48.953422
6390 11:03:48.956308 [CATrainingPosCal] consider 2 rank data
6391 11:03:48.959860 u2DelayCellTimex100 = 270/100 ps
6392 11:03:48.963074 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6393 11:03:48.966156 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6394 11:03:48.969464 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6395 11:03:48.973097 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6396 11:03:48.979327 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 11:03:48.982859 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 11:03:48.982934
6399 11:03:48.985936 CA PerBit enable=1, Macro0, CA PI delay=36
6400 11:03:48.986011
6401 11:03:48.989369 [CBTSetCACLKResult] CA Dly = 36
6402 11:03:48.989445 CS Dly: 1 (0~32)
6403 11:03:48.989503
6404 11:03:48.992704 ----->DramcWriteLeveling(PI) begin...
6405 11:03:48.992781 ==
6406 11:03:48.996018 Dram Type= 6, Freq= 0, CH_1, rank 0
6407 11:03:49.002719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6408 11:03:49.002845 ==
6409 11:03:49.005885 Write leveling (Byte 0): 32 => 0
6410 11:03:49.005997 Write leveling (Byte 1): 32 => 0
6411 11:03:49.009607 DramcWriteLeveling(PI) end<-----
6412 11:03:49.009721
6413 11:03:49.012592 ==
6414 11:03:49.012705 Dram Type= 6, Freq= 0, CH_1, rank 0
6415 11:03:49.019291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6416 11:03:49.019478 ==
6417 11:03:49.022761 [Gating] SW mode calibration
6418 11:03:49.028949 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 11:03:49.032466 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6420 11:03:49.038936 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 11:03:49.042391 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 11:03:49.045377 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 11:03:49.052103 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 11:03:49.056062 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:03:49.059115 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:03:49.065786 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 11:03:49.068708 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6428 11:03:49.072105 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 11:03:49.075575 Total UI for P1: 0, mck2ui 16
6430 11:03:49.078658 best dqsien dly found for B0: ( 0, 10, 16)
6431 11:03:49.082445 Total UI for P1: 0, mck2ui 16
6432 11:03:49.085482 best dqsien dly found for B1: ( 0, 10, 16)
6433 11:03:49.088529 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6434 11:03:49.092534 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6435 11:03:49.092606
6436 11:03:49.098591 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6437 11:03:49.102207 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6438 11:03:49.105339 [Gating] SW calibration Done
6439 11:03:49.105406 ==
6440 11:03:49.108659 Dram Type= 6, Freq= 0, CH_1, rank 0
6441 11:03:49.112211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6442 11:03:49.112274 ==
6443 11:03:49.112329 RX Vref Scan: 0
6444 11:03:49.112381
6445 11:03:49.115519 RX Vref 0 -> 0, step: 1
6446 11:03:49.115584
6447 11:03:49.118534 RX Delay -410 -> 252, step: 16
6448 11:03:49.121805 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6449 11:03:49.128341 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6450 11:03:49.132125 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6451 11:03:49.135020 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6452 11:03:49.138455 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6453 11:03:49.145020 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6454 11:03:49.148528 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6455 11:03:49.151491 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6456 11:03:49.155011 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6457 11:03:49.161420 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6458 11:03:49.164665 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6459 11:03:49.168461 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6460 11:03:49.171445 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6461 11:03:49.178308 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6462 11:03:49.181148 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6463 11:03:49.185044 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6464 11:03:49.185111 ==
6465 11:03:49.187919 Dram Type= 6, Freq= 0, CH_1, rank 0
6466 11:03:49.194629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6467 11:03:49.194698 ==
6468 11:03:49.194755 DQS Delay:
6469 11:03:49.197856 DQS0 = 43, DQS1 = 59
6470 11:03:49.197920 DQM Delay:
6471 11:03:49.197972 DQM0 = 6, DQM1 = 15
6472 11:03:49.201198 DQ Delay:
6473 11:03:49.204570 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6474 11:03:49.204637 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6475 11:03:49.207856 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6476 11:03:49.211044 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6477 11:03:49.211109
6478 11:03:49.211162
6479 11:03:49.214313 ==
6480 11:03:49.217580 Dram Type= 6, Freq= 0, CH_1, rank 0
6481 11:03:49.220869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6482 11:03:49.220930 ==
6483 11:03:49.220983
6484 11:03:49.221036
6485 11:03:49.224765 TX Vref Scan disable
6486 11:03:49.224827 == TX Byte 0 ==
6487 11:03:49.227482 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6488 11:03:49.234356 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6489 11:03:49.234425 == TX Byte 1 ==
6490 11:03:49.237779 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6491 11:03:49.244018 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6492 11:03:49.244088 ==
6493 11:03:49.247440 Dram Type= 6, Freq= 0, CH_1, rank 0
6494 11:03:49.250702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6495 11:03:49.250768 ==
6496 11:03:49.250826
6497 11:03:49.250877
6498 11:03:49.254156 TX Vref Scan disable
6499 11:03:49.254222 == TX Byte 0 ==
6500 11:03:49.260994 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6501 11:03:49.264594 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6502 11:03:49.264667 == TX Byte 1 ==
6503 11:03:49.270947 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6504 11:03:49.274223 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6505 11:03:49.274297
6506 11:03:49.274353 [DATLAT]
6507 11:03:49.277601 Freq=400, CH1 RK0
6508 11:03:49.277674
6509 11:03:49.277731 DATLAT Default: 0xf
6510 11:03:49.280758 0, 0xFFFF, sum = 0
6511 11:03:49.280833 1, 0xFFFF, sum = 0
6512 11:03:49.284268 2, 0xFFFF, sum = 0
6513 11:03:49.284342 3, 0xFFFF, sum = 0
6514 11:03:49.287476 4, 0xFFFF, sum = 0
6515 11:03:49.287550 5, 0xFFFF, sum = 0
6516 11:03:49.291010 6, 0xFFFF, sum = 0
6517 11:03:49.291085 7, 0xFFFF, sum = 0
6518 11:03:49.294127 8, 0xFFFF, sum = 0
6519 11:03:49.294203 9, 0xFFFF, sum = 0
6520 11:03:49.297311 10, 0xFFFF, sum = 0
6521 11:03:49.300551 11, 0xFFFF, sum = 0
6522 11:03:49.300625 12, 0x0, sum = 1
6523 11:03:49.300687 13, 0x0, sum = 2
6524 11:03:49.304309 14, 0x0, sum = 3
6525 11:03:49.304381 15, 0x0, sum = 4
6526 11:03:49.307447 best_step = 13
6527 11:03:49.307514
6528 11:03:49.307572 ==
6529 11:03:49.310426 Dram Type= 6, Freq= 0, CH_1, rank 0
6530 11:03:49.313938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6531 11:03:49.314007 ==
6532 11:03:49.317141 RX Vref Scan: 1
6533 11:03:49.317208
6534 11:03:49.317273 RX Vref 0 -> 0, step: 1
6535 11:03:49.317324
6536 11:03:49.320601 RX Delay -359 -> 252, step: 8
6537 11:03:49.320665
6538 11:03:49.323672 Set Vref, RX VrefLevel [Byte0]: 53
6539 11:03:49.327051 [Byte1]: 48
6540 11:03:49.331935
6541 11:03:49.332009 Final RX Vref Byte 0 = 53 to rank0
6542 11:03:49.335336 Final RX Vref Byte 1 = 48 to rank0
6543 11:03:49.338706 Final RX Vref Byte 0 = 53 to rank1
6544 11:03:49.342086 Final RX Vref Byte 1 = 48 to rank1==
6545 11:03:49.345432 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 11:03:49.352209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 11:03:49.352282 ==
6548 11:03:49.352342 DQS Delay:
6549 11:03:49.355816 DQS0 = 48, DQS1 = 68
6550 11:03:49.355887 DQM Delay:
6551 11:03:49.355944 DQM0 = 9, DQM1 = 19
6552 11:03:49.358594 DQ Delay:
6553 11:03:49.361726 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6554 11:03:49.361798 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6555 11:03:49.365135 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =12
6556 11:03:49.368541 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =28
6557 11:03:49.368608
6558 11:03:49.372012
6559 11:03:49.378570 [DQSOSCAuto] RK0, (LSB)MR18= 0xdfdf, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6560 11:03:49.381706 CH1 RK0: MR19=C0C, MR18=DFDF
6561 11:03:49.388331 CH1_RK0: MR19=0xC0C, MR18=0xDFDF, DQSOSC=382, MR23=63, INC=404, DEC=269
6562 11:03:49.388404 ==
6563 11:03:49.391552 Dram Type= 6, Freq= 0, CH_1, rank 1
6564 11:03:49.394999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6565 11:03:49.395068 ==
6566 11:03:49.398275 [Gating] SW mode calibration
6567 11:03:49.405023 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6568 11:03:49.411933 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6569 11:03:49.415152 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6570 11:03:49.418543 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6571 11:03:49.421568 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6572 11:03:49.428092 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6573 11:03:49.431739 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6574 11:03:49.435084 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6575 11:03:49.442460 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6576 11:03:49.444955 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6577 11:03:49.448285 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6578 11:03:49.451686 Total UI for P1: 0, mck2ui 16
6579 11:03:49.455098 best dqsien dly found for B0: ( 0, 10, 16)
6580 11:03:49.458374 Total UI for P1: 0, mck2ui 16
6581 11:03:49.461853 best dqsien dly found for B1: ( 0, 10, 16)
6582 11:03:49.465107 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6583 11:03:49.468284 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6584 11:03:49.471483
6585 11:03:49.475252 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6586 11:03:49.478230 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6587 11:03:49.481455 [Gating] SW calibration Done
6588 11:03:49.481529 ==
6589 11:03:49.484794 Dram Type= 6, Freq= 0, CH_1, rank 1
6590 11:03:49.488042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6591 11:03:49.488116 ==
6592 11:03:49.488173 RX Vref Scan: 0
6593 11:03:49.491855
6594 11:03:49.491921 RX Vref 0 -> 0, step: 1
6595 11:03:49.491976
6596 11:03:49.495086 RX Delay -410 -> 252, step: 16
6597 11:03:49.498203 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6598 11:03:49.504678 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6599 11:03:49.508111 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6600 11:03:49.511451 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6601 11:03:49.515195 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6602 11:03:49.521456 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6603 11:03:49.524892 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6604 11:03:49.528048 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6605 11:03:49.531565 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6606 11:03:49.538388 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6607 11:03:49.541222 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6608 11:03:49.544573 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6609 11:03:49.548004 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6610 11:03:49.554409 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6611 11:03:49.557826 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6612 11:03:49.561074 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6613 11:03:49.561137 ==
6614 11:03:49.564601 Dram Type= 6, Freq= 0, CH_1, rank 1
6615 11:03:49.571140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6616 11:03:49.571215 ==
6617 11:03:49.571274 DQS Delay:
6618 11:03:49.574274 DQS0 = 35, DQS1 = 59
6619 11:03:49.574341 DQM Delay:
6620 11:03:49.574396 DQM0 = 3, DQM1 = 18
6621 11:03:49.577679 DQ Delay:
6622 11:03:49.581042 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6623 11:03:49.581113 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6624 11:03:49.584348 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6625 11:03:49.587787 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6626 11:03:49.587851
6627 11:03:49.587909
6628 11:03:49.591156 ==
6629 11:03:49.591231 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 11:03:49.597736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6631 11:03:49.597811 ==
6632 11:03:49.597906
6633 11:03:49.597958
6634 11:03:49.600895 TX Vref Scan disable
6635 11:03:49.600968 == TX Byte 0 ==
6636 11:03:49.604632 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6637 11:03:49.611131 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6638 11:03:49.611206 == TX Byte 1 ==
6639 11:03:49.614418 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6640 11:03:49.617601 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6641 11:03:49.621161 ==
6642 11:03:49.624034 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 11:03:49.627370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6644 11:03:49.627444 ==
6645 11:03:49.627502
6646 11:03:49.627555
6647 11:03:49.630890 TX Vref Scan disable
6648 11:03:49.631011 == TX Byte 0 ==
6649 11:03:49.633977 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6650 11:03:49.640923 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6651 11:03:49.641000 == TX Byte 1 ==
6652 11:03:49.644010 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6653 11:03:49.650483 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6654 11:03:49.650621
6655 11:03:49.650753 [DATLAT]
6656 11:03:49.650866 Freq=400, CH1 RK1
6657 11:03:49.650976
6658 11:03:49.653720 DATLAT Default: 0xd
6659 11:03:49.657036 0, 0xFFFF, sum = 0
6660 11:03:49.657172 1, 0xFFFF, sum = 0
6661 11:03:49.660363 2, 0xFFFF, sum = 0
6662 11:03:49.660474 3, 0xFFFF, sum = 0
6663 11:03:49.663930 4, 0xFFFF, sum = 0
6664 11:03:49.664027 5, 0xFFFF, sum = 0
6665 11:03:49.666841 6, 0xFFFF, sum = 0
6666 11:03:49.666964 7, 0xFFFF, sum = 0
6667 11:03:49.670401 8, 0xFFFF, sum = 0
6668 11:03:49.670512 9, 0xFFFF, sum = 0
6669 11:03:49.673832 10, 0xFFFF, sum = 0
6670 11:03:49.673929 11, 0xFFFF, sum = 0
6671 11:03:49.676922 12, 0x0, sum = 1
6672 11:03:49.677034 13, 0x0, sum = 2
6673 11:03:49.680566 14, 0x0, sum = 3
6674 11:03:49.680664 15, 0x0, sum = 4
6675 11:03:49.683755 best_step = 13
6676 11:03:49.683860
6677 11:03:49.683969 ==
6678 11:03:49.687275 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 11:03:49.690186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6680 11:03:49.690300 ==
6681 11:03:49.690395 RX Vref Scan: 0
6682 11:03:49.693654
6683 11:03:49.693751 RX Vref 0 -> 0, step: 1
6684 11:03:49.693847
6685 11:03:49.696763 RX Delay -359 -> 252, step: 8
6686 11:03:49.704215 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6687 11:03:49.708242 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6688 11:03:49.711069 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6689 11:03:49.714551 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6690 11:03:49.720959 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6691 11:03:49.724312 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6692 11:03:49.727491 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6693 11:03:49.730855 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6694 11:03:49.737739 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6695 11:03:49.740928 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6696 11:03:49.744566 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6697 11:03:49.747660 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6698 11:03:49.754189 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6699 11:03:49.757615 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6700 11:03:49.761067 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6701 11:03:49.767475 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6702 11:03:49.767550 ==
6703 11:03:49.770797 Dram Type= 6, Freq= 0, CH_1, rank 1
6704 11:03:49.774226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6705 11:03:49.774301 ==
6706 11:03:49.774358 DQS Delay:
6707 11:03:49.777516 DQS0 = 48, DQS1 = 64
6708 11:03:49.777590 DQM Delay:
6709 11:03:49.780831 DQM0 = 9, DQM1 = 15
6710 11:03:49.780906 DQ Delay:
6711 11:03:49.784127 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6712 11:03:49.787391 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6713 11:03:49.790673 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6714 11:03:49.794302 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6715 11:03:49.794376
6716 11:03:49.794433
6717 11:03:49.800588 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6718 11:03:49.804334 CH1 RK1: MR19=C0C, MR18=B5B5
6719 11:03:49.810497 CH1_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6720 11:03:49.813915 [RxdqsGatingPostProcess] freq 400
6721 11:03:49.817104 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6722 11:03:49.821096 Pre-setting of DQS Precalculation
6723 11:03:49.827044 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6724 11:03:49.833715 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6725 11:03:49.840308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6726 11:03:49.840381
6727 11:03:49.840439
6728 11:03:49.843540 [Calibration Summary] 800 Mbps
6729 11:03:49.846959 CH 0, Rank 0
6730 11:03:49.847026 SW Impedance : PASS
6731 11:03:49.850137 DUTY Scan : NO K
6732 11:03:49.853397 ZQ Calibration : PASS
6733 11:03:49.853462 Jitter Meter : NO K
6734 11:03:49.856874 CBT Training : PASS
6735 11:03:49.856940 Write leveling : PASS
6736 11:03:49.860432 RX DQS gating : PASS
6737 11:03:49.863504 RX DQ/DQS(RDDQC) : PASS
6738 11:03:49.863570 TX DQ/DQS : PASS
6739 11:03:49.866795 RX DATLAT : PASS
6740 11:03:49.870206 RX DQ/DQS(Engine): PASS
6741 11:03:49.870276 TX OE : NO K
6742 11:03:49.873396 All Pass.
6743 11:03:49.873465
6744 11:03:49.873519 CH 0, Rank 1
6745 11:03:49.876713 SW Impedance : PASS
6746 11:03:49.876806 DUTY Scan : NO K
6747 11:03:49.880153 ZQ Calibration : PASS
6748 11:03:49.883306 Jitter Meter : NO K
6749 11:03:49.883372 CBT Training : PASS
6750 11:03:49.886682 Write leveling : NO K
6751 11:03:49.890416 RX DQS gating : PASS
6752 11:03:49.890484 RX DQ/DQS(RDDQC) : PASS
6753 11:03:49.893602 TX DQ/DQS : PASS
6754 11:03:49.896969 RX DATLAT : PASS
6755 11:03:49.897034 RX DQ/DQS(Engine): PASS
6756 11:03:49.900136 TX OE : NO K
6757 11:03:49.900199 All Pass.
6758 11:03:49.900251
6759 11:03:49.903057 CH 1, Rank 0
6760 11:03:49.903118 SW Impedance : PASS
6761 11:03:49.906630 DUTY Scan : NO K
6762 11:03:49.909874 ZQ Calibration : PASS
6763 11:03:49.909936 Jitter Meter : NO K
6764 11:03:49.913028 CBT Training : PASS
6765 11:03:49.913093 Write leveling : PASS
6766 11:03:49.916505 RX DQS gating : PASS
6767 11:03:49.919745 RX DQ/DQS(RDDQC) : PASS
6768 11:03:49.919806 TX DQ/DQS : PASS
6769 11:03:49.923622 RX DATLAT : PASS
6770 11:03:49.926550 RX DQ/DQS(Engine): PASS
6771 11:03:49.926613 TX OE : NO K
6772 11:03:49.929664 All Pass.
6773 11:03:49.929739
6774 11:03:49.929796 CH 1, Rank 1
6775 11:03:49.933203 SW Impedance : PASS
6776 11:03:49.933321 DUTY Scan : NO K
6777 11:03:49.936788 ZQ Calibration : PASS
6778 11:03:49.939583 Jitter Meter : NO K
6779 11:03:49.939657 CBT Training : PASS
6780 11:03:49.943138 Write leveling : NO K
6781 11:03:49.946358 RX DQS gating : PASS
6782 11:03:49.946431 RX DQ/DQS(RDDQC) : PASS
6783 11:03:49.949534 TX DQ/DQS : PASS
6784 11:03:49.953222 RX DATLAT : PASS
6785 11:03:49.953335 RX DQ/DQS(Engine): PASS
6786 11:03:49.956505 TX OE : NO K
6787 11:03:49.956578 All Pass.
6788 11:03:49.956636
6789 11:03:49.959573 DramC Write-DBI off
6790 11:03:49.963065 PER_BANK_REFRESH: Hybrid Mode
6791 11:03:49.963138 TX_TRACKING: ON
6792 11:03:49.973406 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6793 11:03:49.976280 [FAST_K] Save calibration result to emmc
6794 11:03:49.979667 dramc_set_vcore_voltage set vcore to 725000
6795 11:03:49.982889 Read voltage for 1600, 0
6796 11:03:49.982963 Vio18 = 0
6797 11:03:49.983021 Vcore = 725000
6798 11:03:49.986271 Vdram = 0
6799 11:03:49.986412 Vddq = 0
6800 11:03:49.986470 Vmddr = 0
6801 11:03:49.992850 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6802 11:03:49.996645 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6803 11:03:49.999402 MEM_TYPE=3, freq_sel=13
6804 11:03:50.003132 sv_algorithm_assistance_LP4_3733
6805 11:03:50.006288 ============ PULL DRAM RESETB DOWN ============
6806 11:03:50.009531 ========== PULL DRAM RESETB DOWN end =========
6807 11:03:50.016270 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6808 11:03:50.019850 ===================================
6809 11:03:50.019925 LPDDR4 DRAM CONFIGURATION
6810 11:03:50.022855 ===================================
6811 11:03:50.026337 EX_ROW_EN[0] = 0x0
6812 11:03:50.029471 EX_ROW_EN[1] = 0x0
6813 11:03:50.029545 LP4Y_EN = 0x0
6814 11:03:50.032619 WORK_FSP = 0x1
6815 11:03:50.032683 WL = 0x5
6816 11:03:50.036070 RL = 0x5
6817 11:03:50.036144 BL = 0x2
6818 11:03:50.039228 RPST = 0x0
6819 11:03:50.039302 RD_PRE = 0x0
6820 11:03:50.042867 WR_PRE = 0x1
6821 11:03:50.042940 WR_PST = 0x1
6822 11:03:50.045672 DBI_WR = 0x0
6823 11:03:50.045750 DBI_RD = 0x0
6824 11:03:50.049032 OTF = 0x1
6825 11:03:50.052579 ===================================
6826 11:03:50.055655 ===================================
6827 11:03:50.055730 ANA top config
6828 11:03:50.058999 ===================================
6829 11:03:50.062753 DLL_ASYNC_EN = 0
6830 11:03:50.065722 ALL_SLAVE_EN = 0
6831 11:03:50.069126 NEW_RANK_MODE = 1
6832 11:03:50.069232 DLL_IDLE_MODE = 1
6833 11:03:50.072363 LP45_APHY_COMB_EN = 1
6834 11:03:50.075635 TX_ODT_DIS = 0
6835 11:03:50.079085 NEW_8X_MODE = 1
6836 11:03:50.082639 ===================================
6837 11:03:50.085836 ===================================
6838 11:03:50.088831 data_rate = 3200
6839 11:03:50.088928 CKR = 1
6840 11:03:50.092384 DQ_P2S_RATIO = 8
6841 11:03:50.096139 ===================================
6842 11:03:50.099320 CA_P2S_RATIO = 8
6843 11:03:50.102087 DQ_CA_OPEN = 0
6844 11:03:50.105583 DQ_SEMI_OPEN = 0
6845 11:03:50.109093 CA_SEMI_OPEN = 0
6846 11:03:50.109211 CA_FULL_RATE = 0
6847 11:03:50.112101 DQ_CKDIV4_EN = 0
6848 11:03:50.115785 CA_CKDIV4_EN = 0
6849 11:03:50.118981 CA_PREDIV_EN = 0
6850 11:03:50.122419 PH8_DLY = 12
6851 11:03:50.125418 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6852 11:03:50.125492 DQ_AAMCK_DIV = 4
6853 11:03:50.129209 CA_AAMCK_DIV = 4
6854 11:03:50.132486 CA_ADMCK_DIV = 4
6855 11:03:50.135953 DQ_TRACK_CA_EN = 0
6856 11:03:50.138923 CA_PICK = 1600
6857 11:03:50.142376 CA_MCKIO = 1600
6858 11:03:50.145728 MCKIO_SEMI = 0
6859 11:03:50.145803 PLL_FREQ = 3068
6860 11:03:50.148670 DQ_UI_PI_RATIO = 32
6861 11:03:50.152029 CA_UI_PI_RATIO = 0
6862 11:03:50.155629 ===================================
6863 11:03:50.158692 ===================================
6864 11:03:50.162058 memory_type:LPDDR4
6865 11:03:50.162134 GP_NUM : 10
6866 11:03:50.165258 SRAM_EN : 1
6867 11:03:50.168754 MD32_EN : 0
6868 11:03:50.172024 ===================================
6869 11:03:50.172107 [ANA_INIT] >>>>>>>>>>>>>>
6870 11:03:50.175259 <<<<<< [CONFIGURE PHASE]: ANA_TX
6871 11:03:50.178969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6872 11:03:50.182111 ===================================
6873 11:03:50.185021 data_rate = 3200,PCW = 0X7600
6874 11:03:50.188492 ===================================
6875 11:03:50.191896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6876 11:03:50.199063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6877 11:03:50.202166 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6878 11:03:50.208824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6879 11:03:50.212093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6880 11:03:50.215250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6881 11:03:50.215322 [ANA_INIT] flow start
6882 11:03:50.218767 [ANA_INIT] PLL >>>>>>>>
6883 11:03:50.221839 [ANA_INIT] PLL <<<<<<<<
6884 11:03:50.225360 [ANA_INIT] MIDPI >>>>>>>>
6885 11:03:50.225430 [ANA_INIT] MIDPI <<<<<<<<
6886 11:03:50.228339 [ANA_INIT] DLL >>>>>>>>
6887 11:03:50.231569 [ANA_INIT] DLL <<<<<<<<
6888 11:03:50.231640 [ANA_INIT] flow end
6889 11:03:50.235402 ============ LP4 DIFF to SE enter ============
6890 11:03:50.242118 ============ LP4 DIFF to SE exit ============
6891 11:03:50.242186 [ANA_INIT] <<<<<<<<<<<<<
6892 11:03:50.245158 [Flow] Enable top DCM control >>>>>
6893 11:03:50.248409 [Flow] Enable top DCM control <<<<<
6894 11:03:50.251660 Enable DLL master slave shuffle
6895 11:03:50.258537 ==============================================================
6896 11:03:50.258604 Gating Mode config
6897 11:03:50.265206 ==============================================================
6898 11:03:50.268418 Config description:
6899 11:03:50.278042 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6900 11:03:50.284611 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6901 11:03:50.288023 SELPH_MODE 0: By rank 1: By Phase
6902 11:03:50.294666 ==============================================================
6903 11:03:50.297806 GAT_TRACK_EN = 1
6904 11:03:50.301181 RX_GATING_MODE = 2
6905 11:03:50.304695 RX_GATING_TRACK_MODE = 2
6906 11:03:50.304767 SELPH_MODE = 1
6907 11:03:50.308136 PICG_EARLY_EN = 1
6908 11:03:50.311155 VALID_LAT_VALUE = 1
6909 11:03:50.317795 ==============================================================
6910 11:03:50.321201 Enter into Gating configuration >>>>
6911 11:03:50.324413 Exit from Gating configuration <<<<
6912 11:03:50.327776 Enter into DVFS_PRE_config >>>>>
6913 11:03:50.337723 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6914 11:03:50.340758 Exit from DVFS_PRE_config <<<<<
6915 11:03:50.344279 Enter into PICG configuration >>>>
6916 11:03:50.347712 Exit from PICG configuration <<<<
6917 11:03:50.350820 [RX_INPUT] configuration >>>>>
6918 11:03:50.354236 [RX_INPUT] configuration <<<<<
6919 11:03:50.357595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6920 11:03:50.364007 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6921 11:03:50.370770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6922 11:03:50.377326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6923 11:03:50.383974 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6924 11:03:50.387238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6925 11:03:50.393996 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6926 11:03:50.396935 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6927 11:03:50.400303 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6928 11:03:50.404176 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6929 11:03:50.410193 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6930 11:03:50.413635 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6931 11:03:50.416963 ===================================
6932 11:03:50.420332 LPDDR4 DRAM CONFIGURATION
6933 11:03:50.424196 ===================================
6934 11:03:50.424269 EX_ROW_EN[0] = 0x0
6935 11:03:50.426895 EX_ROW_EN[1] = 0x0
6936 11:03:50.426968 LP4Y_EN = 0x0
6937 11:03:50.430070 WORK_FSP = 0x1
6938 11:03:50.430136 WL = 0x5
6939 11:03:50.433476 RL = 0x5
6940 11:03:50.436553 BL = 0x2
6941 11:03:50.436620 RPST = 0x0
6942 11:03:50.439894 RD_PRE = 0x0
6943 11:03:50.439956 WR_PRE = 0x1
6944 11:03:50.443471 WR_PST = 0x1
6945 11:03:50.443535 DBI_WR = 0x0
6946 11:03:50.446620 DBI_RD = 0x0
6947 11:03:50.446685 OTF = 0x1
6948 11:03:50.450041 ===================================
6949 11:03:50.453473 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6950 11:03:50.459846 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6951 11:03:50.463156 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6952 11:03:50.466739 ===================================
6953 11:03:50.470028 LPDDR4 DRAM CONFIGURATION
6954 11:03:50.473128 ===================================
6955 11:03:50.473221 EX_ROW_EN[0] = 0x10
6956 11:03:50.476355 EX_ROW_EN[1] = 0x0
6957 11:03:50.476419 LP4Y_EN = 0x0
6958 11:03:50.479797 WORK_FSP = 0x1
6959 11:03:50.479866 WL = 0x5
6960 11:03:50.483196 RL = 0x5
6961 11:03:50.483263 BL = 0x2
6962 11:03:50.486461 RPST = 0x0
6963 11:03:50.489621 RD_PRE = 0x0
6964 11:03:50.489698 WR_PRE = 0x1
6965 11:03:50.493202 WR_PST = 0x1
6966 11:03:50.493289 DBI_WR = 0x0
6967 11:03:50.496562 DBI_RD = 0x0
6968 11:03:50.496625 OTF = 0x1
6969 11:03:50.499470 ===================================
6970 11:03:50.506388 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6971 11:03:50.506462 ==
6972 11:03:50.509634 Dram Type= 6, Freq= 0, CH_0, rank 0
6973 11:03:50.513068 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6974 11:03:50.513157 ==
6975 11:03:50.516296 [Duty_Offset_Calibration]
6976 11:03:50.519705 B0:0 B1:2 CA:1
6977 11:03:50.519771
6978 11:03:50.522571 [DutyScan_Calibration_Flow] k_type=0
6979 11:03:50.531240
6980 11:03:50.531314 ==CLK 0==
6981 11:03:50.534185 Final CLK duty delay cell = 0
6982 11:03:50.537582 [0] MAX Duty = 5156%(X100), DQS PI = 22
6983 11:03:50.540833 [0] MIN Duty = 4938%(X100), DQS PI = 50
6984 11:03:50.544424 [0] AVG Duty = 5047%(X100)
6985 11:03:50.544497
6986 11:03:50.547683 CH0 CLK Duty spec in!! Max-Min= 218%
6987 11:03:50.550920 [DutyScan_Calibration_Flow] ====Done====
6988 11:03:50.550995
6989 11:03:50.554394 [DutyScan_Calibration_Flow] k_type=1
6990 11:03:50.570991
6991 11:03:50.571079 ==DQS 0 ==
6992 11:03:50.574360 Final DQS duty delay cell = 0
6993 11:03:50.577840 [0] MAX Duty = 5124%(X100), DQS PI = 36
6994 11:03:50.580976 [0] MIN Duty = 5000%(X100), DQS PI = 8
6995 11:03:50.581075 [0] AVG Duty = 5062%(X100)
6996 11:03:50.584362
6997 11:03:50.584437 ==DQS 1 ==
6998 11:03:50.587701 Final DQS duty delay cell = 0
6999 11:03:50.591111 [0] MAX Duty = 5031%(X100), DQS PI = 46
7000 11:03:50.594474 [0] MIN Duty = 4844%(X100), DQS PI = 18
7001 11:03:50.597888 [0] AVG Duty = 4937%(X100)
7002 11:03:50.597952
7003 11:03:50.600756 CH0 DQS 0 Duty spec in!! Max-Min= 124%
7004 11:03:50.600820
7005 11:03:50.604518 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7006 11:03:50.607608 [DutyScan_Calibration_Flow] ====Done====
7007 11:03:50.607679
7008 11:03:50.610878 [DutyScan_Calibration_Flow] k_type=3
7009 11:03:50.628149
7010 11:03:50.628222 ==DQM 0 ==
7011 11:03:50.631583 Final DQM duty delay cell = 0
7012 11:03:50.634820 [0] MAX Duty = 5187%(X100), DQS PI = 24
7013 11:03:50.638411 [0] MIN Duty = 4907%(X100), DQS PI = 42
7014 11:03:50.641418 [0] AVG Duty = 5047%(X100)
7015 11:03:50.641492
7016 11:03:50.641550 ==DQM 1 ==
7017 11:03:50.644854 Final DQM duty delay cell = 0
7018 11:03:50.648528 [0] MAX Duty = 5031%(X100), DQS PI = 50
7019 11:03:50.651603 [0] MIN Duty = 4782%(X100), DQS PI = 14
7020 11:03:50.654817 [0] AVG Duty = 4906%(X100)
7021 11:03:50.654887
7022 11:03:50.658238 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7023 11:03:50.658303
7024 11:03:50.661577 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7025 11:03:50.664718 [DutyScan_Calibration_Flow] ====Done====
7026 11:03:50.664777
7027 11:03:50.668277 [DutyScan_Calibration_Flow] k_type=2
7028 11:03:50.684659
7029 11:03:50.684729 ==DQ 0 ==
7030 11:03:50.688091 Final DQ duty delay cell = 0
7031 11:03:50.691288 [0] MAX Duty = 5218%(X100), DQS PI = 20
7032 11:03:50.694756 [0] MIN Duty = 4938%(X100), DQS PI = 56
7033 11:03:50.694824 [0] AVG Duty = 5078%(X100)
7034 11:03:50.697839
7035 11:03:50.697898 ==DQ 1 ==
7036 11:03:50.701122 Final DQ duty delay cell = -4
7037 11:03:50.704456 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7038 11:03:50.708342 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7039 11:03:50.711160 [-4] AVG Duty = 4953%(X100)
7040 11:03:50.711225
7041 11:03:50.714356 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7042 11:03:50.714413
7043 11:03:50.718043 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7044 11:03:50.721428 [DutyScan_Calibration_Flow] ====Done====
7045 11:03:50.721485 ==
7046 11:03:50.724661 Dram Type= 6, Freq= 0, CH_1, rank 0
7047 11:03:50.727602 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7048 11:03:50.727659 ==
7049 11:03:50.730787 [Duty_Offset_Calibration]
7050 11:03:50.730842 B0:0 B1:4 CA:-5
7051 11:03:50.730895
7052 11:03:50.734081 [DutyScan_Calibration_Flow] k_type=0
7053 11:03:50.745165
7054 11:03:50.745248 ==CLK 0==
7055 11:03:50.748950 Final CLK duty delay cell = 0
7056 11:03:50.752258 [0] MAX Duty = 5156%(X100), DQS PI = 18
7057 11:03:50.755624 [0] MIN Duty = 4906%(X100), DQS PI = 50
7058 11:03:50.758629 [0] AVG Duty = 5031%(X100)
7059 11:03:50.758705
7060 11:03:50.762120 CH1 CLK Duty spec in!! Max-Min= 250%
7061 11:03:50.765345 [DutyScan_Calibration_Flow] ====Done====
7062 11:03:50.765420
7063 11:03:50.768818 [DutyScan_Calibration_Flow] k_type=1
7064 11:03:50.784453
7065 11:03:50.784528 ==DQS 0 ==
7066 11:03:50.787544 Final DQS duty delay cell = 0
7067 11:03:50.790682 [0] MAX Duty = 5187%(X100), DQS PI = 20
7068 11:03:50.793978 [0] MIN Duty = 4907%(X100), DQS PI = 0
7069 11:03:50.794054 [0] AVG Duty = 5047%(X100)
7070 11:03:50.797432
7071 11:03:50.797507 ==DQS 1 ==
7072 11:03:50.800653 Final DQS duty delay cell = -4
7073 11:03:50.804284 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7074 11:03:50.807625 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7075 11:03:50.810693 [-4] AVG Duty = 4922%(X100)
7076 11:03:50.810791
7077 11:03:50.814226 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7078 11:03:50.814301
7079 11:03:50.817466 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7080 11:03:50.820552 [DutyScan_Calibration_Flow] ====Done====
7081 11:03:50.820626
7082 11:03:50.824050 [DutyScan_Calibration_Flow] k_type=3
7083 11:03:50.839985
7084 11:03:50.840061 ==DQM 0 ==
7085 11:03:50.843052 Final DQM duty delay cell = -4
7086 11:03:50.846689 [-4] MAX Duty = 5031%(X100), DQS PI = 34
7087 11:03:50.849977 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7088 11:03:50.852929 [-4] AVG Duty = 4906%(X100)
7089 11:03:50.853003
7090 11:03:50.853062 ==DQM 1 ==
7091 11:03:50.856619 Final DQM duty delay cell = -4
7092 11:03:50.859916 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7093 11:03:50.862982 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7094 11:03:50.866203 [-4] AVG Duty = 4984%(X100)
7095 11:03:50.866263
7096 11:03:50.869751 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7097 11:03:50.869820
7098 11:03:50.873061 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7099 11:03:50.876471 [DutyScan_Calibration_Flow] ====Done====
7100 11:03:50.876535
7101 11:03:50.880315 [DutyScan_Calibration_Flow] k_type=2
7102 11:03:50.897750
7103 11:03:50.897818 ==DQ 0 ==
7104 11:03:50.900826 Final DQ duty delay cell = 0
7105 11:03:50.903973 [0] MAX Duty = 5093%(X100), DQS PI = 18
7106 11:03:50.907945 [0] MIN Duty = 4938%(X100), DQS PI = 46
7107 11:03:50.908009 [0] AVG Duty = 5015%(X100)
7108 11:03:50.911002
7109 11:03:50.911064 ==DQ 1 ==
7110 11:03:50.914055 Final DQ duty delay cell = 0
7111 11:03:50.917275 [0] MAX Duty = 5031%(X100), DQS PI = 4
7112 11:03:50.920544 [0] MIN Duty = 4876%(X100), DQS PI = 28
7113 11:03:50.920619 [0] AVG Duty = 4953%(X100)
7114 11:03:50.920677
7115 11:03:50.924024 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7116 11:03:50.927233
7117 11:03:50.931010 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7118 11:03:50.934059 [DutyScan_Calibration_Flow] ====Done====
7119 11:03:50.937196 nWR fixed to 30
7120 11:03:50.937318 [ModeRegInit_LP4] CH0 RK0
7121 11:03:50.941158 [ModeRegInit_LP4] CH0 RK1
7122 11:03:50.943923 [ModeRegInit_LP4] CH1 RK0
7123 11:03:50.943997 [ModeRegInit_LP4] CH1 RK1
7124 11:03:50.947221 match AC timing 4
7125 11:03:50.950780 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7126 11:03:50.957352 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7127 11:03:50.960624 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7128 11:03:50.967019 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7129 11:03:50.970441 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7130 11:03:50.970516 [MiockJmeterHQA]
7131 11:03:50.970573
7132 11:03:50.973806 [DramcMiockJmeter] u1RxGatingPI = 0
7133 11:03:50.976919 0 : 4365, 4137
7134 11:03:50.976995 4 : 4252, 4027
7135 11:03:50.980715 8 : 4362, 4137
7136 11:03:50.980791 12 : 4367, 4140
7137 11:03:50.980851 16 : 4254, 4024
7138 11:03:50.983847 20 : 4368, 4140
7139 11:03:50.983922 24 : 4253, 4026
7140 11:03:50.986940 28 : 4259, 4029
7141 11:03:50.987016 32 : 4255, 4027
7142 11:03:50.990584 36 : 4255, 4029
7143 11:03:50.990659 40 : 4371, 4140
7144 11:03:50.990719 44 : 4255, 4027
7145 11:03:50.993793 48 : 4370, 4140
7146 11:03:50.993869 52 : 4260, 4030
7147 11:03:50.996747 56 : 4260, 4029
7148 11:03:50.996823 60 : 4253, 4027
7149 11:03:51.000115 64 : 4366, 4138
7150 11:03:51.000191 68 : 4257, 4029
7151 11:03:51.003643 72 : 4253, 4027
7152 11:03:51.003719 76 : 4257, 4029
7153 11:03:51.003778 80 : 4258, 4029
7154 11:03:51.006818 84 : 4255, 4027
7155 11:03:51.006893 88 : 4260, 4032
7156 11:03:51.010182 92 : 4365, 4140
7157 11:03:51.010257 96 : 4255, 4027
7158 11:03:51.013436 100 : 4368, 1925
7159 11:03:51.013512 104 : 4365, 0
7160 11:03:51.013571 108 : 4252, 0
7161 11:03:51.016770 112 : 4258, 0
7162 11:03:51.016845 116 : 4258, 0
7163 11:03:51.019971 120 : 4250, 0
7164 11:03:51.020047 124 : 4253, 0
7165 11:03:51.020105 128 : 4252, 0
7166 11:03:51.023360 132 : 4250, 0
7167 11:03:51.023436 136 : 4250, 0
7168 11:03:51.026768 140 : 4250, 0
7169 11:03:51.026843 144 : 4249, 0
7170 11:03:51.026903 148 : 4250, 0
7171 11:03:51.030062 152 : 4250, 0
7172 11:03:51.030138 156 : 4249, 0
7173 11:03:51.033419 160 : 4361, 0
7174 11:03:51.033494 164 : 4250, 0
7175 11:03:51.033553 168 : 4249, 0
7176 11:03:51.036613 172 : 4250, 0
7177 11:03:51.036690 176 : 4250, 0
7178 11:03:51.036749 180 : 4250, 0
7179 11:03:51.039988 184 : 4249, 0
7180 11:03:51.040064 188 : 4250, 0
7181 11:03:51.043524 192 : 4250, 0
7182 11:03:51.043600 196 : 4250, 0
7183 11:03:51.043658 200 : 4250, 0
7184 11:03:51.046930 204 : 4360, 0
7185 11:03:51.047005 208 : 4360, 0
7186 11:03:51.049999 212 : 4361, 0
7187 11:03:51.050100 216 : 4250, 0
7188 11:03:51.050182 220 : 4249, 763
7189 11:03:51.053321 224 : 4250, 4021
7190 11:03:51.053397 228 : 4361, 4137
7191 11:03:51.056961 232 : 4250, 4027
7192 11:03:51.057037 236 : 4249, 4027
7193 11:03:51.059986 240 : 4250, 4026
7194 11:03:51.060061 244 : 4253, 4029
7195 11:03:51.063084 248 : 4250, 4027
7196 11:03:51.063160 252 : 4250, 4027
7197 11:03:51.066533 256 : 4360, 4137
7198 11:03:51.066609 260 : 4250, 4027
7199 11:03:51.070054 264 : 4250, 4027
7200 11:03:51.070129 268 : 4360, 4138
7201 11:03:51.070188 272 : 4250, 4027
7202 11:03:51.073500 276 : 4250, 4026
7203 11:03:51.073591 280 : 4363, 4140
7204 11:03:51.077103 284 : 4250, 4027
7205 11:03:51.077220 288 : 4249, 4027
7206 11:03:51.079890 292 : 4250, 4027
7207 11:03:51.079965 296 : 4253, 4029
7208 11:03:51.083311 300 : 4250, 4027
7209 11:03:51.083387 304 : 4250, 4027
7210 11:03:51.086801 308 : 4360, 4137
7211 11:03:51.086877 312 : 4250, 4027
7212 11:03:51.089887 316 : 4250, 4027
7213 11:03:51.089963 320 : 4360, 4138
7214 11:03:51.093109 324 : 4249, 4027
7215 11:03:51.093232 328 : 4250, 4026
7216 11:03:51.096609 332 : 4363, 4140
7217 11:03:51.096684 336 : 4250, 3620
7218 11:03:51.096743 340 : 4249, 1625
7219 11:03:51.099666
7220 11:03:51.099740 MIOCK jitter meter ch=0
7221 11:03:51.099798
7222 11:03:51.103000 1T = (340-100) = 240 dly cells
7223 11:03:51.109971 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7224 11:03:51.110046 ==
7225 11:03:51.112849 Dram Type= 6, Freq= 0, CH_0, rank 0
7226 11:03:51.116831 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7227 11:03:51.116952 ==
7228 11:03:51.123069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7229 11:03:51.126221 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7230 11:03:51.129727 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7231 11:03:51.136246 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7232 11:03:51.144659 [CA 0] Center 41 (11~72) winsize 62
7233 11:03:51.147899 [CA 1] Center 41 (11~72) winsize 62
7234 11:03:51.151450 [CA 2] Center 37 (7~67) winsize 61
7235 11:03:51.154820 [CA 3] Center 37 (7~67) winsize 61
7236 11:03:51.158285 [CA 4] Center 35 (5~66) winsize 62
7237 11:03:51.161180 [CA 5] Center 35 (5~65) winsize 61
7238 11:03:51.161289
7239 11:03:51.164763 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7240 11:03:51.164838
7241 11:03:51.168470 [CATrainingPosCal] consider 1 rank data
7242 11:03:51.171229 u2DelayCellTimex100 = 271/100 ps
7243 11:03:51.174882 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7244 11:03:51.181424 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7245 11:03:51.184637 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7246 11:03:51.188032 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7247 11:03:51.191500 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7248 11:03:51.194786 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7249 11:03:51.194861
7250 11:03:51.197963 CA PerBit enable=1, Macro0, CA PI delay=35
7251 11:03:51.198038
7252 11:03:51.201650 [CBTSetCACLKResult] CA Dly = 35
7253 11:03:51.204403 CS Dly: 11 (0~42)
7254 11:03:51.207925 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7255 11:03:51.211554 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7256 11:03:51.211629 ==
7257 11:03:51.214674 Dram Type= 6, Freq= 0, CH_0, rank 1
7258 11:03:51.217743 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7259 11:03:51.217818 ==
7260 11:03:51.224424 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7261 11:03:51.227658 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7262 11:03:51.234591 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7263 11:03:51.237559 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7264 11:03:51.247370 [CA 0] Center 42 (12~73) winsize 62
7265 11:03:51.250512 [CA 1] Center 41 (11~72) winsize 62
7266 11:03:51.254155 [CA 2] Center 38 (8~68) winsize 61
7267 11:03:51.257193 [CA 3] Center 37 (7~67) winsize 61
7268 11:03:51.260593 [CA 4] Center 35 (5~65) winsize 61
7269 11:03:51.263948 [CA 5] Center 35 (5~66) winsize 62
7270 11:03:51.264019
7271 11:03:51.267270 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7272 11:03:51.267334
7273 11:03:51.270296 [CATrainingPosCal] consider 2 rank data
7274 11:03:51.273586 u2DelayCellTimex100 = 271/100 ps
7275 11:03:51.277103 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7276 11:03:51.283821 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7277 11:03:51.287204 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7278 11:03:51.290187 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7279 11:03:51.293547 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7280 11:03:51.296871 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7281 11:03:51.296945
7282 11:03:51.300281 CA PerBit enable=1, Macro0, CA PI delay=35
7283 11:03:51.300372
7284 11:03:51.303770 [CBTSetCACLKResult] CA Dly = 35
7285 11:03:51.306846 CS Dly: 11 (0~43)
7286 11:03:51.310099 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7287 11:03:51.313608 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7288 11:03:51.313684
7289 11:03:51.316676 ----->DramcWriteLeveling(PI) begin...
7290 11:03:51.316753 ==
7291 11:03:51.320007 Dram Type= 6, Freq= 0, CH_0, rank 0
7292 11:03:51.326679 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7293 11:03:51.326755 ==
7294 11:03:51.330149 Write leveling (Byte 0): 29 => 29
7295 11:03:51.330226 Write leveling (Byte 1): 26 => 26
7296 11:03:51.333588 DramcWriteLeveling(PI) end<-----
7297 11:03:51.333658
7298 11:03:51.333741 ==
7299 11:03:51.337024 Dram Type= 6, Freq= 0, CH_0, rank 0
7300 11:03:51.343737 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7301 11:03:51.343813 ==
7302 11:03:51.346844 [Gating] SW mode calibration
7303 11:03:51.353412 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7304 11:03:51.357081 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7305 11:03:51.363891 0 12 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7306 11:03:51.366992 0 12 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
7307 11:03:51.370009 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7308 11:03:51.376957 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7309 11:03:51.380027 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7310 11:03:51.383604 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7311 11:03:51.389945 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7312 11:03:51.393367 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7313 11:03:51.396897 0 13 0 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7314 11:03:51.400212 0 13 4 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 0)
7315 11:03:51.407064 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7316 11:03:51.409774 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7317 11:03:51.413100 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7318 11:03:51.419671 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7319 11:03:51.423005 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7320 11:03:51.426310 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7321 11:03:51.433133 0 14 0 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7322 11:03:51.436363 0 14 4 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
7323 11:03:51.439751 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7324 11:03:51.446410 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7325 11:03:51.449717 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7326 11:03:51.452822 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7327 11:03:51.459653 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7328 11:03:51.462907 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7329 11:03:51.466676 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7330 11:03:51.473060 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7331 11:03:51.476353 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7332 11:03:51.479465 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7333 11:03:51.486452 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7334 11:03:51.489563 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7335 11:03:51.492947 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7336 11:03:51.499603 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 11:03:51.502824 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 11:03:51.506016 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 11:03:51.512779 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 11:03:51.516121 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 11:03:51.519224 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 11:03:51.526157 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 11:03:51.529445 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 11:03:51.532496 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 11:03:51.539036 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7346 11:03:51.542338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7347 11:03:51.545602 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 11:03:51.549051 Total UI for P1: 0, mck2ui 16
7349 11:03:51.552537 best dqsien dly found for B0: ( 1, 1, 2)
7350 11:03:51.555546 Total UI for P1: 0, mck2ui 16
7351 11:03:51.559079 best dqsien dly found for B1: ( 1, 1, 4)
7352 11:03:51.562318 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7353 11:03:51.565784 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7354 11:03:51.565859
7355 11:03:51.569069 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7356 11:03:51.575377 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7357 11:03:51.575450 [Gating] SW calibration Done
7358 11:03:51.575508 ==
7359 11:03:51.578747 Dram Type= 6, Freq= 0, CH_0, rank 0
7360 11:03:51.585402 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7361 11:03:51.585477 ==
7362 11:03:51.585534 RX Vref Scan: 0
7363 11:03:51.585588
7364 11:03:51.588939 RX Vref 0 -> 0, step: 1
7365 11:03:51.589013
7366 11:03:51.592345 RX Delay 0 -> 252, step: 8
7367 11:03:51.595480 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7368 11:03:51.598908 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7369 11:03:51.602308 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7370 11:03:51.605578 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7371 11:03:51.611985 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7372 11:03:51.615247 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7373 11:03:51.618729 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7374 11:03:51.622046 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7375 11:03:51.625423 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7376 11:03:51.632019 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7377 11:03:51.635363 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7378 11:03:51.638810 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7379 11:03:51.642125 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7380 11:03:51.648455 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7381 11:03:51.651733 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7382 11:03:51.655256 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7383 11:03:51.655331 ==
7384 11:03:51.658524 Dram Type= 6, Freq= 0, CH_0, rank 0
7385 11:03:51.661718 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7386 11:03:51.661793 ==
7387 11:03:51.665383 DQS Delay:
7388 11:03:51.665457 DQS0 = 0, DQS1 = 0
7389 11:03:51.668469 DQM Delay:
7390 11:03:51.668543 DQM0 = 130, DQM1 = 123
7391 11:03:51.668602 DQ Delay:
7392 11:03:51.671603 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7393 11:03:51.675006 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7394 11:03:51.681980 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
7395 11:03:51.685334 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7396 11:03:51.685433
7397 11:03:51.685518
7398 11:03:51.685598 ==
7399 11:03:51.688509 Dram Type= 6, Freq= 0, CH_0, rank 0
7400 11:03:51.691817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7401 11:03:51.691893 ==
7402 11:03:51.691951
7403 11:03:51.692005
7404 11:03:51.695202 TX Vref Scan disable
7405 11:03:51.698432 == TX Byte 0 ==
7406 11:03:51.701576 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7407 11:03:51.705607 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7408 11:03:51.708238 == TX Byte 1 ==
7409 11:03:51.711688 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7410 11:03:51.715140 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7411 11:03:51.715215 ==
7412 11:03:51.718443 Dram Type= 6, Freq= 0, CH_0, rank 0
7413 11:03:51.722027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7414 11:03:51.722102 ==
7415 11:03:51.735578
7416 11:03:51.739156 TX Vref early break, caculate TX vref
7417 11:03:51.742707 TX Vref=16, minBit 8, minWin=22, winSum=375
7418 11:03:51.745858 TX Vref=18, minBit 9, minWin=22, winSum=377
7419 11:03:51.749102 TX Vref=20, minBit 8, minWin=23, winSum=390
7420 11:03:51.752280 TX Vref=22, minBit 8, minWin=24, winSum=402
7421 11:03:51.755878 TX Vref=24, minBit 9, minWin=24, winSum=409
7422 11:03:51.762445 TX Vref=26, minBit 1, minWin=25, winSum=416
7423 11:03:51.765667 TX Vref=28, minBit 8, minWin=24, winSum=414
7424 11:03:51.768581 TX Vref=30, minBit 1, minWin=24, winSum=405
7425 11:03:51.772255 TX Vref=32, minBit 8, minWin=24, winSum=405
7426 11:03:51.775434 TX Vref=34, minBit 6, minWin=23, winSum=391
7427 11:03:51.782225 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 26
7428 11:03:51.782300
7429 11:03:51.785885 Final TX Range 0 Vref 26
7430 11:03:51.785961
7431 11:03:51.786037 ==
7432 11:03:51.788716 Dram Type= 6, Freq= 0, CH_0, rank 0
7433 11:03:51.792205 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7434 11:03:51.792281 ==
7435 11:03:51.792340
7436 11:03:51.792393
7437 11:03:51.796003 TX Vref Scan disable
7438 11:03:51.802096 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7439 11:03:51.802171 == TX Byte 0 ==
7440 11:03:51.805429 u2DelayCellOfst[0]=14 cells (4 PI)
7441 11:03:51.808518 u2DelayCellOfst[1]=21 cells (6 PI)
7442 11:03:51.812074 u2DelayCellOfst[2]=14 cells (4 PI)
7443 11:03:51.815653 u2DelayCellOfst[3]=18 cells (5 PI)
7444 11:03:51.818653 u2DelayCellOfst[4]=10 cells (3 PI)
7445 11:03:51.822027 u2DelayCellOfst[5]=0 cells (0 PI)
7446 11:03:51.825418 u2DelayCellOfst[6]=21 cells (6 PI)
7447 11:03:51.828686 u2DelayCellOfst[7]=21 cells (6 PI)
7448 11:03:51.832107 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7449 11:03:51.835491 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7450 11:03:51.838629 == TX Byte 1 ==
7451 11:03:51.838704 u2DelayCellOfst[8]=3 cells (1 PI)
7452 11:03:51.842038 u2DelayCellOfst[9]=0 cells (0 PI)
7453 11:03:51.845462 u2DelayCellOfst[10]=10 cells (3 PI)
7454 11:03:51.848617 u2DelayCellOfst[11]=7 cells (2 PI)
7455 11:03:51.852147 u2DelayCellOfst[12]=18 cells (5 PI)
7456 11:03:51.855403 u2DelayCellOfst[13]=14 cells (4 PI)
7457 11:03:51.858898 u2DelayCellOfst[14]=18 cells (5 PI)
7458 11:03:51.861948 u2DelayCellOfst[15]=14 cells (4 PI)
7459 11:03:51.865072 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7460 11:03:51.871938 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7461 11:03:51.872014 DramC Write-DBI on
7462 11:03:51.872072 ==
7463 11:03:51.875358 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 11:03:51.878661 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7465 11:03:51.882142 ==
7466 11:03:51.882216
7467 11:03:51.882273
7468 11:03:51.882327 TX Vref Scan disable
7469 11:03:51.885432 == TX Byte 0 ==
7470 11:03:51.888805 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7471 11:03:51.891914 == TX Byte 1 ==
7472 11:03:51.895735 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7473 11:03:51.898839 DramC Write-DBI off
7474 11:03:51.898938
7475 11:03:51.899021 [DATLAT]
7476 11:03:51.899102 Freq=1600, CH0 RK0
7477 11:03:51.899161
7478 11:03:51.901886 DATLAT Default: 0xf
7479 11:03:51.901960 0, 0xFFFF, sum = 0
7480 11:03:51.905196 1, 0xFFFF, sum = 0
7481 11:03:51.908482 2, 0xFFFF, sum = 0
7482 11:03:51.908558 3, 0xFFFF, sum = 0
7483 11:03:51.912138 4, 0xFFFF, sum = 0
7484 11:03:51.912214 5, 0xFFFF, sum = 0
7485 11:03:51.915299 6, 0xFFFF, sum = 0
7486 11:03:51.915374 7, 0xFFFF, sum = 0
7487 11:03:51.918411 8, 0xFFFF, sum = 0
7488 11:03:51.918487 9, 0xFFFF, sum = 0
7489 11:03:51.921748 10, 0xFFFF, sum = 0
7490 11:03:51.921849 11, 0xFFFF, sum = 0
7491 11:03:51.924967 12, 0xBFF, sum = 0
7492 11:03:51.925043 13, 0x0, sum = 1
7493 11:03:51.928381 14, 0x0, sum = 2
7494 11:03:51.928457 15, 0x0, sum = 3
7495 11:03:51.931900 16, 0x0, sum = 4
7496 11:03:51.931976 best_step = 14
7497 11:03:51.932034
7498 11:03:51.932087 ==
7499 11:03:51.935399 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 11:03:51.938287 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7501 11:03:51.941621 ==
7502 11:03:51.941695 RX Vref Scan: 1
7503 11:03:51.941752
7504 11:03:51.945112 Set Vref Range= 24 -> 127
7505 11:03:51.945209
7506 11:03:51.945331 RX Vref 24 -> 127, step: 1
7507 11:03:51.948525
7508 11:03:51.948599 RX Delay 11 -> 252, step: 4
7509 11:03:51.948658
7510 11:03:51.951739 Set Vref, RX VrefLevel [Byte0]: 24
7511 11:03:51.954871 [Byte1]: 24
7512 11:03:51.958478
7513 11:03:51.958552 Set Vref, RX VrefLevel [Byte0]: 25
7514 11:03:51.961950 [Byte1]: 25
7515 11:03:51.966284
7516 11:03:51.966358 Set Vref, RX VrefLevel [Byte0]: 26
7517 11:03:51.969453 [Byte1]: 26
7518 11:03:51.973731
7519 11:03:51.973809 Set Vref, RX VrefLevel [Byte0]: 27
7520 11:03:51.977068 [Byte1]: 27
7521 11:03:51.981185
7522 11:03:51.981279 Set Vref, RX VrefLevel [Byte0]: 28
7523 11:03:51.984782 [Byte1]: 28
7524 11:03:51.988853
7525 11:03:51.988926 Set Vref, RX VrefLevel [Byte0]: 29
7526 11:03:51.992349 [Byte1]: 29
7527 11:03:51.996780
7528 11:03:51.996882 Set Vref, RX VrefLevel [Byte0]: 30
7529 11:03:52.000097 [Byte1]: 30
7530 11:03:52.004371
7531 11:03:52.004445 Set Vref, RX VrefLevel [Byte0]: 31
7532 11:03:52.007419 [Byte1]: 31
7533 11:03:52.012043
7534 11:03:52.012117 Set Vref, RX VrefLevel [Byte0]: 32
7535 11:03:52.015203 [Byte1]: 32
7536 11:03:52.019222
7537 11:03:52.022636 Set Vref, RX VrefLevel [Byte0]: 33
7538 11:03:52.022711 [Byte1]: 33
7539 11:03:52.027438
7540 11:03:52.027512 Set Vref, RX VrefLevel [Byte0]: 34
7541 11:03:52.030249 [Byte1]: 34
7542 11:03:52.034576
7543 11:03:52.034650 Set Vref, RX VrefLevel [Byte0]: 35
7544 11:03:52.037756 [Byte1]: 35
7545 11:03:52.042143
7546 11:03:52.042217 Set Vref, RX VrefLevel [Byte0]: 36
7547 11:03:52.045490 [Byte1]: 36
7548 11:03:52.050097
7549 11:03:52.050171 Set Vref, RX VrefLevel [Byte0]: 37
7550 11:03:52.053233 [Byte1]: 37
7551 11:03:52.057667
7552 11:03:52.057741 Set Vref, RX VrefLevel [Byte0]: 38
7553 11:03:52.061007 [Byte1]: 38
7554 11:03:52.065372
7555 11:03:52.065447 Set Vref, RX VrefLevel [Byte0]: 39
7556 11:03:52.068523 [Byte1]: 39
7557 11:03:52.073126
7558 11:03:52.073200 Set Vref, RX VrefLevel [Byte0]: 40
7559 11:03:52.076021 [Byte1]: 40
7560 11:03:52.080204
7561 11:03:52.080279 Set Vref, RX VrefLevel [Byte0]: 41
7562 11:03:52.083804 [Byte1]: 41
7563 11:03:52.088027
7564 11:03:52.088101 Set Vref, RX VrefLevel [Byte0]: 42
7565 11:03:52.091341 [Byte1]: 42
7566 11:03:52.095661
7567 11:03:52.095735 Set Vref, RX VrefLevel [Byte0]: 43
7568 11:03:52.098684 [Byte1]: 43
7569 11:03:52.103248
7570 11:03:52.103322 Set Vref, RX VrefLevel [Byte0]: 44
7571 11:03:52.106337 [Byte1]: 44
7572 11:03:52.111064
7573 11:03:52.111162 Set Vref, RX VrefLevel [Byte0]: 45
7574 11:03:52.113934 [Byte1]: 45
7575 11:03:52.118285
7576 11:03:52.118360 Set Vref, RX VrefLevel [Byte0]: 46
7577 11:03:52.121495 [Byte1]: 46
7578 11:03:52.126231
7579 11:03:52.126305 Set Vref, RX VrefLevel [Byte0]: 47
7580 11:03:52.129473 [Byte1]: 47
7581 11:03:52.133589
7582 11:03:52.133666 Set Vref, RX VrefLevel [Byte0]: 48
7583 11:03:52.136680 [Byte1]: 48
7584 11:03:52.141089
7585 11:03:52.141163 Set Vref, RX VrefLevel [Byte0]: 49
7586 11:03:52.144564 [Byte1]: 49
7587 11:03:52.148834
7588 11:03:52.148926 Set Vref, RX VrefLevel [Byte0]: 50
7589 11:03:52.152518 [Byte1]: 50
7590 11:03:52.156473
7591 11:03:52.156547 Set Vref, RX VrefLevel [Byte0]: 51
7592 11:03:52.159698 [Byte1]: 51
7593 11:03:52.163953
7594 11:03:52.164028 Set Vref, RX VrefLevel [Byte0]: 52
7595 11:03:52.167477 [Byte1]: 52
7596 11:03:52.171467
7597 11:03:52.171542 Set Vref, RX VrefLevel [Byte0]: 53
7598 11:03:52.175033 [Byte1]: 53
7599 11:03:52.179375
7600 11:03:52.179450 Set Vref, RX VrefLevel [Byte0]: 54
7601 11:03:52.182802 [Byte1]: 54
7602 11:03:52.187188
7603 11:03:52.187259 Set Vref, RX VrefLevel [Byte0]: 55
7604 11:03:52.190204 [Byte1]: 55
7605 11:03:52.194509
7606 11:03:52.194583 Set Vref, RX VrefLevel [Byte0]: 56
7607 11:03:52.197996 [Byte1]: 56
7608 11:03:52.202467
7609 11:03:52.202541 Set Vref, RX VrefLevel [Byte0]: 57
7610 11:03:52.205241 [Byte1]: 57
7611 11:03:52.209667
7612 11:03:52.209741 Set Vref, RX VrefLevel [Byte0]: 58
7613 11:03:52.213150 [Byte1]: 58
7614 11:03:52.217368
7615 11:03:52.217442 Set Vref, RX VrefLevel [Byte0]: 59
7616 11:03:52.220805 [Byte1]: 59
7617 11:03:52.225204
7618 11:03:52.225302 Set Vref, RX VrefLevel [Byte0]: 60
7619 11:03:52.228492 [Byte1]: 60
7620 11:03:52.233006
7621 11:03:52.233080 Set Vref, RX VrefLevel [Byte0]: 61
7622 11:03:52.235760 [Byte1]: 61
7623 11:03:52.240285
7624 11:03:52.240360 Set Vref, RX VrefLevel [Byte0]: 62
7625 11:03:52.243296 [Byte1]: 62
7626 11:03:52.247764
7627 11:03:52.247838 Set Vref, RX VrefLevel [Byte0]: 63
7628 11:03:52.254453 [Byte1]: 63
7629 11:03:52.254527
7630 11:03:52.258070 Set Vref, RX VrefLevel [Byte0]: 64
7631 11:03:52.260843 [Byte1]: 64
7632 11:03:52.260917
7633 11:03:52.264204 Set Vref, RX VrefLevel [Byte0]: 65
7634 11:03:52.267519 [Byte1]: 65
7635 11:03:52.267617
7636 11:03:52.271189 Set Vref, RX VrefLevel [Byte0]: 66
7637 11:03:52.274160 [Byte1]: 66
7638 11:03:52.278159
7639 11:03:52.278233 Set Vref, RX VrefLevel [Byte0]: 67
7640 11:03:52.281694 [Byte1]: 67
7641 11:03:52.286271
7642 11:03:52.286345 Set Vref, RX VrefLevel [Byte0]: 68
7643 11:03:52.289588 [Byte1]: 68
7644 11:03:52.293597
7645 11:03:52.293672 Set Vref, RX VrefLevel [Byte0]: 69
7646 11:03:52.296820 [Byte1]: 69
7647 11:03:52.301457
7648 11:03:52.301531 Set Vref, RX VrefLevel [Byte0]: 70
7649 11:03:52.304563 [Byte1]: 70
7650 11:03:52.308868
7651 11:03:52.308943 Set Vref, RX VrefLevel [Byte0]: 71
7652 11:03:52.312054 [Byte1]: 71
7653 11:03:52.316266
7654 11:03:52.316340 Set Vref, RX VrefLevel [Byte0]: 72
7655 11:03:52.319626 [Byte1]: 72
7656 11:03:52.324140
7657 11:03:52.324214 Set Vref, RX VrefLevel [Byte0]: 73
7658 11:03:52.327254 [Byte1]: 73
7659 11:03:52.331674
7660 11:03:52.331749 Set Vref, RX VrefLevel [Byte0]: 74
7661 11:03:52.335079 [Byte1]: 74
7662 11:03:52.339099
7663 11:03:52.339174 Final RX Vref Byte 0 = 52 to rank0
7664 11:03:52.342607 Final RX Vref Byte 1 = 57 to rank0
7665 11:03:52.345749 Final RX Vref Byte 0 = 52 to rank1
7666 11:03:52.348938 Final RX Vref Byte 1 = 57 to rank1==
7667 11:03:52.352577 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 11:03:52.359098 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7669 11:03:52.359173 ==
7670 11:03:52.359231 DQS Delay:
7671 11:03:52.359284 DQS0 = 0, DQS1 = 0
7672 11:03:52.362278 DQM Delay:
7673 11:03:52.362352 DQM0 = 126, DQM1 = 121
7674 11:03:52.365789 DQ Delay:
7675 11:03:52.369056 DQ0 =122, DQ1 =126, DQ2 =124, DQ3 =124
7676 11:03:52.372541 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7677 11:03:52.376218 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7678 11:03:52.378821 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =132
7679 11:03:52.378896
7680 11:03:52.378952
7681 11:03:52.379036
7682 11:03:52.382249 [DramC_TX_OE_Calibration] TA2
7683 11:03:52.385820 Original DQ_B0 (3 6) =30, OEN = 27
7684 11:03:52.389155 Original DQ_B1 (3 6) =30, OEN = 27
7685 11:03:52.391985 24, 0x0, End_B0=24 End_B1=24
7686 11:03:52.392060 25, 0x0, End_B0=25 End_B1=25
7687 11:03:52.395467 26, 0x0, End_B0=26 End_B1=26
7688 11:03:52.398820 27, 0x0, End_B0=27 End_B1=27
7689 11:03:52.402184 28, 0x0, End_B0=28 End_B1=28
7690 11:03:52.405447 29, 0x0, End_B0=29 End_B1=29
7691 11:03:52.405523 30, 0x0, End_B0=30 End_B1=30
7692 11:03:52.408746 31, 0x4141, End_B0=30 End_B1=30
7693 11:03:52.412088 Byte0 end_step=30 best_step=27
7694 11:03:52.415492 Byte1 end_step=30 best_step=27
7695 11:03:52.418598 Byte0 TX OE(2T, 0.5T) = (3, 3)
7696 11:03:52.421881 Byte1 TX OE(2T, 0.5T) = (3, 3)
7697 11:03:52.421955
7698 11:03:52.422013
7699 11:03:52.428551 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7700 11:03:52.431893 CH0 RK0: MR19=303, MR18=1D1D
7701 11:03:52.438651 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7702 11:03:52.438726
7703 11:03:52.442046 ----->DramcWriteLeveling(PI) begin...
7704 11:03:52.442122 ==
7705 11:03:52.444898 Dram Type= 6, Freq= 0, CH_0, rank 1
7706 11:03:52.448618 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7707 11:03:52.448693 ==
7708 11:03:52.451651 Write leveling (Byte 0): 30 => 30
7709 11:03:52.454789 Write leveling (Byte 1): 24 => 24
7710 11:03:52.458589 DramcWriteLeveling(PI) end<-----
7711 11:03:52.458687
7712 11:03:52.458770 ==
7713 11:03:52.461401 Dram Type= 6, Freq= 0, CH_0, rank 1
7714 11:03:52.464970 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7715 11:03:52.465045 ==
7716 11:03:52.468547 [Gating] SW mode calibration
7717 11:03:52.474962 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7718 11:03:52.481624 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7719 11:03:52.485127 0 12 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7720 11:03:52.488494 0 12 4 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7721 11:03:52.495422 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7722 11:03:52.498627 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7723 11:03:52.501697 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7724 11:03:52.508548 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7725 11:03:52.511463 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7726 11:03:52.515456 0 12 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7727 11:03:52.521776 0 13 0 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (1 0)
7728 11:03:52.524942 0 13 4 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7729 11:03:52.528118 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 11:03:52.534786 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7731 11:03:52.538489 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7732 11:03:52.541691 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7733 11:03:52.547876 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7734 11:03:52.551334 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7735 11:03:52.554420 0 14 0 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
7736 11:03:52.561014 0 14 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7737 11:03:52.564522 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 11:03:52.567995 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7739 11:03:52.574997 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 11:03:52.577939 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7741 11:03:52.581269 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7742 11:03:52.587476 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7743 11:03:52.590889 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7744 11:03:52.594621 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7745 11:03:52.600564 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7746 11:03:52.603965 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 11:03:52.607405 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 11:03:52.614563 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 11:03:52.617363 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 11:03:52.620726 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 11:03:52.627633 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 11:03:52.630842 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 11:03:52.633798 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 11:03:52.640611 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 11:03:52.643928 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 11:03:52.647070 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 11:03:52.653673 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7758 11:03:52.657467 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7759 11:03:52.660182 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7760 11:03:52.667321 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7761 11:03:52.667396 Total UI for P1: 0, mck2ui 16
7762 11:03:52.674007 best dqsien dly found for B0: ( 1, 0, 28)
7763 11:03:52.677130 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7764 11:03:52.680262 Total UI for P1: 0, mck2ui 16
7765 11:03:52.683380 best dqsien dly found for B1: ( 1, 1, 2)
7766 11:03:52.686713 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7767 11:03:52.690179 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7768 11:03:52.690253
7769 11:03:52.693404 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7770 11:03:52.696583 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7771 11:03:52.700125 [Gating] SW calibration Done
7772 11:03:52.700201 ==
7773 11:03:52.703277 Dram Type= 6, Freq= 0, CH_0, rank 1
7774 11:03:52.706367 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7775 11:03:52.709894 ==
7776 11:03:52.709968 RX Vref Scan: 0
7777 11:03:52.710026
7778 11:03:52.713484 RX Vref 0 -> 0, step: 1
7779 11:03:52.713559
7780 11:03:52.713618 RX Delay 0 -> 252, step: 8
7781 11:03:52.719839 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7782 11:03:52.723230 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7783 11:03:52.726746 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7784 11:03:52.729902 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7785 11:03:52.733047 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7786 11:03:52.739914 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7787 11:03:52.743303 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7788 11:03:52.746554 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7789 11:03:52.750160 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7790 11:03:52.753410 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7791 11:03:52.759729 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7792 11:03:52.763034 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7793 11:03:52.766462 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7794 11:03:52.769577 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7795 11:03:52.776283 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7796 11:03:52.779615 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7797 11:03:52.779689 ==
7798 11:03:52.782977 Dram Type= 6, Freq= 0, CH_0, rank 1
7799 11:03:52.786601 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7800 11:03:52.786676 ==
7801 11:03:52.786734 DQS Delay:
7802 11:03:52.789559 DQS0 = 0, DQS1 = 0
7803 11:03:52.789633 DQM Delay:
7804 11:03:52.792958 DQM0 = 131, DQM1 = 124
7805 11:03:52.793032 DQ Delay:
7806 11:03:52.796413 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7807 11:03:52.799605 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7808 11:03:52.803149 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7809 11:03:52.806272 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7810 11:03:52.809904
7811 11:03:52.809977
7812 11:03:52.810034 ==
7813 11:03:52.813071 Dram Type= 6, Freq= 0, CH_0, rank 1
7814 11:03:52.816216 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7815 11:03:52.816291 ==
7816 11:03:52.816349
7817 11:03:52.816402
7818 11:03:52.819622 TX Vref Scan disable
7819 11:03:52.819696 == TX Byte 0 ==
7820 11:03:52.826307 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7821 11:03:52.829426 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7822 11:03:52.829500 == TX Byte 1 ==
7823 11:03:52.836372 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7824 11:03:52.839216 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7825 11:03:52.839291 ==
7826 11:03:52.842623 Dram Type= 6, Freq= 0, CH_0, rank 1
7827 11:03:52.845880 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7828 11:03:52.845955 ==
7829 11:03:52.861347
7830 11:03:52.864455 TX Vref early break, caculate TX vref
7831 11:03:52.867936 TX Vref=16, minBit 1, minWin=22, winSum=373
7832 11:03:52.871413 TX Vref=18, minBit 1, minWin=23, winSum=381
7833 11:03:52.874350 TX Vref=20, minBit 1, minWin=23, winSum=391
7834 11:03:52.877608 TX Vref=22, minBit 1, minWin=24, winSum=398
7835 11:03:52.881566 TX Vref=24, minBit 7, minWin=24, winSum=406
7836 11:03:52.887832 TX Vref=26, minBit 1, minWin=25, winSum=416
7837 11:03:52.890802 TX Vref=28, minBit 4, minWin=25, winSum=415
7838 11:03:52.894650 TX Vref=30, minBit 7, minWin=24, winSum=412
7839 11:03:52.897520 TX Vref=32, minBit 7, minWin=24, winSum=401
7840 11:03:52.901134 TX Vref=34, minBit 8, minWin=23, winSum=395
7841 11:03:52.904126 TX Vref=36, minBit 8, minWin=23, winSum=389
7842 11:03:52.911001 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 26
7843 11:03:52.911076
7844 11:03:52.914341 Final TX Range 0 Vref 26
7845 11:03:52.914416
7846 11:03:52.914473 ==
7847 11:03:52.917658 Dram Type= 6, Freq= 0, CH_0, rank 1
7848 11:03:52.920753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7849 11:03:52.920828 ==
7850 11:03:52.920887
7851 11:03:52.920941
7852 11:03:52.924842 TX Vref Scan disable
7853 11:03:52.930757 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7854 11:03:52.930832 == TX Byte 0 ==
7855 11:03:52.934231 u2DelayCellOfst[0]=14 cells (4 PI)
7856 11:03:52.937684 u2DelayCellOfst[1]=18 cells (5 PI)
7857 11:03:52.940736 u2DelayCellOfst[2]=10 cells (3 PI)
7858 11:03:52.944409 u2DelayCellOfst[3]=10 cells (3 PI)
7859 11:03:52.947971 u2DelayCellOfst[4]=7 cells (2 PI)
7860 11:03:52.950761 u2DelayCellOfst[5]=0 cells (0 PI)
7861 11:03:52.954188 u2DelayCellOfst[6]=18 cells (5 PI)
7862 11:03:52.957369 u2DelayCellOfst[7]=18 cells (5 PI)
7863 11:03:52.960712 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7864 11:03:52.963971 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7865 11:03:52.967769 == TX Byte 1 ==
7866 11:03:52.970680 u2DelayCellOfst[8]=3 cells (1 PI)
7867 11:03:52.974121 u2DelayCellOfst[9]=0 cells (0 PI)
7868 11:03:52.974196 u2DelayCellOfst[10]=10 cells (3 PI)
7869 11:03:52.977673 u2DelayCellOfst[11]=3 cells (1 PI)
7870 11:03:52.980503 u2DelayCellOfst[12]=14 cells (4 PI)
7871 11:03:52.984530 u2DelayCellOfst[13]=18 cells (5 PI)
7872 11:03:52.987319 u2DelayCellOfst[14]=18 cells (5 PI)
7873 11:03:52.990548 u2DelayCellOfst[15]=14 cells (4 PI)
7874 11:03:52.997120 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7875 11:03:53.000557 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
7876 11:03:53.000632 DramC Write-DBI on
7877 11:03:53.000690 ==
7878 11:03:53.004366 Dram Type= 6, Freq= 0, CH_0, rank 1
7879 11:03:53.010282 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7880 11:03:53.010357 ==
7881 11:03:53.010415
7882 11:03:53.010468
7883 11:03:53.010518 TX Vref Scan disable
7884 11:03:53.014574 == TX Byte 0 ==
7885 11:03:53.018275 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7886 11:03:53.021347 == TX Byte 1 ==
7887 11:03:53.024381 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
7888 11:03:53.028320 DramC Write-DBI off
7889 11:03:53.028395
7890 11:03:53.028453 [DATLAT]
7891 11:03:53.028507 Freq=1600, CH0 RK1
7892 11:03:53.028558
7893 11:03:53.031287 DATLAT Default: 0xe
7894 11:03:53.031361 0, 0xFFFF, sum = 0
7895 11:03:53.034714 1, 0xFFFF, sum = 0
7896 11:03:53.034790 2, 0xFFFF, sum = 0
7897 11:03:53.038104 3, 0xFFFF, sum = 0
7898 11:03:53.041390 4, 0xFFFF, sum = 0
7899 11:03:53.041466 5, 0xFFFF, sum = 0
7900 11:03:53.044342 6, 0xFFFF, sum = 0
7901 11:03:53.044418 7, 0xFFFF, sum = 0
7902 11:03:53.047765 8, 0xFFFF, sum = 0
7903 11:03:53.047841 9, 0xFFFF, sum = 0
7904 11:03:53.051074 10, 0xFFFF, sum = 0
7905 11:03:53.051150 11, 0xFFFF, sum = 0
7906 11:03:53.054711 12, 0x8FFF, sum = 0
7907 11:03:53.054786 13, 0x0, sum = 1
7908 11:03:53.058117 14, 0x0, sum = 2
7909 11:03:53.058193 15, 0x0, sum = 3
7910 11:03:53.061178 16, 0x0, sum = 4
7911 11:03:53.061274 best_step = 14
7912 11:03:53.061333
7913 11:03:53.061386 ==
7914 11:03:53.064878 Dram Type= 6, Freq= 0, CH_0, rank 1
7915 11:03:53.067788 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7916 11:03:53.071266 ==
7917 11:03:53.071363 RX Vref Scan: 0
7918 11:03:53.071442
7919 11:03:53.074410 RX Vref 0 -> 0, step: 1
7920 11:03:53.074485
7921 11:03:53.074542 RX Delay 11 -> 252, step: 4
7922 11:03:53.081811 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7923 11:03:53.085369 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7924 11:03:53.088238 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7925 11:03:53.091762 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7926 11:03:53.094900 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
7927 11:03:53.102093 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7928 11:03:53.104889 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7929 11:03:53.108204 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7930 11:03:53.111844 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
7931 11:03:53.115116 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7932 11:03:53.121685 iDelay=195, Bit 10, Center 120 (67 ~ 174) 108
7933 11:03:53.125010 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7934 11:03:53.128373 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7935 11:03:53.131341 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7936 11:03:53.138133 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7937 11:03:53.141406 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7938 11:03:53.141480 ==
7939 11:03:53.144595 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 11:03:53.148378 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7941 11:03:53.148453 ==
7942 11:03:53.148511 DQS Delay:
7943 11:03:53.151560 DQS0 = 0, DQS1 = 0
7944 11:03:53.151634 DQM Delay:
7945 11:03:53.154699 DQM0 = 129, DQM1 = 120
7946 11:03:53.154773 DQ Delay:
7947 11:03:53.158326 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7948 11:03:53.161303 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7949 11:03:53.164660 DQ8 =110, DQ9 =106, DQ10 =120, DQ11 =112
7950 11:03:53.171235 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7951 11:03:53.171309
7952 11:03:53.171367
7953 11:03:53.171420
7954 11:03:53.171470 [DramC_TX_OE_Calibration] TA2
7955 11:03:53.174711 Original DQ_B0 (3 6) =30, OEN = 27
7956 11:03:53.178734 Original DQ_B1 (3 6) =30, OEN = 27
7957 11:03:53.181370 24, 0x0, End_B0=24 End_B1=24
7958 11:03:53.184931 25, 0x0, End_B0=25 End_B1=25
7959 11:03:53.187821 26, 0x0, End_B0=26 End_B1=26
7960 11:03:53.187907 27, 0x0, End_B0=27 End_B1=27
7961 11:03:53.191462 28, 0x0, End_B0=28 End_B1=28
7962 11:03:53.194815 29, 0x0, End_B0=29 End_B1=29
7963 11:03:53.198018 30, 0x0, End_B0=30 End_B1=30
7964 11:03:53.201148 31, 0x4141, End_B0=30 End_B1=30
7965 11:03:53.204848 Byte0 end_step=30 best_step=27
7966 11:03:53.204922 Byte1 end_step=30 best_step=27
7967 11:03:53.208242 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 11:03:53.211334 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 11:03:53.211409
7970 11:03:53.211467
7971 11:03:53.221206 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7972 11:03:53.221304 CH0 RK1: MR19=303, MR18=2222
7973 11:03:53.228205 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
7974 11:03:53.231312 [RxdqsGatingPostProcess] freq 1600
7975 11:03:53.237719 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7976 11:03:53.241034 Pre-setting of DQS Precalculation
7977 11:03:53.244669 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7978 11:03:53.244744 ==
7979 11:03:53.247788 Dram Type= 6, Freq= 0, CH_1, rank 0
7980 11:03:53.254283 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7981 11:03:53.254362 ==
7982 11:03:53.257558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7983 11:03:53.261251 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7984 11:03:53.267538 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7985 11:03:53.274218 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7986 11:03:53.280931 [CA 0] Center 41 (11~72) winsize 62
7987 11:03:53.284307 [CA 1] Center 41 (11~72) winsize 62
7988 11:03:53.287412 [CA 2] Center 37 (8~67) winsize 60
7989 11:03:53.290588 [CA 3] Center 36 (7~66) winsize 60
7990 11:03:53.294039 [CA 4] Center 34 (4~64) winsize 61
7991 11:03:53.297231 [CA 5] Center 34 (4~64) winsize 61
7992 11:03:53.297320
7993 11:03:53.300514 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7994 11:03:53.300589
7995 11:03:53.303838 [CATrainingPosCal] consider 1 rank data
7996 11:03:53.307217 u2DelayCellTimex100 = 271/100 ps
7997 11:03:53.310390 CA0 delay=41 (11~72),Diff = 7 PI (25 cell)
7998 11:03:53.316911 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
7999 11:03:53.320583 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8000 11:03:53.323668 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8001 11:03:53.327172 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8002 11:03:53.330126 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8003 11:03:53.330201
8004 11:03:53.333511 CA PerBit enable=1, Macro0, CA PI delay=34
8005 11:03:53.333585
8006 11:03:53.337184 [CBTSetCACLKResult] CA Dly = 34
8007 11:03:53.340500 CS Dly: 8 (0~39)
8008 11:03:53.343503 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8009 11:03:53.347016 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8010 11:03:53.347091 ==
8011 11:03:53.350104 Dram Type= 6, Freq= 0, CH_1, rank 1
8012 11:03:53.353441 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8013 11:03:53.356747 ==
8014 11:03:53.360661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8015 11:03:53.363647 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8016 11:03:53.369930 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8017 11:03:53.376821 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8018 11:03:53.382879 [CA 0] Center 40 (10~70) winsize 61
8019 11:03:53.386455 [CA 1] Center 39 (9~70) winsize 62
8020 11:03:53.389530 [CA 2] Center 35 (6~65) winsize 60
8021 11:03:53.393038 [CA 3] Center 35 (6~65) winsize 60
8022 11:03:53.396308 [CA 4] Center 32 (3~62) winsize 60
8023 11:03:53.399816 [CA 5] Center 33 (4~63) winsize 60
8024 11:03:53.399891
8025 11:03:53.402887 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8026 11:03:53.402962
8027 11:03:53.406211 [CATrainingPosCal] consider 2 rank data
8028 11:03:53.409621 u2DelayCellTimex100 = 271/100 ps
8029 11:03:53.412933 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8030 11:03:53.419504 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8031 11:03:53.423398 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8032 11:03:53.426239 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8033 11:03:53.429545 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8034 11:03:53.432909 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8035 11:03:53.433011
8036 11:03:53.436048 CA PerBit enable=1, Macro0, CA PI delay=33
8037 11:03:53.436123
8038 11:03:53.439211 [CBTSetCACLKResult] CA Dly = 33
8039 11:03:53.442770 CS Dly: 9 (0~41)
8040 11:03:53.446110 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8041 11:03:53.449295 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8042 11:03:53.449370
8043 11:03:53.452836 ----->DramcWriteLeveling(PI) begin...
8044 11:03:53.452912 ==
8045 11:03:53.455926 Dram Type= 6, Freq= 0, CH_1, rank 0
8046 11:03:53.463043 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8047 11:03:53.463140 ==
8048 11:03:53.465867 Write leveling (Byte 0): 23 => 23
8049 11:03:53.465942 Write leveling (Byte 1): 22 => 22
8050 11:03:53.469348 DramcWriteLeveling(PI) end<-----
8051 11:03:53.469423
8052 11:03:53.469480 ==
8053 11:03:53.473126 Dram Type= 6, Freq= 0, CH_1, rank 0
8054 11:03:53.479229 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8055 11:03:53.479303 ==
8056 11:03:53.482598 [Gating] SW mode calibration
8057 11:03:53.489401 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8058 11:03:53.492587 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8059 11:03:53.499321 0 12 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8060 11:03:53.502394 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:03:53.506350 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:03:53.512706 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:03:53.515837 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 11:03:53.519087 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 11:03:53.525645 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8066 11:03:53.529143 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8067 11:03:53.532669 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8068 11:03:53.535586 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8069 11:03:53.542773 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:03:53.545582 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:03:53.549117 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:03:53.555547 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:03:53.559270 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8074 11:03:53.562663 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8075 11:03:53.568855 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8076 11:03:53.572374 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:03:53.575271 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:03:53.582122 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:03:53.585478 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 11:03:53.588739 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 11:03:53.595535 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8082 11:03:53.598477 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8083 11:03:53.601819 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8084 11:03:53.608761 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8085 11:03:53.611637 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:03:53.615261 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:03:53.621525 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:03:53.624939 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:03:53.628257 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:03:53.635025 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:03:53.638497 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:03:53.641504 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:03:53.647939 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:03:53.651345 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:03:53.654697 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:03:53.661553 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:03:53.664423 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8098 11:03:53.667766 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8099 11:03:53.674643 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8100 11:03:53.677744 Total UI for P1: 0, mck2ui 16
8101 11:03:53.681149 best dqsien dly found for B0: ( 1, 0, 26)
8102 11:03:53.684913 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 11:03:53.687945 Total UI for P1: 0, mck2ui 16
8104 11:03:53.691225 best dqsien dly found for B1: ( 1, 0, 30)
8105 11:03:53.694442 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8106 11:03:53.697994 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8107 11:03:53.698068
8108 11:03:53.700944 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8109 11:03:53.704380 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8110 11:03:53.707625 [Gating] SW calibration Done
8111 11:03:53.707700 ==
8112 11:03:53.711010 Dram Type= 6, Freq= 0, CH_1, rank 0
8113 11:03:53.717432 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8114 11:03:53.717507 ==
8115 11:03:53.717565 RX Vref Scan: 0
8116 11:03:53.717641
8117 11:03:53.720877 RX Vref 0 -> 0, step: 1
8118 11:03:53.720950
8119 11:03:53.724007 RX Delay 0 -> 252, step: 8
8120 11:03:53.727248 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8121 11:03:53.730836 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8122 11:03:53.734083 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8123 11:03:53.737570 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8124 11:03:53.744088 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8125 11:03:53.747331 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8126 11:03:53.750604 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8127 11:03:53.754115 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8128 11:03:53.757303 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8129 11:03:53.764070 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8130 11:03:53.767360 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8131 11:03:53.770388 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8132 11:03:53.773692 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8133 11:03:53.777169 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8134 11:03:53.784313 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8135 11:03:53.787114 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8136 11:03:53.787188 ==
8137 11:03:53.790775 Dram Type= 6, Freq= 0, CH_1, rank 0
8138 11:03:53.793690 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8139 11:03:53.793766 ==
8140 11:03:53.797065 DQS Delay:
8141 11:03:53.797138 DQS0 = 0, DQS1 = 0
8142 11:03:53.797195 DQM Delay:
8143 11:03:53.800548 DQM0 = 129, DQM1 = 125
8144 11:03:53.800622 DQ Delay:
8145 11:03:53.803997 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8146 11:03:53.806721 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8147 11:03:53.813549 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8148 11:03:53.816734 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8149 11:03:53.816839
8150 11:03:53.816900
8151 11:03:53.816954 ==
8152 11:03:53.820217 Dram Type= 6, Freq= 0, CH_1, rank 0
8153 11:03:53.823668 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8154 11:03:53.823743 ==
8155 11:03:53.823801
8156 11:03:53.823853
8157 11:03:53.826783 TX Vref Scan disable
8158 11:03:53.826857 == TX Byte 0 ==
8159 11:03:53.833658 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8160 11:03:53.836998 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8161 11:03:53.837073 == TX Byte 1 ==
8162 11:03:53.843410 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8163 11:03:53.846749 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8164 11:03:53.846824 ==
8165 11:03:53.850145 Dram Type= 6, Freq= 0, CH_1, rank 0
8166 11:03:53.853431 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8167 11:03:53.853506 ==
8168 11:03:53.866892
8169 11:03:53.870371 TX Vref early break, caculate TX vref
8170 11:03:53.873508 TX Vref=16, minBit 3, minWin=21, winSum=370
8171 11:03:53.876885 TX Vref=18, minBit 1, minWin=22, winSum=378
8172 11:03:53.880277 TX Vref=20, minBit 1, minWin=23, winSum=386
8173 11:03:53.883534 TX Vref=22, minBit 3, minWin=23, winSum=396
8174 11:03:53.886830 TX Vref=24, minBit 0, minWin=24, winSum=406
8175 11:03:53.893503 TX Vref=26, minBit 3, minWin=24, winSum=415
8176 11:03:53.896896 TX Vref=28, minBit 3, minWin=24, winSum=410
8177 11:03:53.900219 TX Vref=30, minBit 3, minWin=24, winSum=406
8178 11:03:53.903976 TX Vref=32, minBit 3, minWin=23, winSum=397
8179 11:03:53.906787 TX Vref=34, minBit 3, minWin=22, winSum=384
8180 11:03:53.913471 [TxChooseVref] Worse bit 3, Min win 24, Win sum 415, Final Vref 26
8181 11:03:53.913546
8182 11:03:53.917110 Final TX Range 0 Vref 26
8183 11:03:53.917184
8184 11:03:53.917256 ==
8185 11:03:53.920211 Dram Type= 6, Freq= 0, CH_1, rank 0
8186 11:03:53.923647 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8187 11:03:53.923724 ==
8188 11:03:53.923783
8189 11:03:53.923836
8190 11:03:53.926839 TX Vref Scan disable
8191 11:03:53.933672 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8192 11:03:53.933746 == TX Byte 0 ==
8193 11:03:53.937211 u2DelayCellOfst[0]=14 cells (4 PI)
8194 11:03:53.940191 u2DelayCellOfst[1]=7 cells (2 PI)
8195 11:03:53.943664 u2DelayCellOfst[2]=0 cells (0 PI)
8196 11:03:53.946761 u2DelayCellOfst[3]=3 cells (1 PI)
8197 11:03:53.950319 u2DelayCellOfst[4]=7 cells (2 PI)
8198 11:03:53.953514 u2DelayCellOfst[5]=14 cells (4 PI)
8199 11:03:53.953589 u2DelayCellOfst[6]=14 cells (4 PI)
8200 11:03:53.956922 u2DelayCellOfst[7]=3 cells (1 PI)
8201 11:03:53.963467 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8202 11:03:53.966603 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8203 11:03:53.966678 == TX Byte 1 ==
8204 11:03:53.969924 u2DelayCellOfst[8]=0 cells (0 PI)
8205 11:03:53.973609 u2DelayCellOfst[9]=7 cells (2 PI)
8206 11:03:53.976968 u2DelayCellOfst[10]=10 cells (3 PI)
8207 11:03:53.979883 u2DelayCellOfst[11]=3 cells (1 PI)
8208 11:03:53.983376 u2DelayCellOfst[12]=14 cells (4 PI)
8209 11:03:53.986583 u2DelayCellOfst[13]=18 cells (5 PI)
8210 11:03:53.989937 u2DelayCellOfst[14]=18 cells (5 PI)
8211 11:03:53.993088 u2DelayCellOfst[15]=18 cells (5 PI)
8212 11:03:53.996416 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8213 11:03:53.999980 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8214 11:03:54.003122 DramC Write-DBI on
8215 11:03:54.003196 ==
8216 11:03:54.006773 Dram Type= 6, Freq= 0, CH_1, rank 0
8217 11:03:54.010188 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8218 11:03:54.010263 ==
8219 11:03:54.010321
8220 11:03:54.013013
8221 11:03:54.013087 TX Vref Scan disable
8222 11:03:54.016611 == TX Byte 0 ==
8223 11:03:54.019755 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8224 11:03:54.023325 == TX Byte 1 ==
8225 11:03:54.026517 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8226 11:03:54.026592 DramC Write-DBI off
8227 11:03:54.026650
8228 11:03:54.029722 [DATLAT]
8229 11:03:54.029792 Freq=1600, CH1 RK0
8230 11:03:54.029849
8231 11:03:54.032913 DATLAT Default: 0xf
8232 11:03:54.033004 0, 0xFFFF, sum = 0
8233 11:03:54.036461 1, 0xFFFF, sum = 0
8234 11:03:54.036579 2, 0xFFFF, sum = 0
8235 11:03:54.039843 3, 0xFFFF, sum = 0
8236 11:03:54.039919 4, 0xFFFF, sum = 0
8237 11:03:54.043095 5, 0xFFFF, sum = 0
8238 11:03:54.043165 6, 0xFFFF, sum = 0
8239 11:03:54.046611 7, 0xFFFF, sum = 0
8240 11:03:54.046687 8, 0xFFFF, sum = 0
8241 11:03:54.049810 9, 0xFFFF, sum = 0
8242 11:03:54.052808 10, 0xFFFF, sum = 0
8243 11:03:54.052903 11, 0xFFFF, sum = 0
8244 11:03:54.056515 12, 0xF7F, sum = 0
8245 11:03:54.056591 13, 0x0, sum = 1
8246 11:03:54.059627 14, 0x0, sum = 2
8247 11:03:54.059719 15, 0x0, sum = 3
8248 11:03:54.062729 16, 0x0, sum = 4
8249 11:03:54.062826 best_step = 14
8250 11:03:54.062897
8251 11:03:54.062951 ==
8252 11:03:54.066485 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 11:03:54.069685 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8254 11:03:54.069779 ==
8255 11:03:54.073029 RX Vref Scan: 1
8256 11:03:54.073123
8257 11:03:54.076057 Set Vref Range= 24 -> 127
8258 11:03:54.076145
8259 11:03:54.076228 RX Vref 24 -> 127, step: 1
8260 11:03:54.076312
8261 11:03:54.079419 RX Delay 3 -> 252, step: 4
8262 11:03:54.079513
8263 11:03:54.083010 Set Vref, RX VrefLevel [Byte0]: 24
8264 11:03:54.086316 [Byte1]: 24
8265 11:03:54.086391
8266 11:03:54.089508 Set Vref, RX VrefLevel [Byte0]: 25
8267 11:03:54.093011 [Byte1]: 25
8268 11:03:54.096933
8269 11:03:54.097007 Set Vref, RX VrefLevel [Byte0]: 26
8270 11:03:54.100302 [Byte1]: 26
8271 11:03:54.104964
8272 11:03:54.105038 Set Vref, RX VrefLevel [Byte0]: 27
8273 11:03:54.107674 [Byte1]: 27
8274 11:03:54.112119
8275 11:03:54.112193 Set Vref, RX VrefLevel [Byte0]: 28
8276 11:03:54.115435 [Byte1]: 28
8277 11:03:54.119785
8278 11:03:54.119884 Set Vref, RX VrefLevel [Byte0]: 29
8279 11:03:54.123114 [Byte1]: 29
8280 11:03:54.127862
8281 11:03:54.127936 Set Vref, RX VrefLevel [Byte0]: 30
8282 11:03:54.130952 [Byte1]: 30
8283 11:03:54.135125
8284 11:03:54.135199 Set Vref, RX VrefLevel [Byte0]: 31
8285 11:03:54.138838 [Byte1]: 31
8286 11:03:54.142755
8287 11:03:54.142830 Set Vref, RX VrefLevel [Byte0]: 32
8288 11:03:54.146239 [Byte1]: 32
8289 11:03:54.150747
8290 11:03:54.150821 Set Vref, RX VrefLevel [Byte0]: 33
8291 11:03:54.154119 [Byte1]: 33
8292 11:03:54.158195
8293 11:03:54.158284 Set Vref, RX VrefLevel [Byte0]: 34
8294 11:03:54.161582 [Byte1]: 34
8295 11:03:54.165682
8296 11:03:54.165756 Set Vref, RX VrefLevel [Byte0]: 35
8297 11:03:54.169004 [Byte1]: 35
8298 11:03:54.173376
8299 11:03:54.173450 Set Vref, RX VrefLevel [Byte0]: 36
8300 11:03:54.176642 [Byte1]: 36
8301 11:03:54.180947
8302 11:03:54.181020 Set Vref, RX VrefLevel [Byte0]: 37
8303 11:03:54.184247 [Byte1]: 37
8304 11:03:54.189116
8305 11:03:54.189189 Set Vref, RX VrefLevel [Byte0]: 38
8306 11:03:54.191976 [Byte1]: 38
8307 11:03:54.196715
8308 11:03:54.196788 Set Vref, RX VrefLevel [Byte0]: 39
8309 11:03:54.199456 [Byte1]: 39
8310 11:03:54.203987
8311 11:03:54.204061 Set Vref, RX VrefLevel [Byte0]: 40
8312 11:03:54.207322 [Byte1]: 40
8313 11:03:54.212138
8314 11:03:54.212211 Set Vref, RX VrefLevel [Byte0]: 41
8315 11:03:54.214907 [Byte1]: 41
8316 11:03:54.219364
8317 11:03:54.219438 Set Vref, RX VrefLevel [Byte0]: 42
8318 11:03:54.222500 [Byte1]: 42
8319 11:03:54.226977
8320 11:03:54.227091 Set Vref, RX VrefLevel [Byte0]: 43
8321 11:03:54.230104 [Byte1]: 43
8322 11:03:54.234476
8323 11:03:54.234549 Set Vref, RX VrefLevel [Byte0]: 44
8324 11:03:54.237908 [Byte1]: 44
8325 11:03:54.242262
8326 11:03:54.242335 Set Vref, RX VrefLevel [Byte0]: 45
8327 11:03:54.245531 [Byte1]: 45
8328 11:03:54.250235
8329 11:03:54.250314 Set Vref, RX VrefLevel [Byte0]: 46
8330 11:03:54.253334 [Byte1]: 46
8331 11:03:54.257555
8332 11:03:54.257642 Set Vref, RX VrefLevel [Byte0]: 47
8333 11:03:54.261099 [Byte1]: 47
8334 11:03:54.265493
8335 11:03:54.265593 Set Vref, RX VrefLevel [Byte0]: 48
8336 11:03:54.268799 [Byte1]: 48
8337 11:03:54.273012
8338 11:03:54.273124 Set Vref, RX VrefLevel [Byte0]: 49
8339 11:03:54.276176 [Byte1]: 49
8340 11:03:54.281049
8341 11:03:54.281185 Set Vref, RX VrefLevel [Byte0]: 50
8342 11:03:54.284141 [Byte1]: 50
8343 11:03:54.288389
8344 11:03:54.288545 Set Vref, RX VrefLevel [Byte0]: 51
8345 11:03:54.291608 [Byte1]: 51
8346 11:03:54.295931
8347 11:03:54.296214 Set Vref, RX VrefLevel [Byte0]: 52
8348 11:03:54.299274 [Byte1]: 52
8349 11:03:54.303671
8350 11:03:54.304061 Set Vref, RX VrefLevel [Byte0]: 53
8351 11:03:54.307132 [Byte1]: 53
8352 11:03:54.311561
8353 11:03:54.311969 Set Vref, RX VrefLevel [Byte0]: 54
8354 11:03:54.315225 [Byte1]: 54
8355 11:03:54.319517
8356 11:03:54.320080 Set Vref, RX VrefLevel [Byte0]: 55
8357 11:03:54.322657 [Byte1]: 55
8358 11:03:54.327289
8359 11:03:54.327943 Set Vref, RX VrefLevel [Byte0]: 56
8360 11:03:54.330106 [Byte1]: 56
8361 11:03:54.334845
8362 11:03:54.335406 Set Vref, RX VrefLevel [Byte0]: 57
8363 11:03:54.338206 [Byte1]: 57
8364 11:03:54.342167
8365 11:03:54.342589 Set Vref, RX VrefLevel [Byte0]: 58
8366 11:03:54.345483 [Byte1]: 58
8367 11:03:54.349750
8368 11:03:54.350200 Set Vref, RX VrefLevel [Byte0]: 59
8369 11:03:54.353290 [Byte1]: 59
8370 11:03:54.357749
8371 11:03:54.358173 Set Vref, RX VrefLevel [Byte0]: 60
8372 11:03:54.360784 [Byte1]: 60
8373 11:03:54.365007
8374 11:03:54.365606 Set Vref, RX VrefLevel [Byte0]: 61
8375 11:03:54.368798 [Byte1]: 61
8376 11:03:54.372709
8377 11:03:54.373090 Set Vref, RX VrefLevel [Byte0]: 62
8378 11:03:54.376526 [Byte1]: 62
8379 11:03:54.380604
8380 11:03:54.380987 Set Vref, RX VrefLevel [Byte0]: 63
8381 11:03:54.383810 [Byte1]: 63
8382 11:03:54.388274
8383 11:03:54.388655 Set Vref, RX VrefLevel [Byte0]: 64
8384 11:03:54.391567 [Byte1]: 64
8385 11:03:54.395769
8386 11:03:54.396198 Set Vref, RX VrefLevel [Byte0]: 65
8387 11:03:54.399125 [Byte1]: 65
8388 11:03:54.403456
8389 11:03:54.403905 Set Vref, RX VrefLevel [Byte0]: 66
8390 11:03:54.406817 [Byte1]: 66
8391 11:03:54.411085
8392 11:03:54.411544 Set Vref, RX VrefLevel [Byte0]: 67
8393 11:03:54.414431 [Byte1]: 67
8394 11:03:54.419019
8395 11:03:54.419401 Set Vref, RX VrefLevel [Byte0]: 68
8396 11:03:54.422050 [Byte1]: 68
8397 11:03:54.426542
8398 11:03:54.427015 Set Vref, RX VrefLevel [Byte0]: 69
8399 11:03:54.429557 [Byte1]: 69
8400 11:03:54.434015
8401 11:03:54.434438 Set Vref, RX VrefLevel [Byte0]: 70
8402 11:03:54.437516 [Byte1]: 70
8403 11:03:54.441728
8404 11:03:54.442207 Set Vref, RX VrefLevel [Byte0]: 71
8405 11:03:54.445736 [Byte1]: 71
8406 11:03:54.449765
8407 11:03:54.450237 Set Vref, RX VrefLevel [Byte0]: 72
8408 11:03:54.453113 [Byte1]: 72
8409 11:03:54.457000
8410 11:03:54.457524 Set Vref, RX VrefLevel [Byte0]: 73
8411 11:03:54.460407 [Byte1]: 73
8412 11:03:54.465604
8413 11:03:54.466127 Set Vref, RX VrefLevel [Byte0]: 74
8414 11:03:54.468329 [Byte1]: 74
8415 11:03:54.472201
8416 11:03:54.472700 Set Vref, RX VrefLevel [Byte0]: 75
8417 11:03:54.475706 [Byte1]: 75
8418 11:03:54.480018
8419 11:03:54.480441 Set Vref, RX VrefLevel [Byte0]: 76
8420 11:03:54.483428 [Byte1]: 76
8421 11:03:54.487867
8422 11:03:54.488286 Final RX Vref Byte 0 = 62 to rank0
8423 11:03:54.491395 Final RX Vref Byte 1 = 52 to rank0
8424 11:03:54.494363 Final RX Vref Byte 0 = 62 to rank1
8425 11:03:54.497564 Final RX Vref Byte 1 = 52 to rank1==
8426 11:03:54.501131 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 11:03:54.507853 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8428 11:03:54.508359 ==
8429 11:03:54.508749 DQS Delay:
8430 11:03:54.509146 DQS0 = 0, DQS1 = 0
8431 11:03:54.511259 DQM Delay:
8432 11:03:54.511733 DQM0 = 128, DQM1 = 123
8433 11:03:54.514814 DQ Delay:
8434 11:03:54.517524 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8435 11:03:54.520858 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8436 11:03:54.524366 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8437 11:03:54.527698 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8438 11:03:54.528122
8439 11:03:54.528453
8440 11:03:54.528799
8441 11:03:54.530727 [DramC_TX_OE_Calibration] TA2
8442 11:03:54.534737 Original DQ_B0 (3 6) =30, OEN = 27
8443 11:03:54.537373 Original DQ_B1 (3 6) =30, OEN = 27
8444 11:03:54.540959 24, 0x0, End_B0=24 End_B1=24
8445 11:03:54.541440 25, 0x0, End_B0=25 End_B1=25
8446 11:03:54.544568 26, 0x0, End_B0=26 End_B1=26
8447 11:03:54.547320 27, 0x0, End_B0=27 End_B1=27
8448 11:03:54.551002 28, 0x0, End_B0=28 End_B1=28
8449 11:03:54.554129 29, 0x0, End_B0=29 End_B1=29
8450 11:03:54.554610 30, 0x0, End_B0=30 End_B1=30
8451 11:03:54.557191 31, 0x4141, End_B0=30 End_B1=30
8452 11:03:54.560937 Byte0 end_step=30 best_step=27
8453 11:03:54.564292 Byte1 end_step=30 best_step=27
8454 11:03:54.567399 Byte0 TX OE(2T, 0.5T) = (3, 3)
8455 11:03:54.570756 Byte1 TX OE(2T, 0.5T) = (3, 3)
8456 11:03:54.571225
8457 11:03:54.571552
8458 11:03:54.577300 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8459 11:03:54.580407 CH1 RK0: MR19=303, MR18=2A2A
8460 11:03:54.587383 CH1_RK0: MR19=0x303, MR18=0x2A2A, DQSOSC=388, MR23=63, INC=24, DEC=16
8461 11:03:54.587809
8462 11:03:54.590586 ----->DramcWriteLeveling(PI) begin...
8463 11:03:54.591017 ==
8464 11:03:54.593913 Dram Type= 6, Freq= 0, CH_1, rank 1
8465 11:03:54.597138 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8466 11:03:54.597674 ==
8467 11:03:54.600358 Write leveling (Byte 0): 24 => 24
8468 11:03:54.604196 Write leveling (Byte 1): 21 => 21
8469 11:03:54.607107 DramcWriteLeveling(PI) end<-----
8470 11:03:54.607577
8471 11:03:54.607909 ==
8472 11:03:54.610097 Dram Type= 6, Freq= 0, CH_1, rank 1
8473 11:03:54.613621 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8474 11:03:54.614114 ==
8475 11:03:54.617013 [Gating] SW mode calibration
8476 11:03:54.623803 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8477 11:03:54.630111 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8478 11:03:54.633594 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8479 11:03:54.640163 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 11:03:54.643496 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 11:03:54.647099 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 11:03:54.654189 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 11:03:54.657010 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8484 11:03:54.659939 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
8485 11:03:54.666335 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8486 11:03:54.669910 0 13 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8487 11:03:54.673257 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 11:03:54.679628 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 11:03:54.683081 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 11:03:54.686512 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8491 11:03:54.693505 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8492 11:03:54.696279 0 13 24 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8493 11:03:54.699456 0 13 28 | B1->B0 | 2524 4646 | 1 0 | (0 0) (0 0)
8494 11:03:54.706105 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8495 11:03:54.709266 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 11:03:54.712543 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 11:03:54.715994 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 11:03:54.722993 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 11:03:54.726250 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8500 11:03:54.729390 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8501 11:03:54.736085 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8502 11:03:54.739040 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8503 11:03:54.742343 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 11:03:54.749047 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 11:03:54.752370 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 11:03:54.755644 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 11:03:54.762396 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 11:03:54.765558 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 11:03:54.768748 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 11:03:54.775655 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 11:03:54.779047 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 11:03:54.782127 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 11:03:54.788591 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 11:03:54.791814 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 11:03:54.795137 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8516 11:03:54.801851 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8517 11:03:54.805045 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8518 11:03:54.808793 Total UI for P1: 0, mck2ui 16
8519 11:03:54.812190 best dqsien dly found for B0: ( 1, 0, 22)
8520 11:03:54.814998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8521 11:03:54.821986 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8522 11:03:54.822370 Total UI for P1: 0, mck2ui 16
8523 11:03:54.828384 best dqsien dly found for B1: ( 1, 0, 30)
8524 11:03:54.831668 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8525 11:03:54.835128 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8526 11:03:54.835727
8527 11:03:54.838478 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8528 11:03:54.841600 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8529 11:03:54.845153 [Gating] SW calibration Done
8530 11:03:54.845689 ==
8531 11:03:54.848889 Dram Type= 6, Freq= 0, CH_1, rank 1
8532 11:03:54.851828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8533 11:03:54.852379 ==
8534 11:03:54.854948 RX Vref Scan: 0
8535 11:03:54.855352
8536 11:03:54.855652 RX Vref 0 -> 0, step: 1
8537 11:03:54.855931
8538 11:03:54.858815 RX Delay 0 -> 252, step: 8
8539 11:03:54.864892 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8540 11:03:54.867901 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8541 11:03:54.871203 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8542 11:03:54.874513 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8543 11:03:54.878068 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8544 11:03:54.884403 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8545 11:03:54.888011 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8546 11:03:54.891246 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8547 11:03:54.894466 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8548 11:03:54.897908 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8549 11:03:54.904362 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8550 11:03:54.907923 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8551 11:03:54.911596 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8552 11:03:54.914064 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8553 11:03:54.917974 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8554 11:03:54.924324 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8555 11:03:54.924757 ==
8556 11:03:54.927274 Dram Type= 6, Freq= 0, CH_1, rank 1
8557 11:03:54.930625 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8558 11:03:54.931013 ==
8559 11:03:54.931311 DQS Delay:
8560 11:03:54.934683 DQS0 = 0, DQS1 = 0
8561 11:03:54.935110 DQM Delay:
8562 11:03:54.937556 DQM0 = 131, DQM1 = 124
8563 11:03:54.937955 DQ Delay:
8564 11:03:54.940510 DQ0 =131, DQ1 =131, DQ2 =119, DQ3 =131
8565 11:03:54.944104 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =131
8566 11:03:54.947555 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8567 11:03:54.950947 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8568 11:03:54.953769
8569 11:03:54.954154
8570 11:03:54.954449 ==
8571 11:03:54.957001 Dram Type= 6, Freq= 0, CH_1, rank 1
8572 11:03:54.960340 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8573 11:03:54.960728 ==
8574 11:03:54.961027
8575 11:03:54.961346
8576 11:03:54.963917 TX Vref Scan disable
8577 11:03:54.964302 == TX Byte 0 ==
8578 11:03:54.970915 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8579 11:03:54.973919 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8580 11:03:54.974352 == TX Byte 1 ==
8581 11:03:54.980390 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8582 11:03:54.983575 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8583 11:03:54.983960 ==
8584 11:03:54.987426 Dram Type= 6, Freq= 0, CH_1, rank 1
8585 11:03:54.990160 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8586 11:03:54.990607 ==
8587 11:03:55.004779
8588 11:03:55.008155 TX Vref early break, caculate TX vref
8589 11:03:55.011305 TX Vref=16, minBit 0, minWin=22, winSum=381
8590 11:03:55.014598 TX Vref=18, minBit 0, minWin=22, winSum=389
8591 11:03:55.017643 TX Vref=20, minBit 5, minWin=23, winSum=395
8592 11:03:55.021328 TX Vref=22, minBit 0, minWin=23, winSum=407
8593 11:03:55.024567 TX Vref=24, minBit 0, minWin=25, winSum=416
8594 11:03:55.031263 TX Vref=26, minBit 0, minWin=25, winSum=422
8595 11:03:55.034511 TX Vref=28, minBit 0, minWin=24, winSum=421
8596 11:03:55.037686 TX Vref=30, minBit 0, minWin=24, winSum=418
8597 11:03:55.040995 TX Vref=32, minBit 0, minWin=23, winSum=407
8598 11:03:55.044542 TX Vref=34, minBit 0, minWin=23, winSum=404
8599 11:03:55.048032 TX Vref=36, minBit 0, minWin=22, winSum=394
8600 11:03:55.054468 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8601 11:03:55.054543
8602 11:03:55.057609 Final TX Range 0 Vref 26
8603 11:03:55.057684
8604 11:03:55.057740 ==
8605 11:03:55.060987 Dram Type= 6, Freq= 0, CH_1, rank 1
8606 11:03:55.064326 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8607 11:03:55.064401 ==
8608 11:03:55.064459
8609 11:03:55.064512
8610 11:03:55.067608 TX Vref Scan disable
8611 11:03:55.073912 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8612 11:03:55.073987 == TX Byte 0 ==
8613 11:03:55.077361 u2DelayCellOfst[0]=18 cells (5 PI)
8614 11:03:55.080627 u2DelayCellOfst[1]=7 cells (2 PI)
8615 11:03:55.084044 u2DelayCellOfst[2]=0 cells (0 PI)
8616 11:03:55.087350 u2DelayCellOfst[3]=3 cells (1 PI)
8617 11:03:55.090802 u2DelayCellOfst[4]=7 cells (2 PI)
8618 11:03:55.093991 u2DelayCellOfst[5]=18 cells (5 PI)
8619 11:03:55.097218 u2DelayCellOfst[6]=14 cells (4 PI)
8620 11:03:55.100455 u2DelayCellOfst[7]=3 cells (1 PI)
8621 11:03:55.103998 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8622 11:03:55.107658 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8623 11:03:55.111015 == TX Byte 1 ==
8624 11:03:55.114039 u2DelayCellOfst[8]=0 cells (0 PI)
8625 11:03:55.114465 u2DelayCellOfst[9]=3 cells (1 PI)
8626 11:03:55.117387 u2DelayCellOfst[10]=7 cells (2 PI)
8627 11:03:55.120748 u2DelayCellOfst[11]=0 cells (0 PI)
8628 11:03:55.124525 u2DelayCellOfst[12]=14 cells (4 PI)
8629 11:03:55.127490 u2DelayCellOfst[13]=18 cells (5 PI)
8630 11:03:55.131060 u2DelayCellOfst[14]=18 cells (5 PI)
8631 11:03:55.134320 u2DelayCellOfst[15]=14 cells (4 PI)
8632 11:03:55.138005 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8633 11:03:55.144616 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8634 11:03:55.145129 DramC Write-DBI on
8635 11:03:55.145652 ==
8636 11:03:55.147398 Dram Type= 6, Freq= 0, CH_1, rank 1
8637 11:03:55.154208 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8638 11:03:55.154737 ==
8639 11:03:55.155220
8640 11:03:55.155589
8641 11:03:55.155887 TX Vref Scan disable
8642 11:03:55.157756 == TX Byte 0 ==
8643 11:03:55.161374 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8644 11:03:55.164744 == TX Byte 1 ==
8645 11:03:55.168225 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8646 11:03:55.171316 DramC Write-DBI off
8647 11:03:55.171836
8648 11:03:55.172274 [DATLAT]
8649 11:03:55.172680 Freq=1600, CH1 RK1
8650 11:03:55.173076
8651 11:03:55.174839 DATLAT Default: 0xe
8652 11:03:55.175345 0, 0xFFFF, sum = 0
8653 11:03:55.178056 1, 0xFFFF, sum = 0
8654 11:03:55.181187 2, 0xFFFF, sum = 0
8655 11:03:55.181701 3, 0xFFFF, sum = 0
8656 11:03:55.184477 4, 0xFFFF, sum = 0
8657 11:03:55.184966 5, 0xFFFF, sum = 0
8658 11:03:55.187763 6, 0xFFFF, sum = 0
8659 11:03:55.188335 7, 0xFFFF, sum = 0
8660 11:03:55.190933 8, 0xFFFF, sum = 0
8661 11:03:55.191440 9, 0xFFFF, sum = 0
8662 11:03:55.194528 10, 0xFFFF, sum = 0
8663 11:03:55.195163 11, 0xFFFF, sum = 0
8664 11:03:55.197661 12, 0x8FFF, sum = 0
8665 11:03:55.198227 13, 0x0, sum = 1
8666 11:03:55.200894 14, 0x0, sum = 2
8667 11:03:55.201561 15, 0x0, sum = 3
8668 11:03:55.204579 16, 0x0, sum = 4
8669 11:03:55.205095 best_step = 14
8670 11:03:55.205486
8671 11:03:55.205791 ==
8672 11:03:55.207906 Dram Type= 6, Freq= 0, CH_1, rank 1
8673 11:03:55.210961 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8674 11:03:55.214334 ==
8675 11:03:55.214771 RX Vref Scan: 0
8676 11:03:55.215197
8677 11:03:55.217329 RX Vref 0 -> 0, step: 1
8678 11:03:55.217769
8679 11:03:55.218157 RX Delay 3 -> 252, step: 4
8680 11:03:55.224978 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8681 11:03:55.228082 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8682 11:03:55.231299 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8683 11:03:55.235095 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8684 11:03:55.241416 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8685 11:03:55.244512 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8686 11:03:55.247749 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8687 11:03:55.251104 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8688 11:03:55.254352 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8689 11:03:55.261288 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8690 11:03:55.264717 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8691 11:03:55.267817 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8692 11:03:55.270897 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8693 11:03:55.274775 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8694 11:03:55.281215 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8695 11:03:55.284205 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8696 11:03:55.284627 ==
8697 11:03:55.287674 Dram Type= 6, Freq= 0, CH_1, rank 1
8698 11:03:55.290990 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8699 11:03:55.291432 ==
8700 11:03:55.294501 DQS Delay:
8701 11:03:55.294934 DQS0 = 0, DQS1 = 0
8702 11:03:55.295367 DQM Delay:
8703 11:03:55.297810 DQM0 = 126, DQM1 = 122
8704 11:03:55.298247 DQ Delay:
8705 11:03:55.300894 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8706 11:03:55.304411 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8707 11:03:55.311223 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8708 11:03:55.314188 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8709 11:03:55.314662
8710 11:03:55.315088
8711 11:03:55.315490
8712 11:03:55.317798 [DramC_TX_OE_Calibration] TA2
8713 11:03:55.320652 Original DQ_B0 (3 6) =30, OEN = 27
8714 11:03:55.321132 Original DQ_B1 (3 6) =30, OEN = 27
8715 11:03:55.324299 24, 0x0, End_B0=24 End_B1=24
8716 11:03:55.327463 25, 0x0, End_B0=25 End_B1=25
8717 11:03:55.330486 26, 0x0, End_B0=26 End_B1=26
8718 11:03:55.333843 27, 0x0, End_B0=27 End_B1=27
8719 11:03:55.334334 28, 0x0, End_B0=28 End_B1=28
8720 11:03:55.337147 29, 0x0, End_B0=29 End_B1=29
8721 11:03:55.340305 30, 0x0, End_B0=30 End_B1=30
8722 11:03:55.344054 31, 0x4141, End_B0=30 End_B1=30
8723 11:03:55.347148 Byte0 end_step=30 best_step=27
8724 11:03:55.350110 Byte1 end_step=30 best_step=27
8725 11:03:55.350530 Byte0 TX OE(2T, 0.5T) = (3, 3)
8726 11:03:55.353891 Byte1 TX OE(2T, 0.5T) = (3, 3)
8727 11:03:55.354309
8728 11:03:55.354631
8729 11:03:55.363892 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8730 11:03:55.367629 CH1 RK1: MR19=303, MR18=1E1E
8731 11:03:55.370554 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8732 11:03:55.373729 [RxdqsGatingPostProcess] freq 1600
8733 11:03:55.380252 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8734 11:03:55.384218 Pre-setting of DQS Precalculation
8735 11:03:55.386841 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8736 11:03:55.396969 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8737 11:03:55.403806 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8738 11:03:55.404238
8739 11:03:55.404536
8740 11:03:55.406772 [Calibration Summary] 3200 Mbps
8741 11:03:55.407157 CH 0, Rank 0
8742 11:03:55.409923 SW Impedance : PASS
8743 11:03:55.410308 DUTY Scan : NO K
8744 11:03:55.413191 ZQ Calibration : PASS
8745 11:03:55.416914 Jitter Meter : NO K
8746 11:03:55.417407 CBT Training : PASS
8747 11:03:55.420192 Write leveling : PASS
8748 11:03:55.423010 RX DQS gating : PASS
8749 11:03:55.423393 RX DQ/DQS(RDDQC) : PASS
8750 11:03:55.426357 TX DQ/DQS : PASS
8751 11:03:55.429639 RX DATLAT : PASS
8752 11:03:55.430021 RX DQ/DQS(Engine): PASS
8753 11:03:55.433253 TX OE : PASS
8754 11:03:55.433734 All Pass.
8755 11:03:55.434034
8756 11:03:55.436608 CH 0, Rank 1
8757 11:03:55.437080 SW Impedance : PASS
8758 11:03:55.439711 DUTY Scan : NO K
8759 11:03:55.442898 ZQ Calibration : PASS
8760 11:03:55.443437 Jitter Meter : NO K
8761 11:03:55.446366 CBT Training : PASS
8762 11:03:55.450073 Write leveling : PASS
8763 11:03:55.450455 RX DQS gating : PASS
8764 11:03:55.452889 RX DQ/DQS(RDDQC) : PASS
8765 11:03:55.456494 TX DQ/DQS : PASS
8766 11:03:55.456873 RX DATLAT : PASS
8767 11:03:55.460006 RX DQ/DQS(Engine): PASS
8768 11:03:55.460431 TX OE : PASS
8769 11:03:55.463360 All Pass.
8770 11:03:55.463823
8771 11:03:55.464125 CH 1, Rank 0
8772 11:03:55.466318 SW Impedance : PASS
8773 11:03:55.466699 DUTY Scan : NO K
8774 11:03:55.470040 ZQ Calibration : PASS
8775 11:03:55.472912 Jitter Meter : NO K
8776 11:03:55.473395 CBT Training : PASS
8777 11:03:55.476298 Write leveling : PASS
8778 11:03:55.479571 RX DQS gating : PASS
8779 11:03:55.480004 RX DQ/DQS(RDDQC) : PASS
8780 11:03:55.482705 TX DQ/DQS : PASS
8781 11:03:55.486432 RX DATLAT : PASS
8782 11:03:55.486874 RX DQ/DQS(Engine): PASS
8783 11:03:55.489479 TX OE : PASS
8784 11:03:55.489863 All Pass.
8785 11:03:55.490160
8786 11:03:55.492562 CH 1, Rank 1
8787 11:03:55.492945 SW Impedance : PASS
8788 11:03:55.496448 DUTY Scan : NO K
8789 11:03:55.499649 ZQ Calibration : PASS
8790 11:03:55.500134 Jitter Meter : NO K
8791 11:03:55.502884 CBT Training : PASS
8792 11:03:55.506267 Write leveling : PASS
8793 11:03:55.506764 RX DQS gating : PASS
8794 11:03:55.509297 RX DQ/DQS(RDDQC) : PASS
8795 11:03:55.512649 TX DQ/DQS : PASS
8796 11:03:55.513114 RX DATLAT : PASS
8797 11:03:55.516153 RX DQ/DQS(Engine): PASS
8798 11:03:55.516532 TX OE : PASS
8799 11:03:55.519675 All Pass.
8800 11:03:55.520130
8801 11:03:55.520428 DramC Write-DBI on
8802 11:03:55.522625 PER_BANK_REFRESH: Hybrid Mode
8803 11:03:55.525894 TX_TRACKING: ON
8804 11:03:55.532300 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8805 11:03:55.542242 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8806 11:03:55.549080 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8807 11:03:55.552214 [FAST_K] Save calibration result to emmc
8808 11:03:55.555747 sync common calibartion params.
8809 11:03:55.556223 sync cbt_mode0:0, 1:0
8810 11:03:55.558952 dram_init: ddr_geometry: 0
8811 11:03:55.562226 dram_init: ddr_geometry: 0
8812 11:03:55.565317 dram_init: ddr_geometry: 0
8813 11:03:55.565739 0:dram_rank_size:80000000
8814 11:03:55.568914 1:dram_rank_size:80000000
8815 11:03:55.575698 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8816 11:03:55.576194 DFS_SHUFFLE_HW_MODE: ON
8817 11:03:55.582131 dramc_set_vcore_voltage set vcore to 725000
8818 11:03:55.582554 Read voltage for 1600, 0
8819 11:03:55.582886 Vio18 = 0
8820 11:03:55.585843 Vcore = 725000
8821 11:03:55.586267 Vdram = 0
8822 11:03:55.586597 Vddq = 0
8823 11:03:55.588709 Vmddr = 0
8824 11:03:55.589146 switch to 3200 Mbps bootup
8825 11:03:55.592199 [DramcRunTimeConfig]
8826 11:03:55.592623 PHYPLL
8827 11:03:55.595311 DPM_CONTROL_AFTERK: ON
8828 11:03:55.595730 PER_BANK_REFRESH: ON
8829 11:03:55.598562 REFRESH_OVERHEAD_REDUCTION: ON
8830 11:03:55.602163 CMD_PICG_NEW_MODE: OFF
8831 11:03:55.602584 XRTWTW_NEW_MODE: ON
8832 11:03:55.605540 XRTRTR_NEW_MODE: ON
8833 11:03:55.605960 TX_TRACKING: ON
8834 11:03:55.608743 RDSEL_TRACKING: OFF
8835 11:03:55.612027 DQS Precalculation for DVFS: ON
8836 11:03:55.612495 RX_TRACKING: OFF
8837 11:03:55.615609 HW_GATING DBG: ON
8838 11:03:55.616100 ZQCS_ENABLE_LP4: ON
8839 11:03:55.618666 RX_PICG_NEW_MODE: ON
8840 11:03:55.619278 TX_PICG_NEW_MODE: ON
8841 11:03:55.622275 ENABLE_RX_DCM_DPHY: ON
8842 11:03:55.625698 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8843 11:03:55.629015 DUMMY_READ_FOR_TRACKING: OFF
8844 11:03:55.629574 !!! SPM_CONTROL_AFTERK: OFF
8845 11:03:55.632734 !!! SPM could not control APHY
8846 11:03:55.635607 IMPEDANCE_TRACKING: ON
8847 11:03:55.636106 TEMP_SENSOR: ON
8848 11:03:55.638986 HW_SAVE_FOR_SR: OFF
8849 11:03:55.642218 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8850 11:03:55.645346 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8851 11:03:55.649209 Read ODT Tracking: ON
8852 11:03:55.649753 Refresh Rate DeBounce: ON
8853 11:03:55.652467 DFS_NO_QUEUE_FLUSH: ON
8854 11:03:55.655887 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8855 11:03:55.658329 ENABLE_DFS_RUNTIME_MRW: OFF
8856 11:03:55.658867 DDR_RESERVE_NEW_MODE: ON
8857 11:03:55.662091 MR_CBT_SWITCH_FREQ: ON
8858 11:03:55.665339 =========================
8859 11:03:55.682509 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8860 11:03:55.685714 dram_init: ddr_geometry: 0
8861 11:03:55.704104 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8862 11:03:55.707698 dram_init: dram init end (result: 0)
8863 11:03:55.714157 DRAM-K: Full calibration passed in 23424 msecs
8864 11:03:55.717570 MRC: failed to locate region type 0.
8865 11:03:55.718066 DRAM rank0 size:0x80000000,
8866 11:03:55.720606 DRAM rank1 size=0x80000000
8867 11:03:55.730419 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8868 11:03:55.737621 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8869 11:03:55.743357 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8870 11:03:55.750498 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8871 11:03:55.753750 DRAM rank0 size:0x80000000,
8872 11:03:55.757053 DRAM rank1 size=0x80000000
8873 11:03:55.757609 CBMEM:
8874 11:03:55.760483 IMD: root @ 0xfffff000 254 entries.
8875 11:03:55.763575 IMD: root @ 0xffffec00 62 entries.
8876 11:03:55.766833 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8877 11:03:55.769893 WARNING: RO_VPD is uninitialized or empty.
8878 11:03:55.776767 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8879 11:03:55.783301 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8880 11:03:55.796621 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8881 11:03:55.807794 BS: romstage times (exec / console): total (unknown) / 22961 ms
8882 11:03:55.808267
8883 11:03:55.808591
8884 11:03:55.817762 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8885 11:03:55.821360 ARM64: Exception handlers installed.
8886 11:03:55.823939 ARM64: Testing exception
8887 11:03:55.827228 ARM64: Done test exception
8888 11:03:55.827661 Enumerating buses...
8889 11:03:55.830570 Show all devs... Before device enumeration.
8890 11:03:55.834050 Root Device: enabled 1
8891 11:03:55.837355 CPU_CLUSTER: 0: enabled 1
8892 11:03:55.837813 CPU: 00: enabled 1
8893 11:03:55.840553 Compare with tree...
8894 11:03:55.840972 Root Device: enabled 1
8895 11:03:55.843830 CPU_CLUSTER: 0: enabled 1
8896 11:03:55.847109 CPU: 00: enabled 1
8897 11:03:55.847530 Root Device scanning...
8898 11:03:55.850589 scan_static_bus for Root Device
8899 11:03:55.854107 CPU_CLUSTER: 0 enabled
8900 11:03:55.857195 scan_static_bus for Root Device done
8901 11:03:55.860429 scan_bus: bus Root Device finished in 8 msecs
8902 11:03:55.860850 done
8903 11:03:55.866952 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8904 11:03:55.870408 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8905 11:03:55.877454 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8906 11:03:55.880192 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8907 11:03:55.883566 Allocating resources...
8908 11:03:55.887058 Reading resources...
8909 11:03:55.890206 Root Device read_resources bus 0 link: 0
8910 11:03:55.890631 DRAM rank0 size:0x80000000,
8911 11:03:55.894102 DRAM rank1 size=0x80000000
8912 11:03:55.897126 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8913 11:03:55.900162 CPU: 00 missing read_resources
8914 11:03:55.903439 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8915 11:03:55.909980 Root Device read_resources bus 0 link: 0 done
8916 11:03:55.910365 Done reading resources.
8917 11:03:55.917003 Show resources in subtree (Root Device)...After reading.
8918 11:03:55.920186 Root Device child on link 0 CPU_CLUSTER: 0
8919 11:03:55.923454 CPU_CLUSTER: 0 child on link 0 CPU: 00
8920 11:03:55.933387 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8921 11:03:55.933774 CPU: 00
8922 11:03:55.936467 Root Device assign_resources, bus 0 link: 0
8923 11:03:55.940095 CPU_CLUSTER: 0 missing set_resources
8924 11:03:55.946773 Root Device assign_resources, bus 0 link: 0 done
8925 11:03:55.947199 Done setting resources.
8926 11:03:55.953388 Show resources in subtree (Root Device)...After assigning values.
8927 11:03:55.956553 Root Device child on link 0 CPU_CLUSTER: 0
8928 11:03:55.959786 CPU_CLUSTER: 0 child on link 0 CPU: 00
8929 11:03:55.969908 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8930 11:03:55.970646 CPU: 00
8931 11:03:55.973334 Done allocating resources.
8932 11:03:55.976565 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8933 11:03:55.979922 Enabling resources...
8934 11:03:55.980302 done.
8935 11:03:55.986510 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8936 11:03:55.986893 Initializing devices...
8937 11:03:55.989659 Root Device init
8938 11:03:55.990100 init hardware done!
8939 11:03:55.993195 0x00000018: ctrlr->caps
8940 11:03:55.996243 52.000 MHz: ctrlr->f_max
8941 11:03:55.996634 0.400 MHz: ctrlr->f_min
8942 11:03:55.999545 0x40ff8080: ctrlr->voltages
8943 11:03:56.000136 sclk: 390625
8944 11:03:56.002907 Bus Width = 1
8945 11:03:56.003284 sclk: 390625
8946 11:03:56.006542 Bus Width = 1
8947 11:03:56.006920 Early init status = 3
8948 11:03:56.013157 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8949 11:03:56.016514 in-header: 03 fc 00 00 01 00 00 00
8950 11:03:56.016897 in-data: 00
8951 11:03:56.023306 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8952 11:03:56.026774 in-header: 03 fd 00 00 00 00 00 00
8953 11:03:56.029993 in-data:
8954 11:03:56.032984 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8955 11:03:56.036893 in-header: 03 fc 00 00 01 00 00 00
8956 11:03:56.040171 in-data: 00
8957 11:03:56.043363 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8958 11:03:56.048201 in-header: 03 fd 00 00 00 00 00 00
8959 11:03:56.052038 in-data:
8960 11:03:56.054886 [SSUSB] Setting up USB HOST controller...
8961 11:03:56.058321 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8962 11:03:56.061741 [SSUSB] phy power-on done.
8963 11:03:56.065331 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8964 11:03:56.071707 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8965 11:03:56.075155 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8966 11:03:56.081846 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8967 11:03:56.088482 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8968 11:03:56.094987 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8969 11:03:56.101936 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8970 11:03:56.108248 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8971 11:03:56.111780 SPM: binary array size = 0x9dc
8972 11:03:56.115127 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8973 11:03:56.121294 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8974 11:03:56.128314 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8975 11:03:56.131590 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8976 11:03:56.137984 configure_display: Starting display init
8977 11:03:56.171634 anx7625_power_on_init: Init interface.
8978 11:03:56.175091 anx7625_disable_pd_protocol: Disabled PD feature.
8979 11:03:56.178345 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8980 11:03:56.206282 anx7625_start_dp_work: Secure OCM version=00
8981 11:03:56.209338 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8982 11:03:56.224057 sp_tx_get_edid_block: EDID Block = 1
8983 11:03:56.326760 Extracted contents:
8984 11:03:56.330036 header: 00 ff ff ff ff ff ff 00
8985 11:03:56.332855 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8986 11:03:56.336437 version: 01 04
8987 11:03:56.339481 basic params: 95 1f 11 78 0a
8988 11:03:56.342813 chroma info: 76 90 94 55 54 90 27 21 50 54
8989 11:03:56.346644 established: 00 00 00
8990 11:03:56.353128 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8991 11:03:56.359618 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8992 11:03:56.362761 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8993 11:03:56.369593 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8994 11:03:56.376179 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8995 11:03:56.379519 extensions: 00
8996 11:03:56.379943 checksum: fb
8997 11:03:56.380270
8998 11:03:56.382741 Manufacturer: IVO Model 57d Serial Number 0
8999 11:03:56.386076 Made week 0 of 2020
9000 11:03:56.386565 EDID version: 1.4
9001 11:03:56.389502 Digital display
9002 11:03:56.392808 6 bits per primary color channel
9003 11:03:56.393196 DisplayPort interface
9004 11:03:56.396218 Maximum image size: 31 cm x 17 cm
9005 11:03:56.399560 Gamma: 220%
9006 11:03:56.400025 Check DPMS levels
9007 11:03:56.402883 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9008 11:03:56.410000 First detailed timing is preferred timing
9009 11:03:56.410443 Established timings supported:
9010 11:03:56.413173 Standard timings supported:
9011 11:03:56.416289 Detailed timings
9012 11:03:56.419622 Hex of detail: 383680a07038204018303c0035ae10000019
9013 11:03:56.422745 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9014 11:03:56.429586 0780 0798 07c8 0820 hborder 0
9015 11:03:56.432703 0438 043b 0447 0458 vborder 0
9016 11:03:56.436168 -hsync -vsync
9017 11:03:56.436777 Did detailed timing
9018 11:03:56.442420 Hex of detail: 000000000000000000000000000000000000
9019 11:03:56.442839 Manufacturer-specified data, tag 0
9020 11:03:56.449506 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9021 11:03:56.452752 ASCII string: InfoVision
9022 11:03:56.456274 Hex of detail: 000000fe00523134304e574635205248200a
9023 11:03:56.459152 ASCII string: R140NWF5 RH
9024 11:03:56.459543 Checksum
9025 11:03:56.462445 Checksum: 0xfb (valid)
9026 11:03:56.465795 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9027 11:03:56.469014 DSI data_rate: 832800000 bps
9028 11:03:56.476254 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9029 11:03:56.479273 anx7625_parse_edid: pixelclock(138800).
9030 11:03:56.482920 hactive(1920), hsync(48), hfp(24), hbp(88)
9031 11:03:56.485609 vactive(1080), vsync(12), vfp(3), vbp(17)
9032 11:03:56.489221 anx7625_dsi_config: config dsi.
9033 11:03:56.495474 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9034 11:03:56.509187 anx7625_dsi_config: success to config DSI
9035 11:03:56.512166 anx7625_dp_start: MIPI phy setup OK.
9036 11:03:56.515640 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9037 11:03:56.519102 mtk_ddp_mode_set invalid vrefresh 60
9038 11:03:56.522152 main_disp_path_setup
9039 11:03:56.522534 ovl_layer_smi_id_en
9040 11:03:56.525490 ovl_layer_smi_id_en
9041 11:03:56.525871 ccorr_config
9042 11:03:56.526167 aal_config
9043 11:03:56.529173 gamma_config
9044 11:03:56.529585 postmask_config
9045 11:03:56.532453 dither_config
9046 11:03:56.536497 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9047 11:03:56.542299 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9048 11:03:56.545537 Root Device init finished in 552 msecs
9049 11:03:56.545964 CPU_CLUSTER: 0 init
9050 11:03:56.556003 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9051 11:03:56.558911 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9052 11:03:56.562176 APU_MBOX 0x190000b0 = 0x10001
9053 11:03:56.565296 APU_MBOX 0x190001b0 = 0x10001
9054 11:03:56.568791 APU_MBOX 0x190005b0 = 0x10001
9055 11:03:56.572433 APU_MBOX 0x190006b0 = 0x10001
9056 11:03:56.575895 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9057 11:03:56.587628 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9058 11:03:56.600143 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9059 11:03:56.607018 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9060 11:03:56.618445 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9061 11:03:56.627843 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9062 11:03:56.630775 CPU_CLUSTER: 0 init finished in 81 msecs
9063 11:03:56.634069 Devices initialized
9064 11:03:56.637208 Show all devs... After init.
9065 11:03:56.637722 Root Device: enabled 1
9066 11:03:56.640992 CPU_CLUSTER: 0: enabled 1
9067 11:03:56.644164 CPU: 00: enabled 1
9068 11:03:56.647604 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9069 11:03:56.651019 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9070 11:03:56.654254 ELOG: NV offset 0x57f000 size 0x1000
9071 11:03:56.660616 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9072 11:03:56.667700 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9073 11:03:56.670760 ELOG: Event(17) added with size 13 at 2024-07-10 11:03:55 UTC
9074 11:03:56.673991 out: cmd=0x121: 03 db 21 01 00 00 00 00
9075 11:03:56.677543 in-header: 03 32 00 00 2c 00 00 00
9076 11:03:56.690973 in-data: 10 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9077 11:03:56.697503 ELOG: Event(A1) added with size 10 at 2024-07-10 11:03:55 UTC
9078 11:03:56.704575 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9079 11:03:56.707787 ELOG: Event(A0) added with size 9 at 2024-07-10 11:03:55 UTC
9080 11:03:56.714449 elog_add_boot_reason: Logged dev mode boot
9081 11:03:56.717746 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9082 11:03:56.721200 Finalize devices...
9083 11:03:56.721732 Devices finalized
9084 11:03:56.727503 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9085 11:03:56.730883 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9086 11:03:56.734229 in-header: 03 07 00 00 08 00 00 00
9087 11:03:56.737533 in-data: aa e4 47 04 13 02 00 00
9088 11:03:56.737915 Chrome EC: UHEPI supported
9089 11:03:56.744400 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9090 11:03:56.747797 in-header: 03 a9 00 00 08 00 00 00
9091 11:03:56.751194 in-data: 84 60 60 08 00 00 00 00
9092 11:03:56.757677 ELOG: Event(91) added with size 10 at 2024-07-10 11:03:55 UTC
9093 11:03:56.761211 Chrome EC: clear events_b mask to 0x0000000020004000
9094 11:03:56.767468 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9095 11:03:56.772223 in-header: 03 fd 00 00 00 00 00 00
9096 11:03:56.775507 in-data:
9097 11:03:56.779101 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9098 11:03:56.782156 Writing coreboot table at 0xffe64000
9099 11:03:56.785385 0. 000000000010a000-0000000000113fff: RAMSTAGE
9100 11:03:56.792155 1. 0000000040000000-00000000400fffff: RAM
9101 11:03:56.795741 2. 0000000040100000-000000004032afff: RAMSTAGE
9102 11:03:56.798699 3. 000000004032b000-00000000545fffff: RAM
9103 11:03:56.802185 4. 0000000054600000-000000005465ffff: BL31
9104 11:03:56.805638 5. 0000000054660000-00000000ffe63fff: RAM
9105 11:03:56.812351 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9106 11:03:56.815255 7. 0000000100000000-000000013fffffff: RAM
9107 11:03:56.818817 Passing 5 GPIOs to payload:
9108 11:03:56.822113 NAME | PORT | POLARITY | VALUE
9109 11:03:56.828585 EC in RW | 0x000000aa | low | undefined
9110 11:03:56.832205 EC interrupt | 0x00000005 | low | undefined
9111 11:03:56.835618 TPM interrupt | 0x000000ab | high | undefined
9112 11:03:56.842505 SD card detect | 0x00000011 | high | undefined
9113 11:03:56.845202 speaker enable | 0x00000093 | high | undefined
9114 11:03:56.848973 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9115 11:03:56.851981 in-header: 03 f8 00 00 02 00 00 00
9116 11:03:56.855673 in-data: 03 00
9117 11:03:56.858970 ADC[4]: Raw value=669327 ID=5
9118 11:03:56.859353 ADC[3]: Raw value=212917 ID=1
9119 11:03:56.862037 RAM Code: 0x51
9120 11:03:56.865047 ADC[6]: Raw value=74410 ID=0
9121 11:03:56.865459 ADC[5]: Raw value=211444 ID=1
9122 11:03:56.868391 SKU Code: 0x1
9123 11:03:56.875295 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2a67
9124 11:03:56.875693 coreboot table: 964 bytes.
9125 11:03:56.878941 IMD ROOT 0. 0xfffff000 0x00001000
9126 11:03:56.881640 IMD SMALL 1. 0xffffe000 0x00001000
9127 11:03:56.885636 RO MCACHE 2. 0xffffc000 0x00001104
9128 11:03:56.888513 CONSOLE 3. 0xfff7c000 0x00080000
9129 11:03:56.892094 FMAP 4. 0xfff7b000 0x00000452
9130 11:03:56.895114 TIME STAMP 5. 0xfff7a000 0x00000910
9131 11:03:56.898473 VBOOT WORK 6. 0xfff66000 0x00014000
9132 11:03:56.901665 RAMOOPS 7. 0xffe66000 0x00100000
9133 11:03:56.905084 COREBOOT 8. 0xffe64000 0x00002000
9134 11:03:56.908471 IMD small region:
9135 11:03:56.911654 IMD ROOT 0. 0xffffec00 0x00000400
9136 11:03:56.915249 VPD 1. 0xffffeb80 0x0000006c
9137 11:03:56.918659 MMC STATUS 2. 0xffffeb60 0x00000004
9138 11:03:56.922044 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9139 11:03:56.928605 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9140 11:03:56.969294 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9141 11:03:56.972627 Checking segment from ROM address 0x40100000
9142 11:03:56.976205 Checking segment from ROM address 0x4010001c
9143 11:03:56.982579 Loading segment from ROM address 0x40100000
9144 11:03:56.982957 code (compression=0)
9145 11:03:56.992728 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9146 11:03:56.999409 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9147 11:03:56.999819 it's not compressed!
9148 11:03:57.005901 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9149 11:03:57.009185 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9150 11:03:57.029778 Loading segment from ROM address 0x4010001c
9151 11:03:57.030274 Entry Point 0x80000000
9152 11:03:57.033436 Loaded segments
9153 11:03:57.036251 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9154 11:03:57.043180 Jumping to boot code at 0x80000000(0xffe64000)
9155 11:03:57.049711 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9156 11:03:57.056132 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9157 11:03:57.064259 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9158 11:03:57.067340 Checking segment from ROM address 0x40100000
9159 11:03:57.070732 Checking segment from ROM address 0x4010001c
9160 11:03:57.078459 Loading segment from ROM address 0x40100000
9161 11:03:57.079009 code (compression=1)
9162 11:03:57.084067 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9163 11:03:57.093878 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9164 11:03:57.094345 using LZMA
9165 11:03:57.102848 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9166 11:03:57.109109 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9167 11:03:57.112248 Loading segment from ROM address 0x4010001c
9168 11:03:57.112669 Entry Point 0x54601000
9169 11:03:57.116050 Loaded segments
9170 11:03:57.118759 NOTICE: MT8192 bl31_setup
9171 11:03:57.125695 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9172 11:03:57.129197 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9173 11:03:57.132505 WARNING: region 0:
9174 11:03:57.136099 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9175 11:03:57.136769 WARNING: region 1:
9176 11:03:57.142457 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9177 11:03:57.145886 WARNING: region 2:
9178 11:03:57.149468 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9179 11:03:57.152592 WARNING: region 3:
9180 11:03:57.156010 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9181 11:03:57.159705 WARNING: region 4:
9182 11:03:57.165993 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9183 11:03:57.166584 WARNING: region 5:
9184 11:03:57.169222 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9185 11:03:57.172581 WARNING: region 6:
9186 11:03:57.175720 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9187 11:03:57.179574 WARNING: region 7:
9188 11:03:57.182544 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9189 11:03:57.189119 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9190 11:03:57.192760 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9191 11:03:57.195862 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9192 11:03:57.202480 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9193 11:03:57.206211 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9194 11:03:57.209150 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9195 11:03:57.215731 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9196 11:03:57.219085 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9197 11:03:57.225691 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9198 11:03:57.229196 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9199 11:03:57.232233 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9200 11:03:57.239199 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9201 11:03:57.242181 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9202 11:03:57.245843 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9203 11:03:57.252276 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9204 11:03:57.255583 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9205 11:03:57.262293 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9206 11:03:57.265780 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9207 11:03:57.269033 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9208 11:03:57.275900 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9209 11:03:57.279050 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9210 11:03:57.282458 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9211 11:03:57.289018 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9212 11:03:57.292323 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9213 11:03:57.298702 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9214 11:03:57.302592 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9215 11:03:57.305500 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9216 11:03:57.312318 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9217 11:03:57.315802 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9218 11:03:57.322321 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9219 11:03:57.325600 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9220 11:03:57.328973 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9221 11:03:57.335564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9222 11:03:57.338767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9223 11:03:57.342014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9224 11:03:57.345632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9225 11:03:57.352132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9226 11:03:57.355148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9227 11:03:57.358394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9228 11:03:57.361857 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9229 11:03:57.368826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9230 11:03:57.372124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9231 11:03:57.375312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9232 11:03:57.378717 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9233 11:03:57.385036 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9234 11:03:57.388559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9235 11:03:57.391819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9236 11:03:57.398249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9237 11:03:57.402094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9238 11:03:57.405155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9239 11:03:57.411875 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9240 11:03:57.415714 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9241 11:03:57.422080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9242 11:03:57.425084 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9243 11:03:57.428557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9244 11:03:57.435625 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9245 11:03:57.438401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9246 11:03:57.445037 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9247 11:03:57.448657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9248 11:03:57.455548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9249 11:03:57.459006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9250 11:03:57.465013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9251 11:03:57.468685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9252 11:03:57.471635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9253 11:03:57.478573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9254 11:03:57.482268 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9255 11:03:57.488651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9256 11:03:57.491645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9257 11:03:57.499016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9258 11:03:57.502222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9259 11:03:57.505273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9260 11:03:57.512288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9261 11:03:57.515087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9262 11:03:57.521838 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9263 11:03:57.525558 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9264 11:03:57.531930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9265 11:03:57.535649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9266 11:03:57.541895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9267 11:03:57.545050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9268 11:03:57.548865 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9269 11:03:57.555276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9270 11:03:57.558321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9271 11:03:57.565099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9272 11:03:57.568557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9273 11:03:57.575321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9274 11:03:57.578282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9275 11:03:57.581634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9276 11:03:57.588418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9277 11:03:57.591665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9278 11:03:57.598433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9279 11:03:57.601983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9280 11:03:57.608408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9281 11:03:57.612014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9282 11:03:57.614965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9283 11:03:57.621926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9284 11:03:57.624706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9285 11:03:57.631427 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9286 11:03:57.635126 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9287 11:03:57.638737 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9288 11:03:57.641550 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9289 11:03:57.648489 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9290 11:03:57.651373 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9291 11:03:57.654787 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9292 11:03:57.661445 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9293 11:03:57.665452 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9294 11:03:57.671572 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9295 11:03:57.675078 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9296 11:03:57.678330 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9297 11:03:57.684679 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9298 11:03:57.688504 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9299 11:03:57.694771 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9300 11:03:57.698015 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9301 11:03:57.701520 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9302 11:03:57.708377 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9303 11:03:57.711854 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9304 11:03:57.714961 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9305 11:03:57.721507 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9306 11:03:57.725044 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9307 11:03:57.728292 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9308 11:03:57.734951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9309 11:03:57.738246 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9310 11:03:57.741569 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9311 11:03:57.745302 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9312 11:03:57.751876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9313 11:03:57.755227 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9314 11:03:57.758696 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9315 11:03:57.764908 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9316 11:03:57.768732 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9317 11:03:57.775462 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9318 11:03:57.778903 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9319 11:03:57.782102 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9320 11:03:57.788455 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9321 11:03:57.791792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9322 11:03:57.795497 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9323 11:03:57.801928 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9324 11:03:57.805435 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9325 11:03:57.812218 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9326 11:03:57.815369 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9327 11:03:57.818473 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9328 11:03:57.825313 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9329 11:03:57.828900 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9330 11:03:57.835611 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9331 11:03:57.838381 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9332 11:03:57.842221 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9333 11:03:57.848401 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9334 11:03:57.851531 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9335 11:03:57.854768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9336 11:03:57.862233 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9337 11:03:57.865598 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9338 11:03:57.871604 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9339 11:03:57.875280 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9340 11:03:57.878469 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9341 11:03:57.885050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9342 11:03:57.888496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9343 11:03:57.894878 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9344 11:03:57.898214 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9345 11:03:57.901204 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9346 11:03:57.907834 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9347 11:03:57.911690 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9348 11:03:57.917801 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9349 11:03:57.921921 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9350 11:03:57.924845 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9351 11:03:57.931860 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9352 11:03:57.934714 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9353 11:03:57.941290 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9354 11:03:57.944708 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9355 11:03:57.948265 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9356 11:03:57.954293 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9357 11:03:57.958363 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9358 11:03:57.961452 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9359 11:03:57.968247 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9360 11:03:57.971427 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9361 11:03:57.978103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9362 11:03:57.981383 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9363 11:03:57.984427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9364 11:03:57.991604 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9365 11:03:57.994829 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9366 11:03:58.001530 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9367 11:03:58.004233 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9368 11:03:58.007711 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9369 11:03:58.014534 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9370 11:03:58.017849 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9371 11:03:58.024145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9372 11:03:58.027687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9373 11:03:58.030862 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9374 11:03:58.037617 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9375 11:03:58.041004 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9376 11:03:58.044331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9377 11:03:58.051083 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9378 11:03:58.054292 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9379 11:03:58.060870 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9380 11:03:58.063966 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9381 11:03:58.070715 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9382 11:03:58.074220 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9383 11:03:58.077439 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9384 11:03:58.084110 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9385 11:03:58.087510 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9386 11:03:58.094595 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9387 11:03:58.097385 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9388 11:03:58.100755 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9389 11:03:58.108045 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9390 11:03:58.111152 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9391 11:03:58.117585 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9392 11:03:58.120783 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9393 11:03:58.127865 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9394 11:03:58.130795 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9395 11:03:58.134117 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9396 11:03:58.140938 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9397 11:03:58.144018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9398 11:03:58.150717 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9399 11:03:58.154309 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9400 11:03:58.157474 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9401 11:03:58.164264 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9402 11:03:58.167374 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9403 11:03:58.174065 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9404 11:03:58.177480 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9405 11:03:58.180523 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9406 11:03:58.187890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9407 11:03:58.190839 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9408 11:03:58.197482 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9409 11:03:58.200836 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9410 11:03:58.204588 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9411 11:03:58.210875 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9412 11:03:58.214009 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9413 11:03:58.221394 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9414 11:03:58.224474 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9415 11:03:58.230594 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9416 11:03:58.234202 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9417 11:03:58.237535 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9418 11:03:58.244232 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9419 11:03:58.247634 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9420 11:03:58.250753 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9421 11:03:58.253964 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9422 11:03:58.257429 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9423 11:03:58.263999 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9424 11:03:58.267654 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9425 11:03:58.273783 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9426 11:03:58.277029 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9427 11:03:58.280512 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9428 11:03:58.287020 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9429 11:03:58.290288 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9430 11:03:58.293721 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9431 11:03:58.300273 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9432 11:03:58.303531 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9433 11:03:58.310373 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9434 11:03:58.313771 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9435 11:03:58.317385 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9436 11:03:58.323747 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9437 11:03:58.327233 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9438 11:03:58.330486 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9439 11:03:58.336626 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9440 11:03:58.339910 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9441 11:03:58.346832 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9442 11:03:58.349852 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9443 11:03:58.353489 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9444 11:03:58.360248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9445 11:03:58.363523 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9446 11:03:58.367078 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9447 11:03:58.373391 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9448 11:03:58.376885 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9449 11:03:58.380054 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9450 11:03:58.386535 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9451 11:03:58.390363 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9452 11:03:58.393094 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9453 11:03:58.399723 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9454 11:03:58.403261 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9455 11:03:58.410062 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9456 11:03:58.413300 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9457 11:03:58.416838 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9458 11:03:58.420090 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9459 11:03:58.426593 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9460 11:03:58.429605 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9461 11:03:58.433552 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9462 11:03:58.436594 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9463 11:03:58.443020 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9464 11:03:58.446750 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9465 11:03:58.449645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9466 11:03:58.452879 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9467 11:03:58.459501 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9468 11:03:58.462937 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9469 11:03:58.466340 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9470 11:03:58.470150 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9471 11:03:58.476683 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9472 11:03:58.479932 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9473 11:03:58.486629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9474 11:03:58.489882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9475 11:03:58.496748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9476 11:03:58.499527 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9477 11:03:58.503298 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9478 11:03:58.509940 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9479 11:03:58.512951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9480 11:03:58.516177 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9481 11:03:58.523125 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9482 11:03:58.526424 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9483 11:03:58.533290 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9484 11:03:58.536521 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9485 11:03:58.543018 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9486 11:03:58.546430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9487 11:03:58.550472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9488 11:03:58.556312 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9489 11:03:58.559742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9490 11:03:58.566745 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9491 11:03:58.570214 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9492 11:03:58.573286 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9493 11:03:58.580029 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9494 11:03:58.583515 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9495 11:03:58.586792 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9496 11:03:58.593467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9497 11:03:58.596829 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9498 11:03:58.603001 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9499 11:03:58.606966 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9500 11:03:58.613299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9501 11:03:58.616669 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9502 11:03:58.619968 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9503 11:03:58.626264 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9504 11:03:58.629844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9505 11:03:58.636373 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9506 11:03:58.640059 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9507 11:03:58.643256 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9508 11:03:58.649793 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9509 11:03:58.653074 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9510 11:03:58.659627 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9511 11:03:58.662935 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9512 11:03:58.666155 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9513 11:03:58.672748 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9514 11:03:58.676430 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9515 11:03:58.682582 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9516 11:03:58.686025 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9517 11:03:58.693168 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9518 11:03:58.696493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9519 11:03:58.699400 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9520 11:03:58.705972 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9521 11:03:58.709532 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9522 11:03:58.716132 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9523 11:03:58.719540 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9524 11:03:58.722769 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9525 11:03:58.729517 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9526 11:03:58.732612 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9527 11:03:58.736394 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9528 11:03:58.742603 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9529 11:03:58.745884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9530 11:03:58.752710 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9531 11:03:58.755961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9532 11:03:58.762545 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9533 11:03:58.765902 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9534 11:03:58.768878 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9535 11:03:58.775912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9536 11:03:58.779205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9537 11:03:58.785688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9538 11:03:58.789006 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9539 11:03:58.792195 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9540 11:03:58.798809 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9541 11:03:58.802258 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9542 11:03:58.809002 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9543 11:03:58.812236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9544 11:03:58.815521 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9545 11:03:58.822280 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9546 11:03:58.825741 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9547 11:03:58.832074 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9548 11:03:58.835616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9549 11:03:58.841973 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9550 11:03:58.845303 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9551 11:03:58.848593 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9552 11:03:58.855763 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9553 11:03:58.858773 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9554 11:03:58.865309 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9555 11:03:58.868476 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9556 11:03:58.875210 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9557 11:03:58.878427 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9558 11:03:58.885011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9559 11:03:58.888411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9560 11:03:58.891800 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9561 11:03:58.898666 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9562 11:03:58.901949 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9563 11:03:58.908511 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9564 11:03:58.911991 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9565 11:03:58.918729 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9566 11:03:58.922376 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9567 11:03:58.925551 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9568 11:03:58.932282 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9569 11:03:58.935420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9570 11:03:58.942228 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9571 11:03:58.945204 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9572 11:03:58.952617 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9573 11:03:58.955295 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9574 11:03:58.958847 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9575 11:03:58.965549 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9576 11:03:58.968574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9577 11:03:58.975078 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9578 11:03:58.978536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9579 11:03:58.985139 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9580 11:03:58.988161 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9581 11:03:58.995894 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9582 11:03:58.998536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9583 11:03:59.001720 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9584 11:03:59.008535 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9585 11:03:59.011704 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9586 11:03:59.018448 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9587 11:03:59.021720 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9588 11:03:59.028593 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9589 11:03:59.031403 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9590 11:03:59.034816 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9591 11:03:59.041940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9592 11:03:59.044615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9593 11:03:59.051698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9594 11:03:59.054630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9595 11:03:59.061501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9596 11:03:59.064692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9597 11:03:59.071635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9598 11:03:59.074606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9599 11:03:59.081776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9600 11:03:59.084529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9601 11:03:59.088001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9602 11:03:59.095237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9603 11:03:59.097989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9604 11:03:59.104767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9605 11:03:59.107773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9606 11:03:59.114956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9607 11:03:59.118125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9608 11:03:59.124870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9609 11:03:59.127885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9610 11:03:59.134735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9611 11:03:59.138073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9612 11:03:59.144796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9613 11:03:59.148225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9614 11:03:59.154931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9615 11:03:59.158014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9616 11:03:59.164618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9617 11:03:59.168429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9618 11:03:59.175003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9619 11:03:59.178113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9620 11:03:59.184744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9621 11:03:59.188300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9622 11:03:59.194635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9623 11:03:59.197724 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9624 11:03:59.201280 INFO: [APUAPC] vio 0
9625 11:03:59.204885 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9626 11:03:59.211216 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9627 11:03:59.214828 INFO: [APUAPC] D0_APC_0: 0x400510
9628 11:03:59.215304 INFO: [APUAPC] D0_APC_1: 0x0
9629 11:03:59.218387 INFO: [APUAPC] D0_APC_2: 0x1540
9630 11:03:59.221304 INFO: [APUAPC] D0_APC_3: 0x0
9631 11:03:59.224626 INFO: [APUAPC] D1_APC_0: 0xffffffff
9632 11:03:59.227878 INFO: [APUAPC] D1_APC_1: 0xffffffff
9633 11:03:59.231350 INFO: [APUAPC] D1_APC_2: 0x3fffff
9634 11:03:59.234717 INFO: [APUAPC] D1_APC_3: 0x0
9635 11:03:59.237843 INFO: [APUAPC] D2_APC_0: 0xffffffff
9636 11:03:59.241212 INFO: [APUAPC] D2_APC_1: 0xffffffff
9637 11:03:59.244360 INFO: [APUAPC] D2_APC_2: 0x3fffff
9638 11:03:59.247800 INFO: [APUAPC] D2_APC_3: 0x0
9639 11:03:59.251155 INFO: [APUAPC] D3_APC_0: 0xffffffff
9640 11:03:59.254704 INFO: [APUAPC] D3_APC_1: 0xffffffff
9641 11:03:59.257727 INFO: [APUAPC] D3_APC_2: 0x3fffff
9642 11:03:59.260994 INFO: [APUAPC] D3_APC_3: 0x0
9643 11:03:59.264088 INFO: [APUAPC] D4_APC_0: 0xffffffff
9644 11:03:59.267898 INFO: [APUAPC] D4_APC_1: 0xffffffff
9645 11:03:59.271017 INFO: [APUAPC] D4_APC_2: 0x3fffff
9646 11:03:59.274033 INFO: [APUAPC] D4_APC_3: 0x0
9647 11:03:59.277557 INFO: [APUAPC] D5_APC_0: 0xffffffff
9648 11:03:59.281034 INFO: [APUAPC] D5_APC_1: 0xffffffff
9649 11:03:59.284158 INFO: [APUAPC] D5_APC_2: 0x3fffff
9650 11:03:59.287447 INFO: [APUAPC] D5_APC_3: 0x0
9651 11:03:59.290576 INFO: [APUAPC] D6_APC_0: 0xffffffff
9652 11:03:59.294444 INFO: [APUAPC] D6_APC_1: 0xffffffff
9653 11:03:59.297657 INFO: [APUAPC] D6_APC_2: 0x3fffff
9654 11:03:59.300969 INFO: [APUAPC] D6_APC_3: 0x0
9655 11:03:59.303942 INFO: [APUAPC] D7_APC_0: 0xffffffff
9656 11:03:59.307499 INFO: [APUAPC] D7_APC_1: 0xffffffff
9657 11:03:59.310672 INFO: [APUAPC] D7_APC_2: 0x3fffff
9658 11:03:59.314088 INFO: [APUAPC] D7_APC_3: 0x0
9659 11:03:59.317548 INFO: [APUAPC] D8_APC_0: 0xffffffff
9660 11:03:59.321045 INFO: [APUAPC] D8_APC_1: 0xffffffff
9661 11:03:59.324137 INFO: [APUAPC] D8_APC_2: 0x3fffff
9662 11:03:59.327219 INFO: [APUAPC] D8_APC_3: 0x0
9663 11:03:59.330539 INFO: [APUAPC] D9_APC_0: 0xffffffff
9664 11:03:59.333948 INFO: [APUAPC] D9_APC_1: 0xffffffff
9665 11:03:59.337277 INFO: [APUAPC] D9_APC_2: 0x3fffff
9666 11:03:59.337660 INFO: [APUAPC] D9_APC_3: 0x0
9667 11:03:59.340570 INFO: [APUAPC] D10_APC_0: 0xffffffff
9668 11:03:59.347505 INFO: [APUAPC] D10_APC_1: 0xffffffff
9669 11:03:59.351342 INFO: [APUAPC] D10_APC_2: 0x3fffff
9670 11:03:59.351803 INFO: [APUAPC] D10_APC_3: 0x0
9671 11:03:59.354070 INFO: [APUAPC] D11_APC_0: 0xffffffff
9672 11:03:59.360509 INFO: [APUAPC] D11_APC_1: 0xffffffff
9673 11:03:59.364113 INFO: [APUAPC] D11_APC_2: 0x3fffff
9674 11:03:59.364496 INFO: [APUAPC] D11_APC_3: 0x0
9675 11:03:59.370729 INFO: [APUAPC] D12_APC_0: 0xffffffff
9676 11:03:59.374223 INFO: [APUAPC] D12_APC_1: 0xffffffff
9677 11:03:59.377814 INFO: [APUAPC] D12_APC_2: 0x3fffff
9678 11:03:59.378196 INFO: [APUAPC] D12_APC_3: 0x0
9679 11:03:59.383862 INFO: [APUAPC] D13_APC_0: 0xffffffff
9680 11:03:59.387121 INFO: [APUAPC] D13_APC_1: 0xffffffff
9681 11:03:59.390767 INFO: [APUAPC] D13_APC_2: 0x3fffff
9682 11:03:59.391148 INFO: [APUAPC] D13_APC_3: 0x0
9683 11:03:59.397252 INFO: [APUAPC] D14_APC_0: 0xffffffff
9684 11:03:59.400389 INFO: [APUAPC] D14_APC_1: 0xffffffff
9685 11:03:59.403798 INFO: [APUAPC] D14_APC_2: 0x3fffff
9686 11:03:59.407403 INFO: [APUAPC] D14_APC_3: 0x0
9687 11:03:59.410436 INFO: [APUAPC] D15_APC_0: 0xffffffff
9688 11:03:59.413802 INFO: [APUAPC] D15_APC_1: 0xffffffff
9689 11:03:59.417204 INFO: [APUAPC] D15_APC_2: 0x3fffff
9690 11:03:59.420433 INFO: [APUAPC] D15_APC_3: 0x0
9691 11:03:59.420922 INFO: [APUAPC] APC_CON: 0x4
9692 11:03:59.423794 INFO: [NOCDAPC] D0_APC_0: 0x0
9693 11:03:59.427179 INFO: [NOCDAPC] D0_APC_1: 0x0
9694 11:03:59.430210 INFO: [NOCDAPC] D1_APC_0: 0x0
9695 11:03:59.433743 INFO: [NOCDAPC] D1_APC_1: 0xfff
9696 11:03:59.437150 INFO: [NOCDAPC] D2_APC_0: 0x0
9697 11:03:59.440458 INFO: [NOCDAPC] D2_APC_1: 0xfff
9698 11:03:59.443609 INFO: [NOCDAPC] D3_APC_0: 0x0
9699 11:03:59.447053 INFO: [NOCDAPC] D3_APC_1: 0xfff
9700 11:03:59.447496 INFO: [NOCDAPC] D4_APC_0: 0x0
9701 11:03:59.450274 INFO: [NOCDAPC] D4_APC_1: 0xfff
9702 11:03:59.453801 INFO: [NOCDAPC] D5_APC_0: 0x0
9703 11:03:59.457174 INFO: [NOCDAPC] D5_APC_1: 0xfff
9704 11:03:59.460308 INFO: [NOCDAPC] D6_APC_0: 0x0
9705 11:03:59.463905 INFO: [NOCDAPC] D6_APC_1: 0xfff
9706 11:03:59.467324 INFO: [NOCDAPC] D7_APC_0: 0x0
9707 11:03:59.470168 INFO: [NOCDAPC] D7_APC_1: 0xfff
9708 11:03:59.473541 INFO: [NOCDAPC] D8_APC_0: 0x0
9709 11:03:59.477280 INFO: [NOCDAPC] D8_APC_1: 0xfff
9710 11:03:59.480643 INFO: [NOCDAPC] D9_APC_0: 0x0
9711 11:03:59.481070 INFO: [NOCDAPC] D9_APC_1: 0xfff
9712 11:03:59.483882 INFO: [NOCDAPC] D10_APC_0: 0x0
9713 11:03:59.487049 INFO: [NOCDAPC] D10_APC_1: 0xfff
9714 11:03:59.490519 INFO: [NOCDAPC] D11_APC_0: 0x0
9715 11:03:59.494203 INFO: [NOCDAPC] D11_APC_1: 0xfff
9716 11:03:59.497074 INFO: [NOCDAPC] D12_APC_0: 0x0
9717 11:03:59.500228 INFO: [NOCDAPC] D12_APC_1: 0xfff
9718 11:03:59.503771 INFO: [NOCDAPC] D13_APC_0: 0x0
9719 11:03:59.506921 INFO: [NOCDAPC] D13_APC_1: 0xfff
9720 11:03:59.510115 INFO: [NOCDAPC] D14_APC_0: 0x0
9721 11:03:59.514079 INFO: [NOCDAPC] D14_APC_1: 0xfff
9722 11:03:59.517196 INFO: [NOCDAPC] D15_APC_0: 0x0
9723 11:03:59.520396 INFO: [NOCDAPC] D15_APC_1: 0xfff
9724 11:03:59.523500 INFO: [NOCDAPC] APC_CON: 0x4
9725 11:03:59.526718 INFO: [APUAPC] set_apusys_apc done
9726 11:03:59.527141 INFO: [DEVAPC] devapc_init done
9727 11:03:59.533614 INFO: GICv3 without legacy support detected.
9728 11:03:59.536828 INFO: ARM GICv3 driver initialized in EL3
9729 11:03:59.540151 INFO: Maximum SPI INTID supported: 639
9730 11:03:59.543364 INFO: BL31: Initializing runtime services
9731 11:03:59.550269 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9732 11:03:59.553710 INFO: SPM: enable CPC mode
9733 11:03:59.556822 INFO: mcdi ready for mcusys-off-idle and system suspend
9734 11:03:59.563786 INFO: BL31: Preparing for EL3 exit to normal world
9735 11:03:59.567163 INFO: Entry point address = 0x80000000
9736 11:03:59.567630 INFO: SPSR = 0x8
9737 11:03:59.573800
9738 11:03:59.574258
9739 11:03:59.574565
9740 11:03:59.577114 Starting depthcharge on Spherion...
9741 11:03:59.577528
9742 11:03:59.577958 Wipe memory regions:
9743 11:03:59.578258
9744 11:03:59.580622 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9745 11:03:59.581081 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9746 11:03:59.581526 Setting prompt string to ['asurada:']
9747 11:03:59.581856 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9748 11:03:59.582459 [0x00000040000000, 0x00000054600000)
9749 11:03:59.703092
9750 11:03:59.703641 [0x00000054660000, 0x00000080000000)
9751 11:03:59.963364
9752 11:03:59.963857 [0x000000821a7280, 0x000000ffe64000)
9753 11:04:00.708559
9754 11:04:00.709255 [0x00000100000000, 0x00000140000000)
9755 11:04:01.089570
9756 11:04:01.092891 Initializing XHCI USB controller at 0x11200000.
9757 11:04:02.131060
9758 11:04:02.134325 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9759 11:04:02.134768
9760 11:04:02.135100
9761 11:04:02.135790 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9762 11:04:02.136185 Sending line: 'tftpboot 192.168.201.1 14786812/tftp-deploy-mulcmt2h/kernel/image.itb 14786812/tftp-deploy-mulcmt2h/kernel/cmdline '
9764 11:04:02.237680 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9765 11:04:02.238103 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:19)
9766 11:04:02.242692 asurada: tftpboot 192.168.201.1 14786812/tftp-deploy-mulcmt2h/kernel/image.itp-deploy-mulcmt2h/kernel/cmdline
9767 11:04:02.243122
9768 11:04:02.243449 Waiting for link
9769 11:04:02.400816
9770 11:04:02.401399 R8152: Initializing
9771 11:04:02.401745
9772 11:04:02.404075 Version 9 (ocp_data = 6010)
9773 11:04:02.404585
9774 11:04:02.407186 R8152: Done initializing
9775 11:04:02.407686
9776 11:04:02.408016 Adding net device
9777 11:04:04.418163
9778 11:04:04.418646 done.
9779 11:04:04.418974
9780 11:04:04.419275 MAC: 00:e0:4c:68:03:bd
9781 11:04:04.419647
9782 11:04:04.421712 Sending DHCP discover... done.
9783 11:04:04.422131
9784 11:04:04.424979 Waiting for reply... done.
9785 11:04:04.425454
9786 11:04:04.427802 Sending DHCP request... done.
9787 11:04:04.427963
9788 11:04:04.431290 Waiting for reply... done.
9789 11:04:04.431454
9790 11:04:04.431580 My ip is 192.168.201.16
9791 11:04:04.431697
9792 11:04:04.434401 The DHCP server ip is 192.168.201.1
9793 11:04:04.434565
9794 11:04:04.438052 TFTP server IP predefined by user: 192.168.201.1
9795 11:04:04.441180
9796 11:04:04.448436 Bootfile predefined by user: 14786812/tftp-deploy-mulcmt2h/kernel/image.itb
9797 11:04:04.448666
9798 11:04:04.448797 Sending tftp read request... done.
9799 11:04:04.448914
9800 11:04:04.455328 Waiting for the transfer...
9801 11:04:04.455580
9802 11:04:04.727746 00000000 ################################################################
9803 11:04:04.727861
9804 11:04:05.015171 00080000 ################################################################
9805 11:04:05.015282
9806 11:04:05.286175 00100000 ################################################################
9807 11:04:05.286316
9808 11:04:05.559973 00180000 ################################################################
9809 11:04:05.560090
9810 11:04:05.831180 00200000 ################################################################
9811 11:04:05.831294
9812 11:04:06.099411 00280000 ################################################################
9813 11:04:06.099525
9814 11:04:06.370798 00300000 ################################################################
9815 11:04:06.370936
9816 11:04:06.630268 00380000 ################################################################
9817 11:04:06.630394
9818 11:04:06.905956 00400000 ################################################################
9819 11:04:06.906076
9820 11:04:07.176712 00480000 ################################################################
9821 11:04:07.176826
9822 11:04:07.468331 00500000 ################################################################
9823 11:04:07.468469
9824 11:04:07.746443 00580000 ################################################################
9825 11:04:07.746557
9826 11:04:08.027593 00600000 ################################################################
9827 11:04:08.027709
9828 11:04:08.285867 00680000 ################################################################
9829 11:04:08.285979
9830 11:04:08.539884 00700000 ################################################################
9831 11:04:08.540015
9832 11:04:08.809865 00780000 ################################################################
9833 11:04:08.809978
9834 11:04:09.098426 00800000 ################################################################
9835 11:04:09.098540
9836 11:04:09.385542 00880000 ################################################################
9837 11:04:09.385652
9838 11:04:09.683094 00900000 ################################################################
9839 11:04:09.683217
9840 11:04:09.978841 00980000 ################################################################
9841 11:04:09.978959
9842 11:04:10.267574 00a00000 ################################################################
9843 11:04:10.267697
9844 11:04:10.556172 00a80000 ################################################################
9845 11:04:10.556297
9846 11:04:10.847535 00b00000 ################################################################
9847 11:04:10.847651
9848 11:04:11.130822 00b80000 ################################################################
9849 11:04:11.130939
9850 11:04:11.392743 00c00000 ################################################################
9851 11:04:11.392869
9852 11:04:11.641151 00c80000 ################################################################
9853 11:04:11.641307
9854 11:04:11.893946 00d00000 ################################################################
9855 11:04:11.894107
9856 11:04:12.149455 00d80000 ################################################################
9857 11:04:12.149580
9858 11:04:12.403405 00e00000 ################################################################
9859 11:04:12.403527
9860 11:04:12.654884 00e80000 ################################################################
9861 11:04:12.655027
9862 11:04:12.905263 00f00000 ################################################################
9863 11:04:12.905399
9864 11:04:13.161042 00f80000 ################################################################
9865 11:04:13.161160
9866 11:04:13.425875 01000000 ################################################################
9867 11:04:13.426010
9868 11:04:13.691245 01080000 ################################################################
9869 11:04:13.691369
9870 11:04:13.945950 01100000 ################################################################
9871 11:04:13.946071
9872 11:04:14.193095 01180000 ################################################################
9873 11:04:14.193258
9874 11:04:14.441773 01200000 ################################################################
9875 11:04:14.441889
9876 11:04:14.707770 01280000 ################################################################
9877 11:04:14.707889
9878 11:04:14.968860 01300000 ################################################################
9879 11:04:14.968981
9880 11:04:15.259150 01380000 ################################################################
9881 11:04:15.259269
9882 11:04:15.512792 01400000 ################################################################
9883 11:04:15.512906
9884 11:04:15.759321 01480000 ################################################################
9885 11:04:15.759432
9886 11:04:16.015571 01500000 ################################################################
9887 11:04:16.015688
9888 11:04:16.261847 01580000 ################################################################
9889 11:04:16.261958
9890 11:04:16.507758 01600000 ################################################################
9891 11:04:16.507878
9892 11:04:16.771596 01680000 ################################################################
9893 11:04:16.771740
9894 11:04:17.038762 01700000 ################################################################
9895 11:04:17.038877
9896 11:04:17.285812 01780000 ################################################################
9897 11:04:17.285934
9898 11:04:17.539522 01800000 ################################################################
9899 11:04:17.539662
9900 11:04:17.788711 01880000 ################################################################
9901 11:04:17.788837
9902 11:04:18.037878 01900000 ################################################################
9903 11:04:18.038000
9904 11:04:18.285822 01980000 ################################################################
9905 11:04:18.285943
9906 11:04:18.566184 01a00000 ################################################################
9907 11:04:18.566315
9908 11:04:18.822234 01a80000 ################################################################
9909 11:04:18.822357
9910 11:04:19.083975 01b00000 ################################################################
9911 11:04:19.084095
9912 11:04:19.371380 01b80000 ################################################################
9913 11:04:19.371505
9914 11:04:19.623793 01c00000 ################################################################
9915 11:04:19.623923
9916 11:04:19.895693 01c80000 ################################################################
9917 11:04:19.895856
9918 11:04:20.192828 01d00000 ################################################################
9919 11:04:20.192956
9920 11:04:20.457641 01d80000 ################################################################
9921 11:04:20.457800
9922 11:04:20.708392 01e00000 ################################################################
9923 11:04:20.708517
9924 11:04:20.967268 01e80000 ################################################################
9925 11:04:20.967389
9926 11:04:21.222029 01f00000 ################################################################
9927 11:04:21.222169
9928 11:04:21.471901 01f80000 ################################################################
9929 11:04:21.472020
9930 11:04:21.727731 02000000 ################################################################
9931 11:04:21.727859
9932 11:04:21.983224 02080000 ################################################################
9933 11:04:21.983350
9934 11:04:22.233221 02100000 ################################################################
9935 11:04:22.233372
9936 11:04:22.497102 02180000 ################################################################
9937 11:04:22.497220
9938 11:04:22.748168 02200000 ################################################################
9939 11:04:22.748285
9940 11:04:22.998512 02280000 ################################################################
9941 11:04:22.998637
9942 11:04:23.271862 02300000 ################################################################
9943 11:04:23.271988
9944 11:04:23.518191 02380000 ################################################################
9945 11:04:23.518306
9946 11:04:23.768872 02400000 ################################################################
9947 11:04:23.768998
9948 11:04:24.015597 02480000 ################################################################
9949 11:04:24.015750
9950 11:04:24.269550 02500000 ################################################################
9951 11:04:24.269688
9952 11:04:24.530246 02580000 ################################################################
9953 11:04:24.530361
9954 11:04:24.798844 02600000 ################################################################
9955 11:04:24.798966
9956 11:04:25.066717 02680000 ################################################################
9957 11:04:25.066842
9958 11:04:25.346912 02700000 ################################################################
9959 11:04:25.347035
9960 11:04:25.614056 02780000 ################################################################
9961 11:04:25.614198
9962 11:04:25.891390 02800000 ################################################################
9963 11:04:25.891530
9964 11:04:26.157890 02880000 ################################################################
9965 11:04:26.158015
9966 11:04:26.438641 02900000 ################################################################
9967 11:04:26.438758
9968 11:04:26.698037 02980000 ################################################################
9969 11:04:26.698152
9970 11:04:26.968392 02a00000 ################################################################
9971 11:04:26.968527
9972 11:04:27.222499 02a80000 ################################################################
9973 11:04:27.222611
9974 11:04:27.474403 02b00000 ################################################################
9975 11:04:27.474517
9976 11:04:27.753652 02b80000 ################################################################
9977 11:04:27.753777
9978 11:04:28.037578 02c00000 ################################################################
9979 11:04:28.037692
9980 11:04:28.327793 02c80000 ################################################################
9981 11:04:28.327919
9982 11:04:28.598957 02d00000 ################################################################
9983 11:04:28.599075
9984 11:04:28.876247 02d80000 ################################################################
9985 11:04:28.876369
9986 11:04:29.167484 02e00000 ################################################################
9987 11:04:29.167632
9988 11:04:29.459986 02e80000 ################################################################
9989 11:04:29.460122
9990 11:04:29.755380 02f00000 ################################################################
9991 11:04:29.755490
9992 11:04:30.048911 02f80000 ################################################################
9993 11:04:30.049045
9994 11:04:30.316060 03000000 ################################################################
9995 11:04:30.316177
9996 11:04:30.580609 03080000 ################################################################
9997 11:04:30.580723
9998 11:04:30.836261 03100000 ################################################################
9999 11:04:30.836372
10000 11:04:31.101552 03180000 ################################################################
10001 11:04:31.101660
10002 11:04:31.364779 03200000 ################################################################
10003 11:04:31.364911
10004 11:04:31.617332 03280000 ################################################################
10005 11:04:31.617443
10006 11:04:31.868901 03300000 ################################################################
10007 11:04:31.869010
10008 11:04:32.133344 03380000 ################################################################
10009 11:04:32.133457
10010 11:04:32.396675 03400000 ################################################################
10011 11:04:32.396792
10012 11:04:32.649022 03480000 ################################################################
10013 11:04:32.649135
10014 11:04:32.915511 03500000 ################################################################
10015 11:04:32.915623
10016 11:04:33.194817 03580000 ################################################################
10017 11:04:33.194942
10018 11:04:33.482900 03600000 ################################################################
10019 11:04:33.483032
10020 11:04:33.768803 03680000 ################################################################
10021 11:04:33.768926
10022 11:04:34.051922 03700000 ################################################################
10023 11:04:34.052034
10024 11:04:34.336612 03780000 ################################################################
10025 11:04:34.336726
10026 11:04:34.589621 03800000 ################################################################
10027 11:04:34.589735
10028 11:04:34.853835 03880000 ################################################################
10029 11:04:34.853960
10030 11:04:35.122799 03900000 ################################################################
10031 11:04:35.122923
10032 11:04:35.396619 03980000 ################################################################
10033 11:04:35.396734
10034 11:04:35.663467 03a00000 ################################################################
10035 11:04:35.663603
10036 11:04:35.946977 03a80000 ################################################################
10037 11:04:35.947119
10038 11:04:36.229539 03b00000 ################################################################
10039 11:04:36.229672
10040 11:04:36.525776 03b80000 ################################################################
10041 11:04:36.525898
10042 11:04:36.824086 03c00000 ################################################################
10043 11:04:36.824218
10044 11:04:37.121977 03c80000 ################################################################
10045 11:04:37.122095
10046 11:04:37.406871 03d00000 ################################################################
10047 11:04:37.407013
10048 11:04:37.699640 03d80000 ################################################################
10049 11:04:37.699764
10050 11:04:37.997468 03e00000 ################################################################
10051 11:04:37.997590
10052 11:04:38.283735 03e80000 ################################################################
10053 11:04:38.283850
10054 11:04:38.565020 03f00000 ################################################################
10055 11:04:38.565141
10056 11:04:38.839367 03f80000 ################################################################
10057 11:04:38.839478
10058 11:04:39.110838 04000000 ################################################################
10059 11:04:39.110949
10060 11:04:39.395538 04080000 ################################################################
10061 11:04:39.395672
10062 11:04:39.664196 04100000 ################################################################
10063 11:04:39.664317
10064 11:04:39.935840 04180000 ################################################################
10065 11:04:39.935975
10066 11:04:40.203889 04200000 ################################################################
10067 11:04:40.204033
10068 11:04:40.458854 04280000 ################################################################
10069 11:04:40.458972
10070 11:04:40.721303 04300000 ################################################################
10071 11:04:40.721438
10072 11:04:40.992600 04380000 ################################################################
10073 11:04:40.992709
10074 11:04:41.250957 04400000 ################################################################
10075 11:04:41.251067
10076 11:04:41.506360 04480000 ################################################################
10077 11:04:41.506486
10078 11:04:41.755872 04500000 ################################################################
10079 11:04:41.756004
10080 11:04:42.007387 04580000 ################################################################
10081 11:04:42.007513
10082 11:04:42.263705 04600000 ################################################################
10083 11:04:42.263817
10084 11:04:42.366266 04680000 ########################### done.
10085 11:04:42.366370
10086 11:04:42.369588 The bootfile was 74140042 bytes long.
10087 11:04:42.369669
10088 11:04:42.372908 Sending tftp read request... done.
10089 11:04:42.372991
10090 11:04:42.376622 Waiting for the transfer...
10091 11:04:42.376709
10092 11:04:42.376777 00000000 # done.
10093 11:04:42.376841
10094 11:04:42.386496 Command line loaded dynamically from TFTP file: 14786812/tftp-deploy-mulcmt2h/kernel/cmdline
10095 11:04:42.386660
10096 11:04:42.399664 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10097 11:04:42.399875
10098 11:04:42.399998 Loading FIT.
10099 11:04:42.400108
10100 11:04:42.402843 Image ramdisk-1 has 60974499 bytes.
10101 11:04:42.402986
10102 11:04:42.406397 Image fdt-1 has 47258 bytes.
10103 11:04:42.406556
10104 11:04:42.409757 Image kernel-1 has 13116259 bytes.
10105 11:04:42.409941
10106 11:04:42.416537 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10107 11:04:42.416806
10108 11:04:42.436342 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10109 11:04:42.436904
10110 11:04:42.439436 Choosing best match conf-1 for compat google,spherion-rev3.
10111 11:04:42.444885
10112 11:04:42.449143 Connected to device vid:did:rid of 1ae0:0028:00
10113 11:04:42.456417
10114 11:04:42.459558 tpm_get_response: command 0x17b, return code 0x0
10115 11:04:42.460013
10116 11:04:42.463368 ec_init: CrosEC protocol v3 supported (256, 248)
10117 11:04:42.467711
10118 11:04:42.470744 tpm_cleanup: add release locality here.
10119 11:04:42.471173
10120 11:04:42.471498 Shutting down all USB controllers.
10121 11:04:42.474192
10122 11:04:42.474645 Removing current net device
10123 11:04:42.474972
10124 11:04:42.481116 Exiting depthcharge with code 4 at timestamp: 71140802
10125 11:04:42.481743
10126 11:04:42.484194 LZMA decompressing kernel-1 to 0x821a6718
10127 11:04:42.484640
10128 11:04:42.487379 LZMA decompressing kernel-1 to 0x40000000
10129 11:04:44.102518
10130 11:04:44.103037 jumping to kernel
10131 11:04:44.105462 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10132 11:04:44.106021 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10133 11:04:44.106392 Setting prompt string to ['Linux version [0-9]']
10134 11:04:44.106736 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 11:04:44.107077 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10136 11:04:44.152170
10137 11:04:44.155515 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10138 11:04:44.159318 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10139 11:04:44.159888 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10140 11:04:44.160270 Setting prompt string to []
10141 11:04:44.160674 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10142 11:04:44.161037 Using line separator: #'\n'#
10143 11:04:44.161396 No login prompt set.
10144 11:04:44.161728 Parsing kernel messages
10145 11:04:44.162017 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10146 11:04:44.162540 [login-action] Waiting for messages, (timeout 00:03:37)
10147 11:04:44.162854 Waiting using forced prompt support (timeout 00:01:48)
10148 11:04:44.178780 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10149 11:04:44.182034 [ 0.000000] random: crng init done
10150 11:04:44.185291 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10151 11:04:44.188786 [ 0.000000] efi: UEFI not found.
10152 11:04:44.198266 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10153 11:04:44.205217 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10154 11:04:44.215311 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10155 11:04:44.224936 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10156 11:04:44.231952 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10157 11:04:44.235000 [ 0.000000] printk: bootconsole [mtk8250] enabled
10158 11:04:44.243250 [ 0.000000] NUMA: No NUMA configuration found
10159 11:04:44.249943 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10160 11:04:44.256683 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10161 11:04:44.257066 [ 0.000000] Zone ranges:
10162 11:04:44.263475 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10163 11:04:44.266772 [ 0.000000] DMA32 empty
10164 11:04:44.273090 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10165 11:04:44.276487 [ 0.000000] Movable zone start for each node
10166 11:04:44.279962 [ 0.000000] Early memory node ranges
10167 11:04:44.286647 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10168 11:04:44.292894 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10169 11:04:44.299322 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10170 11:04:44.306078 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10171 11:04:44.313190 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10172 11:04:44.319056 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10173 11:04:44.349436 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10174 11:04:44.356157 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10175 11:04:44.363066 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10176 11:04:44.366305 [ 0.000000] psci: probing for conduit method from DT.
10177 11:04:44.372903 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10178 11:04:44.376806 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10179 11:04:44.383021 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10180 11:04:44.386137 [ 0.000000] psci: SMC Calling Convention v1.2
10181 11:04:44.392835 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10182 11:04:44.396183 [ 0.000000] Detected VIPT I-cache on CPU0
10183 11:04:44.403156 [ 0.000000] CPU features: detected: GIC system register CPU interface
10184 11:04:44.409451 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10185 11:04:44.416097 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10186 11:04:44.423018 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10187 11:04:44.429416 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10188 11:04:44.435902 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10189 11:04:44.442583 [ 0.000000] alternatives: applying boot alternatives
10190 11:04:44.445896 [ 0.000000] Fallback order for Node 0: 0
10191 11:04:44.455726 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10192 11:04:44.455804 [ 0.000000] Policy zone: Normal
10193 11:04:44.472259 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10194 11:04:44.482023 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10195 11:04:44.492442 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10196 11:04:44.502518 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10197 11:04:44.509016 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10198 11:04:44.512172 <6>[ 0.000000] software IO TLB: area num 8.
10199 11:04:44.569095 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10200 11:04:44.649328 <6>[ 0.000000] Memory: 3790096K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 368368K reserved, 32768K cma-reserved)
10201 11:04:44.655877 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10202 11:04:44.662511 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10203 11:04:44.665765 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10204 11:04:44.672234 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10205 11:04:44.679066 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10206 11:04:44.682425 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10207 11:04:44.692212 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10208 11:04:44.698834 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10209 11:04:44.705603 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10210 11:04:44.711938 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10211 11:04:44.715273 <6>[ 0.000000] GICv3: 608 SPIs implemented
10212 11:04:44.718407 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10213 11:04:44.725111 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10214 11:04:44.728415 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10215 11:04:44.735308 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10216 11:04:44.748756 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10217 11:04:44.761509 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10218 11:04:44.767751 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10219 11:04:44.775957 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10220 11:04:44.789126 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10221 11:04:44.795925 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10222 11:04:44.802552 <6>[ 0.009177] Console: colour dummy device 80x25
10223 11:04:44.812378 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10224 11:04:44.815702 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10225 11:04:44.822461 <6>[ 0.029252] LSM: Security Framework initializing
10226 11:04:44.829070 <6>[ 0.034166] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10227 11:04:44.838898 <6>[ 0.041820] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10228 11:04:44.845615 <6>[ 0.051061] cblist_init_generic: Setting adjustable number of callback queues.
10229 11:04:44.852532 <6>[ 0.058503] cblist_init_generic: Setting shift to 3 and lim to 1.
10230 11:04:44.859046 <6>[ 0.064842] cblist_init_generic: Setting adjustable number of callback queues.
10231 11:04:44.865200 <6>[ 0.072270] cblist_init_generic: Setting shift to 3 and lim to 1.
10232 11:04:44.872114 <6>[ 0.078672] rcu: Hierarchical SRCU implementation.
10233 11:04:44.878798 <6>[ 0.083716] rcu: Max phase no-delay instances is 1000.
10234 11:04:44.885207 <6>[ 0.090764] EFI services will not be available.
10235 11:04:44.888877 <6>[ 0.095722] smp: Bringing up secondary CPUs ...
10236 11:04:44.896120 <6>[ 0.100773] Detected VIPT I-cache on CPU1
10237 11:04:44.902775 <6>[ 0.100844] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10238 11:04:44.909744 <6>[ 0.100876] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10239 11:04:44.912516 <6>[ 0.101215] Detected VIPT I-cache on CPU2
10240 11:04:44.922919 <6>[ 0.101269] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10241 11:04:44.928983 <6>[ 0.101287] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10242 11:04:44.932447 <6>[ 0.101548] Detected VIPT I-cache on CPU3
10243 11:04:44.938842 <6>[ 0.101596] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10244 11:04:44.945512 <6>[ 0.101610] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10245 11:04:44.952241 <6>[ 0.101917] CPU features: detected: Spectre-v4
10246 11:04:44.955573 <6>[ 0.101923] CPU features: detected: Spectre-BHB
10247 11:04:44.958798 <6>[ 0.101929] Detected PIPT I-cache on CPU4
10248 11:04:44.965442 <6>[ 0.101990] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10249 11:04:44.972481 <6>[ 0.102007] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10250 11:04:44.978964 <6>[ 0.102300] Detected PIPT I-cache on CPU5
10251 11:04:44.985342 <6>[ 0.102364] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10252 11:04:44.991995 <6>[ 0.102380] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10253 11:04:44.995045 <6>[ 0.102663] Detected PIPT I-cache on CPU6
10254 11:04:45.001821 <6>[ 0.102726] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10255 11:04:45.008590 <6>[ 0.102742] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10256 11:04:45.015468 <6>[ 0.103047] Detected PIPT I-cache on CPU7
10257 11:04:45.021691 <6>[ 0.103113] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10258 11:04:45.028522 <6>[ 0.103129] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10259 11:04:45.031683 <6>[ 0.103177] smp: Brought up 1 node, 8 CPUs
10260 11:04:45.038444 <6>[ 0.244489] SMP: Total of 8 processors activated.
10261 11:04:45.041431 <6>[ 0.249411] CPU features: detected: 32-bit EL0 Support
10262 11:04:45.051095 <6>[ 0.254773] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10263 11:04:45.057849 <6>[ 0.263574] CPU features: detected: Common not Private translations
10264 11:04:45.064524 <6>[ 0.270050] CPU features: detected: CRC32 instructions
10265 11:04:45.071161 <6>[ 0.275401] CPU features: detected: RCpc load-acquire (LDAPR)
10266 11:04:45.074504 <6>[ 0.281398] CPU features: detected: LSE atomic instructions
10267 11:04:45.081000 <6>[ 0.287179] CPU features: detected: Privileged Access Never
10268 11:04:45.087520 <6>[ 0.292995] CPU features: detected: RAS Extension Support
10269 11:04:45.094136 <6>[ 0.298603] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10270 11:04:45.097538 <6>[ 0.305824] CPU: All CPU(s) started at EL2
10271 11:04:45.104025 <6>[ 0.310140] alternatives: applying system-wide alternatives
10272 11:04:45.113144 <6>[ 0.320157] devtmpfs: initialized
10273 11:04:45.124595 <6>[ 0.328251] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10274 11:04:45.134630 <6>[ 0.338208] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10275 11:04:45.141113 <6>[ 0.346450] pinctrl core: initialized pinctrl subsystem
10276 11:04:45.144496 <6>[ 0.353122] DMI not present or invalid.
10277 11:04:45.151047 <6>[ 0.357524] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10278 11:04:45.161112 <6>[ 0.364392] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10279 11:04:45.167618 <6>[ 0.371842] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10280 11:04:45.177552 <6>[ 0.379935] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10281 11:04:45.180728 <6>[ 0.388090] audit: initializing netlink subsys (disabled)
10282 11:04:45.191090 <5>[ 0.393790] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10283 11:04:45.197343 <6>[ 0.394498] thermal_sys: Registered thermal governor 'step_wise'
10284 11:04:45.203865 <6>[ 0.401754] thermal_sys: Registered thermal governor 'power_allocator'
10285 11:04:45.207322 <6>[ 0.408005] cpuidle: using governor menu
10286 11:04:45.213675 <6>[ 0.418962] NET: Registered PF_QIPCRTR protocol family
10287 11:04:45.220480 <6>[ 0.424483] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10288 11:04:45.223716 <6>[ 0.431585] ASID allocator initialised with 32768 entries
10289 11:04:45.231143 <6>[ 0.438140] Serial: AMBA PL011 UART driver
10290 11:04:45.240445 <4>[ 0.447412] Trying to register duplicate clock ID: 134
10291 11:04:45.298313 <6>[ 0.508581] KASLR enabled
10292 11:04:45.312485 <6>[ 0.516236] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10293 11:04:45.319186 <6>[ 0.523254] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10294 11:04:45.325700 <6>[ 0.529742] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10295 11:04:45.332294 <6>[ 0.536748] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10296 11:04:45.338855 <6>[ 0.543236] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10297 11:04:45.345395 <6>[ 0.550240] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10298 11:04:45.352017 <6>[ 0.556728] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10299 11:04:45.358537 <6>[ 0.563734] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10300 11:04:45.361956 <6>[ 0.571238] ACPI: Interpreter disabled.
10301 11:04:45.371018 <6>[ 0.577619] iommu: Default domain type: Translated
10302 11:04:45.377855 <6>[ 0.582731] iommu: DMA domain TLB invalidation policy: strict mode
10303 11:04:45.381030 <5>[ 0.589376] SCSI subsystem initialized
10304 11:04:45.387722 <6>[ 0.593535] usbcore: registered new interface driver usbfs
10305 11:04:45.394119 <6>[ 0.599267] usbcore: registered new interface driver hub
10306 11:04:45.396979 <6>[ 0.604816] usbcore: registered new device driver usb
10307 11:04:45.404121 <6>[ 0.610915] pps_core: LinuxPPS API ver. 1 registered
10308 11:04:45.414182 <6>[ 0.616104] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10309 11:04:45.417417 <6>[ 0.625448] PTP clock support registered
10310 11:04:45.420737 <6>[ 0.629692] EDAC MC: Ver: 3.0.0
10311 11:04:45.427965 <6>[ 0.634854] FPGA manager framework
10312 11:04:45.434366 <6>[ 0.638538] Advanced Linux Sound Architecture Driver Initialized.
10313 11:04:45.437720 <6>[ 0.645325] vgaarb: loaded
10314 11:04:45.444402 <6>[ 0.648472] clocksource: Switched to clocksource arch_sys_counter
10315 11:04:45.448103 <5>[ 0.654910] VFS: Disk quotas dquot_6.6.0
10316 11:04:45.454740 <6>[ 0.659094] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10317 11:04:45.457892 <6>[ 0.666279] pnp: PnP ACPI: disabled
10318 11:04:45.465901 <6>[ 0.672950] NET: Registered PF_INET protocol family
10319 11:04:45.472341 <6>[ 0.678330] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10320 11:04:45.484773 <6>[ 0.688335] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10321 11:04:45.494508 <6>[ 0.697119] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10322 11:04:45.501414 <6>[ 0.705087] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10323 11:04:45.507703 <6>[ 0.713487] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10324 11:04:45.518225 <6>[ 0.722143] TCP: Hash tables configured (established 32768 bind 32768)
10325 11:04:45.524983 <6>[ 0.728999] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10326 11:04:45.531571 <6>[ 0.736016] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10327 11:04:45.538040 <6>[ 0.743537] NET: Registered PF_UNIX/PF_LOCAL protocol family
10328 11:04:45.544872 <6>[ 0.749661] RPC: Registered named UNIX socket transport module.
10329 11:04:45.547988 <6>[ 0.755811] RPC: Registered udp transport module.
10330 11:04:45.554780 <6>[ 0.760743] RPC: Registered tcp transport module.
10331 11:04:45.561403 <6>[ 0.765672] RPC: Registered tcp NFSv4.1 backchannel transport module.
10332 11:04:45.564772 <6>[ 0.772338] PCI: CLS 0 bytes, default 64
10333 11:04:45.567911 <6>[ 0.776747] Unpacking initramfs...
10334 11:04:45.577788 <6>[ 0.780455] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10335 11:04:45.584356 <6>[ 0.789106] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10336 11:04:45.591027 <6>[ 0.797950] kvm [1]: IPA Size Limit: 40 bits
10337 11:04:45.594187 <6>[ 0.802477] kvm [1]: GICv3: no GICV resource entry
10338 11:04:45.600901 <6>[ 0.807498] kvm [1]: disabling GICv2 emulation
10339 11:04:45.607324 <6>[ 0.812188] kvm [1]: GIC system register CPU interface enabled
10340 11:04:45.610620 <6>[ 0.818353] kvm [1]: vgic interrupt IRQ18
10341 11:04:45.617091 <6>[ 0.822719] kvm [1]: VHE mode initialized successfully
10342 11:04:45.620520 <5>[ 0.828941] Initialise system trusted keyrings
10343 11:04:45.627150 <6>[ 0.833783] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10344 11:04:45.636712 <6>[ 0.843787] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10345 11:04:45.643503 <5>[ 0.850180] NFS: Registering the id_resolver key type
10346 11:04:45.646664 <5>[ 0.855480] Key type id_resolver registered
10347 11:04:45.653118 <5>[ 0.859894] Key type id_legacy registered
10348 11:04:45.659957 <6>[ 0.864177] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10349 11:04:45.666690 <6>[ 0.871097] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10350 11:04:45.673144 <6>[ 0.878790] 9p: Installing v9fs 9p2000 file system support
10351 11:04:45.710235 <5>[ 0.916974] Key type asymmetric registered
10352 11:04:45.713317 <5>[ 0.921306] Asymmetric key parser 'x509' registered
10353 11:04:45.723040 <6>[ 0.926442] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10354 11:04:45.726377 <6>[ 0.934053] io scheduler mq-deadline registered
10355 11:04:45.729708 <6>[ 0.938812] io scheduler kyber registered
10356 11:04:45.748610 <6>[ 0.955883] EINJ: ACPI disabled.
10357 11:04:45.781901 <4>[ 0.982175] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10358 11:04:45.792231 <4>[ 0.992822] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10359 11:04:45.806802 <6>[ 1.013613] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10360 11:04:45.815077 <6>[ 1.021631] printk: console [ttyS0] disabled
10361 11:04:45.842925 <6>[ 1.046265] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10362 11:04:45.849345 <6>[ 1.055734] printk: console [ttyS0] enabled
10363 11:04:45.852864 <6>[ 1.055734] printk: console [ttyS0] enabled
10364 11:04:45.859718 <6>[ 1.064629] printk: bootconsole [mtk8250] disabled
10365 11:04:45.863169 <6>[ 1.064629] printk: bootconsole [mtk8250] disabled
10366 11:04:45.869460 <6>[ 1.075658] SuperH (H)SCI(F) driver initialized
10367 11:04:45.872617 <6>[ 1.080957] msm_serial: driver initialized
10368 11:04:45.886411 <6>[ 1.089906] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10369 11:04:45.896473 <6>[ 1.098451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10370 11:04:45.903537 <6>[ 1.106994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10371 11:04:45.913321 <6>[ 1.115622] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10372 11:04:45.920461 <6>[ 1.124328] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10373 11:04:45.929757 <6>[ 1.133043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10374 11:04:45.939698 <6>[ 1.141583] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10375 11:04:45.946418 <6>[ 1.150396] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10376 11:04:45.956264 <6>[ 1.158938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10377 11:04:45.968323 <6>[ 1.174800] loop: module loaded
10378 11:04:45.974791 <6>[ 1.180605] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10379 11:04:45.996802 <4>[ 1.203531] mtk-pmic-keys: Failed to locate of_node [id: -1]
10380 11:04:46.003776 <6>[ 1.210282] megasas: 07.719.03.00-rc1
10381 11:04:46.013185 <6>[ 1.219931] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10382 11:04:46.021729 <6>[ 1.227868] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10383 11:04:46.038106 <6>[ 1.244436] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10384 11:04:46.093407 <6>[ 1.293890] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10385 11:04:48.278242 <6>[ 3.485309] Freeing initrd memory: 59544K
10386 11:04:48.290675 <6>[ 3.497183] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10387 11:04:48.301399 <6>[ 3.508287] tun: Universal TUN/TAP device driver, 1.6
10388 11:04:48.305079 <6>[ 3.514375] thunder_xcv, ver 1.0
10389 11:04:48.308092 <6>[ 3.517881] thunder_bgx, ver 1.0
10390 11:04:48.311444 <6>[ 3.521374] nicpf, ver 1.0
10391 11:04:48.321896 <6>[ 3.525409] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10392 11:04:48.325080 <6>[ 3.532884] hns3: Copyright (c) 2017 Huawei Corporation.
10393 11:04:48.331790 <6>[ 3.538472] hclge is initializing
10394 11:04:48.334935 <6>[ 3.542051] e1000: Intel(R) PRO/1000 Network Driver
10395 11:04:48.341747 <6>[ 3.547179] e1000: Copyright (c) 1999-2006 Intel Corporation.
10396 11:04:48.344893 <6>[ 3.553191] e1000e: Intel(R) PRO/1000 Network Driver
10397 11:04:48.351532 <6>[ 3.558407] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10398 11:04:48.358239 <6>[ 3.564596] igb: Intel(R) Gigabit Ethernet Network Driver
10399 11:04:48.365035 <6>[ 3.570247] igb: Copyright (c) 2007-2014 Intel Corporation.
10400 11:04:48.371475 <6>[ 3.576084] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10401 11:04:48.377970 <6>[ 3.582602] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10402 11:04:48.381058 <6>[ 3.589065] sky2: driver version 1.30
10403 11:04:48.388552 <6>[ 3.594010] usbcore: registered new device driver r8152-cfgselector
10404 11:04:48.394624 <6>[ 3.600546] usbcore: registered new interface driver r8152
10405 11:04:48.400989 <6>[ 3.606367] VFIO - User Level meta-driver version: 0.3
10406 11:04:48.408006 <6>[ 3.614595] usbcore: registered new interface driver usb-storage
10407 11:04:48.414360 <6>[ 3.621043] usbcore: registered new device driver onboard-usb-hub
10408 11:04:48.423868 <6>[ 3.630245] mt6397-rtc mt6359-rtc: registered as rtc0
10409 11:04:48.433609 <6>[ 3.635715] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:04:47 UTC (1720609487)
10410 11:04:48.436838 <6>[ 3.645301] i2c_dev: i2c /dev entries driver
10411 11:04:48.450604 <4>[ 3.657227] cpu cpu0: supply cpu not found, using dummy regulator
10412 11:04:48.456714 <4>[ 3.663652] cpu cpu1: supply cpu not found, using dummy regulator
10413 11:04:48.463394 <4>[ 3.670072] cpu cpu2: supply cpu not found, using dummy regulator
10414 11:04:48.469869 <4>[ 3.676473] cpu cpu3: supply cpu not found, using dummy regulator
10415 11:04:48.476863 <4>[ 3.682869] cpu cpu4: supply cpu not found, using dummy regulator
10416 11:04:48.483071 <4>[ 3.689263] cpu cpu5: supply cpu not found, using dummy regulator
10417 11:04:48.489950 <4>[ 3.695662] cpu cpu6: supply cpu not found, using dummy regulator
10418 11:04:48.496233 <4>[ 3.702071] cpu cpu7: supply cpu not found, using dummy regulator
10419 11:04:48.515636 <6>[ 3.722688] cpu cpu0: EM: created perf domain
10420 11:04:48.519134 <6>[ 3.727597] cpu cpu4: EM: created perf domain
10421 11:04:48.526217 <6>[ 3.733143] sdhci: Secure Digital Host Controller Interface driver
10422 11:04:48.532969 <6>[ 3.739574] sdhci: Copyright(c) Pierre Ossman
10423 11:04:48.539365 <6>[ 3.744476] Synopsys Designware Multimedia Card Interface Driver
10424 11:04:48.545843 <6>[ 3.751071] sdhci-pltfm: SDHCI platform and OF driver helper
10425 11:04:48.549267 <6>[ 3.751110] mmc0: CQHCI version 5.10
10426 11:04:48.556259 <6>[ 3.761032] ledtrig-cpu: registered to indicate activity on CPUs
10427 11:04:48.562792 <6>[ 3.767935] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10428 11:04:48.569626 <6>[ 3.774984] usbcore: registered new interface driver usbhid
10429 11:04:48.572644 <6>[ 3.780806] usbhid: USB HID core driver
10430 11:04:48.579112 <6>[ 3.785001] spi_master spi0: will run message pump with realtime priority
10431 11:04:48.621824 <6>[ 3.822199] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10432 11:04:48.639992 <6>[ 3.837058] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10433 11:04:48.646836 <6>[ 3.851732] cros-ec-spi spi0.0: Chrome EC device registered
10434 11:04:48.650074 <6>[ 3.852627] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10435 11:04:48.660966 <6>[ 3.867837] mmc0: Command Queue Engine enabled
10436 11:04:48.667620 <6>[ 3.872575] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10437 11:04:48.674119 <6>[ 3.880038] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10438 11:04:48.681735 <6>[ 3.888610] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10439 11:04:48.691731 <6>[ 3.890735] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10440 11:04:48.698079 <6>[ 3.895745] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10441 11:04:48.701400 <6>[ 3.904953] NET: Registered PF_PACKET protocol family
10442 11:04:48.708264 <6>[ 3.909745] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10443 11:04:48.711177 <6>[ 3.914420] 9pnet: Installing 9P2000 support
10444 11:04:48.717735 <6>[ 3.920196] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10445 11:04:48.724425 <5>[ 3.924122] Key type dns_resolver registered
10446 11:04:48.728240 <6>[ 3.935558] registered taskstats version 1
10447 11:04:48.734335 <5>[ 3.939938] Loading compiled-in X.509 certificates
10448 11:04:48.763977 <4>[ 3.964304] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10449 11:04:48.773835 <4>[ 3.974993] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10450 11:04:48.787579 <6>[ 3.994619] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10451 11:04:48.794677 <6>[ 4.001437] xhci-mtk 11200000.usb: xHCI Host Controller
10452 11:04:48.801121 <6>[ 4.006945] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10453 11:04:48.811169 <6>[ 4.014878] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10454 11:04:48.817751 <6>[ 4.024348] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10455 11:04:48.824588 <6>[ 4.030464] xhci-mtk 11200000.usb: xHCI Host Controller
10456 11:04:48.831008 <6>[ 4.035958] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10457 11:04:48.837876 <6>[ 4.043613] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10458 11:04:48.844933 <6>[ 4.051617] hub 1-0:1.0: USB hub found
10459 11:04:48.848353 <6>[ 4.055649] hub 1-0:1.0: 1 port detected
10460 11:04:48.857749 <6>[ 4.059983] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10461 11:04:48.861483 <6>[ 4.068894] hub 2-0:1.0: USB hub found
10462 11:04:48.864370 <6>[ 4.072916] hub 2-0:1.0: 1 port detected
10463 11:04:48.873525 <6>[ 4.080450] mtk-msdc 11f70000.mmc: Got CD GPIO
10464 11:04:48.886306 <6>[ 4.089805] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10465 11:04:48.896143 <6>[ 4.098185] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10466 11:04:48.903326 <6>[ 4.106529] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10467 11:04:48.912548 <6>[ 4.114880] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10468 11:04:48.919202 <6>[ 4.123221] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10469 11:04:48.929033 <6>[ 4.131563] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10470 11:04:48.935968 <6>[ 4.139904] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10471 11:04:48.945617 <6>[ 4.148243] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10472 11:04:48.952397 <6>[ 4.156582] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10473 11:04:48.962651 <6>[ 4.164932] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10474 11:04:48.969053 <6>[ 4.173271] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10475 11:04:48.979420 <6>[ 4.181613] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10476 11:04:48.985672 <6>[ 4.189951] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10477 11:04:48.995533 <6>[ 4.198290] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10478 11:04:49.002011 <6>[ 4.206631] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10479 11:04:49.009122 <6>[ 4.215318] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10480 11:04:49.015374 <6>[ 4.222459] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10481 11:04:49.022347 <6>[ 4.229243] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10482 11:04:49.032592 <6>[ 4.235982] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10483 11:04:49.039037 <6>[ 4.242883] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10484 11:04:49.045572 <6>[ 4.249749] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10485 11:04:49.055560 <6>[ 4.258882] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10486 11:04:49.065190 <6>[ 4.268002] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10487 11:04:49.075044 <6>[ 4.277296] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10488 11:04:49.085092 <6>[ 4.286763] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10489 11:04:49.091649 <6>[ 4.296231] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10490 11:04:49.102089 <6>[ 4.305351] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10491 11:04:49.111798 <6>[ 4.314817] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10492 11:04:49.121834 <6>[ 4.323938] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10493 11:04:49.131383 <6>[ 4.333232] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10494 11:04:49.141643 <6>[ 4.343393] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10495 11:04:49.151610 <6>[ 4.355055] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10496 11:04:49.277340 <6>[ 4.480795] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10497 11:04:49.432359 <6>[ 4.638778] hub 1-1:1.0: USB hub found
10498 11:04:49.435004 <6>[ 4.643304] hub 1-1:1.0: 4 ports detected
10499 11:04:49.447074 <6>[ 4.654167] hub 1-1:1.0: USB hub found
10500 11:04:49.450518 <6>[ 4.658533] hub 1-1:1.0: 4 ports detected
10501 11:04:49.557622 <6>[ 4.760985] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10502 11:04:49.582130 <6>[ 4.789312] hub 2-1:1.0: USB hub found
10503 11:04:49.585663 <6>[ 4.793745] hub 2-1:1.0: 3 ports detected
10504 11:04:49.596988 <6>[ 4.803586] hub 2-1:1.0: USB hub found
10505 11:04:49.599272 <6>[ 4.807985] hub 2-1:1.0: 3 ports detected
10506 11:04:49.772812 <6>[ 4.976734] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10507 11:04:49.905369 <6>[ 5.112272] hub 1-1.4:1.0: USB hub found
10508 11:04:49.908757 <6>[ 5.116956] hub 1-1.4:1.0: 2 ports detected
10509 11:04:49.921150 <6>[ 5.128169] hub 1-1.4:1.0: USB hub found
10510 11:04:49.924496 <6>[ 5.132776] hub 1-1.4:1.0: 2 ports detected
10511 11:04:49.985103 <6>[ 5.188925] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10512 11:04:50.094129 <6>[ 5.297423] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10513 11:04:50.129398 <4>[ 5.332850] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10514 11:04:50.139013 <4>[ 5.341945] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10515 11:04:50.183744 <6>[ 5.390591] r8152 2-1.3:1.0 eth0: v1.12.13
10516 11:04:50.221039 <6>[ 5.424599] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10517 11:04:50.412869 <6>[ 5.616804] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10518 11:04:51.792709 <6>[ 6.999978] r8152 2-1.3:1.0 eth0: carrier on
10519 11:04:53.844919 <5>[ 7.028600] Sending DHCP requests .., OK
10520 11:04:53.851775 <6>[ 9.056920] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10521 11:04:53.855027 <6>[ 9.065217] IP-Config: Complete:
10522 11:04:53.868332 <6>[ 9.068710] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10523 11:04:53.874955 <6>[ 9.079417] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10524 11:04:53.881457 <6>[ 9.088033] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10525 11:04:53.888144 <6>[ 9.088042] nameserver0=192.168.201.1
10526 11:04:53.891220 <6>[ 9.100166] clk: Disabling unused clocks
10527 11:04:53.895067 <6>[ 9.105895] ALSA device list:
10528 11:04:53.901732 <6>[ 9.109137] No soundcards found.
10529 11:04:53.909166 <6>[ 9.116558] Freeing unused kernel memory: 8512K
10530 11:04:53.912275 <6>[ 9.121448] Run /init as init process
10531 11:04:53.942821 <6>[ 9.150173] NET: Registered PF_INET6 protocol family
10532 11:04:53.949558 <6>[ 9.156759] Segment Routing with IPv6
10533 11:04:53.952729 <6>[ 9.160701] In-situ OAM (IOAM) with IPv6
10534 11:04:53.993170 <30>[ 9.174829] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10535 11:04:53.999892 <30>[ 9.207866] systemd[1]: Detected architecture arm64.
10536 11:04:53.999989
10537 11:04:54.006729 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10538 11:04:54.006826
10539 11:04:54.021112 <30>[ 9.228886] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10540 11:04:54.158563 <30>[ 9.362940] systemd[1]: Queued start job for default target graphical.target.
10541 11:04:54.222022 <30>[ 9.426150] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10542 11:04:54.228201 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10543 11:04:54.248706 <30>[ 9.453125] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10544 11:04:54.258676 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10545 11:04:54.277491 <30>[ 9.481822] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10546 11:04:54.287264 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10547 11:04:54.306062 <30>[ 9.509913] systemd[1]: Created slice user.slice - User and Session Slice.
10548 11:04:54.312269 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10549 11:04:54.331974 <30>[ 9.532807] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10550 11:04:54.338279 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10551 11:04:54.360107 <30>[ 9.561274] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10552 11:04:54.366663 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10553 11:04:54.394176 <30>[ 9.588845] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10554 11:04:54.404730 <30>[ 9.608650] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10555 11:04:54.410947 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10556 11:04:54.428597 <30>[ 9.633066] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10557 11:04:54.438686 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10558 11:04:54.452514 <30>[ 9.656849] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10559 11:04:54.462286 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10560 11:04:54.477827 <30>[ 9.685189] systemd[1]: Reached target paths.target - Path Units.
10561 11:04:54.487697 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10562 11:04:54.504936 <30>[ 9.709236] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10563 11:04:54.511828 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10564 11:04:54.525108 <30>[ 9.732765] systemd[1]: Reached target slices.target - Slice Units.
10565 11:04:54.534951 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10566 11:04:54.549631 <30>[ 9.757237] systemd[1]: Reached target swap.target - Swaps.
10567 11:04:54.556056 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10568 11:04:54.576713 <30>[ 9.781180] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10569 11:04:54.586808 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10570 11:04:54.604857 <30>[ 9.809262] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10571 11:04:54.614810 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10572 11:04:54.634129 <30>[ 9.838210] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10573 11:04:54.644077 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10574 11:04:54.661441 <30>[ 9.865370] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10575 11:04:54.671334 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10576 11:04:54.690275 <30>[ 9.894120] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10577 11:04:54.696641 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10578 11:04:54.717417 <30>[ 9.921464] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10579 11:04:54.726961 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10580 11:04:54.745032 <30>[ 9.949275] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10581 11:04:54.754988 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10582 11:04:54.796673 <30>[ 10.000914] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10583 11:04:54.802951 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10584 11:04:54.816177 <30>[ 10.020511] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10585 11:04:54.822602 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10586 11:04:54.884675 <30>[ 10.089022] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10587 11:04:54.891131 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10588 11:04:54.919660 <30>[ 10.117329] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10589 11:04:54.933266 <30>[ 10.137701] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10590 11:04:54.943145 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10591 11:04:54.965453 <30>[ 10.169874] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10592 11:04:54.971881 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10593 11:04:55.017139 <30>[ 10.221019] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10594 11:04:55.030174 Starting [0;1;39mmodprobe@dm_mod.s…[<6>[ 10.232397] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10595 11:04:55.033593 0m - Load Kernel Module dm_mod...
10596 11:04:55.057874 <30>[ 10.261918] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10597 11:04:55.064232 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10598 11:04:55.089471 <30>[ 10.293247] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10599 11:04:55.095870 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10600 11:04:55.156583 <30>[ 10.361231] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10601 11:04:55.162961 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10602 11:04:55.192723 <30>[ 10.397614] systemd[1]: Starting systemd-journald.service - Journal Service...
10603 11:04:55.199315 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10604 11:04:55.218752 <30>[ 10.423615] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10605 11:04:55.225398 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10606 11:04:55.276120 <30>[ 10.477441] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10607 11:04:55.282435 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10608 11:04:55.305163 <30>[ 10.509591] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10609 11:04:55.314744 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10610 11:04:55.335053 <30>[ 10.540025] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10611 11:04:55.341650 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10612 11:04:55.368931 <30>[ 10.573856] systemd[1]: Started systemd-journald.service - Journal Service.
10613 11:04:55.375440 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10614 11:04:55.398339 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10615 11:04:55.420614 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10616 11:04:55.440542 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10617 11:04:55.465354 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10618 11:04:55.487516 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10619 11:04:55.506973 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10620 11:04:55.527543 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10621 11:04:55.550522 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10622 11:04:55.575090 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10623 11:04:55.597761 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10624 11:04:55.621261 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10625 11:04:55.646770 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10626 11:04:55.664645 See 'systemctl status systemd-remount-fs.service' for details.
10627 11:04:55.685565 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10628 11:04:55.706733 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10629 11:04:55.772898 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10630 11:04:55.794184 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10631 11:04:55.808515 <46>[ 11.013603] systemd-journald[182]: Received client request to flush runtime journal.
10632 11:04:55.820115 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10633 11:04:55.843368 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10634 11:04:55.864143 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10635 11:04:55.889129 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10636 11:04:55.909857 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10637 11:04:55.929589 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10638 11:04:55.949748 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10639 11:04:55.973654 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10640 11:04:56.016566 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10641 11:04:56.039204 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10642 11:04:56.060382 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10643 11:04:56.079888 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10644 11:04:56.148420 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10645 11:04:56.168054 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10646 11:04:56.187990 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10647 11:04:56.224559 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10648 11:04:56.245412 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10649 11:04:56.267312 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10650 11:04:56.304029 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10651 11:04:56.329156 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10652 11:04:56.353487 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10653 11:04:56.449177 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10654 11:04:56.468633 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10655 11:04:56.488170 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10656 11:04:56.505469 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10657 11:04:56.524323 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10658 11:04:56.541728 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10659 11:04:56.560684 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10660 11:04:56.577680 <6>[ 11.782596] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10661 11:04:56.592100 [[0;32m OK [0m] Reached target [0;1;39mbasi<6>[ 11.797457] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10662 11:04:56.601784 c.target[0m - B<6>[ 11.798359] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10663 11:04:56.601955 asic System.
10664 11:04:56.612158 <6>[ 11.805322] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10665 11:04:56.618273 <6>[ 11.814649] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10666 11:04:56.628140 <6>[ 11.824568] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10667 11:04:56.638157 <4>[ 11.832682] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10668 11:04:56.644702 <6>[ 11.850697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10669 11:04:56.654772 <6>[ 11.857762] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10670 11:04:56.661287 <6>[ 11.859011] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10671 11:04:56.668069 <3>[ 11.869124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 11:04:56.677664 <3>[ 11.882134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 11:04:56.684928 <6>[ 11.884270] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10674 11:04:56.694349 <3>[ 11.890264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 11:04:56.701289 <6>[ 11.898294] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10676 11:04:56.707633 <6>[ 11.900377] remoteproc remoteproc0: scp is available
10677 11:04:56.711316 <6>[ 11.900547] remoteproc remoteproc0: powering up scp
10678 11:04:56.720783 <6>[ 11.900555] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10679 11:04:56.727266 <6>[ 11.900591] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10680 11:04:56.733962 <6>[ 11.938784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10681 11:04:56.743867 <6>[ 11.946652] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10682 11:04:56.750345 <3>[ 11.950341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 11:04:56.757193 <6>[ 11.957344] mc: Linux media interface: v0.10
10684 11:04:56.763488 <3>[ 11.964023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 11:04:56.770214 <6>[ 11.968691] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10686 11:04:56.780138 <3>[ 11.976523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 11:04:56.786907 <3>[ 11.976531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 11:04:56.793422 <3>[ 11.976534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 11:04:56.800072 <6>[ 11.983519] pci_bus 0000:00: root bus resource [bus 00-ff]
10690 11:04:56.806579 <4>[ 11.994063] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10691 11:04:56.816547 <6>[ 11.999571] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10692 11:04:56.823025 <3>[ 12.000900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 11:04:56.829559 <3>[ 12.012769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 11:04:56.839294 <4>[ 12.012811] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10695 11:04:56.849113 <6>[ 12.013351] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10696 11:04:56.859181 <6>[ 12.013392] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10697 11:04:56.865571 <3>[ 12.020694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 11:04:56.876449 <6>[ 12.025693] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10699 11:04:56.883211 <6>[ 12.025700] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10700 11:04:56.889743 <6>[ 12.025706] remoteproc remoteproc0: remote processor scp is now up
10701 11:04:56.896784 <6>[ 12.025833] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10702 11:04:56.903136 <6>[ 12.027874] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10703 11:04:56.913128 <3>[ 12.036049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 11:04:56.920022 <6>[ 12.044358] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10705 11:04:56.927190 <6>[ 12.045162] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10706 11:04:56.936661 <3>[ 12.051574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 11:04:56.939876 <6>[ 12.061574] pci 0000:00:00.0: supports D1 D2
10708 11:04:56.946403 <3>[ 12.071399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 11:04:56.956939 <3>[ 12.071402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 11:04:56.963541 <4>[ 12.073958] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10711 11:04:56.970272 <4>[ 12.073958] Fallback method does not support PEC.
10712 11:04:56.977773 <6>[ 12.079477] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10713 11:04:56.983926 <3>[ 12.087994] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 11:04:56.993941 <3>[ 12.088041] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10715 11:04:57.000853 <6>[ 12.095875] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10716 11:04:57.010675 <3>[ 12.101447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 11:04:57.017175 <3>[ 12.101474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 11:04:57.027146 <3>[ 12.109045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 11:04:57.033601 <6>[ 12.110573] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10720 11:04:57.043700 <6>[ 12.138603] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10721 11:04:57.050168 <6>[ 12.139948] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10722 11:04:57.056677 <6>[ 12.161033] videodev: Linux video capture interface: v2.00
10723 11:04:57.063407 <6>[ 12.168704] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10724 11:04:57.070063 <3>[ 12.169923] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10725 11:04:57.080168 <6>[ 12.179205] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10726 11:04:57.086581 <6>[ 12.181161] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10727 11:04:57.090006 <6>[ 12.189705] Bluetooth: Core ver 2.22
10728 11:04:57.100033 <3>[ 12.191917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10729 11:04:57.106541 <6>[ 12.197289] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10730 11:04:57.113176 <6>[ 12.206142] NET: Registered PF_BLUETOOTH protocol family
10731 11:04:57.116742 <6>[ 12.214410] pci 0000:01:00.0: supports D1 D2
10732 11:04:57.124190 <6>[ 12.222381] Bluetooth: HCI device and connection manager initialized
10733 11:04:57.130960 <6>[ 12.222395] Bluetooth: HCI socket layer initialized
10734 11:04:57.137625 <6>[ 12.230459] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10735 11:04:57.140781 <6>[ 12.239233] Bluetooth: L2CAP socket layer initialized
10736 11:04:57.148113 <6>[ 12.247126] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10737 11:04:57.154823 <6>[ 12.255027] Bluetooth: SCO socket layer initialized
10738 11:04:57.161213 <6>[ 12.260651] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10739 11:04:57.168254 <6>[ 12.260678] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10740 11:04:57.178569 <6>[ 12.260681] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10741 11:04:57.184893 <6>[ 12.260688] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10742 11:04:57.194750 <6>[ 12.260701] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10743 11:04:57.201441 <6>[ 12.260713] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10744 11:04:57.207928 <6>[ 12.260725] pci 0000:00:00.0: PCI bridge to [bus 01]
10745 11:04:57.214432 <6>[ 12.260730] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10746 11:04:57.221417 <6>[ 12.260863] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10747 11:04:57.228063 <6>[ 12.261329] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10748 11:04:57.231429 <6>[ 12.261849] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10749 11:04:57.244597 <6>[ 12.267227] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10750 11:04:57.251569 <6>[ 12.277922] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10751 11:04:57.260851 <5>[ 12.278191] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10752 11:04:57.264197 <6>[ 12.285213] usbcore: registered new interface driver uvcvideo
10753 11:04:57.274091 <3>[ 12.288361] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10754 11:04:57.280491 <5>[ 12.295070] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10755 11:04:57.287389 <6>[ 12.314688] usbcore: registered new interface driver btusb
10756 11:04:57.293935 <5>[ 12.321825] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10757 11:04:57.306954 <4>[ 12.321899] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10758 11:04:57.310751 <3>[ 12.321910] Bluetooth: hci0: Failed to load firmware file (-2)
10759 11:04:57.317101 <3>[ 12.321914] Bluetooth: hci0: Failed to set up firmware (-2)
10760 11:04:57.327189 <4>[ 12.321918] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10761 11:04:57.337121 <3>[ 12.333369] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10762 11:04:57.346787 <4>[ 12.338191] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10763 11:04:57.353467 <3>[ 12.361708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10764 11:04:57.360074 <6>[ 12.362635] cfg80211: failed to load regulatory.db
10765 11:04:57.370047 <3>[ 12.387795] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10766 11:04:57.376668 <6>[ 12.425457] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10767 11:04:57.383221 <6>[ 12.589177] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10768 11:04:57.390029 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10769 11:04:57.407855 <6>[ 12.615825] mt7921e 0000:01:00.0: ASIC revision: 79610010
10770 11:04:57.457287 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10771 11:04:57.480479 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10772 11:04:57.498722 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10773 11:04:57.511312 <6>[ 12.716095] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10774 11:04:57.514702 <6>[ 12.716095]
10775 11:04:57.540813 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice<3>[ 12.742622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10776 11:04:57.541449 [0m - Permit User Sessions.
10777 11:04:57.568485 <3>[ 12.773022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 11:04:57.584534 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10779 11:04:57.604773 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10780 11:04:57.621120 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10781 11:04:57.640152 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10782 11:04:57.694681 [[0;32m OK [<46>[ 12.886439] systemd-journald[182]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.0 (1536 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
10783 11:04:57.710941 0m] Started [0;<46>[ 12.908942] systemd-journald[182]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
10784 11:04:57.714729 1;39mgetty@tty1.service[0m - Getty on tty1.
10785 11:04:57.761747 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10786 11:04:57.784715 [[0;32m OK [<6>[ 12.986438] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10787 11:04:57.787806 0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10788 11:04:57.808475 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10789 11:04:57.828649 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10790 11:04:57.882326 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10791 11:04:57.906763 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10792 11:04:57.932708 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10793 11:04:57.990603 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10794 11:04:58.010477 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10795 11:04:58.037275 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10796 11:04:58.081517
10797 11:04:58.084812 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10798 11:04:58.085195
10799 11:04:58.088073 debian-bookworm-arm64 login: root (automatic login)
10800 11:04:58.088575
10801 11:04:58.101694 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
10802 11:04:58.102103
10803 11:04:58.108167 The programs included with the Debian GNU/Linux system are free software;
10804 11:04:58.114719 the exact distribution terms for each program are described in the
10805 11:04:58.118276 individual files in /usr/share/doc/*/copyright.
10806 11:04:58.118679
10807 11:04:58.124809 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10808 11:04:58.128063 permitted by applicable law.
10809 11:04:58.129339 Matched prompt #10: / #
10811 11:04:58.130327 Setting prompt string to ['/ #']
10812 11:04:58.130751 end: 2.2.5.1 login-action (duration 00:00:14) [common]
10814 11:04:58.131664 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
10815 11:04:58.132069 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
10816 11:04:58.132410 Setting prompt string to ['/ #']
10817 11:04:58.132686 Forcing a shell prompt, looking for ['/ #']
10818 11:04:58.133096 Sending line: ''
10820 11:04:58.184207 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10821 11:04:58.184550 Waiting using forced prompt support (timeout 00:02:30)
10822 11:04:58.189370 / #
10823 11:04:58.190067 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10824 11:04:58.190504 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
10825 11:04:58.190944 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10826 11:04:58.191331 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
10827 11:04:58.191741 end: 2 depthcharge-action (duration 00:01:37) [common]
10828 11:04:58.192145 start: 3 lava-test-retry (timeout 00:07:53) [common]
10829 11:04:58.192551 start: 3.1 lava-test-shell (timeout 00:07:53) [common]
10830 11:04:58.192886 Using namespace: common
10831 11:04:58.193216 Sending line: '#'
10833 11:04:58.294005 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10834 11:04:58.298629 / # #
10835 11:04:58.298882 Using /lava-14786812
10836 11:04:58.298945 Sending line: 'export SHELL=/bin/sh'
10838 11:04:58.404859 / # export SHELL=/bin/sh
10839 11:04:58.405431 Sending line: '. /lava-14786812/environment'
10841 11:04:58.511286 / # . /lava-14786812/environment
10842 11:04:58.511578 Sending line: '/lava-14786812/bin/lava-test-runner /lava-14786812/0'
10844 11:04:58.612030 Test shell timeout: 10s (minimum of the action and connection timeout)
10845 11:04:58.616613 / # /lava-14786812/bin/lava-test-runner /lava-14786812/0
10846 11:04:58.649486 + export TESTRUN_ID=0_igt-kms-me<8>[ 13.856162] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14786812_1.5.2.3.1>
10847 11:04:58.649751 Received signal: <STARTRUN> 0_igt-kms-mediatek 14786812_1.5.2.3.1
10848 11:04:58.649821 Starting test lava.0_igt-kms-mediatek (14786812_1.5.2.3.1)
10849 11:04:58.649897 Skipping test definition patterns.
10850 11:04:58.655685 <6>[ 13.856922] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10851 11:04:58.655763 diatek
10852 11:04:58.662449 + cd /lava-14786812/0/tests/0_igt-kms-mediatek
10853 11:04:58.662525 + cat uuid
10854 11:04:58.666035 + UUID=14786812_1.5.2.3.1
10855 11:04:58.666111 + set +x
10856 11:04:58.679318 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<8>[ 13.887203] <LAVA_SIGNAL_TESTSET START core_auth>
10857 11:04:58.679564 Received signal: <TESTSET> START core_auth
10858 11:04:58.679633 Starting test_set core_auth
10859 11:04:58.688953 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
10860 11:04:58.701202 <14>[ 13.909730] [IGT] core_auth: executing
10861 11:04:58.707845 IGT-Version: 1.2<14>[ 13.914287] [IGT] core_auth: starting subtest getclient-simple
10862 11:04:58.717791 8-ga44ebfe (aarc<14>[ 13.922030] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
10863 11:04:58.721278 h64) (Linux: 6.1<14>[ 13.930262] [IGT] core_auth: exiting, ret=0
10864 11:04:58.724155 .96-cip24 aarch64)
10865 11:04:58.727693 Using IGT_SRANDOM=1720609498 for randomisation
10866 11:04:58.730927 Starting subtest: getclient-simple
10867 11:04:58.740784 Opened d<8>[ 13.944657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
10868 11:04:58.740860 evice: /dev/dri/card0
10869 11:04:58.741087 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
10871 11:04:58.747347 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
10872 11:04:58.757681 <14>[ 13.966188] [IGT] core_auth: executing
10873 11:04:58.764255 IGT-Version: 1.2<14>[ 13.970598] [IGT] core_auth: starting subtest getclient-master-drop
10874 11:04:58.774823 8-ga44ebfe (aarc<14>[ 13.978712] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
10875 11:04:58.781000 h64) (Linux: 6.1<14>[ 13.987429] [IGT] core_auth: exiting, ret=0
10876 11:04:58.781074 .96-cip24 aarch64)
10877 11:04:58.794108 Using IGT_SRANDOM=1720609498 for randomisati<8>[ 13.997988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
10878 11:04:58.794184 on
10879 11:04:58.794411 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
10881 11:04:58.797356 Starting subtest: getclient-master-drop
10882 11:04:58.801143 Opened device: /dev/dri/card0
10883 11:04:58.804072 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
10884 11:04:58.810694 <14>[ 14.018777] [IGT] core_auth: executing
10885 11:04:58.817337 IGT-Version: 1.2<14>[ 14.023213] [IGT] core_auth: starting subtest basic-auth
10886 11:04:58.823883 8-ga44ebfe (aarc<14>[ 14.030224] [IGT] core_auth: finished subtest basic-auth, SUCCESS
10887 11:04:58.830536 h64) (Linux: 6.1<14>[ 14.038085] [IGT] core_auth: exiting, ret=0
10888 11:04:58.834007 .96-cip24 aarch64)
10889 11:04:58.844851 Using IGT_SRANDOM=1720609498 for randomisati<8>[ 14.049403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
10890 11:04:58.844977 on
10891 11:04:58.845266 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
10893 11:04:58.847196 Opened device: /dev/dri/card0
10894 11:04:58.847317 Starting subtest: basic-auth
10895 11:04:58.853913 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
10896 11:04:58.860658 <14>[ 14.068881] [IGT] core_auth: executing
10897 11:04:58.867363 IGT-Version: 1.2<14>[ 14.073289] [IGT] core_auth: starting subtest many-magics
10898 11:04:58.870340 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10899 11:04:58.880782 Using IGT_SRANDOM=1720609498<14>[ 14.085996] [IGT] core_auth: finished subtest many-magics, SUCCESS
10900 11:04:58.887363 for randomisati<14>[ 14.093852] [IGT] core_auth: exiting, ret=0
10901 11:04:58.887852 on
10902 11:04:58.890483 Opened device: /dev/dri/card0
10903 11:04:58.900451 Starting subtest: many-magics<8>[ 14.104179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
10904 11:04:58.900834
10905 11:04:58.901321 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
10907 11:04:58.907137 Reopening device failed after <8>[ 14.113694] <LAVA_SIGNAL_TESTSET STOP>
10908 11:04:58.907529 1020 opens
10909 11:04:58.908100 Received signal: <TESTSET> STOP
10910 11:04:58.908410 Closing test_set core_auth
10911 11:04:58.910706 [1mSubtest many-magics: SUCCESS (0.006s)[0m
10912 11:04:58.936606 <14>[ 14.144859] [IGT] core_getclient: executing
10913 11:04:58.943330 IGT-Version: 1.2<14>[ 14.149809] [IGT] core_getclient: exiting, ret=0
10914 11:04:58.946601 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10915 11:04:58.956440 Using IGT_SR<8>[ 14.161536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
10916 11:04:58.957103 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
10918 11:04:58.960088 ANDOM=1720609498 for randomisation
10919 11:04:58.960478 Opened device: /dev/dri/card0
10920 11:04:58.963371 SUCCESS (0.006s)
10921 11:04:58.986394 <14>[ 14.194341] [IGT] core_getstats: executing
10922 11:04:58.992865 IGT-Version: 1.2<14>[ 14.199159] [IGT] core_getstats: exiting, ret=0
10923 11:04:58.996362 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10924 11:04:59.006289 Using IGT_SRANDOM=1720609498 for randomisati<8>[ 14.212308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
10925 11:04:59.006914 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
10927 11:04:59.008988 on
10928 11:04:59.009065 Opened device: /dev/dri/card0
10929 11:04:59.012131 SUCCESS (0.006s)
10930 11:04:59.050129 <14>[ 14.258673] [IGT] core_getversion: executing
10931 11:04:59.056587 IGT-Version: 1.2<14>[ 14.263669] [IGT] core_getversion: exiting, ret=0
10932 11:04:59.060311 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10933 11:04:59.069998 Using IGT_SRANDOM=1720609499<8>[ 14.275711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
10934 11:04:59.070374 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
10936 11:04:59.073245 for randomisation
10937 11:04:59.076447 Opened device: /dev/dri/card0
10938 11:04:59.076644 SUCCESS (0.006s)
10939 11:04:59.117500 <14>[ 14.325770] [IGT] core_setmaster_vs_auth: executing
10940 11:04:59.124211 IGT-Version: 1.2<14>[ 14.331779] [IGT] core_setmaster_vs_auth: exiting, ret=0
10941 11:04:59.130673 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10942 11:04:59.140961 Using IGT_SRANDOM=1720609499<8>[ 14.343913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
10943 11:04:59.141399 for randomisation
10944 11:04:59.141943 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
10946 11:04:59.144554 Opened device: /dev/dri/card0
10947 11:04:59.147178 SUCCESS (0.007s)
10948 11:04:59.160860 <8>[ 14.368976] <LAVA_SIGNAL_TESTSET START drm_read>
10949 11:04:59.161520 Received signal: <TESTSET> START drm_read
10950 11:04:59.161859 Starting test_set drm_read
10951 11:04:59.177036 <14>[ 14.385151] [IGT] drm_read: executing
10952 11:04:59.183536 IGT-Version: 1.2<14>[ 14.389582] [IGT] drm_read: exiting, ret=77
10953 11:04:59.187045 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10954 11:04:59.193647 Using IGT_SR<8>[ 14.400421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
10955 11:04:59.194630 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
10957 11:04:59.196831 ANDOM=1720609499 for randomisation
10958 11:04:59.200290 Opened device: /dev/dri/card0
10959 11:04:59.203477 No KMS driver or no outputs, pipes: 16, outputs: 0
10960 11:04:59.210232 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
10961 11:04:59.223945 <14>[ 14.432077] [IGT] drm_read: executing
10962 11:04:59.230643 IGT-Version: 1.2<14>[ 14.437197] [IGT] drm_read: exiting, ret=77
10963 11:04:59.234072 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10964 11:04:59.243691 Using IGT_SRANDOM=1720609499<8>[ 14.449039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
10965 11:04:59.243777 for randomisation
10966 11:04:59.244002 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
10968 11:04:59.247074 Opened device: /dev/dri/card0
10969 11:04:59.250098 No KMS driver or no outputs, pipes: 16, outputs: 0
10970 11:04:59.256569 [1mSubtest fault-buffer: SKIP (0.000s)[0m
10971 11:04:59.263818 <14>[ 14.472587] [IGT] drm_read: executing
10972 11:04:59.270593 IGT-Version: 1.2<14>[ 14.477079] [IGT] drm_read: exiting, ret=77
10973 11:04:59.273679 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10974 11:04:59.280377 Using IGT_SR<8>[ 14.487849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
10975 11:04:59.280618 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
10977 11:04:59.284066 ANDOM=1720609499 for randomisation
10978 11:04:59.287113 Opened device: /dev/dri/card0
10979 11:04:59.290253 No KMS driver or no outputs, pipes: 16, outputs: 0
10980 11:04:59.296973 [1mSubtest empty-block: <14>[ 14.507434] [IGT] drm_read: executing
10981 11:04:59.303554 SKIP (0.000s)[0<14>[ 14.512078] [IGT] drm_read: exiting, ret=77
10982 11:04:59.303638 m
10983 11:04:59.310450 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10984 11:04:59.316945 Using IGT<8>[ 14.523259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
10985 11:04:59.317192 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
10987 11:04:59.320000 _SRANDOM=1720609499 for randomisation
10988 11:04:59.323532 Opened device: /dev/dri/card0
10989 11:04:59.329795 No KMS driver or no outputs, pipes: 16, outputs: 0
10990 11:04:59.333469 [1mSubtest empty-nonb<14>[ 14.544128] [IGT] drm_read: executing
10991 11:04:59.339881 lock: SKIP (0.00<14>[ 14.548902] [IGT] drm_read: exiting, ret=77
10992 11:04:59.339956 0s)[0m
10993 11:04:59.346579 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10994 11:04:59.356620 Usi<8>[ 14.559911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
10995 11:04:59.356864 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
10997 11:04:59.359736 ng IGT_SRANDOM=1720609499 for randomisation
10998 11:04:59.363229 Opened device: /dev/dri/card0
10999 11:04:59.366466 No KMS driver or no outputs, pipes: 16, outputs: 0
11000 11:04:59.373044 [1mSubtest short-buffer-block: SKIP (0.000s)[0<14>[ 14.582685] [IGT] drm_read: executing
11001 11:04:59.376231 m
11002 11:04:59.379449 IGT-Version: 1.2<14>[ 14.588495] [IGT] drm_read: exiting, ret=77
11003 11:04:59.386275 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11004 11:04:59.392648 Using IGT_SR<8>[ 14.599068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11005 11:04:59.392895 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11007 11:04:59.396120 ANDOM=1720609499 for randomisation
11008 11:04:59.399535 Opened device: /dev/dri/card0
11009 11:04:59.406168 No KMS driver or no outputs, pipes: 16, outputs: 0
11010 11:04:59.409184 [1mSubtest short-buffer-<14>[ 14.619616] [IGT] drm_read: executing
11011 11:04:59.416112 nonblock: SKIP (<14>[ 14.624904] [IGT] drm_read: exiting, ret=77
11012 11:04:59.419053 0.000s)[0m
11013 11:04:59.422303 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11014 11:04:59.432495 <8>[ 14.635963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11015 11:04:59.432571
11016 11:04:59.432798 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11018 11:04:59.439301 Using IGT_SRANDOM=1720609499 fo<8>[ 14.646484] <LAVA_SIGNAL_TESTSET STOP>
11019 11:04:59.439376 r randomisation
11020 11:04:59.439601 Received signal: <TESTSET> STOP
11021 11:04:59.439661 Closing test_set drm_read
11022 11:04:59.442377 Opened device: /dev/dri/card0
11023 11:04:59.445809 No KMS driver or no outputs, pipes: 16, outputs: 0
11024 11:04:59.452338 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11025 11:04:59.469565 <8>[ 14.678206] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11026 11:04:59.469861 Received signal: <TESTSET> START kms_addfb_basic
11027 11:04:59.469948 Starting test_set kms_addfb_basic
11028 11:04:59.497118 <14>[ 14.705841] [IGT] kms_addfb_basic: executing
11029 11:04:59.510835 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 14.715308] [IGT] kms_addfb_basic: starting subtest unused-handle
11030 11:04:59.510916 4)
11031 11:04:59.517059 Using IGT_SR<14>[ 14.722896] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11032 11:04:59.520396 ANDOM=1720609499 for randomisation
11033 11:04:59.523765 Opened device: /dev/dri/card0
11034 11:04:59.527130 Starting subtest: unused-handle
11035 11:04:59.533474 [1mSubtest <14>[ 14.740219] [IGT] kms_addfb_basic: exiting, ret=0
11036 11:04:59.536939 unused-handle: SUCCESS (0.000s)[0m
11037 11:04:59.547021 Test requirement not met in function igt_re<8>[ 14.753002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11038 11:04:59.547267 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11040 11:04:59.549996 quire_intel, file ../lib/drmtest.c:880:
11041 11:04:59.553298 Test requirement: is_intel_device(fd)
11042 11:04:59.560240 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11043 11:04:59.563414 Test requirement: is_intel_device(fd)
11044 11:04:59.570051 No KMS driver or no outputs, pipes: 16, outputs: 0
11045 11:04:59.573175 <14>[ 14.783380] [IGT] kms_addfb_basic: executing
11046 11:04:59.586458 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 14.793114] [IGT] kms_addfb_basic: starting subtest unused-pitches
11047 11:04:59.586536 4)
11048 11:04:59.596751 Using IGT_SR<14>[ 14.800652] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11049 11:04:59.599561 ANDOM=1720609499 for randomisation
11050 11:04:59.603225 Opened device: /dev/dri/card0
11051 11:04:59.603303 Starting subtest: unused-pitches
11052 11:04:59.609715 [1mSubtest<14>[ 14.818156] [IGT] kms_addfb_basic: exiting, ret=0
11053 11:04:59.612934 unused-pitches: SUCCESS (0.000s)[0m
11054 11:04:59.625903 Test requirement not met in function igt_<8>[ 14.831012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11055 11:04:59.626162 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11057 11:04:59.629360 require_intel, file ../lib/drmtest.c:880:
11058 11:04:59.632581 Test requirement: is_intel_device(fd)
11059 11:04:59.639217 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11060 11:04:59.642718 Test requirement: is_intel_device(fd)
11061 11:04:59.646091 No KMS driver or no outputs, pipes: 16, outputs: 0
11062 11:04:59.653094 <14>[ 14.861267] [IGT] kms_addfb_basic: executing
11063 11:04:59.666158 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 14.870851] [IGT] kms_addfb_basic: starting subtest unused-offsets
11064 11:04:59.666658 4)
11065 11:04:59.673186 Using IGT_SR<14>[ 14.878460] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11066 11:04:59.676358 ANDOM=1720609499 for randomisation
11067 11:04:59.679588 Opened device: /dev/dri/card0
11068 11:04:59.683064 Starting subtest: unused-offsets
11069 11:04:59.689459 [1mSubtest<14>[ 14.895775] [IGT] kms_addfb_basic: exiting, ret=0
11070 11:04:59.692876 unused-offsets: SUCCESS (0.000s)[0m
11071 11:04:59.702906 Test requirement not met in function igt_<8>[ 14.908641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11072 11:04:59.703676 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11074 11:04:59.706187 require_intel, file ../lib/drmtest.c:880:
11075 11:04:59.709420 Test requirement: is_intel_device(fd)
11076 11:04:59.715990 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11077 11:04:59.719123 Test requirement: is_intel_device(fd)
11078 11:04:59.726109 No KMS driver or no outputs, pipes: 16, outputs: 0
11079 11:04:59.732530 <14>[ 14.939454] [IGT] kms_addfb_basic: executing
11080 11:04:59.742273 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 14.949166] [IGT] kms_addfb_basic: starting subtest unused-modifier
11081 11:04:59.742664 4)
11082 11:04:59.752539 Using IGT_SR<14>[ 14.956553] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11083 11:04:59.755859 ANDOM=1720609499 for randomisation
11084 11:04:59.759021 Opened device: /dev/dri/card0
11085 11:04:59.761973 Starting subtest: unused-modifier
11086 11:04:59.765169 [1mSubtes<14>[ 14.974012] [IGT] kms_addfb_basic: exiting, ret=0
11087 11:04:59.768552 t unused-modifier: SUCCESS (0.000s)[0m
11088 11:04:59.781972 Test requirement not met in function ig<8>[ 14.986528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11089 11:04:59.782220 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11091 11:04:59.785272 t_require_intel, file ../lib/drmtest.c:880:
11092 11:04:59.788412 Test requirement: is_intel_device(fd)
11093 11:04:59.794967 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11094 11:04:59.798270 Test requirement: is_intel_device(fd)
11095 11:04:59.805192 No KMS driver or no outputs, pipes: 16, outputs: 0
11096 11:04:59.808412 <14>[ 15.017160] [IGT] kms_addfb_basic: executing
11097 11:04:59.821500 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 15.026661] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11098 11:04:59.821889 4)
11099 11:04:59.831453 Using IGT_SR<14>[ 15.034699] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11100 11:04:59.834818 ANDOM=1720609499 for randomisation
11101 11:04:59.835202 Opened device: /dev/dri/card0
11102 11:04:59.838086 Starting subtest: clobberred-modifier
11103 11:04:59.844918 Test r<14>[ 15.052273] [IGT] kms_addfb_basic: exiting, ret=77
11104 11:04:59.851305 equirement not met in function igt_require_i915, file ../lib/drmtest.c:885:
11105 11:04:59.858383 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11107 11:04:59.861529 Tes<8>[ 15.065113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11108 11:04:59.861964 t requirement: is_i915_device(fd)
11109 11:04:59.867840 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11110 11:04:59.874579 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11111 11:04:59.878246 Test requirement: is_intel_device(fd)
11112 11:04:59.887646 Test requirement not met in function igt_require_intel, file .<14>[ 15.096046] [IGT] kms_addfb_basic: executing
11113 11:04:59.891067 ./lib/drmtest.c:880:
11114 11:04:59.894645 Test requirement: is_intel_device(fd)
11115 11:04:59.900709 No <14>[ 15.106166] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11116 11:04:59.910851 KMS driver or no<14>[ 15.114561] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11117 11:04:59.914000 outputs, pipes: 16, outputs: 0
11118 11:04:59.920611 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11119 11:04:59.927249 Using IGT_S<14>[ 15.132925] [IGT] kms_addfb_basic: exiting, ret=77
11120 11:04:59.930411 RANDOM=1720609499 for randomisation
11121 11:04:59.930796 Opened device: /dev/dri/card0
11122 11:04:59.940687 Starting sub<8>[ 15.145531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11123 11:04:59.941341 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11125 11:04:59.943855 test: invalid-smem-bo-on-discrete
11126 11:04:59.950519 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11127 11:04:59.953539 Test requirement: is_intel_device(fd)
11128 11:04:59.960197 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11129 11:04:59.970317 Test requirement not met in function igt_require_intel<14>[ 15.177156] [IGT] kms_addfb_basic: executing
11130 11:04:59.970712 , file ../lib/drmtest.c:880:
11131 11:04:59.980024 Test requirement: is_intel_device(<14>[ 15.187459] [IGT] kms_addfb_basic: starting subtest legacy-format
11132 11:04:59.980100 fd)
11133 11:04:59.989753 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11134 11:04:59.993121 Test requirement: is_intel_device(fd)
11135 11:04:59.999780 <14>[ 15.205088] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11136 11:05:00.003112 No KMS driver or no outputs, pipes: 16, outputs: 0
11137 11:05:00.012978 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 15.221150] [IGT] kms_addfb_basic: exiting, ret=0
11138 11:05:00.013054 6.1.96-cip24 aarch64)
11139 11:05:00.020259 Using IGT_SRANDOM=1720609499 for randomisation
11140 11:05:00.026812 Opened d<8>[ 15.232976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11141 11:05:00.027451 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11143 11:05:00.030266 evice: /dev/dri/card0
11144 11:05:00.033327 Starting subtest: legacy-format
11145 11:05:00.036934 Successfully fuzzed 10000 {bpp, depth} variations
11146 11:05:00.039907 [1mSubtest legacy-format: SUCCESS (0.011s)[0m
11147 11:05:00.046534 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11148 11:05:00.056234 Test requirement: is_intel_devic<14>[ 15.263484] [IGT] kms_addfb_basic: executing
11149 11:05:00.056623 e(fd)
11150 11:05:00.062871 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11151 11:05:00.069700 Test <14>[ 15.275787] [IGT] kms_addfb_basic: starting subtest no-handle
11152 11:05:00.079321 requirement: is_<14>[ 15.283155] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11153 11:05:00.079703 intel_device(fd)
11154 11:05:00.082818 No KMS driver or no outputs, pipes: 16, outputs: 0
11155 11:05:00.089263 IGT-Versio<14>[ 15.297796] [IGT] kms_addfb_basic: exiting, ret=0
11156 11:05:00.095835 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11157 11:05:00.102372 Using IGT_SRANDOM=1720<8>[ 15.310168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11158 11:05:00.102992 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11160 11:05:00.105590 609500 for randomisation
11161 11:05:00.109022 Opened device: /dev/dri/card0
11162 11:05:00.112257 Starting subtest: no-handle
11163 11:05:00.115482 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11164 11:05:00.122195 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11165 11:05:00.125839 Test requirement: is_intel_device(fd)
11166 11:05:00.132211 Test requirement n<14>[ 15.340137] [IGT] kms_addfb_basic: executing
11167 11:05:00.138833 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11168 11:05:00.145488 Test requirement: is_intel_dev<14>[ 15.352677] [IGT] kms_addfb_basic: starting subtest basic
11169 11:05:00.145871 ice(fd)
11170 11:05:00.155077 No KMS <14>[ 15.359498] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11171 11:05:00.158832 driver or no outputs, pipes: 16, outputs: 0
11172 11:05:00.165546 IGT-Version: 1.28-ga44ebfe (aarch64<14>[ 15.373872] [IGT] kms_addfb_basic: exiting, ret=0
11173 11:05:00.168938 ) (Linux: 6.1.96-cip24 aarch64)
11174 11:05:00.172165 Using IGT_SRANDOM=1720609500 for randomisation
11175 11:05:00.178584 <8>[ 15.386152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11176 11:05:00.178972
11177 11:05:00.179553 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11179 11:05:00.181935 Opened device: /dev/dri/card0
11180 11:05:00.184995 Starting subtest: basic
11181 11:05:00.188290 [1mSubtest basic: SUCCESS (0.000s)[0m
11182 11:05:00.194803 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11183 11:05:00.198393 Test requirement: is_intel_device(fd)
11184 11:05:00.208159 Test requirement not met in function igt_require_in<14>[ 15.415598] [IGT] kms_addfb_basic: executing
11185 11:05:00.211302 tel, file ../lib/drmtest.c:880:
11186 11:05:00.214837 Test requirement: is_intel_device(fd)
11187 11:05:00.221485 No KMS driver or no outp<14>[ 15.428461] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11188 11:05:00.231328 uts, pipes: 16, <14>[ 15.435719] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11189 11:05:00.231755 outputs: 0
11190 11:05:00.237854 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11191 11:05:00.244309 <14>[ 15.450593] [IGT] kms_addfb_basic: exiting, ret=0
11192 11:05:00.247867 Using IGT_SRANDOM=1720609500 for randomisation
11193 11:05:00.251086 Opened device: /dev/dri/card0
11194 11:05:00.257860 S<8>[ 15.461930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11195 11:05:00.258475 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11197 11:05:00.261053 tarting subtest: bad-pitch-0
11198 11:05:00.264133 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11199 11:05:00.270799 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11200 11:05:00.274208 <14>[ 15.482772] [IGT] kms_addfb_basic: executing
11201 11:05:00.274614
11202 11:05:00.277377 Test requirement: is_intel_device(fd)
11203 11:05:00.287394 Test requirement not met in function igt<14>[ 15.494955] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11204 11:05:00.297051 _require_intel, <14>[ 15.502070] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11205 11:05:00.300425 file ../lib/drmtest.c:880:
11206 11:05:00.303804 Test requirement: is_intel_device(fd)
11207 11:05:00.310425 No KMS driver<14>[ 15.516282] [IGT] kms_addfb_basic: exiting, ret=0
11208 11:05:00.313567 or no outputs, pipes: 16, outputs: 0
11209 11:05:00.323781 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 15.529224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11210 11:05:00.324437 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11212 11:05:00.327305 ux: 6.1.96-cip24 aarch64)
11213 11:05:00.330326 Using IGT_SRANDOM=1720609500 for randomisation
11214 11:05:00.333739 Opened device: /dev/dri/card0
11215 11:05:00.334121 Starting subtest: bad-pitch-32
11216 11:05:00.340004 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11217 11:05:00.346712 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11218 11:05:00.349906 Te<14>[ 15.559356] [IGT] kms_addfb_basic: executing
11219 11:05:00.353640 st requirement: is_intel_device(fd)
11220 11:05:00.366728 Test requirement not met in function igt_require_intel, fil<14>[ 15.572102] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11221 11:05:00.373774 e ../lib/drmtest<14>[ 15.579542] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11222 11:05:00.376845 .c:880:
11223 11:05:00.379808 Test requirement: is_intel_device(fd)
11224 11:05:00.386827 No KMS driver or no outputs, pip<14>[ 15.594473] [IGT] kms_addfb_basic: exiting, ret=0
11225 11:05:00.389755 es: 16, outputs: 0
11226 11:05:00.399629 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aa<8>[ 15.606717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11227 11:05:00.400297 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11229 11:05:00.402750 rch64)
11230 11:05:00.406291 Using IGT_SRANDOM=1720609500 for randomisation
11231 11:05:00.409759 Opened device: /dev/dri/card0
11232 11:05:00.410139 Starting subtest: bad-pitch-63
11233 11:05:00.416612 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11234 11:05:00.423031 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11235 11:05:00.429203 Test requirement: is_<14>[ 15.637084] [IGT] kms_addfb_basic: executing
11236 11:05:00.429659 intel_device(fd)
11237 11:05:00.443084 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 15.649627] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11238 11:05:00.446317 880:
11239 11:05:00.452571 Test requi<14>[ 15.657166] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11240 11:05:00.456344 rement: is_intel_device(fd)
11241 11:05:00.459366 No KMS driver or no outputs, pipes: 16, outputs: 0
11242 11:05:00.465923 <14>[ 15.672156] [IGT] kms_addfb_basic: exiting, ret=0
11243 11:05:00.466346
11244 11:05:00.469310 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11245 11:05:00.479260 Using IGT_S<8>[ 15.684576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11246 11:05:00.480039 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11248 11:05:00.482617 RANDOM=1720609500 for randomisation
11249 11:05:00.485400 Opened device: /dev/dri/card0
11250 11:05:00.488998 Starting subtest: bad-pitch-128
11251 11:05:00.492272 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11252 11:05:00.498609 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11253 11:05:00.501849 Test requirement: is_intel_device(fd)
11254 11:05:00.505191 <14>[ 15.715059] [IGT] kms_addfb_basic: executing
11255 11:05:00.505665
11256 11:05:00.515313 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11257 11:05:00.521909 Test requir<14>[ 15.727525] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11258 11:05:00.532006 ement: is_intel_<14>[ 15.735025] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11259 11:05:00.532431 device(fd)
11260 11:05:00.535191 No KMS driver or no outputs, pipes: 16, outputs: 0
11261 11:05:00.541821 IGT-Version: 1.2<14>[ 15.749994] [IGT] kms_addfb_basic: exiting, ret=0
11262 11:05:00.548412 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11263 11:05:00.554933 Using IGT_SRANDOM=1720609500<8>[ 15.761447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11264 11:05:00.555599 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11266 11:05:00.558409 for randomisation
11267 11:05:00.561756 Opened device: /dev/dri/card0
11268 11:05:00.564869 Starting subtest: bad-pitch-256
11269 11:05:00.568316 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11270 11:05:00.574846 Test requir<14>[ 15.781921] [IGT] kms_addfb_basic: executing
11271 11:05:00.581309 ement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11272 11:05:00.588017 Test re<14>[ 15.793170] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11273 11:05:00.594748 quirement: is_in<14>[ 15.800418] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11274 11:05:00.597903 tel_device(fd)
11275 11:05:00.607861 Test requirement not met in function igt_require_intel, file ../<14>[ 15.814828] [IGT] kms_addfb_basic: exiting, ret=0
11276 11:05:00.611321 lib/drmtest.c:880:
11277 11:05:00.614435 Test requirement: is_intel_device(fd)
11278 11:05:00.621318 No KMS driver or no o<8>[ 15.827675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11279 11:05:00.622008 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11281 11:05:00.624801 utputs, pipes: 16, outputs: 0
11282 11:05:00.631050 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11283 11:05:00.634613 Using IGT_SRANDOM=1720609500 for randomisation
11284 11:05:00.640861 Opened device<14>[ 15.848405] [IGT] kms_addfb_basic: executing
11285 11:05:00.641324 : /dev/dri/card0
11286 11:05:00.644149 Starting subtest: bad-pitch-1024
11287 11:05:00.653757 [1mSubtest bad-pitch-1024: <14>[ 15.860131] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11288 11:05:00.663797 SUCCESS (0.000s)<14>[ 15.867461] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11289 11:05:00.663872 [0m
11290 11:05:00.673185 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 15.881769] [IGT] kms_addfb_basic: exiting, ret=0
11291 11:05:00.676487 t.c:880:
11292 11:05:00.680050 Test requirement: is_intel_device(fd)
11293 11:05:00.686659 Test requirement not met in fun<8>[ 15.894307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11294 11:05:00.686903 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11296 11:05:00.693299 ction igt_require_intel, file ../lib/drmtest.c:880:
11297 11:05:00.696515 Test requirement: is_intel_device(fd)
11298 11:05:00.700165 No KMS driver or no outputs, pipes: 16, outputs: 0
11299 11:05:00.706616 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11300 11:05:00.709814 Using IGT_SRANDOM=1720609500 for randomisation
11301 11:05:00.716562 Opened devic<14>[ 15.925119] [IGT] kms_addfb_basic: executing
11302 11:05:00.719571 e: /dev/dri/card0
11303 11:05:00.719644 Starting subtest: bad-pitch-999
11304 11:05:00.732842 [1mSubtest bad-pitch-999: SUCCESS (0.000s)<14>[ 15.937781] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11305 11:05:00.732917 [0m
11306 11:05:00.739619 Test requir<14>[ 15.945342] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11307 11:05:00.745993 ement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11308 11:05:00.752764 Test re<14>[ 15.960665] [IGT] kms_addfb_basic: exiting, ret=0
11309 11:05:00.756267 quirement: is_intel_device(fd)
11310 11:05:00.765917 Test requirement not met in function igt_require<8>[ 15.972878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11311 11:05:00.766162 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11313 11:05:00.769380 _intel, file ../lib/drmtest.c:880:
11314 11:05:00.772447 Test requirement: is_intel_device(fd)
11315 11:05:00.779349 No KMS driver or no outputs, pipes: 16, outputs: 0
11316 11:05:00.782567 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11317 11:05:00.789030 Using IGT_SRANDOM=1720609500 for randomisation
11318 11:05:00.795736 Opened device: /dev/dri/card0<14>[ 16.003551] [IGT] kms_addfb_basic: executing
11319 11:05:00.795810
11320 11:05:00.798806 Starting subtest: bad-pitch-65536
11321 11:05:00.802489 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11322 11:05:00.812308 Test requirement not met<14>[ 16.017926] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11323 11:05:00.822410 in function igt<14>[ 16.025528] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11324 11:05:00.825465 _require_intel, file ../lib/drmtest.c:880:
11325 11:05:00.831830 Test requirement: is<14>[ 16.039086] [IGT] kms_addfb_basic: exiting, ret=0
11326 11:05:00.831904 _intel_device(fd)
11327 11:05:00.845239 Test requirement not met in function igt_require_intel, file <8>[ 16.052128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11328 11:05:00.845482 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11330 11:05:00.848401 ../lib/drmtest.c:880:
11331 11:05:00.851662 Test requirement: is_intel_device(fd)
11332 11:05:00.855103 No KMS driver or no outputs, pipes: 16, outputs: 0
11333 11:05:00.864769 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<14>[ 16.072574] [IGT] kms_addfb_basic: executing
11334 11:05:00.868414 .1.96-cip24 aarch64)
11335 11:05:00.871567 Using IGT_SRANDOM=1720609500 for randomisation
11336 11:05:00.881233 Opened device: /dev/dri/ca<14>[ 16.086645] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11337 11:05:00.881343 rd0
11338 11:05:00.888120 Starting su<14>[ 16.093772] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11339 11:05:00.891399 btest: invalid-get-prop-any
11340 11:05:00.897944 [1mSubtest invalid<14>[ 16.106490] [IGT] kms_addfb_basic: exiting, ret=0
11341 11:05:00.901062 -get-prop-any: SUCCESS (0.000s)[0m
11342 11:05:00.911300 Test requirement not met in function igt_re<8>[ 16.118480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11343 11:05:00.911542 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11345 11:05:00.914575 quire_intel, file ../lib/drmtest.c:880:
11346 11:05:00.917887 Test requirement: is_intel_device(fd)
11347 11:05:00.931210 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 16.139289] [IGT] kms_addfb_basic: executing
11348 11:05:00.931289 0:
11349 11:05:00.934332 Test requirement: is_intel_device(fd)
11350 11:05:00.940864 No KMS driver or no outputs, pipes: 16, outputs: 0
11351 11:05:00.947481 I<14>[ 16.153217] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11352 11:05:00.954177 GT-Version: 1.28<14>[ 16.160375] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11353 11:05:00.964173 -ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64<14>[ 16.173496] [IGT] kms_addfb_basic: exiting, ret=0
11354 11:05:00.964249 )
11355 11:05:00.970764 Using IGT_SRANDOM=1720609500 for randomisation
11356 11:05:00.980534 Opened device: /dev/dri/card0<8>[ 16.185407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11357 11:05:00.980609
11358 11:05:00.980835 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11360 11:05:00.983977 Starting subtest: invalid-get-prop
11361 11:05:00.987242 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11362 11:05:00.997025 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 16.206730] [IGT] kms_addfb_basic: executing
11363 11:05:01.000501 mtest.c:880:
11364 11:05:01.003841 Test requirement: is_intel_device(fd)
11365 11:05:01.013501 Test requirement not met in function igt_re<14>[ 16.220213] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11366 11:05:01.023498 quire_intel, fil<14>[ 16.227258] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11367 11:05:01.023573 e ../lib/drmtest.c:880:
11368 11:05:01.030114 Test requirement: is_in<14>[ 16.239914] [IGT] kms_addfb_basic: exiting, ret=0
11369 11:05:01.033353 tel_device(fd)
11370 11:05:01.036828 No KMS driver or no outputs, pipes: 16, outputs: 0
11371 11:05:01.046631 IGT-Version:<8>[ 16.251654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11372 11:05:01.046873 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11374 11:05:01.049919 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11375 11:05:01.053237 Using IGT_SRANDOM=1720609500 for randomisation
11376 11:05:01.056722 Opened device: /dev/dri/card0
11377 11:05:01.059791 Starting subtest: invalid-set-prop-any
11378 11:05:01.066356 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11379 11:05:01.073108 Test requirement not met in function igt_<14>[ 16.282651] [IGT] kms_addfb_basic: executing
11380 11:05:01.076305 require_intel, file ../lib/drmtest.c:880:
11381 11:05:01.079997 Test requirement: is_intel_device(fd)
11382 11:05:01.092808 Test requirement not met in function igt_require_intel, file .<14>[ 16.299514] [IGT] kms_addfb_basic: starting subtest master-rmfb
11383 11:05:01.102606 ./lib/drmtest.c:<14>[ 16.306838] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11384 11:05:01.102681 880:
11385 11:05:01.109453 Test requirement: is_intel<14>[ 16.317533] [IGT] kms_addfb_basic: exiting, ret=0
11386 11:05:01.109527 _device(fd)
11387 11:05:01.116272 No KMS driver or no outputs, pipes: 16, outputs: 0
11388 11:05:01.122686 IGT-Version: 1.<8>[ 16.329554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11389 11:05:01.122928 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11391 11:05:01.129129 28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11392 11:05:01.132989 Using IGT_SRANDOM=1720609500 for randomisation
11393 11:05:01.135774 Opened device: /dev/dri/card0
11394 11:05:01.139009 Starting subtest: invalid-set-prop
11395 11:05:01.142438 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11396 11:05:01.152478 Test requirement not met in function igt_require_int<14>[ 16.359801] [IGT] kms_addfb_basic: executing
11397 11:05:01.155748 el, file ../lib/drmtest.c:880:
11398 11:05:01.158878 Test requirement: is_intel_device(fd)
11399 11:05:01.165678 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11400 11:05:01.172226 Test <14>[ 16.378703] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11401 11:05:01.182145 requirement: is_<14>[ 16.386588] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11402 11:05:01.188830 intel_device(fd)<14>[ 16.396438] [IGT] kms_addfb_basic: exiting, ret=0
11403 11:05:01.189011
11404 11:05:01.192362 No KMS driver or no outputs, pipes: 16, outputs: 0
11405 11:05:01.202327 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11407 11:05:01.205560 IGT-Version: 1.28-ga44ebfe<8>[ 16.409083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11408 11:05:01.208570 (aarch64) (Linux: 6.1.96-cip24 aarch64)
11409 11:05:01.211915 Using IGT_SRANDOM=1720609501 for randomisation
11410 11:05:01.215290 Opened device: /dev/dri/card0
11411 11:05:01.218681 Starting subtest: master-rmfb
11412 11:05:01.222418 [1mSubt<14>[ 16.430035] [IGT] kms_addfb_basic: executing
11413 11:05:01.224973 est master-rmfb: SUCCESS (0.000s)[0m
11414 11:05:01.232041 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11415 11:05:01.242224 Test requirement: is_<14>[ 16.447806] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11416 11:05:01.245169 intel_device(fd)
11417 11:05:01.255293 Test requirement not met in function igt_requi<14>[ 16.461089] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11418 11:05:01.261669 re_intel, file .<14>[ 16.469271] [IGT] kms_addfb_basic: exiting, ret=98
11419 11:05:01.264933 ./lib/drmtest.c:880:
11420 11:05:01.268331 Test requirement: is_intel_device(fd)
11421 11:05:01.274727 No KMS driver or no<8>[ 16.481686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11422 11:05:01.275096 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11424 11:05:01.278260 outputs, pipes: 16, outputs: 0
11425 11:05:01.284721 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11426 11:05:01.287921 Using IGT_SRANDOM=1720609501 for randomisation
11427 11:05:01.294497 Opened devi<14>[ 16.503202] [IGT] kms_addfb_basic: executing
11428 11:05:01.297616 ce: /dev/dri/card0
11429 11:05:01.301256 Starting subtest: addfb25-modifier-no-flag
11430 11:05:01.304487 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11431 11:05:01.314243 Test requirement not<14>[ 16.520987] [IGT] kms_addfb_basic: exiting, ret=77
11432 11:05:01.317582 met in function igt_require_intel, file ../lib/drmtest.c:880:
11433 11:05:01.327776 Test requirement<8>[ 16.533013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11434 11:05:01.328146 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11436 11:05:01.331115 : is_intel_device(fd)
11437 11:05:01.337572 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11438 11:05:01.340827 Test requirement: is_intel_device(fd)
11439 11:05:01.347758 No KMS driver <14>[ 16.555795] [IGT] kms_addfb_basic: executing
11440 11:05:01.351033 or no outputs, pipes: 16, outputs: 0
11441 11:05:01.357659 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11442 11:05:01.364565 Using IGT_SRANDOM=1720609501 for rando<14>[ 16.572892] [IGT] kms_addfb_basic: exiting, ret=77
11443 11:05:01.365064 misation
11444 11:05:01.367567 Opened device: /dev/dri/card0
11445 11:05:01.371059 Starting subtest: addfb25-bad-modifier
11446 11:05:01.380817 <8>[ 16.584912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11447 11:05:01.381277
11448 11:05:01.381955 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11450 11:05:01.390891 (kms_addfb_basic:428) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11451 11:05:01.407215 (kms_addfb_basic:428) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct<14>[ 16.616255] [IGT] kms_addfb_basic: executing
11452 11:05:01.414239 drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11453 11:05:01.417571 (kms_addfb_basic:428) CRITICAL: error: 0 != -1
11454 11:05:01.418262 Stack trace:
11455 11:05:01.423835 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11456 11:05:01.427047 #1 [<unknow<14>[ 16.635432] [IGT] kms_addfb_basic: exiting, ret=77
11457 11:05:01.430415 n>+0xd0944358]
11458 11:05:01.433574 #2 [<unknown>+0xd0945fbc]
11459 11:05:01.433970 #3 [<unknown>+0xd094156c]
11460 11:05:01.446956 #4 [__libc_init_firs<8>[ 16.648880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11461 11:05:01.447352 t+0x80]
11462 11:05:01.447987 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11464 11:05:01.450426 #5 [__libc_start_main+0x98]
11465 11:05:01.450874 #6 [<unknown>+0xd09415b0]
11466 11:05:01.453571 Subtest addfb25-bad-modifier failed.
11467 11:05:01.457253 **** DEBUG ****
11468 11:05:01.463321 (kms_addfb_basic:428) ioctl_wrappers<14>[ 16.671733] [IGT] kms_addfb_basic: executing
11469 11:05:01.470163 -DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11470 11:05:01.483152 (kms_addfb_basic:428) CRITICAL: Test assertion failure function addfb25_tests, file .<14>[ 16.689757] [IGT] kms_addfb_basic: exiting, ret=77
11471 11:05:01.483703 ./tests/kms_addfb_basic.c:714:
11472 11:05:01.496613 (kms_addfb_basic:428) CRITICAL: Failed assertion<8>[ 16.701742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11473 11:05:01.497379 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11475 11:05:01.509800 : igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11476 11:05:01.512937 (kms_addfb_basic:428) CRITICAL: error: 0 != -1
11477 11:05:01.519504 (kms_addfb_basic:428) igt_core-INFO: Stack trace:
11478 11:05:01.526277 (kms_addfb_basi<14>[ 16.733042] [IGT] kms_addfb_basic: executing
11479 11:05:01.529337 c:428) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11480 11:05:01.536053 (kms_addfb_basic:428) igt_core-INFO: #1 [<unknown>+0xd0944358]
11481 11:05:01.545891 (kms_addfb_basic:428) igt_core-INFO: <14>[ 16.752379] [IGT] kms_addfb_basic: exiting, ret=77
11482 11:05:01.549111 #2 [<unknown>+0xd0945fbc]
11483 11:05:01.552298 (kms_addfb_basic:428) igt_core-INFO: #3 [<unknown>+0xd094156c]
11484 11:05:01.562429 (km<8>[ 16.765908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11485 11:05:01.563077 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11487 11:05:01.568975 s_addfb_basic:428) igt_core-INFO: #4 [__libc_init_first+0x80]
11488 11:05:01.572191 (kms_addfb_basic:428) igt_core-INFO: #5 [__libc_start_main+0x98]
11489 11:05:01.578969 (kms_addfb_basic:428) igt_core-INFO: #6 [<unknown>+0xd09415b0]
11490 11:05:01.582065 **** END ****
11491 11:05:01.585731 [1mSubtest addfb25-bad-modifier: FAIL (0.005s)[0m
11492 11:05:01.589023 Tes<14>[ 16.798297] [IGT] kms_addfb_basic: executing
11493 11:05:01.598497 t requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11494 11:05:01.602068 Test requirement: is_intel_device(fd)
11495 11:05:01.611731 Test requirement not met in function igt_require_intel, <14>[ 16.817542] [IGT] kms_addfb_basic: exiting, ret=77
11496 11:05:01.612161 file ../lib/drmtest.c:880:
11497 11:05:01.615054 Test requirement: is_intel_device(fd)
11498 11:05:01.624952 No KMS driver<8>[ 16.830602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11499 11:05:01.625764 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11501 11:05:01.628228 or no outputs, pipes: 16, outputs: 0
11502 11:05:01.634756 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11503 11:05:01.638489 Using IGT_SRANDOM=1720609501 for randomisation
11504 11:05:01.641625 Opened device: /dev/dri/card0
11505 11:05:01.648485 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11506 11:05:01.654821 Te<14>[ 16.861431] [IGT] kms_addfb_basic: executing
11507 11:05:01.657872 st requirement: is_intel_device(fd)
11508 11:05:01.661258 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11509 11:05:01.674747 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 16.880828] [IGT] kms_addfb_basic: exiting, ret=77
11510 11:05:01.675255 .c:880:
11511 11:05:01.677863 Test requirement: is_intel_device(fd)
11512 11:05:01.687991 No KMS driver or no outputs, pip<8>[ 16.893949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11513 11:05:01.688755 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11515 11:05:01.691271 es: 16, outputs: 0
11516 11:05:01.697653 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11517 11:05:01.700858 Using IGT_SRANDOM=1720609501 for randomisation
11518 11:05:01.704360 Opened device: /dev/dri/card0
11519 11:05:01.710963 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11520 11:05:01.717517 Test requirement: is_<14>[ 16.924856] [IGT] kms_addfb_basic: executing
11521 11:05:01.717940 intel_device(fd)
11522 11:05:01.724378 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11523 11:05:01.730642 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11524 11:05:01.737190 Test requirement: i<14>[ 16.944132] [IGT] kms_addfb_basic: exiting, ret=77
11525 11:05:01.737664 s_intel_device(fd)
11526 11:05:01.744164 No KMS driver or no outputs, pipes: 16, outputs: 0
11527 11:05:01.750536 IGT-Version: 1.28-ga44eb<8>[ 16.957544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11528 11:05:01.751287 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11530 11:05:01.757072 fe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11531 11:05:01.760274 Using IGT_SRANDOM=1720609501 for randomisation
11532 11:05:01.763591 Opened device: /dev/dri/card0
11533 11:05:01.770257 Test requirement not met in function <14>[ 16.979092] [IGT] kms_addfb_basic: executing
11534 11:05:01.773535 igt_require_intel, file ../lib/drmtest.c:880:
11535 11:05:01.777426 Test requirement: is_intel_device(fd)
11536 11:05:01.787107 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000<14>[ 16.996222] [IGT] kms_addfb_basic: exiting, ret=77
11537 11:05:01.790091 s)[0m
11538 11:05:01.803863 Test requirement not met in function igt_require_intel, file ../lib/drmt<8>[ 17.008717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11539 11:05:01.804363 est.c:880:
11540 11:05:01.804943 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11542 11:05:01.806434 Test requirement: is_intel_device(fd)
11543 11:05:01.809844 No KMS driver or no outputs, pipes: 16, outputs: 0
11544 11:05:01.819731 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24<14>[ 17.028903] [IGT] kms_addfb_basic: executing
11545 11:05:01.823293 aarch64)
11546 11:05:01.826524 Using IGT_SRANDOM=1720609501 for randomisation
11547 11:05:01.829753 Opened device: /dev/dri/card0
11548 11:05:01.839853 Test requirement not met in function igt_require_intel<14>[ 17.046445] [IGT] kms_addfb_basic: exiting, ret=77
11549 11:05:01.840221 , file ../lib/drmtest.c:880:
11550 11:05:01.842799 Test requirement: is_intel_device(fd)
11551 11:05:01.852954 Test requir<8>[ 17.058493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11552 11:05:01.853593 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11554 11:05:01.859448 ement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11555 11:05:01.862658 Test requirement: is_intel_device(fd)
11556 11:05:01.869383 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)<14>[ 17.078995] [IGT] kms_addfb_basic: executing
11557 11:05:01.872720 [0m
11558 11:05:01.876233 No KMS driver or no outputs, pipes: 16, outputs: 0
11559 11:05:01.882944 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11560 11:05:01.889694 Using IGT_SRANDOM=1<14>[ 17.096372] [IGT] kms_addfb_basic: exiting, ret=77
11561 11:05:01.892516 720609501 for randomisation
11562 11:05:01.892940 Opened device: /dev/dri/card0
11563 11:05:01.902914 Test requirement not<8>[ 17.108708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11564 11:05:01.903665 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11566 11:05:01.908877 met in function igt_require_intel, file ../lib/drmtest.c:880:
11567 11:05:01.912304 Test requirement: is_intel_device(fd)
11568 11:05:01.922198 Test requirement not met in function igt_require_intel, file ../lib/drmte<14>[ 17.129848] [IGT] kms_addfb_basic: executing
11569 11:05:01.922703 st.c:880:
11570 11:05:01.925518 Test requirement: is_intel_device(fd)
11571 11:05:01.932146 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11572 11:05:01.938834 No KMS driver or no outputs, pipes: <14>[ 17.147895] [IGT] kms_addfb_basic: exiting, ret=77
11573 11:05:01.941962 16, outputs: 0
11574 11:05:01.952604 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11576 11:05:01.955402 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<8>[ 17.159827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11577 11:05:01.955828 4)
11578 11:05:01.958567 Using IGT_SRANDOM=1720609501 for randomisation
11579 11:05:01.961809 Opened device: /dev/dri/card0
11580 11:05:01.971849 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<14>[ 17.179866] [IGT] kms_addfb_basic: executing
11581 11:05:01.972274 :880:
11582 11:05:01.975201 Test requirement: is_intel_device(fd)
11583 11:05:01.984974 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11584 11:05:01.991798 Test requireme<14>[ 17.197636] [IGT] kms_addfb_basic: exiting, ret=77
11585 11:05:01.992307 nt: is_intel_device(fd)
11586 11:05:01.998391 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11587 11:05:02.004719 No <8>[ 17.209843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11588 11:05:02.005531 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11590 11:05:02.008495 KMS driver or no outputs, pipes: 16, outputs: 0
11591 11:05:02.014462 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11592 11:05:02.017838 Using IGT_SRANDOM=1720609501 for randomisation
11593 11:05:02.021272 Opened device: /dev/dri/card0
11594 11:05:02.034830 Test requirement not met in function igt_require_intel, file ../lib/drmtest.<14>[ 17.241316] [IGT] kms_addfb_basic: executing
11595 11:05:02.035332 c:880:
11596 11:05:02.037549 Test requirement: is_intel_device(fd)
11597 11:05:02.044477 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11598 11:05:02.047922 Test requirement: is_intel_device(fd)
11599 11:05:02.054091 [1mSu<14>[ 17.260833] [IGT] kms_addfb_basic: exiting, ret=77
11600 11:05:02.057839 btest basic-y-tiled-legacy: SKIP (0.000s)[0m
11601 11:05:02.060674 No KMS driver or no outputs, pipes: 16, outputs: 0
11602 11:05:02.070862 IGT-Version: <8>[ 17.276294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11603 11:05:02.071534 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11605 11:05:02.077437 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11606 11:05:02.080738 Using IGT_SRANDOM=1720609501 for randomisation
11607 11:05:02.084490 Opened device: /dev/dri/card0
11608 11:05:02.090571 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11609 11:05:02.093923 Test requirement: is_intel_device(fd)
11610 11:05:02.100296 Test requirement not met in fun<14>[ 17.308711] [IGT] kms_addfb_basic: executing
11611 11:05:02.106803 ction igt_require_intel, file ../lib/drmtest.c:880:
11612 11:05:02.110316 Test requirement: is_intel_device(fd)
11613 11:05:02.113349 No KMS driver or no outputs, pipes: 16, outputs: 0
11614 11:05:02.120421 [1mSubtest size-max: SKIP (0.00<14>[ 17.328555] [IGT] kms_addfb_basic: exiting, ret=77
11615 11:05:02.123500 0s)[0m
11616 11:05:02.126865 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11617 11:05:02.136735 Usi<8>[ 17.341095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11618 11:05:02.137408 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11620 11:05:02.139858 ng IGT_SRANDOM=1720609501 for randomisation
11621 11:05:02.143630 Opened device: /dev/dri/card0
11622 11:05:02.153134 Test requirement not met in function igt_require_intel, file ../lib/<14>[ 17.362351] [IGT] kms_addfb_basic: executing
11623 11:05:02.156739 drmtest.c:880:
11624 11:05:02.159964 Test requirement: is_intel_device(fd)
11625 11:05:02.166846 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11626 11:05:02.169748 Test <14>[ 17.379216] [IGT] kms_addfb_basic: exiting, ret=77
11627 11:05:02.172856 requirement: is_intel_device(fd)
11628 11:05:02.186455 No KMS driver or no outputs, pipes: 16, output<8>[ 17.391518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11629 11:05:02.186849 s: 0
11630 11:05:02.187378 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11632 11:05:02.189564 [1mSubtest too-wide: SKIP (0.000s)[0m
11633 11:05:02.196118 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11634 11:05:02.199400 Using IGT_SRANDOM=1720609501 for randomisation
11635 11:05:02.202668 Opened device: /dev/dri/card0
11636 11:05:02.215853 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 17.423221] [IGT] kms_addfb_basic: executing
11637 11:05:02.216238 880:
11638 11:05:02.219020 Test requirement: is_intel_device(fd)
11639 11:05:02.226052 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11640 11:05:02.228889 Test requirement: is_intel_device(fd)
11641 11:05:02.235781 No KMS d<14>[ 17.442564] [IGT] kms_addfb_basic: exiting, ret=77
11642 11:05:02.238896 river or no outputs, pipes: 16, outputs: 0
11643 11:05:02.248733 [1mSubtest too-high: SKIP (0.000s)<8>[ 17.455557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11644 11:05:02.249115 [0m
11645 11:05:02.249679 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11647 11:05:02.255515 IGT-Version: 1.28-ga44ebfe <8>[ 17.464449] <LAVA_SIGNAL_TESTSET STOP>
11648 11:05:02.256148 Received signal: <TESTSET> STOP
11649 11:05:02.256471 Closing test_set kms_addfb_basic
11650 11:05:02.259068 (aarch64) (Linux: 6.1.96-cip24 aarch64)
11651 11:05:02.265320 Using IGT_SRANDOM=1720609501 for randomisation
11652 11:05:02.265702 Opened device: /dev/dri/card0
11653 11:05:02.275303 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11654 11:05:02.278369 Test requirement: is_intel_device(fd)
11655 11:05:02.288679 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<8>[ 17.496680] <LAVA_SIGNAL_TESTSET START kms_atomic>
11656 11:05:02.289156 :880:
11657 11:05:02.289748 Received signal: <TESTSET> START kms_atomic
11658 11:05:02.290066 Starting test_set kms_atomic
11659 11:05:02.291911 Test requirement: is_intel_device(fd)
11660 11:05:02.298331 No KMS driver or no outputs, pipes: 16, outputs: 0
11661 11:05:02.301916 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11662 11:05:02.308334 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11663 11:05:02.314914 Using IGT_SRANDOM=1720609501 for randomisatio<14>[ 17.524687] [IGT] kms_atomic: executing
11664 11:05:02.315293 n
11665 11:05:02.321742 Opened device<14>[ 17.529920] [IGT] kms_atomic: exiting, ret=77
11666 11:05:02.322122 : /dev/dri/card0
11667 11:05:02.335254 Test requirement not met in function igt_require_intel, file .<8>[ 17.541542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11668 11:05:02.336008 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11670 11:05:02.338359 ./lib/drmtest.c:880:
11671 11:05:02.341968 Test requirement: is_intel_device(fd)
11672 11:05:02.348479 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11673 11:05:02.355023 Test requiremen<14>[ 17.563111] [IGT] kms_atomic: executing
11674 11:05:02.361323 t: is_intel_devi<14>[ 17.568651] [IGT] kms_atomic: exiting, ret=77
11675 11:05:02.361767 ce(fd)
11676 11:05:02.364656 No KMS driver or no outputs, pipes: 16, outputs: 0
11677 11:05:02.377904 [1mSubtest small-bo: SKIP (0.000s)<8>[ 17.581579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11678 11:05:02.378391 [0m
11679 11:05:02.378957 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11681 11:05:02.384260 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11682 11:05:02.388439 Using IGT_SRANDOM=1720609501 for randomisation
11683 11:05:02.390971 Opened device: /dev/dri/card0
11684 11:05:02.394363 Test req<14>[ 17.603769] [IGT] kms_atomic: executing
11685 11:05:02.400936 uirement not met<14>[ 17.609005] [IGT] kms_atomic: exiting, ret=77
11686 11:05:02.407686 in function igt_require_intel, file ../lib/drmtest.c:880:
11687 11:05:02.417541 Test requirement: is<8>[ 17.620910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11688 11:05:02.418029 _intel_device(fd)
11689 11:05:02.418602 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11691 11:05:02.427695 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11692 11:05:02.430594 Test requirement: is_intel_device(fd)
11693 11:05:02.433876 No KMS driver or no outputs, pipes: 16, outputs: 0
11694 11:05:02.440255 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11695 11:05:02.443639 IGT-Version: 1.28-g<14>[ 17.653807] [IGT] kms_atomic: executing
11696 11:05:02.450242 a44ebfe (aarch64<14>[ 17.659163] [IGT] kms_atomic: exiting, ret=77
11697 11:05:02.453675 ) (Linux: 6.1.96-cip24 aarch64)
11698 11:05:02.457109 Using IGT_SRANDOM=1720609502 for randomisation
11699 11:05:02.460342 Opened device: /dev/dri/card0
11700 11:05:02.467015 <8>[ 17.673886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11701 11:05:02.467728 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11703 11:05:02.476713 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11704 11:05:02.480168 Test requirement: is_intel_device(fd)
11705 11:05:02.486912 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11706 11:05:02.489789 Test requirement: is_intel_device(fd)
11707 11:05:02.496655 No KMS driver or no outputs, pipes: 16, ou<14>[ 17.706126] [IGT] kms_atomic: executing
11708 11:05:02.499950 tputs: 0
11709 11:05:02.503158 [1mSu<14>[ 17.711921] [IGT] kms_atomic: exiting, ret=77
11710 11:05:02.506561 btest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11711 11:05:02.516336 IGT-Version: 1.<8>[ 17.722636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11712 11:05:02.517043 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11714 11:05:02.520116 28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11715 11:05:02.526434 Using IGT_SRANDOM=1720609502 for randomisation
11716 11:05:02.526851 Opened device: /dev/dri/card0
11717 11:05:02.536429 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11718 11:05:02.539613 Test requirement: is_intel_device(fd)
11719 11:05:02.543088 Test requirement <14>[ 17.752827] [IGT] kms_atomic: executing
11720 11:05:02.549486 not met in funct<14>[ 17.758108] [IGT] kms_atomic: exiting, ret=77
11721 11:05:02.553010 ion igt_require_intel, file ../lib/drmtest.c:880:
11722 11:05:02.562784 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11724 11:05:02.565787 Test requirement: is_intel_de<8>[ 17.769673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11725 11:05:02.566378 vice(fd)
11726 11:05:02.569175 No KMS driver or no outputs, pipes: 16, outputs: 0
11727 11:05:02.575839 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11728 11:05:02.579261 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11729 11:05:02.585640 Using IGT_SRANDOM=1720609502 for randomisation
11730 11:05:02.588837 Opened device: /dev/dri/card0
11731 11:05:02.592516 Test re<14>[ 17.800881] [IGT] kms_atomic: executing
11732 11:05:02.598901 quirement not me<14>[ 17.806469] [IGT] kms_atomic: exiting, ret=77
11733 11:05:02.602186 t in function igt_require_intel, file ../lib/drmtest.c:880:
11734 11:05:02.612334 Test requirement: i<8>[ 17.817753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11735 11:05:02.613117 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11737 11:05:02.615642 s_intel_device(fd)
11738 11:05:02.622438 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11739 11:05:02.625187 Test requirement: is_intel_device(fd)
11740 11:05:02.629222 No KMS driver or no outputs, pipes: 16, outputs: 0
11741 11:05:02.635138 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11742 11:05:02.642032 IGT-Version: 1.2<14>[ 17.849844] [IGT] kms_atomic: executing
11743 11:05:02.645330 8-ga44ebfe (aarc<14>[ 17.855119] [IGT] kms_atomic: exiting, ret=77
11744 11:05:02.648602 h64) (Linux: 6.1.96-cip24 aarch64)
11745 11:05:02.655103 Using IGT_SRANDOM=1720609502 for randomisation
11746 11:05:02.661827 Opened devic<8>[ 17.868016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11747 11:05:02.662443 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11749 11:05:02.664786 e: /dev/dri/card0
11750 11:05:02.671648 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11751 11:05:02.674808 Test requirement: is_intel_device(fd)
11752 11:05:02.681706 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11753 11:05:02.684754 Test requirement: is_intel_device(fd)
11754 11:05:02.691337 No KMS driver or no out<14>[ 17.901160] [IGT] kms_atomic: executing
11755 11:05:02.697940 puts, pipes: 16,<14>[ 17.906801] [IGT] kms_atomic: exiting, ret=77
11756 11:05:02.701108 outputs: 0
11757 11:05:02.704527 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11758 11:05:02.714636 IGT-Version: 1.28-g<8>[ 17.918078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11759 11:05:02.715306 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11761 11:05:02.717808 a44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11762 11:05:02.721348 Using IGT_SRANDOM=1720609502 for randomisation
11763 11:05:02.724402 Opened device: /dev/dri/card0
11764 11:05:02.731074 No KMS driver or no outputs, pip<14>[ 17.939689] [IGT] kms_atomic: executing
11765 11:05:02.737637 es: 16, outputs:<14>[ 17.945380] [IGT] kms_atomic: exiting, ret=77
11766 11:05:02.738052 0
11767 11:05:02.740811 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11768 11:05:02.750853 IGT-Version: 1.28-ga44e<8>[ 17.957353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11769 11:05:02.751475 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11771 11:05:02.757625 bfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11772 11:05:02.761114 Using IGT_SRANDOM=1720609502 for randomisation
11773 11:05:02.764140 Opened device: /dev/dri/card0
11774 11:05:02.767636 No KMS driver or no outputs, pipes: 16, outputs: 0
11775 11:05:02.773827 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11776 11:05:02.780819 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 17.989316] [IGT] kms_atomic: executing
11777 11:05:02.787819 : 6.1.96-cip24 a<14>[ 17.994737] [IGT] kms_atomic: exiting, ret=77
11778 11:05:02.788208 arch64)
11779 11:05:02.790930 Using IGT_SRANDOM=1720609502 for randomisation
11780 11:05:02.793984 Opened device: /dev/dri/card0
11781 11:05:02.804002 No KMS driver or no outp<8>[ 18.009600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11782 11:05:02.804689 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11784 11:05:02.807268 uts, pipes: 16, outputs: 0
11785 11:05:02.813921 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11786 11:05:02.817312 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11787 11:05:02.823833 Using IGT_SRANDOM=1720609502 for randomisation
11788 11:05:02.824313 Opened device: /dev/dri/card0
11789 11:05:02.833944 No KMS driver or no outputs, pipes: 16, output<14>[ 18.041543] [IGT] kms_atomic: executing
11790 11:05:02.834451 s: 0
11791 11:05:02.840986 [1mSubtes<14>[ 18.047526] [IGT] kms_atomic: exiting, ret=77
11792 11:05:02.843509 t plane-immutable-zpos: SKIP (0.000s)[0m
11793 11:05:02.853559 IGT-Version: 1.28-ga44ebfe (aarch64) <8>[ 18.058551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
11794 11:05:02.854297 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
11796 11:05:02.856719 (Linux: 6.1.96-cip24 aarch64)
11797 11:05:02.860440 U<8>[ 18.069180] <LAVA_SIGNAL_TESTSET STOP>
11798 11:05:02.861172 Received signal: <TESTSET> STOP
11799 11:05:02.861541 Closing test_set kms_atomic
11800 11:05:02.863521 sing IGT_SRANDOM=1720609502 for randomisation
11801 11:05:02.866806 Opened device: /dev/dri/card0
11802 11:05:02.873462 No KMS driver or no outputs, pipes: 16, outputs: 0
11803 11:05:02.876856 [1mSubtest test-only: SKIP (0.000s)[0m
11804 11:05:02.879922 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11805 11:05:02.886608 Using IGT_SRANDOM=1720609502 for randomisation
11806 11:05:02.889818 Opened device: /dev/dri/card0
11807 11:05:02.893005 N<8>[ 18.101173] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11808 11:05:02.893667 Received signal: <TESTSET> START kms_flip_event_leak
11809 11:05:02.894022 Starting test_set kms_flip_event_leak
11810 11:05:02.900032 o KMS driver or no outputs, pipes: 16, outputs: 0
11811 11:05:02.903230 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11812 11:05:02.909644 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11813 11:05:02.913267 Using IGT_SRANDOM=1720609502 for randomisation
11814 11:05:02.916350 Opened device: /dev/dri/card0
11815 11:05:02.923439 No KMS<14>[ 18.130000] [IGT] kms_flip_event_leak: executing
11816 11:05:02.929844 driver or no ou<14>[ 18.135836] [IGT] kms_flip_event_leak: exiting, ret=77
11817 11:05:02.933223 tputs, pipes: 16, outputs: 0
11818 11:05:02.942623 [1mSubtest plane-invalid-params: SKIP (0.000s)[0<8>[ 18.148645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11819 11:05:02.943110 m
11820 11:05:02.943682 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11822 11:05:02.949894 IGT-Version: 1.28-ga44ebfe (a<8>[ 18.157043] <LAVA_SIGNAL_TESTSET STOP>
11823 11:05:02.950633 Received signal: <TESTSET> STOP
11824 11:05:02.950975 Closing test_set kms_flip_event_leak
11825 11:05:02.953104 arch64) (Linux: 6.1.96-cip24 aarch64)
11826 11:05:02.956011 Using IGT_SRANDOM=1720609502 for randomisation
11827 11:05:02.959503 Opened device: /dev/dri/card0
11828 11:05:02.962211 No KMS driver or no outputs, pipes: 16, outputs: 0
11829 11:05:02.968921 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11830 11:05:02.975777 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11831 11:05:02.982246 Using IGT_SRANDOM=17206<8>[ 18.189356] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11832 11:05:02.982666 09502 for randomisation
11833 11:05:02.983237 Received signal: <TESTSET> START kms_prop_blob
11834 11:05:02.983582 Starting test_set kms_prop_blob
11835 11:05:02.985858 Opened device: /dev/dri/card0
11836 11:05:02.992161 No KMS driver or no outputs, pipes: 16, outputs: 0
11837 11:05:02.995427 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11838 11:05:02.998635 <14>[ 18.208143] [IGT] kms_prop_blob: executing
11839 11:05:03.008606 IGT-Version: 1.2<14>[ 18.213973] [IGT] kms_prop_blob: starting subtest basic
11840 11:05:03.015286 8-ga44ebfe (aarc<14>[ 18.220704] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
11841 11:05:03.022268 h64) (Linux: 6.1<14>[ 18.228476] [IGT] kms_prop_blob: exiting, ret=0
11842 11:05:03.022671 .96-cip24 aarch64)
11843 11:05:03.028114 Using IGT_SRANDOM=1720609502 for randomisation
11844 11:05:03.035070 Opened devic<8>[ 18.241127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11845 11:05:03.035453 e: /dev/dri/card0
11846 11:05:03.035984 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11848 11:05:03.041928 No KMS driver or no outputs, pipes: 16, outputs: 0
11849 11:05:03.045065 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11850 11:05:03.051570 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11851 11:05:03.054761 Using IGT_SRANDOM=1720609502 for randomisation
11852 11:05:03.061281 Opened device: /dev/dri/car<14>[ 18.271149] [IGT] kms_prop_blob: executing
11853 11:05:03.061665 d0
11854 11:05:03.071345 No KMS drive<14>[ 18.276722] [IGT] kms_prop_blob: starting subtest blob-prop-core
11855 11:05:03.077987 r or no outputs,<14>[ 18.283961] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
11856 11:05:03.084511 pipes: 16, outp<14>[ 18.292571] [IGT] kms_prop_blob: exiting, ret=0
11857 11:05:03.084892 uts: 0
11858 11:05:03.091187 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11859 11:05:03.097677 IGT-Version: 1.28-<8>[ 18.305573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11860 11:05:03.098305 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11862 11:05:03.104257 ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11863 11:05:03.107692 Using IGT_SRANDOM=1720609502 for randomisation
11864 11:05:03.110792 Opened device: /dev/dri/card0
11865 11:05:03.114645 No KMS driver or no outputs, pipes: 16, outputs: 0
11866 11:05:03.121062 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
11867 11:05:03.127647 IGT-Version: 1.28-ga44ebfe (aarch64) (L<14>[ 18.335648] [IGT] kms_prop_blob: executing
11868 11:05:03.134032 inux: 6.1.96-cip<14>[ 18.341662] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11869 11:05:03.137724 24 aarch64)
11870 11:05:03.144242 Usi<14>[ 18.349253] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
11871 11:05:03.150821 ng IGT_SRANDOM=1<14>[ 18.358063] [IGT] kms_prop_blob: exiting, ret=0
11872 11:05:03.153747 720609502 for randomisation
11873 11:05:03.157427 Opened device: /dev/dri/card0
11874 11:05:03.163826 No KMS driver or no <8>[ 18.370178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11875 11:05:03.164537 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
11877 11:05:03.167265 outputs, pipes: 16, outputs: 0
11878 11:05:03.170714 [1mSubtest basic: SKIP (0.000s)[0m
11879 11:05:03.177194 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11880 11:05:03.180230 Using IGT_SRANDOM=1720609502 for randomisation
11881 11:05:03.183925 Opened device: /dev/dri/card0
11882 11:05:03.186849 Starting subtest: basic
11883 11:05:03.193433 [1mSubtest basic: SUCCESS (0.<14>[ 18.401691] [IGT] kms_prop_blob: executing
11884 11:05:03.193918 000s)[0m
11885 11:05:03.200014 IGT-V<14>[ 18.407421] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
11886 11:05:03.209958 ersion: 1.28-ga4<14>[ 18.415092] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
11887 11:05:03.216363 4ebfe (aarch64) <14>[ 18.423903] [IGT] kms_prop_blob: exiting, ret=0
11888 11:05:03.219849 (Linux: 6.1.96-cip24 aarch64)
11889 11:05:03.223547 Using IGT_SRANDOM=1720609503 for randomisation
11890 11:05:03.232801 Opened device: /d<8>[ 18.438128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
11891 11:05:03.233276 ev/dri/card0
11892 11:05:03.233871 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
11894 11:05:03.236258 Starting subtest: blob-prop-core
11895 11:05:03.239876 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11896 11:05:03.246291 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11897 11:05:03.249475 Using IGT_SRANDOM=1720609503 for randomisation
11898 11:05:03.252636 Opened device: /dev/dri/card0
11899 11:05:03.259450 Starting subtest: blob-prop<14>[ 18.469067] [IGT] kms_prop_blob: executing
11900 11:05:03.262737 -validate
11901 11:05:03.269164 [1mS<14>[ 18.474720] [IGT] kms_prop_blob: starting subtest blob-multiple
11902 11:05:03.275887 ubtest blob-prop<14>[ 18.482069] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
11903 11:05:03.282519 -validate: SUCCE<14>[ 18.490278] [IGT] kms_prop_blob: exiting, ret=0
11904 11:05:03.285775 SS (0.000s)[0m
11905 11:05:03.296034 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch<8>[ 18.502725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
11906 11:05:03.296480 64)
11907 11:05:03.297020 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
11909 11:05:03.302576 Using IGT_SRANDOM=1720609503 for randomisation
11910 11:05:03.305920 Opened device: /dev/dri/card0
11911 11:05:03.309023 Starting subtest: blob-prop-lifetime
11912 11:05:03.312542 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
11913 11:05:03.318982 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11914 11:05:03.325387 Using IGT_SRANDOM=1720609503<14>[ 18.533459] [IGT] kms_prop_blob: executing
11915 11:05:03.332236 for randomisati<14>[ 18.539211] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
11916 11:05:03.332761 on
11917 11:05:03.342323 Opened devic<14>[ 18.546995] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
11918 11:05:03.348681 e: /dev/dri/card<14>[ 18.556092] [IGT] kms_prop_blob: exiting, ret=0
11919 11:05:03.349150 0
11920 11:05:03.352396 Starting subtest: blob-multiple
11921 11:05:03.361784 [1mSubtest blob-multiple: SUCCESS (0.000s)<8>[ 18.569211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11922 11:05:03.362554 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11924 11:05:03.365356 [0m
11925 11:05:03.368771 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11926 11:05:03.375061 Using IGT_SRANDOM=1720609503 for randomisation
11927 11:05:03.375484 Opened device: /dev/dri/card0
11928 11:05:03.378530 Starting subtest: invalid-get-prop-any
11929 11:05:03.385358 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11930 11:05:03.391523 <14>[ 18.600306] [IGT] kms_prop_blob: executing
11931 11:05:03.398558 IGT-Version: 1.2<14>[ 18.605454] [IGT] kms_prop_blob: starting subtest invalid-get-prop
11932 11:05:03.408165 8-ga44ebfe (aarc<14>[ 18.613205] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
11933 11:05:03.414911 h64) (Linux: 6.1<14>[ 18.621911] [IGT] kms_prop_blob: exiting, ret=0
11934 11:05:03.415378 .96-cip24 aarch64)
11935 11:05:03.421387 Using IGT_SRANDOM=1720609503 for randomisation
11936 11:05:03.428022 Opened devic<8>[ 18.634747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11937 11:05:03.428778 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11939 11:05:03.431333 e: /dev/dri/card0
11940 11:05:03.434635 Starting subtest: invalid-get-prop
11941 11:05:03.437624 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11942 11:05:03.457134 <14>[ 18.665537] [IGT] kms_prop_blob: executing
11943 11:05:03.463444 IGT-Version: 1.2<14>[ 18.670654] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
11944 11:05:03.473514 8-ga44ebfe (aarc<14>[ 18.678767] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
11945 11:05:03.480398 h64) (Linux: 6.1<14>[ 18.687844] [IGT] kms_prop_blob: exiting, ret=0
11946 11:05:03.483334 .96-cip24 aarch64)
11947 11:05:03.486527 Using IGT_SRANDOM=1720609503 for randomisation
11948 11:05:03.493352 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11950 11:05:03.496727 Opened devic<8>[ 18.700756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11951 11:05:03.497291 e: /dev/dri/card0
11952 11:05:03.499832 Starting subtest: invalid-set-prop-any
11953 11:05:03.506501 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11954 11:05:03.512921 <14>[ 18.721623] [IGT] kms_prop_blob: executing
11955 11:05:03.519699 IGT-Version: 1.2<14>[ 18.726405] [IGT] kms_prop_blob: starting subtest invalid-set-prop
11956 11:05:03.529811 8-ga44ebfe (aarc<14>[ 18.734171] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
11957 11:05:03.536010 h64) (Linux: 6.1<14>[ 18.742927] [IGT] kms_prop_blob: exiting, ret=0
11958 11:05:03.536437 .96-cip24 aarch64)
11959 11:05:03.542796 Using IGT_SRANDOM=1720609503 for randomisation
11960 11:05:03.549199 Opened devic<8>[ 18.755807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11961 11:05:03.549913 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11963 11:05:03.552685 e: /dev/dri/card0
11964 11:05:03.556072 Starting subt<8>[ 18.765405] <LAVA_SIGNAL_TESTSET STOP>
11965 11:05:03.556746 Received signal: <TESTSET> STOP
11966 11:05:03.557058 Closing test_set kms_prop_blob
11967 11:05:03.559757 est: invalid-set-prop
11968 11:05:03.562729 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11969 11:05:03.588411 <8>[ 18.796978] <LAVA_SIGNAL_TESTSET START kms_setmode>
11970 11:05:03.589138 Received signal: <TESTSET> START kms_setmode
11971 11:05:03.589549 Starting test_set kms_setmode
11972 11:05:03.618061 <14>[ 18.826843] [IGT] kms_setmode: executing
11973 11:05:03.624715 IGT-Version: 1.2<14>[ 18.831831] [IGT] kms_setmode: starting subtest basic
11974 11:05:03.631335 8-ga44ebfe (aarc<14>[ 18.838412] [IGT] kms_setmode: finished subtest basic, SKIP
11975 11:05:03.638117 h64) (Linux: 6.1<14>[ 18.845691] [IGT] kms_setmode: exiting, ret=77
11976 11:05:03.641476 .96-cip24 aarch64)
11977 11:05:03.644564 Using IGT_SRANDOM=1720609503 for randomisation
11978 11:05:03.651731 Opened devic<8>[ 18.857582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11979 11:05:03.652458 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11981 11:05:03.654739 e: /dev/dri/card0
11982 11:05:03.655157 Starting subtest: basic
11983 11:05:03.657741 No dynamic tests executed.
11984 11:05:03.660998 [1mSubtest basic: SKIP (0.000s)[0m
11985 11:05:03.669318 <14>[ 18.877948] [IGT] kms_setmode: executing
11986 11:05:03.676036 IGT-Version: 1.2<14>[ 18.882579] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
11987 11:05:03.685891 8-ga44ebfe (aarc<14>[ 18.890782] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
11988 11:05:03.692346 h64) (Linux: 6.1<14>[ 18.899760] [IGT] kms_setmode: exiting, ret=77
11989 11:05:03.692730 .96-cip24 aarch64)
11990 11:05:03.705455 Using IGT_SRANDOM=1720609503 for randomisati<8>[ 18.910952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
11991 11:05:03.705915 on
11992 11:05:03.706468 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
11994 11:05:03.708763 Opened device: /dev/dri/card0
11995 11:05:03.712569 Starting subtest: basic-clone-single-crtc
11996 11:05:03.715668 No dynamic tests executed.
11997 11:05:03.718901 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
11998 11:05:03.725386 <14>[ 18.934026] [IGT] kms_setmode: executing
11999 11:05:03.732035 IGT-Version: 1.2<14>[ 18.938714] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12000 11:05:03.741746 8-ga44ebfe (aarc<14>[ 18.947077] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12001 11:05:03.748630 h64) (Linux: 6.1<14>[ 18.956273] [IGT] kms_setmode: exiting, ret=77
12002 11:05:03.751700 .96-cip24 aarch64)
12003 11:05:03.761560 Using IGT_SRANDOM=1720609503 for randomisati<8>[ 18.967703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12004 11:05:03.761997 on
12005 11:05:03.762578 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12007 11:05:03.765122 Opened device: /dev/dri/card0
12008 11:05:03.768376 Starting subtest: invalid-clone-single-crtc
12009 11:05:03.771750 No dynamic tests executed.
12010 11:05:03.778290 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12011 11:05:03.790471 <14>[ 18.999298] [IGT] kms_setmode: executing
12012 11:05:03.800688 IGT-Version: 1.2<14>[ 19.004276] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12013 11:05:03.807018 8-ga44ebfe (aarc<14>[ 19.012803] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12014 11:05:03.813753 h64) (Linux: 6.1<14>[ 19.022147] [IGT] kms_setmode: exiting, ret=77
12015 11:05:03.817185 .96-cip24 aarch64)
12016 11:05:03.820176 Using IGT_SRANDOM=1720609503 for randomisation
12017 11:05:03.824185 Opened device: /dev/dri/card0
12018 11:05:03.833346 Starting subt<8>[ 19.037109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12019 11:05:03.834057 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12021 11:05:03.836710 est: invalid-clone-exclusive-crtc
12022 11:05:03.837327 No dynamic tests executed.
12023 11:05:03.843293 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12024 11:05:03.852119 <14>[ 19.060974] [IGT] kms_setmode: executing
12025 11:05:03.858629 IGT-Version: 1.2<14>[ 19.065685] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12026 11:05:03.868741 8-ga44ebfe (aarc<14>[ 19.073627] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12027 11:05:03.874973 h64) (Linux: 6.1<14>[ 19.082318] [IGT] kms_setmode: exiting, ret=77
12028 11:05:03.875078 .96-cip24 aarch64)
12029 11:05:03.888291 Using IGT_SRANDOM=1720609503 for randomisati<8>[ 19.093091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12030 11:05:03.888405 on
12031 11:05:03.888715 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12033 11:05:03.891824 Opened device: /dev/dri/card0
12034 11:05:03.894985 Starting subtest: clone-exclusive-crtc
12035 11:05:03.898449 No dynamic tests executed.
12036 11:05:03.905423 [1mSubtest clone-exclusive-crtc: SKIP (0<14>[ 19.113151] [IGT] kms_setmode: executing
12037 11:05:03.905871 .000s)[0m
12038 11:05:03.915439 <14>[ 19.119014] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12039 11:05:03.925138 IGT-Version: 1.2<14>[ 19.127715] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12040 11:05:03.931913 8-ga44ebfe (aarc<14>[ 19.137686] [IGT] kms_setmode: exiting, ret=77
12041 11:05:03.932431 h64) (Linux: 6.1.96-cip24 aarch64)
12042 11:05:03.945094 Using IGT_SRANDOM=1720609503<8>[ 19.148143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12043 11:05:03.945805 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12045 11:05:03.948177 Received signal: <TESTSET> STOP
12046 11:05:03.948571 Closing test_set kms_setmode
12047 11:05:03.951470 for randomisati<8>[ 19.159519] <LAVA_SIGNAL_TESTSET STOP>
12048 11:05:03.951892 on
12049 11:05:03.952220 Opened device: /dev/dri/card0
12050 11:05:03.958087 Starting subtest: invalid-clone-single-crtc-stealing
12051 11:05:03.961406 No dynamic tests executed.
12052 11:05:03.971095 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000<8>[ 19.178476] <LAVA_SIGNAL_TESTSET START kms_vblank>
12053 11:05:03.971483 s)[0m
12054 11:05:03.972089 Received signal: <TESTSET> START kms_vblank
12055 11:05:03.972533 Starting test_set kms_vblank
12056 11:05:03.988736 <14>[ 19.197257] [IGT] kms_vblank: executing
12057 11:05:03.995097 IGT-Version: 1.2<14>[ 19.202006] [IGT] kms_vblank: exiting, ret=77
12058 11:05:03.999066 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12059 11:05:04.004931 Using IGT_SR<8>[ 19.212115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12060 11:05:04.005582 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12062 11:05:04.008077 ANDOM=1720609503 for randomisation
12063 11:05:04.011953 Opened device: /dev/dri/card0
12064 11:05:04.018449 No KMS driver or no outputs, pipes: 16, outputs: 0
12065 11:05:04.021609 [1mSubtest invalid: SKIP<14>[ 19.232435] [IGT] kms_vblank: executing
12066 11:05:04.025167 (0.000s)[0m
12067 11:05:04.028055 <14>[ 19.237242] [IGT] kms_vblank: exiting, ret=77
12068 11:05:04.034749 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12069 11:05:04.045076 Using IGT_SRANDOM=1720609504<8>[ 19.250261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12070 11:05:04.045642 for randomisation
12071 11:05:04.046225 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12073 11:05:04.048099 Opened device: /dev/dri/card0
12074 11:05:04.054644 No KMS driver or no outputs, pipes: 16, outputs: 0
12075 11:05:04.058121 [1mSubtest crtc-id: SKIP (0.000s)[0m
12076 11:05:04.061146 <14>[ 19.270674] [IGT] kms_vblank: executing
12077 11:05:04.068227 IGT-Version: 1.2<14>[ 19.275334] [IGT] kms_vblank: exiting, ret=77
12078 11:05:04.070868 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12079 11:05:04.081311 Using IGT_SRANDOM=1720609504<8>[ 19.286838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12080 11:05:04.082165 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12082 11:05:04.084269 for randomisation
12083 11:05:04.084688 Opened device: /dev/dri/card0
12084 11:05:04.091119 No KMS driver or no outputs, pipes: 16, outputs: 0
12085 11:05:04.094524 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12086 11:05:04.097557 <14>[ 19.307773] [IGT] kms_vblank: executing
12087 11:05:04.104285 IGT-Version: 1.2<14>[ 19.313045] [IGT] kms_vblank: exiting, ret=77
12088 11:05:04.111149 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12089 11:05:04.117731 Using IGT_SR<8>[ 19.323998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12090 11:05:04.118421 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12092 11:05:04.121005 ANDOM=1720609504 for randomisation
12093 11:05:04.124084 Opened device: /dev/dri/card0
12094 11:05:04.127802 No KMS driver or no outputs, pipes: 16, outputs: 0
12095 11:05:04.130582 [1mSubtest query-idle: SKIP (0.000s)[0m
12096 11:05:04.148280 <14>[ 19.356083] [IGT] kms_vblank: executing
12097 11:05:04.154100 IGT-Version: 1.2<14>[ 19.361321] [IGT] kms_vblank: exiting, ret=77
12098 11:05:04.157622 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12099 11:05:04.167172 Using IGT_SRANDOM=1720609504<8>[ 19.372826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12100 11:05:04.167937 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12102 11:05:04.170402 for randomisation
12103 11:05:04.170839 Opened device: /dev/dri/card0
12104 11:05:04.177361 No KMS driver or no outputs, pipes: 16, outputs: 0
12105 11:05:04.180765 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12106 11:05:04.183725 <14>[ 19.393570] [IGT] kms_vblank: executing
12107 11:05:04.190297 IGT-Version: 1.2<14>[ 19.398674] [IGT] kms_vblank: exiting, ret=77
12108 11:05:04.196956 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12109 11:05:04.203747 Using IGT_SRANDOM=1720609504<8>[ 19.410209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12110 11:05:04.204500 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12112 11:05:04.206739 for randomisation
12113 11:05:04.210221 Opened device: /dev/dri/card0
12114 11:05:04.213839 No KMS driver or no outputs, pipes: 16, outputs: 0
12115 11:05:04.220043 [1mSubtest query-forked: SKIP (0.000s)[<14>[ 19.430933] [IGT] kms_vblank: executing
12116 11:05:04.223567 0m
12117 11:05:04.226742 IGT-Version: 1.2<14>[ 19.435797] [IGT] kms_vblank: exiting, ret=77
12118 11:05:04.233340 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12119 11:05:04.243308 Using IGT_SRANDOM=1720609504<8>[ 19.447771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12120 11:05:04.243756 for randomisation
12121 11:05:04.244446 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12123 11:05:04.246923 Opened device: /dev/dri/card0
12124 11:05:04.252847 No KMS driver or no outputs, pipes: 16, outputs: 0
12125 11:05:04.256180 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12126 11:05:04.259554 <14>[ 19.468733] [IGT] kms_vblank: executing
12127 11:05:04.266645 IGT-Version: 1.2<14>[ 19.474063] [IGT] kms_vblank: exiting, ret=77
12128 11:05:04.269759 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12129 11:05:04.279931 Using IGT_SRANDOM=1720609504<8>[ 19.485821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12130 11:05:04.280626 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12132 11:05:04.283390 for randomisation
12133 11:05:04.283828 Opened device: /dev/dri/card0
12134 11:05:04.289483 No KMS driver or no outputs, pipes: 16, outputs: 0
12135 11:05:04.292754 [1mSubtest query-busy: SKIP (0.000s)[0m
12136 11:05:04.296253 <14>[ 19.506350] [IGT] kms_vblank: executing
12137 11:05:04.302712 IGT-Version: 1.2<14>[ 19.511056] [IGT] kms_vblank: exiting, ret=77
12138 11:05:04.306093 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12139 11:05:04.315764 Using IGT_SRANDOM=1720609504<8>[ 19.522568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12140 11:05:04.316401 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12142 11:05:04.319112 for randomisation
12143 11:05:04.322284 Opened device: /dev/dri/card0
12144 11:05:04.326080 No KMS driver or no outputs, pipes: 16, outputs: 0
12145 11:05:04.329086 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12146 11:05:04.335814 <14>[ 19.543725] [IGT] kms_vblank: executing
12147 11:05:04.342332 IGT-Version: 1.2<14>[ 19.548997] [IGT] kms_vblank: exiting, ret=77
12148 11:05:04.346081 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12149 11:05:04.352181 Using IGT_SR<8>[ 19.560129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12150 11:05:04.352815 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12152 11:05:04.355584 ANDOM=1720609504 for randomisation
12153 11:05:04.358807 Opened device: /dev/dri/card0
12154 11:05:04.365586 No KMS driver or no outputs, pipes: 16, outputs: 0
12155 11:05:04.372035 [1mSubtest query-forked-busy: SKIP (0.00<14>[ 19.580445] [IGT] kms_vblank: executing
12156 11:05:04.372465 0s)[0m
12157 11:05:04.378738 <14>[ 19.586289] [IGT] kms_vblank: exiting, ret=77
12158 11:05:04.392108 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<8>[ 19.596640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12159 11:05:04.392511 4)
12160 11:05:04.393167 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12162 11:05:04.395361 Using IGT_SRANDOM=1720609504 for randomisation
12163 11:05:04.398544 Opened device: /dev/dri/card0
12164 11:05:04.401869 No KMS driver or no outputs, pipes: 16, outputs: 0
12165 11:05:04.408564 [1mSubtest query-forked-<14>[ 19.617440] [IGT] kms_vblank: executing
12166 11:05:04.415548 busy-hang: SKIP <14>[ 19.623394] [IGT] kms_vblank: exiting, ret=77
12167 11:05:04.415948 (0.000s)[0m
12168 11:05:04.428415 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)<8>[ 19.634666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12169 11:05:04.428819
12170 11:05:04.429459 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12172 11:05:04.434909 Using IGT_SRANDOM=1720609504 for randomisation
12173 11:05:04.435315 Opened device: /dev/dri/card0
12174 11:05:04.441551 No KMS driver or no outputs, pipes: 16, outputs: 0
12175 11:05:04.448115 [1mSubtest wait-idle: SKIP<14>[ 19.655660] [IGT] kms_vblank: executing
12176 11:05:04.448503 (0.000s)[0m
12177 11:05:04.454885 <14>[ 19.661453] [IGT] kms_vblank: exiting, ret=77
12178 11:05:04.464557 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<8>[ 19.671068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12179 11:05:04.465305 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12181 11:05:04.468000 .96-cip24 aarch64)
12182 11:05:04.471268 Using IGT_SRANDOM=1720609504 for randomisation
12183 11:05:04.474656 Opened device: /dev/dri/card0
12184 11:05:04.480760 No KMS driver or no outputs, pipes: 16, outpu<14>[ 19.690832] [IGT] kms_vblank: executing
12185 11:05:04.481051 ts: 0
12186 11:05:04.487616 [1mSubte<14>[ 19.695499] [IGT] kms_vblank: exiting, ret=77
12187 11:05:04.490693 st wait-idle-hang: SKIP (0.000s)[0m
12188 11:05:04.500652 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<8>[ 19.706941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12189 11:05:04.500982 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12191 11:05:04.503897 x: 6.1.96-cip24 aarch64)
12192 11:05:04.507123 Using IGT_SRANDOM=1720609504 for randomisation
12193 11:05:04.510506 Opened device: /dev/dri/card0
12194 11:05:04.514209 No KMS driver or no outputs, pipes: 16, outputs: 0
12195 11:05:04.520296 [1<14>[ 19.727924] [IGT] kms_vblank: executing
12196 11:05:04.523646 mSubtest wait-fo<14>[ 19.733615] [IGT] kms_vblank: exiting, ret=77
12197 11:05:04.527235 rked: SKIP (0.000s)[0m
12198 11:05:04.540081 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip<8>[ 19.744946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12199 11:05:04.540192 24 aarch64)
12200 11:05:04.540402 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12202 11:05:04.543429 Using IGT_SRANDOM=1720609504 for randomisation
12203 11:05:04.546972 Opened device: /dev/dri/card0
12204 11:05:04.553688 No KMS driver or no outputs, pipes: 16, outputs: 0
12205 11:05:04.556941 [1mSubtest wait<14>[ 19.766416] [IGT] kms_vblank: executing
12206 11:05:04.563368 -forked-hang: SK<14>[ 19.772148] [IGT] kms_vblank: exiting, ret=77
12207 11:05:04.566688 IP (0.000s)[0m
12208 11:05:04.576915 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch<8>[ 19.783610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12209 11:05:04.577088 64)
12210 11:05:04.577413 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12212 11:05:04.583576 Using IGT_SRANDOM=1720609504 for randomisation
12213 11:05:04.583739 Opened device: /dev/dri/card0
12214 11:05:04.590069 No KMS driver or no outputs, pipes: 16, outputs: 0
12215 11:05:04.593269 [1mSubt<14>[ 19.803997] [IGT] kms_vblank: executing
12216 11:05:04.600214 est wait-busy: S<14>[ 19.808912] [IGT] kms_vblank: exiting, ret=77
12217 11:05:04.603275 KIP (0.000s)[0m
12218 11:05:04.613193 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarc<8>[ 19.820127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12219 11:05:04.613491 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12221 11:05:04.616330 h64)
12222 11:05:04.619860 Using IGT_SRANDOM=1720609504 for randomisation
12223 11:05:04.622944 Opened device: /dev/dri/card0
12224 11:05:04.626373 No KMS driver or no outputs, pipes: 16, outputs: 0
12225 11:05:04.633082 [1mSubtest wait-busy-h<14>[ 19.841485] [IGT] kms_vblank: executing
12226 11:05:04.639641 ang: SKIP (0.000<14>[ 19.847175] [IGT] kms_vblank: exiting, ret=77
12227 11:05:04.639730 s)[0m
12228 11:05:04.646295 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12229 11:05:04.652851 Usin<8>[ 19.859099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12230 11:05:04.653108 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12232 11:05:04.656347 g IGT_SRANDOM=1720609504 for randomisation
12233 11:05:04.659530 Opened device: /dev/dri/card0
12234 11:05:04.663145 No KMS driver or no outputs, pipes: 16, outputs: 0
12235 11:05:04.669590 [1mSubtest wait-<14>[ 19.879707] [IGT] kms_vblank: executing
12236 11:05:04.676235 forked-busy: SKI<14>[ 19.884513] [IGT] kms_vblank: exiting, ret=77
12237 11:05:04.676330 P (0.000s)[0m
12238 11:05:04.689275 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<8>[ 19.895917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12239 11:05:04.689559 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12241 11:05:04.692360 4)
12242 11:05:04.695750 Using IGT_SRANDOM=1720609504 for randomisation
12243 11:05:04.699049 Opened device: /dev/dri/card0
12244 11:05:04.702457 No KMS driver or no outputs, pipes: 16, outputs: 0
12245 11:05:04.708978 [1mSubtest wait-forked-b<14>[ 19.917662] [IGT] kms_vblank: executing
12246 11:05:04.715760 usy-hang: SKIP (<14>[ 19.923495] [IGT] kms_vblank: exiting, ret=77
12247 11:05:04.715837 0.000s)[0m
12248 11:05:04.722460 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12249 11:05:04.728889 <8>[ 19.935015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12250 11:05:04.728965
12251 11:05:04.729193 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12253 11:05:04.735711 Using IGT_SRANDOM=1720609504 for randomisation
12254 11:05:04.735786 Opened device: /dev/dri/card0
12255 11:05:04.742326 No KMS driver or no outputs, pipes: 16, outputs: 0
12256 11:05:04.748774 [1mSubtest ts-continuation-<14>[ 19.956502] [IGT] kms_vblank: executing
12257 11:05:04.755405 idle: SKIP (0.00<14>[ 19.962499] [IGT] kms_vblank: exiting, ret=77
12258 11:05:04.755499 0s)[0m
12259 11:05:04.761968 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12260 11:05:04.769128 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12262 11:05:04.772237 Using IGT_SRANDOM=1<8>[ 19.975280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12263 11:05:04.772362 720609504 for randomisation
12264 11:05:04.775480 Opened device: /dev/dri/card0
12265 11:05:04.778873 No KMS driver or no outputs, pipes: 16, outputs: 0
12266 11:05:04.788665 [1mSubtest ts-continuation-idle-hang: SKIP (0.0<14>[ 19.997860] [IGT] kms_vblank: executing
12267 11:05:04.788851 00s)[0m
12268 11:05:04.795368 <14>[ 20.003141] [IGT] kms_vblank: exiting, ret=77
12269 11:05:04.798796 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12270 11:05:04.808645 Using IGT_SR<8>[ 20.014335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12271 11:05:04.809308 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12273 11:05:04.812419 ANDOM=1720609504 for randomisation
12274 11:05:04.815513 Opened device: /dev/dri/card0
12275 11:05:04.818671 No KMS driver or no outputs, pipes: 16, outputs: 0
12276 11:05:04.828819 [1mSubtest ts-continuation-dpms-rpm: SKI<14>[ 20.035899] [IGT] kms_vblank: executing
12277 11:05:04.829258 P (0.000s)[0m
12278 11:05:04.835250 <14>[ 20.041905] [IGT] kms_vblank: exiting, ret=77
12279 11:05:04.838586 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12280 11:05:04.848451 Using IGT_SR<8>[ 20.053336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12281 11:05:04.849074 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12283 11:05:04.851688 ANDOM=1720609504 for randomisation
12284 11:05:04.855246 Opened device: /dev/dri/card0
12285 11:05:04.858628 No KMS driver or no outputs, pipes: 16, outputs: 0
12286 11:05:04.868501 [1mSubtest ts-continuation-dpms-suspend:<14>[ 20.075777] [IGT] kms_vblank: executing
12287 11:05:04.875037 SKIP (0.000s)[<14>[ 20.081612] [IGT] kms_vblank: exiting, ret=77
12288 11:05:04.875425 0m
12289 11:05:04.878281 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12290 11:05:04.888164 Using IG<8>[ 20.093016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12291 11:05:04.888787 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12293 11:05:04.891390 T_SRANDOM=1720609504 for randomisation
12294 11:05:04.894678 Opened device: /dev/dri/card0
12295 11:05:04.898057 No KMS driver or no outputs, pipes: 16, outputs: 0
12296 11:05:04.907930 [1mSubtest ts-continuation-suspend: <14>[ 20.115008] [IGT] kms_vblank: executing
12297 11:05:04.911721 SKIP (0.000s)[0<14>[ 20.120835] [IGT] kms_vblank: exiting, ret=77
12298 11:05:04.912104 m
12299 11:05:04.924639 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aar<8>[ 20.131794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12300 11:05:04.925404 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12302 11:05:04.927926 ch64)
12303 11:05:04.931049 Using IGT_SRANDOM=1720609504 for randomisation
12304 11:05:04.934459 Opened device: /dev/dri/card0
12305 11:05:04.937946 No KMS driver or no outputs, pipes: 16, outputs: 0
12306 11:05:04.944568 [1mSubtest ts-continu<14>[ 20.152684] [IGT] kms_vblank: executing
12307 11:05:04.951326 ation-modeset: S<14>[ 20.158447] [IGT] kms_vblank: exiting, ret=77
12308 11:05:04.951755 KIP (0.000s)[0m
12309 11:05:04.964549 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<8>[ 20.169704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12310 11:05:04.965200 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12312 11:05:04.967850 .1.96-cip24 aarch64)
12313 11:05:04.971306 Using IGT_SRANDOM=1720609504 for randomisation
12314 11:05:04.974226 Opened device: /dev/dri/card0
12315 11:05:04.977753 No KMS driver or no outputs, pipes: 16, outputs: 0
12316 11:05:04.980681 [1mSub<14>[ 20.190713] [IGT] kms_vblank: executing
12317 11:05:04.987556 test ts-continua<14>[ 20.196888] [IGT] kms_vblank: exiting, ret=77
12318 11:05:04.990659 tion-modeset-hang: SKIP (0.000s)[0m
12319 11:05:05.001458 IGT-Version: 1.28-ga44ebfe<8>[ 20.207785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12320 11:05:05.002108 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12322 11:05:05.007766 Received signal: <TESTSET> STOP
12323 11:05:05.008203 Closing test_set kms_vblank
12324 11:05:05.010346 (aarch64) (Linux: 6.1.96-cip24 <8>[ 20.217782] <LAVA_SIGNAL_TESTSET STOP>
12325 11:05:05.010743 aarch64)
12326 11:05:05.017006 Using <8>[ 20.224279] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14786812_1.5.2.3.1>
12327 11:05:05.017691 Received signal: <ENDRUN> 0_igt-kms-mediatek 14786812_1.5.2.3.1
12328 11:05:05.018093 Ending use of test pattern.
12329 11:05:05.018439 Ending test lava.0_igt-kms-mediatek (14786812_1.5.2.3.1), duration 6.37
12331 11:05:05.020404 IGT_SRANDOM=1720609504 for randomisation
12332 11:05:05.023848 Opened device: /dev/dri/card0
12333 11:05:05.027169 No KMS driver or no outputs, pipes: 16, outputs: 0
12334 11:05:05.033740 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12335 11:05:05.034124 + set +x
12336 11:05:05.036927 <LAVA_TEST_RUNNER EXIT>
12337 11:05:05.037602 ok: lava_test_shell seems to have completed
12338 11:05:05.044666 getclient-simple:
set: core_auth
result: pass
getclient-master-drop:
set: core_auth
result: pass
basic-auth:
set: core_auth
result: pass
many-magics:
set: core_auth
result: pass
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
invalid-buffer:
set: drm_read
result: skip
fault-buffer:
set: drm_read
result: skip
empty-block:
set: drm_read
result: skip
empty-nonblock:
set: drm_read
result: skip
short-buffer-block:
set: drm_read
result: skip
short-buffer-nonblock:
set: drm_read
result: skip
short-buffer-wakeup:
set: drm_read
result: skip
unused-handle:
set: kms_addfb_basic
result: pass
unused-pitches:
set: kms_addfb_basic
result: pass
unused-offsets:
set: kms_addfb_basic
result: pass
unused-modifier:
set: kms_addfb_basic
result: pass
clobberred-modifier:
set: kms_addfb_basic
result: skip
invalid-smem-bo-on-discrete:
set: kms_addfb_basic
result: skip
legacy-format:
set: kms_addfb_basic
result: pass
no-handle:
set: kms_addfb_basic
result: pass
basic:
set: kms_setmode
result: skip
bad-pitch-0:
set: kms_addfb_basic
result: pass
bad-pitch-32:
set: kms_addfb_basic
result: pass
bad-pitch-63:
set: kms_addfb_basic
result: pass
bad-pitch-128:
set: kms_addfb_basic
result: pass
bad-pitch-256:
set: kms_addfb_basic
result: pass
bad-pitch-1024:
set: kms_addfb_basic
result: pass
bad-pitch-999:
set: kms_addfb_basic
result: pass
bad-pitch-65536:
set: kms_addfb_basic
result: pass
invalid-get-prop-any:
set: kms_prop_blob
result: pass
invalid-get-prop:
set: kms_prop_blob
result: pass
invalid-set-prop-any:
set: kms_prop_blob
result: pass
invalid-set-prop:
set: kms_prop_blob
result: pass
master-rmfb:
set: kms_addfb_basic
result: pass
addfb25-modifier-no-flag:
set: kms_addfb_basic
result: pass
addfb25-bad-modifier:
set: kms_addfb_basic
result: fail
addfb25-x-tiled-mismatch-legacy:
set: kms_addfb_basic
result: skip
addfb25-x-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-framebuffer-vs-set-tiling:
set: kms_addfb_basic
result: skip
basic-x-tiled-legacy:
set: kms_addfb_basic
result: skip
framebuffer-vs-set-tiling:
set: kms_addfb_basic
result: skip
tile-pitch-mismatch:
set: kms_addfb_basic
result: skip
basic-y-tiled-legacy:
set: kms_addfb_basic
result: skip
size-max:
set: kms_addfb_basic
result: skip
too-wide:
set: kms_addfb_basic
result: skip
too-high:
set: kms_addfb_basic
result: skip
bo-too-small:
set: kms_addfb_basic
result: skip
small-bo:
set: kms_addfb_basic
result: skip
bo-too-small-due-to-tiling:
set: kms_addfb_basic
result: skip
addfb25-y-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-yf-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-y-tiled-small-legacy:
set: kms_addfb_basic
result: skip
addfb25-4-tiled:
set: kms_addfb_basic
result: skip
plane-overlay-legacy:
set: kms_atomic
result: skip
plane-primary-legacy:
set: kms_atomic
result: skip
plane-primary-overlay-mutable-zpos:
set: kms_atomic
result: skip
plane-immutable-zpos:
set: kms_atomic
result: skip
test-only:
set: kms_atomic
result: skip
plane-cursor-legacy:
set: kms_atomic
result: skip
plane-invalid-params:
set: kms_atomic
result: skip
plane-invalid-params-fence:
set: kms_atomic
result: skip
crtc-invalid-params:
set: kms_atomic
result: skip
crtc-invalid-params-fence:
set: kms_atomic
result: skip
atomic-invalid-params:
set: kms_atomic
result: skip
atomic-plane-damage:
set: kms_atomic
result: skip
blob-prop-core:
set: kms_prop_blob
result: pass
blob-prop-validate:
set: kms_prop_blob
result: pass
blob-prop-lifetime:
set: kms_prop_blob
result: pass
blob-multiple:
set: kms_prop_blob
result: pass
basic-clone-single-crtc:
set: kms_setmode
result: skip
invalid-clone-single-crtc:
set: kms_setmode
result: skip
invalid-clone-exclusive-crtc:
set: kms_setmode
result: skip
clone-exclusive-crtc:
set: kms_setmode
result: skip
invalid-clone-single-crtc-stealing:
set: kms_setmode
result: skip
invalid:
set: kms_vblank
result: skip
crtc-id:
set: kms_vblank
result: skip
accuracy-idle:
set: kms_vblank
result: skip
query-idle:
set: kms_vblank
result: skip
query-idle-hang:
set: kms_vblank
result: skip
query-forked:
set: kms_vblank
result: skip
query-forked-hang:
set: kms_vblank
result: skip
query-busy:
set: kms_vblank
result: skip
query-busy-hang:
set: kms_vblank
result: skip
query-forked-busy:
set: kms_vblank
result: skip
query-forked-busy-hang:
set: kms_vblank
result: skip
wait-idle:
set: kms_vblank
result: skip
wait-idle-hang:
set: kms_vblank
result: skip
wait-forked:
set: kms_vblank
result: skip
wait-forked-hang:
set: kms_vblank
result: skip
wait-busy:
set: kms_vblank
result: skip
wait-busy-hang:
set: kms_vblank
result: skip
wait-forked-busy:
set: kms_vblank
result: skip
wait-forked-busy-hang:
set: kms_vblank
result: skip
ts-continuation-idle:
set: kms_vblank
result: skip
ts-continuation-idle-hang:
set: kms_vblank
result: skip
ts-continuation-dpms-rpm:
set: kms_vblank
result: skip
ts-continuation-dpms-suspend:
set: kms_vblank
result: skip
ts-continuation-suspend:
set: kms_vblank
result: skip
ts-continuation-modeset:
set: kms_vblank
result: skip
ts-continuation-modeset-hang:
set: kms_vblank
result: skip
ts-continuation-modeset-rpm:
set: kms_vblank
result: skip
12339 11:05:05.045438 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12340 11:05:05.045845 end: 3 lava-test-retry (duration 00:00:07) [common]
12341 11:05:05.046311 start: 4 finalize (timeout 00:07:47) [common]
12342 11:05:05.046718 start: 4.1 power-off (timeout 00:00:30) [common]
12343 11:05:05.047323 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
12344 11:05:07.173546 >> Command sent successfully.
12345 11:05:07.187551 Returned 0 in 2 seconds
12346 11:05:07.188149 end: 4.1 power-off (duration 00:00:02) [common]
12348 11:05:07.189134 start: 4.2 read-feedback (timeout 00:07:44) [common]
12349 11:05:07.189793 Listened to connection for namespace 'common' for up to 1s
12350 11:05:08.190763 Finalising connection for namespace 'common'
12351 11:05:08.190937 Disconnecting from shell: Finalise
12352 11:05:08.191004 / #
12353 11:05:08.291266 end: 4.2 read-feedback (duration 00:00:01) [common]
12354 11:05:08.291411 end: 4 finalize (duration 00:00:03) [common]
12355 11:05:08.291506 Cleaning after the job
12356 11:05:08.291594 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/ramdisk
12357 11:05:08.298304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/kernel
12358 11:05:08.313724 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/dtb
12359 11:05:08.313927 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786812/tftp-deploy-mulcmt2h/modules
12360 11:05:08.319873 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786812
12361 11:05:08.430462 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786812
12362 11:05:08.430628 Job finished correctly