Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:05:14.068398 lava-dispatcher, installed at version: 2024.05
2 11:05:14.068595 start: 0 validate
3 11:05:14.068716 Start time: 2024-07-10 11:05:14.068707+00:00 (UTC)
4 11:05:14.068842 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:05:14.068978 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:05:14.338873 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:05:14.339483 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:05:14.608468 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:05:14.609244 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:05:14.878927 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:05:14.879481 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:05:15.149645 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:05:15.150220 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:05:15.427147 validate duration: 1.36
16 11:05:15.428261 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:05:15.428741 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:05:15.429165 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:05:15.429823 Not decompressing ramdisk as can be used compressed.
20 11:05:15.430242 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:05:15.430549 saving as /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/ramdisk/initrd.cpio.gz
22 11:05:15.430839 total size: 5628169 (5 MB)
23 11:05:15.435224 progress 0 % (0 MB)
24 11:05:15.443354 progress 5 % (0 MB)
25 11:05:15.451277 progress 10 % (0 MB)
26 11:05:15.456173 progress 15 % (0 MB)
27 11:05:15.460279 progress 20 % (1 MB)
28 11:05:15.463494 progress 25 % (1 MB)
29 11:05:15.466759 progress 30 % (1 MB)
30 11:05:15.469523 progress 35 % (1 MB)
31 11:05:15.471840 progress 40 % (2 MB)
32 11:05:15.474231 progress 45 % (2 MB)
33 11:05:15.476282 progress 50 % (2 MB)
34 11:05:15.478346 progress 55 % (2 MB)
35 11:05:15.480401 progress 60 % (3 MB)
36 11:05:15.482123 progress 65 % (3 MB)
37 11:05:15.483962 progress 70 % (3 MB)
38 11:05:15.485613 progress 75 % (4 MB)
39 11:05:15.487300 progress 80 % (4 MB)
40 11:05:15.488777 progress 85 % (4 MB)
41 11:05:15.490494 progress 90 % (4 MB)
42 11:05:15.492051 progress 95 % (5 MB)
43 11:05:15.493425 progress 100 % (5 MB)
44 11:05:15.493633 5 MB downloaded in 0.06 s (85.45 MB/s)
45 11:05:15.493780 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:05:15.493997 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:05:15.494076 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:05:15.494152 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:05:15.494282 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:05:15.494344 saving as /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/kernel/Image
52 11:05:15.494398 total size: 54813184 (52 MB)
53 11:05:15.494452 No compression specified
54 11:05:15.495422 progress 0 % (0 MB)
55 11:05:15.508731 progress 5 % (2 MB)
56 11:05:15.522228 progress 10 % (5 MB)
57 11:05:15.535615 progress 15 % (7 MB)
58 11:05:15.549255 progress 20 % (10 MB)
59 11:05:15.562836 progress 25 % (13 MB)
60 11:05:15.576403 progress 30 % (15 MB)
61 11:05:15.590158 progress 35 % (18 MB)
62 11:05:15.603728 progress 40 % (20 MB)
63 11:05:15.617244 progress 45 % (23 MB)
64 11:05:15.630854 progress 50 % (26 MB)
65 11:05:15.644457 progress 55 % (28 MB)
66 11:05:15.657999 progress 60 % (31 MB)
67 11:05:15.671739 progress 65 % (34 MB)
68 11:05:15.685274 progress 70 % (36 MB)
69 11:05:15.698898 progress 75 % (39 MB)
70 11:05:15.712701 progress 80 % (41 MB)
71 11:05:15.725991 progress 85 % (44 MB)
72 11:05:15.739413 progress 90 % (47 MB)
73 11:05:15.752727 progress 95 % (49 MB)
74 11:05:15.765986 progress 100 % (52 MB)
75 11:05:15.766199 52 MB downloaded in 0.27 s (192.33 MB/s)
76 11:05:15.766377 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:05:15.766594 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:05:15.766674 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:05:15.766749 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:05:15.766876 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:05:15.766942 saving as /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/dtb/mt8192-asurada-spherion-r0.dtb
83 11:05:15.766995 total size: 47258 (0 MB)
84 11:05:15.767048 No compression specified
85 11:05:15.768148 progress 69 % (0 MB)
86 11:05:15.768403 progress 100 % (0 MB)
87 11:05:15.768550 0 MB downloaded in 0.00 s (29.03 MB/s)
88 11:05:15.768659 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:05:15.768856 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:05:15.768931 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:05:15.769005 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:05:15.769112 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:05:15.769219 saving as /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/nfsrootfs/full.rootfs.tar
95 11:05:15.769272 total size: 120894716 (115 MB)
96 11:05:15.769326 Using unxz to decompress xz
97 11:05:15.770493 progress 0 % (0 MB)
98 11:05:16.101687 progress 5 % (5 MB)
99 11:05:16.432922 progress 10 % (11 MB)
100 11:05:16.768359 progress 15 % (17 MB)
101 11:05:17.084797 progress 20 % (23 MB)
102 11:05:17.384187 progress 25 % (28 MB)
103 11:05:17.720897 progress 30 % (34 MB)
104 11:05:18.036284 progress 35 % (40 MB)
105 11:05:18.204282 progress 40 % (46 MB)
106 11:05:18.386373 progress 45 % (51 MB)
107 11:05:18.685529 progress 50 % (57 MB)
108 11:05:19.034520 progress 55 % (63 MB)
109 11:05:19.365291 progress 60 % (69 MB)
110 11:05:19.697925 progress 65 % (74 MB)
111 11:05:20.038547 progress 70 % (80 MB)
112 11:05:20.400371 progress 75 % (86 MB)
113 11:05:20.724817 progress 80 % (92 MB)
114 11:05:21.053329 progress 85 % (98 MB)
115 11:05:21.382687 progress 90 % (103 MB)
116 11:05:21.695810 progress 95 % (109 MB)
117 11:05:22.042071 progress 100 % (115 MB)
118 11:05:22.047480 115 MB downloaded in 6.28 s (18.36 MB/s)
119 11:05:22.047634 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:05:22.047839 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:05:22.047916 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:05:22.047990 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:05:22.048118 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:05:22.048178 saving as /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/modules/modules.tar
126 11:05:22.048230 total size: 8607984 (8 MB)
127 11:05:22.048283 Using unxz to decompress xz
128 11:05:22.049555 progress 0 % (0 MB)
129 11:05:22.069749 progress 5 % (0 MB)
130 11:05:22.093801 progress 10 % (0 MB)
131 11:05:22.117206 progress 15 % (1 MB)
132 11:05:22.140982 progress 20 % (1 MB)
133 11:05:22.164750 progress 25 % (2 MB)
134 11:05:22.187797 progress 30 % (2 MB)
135 11:05:22.209692 progress 35 % (2 MB)
136 11:05:22.235364 progress 40 % (3 MB)
137 11:05:22.259017 progress 45 % (3 MB)
138 11:05:22.282471 progress 50 % (4 MB)
139 11:05:22.306770 progress 55 % (4 MB)
140 11:05:22.330172 progress 60 % (4 MB)
141 11:05:22.352790 progress 65 % (5 MB)
142 11:05:22.377380 progress 70 % (5 MB)
143 11:05:22.403770 progress 75 % (6 MB)
144 11:05:22.430787 progress 80 % (6 MB)
145 11:05:22.453725 progress 85 % (7 MB)
146 11:05:22.476147 progress 90 % (7 MB)
147 11:05:22.498944 progress 95 % (7 MB)
148 11:05:22.520882 progress 100 % (8 MB)
149 11:05:22.526087 8 MB downloaded in 0.48 s (17.18 MB/s)
150 11:05:22.526235 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:05:22.526441 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:05:22.526518 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 11:05:22.526593 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 11:05:25.942541 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786840/extract-nfsrootfs-171i6dsw
156 11:05:25.942696 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:05:25.942787 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:05:25.942946 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1
159 11:05:25.943059 makedir: /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin
160 11:05:25.943147 makedir: /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/tests
161 11:05:25.943232 makedir: /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/results
162 11:05:25.943314 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-add-keys
163 11:05:25.943439 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-add-sources
164 11:05:25.943555 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-background-process-start
165 11:05:25.943668 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-background-process-stop
166 11:05:25.943813 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-common-functions
167 11:05:25.943926 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-echo-ipv4
168 11:05:25.944038 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-install-packages
169 11:05:25.944176 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-installed-packages
170 11:05:25.944313 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-os-build
171 11:05:25.944429 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-probe-channel
172 11:05:25.944540 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-probe-ip
173 11:05:25.944650 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-target-ip
174 11:05:25.944759 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-target-mac
175 11:05:25.944904 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-target-storage
176 11:05:25.945044 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-test-case
177 11:05:25.945161 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-test-event
178 11:05:25.945284 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-test-feedback
179 11:05:25.945392 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-test-raise
180 11:05:25.945499 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-test-reference
181 11:05:25.945638 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-test-runner
182 11:05:25.945748 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-test-set
183 11:05:25.945857 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-test-shell
184 11:05:25.945967 Updating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-add-keys (debian)
185 11:05:25.946104 Updating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-add-sources (debian)
186 11:05:25.946234 Updating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-install-packages (debian)
187 11:05:25.946365 Updating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-installed-packages (debian)
188 11:05:25.946492 Updating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/bin/lava-os-build (debian)
189 11:05:25.946608 Creating /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/environment
190 11:05:25.946696 LAVA metadata
191 11:05:25.946758 - LAVA_JOB_ID=14786840
192 11:05:25.946814 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:05:25.946904 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 11:05:25.946960 skipped lava-vland-overlay
195 11:05:25.947026 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:05:25.947096 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 11:05:25.947148 skipped lava-multinode-overlay
198 11:05:25.947210 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:05:25.947278 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 11:05:25.947337 Loading test definitions
201 11:05:25.947409 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 11:05:25.947465 Using /lava-14786840 at stage 0
203 11:05:25.947726 uuid=14786840_1.6.2.3.1 testdef=None
204 11:05:25.947804 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:05:25.947877 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 11:05:25.948260 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:05:25.948453 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 11:05:25.948950 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:05:25.949185 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 11:05:25.949684 runner path: /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/0/tests/0_timesync-off test_uuid 14786840_1.6.2.3.1
213 11:05:25.949824 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:05:25.950020 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 11:05:25.950084 Using /lava-14786840 at stage 0
217 11:05:25.950186 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:05:25.950263 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/0/tests/1_kselftest-alsa'
219 11:05:28.685874 Running '/usr/bin/git checkout kernelci.org
220 11:05:28.829652 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:05:28.830160 uuid=14786840_1.6.2.3.5 testdef=None
222 11:05:28.830306 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:05:28.830492 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 11:05:28.831110 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:05:28.831304 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 11:05:28.832151 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:05:28.832357 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 11:05:28.833234 runner path: /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/0/tests/1_kselftest-alsa test_uuid 14786840_1.6.2.3.5
232 11:05:28.833311 BOARD='mt8192-asurada-spherion-r0'
233 11:05:28.833368 BRANCH='cip'
234 11:05:28.833419 SKIPFILE='/dev/null'
235 11:05:28.833469 SKIP_INSTALL='True'
236 11:05:28.833518 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:05:28.833567 TST_CASENAME=''
238 11:05:28.833614 TST_CMDFILES='alsa'
239 11:05:28.833740 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:05:28.833913 Creating lava-test-runner.conf files
242 11:05:28.833967 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786840/lava-overlay-767n6yd1/lava-14786840/0 for stage 0
243 11:05:28.834044 - 0_timesync-off
244 11:05:28.834104 - 1_kselftest-alsa
245 11:05:28.834201 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:05:28.834306 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 11:05:36.257190 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:05:36.257312 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 11:05:36.257399 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:05:36.257491 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 11:05:36.257567 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 11:05:36.414766 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:05:36.414904 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 11:05:36.414988 extracting modules file /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786840/extract-nfsrootfs-171i6dsw
255 11:05:36.710221 extracting modules file /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786840/extract-overlay-ramdisk-eic82qjy/ramdisk
256 11:05:37.034534 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 11:05:37.034664 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 11:05:37.034752 [common] Applying overlay to NFS
259 11:05:37.034815 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786840/compress-overlay-cqudcuy1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786840/extract-nfsrootfs-171i6dsw
260 11:05:37.913717 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:05:37.913905 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 11:05:37.914004 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:05:37.914084 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 11:05:37.914152 Building ramdisk /var/lib/lava/dispatcher/tmp/14786840/extract-overlay-ramdisk-eic82qjy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786840/extract-overlay-ramdisk-eic82qjy/ramdisk
265 11:05:38.328709 >> 129845 blocks
266 11:05:40.396451 rename /var/lib/lava/dispatcher/tmp/14786840/extract-overlay-ramdisk-eic82qjy/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/ramdisk/ramdisk.cpio.gz
267 11:05:40.396615 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:05:40.396715 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 11:05:40.396797 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 11:05:40.396870 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/kernel/Image']
271 11:05:53.938293 Returned 0 in 13 seconds
272 11:05:53.938461 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/kernel/image.itb
273 11:05:54.429617 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:05:54.429745 output: Created: Wed Jul 10 12:05:54 2024
275 11:05:54.429807 output: Image 0 (kernel-1)
276 11:05:54.429861 output: Description:
277 11:05:54.429913 output: Created: Wed Jul 10 12:05:54 2024
278 11:05:54.429964 output: Type: Kernel Image
279 11:05:54.430014 output: Compression: lzma compressed
280 11:05:54.430066 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
281 11:05:54.430115 output: Architecture: AArch64
282 11:05:54.430162 output: OS: Linux
283 11:05:54.430208 output: Load Address: 0x00000000
284 11:05:54.430255 output: Entry Point: 0x00000000
285 11:05:54.430303 output: Hash algo: crc32
286 11:05:54.430351 output: Hash value: 9bb85fb9
287 11:05:54.430398 output: Image 1 (fdt-1)
288 11:05:54.430444 output: Description: mt8192-asurada-spherion-r0
289 11:05:54.430492 output: Created: Wed Jul 10 12:05:54 2024
290 11:05:54.430539 output: Type: Flat Device Tree
291 11:05:54.430586 output: Compression: uncompressed
292 11:05:54.430632 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:05:54.430680 output: Architecture: AArch64
294 11:05:54.430727 output: Hash algo: crc32
295 11:05:54.430773 output: Hash value: 0f8e4d2e
296 11:05:54.430818 output: Image 2 (ramdisk-1)
297 11:05:54.430864 output: Description: unavailable
298 11:05:54.430911 output: Created: Wed Jul 10 12:05:54 2024
299 11:05:54.430957 output: Type: RAMDisk Image
300 11:05:54.431003 output: Compression: uncompressed
301 11:05:54.431050 output: Data Size: 18709345 Bytes = 18270.84 KiB = 17.84 MiB
302 11:05:54.431096 output: Architecture: AArch64
303 11:05:54.431142 output: OS: Linux
304 11:05:54.431188 output: Load Address: unavailable
305 11:05:54.431234 output: Entry Point: unavailable
306 11:05:54.431280 output: Hash algo: crc32
307 11:05:54.431326 output: Hash value: 4149d564
308 11:05:54.431372 output: Default Configuration: 'conf-1'
309 11:05:54.431417 output: Configuration 0 (conf-1)
310 11:05:54.431462 output: Description: mt8192-asurada-spherion-r0
311 11:05:54.431508 output: Kernel: kernel-1
312 11:05:54.431554 output: Init Ramdisk: ramdisk-1
313 11:05:54.431600 output: FDT: fdt-1
314 11:05:54.431646 output: Loadables: kernel-1
315 11:05:54.431692 output:
316 11:05:54.431788 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:05:54.431859 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:05:54.431932 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 11:05:54.432010 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 11:05:54.432065 No LXC device requested
321 11:05:54.432128 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:05:54.432196 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 11:05:54.432260 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:05:54.432313 Checking files for TFTP limit of 4294967296 bytes.
325 11:05:54.432663 end: 1 tftp-deploy (duration 00:00:39) [common]
326 11:05:54.432748 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:05:54.432824 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:05:54.432910 substitutions:
329 11:05:54.432999 - {DTB}: 14786840/tftp-deploy-vj02v5np/dtb/mt8192-asurada-spherion-r0.dtb
330 11:05:54.433087 - {INITRD}: 14786840/tftp-deploy-vj02v5np/ramdisk/ramdisk.cpio.gz
331 11:05:54.433201 - {KERNEL}: 14786840/tftp-deploy-vj02v5np/kernel/Image
332 11:05:54.433254 - {LAVA_MAC}: None
333 11:05:54.433305 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786840/extract-nfsrootfs-171i6dsw
334 11:05:54.433355 - {NFS_SERVER_IP}: 192.168.201.1
335 11:05:54.433404 - {PRESEED_CONFIG}: None
336 11:05:54.433458 - {PRESEED_LOCAL}: None
337 11:05:54.433507 - {RAMDISK}: 14786840/tftp-deploy-vj02v5np/ramdisk/ramdisk.cpio.gz
338 11:05:54.433554 - {ROOT_PART}: None
339 11:05:54.433601 - {ROOT}: None
340 11:05:54.433649 - {SERVER_IP}: 192.168.201.1
341 11:05:54.433696 - {TEE}: None
342 11:05:54.433743 Parsed boot commands:
343 11:05:54.433789 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:05:54.433924 Parsed boot commands: tftpboot 192.168.201.1 14786840/tftp-deploy-vj02v5np/kernel/image.itb 14786840/tftp-deploy-vj02v5np/kernel/cmdline
345 11:05:54.434000 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:05:54.434071 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:05:54.434141 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:05:54.434209 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:05:54.434262 Not connected, no need to disconnect.
350 11:05:54.434326 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:05:54.434391 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:05:54.434444 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 11:05:54.437267 Setting prompt string to ['lava-test: # ']
354 11:05:54.437567 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:05:54.437653 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:05:54.437743 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:05:54.437818 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:05:54.437985 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=reboot']
359 11:06:03.640599 >> Command sent successfully.
360 11:06:03.655549 Returned 0 in 9 seconds
361 11:06:03.656161 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:06:03.657185 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:06:03.657623 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:06:03.658003 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:06:03.658285 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:06:03.658576 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:06:03.660105 [Enter `^Ec?' for help]
369 11:06:05.235319
370 11:06:05.235793
371 11:06:05.236100 F0: 102B 0000
372 11:06:05.236412
373 11:06:05.236678 F3: 1001 0000 [0200]
374 11:06:05.239038
375 11:06:05.239427 F3: 1001 0000
376 11:06:05.239831
377 11:06:05.240178 F7: 102D 0000
378 11:06:05.240613
379 11:06:05.242279 F1: 0000 0000
380 11:06:05.242668
381 11:06:05.242965 V0: 0000 0000 [0001]
382 11:06:05.243239
383 11:06:05.243500 00: 0007 8000
384 11:06:05.243768
385 11:06:05.246117 01: 0000 0000
386 11:06:05.246509
387 11:06:05.246805 BP: 0C00 0209 [0000]
388 11:06:05.247080
389 11:06:05.250200 G0: 1182 0000
390 11:06:05.250583
391 11:06:05.250880 EC: 0000 0021 [4000]
392 11:06:05.251218
393 11:06:05.253917 S7: 0000 0000 [0000]
394 11:06:05.254302
395 11:06:05.254601 CC: 0000 0000 [0001]
396 11:06:05.254876
397 11:06:05.256830 T0: 0000 0040 [010F]
398 11:06:05.257242
399 11:06:05.257546 Jump to BL
400 11:06:05.257821
401 11:06:05.282361
402 11:06:05.282879
403 11:06:05.289503 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:06:05.292917 ARM64: Exception handlers installed.
405 11:06:05.296638 ARM64: Testing exception
406 11:06:05.299875 ARM64: Done test exception
407 11:06:05.306094 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:06:05.316238 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:06:05.322502 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:06:05.332928 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:06:05.339921 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:06:05.349960 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:06:05.359564 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:06:05.366625 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:06:05.385048 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:06:05.388926 WDT: Last reset was cold boot
417 11:06:05.392203 SPI1(PAD0) initialized at 2873684 Hz
418 11:06:05.395183 SPI5(PAD0) initialized at 992727 Hz
419 11:06:05.398300 VBOOT: Loading verstage.
420 11:06:05.404966 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:06:05.408663 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:06:05.411755 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:06:05.415001 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:06:05.422871 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:06:05.429255 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:06:05.440264 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
427 11:06:05.440662
428 11:06:05.441050
429 11:06:05.449928 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:06:05.453591 ARM64: Exception handlers installed.
431 11:06:05.456384 ARM64: Testing exception
432 11:06:05.456782 ARM64: Done test exception
433 11:06:05.463709 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:06:05.466417 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:06:05.481227 Probing TPM: . done!
436 11:06:05.481701 TPM ready after 0 ms
437 11:06:05.487887 Connected to device vid:did:rid of 1ae0:0028:00
438 11:06:05.497698 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
439 11:06:05.533554 Initialized TPM device CR50 revision 0
440 11:06:05.545106 tlcl_send_startup: Startup return code is 0
441 11:06:05.545237 TPM: setup succeeded
442 11:06:05.556429 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:06:05.565059 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:06:05.575535 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:06:05.584802 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:06:05.587752 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:06:05.591143 in-header: 03 07 00 00 08 00 00 00
448 11:06:05.594558 in-data: aa e4 47 04 13 02 00 00
449 11:06:05.597708 Chrome EC: UHEPI supported
450 11:06:05.604471 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:06:05.607788 in-header: 03 a9 00 00 08 00 00 00
452 11:06:05.611301 in-data: 84 60 60 08 00 00 00 00
453 11:06:05.611395 Phase 1
454 11:06:05.614319 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:06:05.621257 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:06:05.627899 VB2:vb2_check_recovery() Recovery was requested manually
457 11:06:05.631489 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:06:05.634657 Recovery requested (1009000e)
459 11:06:05.642633 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:06:05.648118 tlcl_extend: response is 0
461 11:06:05.658440 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:06:05.662008 tlcl_extend: response is 0
463 11:06:05.668428 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:06:05.688677 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 11:06:05.695397 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:06:05.695487
467 11:06:05.695564
468 11:06:05.705442 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:06:05.708946 ARM64: Exception handlers installed.
470 11:06:05.712212 ARM64: Testing exception
471 11:06:05.712294 ARM64: Done test exception
472 11:06:05.734568 pmic_efuse_setting: Set efuses in 11 msecs
473 11:06:05.738444 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:06:05.742278 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:06:05.749301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:06:05.752918 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:06:05.759734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:06:05.763115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:06:05.766598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:06:05.773533 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:06:05.776778 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:06:05.783618 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:06:05.786534 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:06:05.789654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:06:05.796461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:06:05.799723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:06:05.806728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:06:05.813422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:06:05.816597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:06:05.822963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:06:05.829869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:06:05.836687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:06:05.839821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:06:05.846489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:06:05.852979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:06:05.856258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:06:05.862821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:06:05.866328 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:06:05.872836 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:06:05.879640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:06:05.883186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:06:05.889265 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:06:05.892702 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:06:05.899533 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:06:05.903115 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:06:05.909419 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:06:05.913006 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:06:05.919719 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:06:05.922867 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:06:05.929448 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:06:05.932513 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:06:05.935950 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:06:05.943323 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:06:05.946561 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:06:05.949972 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:06:05.956399 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:06:05.960155 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:06:05.963999 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:06:05.969761 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:06:05.973444 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:06:05.976836 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:06:05.979563 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:06:05.986404 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:06:05.989931 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:06:05.996394 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:06:06.006334 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:06:06.009960 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:06:06.019954 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:06:06.026627 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:06:06.033027 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:06:06.036329 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:06:06.039489 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:06:06.047001 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 11:06:06.053582 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:06:06.057212 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 11:06:06.059981 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:06:06.071821 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 11:06:06.081093 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 11:06:06.090063 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 11:06:06.099951 [RTC]rtc_get_frequency_meter,154: input=13, output=822
541 11:06:06.109319 [RTC]rtc_get_frequency_meter,154: input=12, output=806
542 11:06:06.118758 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 11:06:06.128822 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 11:06:06.131540 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 11:06:06.138750 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 11:06:06.141798 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:06:06.145301 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 11:06:06.152444 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:06:06.155662 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 11:06:06.158831 ADC[4]: Raw value=904802 ID=7
551 11:06:06.158908 ADC[3]: Raw value=213916 ID=1
552 11:06:06.162175 RAM Code: 0x71
553 11:06:06.165248 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:06:06.172428 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:06:06.178577 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:06:06.185087 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:06:06.188550 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:06:06.191807 in-header: 03 07 00 00 08 00 00 00
559 11:06:06.195179 in-data: aa e4 47 04 13 02 00 00
560 11:06:06.198519 Chrome EC: UHEPI supported
561 11:06:06.205352 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:06:06.208503 in-header: 03 a9 00 00 08 00 00 00
563 11:06:06.211989 in-data: 84 60 60 08 00 00 00 00
564 11:06:06.215502 MRC: failed to locate region type 0.
565 11:06:06.222222 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:06:06.225034 DRAM-K: Running full calibration
567 11:06:06.232041 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:06:06.232271 header.status = 0x0
569 11:06:06.235085 header.version = 0x6 (expected: 0x6)
570 11:06:06.238724 header.size = 0xd00 (expected: 0xd00)
571 11:06:06.241962 header.flags = 0x0
572 11:06:06.248485 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:06:06.265203 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 11:06:06.272075 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:06:06.275017 dram_init: ddr_geometry: 2
576 11:06:06.278447 [EMI] MDL number = 2
577 11:06:06.278601 [EMI] Get MDL freq = 0
578 11:06:06.281305 dram_init: ddr_type: 0
579 11:06:06.281469 is_discrete_lpddr4: 1
580 11:06:06.284636 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:06:06.284822
582 11:06:06.284965
583 11:06:06.288733 [Bian_co] ETT version 0.0.0.1
584 11:06:06.295038 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:06:06.295166
586 11:06:06.298388 dramc_set_vcore_voltage set vcore to 650000
587 11:06:06.298502 Read voltage for 800, 4
588 11:06:06.301908 Vio18 = 0
589 11:06:06.301993 Vcore = 650000
590 11:06:06.302059 Vdram = 0
591 11:06:06.304815 Vddq = 0
592 11:06:06.304915 Vmddr = 0
593 11:06:06.308535 dram_init: config_dvfs: 1
594 11:06:06.311834 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:06:06.318387 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:06:06.321435 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 11:06:06.324872 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 11:06:06.328320 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 11:06:06.331730 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 11:06:06.334852 MEM_TYPE=3, freq_sel=18
601 11:06:06.338692 sv_algorithm_assistance_LP4_1600
602 11:06:06.341505 ============ PULL DRAM RESETB DOWN ============
603 11:06:06.345487 ========== PULL DRAM RESETB DOWN end =========
604 11:06:06.351622 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:06:06.355124 ===================================
606 11:06:06.358265 LPDDR4 DRAM CONFIGURATION
607 11:06:06.361541 ===================================
608 11:06:06.361676 EX_ROW_EN[0] = 0x0
609 11:06:06.365067 EX_ROW_EN[1] = 0x0
610 11:06:06.365229 LP4Y_EN = 0x0
611 11:06:06.368182 WORK_FSP = 0x0
612 11:06:06.368354 WL = 0x2
613 11:06:06.371914 RL = 0x2
614 11:06:06.372079 BL = 0x2
615 11:06:06.374833 RPST = 0x0
616 11:06:06.375035 RD_PRE = 0x0
617 11:06:06.378351 WR_PRE = 0x1
618 11:06:06.378597 WR_PST = 0x0
619 11:06:06.381776 DBI_WR = 0x0
620 11:06:06.382038 DBI_RD = 0x0
621 11:06:06.384842 OTF = 0x1
622 11:06:06.388731 ===================================
623 11:06:06.391630 ===================================
624 11:06:06.392025 ANA top config
625 11:06:06.394966 ===================================
626 11:06:06.398889 DLL_ASYNC_EN = 0
627 11:06:06.402338 ALL_SLAVE_EN = 1
628 11:06:06.402720 NEW_RANK_MODE = 1
629 11:06:06.406156 DLL_IDLE_MODE = 1
630 11:06:06.409652 LP45_APHY_COMB_EN = 1
631 11:06:06.413106 TX_ODT_DIS = 1
632 11:06:06.413533 NEW_8X_MODE = 1
633 11:06:06.417293 ===================================
634 11:06:06.420714 ===================================
635 11:06:06.424097 data_rate = 1600
636 11:06:06.427657 CKR = 1
637 11:06:06.428157 DQ_P2S_RATIO = 8
638 11:06:06.431342 ===================================
639 11:06:06.435175 CA_P2S_RATIO = 8
640 11:06:06.438081 DQ_CA_OPEN = 0
641 11:06:06.441675 DQ_SEMI_OPEN = 0
642 11:06:06.445102 CA_SEMI_OPEN = 0
643 11:06:06.445526 CA_FULL_RATE = 0
644 11:06:06.448321 DQ_CKDIV4_EN = 1
645 11:06:06.451646 CA_CKDIV4_EN = 1
646 11:06:06.454857 CA_PREDIV_EN = 0
647 11:06:06.457991 PH8_DLY = 0
648 11:06:06.461754 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:06:06.462141 DQ_AAMCK_DIV = 4
650 11:06:06.465307 CA_AAMCK_DIV = 4
651 11:06:06.468027 CA_ADMCK_DIV = 4
652 11:06:06.472057 DQ_TRACK_CA_EN = 0
653 11:06:06.474781 CA_PICK = 800
654 11:06:06.477990 CA_MCKIO = 800
655 11:06:06.478425 MCKIO_SEMI = 0
656 11:06:06.481665 PLL_FREQ = 3068
657 11:06:06.485328 DQ_UI_PI_RATIO = 32
658 11:06:06.488755 CA_UI_PI_RATIO = 0
659 11:06:06.491918 ===================================
660 11:06:06.494873 ===================================
661 11:06:06.498361 memory_type:LPDDR4
662 11:06:06.498756 GP_NUM : 10
663 11:06:06.502031 SRAM_EN : 1
664 11:06:06.504687 MD32_EN : 0
665 11:06:06.507996 ===================================
666 11:06:06.508386 [ANA_INIT] >>>>>>>>>>>>>>
667 11:06:06.511304 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:06:06.515159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:06:06.518500 ===================================
670 11:06:06.521775 data_rate = 1600,PCW = 0X7600
671 11:06:06.524968 ===================================
672 11:06:06.528215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:06:06.534787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:06:06.538396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:06:06.544974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:06:06.548118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:06:06.551566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:06:06.552050 [ANA_INIT] flow start
679 11:06:06.554934 [ANA_INIT] PLL >>>>>>>>
680 11:06:06.557725 [ANA_INIT] PLL <<<<<<<<
681 11:06:06.558150 [ANA_INIT] MIDPI >>>>>>>>
682 11:06:06.561758 [ANA_INIT] MIDPI <<<<<<<<
683 11:06:06.565356 [ANA_INIT] DLL >>>>>>>>
684 11:06:06.565749 [ANA_INIT] flow end
685 11:06:06.571453 ============ LP4 DIFF to SE enter ============
686 11:06:06.574771 ============ LP4 DIFF to SE exit ============
687 11:06:06.578391 [ANA_INIT] <<<<<<<<<<<<<
688 11:06:06.581645 [Flow] Enable top DCM control >>>>>
689 11:06:06.584937 [Flow] Enable top DCM control <<<<<
690 11:06:06.585504 Enable DLL master slave shuffle
691 11:06:06.591202 ==============================================================
692 11:06:06.594662 Gating Mode config
693 11:06:06.598143 ==============================================================
694 11:06:06.601341 Config description:
695 11:06:06.611555 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:06:06.617907 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:06:06.621091 SELPH_MODE 0: By rank 1: By Phase
698 11:06:06.627760 ==============================================================
699 11:06:06.631667 GAT_TRACK_EN = 1
700 11:06:06.634235 RX_GATING_MODE = 2
701 11:06:06.637916 RX_GATING_TRACK_MODE = 2
702 11:06:06.641191 SELPH_MODE = 1
703 11:06:06.641574 PICG_EARLY_EN = 1
704 11:06:06.644491 VALID_LAT_VALUE = 1
705 11:06:06.651546 ==============================================================
706 11:06:06.654127 Enter into Gating configuration >>>>
707 11:06:06.658022 Exit from Gating configuration <<<<
708 11:06:06.660545 Enter into DVFS_PRE_config >>>>>
709 11:06:06.670776 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:06:06.673889 Exit from DVFS_PRE_config <<<<<
711 11:06:06.677501 Enter into PICG configuration >>>>
712 11:06:06.680587 Exit from PICG configuration <<<<
713 11:06:06.683909 [RX_INPUT] configuration >>>>>
714 11:06:06.687253 [RX_INPUT] configuration <<<<<
715 11:06:06.690951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:06:06.697252 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:06:06.703705 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:06:06.710742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:06:06.717129 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:06:06.723998 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:06:06.726998 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:06:06.730579 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:06:06.733828 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:06:06.740669 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:06:06.743929 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:06:06.747393 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:06:06.750525 ===================================
728 11:06:06.753577 LPDDR4 DRAM CONFIGURATION
729 11:06:06.757214 ===================================
730 11:06:06.757499 EX_ROW_EN[0] = 0x0
731 11:06:06.760352 EX_ROW_EN[1] = 0x0
732 11:06:06.760703 LP4Y_EN = 0x0
733 11:06:06.763857 WORK_FSP = 0x0
734 11:06:06.764138 WL = 0x2
735 11:06:06.766850 RL = 0x2
736 11:06:06.770363 BL = 0x2
737 11:06:06.770647 RPST = 0x0
738 11:06:06.773263 RD_PRE = 0x0
739 11:06:06.773546 WR_PRE = 0x1
740 11:06:06.776756 WR_PST = 0x0
741 11:06:06.777037 DBI_WR = 0x0
742 11:06:06.780025 DBI_RD = 0x0
743 11:06:06.780308 OTF = 0x1
744 11:06:06.783244 ===================================
745 11:06:06.786844 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:06:06.793350 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:06:06.796753 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:06:06.800393 ===================================
749 11:06:06.803379 LPDDR4 DRAM CONFIGURATION
750 11:06:06.806951 ===================================
751 11:06:06.807259 EX_ROW_EN[0] = 0x10
752 11:06:06.810043 EX_ROW_EN[1] = 0x0
753 11:06:06.810316 LP4Y_EN = 0x0
754 11:06:06.812962 WORK_FSP = 0x0
755 11:06:06.813351 WL = 0x2
756 11:06:06.816454 RL = 0x2
757 11:06:06.816772 BL = 0x2
758 11:06:06.820156 RPST = 0x0
759 11:06:06.820427 RD_PRE = 0x0
760 11:06:06.823423 WR_PRE = 0x1
761 11:06:06.826797 WR_PST = 0x0
762 11:06:06.827148 DBI_WR = 0x0
763 11:06:06.830545 DBI_RD = 0x0
764 11:06:06.830895 OTF = 0x1
765 11:06:06.833483 ===================================
766 11:06:06.840015 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:06:06.843266 nWR fixed to 40
768 11:06:06.846801 [ModeRegInit_LP4] CH0 RK0
769 11:06:06.847074 [ModeRegInit_LP4] CH0 RK1
770 11:06:06.850183 [ModeRegInit_LP4] CH1 RK0
771 11:06:06.852997 [ModeRegInit_LP4] CH1 RK1
772 11:06:06.853072 match AC timing 13
773 11:06:06.859803 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:06:06.863011 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:06:06.866812 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:06:06.873261 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:06:06.876623 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:06:06.876711 [EMI DOE] emi_dcm 0
779 11:06:06.883170 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:06:06.883251 ==
781 11:06:06.886548 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:06:06.889825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:06:06.889907 ==
784 11:06:06.896755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:06:06.903195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:06:06.911271 [CA 0] Center 37 (7~68) winsize 62
787 11:06:06.914166 [CA 1] Center 37 (6~68) winsize 63
788 11:06:06.918058 [CA 2] Center 34 (4~65) winsize 62
789 11:06:06.921104 [CA 3] Center 34 (4~65) winsize 62
790 11:06:06.924634 [CA 4] Center 33 (3~64) winsize 62
791 11:06:06.927842 [CA 5] Center 33 (3~64) winsize 62
792 11:06:06.928096
793 11:06:06.931079 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:06:06.931370
795 11:06:06.934499 [CATrainingPosCal] consider 1 rank data
796 11:06:06.937734 u2DelayCellTimex100 = 270/100 ps
797 11:06:06.941667 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 11:06:06.944527 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 11:06:06.948342 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:06:06.955135 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:06:06.958129 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:06:06.961213 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:06:06.961602
804 11:06:06.964959 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:06:06.965461
806 11:06:06.968046 [CBTSetCACLKResult] CA Dly = 33
807 11:06:06.968429 CS Dly: 5 (0~36)
808 11:06:06.968727 ==
809 11:06:06.971189 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:06:06.978473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:06:06.978943 ==
812 11:06:06.982030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:06:06.988578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:06:06.997303 [CA 0] Center 38 (7~69) winsize 63
815 11:06:07.001028 [CA 1] Center 37 (7~68) winsize 62
816 11:06:07.003909 [CA 2] Center 35 (4~66) winsize 63
817 11:06:07.007446 [CA 3] Center 34 (4~65) winsize 62
818 11:06:07.010828 [CA 4] Center 34 (3~65) winsize 63
819 11:06:07.014765 [CA 5] Center 33 (3~64) winsize 62
820 11:06:07.015150
821 11:06:07.017481 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:06:07.017866
823 11:06:07.020809 [CATrainingPosCal] consider 2 rank data
824 11:06:07.024076 u2DelayCellTimex100 = 270/100 ps
825 11:06:07.027498 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:06:07.030769 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:06:07.037739 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:06:07.040802 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:06:07.044276 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:06:07.047355 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:06:07.047740
832 11:06:07.050989 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:06:07.051375
834 11:06:07.054325 [CBTSetCACLKResult] CA Dly = 33
835 11:06:07.054793 CS Dly: 6 (0~38)
836 11:06:07.055097
837 11:06:07.057255 ----->DramcWriteLeveling(PI) begin...
838 11:06:07.060383 ==
839 11:06:07.063851 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:06:07.067472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:06:07.067863 ==
842 11:06:07.070741 Write leveling (Byte 0): 32 => 32
843 11:06:07.073919 Write leveling (Byte 1): 27 => 27
844 11:06:07.074305 DramcWriteLeveling(PI) end<-----
845 11:06:07.077499
846 11:06:07.077883 ==
847 11:06:07.080715 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:06:07.084315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:06:07.084708 ==
850 11:06:07.087396 [Gating] SW mode calibration
851 11:06:07.094048 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:06:07.097426 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:06:07.104209 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:06:07.107778 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:06:07.111623 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 11:06:07.118335 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:06:07.120761 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:06:07.124468 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:06:07.130753 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:06:07.134392 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:06:07.137735 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:06:07.144450 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:06:07.147992 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:06:07.151148 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:06:07.157673 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:06:07.160901 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:06:07.164151 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:06:07.170743 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:06:07.173781 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:06:07.177195 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 11:06:07.180797 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
872 11:06:07.187550 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:06:07.190517 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:06:07.193963 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:06:07.200700 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:06:07.204159 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:06:07.207661 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:06:07.214126 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:06:07.217098 0 9 8 | B1->B0 | 2323 3030 | 1 0 | (1 1) (0 0)
880 11:06:07.220820 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:06:07.227047 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:06:07.230384 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:06:07.233676 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:06:07.240570 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:06:07.243795 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:06:07.247696 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
887 11:06:07.254138 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
888 11:06:07.257040 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 11:06:07.260709 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:06:07.267216 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:06:07.270512 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:06:07.273716 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:06:07.280099 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:06:07.283477 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
895 11:06:07.287021 0 11 8 | B1->B0 | 2b2a 4545 | 1 0 | (0 0) (0 0)
896 11:06:07.293711 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
897 11:06:07.296656 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:06:07.300518 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:06:07.303804 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:06:07.310068 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:06:07.313692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:06:07.316736 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:06:07.323621 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 11:06:07.326598 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 11:06:07.330093 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:06:07.336685 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:06:07.340047 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:06:07.343269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:06:07.350418 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:06:07.353624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:06:07.356680 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:06:07.363264 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:06:07.366708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:06:07.370010 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:06:07.376623 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:06:07.379529 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:06:07.382970 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:06:07.389901 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:06:07.393058 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
920 11:06:07.396623 Total UI for P1: 0, mck2ui 16
921 11:06:07.400045 best dqsien dly found for B0: ( 0, 14, 6)
922 11:06:07.402828 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 11:06:07.406395 Total UI for P1: 0, mck2ui 16
924 11:06:07.409759 best dqsien dly found for B1: ( 0, 14, 10)
925 11:06:07.412798 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 11:06:07.416319 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 11:06:07.416564
928 11:06:07.422776 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 11:06:07.426127 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 11:06:07.426356 [Gating] SW calibration Done
931 11:06:07.429489 ==
932 11:06:07.433028 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:06:07.436211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:06:07.436470 ==
935 11:06:07.436678 RX Vref Scan: 0
936 11:06:07.436867
937 11:06:07.439939 RX Vref 0 -> 0, step: 1
938 11:06:07.440188
939 11:06:07.442847 RX Delay -130 -> 252, step: 16
940 11:06:07.446227 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 11:06:07.450190 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 11:06:07.453337 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 11:06:07.459354 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 11:06:07.462728 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 11:06:07.466096 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 11:06:07.469731 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 11:06:07.472831 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 11:06:07.479433 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 11:06:07.482628 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
950 11:06:07.486360 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 11:06:07.489434 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 11:06:07.496419 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 11:06:07.499361 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 11:06:07.502374 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:06:07.506037 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 11:06:07.506217 ==
957 11:06:07.509081 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:06:07.512531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:06:07.515995 ==
960 11:06:07.516167 DQS Delay:
961 11:06:07.516314 DQS0 = 0, DQS1 = 0
962 11:06:07.519488 DQM Delay:
963 11:06:07.519657 DQM0 = 87, DQM1 = 77
964 11:06:07.522827 DQ Delay:
965 11:06:07.526097 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 11:06:07.526284 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
967 11:06:07.529366 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
968 11:06:07.532826 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 11:06:07.535699
970 11:06:07.535865
971 11:06:07.536019 ==
972 11:06:07.538960 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:06:07.542423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:06:07.542604 ==
975 11:06:07.542758
976 11:06:07.542904
977 11:06:07.545628 TX Vref Scan disable
978 11:06:07.545792 == TX Byte 0 ==
979 11:06:07.552283 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 11:06:07.555660 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 11:06:07.555837 == TX Byte 1 ==
982 11:06:07.562462 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
983 11:06:07.565828 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
984 11:06:07.566063 ==
985 11:06:07.569132 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:06:07.572440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:06:07.572731 ==
988 11:06:07.586850 TX Vref=22, minBit 1, minWin=26, winSum=437
989 11:06:07.590207 TX Vref=24, minBit 1, minWin=26, winSum=441
990 11:06:07.593358 TX Vref=26, minBit 0, minWin=27, winSum=445
991 11:06:07.596900 TX Vref=28, minBit 2, minWin=27, winSum=451
992 11:06:07.600149 TX Vref=30, minBit 0, minWin=28, winSum=453
993 11:06:07.603344 TX Vref=32, minBit 2, minWin=27, winSum=449
994 11:06:07.609755 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
995 11:06:07.609944
996 11:06:07.613261 Final TX Range 1 Vref 30
997 11:06:07.613459
998 11:06:07.613609 ==
999 11:06:07.617096 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:06:07.620099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:06:07.620290 ==
1002 11:06:07.620444
1003 11:06:07.623393
1004 11:06:07.623566 TX Vref Scan disable
1005 11:06:07.626560 == TX Byte 0 ==
1006 11:06:07.629705 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 11:06:07.633392 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 11:06:07.636632 == TX Byte 1 ==
1009 11:06:07.640011 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1010 11:06:07.646564 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1011 11:06:07.646781
1012 11:06:07.646994 [DATLAT]
1013 11:06:07.647191 Freq=800, CH0 RK0
1014 11:06:07.647385
1015 11:06:07.649684 DATLAT Default: 0xa
1016 11:06:07.649903 0, 0xFFFF, sum = 0
1017 11:06:07.652958 1, 0xFFFF, sum = 0
1018 11:06:07.653202 2, 0xFFFF, sum = 0
1019 11:06:07.656363 3, 0xFFFF, sum = 0
1020 11:06:07.659604 4, 0xFFFF, sum = 0
1021 11:06:07.659820 5, 0xFFFF, sum = 0
1022 11:06:07.662966 6, 0xFFFF, sum = 0
1023 11:06:07.663184 7, 0xFFFF, sum = 0
1024 11:06:07.666248 8, 0xFFFF, sum = 0
1025 11:06:07.666465 9, 0x0, sum = 1
1026 11:06:07.666678 10, 0x0, sum = 2
1027 11:06:07.669789 11, 0x0, sum = 3
1028 11:06:07.670008 12, 0x0, sum = 4
1029 11:06:07.673108 best_step = 10
1030 11:06:07.673207
1031 11:06:07.673300 ==
1032 11:06:07.676377 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:06:07.679783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:06:07.679861 ==
1035 11:06:07.682519 RX Vref Scan: 1
1036 11:06:07.682596
1037 11:06:07.686392 Set Vref Range= 32 -> 127
1038 11:06:07.686467
1039 11:06:07.686527 RX Vref 32 -> 127, step: 1
1040 11:06:07.686587
1041 11:06:07.689552 RX Delay -95 -> 252, step: 8
1042 11:06:07.689616
1043 11:06:07.692746 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:06:07.696092 [Byte1]: 32
1045 11:06:07.696159
1046 11:06:07.699294 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:06:07.702591 [Byte1]: 33
1048 11:06:07.706980
1049 11:06:07.707042 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:06:07.709872 [Byte1]: 34
1051 11:06:07.714147
1052 11:06:07.714210 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:06:07.717607 [Byte1]: 35
1054 11:06:07.722008
1055 11:06:07.722071 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:06:07.725041 [Byte1]: 36
1057 11:06:07.729344
1058 11:06:07.729410 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:06:07.732596 [Byte1]: 37
1060 11:06:07.737269
1061 11:06:07.737332 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:06:07.740645 [Byte1]: 38
1063 11:06:07.744724
1064 11:06:07.744787 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:06:07.747736 [Byte1]: 39
1066 11:06:07.752232
1067 11:06:07.752294 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:06:07.755823 [Byte1]: 40
1069 11:06:07.760591
1070 11:06:07.760653 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:06:07.763060 [Byte1]: 41
1072 11:06:07.767686
1073 11:06:07.767753 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:06:07.770574 [Byte1]: 42
1075 11:06:07.775343
1076 11:06:07.775411 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:06:07.778175 [Byte1]: 43
1078 11:06:07.783246
1079 11:06:07.783328 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:06:07.788995 [Byte1]: 44
1081 11:06:07.789063
1082 11:06:07.792455 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:06:07.795549 [Byte1]: 45
1084 11:06:07.795615
1085 11:06:07.798905 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:06:07.802652 [Byte1]: 46
1087 11:06:07.802719
1088 11:06:07.805982 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:06:07.809289 [Byte1]: 47
1090 11:06:07.812900
1091 11:06:07.812963 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:06:07.816637 [Byte1]: 48
1093 11:06:07.820834
1094 11:06:07.820897 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:06:07.823694 [Byte1]: 49
1096 11:06:07.828162
1097 11:06:07.828225 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:06:07.831251 [Byte1]: 50
1099 11:06:07.835622
1100 11:06:07.835684 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:06:07.839263 [Byte1]: 51
1102 11:06:07.843544
1103 11:06:07.843609 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:06:07.846811 [Byte1]: 52
1105 11:06:07.851210
1106 11:06:07.851272 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:06:07.854294 [Byte1]: 53
1108 11:06:07.858758
1109 11:06:07.858821 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:06:07.861757 [Byte1]: 54
1111 11:06:07.866400
1112 11:06:07.866464 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:06:07.869731 [Byte1]: 55
1114 11:06:07.873655
1115 11:06:07.873719 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:06:07.877064 [Byte1]: 56
1117 11:06:07.881709
1118 11:06:07.881772 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:06:07.884487 [Byte1]: 57
1120 11:06:07.889537
1121 11:06:07.889605 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:06:07.892303 [Byte1]: 58
1123 11:06:07.896610
1124 11:06:07.896674 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:06:07.899589 [Byte1]: 59
1126 11:06:07.904335
1127 11:06:07.904400 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:06:07.907669 [Byte1]: 60
1129 11:06:07.911577
1130 11:06:07.911643 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:06:07.915012 [Byte1]: 61
1132 11:06:07.919281
1133 11:06:07.919344 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:06:07.922717 [Byte1]: 62
1135 11:06:07.926882
1136 11:06:07.926950 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:06:07.930519 [Byte1]: 63
1138 11:06:07.934538
1139 11:06:07.934604 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:06:07.937894 [Byte1]: 64
1141 11:06:07.942509
1142 11:06:07.942573 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:06:07.945566 [Byte1]: 65
1144 11:06:07.949767
1145 11:06:07.949831 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:06:07.953031 [Byte1]: 66
1147 11:06:07.957347
1148 11:06:07.957410 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:06:07.960621 [Byte1]: 67
1150 11:06:07.964656
1151 11:06:07.964722 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:06:07.968011 [Byte1]: 68
1153 11:06:07.972287
1154 11:06:07.972350 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:06:07.975950 [Byte1]: 69
1156 11:06:07.980206
1157 11:06:07.980268 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:06:07.983504 [Byte1]: 70
1159 11:06:07.987661
1160 11:06:07.987724 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:06:07.991153 [Byte1]: 71
1162 11:06:07.995315
1163 11:06:07.995385 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:06:07.998645 [Byte1]: 72
1165 11:06:08.003172
1166 11:06:08.003236 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:06:08.006288 [Byte1]: 73
1168 11:06:08.010544
1169 11:06:08.010610 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:06:08.014313 [Byte1]: 74
1171 11:06:08.018359
1172 11:06:08.018425 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:06:08.021266 [Byte1]: 75
1174 11:06:08.025831
1175 11:06:08.025898 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:06:08.029383 [Byte1]: 76
1177 11:06:08.032980
1178 11:06:08.033045 Final RX Vref Byte 0 = 55 to rank0
1179 11:06:08.036514 Final RX Vref Byte 1 = 58 to rank0
1180 11:06:08.040265 Final RX Vref Byte 0 = 55 to rank1
1181 11:06:08.043376 Final RX Vref Byte 1 = 58 to rank1==
1182 11:06:08.046744 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 11:06:08.053417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 11:06:08.053510 ==
1185 11:06:08.053584 DQS Delay:
1186 11:06:08.053652 DQS0 = 0, DQS1 = 0
1187 11:06:08.056513 DQM Delay:
1188 11:06:08.056623 DQM0 = 88, DQM1 = 75
1189 11:06:08.060300 DQ Delay:
1190 11:06:08.063580 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1191 11:06:08.066490 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1192 11:06:08.066657 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1193 11:06:08.073291 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1194 11:06:08.073391
1195 11:06:08.073480
1196 11:06:08.080089 [DQSOSCAuto] RK0, (LSB)MR18= 0x332d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1197 11:06:08.083286 CH0 RK0: MR19=606, MR18=332D
1198 11:06:08.090173 CH0_RK0: MR19=0x606, MR18=0x332D, DQSOSC=396, MR23=63, INC=94, DEC=62
1199 11:06:08.090245
1200 11:06:08.092900 ----->DramcWriteLeveling(PI) begin...
1201 11:06:08.092966 ==
1202 11:06:08.096076 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 11:06:08.099467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 11:06:08.099539 ==
1205 11:06:08.103107 Write leveling (Byte 0): 30 => 30
1206 11:06:08.106381 Write leveling (Byte 1): 29 => 29
1207 11:06:08.109473 DramcWriteLeveling(PI) end<-----
1208 11:06:08.109545
1209 11:06:08.109601 ==
1210 11:06:08.112882 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 11:06:08.116656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 11:06:08.116724 ==
1213 11:06:08.119930 [Gating] SW mode calibration
1214 11:06:08.126397 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 11:06:08.133018 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 11:06:08.136118 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 11:06:08.139349 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 11:06:08.146265 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1219 11:06:08.149274 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:06:08.193512 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:06:08.193798 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:06:08.194232 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:06:08.194315 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:06:08.194557 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:06:08.194654 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:06:08.195271 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:06:08.195537 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:06:08.195639 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:06:08.195738 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:06:08.237875 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:06:08.238132 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:06:08.238405 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:06:08.238507 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1234 11:06:08.238601 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1235 11:06:08.238873 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:06:08.239142 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:06:08.239502 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:06:08.239569 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:06:08.239818 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:06:08.242910 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:06:08.246273 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:06:08.249076 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1243 11:06:08.256170 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1244 11:06:08.259141 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:06:08.262742 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:06:08.269008 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:06:08.272578 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:06:08.275514 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:06:08.282201 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1250 11:06:08.285759 0 10 8 | B1->B0 | 3131 2828 | 1 0 | (0 0) (0 0)
1251 11:06:08.289133 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:06:08.295754 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:06:08.299003 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:06:08.302355 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:06:08.308773 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:06:08.312314 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:06:08.315602 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
1258 11:06:08.322309 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
1259 11:06:08.325797 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:06:08.328691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:06:08.335773 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:06:08.338915 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:06:08.342867 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:06:08.349353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:06:08.352265 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1266 11:06:08.356065 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1267 11:06:08.362098 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:06:08.365600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:06:08.368803 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:06:08.375295 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:06:08.378581 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:06:08.382109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:06:08.389065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:06:08.391755 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:06:08.395673 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:06:08.398872 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:06:08.405510 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:06:08.408787 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:06:08.412359 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:06:08.418919 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:06:08.421960 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1282 11:06:08.425488 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 11:06:08.429457 Total UI for P1: 0, mck2ui 16
1284 11:06:08.432461 best dqsien dly found for B0: ( 0, 14, 4)
1285 11:06:08.438704 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 11:06:08.438945 Total UI for P1: 0, mck2ui 16
1287 11:06:08.445697 best dqsien dly found for B1: ( 0, 14, 6)
1288 11:06:08.448927 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1289 11:06:08.452631 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1290 11:06:08.452984
1291 11:06:08.456123 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 11:06:08.458888 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1293 11:06:08.462234 [Gating] SW calibration Done
1294 11:06:08.462737 ==
1295 11:06:08.465133 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 11:06:08.468490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 11:06:08.468572 ==
1298 11:06:08.471604 RX Vref Scan: 0
1299 11:06:08.471695
1300 11:06:08.471751 RX Vref 0 -> 0, step: 1
1301 11:06:08.471803
1302 11:06:08.475231 RX Delay -130 -> 252, step: 16
1303 11:06:08.478449 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1304 11:06:08.484955 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1305 11:06:08.488214 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1306 11:06:08.491636 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1307 11:06:08.494676 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1308 11:06:08.497956 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1309 11:06:08.505002 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1310 11:06:08.508069 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1311 11:06:08.511321 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1312 11:06:08.514836 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1313 11:06:08.518420 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1314 11:06:08.525216 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1315 11:06:08.528101 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1316 11:06:08.531234 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1317 11:06:08.534748 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1318 11:06:08.541659 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1319 11:06:08.541725 ==
1320 11:06:08.545329 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 11:06:08.547778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 11:06:08.547845 ==
1323 11:06:08.547902 DQS Delay:
1324 11:06:08.551382 DQS0 = 0, DQS1 = 0
1325 11:06:08.551444 DQM Delay:
1326 11:06:08.555068 DQM0 = 86, DQM1 = 77
1327 11:06:08.555126 DQ Delay:
1328 11:06:08.558143 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1329 11:06:08.561543 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1330 11:06:08.564682 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1331 11:06:08.567787 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1332 11:06:08.567848
1333 11:06:08.567899
1334 11:06:08.567952 ==
1335 11:06:08.571372 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 11:06:08.574545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 11:06:08.574609 ==
1338 11:06:08.574661
1339 11:06:08.574714
1340 11:06:08.577830 TX Vref Scan disable
1341 11:06:08.581669 == TX Byte 0 ==
1342 11:06:08.584246 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1343 11:06:08.588109 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1344 11:06:08.591125 == TX Byte 1 ==
1345 11:06:08.594458 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1346 11:06:08.597558 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1347 11:06:08.597617 ==
1348 11:06:08.600832 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 11:06:08.607534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 11:06:08.607597 ==
1351 11:06:08.619306 TX Vref=22, minBit 0, minWin=27, winSum=440
1352 11:06:08.622396 TX Vref=24, minBit 1, minWin=27, winSum=442
1353 11:06:08.626303 TX Vref=26, minBit 0, minWin=27, winSum=445
1354 11:06:08.629213 TX Vref=28, minBit 1, minWin=27, winSum=443
1355 11:06:08.632849 TX Vref=30, minBit 3, minWin=27, winSum=448
1356 11:06:08.638946 TX Vref=32, minBit 2, minWin=27, winSum=445
1357 11:06:08.642327 [TxChooseVref] Worse bit 3, Min win 27, Win sum 448, Final Vref 30
1358 11:06:08.642396
1359 11:06:08.646009 Final TX Range 1 Vref 30
1360 11:06:08.646075
1361 11:06:08.646133 ==
1362 11:06:08.648979 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 11:06:08.652648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 11:06:08.652713 ==
1365 11:06:08.655691
1366 11:06:08.655763
1367 11:06:08.655823 TX Vref Scan disable
1368 11:06:08.659171 == TX Byte 0 ==
1369 11:06:08.662529 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1370 11:06:08.669354 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1371 11:06:08.669418 == TX Byte 1 ==
1372 11:06:08.672415 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1373 11:06:08.678935 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1374 11:06:08.679005
1375 11:06:08.679060 [DATLAT]
1376 11:06:08.679112 Freq=800, CH0 RK1
1377 11:06:08.679162
1378 11:06:08.682387 DATLAT Default: 0xa
1379 11:06:08.682447 0, 0xFFFF, sum = 0
1380 11:06:08.685407 1, 0xFFFF, sum = 0
1381 11:06:08.685473 2, 0xFFFF, sum = 0
1382 11:06:08.688793 3, 0xFFFF, sum = 0
1383 11:06:08.688851 4, 0xFFFF, sum = 0
1384 11:06:08.692344 5, 0xFFFF, sum = 0
1385 11:06:08.696125 6, 0xFFFF, sum = 0
1386 11:06:08.696185 7, 0xFFFF, sum = 0
1387 11:06:08.699353 8, 0xFFFF, sum = 0
1388 11:06:08.699416 9, 0x0, sum = 1
1389 11:06:08.699469 10, 0x0, sum = 2
1390 11:06:08.702379 11, 0x0, sum = 3
1391 11:06:08.702443 12, 0x0, sum = 4
1392 11:06:08.705679 best_step = 10
1393 11:06:08.705739
1394 11:06:08.705790 ==
1395 11:06:08.708929 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 11:06:08.712399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 11:06:08.712474 ==
1398 11:06:08.715564 RX Vref Scan: 0
1399 11:06:08.715625
1400 11:06:08.715677 RX Vref 0 -> 0, step: 1
1401 11:06:08.718944
1402 11:06:08.719013 RX Delay -95 -> 252, step: 8
1403 11:06:08.726193 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1404 11:06:08.729528 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1405 11:06:08.732849 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1406 11:06:08.736156 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1407 11:06:08.739448 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 11:06:08.746083 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 11:06:08.749623 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1410 11:06:08.753099 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 11:06:08.756175 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1412 11:06:08.759787 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1413 11:06:08.766498 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 11:06:08.769392 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1415 11:06:08.772719 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1416 11:06:08.776448 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1417 11:06:08.779753 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 11:06:08.785896 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1419 11:06:08.786330 ==
1420 11:06:08.789462 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 11:06:08.793220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 11:06:08.793676 ==
1423 11:06:08.793976 DQS Delay:
1424 11:06:08.796280 DQS0 = 0, DQS1 = 0
1425 11:06:08.796691 DQM Delay:
1426 11:06:08.799599 DQM0 = 86, DQM1 = 76
1427 11:06:08.799976 DQ Delay:
1428 11:06:08.802783 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1429 11:06:08.805902 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1430 11:06:08.809366 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1431 11:06:08.813116 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1432 11:06:08.813699
1433 11:06:08.814001
1434 11:06:08.822759 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1435 11:06:08.823219 CH0 RK1: MR19=606, MR18=2A27
1436 11:06:08.829205 CH0_RK1: MR19=0x606, MR18=0x2A27, DQSOSC=399, MR23=63, INC=92, DEC=61
1437 11:06:08.832820 [RxdqsGatingPostProcess] freq 800
1438 11:06:08.839296 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 11:06:08.842145 Pre-setting of DQS Precalculation
1440 11:06:08.845763 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 11:06:08.846175 ==
1442 11:06:08.849025 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:06:08.852234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:06:08.855700 ==
1445 11:06:08.858954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 11:06:08.865507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 11:06:08.874401 [CA 0] Center 36 (6~67) winsize 62
1448 11:06:08.878399 [CA 1] Center 37 (6~68) winsize 63
1449 11:06:08.881118 [CA 2] Center 35 (4~66) winsize 63
1450 11:06:08.885019 [CA 3] Center 34 (4~65) winsize 62
1451 11:06:08.887860 [CA 4] Center 35 (4~66) winsize 63
1452 11:06:08.891229 [CA 5] Center 34 (4~65) winsize 62
1453 11:06:08.891610
1454 11:06:08.894463 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 11:06:08.894861
1456 11:06:08.897845 [CATrainingPosCal] consider 1 rank data
1457 11:06:08.900846 u2DelayCellTimex100 = 270/100 ps
1458 11:06:08.904599 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 11:06:08.911196 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1460 11:06:08.914439 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1461 11:06:08.917621 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 11:06:08.921119 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1463 11:06:08.924514 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 11:06:08.924901
1465 11:06:08.927250 CA PerBit enable=1, Macro0, CA PI delay=34
1466 11:06:08.927641
1467 11:06:08.931408 [CBTSetCACLKResult] CA Dly = 34
1468 11:06:08.931867 CS Dly: 4 (0~35)
1469 11:06:08.934111 ==
1470 11:06:08.937779 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 11:06:08.940809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 11:06:08.941240 ==
1473 11:06:08.947538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 11:06:08.950580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 11:06:08.960848 [CA 0] Center 36 (6~67) winsize 62
1476 11:06:08.964553 [CA 1] Center 37 (6~68) winsize 63
1477 11:06:08.967537 [CA 2] Center 35 (4~66) winsize 63
1478 11:06:08.970838 [CA 3] Center 34 (4~65) winsize 62
1479 11:06:08.974068 [CA 4] Center 34 (4~65) winsize 62
1480 11:06:08.976988 [CA 5] Center 34 (4~65) winsize 62
1481 11:06:08.977424
1482 11:06:08.980684 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 11:06:08.981064
1484 11:06:08.984079 [CATrainingPosCal] consider 2 rank data
1485 11:06:08.987243 u2DelayCellTimex100 = 270/100 ps
1486 11:06:08.991378 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 11:06:08.997201 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1488 11:06:09.000169 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1489 11:06:09.003959 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 11:06:09.007447 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1491 11:06:09.010268 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1492 11:06:09.010650
1493 11:06:09.013488 CA PerBit enable=1, Macro0, CA PI delay=34
1494 11:06:09.013888
1495 11:06:09.017104 [CBTSetCACLKResult] CA Dly = 34
1496 11:06:09.017549 CS Dly: 5 (0~37)
1497 11:06:09.017867
1498 11:06:09.023661 ----->DramcWriteLeveling(PI) begin...
1499 11:06:09.024050 ==
1500 11:06:09.027085 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 11:06:09.031174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 11:06:09.031557 ==
1503 11:06:09.033500 Write leveling (Byte 0): 25 => 25
1504 11:06:09.036906 Write leveling (Byte 1): 27 => 27
1505 11:06:09.040065 DramcWriteLeveling(PI) end<-----
1506 11:06:09.040445
1507 11:06:09.040742 ==
1508 11:06:09.043489 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 11:06:09.046631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 11:06:09.046706 ==
1511 11:06:09.049889 [Gating] SW mode calibration
1512 11:06:09.057110 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 11:06:09.063430 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 11:06:09.066893 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 11:06:09.070135 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1516 11:06:09.073696 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1517 11:06:09.079624 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:06:09.082941 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:06:09.086316 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:06:09.093253 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:06:09.096763 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:06:09.100024 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:06:09.106524 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:06:09.110365 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:06:09.112854 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:06:09.119501 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:06:09.122708 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:06:09.126349 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:06:09.133062 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:06:09.136351 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:06:09.139418 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1532 11:06:09.146006 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:06:09.149079 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:06:09.152687 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:06:09.159553 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:06:09.162279 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:06:09.165608 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:06:09.172510 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:06:09.175890 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:06:09.179145 0 9 8 | B1->B0 | 2c2c 3434 | 1 0 | (0 0) (0 0)
1541 11:06:09.185972 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 11:06:09.189366 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 11:06:09.192648 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:06:09.199157 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:06:09.202330 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:06:09.205849 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:06:09.212196 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 1)
1548 11:06:09.215296 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
1549 11:06:09.218658 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:06:09.225374 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:06:09.228947 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:06:09.231944 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:06:09.238628 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:06:09.242022 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:06:09.244879 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1556 11:06:09.251729 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1557 11:06:09.255304 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:06:09.258057 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:06:09.264712 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:06:09.268409 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:06:09.271639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:06:09.278553 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:06:09.281770 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1564 11:06:09.284933 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1565 11:06:09.291686 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:06:09.295256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:06:09.298105 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:06:09.304996 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:06:09.308238 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:06:09.311653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:06:09.318000 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:06:09.321627 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:06:09.324761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:06:09.328162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:06:09.334757 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:06:09.337849 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:06:09.341510 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:06:09.347602 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:06:09.351510 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1580 11:06:09.354631 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 11:06:09.357879 Total UI for P1: 0, mck2ui 16
1582 11:06:09.361098 best dqsien dly found for B0: ( 0, 14, 4)
1583 11:06:09.364695 Total UI for P1: 0, mck2ui 16
1584 11:06:09.368103 best dqsien dly found for B1: ( 0, 14, 4)
1585 11:06:09.371121 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1586 11:06:09.374433 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1587 11:06:09.377809
1588 11:06:09.380907 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 11:06:09.384497 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1590 11:06:09.387635 [Gating] SW calibration Done
1591 11:06:09.387711 ==
1592 11:06:09.391280 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 11:06:09.394720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 11:06:09.394798 ==
1595 11:06:09.394857 RX Vref Scan: 0
1596 11:06:09.394958
1597 11:06:09.397785 RX Vref 0 -> 0, step: 1
1598 11:06:09.397861
1599 11:06:09.400956 RX Delay -130 -> 252, step: 16
1600 11:06:09.404353 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1601 11:06:09.408080 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1602 11:06:09.414220 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1603 11:06:09.418112 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1604 11:06:09.420946 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1605 11:06:09.424434 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1606 11:06:09.427724 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1607 11:06:09.434097 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1608 11:06:09.437408 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1609 11:06:09.440590 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1610 11:06:09.444472 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1611 11:06:09.447755 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1612 11:06:09.454188 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1613 11:06:09.457446 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1614 11:06:09.460833 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1615 11:06:09.464216 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1616 11:06:09.464292 ==
1617 11:06:09.467947 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 11:06:09.474937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 11:06:09.475014 ==
1620 11:06:09.475073 DQS Delay:
1621 11:06:09.475127 DQS0 = 0, DQS1 = 0
1622 11:06:09.477570 DQM Delay:
1623 11:06:09.477645 DQM0 = 88, DQM1 = 82
1624 11:06:09.481280 DQ Delay:
1625 11:06:09.484549 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1626 11:06:09.487466 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1627 11:06:09.491064 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1628 11:06:09.494612 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1629 11:06:09.494688
1630 11:06:09.494746
1631 11:06:09.494799 ==
1632 11:06:09.498036 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 11:06:09.501041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 11:06:09.501486 ==
1635 11:06:09.501795
1636 11:06:09.502074
1637 11:06:09.504511 TX Vref Scan disable
1638 11:06:09.504898 == TX Byte 0 ==
1639 11:06:09.511488 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1640 11:06:09.514781 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1641 11:06:09.515185 == TX Byte 1 ==
1642 11:06:09.521122 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 11:06:09.524346 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 11:06:09.524735 ==
1645 11:06:09.527885 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 11:06:09.531046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 11:06:09.531323 ==
1648 11:06:09.545189 TX Vref=22, minBit 1, minWin=27, winSum=443
1649 11:06:09.548268 TX Vref=24, minBit 4, minWin=26, winSum=445
1650 11:06:09.551448 TX Vref=26, minBit 2, minWin=27, winSum=451
1651 11:06:09.554891 TX Vref=28, minBit 2, minWin=27, winSum=453
1652 11:06:09.558641 TX Vref=30, minBit 3, minWin=27, winSum=456
1653 11:06:09.564878 TX Vref=32, minBit 1, minWin=27, winSum=454
1654 11:06:09.568172 [TxChooseVref] Worse bit 3, Min win 27, Win sum 456, Final Vref 30
1655 11:06:09.568295
1656 11:06:09.571501 Final TX Range 1 Vref 30
1657 11:06:09.571622
1658 11:06:09.571714 ==
1659 11:06:09.575108 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 11:06:09.578545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 11:06:09.578681 ==
1662 11:06:09.581730
1663 11:06:09.581881
1664 11:06:09.582000 TX Vref Scan disable
1665 11:06:09.584988 == TX Byte 0 ==
1666 11:06:09.588609 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1667 11:06:09.594960 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1668 11:06:09.595170 == TX Byte 1 ==
1669 11:06:09.598661 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1670 11:06:09.601970 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1671 11:06:09.605403
1672 11:06:09.605730 [DATLAT]
1673 11:06:09.605986 Freq=800, CH1 RK0
1674 11:06:09.606225
1675 11:06:09.608713 DATLAT Default: 0xa
1676 11:06:09.609100 0, 0xFFFF, sum = 0
1677 11:06:09.611875 1, 0xFFFF, sum = 0
1678 11:06:09.612268 2, 0xFFFF, sum = 0
1679 11:06:09.615277 3, 0xFFFF, sum = 0
1680 11:06:09.615673 4, 0xFFFF, sum = 0
1681 11:06:09.618480 5, 0xFFFF, sum = 0
1682 11:06:09.621981 6, 0xFFFF, sum = 0
1683 11:06:09.622380 7, 0xFFFF, sum = 0
1684 11:06:09.625103 8, 0xFFFF, sum = 0
1685 11:06:09.625540 9, 0x0, sum = 1
1686 11:06:09.625851 10, 0x0, sum = 2
1687 11:06:09.628287 11, 0x0, sum = 3
1688 11:06:09.628685 12, 0x0, sum = 4
1689 11:06:09.631508 best_step = 10
1690 11:06:09.631893
1691 11:06:09.632190 ==
1692 11:06:09.634796 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 11:06:09.638160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 11:06:09.638551 ==
1695 11:06:09.641809 RX Vref Scan: 1
1696 11:06:09.642220
1697 11:06:09.642525 Set Vref Range= 32 -> 127
1698 11:06:09.644756
1699 11:06:09.645176 RX Vref 32 -> 127, step: 1
1700 11:06:09.645492
1701 11:06:09.648129 RX Delay -95 -> 252, step: 8
1702 11:06:09.648204
1703 11:06:09.651786 Set Vref, RX VrefLevel [Byte0]: 32
1704 11:06:09.655034 [Byte1]: 32
1705 11:06:09.655110
1706 11:06:09.657679 Set Vref, RX VrefLevel [Byte0]: 33
1707 11:06:09.661411 [Byte1]: 33
1708 11:06:09.665443
1709 11:06:09.665520 Set Vref, RX VrefLevel [Byte0]: 34
1710 11:06:09.668272 [Byte1]: 34
1711 11:06:09.672973
1712 11:06:09.673073 Set Vref, RX VrefLevel [Byte0]: 35
1713 11:06:09.676173 [Byte1]: 35
1714 11:06:09.680232
1715 11:06:09.680308 Set Vref, RX VrefLevel [Byte0]: 36
1716 11:06:09.683794 [Byte1]: 36
1717 11:06:09.688037
1718 11:06:09.688114 Set Vref, RX VrefLevel [Byte0]: 37
1719 11:06:09.691452 [Byte1]: 37
1720 11:06:09.695729
1721 11:06:09.695805 Set Vref, RX VrefLevel [Byte0]: 38
1722 11:06:09.699078 [Byte1]: 38
1723 11:06:09.703465
1724 11:06:09.703540 Set Vref, RX VrefLevel [Byte0]: 39
1725 11:06:09.706344 [Byte1]: 39
1726 11:06:09.711010
1727 11:06:09.711086 Set Vref, RX VrefLevel [Byte0]: 40
1728 11:06:09.714405 [Byte1]: 40
1729 11:06:09.718300
1730 11:06:09.718408 Set Vref, RX VrefLevel [Byte0]: 41
1731 11:06:09.721486 [Byte1]: 41
1732 11:06:09.726413
1733 11:06:09.726491 Set Vref, RX VrefLevel [Byte0]: 42
1734 11:06:09.729672 [Byte1]: 42
1735 11:06:09.734011
1736 11:06:09.734086 Set Vref, RX VrefLevel [Byte0]: 43
1737 11:06:09.737287 [Byte1]: 43
1738 11:06:09.741211
1739 11:06:09.741294 Set Vref, RX VrefLevel [Byte0]: 44
1740 11:06:09.744528 [Byte1]: 44
1741 11:06:09.748765
1742 11:06:09.748833 Set Vref, RX VrefLevel [Byte0]: 45
1743 11:06:09.755308 [Byte1]: 45
1744 11:06:09.755383
1745 11:06:09.758636 Set Vref, RX VrefLevel [Byte0]: 46
1746 11:06:09.761718 [Byte1]: 46
1747 11:06:09.761794
1748 11:06:09.765085 Set Vref, RX VrefLevel [Byte0]: 47
1749 11:06:09.768590 [Byte1]: 47
1750 11:06:09.768665
1751 11:06:09.771763 Set Vref, RX VrefLevel [Byte0]: 48
1752 11:06:09.775084 [Byte1]: 48
1753 11:06:09.779150
1754 11:06:09.779225 Set Vref, RX VrefLevel [Byte0]: 49
1755 11:06:09.782491 [Byte1]: 49
1756 11:06:09.786666
1757 11:06:09.786745 Set Vref, RX VrefLevel [Byte0]: 50
1758 11:06:09.790028 [Byte1]: 50
1759 11:06:09.794503
1760 11:06:09.794580 Set Vref, RX VrefLevel [Byte0]: 51
1761 11:06:09.797385 [Byte1]: 51
1762 11:06:09.801908
1763 11:06:09.801987 Set Vref, RX VrefLevel [Byte0]: 52
1764 11:06:09.805340 [Byte1]: 52
1765 11:06:09.809406
1766 11:06:09.809483 Set Vref, RX VrefLevel [Byte0]: 53
1767 11:06:09.812673 [Byte1]: 53
1768 11:06:09.817144
1769 11:06:09.817257 Set Vref, RX VrefLevel [Byte0]: 54
1770 11:06:09.820389 [Byte1]: 54
1771 11:06:09.824672
1772 11:06:09.824749 Set Vref, RX VrefLevel [Byte0]: 55
1773 11:06:09.828105 [Byte1]: 55
1774 11:06:09.832117
1775 11:06:09.832198 Set Vref, RX VrefLevel [Byte0]: 56
1776 11:06:09.835629 [Byte1]: 56
1777 11:06:09.839789
1778 11:06:09.839866 Set Vref, RX VrefLevel [Byte0]: 57
1779 11:06:09.843499 [Byte1]: 57
1780 11:06:09.847262
1781 11:06:09.847349 Set Vref, RX VrefLevel [Byte0]: 58
1782 11:06:09.850699 [Byte1]: 58
1783 11:06:09.855261
1784 11:06:09.855337 Set Vref, RX VrefLevel [Byte0]: 59
1785 11:06:09.858492 [Byte1]: 59
1786 11:06:09.862786
1787 11:06:09.862894 Set Vref, RX VrefLevel [Byte0]: 60
1788 11:06:09.866112 [Byte1]: 60
1789 11:06:09.870694
1790 11:06:09.870770 Set Vref, RX VrefLevel [Byte0]: 61
1791 11:06:09.873356 [Byte1]: 61
1792 11:06:09.878236
1793 11:06:09.878318 Set Vref, RX VrefLevel [Byte0]: 62
1794 11:06:09.881403 [Byte1]: 62
1795 11:06:09.885357
1796 11:06:09.885507 Set Vref, RX VrefLevel [Byte0]: 63
1797 11:06:09.888951 [Byte1]: 63
1798 11:06:09.892866
1799 11:06:09.892971 Set Vref, RX VrefLevel [Byte0]: 64
1800 11:06:09.896225 [Byte1]: 64
1801 11:06:09.900725
1802 11:06:09.900802 Set Vref, RX VrefLevel [Byte0]: 65
1803 11:06:09.903864 [Byte1]: 65
1804 11:06:09.908520
1805 11:06:09.908602 Set Vref, RX VrefLevel [Byte0]: 66
1806 11:06:09.911765 [Byte1]: 66
1807 11:06:09.915911
1808 11:06:09.916004 Set Vref, RX VrefLevel [Byte0]: 67
1809 11:06:09.919327 [Byte1]: 67
1810 11:06:09.923436
1811 11:06:09.923519 Set Vref, RX VrefLevel [Byte0]: 68
1812 11:06:09.926571 [Byte1]: 68
1813 11:06:09.930877
1814 11:06:09.930966 Set Vref, RX VrefLevel [Byte0]: 69
1815 11:06:09.934285 [Byte1]: 69
1816 11:06:09.938608
1817 11:06:09.938712 Set Vref, RX VrefLevel [Byte0]: 70
1818 11:06:09.942291 [Byte1]: 70
1819 11:06:09.946903
1820 11:06:09.947377 Set Vref, RX VrefLevel [Byte0]: 71
1821 11:06:09.949584 [Byte1]: 71
1822 11:06:09.953797
1823 11:06:09.954198 Set Vref, RX VrefLevel [Byte0]: 72
1824 11:06:09.957963 [Byte1]: 72
1825 11:06:09.961799
1826 11:06:09.962196 Set Vref, RX VrefLevel [Byte0]: 73
1827 11:06:09.965286 [Byte1]: 73
1828 11:06:09.969532
1829 11:06:09.969930 Set Vref, RX VrefLevel [Byte0]: 74
1830 11:06:09.972804 [Byte1]: 74
1831 11:06:09.976962
1832 11:06:09.977437 Set Vref, RX VrefLevel [Byte0]: 75
1833 11:06:09.980139 [Byte1]: 75
1834 11:06:09.984191
1835 11:06:09.984268 Set Vref, RX VrefLevel [Byte0]: 76
1836 11:06:09.987480 [Byte1]: 76
1837 11:06:09.991944
1838 11:06:09.992026 Final RX Vref Byte 0 = 57 to rank0
1839 11:06:09.995183 Final RX Vref Byte 1 = 58 to rank0
1840 11:06:09.998854 Final RX Vref Byte 0 = 57 to rank1
1841 11:06:10.002107 Final RX Vref Byte 1 = 58 to rank1==
1842 11:06:10.004865 Dram Type= 6, Freq= 0, CH_1, rank 0
1843 11:06:10.011730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 11:06:10.011808 ==
1845 11:06:10.011884 DQS Delay:
1846 11:06:10.011955 DQS0 = 0, DQS1 = 0
1847 11:06:10.015332 DQM Delay:
1848 11:06:10.015409 DQM0 = 86, DQM1 = 81
1849 11:06:10.018415 DQ Delay:
1850 11:06:10.021868 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1851 11:06:10.025170 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =84
1852 11:06:10.025252 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1853 11:06:10.032264 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1854 11:06:10.032661
1855 11:06:10.033053
1856 11:06:10.038531 [DQSOSCAuto] RK0, (LSB)MR18= 0x2336, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
1857 11:06:10.042408 CH1 RK0: MR19=606, MR18=2336
1858 11:06:10.048908 CH1_RK0: MR19=0x606, MR18=0x2336, DQSOSC=396, MR23=63, INC=94, DEC=62
1859 11:06:10.049339
1860 11:06:10.051665 ----->DramcWriteLeveling(PI) begin...
1861 11:06:10.052111 ==
1862 11:06:10.055154 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 11:06:10.058349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 11:06:10.058828 ==
1865 11:06:10.061904 Write leveling (Byte 0): 25 => 25
1866 11:06:10.064918 Write leveling (Byte 1): 29 => 29
1867 11:06:10.069346 DramcWriteLeveling(PI) end<-----
1868 11:06:10.069804
1869 11:06:10.070107 ==
1870 11:06:10.072311 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 11:06:10.075004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 11:06:10.075460 ==
1873 11:06:10.078454 [Gating] SW mode calibration
1874 11:06:10.085305 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1875 11:06:10.092012 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1876 11:06:10.094991 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1877 11:06:10.098504 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1878 11:06:10.105128 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1879 11:06:10.108487 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:06:10.111759 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:06:10.118331 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:06:10.121228 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:06:10.124756 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:06:10.131381 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:06:10.135593 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:06:10.138162 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:06:10.145231 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:06:10.148411 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:06:10.151577 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:06:10.157831 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:06:10.161538 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:06:10.164576 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1893 11:06:10.170979 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1894 11:06:10.174201 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1895 11:06:10.177809 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:06:10.184355 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:06:10.188141 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:06:10.191454 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:06:10.197819 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:06:10.200945 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:06:10.204460 0 9 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1902 11:06:10.210952 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1903 11:06:10.214094 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 11:06:10.217536 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 11:06:10.224314 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 11:06:10.227734 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 11:06:10.230821 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 11:06:10.237992 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
1909 11:06:10.241377 0 10 4 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 0)
1910 11:06:10.244344 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1911 11:06:10.250937 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:06:10.254391 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:06:10.258062 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:06:10.260745 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:06:10.267787 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:06:10.270762 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:06:10.274178 0 11 4 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
1918 11:06:10.280491 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1919 11:06:10.284130 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 11:06:10.287465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 11:06:10.293714 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 11:06:10.297729 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 11:06:10.300453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 11:06:10.307204 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1925 11:06:10.310555 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1926 11:06:10.314041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1927 11:06:10.320736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:06:10.323862 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:06:10.327435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:06:10.334411 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:06:10.337026 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:06:10.340564 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:06:10.347446 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:06:10.350513 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:06:10.354266 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:06:10.360658 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:06:10.364449 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:06:10.367273 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:06:10.373665 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:06:10.376745 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1941 11:06:10.380589 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1942 11:06:10.386613 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 11:06:10.386893 Total UI for P1: 0, mck2ui 16
1944 11:06:10.393603 best dqsien dly found for B0: ( 0, 14, 2)
1945 11:06:10.393903 Total UI for P1: 0, mck2ui 16
1946 11:06:10.397172 best dqsien dly found for B1: ( 0, 14, 6)
1947 11:06:10.403743 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1948 11:06:10.406772 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1949 11:06:10.407075
1950 11:06:10.410197 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1951 11:06:10.413513 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1952 11:06:10.417277 [Gating] SW calibration Done
1953 11:06:10.417680 ==
1954 11:06:10.420180 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 11:06:10.423545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 11:06:10.423854 ==
1957 11:06:10.424091 RX Vref Scan: 0
1958 11:06:10.426599
1959 11:06:10.426900 RX Vref 0 -> 0, step: 1
1960 11:06:10.427136
1961 11:06:10.429994 RX Delay -130 -> 252, step: 16
1962 11:06:10.433592 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1963 11:06:10.437224 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1964 11:06:10.443865 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1965 11:06:10.447111 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1966 11:06:10.450860 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1967 11:06:10.453901 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1968 11:06:10.456929 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1969 11:06:10.464005 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1970 11:06:10.467206 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1971 11:06:10.470087 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1972 11:06:10.473730 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1973 11:06:10.476808 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1974 11:06:10.483456 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1975 11:06:10.487111 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1976 11:06:10.490103 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1977 11:06:10.493546 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1978 11:06:10.493982 ==
1979 11:06:10.496553 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 11:06:10.503462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 11:06:10.503876 ==
1982 11:06:10.504327 DQS Delay:
1983 11:06:10.507037 DQS0 = 0, DQS1 = 0
1984 11:06:10.507426 DQM Delay:
1985 11:06:10.507728 DQM0 = 83, DQM1 = 81
1986 11:06:10.509969 DQ Delay:
1987 11:06:10.513074 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1988 11:06:10.516618 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1989 11:06:10.520255 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1990 11:06:10.523548 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1991 11:06:10.523938
1992 11:06:10.524239
1993 11:06:10.524512 ==
1994 11:06:10.526656 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 11:06:10.529949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 11:06:10.530341 ==
1997 11:06:10.530644
1998 11:06:10.530921
1999 11:06:10.533066 TX Vref Scan disable
2000 11:06:10.536279 == TX Byte 0 ==
2001 11:06:10.539693 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2002 11:06:10.542992 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2003 11:06:10.543402 == TX Byte 1 ==
2004 11:06:10.549559 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2005 11:06:10.552800 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2006 11:06:10.552900 ==
2007 11:06:10.556044 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 11:06:10.559228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 11:06:10.559307 ==
2010 11:06:10.574113 TX Vref=22, minBit 1, minWin=27, winSum=444
2011 11:06:10.577589 TX Vref=24, minBit 1, minWin=27, winSum=447
2012 11:06:10.580761 TX Vref=26, minBit 2, minWin=27, winSum=448
2013 11:06:10.584259 TX Vref=28, minBit 2, minWin=27, winSum=452
2014 11:06:10.587355 TX Vref=30, minBit 3, minWin=27, winSum=454
2015 11:06:10.590889 TX Vref=32, minBit 3, minWin=27, winSum=451
2016 11:06:10.597442 [TxChooseVref] Worse bit 3, Min win 27, Win sum 454, Final Vref 30
2017 11:06:10.597513
2018 11:06:10.600593 Final TX Range 1 Vref 30
2019 11:06:10.600688
2020 11:06:10.600772 ==
2021 11:06:10.604484 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 11:06:10.607062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 11:06:10.607179 ==
2024 11:06:10.607279
2025 11:06:10.611140
2026 11:06:10.611251 TX Vref Scan disable
2027 11:06:10.613945 == TX Byte 0 ==
2028 11:06:10.617152 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2029 11:06:10.620724 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2030 11:06:10.624082 == TX Byte 1 ==
2031 11:06:10.627282 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2032 11:06:10.634157 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2033 11:06:10.634234
2034 11:06:10.634292 [DATLAT]
2035 11:06:10.634346 Freq=800, CH1 RK1
2036 11:06:10.634397
2037 11:06:10.637313 DATLAT Default: 0xa
2038 11:06:10.637389 0, 0xFFFF, sum = 0
2039 11:06:10.640718 1, 0xFFFF, sum = 0
2040 11:06:10.640829 2, 0xFFFF, sum = 0
2041 11:06:10.643969 3, 0xFFFF, sum = 0
2042 11:06:10.644086 4, 0xFFFF, sum = 0
2043 11:06:10.647309 5, 0xFFFF, sum = 0
2044 11:06:10.650915 6, 0xFFFF, sum = 0
2045 11:06:10.650993 7, 0xFFFF, sum = 0
2046 11:06:10.654143 8, 0xFFFF, sum = 0
2047 11:06:10.654225 9, 0x0, sum = 1
2048 11:06:10.654286 10, 0x0, sum = 2
2049 11:06:10.657247 11, 0x0, sum = 3
2050 11:06:10.657327 12, 0x0, sum = 4
2051 11:06:10.660545 best_step = 10
2052 11:06:10.660646
2053 11:06:10.660772 ==
2054 11:06:10.664018 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 11:06:10.667458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 11:06:10.667558 ==
2057 11:06:10.670349 RX Vref Scan: 0
2058 11:06:10.670438
2059 11:06:10.670496 RX Vref 0 -> 0, step: 1
2060 11:06:10.670549
2061 11:06:10.673653 RX Delay -95 -> 252, step: 8
2062 11:06:10.680348 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2063 11:06:10.684049 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2064 11:06:10.687386 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2065 11:06:10.690360 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2066 11:06:10.693948 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2067 11:06:10.700748 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2068 11:06:10.704187 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2069 11:06:10.706858 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2070 11:06:10.710394 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2071 11:06:10.713638 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2072 11:06:10.720796 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2073 11:06:10.724009 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2074 11:06:10.727027 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2075 11:06:10.730097 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2076 11:06:10.737163 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2077 11:06:10.740371 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2078 11:06:10.740447 ==
2079 11:06:10.743753 Dram Type= 6, Freq= 0, CH_1, rank 1
2080 11:06:10.747034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2081 11:06:10.747111 ==
2082 11:06:10.747170 DQS Delay:
2083 11:06:10.750599 DQS0 = 0, DQS1 = 0
2084 11:06:10.750680 DQM Delay:
2085 11:06:10.753610 DQM0 = 87, DQM1 = 84
2086 11:06:10.753697 DQ Delay:
2087 11:06:10.756979 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2088 11:06:10.760484 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2089 11:06:10.763490 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
2090 11:06:10.766818 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2091 11:06:10.766899
2092 11:06:10.766962
2093 11:06:10.776911 [DQSOSCAuto] RK1, (LSB)MR18= 0x2642, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2094 11:06:10.777006 CH1 RK1: MR19=606, MR18=2642
2095 11:06:10.784004 CH1_RK1: MR19=0x606, MR18=0x2642, DQSOSC=393, MR23=63, INC=95, DEC=63
2096 11:06:10.786884 [RxdqsGatingPostProcess] freq 800
2097 11:06:10.793842 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2098 11:06:10.796864 Pre-setting of DQS Precalculation
2099 11:06:10.799973 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2100 11:06:10.808017 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2101 11:06:10.817053 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2102 11:06:10.817518
2103 11:06:10.817841
2104 11:06:10.820375 [Calibration Summary] 1600 Mbps
2105 11:06:10.820764 CH 0, Rank 0
2106 11:06:10.823568 SW Impedance : PASS
2107 11:06:10.824095 DUTY Scan : NO K
2108 11:06:10.826742 ZQ Calibration : PASS
2109 11:06:10.827136 Jitter Meter : NO K
2110 11:06:10.829959 CBT Training : PASS
2111 11:06:10.833464 Write leveling : PASS
2112 11:06:10.833859 RX DQS gating : PASS
2113 11:06:10.836811 RX DQ/DQS(RDDQC) : PASS
2114 11:06:10.840303 TX DQ/DQS : PASS
2115 11:06:10.840696 RX DATLAT : PASS
2116 11:06:10.843520 RX DQ/DQS(Engine): PASS
2117 11:06:10.847143 TX OE : NO K
2118 11:06:10.847534 All Pass.
2119 11:06:10.847834
2120 11:06:10.848110 CH 0, Rank 1
2121 11:06:10.850114 SW Impedance : PASS
2122 11:06:10.853661 DUTY Scan : NO K
2123 11:06:10.854050 ZQ Calibration : PASS
2124 11:06:10.856817 Jitter Meter : NO K
2125 11:06:10.860200 CBT Training : PASS
2126 11:06:10.860589 Write leveling : PASS
2127 11:06:10.863363 RX DQS gating : PASS
2128 11:06:10.866877 RX DQ/DQS(RDDQC) : PASS
2129 11:06:10.867380 TX DQ/DQS : PASS
2130 11:06:10.870070 RX DATLAT : PASS
2131 11:06:10.873358 RX DQ/DQS(Engine): PASS
2132 11:06:10.873746 TX OE : NO K
2133 11:06:10.874051 All Pass.
2134 11:06:10.876349
2135 11:06:10.876734 CH 1, Rank 0
2136 11:06:10.879649 SW Impedance : PASS
2137 11:06:10.880040 DUTY Scan : NO K
2138 11:06:10.883104 ZQ Calibration : PASS
2139 11:06:10.883490 Jitter Meter : NO K
2140 11:06:10.886572 CBT Training : PASS
2141 11:06:10.889672 Write leveling : PASS
2142 11:06:10.890059 RX DQS gating : PASS
2143 11:06:10.893238 RX DQ/DQS(RDDQC) : PASS
2144 11:06:10.896334 TX DQ/DQS : PASS
2145 11:06:10.896723 RX DATLAT : PASS
2146 11:06:10.899724 RX DQ/DQS(Engine): PASS
2147 11:06:10.903134 TX OE : NO K
2148 11:06:10.903525 All Pass.
2149 11:06:10.903824
2150 11:06:10.904100 CH 1, Rank 1
2151 11:06:10.906852 SW Impedance : PASS
2152 11:06:10.910008 DUTY Scan : NO K
2153 11:06:10.910397 ZQ Calibration : PASS
2154 11:06:10.913247 Jitter Meter : NO K
2155 11:06:10.916816 CBT Training : PASS
2156 11:06:10.917255 Write leveling : PASS
2157 11:06:10.919549 RX DQS gating : PASS
2158 11:06:10.923215 RX DQ/DQS(RDDQC) : PASS
2159 11:06:10.923601 TX DQ/DQS : PASS
2160 11:06:10.926706 RX DATLAT : PASS
2161 11:06:10.930044 RX DQ/DQS(Engine): PASS
2162 11:06:10.930432 TX OE : NO K
2163 11:06:10.930736 All Pass.
2164 11:06:10.933281
2165 11:06:10.933747 DramC Write-DBI off
2166 11:06:10.936634 PER_BANK_REFRESH: Hybrid Mode
2167 11:06:10.937104 TX_TRACKING: ON
2168 11:06:10.940065 [GetDramInforAfterCalByMRR] Vendor 6.
2169 11:06:10.942911 [GetDramInforAfterCalByMRR] Revision 606.
2170 11:06:10.949827 [GetDramInforAfterCalByMRR] Revision 2 0.
2171 11:06:10.950219 MR0 0x3b3b
2172 11:06:10.950521 MR8 0x5151
2173 11:06:10.953213 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 11:06:10.953623
2175 11:06:10.956203 MR0 0x3b3b
2176 11:06:10.956592 MR8 0x5151
2177 11:06:10.959399 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 11:06:10.959933
2179 11:06:10.969539 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2180 11:06:10.973079 [FAST_K] Save calibration result to emmc
2181 11:06:10.976532 [FAST_K] Save calibration result to emmc
2182 11:06:10.979909 dram_init: config_dvfs: 1
2183 11:06:10.983016 dramc_set_vcore_voltage set vcore to 662500
2184 11:06:10.986441 Read voltage for 1200, 2
2185 11:06:10.986828 Vio18 = 0
2186 11:06:10.987127 Vcore = 662500
2187 11:06:10.989741 Vdram = 0
2188 11:06:10.990129 Vddq = 0
2189 11:06:10.990644 Vmddr = 0
2190 11:06:10.996401 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2191 11:06:10.999557 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2192 11:06:11.002743 MEM_TYPE=3, freq_sel=15
2193 11:06:11.006271 sv_algorithm_assistance_LP4_1600
2194 11:06:11.009883 ============ PULL DRAM RESETB DOWN ============
2195 11:06:11.012836 ========== PULL DRAM RESETB DOWN end =========
2196 11:06:11.019735 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2197 11:06:11.022817 ===================================
2198 11:06:11.023210 LPDDR4 DRAM CONFIGURATION
2199 11:06:11.026088 ===================================
2200 11:06:11.029663 EX_ROW_EN[0] = 0x0
2201 11:06:11.032931 EX_ROW_EN[1] = 0x0
2202 11:06:11.033343 LP4Y_EN = 0x0
2203 11:06:11.036464 WORK_FSP = 0x0
2204 11:06:11.036927 WL = 0x4
2205 11:06:11.039882 RL = 0x4
2206 11:06:11.040273 BL = 0x2
2207 11:06:11.042752 RPST = 0x0
2208 11:06:11.043140 RD_PRE = 0x0
2209 11:06:11.046821 WR_PRE = 0x1
2210 11:06:11.047290 WR_PST = 0x0
2211 11:06:11.049571 DBI_WR = 0x0
2212 11:06:11.049956 DBI_RD = 0x0
2213 11:06:11.052690 OTF = 0x1
2214 11:06:11.056350 ===================================
2215 11:06:11.059743 ===================================
2216 11:06:11.060219 ANA top config
2217 11:06:11.063250 ===================================
2218 11:06:11.066170 DLL_ASYNC_EN = 0
2219 11:06:11.069500 ALL_SLAVE_EN = 0
2220 11:06:11.069928 NEW_RANK_MODE = 1
2221 11:06:11.072669 DLL_IDLE_MODE = 1
2222 11:06:11.075810 LP45_APHY_COMB_EN = 1
2223 11:06:11.079162 TX_ODT_DIS = 1
2224 11:06:11.082387 NEW_8X_MODE = 1
2225 11:06:11.086041 ===================================
2226 11:06:11.086435 ===================================
2227 11:06:11.089323 data_rate = 2400
2228 11:06:11.092446 CKR = 1
2229 11:06:11.096027 DQ_P2S_RATIO = 8
2230 11:06:11.099359 ===================================
2231 11:06:11.102966 CA_P2S_RATIO = 8
2232 11:06:11.105840 DQ_CA_OPEN = 0
2233 11:06:11.109723 DQ_SEMI_OPEN = 0
2234 11:06:11.110112 CA_SEMI_OPEN = 0
2235 11:06:11.112576 CA_FULL_RATE = 0
2236 11:06:11.115704 DQ_CKDIV4_EN = 0
2237 11:06:11.119185 CA_CKDIV4_EN = 0
2238 11:06:11.122583 CA_PREDIV_EN = 0
2239 11:06:11.125694 PH8_DLY = 17
2240 11:06:11.126083 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2241 11:06:11.129338 DQ_AAMCK_DIV = 4
2242 11:06:11.132454 CA_AAMCK_DIV = 4
2243 11:06:11.135261 CA_ADMCK_DIV = 4
2244 11:06:11.139262 DQ_TRACK_CA_EN = 0
2245 11:06:11.142126 CA_PICK = 1200
2246 11:06:11.145668 CA_MCKIO = 1200
2247 11:06:11.146054 MCKIO_SEMI = 0
2248 11:06:11.149189 PLL_FREQ = 2366
2249 11:06:11.152302 DQ_UI_PI_RATIO = 32
2250 11:06:11.155686 CA_UI_PI_RATIO = 0
2251 11:06:11.158709 ===================================
2252 11:06:11.161838 ===================================
2253 11:06:11.165111 memory_type:LPDDR4
2254 11:06:11.165659 GP_NUM : 10
2255 11:06:11.168792 SRAM_EN : 1
2256 11:06:11.172058 MD32_EN : 0
2257 11:06:11.175369 ===================================
2258 11:06:11.175925 [ANA_INIT] >>>>>>>>>>>>>>
2259 11:06:11.178601 <<<<<< [CONFIGURE PHASE]: ANA_TX
2260 11:06:11.181795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2261 11:06:11.185383 ===================================
2262 11:06:11.188497 data_rate = 2400,PCW = 0X5b00
2263 11:06:11.191633 ===================================
2264 11:06:11.194991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2265 11:06:11.201952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 11:06:11.205640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 11:06:11.212376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2268 11:06:11.215016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2269 11:06:11.218669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2270 11:06:11.219067 [ANA_INIT] flow start
2271 11:06:11.222509 [ANA_INIT] PLL >>>>>>>>
2272 11:06:11.225322 [ANA_INIT] PLL <<<<<<<<
2273 11:06:11.225750 [ANA_INIT] MIDPI >>>>>>>>
2274 11:06:11.228315 [ANA_INIT] MIDPI <<<<<<<<
2275 11:06:11.231959 [ANA_INIT] DLL >>>>>>>>
2276 11:06:11.235275 [ANA_INIT] DLL <<<<<<<<
2277 11:06:11.235682 [ANA_INIT] flow end
2278 11:06:11.238454 ============ LP4 DIFF to SE enter ============
2279 11:06:11.244913 ============ LP4 DIFF to SE exit ============
2280 11:06:11.245489 [ANA_INIT] <<<<<<<<<<<<<
2281 11:06:11.248211 [Flow] Enable top DCM control >>>>>
2282 11:06:11.251764 [Flow] Enable top DCM control <<<<<
2283 11:06:11.254992 Enable DLL master slave shuffle
2284 11:06:11.261277 ==============================================================
2285 11:06:11.261675 Gating Mode config
2286 11:06:11.268457 ==============================================================
2287 11:06:11.271625 Config description:
2288 11:06:11.281545 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2289 11:06:11.288461 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2290 11:06:11.291406 SELPH_MODE 0: By rank 1: By Phase
2291 11:06:11.298397 ==============================================================
2292 11:06:11.301511 GAT_TRACK_EN = 1
2293 11:06:11.301900 RX_GATING_MODE = 2
2294 11:06:11.304779 RX_GATING_TRACK_MODE = 2
2295 11:06:11.307852 SELPH_MODE = 1
2296 11:06:11.311731 PICG_EARLY_EN = 1
2297 11:06:11.314886 VALID_LAT_VALUE = 1
2298 11:06:11.321391 ==============================================================
2299 11:06:11.324958 Enter into Gating configuration >>>>
2300 11:06:11.328253 Exit from Gating configuration <<<<
2301 11:06:11.331419 Enter into DVFS_PRE_config >>>>>
2302 11:06:11.341241 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2303 11:06:11.344323 Exit from DVFS_PRE_config <<<<<
2304 11:06:11.347545 Enter into PICG configuration >>>>
2305 11:06:11.351034 Exit from PICG configuration <<<<
2306 11:06:11.355085 [RX_INPUT] configuration >>>>>
2307 11:06:11.357627 [RX_INPUT] configuration <<<<<
2308 11:06:11.361483 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2309 11:06:11.367791 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2310 11:06:11.374874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 11:06:11.381065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 11:06:11.384794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 11:06:11.391245 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 11:06:11.394167 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2315 11:06:11.400936 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2316 11:06:11.404444 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2317 11:06:11.407912 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2318 11:06:11.411195 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2319 11:06:11.417667 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 11:06:11.420879 ===================================
2321 11:06:11.421292 LPDDR4 DRAM CONFIGURATION
2322 11:06:11.424342 ===================================
2323 11:06:11.427895 EX_ROW_EN[0] = 0x0
2324 11:06:11.430778 EX_ROW_EN[1] = 0x0
2325 11:06:11.431171 LP4Y_EN = 0x0
2326 11:06:11.434069 WORK_FSP = 0x0
2327 11:06:11.434458 WL = 0x4
2328 11:06:11.437362 RL = 0x4
2329 11:06:11.437748 BL = 0x2
2330 11:06:11.440562 RPST = 0x0
2331 11:06:11.440949 RD_PRE = 0x0
2332 11:06:11.444376 WR_PRE = 0x1
2333 11:06:11.444854 WR_PST = 0x0
2334 11:06:11.447743 DBI_WR = 0x0
2335 11:06:11.448223 DBI_RD = 0x0
2336 11:06:11.450694 OTF = 0x1
2337 11:06:11.454101 ===================================
2338 11:06:11.457726 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2339 11:06:11.461000 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2340 11:06:11.467487 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 11:06:11.470398 ===================================
2342 11:06:11.470792 LPDDR4 DRAM CONFIGURATION
2343 11:06:11.474234 ===================================
2344 11:06:11.477722 EX_ROW_EN[0] = 0x10
2345 11:06:11.480776 EX_ROW_EN[1] = 0x0
2346 11:06:11.481288 LP4Y_EN = 0x0
2347 11:06:11.484410 WORK_FSP = 0x0
2348 11:06:11.484825 WL = 0x4
2349 11:06:11.487272 RL = 0x4
2350 11:06:11.487661 BL = 0x2
2351 11:06:11.490655 RPST = 0x0
2352 11:06:11.491176 RD_PRE = 0x0
2353 11:06:11.493745 WR_PRE = 0x1
2354 11:06:11.494267 WR_PST = 0x0
2355 11:06:11.497620 DBI_WR = 0x0
2356 11:06:11.498007 DBI_RD = 0x0
2357 11:06:11.500214 OTF = 0x1
2358 11:06:11.503970 ===================================
2359 11:06:11.510410 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2360 11:06:11.510831 ==
2361 11:06:11.513660 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 11:06:11.516932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 11:06:11.517410 ==
2364 11:06:11.520197 [Duty_Offset_Calibration]
2365 11:06:11.520603 B0:2 B1:0 CA:4
2366 11:06:11.520943
2367 11:06:11.523613 [DutyScan_Calibration_Flow] k_type=0
2368 11:06:11.533280
2369 11:06:11.533688 ==CLK 0==
2370 11:06:11.536488 Final CLK duty delay cell = -4
2371 11:06:11.539505 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2372 11:06:11.542679 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2373 11:06:11.546507 [-4] AVG Duty = 4937%(X100)
2374 11:06:11.546891
2375 11:06:11.549659 CH0 CLK Duty spec in!! Max-Min= 187%
2376 11:06:11.552560 [DutyScan_Calibration_Flow] ====Done====
2377 11:06:11.553063
2378 11:06:11.555724 [DutyScan_Calibration_Flow] k_type=1
2379 11:06:11.572397
2380 11:06:11.572680 ==DQS 0 ==
2381 11:06:11.575820 Final DQS duty delay cell = 0
2382 11:06:11.578906 [0] MAX Duty = 5156%(X100), DQS PI = 18
2383 11:06:11.582560 [0] MIN Duty = 5093%(X100), DQS PI = 0
2384 11:06:11.582753 [0] AVG Duty = 5124%(X100)
2385 11:06:11.585932
2386 11:06:11.586106 ==DQS 1 ==
2387 11:06:11.588796 Final DQS duty delay cell = 0
2388 11:06:11.592443 [0] MAX Duty = 5125%(X100), DQS PI = 4
2389 11:06:11.595504 [0] MIN Duty = 5000%(X100), DQS PI = 0
2390 11:06:11.595713 [0] AVG Duty = 5062%(X100)
2391 11:06:11.598692
2392 11:06:11.602346 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2393 11:06:11.602551
2394 11:06:11.605607 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2395 11:06:11.609063 [DutyScan_Calibration_Flow] ====Done====
2396 11:06:11.609286
2397 11:06:11.612144 [DutyScan_Calibration_Flow] k_type=3
2398 11:06:11.629195
2399 11:06:11.629580 ==DQM 0 ==
2400 11:06:11.632166 Final DQM duty delay cell = 0
2401 11:06:11.635511 [0] MAX Duty = 5093%(X100), DQS PI = 18
2402 11:06:11.638815 [0] MIN Duty = 4844%(X100), DQS PI = 52
2403 11:06:11.639201 [0] AVG Duty = 4968%(X100)
2404 11:06:11.642593
2405 11:06:11.642973 ==DQM 1 ==
2406 11:06:11.645330 Final DQM duty delay cell = 0
2407 11:06:11.648712 [0] MAX Duty = 4969%(X100), DQS PI = 4
2408 11:06:11.651798 [0] MIN Duty = 4875%(X100), DQS PI = 18
2409 11:06:11.651872 [0] AVG Duty = 4922%(X100)
2410 11:06:11.654945
2411 11:06:11.658776 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2412 11:06:11.658850
2413 11:06:11.661922 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2414 11:06:11.664842 [DutyScan_Calibration_Flow] ====Done====
2415 11:06:11.664916
2416 11:06:11.668384 [DutyScan_Calibration_Flow] k_type=2
2417 11:06:11.684840
2418 11:06:11.684922 ==DQ 0 ==
2419 11:06:11.688738 Final DQ duty delay cell = 0
2420 11:06:11.692164 [0] MAX Duty = 5125%(X100), DQS PI = 18
2421 11:06:11.695055 [0] MIN Duty = 4969%(X100), DQS PI = 52
2422 11:06:11.698669 [0] AVG Duty = 5047%(X100)
2423 11:06:11.699051
2424 11:06:11.699349 ==DQ 1 ==
2425 11:06:11.701737 Final DQ duty delay cell = 0
2426 11:06:11.705002 [0] MAX Duty = 5125%(X100), DQS PI = 6
2427 11:06:11.708221 [0] MIN Duty = 4938%(X100), DQS PI = 14
2428 11:06:11.708672 [0] AVG Duty = 5031%(X100)
2429 11:06:11.708969
2430 11:06:11.715165 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2431 11:06:11.715623
2432 11:06:11.718419 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2433 11:06:11.721920 [DutyScan_Calibration_Flow] ====Done====
2434 11:06:11.722378 ==
2435 11:06:11.725438 Dram Type= 6, Freq= 0, CH_1, rank 0
2436 11:06:11.728487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2437 11:06:11.728953 ==
2438 11:06:11.731908 [Duty_Offset_Calibration]
2439 11:06:11.732368 B0:0 B1:-1 CA:3
2440 11:06:11.732672
2441 11:06:11.734910 [DutyScan_Calibration_Flow] k_type=0
2442 11:06:11.744773
2443 11:06:11.745269 ==CLK 0==
2444 11:06:11.748102 Final CLK duty delay cell = -4
2445 11:06:11.750874 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2446 11:06:11.754517 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2447 11:06:11.758028 [-4] AVG Duty = 4938%(X100)
2448 11:06:11.758526
2449 11:06:11.761498 CH1 CLK Duty spec in!! Max-Min= 124%
2450 11:06:11.764615 [DutyScan_Calibration_Flow] ====Done====
2451 11:06:11.765111
2452 11:06:11.767638 [DutyScan_Calibration_Flow] k_type=1
2453 11:06:11.784027
2454 11:06:11.784523 ==DQS 0 ==
2455 11:06:11.787530 Final DQS duty delay cell = 0
2456 11:06:11.790564 [0] MAX Duty = 5156%(X100), DQS PI = 18
2457 11:06:11.794040 [0] MIN Duty = 4907%(X100), DQS PI = 38
2458 11:06:11.797414 [0] AVG Duty = 5031%(X100)
2459 11:06:11.797892
2460 11:06:11.798351 ==DQS 1 ==
2461 11:06:11.800557 Final DQS duty delay cell = 0
2462 11:06:11.803941 [0] MAX Duty = 5156%(X100), DQS PI = 8
2463 11:06:11.807269 [0] MIN Duty = 5031%(X100), DQS PI = 18
2464 11:06:11.810908 [0] AVG Duty = 5093%(X100)
2465 11:06:11.811417
2466 11:06:11.814068 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2467 11:06:11.814498
2468 11:06:11.817298 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2469 11:06:11.820416 [DutyScan_Calibration_Flow] ====Done====
2470 11:06:11.820932
2471 11:06:11.824062 [DutyScan_Calibration_Flow] k_type=3
2472 11:06:11.840247
2473 11:06:11.840710 ==DQM 0 ==
2474 11:06:11.842998 Final DQM duty delay cell = 0
2475 11:06:11.846656 [0] MAX Duty = 5031%(X100), DQS PI = 28
2476 11:06:11.849708 [0] MIN Duty = 4813%(X100), DQS PI = 38
2477 11:06:11.853447 [0] AVG Duty = 4922%(X100)
2478 11:06:11.853523
2479 11:06:11.853581 ==DQM 1 ==
2480 11:06:11.856462 Final DQM duty delay cell = 0
2481 11:06:11.860135 [0] MAX Duty = 5000%(X100), DQS PI = 34
2482 11:06:11.863508 [0] MIN Duty = 4813%(X100), DQS PI = 0
2483 11:06:11.866830 [0] AVG Duty = 4906%(X100)
2484 11:06:11.866976
2485 11:06:11.870432 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2486 11:06:11.870586
2487 11:06:11.873657 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2488 11:06:11.876548 [DutyScan_Calibration_Flow] ====Done====
2489 11:06:11.876712
2490 11:06:11.879674 [DutyScan_Calibration_Flow] k_type=2
2491 11:06:11.896032
2492 11:06:11.896267 ==DQ 0 ==
2493 11:06:11.899486 Final DQ duty delay cell = -4
2494 11:06:11.903013 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2495 11:06:11.905682 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2496 11:06:11.908937 [-4] AVG Duty = 4937%(X100)
2497 11:06:11.909234
2498 11:06:11.909449 ==DQ 1 ==
2499 11:06:11.912479 Final DQ duty delay cell = 0
2500 11:06:11.915806 [0] MAX Duty = 5031%(X100), DQS PI = 34
2501 11:06:11.919137 [0] MIN Duty = 4844%(X100), DQS PI = 0
2502 11:06:11.922514 [0] AVG Duty = 4937%(X100)
2503 11:06:11.922900
2504 11:06:11.925598 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2505 11:06:11.926104
2506 11:06:11.929229 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2507 11:06:11.932634 [DutyScan_Calibration_Flow] ====Done====
2508 11:06:11.935836 nWR fixed to 30
2509 11:06:11.939430 [ModeRegInit_LP4] CH0 RK0
2510 11:06:11.939910 [ModeRegInit_LP4] CH0 RK1
2511 11:06:11.942627 [ModeRegInit_LP4] CH1 RK0
2512 11:06:11.945622 [ModeRegInit_LP4] CH1 RK1
2513 11:06:11.946008 match AC timing 7
2514 11:06:11.952355 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2515 11:06:11.955571 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2516 11:06:11.959114 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2517 11:06:11.965713 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2518 11:06:11.969352 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2519 11:06:11.969820 ==
2520 11:06:11.972354 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 11:06:11.976332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 11:06:11.976846 ==
2523 11:06:11.982328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 11:06:11.989373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 11:06:11.996936 [CA 0] Center 39 (9~70) winsize 62
2526 11:06:11.999398 [CA 1] Center 39 (9~70) winsize 62
2527 11:06:12.002671 [CA 2] Center 35 (5~66) winsize 62
2528 11:06:12.006283 [CA 3] Center 35 (5~66) winsize 62
2529 11:06:12.009287 [CA 4] Center 33 (3~64) winsize 62
2530 11:06:12.012685 [CA 5] Center 33 (3~63) winsize 61
2531 11:06:12.013114
2532 11:06:12.016367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2533 11:06:12.016864
2534 11:06:12.019265 [CATrainingPosCal] consider 1 rank data
2535 11:06:12.022588 u2DelayCellTimex100 = 270/100 ps
2536 11:06:12.026389 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2537 11:06:12.032588 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2538 11:06:12.036589 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 11:06:12.039860 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2540 11:06:12.042685 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2541 11:06:12.045963 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2542 11:06:12.046455
2543 11:06:12.049222 CA PerBit enable=1, Macro0, CA PI delay=33
2544 11:06:12.049654
2545 11:06:12.052664 [CBTSetCACLKResult] CA Dly = 33
2546 11:06:12.055841 CS Dly: 7 (0~38)
2547 11:06:12.056310 ==
2548 11:06:12.058962 Dram Type= 6, Freq= 0, CH_0, rank 1
2549 11:06:12.062314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 11:06:12.062745 ==
2551 11:06:12.065850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2552 11:06:12.072404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2553 11:06:12.082444 [CA 0] Center 39 (9~70) winsize 62
2554 11:06:12.085021 [CA 1] Center 39 (9~70) winsize 62
2555 11:06:12.088509 [CA 2] Center 35 (5~66) winsize 62
2556 11:06:12.091837 [CA 3] Center 35 (5~66) winsize 62
2557 11:06:12.095126 [CA 4] Center 34 (4~65) winsize 62
2558 11:06:12.098706 [CA 5] Center 33 (3~64) winsize 62
2559 11:06:12.099178
2560 11:06:12.102656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2561 11:06:12.103145
2562 11:06:12.105271 [CATrainingPosCal] consider 2 rank data
2563 11:06:12.109212 u2DelayCellTimex100 = 270/100 ps
2564 11:06:12.112560 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2565 11:06:12.118764 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2566 11:06:12.121676 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2567 11:06:12.125815 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2568 11:06:12.128439 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2569 11:06:12.131769 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2570 11:06:12.132208
2571 11:06:12.135198 CA PerBit enable=1, Macro0, CA PI delay=33
2572 11:06:12.135586
2573 11:06:12.138382 [CBTSetCACLKResult] CA Dly = 33
2574 11:06:12.138830 CS Dly: 8 (0~41)
2575 11:06:12.141649
2576 11:06:12.144893 ----->DramcWriteLeveling(PI) begin...
2577 11:06:12.145406 ==
2578 11:06:12.148208 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 11:06:12.151833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 11:06:12.152330 ==
2581 11:06:12.154863 Write leveling (Byte 0): 32 => 32
2582 11:06:12.158228 Write leveling (Byte 1): 27 => 27
2583 11:06:12.161255 DramcWriteLeveling(PI) end<-----
2584 11:06:12.161642
2585 11:06:12.161943 ==
2586 11:06:12.164833 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 11:06:12.168458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 11:06:12.168913 ==
2589 11:06:12.171654 [Gating] SW mode calibration
2590 11:06:12.177949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2591 11:06:12.184724 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2592 11:06:12.188083 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2593 11:06:12.191481 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2594 11:06:12.198076 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 11:06:12.201675 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 11:06:12.205390 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 11:06:12.211455 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 11:06:12.214348 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2599 11:06:12.218074 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
2600 11:06:12.225277 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2601 11:06:12.227932 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2602 11:06:12.231584 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 11:06:12.234754 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 11:06:12.241820 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 11:06:12.244311 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 11:06:12.247730 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2607 11:06:12.254823 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2608 11:06:12.257616 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2609 11:06:12.264444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 11:06:12.267864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 11:06:12.270794 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 11:06:12.274000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 11:06:12.281012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 11:06:12.284249 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 11:06:12.290812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2616 11:06:12.293672 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2617 11:06:12.297095 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2618 11:06:12.300410 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:06:12.307386 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:06:12.310711 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:06:12.316744 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:06:12.320371 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:06:12.323358 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:06:12.329940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:06:12.333822 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:06:12.336800 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:06:12.343617 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:06:12.346505 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:06:12.350545 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:06:12.356685 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2631 11:06:12.360032 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2632 11:06:12.363154 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2633 11:06:12.366320 Total UI for P1: 0, mck2ui 16
2634 11:06:12.370025 best dqsien dly found for B0: ( 1, 3, 26)
2635 11:06:12.373296 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2636 11:06:12.379864 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 11:06:12.382904 Total UI for P1: 0, mck2ui 16
2638 11:06:12.386695 best dqsien dly found for B1: ( 1, 4, 0)
2639 11:06:12.389972 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2640 11:06:12.393028 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2641 11:06:12.393454
2642 11:06:12.396421 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2643 11:06:12.400282 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2644 11:06:12.403368 [Gating] SW calibration Done
2645 11:06:12.403750 ==
2646 11:06:12.406279 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 11:06:12.409710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 11:06:12.410099 ==
2649 11:06:12.413104 RX Vref Scan: 0
2650 11:06:12.413515
2651 11:06:12.413815 RX Vref 0 -> 0, step: 1
2652 11:06:12.414091
2653 11:06:12.416454 RX Delay -40 -> 252, step: 8
2654 11:06:12.419976 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2655 11:06:12.426284 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2656 11:06:12.429635 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2657 11:06:12.432912 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2658 11:06:12.436520 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2659 11:06:12.439720 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2660 11:06:12.446638 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2661 11:06:12.449653 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2662 11:06:12.453066 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2663 11:06:12.456155 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2664 11:06:12.459397 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2665 11:06:12.466278 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2666 11:06:12.469359 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2667 11:06:12.472778 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2668 11:06:12.475927 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2669 11:06:12.479732 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2670 11:06:12.482836 ==
2671 11:06:12.486281 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 11:06:12.489661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 11:06:12.490136 ==
2674 11:06:12.490444 DQS Delay:
2675 11:06:12.493099 DQS0 = 0, DQS1 = 0
2676 11:06:12.493640 DQM Delay:
2677 11:06:12.496100 DQM0 = 117, DQM1 = 107
2678 11:06:12.496483 DQ Delay:
2679 11:06:12.499676 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2680 11:06:12.502977 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =119
2681 11:06:12.506401 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2682 11:06:12.509206 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2683 11:06:12.509596
2684 11:06:12.509898
2685 11:06:12.510174 ==
2686 11:06:12.512532 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 11:06:12.519007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 11:06:12.519394 ==
2689 11:06:12.519699
2690 11:06:12.519976
2691 11:06:12.520242 TX Vref Scan disable
2692 11:06:12.522694 == TX Byte 0 ==
2693 11:06:12.526189 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2694 11:06:12.532617 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2695 11:06:12.533008 == TX Byte 1 ==
2696 11:06:12.535943 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2697 11:06:12.542782 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2698 11:06:12.543169 ==
2699 11:06:12.545893 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 11:06:12.548957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 11:06:12.549032 ==
2702 11:06:12.561472 TX Vref=22, minBit 4, minWin=24, winSum=405
2703 11:06:12.564249 TX Vref=24, minBit 10, minWin=25, winSum=421
2704 11:06:12.567531 TX Vref=26, minBit 10, minWin=25, winSum=423
2705 11:06:12.570940 TX Vref=28, minBit 5, minWin=26, winSum=430
2706 11:06:12.574372 TX Vref=30, minBit 5, minWin=26, winSum=430
2707 11:06:12.581124 TX Vref=32, minBit 5, minWin=26, winSum=429
2708 11:06:12.584093 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
2709 11:06:12.584486
2710 11:06:12.587910 Final TX Range 1 Vref 28
2711 11:06:12.588295
2712 11:06:12.588593 ==
2713 11:06:12.591025 Dram Type= 6, Freq= 0, CH_0, rank 0
2714 11:06:12.594061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2715 11:06:12.597524 ==
2716 11:06:12.597927
2717 11:06:12.598270
2718 11:06:12.598574 TX Vref Scan disable
2719 11:06:12.601037 == TX Byte 0 ==
2720 11:06:12.604128 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2721 11:06:12.610884 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2722 11:06:12.611424 == TX Byte 1 ==
2723 11:06:12.614407 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2724 11:06:12.621121 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2725 11:06:12.621777
2726 11:06:12.622415 [DATLAT]
2727 11:06:12.622914 Freq=1200, CH0 RK0
2728 11:06:12.623442
2729 11:06:12.624379 DATLAT Default: 0xd
2730 11:06:12.624940 0, 0xFFFF, sum = 0
2731 11:06:12.627658 1, 0xFFFF, sum = 0
2732 11:06:12.630735 2, 0xFFFF, sum = 0
2733 11:06:12.631140 3, 0xFFFF, sum = 0
2734 11:06:12.634146 4, 0xFFFF, sum = 0
2735 11:06:12.634539 5, 0xFFFF, sum = 0
2736 11:06:12.637307 6, 0xFFFF, sum = 0
2737 11:06:12.637847 7, 0xFFFF, sum = 0
2738 11:06:12.640428 8, 0xFFFF, sum = 0
2739 11:06:12.640831 9, 0xFFFF, sum = 0
2740 11:06:12.644028 10, 0xFFFF, sum = 0
2741 11:06:12.644598 11, 0xFFFF, sum = 0
2742 11:06:12.647458 12, 0x0, sum = 1
2743 11:06:12.647986 13, 0x0, sum = 2
2744 11:06:12.650917 14, 0x0, sum = 3
2745 11:06:12.651434 15, 0x0, sum = 4
2746 11:06:12.653437 best_step = 13
2747 11:06:12.653534
2748 11:06:12.653627 ==
2749 11:06:12.657412 Dram Type= 6, Freq= 0, CH_0, rank 0
2750 11:06:12.660310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2751 11:06:12.660384 ==
2752 11:06:12.660442 RX Vref Scan: 1
2753 11:06:12.660495
2754 11:06:12.663502 Set Vref Range= 32 -> 127
2755 11:06:12.663576
2756 11:06:12.666775 RX Vref 32 -> 127, step: 1
2757 11:06:12.666849
2758 11:06:12.670143 RX Delay -21 -> 252, step: 4
2759 11:06:12.670234
2760 11:06:12.673928 Set Vref, RX VrefLevel [Byte0]: 32
2761 11:06:12.676927 [Byte1]: 32
2762 11:06:12.677025
2763 11:06:12.680292 Set Vref, RX VrefLevel [Byte0]: 33
2764 11:06:12.683621 [Byte1]: 33
2765 11:06:12.687020
2766 11:06:12.687094 Set Vref, RX VrefLevel [Byte0]: 34
2767 11:06:12.690462 [Byte1]: 34
2768 11:06:12.694759
2769 11:06:12.694837 Set Vref, RX VrefLevel [Byte0]: 35
2770 11:06:12.698115 [Byte1]: 35
2771 11:06:12.703000
2772 11:06:12.703075 Set Vref, RX VrefLevel [Byte0]: 36
2773 11:06:12.705983 [Byte1]: 36
2774 11:06:12.710974
2775 11:06:12.711072 Set Vref, RX VrefLevel [Byte0]: 37
2776 11:06:12.714048 [Byte1]: 37
2777 11:06:12.718983
2778 11:06:12.719052 Set Vref, RX VrefLevel [Byte0]: 38
2779 11:06:12.721997 [Byte1]: 38
2780 11:06:12.726455
2781 11:06:12.726530 Set Vref, RX VrefLevel [Byte0]: 39
2782 11:06:12.730230 [Byte1]: 39
2783 11:06:12.734932
2784 11:06:12.735011 Set Vref, RX VrefLevel [Byte0]: 40
2785 11:06:12.738036 [Byte1]: 40
2786 11:06:12.742938
2787 11:06:12.743031 Set Vref, RX VrefLevel [Byte0]: 41
2788 11:06:12.745775 [Byte1]: 41
2789 11:06:12.750461
2790 11:06:12.750536 Set Vref, RX VrefLevel [Byte0]: 42
2791 11:06:12.754098 [Byte1]: 42
2792 11:06:12.758486
2793 11:06:12.758561 Set Vref, RX VrefLevel [Byte0]: 43
2794 11:06:12.761713 [Byte1]: 43
2795 11:06:12.766283
2796 11:06:12.766358 Set Vref, RX VrefLevel [Byte0]: 44
2797 11:06:12.769576 [Byte1]: 44
2798 11:06:12.774327
2799 11:06:12.774402 Set Vref, RX VrefLevel [Byte0]: 45
2800 11:06:12.777364 [Byte1]: 45
2801 11:06:12.782109
2802 11:06:12.782195 Set Vref, RX VrefLevel [Byte0]: 46
2803 11:06:12.785744 [Byte1]: 46
2804 11:06:12.790177
2805 11:06:12.790251 Set Vref, RX VrefLevel [Byte0]: 47
2806 11:06:12.793235 [Byte1]: 47
2807 11:06:12.798078
2808 11:06:12.798158 Set Vref, RX VrefLevel [Byte0]: 48
2809 11:06:12.801109 [Byte1]: 48
2810 11:06:12.806420
2811 11:06:12.806506 Set Vref, RX VrefLevel [Byte0]: 49
2812 11:06:12.809461 [Byte1]: 49
2813 11:06:12.814241
2814 11:06:12.817052 Set Vref, RX VrefLevel [Byte0]: 50
2815 11:06:12.820606 [Byte1]: 50
2816 11:06:12.820718
2817 11:06:12.823942 Set Vref, RX VrefLevel [Byte0]: 51
2818 11:06:12.827082 [Byte1]: 51
2819 11:06:12.827205
2820 11:06:12.830299 Set Vref, RX VrefLevel [Byte0]: 52
2821 11:06:12.833458 [Byte1]: 52
2822 11:06:12.837755
2823 11:06:12.837936 Set Vref, RX VrefLevel [Byte0]: 53
2824 11:06:12.841178 [Byte1]: 53
2825 11:06:12.846127
2826 11:06:12.846341 Set Vref, RX VrefLevel [Byte0]: 54
2827 11:06:12.849063 [Byte1]: 54
2828 11:06:12.853664
2829 11:06:12.854028 Set Vref, RX VrefLevel [Byte0]: 55
2830 11:06:12.856730 [Byte1]: 55
2831 11:06:12.861606
2832 11:06:12.861891 Set Vref, RX VrefLevel [Byte0]: 56
2833 11:06:12.864799 [Byte1]: 56
2834 11:06:12.869682
2835 11:06:12.869923 Set Vref, RX VrefLevel [Byte0]: 57
2836 11:06:12.872781 [Byte1]: 57
2837 11:06:12.877651
2838 11:06:12.877934 Set Vref, RX VrefLevel [Byte0]: 58
2839 11:06:12.880895 [Byte1]: 58
2840 11:06:12.885436
2841 11:06:12.885725 Set Vref, RX VrefLevel [Byte0]: 59
2842 11:06:12.888494 [Byte1]: 59
2843 11:06:12.893607
2844 11:06:12.893886 Set Vref, RX VrefLevel [Byte0]: 60
2845 11:06:12.896601 [Byte1]: 60
2846 11:06:12.901110
2847 11:06:12.901467 Set Vref, RX VrefLevel [Byte0]: 61
2848 11:06:12.904367 [Byte1]: 61
2849 11:06:12.909086
2850 11:06:12.909436 Set Vref, RX VrefLevel [Byte0]: 62
2851 11:06:12.912492 [Byte1]: 62
2852 11:06:12.917058
2853 11:06:12.917369 Set Vref, RX VrefLevel [Byte0]: 63
2854 11:06:12.920159 [Byte1]: 63
2855 11:06:12.925417
2856 11:06:12.925689 Set Vref, RX VrefLevel [Byte0]: 64
2857 11:06:12.928336 [Byte1]: 64
2858 11:06:12.932911
2859 11:06:12.933209 Set Vref, RX VrefLevel [Byte0]: 65
2860 11:06:12.936105 [Byte1]: 65
2861 11:06:12.940819
2862 11:06:12.941198 Set Vref, RX VrefLevel [Byte0]: 66
2863 11:06:12.944207 [Byte1]: 66
2864 11:06:12.948607
2865 11:06:12.948682 Set Vref, RX VrefLevel [Byte0]: 67
2866 11:06:12.951922 [Byte1]: 67
2867 11:06:12.956364
2868 11:06:12.956448 Set Vref, RX VrefLevel [Byte0]: 68
2869 11:06:12.959837 [Byte1]: 68
2870 11:06:12.964166
2871 11:06:12.964268 Final RX Vref Byte 0 = 54 to rank0
2872 11:06:12.967565 Final RX Vref Byte 1 = 45 to rank0
2873 11:06:12.970932 Final RX Vref Byte 0 = 54 to rank1
2874 11:06:12.974438 Final RX Vref Byte 1 = 45 to rank1==
2875 11:06:12.977654 Dram Type= 6, Freq= 0, CH_0, rank 0
2876 11:06:12.984527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 11:06:12.984620 ==
2878 11:06:12.984694 DQS Delay:
2879 11:06:12.984761 DQS0 = 0, DQS1 = 0
2880 11:06:12.987820 DQM Delay:
2881 11:06:12.987906 DQM0 = 117, DQM1 = 102
2882 11:06:12.991125 DQ Delay:
2883 11:06:12.994643 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2884 11:06:12.998029 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2885 11:06:13.001465 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2886 11:06:13.004805 DQ12 =110, DQ13 =106, DQ14 =112, DQ15 =110
2887 11:06:13.005006
2888 11:06:13.005178
2889 11:06:13.011019 [DQSOSCAuto] RK0, (LSB)MR18= 0x3fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2890 11:06:13.014997 CH0 RK0: MR19=403, MR18=3FE
2891 11:06:13.021112 CH0_RK0: MR19=0x403, MR18=0x3FE, DQSOSC=408, MR23=63, INC=39, DEC=26
2892 11:06:13.021319
2893 11:06:13.025159 ----->DramcWriteLeveling(PI) begin...
2894 11:06:13.025430 ==
2895 11:06:13.028306 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 11:06:13.031359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 11:06:13.031646 ==
2898 11:06:13.034692 Write leveling (Byte 0): 31 => 31
2899 11:06:13.038244 Write leveling (Byte 1): 27 => 27
2900 11:06:13.041132 DramcWriteLeveling(PI) end<-----
2901 11:06:13.041337
2902 11:06:13.041483 ==
2903 11:06:13.044626 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 11:06:13.047922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 11:06:13.051581 ==
2906 11:06:13.051766 [Gating] SW mode calibration
2907 11:06:13.058348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2908 11:06:13.065042 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2909 11:06:13.067981 0 15 0 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
2910 11:06:13.074674 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2911 11:06:13.077877 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 11:06:13.081453 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 11:06:13.088082 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 11:06:13.091299 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 11:06:13.094526 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2916 11:06:13.101179 0 15 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
2917 11:06:13.104598 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2918 11:06:13.107711 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 11:06:13.114644 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 11:06:13.117894 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 11:06:13.120988 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 11:06:13.127817 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 11:06:13.131332 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2924 11:06:13.134075 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2925 11:06:13.140958 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2926 11:06:13.144410 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 11:06:13.147821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 11:06:13.151086 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 11:06:13.157849 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 11:06:13.160799 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 11:06:13.164329 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2932 11:06:13.170800 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2933 11:06:13.174485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2934 11:06:13.177276 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:06:13.184129 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:06:13.187351 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:06:13.191021 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:06:13.197771 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:06:13.200662 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:06:13.203984 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:06:13.210771 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 11:06:13.213953 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 11:06:13.217646 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 11:06:13.224289 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 11:06:13.227417 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 11:06:13.231061 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 11:06:13.237434 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2948 11:06:13.240413 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2949 11:06:13.244012 Total UI for P1: 0, mck2ui 16
2950 11:06:13.246966 best dqsien dly found for B0: ( 1, 3, 24)
2951 11:06:13.250681 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 11:06:13.253891 Total UI for P1: 0, mck2ui 16
2953 11:06:13.257009 best dqsien dly found for B1: ( 1, 3, 28)
2954 11:06:13.260565 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2955 11:06:13.263923 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2956 11:06:13.264018
2957 11:06:13.267653 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2958 11:06:13.273927 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2959 11:06:13.274003 [Gating] SW calibration Done
2960 11:06:13.274067 ==
2961 11:06:13.276960 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 11:06:13.283720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 11:06:13.283811 ==
2964 11:06:13.283872 RX Vref Scan: 0
2965 11:06:13.283928
2966 11:06:13.287441 RX Vref 0 -> 0, step: 1
2967 11:06:13.287517
2968 11:06:13.290243 RX Delay -40 -> 252, step: 8
2969 11:06:13.293819 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2970 11:06:13.296885 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2971 11:06:13.300571 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2972 11:06:13.307272 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2973 11:06:13.310481 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2974 11:06:13.313749 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2975 11:06:13.317273 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2976 11:06:13.320072 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2977 11:06:13.326688 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2978 11:06:13.329946 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2979 11:06:13.333732 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2980 11:06:13.337692 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2981 11:06:13.340153 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2982 11:06:13.346932 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2983 11:06:13.350526 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2984 11:06:13.353332 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2985 11:06:13.353407 ==
2986 11:06:13.356825 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 11:06:13.360510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 11:06:13.360586 ==
2989 11:06:13.363216 DQS Delay:
2990 11:06:13.363292 DQS0 = 0, DQS1 = 0
2991 11:06:13.366631 DQM Delay:
2992 11:06:13.366707 DQM0 = 116, DQM1 = 106
2993 11:06:13.366765 DQ Delay:
2994 11:06:13.373166 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2995 11:06:13.376437 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2996 11:06:13.379796 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2997 11:06:13.383151 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2998 11:06:13.383226
2999 11:06:13.383285
3000 11:06:13.383338 ==
3001 11:06:13.386463 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 11:06:13.390318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 11:06:13.390395 ==
3004 11:06:13.390453
3005 11:06:13.390507
3006 11:06:13.393242 TX Vref Scan disable
3007 11:06:13.396036 == TX Byte 0 ==
3008 11:06:13.399917 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3009 11:06:13.403142 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3010 11:06:13.406441 == TX Byte 1 ==
3011 11:06:13.410051 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3012 11:06:13.413210 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3013 11:06:13.413363 ==
3014 11:06:13.415912 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 11:06:13.422952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 11:06:13.423060 ==
3017 11:06:13.433154 TX Vref=22, minBit 0, minWin=25, winSum=412
3018 11:06:13.436440 TX Vref=24, minBit 1, minWin=25, winSum=419
3019 11:06:13.439731 TX Vref=26, minBit 0, minWin=26, winSum=419
3020 11:06:13.443285 TX Vref=28, minBit 10, minWin=25, winSum=424
3021 11:06:13.446348 TX Vref=30, minBit 15, minWin=25, winSum=426
3022 11:06:13.453248 TX Vref=32, minBit 14, minWin=25, winSum=422
3023 11:06:13.456544 [TxChooseVref] Worse bit 0, Min win 26, Win sum 419, Final Vref 26
3024 11:06:13.456934
3025 11:06:13.459873 Final TX Range 1 Vref 26
3026 11:06:13.460264
3027 11:06:13.460616 ==
3028 11:06:13.463343 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 11:06:13.469695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 11:06:13.470122 ==
3031 11:06:13.470428
3032 11:06:13.470703
3033 11:06:13.471112 TX Vref Scan disable
3034 11:06:13.473300 == TX Byte 0 ==
3035 11:06:13.477004 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3036 11:06:13.483859 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3037 11:06:13.484252 == TX Byte 1 ==
3038 11:06:13.486713 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3039 11:06:13.493923 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3040 11:06:13.494401
3041 11:06:13.494861 [DATLAT]
3042 11:06:13.495317 Freq=1200, CH0 RK1
3043 11:06:13.495741
3044 11:06:13.496541 DATLAT Default: 0xd
3045 11:06:13.499701 0, 0xFFFF, sum = 0
3046 11:06:13.500166 1, 0xFFFF, sum = 0
3047 11:06:13.502727 2, 0xFFFF, sum = 0
3048 11:06:13.503351 3, 0xFFFF, sum = 0
3049 11:06:13.506478 4, 0xFFFF, sum = 0
3050 11:06:13.507056 5, 0xFFFF, sum = 0
3051 11:06:13.509670 6, 0xFFFF, sum = 0
3052 11:06:13.510078 7, 0xFFFF, sum = 0
3053 11:06:13.513061 8, 0xFFFF, sum = 0
3054 11:06:13.513510 9, 0xFFFF, sum = 0
3055 11:06:13.516067 10, 0xFFFF, sum = 0
3056 11:06:13.516458 11, 0xFFFF, sum = 0
3057 11:06:13.519760 12, 0x0, sum = 1
3058 11:06:13.520168 13, 0x0, sum = 2
3059 11:06:13.522846 14, 0x0, sum = 3
3060 11:06:13.523417 15, 0x0, sum = 4
3061 11:06:13.526132 best_step = 13
3062 11:06:13.526513
3063 11:06:13.526814 ==
3064 11:06:13.529561 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 11:06:13.532749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 11:06:13.533323 ==
3067 11:06:13.536256 RX Vref Scan: 0
3068 11:06:13.536642
3069 11:06:13.536942 RX Vref 0 -> 0, step: 1
3070 11:06:13.537259
3071 11:06:13.539002 RX Delay -21 -> 252, step: 4
3072 11:06:13.546098 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3073 11:06:13.548900 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3074 11:06:13.552402 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3075 11:06:13.555739 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3076 11:06:13.559070 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3077 11:06:13.565473 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3078 11:06:13.569571 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3079 11:06:13.572058 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3080 11:06:13.575309 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3081 11:06:13.578688 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3082 11:06:13.585159 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3083 11:06:13.588513 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3084 11:06:13.591520 iDelay=195, Bit 12, Center 108 (43 ~ 174) 132
3085 11:06:13.595238 iDelay=195, Bit 13, Center 108 (43 ~ 174) 132
3086 11:06:13.601633 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3087 11:06:13.604963 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3088 11:06:13.605059 ==
3089 11:06:13.608091 Dram Type= 6, Freq= 0, CH_0, rank 1
3090 11:06:13.611474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 11:06:13.611544 ==
3092 11:06:13.611600 DQS Delay:
3093 11:06:13.614559 DQS0 = 0, DQS1 = 0
3094 11:06:13.614634 DQM Delay:
3095 11:06:13.618228 DQM0 = 115, DQM1 = 103
3096 11:06:13.618303 DQ Delay:
3097 11:06:13.621508 DQ0 =112, DQ1 =116, DQ2 =110, DQ3 =112
3098 11:06:13.624962 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3099 11:06:13.628058 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3100 11:06:13.634970 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =110
3101 11:06:13.635046
3102 11:06:13.635104
3103 11:06:13.641469 [DQSOSCAuto] RK1, (LSB)MR18= 0x401, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 408 ps
3104 11:06:13.644735 CH0 RK1: MR19=404, MR18=401
3105 11:06:13.650832 CH0_RK1: MR19=0x404, MR18=0x401, DQSOSC=408, MR23=63, INC=39, DEC=26
3106 11:06:13.654372 [RxdqsGatingPostProcess] freq 1200
3107 11:06:13.657280 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3108 11:06:13.660771 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 11:06:13.663918 best DQS1 dly(2T, 0.5T) = (0, 12)
3110 11:06:13.667733 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 11:06:13.670484 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3112 11:06:13.674103 best DQS0 dly(2T, 0.5T) = (0, 11)
3113 11:06:13.677204 best DQS1 dly(2T, 0.5T) = (0, 11)
3114 11:06:13.680623 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3115 11:06:13.683686 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3116 11:06:13.687160 Pre-setting of DQS Precalculation
3117 11:06:13.690632 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3118 11:06:13.690731 ==
3119 11:06:13.693901 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 11:06:13.700545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 11:06:13.700621 ==
3122 11:06:13.703798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 11:06:13.710675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3124 11:06:13.719116 [CA 0] Center 38 (8~68) winsize 61
3125 11:06:13.722606 [CA 1] Center 37 (7~68) winsize 62
3126 11:06:13.725992 [CA 2] Center 35 (5~65) winsize 61
3127 11:06:13.729203 [CA 3] Center 34 (4~64) winsize 61
3128 11:06:13.732342 [CA 4] Center 35 (5~65) winsize 61
3129 11:06:13.735403 [CA 5] Center 33 (3~63) winsize 61
3130 11:06:13.735482
3131 11:06:13.739247 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3132 11:06:13.739348
3133 11:06:13.742159 [CATrainingPosCal] consider 1 rank data
3134 11:06:13.745506 u2DelayCellTimex100 = 270/100 ps
3135 11:06:13.748809 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3136 11:06:13.755692 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3137 11:06:13.759129 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3138 11:06:13.762071 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3139 11:06:13.765113 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3140 11:06:13.768634 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3141 11:06:13.768736
3142 11:06:13.771642 CA PerBit enable=1, Macro0, CA PI delay=33
3143 11:06:13.771722
3144 11:06:13.775109 [CBTSetCACLKResult] CA Dly = 33
3145 11:06:13.778366 CS Dly: 5 (0~36)
3146 11:06:13.778469 ==
3147 11:06:13.781664 Dram Type= 6, Freq= 0, CH_1, rank 1
3148 11:06:13.785212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 11:06:13.785316 ==
3150 11:06:13.791820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3151 11:06:13.795169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3152 11:06:13.805058 [CA 0] Center 37 (7~68) winsize 62
3153 11:06:13.808510 [CA 1] Center 38 (8~68) winsize 61
3154 11:06:13.811719 [CA 2] Center 35 (5~65) winsize 61
3155 11:06:13.814885 [CA 3] Center 33 (3~64) winsize 62
3156 11:06:13.818022 [CA 4] Center 34 (4~64) winsize 61
3157 11:06:13.821293 [CA 5] Center 33 (3~63) winsize 61
3158 11:06:13.821394
3159 11:06:13.824983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3160 11:06:13.825141
3161 11:06:13.827928 [CATrainingPosCal] consider 2 rank data
3162 11:06:13.831424 u2DelayCellTimex100 = 270/100 ps
3163 11:06:13.837538 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3164 11:06:13.840736 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3165 11:06:13.844020 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3166 11:06:13.847102 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3167 11:06:13.850557 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3168 11:06:13.854178 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3169 11:06:13.854257
3170 11:06:13.857117 CA PerBit enable=1, Macro0, CA PI delay=33
3171 11:06:13.857205
3172 11:06:13.860461 [CBTSetCACLKResult] CA Dly = 33
3173 11:06:13.864038 CS Dly: 6 (0~39)
3174 11:06:13.864131
3175 11:06:13.867081 ----->DramcWriteLeveling(PI) begin...
3176 11:06:13.867175 ==
3177 11:06:13.870654 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 11:06:13.874066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 11:06:13.874179 ==
3180 11:06:13.877207 Write leveling (Byte 0): 24 => 24
3181 11:06:13.880360 Write leveling (Byte 1): 27 => 27
3182 11:06:13.884034 DramcWriteLeveling(PI) end<-----
3183 11:06:13.884172
3184 11:06:13.884278 ==
3185 11:06:13.887544 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 11:06:13.890422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 11:06:13.890584 ==
3188 11:06:13.894193 [Gating] SW mode calibration
3189 11:06:13.900194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3190 11:06:13.907164 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3191 11:06:13.910373 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:06:13.916807 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 11:06:13.920267 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 11:06:13.923594 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 11:06:13.930160 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 11:06:13.933980 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 11:06:13.936495 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
3198 11:06:13.943790 0 15 28 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (0 0)
3199 11:06:13.946557 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 11:06:13.949863 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 11:06:13.957121 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 11:06:13.960247 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 11:06:13.962997 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 11:06:13.969473 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 11:06:13.972811 1 0 24 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
3206 11:06:13.976175 1 0 28 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
3207 11:06:13.982669 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:06:13.986064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 11:06:13.989310 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 11:06:13.996185 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 11:06:13.999145 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 11:06:14.002465 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 11:06:14.009385 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3214 11:06:14.012930 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3215 11:06:14.015436 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:06:14.022242 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:06:14.025349 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:06:14.029007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:06:14.035271 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:06:14.038519 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:06:14.041663 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:06:14.048592 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:06:14.051763 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:06:14.055371 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 11:06:14.061935 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 11:06:14.065240 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 11:06:14.068769 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 11:06:14.075043 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 11:06:14.078259 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3230 11:06:14.081550 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3231 11:06:14.088075 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 11:06:14.088476 Total UI for P1: 0, mck2ui 16
3233 11:06:14.094701 best dqsien dly found for B0: ( 1, 3, 26)
3234 11:06:14.095121 Total UI for P1: 0, mck2ui 16
3235 11:06:14.101610 best dqsien dly found for B1: ( 1, 3, 26)
3236 11:06:14.104763 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3237 11:06:14.107733 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3238 11:06:14.108122
3239 11:06:14.111067 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3240 11:06:14.114342 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3241 11:06:14.117879 [Gating] SW calibration Done
3242 11:06:14.118268 ==
3243 11:06:14.121183 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 11:06:14.124407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 11:06:14.124804 ==
3246 11:06:14.127729 RX Vref Scan: 0
3247 11:06:14.128114
3248 11:06:14.128416 RX Vref 0 -> 0, step: 1
3249 11:06:14.128698
3250 11:06:14.130806 RX Delay -40 -> 252, step: 8
3251 11:06:14.134328 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3252 11:06:14.140791 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3253 11:06:14.144423 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3254 11:06:14.147909 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3255 11:06:14.151334 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3256 11:06:14.153980 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3257 11:06:14.160525 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3258 11:06:14.163904 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3259 11:06:14.167184 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3260 11:06:14.170700 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3261 11:06:14.174237 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3262 11:06:14.180193 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3263 11:06:14.183804 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3264 11:06:14.186797 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3265 11:06:14.190093 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3266 11:06:14.196816 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3267 11:06:14.197426 ==
3268 11:06:14.200139 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 11:06:14.203456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 11:06:14.204035 ==
3271 11:06:14.204365 DQS Delay:
3272 11:06:14.206961 DQS0 = 0, DQS1 = 0
3273 11:06:14.207343 DQM Delay:
3274 11:06:14.210299 DQM0 = 115, DQM1 = 112
3275 11:06:14.210678 DQ Delay:
3276 11:06:14.213533 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3277 11:06:14.216961 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3278 11:06:14.220092 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3279 11:06:14.223382 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3280 11:06:14.226622
3281 11:06:14.227003
3282 11:06:14.227296 ==
3283 11:06:14.229644 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 11:06:14.233290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 11:06:14.233678 ==
3286 11:06:14.233978
3287 11:06:14.234251
3288 11:06:14.236564 TX Vref Scan disable
3289 11:06:14.236945 == TX Byte 0 ==
3290 11:06:14.243299 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3291 11:06:14.246088 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3292 11:06:14.246486 == TX Byte 1 ==
3293 11:06:14.252354 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3294 11:06:14.255884 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3295 11:06:14.256339 ==
3296 11:06:14.258972 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 11:06:14.262591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 11:06:14.262976 ==
3299 11:06:14.275479 TX Vref=22, minBit 3, minWin=24, winSum=411
3300 11:06:14.278393 TX Vref=24, minBit 11, minWin=24, winSum=414
3301 11:06:14.281724 TX Vref=26, minBit 3, minWin=25, winSum=418
3302 11:06:14.285544 TX Vref=28, minBit 9, minWin=25, winSum=424
3303 11:06:14.288754 TX Vref=30, minBit 2, minWin=26, winSum=428
3304 11:06:14.295109 TX Vref=32, minBit 8, minWin=26, winSum=428
3305 11:06:14.298386 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 30
3306 11:06:14.298805
3307 11:06:14.301727 Final TX Range 1 Vref 30
3308 11:06:14.302258
3309 11:06:14.302802 ==
3310 11:06:14.304895 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 11:06:14.311278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 11:06:14.311736 ==
3313 11:06:14.312042
3314 11:06:14.312320
3315 11:06:14.312589 TX Vref Scan disable
3316 11:06:14.314877 == TX Byte 0 ==
3317 11:06:14.318916 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3318 11:06:14.325028 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3319 11:06:14.325470 == TX Byte 1 ==
3320 11:06:14.328145 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3321 11:06:14.335181 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3322 11:06:14.335570
3323 11:06:14.335873 [DATLAT]
3324 11:06:14.336153 Freq=1200, CH1 RK0
3325 11:06:14.336422
3326 11:06:14.338271 DATLAT Default: 0xd
3327 11:06:14.341285 0, 0xFFFF, sum = 0
3328 11:06:14.341683 1, 0xFFFF, sum = 0
3329 11:06:14.344647 2, 0xFFFF, sum = 0
3330 11:06:14.345038 3, 0xFFFF, sum = 0
3331 11:06:14.348070 4, 0xFFFF, sum = 0
3332 11:06:14.348463 5, 0xFFFF, sum = 0
3333 11:06:14.351713 6, 0xFFFF, sum = 0
3334 11:06:14.352108 7, 0xFFFF, sum = 0
3335 11:06:14.354300 8, 0xFFFF, sum = 0
3336 11:06:14.354693 9, 0xFFFF, sum = 0
3337 11:06:14.357983 10, 0xFFFF, sum = 0
3338 11:06:14.358377 11, 0xFFFF, sum = 0
3339 11:06:14.361440 12, 0x0, sum = 1
3340 11:06:14.361835 13, 0x0, sum = 2
3341 11:06:14.364598 14, 0x0, sum = 3
3342 11:06:14.364992 15, 0x0, sum = 4
3343 11:06:14.367687 best_step = 13
3344 11:06:14.368119
3345 11:06:14.368424 ==
3346 11:06:14.371257 Dram Type= 6, Freq= 0, CH_1, rank 0
3347 11:06:14.374421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3348 11:06:14.374864 ==
3349 11:06:14.377688 RX Vref Scan: 1
3350 11:06:14.378070
3351 11:06:14.378370 Set Vref Range= 32 -> 127
3352 11:06:14.378652
3353 11:06:14.380822 RX Vref 32 -> 127, step: 1
3354 11:06:14.381346
3355 11:06:14.384712 RX Delay -13 -> 252, step: 4
3356 11:06:14.385176
3357 11:06:14.387571 Set Vref, RX VrefLevel [Byte0]: 32
3358 11:06:14.391271 [Byte1]: 32
3359 11:06:14.391654
3360 11:06:14.394506 Set Vref, RX VrefLevel [Byte0]: 33
3361 11:06:14.397271 [Byte1]: 33
3362 11:06:14.401483
3363 11:06:14.401865 Set Vref, RX VrefLevel [Byte0]: 34
3364 11:06:14.404931 [Byte1]: 34
3365 11:06:14.409699
3366 11:06:14.410086 Set Vref, RX VrefLevel [Byte0]: 35
3367 11:06:14.412769 [Byte1]: 35
3368 11:06:14.417601
3369 11:06:14.418113 Set Vref, RX VrefLevel [Byte0]: 36
3370 11:06:14.420649 [Byte1]: 36
3371 11:06:14.425055
3372 11:06:14.425474 Set Vref, RX VrefLevel [Byte0]: 37
3373 11:06:14.428486 [Byte1]: 37
3374 11:06:14.433297
3375 11:06:14.433676 Set Vref, RX VrefLevel [Byte0]: 38
3376 11:06:14.436480 [Byte1]: 38
3377 11:06:14.440874
3378 11:06:14.441291 Set Vref, RX VrefLevel [Byte0]: 39
3379 11:06:14.444166 [Byte1]: 39
3380 11:06:14.448657
3381 11:06:14.448925 Set Vref, RX VrefLevel [Byte0]: 40
3382 11:06:14.451940 [Byte1]: 40
3383 11:06:14.457106
3384 11:06:14.457480 Set Vref, RX VrefLevel [Byte0]: 41
3385 11:06:14.460212 [Byte1]: 41
3386 11:06:14.464505
3387 11:06:14.464881 Set Vref, RX VrefLevel [Byte0]: 42
3388 11:06:14.468063 [Byte1]: 42
3389 11:06:14.472783
3390 11:06:14.473182 Set Vref, RX VrefLevel [Byte0]: 43
3391 11:06:14.476022 [Byte1]: 43
3392 11:06:14.480289
3393 11:06:14.480718 Set Vref, RX VrefLevel [Byte0]: 44
3394 11:06:14.483399 [Byte1]: 44
3395 11:06:14.488482
3396 11:06:14.488878 Set Vref, RX VrefLevel [Byte0]: 45
3397 11:06:14.491324 [Byte1]: 45
3398 11:06:14.495957
3399 11:06:14.496443 Set Vref, RX VrefLevel [Byte0]: 46
3400 11:06:14.499052 [Byte1]: 46
3401 11:06:14.503918
3402 11:06:14.504335 Set Vref, RX VrefLevel [Byte0]: 47
3403 11:06:14.507175 [Byte1]: 47
3404 11:06:14.511631
3405 11:06:14.512016 Set Vref, RX VrefLevel [Byte0]: 48
3406 11:06:14.515589 [Byte1]: 48
3407 11:06:14.519934
3408 11:06:14.520318 Set Vref, RX VrefLevel [Byte0]: 49
3409 11:06:14.523166 [Byte1]: 49
3410 11:06:14.528087
3411 11:06:14.528487 Set Vref, RX VrefLevel [Byte0]: 50
3412 11:06:14.530975 [Byte1]: 50
3413 11:06:14.535778
3414 11:06:14.536291 Set Vref, RX VrefLevel [Byte0]: 51
3415 11:06:14.539060 [Byte1]: 51
3416 11:06:14.543600
3417 11:06:14.544063 Set Vref, RX VrefLevel [Byte0]: 52
3418 11:06:14.546542 [Byte1]: 52
3419 11:06:14.551353
3420 11:06:14.551761 Set Vref, RX VrefLevel [Byte0]: 53
3421 11:06:14.555001 [Byte1]: 53
3422 11:06:14.559521
3423 11:06:14.559943 Set Vref, RX VrefLevel [Byte0]: 54
3424 11:06:14.562569 [Byte1]: 54
3425 11:06:14.567097
3426 11:06:14.567512 Set Vref, RX VrefLevel [Byte0]: 55
3427 11:06:14.570398 [Byte1]: 55
3428 11:06:14.574585
3429 11:06:14.574997 Set Vref, RX VrefLevel [Byte0]: 56
3430 11:06:14.578381 [Byte1]: 56
3431 11:06:14.582787
3432 11:06:14.583169 Set Vref, RX VrefLevel [Byte0]: 57
3433 11:06:14.586350 [Byte1]: 57
3434 11:06:14.590557
3435 11:06:14.590940 Set Vref, RX VrefLevel [Byte0]: 58
3436 11:06:14.594180 [Byte1]: 58
3437 11:06:14.598374
3438 11:06:14.598853 Set Vref, RX VrefLevel [Byte0]: 59
3439 11:06:14.601666 [Byte1]: 59
3440 11:06:14.606072
3441 11:06:14.606487 Set Vref, RX VrefLevel [Byte0]: 60
3442 11:06:14.609368 [Byte1]: 60
3443 11:06:14.614512
3444 11:06:14.615049 Set Vref, RX VrefLevel [Byte0]: 61
3445 11:06:14.617296 [Byte1]: 61
3446 11:06:14.622513
3447 11:06:14.623040 Set Vref, RX VrefLevel [Byte0]: 62
3448 11:06:14.625819 [Byte1]: 62
3449 11:06:14.630258
3450 11:06:14.630778 Set Vref, RX VrefLevel [Byte0]: 63
3451 11:06:14.633441 [Byte1]: 63
3452 11:06:14.637937
3453 11:06:14.638469 Set Vref, RX VrefLevel [Byte0]: 64
3454 11:06:14.641122 [Byte1]: 64
3455 11:06:14.645945
3456 11:06:14.646490 Set Vref, RX VrefLevel [Byte0]: 65
3457 11:06:14.649381 [Byte1]: 65
3458 11:06:14.653767
3459 11:06:14.654158 Final RX Vref Byte 0 = 51 to rank0
3460 11:06:14.657133 Final RX Vref Byte 1 = 52 to rank0
3461 11:06:14.660575 Final RX Vref Byte 0 = 51 to rank1
3462 11:06:14.663333 Final RX Vref Byte 1 = 52 to rank1==
3463 11:06:14.667136 Dram Type= 6, Freq= 0, CH_1, rank 0
3464 11:06:14.673699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 11:06:14.674211 ==
3466 11:06:14.674664 DQS Delay:
3467 11:06:14.674967 DQS0 = 0, DQS1 = 0
3468 11:06:14.676656 DQM Delay:
3469 11:06:14.677070 DQM0 = 115, DQM1 = 113
3470 11:06:14.679759 DQ Delay:
3471 11:06:14.683520 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3472 11:06:14.686771 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3473 11:06:14.690095 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3474 11:06:14.692968 DQ12 =122, DQ13 =122, DQ14 =118, DQ15 =122
3475 11:06:14.693461
3476 11:06:14.693808
3477 11:06:14.703457 [DQSOSCAuto] RK0, (LSB)MR18= 0xf603, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 414 ps
3478 11:06:14.703929 CH1 RK0: MR19=304, MR18=F603
3479 11:06:14.709836 CH1_RK0: MR19=0x304, MR18=0xF603, DQSOSC=408, MR23=63, INC=39, DEC=26
3480 11:06:14.710268
3481 11:06:14.713162 ----->DramcWriteLeveling(PI) begin...
3482 11:06:14.713608 ==
3483 11:06:14.716188 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 11:06:14.722896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 11:06:14.723595 ==
3486 11:06:14.725960 Write leveling (Byte 0): 25 => 25
3487 11:06:14.729453 Write leveling (Byte 1): 28 => 28
3488 11:06:14.732608 DramcWriteLeveling(PI) end<-----
3489 11:06:14.733246
3490 11:06:14.733651 ==
3491 11:06:14.736093 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 11:06:14.739522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 11:06:14.740046 ==
3494 11:06:14.742464 [Gating] SW mode calibration
3495 11:06:14.748996 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3496 11:06:14.756113 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3497 11:06:14.759113 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3498 11:06:14.762345 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 11:06:14.769458 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 11:06:14.772287 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 11:06:14.775698 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 11:06:14.781921 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3503 11:06:14.785373 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3504 11:06:14.788817 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
3505 11:06:14.795453 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 11:06:14.798262 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 11:06:14.801516 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 11:06:14.807722 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 11:06:14.811532 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 11:06:14.814537 1 0 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3511 11:06:14.821254 1 0 24 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
3512 11:06:14.824821 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3513 11:06:14.827714 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 11:06:14.834242 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 11:06:14.837989 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 11:06:14.841053 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 11:06:14.847621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 11:06:14.851179 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3519 11:06:14.854419 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3520 11:06:14.860732 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3521 11:06:14.864145 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:06:14.867539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:06:14.874046 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:06:14.877188 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:06:14.880476 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:06:14.887010 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:06:14.890283 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:06:14.893531 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:06:14.900577 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 11:06:14.903618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 11:06:14.906717 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:06:14.913783 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:06:14.916717 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:06:14.920288 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:06:14.926997 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3536 11:06:14.930125 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3537 11:06:14.933308 Total UI for P1: 0, mck2ui 16
3538 11:06:14.936505 best dqsien dly found for B0: ( 1, 3, 24)
3539 11:06:14.939703 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:06:14.943267 Total UI for P1: 0, mck2ui 16
3541 11:06:14.946399 best dqsien dly found for B1: ( 1, 3, 26)
3542 11:06:14.949809 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3543 11:06:14.952811 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3544 11:06:14.953243
3545 11:06:14.959475 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3546 11:06:14.963232 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3547 11:06:14.963654 [Gating] SW calibration Done
3548 11:06:14.966414 ==
3549 11:06:14.969664 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 11:06:14.973066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 11:06:14.973613 ==
3552 11:06:14.974054 RX Vref Scan: 0
3553 11:06:14.974468
3554 11:06:14.976598 RX Vref 0 -> 0, step: 1
3555 11:06:14.977113
3556 11:06:14.979281 RX Delay -40 -> 252, step: 8
3557 11:06:14.983066 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3558 11:06:14.985797 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3559 11:06:14.992853 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3560 11:06:14.996139 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3561 11:06:14.999327 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3562 11:06:15.002570 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3563 11:06:15.006227 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3564 11:06:15.012141 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3565 11:06:15.016205 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3566 11:06:15.018915 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3567 11:06:15.022503 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3568 11:06:15.025869 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3569 11:06:15.032191 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3570 11:06:15.035729 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3571 11:06:15.038865 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3572 11:06:15.042534 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3573 11:06:15.043035 ==
3574 11:06:15.045247 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 11:06:15.052114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 11:06:15.052582 ==
3577 11:06:15.053004 DQS Delay:
3578 11:06:15.055717 DQS0 = 0, DQS1 = 0
3579 11:06:15.056153 DQM Delay:
3580 11:06:15.056557 DQM0 = 114, DQM1 = 111
3581 11:06:15.058587 DQ Delay:
3582 11:06:15.061822 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3583 11:06:15.066035 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3584 11:06:15.068755 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3585 11:06:15.072355 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3586 11:06:15.072904
3587 11:06:15.073392
3588 11:06:15.073707 ==
3589 11:06:15.075353 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 11:06:15.078439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 11:06:15.081892 ==
3592 11:06:15.082365
3593 11:06:15.082670
3594 11:06:15.082949 TX Vref Scan disable
3595 11:06:15.085028 == TX Byte 0 ==
3596 11:06:15.088539 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3597 11:06:15.091717 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3598 11:06:15.095373 == TX Byte 1 ==
3599 11:06:15.098551 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3600 11:06:15.101652 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3601 11:06:15.104771 ==
3602 11:06:15.108012 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 11:06:15.111379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 11:06:15.111944 ==
3605 11:06:15.122522 TX Vref=22, minBit 9, minWin=25, winSum=421
3606 11:06:15.125920 TX Vref=24, minBit 9, minWin=25, winSum=425
3607 11:06:15.129211 TX Vref=26, minBit 3, minWin=25, winSum=426
3608 11:06:15.132198 TX Vref=28, minBit 2, minWin=26, winSum=432
3609 11:06:15.135915 TX Vref=30, minBit 1, minWin=26, winSum=434
3610 11:06:15.142344 TX Vref=32, minBit 3, minWin=26, winSum=427
3611 11:06:15.145835 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
3612 11:06:15.146474
3613 11:06:15.149369 Final TX Range 1 Vref 30
3614 11:06:15.149754
3615 11:06:15.150112 ==
3616 11:06:15.153095 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 11:06:15.155887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 11:06:15.159414 ==
3619 11:06:15.160018
3620 11:06:15.160497
3621 11:06:15.160911 TX Vref Scan disable
3622 11:06:15.162826 == TX Byte 0 ==
3623 11:06:15.166482 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3624 11:06:15.169618 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3625 11:06:15.172966 == TX Byte 1 ==
3626 11:06:15.175788 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3627 11:06:15.179253 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3628 11:06:15.179653
3629 11:06:15.182451 [DATLAT]
3630 11:06:15.182864 Freq=1200, CH1 RK1
3631 11:06:15.183168
3632 11:06:15.186113 DATLAT Default: 0xd
3633 11:06:15.186680 0, 0xFFFF, sum = 0
3634 11:06:15.188960 1, 0xFFFF, sum = 0
3635 11:06:15.189527 2, 0xFFFF, sum = 0
3636 11:06:15.192463 3, 0xFFFF, sum = 0
3637 11:06:15.192859 4, 0xFFFF, sum = 0
3638 11:06:15.195564 5, 0xFFFF, sum = 0
3639 11:06:15.198893 6, 0xFFFF, sum = 0
3640 11:06:15.199198 7, 0xFFFF, sum = 0
3641 11:06:15.202349 8, 0xFFFF, sum = 0
3642 11:06:15.202563 9, 0xFFFF, sum = 0
3643 11:06:15.205334 10, 0xFFFF, sum = 0
3644 11:06:15.205513 11, 0xFFFF, sum = 0
3645 11:06:15.209123 12, 0x0, sum = 1
3646 11:06:15.209330 13, 0x0, sum = 2
3647 11:06:15.212405 14, 0x0, sum = 3
3648 11:06:15.212536 15, 0x0, sum = 4
3649 11:06:15.212644 best_step = 13
3650 11:06:15.215529
3651 11:06:15.215667 ==
3652 11:06:15.218633 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 11:06:15.222015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 11:06:15.222168 ==
3655 11:06:15.222252 RX Vref Scan: 0
3656 11:06:15.222326
3657 11:06:15.225249 RX Vref 0 -> 0, step: 1
3658 11:06:15.225389
3659 11:06:15.228561 RX Delay -13 -> 252, step: 4
3660 11:06:15.231690 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3661 11:06:15.238438 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3662 11:06:15.241964 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3663 11:06:15.244983 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3664 11:06:15.248241 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3665 11:06:15.251489 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3666 11:06:15.258166 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3667 11:06:15.261813 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3668 11:06:15.264962 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3669 11:06:15.268887 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3670 11:06:15.272067 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3671 11:06:15.278276 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3672 11:06:15.281095 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3673 11:06:15.284769 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3674 11:06:15.288005 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3675 11:06:15.294612 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3676 11:06:15.294702 ==
3677 11:06:15.297826 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 11:06:15.301343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 11:06:15.301449 ==
3680 11:06:15.301531 DQS Delay:
3681 11:06:15.304465 DQS0 = 0, DQS1 = 0
3682 11:06:15.304576 DQM Delay:
3683 11:06:15.307667 DQM0 = 115, DQM1 = 111
3684 11:06:15.307877 DQ Delay:
3685 11:06:15.311226 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3686 11:06:15.314629 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3687 11:06:15.317588 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =106
3688 11:06:15.320983 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3689 11:06:15.321087
3690 11:06:15.321177
3691 11:06:15.330669 [DQSOSCAuto] RK1, (LSB)MR18= 0xf80a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3692 11:06:15.334273 CH1 RK1: MR19=304, MR18=F80A
3693 11:06:15.340771 CH1_RK1: MR19=0x304, MR18=0xF80A, DQSOSC=406, MR23=63, INC=39, DEC=26
3694 11:06:15.340886 [RxdqsGatingPostProcess] freq 1200
3695 11:06:15.347124 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3696 11:06:15.350936 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 11:06:15.353731 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 11:06:15.357184 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 11:06:15.360707 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 11:06:15.364019 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 11:06:15.367148 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 11:06:15.370287 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 11:06:15.373559 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 11:06:15.377007 Pre-setting of DQS Precalculation
3705 11:06:15.380098 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3706 11:06:15.390462 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3707 11:06:15.396583 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3708 11:06:15.396704
3709 11:06:15.396792
3710 11:06:15.400242 [Calibration Summary] 2400 Mbps
3711 11:06:15.400329 CH 0, Rank 0
3712 11:06:15.403535 SW Impedance : PASS
3713 11:06:15.403621 DUTY Scan : NO K
3714 11:06:15.406628 ZQ Calibration : PASS
3715 11:06:15.409822 Jitter Meter : NO K
3716 11:06:15.409916 CBT Training : PASS
3717 11:06:15.413348 Write leveling : PASS
3718 11:06:15.416738 RX DQS gating : PASS
3719 11:06:15.416820 RX DQ/DQS(RDDQC) : PASS
3720 11:06:15.419992 TX DQ/DQS : PASS
3721 11:06:15.423043 RX DATLAT : PASS
3722 11:06:15.423125 RX DQ/DQS(Engine): PASS
3723 11:06:15.426232 TX OE : NO K
3724 11:06:15.426339 All Pass.
3725 11:06:15.426399
3726 11:06:15.429607 CH 0, Rank 1
3727 11:06:15.429710 SW Impedance : PASS
3728 11:06:15.433114 DUTY Scan : NO K
3729 11:06:15.435999 ZQ Calibration : PASS
3730 11:06:15.436099 Jitter Meter : NO K
3731 11:06:15.439525 CBT Training : PASS
3732 11:06:15.439611 Write leveling : PASS
3733 11:06:15.442841 RX DQS gating : PASS
3734 11:06:15.446306 RX DQ/DQS(RDDQC) : PASS
3735 11:06:15.446396 TX DQ/DQS : PASS
3736 11:06:15.449515 RX DATLAT : PASS
3737 11:06:15.453838 RX DQ/DQS(Engine): PASS
3738 11:06:15.453918 TX OE : NO K
3739 11:06:15.456467 All Pass.
3740 11:06:15.456539
3741 11:06:15.456597 CH 1, Rank 0
3742 11:06:15.459768 SW Impedance : PASS
3743 11:06:15.459843 DUTY Scan : NO K
3744 11:06:15.462853 ZQ Calibration : PASS
3745 11:06:15.466257 Jitter Meter : NO K
3746 11:06:15.466353 CBT Training : PASS
3747 11:06:15.469756 Write leveling : PASS
3748 11:06:15.472697 RX DQS gating : PASS
3749 11:06:15.472779 RX DQ/DQS(RDDQC) : PASS
3750 11:06:15.476261 TX DQ/DQS : PASS
3751 11:06:15.479315 RX DATLAT : PASS
3752 11:06:15.479436 RX DQ/DQS(Engine): PASS
3753 11:06:15.482661 TX OE : NO K
3754 11:06:15.482739 All Pass.
3755 11:06:15.482816
3756 11:06:15.486023 CH 1, Rank 1
3757 11:06:15.486102 SW Impedance : PASS
3758 11:06:15.489111 DUTY Scan : NO K
3759 11:06:15.492675 ZQ Calibration : PASS
3760 11:06:15.492754 Jitter Meter : NO K
3761 11:06:15.495685 CBT Training : PASS
3762 11:06:15.499376 Write leveling : PASS
3763 11:06:15.499484 RX DQS gating : PASS
3764 11:06:15.502447 RX DQ/DQS(RDDQC) : PASS
3765 11:06:15.502526 TX DQ/DQS : PASS
3766 11:06:15.506009 RX DATLAT : PASS
3767 11:06:15.509077 RX DQ/DQS(Engine): PASS
3768 11:06:15.509223 TX OE : NO K
3769 11:06:15.512197 All Pass.
3770 11:06:15.512303
3771 11:06:15.512385 DramC Write-DBI off
3772 11:06:15.515628 PER_BANK_REFRESH: Hybrid Mode
3773 11:06:15.519258 TX_TRACKING: ON
3774 11:06:15.525462 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3775 11:06:15.528628 [FAST_K] Save calibration result to emmc
3776 11:06:15.535467 dramc_set_vcore_voltage set vcore to 650000
3777 11:06:15.535632 Read voltage for 600, 5
3778 11:06:15.538718 Vio18 = 0
3779 11:06:15.538869 Vcore = 650000
3780 11:06:15.539007 Vdram = 0
3781 11:06:15.539136 Vddq = 0
3782 11:06:15.542182 Vmddr = 0
3783 11:06:15.545251 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3784 11:06:15.551493 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3785 11:06:15.555004 MEM_TYPE=3, freq_sel=19
3786 11:06:15.558529 sv_algorithm_assistance_LP4_1600
3787 11:06:15.561698 ============ PULL DRAM RESETB DOWN ============
3788 11:06:15.564731 ========== PULL DRAM RESETB DOWN end =========
3789 11:06:15.568091 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3790 11:06:15.572028 ===================================
3791 11:06:15.574858 LPDDR4 DRAM CONFIGURATION
3792 11:06:15.577914 ===================================
3793 11:06:15.581961 EX_ROW_EN[0] = 0x0
3794 11:06:15.582059 EX_ROW_EN[1] = 0x0
3795 11:06:15.584653 LP4Y_EN = 0x0
3796 11:06:15.584756 WORK_FSP = 0x0
3797 11:06:15.587879 WL = 0x2
3798 11:06:15.587983 RL = 0x2
3799 11:06:15.591119 BL = 0x2
3800 11:06:15.591224 RPST = 0x0
3801 11:06:15.594881 RD_PRE = 0x0
3802 11:06:15.597763 WR_PRE = 0x1
3803 11:06:15.597864 WR_PST = 0x0
3804 11:06:15.600982 DBI_WR = 0x0
3805 11:06:15.601084 DBI_RD = 0x0
3806 11:06:15.604307 OTF = 0x1
3807 11:06:15.607642 ===================================
3808 11:06:15.611346 ===================================
3809 11:06:15.611426 ANA top config
3810 11:06:15.614495 ===================================
3811 11:06:15.618087 DLL_ASYNC_EN = 0
3812 11:06:15.621010 ALL_SLAVE_EN = 1
3813 11:06:15.621087 NEW_RANK_MODE = 1
3814 11:06:15.623924 DLL_IDLE_MODE = 1
3815 11:06:15.627740 LP45_APHY_COMB_EN = 1
3816 11:06:15.631061 TX_ODT_DIS = 1
3817 11:06:15.633944 NEW_8X_MODE = 1
3818 11:06:15.637389 ===================================
3819 11:06:15.641000 ===================================
3820 11:06:15.641076 data_rate = 1200
3821 11:06:15.644126 CKR = 1
3822 11:06:15.647237 DQ_P2S_RATIO = 8
3823 11:06:15.650285 ===================================
3824 11:06:15.654307 CA_P2S_RATIO = 8
3825 11:06:15.657132 DQ_CA_OPEN = 0
3826 11:06:15.660610 DQ_SEMI_OPEN = 0
3827 11:06:15.660686 CA_SEMI_OPEN = 0
3828 11:06:15.663965 CA_FULL_RATE = 0
3829 11:06:15.667089 DQ_CKDIV4_EN = 1
3830 11:06:15.670218 CA_CKDIV4_EN = 1
3831 11:06:15.673366 CA_PREDIV_EN = 0
3832 11:06:15.676702 PH8_DLY = 0
3833 11:06:15.676784 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3834 11:06:15.680483 DQ_AAMCK_DIV = 4
3835 11:06:15.683355 CA_AAMCK_DIV = 4
3836 11:06:15.686656 CA_ADMCK_DIV = 4
3837 11:06:15.690135 DQ_TRACK_CA_EN = 0
3838 11:06:15.693542 CA_PICK = 600
3839 11:06:15.696434 CA_MCKIO = 600
3840 11:06:15.696511 MCKIO_SEMI = 0
3841 11:06:15.700152 PLL_FREQ = 2288
3842 11:06:15.703398 DQ_UI_PI_RATIO = 32
3843 11:06:15.706499 CA_UI_PI_RATIO = 0
3844 11:06:15.710251 ===================================
3845 11:06:15.713087 ===================================
3846 11:06:15.716753 memory_type:LPDDR4
3847 11:06:15.716856 GP_NUM : 10
3848 11:06:15.719939 SRAM_EN : 1
3849 11:06:15.723234 MD32_EN : 0
3850 11:06:15.726237 ===================================
3851 11:06:15.726363 [ANA_INIT] >>>>>>>>>>>>>>
3852 11:06:15.729577 <<<<<< [CONFIGURE PHASE]: ANA_TX
3853 11:06:15.733384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3854 11:06:15.736508 ===================================
3855 11:06:15.739801 data_rate = 1200,PCW = 0X5800
3856 11:06:15.742903 ===================================
3857 11:06:15.746394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3858 11:06:15.752682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 11:06:15.756201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 11:06:15.762737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3861 11:06:15.766450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3862 11:06:15.769488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3863 11:06:15.772791 [ANA_INIT] flow start
3864 11:06:15.773206 [ANA_INIT] PLL >>>>>>>>
3865 11:06:15.775971 [ANA_INIT] PLL <<<<<<<<
3866 11:06:15.779576 [ANA_INIT] MIDPI >>>>>>>>
3867 11:06:15.779961 [ANA_INIT] MIDPI <<<<<<<<
3868 11:06:15.782884 [ANA_INIT] DLL >>>>>>>>
3869 11:06:15.786170 [ANA_INIT] flow end
3870 11:06:15.789419 ============ LP4 DIFF to SE enter ============
3871 11:06:15.792587 ============ LP4 DIFF to SE exit ============
3872 11:06:15.796516 [ANA_INIT] <<<<<<<<<<<<<
3873 11:06:15.799269 [Flow] Enable top DCM control >>>>>
3874 11:06:15.802549 [Flow] Enable top DCM control <<<<<
3875 11:06:15.805957 Enable DLL master slave shuffle
3876 11:06:15.809014 ==============================================================
3877 11:06:15.812502 Gating Mode config
3878 11:06:15.819225 ==============================================================
3879 11:06:15.819620 Config description:
3880 11:06:15.828902 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3881 11:06:15.835522 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3882 11:06:15.842695 SELPH_MODE 0: By rank 1: By Phase
3883 11:06:15.845314 ==============================================================
3884 11:06:15.848843 GAT_TRACK_EN = 1
3885 11:06:15.852243 RX_GATING_MODE = 2
3886 11:06:15.855660 RX_GATING_TRACK_MODE = 2
3887 11:06:15.858686 SELPH_MODE = 1
3888 11:06:15.862077 PICG_EARLY_EN = 1
3889 11:06:15.865100 VALID_LAT_VALUE = 1
3890 11:06:15.868513 ==============================================================
3891 11:06:15.871805 Enter into Gating configuration >>>>
3892 11:06:15.874805 Exit from Gating configuration <<<<
3893 11:06:15.879003 Enter into DVFS_PRE_config >>>>>
3894 11:06:15.891851 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3895 11:06:15.894678 Exit from DVFS_PRE_config <<<<<
3896 11:06:15.897930 Enter into PICG configuration >>>>
3897 11:06:15.901227 Exit from PICG configuration <<<<
3898 11:06:15.901616 [RX_INPUT] configuration >>>>>
3899 11:06:15.904650 [RX_INPUT] configuration <<<<<
3900 11:06:15.910993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3901 11:06:15.917619 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3902 11:06:15.920871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 11:06:15.927560 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 11:06:15.933966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3905 11:06:15.940622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3906 11:06:15.943814 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3907 11:06:15.947210 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3908 11:06:15.953811 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3909 11:06:15.956934 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3910 11:06:15.960121 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3911 11:06:15.966740 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 11:06:15.970304 ===================================
3913 11:06:15.970728 LPDDR4 DRAM CONFIGURATION
3914 11:06:15.973681 ===================================
3915 11:06:15.976535 EX_ROW_EN[0] = 0x0
3916 11:06:15.980187 EX_ROW_EN[1] = 0x0
3917 11:06:15.980570 LP4Y_EN = 0x0
3918 11:06:15.983323 WORK_FSP = 0x0
3919 11:06:15.983705 WL = 0x2
3920 11:06:15.986529 RL = 0x2
3921 11:06:15.986949 BL = 0x2
3922 11:06:15.990049 RPST = 0x0
3923 11:06:15.990436 RD_PRE = 0x0
3924 11:06:15.993098 WR_PRE = 0x1
3925 11:06:15.993532 WR_PST = 0x0
3926 11:06:15.996901 DBI_WR = 0x0
3927 11:06:15.997355 DBI_RD = 0x0
3928 11:06:16.000103 OTF = 0x1
3929 11:06:16.003023 ===================================
3930 11:06:16.006696 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3931 11:06:16.009683 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3932 11:06:16.016393 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 11:06:16.019385 ===================================
3934 11:06:16.019774 LPDDR4 DRAM CONFIGURATION
3935 11:06:16.022956 ===================================
3936 11:06:16.026446 EX_ROW_EN[0] = 0x10
3937 11:06:16.030026 EX_ROW_EN[1] = 0x0
3938 11:06:16.030433 LP4Y_EN = 0x0
3939 11:06:16.033121 WORK_FSP = 0x0
3940 11:06:16.033554 WL = 0x2
3941 11:06:16.036294 RL = 0x2
3942 11:06:16.036682 BL = 0x2
3943 11:06:16.039463 RPST = 0x0
3944 11:06:16.039851 RD_PRE = 0x0
3945 11:06:16.042772 WR_PRE = 0x1
3946 11:06:16.043158 WR_PST = 0x0
3947 11:06:16.046091 DBI_WR = 0x0
3948 11:06:16.046481 DBI_RD = 0x0
3949 11:06:16.049266 OTF = 0x1
3950 11:06:16.052563 ===================================
3951 11:06:16.059093 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3952 11:06:16.062967 nWR fixed to 30
3953 11:06:16.066276 [ModeRegInit_LP4] CH0 RK0
3954 11:06:16.066663 [ModeRegInit_LP4] CH0 RK1
3955 11:06:16.069324 [ModeRegInit_LP4] CH1 RK0
3956 11:06:16.072541 [ModeRegInit_LP4] CH1 RK1
3957 11:06:16.072923 match AC timing 17
3958 11:06:16.079312 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3959 11:06:16.082576 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3960 11:06:16.085585 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3961 11:06:16.092294 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3962 11:06:16.095589 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3963 11:06:16.095982 ==
3964 11:06:16.099050 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 11:06:16.102618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 11:06:16.103036 ==
3967 11:06:16.108602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 11:06:16.115099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3969 11:06:16.118381 [CA 0] Center 36 (6~67) winsize 62
3970 11:06:16.121823 [CA 1] Center 36 (5~67) winsize 63
3971 11:06:16.125261 [CA 2] Center 34 (4~65) winsize 62
3972 11:06:16.128491 [CA 3] Center 34 (3~65) winsize 63
3973 11:06:16.131818 [CA 4] Center 33 (3~64) winsize 62
3974 11:06:16.135162 [CA 5] Center 33 (2~64) winsize 63
3975 11:06:16.135664
3976 11:06:16.138350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3977 11:06:16.138755
3978 11:06:16.141782 [CATrainingPosCal] consider 1 rank data
3979 11:06:16.145449 u2DelayCellTimex100 = 270/100 ps
3980 11:06:16.148078 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3981 11:06:16.151253 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3982 11:06:16.155020 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 11:06:16.158337 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3984 11:06:16.165012 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 11:06:16.167990 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3986 11:06:16.168548
3987 11:06:16.171258 CA PerBit enable=1, Macro0, CA PI delay=33
3988 11:06:16.171791
3989 11:06:16.174423 [CBTSetCACLKResult] CA Dly = 33
3990 11:06:16.174830 CS Dly: 4 (0~35)
3991 11:06:16.175253 ==
3992 11:06:16.177701 Dram Type= 6, Freq= 0, CH_0, rank 1
3993 11:06:16.184531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 11:06:16.184917 ==
3995 11:06:16.188176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 11:06:16.194336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3997 11:06:16.197856 [CA 0] Center 36 (6~67) winsize 62
3998 11:06:16.201524 [CA 1] Center 36 (6~67) winsize 62
3999 11:06:16.204318 [CA 2] Center 34 (4~65) winsize 62
4000 11:06:16.207569 [CA 3] Center 34 (3~65) winsize 63
4001 11:06:16.210678 [CA 4] Center 34 (3~65) winsize 63
4002 11:06:16.214383 [CA 5] Center 33 (3~64) winsize 62
4003 11:06:16.214766
4004 11:06:16.218069 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4005 11:06:16.218537
4006 11:06:16.220743 [CATrainingPosCal] consider 2 rank data
4007 11:06:16.224214 u2DelayCellTimex100 = 270/100 ps
4008 11:06:16.227522 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4009 11:06:16.234084 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4010 11:06:16.237629 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4011 11:06:16.240557 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4012 11:06:16.243867 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 11:06:16.247178 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4014 11:06:16.247719
4015 11:06:16.250549 CA PerBit enable=1, Macro0, CA PI delay=33
4016 11:06:16.251050
4017 11:06:16.253965 [CBTSetCACLKResult] CA Dly = 33
4018 11:06:16.256888 CS Dly: 5 (0~37)
4019 11:06:16.257163
4020 11:06:16.260820 ----->DramcWriteLeveling(PI) begin...
4021 11:06:16.261031 ==
4022 11:06:16.263471 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 11:06:16.266552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 11:06:16.266779 ==
4025 11:06:16.269841 Write leveling (Byte 0): 32 => 32
4026 11:06:16.273281 Write leveling (Byte 1): 30 => 30
4027 11:06:16.276569 DramcWriteLeveling(PI) end<-----
4028 11:06:16.276732
4029 11:06:16.276869 ==
4030 11:06:16.279776 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 11:06:16.283433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 11:06:16.283591 ==
4033 11:06:16.286525 [Gating] SW mode calibration
4034 11:06:16.292992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 11:06:16.299912 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4036 11:06:16.303139 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 11:06:16.306472 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 11:06:16.313035 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 11:06:16.316505 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
4040 11:06:16.319361 0 9 16 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
4041 11:06:16.326708 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 11:06:16.329551 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 11:06:16.332573 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 11:06:16.339344 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 11:06:16.342339 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 11:06:16.346134 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 11:06:16.352388 0 10 12 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
4048 11:06:16.355759 0 10 16 | B1->B0 | 3838 4040 | 0 0 | (0 0) (0 0)
4049 11:06:16.358844 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 11:06:16.365971 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 11:06:16.369247 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 11:06:16.372512 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 11:06:16.379217 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 11:06:16.382311 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 11:06:16.385682 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 11:06:16.392324 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4057 11:06:16.395816 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:06:16.399197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:06:16.405584 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:06:16.408616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:06:16.412245 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:06:16.418696 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:06:16.421970 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:06:16.425685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:06:16.432158 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:06:16.434964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:06:16.438415 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:06:16.445467 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:06:16.448352 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:06:16.451967 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:06:16.458327 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:06:16.461947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4073 11:06:16.464746 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 11:06:16.467972 Total UI for P1: 0, mck2ui 16
4075 11:06:16.471273 best dqsien dly found for B0: ( 0, 13, 16)
4076 11:06:16.475023 Total UI for P1: 0, mck2ui 16
4077 11:06:16.478012 best dqsien dly found for B1: ( 0, 13, 16)
4078 11:06:16.481213 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4079 11:06:16.484486 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4080 11:06:16.488008
4081 11:06:16.491414 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4082 11:06:16.494353 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4083 11:06:16.497606 [Gating] SW calibration Done
4084 11:06:16.497996 ==
4085 11:06:16.500951 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 11:06:16.504516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 11:06:16.504902 ==
4088 11:06:16.505244 RX Vref Scan: 0
4089 11:06:16.507726
4090 11:06:16.508110 RX Vref 0 -> 0, step: 1
4091 11:06:16.508412
4092 11:06:16.510906 RX Delay -230 -> 252, step: 16
4093 11:06:16.514160 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4094 11:06:16.520788 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4095 11:06:16.524187 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4096 11:06:16.527973 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4097 11:06:16.530733 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4098 11:06:16.537394 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4099 11:06:16.541296 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4100 11:06:16.543859 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4101 11:06:16.547599 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4102 11:06:16.550771 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4103 11:06:16.557745 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4104 11:06:16.560304 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4105 11:06:16.563643 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4106 11:06:16.566881 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4107 11:06:16.573658 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4108 11:06:16.576721 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4109 11:06:16.577108 ==
4110 11:06:16.580926 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 11:06:16.583500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 11:06:16.583888 ==
4113 11:06:16.587067 DQS Delay:
4114 11:06:16.587453 DQS0 = 0, DQS1 = 0
4115 11:06:16.590019 DQM Delay:
4116 11:06:16.590402 DQM0 = 41, DQM1 = 36
4117 11:06:16.590704 DQ Delay:
4118 11:06:16.593566 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4119 11:06:16.596585 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4120 11:06:16.599743 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4121 11:06:16.603011 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4122 11:06:16.603397
4123 11:06:16.603696
4124 11:06:16.607064 ==
4125 11:06:16.610049 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 11:06:16.613083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 11:06:16.613513 ==
4128 11:06:16.613812
4129 11:06:16.614102
4130 11:06:16.616468 TX Vref Scan disable
4131 11:06:16.616849 == TX Byte 0 ==
4132 11:06:16.622670 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4133 11:06:16.626215 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4134 11:06:16.626612 == TX Byte 1 ==
4135 11:06:16.632722 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4136 11:06:16.636201 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4137 11:06:16.636753 ==
4138 11:06:16.639491 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 11:06:16.643322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 11:06:16.643731 ==
4141 11:06:16.644169
4142 11:06:16.644542
4143 11:06:16.646401 TX Vref Scan disable
4144 11:06:16.649314 == TX Byte 0 ==
4145 11:06:16.652619 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4146 11:06:16.655743 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4147 11:06:16.659191 == TX Byte 1 ==
4148 11:06:16.662615 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4149 11:06:16.665900 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4150 11:06:16.669292
4151 11:06:16.669714 [DATLAT]
4152 11:06:16.670099 Freq=600, CH0 RK0
4153 11:06:16.670509
4154 11:06:16.672695 DATLAT Default: 0x9
4155 11:06:16.673087 0, 0xFFFF, sum = 0
4156 11:06:16.675759 1, 0xFFFF, sum = 0
4157 11:06:16.676156 2, 0xFFFF, sum = 0
4158 11:06:16.678933 3, 0xFFFF, sum = 0
4159 11:06:16.682499 4, 0xFFFF, sum = 0
4160 11:06:16.682902 5, 0xFFFF, sum = 0
4161 11:06:16.685676 6, 0xFFFF, sum = 0
4162 11:06:16.686073 7, 0xFFFF, sum = 0
4163 11:06:16.689117 8, 0x0, sum = 1
4164 11:06:16.689555 9, 0x0, sum = 2
4165 11:06:16.689858 10, 0x0, sum = 3
4166 11:06:16.692420 11, 0x0, sum = 4
4167 11:06:16.692809 best_step = 9
4168 11:06:16.693108
4169 11:06:16.693433 ==
4170 11:06:16.696441 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 11:06:16.702469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 11:06:16.702859 ==
4173 11:06:16.703164 RX Vref Scan: 1
4174 11:06:16.703440
4175 11:06:16.705628 RX Vref 0 -> 0, step: 1
4176 11:06:16.706009
4177 11:06:16.708654 RX Delay -179 -> 252, step: 8
4178 11:06:16.709037
4179 11:06:16.711820 Set Vref, RX VrefLevel [Byte0]: 54
4180 11:06:16.715096 [Byte1]: 45
4181 11:06:16.715478
4182 11:06:16.719038 Final RX Vref Byte 0 = 54 to rank0
4183 11:06:16.722133 Final RX Vref Byte 1 = 45 to rank0
4184 11:06:16.725584 Final RX Vref Byte 0 = 54 to rank1
4185 11:06:16.728405 Final RX Vref Byte 1 = 45 to rank1==
4186 11:06:16.731942 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 11:06:16.735080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 11:06:16.735464 ==
4189 11:06:16.738249 DQS Delay:
4190 11:06:16.738752 DQS0 = 0, DQS1 = 0
4191 11:06:16.741961 DQM Delay:
4192 11:06:16.742340 DQM0 = 41, DQM1 = 33
4193 11:06:16.742634 DQ Delay:
4194 11:06:16.745209 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4195 11:06:16.748146 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4196 11:06:16.752151 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4197 11:06:16.754863 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4198 11:06:16.755244
4199 11:06:16.755538
4200 11:06:16.765039 [DQSOSCAuto] RK0, (LSB)MR18= 0x5048, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4201 11:06:16.767790 CH0 RK0: MR19=808, MR18=5048
4202 11:06:16.774499 CH0_RK0: MR19=0x808, MR18=0x5048, DQSOSC=394, MR23=63, INC=168, DEC=112
4203 11:06:16.774908
4204 11:06:16.777597 ----->DramcWriteLeveling(PI) begin...
4205 11:06:16.777985 ==
4206 11:06:16.780967 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 11:06:16.784226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 11:06:16.784608 ==
4209 11:06:16.787482 Write leveling (Byte 0): 33 => 33
4210 11:06:16.791208 Write leveling (Byte 1): 30 => 30
4211 11:06:16.794211 DramcWriteLeveling(PI) end<-----
4212 11:06:16.794590
4213 11:06:16.794882 ==
4214 11:06:16.797571 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 11:06:16.801084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 11:06:16.801526 ==
4217 11:06:16.804254 [Gating] SW mode calibration
4218 11:06:16.810879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4219 11:06:16.817359 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4220 11:06:16.820924 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 11:06:16.827771 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 11:06:16.830872 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 11:06:16.833722 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4224 11:06:16.840716 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4225 11:06:16.843874 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:06:16.847114 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 11:06:16.853591 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 11:06:16.856884 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 11:06:16.860458 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 11:06:16.866927 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 11:06:16.870336 0 10 12 | B1->B0 | 2b2b 3535 | 0 0 | (0 0) (0 0)
4232 11:06:16.873303 0 10 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
4233 11:06:16.880071 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:06:16.883106 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 11:06:16.886387 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 11:06:16.893280 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 11:06:16.897053 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 11:06:16.899631 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 11:06:16.906262 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4240 11:06:16.909722 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4241 11:06:16.913383 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:06:16.919422 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:06:16.922812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:06:16.926452 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:06:16.932662 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:06:16.935884 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:06:16.939267 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:06:16.945767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:06:16.949326 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:06:16.952609 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:06:16.959045 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:06:16.962511 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:06:16.965434 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:06:16.971969 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:06:16.975474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4256 11:06:16.979087 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:06:16.981963 Total UI for P1: 0, mck2ui 16
4258 11:06:16.985412 best dqsien dly found for B0: ( 0, 13, 12)
4259 11:06:16.988403 Total UI for P1: 0, mck2ui 16
4260 11:06:16.991888 best dqsien dly found for B1: ( 0, 13, 12)
4261 11:06:16.995398 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4262 11:06:16.998790 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4263 11:06:16.999169
4264 11:06:17.004704 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4265 11:06:17.008405 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4266 11:06:17.011883 [Gating] SW calibration Done
4267 11:06:17.012263 ==
4268 11:06:17.015183 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 11:06:17.017989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 11:06:17.018416 ==
4271 11:06:17.018720 RX Vref Scan: 0
4272 11:06:17.019000
4273 11:06:17.021731 RX Vref 0 -> 0, step: 1
4274 11:06:17.022113
4275 11:06:17.024445 RX Delay -230 -> 252, step: 16
4276 11:06:17.027868 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4277 11:06:17.034862 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4278 11:06:17.038273 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4279 11:06:17.040992 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4280 11:06:17.044697 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4281 11:06:17.047949 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4282 11:06:17.054182 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4283 11:06:17.057911 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4284 11:06:17.061087 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4285 11:06:17.064292 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4286 11:06:17.070479 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4287 11:06:17.074228 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4288 11:06:17.077607 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4289 11:06:17.080942 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4290 11:06:17.087058 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4291 11:06:17.090540 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4292 11:06:17.090996 ==
4293 11:06:17.093679 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 11:06:17.097266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 11:06:17.097652 ==
4296 11:06:17.100822 DQS Delay:
4297 11:06:17.101245 DQS0 = 0, DQS1 = 0
4298 11:06:17.101704 DQM Delay:
4299 11:06:17.103866 DQM0 = 45, DQM1 = 32
4300 11:06:17.104249 DQ Delay:
4301 11:06:17.107374 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4302 11:06:17.110449 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4303 11:06:17.113944 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4304 11:06:17.117280 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4305 11:06:17.117683
4306 11:06:17.117998
4307 11:06:17.118270 ==
4308 11:06:17.120363 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 11:06:17.126779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 11:06:17.127165 ==
4311 11:06:17.127461
4312 11:06:17.127785
4313 11:06:17.128065 TX Vref Scan disable
4314 11:06:17.130782 == TX Byte 0 ==
4315 11:06:17.133819 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4316 11:06:17.140799 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4317 11:06:17.141217 == TX Byte 1 ==
4318 11:06:17.143948 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4319 11:06:17.150791 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4320 11:06:17.151172 ==
4321 11:06:17.154077 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 11:06:17.157532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 11:06:17.157915 ==
4324 11:06:17.158222
4325 11:06:17.158494
4326 11:06:17.160520 TX Vref Scan disable
4327 11:06:17.163842 == TX Byte 0 ==
4328 11:06:17.167052 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4329 11:06:17.171111 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4330 11:06:17.174098 == TX Byte 1 ==
4331 11:06:17.177276 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4332 11:06:17.180591 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4333 11:06:17.181011
4334 11:06:17.181353 [DATLAT]
4335 11:06:17.184015 Freq=600, CH0 RK1
4336 11:06:17.184393
4337 11:06:17.186963 DATLAT Default: 0x9
4338 11:06:17.187339 0, 0xFFFF, sum = 0
4339 11:06:17.190575 1, 0xFFFF, sum = 0
4340 11:06:17.190992 2, 0xFFFF, sum = 0
4341 11:06:17.193815 3, 0xFFFF, sum = 0
4342 11:06:17.194201 4, 0xFFFF, sum = 0
4343 11:06:17.197415 5, 0xFFFF, sum = 0
4344 11:06:17.197803 6, 0xFFFF, sum = 0
4345 11:06:17.200013 7, 0xFFFF, sum = 0
4346 11:06:17.200399 8, 0x0, sum = 1
4347 11:06:17.203813 9, 0x0, sum = 2
4348 11:06:17.204199 10, 0x0, sum = 3
4349 11:06:17.206544 11, 0x0, sum = 4
4350 11:06:17.207074 best_step = 9
4351 11:06:17.207383
4352 11:06:17.207656 ==
4353 11:06:17.210069 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 11:06:17.213394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 11:06:17.213855 ==
4356 11:06:17.217075 RX Vref Scan: 0
4357 11:06:17.217542
4358 11:06:17.219879 RX Vref 0 -> 0, step: 1
4359 11:06:17.220258
4360 11:06:17.220553 RX Delay -195 -> 252, step: 8
4361 11:06:17.228608 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4362 11:06:17.231706 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4363 11:06:17.234639 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4364 11:06:17.237992 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4365 11:06:17.244582 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4366 11:06:17.247810 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4367 11:06:17.250995 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4368 11:06:17.254511 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4369 11:06:17.258114 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4370 11:06:17.264522 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4371 11:06:17.267466 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4372 11:06:17.271315 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4373 11:06:17.274682 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4374 11:06:17.280741 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4375 11:06:17.284279 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4376 11:06:17.286979 iDelay=205, Bit 15, Center 36 (-115 ~ 188) 304
4377 11:06:17.287187 ==
4378 11:06:17.290786 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 11:06:17.296998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 11:06:17.297222 ==
4381 11:06:17.297385 DQS Delay:
4382 11:06:17.300309 DQS0 = 0, DQS1 = 0
4383 11:06:17.300512 DQM Delay:
4384 11:06:17.300671 DQM0 = 40, DQM1 = 33
4385 11:06:17.303515 DQ Delay:
4386 11:06:17.306659 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4387 11:06:17.310100 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44
4388 11:06:17.313507 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4389 11:06:17.316711 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =36
4390 11:06:17.316923
4391 11:06:17.317083
4392 11:06:17.323187 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4393 11:06:17.326920 CH0 RK1: MR19=808, MR18=4C48
4394 11:06:17.333158 CH0_RK1: MR19=0x808, MR18=0x4C48, DQSOSC=395, MR23=63, INC=168, DEC=112
4395 11:06:17.336876 [RxdqsGatingPostProcess] freq 600
4396 11:06:17.339735 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4397 11:06:17.343289 Pre-setting of DQS Precalculation
4398 11:06:17.350199 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4399 11:06:17.350640 ==
4400 11:06:17.353191 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 11:06:17.356693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 11:06:17.357085 ==
4403 11:06:17.363310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 11:06:17.369650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4405 11:06:17.372992 [CA 0] Center 35 (5~66) winsize 62
4406 11:06:17.376413 [CA 1] Center 35 (5~66) winsize 62
4407 11:06:17.380270 [CA 2] Center 34 (4~65) winsize 62
4408 11:06:17.383220 [CA 3] Center 34 (4~65) winsize 62
4409 11:06:17.386281 [CA 4] Center 34 (4~65) winsize 62
4410 11:06:17.389348 [CA 5] Center 33 (3~64) winsize 62
4411 11:06:17.389726
4412 11:06:17.393092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4413 11:06:17.393510
4414 11:06:17.396736 [CATrainingPosCal] consider 1 rank data
4415 11:06:17.400009 u2DelayCellTimex100 = 270/100 ps
4416 11:06:17.402631 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 11:06:17.406408 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4418 11:06:17.409684 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 11:06:17.412817 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 11:06:17.415671 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4421 11:06:17.422493 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 11:06:17.422938
4423 11:06:17.425953 CA PerBit enable=1, Macro0, CA PI delay=33
4424 11:06:17.426331
4425 11:06:17.429184 [CBTSetCACLKResult] CA Dly = 33
4426 11:06:17.429567 CS Dly: 4 (0~35)
4427 11:06:17.429931 ==
4428 11:06:17.432495 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 11:06:17.436019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 11:06:17.438661 ==
4431 11:06:17.441893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 11:06:17.448921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4433 11:06:17.452451 [CA 0] Center 35 (5~66) winsize 62
4434 11:06:17.455579 [CA 1] Center 36 (6~66) winsize 61
4435 11:06:17.458590 [CA 2] Center 34 (4~65) winsize 62
4436 11:06:17.461908 [CA 3] Center 34 (3~65) winsize 63
4437 11:06:17.465309 [CA 4] Center 34 (4~65) winsize 62
4438 11:06:17.468898 [CA 5] Center 33 (3~64) winsize 62
4439 11:06:17.469444
4440 11:06:17.472207 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4441 11:06:17.472636
4442 11:06:17.475445 [CATrainingPosCal] consider 2 rank data
4443 11:06:17.478920 u2DelayCellTimex100 = 270/100 ps
4444 11:06:17.481900 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 11:06:17.485119 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4446 11:06:17.491605 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 11:06:17.495066 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 11:06:17.498403 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 11:06:17.501248 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 11:06:17.501735
4451 11:06:17.504282 CA PerBit enable=1, Macro0, CA PI delay=33
4452 11:06:17.504795
4453 11:06:17.508090 [CBTSetCACLKResult] CA Dly = 33
4454 11:06:17.508498 CS Dly: 4 (0~36)
4455 11:06:17.511517
4456 11:06:17.514770 ----->DramcWriteLeveling(PI) begin...
4457 11:06:17.515184 ==
4458 11:06:17.517857 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 11:06:17.521234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 11:06:17.521751 ==
4461 11:06:17.524409 Write leveling (Byte 0): 27 => 27
4462 11:06:17.527574 Write leveling (Byte 1): 29 => 29
4463 11:06:17.531166 DramcWriteLeveling(PI) end<-----
4464 11:06:17.531694
4465 11:06:17.532135 ==
4466 11:06:17.534055 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 11:06:17.537994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 11:06:17.538522 ==
4469 11:06:17.541188 [Gating] SW mode calibration
4470 11:06:17.547545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 11:06:17.554370 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4472 11:06:17.557371 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 11:06:17.560540 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 11:06:17.567068 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4475 11:06:17.570487 0 9 12 | B1->B0 | 3030 2d2d | 0 0 | (1 1) (0 1)
4476 11:06:17.573781 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 11:06:17.580185 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 11:06:17.583806 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 11:06:17.587334 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 11:06:17.593876 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 11:06:17.597120 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 11:06:17.600505 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 11:06:17.607014 0 10 12 | B1->B0 | 3333 3939 | 0 1 | (0 0) (0 0)
4484 11:06:17.610741 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 11:06:17.613731 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 11:06:17.620598 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 11:06:17.623563 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 11:06:17.626882 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 11:06:17.633679 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 11:06:17.636733 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 11:06:17.640423 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4492 11:06:17.647143 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:06:17.650173 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:06:17.653590 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:06:17.659857 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:06:17.663516 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:06:17.666207 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:06:17.673014 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:06:17.676325 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:06:17.679719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:06:17.686291 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:06:17.689042 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:06:17.692851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:06:17.699620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:06:17.702284 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:06:17.705885 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4507 11:06:17.712376 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4508 11:06:17.712890 Total UI for P1: 0, mck2ui 16
4509 11:06:17.718727 best dqsien dly found for B1: ( 0, 13, 10)
4510 11:06:17.722501 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:06:17.725690 Total UI for P1: 0, mck2ui 16
4512 11:06:17.729252 best dqsien dly found for B0: ( 0, 13, 10)
4513 11:06:17.732424 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4514 11:06:17.735972 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4515 11:06:17.736474
4516 11:06:17.739022 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4517 11:06:17.745202 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4518 11:06:17.745632 [Gating] SW calibration Done
4519 11:06:17.745964 ==
4520 11:06:17.748902 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 11:06:17.755366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 11:06:17.755940 ==
4523 11:06:17.756283 RX Vref Scan: 0
4524 11:06:17.756594
4525 11:06:17.758440 RX Vref 0 -> 0, step: 1
4526 11:06:17.758864
4527 11:06:17.761985 RX Delay -230 -> 252, step: 16
4528 11:06:17.765300 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4529 11:06:17.768657 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4530 11:06:17.771755 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4531 11:06:17.778559 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4532 11:06:17.781535 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4533 11:06:17.785186 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4534 11:06:17.788012 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4535 11:06:17.794737 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4536 11:06:17.798042 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4537 11:06:17.801390 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4538 11:06:17.805346 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4539 11:06:17.811682 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4540 11:06:17.814818 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4541 11:06:17.817791 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4542 11:06:17.821496 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4543 11:06:17.828087 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4544 11:06:17.828476 ==
4545 11:06:17.831012 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 11:06:17.834448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 11:06:17.834886 ==
4548 11:06:17.835201 DQS Delay:
4549 11:06:17.837694 DQS0 = 0, DQS1 = 0
4550 11:06:17.838079 DQM Delay:
4551 11:06:17.841030 DQM0 = 39, DQM1 = 37
4552 11:06:17.841463 DQ Delay:
4553 11:06:17.844403 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4554 11:06:17.847951 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4555 11:06:17.851111 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4556 11:06:17.854233 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4557 11:06:17.854800
4558 11:06:17.855119
4559 11:06:17.855448 ==
4560 11:06:17.857743 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 11:06:17.861013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 11:06:17.861445 ==
4563 11:06:17.861750
4564 11:06:17.864572
4565 11:06:17.865038 TX Vref Scan disable
4566 11:06:17.867810 == TX Byte 0 ==
4567 11:06:17.870654 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4568 11:06:17.874323 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4569 11:06:17.877670 == TX Byte 1 ==
4570 11:06:17.880690 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 11:06:17.884120 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 11:06:17.886922 ==
4573 11:06:17.887310 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 11:06:17.893695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 11:06:17.894087 ==
4576 11:06:17.894384
4577 11:06:17.894657
4578 11:06:17.896865 TX Vref Scan disable
4579 11:06:17.897280 == TX Byte 0 ==
4580 11:06:17.903974 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4581 11:06:17.907054 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4582 11:06:17.907540 == TX Byte 1 ==
4583 11:06:17.913989 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4584 11:06:17.917344 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4585 11:06:17.918057
4586 11:06:17.918430 [DATLAT]
4587 11:06:17.920301 Freq=600, CH1 RK0
4588 11:06:17.920775
4589 11:06:17.921077 DATLAT Default: 0x9
4590 11:06:17.923752 0, 0xFFFF, sum = 0
4591 11:06:17.924144 1, 0xFFFF, sum = 0
4592 11:06:17.926855 2, 0xFFFF, sum = 0
4593 11:06:17.930657 3, 0xFFFF, sum = 0
4594 11:06:17.931126 4, 0xFFFF, sum = 0
4595 11:06:17.933486 5, 0xFFFF, sum = 0
4596 11:06:17.933962 6, 0xFFFF, sum = 0
4597 11:06:17.936789 7, 0xFFFF, sum = 0
4598 11:06:17.937303 8, 0x0, sum = 1
4599 11:06:17.937619 9, 0x0, sum = 2
4600 11:06:17.939763 10, 0x0, sum = 3
4601 11:06:17.940159 11, 0x0, sum = 4
4602 11:06:17.943562 best_step = 9
4603 11:06:17.943952
4604 11:06:17.944254 ==
4605 11:06:17.947493 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 11:06:17.950128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 11:06:17.950520 ==
4608 11:06:17.953222 RX Vref Scan: 1
4609 11:06:17.953610
4610 11:06:17.953911 RX Vref 0 -> 0, step: 1
4611 11:06:17.954193
4612 11:06:17.956372 RX Delay -179 -> 252, step: 8
4613 11:06:17.956757
4614 11:06:17.959666 Set Vref, RX VrefLevel [Byte0]: 51
4615 11:06:17.963516 [Byte1]: 52
4616 11:06:17.967270
4617 11:06:17.967661 Final RX Vref Byte 0 = 51 to rank0
4618 11:06:17.970805 Final RX Vref Byte 1 = 52 to rank0
4619 11:06:17.973822 Final RX Vref Byte 0 = 51 to rank1
4620 11:06:17.977358 Final RX Vref Byte 1 = 52 to rank1==
4621 11:06:17.980586 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 11:06:17.987314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 11:06:17.987738 ==
4624 11:06:17.988040 DQS Delay:
4625 11:06:17.990582 DQS0 = 0, DQS1 = 0
4626 11:06:17.990964 DQM Delay:
4627 11:06:17.991265 DQM0 = 42, DQM1 = 33
4628 11:06:17.994305 DQ Delay:
4629 11:06:17.996862 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4630 11:06:18.000736 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4631 11:06:18.003498 DQ8 =16, DQ9 =24, DQ10 =32, DQ11 =28
4632 11:06:18.007255 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4633 11:06:18.007636
4634 11:06:18.007933
4635 11:06:18.013824 [DQSOSCAuto] RK0, (LSB)MR18= 0x3751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4636 11:06:18.017453 CH1 RK0: MR19=808, MR18=3751
4637 11:06:18.023376 CH1_RK0: MR19=0x808, MR18=0x3751, DQSOSC=394, MR23=63, INC=168, DEC=112
4638 11:06:18.023768
4639 11:06:18.026621 ----->DramcWriteLeveling(PI) begin...
4640 11:06:18.027070 ==
4641 11:06:18.030368 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 11:06:18.033500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 11:06:18.033888 ==
4644 11:06:18.036834 Write leveling (Byte 0): 29 => 29
4645 11:06:18.040237 Write leveling (Byte 1): 29 => 29
4646 11:06:18.043239 DramcWriteLeveling(PI) end<-----
4647 11:06:18.043626
4648 11:06:18.043928 ==
4649 11:06:18.046686 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 11:06:18.049647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 11:06:18.053284 ==
4652 11:06:18.053743 [Gating] SW mode calibration
4653 11:06:18.063810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4654 11:06:18.065925 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4655 11:06:18.069233 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 11:06:18.076253 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 11:06:18.079902 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4658 11:06:18.083080 0 9 12 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
4659 11:06:18.089067 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4660 11:06:18.092705 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 11:06:18.096356 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 11:06:18.102477 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 11:06:18.105683 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 11:06:18.108763 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 11:06:18.115792 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4666 11:06:18.118820 0 10 12 | B1->B0 | 3434 4343 | 1 1 | (0 0) (0 0)
4667 11:06:18.122296 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 11:06:18.128603 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:06:18.132355 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 11:06:18.135660 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 11:06:18.141833 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 11:06:18.145263 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 11:06:18.149305 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 11:06:18.155339 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4675 11:06:18.158663 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:06:18.161673 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:06:18.168689 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:06:18.171554 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:06:18.174831 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:06:18.181576 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:06:18.185184 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:06:18.188011 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:06:18.194605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:06:18.198116 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:06:18.201345 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:06:18.208337 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:06:18.211589 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:06:18.214645 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:06:18.220880 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:06:18.224604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4691 11:06:18.227818 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 11:06:18.230901 Total UI for P1: 0, mck2ui 16
4693 11:06:18.234308 best dqsien dly found for B0: ( 0, 13, 12)
4694 11:06:18.237753 Total UI for P1: 0, mck2ui 16
4695 11:06:18.240799 best dqsien dly found for B1: ( 0, 13, 12)
4696 11:06:18.244227 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4697 11:06:18.250822 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4698 11:06:18.251204
4699 11:06:18.254092 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4700 11:06:18.257512 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4701 11:06:18.260324 [Gating] SW calibration Done
4702 11:06:18.260777 ==
4703 11:06:18.264313 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 11:06:18.267396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 11:06:18.267865 ==
4706 11:06:18.270706 RX Vref Scan: 0
4707 11:06:18.271092
4708 11:06:18.271491 RX Vref 0 -> 0, step: 1
4709 11:06:18.271778
4710 11:06:18.273484 RX Delay -230 -> 252, step: 16
4711 11:06:18.277317 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4712 11:06:18.283539 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4713 11:06:18.286973 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4714 11:06:18.290056 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4715 11:06:18.293552 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4716 11:06:18.300318 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4717 11:06:18.303784 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4718 11:06:18.306670 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4719 11:06:18.310448 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4720 11:06:18.313460 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4721 11:06:18.319723 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4722 11:06:18.323042 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4723 11:06:18.326777 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4724 11:06:18.332969 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4725 11:06:18.336650 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4726 11:06:18.339698 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4727 11:06:18.340221 ==
4728 11:06:18.343592 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 11:06:18.346785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 11:06:18.347176 ==
4731 11:06:18.349466 DQS Delay:
4732 11:06:18.349891 DQS0 = 0, DQS1 = 0
4733 11:06:18.353703 DQM Delay:
4734 11:06:18.354221 DQM0 = 42, DQM1 = 39
4735 11:06:18.354662 DQ Delay:
4736 11:06:18.356552 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4737 11:06:18.359931 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4738 11:06:18.363044 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4739 11:06:18.365903 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4740 11:06:18.366291
4741 11:06:18.366590
4742 11:06:18.369479 ==
4743 11:06:18.372729 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 11:06:18.375723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 11:06:18.376224 ==
4746 11:06:18.376532
4747 11:06:18.376827
4748 11:06:18.379301 TX Vref Scan disable
4749 11:06:18.379756 == TX Byte 0 ==
4750 11:06:18.386075 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4751 11:06:18.389419 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4752 11:06:18.389843 == TX Byte 1 ==
4753 11:06:18.396073 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4754 11:06:18.399042 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4755 11:06:18.399456 ==
4756 11:06:18.403113 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 11:06:18.405667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 11:06:18.406056 ==
4759 11:06:18.406356
4760 11:06:18.406628
4761 11:06:18.409430 TX Vref Scan disable
4762 11:06:18.412594 == TX Byte 0 ==
4763 11:06:18.415751 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4764 11:06:18.419121 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4765 11:06:18.421808 == TX Byte 1 ==
4766 11:06:18.425627 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4767 11:06:18.428505 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4768 11:06:18.432026
4769 11:06:18.432407 [DATLAT]
4770 11:06:18.432704 Freq=600, CH1 RK1
4771 11:06:18.432982
4772 11:06:18.435149 DATLAT Default: 0x9
4773 11:06:18.435532 0, 0xFFFF, sum = 0
4774 11:06:18.438246 1, 0xFFFF, sum = 0
4775 11:06:18.438639 2, 0xFFFF, sum = 0
4776 11:06:18.441927 3, 0xFFFF, sum = 0
4777 11:06:18.445681 4, 0xFFFF, sum = 0
4778 11:06:18.446086 5, 0xFFFF, sum = 0
4779 11:06:18.448364 6, 0xFFFF, sum = 0
4780 11:06:18.448699 7, 0xFFFF, sum = 0
4781 11:06:18.451813 8, 0x0, sum = 1
4782 11:06:18.452090 9, 0x0, sum = 2
4783 11:06:18.452308 10, 0x0, sum = 3
4784 11:06:18.454665 11, 0x0, sum = 4
4785 11:06:18.454955 best_step = 9
4786 11:06:18.455121
4787 11:06:18.455290 ==
4788 11:06:18.458038 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 11:06:18.464612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 11:06:18.464755 ==
4791 11:06:18.464865 RX Vref Scan: 0
4792 11:06:18.464965
4793 11:06:18.467910 RX Vref 0 -> 0, step: 1
4794 11:06:18.468049
4795 11:06:18.471226 RX Delay -179 -> 252, step: 8
4796 11:06:18.474400 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4797 11:06:18.481037 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4798 11:06:18.484752 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4799 11:06:18.487384 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4800 11:06:18.491019 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4801 11:06:18.497109 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4802 11:06:18.500662 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4803 11:06:18.503777 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4804 11:06:18.507214 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4805 11:06:18.513633 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4806 11:06:18.517134 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4807 11:06:18.520685 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4808 11:06:18.524068 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4809 11:06:18.530789 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4810 11:06:18.534617 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4811 11:06:18.537128 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4812 11:06:18.537294 ==
4813 11:06:18.540593 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 11:06:18.543627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 11:06:18.546697 ==
4816 11:06:18.546825 DQS Delay:
4817 11:06:18.546893 DQS0 = 0, DQS1 = 0
4818 11:06:18.550989 DQM Delay:
4819 11:06:18.551152 DQM0 = 37, DQM1 = 35
4820 11:06:18.553585 DQ Delay:
4821 11:06:18.557013 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4822 11:06:18.557154 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4823 11:06:18.560032 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4824 11:06:18.566819 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4825 11:06:18.567039
4826 11:06:18.567165
4827 11:06:18.573348 [DQSOSCAuto] RK1, (LSB)MR18= 0x375c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4828 11:06:18.576265 CH1 RK1: MR19=808, MR18=375C
4829 11:06:18.582796 CH1_RK1: MR19=0x808, MR18=0x375C, DQSOSC=392, MR23=63, INC=170, DEC=113
4830 11:06:18.586272 [RxdqsGatingPostProcess] freq 600
4831 11:06:18.589913 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4832 11:06:18.593058 Pre-setting of DQS Precalculation
4833 11:06:18.599897 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4834 11:06:18.606229 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4835 11:06:18.612829 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4836 11:06:18.613012
4837 11:06:18.613130
4838 11:06:18.615946 [Calibration Summary] 1200 Mbps
4839 11:06:18.616085 CH 0, Rank 0
4840 11:06:18.619259 SW Impedance : PASS
4841 11:06:18.622869 DUTY Scan : NO K
4842 11:06:18.623001 ZQ Calibration : PASS
4843 11:06:18.625875 Jitter Meter : NO K
4844 11:06:18.629102 CBT Training : PASS
4845 11:06:18.629256 Write leveling : PASS
4846 11:06:18.632633 RX DQS gating : PASS
4847 11:06:18.636130 RX DQ/DQS(RDDQC) : PASS
4848 11:06:18.636210 TX DQ/DQS : PASS
4849 11:06:18.639120 RX DATLAT : PASS
4850 11:06:18.642680 RX DQ/DQS(Engine): PASS
4851 11:06:18.642767 TX OE : NO K
4852 11:06:18.642835 All Pass.
4853 11:06:18.645719
4854 11:06:18.645805 CH 0, Rank 1
4855 11:06:18.649003 SW Impedance : PASS
4856 11:06:18.649096 DUTY Scan : NO K
4857 11:06:18.652555 ZQ Calibration : PASS
4858 11:06:18.655712 Jitter Meter : NO K
4859 11:06:18.655884 CBT Training : PASS
4860 11:06:18.658933 Write leveling : PASS
4861 11:06:18.659076 RX DQS gating : PASS
4862 11:06:18.662419 RX DQ/DQS(RDDQC) : PASS
4863 11:06:18.665969 TX DQ/DQS : PASS
4864 11:06:18.666161 RX DATLAT : PASS
4865 11:06:18.668899 RX DQ/DQS(Engine): PASS
4866 11:06:18.672674 TX OE : NO K
4867 11:06:18.673045 All Pass.
4868 11:06:18.673388
4869 11:06:18.673671 CH 1, Rank 0
4870 11:06:18.676102 SW Impedance : PASS
4871 11:06:18.679543 DUTY Scan : NO K
4872 11:06:18.679931 ZQ Calibration : PASS
4873 11:06:18.682796 Jitter Meter : NO K
4874 11:06:18.685733 CBT Training : PASS
4875 11:06:18.686122 Write leveling : PASS
4876 11:06:18.688865 RX DQS gating : PASS
4877 11:06:18.692180 RX DQ/DQS(RDDQC) : PASS
4878 11:06:18.692612 TX DQ/DQS : PASS
4879 11:06:18.695947 RX DATLAT : PASS
4880 11:06:18.699085 RX DQ/DQS(Engine): PASS
4881 11:06:18.699468 TX OE : NO K
4882 11:06:18.702175 All Pass.
4883 11:06:18.702690
4884 11:06:18.703004 CH 1, Rank 1
4885 11:06:18.705978 SW Impedance : PASS
4886 11:06:18.706362 DUTY Scan : NO K
4887 11:06:18.709071 ZQ Calibration : PASS
4888 11:06:18.712758 Jitter Meter : NO K
4889 11:06:18.713374 CBT Training : PASS
4890 11:06:18.715313 Write leveling : PASS
4891 11:06:18.718749 RX DQS gating : PASS
4892 11:06:18.719193 RX DQ/DQS(RDDQC) : PASS
4893 11:06:18.721960 TX DQ/DQS : PASS
4894 11:06:18.722346 RX DATLAT : PASS
4895 11:06:18.726158 RX DQ/DQS(Engine): PASS
4896 11:06:18.728561 TX OE : NO K
4897 11:06:18.729042 All Pass.
4898 11:06:18.729401
4899 11:06:18.731713 DramC Write-DBI off
4900 11:06:18.735006 PER_BANK_REFRESH: Hybrid Mode
4901 11:06:18.735398 TX_TRACKING: ON
4902 11:06:18.745209 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4903 11:06:18.748279 [FAST_K] Save calibration result to emmc
4904 11:06:18.751928 dramc_set_vcore_voltage set vcore to 662500
4905 11:06:18.755019 Read voltage for 933, 3
4906 11:06:18.755504 Vio18 = 0
4907 11:06:18.755810 Vcore = 662500
4908 11:06:18.758150 Vdram = 0
4909 11:06:18.758533 Vddq = 0
4910 11:06:18.758834 Vmddr = 0
4911 11:06:18.764707 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4912 11:06:18.768312 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4913 11:06:18.771411 MEM_TYPE=3, freq_sel=17
4914 11:06:18.774813 sv_algorithm_assistance_LP4_1600
4915 11:06:18.778224 ============ PULL DRAM RESETB DOWN ============
4916 11:06:18.781638 ========== PULL DRAM RESETB DOWN end =========
4917 11:06:18.788041 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4918 11:06:18.791275 ===================================
4919 11:06:18.791659 LPDDR4 DRAM CONFIGURATION
4920 11:06:18.794565 ===================================
4921 11:06:18.797700 EX_ROW_EN[0] = 0x0
4922 11:06:18.801299 EX_ROW_EN[1] = 0x0
4923 11:06:18.801755 LP4Y_EN = 0x0
4924 11:06:18.804233 WORK_FSP = 0x0
4925 11:06:18.804631 WL = 0x3
4926 11:06:18.807694 RL = 0x3
4927 11:06:18.808073 BL = 0x2
4928 11:06:18.810970 RPST = 0x0
4929 11:06:18.811433 RD_PRE = 0x0
4930 11:06:18.814317 WR_PRE = 0x1
4931 11:06:18.814794 WR_PST = 0x0
4932 11:06:18.817959 DBI_WR = 0x0
4933 11:06:18.818422 DBI_RD = 0x0
4934 11:06:18.820593 OTF = 0x1
4935 11:06:18.824485 ===================================
4936 11:06:18.827557 ===================================
4937 11:06:18.828053 ANA top config
4938 11:06:18.830405 ===================================
4939 11:06:18.833844 DLL_ASYNC_EN = 0
4940 11:06:18.837635 ALL_SLAVE_EN = 1
4941 11:06:18.840809 NEW_RANK_MODE = 1
4942 11:06:18.843949 DLL_IDLE_MODE = 1
4943 11:06:18.844544 LP45_APHY_COMB_EN = 1
4944 11:06:18.847060 TX_ODT_DIS = 1
4945 11:06:18.850425 NEW_8X_MODE = 1
4946 11:06:18.853738 ===================================
4947 11:06:18.856846 ===================================
4948 11:06:18.860358 data_rate = 1866
4949 11:06:18.863863 CKR = 1
4950 11:06:18.864249 DQ_P2S_RATIO = 8
4951 11:06:18.867079 ===================================
4952 11:06:18.870629 CA_P2S_RATIO = 8
4953 11:06:18.874238 DQ_CA_OPEN = 0
4954 11:06:18.876916 DQ_SEMI_OPEN = 0
4955 11:06:18.880045 CA_SEMI_OPEN = 0
4956 11:06:18.884176 CA_FULL_RATE = 0
4957 11:06:18.884633 DQ_CKDIV4_EN = 1
4958 11:06:18.886848 CA_CKDIV4_EN = 1
4959 11:06:18.890247 CA_PREDIV_EN = 0
4960 11:06:18.893463 PH8_DLY = 0
4961 11:06:18.896933 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4962 11:06:18.900265 DQ_AAMCK_DIV = 4
4963 11:06:18.900654 CA_AAMCK_DIV = 4
4964 11:06:18.903605 CA_ADMCK_DIV = 4
4965 11:06:18.906634 DQ_TRACK_CA_EN = 0
4966 11:06:18.909744 CA_PICK = 933
4967 11:06:18.913493 CA_MCKIO = 933
4968 11:06:18.916662 MCKIO_SEMI = 0
4969 11:06:18.919669 PLL_FREQ = 3732
4970 11:06:18.920157 DQ_UI_PI_RATIO = 32
4971 11:06:18.923179 CA_UI_PI_RATIO = 0
4972 11:06:18.926358 ===================================
4973 11:06:18.929841 ===================================
4974 11:06:18.933017 memory_type:LPDDR4
4975 11:06:18.936340 GP_NUM : 10
4976 11:06:18.936724 SRAM_EN : 1
4977 11:06:18.939893 MD32_EN : 0
4978 11:06:18.943647 ===================================
4979 11:06:18.946167 [ANA_INIT] >>>>>>>>>>>>>>
4980 11:06:18.949506 <<<<<< [CONFIGURE PHASE]: ANA_TX
4981 11:06:18.952565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4982 11:06:18.956157 ===================================
4983 11:06:18.956545 data_rate = 1866,PCW = 0X8f00
4984 11:06:18.959321 ===================================
4985 11:06:18.962945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4986 11:06:18.969283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 11:06:18.976291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 11:06:18.979471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4989 11:06:18.982850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4990 11:06:18.985446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4991 11:06:18.988945 [ANA_INIT] flow start
4992 11:06:18.992021 [ANA_INIT] PLL >>>>>>>>
4993 11:06:18.992403 [ANA_INIT] PLL <<<<<<<<
4994 11:06:18.995513 [ANA_INIT] MIDPI >>>>>>>>
4995 11:06:18.998618 [ANA_INIT] MIDPI <<<<<<<<
4996 11:06:18.999002 [ANA_INIT] DLL >>>>>>>>
4997 11:06:19.002377 [ANA_INIT] flow end
4998 11:06:19.005421 ============ LP4 DIFF to SE enter ============
4999 11:06:19.008773 ============ LP4 DIFF to SE exit ============
5000 11:06:19.012639 [ANA_INIT] <<<<<<<<<<<<<
5001 11:06:19.015141 [Flow] Enable top DCM control >>>>>
5002 11:06:19.018531 [Flow] Enable top DCM control <<<<<
5003 11:06:19.022374 Enable DLL master slave shuffle
5004 11:06:19.028879 ==============================================================
5005 11:06:19.029502 Gating Mode config
5006 11:06:19.034792 ==============================================================
5007 11:06:19.038218 Config description:
5008 11:06:19.045171 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5009 11:06:19.051478 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5010 11:06:19.058317 SELPH_MODE 0: By rank 1: By Phase
5011 11:06:19.064803 ==============================================================
5012 11:06:19.065329 GAT_TRACK_EN = 1
5013 11:06:19.068541 RX_GATING_MODE = 2
5014 11:06:19.071547 RX_GATING_TRACK_MODE = 2
5015 11:06:19.074831 SELPH_MODE = 1
5016 11:06:19.077883 PICG_EARLY_EN = 1
5017 11:06:19.081496 VALID_LAT_VALUE = 1
5018 11:06:19.087929 ==============================================================
5019 11:06:19.091017 Enter into Gating configuration >>>>
5020 11:06:19.094244 Exit from Gating configuration <<<<
5021 11:06:19.097793 Enter into DVFS_PRE_config >>>>>
5022 11:06:19.107568 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5023 11:06:19.111300 Exit from DVFS_PRE_config <<<<<
5024 11:06:19.115252 Enter into PICG configuration >>>>
5025 11:06:19.117803 Exit from PICG configuration <<<<
5026 11:06:19.121114 [RX_INPUT] configuration >>>>>
5027 11:06:19.124109 [RX_INPUT] configuration <<<<<
5028 11:06:19.128058 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5029 11:06:19.133948 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5030 11:06:19.140610 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 11:06:19.147472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 11:06:19.150457 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 11:06:19.156941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 11:06:19.160405 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5035 11:06:19.166906 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5036 11:06:19.170437 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5037 11:06:19.173796 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5038 11:06:19.176974 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5039 11:06:19.183799 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 11:06:19.187383 ===================================
5041 11:06:19.189905 LPDDR4 DRAM CONFIGURATION
5042 11:06:19.193203 ===================================
5043 11:06:19.193670 EX_ROW_EN[0] = 0x0
5044 11:06:19.196382 EX_ROW_EN[1] = 0x0
5045 11:06:19.196765 LP4Y_EN = 0x0
5046 11:06:19.199609 WORK_FSP = 0x0
5047 11:06:19.199998 WL = 0x3
5048 11:06:19.202893 RL = 0x3
5049 11:06:19.203279 BL = 0x2
5050 11:06:19.206232 RPST = 0x0
5051 11:06:19.206619 RD_PRE = 0x0
5052 11:06:19.209781 WR_PRE = 0x1
5053 11:06:19.212933 WR_PST = 0x0
5054 11:06:19.213437 DBI_WR = 0x0
5055 11:06:19.216422 DBI_RD = 0x0
5056 11:06:19.216805 OTF = 0x1
5057 11:06:19.219531 ===================================
5058 11:06:19.222809 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5059 11:06:19.229229 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5060 11:06:19.232508 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 11:06:19.235992 ===================================
5062 11:06:19.239332 LPDDR4 DRAM CONFIGURATION
5063 11:06:19.242520 ===================================
5064 11:06:19.242982 EX_ROW_EN[0] = 0x10
5065 11:06:19.245581 EX_ROW_EN[1] = 0x0
5066 11:06:19.245967 LP4Y_EN = 0x0
5067 11:06:19.249166 WORK_FSP = 0x0
5068 11:06:19.249555 WL = 0x3
5069 11:06:19.252338 RL = 0x3
5070 11:06:19.255946 BL = 0x2
5071 11:06:19.256418 RPST = 0x0
5072 11:06:19.259665 RD_PRE = 0x0
5073 11:06:19.260121 WR_PRE = 0x1
5074 11:06:19.262481 WR_PST = 0x0
5075 11:06:19.262867 DBI_WR = 0x0
5076 11:06:19.265677 DBI_RD = 0x0
5077 11:06:19.266066 OTF = 0x1
5078 11:06:19.269020 ===================================
5079 11:06:19.275392 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5080 11:06:19.279389 nWR fixed to 30
5081 11:06:19.282748 [ModeRegInit_LP4] CH0 RK0
5082 11:06:19.283341 [ModeRegInit_LP4] CH0 RK1
5083 11:06:19.286149 [ModeRegInit_LP4] CH1 RK0
5084 11:06:19.288992 [ModeRegInit_LP4] CH1 RK1
5085 11:06:19.289482 match AC timing 9
5086 11:06:19.296027 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5087 11:06:19.299225 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5088 11:06:19.302567 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5089 11:06:19.308934 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5090 11:06:19.313050 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5091 11:06:19.313559 ==
5092 11:06:19.315787 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 11:06:19.318952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 11:06:19.319571 ==
5095 11:06:19.325572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 11:06:19.331829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5097 11:06:19.335233 [CA 0] Center 37 (7~68) winsize 62
5098 11:06:19.338667 [CA 1] Center 37 (7~68) winsize 62
5099 11:06:19.341949 [CA 2] Center 34 (4~65) winsize 62
5100 11:06:19.344980 [CA 3] Center 34 (4~65) winsize 62
5101 11:06:19.348976 [CA 4] Center 33 (3~63) winsize 61
5102 11:06:19.351863 [CA 5] Center 33 (3~63) winsize 61
5103 11:06:19.352338
5104 11:06:19.355549 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5105 11:06:19.356013
5106 11:06:19.358970 [CATrainingPosCal] consider 1 rank data
5107 11:06:19.361347 u2DelayCellTimex100 = 270/100 ps
5108 11:06:19.364974 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5109 11:06:19.367988 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5110 11:06:19.371798 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5111 11:06:19.378315 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5112 11:06:19.381540 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5113 11:06:19.384658 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5114 11:06:19.385119
5115 11:06:19.388097 CA PerBit enable=1, Macro0, CA PI delay=33
5116 11:06:19.388481
5117 11:06:19.391263 [CBTSetCACLKResult] CA Dly = 33
5118 11:06:19.391648 CS Dly: 6 (0~37)
5119 11:06:19.391953 ==
5120 11:06:19.394121 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 11:06:19.401120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 11:06:19.401539 ==
5123 11:06:19.404557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 11:06:19.411075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 11:06:19.414756 [CA 0] Center 38 (7~69) winsize 63
5126 11:06:19.418132 [CA 1] Center 37 (7~68) winsize 62
5127 11:06:19.420977 [CA 2] Center 34 (4~65) winsize 62
5128 11:06:19.424612 [CA 3] Center 34 (4~65) winsize 62
5129 11:06:19.427821 [CA 4] Center 33 (3~64) winsize 62
5130 11:06:19.430886 [CA 5] Center 32 (2~63) winsize 62
5131 11:06:19.431278
5132 11:06:19.434349 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 11:06:19.434815
5134 11:06:19.437864 [CATrainingPosCal] consider 2 rank data
5135 11:06:19.441310 u2DelayCellTimex100 = 270/100 ps
5136 11:06:19.444499 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5137 11:06:19.450858 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5138 11:06:19.453802 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5139 11:06:19.457303 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5140 11:06:19.460606 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5141 11:06:19.463903 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5142 11:06:19.464388
5143 11:06:19.467245 CA PerBit enable=1, Macro0, CA PI delay=33
5144 11:06:19.467626
5145 11:06:19.470413 [CBTSetCACLKResult] CA Dly = 33
5146 11:06:19.473727 CS Dly: 7 (0~39)
5147 11:06:19.474104
5148 11:06:19.477053 ----->DramcWriteLeveling(PI) begin...
5149 11:06:19.477592 ==
5150 11:06:19.480534 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 11:06:19.483674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 11:06:19.484136 ==
5153 11:06:19.487058 Write leveling (Byte 0): 31 => 31
5154 11:06:19.490180 Write leveling (Byte 1): 28 => 28
5155 11:06:19.493407 DramcWriteLeveling(PI) end<-----
5156 11:06:19.493901
5157 11:06:19.494206 ==
5158 11:06:19.496982 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 11:06:19.500017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 11:06:19.500400 ==
5161 11:06:19.503644 [Gating] SW mode calibration
5162 11:06:19.509988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5163 11:06:19.516761 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5164 11:06:19.519709 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5165 11:06:19.526266 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 11:06:19.529507 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 11:06:19.533037 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 11:06:19.539590 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 11:06:19.542720 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 11:06:19.546105 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5171 11:06:19.552476 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
5172 11:06:19.556030 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5173 11:06:19.558981 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 11:06:19.565561 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 11:06:19.569117 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 11:06:19.572478 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 11:06:19.578993 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 11:06:19.581982 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5179 11:06:19.585608 0 15 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
5180 11:06:19.591824 1 0 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5181 11:06:19.595053 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 11:06:19.598456 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 11:06:19.605837 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 11:06:19.608266 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 11:06:19.611444 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 11:06:19.618302 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 11:06:19.621641 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 11:06:19.625086 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5189 11:06:19.631612 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:06:19.635228 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:06:19.638293 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:06:19.645023 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:06:19.648101 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:06:19.651909 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:06:19.658530 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:06:19.660997 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:06:19.664672 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:06:19.670917 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:06:19.674675 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:06:19.677914 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:06:19.684781 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:06:19.687702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5203 11:06:19.691302 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5204 11:06:19.697530 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5205 11:06:19.697941 Total UI for P1: 0, mck2ui 16
5206 11:06:19.704353 best dqsien dly found for B0: ( 1, 2, 26)
5207 11:06:19.707490 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:06:19.710444 Total UI for P1: 0, mck2ui 16
5209 11:06:19.713616 best dqsien dly found for B1: ( 1, 3, 0)
5210 11:06:19.717195 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5211 11:06:19.720595 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5212 11:06:19.721054
5213 11:06:19.724312 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5214 11:06:19.727272 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5215 11:06:19.730063 [Gating] SW calibration Done
5216 11:06:19.730481 ==
5217 11:06:19.733643 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 11:06:19.736630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 11:06:19.740210 ==
5220 11:06:19.740689 RX Vref Scan: 0
5221 11:06:19.740996
5222 11:06:19.743281 RX Vref 0 -> 0, step: 1
5223 11:06:19.743666
5224 11:06:19.746689 RX Delay -80 -> 252, step: 8
5225 11:06:19.750237 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5226 11:06:19.753169 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5227 11:06:19.756759 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5228 11:06:19.759956 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5229 11:06:19.763146 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5230 11:06:19.769904 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5231 11:06:19.773062 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5232 11:06:19.777280 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5233 11:06:19.779789 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5234 11:06:19.782564 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5235 11:06:19.789525 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5236 11:06:19.793285 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5237 11:06:19.796045 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5238 11:06:19.799519 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5239 11:06:19.802738 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5240 11:06:19.806166 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5241 11:06:19.806600 ==
5242 11:06:19.809334 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 11:06:19.816364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 11:06:19.816823 ==
5245 11:06:19.817129 DQS Delay:
5246 11:06:19.819466 DQS0 = 0, DQS1 = 0
5247 11:06:19.819932 DQM Delay:
5248 11:06:19.822782 DQM0 = 98, DQM1 = 89
5249 11:06:19.823243 DQ Delay:
5250 11:06:19.825710 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5251 11:06:19.829003 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5252 11:06:19.832594 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5253 11:06:19.835638 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5254 11:06:19.836021
5255 11:06:19.836322
5256 11:06:19.836594 ==
5257 11:06:19.839196 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:06:19.842553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:06:19.842941 ==
5260 11:06:19.843241
5261 11:06:19.843514
5262 11:06:19.845415 TX Vref Scan disable
5263 11:06:19.849101 == TX Byte 0 ==
5264 11:06:19.852298 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5265 11:06:19.855287 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5266 11:06:19.858658 == TX Byte 1 ==
5267 11:06:19.861774 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5268 11:06:19.865107 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5269 11:06:19.865520 ==
5270 11:06:19.869066 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:06:19.875391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:06:19.875860 ==
5273 11:06:19.876166
5274 11:06:19.876442
5275 11:06:19.876702 TX Vref Scan disable
5276 11:06:19.879988 == TX Byte 0 ==
5277 11:06:19.882553 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5278 11:06:19.889361 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5279 11:06:19.889746 == TX Byte 1 ==
5280 11:06:19.892545 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5281 11:06:19.899014 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5282 11:06:19.899397
5283 11:06:19.899693 [DATLAT]
5284 11:06:19.899965 Freq=933, CH0 RK0
5285 11:06:19.900229
5286 11:06:19.902340 DATLAT Default: 0xd
5287 11:06:19.902721 0, 0xFFFF, sum = 0
5288 11:06:19.905890 1, 0xFFFF, sum = 0
5289 11:06:19.906275 2, 0xFFFF, sum = 0
5290 11:06:19.909119 3, 0xFFFF, sum = 0
5291 11:06:19.912851 4, 0xFFFF, sum = 0
5292 11:06:19.913265 5, 0xFFFF, sum = 0
5293 11:06:19.915636 6, 0xFFFF, sum = 0
5294 11:06:19.916035 7, 0xFFFF, sum = 0
5295 11:06:19.919153 8, 0xFFFF, sum = 0
5296 11:06:19.919635 9, 0xFFFF, sum = 0
5297 11:06:19.922362 10, 0x0, sum = 1
5298 11:06:19.922827 11, 0x0, sum = 2
5299 11:06:19.925802 12, 0x0, sum = 3
5300 11:06:19.926264 13, 0x0, sum = 4
5301 11:06:19.926572 best_step = 11
5302 11:06:19.926846
5303 11:06:19.929109 ==
5304 11:06:19.932637 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 11:06:19.935668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 11:06:19.936086 ==
5307 11:06:19.936395 RX Vref Scan: 1
5308 11:06:19.936675
5309 11:06:19.938621 RX Vref 0 -> 0, step: 1
5310 11:06:19.939005
5311 11:06:19.942031 RX Delay -61 -> 252, step: 4
5312 11:06:19.942416
5313 11:06:19.945641 Set Vref, RX VrefLevel [Byte0]: 54
5314 11:06:19.948425 [Byte1]: 45
5315 11:06:19.952112
5316 11:06:19.952498 Final RX Vref Byte 0 = 54 to rank0
5317 11:06:19.955434 Final RX Vref Byte 1 = 45 to rank0
5318 11:06:19.958634 Final RX Vref Byte 0 = 54 to rank1
5319 11:06:19.961984 Final RX Vref Byte 1 = 45 to rank1==
5320 11:06:19.965862 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 11:06:19.968464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 11:06:19.972476 ==
5323 11:06:19.972928 DQS Delay:
5324 11:06:19.973277 DQS0 = 0, DQS1 = 0
5325 11:06:19.975227 DQM Delay:
5326 11:06:19.975695 DQM0 = 98, DQM1 = 86
5327 11:06:19.978622 DQ Delay:
5328 11:06:19.981715 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5329 11:06:19.985488 DQ4 =98, DQ5 =90, DQ6 =108, DQ7 =104
5330 11:06:19.988890 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =82
5331 11:06:19.991762 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =96
5332 11:06:19.992140
5333 11:06:19.992433
5334 11:06:19.998452 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5335 11:06:20.001561 CH0 RK0: MR19=505, MR18=1A15
5336 11:06:20.008289 CH0_RK0: MR19=0x505, MR18=0x1A15, DQSOSC=413, MR23=63, INC=63, DEC=42
5337 11:06:20.008776
5338 11:06:20.011779 ----->DramcWriteLeveling(PI) begin...
5339 11:06:20.012243 ==
5340 11:06:20.014562 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 11:06:20.018456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 11:06:20.018926 ==
5343 11:06:20.021801 Write leveling (Byte 0): 33 => 33
5344 11:06:20.024643 Write leveling (Byte 1): 30 => 30
5345 11:06:20.027780 DramcWriteLeveling(PI) end<-----
5346 11:06:20.028181
5347 11:06:20.028476 ==
5348 11:06:20.031137 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 11:06:20.035197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 11:06:20.037980 ==
5351 11:06:20.038364 [Gating] SW mode calibration
5352 11:06:20.044892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 11:06:20.051061 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 11:06:20.054293 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5355 11:06:20.060925 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 11:06:20.064417 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 11:06:20.067523 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 11:06:20.074235 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 11:06:20.077570 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 11:06:20.081541 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5361 11:06:20.087210 0 14 28 | B1->B0 | 3232 2828 | 1 0 | (1 0) (0 0)
5362 11:06:20.090799 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5363 11:06:20.094106 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 11:06:20.100374 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 11:06:20.103943 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 11:06:20.107040 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 11:06:20.114114 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 11:06:20.117098 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5369 11:06:20.120445 0 15 28 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (0 0)
5370 11:06:20.126924 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5371 11:06:20.129904 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:06:20.133253 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 11:06:20.140144 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 11:06:20.143121 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 11:06:20.147064 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 11:06:20.153100 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5377 11:06:20.156617 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5378 11:06:20.159908 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:06:20.166542 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:06:20.169669 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:06:20.174019 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:06:20.179797 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:06:20.182751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:06:20.186368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:06:20.192886 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:06:20.196066 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:06:20.199137 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:06:20.205820 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:06:20.209088 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:06:20.212850 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:06:20.219204 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:06:20.222377 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5393 11:06:20.225440 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5394 11:06:20.232248 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5395 11:06:20.235474 Total UI for P1: 0, mck2ui 16
5396 11:06:20.238698 best dqsien dly found for B0: ( 1, 2, 26)
5397 11:06:20.241957 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 11:06:20.245462 Total UI for P1: 0, mck2ui 16
5399 11:06:20.249072 best dqsien dly found for B1: ( 1, 3, 2)
5400 11:06:20.252731 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5401 11:06:20.255469 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5402 11:06:20.255870
5403 11:06:20.258798 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5404 11:06:20.262115 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5405 11:06:20.265709 [Gating] SW calibration Done
5406 11:06:20.266111 ==
5407 11:06:20.268489 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 11:06:20.272440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 11:06:20.275240 ==
5410 11:06:20.275616 RX Vref Scan: 0
5411 11:06:20.275909
5412 11:06:20.278981 RX Vref 0 -> 0, step: 1
5413 11:06:20.279441
5414 11:06:20.281681 RX Delay -80 -> 252, step: 8
5415 11:06:20.285339 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5416 11:06:20.288666 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5417 11:06:20.292048 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5418 11:06:20.294846 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5419 11:06:20.298495 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5420 11:06:20.305281 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5421 11:06:20.308307 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5422 11:06:20.311239 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5423 11:06:20.314991 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5424 11:06:20.318348 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5425 11:06:20.324605 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5426 11:06:20.327824 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5427 11:06:20.331275 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5428 11:06:20.334413 iDelay=200, Bit 13, Center 95 (8 ~ 183) 176
5429 11:06:20.337877 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5430 11:06:20.341134 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5431 11:06:20.344584 ==
5432 11:06:20.347937 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 11:06:20.351239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 11:06:20.351640 ==
5435 11:06:20.351939 DQS Delay:
5436 11:06:20.354601 DQS0 = 0, DQS1 = 0
5437 11:06:20.355059 DQM Delay:
5438 11:06:20.357769 DQM0 = 98, DQM1 = 88
5439 11:06:20.358150 DQ Delay:
5440 11:06:20.361526 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5441 11:06:20.364046 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5442 11:06:20.367483 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5443 11:06:20.370852 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5444 11:06:20.371237
5445 11:06:20.371537
5446 11:06:20.371809 ==
5447 11:06:20.374492 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 11:06:20.377465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 11:06:20.377969 ==
5450 11:06:20.380771
5451 11:06:20.381324
5452 11:06:20.381665 TX Vref Scan disable
5453 11:06:20.383771 == TX Byte 0 ==
5454 11:06:20.387576 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5455 11:06:20.390951 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5456 11:06:20.393898 == TX Byte 1 ==
5457 11:06:20.397315 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5458 11:06:20.400258 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5459 11:06:20.400643 ==
5460 11:06:20.404142 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 11:06:20.410494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 11:06:20.410887 ==
5463 11:06:20.411192
5464 11:06:20.411468
5465 11:06:20.413418 TX Vref Scan disable
5466 11:06:20.413803 == TX Byte 0 ==
5467 11:06:20.420133 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5468 11:06:20.423537 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5469 11:06:20.424000 == TX Byte 1 ==
5470 11:06:20.430288 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5471 11:06:20.433704 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5472 11:06:20.434091
5473 11:06:20.434391 [DATLAT]
5474 11:06:20.436738 Freq=933, CH0 RK1
5475 11:06:20.437126
5476 11:06:20.437462 DATLAT Default: 0xb
5477 11:06:20.440252 0, 0xFFFF, sum = 0
5478 11:06:20.440662 1, 0xFFFF, sum = 0
5479 11:06:20.444174 2, 0xFFFF, sum = 0
5480 11:06:20.444637 3, 0xFFFF, sum = 0
5481 11:06:20.446961 4, 0xFFFF, sum = 0
5482 11:06:20.447352 5, 0xFFFF, sum = 0
5483 11:06:20.449981 6, 0xFFFF, sum = 0
5484 11:06:20.450371 7, 0xFFFF, sum = 0
5485 11:06:20.453250 8, 0xFFFF, sum = 0
5486 11:06:20.456431 9, 0xFFFF, sum = 0
5487 11:06:20.456846 10, 0x0, sum = 1
5488 11:06:20.457191 11, 0x0, sum = 2
5489 11:06:20.460098 12, 0x0, sum = 3
5490 11:06:20.460564 13, 0x0, sum = 4
5491 11:06:20.463215 best_step = 11
5492 11:06:20.463600
5493 11:06:20.463900 ==
5494 11:06:20.466798 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 11:06:20.469855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 11:06:20.470250 ==
5497 11:06:20.473066 RX Vref Scan: 0
5498 11:06:20.473574
5499 11:06:20.473879 RX Vref 0 -> 0, step: 1
5500 11:06:20.474159
5501 11:06:20.476836 RX Delay -61 -> 252, step: 4
5502 11:06:20.483595 iDelay=195, Bit 0, Center 96 (7 ~ 186) 180
5503 11:06:20.487201 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5504 11:06:20.490552 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5505 11:06:20.493573 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5506 11:06:20.497018 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5507 11:06:20.500311 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5508 11:06:20.506967 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5509 11:06:20.510279 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5510 11:06:20.513682 iDelay=195, Bit 8, Center 78 (-9 ~ 166) 176
5511 11:06:20.516932 iDelay=195, Bit 9, Center 74 (-13 ~ 162) 176
5512 11:06:20.520184 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5513 11:06:20.526829 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5514 11:06:20.529822 iDelay=195, Bit 12, Center 88 (-1 ~ 178) 180
5515 11:06:20.533717 iDelay=195, Bit 13, Center 92 (7 ~ 178) 172
5516 11:06:20.536466 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5517 11:06:20.540609 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5518 11:06:20.541113 ==
5519 11:06:20.543442 Dram Type= 6, Freq= 0, CH_0, rank 1
5520 11:06:20.549992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 11:06:20.550453 ==
5522 11:06:20.550788 DQS Delay:
5523 11:06:20.553215 DQS0 = 0, DQS1 = 0
5524 11:06:20.553601 DQM Delay:
5525 11:06:20.556480 DQM0 = 97, DQM1 = 86
5526 11:06:20.556946 DQ Delay:
5527 11:06:20.560053 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5528 11:06:20.563317 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =106
5529 11:06:20.566697 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5530 11:06:20.569606 DQ12 =88, DQ13 =92, DQ14 =98, DQ15 =94
5531 11:06:20.570029
5532 11:06:20.570356
5533 11:06:20.576860 [DQSOSCAuto] RK1, (LSB)MR18= 0x1917, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5534 11:06:20.580122 CH0 RK1: MR19=505, MR18=1917
5535 11:06:20.586090 CH0_RK1: MR19=0x505, MR18=0x1917, DQSOSC=413, MR23=63, INC=63, DEC=42
5536 11:06:20.589259 [RxdqsGatingPostProcess] freq 933
5537 11:06:20.596799 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5538 11:06:20.599625 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 11:06:20.600009 best DQS1 dly(2T, 0.5T) = (0, 11)
5540 11:06:20.603247 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 11:06:20.606345 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5542 11:06:20.609075 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 11:06:20.612730 best DQS1 dly(2T, 0.5T) = (0, 11)
5544 11:06:20.616068 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 11:06:20.619136 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5546 11:06:20.622544 Pre-setting of DQS Precalculation
5547 11:06:20.628969 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5548 11:06:20.629588 ==
5549 11:06:20.632344 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 11:06:20.635245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 11:06:20.635629 ==
5552 11:06:20.642285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 11:06:20.648413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 11:06:20.651966 [CA 0] Center 36 (6~67) winsize 62
5555 11:06:20.655645 [CA 1] Center 36 (6~67) winsize 62
5556 11:06:20.658265 [CA 2] Center 34 (4~64) winsize 61
5557 11:06:20.661762 [CA 3] Center 33 (3~64) winsize 62
5558 11:06:20.664915 [CA 4] Center 33 (3~64) winsize 62
5559 11:06:20.665446 [CA 5] Center 33 (3~64) winsize 62
5560 11:06:20.668967
5561 11:06:20.671884 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 11:06:20.672374
5563 11:06:20.675432 [CATrainingPosCal] consider 1 rank data
5564 11:06:20.678610 u2DelayCellTimex100 = 270/100 ps
5565 11:06:20.681783 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 11:06:20.685239 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 11:06:20.689042 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 11:06:20.692103 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 11:06:20.694943 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 11:06:20.698227 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 11:06:20.698611
5572 11:06:20.701430 CA PerBit enable=1, Macro0, CA PI delay=33
5573 11:06:20.704768
5574 11:06:20.705184 [CBTSetCACLKResult] CA Dly = 33
5575 11:06:20.708294 CS Dly: 4 (0~35)
5576 11:06:20.708690 ==
5577 11:06:20.711601 Dram Type= 6, Freq= 0, CH_1, rank 1
5578 11:06:20.714569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 11:06:20.714956 ==
5580 11:06:20.721021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5581 11:06:20.727957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5582 11:06:20.731091 [CA 0] Center 36 (6~66) winsize 61
5583 11:06:20.734301 [CA 1] Center 36 (6~67) winsize 62
5584 11:06:20.737613 [CA 2] Center 34 (4~65) winsize 62
5585 11:06:20.740709 [CA 3] Center 33 (3~64) winsize 62
5586 11:06:20.744273 [CA 4] Center 33 (3~64) winsize 62
5587 11:06:20.748013 [CA 5] Center 33 (3~64) winsize 62
5588 11:06:20.748400
5589 11:06:20.750946 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5590 11:06:20.751369
5591 11:06:20.754290 [CATrainingPosCal] consider 2 rank data
5592 11:06:20.757435 u2DelayCellTimex100 = 270/100 ps
5593 11:06:20.761208 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5594 11:06:20.764228 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5595 11:06:20.767151 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5596 11:06:20.770747 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5597 11:06:20.774057 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 11:06:20.780407 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 11:06:20.780848
5600 11:06:20.783846 CA PerBit enable=1, Macro0, CA PI delay=33
5601 11:06:20.784228
5602 11:06:20.787444 [CBTSetCACLKResult] CA Dly = 33
5603 11:06:20.787915 CS Dly: 5 (0~38)
5604 11:06:20.788222
5605 11:06:20.791292 ----->DramcWriteLeveling(PI) begin...
5606 11:06:20.791685 ==
5607 11:06:20.793555 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 11:06:20.800387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 11:06:20.800773 ==
5610 11:06:20.803518 Write leveling (Byte 0): 25 => 25
5611 11:06:20.803906 Write leveling (Byte 1): 29 => 29
5612 11:06:20.806752 DramcWriteLeveling(PI) end<-----
5613 11:06:20.807134
5614 11:06:20.810562 ==
5615 11:06:20.810948 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 11:06:20.816783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 11:06:20.817286 ==
5618 11:06:20.820432 [Gating] SW mode calibration
5619 11:06:20.827016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5620 11:06:20.830184 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5621 11:06:20.836527 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 11:06:20.840035 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 11:06:20.843603 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 11:06:20.850113 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 11:06:20.853385 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 11:06:20.856402 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 11:06:20.862804 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
5628 11:06:20.866368 0 14 28 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (1 0)
5629 11:06:20.869852 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 11:06:20.876639 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 11:06:20.880157 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 11:06:20.882678 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 11:06:20.889464 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 11:06:20.892873 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 11:06:20.896400 0 15 24 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
5636 11:06:20.902482 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5637 11:06:20.906536 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 11:06:20.909290 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 11:06:20.915939 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 11:06:20.919431 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 11:06:20.922687 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 11:06:20.929134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 11:06:20.932565 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 11:06:20.935918 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:06:20.942323 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5646 11:06:20.945592 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:06:20.949131 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:06:20.955698 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:06:20.958579 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:06:20.961924 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:06:20.968399 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:06:20.972547 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:06:20.975394 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:06:20.981760 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:06:20.985121 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:06:20.988713 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:06:20.995474 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:06:20.998753 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:06:21.001456 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5660 11:06:21.008605 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5661 11:06:21.009114 Total UI for P1: 0, mck2ui 16
5662 11:06:21.014603 best dqsien dly found for B1: ( 1, 2, 24)
5663 11:06:21.018406 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:06:21.021546 Total UI for P1: 0, mck2ui 16
5665 11:06:21.024853 best dqsien dly found for B0: ( 1, 2, 26)
5666 11:06:21.028065 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5667 11:06:21.031056 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5668 11:06:21.031444
5669 11:06:21.034392 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5670 11:06:21.037838 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5671 11:06:21.041453 [Gating] SW calibration Done
5672 11:06:21.041845 ==
5673 11:06:21.044219 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 11:06:21.050755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 11:06:21.051229 ==
5676 11:06:21.051538 RX Vref Scan: 0
5677 11:06:21.051815
5678 11:06:21.054277 RX Vref 0 -> 0, step: 1
5679 11:06:21.054665
5680 11:06:21.057658 RX Delay -80 -> 252, step: 8
5681 11:06:21.061038 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5682 11:06:21.064710 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5683 11:06:21.067287 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5684 11:06:21.071057 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5685 11:06:21.074300 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5686 11:06:21.081455 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5687 11:06:21.084977 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5688 11:06:21.087464 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5689 11:06:21.090809 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5690 11:06:21.093986 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5691 11:06:21.100324 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5692 11:06:21.103813 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5693 11:06:21.107803 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5694 11:06:21.110104 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5695 11:06:21.113811 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5696 11:06:21.120156 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5697 11:06:21.120659 ==
5698 11:06:21.123917 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 11:06:21.127136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 11:06:21.127650 ==
5701 11:06:21.127983 DQS Delay:
5702 11:06:21.130381 DQS0 = 0, DQS1 = 0
5703 11:06:21.130892 DQM Delay:
5704 11:06:21.133189 DQM0 = 99, DQM1 = 95
5705 11:06:21.133743 DQ Delay:
5706 11:06:21.136492 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5707 11:06:21.140392 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5708 11:06:21.143605 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5709 11:06:21.146905 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5710 11:06:21.147420
5711 11:06:21.147755
5712 11:06:21.148061 ==
5713 11:06:21.149851 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 11:06:21.156647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 11:06:21.157212 ==
5716 11:06:21.157562
5717 11:06:21.157872
5718 11:06:21.158167 TX Vref Scan disable
5719 11:06:21.159952 == TX Byte 0 ==
5720 11:06:21.163123 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5721 11:06:21.170135 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5722 11:06:21.170589 == TX Byte 1 ==
5723 11:06:21.174398 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5724 11:06:21.180018 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5725 11:06:21.180486 ==
5726 11:06:21.183410 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 11:06:21.187009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 11:06:21.187484 ==
5729 11:06:21.187791
5730 11:06:21.188068
5731 11:06:21.189811 TX Vref Scan disable
5732 11:06:21.190199 == TX Byte 0 ==
5733 11:06:21.196253 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5734 11:06:21.199505 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5735 11:06:21.202726 == TX Byte 1 ==
5736 11:06:21.206023 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5737 11:06:21.209293 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5738 11:06:21.209811
5739 11:06:21.210130 [DATLAT]
5740 11:06:21.212632 Freq=933, CH1 RK0
5741 11:06:21.213027
5742 11:06:21.213362 DATLAT Default: 0xd
5743 11:06:21.216454 0, 0xFFFF, sum = 0
5744 11:06:21.219543 1, 0xFFFF, sum = 0
5745 11:06:21.219939 2, 0xFFFF, sum = 0
5746 11:06:21.223085 3, 0xFFFF, sum = 0
5747 11:06:21.223561 4, 0xFFFF, sum = 0
5748 11:06:21.226086 5, 0xFFFF, sum = 0
5749 11:06:21.226580 6, 0xFFFF, sum = 0
5750 11:06:21.229357 7, 0xFFFF, sum = 0
5751 11:06:21.229752 8, 0xFFFF, sum = 0
5752 11:06:21.233652 9, 0xFFFF, sum = 0
5753 11:06:21.234085 10, 0x0, sum = 1
5754 11:06:21.235816 11, 0x0, sum = 2
5755 11:06:21.236214 12, 0x0, sum = 3
5756 11:06:21.238988 13, 0x0, sum = 4
5757 11:06:21.239382 best_step = 11
5758 11:06:21.239679
5759 11:06:21.239960 ==
5760 11:06:21.242257 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 11:06:21.245874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 11:06:21.246269 ==
5763 11:06:21.249459 RX Vref Scan: 1
5764 11:06:21.249844
5765 11:06:21.252848 RX Vref 0 -> 0, step: 1
5766 11:06:21.253273
5767 11:06:21.253580 RX Delay -53 -> 252, step: 4
5768 11:06:21.255899
5769 11:06:21.256363 Set Vref, RX VrefLevel [Byte0]: 51
5770 11:06:21.258694 [Byte1]: 52
5771 11:06:21.263929
5772 11:06:21.264391 Final RX Vref Byte 0 = 51 to rank0
5773 11:06:21.266787 Final RX Vref Byte 1 = 52 to rank0
5774 11:06:21.270347 Final RX Vref Byte 0 = 51 to rank1
5775 11:06:21.273364 Final RX Vref Byte 1 = 52 to rank1==
5776 11:06:21.277233 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 11:06:21.283419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 11:06:21.283808 ==
5779 11:06:21.284145 DQS Delay:
5780 11:06:21.287120 DQS0 = 0, DQS1 = 0
5781 11:06:21.287586 DQM Delay:
5782 11:06:21.287888 DQM0 = 98, DQM1 = 94
5783 11:06:21.290100 DQ Delay:
5784 11:06:21.293803 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =96
5785 11:06:21.296745 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5786 11:06:21.300332 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =88
5787 11:06:21.303142 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5788 11:06:21.303529
5789 11:06:21.303870
5790 11:06:21.309893 [DQSOSCAuto] RK0, (LSB)MR18= 0xe1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 417 ps
5791 11:06:21.314053 CH1 RK0: MR19=505, MR18=E1E
5792 11:06:21.319631 CH1_RK0: MR19=0x505, MR18=0xE1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5793 11:06:21.320024
5794 11:06:21.323091 ----->DramcWriteLeveling(PI) begin...
5795 11:06:21.323564 ==
5796 11:06:21.326295 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 11:06:21.329593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 11:06:21.330068 ==
5799 11:06:21.332929 Write leveling (Byte 0): 25 => 25
5800 11:06:21.336433 Write leveling (Byte 1): 27 => 27
5801 11:06:21.339837 DramcWriteLeveling(PI) end<-----
5802 11:06:21.340221
5803 11:06:21.340519 ==
5804 11:06:21.342979 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 11:06:21.349442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 11:06:21.349901 ==
5807 11:06:21.350208 [Gating] SW mode calibration
5808 11:06:21.359413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 11:06:21.362774 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 11:06:21.368933 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 11:06:21.372195 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 11:06:21.375942 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 11:06:21.382209 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 11:06:21.385445 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 11:06:21.388697 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 11:06:21.395536 0 14 24 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 1)
5817 11:06:21.398826 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5818 11:06:21.402277 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 11:06:21.408415 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 11:06:21.411657 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 11:06:21.415536 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 11:06:21.421922 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 11:06:21.425472 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 11:06:21.428508 0 15 24 | B1->B0 | 2727 3838 | 0 1 | (0 0) (0 0)
5825 11:06:21.434842 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5826 11:06:21.438107 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 11:06:21.441870 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 11:06:21.447864 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 11:06:21.451535 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 11:06:21.454597 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 11:06:21.461132 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 11:06:21.464426 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5833 11:06:21.468089 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5834 11:06:21.474572 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:06:21.478128 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:06:21.481541 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:06:21.488027 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:06:21.491080 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:06:21.494164 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:06:21.500809 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:06:21.504351 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:06:21.507332 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:06:21.513958 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:06:21.517347 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:06:21.520763 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:06:21.527544 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:06:21.530749 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:06:21.534037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:06:21.540875 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 11:06:21.541310 Total UI for P1: 0, mck2ui 16
5851 11:06:21.544112 best dqsien dly found for B0: ( 1, 2, 26)
5852 11:06:21.547126 Total UI for P1: 0, mck2ui 16
5853 11:06:21.550263 best dqsien dly found for B1: ( 1, 2, 26)
5854 11:06:21.557275 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5855 11:06:21.561018 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5856 11:06:21.561533
5857 11:06:21.563875 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5858 11:06:21.566708 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5859 11:06:21.570863 [Gating] SW calibration Done
5860 11:06:21.571329 ==
5861 11:06:21.573604 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 11:06:21.577241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 11:06:21.577715 ==
5864 11:06:21.579845 RX Vref Scan: 0
5865 11:06:21.580229
5866 11:06:21.580527 RX Vref 0 -> 0, step: 1
5867 11:06:21.580805
5868 11:06:21.583493 RX Delay -80 -> 252, step: 8
5869 11:06:21.587133 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5870 11:06:21.593217 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5871 11:06:21.596386 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5872 11:06:21.599921 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5873 11:06:21.603029 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5874 11:06:21.606394 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5875 11:06:21.609617 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5876 11:06:21.616465 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5877 11:06:21.619330 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5878 11:06:21.623202 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5879 11:06:21.625922 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5880 11:06:21.629096 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5881 11:06:21.635429 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5882 11:06:21.638749 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5883 11:06:21.642589 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5884 11:06:21.645739 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5885 11:06:21.646209 ==
5886 11:06:21.648964 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 11:06:21.655536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 11:06:21.655930 ==
5889 11:06:21.656234 DQS Delay:
5890 11:06:21.656513 DQS0 = 0, DQS1 = 0
5891 11:06:21.658613 DQM Delay:
5892 11:06:21.658998 DQM0 = 97, DQM1 = 94
5893 11:06:21.662142 DQ Delay:
5894 11:06:21.665229 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5895 11:06:21.668552 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5896 11:06:21.671818 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5897 11:06:21.675087 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5898 11:06:21.675474
5899 11:06:21.675828
5900 11:06:21.676128 ==
5901 11:06:21.678389 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 11:06:21.681772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 11:06:21.682162 ==
5904 11:06:21.682462
5905 11:06:21.682739
5906 11:06:21.685513 TX Vref Scan disable
5907 11:06:21.688610 == TX Byte 0 ==
5908 11:06:21.691852 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5909 11:06:21.695107 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5910 11:06:21.698394 == TX Byte 1 ==
5911 11:06:21.701822 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 11:06:21.705126 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 11:06:21.705649 ==
5914 11:06:21.709095 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 11:06:21.714543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 11:06:21.714931 ==
5917 11:06:21.715234
5918 11:06:21.715511
5919 11:06:21.715776 TX Vref Scan disable
5920 11:06:21.718861 == TX Byte 0 ==
5921 11:06:21.722164 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5922 11:06:21.728469 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5923 11:06:21.728944 == TX Byte 1 ==
5924 11:06:21.731860 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 11:06:21.738553 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 11:06:21.738994
5927 11:06:21.739327 [DATLAT]
5928 11:06:21.739640 Freq=933, CH1 RK1
5929 11:06:21.739908
5930 11:06:21.741499 DATLAT Default: 0xb
5931 11:06:21.741888 0, 0xFFFF, sum = 0
5932 11:06:21.744743 1, 0xFFFF, sum = 0
5933 11:06:21.748348 2, 0xFFFF, sum = 0
5934 11:06:21.749009 3, 0xFFFF, sum = 0
5935 11:06:21.751583 4, 0xFFFF, sum = 0
5936 11:06:21.752054 5, 0xFFFF, sum = 0
5937 11:06:21.754866 6, 0xFFFF, sum = 0
5938 11:06:21.755259 7, 0xFFFF, sum = 0
5939 11:06:21.758204 8, 0xFFFF, sum = 0
5940 11:06:21.758797 9, 0xFFFF, sum = 0
5941 11:06:21.761514 10, 0x0, sum = 1
5942 11:06:21.761986 11, 0x0, sum = 2
5943 11:06:21.764563 12, 0x0, sum = 3
5944 11:06:21.764958 13, 0x0, sum = 4
5945 11:06:21.765295 best_step = 11
5946 11:06:21.767798
5947 11:06:21.768182 ==
5948 11:06:21.771214 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 11:06:21.774677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 11:06:21.775068 ==
5951 11:06:21.775371 RX Vref Scan: 0
5952 11:06:21.775650
5953 11:06:21.778128 RX Vref 0 -> 0, step: 1
5954 11:06:21.778514
5955 11:06:21.781168 RX Delay -53 -> 252, step: 4
5956 11:06:21.788617 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5957 11:06:21.790804 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5958 11:06:21.794987 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5959 11:06:21.797724 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5960 11:06:21.801366 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5961 11:06:21.804296 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5962 11:06:21.811333 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5963 11:06:21.814100 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5964 11:06:21.817388 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5965 11:06:21.821234 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5966 11:06:21.824440 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5967 11:06:21.830723 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5968 11:06:21.833755 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5969 11:06:21.837298 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5970 11:06:21.841024 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5971 11:06:21.843669 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5972 11:06:21.847463 ==
5973 11:06:21.850578 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 11:06:21.853604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 11:06:21.854040 ==
5976 11:06:21.854375 DQS Delay:
5977 11:06:21.857064 DQS0 = 0, DQS1 = 0
5978 11:06:21.857633 DQM Delay:
5979 11:06:21.860284 DQM0 = 97, DQM1 = 92
5980 11:06:21.860789 DQ Delay:
5981 11:06:21.863588 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5982 11:06:21.866979 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =92
5983 11:06:21.869991 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5984 11:06:21.873077 DQ12 =100, DQ13 =102, DQ14 =98, DQ15 =100
5985 11:06:21.873494
5986 11:06:21.873793
5987 11:06:21.883090 [DQSOSCAuto] RK1, (LSB)MR18= 0x132a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5988 11:06:21.883547 CH1 RK1: MR19=505, MR18=132A
5989 11:06:21.890000 CH1_RK1: MR19=0x505, MR18=0x132A, DQSOSC=408, MR23=63, INC=65, DEC=43
5990 11:06:21.893369 [RxdqsGatingPostProcess] freq 933
5991 11:06:21.899325 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5992 11:06:21.902902 best DQS0 dly(2T, 0.5T) = (0, 10)
5993 11:06:21.906122 best DQS1 dly(2T, 0.5T) = (0, 10)
5994 11:06:21.909600 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5995 11:06:21.913059 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5996 11:06:21.915866 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 11:06:21.916255 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 11:06:21.919908 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 11:06:21.922868 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 11:06:21.926344 Pre-setting of DQS Precalculation
6001 11:06:21.932743 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6002 11:06:21.939417 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6003 11:06:21.946124 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6004 11:06:21.946546
6005 11:06:21.946877
6006 11:06:21.948996 [Calibration Summary] 1866 Mbps
6007 11:06:21.952423 CH 0, Rank 0
6008 11:06:21.952917 SW Impedance : PASS
6009 11:06:21.955922 DUTY Scan : NO K
6010 11:06:21.959467 ZQ Calibration : PASS
6011 11:06:21.959937 Jitter Meter : NO K
6012 11:06:21.962519 CBT Training : PASS
6013 11:06:21.965528 Write leveling : PASS
6014 11:06:21.965920 RX DQS gating : PASS
6015 11:06:21.968807 RX DQ/DQS(RDDQC) : PASS
6016 11:06:21.972451 TX DQ/DQS : PASS
6017 11:06:21.972935 RX DATLAT : PASS
6018 11:06:21.975372 RX DQ/DQS(Engine): PASS
6019 11:06:21.975758 TX OE : NO K
6020 11:06:21.979146 All Pass.
6021 11:06:21.979533
6022 11:06:21.979837 CH 0, Rank 1
6023 11:06:21.982422 SW Impedance : PASS
6024 11:06:21.982809 DUTY Scan : NO K
6025 11:06:21.985665 ZQ Calibration : PASS
6026 11:06:21.988771 Jitter Meter : NO K
6027 11:06:21.989283 CBT Training : PASS
6028 11:06:21.992059 Write leveling : PASS
6029 11:06:21.995091 RX DQS gating : PASS
6030 11:06:21.995481 RX DQ/DQS(RDDQC) : PASS
6031 11:06:21.998785 TX DQ/DQS : PASS
6032 11:06:22.001789 RX DATLAT : PASS
6033 11:06:22.002174 RX DQ/DQS(Engine): PASS
6034 11:06:22.005070 TX OE : NO K
6035 11:06:22.005669 All Pass.
6036 11:06:22.005987
6037 11:06:22.008548 CH 1, Rank 0
6038 11:06:22.009007 SW Impedance : PASS
6039 11:06:22.012053 DUTY Scan : NO K
6040 11:06:22.015126 ZQ Calibration : PASS
6041 11:06:22.015521 Jitter Meter : NO K
6042 11:06:22.018059 CBT Training : PASS
6043 11:06:22.021832 Write leveling : PASS
6044 11:06:22.022320 RX DQS gating : PASS
6045 11:06:22.024835 RX DQ/DQS(RDDQC) : PASS
6046 11:06:22.028013 TX DQ/DQS : PASS
6047 11:06:22.028477 RX DATLAT : PASS
6048 11:06:22.031521 RX DQ/DQS(Engine): PASS
6049 11:06:22.034370 TX OE : NO K
6050 11:06:22.034761 All Pass.
6051 11:06:22.035062
6052 11:06:22.035340 CH 1, Rank 1
6053 11:06:22.038031 SW Impedance : PASS
6054 11:06:22.041543 DUTY Scan : NO K
6055 11:06:22.041943 ZQ Calibration : PASS
6056 11:06:22.044596 Jitter Meter : NO K
6057 11:06:22.048092 CBT Training : PASS
6058 11:06:22.048561 Write leveling : PASS
6059 11:06:22.051535 RX DQS gating : PASS
6060 11:06:22.054719 RX DQ/DQS(RDDQC) : PASS
6061 11:06:22.055188 TX DQ/DQS : PASS
6062 11:06:22.057987 RX DATLAT : PASS
6063 11:06:22.058377 RX DQ/DQS(Engine): PASS
6064 11:06:22.061438 TX OE : NO K
6065 11:06:22.061826 All Pass.
6066 11:06:22.062128
6067 11:06:22.064233 DramC Write-DBI off
6068 11:06:22.067716 PER_BANK_REFRESH: Hybrid Mode
6069 11:06:22.068324 TX_TRACKING: ON
6070 11:06:22.077392 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6071 11:06:22.080928 [FAST_K] Save calibration result to emmc
6072 11:06:22.084088 dramc_set_vcore_voltage set vcore to 650000
6073 11:06:22.086999 Read voltage for 400, 6
6074 11:06:22.087399 Vio18 = 0
6075 11:06:22.091127 Vcore = 650000
6076 11:06:22.091634 Vdram = 0
6077 11:06:22.092070 Vddq = 0
6078 11:06:22.092474 Vmddr = 0
6079 11:06:22.097496 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6080 11:06:22.104045 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6081 11:06:22.104447 MEM_TYPE=3, freq_sel=20
6082 11:06:22.106803 sv_algorithm_assistance_LP4_800
6083 11:06:22.110371 ============ PULL DRAM RESETB DOWN ============
6084 11:06:22.117274 ========== PULL DRAM RESETB DOWN end =========
6085 11:06:22.120275 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6086 11:06:22.123411 ===================================
6087 11:06:22.126584 LPDDR4 DRAM CONFIGURATION
6088 11:06:22.130175 ===================================
6089 11:06:22.130691 EX_ROW_EN[0] = 0x0
6090 11:06:22.133351 EX_ROW_EN[1] = 0x0
6091 11:06:22.136676 LP4Y_EN = 0x0
6092 11:06:22.137206 WORK_FSP = 0x0
6093 11:06:22.139845 WL = 0x2
6094 11:06:22.140232 RL = 0x2
6095 11:06:22.143382 BL = 0x2
6096 11:06:22.143770 RPST = 0x0
6097 11:06:22.146435 RD_PRE = 0x0
6098 11:06:22.146820 WR_PRE = 0x1
6099 11:06:22.150051 WR_PST = 0x0
6100 11:06:22.150440 DBI_WR = 0x0
6101 11:06:22.153210 DBI_RD = 0x0
6102 11:06:22.153601 OTF = 0x1
6103 11:06:22.156776 ===================================
6104 11:06:22.160213 ===================================
6105 11:06:22.163218 ANA top config
6106 11:06:22.166290 ===================================
6107 11:06:22.169626 DLL_ASYNC_EN = 0
6108 11:06:22.170014 ALL_SLAVE_EN = 1
6109 11:06:22.173197 NEW_RANK_MODE = 1
6110 11:06:22.176777 DLL_IDLE_MODE = 1
6111 11:06:22.179483 LP45_APHY_COMB_EN = 1
6112 11:06:22.179874 TX_ODT_DIS = 1
6113 11:06:22.182611 NEW_8X_MODE = 1
6114 11:06:22.186449 ===================================
6115 11:06:22.189279 ===================================
6116 11:06:22.192804 data_rate = 800
6117 11:06:22.195702 CKR = 1
6118 11:06:22.199038 DQ_P2S_RATIO = 4
6119 11:06:22.202693 ===================================
6120 11:06:22.205939 CA_P2S_RATIO = 4
6121 11:06:22.206326 DQ_CA_OPEN = 0
6122 11:06:22.209618 DQ_SEMI_OPEN = 1
6123 11:06:22.212653 CA_SEMI_OPEN = 1
6124 11:06:22.215697 CA_FULL_RATE = 0
6125 11:06:22.219057 DQ_CKDIV4_EN = 0
6126 11:06:22.223162 CA_CKDIV4_EN = 1
6127 11:06:22.223623 CA_PREDIV_EN = 0
6128 11:06:22.226134 PH8_DLY = 0
6129 11:06:22.228615 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6130 11:06:22.232129 DQ_AAMCK_DIV = 0
6131 11:06:22.235322 CA_AAMCK_DIV = 0
6132 11:06:22.238728 CA_ADMCK_DIV = 4
6133 11:06:22.239126 DQ_TRACK_CA_EN = 0
6134 11:06:22.242206 CA_PICK = 800
6135 11:06:22.245618 CA_MCKIO = 400
6136 11:06:22.248737 MCKIO_SEMI = 400
6137 11:06:22.252050 PLL_FREQ = 3016
6138 11:06:22.255813 DQ_UI_PI_RATIO = 32
6139 11:06:22.258572 CA_UI_PI_RATIO = 32
6140 11:06:22.262081 ===================================
6141 11:06:22.265620 ===================================
6142 11:06:22.268526 memory_type:LPDDR4
6143 11:06:22.268989 GP_NUM : 10
6144 11:06:22.272276 SRAM_EN : 1
6145 11:06:22.272745 MD32_EN : 0
6146 11:06:22.275470 ===================================
6147 11:06:22.278612 [ANA_INIT] >>>>>>>>>>>>>>
6148 11:06:22.282180 <<<<<< [CONFIGURE PHASE]: ANA_TX
6149 11:06:22.285133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6150 11:06:22.288553 ===================================
6151 11:06:22.291969 data_rate = 800,PCW = 0X7400
6152 11:06:22.294874 ===================================
6153 11:06:22.298365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6154 11:06:22.304737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6155 11:06:22.315094 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 11:06:22.318189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6157 11:06:22.321250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6158 11:06:22.325122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6159 11:06:22.327842 [ANA_INIT] flow start
6160 11:06:22.331173 [ANA_INIT] PLL >>>>>>>>
6161 11:06:22.331559 [ANA_INIT] PLL <<<<<<<<
6162 11:06:22.334433 [ANA_INIT] MIDPI >>>>>>>>
6163 11:06:22.337971 [ANA_INIT] MIDPI <<<<<<<<
6164 11:06:22.341086 [ANA_INIT] DLL >>>>>>>>
6165 11:06:22.341509 [ANA_INIT] flow end
6166 11:06:22.345124 ============ LP4 DIFF to SE enter ============
6167 11:06:22.350789 ============ LP4 DIFF to SE exit ============
6168 11:06:22.351187 [ANA_INIT] <<<<<<<<<<<<<
6169 11:06:22.354722 [Flow] Enable top DCM control >>>>>
6170 11:06:22.357234 [Flow] Enable top DCM control <<<<<
6171 11:06:22.361292 Enable DLL master slave shuffle
6172 11:06:22.367722 ==============================================================
6173 11:06:22.368181 Gating Mode config
6174 11:06:22.374165 ==============================================================
6175 11:06:22.377279 Config description:
6176 11:06:22.387109 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6177 11:06:22.393762 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6178 11:06:22.397417 SELPH_MODE 0: By rank 1: By Phase
6179 11:06:22.403342 ==============================================================
6180 11:06:22.407908 GAT_TRACK_EN = 0
6181 11:06:22.410125 RX_GATING_MODE = 2
6182 11:06:22.413220 RX_GATING_TRACK_MODE = 2
6183 11:06:22.416499 SELPH_MODE = 1
6184 11:06:22.416890 PICG_EARLY_EN = 1
6185 11:06:22.419829 VALID_LAT_VALUE = 1
6186 11:06:22.426340 ==============================================================
6187 11:06:22.430080 Enter into Gating configuration >>>>
6188 11:06:22.433059 Exit from Gating configuration <<<<
6189 11:06:22.436534 Enter into DVFS_PRE_config >>>>>
6190 11:06:22.446319 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6191 11:06:22.449532 Exit from DVFS_PRE_config <<<<<
6192 11:06:22.452874 Enter into PICG configuration >>>>
6193 11:06:22.456528 Exit from PICG configuration <<<<
6194 11:06:22.459529 [RX_INPUT] configuration >>>>>
6195 11:06:22.463004 [RX_INPUT] configuration <<<<<
6196 11:06:22.469196 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6197 11:06:22.472512 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6198 11:06:22.479292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 11:06:22.486057 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 11:06:22.492878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 11:06:22.499481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 11:06:22.502238 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6203 11:06:22.505635 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6204 11:06:22.509207 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6205 11:06:22.515958 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6206 11:06:22.518768 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6207 11:06:22.521975 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 11:06:22.524978 ===================================
6209 11:06:22.528421 LPDDR4 DRAM CONFIGURATION
6210 11:06:22.531490 ===================================
6211 11:06:22.531973 EX_ROW_EN[0] = 0x0
6212 11:06:22.535000 EX_ROW_EN[1] = 0x0
6213 11:06:22.538312 LP4Y_EN = 0x0
6214 11:06:22.538732 WORK_FSP = 0x0
6215 11:06:22.541648 WL = 0x2
6216 11:06:22.542177 RL = 0x2
6217 11:06:22.544773 BL = 0x2
6218 11:06:22.545335 RPST = 0x0
6219 11:06:22.548085 RD_PRE = 0x0
6220 11:06:22.548591 WR_PRE = 0x1
6221 11:06:22.551734 WR_PST = 0x0
6222 11:06:22.552146 DBI_WR = 0x0
6223 11:06:22.554583 DBI_RD = 0x0
6224 11:06:22.555017 OTF = 0x1
6225 11:06:22.558308 ===================================
6226 11:06:22.561021 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6227 11:06:22.567447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6228 11:06:22.571020 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 11:06:22.574280 ===================================
6230 11:06:22.577798 LPDDR4 DRAM CONFIGURATION
6231 11:06:22.581180 ===================================
6232 11:06:22.581259 EX_ROW_EN[0] = 0x10
6233 11:06:22.584128 EX_ROW_EN[1] = 0x0
6234 11:06:22.587451 LP4Y_EN = 0x0
6235 11:06:22.587528 WORK_FSP = 0x0
6236 11:06:22.590745 WL = 0x2
6237 11:06:22.590822 RL = 0x2
6238 11:06:22.594394 BL = 0x2
6239 11:06:22.594459 RPST = 0x0
6240 11:06:22.597397 RD_PRE = 0x0
6241 11:06:22.597479 WR_PRE = 0x1
6242 11:06:22.600383 WR_PST = 0x0
6243 11:06:22.600486 DBI_WR = 0x0
6244 11:06:22.603949 DBI_RD = 0x0
6245 11:06:22.604029 OTF = 0x1
6246 11:06:22.607904 ===================================
6247 11:06:22.614255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6248 11:06:22.618629 nWR fixed to 30
6249 11:06:22.622078 [ModeRegInit_LP4] CH0 RK0
6250 11:06:22.622203 [ModeRegInit_LP4] CH0 RK1
6251 11:06:22.625372 [ModeRegInit_LP4] CH1 RK0
6252 11:06:22.628782 [ModeRegInit_LP4] CH1 RK1
6253 11:06:22.628952 match AC timing 19
6254 11:06:22.635380 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6255 11:06:22.639053 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6256 11:06:22.642103 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6257 11:06:22.648924 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6258 11:06:22.652125 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6259 11:06:22.652551 ==
6260 11:06:22.655517 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 11:06:22.658604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 11:06:22.658974 ==
6263 11:06:22.665116 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 11:06:22.671747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6265 11:06:22.675078 [CA 0] Center 36 (8~64) winsize 57
6266 11:06:22.678184 [CA 1] Center 36 (8~64) winsize 57
6267 11:06:22.681742 [CA 2] Center 36 (8~64) winsize 57
6268 11:06:22.684756 [CA 3] Center 36 (8~64) winsize 57
6269 11:06:22.688095 [CA 4] Center 36 (8~64) winsize 57
6270 11:06:22.688360 [CA 5] Center 36 (8~64) winsize 57
6271 11:06:22.691231
6272 11:06:22.694854 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6273 11:06:22.695057
6274 11:06:22.697998 [CATrainingPosCal] consider 1 rank data
6275 11:06:22.701182 u2DelayCellTimex100 = 270/100 ps
6276 11:06:22.704407 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:06:22.708402 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 11:06:22.711442 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 11:06:22.714401 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:06:22.717602 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 11:06:22.720766 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 11:06:22.720953
6283 11:06:22.723879 CA PerBit enable=1, Macro0, CA PI delay=36
6284 11:06:22.727323
6285 11:06:22.727470 [CBTSetCACLKResult] CA Dly = 36
6286 11:06:22.730910 CS Dly: 1 (0~32)
6287 11:06:22.731061 ==
6288 11:06:22.734112 Dram Type= 6, Freq= 0, CH_0, rank 1
6289 11:06:22.737412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 11:06:22.737554 ==
6291 11:06:22.743822 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6292 11:06:22.750593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6293 11:06:22.754077 [CA 0] Center 36 (8~64) winsize 57
6294 11:06:22.757132 [CA 1] Center 36 (8~64) winsize 57
6295 11:06:22.760297 [CA 2] Center 36 (8~64) winsize 57
6296 11:06:22.763755 [CA 3] Center 36 (8~64) winsize 57
6297 11:06:22.763876 [CA 4] Center 36 (8~64) winsize 57
6298 11:06:22.766775 [CA 5] Center 36 (8~64) winsize 57
6299 11:06:22.766910
6300 11:06:22.773506 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6301 11:06:22.773704
6302 11:06:22.776922 [CATrainingPosCal] consider 2 rank data
6303 11:06:22.780116 u2DelayCellTimex100 = 270/100 ps
6304 11:06:22.783508 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:06:22.786585 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:06:22.790480 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:06:22.793392 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:06:22.796700 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 11:06:22.800363 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 11:06:22.800498
6311 11:06:22.803075 CA PerBit enable=1, Macro0, CA PI delay=36
6312 11:06:22.803194
6313 11:06:22.806432 [CBTSetCACLKResult] CA Dly = 36
6314 11:06:22.810059 CS Dly: 1 (0~32)
6315 11:06:22.810163
6316 11:06:22.813822 ----->DramcWriteLeveling(PI) begin...
6317 11:06:22.813922 ==
6318 11:06:22.816548 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 11:06:22.819857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 11:06:22.819944 ==
6321 11:06:22.823168 Write leveling (Byte 0): 40 => 8
6322 11:06:22.826558 Write leveling (Byte 1): 40 => 8
6323 11:06:22.829687 DramcWriteLeveling(PI) end<-----
6324 11:06:22.829772
6325 11:06:22.829849 ==
6326 11:06:22.833081 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 11:06:22.836599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 11:06:22.836707 ==
6329 11:06:22.839836 [Gating] SW mode calibration
6330 11:06:22.846128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6331 11:06:22.852611 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6332 11:06:22.855727 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6333 11:06:22.862918 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 11:06:22.866038 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 11:06:22.869349 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 11:06:22.875928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 11:06:22.879243 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 11:06:22.882745 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 11:06:22.889270 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 11:06:22.892320 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 11:06:22.895363 Total UI for P1: 0, mck2ui 16
6342 11:06:22.898681 best dqsien dly found for B0: ( 0, 14, 24)
6343 11:06:22.902416 Total UI for P1: 0, mck2ui 16
6344 11:06:22.905616 best dqsien dly found for B1: ( 0, 14, 24)
6345 11:06:22.908784 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6346 11:06:22.912130 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6347 11:06:22.912225
6348 11:06:22.915138 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6349 11:06:22.918754 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 11:06:22.922059 [Gating] SW calibration Done
6351 11:06:22.922138 ==
6352 11:06:22.925188 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 11:06:22.931832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 11:06:22.931988 ==
6355 11:06:22.932061 RX Vref Scan: 0
6356 11:06:22.932121
6357 11:06:22.935319 RX Vref 0 -> 0, step: 1
6358 11:06:22.935397
6359 11:06:22.938602 RX Delay -410 -> 252, step: 16
6360 11:06:22.941649 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6361 11:06:22.945087 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6362 11:06:22.951146 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6363 11:06:22.954830 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6364 11:06:22.957793 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6365 11:06:22.960950 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6366 11:06:22.968053 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6367 11:06:22.970963 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6368 11:06:22.974174 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6369 11:06:22.977843 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6370 11:06:22.984547 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6371 11:06:22.987506 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6372 11:06:22.990746 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6373 11:06:22.994064 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6374 11:06:23.000518 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6375 11:06:23.004185 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6376 11:06:23.004281 ==
6377 11:06:23.007686 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 11:06:23.010813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 11:06:23.010894 ==
6380 11:06:23.013774 DQS Delay:
6381 11:06:23.013888 DQS0 = 35, DQS1 = 59
6382 11:06:23.017072 DQM Delay:
6383 11:06:23.017173 DQM0 = 4, DQM1 = 17
6384 11:06:23.020302 DQ Delay:
6385 11:06:23.020394 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6386 11:06:23.024191 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6387 11:06:23.026879 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6388 11:06:23.030391 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6389 11:06:23.030538
6390 11:06:23.030628
6391 11:06:23.030707 ==
6392 11:06:23.033939 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 11:06:23.040331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 11:06:23.040504 ==
6395 11:06:23.040608
6396 11:06:23.040697
6397 11:06:23.040781 TX Vref Scan disable
6398 11:06:23.043562 == TX Byte 0 ==
6399 11:06:23.046731 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 11:06:23.050096 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 11:06:23.053593 == TX Byte 1 ==
6402 11:06:23.056828 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 11:06:23.060372 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 11:06:23.063318 ==
6405 11:06:23.066627 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 11:06:23.070265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 11:06:23.070362 ==
6408 11:06:23.070436
6409 11:06:23.070502
6410 11:06:23.073152 TX Vref Scan disable
6411 11:06:23.073247 == TX Byte 0 ==
6412 11:06:23.076687 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 11:06:23.083174 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 11:06:23.083269 == TX Byte 1 ==
6415 11:06:23.086314 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 11:06:23.093380 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 11:06:23.093493
6418 11:06:23.093582 [DATLAT]
6419 11:06:23.093662 Freq=400, CH0 RK0
6420 11:06:23.093740
6421 11:06:23.096487 DATLAT Default: 0xf
6422 11:06:23.099548 0, 0xFFFF, sum = 0
6423 11:06:23.099705 1, 0xFFFF, sum = 0
6424 11:06:23.103089 2, 0xFFFF, sum = 0
6425 11:06:23.103232 3, 0xFFFF, sum = 0
6426 11:06:23.106234 4, 0xFFFF, sum = 0
6427 11:06:23.106379 5, 0xFFFF, sum = 0
6428 11:06:23.109755 6, 0xFFFF, sum = 0
6429 11:06:23.109921 7, 0xFFFF, sum = 0
6430 11:06:23.112998 8, 0xFFFF, sum = 0
6431 11:06:23.113216 9, 0xFFFF, sum = 0
6432 11:06:23.116420 10, 0xFFFF, sum = 0
6433 11:06:23.116654 11, 0xFFFF, sum = 0
6434 11:06:23.120021 12, 0xFFFF, sum = 0
6435 11:06:23.120259 13, 0x0, sum = 1
6436 11:06:23.123029 14, 0x0, sum = 2
6437 11:06:23.123331 15, 0x0, sum = 3
6438 11:06:23.126374 16, 0x0, sum = 4
6439 11:06:23.126741 best_step = 14
6440 11:06:23.127038
6441 11:06:23.127317 ==
6442 11:06:23.129737 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 11:06:23.133008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 11:06:23.136805 ==
6445 11:06:23.137238 RX Vref Scan: 1
6446 11:06:23.137542
6447 11:06:23.139820 RX Vref 0 -> 0, step: 1
6448 11:06:23.140203
6449 11:06:23.143102 RX Delay -359 -> 252, step: 8
6450 11:06:23.143544
6451 11:06:23.146543 Set Vref, RX VrefLevel [Byte0]: 54
6452 11:06:23.149462 [Byte1]: 45
6453 11:06:23.149847
6454 11:06:23.152683 Final RX Vref Byte 0 = 54 to rank0
6455 11:06:23.155884 Final RX Vref Byte 1 = 45 to rank0
6456 11:06:23.159404 Final RX Vref Byte 0 = 54 to rank1
6457 11:06:23.162861 Final RX Vref Byte 1 = 45 to rank1==
6458 11:06:23.166202 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 11:06:23.169504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 11:06:23.172394 ==
6461 11:06:23.172795 DQS Delay:
6462 11:06:23.173094 DQS0 = 44, DQS1 = 56
6463 11:06:23.175835 DQM Delay:
6464 11:06:23.176218 DQM0 = 10, DQM1 = 13
6465 11:06:23.179302 DQ Delay:
6466 11:06:23.182319 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6467 11:06:23.182703 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6468 11:06:23.185466 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6469 11:06:23.188852 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6470 11:06:23.189255
6471 11:06:23.192235
6472 11:06:23.198924 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 390 ps
6473 11:06:23.202942 CH0 RK0: MR19=C0C, MR18=9D90
6474 11:06:23.208839 CH0_RK0: MR19=0xC0C, MR18=0x9D90, DQSOSC=390, MR23=63, INC=388, DEC=258
6475 11:06:23.209261 ==
6476 11:06:23.212332 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 11:06:23.215781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 11:06:23.216183 ==
6479 11:06:23.219015 [Gating] SW mode calibration
6480 11:06:23.225366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6481 11:06:23.231665 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6482 11:06:23.234897 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 11:06:23.238596 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 11:06:23.245074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 11:06:23.248101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 11:06:23.251120 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 11:06:23.258062 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 11:06:23.261243 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 11:06:23.264421 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 11:06:23.271668 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 11:06:23.272194 Total UI for P1: 0, mck2ui 16
6492 11:06:23.277904 best dqsien dly found for B0: ( 0, 14, 24)
6493 11:06:23.278287 Total UI for P1: 0, mck2ui 16
6494 11:06:23.284127 best dqsien dly found for B1: ( 0, 14, 24)
6495 11:06:23.287525 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6496 11:06:23.291003 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6497 11:06:23.291389
6498 11:06:23.294015 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6499 11:06:23.297363 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 11:06:23.301201 [Gating] SW calibration Done
6501 11:06:23.301585 ==
6502 11:06:23.304125 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 11:06:23.307399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 11:06:23.307936 ==
6505 11:06:23.311234 RX Vref Scan: 0
6506 11:06:23.311718
6507 11:06:23.313950 RX Vref 0 -> 0, step: 1
6508 11:06:23.314442
6509 11:06:23.314898 RX Delay -410 -> 252, step: 16
6510 11:06:23.320845 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6511 11:06:23.324034 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6512 11:06:23.327174 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6513 11:06:23.333651 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6514 11:06:23.337173 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6515 11:06:23.340522 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6516 11:06:23.343526 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6517 11:06:23.350504 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6518 11:06:23.353485 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6519 11:06:23.357025 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6520 11:06:23.360150 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6521 11:06:23.366664 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6522 11:06:23.369953 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6523 11:06:23.373170 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6524 11:06:23.376655 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6525 11:06:23.383028 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6526 11:06:23.383565 ==
6527 11:06:23.386353 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 11:06:23.389725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 11:06:23.390232 ==
6530 11:06:23.390696 DQS Delay:
6531 11:06:23.392820 DQS0 = 35, DQS1 = 59
6532 11:06:23.393338 DQM Delay:
6533 11:06:23.396469 DQM0 = 6, DQM1 = 17
6534 11:06:23.396894 DQ Delay:
6535 11:06:23.399693 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6536 11:06:23.402778 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6537 11:06:23.406241 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6538 11:06:23.409662 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6539 11:06:23.410061
6540 11:06:23.410457
6541 11:06:23.410821 ==
6542 11:06:23.413067 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 11:06:23.415881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 11:06:23.416285 ==
6545 11:06:23.416680
6546 11:06:23.419510
6547 11:06:23.419908 TX Vref Scan disable
6548 11:06:23.422806 == TX Byte 0 ==
6549 11:06:23.425909 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6550 11:06:23.429268 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6551 11:06:23.432877 == TX Byte 1 ==
6552 11:06:23.436349 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6553 11:06:23.439126 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6554 11:06:23.439527 ==
6555 11:06:23.442695 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 11:06:23.445718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 11:06:23.449114 ==
6558 11:06:23.449553
6559 11:06:23.449942
6560 11:06:23.450311 TX Vref Scan disable
6561 11:06:23.452334 == TX Byte 0 ==
6562 11:06:23.455993 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6563 11:06:23.458748 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6564 11:06:23.462179 == TX Byte 1 ==
6565 11:06:23.465705 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6566 11:06:23.468930 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6567 11:06:23.469492
6568 11:06:23.469808 [DATLAT]
6569 11:06:23.472226 Freq=400, CH0 RK1
6570 11:06:23.472608
6571 11:06:23.475494 DATLAT Default: 0xe
6572 11:06:23.475877 0, 0xFFFF, sum = 0
6573 11:06:23.478504 1, 0xFFFF, sum = 0
6574 11:06:23.478909 2, 0xFFFF, sum = 0
6575 11:06:23.481871 3, 0xFFFF, sum = 0
6576 11:06:23.482259 4, 0xFFFF, sum = 0
6577 11:06:23.485495 5, 0xFFFF, sum = 0
6578 11:06:23.485917 6, 0xFFFF, sum = 0
6579 11:06:23.488411 7, 0xFFFF, sum = 0
6580 11:06:23.488799 8, 0xFFFF, sum = 0
6581 11:06:23.492016 9, 0xFFFF, sum = 0
6582 11:06:23.492405 10, 0xFFFF, sum = 0
6583 11:06:23.494992 11, 0xFFFF, sum = 0
6584 11:06:23.498410 12, 0xFFFF, sum = 0
6585 11:06:23.498801 13, 0x0, sum = 1
6586 11:06:23.499106 14, 0x0, sum = 2
6587 11:06:23.501832 15, 0x0, sum = 3
6588 11:06:23.502385 16, 0x0, sum = 4
6589 11:06:23.504833 best_step = 14
6590 11:06:23.505340
6591 11:06:23.505797 ==
6592 11:06:23.508213 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 11:06:23.511549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 11:06:23.511934 ==
6595 11:06:23.514910 RX Vref Scan: 0
6596 11:06:23.515294
6597 11:06:23.515592 RX Vref 0 -> 0, step: 1
6598 11:06:23.518344
6599 11:06:23.518725 RX Delay -359 -> 252, step: 8
6600 11:06:23.526993 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6601 11:06:23.529998 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6602 11:06:23.533091 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6603 11:06:23.539823 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6604 11:06:23.542971 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6605 11:06:23.546196 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6606 11:06:23.549754 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6607 11:06:23.556446 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6608 11:06:23.559871 iDelay=209, Bit 8, Center -56 (-295 ~ 184) 480
6609 11:06:23.563242 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6610 11:06:23.566394 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6611 11:06:23.572718 iDelay=209, Bit 11, Center -52 (-287 ~ 184) 472
6612 11:06:23.575873 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6613 11:06:23.579742 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6614 11:06:23.582592 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6615 11:06:23.589358 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6616 11:06:23.589756 ==
6617 11:06:23.592419 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 11:06:23.595694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 11:06:23.596080 ==
6620 11:06:23.596376 DQS Delay:
6621 11:06:23.599206 DQS0 = 44, DQS1 = 60
6622 11:06:23.599591 DQM Delay:
6623 11:06:23.602536 DQM0 = 9, DQM1 = 14
6624 11:06:23.602918 DQ Delay:
6625 11:06:23.605644 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6626 11:06:23.609445 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6627 11:06:23.612723 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6628 11:06:23.615575 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6629 11:06:23.615958
6630 11:06:23.616253
6631 11:06:23.622470 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e86, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6632 11:06:23.625800 CH0 RK1: MR19=C0C, MR18=8E86
6633 11:06:23.632017 CH0_RK1: MR19=0xC0C, MR18=0x8E86, DQSOSC=392, MR23=63, INC=384, DEC=256
6634 11:06:23.635569 [RxdqsGatingPostProcess] freq 400
6635 11:06:23.642386 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6636 11:06:23.645339 best DQS0 dly(2T, 0.5T) = (0, 10)
6637 11:06:23.648693 best DQS1 dly(2T, 0.5T) = (0, 10)
6638 11:06:23.652092 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6639 11:06:23.655680 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6640 11:06:23.656202 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 11:06:23.658960 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 11:06:23.661837 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 11:06:23.665233 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 11:06:23.668930 Pre-setting of DQS Precalculation
6645 11:06:23.674998 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6646 11:06:23.675384 ==
6647 11:06:23.678235 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 11:06:23.681756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 11:06:23.682144 ==
6650 11:06:23.688042 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 11:06:23.694725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6652 11:06:23.698364 [CA 0] Center 36 (8~64) winsize 57
6653 11:06:23.698748 [CA 1] Center 36 (8~64) winsize 57
6654 11:06:23.701750 [CA 2] Center 36 (8~64) winsize 57
6655 11:06:23.704902 [CA 3] Center 36 (8~64) winsize 57
6656 11:06:23.708097 [CA 4] Center 36 (8~64) winsize 57
6657 11:06:23.711664 [CA 5] Center 36 (8~64) winsize 57
6658 11:06:23.712042
6659 11:06:23.714971 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6660 11:06:23.715350
6661 11:06:23.721515 [CATrainingPosCal] consider 1 rank data
6662 11:06:23.721898 u2DelayCellTimex100 = 270/100 ps
6663 11:06:23.728055 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:06:23.731467 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 11:06:23.734467 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 11:06:23.737920 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:06:23.741201 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 11:06:23.744368 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 11:06:23.744745
6670 11:06:23.747978 CA PerBit enable=1, Macro0, CA PI delay=36
6671 11:06:23.748374
6672 11:06:23.750978 [CBTSetCACLKResult] CA Dly = 36
6673 11:06:23.754139 CS Dly: 1 (0~32)
6674 11:06:23.754530 ==
6675 11:06:23.757655 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 11:06:23.760865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 11:06:23.761300 ==
6678 11:06:23.767512 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6679 11:06:23.770771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6680 11:06:23.774598 [CA 0] Center 36 (8~64) winsize 57
6681 11:06:23.777499 [CA 1] Center 36 (8~64) winsize 57
6682 11:06:23.780667 [CA 2] Center 36 (8~64) winsize 57
6683 11:06:23.783961 [CA 3] Center 36 (8~64) winsize 57
6684 11:06:23.787576 [CA 4] Center 36 (8~64) winsize 57
6685 11:06:23.791209 [CA 5] Center 36 (8~64) winsize 57
6686 11:06:23.791599
6687 11:06:23.793940 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6688 11:06:23.794330
6689 11:06:23.797304 [CATrainingPosCal] consider 2 rank data
6690 11:06:23.800692 u2DelayCellTimex100 = 270/100 ps
6691 11:06:23.803535 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:06:23.807392 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:06:23.813705 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:06:23.816775 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:06:23.819977 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 11:06:23.823673 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 11:06:23.824058
6698 11:06:23.826942 CA PerBit enable=1, Macro0, CA PI delay=36
6699 11:06:23.827329
6700 11:06:23.830506 [CBTSetCACLKResult] CA Dly = 36
6701 11:06:23.830895 CS Dly: 1 (0~32)
6702 11:06:23.833319
6703 11:06:23.836689 ----->DramcWriteLeveling(PI) begin...
6704 11:06:23.837084 ==
6705 11:06:23.839899 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 11:06:23.843203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 11:06:23.843594 ==
6708 11:06:23.847082 Write leveling (Byte 0): 40 => 8
6709 11:06:23.849875 Write leveling (Byte 1): 40 => 8
6710 11:06:23.853648 DramcWriteLeveling(PI) end<-----
6711 11:06:23.854036
6712 11:06:23.854335 ==
6713 11:06:23.856509 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 11:06:23.859789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 11:06:23.860277 ==
6716 11:06:23.862846 [Gating] SW mode calibration
6717 11:06:23.869556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6718 11:06:23.876132 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6719 11:06:23.879689 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6720 11:06:23.882813 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 11:06:23.889676 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 11:06:23.892972 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 11:06:23.896055 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 11:06:23.902893 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 11:06:23.905930 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 11:06:23.909548 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 11:06:23.916068 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 11:06:23.916459 Total UI for P1: 0, mck2ui 16
6729 11:06:23.922466 best dqsien dly found for B0: ( 0, 14, 24)
6730 11:06:23.922858 Total UI for P1: 0, mck2ui 16
6731 11:06:23.929106 best dqsien dly found for B1: ( 0, 14, 24)
6732 11:06:23.932432 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6733 11:06:23.935607 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6734 11:06:23.935996
6735 11:06:23.939119 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6736 11:06:23.941939 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 11:06:23.945652 [Gating] SW calibration Done
6738 11:06:23.946036 ==
6739 11:06:23.948592 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 11:06:23.952424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 11:06:23.952816 ==
6742 11:06:23.955146 RX Vref Scan: 0
6743 11:06:23.955533
6744 11:06:23.955837 RX Vref 0 -> 0, step: 1
6745 11:06:23.958677
6746 11:06:23.959066 RX Delay -410 -> 252, step: 16
6747 11:06:23.965272 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6748 11:06:23.968356 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6749 11:06:23.971458 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6750 11:06:23.978482 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6751 11:06:23.981601 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6752 11:06:23.985196 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6753 11:06:23.988612 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6754 11:06:23.995209 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6755 11:06:23.997980 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6756 11:06:24.001431 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6757 11:06:24.004547 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6758 11:06:24.011455 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6759 11:06:24.014380 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6760 11:06:24.017624 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6761 11:06:24.020912 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6762 11:06:24.027558 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6763 11:06:24.027946 ==
6764 11:06:24.031428 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 11:06:24.034527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 11:06:24.034917 ==
6767 11:06:24.037518 DQS Delay:
6768 11:06:24.037903 DQS0 = 43, DQS1 = 51
6769 11:06:24.038204 DQM Delay:
6770 11:06:24.040841 DQM0 = 13, DQM1 = 13
6771 11:06:24.041256 DQ Delay:
6772 11:06:24.044056 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6773 11:06:24.047634 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6774 11:06:24.050673 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6775 11:06:24.054017 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6776 11:06:24.054406
6777 11:06:24.054704
6778 11:06:24.054981 ==
6779 11:06:24.057203 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 11:06:24.060650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 11:06:24.061051 ==
6782 11:06:24.064121
6783 11:06:24.064516
6784 11:06:24.064913 TX Vref Scan disable
6785 11:06:24.067627 == TX Byte 0 ==
6786 11:06:24.070496 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 11:06:24.073973 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 11:06:24.077355 == TX Byte 1 ==
6789 11:06:24.080177 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 11:06:24.083971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 11:06:24.084373 ==
6792 11:06:24.087547 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 11:06:24.093706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 11:06:24.094096 ==
6795 11:06:24.094397
6796 11:06:24.094673
6797 11:06:24.094937 TX Vref Scan disable
6798 11:06:24.096936 == TX Byte 0 ==
6799 11:06:24.100257 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 11:06:24.103520 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 11:06:24.106538 == TX Byte 1 ==
6802 11:06:24.110175 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 11:06:24.113409 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 11:06:24.113820
6805 11:06:24.116619 [DATLAT]
6806 11:06:24.117010 Freq=400, CH1 RK0
6807 11:06:24.117351
6808 11:06:24.119770 DATLAT Default: 0xf
6809 11:06:24.120158 0, 0xFFFF, sum = 0
6810 11:06:24.123172 1, 0xFFFF, sum = 0
6811 11:06:24.123571 2, 0xFFFF, sum = 0
6812 11:06:24.126410 3, 0xFFFF, sum = 0
6813 11:06:24.126807 4, 0xFFFF, sum = 0
6814 11:06:24.129936 5, 0xFFFF, sum = 0
6815 11:06:24.130336 6, 0xFFFF, sum = 0
6816 11:06:24.132909 7, 0xFFFF, sum = 0
6817 11:06:24.133354 8, 0xFFFF, sum = 0
6818 11:06:24.136480 9, 0xFFFF, sum = 0
6819 11:06:24.136878 10, 0xFFFF, sum = 0
6820 11:06:24.139840 11, 0xFFFF, sum = 0
6821 11:06:24.143299 12, 0xFFFF, sum = 0
6822 11:06:24.143778 13, 0x0, sum = 1
6823 11:06:24.146075 14, 0x0, sum = 2
6824 11:06:24.146472 15, 0x0, sum = 3
6825 11:06:24.146782 16, 0x0, sum = 4
6826 11:06:24.149681 best_step = 14
6827 11:06:24.150067
6828 11:06:24.150367 ==
6829 11:06:24.153106 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 11:06:24.156304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 11:06:24.156692 ==
6832 11:06:24.159487 RX Vref Scan: 1
6833 11:06:24.159872
6834 11:06:24.162971 RX Vref 0 -> 0, step: 1
6835 11:06:24.163359
6836 11:06:24.163661 RX Delay -343 -> 252, step: 8
6837 11:06:24.163939
6838 11:06:24.166300 Set Vref, RX VrefLevel [Byte0]: 51
6839 11:06:24.169442 [Byte1]: 52
6840 11:06:24.174812
6841 11:06:24.175198 Final RX Vref Byte 0 = 51 to rank0
6842 11:06:24.178255 Final RX Vref Byte 1 = 52 to rank0
6843 11:06:24.181550 Final RX Vref Byte 0 = 51 to rank1
6844 11:06:24.184718 Final RX Vref Byte 1 = 52 to rank1==
6845 11:06:24.188284 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 11:06:24.194979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 11:06:24.195371 ==
6848 11:06:24.195673 DQS Delay:
6849 11:06:24.198555 DQS0 = 44, DQS1 = 52
6850 11:06:24.198942 DQM Delay:
6851 11:06:24.199240 DQM0 = 11, DQM1 = 11
6852 11:06:24.201090 DQ Delay:
6853 11:06:24.204240 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6854 11:06:24.207617 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6855 11:06:24.208006 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6856 11:06:24.210866 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6857 11:06:24.214610
6858 11:06:24.214993
6859 11:06:24.220995 [DQSOSCAuto] RK0, (LSB)MR18= 0x7097, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6860 11:06:24.224230 CH1 RK0: MR19=C0C, MR18=7097
6861 11:06:24.231052 CH1_RK0: MR19=0xC0C, MR18=0x7097, DQSOSC=390, MR23=63, INC=388, DEC=258
6862 11:06:24.231442 ==
6863 11:06:24.233842 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 11:06:24.237414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 11:06:24.237801 ==
6866 11:06:24.240700 [Gating] SW mode calibration
6867 11:06:24.247316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6868 11:06:24.254066 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6869 11:06:24.257577 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6870 11:06:24.260200 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 11:06:24.267179 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 11:06:24.270691 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 11:06:24.274453 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 11:06:24.280080 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 11:06:24.283840 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 11:06:24.286679 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 11:06:24.293255 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 11:06:24.293661 Total UI for P1: 0, mck2ui 16
6879 11:06:24.300268 best dqsien dly found for B0: ( 0, 14, 24)
6880 11:06:24.300813 Total UI for P1: 0, mck2ui 16
6881 11:06:24.306986 best dqsien dly found for B1: ( 0, 14, 24)
6882 11:06:24.310409 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6883 11:06:24.313361 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6884 11:06:24.313763
6885 11:06:24.316620 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6886 11:06:24.320004 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 11:06:24.323003 [Gating] SW calibration Done
6888 11:06:24.323401 ==
6889 11:06:24.326340 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 11:06:24.330207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 11:06:24.330608 ==
6892 11:06:24.333510 RX Vref Scan: 0
6893 11:06:24.333907
6894 11:06:24.334300 RX Vref 0 -> 0, step: 1
6895 11:06:24.336767
6896 11:06:24.337182 RX Delay -410 -> 252, step: 16
6897 11:06:24.342949 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6898 11:06:24.346327 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6899 11:06:24.349769 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6900 11:06:24.353001 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6901 11:06:24.359553 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6902 11:06:24.363310 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6903 11:06:24.366092 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6904 11:06:24.369644 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6905 11:06:24.376070 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6906 11:06:24.379925 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6907 11:06:24.382647 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6908 11:06:24.389655 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6909 11:06:24.392497 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6910 11:06:24.395873 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6911 11:06:24.398984 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6912 11:06:24.405501 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6913 11:06:24.405892 ==
6914 11:06:24.408831 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 11:06:24.412202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 11:06:24.412588 ==
6917 11:06:24.412896 DQS Delay:
6918 11:06:24.415541 DQS0 = 43, DQS1 = 51
6919 11:06:24.415928 DQM Delay:
6920 11:06:24.418506 DQM0 = 9, DQM1 = 14
6921 11:06:24.418897 DQ Delay:
6922 11:06:24.422091 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6923 11:06:24.425117 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6924 11:06:24.428743 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6925 11:06:24.432272 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6926 11:06:24.432662
6927 11:06:24.433007
6928 11:06:24.433339 ==
6929 11:06:24.435167 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 11:06:24.438676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 11:06:24.439071 ==
6932 11:06:24.439375
6933 11:06:24.441636
6934 11:06:24.442025 TX Vref Scan disable
6935 11:06:24.445598 == TX Byte 0 ==
6936 11:06:24.448628 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6937 11:06:24.451539 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6938 11:06:24.454908 == TX Byte 1 ==
6939 11:06:24.458764 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6940 11:06:24.461628 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6941 11:06:24.462015 ==
6942 11:06:24.465183 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 11:06:24.468748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 11:06:24.469164 ==
6945 11:06:24.471553
6946 11:06:24.471949
6947 11:06:24.472256 TX Vref Scan disable
6948 11:06:24.475065 == TX Byte 0 ==
6949 11:06:24.478361 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6950 11:06:24.481438 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6951 11:06:24.484886 == TX Byte 1 ==
6952 11:06:24.488436 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6953 11:06:24.491287 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6954 11:06:24.491674
6955 11:06:24.491973 [DATLAT]
6956 11:06:24.494843 Freq=400, CH1 RK1
6957 11:06:24.495231
6958 11:06:24.498087 DATLAT Default: 0xe
6959 11:06:24.498472 0, 0xFFFF, sum = 0
6960 11:06:24.501708 1, 0xFFFF, sum = 0
6961 11:06:24.502224 2, 0xFFFF, sum = 0
6962 11:06:24.504607 3, 0xFFFF, sum = 0
6963 11:06:24.504999 4, 0xFFFF, sum = 0
6964 11:06:24.508153 5, 0xFFFF, sum = 0
6965 11:06:24.508540 6, 0xFFFF, sum = 0
6966 11:06:24.511385 7, 0xFFFF, sum = 0
6967 11:06:24.511784 8, 0xFFFF, sum = 0
6968 11:06:24.514898 9, 0xFFFF, sum = 0
6969 11:06:24.515289 10, 0xFFFF, sum = 0
6970 11:06:24.517861 11, 0xFFFF, sum = 0
6971 11:06:24.518260 12, 0xFFFF, sum = 0
6972 11:06:24.520967 13, 0x0, sum = 1
6973 11:06:24.521390 14, 0x0, sum = 2
6974 11:06:24.524213 15, 0x0, sum = 3
6975 11:06:24.524610 16, 0x0, sum = 4
6976 11:06:24.527614 best_step = 14
6977 11:06:24.528000
6978 11:06:24.528343 ==
6979 11:06:24.531029 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 11:06:24.534244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 11:06:24.534783 ==
6982 11:06:24.537673 RX Vref Scan: 0
6983 11:06:24.538061
6984 11:06:24.538359 RX Vref 0 -> 0, step: 1
6985 11:06:24.538639
6986 11:06:24.541478 RX Delay -343 -> 252, step: 8
6987 11:06:24.549502 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6988 11:06:24.552953 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6989 11:06:24.555325 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6990 11:06:24.561920 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6991 11:06:24.565360 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6992 11:06:24.568699 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6993 11:06:24.572009 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6994 11:06:24.578405 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6995 11:06:24.582281 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6996 11:06:24.585134 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6997 11:06:24.588380 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6998 11:06:24.595248 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6999 11:06:24.598086 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
7000 11:06:24.601615 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
7001 11:06:24.605127 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
7002 11:06:24.611277 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7003 11:06:24.611668 ==
7004 11:06:24.614562 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 11:06:24.617805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 11:06:24.618342 ==
7007 11:06:24.621647 DQS Delay:
7008 11:06:24.622033 DQS0 = 48, DQS1 = 52
7009 11:06:24.622333 DQM Delay:
7010 11:06:24.624547 DQM0 = 12, DQM1 = 10
7011 11:06:24.624935 DQ Delay:
7012 11:06:24.628231 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7013 11:06:24.631140 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
7014 11:06:24.634713 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7015 11:06:24.637683 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7016 11:06:24.638074
7017 11:06:24.638370
7018 11:06:24.647998 [DQSOSCAuto] RK1, (LSB)MR18= 0x82b9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 393 ps
7019 11:06:24.648557 CH1 RK1: MR19=C0C, MR18=82B9
7020 11:06:24.654293 CH1_RK1: MR19=0xC0C, MR18=0x82B9, DQSOSC=386, MR23=63, INC=396, DEC=264
7021 11:06:24.657241 [RxdqsGatingPostProcess] freq 400
7022 11:06:24.664302 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7023 11:06:24.667590 best DQS0 dly(2T, 0.5T) = (0, 10)
7024 11:06:24.670572 best DQS1 dly(2T, 0.5T) = (0, 10)
7025 11:06:24.674097 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7026 11:06:24.677236 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7027 11:06:24.681249 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 11:06:24.683853 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 11:06:24.687127 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 11:06:24.690268 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 11:06:24.690659 Pre-setting of DQS Precalculation
7032 11:06:24.696915 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7033 11:06:24.703539 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7034 11:06:24.710500 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7035 11:06:24.710890
7036 11:06:24.711187
7037 11:06:24.713405 [Calibration Summary] 800 Mbps
7038 11:06:24.716827 CH 0, Rank 0
7039 11:06:24.717270 SW Impedance : PASS
7040 11:06:24.719899 DUTY Scan : NO K
7041 11:06:24.723244 ZQ Calibration : PASS
7042 11:06:24.723631 Jitter Meter : NO K
7043 11:06:24.727061 CBT Training : PASS
7044 11:06:24.729885 Write leveling : PASS
7045 11:06:24.730273 RX DQS gating : PASS
7046 11:06:24.733259 RX DQ/DQS(RDDQC) : PASS
7047 11:06:24.736461 TX DQ/DQS : PASS
7048 11:06:24.736849 RX DATLAT : PASS
7049 11:06:24.739970 RX DQ/DQS(Engine): PASS
7050 11:06:24.743151 TX OE : NO K
7051 11:06:24.743543 All Pass.
7052 11:06:24.743844
7053 11:06:24.744120 CH 0, Rank 1
7054 11:06:24.746562 SW Impedance : PASS
7055 11:06:24.749841 DUTY Scan : NO K
7056 11:06:24.750227 ZQ Calibration : PASS
7057 11:06:24.752879 Jitter Meter : NO K
7058 11:06:24.753297 CBT Training : PASS
7059 11:06:24.756114 Write leveling : NO K
7060 11:06:24.760031 RX DQS gating : PASS
7061 11:06:24.760417 RX DQ/DQS(RDDQC) : PASS
7062 11:06:24.763028 TX DQ/DQS : PASS
7063 11:06:24.766642 RX DATLAT : PASS
7064 11:06:24.767190 RX DQ/DQS(Engine): PASS
7065 11:06:24.769378 TX OE : NO K
7066 11:06:24.769768 All Pass.
7067 11:06:24.770068
7068 11:06:24.772533 CH 1, Rank 0
7069 11:06:24.773106 SW Impedance : PASS
7070 11:06:24.776100 DUTY Scan : NO K
7071 11:06:24.779441 ZQ Calibration : PASS
7072 11:06:24.779971 Jitter Meter : NO K
7073 11:06:24.782625 CBT Training : PASS
7074 11:06:24.785942 Write leveling : PASS
7075 11:06:24.786469 RX DQS gating : PASS
7076 11:06:24.789382 RX DQ/DQS(RDDQC) : PASS
7077 11:06:24.792324 TX DQ/DQS : PASS
7078 11:06:24.792713 RX DATLAT : PASS
7079 11:06:24.796079 RX DQ/DQS(Engine): PASS
7080 11:06:24.799183 TX OE : NO K
7081 11:06:24.799638 All Pass.
7082 11:06:24.799948
7083 11:06:24.800225 CH 1, Rank 1
7084 11:06:24.802379 SW Impedance : PASS
7085 11:06:24.805879 DUTY Scan : NO K
7086 11:06:24.806268 ZQ Calibration : PASS
7087 11:06:24.809656 Jitter Meter : NO K
7088 11:06:24.812622 CBT Training : PASS
7089 11:06:24.813009 Write leveling : NO K
7090 11:06:24.816079 RX DQS gating : PASS
7091 11:06:24.819584 RX DQ/DQS(RDDQC) : PASS
7092 11:06:24.819973 TX DQ/DQS : PASS
7093 11:06:24.822535 RX DATLAT : PASS
7094 11:06:24.822923 RX DQ/DQS(Engine): PASS
7095 11:06:24.825625 TX OE : NO K
7096 11:06:24.826097 All Pass.
7097 11:06:24.826401
7098 11:06:24.829019 DramC Write-DBI off
7099 11:06:24.832490 PER_BANK_REFRESH: Hybrid Mode
7100 11:06:24.832877 TX_TRACKING: ON
7101 11:06:24.842360 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7102 11:06:24.845380 [FAST_K] Save calibration result to emmc
7103 11:06:24.848507 dramc_set_vcore_voltage set vcore to 725000
7104 11:06:24.852042 Read voltage for 1600, 0
7105 11:06:24.852498 Vio18 = 0
7106 11:06:24.855028 Vcore = 725000
7107 11:06:24.855405 Vdram = 0
7108 11:06:24.855697 Vddq = 0
7109 11:06:24.856064 Vmddr = 0
7110 11:06:24.862175 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7111 11:06:24.868964 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7112 11:06:24.869378 MEM_TYPE=3, freq_sel=13
7113 11:06:24.871553 sv_algorithm_assistance_LP4_3733
7114 11:06:24.878068 ============ PULL DRAM RESETB DOWN ============
7115 11:06:24.881676 ========== PULL DRAM RESETB DOWN end =========
7116 11:06:24.884877 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7117 11:06:24.888433 ===================================
7118 11:06:24.891139 LPDDR4 DRAM CONFIGURATION
7119 11:06:24.894644 ===================================
7120 11:06:24.895029 EX_ROW_EN[0] = 0x0
7121 11:06:24.898216 EX_ROW_EN[1] = 0x0
7122 11:06:24.901202 LP4Y_EN = 0x0
7123 11:06:24.901592 WORK_FSP = 0x1
7124 11:06:24.904407 WL = 0x5
7125 11:06:24.904808 RL = 0x5
7126 11:06:24.908181 BL = 0x2
7127 11:06:24.908572 RPST = 0x0
7128 11:06:24.911109 RD_PRE = 0x0
7129 11:06:24.911508 WR_PRE = 0x1
7130 11:06:24.914807 WR_PST = 0x1
7131 11:06:24.915294 DBI_WR = 0x0
7132 11:06:24.917768 DBI_RD = 0x0
7133 11:06:24.918153 OTF = 0x1
7134 11:06:24.921067 ===================================
7135 11:06:24.924534 ===================================
7136 11:06:24.927741 ANA top config
7137 11:06:24.931205 ===================================
7138 11:06:24.934185 DLL_ASYNC_EN = 0
7139 11:06:24.934648 ALL_SLAVE_EN = 0
7140 11:06:24.937483 NEW_RANK_MODE = 1
7141 11:06:24.941166 DLL_IDLE_MODE = 1
7142 11:06:24.944002 LP45_APHY_COMB_EN = 1
7143 11:06:24.944390 TX_ODT_DIS = 0
7144 11:06:24.947898 NEW_8X_MODE = 1
7145 11:06:24.951206 ===================================
7146 11:06:24.954135 ===================================
7147 11:06:24.957256 data_rate = 3200
7148 11:06:24.960739 CKR = 1
7149 11:06:24.963945 DQ_P2S_RATIO = 8
7150 11:06:24.967482 ===================================
7151 11:06:24.970420 CA_P2S_RATIO = 8
7152 11:06:24.970964 DQ_CA_OPEN = 0
7153 11:06:24.973897 DQ_SEMI_OPEN = 0
7154 11:06:24.977535 CA_SEMI_OPEN = 0
7155 11:06:24.980664 CA_FULL_RATE = 0
7156 11:06:24.984214 DQ_CKDIV4_EN = 0
7157 11:06:24.987016 CA_CKDIV4_EN = 0
7158 11:06:24.987405 CA_PREDIV_EN = 0
7159 11:06:24.990277 PH8_DLY = 12
7160 11:06:24.993709 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7161 11:06:24.997017 DQ_AAMCK_DIV = 4
7162 11:06:25.000283 CA_AAMCK_DIV = 4
7163 11:06:25.003284 CA_ADMCK_DIV = 4
7164 11:06:25.006658 DQ_TRACK_CA_EN = 0
7165 11:06:25.007046 CA_PICK = 1600
7166 11:06:25.010183 CA_MCKIO = 1600
7167 11:06:25.013653 MCKIO_SEMI = 0
7168 11:06:25.016562 PLL_FREQ = 3068
7169 11:06:25.020238 DQ_UI_PI_RATIO = 32
7170 11:06:25.023216 CA_UI_PI_RATIO = 0
7171 11:06:25.026928 ===================================
7172 11:06:25.030396 ===================================
7173 11:06:25.033091 memory_type:LPDDR4
7174 11:06:25.033612 GP_NUM : 10
7175 11:06:25.037007 SRAM_EN : 1
7176 11:06:25.037518 MD32_EN : 0
7177 11:06:25.039889 ===================================
7178 11:06:25.043486 [ANA_INIT] >>>>>>>>>>>>>>
7179 11:06:25.046645 <<<<<< [CONFIGURE PHASE]: ANA_TX
7180 11:06:25.049860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7181 11:06:25.052809 ===================================
7182 11:06:25.056425 data_rate = 3200,PCW = 0X7600
7183 11:06:25.059808 ===================================
7184 11:06:25.063419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7185 11:06:25.069492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7186 11:06:25.072715 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 11:06:25.079615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7188 11:06:25.082996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7189 11:06:25.085911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7190 11:06:25.086330 [ANA_INIT] flow start
7191 11:06:25.089753 [ANA_INIT] PLL >>>>>>>>
7192 11:06:25.092835 [ANA_INIT] PLL <<<<<<<<
7193 11:06:25.093353 [ANA_INIT] MIDPI >>>>>>>>
7194 11:06:25.096045 [ANA_INIT] MIDPI <<<<<<<<
7195 11:06:25.099100 [ANA_INIT] DLL >>>>>>>>
7196 11:06:25.099506 [ANA_INIT] DLL <<<<<<<<
7197 11:06:25.102421 [ANA_INIT] flow end
7198 11:06:25.105764 ============ LP4 DIFF to SE enter ============
7199 11:06:25.112628 ============ LP4 DIFF to SE exit ============
7200 11:06:25.113132 [ANA_INIT] <<<<<<<<<<<<<
7201 11:06:25.115679 [Flow] Enable top DCM control >>>>>
7202 11:06:25.118737 [Flow] Enable top DCM control <<<<<
7203 11:06:25.122289 Enable DLL master slave shuffle
7204 11:06:25.128873 ==============================================================
7205 11:06:25.129373 Gating Mode config
7206 11:06:25.135378 ==============================================================
7207 11:06:25.138800 Config description:
7208 11:06:25.148327 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7209 11:06:25.155119 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7210 11:06:25.158872 SELPH_MODE 0: By rank 1: By Phase
7211 11:06:25.165260 ==============================================================
7212 11:06:25.168319 GAT_TRACK_EN = 1
7213 11:06:25.171603 RX_GATING_MODE = 2
7214 11:06:25.171986 RX_GATING_TRACK_MODE = 2
7215 11:06:25.175207 SELPH_MODE = 1
7216 11:06:25.178365 PICG_EARLY_EN = 1
7217 11:06:25.181651 VALID_LAT_VALUE = 1
7218 11:06:25.188679 ==============================================================
7219 11:06:25.191688 Enter into Gating configuration >>>>
7220 11:06:25.195544 Exit from Gating configuration <<<<
7221 11:06:25.198116 Enter into DVFS_PRE_config >>>>>
7222 11:06:25.208599 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7223 11:06:25.211376 Exit from DVFS_PRE_config <<<<<
7224 11:06:25.214883 Enter into PICG configuration >>>>
7225 11:06:25.218283 Exit from PICG configuration <<<<
7226 11:06:25.221487 [RX_INPUT] configuration >>>>>
7227 11:06:25.224570 [RX_INPUT] configuration <<<<<
7228 11:06:25.228556 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7229 11:06:25.234812 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7230 11:06:25.241647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 11:06:25.247918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 11:06:25.250871 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 11:06:25.257743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 11:06:25.260895 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7235 11:06:25.267898 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7236 11:06:25.270844 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7237 11:06:25.274392 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7238 11:06:25.277808 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7239 11:06:25.284028 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 11:06:25.287778 ===================================
7241 11:06:25.291527 LPDDR4 DRAM CONFIGURATION
7242 11:06:25.294326 ===================================
7243 11:06:25.294791 EX_ROW_EN[0] = 0x0
7244 11:06:25.297488 EX_ROW_EN[1] = 0x0
7245 11:06:25.297871 LP4Y_EN = 0x0
7246 11:06:25.301000 WORK_FSP = 0x1
7247 11:06:25.301425 WL = 0x5
7248 11:06:25.304098 RL = 0x5
7249 11:06:25.304480 BL = 0x2
7250 11:06:25.307357 RPST = 0x0
7251 11:06:25.307739 RD_PRE = 0x0
7252 11:06:25.310350 WR_PRE = 0x1
7253 11:06:25.310782 WR_PST = 0x1
7254 11:06:25.314291 DBI_WR = 0x0
7255 11:06:25.317592 DBI_RD = 0x0
7256 11:06:25.317974 OTF = 0x1
7257 11:06:25.320390 ===================================
7258 11:06:25.323985 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7259 11:06:25.327224 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7260 11:06:25.333928 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 11:06:25.337375 ===================================
7262 11:06:25.340400 LPDDR4 DRAM CONFIGURATION
7263 11:06:25.344137 ===================================
7264 11:06:25.344593 EX_ROW_EN[0] = 0x10
7265 11:06:25.346910 EX_ROW_EN[1] = 0x0
7266 11:06:25.347365 LP4Y_EN = 0x0
7267 11:06:25.350133 WORK_FSP = 0x1
7268 11:06:25.350518 WL = 0x5
7269 11:06:25.353753 RL = 0x5
7270 11:06:25.354137 BL = 0x2
7271 11:06:25.356573 RPST = 0x0
7272 11:06:25.356953 RD_PRE = 0x0
7273 11:06:25.359784 WR_PRE = 0x1
7274 11:06:25.363224 WR_PST = 0x1
7275 11:06:25.363606 DBI_WR = 0x0
7276 11:06:25.366337 DBI_RD = 0x0
7277 11:06:25.366720 OTF = 0x1
7278 11:06:25.369705 ===================================
7279 11:06:25.376667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7280 11:06:25.377065 ==
7281 11:06:25.380427 Dram Type= 6, Freq= 0, CH_0, rank 0
7282 11:06:25.383099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 11:06:25.383568 ==
7284 11:06:25.386195 [Duty_Offset_Calibration]
7285 11:06:25.389479 B0:2 B1:0 CA:4
7286 11:06:25.389866
7287 11:06:25.392567 [DutyScan_Calibration_Flow] k_type=0
7288 11:06:25.400682
7289 11:06:25.401230 ==CLK 0==
7290 11:06:25.403543 Final CLK duty delay cell = -4
7291 11:06:25.406997 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7292 11:06:25.410268 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7293 11:06:25.413372 [-4] AVG Duty = 4937%(X100)
7294 11:06:25.413759
7295 11:06:25.417101 CH0 CLK Duty spec in!! Max-Min= 187%
7296 11:06:25.420184 [DutyScan_Calibration_Flow] ====Done====
7297 11:06:25.420571
7298 11:06:25.423426 [DutyScan_Calibration_Flow] k_type=1
7299 11:06:25.440885
7300 11:06:25.441408 ==DQS 0 ==
7301 11:06:25.443698 Final DQS duty delay cell = 0
7302 11:06:25.447718 [0] MAX Duty = 5218%(X100), DQS PI = 22
7303 11:06:25.450745 [0] MIN Duty = 5093%(X100), DQS PI = 6
7304 11:06:25.454070 [0] AVG Duty = 5155%(X100)
7305 11:06:25.454458
7306 11:06:25.454759 ==DQS 1 ==
7307 11:06:25.456877 Final DQS duty delay cell = 0
7308 11:06:25.460418 [0] MAX Duty = 5156%(X100), DQS PI = 2
7309 11:06:25.464000 [0] MIN Duty = 4969%(X100), DQS PI = 10
7310 11:06:25.467023 [0] AVG Duty = 5062%(X100)
7311 11:06:25.467412
7312 11:06:25.470510 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7313 11:06:25.470898
7314 11:06:25.473702 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7315 11:06:25.476955 [DutyScan_Calibration_Flow] ====Done====
7316 11:06:25.477365
7317 11:06:25.480602 [DutyScan_Calibration_Flow] k_type=3
7318 11:06:25.497946
7319 11:06:25.498438 ==DQM 0 ==
7320 11:06:25.501553 Final DQM duty delay cell = 0
7321 11:06:25.504255 [0] MAX Duty = 5124%(X100), DQS PI = 22
7322 11:06:25.507692 [0] MIN Duty = 4844%(X100), DQS PI = 56
7323 11:06:25.511457 [0] AVG Duty = 4984%(X100)
7324 11:06:25.511868
7325 11:06:25.512202 ==DQM 1 ==
7326 11:06:25.514710 Final DQM duty delay cell = 0
7327 11:06:25.517983 [0] MAX Duty = 5000%(X100), DQS PI = 2
7328 11:06:25.521050 [0] MIN Duty = 4844%(X100), DQS PI = 14
7329 11:06:25.524264 [0] AVG Duty = 4922%(X100)
7330 11:06:25.524757
7331 11:06:25.527279 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7332 11:06:25.527863
7333 11:06:25.530962 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7334 11:06:25.534202 [DutyScan_Calibration_Flow] ====Done====
7335 11:06:25.534631
7336 11:06:25.537541 [DutyScan_Calibration_Flow] k_type=2
7337 11:06:25.555349
7338 11:06:25.555844 ==DQ 0 ==
7339 11:06:25.559223 Final DQ duty delay cell = 0
7340 11:06:25.561709 [0] MAX Duty = 5124%(X100), DQS PI = 20
7341 11:06:25.564748 [0] MIN Duty = 4938%(X100), DQS PI = 12
7342 11:06:25.565277 [0] AVG Duty = 5031%(X100)
7343 11:06:25.568127
7344 11:06:25.568619 ==DQ 1 ==
7345 11:06:25.571517 Final DQ duty delay cell = 0
7346 11:06:25.574443 [0] MAX Duty = 5187%(X100), DQS PI = 4
7347 11:06:25.577785 [0] MIN Duty = 4907%(X100), DQS PI = 32
7348 11:06:25.578170 [0] AVG Duty = 5047%(X100)
7349 11:06:25.581098
7350 11:06:25.584610 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7351 11:06:25.584994
7352 11:06:25.587847 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7353 11:06:25.591091 [DutyScan_Calibration_Flow] ====Done====
7354 11:06:25.591477 ==
7355 11:06:25.594566 Dram Type= 6, Freq= 0, CH_1, rank 0
7356 11:06:25.597695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7357 11:06:25.598084 ==
7358 11:06:25.601195 [Duty_Offset_Calibration]
7359 11:06:25.601668 B0:0 B1:-1 CA:3
7360 11:06:25.601976
7361 11:06:25.604205 [DutyScan_Calibration_Flow] k_type=0
7362 11:06:25.614391
7363 11:06:25.614843 ==CLK 0==
7364 11:06:25.617354 Final CLK duty delay cell = -4
7365 11:06:25.620658 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7366 11:06:25.624559 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7367 11:06:25.627885 [-4] AVG Duty = 4906%(X100)
7368 11:06:25.628350
7369 11:06:25.631095 CH1 CLK Duty spec in!! Max-Min= 187%
7370 11:06:25.634308 [DutyScan_Calibration_Flow] ====Done====
7371 11:06:25.634723
7372 11:06:25.637233 [DutyScan_Calibration_Flow] k_type=1
7373 11:06:25.653489
7374 11:06:25.653894 ==DQS 0 ==
7375 11:06:25.656924 Final DQS duty delay cell = 0
7376 11:06:25.660351 [0] MAX Duty = 5218%(X100), DQS PI = 20
7377 11:06:25.663270 [0] MIN Duty = 4907%(X100), DQS PI = 58
7378 11:06:25.667307 [0] AVG Duty = 5062%(X100)
7379 11:06:25.667784
7380 11:06:25.668253 ==DQS 1 ==
7381 11:06:25.670283 Final DQS duty delay cell = -4
7382 11:06:25.673779 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7383 11:06:25.676621 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7384 11:06:25.680099 [-4] AVG Duty = 4906%(X100)
7385 11:06:25.680585
7386 11:06:25.683096 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7387 11:06:25.683476
7388 11:06:25.686782 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7389 11:06:25.690124 [DutyScan_Calibration_Flow] ====Done====
7390 11:06:25.690593
7391 11:06:25.693170 [DutyScan_Calibration_Flow] k_type=3
7392 11:06:25.711005
7393 11:06:25.711490 ==DQM 0 ==
7394 11:06:25.714201 Final DQM duty delay cell = 0
7395 11:06:25.717241 [0] MAX Duty = 5031%(X100), DQS PI = 6
7396 11:06:25.721661 [0] MIN Duty = 4782%(X100), DQS PI = 40
7397 11:06:25.723989 [0] AVG Duty = 4906%(X100)
7398 11:06:25.724366
7399 11:06:25.724661 ==DQM 1 ==
7400 11:06:25.727344 Final DQM duty delay cell = 0
7401 11:06:25.731184 [0] MAX Duty = 4969%(X100), DQS PI = 30
7402 11:06:25.734062 [0] MIN Duty = 4813%(X100), DQS PI = 60
7403 11:06:25.737036 [0] AVG Duty = 4891%(X100)
7404 11:06:25.737586
7405 11:06:25.740375 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7406 11:06:25.740754
7407 11:06:25.743622 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7408 11:06:25.747410 [DutyScan_Calibration_Flow] ====Done====
7409 11:06:25.747866
7410 11:06:25.750835 [DutyScan_Calibration_Flow] k_type=2
7411 11:06:25.767166
7412 11:06:25.767657 ==DQ 0 ==
7413 11:06:25.770501 Final DQ duty delay cell = -4
7414 11:06:25.773269 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7415 11:06:25.776859 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7416 11:06:25.780414 [-4] AVG Duty = 4891%(X100)
7417 11:06:25.780917
7418 11:06:25.781279 ==DQ 1 ==
7419 11:06:25.783031 Final DQ duty delay cell = 0
7420 11:06:25.786420 [0] MAX Duty = 5062%(X100), DQS PI = 32
7421 11:06:25.790047 [0] MIN Duty = 4875%(X100), DQS PI = 0
7422 11:06:25.801041 [0] AVG Duty = 4968%(X100)
7423 11:06:25.801608
7424 11:06:25.801939 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7425 11:06:25.802246
7426 11:06:25.802701 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7427 11:06:25.803339 [DutyScan_Calibration_Flow] ====Done====
7428 11:06:25.806848 nWR fixed to 30
7429 11:06:25.809382 [ModeRegInit_LP4] CH0 RK0
7430 11:06:25.809809 [ModeRegInit_LP4] CH0 RK1
7431 11:06:25.812895 [ModeRegInit_LP4] CH1 RK0
7432 11:06:25.816585 [ModeRegInit_LP4] CH1 RK1
7433 11:06:25.817075 match AC timing 5
7434 11:06:25.822846 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7435 11:06:25.826039 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7436 11:06:25.829225 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7437 11:06:25.835625 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7438 11:06:25.838920 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7439 11:06:25.839307 [MiockJmeterHQA]
7440 11:06:25.842566
7441 11:06:25.843020 [DramcMiockJmeter] u1RxGatingPI = 0
7442 11:06:25.845704 0 : 4253, 4027
7443 11:06:25.846177 4 : 4365, 4137
7444 11:06:25.849388 8 : 4258, 4026
7445 11:06:25.849774 12 : 4253, 4027
7446 11:06:25.852217 16 : 4253, 4026
7447 11:06:25.852606 20 : 4252, 4027
7448 11:06:25.855520 24 : 4255, 4029
7449 11:06:25.855911 28 : 4253, 4026
7450 11:06:25.856324 32 : 4252, 4027
7451 11:06:25.859167 36 : 4366, 4139
7452 11:06:25.859647 40 : 4253, 4027
7453 11:06:25.862593 44 : 4255, 4029
7454 11:06:25.862983 48 : 4255, 4029
7455 11:06:25.865275 52 : 4365, 4140
7456 11:06:25.865667 56 : 4250, 4027
7457 11:06:25.869225 60 : 4363, 4140
7458 11:06:25.869617 64 : 4250, 4027
7459 11:06:25.869921 68 : 4363, 4139
7460 11:06:25.872634 72 : 4250, 4027
7461 11:06:25.873109 76 : 4250, 4027
7462 11:06:25.875273 80 : 4255, 4029
7463 11:06:25.875661 84 : 4250, 4026
7464 11:06:25.878821 88 : 4363, 4140
7465 11:06:25.879282 92 : 4363, 4140
7466 11:06:25.882101 96 : 4252, 2564
7467 11:06:25.882492 100 : 4252, 0
7468 11:06:25.882796 104 : 4253, 0
7469 11:06:25.885402 108 : 4253, 0
7470 11:06:25.885792 112 : 4250, 0
7471 11:06:25.886101 116 : 4253, 0
7472 11:06:25.888648 120 : 4363, 0
7473 11:06:25.889039 124 : 4361, 0
7474 11:06:25.892440 128 : 4250, 0
7475 11:06:25.892837 132 : 4252, 0
7476 11:06:25.893176 136 : 4250, 0
7477 11:06:25.895120 140 : 4363, 0
7478 11:06:25.895513 144 : 4255, 0
7479 11:06:25.898429 148 : 4250, 0
7480 11:06:25.898821 152 : 4250, 0
7481 11:06:25.899124 156 : 4252, 0
7482 11:06:25.901816 160 : 4250, 0
7483 11:06:25.902208 164 : 4250, 0
7484 11:06:25.904904 168 : 4252, 0
7485 11:06:25.905349 172 : 4361, 0
7486 11:06:25.905658 176 : 4360, 0
7487 11:06:25.908693 180 : 4250, 0
7488 11:06:25.909085 184 : 4255, 0
7489 11:06:25.911434 188 : 4361, 0
7490 11:06:25.911873 192 : 4361, 0
7491 11:06:25.912185 196 : 4250, 0
7492 11:06:25.914861 200 : 4250, 0
7493 11:06:25.915255 204 : 4250, 0
7494 11:06:25.918603 208 : 4250, 0
7495 11:06:25.918882 212 : 4250, 0
7496 11:06:25.919098 216 : 4252, 0
7497 11:06:25.921265 220 : 4253, 711
7498 11:06:25.921543 224 : 4363, 4133
7499 11:06:25.924892 228 : 4361, 4137
7500 11:06:25.925103 232 : 4250, 4027
7501 11:06:25.928023 236 : 4250, 4027
7502 11:06:25.928207 240 : 4250, 4026
7503 11:06:25.931270 244 : 4250, 4027
7504 11:06:25.931439 248 : 4252, 4030
7505 11:06:25.931579 252 : 4253, 4029
7506 11:06:25.934979 256 : 4252, 4029
7507 11:06:25.935121 260 : 4363, 4140
7508 11:06:25.937978 264 : 4255, 4029
7509 11:06:25.938099 268 : 4250, 4027
7510 11:06:25.941124 272 : 4250, 4026
7511 11:06:25.941258 276 : 4363, 4140
7512 11:06:25.944083 280 : 4363, 4137
7513 11:06:25.944191 284 : 4247, 4024
7514 11:06:25.947603 288 : 4365, 4140
7515 11:06:25.947699 292 : 4252, 4030
7516 11:06:25.950861 296 : 4250, 4027
7517 11:06:25.950955 300 : 4252, 4030
7518 11:06:25.954054 304 : 4253, 4029
7519 11:06:25.954141 308 : 4252, 4029
7520 11:06:25.957350 312 : 4363, 4140
7521 11:06:25.957431 316 : 4255, 4029
7522 11:06:25.961281 320 : 4250, 4027
7523 11:06:25.961362 324 : 4250, 4027
7524 11:06:25.961422 328 : 4363, 4140
7525 11:06:25.964119 332 : 4362, 4071
7526 11:06:25.964195 336 : 4250, 1737
7527 11:06:25.964264
7528 11:06:25.967212 MIOCK jitter meter ch=0
7529 11:06:25.967287
7530 11:06:25.970868 1T = (336-100) = 236 dly cells
7531 11:06:25.977175 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7532 11:06:25.977254 ==
7533 11:06:25.980668 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 11:06:25.983705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 11:06:25.983781 ==
7536 11:06:25.990335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 11:06:25.993514 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 11:06:25.997121 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 11:06:26.003301 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 11:06:26.012788 [CA 0] Center 44 (14~74) winsize 61
7541 11:06:26.016324 [CA 1] Center 43 (13~74) winsize 62
7542 11:06:26.019451 [CA 2] Center 39 (10~68) winsize 59
7543 11:06:26.023151 [CA 3] Center 38 (9~68) winsize 60
7544 11:06:26.026387 [CA 4] Center 36 (7~66) winsize 60
7545 11:06:26.029326 [CA 5] Center 36 (6~66) winsize 61
7546 11:06:26.029402
7547 11:06:26.033055 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7548 11:06:26.033189
7549 11:06:26.039284 [CATrainingPosCal] consider 1 rank data
7550 11:06:26.039361 u2DelayCellTimex100 = 275/100 ps
7551 11:06:26.046081 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7552 11:06:26.049072 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7553 11:06:26.053014 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7554 11:06:26.055751 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7555 11:06:26.059449 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7556 11:06:26.062390 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7557 11:06:26.062467
7558 11:06:26.065755 CA PerBit enable=1, Macro0, CA PI delay=36
7559 11:06:26.065833
7560 11:06:26.068649 [CBTSetCACLKResult] CA Dly = 36
7561 11:06:26.072037 CS Dly: 11 (0~42)
7562 11:06:26.075854 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 11:06:26.078987 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 11:06:26.079065 ==
7565 11:06:26.082353 Dram Type= 6, Freq= 0, CH_0, rank 1
7566 11:06:26.088834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 11:06:26.088913 ==
7568 11:06:26.092038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7569 11:06:26.098749 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7570 11:06:26.102243 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7571 11:06:26.108891 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7572 11:06:26.116787 [CA 0] Center 43 (13~74) winsize 62
7573 11:06:26.120305 [CA 1] Center 43 (13~73) winsize 61
7574 11:06:26.123293 [CA 2] Center 38 (9~68) winsize 60
7575 11:06:26.126523 [CA 3] Center 38 (9~68) winsize 60
7576 11:06:26.129566 [CA 4] Center 36 (6~66) winsize 61
7577 11:06:26.132781 [CA 5] Center 36 (6~66) winsize 61
7578 11:06:26.132886
7579 11:06:26.136472 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7580 11:06:26.136549
7581 11:06:26.142805 [CATrainingPosCal] consider 2 rank data
7582 11:06:26.142883 u2DelayCellTimex100 = 275/100 ps
7583 11:06:26.149615 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7584 11:06:26.152911 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7585 11:06:26.156339 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7586 11:06:26.159382 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7587 11:06:26.162912 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7588 11:06:26.166286 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7589 11:06:26.166363
7590 11:06:26.169445 CA PerBit enable=1, Macro0, CA PI delay=36
7591 11:06:26.169521
7592 11:06:26.172405 [CBTSetCACLKResult] CA Dly = 36
7593 11:06:26.175721 CS Dly: 12 (0~44)
7594 11:06:26.179531 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7595 11:06:26.182473 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7596 11:06:26.182549
7597 11:06:26.186001 ----->DramcWriteLeveling(PI) begin...
7598 11:06:26.186078 ==
7599 11:06:26.189087 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 11:06:26.195958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 11:06:26.196044 ==
7602 11:06:26.199048 Write leveling (Byte 0): 34 => 34
7603 11:06:26.202001 Write leveling (Byte 1): 28 => 28
7604 11:06:26.205882 DramcWriteLeveling(PI) end<-----
7605 11:06:26.205958
7606 11:06:26.206016 ==
7607 11:06:26.209253 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 11:06:26.212944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 11:06:26.213019 ==
7610 11:06:26.215162 [Gating] SW mode calibration
7611 11:06:26.221896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7612 11:06:26.228987 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7613 11:06:26.232154 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 11:06:26.235337 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 11:06:26.241786 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
7616 11:06:26.245032 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
7617 11:06:26.248582 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7618 11:06:26.255252 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7619 11:06:26.258258 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 11:06:26.261504 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 11:06:26.267891 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 11:06:26.271163 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7623 11:06:26.274454 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7624 11:06:26.281285 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
7625 11:06:26.284359 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7626 11:06:26.287830 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7627 11:06:26.294209 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 11:06:26.297970 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 11:06:26.300770 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 11:06:26.307867 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 11:06:26.310952 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7632 11:06:26.314155 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7633 11:06:26.320877 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7634 11:06:26.324102 1 6 20 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
7635 11:06:26.327680 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 11:06:26.333793 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 11:06:26.337014 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 11:06:26.340613 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 11:06:26.347113 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7640 11:06:26.350328 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7641 11:06:26.353462 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7642 11:06:26.360166 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7643 11:06:26.363457 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 11:06:26.366758 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 11:06:26.373384 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 11:06:26.376426 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 11:06:26.379899 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 11:06:26.386327 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 11:06:26.389917 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 11:06:26.393299 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:06:26.399645 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:06:26.402784 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:06:26.406300 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:06:26.412898 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:06:26.416242 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7656 11:06:26.419181 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7657 11:06:26.422887 Total UI for P1: 0, mck2ui 16
7658 11:06:26.425821 best dqsien dly found for B0: ( 1, 9, 8)
7659 11:06:26.432729 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7660 11:06:26.435945 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7661 11:06:26.439242 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7662 11:06:26.445882 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 11:06:26.445960 Total UI for P1: 0, mck2ui 16
7664 11:06:26.452278 best dqsien dly found for B1: ( 1, 9, 22)
7665 11:06:26.455610 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7666 11:06:26.458778 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7667 11:06:26.458853
7668 11:06:26.462078 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7669 11:06:26.465363 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7670 11:06:26.469029 [Gating] SW calibration Done
7671 11:06:26.469128 ==
7672 11:06:26.472211 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 11:06:26.475223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 11:06:26.475304 ==
7675 11:06:26.478446 RX Vref Scan: 0
7676 11:06:26.478521
7677 11:06:26.478580 RX Vref 0 -> 0, step: 1
7678 11:06:26.478634
7679 11:06:26.482121 RX Delay 0 -> 252, step: 8
7680 11:06:26.485427 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7681 11:06:26.491668 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7682 11:06:26.494906 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7683 11:06:26.498152 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7684 11:06:26.502217 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7685 11:06:26.504856 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7686 11:06:26.511421 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7687 11:06:26.514681 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7688 11:06:26.518021 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7689 11:06:26.521995 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7690 11:06:26.525686 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7691 11:06:26.531627 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7692 11:06:26.534824 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7693 11:06:26.537928 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7694 11:06:26.541210 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7695 11:06:26.547893 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7696 11:06:26.547972 ==
7697 11:06:26.551519 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 11:06:26.554566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 11:06:26.554695 ==
7700 11:06:26.554777 DQS Delay:
7701 11:06:26.557886 DQS0 = 0, DQS1 = 0
7702 11:06:26.558015 DQM Delay:
7703 11:06:26.561803 DQM0 = 131, DQM1 = 125
7704 11:06:26.561927 DQ Delay:
7705 11:06:26.564793 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7706 11:06:26.568342 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7707 11:06:26.571262 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7708 11:06:26.574467 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7709 11:06:26.574596
7710 11:06:26.578079
7711 11:06:26.578207 ==
7712 11:06:26.580966 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 11:06:26.584605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 11:06:26.584745 ==
7715 11:06:26.584820
7716 11:06:26.584887
7717 11:06:26.587593 TX Vref Scan disable
7718 11:06:26.587688 == TX Byte 0 ==
7719 11:06:26.594146 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7720 11:06:26.597593 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7721 11:06:26.597741 == TX Byte 1 ==
7722 11:06:26.604051 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7723 11:06:26.607802 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7724 11:06:26.607916 ==
7725 11:06:26.610631 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 11:06:26.614167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 11:06:26.614356 ==
7728 11:06:26.628388
7729 11:06:26.631421 TX Vref early break, caculate TX vref
7730 11:06:26.634568 TX Vref=16, minBit 1, minWin=22, winSum=371
7731 11:06:26.638305 TX Vref=18, minBit 8, minWin=22, winSum=383
7732 11:06:26.641122 TX Vref=20, minBit 1, minWin=23, winSum=390
7733 11:06:26.644470 TX Vref=22, minBit 4, minWin=24, winSum=398
7734 11:06:26.648106 TX Vref=24, minBit 7, minWin=24, winSum=410
7735 11:06:26.654255 TX Vref=26, minBit 1, minWin=25, winSum=418
7736 11:06:26.657806 TX Vref=28, minBit 1, minWin=25, winSum=423
7737 11:06:26.661000 TX Vref=30, minBit 2, minWin=25, winSum=420
7738 11:06:26.664085 TX Vref=32, minBit 4, minWin=24, winSum=414
7739 11:06:26.667398 TX Vref=34, minBit 0, minWin=24, winSum=399
7740 11:06:26.673953 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
7741 11:06:26.674097
7742 11:06:26.678081 Final TX Range 0 Vref 28
7743 11:06:26.678199
7744 11:06:26.678277 ==
7745 11:06:26.680690 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 11:06:26.684285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 11:06:26.684433 ==
7748 11:06:26.684506
7749 11:06:26.684572
7750 11:06:26.687602 TX Vref Scan disable
7751 11:06:26.694021 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7752 11:06:26.694161 == TX Byte 0 ==
7753 11:06:26.697523 u2DelayCellOfst[0]=14 cells (4 PI)
7754 11:06:26.700923 u2DelayCellOfst[1]=17 cells (5 PI)
7755 11:06:26.703628 u2DelayCellOfst[2]=10 cells (3 PI)
7756 11:06:26.707648 u2DelayCellOfst[3]=14 cells (4 PI)
7757 11:06:26.710268 u2DelayCellOfst[4]=10 cells (3 PI)
7758 11:06:26.713995 u2DelayCellOfst[5]=0 cells (0 PI)
7759 11:06:26.718096 u2DelayCellOfst[6]=17 cells (5 PI)
7760 11:06:26.720576 u2DelayCellOfst[7]=17 cells (5 PI)
7761 11:06:26.723989 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7762 11:06:26.727030 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7763 11:06:26.730420 == TX Byte 1 ==
7764 11:06:26.733385 u2DelayCellOfst[8]=0 cells (0 PI)
7765 11:06:26.737132 u2DelayCellOfst[9]=0 cells (0 PI)
7766 11:06:26.740489 u2DelayCellOfst[10]=7 cells (2 PI)
7767 11:06:26.740684 u2DelayCellOfst[11]=3 cells (1 PI)
7768 11:06:26.743504 u2DelayCellOfst[12]=10 cells (3 PI)
7769 11:06:26.746907 u2DelayCellOfst[13]=10 cells (3 PI)
7770 11:06:26.749906 u2DelayCellOfst[14]=14 cells (4 PI)
7771 11:06:26.753584 u2DelayCellOfst[15]=10 cells (3 PI)
7772 11:06:26.760379 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7773 11:06:26.763614 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7774 11:06:26.763922 DramC Write-DBI on
7775 11:06:26.766624 ==
7776 11:06:26.770129 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 11:06:26.773528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 11:06:26.773972 ==
7779 11:06:26.774305
7780 11:06:26.774610
7781 11:06:26.776530 TX Vref Scan disable
7782 11:06:26.776955 == TX Byte 0 ==
7783 11:06:26.783458 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7784 11:06:26.783945 == TX Byte 1 ==
7785 11:06:26.786967 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7786 11:06:26.790345 DramC Write-DBI off
7787 11:06:26.790810
7788 11:06:26.791116 [DATLAT]
7789 11:06:26.793364 Freq=1600, CH0 RK0
7790 11:06:26.793753
7791 11:06:26.794052 DATLAT Default: 0xf
7792 11:06:26.796667 0, 0xFFFF, sum = 0
7793 11:06:26.797204 1, 0xFFFF, sum = 0
7794 11:06:26.799874 2, 0xFFFF, sum = 0
7795 11:06:26.800386 3, 0xFFFF, sum = 0
7796 11:06:26.802799 4, 0xFFFF, sum = 0
7797 11:06:26.806362 5, 0xFFFF, sum = 0
7798 11:06:26.806787 6, 0xFFFF, sum = 0
7799 11:06:26.809580 7, 0xFFFF, sum = 0
7800 11:06:26.810014 8, 0xFFFF, sum = 0
7801 11:06:26.812775 9, 0xFFFF, sum = 0
7802 11:06:26.813239 10, 0xFFFF, sum = 0
7803 11:06:26.816398 11, 0xFFFF, sum = 0
7804 11:06:26.816874 12, 0xFFFF, sum = 0
7805 11:06:26.819203 13, 0xFFFF, sum = 0
7806 11:06:26.819601 14, 0x0, sum = 1
7807 11:06:26.822359 15, 0x0, sum = 2
7808 11:06:26.822769 16, 0x0, sum = 3
7809 11:06:26.826507 17, 0x0, sum = 4
7810 11:06:26.826983 best_step = 15
7811 11:06:26.827289
7812 11:06:26.827568 ==
7813 11:06:26.829056 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 11:06:26.836013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 11:06:26.836483 ==
7816 11:06:26.836791 RX Vref Scan: 1
7817 11:06:26.837069
7818 11:06:26.838784 Set Vref Range= 24 -> 127
7819 11:06:26.839176
7820 11:06:26.842426 RX Vref 24 -> 127, step: 1
7821 11:06:26.842828
7822 11:06:26.843134 RX Delay 11 -> 252, step: 4
7823 11:06:26.843419
7824 11:06:26.845809 Set Vref, RX VrefLevel [Byte0]: 24
7825 11:06:26.849461 [Byte1]: 24
7826 11:06:26.853680
7827 11:06:26.854182 Set Vref, RX VrefLevel [Byte0]: 25
7828 11:06:26.856361 [Byte1]: 25
7829 11:06:26.860972
7830 11:06:26.861399 Set Vref, RX VrefLevel [Byte0]: 26
7831 11:06:26.863866 [Byte1]: 26
7832 11:06:26.868493
7833 11:06:26.868880 Set Vref, RX VrefLevel [Byte0]: 27
7834 11:06:26.871973 [Byte1]: 27
7835 11:06:26.876042
7836 11:06:26.876533 Set Vref, RX VrefLevel [Byte0]: 28
7837 11:06:26.880047 [Byte1]: 28
7838 11:06:26.884141
7839 11:06:26.884645 Set Vref, RX VrefLevel [Byte0]: 29
7840 11:06:26.887311 [Byte1]: 29
7841 11:06:26.891173
7842 11:06:26.891603 Set Vref, RX VrefLevel [Byte0]: 30
7843 11:06:26.894558 [Byte1]: 30
7844 11:06:26.899277
7845 11:06:26.899788 Set Vref, RX VrefLevel [Byte0]: 31
7846 11:06:26.902302 [Byte1]: 31
7847 11:06:26.906356
7848 11:06:26.906781 Set Vref, RX VrefLevel [Byte0]: 32
7849 11:06:26.909547 [Byte1]: 32
7850 11:06:26.913873
7851 11:06:26.914261 Set Vref, RX VrefLevel [Byte0]: 33
7852 11:06:26.917445 [Byte1]: 33
7853 11:06:26.921830
7854 11:06:26.922259 Set Vref, RX VrefLevel [Byte0]: 34
7855 11:06:26.925046 [Byte1]: 34
7856 11:06:26.929104
7857 11:06:26.929600 Set Vref, RX VrefLevel [Byte0]: 35
7858 11:06:26.932801 [Byte1]: 35
7859 11:06:26.936979
7860 11:06:26.937526 Set Vref, RX VrefLevel [Byte0]: 36
7861 11:06:26.940081 [Byte1]: 36
7862 11:06:26.945033
7863 11:06:26.945560 Set Vref, RX VrefLevel [Byte0]: 37
7864 11:06:26.947672 [Byte1]: 37
7865 11:06:26.952007
7866 11:06:26.952461 Set Vref, RX VrefLevel [Byte0]: 38
7867 11:06:26.955037 [Byte1]: 38
7868 11:06:26.959607
7869 11:06:26.960075 Set Vref, RX VrefLevel [Byte0]: 39
7870 11:06:26.962902 [Byte1]: 39
7871 11:06:26.967096
7872 11:06:26.967479 Set Vref, RX VrefLevel [Byte0]: 40
7873 11:06:26.970378 [Byte1]: 40
7874 11:06:26.975304
7875 11:06:26.975850 Set Vref, RX VrefLevel [Byte0]: 41
7876 11:06:26.978289 [Byte1]: 41
7877 11:06:26.982452
7878 11:06:26.982838 Set Vref, RX VrefLevel [Byte0]: 42
7879 11:06:26.985928 [Byte1]: 42
7880 11:06:26.990085
7881 11:06:26.990471 Set Vref, RX VrefLevel [Byte0]: 43
7882 11:06:26.994037 [Byte1]: 43
7883 11:06:26.997605
7884 11:06:26.997993 Set Vref, RX VrefLevel [Byte0]: 44
7885 11:06:27.000817 [Byte1]: 44
7886 11:06:27.005125
7887 11:06:27.005548 Set Vref, RX VrefLevel [Byte0]: 45
7888 11:06:27.008396 [Byte1]: 45
7889 11:06:27.013078
7890 11:06:27.013681 Set Vref, RX VrefLevel [Byte0]: 46
7891 11:06:27.016350 [Byte1]: 46
7892 11:06:27.020646
7893 11:06:27.021029 Set Vref, RX VrefLevel [Byte0]: 47
7894 11:06:27.024116 [Byte1]: 47
7895 11:06:27.028484
7896 11:06:27.028998 Set Vref, RX VrefLevel [Byte0]: 48
7897 11:06:27.032239 [Byte1]: 48
7898 11:06:27.035994
7899 11:06:27.036472 Set Vref, RX VrefLevel [Byte0]: 49
7900 11:06:27.039462 [Byte1]: 49
7901 11:06:27.043507
7902 11:06:27.044034 Set Vref, RX VrefLevel [Byte0]: 50
7903 11:06:27.047097 [Byte1]: 50
7904 11:06:27.051010
7905 11:06:27.051435 Set Vref, RX VrefLevel [Byte0]: 51
7906 11:06:27.054405 [Byte1]: 51
7907 11:06:27.058775
7908 11:06:27.059219 Set Vref, RX VrefLevel [Byte0]: 52
7909 11:06:27.061679 [Byte1]: 52
7910 11:06:27.066065
7911 11:06:27.066487 Set Vref, RX VrefLevel [Byte0]: 53
7912 11:06:27.069522 [Byte1]: 53
7913 11:06:27.073661
7914 11:06:27.074040 Set Vref, RX VrefLevel [Byte0]: 54
7915 11:06:27.078096 [Byte1]: 54
7916 11:06:27.082563
7917 11:06:27.083019 Set Vref, RX VrefLevel [Byte0]: 55
7918 11:06:27.084764 [Byte1]: 55
7919 11:06:27.089476
7920 11:06:27.089935 Set Vref, RX VrefLevel [Byte0]: 56
7921 11:06:27.092618 [Byte1]: 56
7922 11:06:27.097190
7923 11:06:27.097668 Set Vref, RX VrefLevel [Byte0]: 57
7924 11:06:27.100396 [Byte1]: 57
7925 11:06:27.104562
7926 11:06:27.104945 Set Vref, RX VrefLevel [Byte0]: 58
7927 11:06:27.107626 [Byte1]: 58
7928 11:06:27.111751
7929 11:06:27.112174 Set Vref, RX VrefLevel [Byte0]: 59
7930 11:06:27.115303 [Byte1]: 59
7931 11:06:27.119542
7932 11:06:27.119996 Set Vref, RX VrefLevel [Byte0]: 60
7933 11:06:27.122750 [Byte1]: 60
7934 11:06:27.127590
7935 11:06:27.128068 Set Vref, RX VrefLevel [Byte0]: 61
7936 11:06:27.130129 [Byte1]: 61
7937 11:06:27.134623
7938 11:06:27.135079 Set Vref, RX VrefLevel [Byte0]: 62
7939 11:06:27.138029 [Byte1]: 62
7940 11:06:27.142887
7941 11:06:27.143380 Set Vref, RX VrefLevel [Byte0]: 63
7942 11:06:27.145853 [Byte1]: 63
7943 11:06:27.149775
7944 11:06:27.150229 Set Vref, RX VrefLevel [Byte0]: 64
7945 11:06:27.153328 [Byte1]: 64
7946 11:06:27.158158
7947 11:06:27.158779 Set Vref, RX VrefLevel [Byte0]: 65
7948 11:06:27.160802 [Byte1]: 65
7949 11:06:27.165071
7950 11:06:27.165490 Set Vref, RX VrefLevel [Byte0]: 66
7951 11:06:27.169212 [Byte1]: 66
7952 11:06:27.172989
7953 11:06:27.173413 Set Vref, RX VrefLevel [Byte0]: 67
7954 11:06:27.176116 [Byte1]: 67
7955 11:06:27.180511
7956 11:06:27.181128 Set Vref, RX VrefLevel [Byte0]: 68
7957 11:06:27.184130 [Byte1]: 68
7958 11:06:27.188187
7959 11:06:27.188640 Set Vref, RX VrefLevel [Byte0]: 69
7960 11:06:27.191702 [Byte1]: 69
7961 11:06:27.195897
7962 11:06:27.196389 Set Vref, RX VrefLevel [Byte0]: 70
7963 11:06:27.199387 [Byte1]: 70
7964 11:06:27.203122
7965 11:06:27.203609 Set Vref, RX VrefLevel [Byte0]: 71
7966 11:06:27.206668 [Byte1]: 71
7967 11:06:27.210941
7968 11:06:27.211327 Set Vref, RX VrefLevel [Byte0]: 72
7969 11:06:27.214033 [Byte1]: 72
7970 11:06:27.218856
7971 11:06:27.219377 Set Vref, RX VrefLevel [Byte0]: 73
7972 11:06:27.221901 [Byte1]: 73
7973 11:06:27.226010
7974 11:06:27.226434 Set Vref, RX VrefLevel [Byte0]: 74
7975 11:06:27.229918 [Byte1]: 74
7976 11:06:27.234166
7977 11:06:27.234673 Set Vref, RX VrefLevel [Byte0]: 75
7978 11:06:27.237530 [Byte1]: 75
7979 11:06:27.241874
7980 11:06:27.242373 Final RX Vref Byte 0 = 56 to rank0
7981 11:06:27.244910 Final RX Vref Byte 1 = 60 to rank0
7982 11:06:27.248184 Final RX Vref Byte 0 = 56 to rank1
7983 11:06:27.251521 Final RX Vref Byte 1 = 60 to rank1==
7984 11:06:27.255037 Dram Type= 6, Freq= 0, CH_0, rank 0
7985 11:06:27.261318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 11:06:27.261747 ==
7987 11:06:27.262078 DQS Delay:
7988 11:06:27.264264 DQS0 = 0, DQS1 = 0
7989 11:06:27.264682 DQM Delay:
7990 11:06:27.264981 DQM0 = 128, DQM1 = 123
7991 11:06:27.267565 DQ Delay:
7992 11:06:27.270953 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7993 11:06:27.274544 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
7994 11:06:27.277643 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7995 11:06:27.280870 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7996 11:06:27.281379
7997 11:06:27.281704
7998 11:06:27.281985
7999 11:06:27.284005 [DramC_TX_OE_Calibration] TA2
8000 11:06:27.287255 Original DQ_B0 (3 6) =30, OEN = 27
8001 11:06:27.290969 Original DQ_B1 (3 6) =30, OEN = 27
8002 11:06:27.294016 24, 0x0, End_B0=24 End_B1=24
8003 11:06:27.297650 25, 0x0, End_B0=25 End_B1=25
8004 11:06:27.298116 26, 0x0, End_B0=26 End_B1=26
8005 11:06:27.300980 27, 0x0, End_B0=27 End_B1=27
8006 11:06:27.303717 28, 0x0, End_B0=28 End_B1=28
8007 11:06:27.306892 29, 0x0, End_B0=29 End_B1=29
8008 11:06:27.307287 30, 0x0, End_B0=30 End_B1=30
8009 11:06:27.310440 31, 0x4141, End_B0=30 End_B1=30
8010 11:06:27.313639 Byte0 end_step=30 best_step=27
8011 11:06:27.317195 Byte1 end_step=30 best_step=27
8012 11:06:27.320792 Byte0 TX OE(2T, 0.5T) = (3, 3)
8013 11:06:27.323736 Byte1 TX OE(2T, 0.5T) = (3, 3)
8014 11:06:27.324273
8015 11:06:27.324570
8016 11:06:27.330385 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
8017 11:06:27.333673 CH0 RK0: MR19=303, MR18=1B18
8018 11:06:27.340235 CH0_RK0: MR19=0x303, MR18=0x1B18, DQSOSC=396, MR23=63, INC=23, DEC=15
8019 11:06:27.340648
8020 11:06:27.343749 ----->DramcWriteLeveling(PI) begin...
8021 11:06:27.344228 ==
8022 11:06:27.346877 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 11:06:27.350266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 11:06:27.350729 ==
8025 11:06:27.353790 Write leveling (Byte 0): 35 => 35
8026 11:06:27.357052 Write leveling (Byte 1): 26 => 26
8027 11:06:27.359804 DramcWriteLeveling(PI) end<-----
8028 11:06:27.360209
8029 11:06:27.360515 ==
8030 11:06:27.363618 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 11:06:27.366380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 11:06:27.371048 ==
8033 11:06:27.371548 [Gating] SW mode calibration
8034 11:06:27.380004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8035 11:06:27.383204 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8036 11:06:27.386817 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 11:06:27.393261 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 11:06:27.396349 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8039 11:06:27.399859 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8040 11:06:27.406247 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8041 11:06:27.409491 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8042 11:06:27.412607 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 11:06:27.419412 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 11:06:27.422655 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 11:06:27.426021 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8046 11:06:27.432672 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8047 11:06:27.435849 1 5 12 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
8048 11:06:27.439337 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8049 11:06:27.446236 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8050 11:06:27.448966 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 11:06:27.452531 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 11:06:27.458769 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 11:06:27.462365 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8054 11:06:27.465481 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8055 11:06:27.472376 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8056 11:06:27.475760 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8057 11:06:27.479005 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 11:06:27.485460 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 11:06:27.488729 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 11:06:27.492393 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 11:06:27.498795 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8062 11:06:27.502036 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8063 11:06:27.505323 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8064 11:06:27.511742 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8065 11:06:27.514945 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8066 11:06:27.518292 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 11:06:27.524772 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 11:06:27.528397 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 11:06:27.531967 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 11:06:27.538233 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 11:06:27.541439 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 11:06:27.544908 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 11:06:27.551440 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 11:06:27.554678 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 11:06:27.558264 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 11:06:27.564648 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 11:06:27.567912 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8078 11:06:27.570830 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8079 11:06:27.578038 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8080 11:06:27.580680 Total UI for P1: 0, mck2ui 16
8081 11:06:27.584407 best dqsien dly found for B0: ( 1, 9, 6)
8082 11:06:27.587353 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8083 11:06:27.590601 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8084 11:06:27.597910 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 11:06:27.601184 Total UI for P1: 0, mck2ui 16
8086 11:06:27.603860 best dqsien dly found for B1: ( 1, 9, 16)
8087 11:06:27.607143 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8088 11:06:27.610572 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8089 11:06:27.610978
8090 11:06:27.614174 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8091 11:06:27.617512 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8092 11:06:27.620798 [Gating] SW calibration Done
8093 11:06:27.621330 ==
8094 11:06:27.623806 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 11:06:27.627468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 11:06:27.627962 ==
8097 11:06:27.630529 RX Vref Scan: 0
8098 11:06:27.630938
8099 11:06:27.631234 RX Vref 0 -> 0, step: 1
8100 11:06:27.633766
8101 11:06:27.634146 RX Delay 0 -> 252, step: 8
8102 11:06:27.639980 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8103 11:06:27.643989 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8104 11:06:27.647041 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8105 11:06:27.649942 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8106 11:06:27.653949 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8107 11:06:27.660058 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8108 11:06:27.663570 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8109 11:06:27.666712 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8110 11:06:27.670745 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8111 11:06:27.673404 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8112 11:06:27.680089 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8113 11:06:27.683501 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8114 11:06:27.686518 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8115 11:06:27.689574 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8116 11:06:27.696484 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8117 11:06:27.699601 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8118 11:06:27.700060 ==
8119 11:06:27.702733 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 11:06:27.705891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 11:06:27.706275 ==
8122 11:06:27.706571 DQS Delay:
8123 11:06:27.709568 DQS0 = 0, DQS1 = 0
8124 11:06:27.709946 DQM Delay:
8125 11:06:27.712586 DQM0 = 132, DQM1 = 124
8126 11:06:27.713169 DQ Delay:
8127 11:06:27.716561 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8128 11:06:27.719646 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8129 11:06:27.722792 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8130 11:06:27.729071 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8131 11:06:27.729578
8132 11:06:27.729881
8133 11:06:27.730154 ==
8134 11:06:27.732305 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 11:06:27.736403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 11:06:27.736786 ==
8137 11:06:27.737081
8138 11:06:27.737443
8139 11:06:27.739364 TX Vref Scan disable
8140 11:06:27.739816 == TX Byte 0 ==
8141 11:06:27.745509 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8142 11:06:27.749547 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8143 11:06:27.750180 == TX Byte 1 ==
8144 11:06:27.755676 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8145 11:06:27.759110 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8146 11:06:27.759591 ==
8147 11:06:27.762205 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 11:06:27.765263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 11:06:27.765809 ==
8150 11:06:27.781729
8151 11:06:27.785441 TX Vref early break, caculate TX vref
8152 11:06:27.788225 TX Vref=16, minBit 9, minWin=23, winSum=383
8153 11:06:27.792172 TX Vref=18, minBit 8, minWin=23, winSum=387
8154 11:06:27.794996 TX Vref=20, minBit 2, minWin=24, winSum=394
8155 11:06:27.798019 TX Vref=22, minBit 0, minWin=24, winSum=401
8156 11:06:27.802209 TX Vref=24, minBit 2, minWin=25, winSum=411
8157 11:06:27.808082 TX Vref=26, minBit 1, minWin=25, winSum=415
8158 11:06:27.811318 TX Vref=28, minBit 4, minWin=25, winSum=418
8159 11:06:27.814574 TX Vref=30, minBit 1, minWin=25, winSum=413
8160 11:06:27.817858 TX Vref=32, minBit 8, minWin=24, winSum=403
8161 11:06:27.821423 TX Vref=34, minBit 0, minWin=24, winSum=398
8162 11:06:27.827942 TX Vref=36, minBit 13, minWin=23, winSum=389
8163 11:06:27.831131 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
8164 11:06:27.831514
8165 11:06:27.834328 Final TX Range 0 Vref 28
8166 11:06:27.834711
8167 11:06:27.835006 ==
8168 11:06:27.837821 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 11:06:27.841279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 11:06:27.841692 ==
8171 11:06:27.844181
8172 11:06:27.844559
8173 11:06:27.844854 TX Vref Scan disable
8174 11:06:27.850851 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8175 11:06:27.851299 == TX Byte 0 ==
8176 11:06:27.854516 u2DelayCellOfst[0]=10 cells (3 PI)
8177 11:06:27.857837 u2DelayCellOfst[1]=14 cells (4 PI)
8178 11:06:27.861249 u2DelayCellOfst[2]=7 cells (2 PI)
8179 11:06:27.864085 u2DelayCellOfst[3]=10 cells (3 PI)
8180 11:06:27.867207 u2DelayCellOfst[4]=3 cells (1 PI)
8181 11:06:27.870989 u2DelayCellOfst[5]=0 cells (0 PI)
8182 11:06:27.873885 u2DelayCellOfst[6]=14 cells (4 PI)
8183 11:06:27.877227 u2DelayCellOfst[7]=14 cells (4 PI)
8184 11:06:27.880684 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8185 11:06:27.883807 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8186 11:06:27.887453 == TX Byte 1 ==
8187 11:06:27.890726 u2DelayCellOfst[8]=0 cells (0 PI)
8188 11:06:27.893770 u2DelayCellOfst[9]=0 cells (0 PI)
8189 11:06:27.897542 u2DelayCellOfst[10]=3 cells (1 PI)
8190 11:06:27.901013 u2DelayCellOfst[11]=0 cells (0 PI)
8191 11:06:27.903711 u2DelayCellOfst[12]=10 cells (3 PI)
8192 11:06:27.906934 u2DelayCellOfst[13]=10 cells (3 PI)
8193 11:06:27.907419 u2DelayCellOfst[14]=14 cells (4 PI)
8194 11:06:27.910476 u2DelayCellOfst[15]=10 cells (3 PI)
8195 11:06:27.917311 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8196 11:06:27.920690 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8197 11:06:27.923951 DramC Write-DBI on
8198 11:06:27.924436 ==
8199 11:06:27.926562 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 11:06:27.929965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 11:06:27.930427 ==
8202 11:06:27.930722
8203 11:06:27.931026
8204 11:06:27.933229 TX Vref Scan disable
8205 11:06:27.936754 == TX Byte 0 ==
8206 11:06:27.940243 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8207 11:06:27.940624 == TX Byte 1 ==
8208 11:06:27.946460 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8209 11:06:27.946911 DramC Write-DBI off
8210 11:06:27.947212
8211 11:06:27.947487 [DATLAT]
8212 11:06:27.949997 Freq=1600, CH0 RK1
8213 11:06:27.950468
8214 11:06:27.950768 DATLAT Default: 0xf
8215 11:06:27.953081 0, 0xFFFF, sum = 0
8216 11:06:27.956324 1, 0xFFFF, sum = 0
8217 11:06:27.956779 2, 0xFFFF, sum = 0
8218 11:06:27.960295 3, 0xFFFF, sum = 0
8219 11:06:27.960932 4, 0xFFFF, sum = 0
8220 11:06:27.963027 5, 0xFFFF, sum = 0
8221 11:06:27.963415 6, 0xFFFF, sum = 0
8222 11:06:27.966228 7, 0xFFFF, sum = 0
8223 11:06:27.966700 8, 0xFFFF, sum = 0
8224 11:06:27.969819 9, 0xFFFF, sum = 0
8225 11:06:27.970207 10, 0xFFFF, sum = 0
8226 11:06:27.973271 11, 0xFFFF, sum = 0
8227 11:06:27.973664 12, 0xFFFF, sum = 0
8228 11:06:27.976044 13, 0xFFFF, sum = 0
8229 11:06:27.976567 14, 0x0, sum = 1
8230 11:06:27.979685 15, 0x0, sum = 2
8231 11:06:27.980177 16, 0x0, sum = 3
8232 11:06:27.982762 17, 0x0, sum = 4
8233 11:06:27.983162 best_step = 15
8234 11:06:27.983543
8235 11:06:27.983902 ==
8236 11:06:27.985979 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 11:06:27.992527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 11:06:27.992923 ==
8239 11:06:27.993440 RX Vref Scan: 0
8240 11:06:27.993809
8241 11:06:27.996321 RX Vref 0 -> 0, step: 1
8242 11:06:27.996711
8243 11:06:27.999368 RX Delay 11 -> 252, step: 4
8244 11:06:28.002778 iDelay=187, Bit 0, Center 128 (79 ~ 178) 100
8245 11:06:28.006473 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8246 11:06:28.012615 iDelay=187, Bit 2, Center 124 (75 ~ 174) 100
8247 11:06:28.016070 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8248 11:06:28.019107 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8249 11:06:28.022214 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8250 11:06:28.025543 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8251 11:06:28.032677 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8252 11:06:28.035670 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8253 11:06:28.038930 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8254 11:06:28.041916 iDelay=187, Bit 10, Center 128 (75 ~ 182) 108
8255 11:06:28.045133 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8256 11:06:28.052318 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8257 11:06:28.055427 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8258 11:06:28.058579 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8259 11:06:28.061680 iDelay=187, Bit 15, Center 132 (79 ~ 186) 108
8260 11:06:28.062064 ==
8261 11:06:28.064907 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 11:06:28.071864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 11:06:28.072317 ==
8264 11:06:28.072616 DQS Delay:
8265 11:06:28.075222 DQS0 = 0, DQS1 = 0
8266 11:06:28.075717 DQM Delay:
8267 11:06:28.077962 DQM0 = 129, DQM1 = 124
8268 11:06:28.078341 DQ Delay:
8269 11:06:28.081637 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8270 11:06:28.084642 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8271 11:06:28.088143 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8272 11:06:28.092062 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8273 11:06:28.092619
8274 11:06:28.092939
8275 11:06:28.093260
8276 11:06:28.094604 [DramC_TX_OE_Calibration] TA2
8277 11:06:28.098091 Original DQ_B0 (3 6) =30, OEN = 27
8278 11:06:28.101035 Original DQ_B1 (3 6) =30, OEN = 27
8279 11:06:28.104591 24, 0x0, End_B0=24 End_B1=24
8280 11:06:28.107873 25, 0x0, End_B0=25 End_B1=25
8281 11:06:28.108415 26, 0x0, End_B0=26 End_B1=26
8282 11:06:28.110914 27, 0x0, End_B0=27 End_B1=27
8283 11:06:28.114102 28, 0x0, End_B0=28 End_B1=28
8284 11:06:28.117735 29, 0x0, End_B0=29 End_B1=29
8285 11:06:28.121048 30, 0x0, End_B0=30 End_B1=30
8286 11:06:28.121564 31, 0x4141, End_B0=30 End_B1=30
8287 11:06:28.124216 Byte0 end_step=30 best_step=27
8288 11:06:28.128200 Byte1 end_step=30 best_step=27
8289 11:06:28.130692 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 11:06:28.134207 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 11:06:28.134856
8292 11:06:28.135278
8293 11:06:28.141262 [DQSOSCAuto] RK1, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8294 11:06:28.144657 CH0 RK1: MR19=303, MR18=1312
8295 11:06:28.150748 CH0_RK1: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8296 11:06:28.153797 [RxdqsGatingPostProcess] freq 1600
8297 11:06:28.160918 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 11:06:28.163672 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 11:06:28.164055 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 11:06:28.166816 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 11:06:28.170035 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 11:06:28.173929 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 11:06:28.177274 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 11:06:28.180801 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 11:06:28.183583 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 11:06:28.187142 Pre-setting of DQS Precalculation
8307 11:06:28.190224 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 11:06:28.193966 ==
8309 11:06:28.196792 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 11:06:28.200755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 11:06:28.201293 ==
8312 11:06:28.203217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 11:06:28.210245 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 11:06:28.213036 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 11:06:28.220390 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 11:06:28.228396 [CA 0] Center 41 (11~72) winsize 62
8317 11:06:28.231717 [CA 1] Center 42 (12~72) winsize 61
8318 11:06:28.234864 [CA 2] Center 38 (9~67) winsize 59
8319 11:06:28.238628 [CA 3] Center 37 (8~66) winsize 59
8320 11:06:28.241172 [CA 4] Center 38 (8~68) winsize 61
8321 11:06:28.244512 [CA 5] Center 36 (7~66) winsize 60
8322 11:06:28.244905
8323 11:06:28.248282 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8324 11:06:28.248752
8325 11:06:28.254258 [CATrainingPosCal] consider 1 rank data
8326 11:06:28.254652 u2DelayCellTimex100 = 275/100 ps
8327 11:06:28.261501 CA0 delay=41 (11~72),Diff = 5 PI (17 cell)
8328 11:06:28.264197 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8329 11:06:28.267663 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8330 11:06:28.271087 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 11:06:28.274967 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8332 11:06:28.277506 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 11:06:28.277898
8334 11:06:28.280525 CA PerBit enable=1, Macro0, CA PI delay=36
8335 11:06:28.280906
8336 11:06:28.284550 [CBTSetCACLKResult] CA Dly = 36
8337 11:06:28.287818 CS Dly: 8 (0~39)
8338 11:06:28.291090 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 11:06:28.294314 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 11:06:28.294695 ==
8341 11:06:28.297172 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 11:06:28.304043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 11:06:28.304500 ==
8344 11:06:28.307669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 11:06:28.313875 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 11:06:28.317401 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 11:06:28.323523 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 11:06:28.331089 [CA 0] Center 42 (12~72) winsize 61
8349 11:06:28.334971 [CA 1] Center 42 (12~72) winsize 61
8350 11:06:28.338106 [CA 2] Center 38 (8~68) winsize 61
8351 11:06:28.341218 [CA 3] Center 37 (7~67) winsize 61
8352 11:06:28.344211 [CA 4] Center 37 (8~67) winsize 60
8353 11:06:28.348225 [CA 5] Center 36 (7~66) winsize 60
8354 11:06:28.348688
8355 11:06:28.350951 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8356 11:06:28.351330
8357 11:06:28.354643 [CATrainingPosCal] consider 2 rank data
8358 11:06:28.357844 u2DelayCellTimex100 = 275/100 ps
8359 11:06:28.364470 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8360 11:06:28.367893 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8361 11:06:28.371312 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8362 11:06:28.374163 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8363 11:06:28.377525 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8364 11:06:28.380934 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8365 11:06:28.381371
8366 11:06:28.384288 CA PerBit enable=1, Macro0, CA PI delay=36
8367 11:06:28.384746
8368 11:06:28.387475 [CBTSetCACLKResult] CA Dly = 36
8369 11:06:28.390999 CS Dly: 10 (0~43)
8370 11:06:28.394096 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 11:06:28.397129 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 11:06:28.397730
8373 11:06:28.400458 ----->DramcWriteLeveling(PI) begin...
8374 11:06:28.400841 ==
8375 11:06:28.403982 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 11:06:28.411039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 11:06:28.411425 ==
8378 11:06:28.413853 Write leveling (Byte 0): 26 => 26
8379 11:06:28.417291 Write leveling (Byte 1): 26 => 26
8380 11:06:28.417677 DramcWriteLeveling(PI) end<-----
8381 11:06:28.417974
8382 11:06:28.420459 ==
8383 11:06:28.423940 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 11:06:28.426919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 11:06:28.427307 ==
8386 11:06:28.430685 [Gating] SW mode calibration
8387 11:06:28.437079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 11:06:28.440920 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 11:06:28.446954 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 11:06:28.449874 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 11:06:28.453192 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 11:06:28.459981 1 4 12 | B1->B0 | 2322 3333 | 1 0 | (0 0) (0 0)
8393 11:06:28.464235 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 11:06:28.466724 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 11:06:28.473423 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 11:06:28.476594 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 11:06:28.480305 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 11:06:28.486477 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 11:06:28.489852 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8400 11:06:28.492744 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 1) (1 0)
8401 11:06:28.499712 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8402 11:06:28.502988 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 11:06:28.505975 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 11:06:28.512692 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 11:06:28.515784 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:06:28.519198 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:06:28.525806 1 6 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
8408 11:06:28.528957 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8409 11:06:28.532561 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 11:06:28.539360 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 11:06:28.542568 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 11:06:28.545510 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 11:06:28.552726 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 11:06:28.555284 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 11:06:28.561615 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 11:06:28.565650 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8417 11:06:28.568333 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8418 11:06:28.575414 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 11:06:28.578591 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 11:06:28.581993 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 11:06:28.588719 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 11:06:28.591593 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 11:06:28.594941 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 11:06:28.601737 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 11:06:28.605074 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 11:06:28.608518 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 11:06:28.615268 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 11:06:28.617769 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 11:06:28.621008 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 11:06:28.627964 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 11:06:28.631058 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8432 11:06:28.634209 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8433 11:06:28.641263 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8434 11:06:28.641722 Total UI for P1: 0, mck2ui 16
8435 11:06:28.644180 best dqsien dly found for B0: ( 1, 9, 10)
8436 11:06:28.650839 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 11:06:28.654116 Total UI for P1: 0, mck2ui 16
8438 11:06:28.657690 best dqsien dly found for B1: ( 1, 9, 14)
8439 11:06:28.660925 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8440 11:06:28.664296 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8441 11:06:28.664762
8442 11:06:28.667164 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8443 11:06:28.670420 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8444 11:06:28.673798 [Gating] SW calibration Done
8445 11:06:28.674181 ==
8446 11:06:28.676735 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 11:06:28.681091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 11:06:28.684180 ==
8449 11:06:28.684633 RX Vref Scan: 0
8450 11:06:28.684930
8451 11:06:28.686998 RX Vref 0 -> 0, step: 1
8452 11:06:28.687382
8453 11:06:28.689946 RX Delay 0 -> 252, step: 8
8454 11:06:28.693763 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8455 11:06:28.697063 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8456 11:06:28.700249 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8457 11:06:28.703300 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8458 11:06:28.710267 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8459 11:06:28.713428 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8460 11:06:28.716899 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8461 11:06:28.720065 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8462 11:06:28.723288 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8463 11:06:28.729675 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8464 11:06:28.733230 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8465 11:06:28.737183 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8466 11:06:28.740086 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8467 11:06:28.743215 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8468 11:06:28.750192 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8469 11:06:28.753248 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8470 11:06:28.753711 ==
8471 11:06:28.756776 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 11:06:28.759524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 11:06:28.759996 ==
8474 11:06:28.762723 DQS Delay:
8475 11:06:28.763106 DQS0 = 0, DQS1 = 0
8476 11:06:28.766015 DQM Delay:
8477 11:06:28.766497 DQM0 = 134, DQM1 = 131
8478 11:06:28.767005 DQ Delay:
8479 11:06:28.769108 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8480 11:06:28.776221 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8481 11:06:28.779843 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8482 11:06:28.782559 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8483 11:06:28.782948
8484 11:06:28.783244
8485 11:06:28.783522 ==
8486 11:06:28.785791 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 11:06:28.789013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 11:06:28.789447 ==
8489 11:06:28.789751
8490 11:06:28.790024
8491 11:06:28.792450 TX Vref Scan disable
8492 11:06:28.796107 == TX Byte 0 ==
8493 11:06:28.798980 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8494 11:06:28.802576 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8495 11:06:28.805430 == TX Byte 1 ==
8496 11:06:28.808882 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8497 11:06:28.812400 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8498 11:06:28.812866 ==
8499 11:06:28.815492 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 11:06:28.821912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 11:06:28.822365 ==
8502 11:06:28.833916
8503 11:06:28.836831 TX Vref early break, caculate TX vref
8504 11:06:28.839704 TX Vref=16, minBit 9, minWin=21, winSum=370
8505 11:06:28.842874 TX Vref=18, minBit 8, minWin=22, winSum=380
8506 11:06:28.846251 TX Vref=20, minBit 1, minWin=23, winSum=388
8507 11:06:28.849921 TX Vref=22, minBit 8, minWin=23, winSum=392
8508 11:06:28.853522 TX Vref=24, minBit 8, minWin=24, winSum=404
8509 11:06:28.860171 TX Vref=26, minBit 3, minWin=25, winSum=414
8510 11:06:28.862957 TX Vref=28, minBit 12, minWin=25, winSum=421
8511 11:06:28.866451 TX Vref=30, minBit 0, minWin=25, winSum=414
8512 11:06:28.869547 TX Vref=32, minBit 0, minWin=24, winSum=405
8513 11:06:28.872770 TX Vref=34, minBit 9, minWin=23, winSum=397
8514 11:06:28.879408 [TxChooseVref] Worse bit 12, Min win 25, Win sum 421, Final Vref 28
8515 11:06:28.879943
8516 11:06:28.882611 Final TX Range 0 Vref 28
8517 11:06:28.883001
8518 11:06:28.883312 ==
8519 11:06:28.886210 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 11:06:28.889284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 11:06:28.889680 ==
8522 11:06:28.889982
8523 11:06:28.890256
8524 11:06:28.892393 TX Vref Scan disable
8525 11:06:28.899118 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8526 11:06:28.899508 == TX Byte 0 ==
8527 11:06:28.902670 u2DelayCellOfst[0]=14 cells (4 PI)
8528 11:06:28.905812 u2DelayCellOfst[1]=10 cells (3 PI)
8529 11:06:28.908812 u2DelayCellOfst[2]=0 cells (0 PI)
8530 11:06:28.912174 u2DelayCellOfst[3]=3 cells (1 PI)
8531 11:06:28.915838 u2DelayCellOfst[4]=7 cells (2 PI)
8532 11:06:28.919314 u2DelayCellOfst[5]=17 cells (5 PI)
8533 11:06:28.922464 u2DelayCellOfst[6]=17 cells (5 PI)
8534 11:06:28.925979 u2DelayCellOfst[7]=7 cells (2 PI)
8535 11:06:28.928999 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8536 11:06:28.932855 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8537 11:06:28.935874 == TX Byte 1 ==
8538 11:06:28.938892 u2DelayCellOfst[8]=0 cells (0 PI)
8539 11:06:28.939363 u2DelayCellOfst[9]=3 cells (1 PI)
8540 11:06:28.942391 u2DelayCellOfst[10]=10 cells (3 PI)
8541 11:06:28.945609 u2DelayCellOfst[11]=7 cells (2 PI)
8542 11:06:28.948956 u2DelayCellOfst[12]=14 cells (4 PI)
8543 11:06:28.951962 u2DelayCellOfst[13]=14 cells (4 PI)
8544 11:06:28.955484 u2DelayCellOfst[14]=17 cells (5 PI)
8545 11:06:28.958440 u2DelayCellOfst[15]=17 cells (5 PI)
8546 11:06:28.965475 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8547 11:06:28.968484 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8548 11:06:28.968868 DramC Write-DBI on
8549 11:06:28.969209 ==
8550 11:06:28.971829 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 11:06:28.978567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 11:06:28.979083 ==
8553 11:06:28.979415
8554 11:06:28.979712
8555 11:06:28.979970 TX Vref Scan disable
8556 11:06:28.982833 == TX Byte 0 ==
8557 11:06:28.985738 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8558 11:06:28.989078 == TX Byte 1 ==
8559 11:06:28.992645 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8560 11:06:28.995565 DramC Write-DBI off
8561 11:06:28.996049
8562 11:06:28.996480 [DATLAT]
8563 11:06:28.996905 Freq=1600, CH1 RK0
8564 11:06:28.997413
8565 11:06:28.998866 DATLAT Default: 0xf
8566 11:06:29.002616 0, 0xFFFF, sum = 0
8567 11:06:29.003096 1, 0xFFFF, sum = 0
8568 11:06:29.005436 2, 0xFFFF, sum = 0
8569 11:06:29.005857 3, 0xFFFF, sum = 0
8570 11:06:29.009519 4, 0xFFFF, sum = 0
8571 11:06:29.009909 5, 0xFFFF, sum = 0
8572 11:06:29.012148 6, 0xFFFF, sum = 0
8573 11:06:29.012535 7, 0xFFFF, sum = 0
8574 11:06:29.015160 8, 0xFFFF, sum = 0
8575 11:06:29.015567 9, 0xFFFF, sum = 0
8576 11:06:29.019617 10, 0xFFFF, sum = 0
8577 11:06:29.020005 11, 0xFFFF, sum = 0
8578 11:06:29.021691 12, 0xFFFF, sum = 0
8579 11:06:29.022269 13, 0xFFFF, sum = 0
8580 11:06:29.025239 14, 0x0, sum = 1
8581 11:06:29.025626 15, 0x0, sum = 2
8582 11:06:29.028975 16, 0x0, sum = 3
8583 11:06:29.029431 17, 0x0, sum = 4
8584 11:06:29.031671 best_step = 15
8585 11:06:29.032064
8586 11:06:29.032451 ==
8587 11:06:29.035427 Dram Type= 6, Freq= 0, CH_1, rank 0
8588 11:06:29.038262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8589 11:06:29.038660 ==
8590 11:06:29.041672 RX Vref Scan: 1
8591 11:06:29.042066
8592 11:06:29.042456 Set Vref Range= 24 -> 127
8593 11:06:29.042821
8594 11:06:29.045260 RX Vref 24 -> 127, step: 1
8595 11:06:29.045669
8596 11:06:29.048422 RX Delay 19 -> 252, step: 4
8597 11:06:29.048821
8598 11:06:29.051645 Set Vref, RX VrefLevel [Byte0]: 24
8599 11:06:29.055401 [Byte1]: 24
8600 11:06:29.055789
8601 11:06:29.058267 Set Vref, RX VrefLevel [Byte0]: 25
8602 11:06:29.062001 [Byte1]: 25
8603 11:06:29.065471
8604 11:06:29.065948 Set Vref, RX VrefLevel [Byte0]: 26
8605 11:06:29.068365 [Byte1]: 26
8606 11:06:29.072950
8607 11:06:29.073380 Set Vref, RX VrefLevel [Byte0]: 27
8608 11:06:29.076259 [Byte1]: 27
8609 11:06:29.080573
8610 11:06:29.081040 Set Vref, RX VrefLevel [Byte0]: 28
8611 11:06:29.083662 [Byte1]: 28
8612 11:06:29.087982
8613 11:06:29.088438 Set Vref, RX VrefLevel [Byte0]: 29
8614 11:06:29.091390 [Byte1]: 29
8615 11:06:29.095484
8616 11:06:29.095940 Set Vref, RX VrefLevel [Byte0]: 30
8617 11:06:29.098641 [Byte1]: 30
8618 11:06:29.103073
8619 11:06:29.103534 Set Vref, RX VrefLevel [Byte0]: 31
8620 11:06:29.106169 [Byte1]: 31
8621 11:06:29.110554
8622 11:06:29.111066 Set Vref, RX VrefLevel [Byte0]: 32
8623 11:06:29.113638 [Byte1]: 32
8624 11:06:29.118123
8625 11:06:29.118521 Set Vref, RX VrefLevel [Byte0]: 33
8626 11:06:29.121644 [Byte1]: 33
8627 11:06:29.125937
8628 11:06:29.126332 Set Vref, RX VrefLevel [Byte0]: 34
8629 11:06:29.129229 [Byte1]: 34
8630 11:06:29.133932
8631 11:06:29.134409 Set Vref, RX VrefLevel [Byte0]: 35
8632 11:06:29.136537 [Byte1]: 35
8633 11:06:29.141280
8634 11:06:29.141758 Set Vref, RX VrefLevel [Byte0]: 36
8635 11:06:29.144399 [Byte1]: 36
8636 11:06:29.148702
8637 11:06:29.149238 Set Vref, RX VrefLevel [Byte0]: 37
8638 11:06:29.152101 [Byte1]: 37
8639 11:06:29.156035
8640 11:06:29.156425 Set Vref, RX VrefLevel [Byte0]: 38
8641 11:06:29.159537 [Byte1]: 38
8642 11:06:29.164068
8643 11:06:29.164533 Set Vref, RX VrefLevel [Byte0]: 39
8644 11:06:29.166827 [Byte1]: 39
8645 11:06:29.171467
8646 11:06:29.171853 Set Vref, RX VrefLevel [Byte0]: 40
8647 11:06:29.174740 [Byte1]: 40
8648 11:06:29.179033
8649 11:06:29.179501 Set Vref, RX VrefLevel [Byte0]: 41
8650 11:06:29.182032 [Byte1]: 41
8651 11:06:29.186889
8652 11:06:29.187365 Set Vref, RX VrefLevel [Byte0]: 42
8653 11:06:29.189974 [Byte1]: 42
8654 11:06:29.194555
8655 11:06:29.194938 Set Vref, RX VrefLevel [Byte0]: 43
8656 11:06:29.197201 [Byte1]: 43
8657 11:06:29.201852
8658 11:06:29.202236 Set Vref, RX VrefLevel [Byte0]: 44
8659 11:06:29.204715 [Byte1]: 44
8660 11:06:29.209192
8661 11:06:29.209651 Set Vref, RX VrefLevel [Byte0]: 45
8662 11:06:29.212189 [Byte1]: 45
8663 11:06:29.216958
8664 11:06:29.217372 Set Vref, RX VrefLevel [Byte0]: 46
8665 11:06:29.220110 [Byte1]: 46
8666 11:06:29.224022
8667 11:06:29.224410 Set Vref, RX VrefLevel [Byte0]: 47
8668 11:06:29.227928 [Byte1]: 47
8669 11:06:29.231888
8670 11:06:29.232354 Set Vref, RX VrefLevel [Byte0]: 48
8671 11:06:29.234915 [Byte1]: 48
8672 11:06:29.239614
8673 11:06:29.240210 Set Vref, RX VrefLevel [Byte0]: 49
8674 11:06:29.242811 [Byte1]: 49
8675 11:06:29.246977
8676 11:06:29.247363 Set Vref, RX VrefLevel [Byte0]: 50
8677 11:06:29.250054 [Byte1]: 50
8678 11:06:29.254868
8679 11:06:29.255350 Set Vref, RX VrefLevel [Byte0]: 51
8680 11:06:29.257650 [Byte1]: 51
8681 11:06:29.262066
8682 11:06:29.262547 Set Vref, RX VrefLevel [Byte0]: 52
8683 11:06:29.265502 [Byte1]: 52
8684 11:06:29.269428
8685 11:06:29.269814 Set Vref, RX VrefLevel [Byte0]: 53
8686 11:06:29.272761 [Byte1]: 53
8687 11:06:29.277370
8688 11:06:29.277755 Set Vref, RX VrefLevel [Byte0]: 54
8689 11:06:29.280463 [Byte1]: 54
8690 11:06:29.284722
8691 11:06:29.285119 Set Vref, RX VrefLevel [Byte0]: 55
8692 11:06:29.288080 [Byte1]: 55
8693 11:06:29.292550
8694 11:06:29.293009 Set Vref, RX VrefLevel [Byte0]: 56
8695 11:06:29.295818 [Byte1]: 56
8696 11:06:29.299899
8697 11:06:29.300286 Set Vref, RX VrefLevel [Byte0]: 57
8698 11:06:29.303333 [Byte1]: 57
8699 11:06:29.307710
8700 11:06:29.308096 Set Vref, RX VrefLevel [Byte0]: 58
8701 11:06:29.310930 [Byte1]: 58
8702 11:06:29.315318
8703 11:06:29.315705 Set Vref, RX VrefLevel [Byte0]: 59
8704 11:06:29.318426 [Byte1]: 59
8705 11:06:29.322818
8706 11:06:29.323204 Set Vref, RX VrefLevel [Byte0]: 60
8707 11:06:29.326488 [Byte1]: 60
8708 11:06:29.330073
8709 11:06:29.330461 Set Vref, RX VrefLevel [Byte0]: 61
8710 11:06:29.333539 [Byte1]: 61
8711 11:06:29.337798
8712 11:06:29.338192 Set Vref, RX VrefLevel [Byte0]: 62
8713 11:06:29.340945 [Byte1]: 62
8714 11:06:29.345550
8715 11:06:29.345944 Set Vref, RX VrefLevel [Byte0]: 63
8716 11:06:29.348700 [Byte1]: 63
8717 11:06:29.353122
8718 11:06:29.353621 Set Vref, RX VrefLevel [Byte0]: 64
8719 11:06:29.356082 [Byte1]: 64
8720 11:06:29.360543
8721 11:06:29.361011 Set Vref, RX VrefLevel [Byte0]: 65
8722 11:06:29.363911 [Byte1]: 65
8723 11:06:29.368041
8724 11:06:29.371169 Set Vref, RX VrefLevel [Byte0]: 66
8725 11:06:29.371567 [Byte1]: 66
8726 11:06:29.375767
8727 11:06:29.376154 Set Vref, RX VrefLevel [Byte0]: 67
8728 11:06:29.379382 [Byte1]: 67
8729 11:06:29.383411
8730 11:06:29.383800 Set Vref, RX VrefLevel [Byte0]: 68
8731 11:06:29.387034 [Byte1]: 68
8732 11:06:29.391236
8733 11:06:29.391714 Set Vref, RX VrefLevel [Byte0]: 69
8734 11:06:29.394118 [Byte1]: 69
8735 11:06:29.398616
8736 11:06:29.399003 Set Vref, RX VrefLevel [Byte0]: 70
8737 11:06:29.401457 [Byte1]: 70
8738 11:06:29.406003
8739 11:06:29.406461 Set Vref, RX VrefLevel [Byte0]: 71
8740 11:06:29.409574 [Byte1]: 71
8741 11:06:29.413455
8742 11:06:29.413843 Final RX Vref Byte 0 = 58 to rank0
8743 11:06:29.416419 Final RX Vref Byte 1 = 61 to rank0
8744 11:06:29.420788 Final RX Vref Byte 0 = 58 to rank1
8745 11:06:29.423641 Final RX Vref Byte 1 = 61 to rank1==
8746 11:06:29.426496 Dram Type= 6, Freq= 0, CH_1, rank 0
8747 11:06:29.433438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 11:06:29.433829 ==
8749 11:06:29.434135 DQS Delay:
8750 11:06:29.436476 DQS0 = 0, DQS1 = 0
8751 11:06:29.436866 DQM Delay:
8752 11:06:29.437197 DQM0 = 132, DQM1 = 130
8753 11:06:29.439721 DQ Delay:
8754 11:06:29.443003 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =130
8755 11:06:29.446777 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =130
8756 11:06:29.450551 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8757 11:06:29.453827 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8758 11:06:29.454308
8759 11:06:29.454702
8760 11:06:29.455127
8761 11:06:29.457505 [DramC_TX_OE_Calibration] TA2
8762 11:06:29.459980 Original DQ_B0 (3 6) =30, OEN = 27
8763 11:06:29.463082 Original DQ_B1 (3 6) =30, OEN = 27
8764 11:06:29.466263 24, 0x0, End_B0=24 End_B1=24
8765 11:06:29.466669 25, 0x0, End_B0=25 End_B1=25
8766 11:06:29.469816 26, 0x0, End_B0=26 End_B1=26
8767 11:06:29.473186 27, 0x0, End_B0=27 End_B1=27
8768 11:06:29.476360 28, 0x0, End_B0=28 End_B1=28
8769 11:06:29.479922 29, 0x0, End_B0=29 End_B1=29
8770 11:06:29.480386 30, 0x0, End_B0=30 End_B1=30
8771 11:06:29.483170 31, 0x4545, End_B0=30 End_B1=30
8772 11:06:29.486417 Byte0 end_step=30 best_step=27
8773 11:06:29.489277 Byte1 end_step=30 best_step=27
8774 11:06:29.493013 Byte0 TX OE(2T, 0.5T) = (3, 3)
8775 11:06:29.496253 Byte1 TX OE(2T, 0.5T) = (3, 3)
8776 11:06:29.496718
8777 11:06:29.497022
8778 11:06:29.502670 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8779 11:06:29.505834 CH1 RK0: MR19=303, MR18=E18
8780 11:06:29.512879 CH1_RK0: MR19=0x303, MR18=0xE18, DQSOSC=397, MR23=63, INC=23, DEC=15
8781 11:06:29.513297
8782 11:06:29.516095 ----->DramcWriteLeveling(PI) begin...
8783 11:06:29.516488 ==
8784 11:06:29.519180 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 11:06:29.522439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 11:06:29.522830 ==
8787 11:06:29.525652 Write leveling (Byte 0): 25 => 25
8788 11:06:29.529079 Write leveling (Byte 1): 26 => 26
8789 11:06:29.532946 DramcWriteLeveling(PI) end<-----
8790 11:06:29.533448
8791 11:06:29.533755 ==
8792 11:06:29.535633 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 11:06:29.539138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 11:06:29.539608 ==
8795 11:06:29.542313 [Gating] SW mode calibration
8796 11:06:29.548968 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8797 11:06:29.555426 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8798 11:06:29.558949 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 11:06:29.565325 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8800 11:06:29.568687 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8801 11:06:29.572151 1 4 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8802 11:06:29.578545 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 11:06:29.581377 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 11:06:29.585030 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 11:06:29.592024 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 11:06:29.594692 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 11:06:29.598063 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8808 11:06:29.604798 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8809 11:06:29.608331 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8810 11:06:29.611128 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8811 11:06:29.618032 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 11:06:29.620857 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 11:06:29.624521 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 11:06:29.630814 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 11:06:29.634689 1 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8816 11:06:29.638112 1 6 8 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8817 11:06:29.644480 1 6 12 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8818 11:06:29.647982 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 11:06:29.650656 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 11:06:29.657595 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 11:06:29.660484 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 11:06:29.664156 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 11:06:29.670661 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 11:06:29.673696 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8825 11:06:29.677426 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8826 11:06:29.683429 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 11:06:29.687681 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 11:06:29.690386 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 11:06:29.697001 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 11:06:29.700338 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 11:06:29.703406 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 11:06:29.710236 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 11:06:29.713380 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 11:06:29.716635 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 11:06:29.723374 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 11:06:29.726409 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 11:06:29.729953 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 11:06:29.736428 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 11:06:29.739572 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8840 11:06:29.743079 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8841 11:06:29.749756 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8842 11:06:29.753247 Total UI for P1: 0, mck2ui 16
8843 11:06:29.756110 best dqsien dly found for B0: ( 1, 9, 6)
8844 11:06:29.759519 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 11:06:29.762612 Total UI for P1: 0, mck2ui 16
8846 11:06:29.765855 best dqsien dly found for B1: ( 1, 9, 12)
8847 11:06:29.769271 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8848 11:06:29.772634 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8849 11:06:29.773023
8850 11:06:29.776180 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8851 11:06:29.779881 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8852 11:06:29.782422 [Gating] SW calibration Done
8853 11:06:29.782810 ==
8854 11:06:29.786478 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 11:06:29.792467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 11:06:29.792998 ==
8857 11:06:29.793425 RX Vref Scan: 0
8858 11:06:29.793724
8859 11:06:29.795689 RX Vref 0 -> 0, step: 1
8860 11:06:29.796076
8861 11:06:29.799502 RX Delay 0 -> 252, step: 8
8862 11:06:29.802401 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8863 11:06:29.806145 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8864 11:06:29.809021 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8865 11:06:29.812348 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8866 11:06:29.818563 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8867 11:06:29.822950 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8868 11:06:29.825306 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8869 11:06:29.828376 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8870 11:06:29.838015 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8871 11:06:29.839023 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8872 11:06:29.841976 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8873 11:06:29.844951 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8874 11:06:29.848359 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8875 11:06:29.855212 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8876 11:06:29.858690 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8877 11:06:29.862218 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8878 11:06:29.862642 ==
8879 11:06:29.864810 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 11:06:29.867968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 11:06:29.871316 ==
8882 11:06:29.871895 DQS Delay:
8883 11:06:29.872334 DQS0 = 0, DQS1 = 0
8884 11:06:29.874707 DQM Delay:
8885 11:06:29.875165 DQM0 = 137, DQM1 = 130
8886 11:06:29.878464 DQ Delay:
8887 11:06:29.881503 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8888 11:06:29.884544 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8889 11:06:29.887660 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8890 11:06:29.891454 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8891 11:06:29.891916
8892 11:06:29.892214
8893 11:06:29.892633 ==
8894 11:06:29.894506 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 11:06:29.897777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 11:06:29.898252 ==
8897 11:06:29.901301
8898 11:06:29.901683
8899 11:06:29.901981 TX Vref Scan disable
8900 11:06:29.904321 == TX Byte 0 ==
8901 11:06:29.907532 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8902 11:06:29.910966 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8903 11:06:29.914155 == TX Byte 1 ==
8904 11:06:29.917845 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8905 11:06:29.920799 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8906 11:06:29.921207 ==
8907 11:06:29.924528 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 11:06:29.930487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 11:06:29.930879 ==
8910 11:06:29.942526
8911 11:06:29.945897 TX Vref early break, caculate TX vref
8912 11:06:29.949050 TX Vref=16, minBit 9, minWin=22, winSum=380
8913 11:06:29.952742 TX Vref=18, minBit 5, minWin=23, winSum=386
8914 11:06:29.955500 TX Vref=20, minBit 9, minWin=22, winSum=389
8915 11:06:29.958885 TX Vref=22, minBit 9, minWin=23, winSum=402
8916 11:06:29.962054 TX Vref=24, minBit 9, minWin=23, winSum=408
8917 11:06:29.968591 TX Vref=26, minBit 9, minWin=24, winSum=413
8918 11:06:29.971904 TX Vref=28, minBit 9, minWin=24, winSum=419
8919 11:06:29.975125 TX Vref=30, minBit 5, minWin=25, winSum=419
8920 11:06:29.978719 TX Vref=32, minBit 0, minWin=25, winSum=410
8921 11:06:29.982048 TX Vref=34, minBit 9, minWin=23, winSum=396
8922 11:06:29.988747 [TxChooseVref] Worse bit 5, Min win 25, Win sum 419, Final Vref 30
8923 11:06:29.989247
8924 11:06:29.991675 Final TX Range 0 Vref 30
8925 11:06:29.992121
8926 11:06:29.992421 ==
8927 11:06:29.995350 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:06:29.998466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:06:29.998854 ==
8930 11:06:29.999153
8931 11:06:29.999425
8932 11:06:30.001864 TX Vref Scan disable
8933 11:06:30.008103 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8934 11:06:30.008600 == TX Byte 0 ==
8935 11:06:30.011930 u2DelayCellOfst[0]=14 cells (4 PI)
8936 11:06:30.015459 u2DelayCellOfst[1]=10 cells (3 PI)
8937 11:06:30.018040 u2DelayCellOfst[2]=0 cells (0 PI)
8938 11:06:30.021239 u2DelayCellOfst[3]=3 cells (1 PI)
8939 11:06:30.025058 u2DelayCellOfst[4]=7 cells (2 PI)
8940 11:06:30.028328 u2DelayCellOfst[5]=17 cells (5 PI)
8941 11:06:30.031645 u2DelayCellOfst[6]=14 cells (4 PI)
8942 11:06:30.034444 u2DelayCellOfst[7]=7 cells (2 PI)
8943 11:06:30.038507 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8944 11:06:30.041785 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8945 11:06:30.044720 == TX Byte 1 ==
8946 11:06:30.047695 u2DelayCellOfst[8]=0 cells (0 PI)
8947 11:06:30.051441 u2DelayCellOfst[9]=3 cells (1 PI)
8948 11:06:30.054264 u2DelayCellOfst[10]=10 cells (3 PI)
8949 11:06:30.054649 u2DelayCellOfst[11]=7 cells (2 PI)
8950 11:06:30.057416 u2DelayCellOfst[12]=14 cells (4 PI)
8951 11:06:30.060728 u2DelayCellOfst[13]=17 cells (5 PI)
8952 11:06:30.064266 u2DelayCellOfst[14]=14 cells (4 PI)
8953 11:06:30.068093 u2DelayCellOfst[15]=14 cells (4 PI)
8954 11:06:30.074143 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8955 11:06:30.077373 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8956 11:06:30.077837 DramC Write-DBI on
8957 11:06:30.078137 ==
8958 11:06:30.081319 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 11:06:30.088557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 11:06:30.089011 ==
8961 11:06:30.089354
8962 11:06:30.089634
8963 11:06:30.089901 TX Vref Scan disable
8964 11:06:30.092069 == TX Byte 0 ==
8965 11:06:30.095018 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8966 11:06:30.098118 == TX Byte 1 ==
8967 11:06:30.101560 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8968 11:06:30.101966 DramC Write-DBI off
8969 11:06:30.104821
8970 11:06:30.105336 [DATLAT]
8971 11:06:30.105645 Freq=1600, CH1 RK1
8972 11:06:30.105927
8973 11:06:30.108785 DATLAT Default: 0xf
8974 11:06:30.109198 0, 0xFFFF, sum = 0
8975 11:06:30.111704 1, 0xFFFF, sum = 0
8976 11:06:30.112097 2, 0xFFFF, sum = 0
8977 11:06:30.115700 3, 0xFFFF, sum = 0
8978 11:06:30.118075 4, 0xFFFF, sum = 0
8979 11:06:30.118495 5, 0xFFFF, sum = 0
8980 11:06:30.121369 6, 0xFFFF, sum = 0
8981 11:06:30.121764 7, 0xFFFF, sum = 0
8982 11:06:30.124697 8, 0xFFFF, sum = 0
8983 11:06:30.125192 9, 0xFFFF, sum = 0
8984 11:06:30.128347 10, 0xFFFF, sum = 0
8985 11:06:30.128741 11, 0xFFFF, sum = 0
8986 11:06:30.131165 12, 0xFFFF, sum = 0
8987 11:06:30.131559 13, 0xFFFF, sum = 0
8988 11:06:30.135061 14, 0x0, sum = 1
8989 11:06:30.135545 15, 0x0, sum = 2
8990 11:06:30.138022 16, 0x0, sum = 3
8991 11:06:30.138416 17, 0x0, sum = 4
8992 11:06:30.141220 best_step = 15
8993 11:06:30.141606
8994 11:06:30.141909 ==
8995 11:06:30.144219 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 11:06:30.147946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 11:06:30.148340 ==
8998 11:06:30.151713 RX Vref Scan: 0
8999 11:06:30.152097
9000 11:06:30.152398 RX Vref 0 -> 0, step: 1
9001 11:06:30.152678
9002 11:06:30.154311 RX Delay 11 -> 252, step: 4
9003 11:06:30.161130 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
9004 11:06:30.164490 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
9005 11:06:30.168154 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9006 11:06:30.171136 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
9007 11:06:30.173802 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
9008 11:06:30.181416 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9009 11:06:30.184064 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9010 11:06:30.187730 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9011 11:06:30.190529 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9012 11:06:30.194026 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9013 11:06:30.201839 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
9014 11:06:30.203714 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9015 11:06:30.207919 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9016 11:06:30.210589 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9017 11:06:30.214029 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9018 11:06:30.220542 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9019 11:06:30.220925 ==
9020 11:06:30.224003 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 11:06:30.226823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 11:06:30.227214 ==
9023 11:06:30.230082 DQS Delay:
9024 11:06:30.230466 DQS0 = 0, DQS1 = 0
9025 11:06:30.230767 DQM Delay:
9026 11:06:30.233554 DQM0 = 132, DQM1 = 128
9027 11:06:30.234115 DQ Delay:
9028 11:06:30.236691 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
9029 11:06:30.240191 DQ4 =132, DQ5 =144, DQ6 =140, DQ7 =128
9030 11:06:30.243878 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9031 11:06:30.249875 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9032 11:06:30.250299
9033 11:06:30.250601
9034 11:06:30.250878
9035 11:06:30.253570 [DramC_TX_OE_Calibration] TA2
9036 11:06:30.253958 Original DQ_B0 (3 6) =30, OEN = 27
9037 11:06:30.256382 Original DQ_B1 (3 6) =30, OEN = 27
9038 11:06:30.260455 24, 0x0, End_B0=24 End_B1=24
9039 11:06:30.263462 25, 0x0, End_B0=25 End_B1=25
9040 11:06:30.267802 26, 0x0, End_B0=26 End_B1=26
9041 11:06:30.269873 27, 0x0, End_B0=27 End_B1=27
9042 11:06:30.270268 28, 0x0, End_B0=28 End_B1=28
9043 11:06:30.273558 29, 0x0, End_B0=29 End_B1=29
9044 11:06:30.276693 30, 0x0, End_B0=30 End_B1=30
9045 11:06:30.279726 31, 0x4141, End_B0=30 End_B1=30
9046 11:06:30.282733 Byte0 end_step=30 best_step=27
9047 11:06:30.286414 Byte1 end_step=30 best_step=27
9048 11:06:30.286799 Byte0 TX OE(2T, 0.5T) = (3, 3)
9049 11:06:30.289592 Byte1 TX OE(2T, 0.5T) = (3, 3)
9050 11:06:30.289980
9051 11:06:30.290279
9052 11:06:30.299911 [DQSOSCAuto] RK1, (LSB)MR18= 0x111f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9053 11:06:30.302496 CH1 RK1: MR19=303, MR18=111F
9054 11:06:30.306610 CH1_RK1: MR19=0x303, MR18=0x111F, DQSOSC=394, MR23=63, INC=23, DEC=15
9055 11:06:30.309976 [RxdqsGatingPostProcess] freq 1600
9056 11:06:30.315785 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9057 11:06:30.319379 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 11:06:30.322613 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 11:06:30.326033 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 11:06:30.329122 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 11:06:30.332462 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 11:06:30.335684 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 11:06:30.336142 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 11:06:30.338922 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 11:06:30.342556 Pre-setting of DQS Precalculation
9066 11:06:30.348741 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9067 11:06:30.355768 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9068 11:06:30.361851 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 11:06:30.362364
9070 11:06:30.362712
9071 11:06:30.365295 [Calibration Summary] 3200 Mbps
9072 11:06:30.368862 CH 0, Rank 0
9073 11:06:30.369410 SW Impedance : PASS
9074 11:06:30.371628 DUTY Scan : NO K
9075 11:06:30.375429 ZQ Calibration : PASS
9076 11:06:30.375855 Jitter Meter : NO K
9077 11:06:30.378570 CBT Training : PASS
9078 11:06:30.381466 Write leveling : PASS
9079 11:06:30.381870 RX DQS gating : PASS
9080 11:06:30.384803 RX DQ/DQS(RDDQC) : PASS
9081 11:06:30.388186 TX DQ/DQS : PASS
9082 11:06:30.388675 RX DATLAT : PASS
9083 11:06:30.391892 RX DQ/DQS(Engine): PASS
9084 11:06:30.394637 TX OE : PASS
9085 11:06:30.395026 All Pass.
9086 11:06:30.395321
9087 11:06:30.395597 CH 0, Rank 1
9088 11:06:30.398175 SW Impedance : PASS
9089 11:06:30.401193 DUTY Scan : NO K
9090 11:06:30.401576 ZQ Calibration : PASS
9091 11:06:30.404570 Jitter Meter : NO K
9092 11:06:30.407953 CBT Training : PASS
9093 11:06:30.408340 Write leveling : PASS
9094 11:06:30.411265 RX DQS gating : PASS
9095 11:06:30.411650 RX DQ/DQS(RDDQC) : PASS
9096 11:06:30.414496 TX DQ/DQS : PASS
9097 11:06:30.417656 RX DATLAT : PASS
9098 11:06:30.418041 RX DQ/DQS(Engine): PASS
9099 11:06:30.420965 TX OE : PASS
9100 11:06:30.421393 All Pass.
9101 11:06:30.421694
9102 11:06:30.424083 CH 1, Rank 0
9103 11:06:30.424465 SW Impedance : PASS
9104 11:06:30.428258 DUTY Scan : NO K
9105 11:06:30.430964 ZQ Calibration : PASS
9106 11:06:30.431406 Jitter Meter : NO K
9107 11:06:30.434296 CBT Training : PASS
9108 11:06:30.437613 Write leveling : PASS
9109 11:06:30.437999 RX DQS gating : PASS
9110 11:06:30.440930 RX DQ/DQS(RDDQC) : PASS
9111 11:06:30.444407 TX DQ/DQS : PASS
9112 11:06:30.444874 RX DATLAT : PASS
9113 11:06:30.447769 RX DQ/DQS(Engine): PASS
9114 11:06:30.450933 TX OE : PASS
9115 11:06:30.451322 All Pass.
9116 11:06:30.451622
9117 11:06:30.451897 CH 1, Rank 1
9118 11:06:30.453670 SW Impedance : PASS
9119 11:06:30.457293 DUTY Scan : NO K
9120 11:06:30.457794 ZQ Calibration : PASS
9121 11:06:30.460936 Jitter Meter : NO K
9122 11:06:30.464028 CBT Training : PASS
9123 11:06:30.464486 Write leveling : PASS
9124 11:06:30.467277 RX DQS gating : PASS
9125 11:06:30.470262 RX DQ/DQS(RDDQC) : PASS
9126 11:06:30.470645 TX DQ/DQS : PASS
9127 11:06:30.473680 RX DATLAT : PASS
9128 11:06:30.477075 RX DQ/DQS(Engine): PASS
9129 11:06:30.477497 TX OE : PASS
9130 11:06:30.480325 All Pass.
9131 11:06:30.480708
9132 11:06:30.480999 DramC Write-DBI on
9133 11:06:30.483724 PER_BANK_REFRESH: Hybrid Mode
9134 11:06:30.484108 TX_TRACKING: ON
9135 11:06:30.493282 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9136 11:06:30.503081 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9137 11:06:30.510063 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 11:06:30.512921 [FAST_K] Save calibration result to emmc
9139 11:06:30.516891 sync common calibartion params.
9140 11:06:30.517402 sync cbt_mode0:1, 1:1
9141 11:06:30.519579 dram_init: ddr_geometry: 2
9142 11:06:30.523404 dram_init: ddr_geometry: 2
9143 11:06:30.523865 dram_init: ddr_geometry: 2
9144 11:06:30.526645 0:dram_rank_size:100000000
9145 11:06:30.529739 1:dram_rank_size:100000000
9146 11:06:30.536134 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9147 11:06:30.536581 DFS_SHUFFLE_HW_MODE: ON
9148 11:06:30.539628 dramc_set_vcore_voltage set vcore to 725000
9149 11:06:30.543451 Read voltage for 1600, 0
9150 11:06:30.543908 Vio18 = 0
9151 11:06:30.546240 Vcore = 725000
9152 11:06:30.546684 Vdram = 0
9153 11:06:30.547049 Vddq = 0
9154 11:06:30.549343 Vmddr = 0
9155 11:06:30.549728 switch to 3200 Mbps bootup
9156 11:06:30.552699 [DramcRunTimeConfig]
9157 11:06:30.553110 PHYPLL
9158 11:06:30.556257 DPM_CONTROL_AFTERK: ON
9159 11:06:30.556727 PER_BANK_REFRESH: ON
9160 11:06:30.559347 REFRESH_OVERHEAD_REDUCTION: ON
9161 11:06:30.562447 CMD_PICG_NEW_MODE: OFF
9162 11:06:30.562852 XRTWTW_NEW_MODE: ON
9163 11:06:30.566012 XRTRTR_NEW_MODE: ON
9164 11:06:30.566470 TX_TRACKING: ON
9165 11:06:30.569092 RDSEL_TRACKING: OFF
9166 11:06:30.572512 DQS Precalculation for DVFS: ON
9167 11:06:30.572898 RX_TRACKING: OFF
9168 11:06:30.575742 HW_GATING DBG: ON
9169 11:06:30.576126 ZQCS_ENABLE_LP4: ON
9170 11:06:30.579082 RX_PICG_NEW_MODE: ON
9171 11:06:30.579465 TX_PICG_NEW_MODE: ON
9172 11:06:30.582638 ENABLE_RX_DCM_DPHY: ON
9173 11:06:30.586063 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9174 11:06:30.589188 DUMMY_READ_FOR_TRACKING: OFF
9175 11:06:30.592758 !!! SPM_CONTROL_AFTERK: OFF
9176 11:06:30.593318 !!! SPM could not control APHY
9177 11:06:30.595562 IMPEDANCE_TRACKING: ON
9178 11:06:30.595942 TEMP_SENSOR: ON
9179 11:06:30.598870 HW_SAVE_FOR_SR: OFF
9180 11:06:30.602114 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9181 11:06:30.605499 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9182 11:06:30.608740 Read ODT Tracking: ON
9183 11:06:30.609126 Refresh Rate DeBounce: ON
9184 11:06:30.612578 DFS_NO_QUEUE_FLUSH: ON
9185 11:06:30.615315 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9186 11:06:30.618757 ENABLE_DFS_RUNTIME_MRW: OFF
9187 11:06:30.619142 DDR_RESERVE_NEW_MODE: ON
9188 11:06:30.622568 MR_CBT_SWITCH_FREQ: ON
9189 11:06:30.625111 =========================
9190 11:06:30.643131 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9191 11:06:30.646450 dram_init: ddr_geometry: 2
9192 11:06:30.664856 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9193 11:06:30.668471 dram_init: dram init end (result: 0)
9194 11:06:30.674595 DRAM-K: Full calibration passed in 24437 msecs
9195 11:06:30.677718 MRC: failed to locate region type 0.
9196 11:06:30.678102 DRAM rank0 size:0x100000000,
9197 11:06:30.681415 DRAM rank1 size=0x100000000
9198 11:06:30.691098 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9199 11:06:30.697711 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9200 11:06:30.704389 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9201 11:06:30.714230 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9202 11:06:30.714677 DRAM rank0 size:0x100000000,
9203 11:06:30.717413 DRAM rank1 size=0x100000000
9204 11:06:30.717794 CBMEM:
9205 11:06:30.720835 IMD: root @ 0xfffff000 254 entries.
9206 11:06:30.724269 IMD: root @ 0xffffec00 62 entries.
9207 11:06:30.727139 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9208 11:06:30.733673 WARNING: RO_VPD is uninitialized or empty.
9209 11:06:30.737088 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9210 11:06:30.744811 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9211 11:06:30.758018 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9212 11:06:30.769296 BS: romstage times (exec / console): total (unknown) / 23966 ms
9213 11:06:30.769756
9214 11:06:30.770056
9215 11:06:30.778761 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9216 11:06:30.781791 ARM64: Exception handlers installed.
9217 11:06:30.785393 ARM64: Testing exception
9218 11:06:30.788431 ARM64: Done test exception
9219 11:06:30.788813 Enumerating buses...
9220 11:06:30.792143 Show all devs... Before device enumeration.
9221 11:06:30.795082 Root Device: enabled 1
9222 11:06:30.798321 CPU_CLUSTER: 0: enabled 1
9223 11:06:30.798802 CPU: 00: enabled 1
9224 11:06:30.801856 Compare with tree...
9225 11:06:30.802235 Root Device: enabled 1
9226 11:06:30.805071 CPU_CLUSTER: 0: enabled 1
9227 11:06:30.808087 CPU: 00: enabled 1
9228 11:06:30.808504 Root Device scanning...
9229 11:06:30.812330 scan_static_bus for Root Device
9230 11:06:30.815255 CPU_CLUSTER: 0 enabled
9231 11:06:30.818412 scan_static_bus for Root Device done
9232 11:06:30.821491 scan_bus: bus Root Device finished in 8 msecs
9233 11:06:30.821880 done
9234 11:06:30.828737 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9235 11:06:30.831630 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9236 11:06:30.838041 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9237 11:06:30.844745 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9238 11:06:30.845241 Allocating resources...
9239 11:06:30.847822 Reading resources...
9240 11:06:30.851178 Root Device read_resources bus 0 link: 0
9241 11:06:30.854442 DRAM rank0 size:0x100000000,
9242 11:06:30.854897 DRAM rank1 size=0x100000000
9243 11:06:30.861129 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9244 11:06:30.861640 CPU: 00 missing read_resources
9245 11:06:30.867792 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9246 11:06:30.871285 Root Device read_resources bus 0 link: 0 done
9247 11:06:30.874971 Done reading resources.
9248 11:06:30.877813 Show resources in subtree (Root Device)...After reading.
9249 11:06:30.881349 Root Device child on link 0 CPU_CLUSTER: 0
9250 11:06:30.884258 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 11:06:30.894580 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 11:06:30.895048 CPU: 00
9253 11:06:30.900824 Root Device assign_resources, bus 0 link: 0
9254 11:06:30.904111 CPU_CLUSTER: 0 missing set_resources
9255 11:06:30.907191 Root Device assign_resources, bus 0 link: 0 done
9256 11:06:30.907628 Done setting resources.
9257 11:06:30.913921 Show resources in subtree (Root Device)...After assigning values.
9258 11:06:30.917083 Root Device child on link 0 CPU_CLUSTER: 0
9259 11:06:30.923823 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 11:06:30.930440 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 11:06:30.933575 CPU: 00
9262 11:06:30.933956 Done allocating resources.
9263 11:06:30.940221 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9264 11:06:30.940667 Enabling resources...
9265 11:06:30.943830 done.
9266 11:06:30.947242 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9267 11:06:30.949982 Initializing devices...
9268 11:06:30.950446 Root Device init
9269 11:06:30.953794 init hardware done!
9270 11:06:30.954251 0x00000018: ctrlr->caps
9271 11:06:30.956943 52.000 MHz: ctrlr->f_max
9272 11:06:30.959932 0.400 MHz: ctrlr->f_min
9273 11:06:30.963322 0x40ff8080: ctrlr->voltages
9274 11:06:30.963790 sclk: 390625
9275 11:06:30.964091 Bus Width = 1
9276 11:06:30.966385 sclk: 390625
9277 11:06:30.966768 Bus Width = 1
9278 11:06:30.970232 Early init status = 3
9279 11:06:30.972962 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9280 11:06:30.976570 in-header: 03 fc 00 00 01 00 00 00
9281 11:06:30.979657 in-data: 00
9282 11:06:30.983725 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9283 11:06:30.988139 in-header: 03 fd 00 00 00 00 00 00
9284 11:06:30.991400 in-data:
9285 11:06:30.994424 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9286 11:06:30.997646 in-header: 03 fc 00 00 01 00 00 00
9287 11:06:31.001394 in-data: 00
9288 11:06:31.004151 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9289 11:06:31.009108 in-header: 03 fd 00 00 00 00 00 00
9290 11:06:31.012808 in-data:
9291 11:06:31.015715 [SSUSB] Setting up USB HOST controller...
9292 11:06:31.019327 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9293 11:06:31.022333 [SSUSB] phy power-on done.
9294 11:06:31.025589 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9295 11:06:31.032332 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9296 11:06:31.035783 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9297 11:06:31.042517 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9298 11:06:31.049176 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9299 11:06:31.055447 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9300 11:06:31.062235 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9301 11:06:31.068704 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9302 11:06:31.072197 SPM: binary array size = 0x9dc
9303 11:06:31.075339 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9304 11:06:31.081973 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9305 11:06:31.088395 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9306 11:06:31.095451 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9307 11:06:31.098612 configure_display: Starting display init
9308 11:06:31.132708 anx7625_power_on_init: Init interface.
9309 11:06:31.135552 anx7625_disable_pd_protocol: Disabled PD feature.
9310 11:06:31.139091 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9311 11:06:31.166828 anx7625_start_dp_work: Secure OCM version=00
9312 11:06:31.170179 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9313 11:06:31.185319 sp_tx_get_edid_block: EDID Block = 1
9314 11:06:31.287907 Extracted contents:
9315 11:06:31.292170 header: 00 ff ff ff ff ff ff 00
9316 11:06:31.294639 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9317 11:06:31.297536 version: 01 04
9318 11:06:31.301733 basic params: 95 1f 11 78 0a
9319 11:06:31.303949 chroma info: 76 90 94 55 54 90 27 21 50 54
9320 11:06:31.307290 established: 00 00 00
9321 11:06:31.313856 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9322 11:06:31.317653 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9323 11:06:31.324318 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 11:06:31.331193 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9325 11:06:31.337233 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9326 11:06:31.340549 extensions: 00
9327 11:06:31.340998 checksum: fb
9328 11:06:31.341331
9329 11:06:31.343757 Manufacturer: IVO Model 57d Serial Number 0
9330 11:06:31.347496 Made week 0 of 2020
9331 11:06:31.347954 EDID version: 1.4
9332 11:06:31.350481 Digital display
9333 11:06:31.354125 6 bits per primary color channel
9334 11:06:31.354514 DisplayPort interface
9335 11:06:31.356895 Maximum image size: 31 cm x 17 cm
9336 11:06:31.360471 Gamma: 220%
9337 11:06:31.360937 Check DPMS levels
9338 11:06:31.363789 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9339 11:06:31.370758 First detailed timing is preferred timing
9340 11:06:31.371218 Established timings supported:
9341 11:06:31.373276 Standard timings supported:
9342 11:06:31.376839 Detailed timings
9343 11:06:31.379709 Hex of detail: 383680a07038204018303c0035ae10000019
9344 11:06:31.386775 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9345 11:06:31.389985 0780 0798 07c8 0820 hborder 0
9346 11:06:31.393040 0438 043b 0447 0458 vborder 0
9347 11:06:31.396736 -hsync -vsync
9348 11:06:31.397118 Did detailed timing
9349 11:06:31.403327 Hex of detail: 000000000000000000000000000000000000
9350 11:06:31.406110 Manufacturer-specified data, tag 0
9351 11:06:31.409621 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9352 11:06:31.412943 ASCII string: InfoVision
9353 11:06:31.416108 Hex of detail: 000000fe00523134304e574635205248200a
9354 11:06:31.419538 ASCII string: R140NWF5 RH
9355 11:06:31.419975 Checksum
9356 11:06:31.422953 Checksum: 0xfb (valid)
9357 11:06:31.426097 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9358 11:06:31.429523 DSI data_rate: 832800000 bps
9359 11:06:31.436414 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9360 11:06:31.439458 anx7625_parse_edid: pixelclock(138800).
9361 11:06:31.443023 hactive(1920), hsync(48), hfp(24), hbp(88)
9362 11:06:31.446247 vactive(1080), vsync(12), vfp(3), vbp(17)
9363 11:06:31.449558 anx7625_dsi_config: config dsi.
9364 11:06:31.455875 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9365 11:06:31.469896 anx7625_dsi_config: success to config DSI
9366 11:06:31.473185 anx7625_dp_start: MIPI phy setup OK.
9367 11:06:31.476101 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9368 11:06:31.479987 mtk_ddp_mode_set invalid vrefresh 60
9369 11:06:31.482940 main_disp_path_setup
9370 11:06:31.483318 ovl_layer_smi_id_en
9371 11:06:31.486260 ovl_layer_smi_id_en
9372 11:06:31.486632 ccorr_config
9373 11:06:31.486920 aal_config
9374 11:06:31.490250 gamma_config
9375 11:06:31.490624 postmask_config
9376 11:06:31.492523 dither_config
9377 11:06:31.496184 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9378 11:06:31.502548 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9379 11:06:31.506102 Root Device init finished in 551 msecs
9380 11:06:31.509215 CPU_CLUSTER: 0 init
9381 11:06:31.516020 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9382 11:06:31.519208 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9383 11:06:31.522615 APU_MBOX 0x190000b0 = 0x10001
9384 11:06:31.525889 APU_MBOX 0x190001b0 = 0x10001
9385 11:06:31.529170 APU_MBOX 0x190005b0 = 0x10001
9386 11:06:31.532531 APU_MBOX 0x190006b0 = 0x10001
9387 11:06:31.536027 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9388 11:06:31.548641 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9389 11:06:31.561235 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9390 11:06:31.568039 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9391 11:06:31.579085 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9392 11:06:31.588330 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9393 11:06:31.592436 CPU_CLUSTER: 0 init finished in 81 msecs
9394 11:06:31.595266 Devices initialized
9395 11:06:31.598436 Show all devs... After init.
9396 11:06:31.598897 Root Device: enabled 1
9397 11:06:31.601822 CPU_CLUSTER: 0: enabled 1
9398 11:06:31.605476 CPU: 00: enabled 1
9399 11:06:31.608327 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9400 11:06:31.612050 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9401 11:06:31.614272 ELOG: NV offset 0x57f000 size 0x1000
9402 11:06:31.621237 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9403 11:06:31.628118 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9404 11:06:31.631560 ELOG: Event(17) added with size 13 at 2024-07-10 11:06:31 UTC
9405 11:06:31.638480 ELOG: Event(16) added with size 11 at 2024-07-10 11:06:31 UTC
9406 11:06:31.720155 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9407 11:06:31.723594 out: cmd=0x121: 03 db 21 01 00 00 00 00
9408 11:06:31.726268 in-header: 03 9e 00 00 2c 00 00 00
9409 11:06:31.740091 in-data: 9f 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9410 11:06:31.745966 ELOG: Event(A1) added with size 10 at 2024-07-10 11:06:31 UTC
9411 11:06:31.752809 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9412 11:06:31.756176 ELOG: Event(A0) added with size 9 at 2024-07-10 11:06:31 UTC
9413 11:06:31.762698 elog_add_boot_reason: Logged dev mode boot
9414 11:06:31.766040 BS: BS_POST_DEVICE entry times (exec / console): 79 / 74 ms
9415 11:06:31.769188 Finalize devices...
9416 11:06:31.769577 Devices finalized
9417 11:06:31.775955 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9418 11:06:31.779005 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9419 11:06:31.782822 in-header: 03 07 00 00 08 00 00 00
9420 11:06:31.785677 in-data: aa e4 47 04 13 02 00 00
9421 11:06:31.789024 Chrome EC: UHEPI supported
9422 11:06:31.795338 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9423 11:06:31.798765 in-header: 03 a9 00 00 08 00 00 00
9424 11:06:31.802317 in-data: 84 60 60 08 00 00 00 00
9425 11:06:31.806050 ELOG: Event(91) added with size 10 at 2024-07-10 11:06:31 UTC
9426 11:06:31.812029 Chrome EC: clear events_b mask to 0x0000000020004000
9427 11:06:31.818990 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9428 11:06:31.822587 in-header: 03 fd 00 00 00 00 00 00
9429 11:06:31.822971 in-data:
9430 11:06:31.828579 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9431 11:06:31.832234 Writing coreboot table at 0xffe64000
9432 11:06:31.835843 0. 000000000010a000-0000000000113fff: RAMSTAGE
9433 11:06:31.838594 1. 0000000040000000-00000000400fffff: RAM
9434 11:06:31.846113 2. 0000000040100000-000000004032afff: RAMSTAGE
9435 11:06:31.848232 3. 000000004032b000-00000000545fffff: RAM
9436 11:06:31.852185 4. 0000000054600000-000000005465ffff: BL31
9437 11:06:31.855051 5. 0000000054660000-00000000ffe63fff: RAM
9438 11:06:31.862150 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9439 11:06:31.864793 7. 0000000100000000-000000023fffffff: RAM
9440 11:06:31.867882 Passing 5 GPIOs to payload:
9441 11:06:31.871796 NAME | PORT | POLARITY | VALUE
9442 11:06:31.874602 EC in RW | 0x000000aa | low | undefined
9443 11:06:31.881420 EC interrupt | 0x00000005 | low | undefined
9444 11:06:31.884423 TPM interrupt | 0x000000ab | high | undefined
9445 11:06:31.891415 SD card detect | 0x00000011 | high | undefined
9446 11:06:31.894487 speaker enable | 0x00000093 | high | undefined
9447 11:06:31.898042 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9448 11:06:31.901016 in-header: 03 f9 00 00 02 00 00 00
9449 11:06:31.904478 in-data: 02 00
9450 11:06:31.904932 ADC[4]: Raw value=902955 ID=7
9451 11:06:31.907104 ADC[3]: Raw value=213546 ID=1
9452 11:06:31.911008 RAM Code: 0x71
9453 11:06:31.914130 ADC[6]: Raw value=74630 ID=0
9454 11:06:31.914510 ADC[5]: Raw value=213177 ID=1
9455 11:06:31.916919 SKU Code: 0x1
9456 11:06:31.920483 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7908
9457 11:06:31.923659 coreboot table: 964 bytes.
9458 11:06:31.927028 IMD ROOT 0. 0xfffff000 0x00001000
9459 11:06:31.931575 IMD SMALL 1. 0xffffe000 0x00001000
9460 11:06:31.933615 RO MCACHE 2. 0xffffc000 0x00001104
9461 11:06:31.937179 CONSOLE 3. 0xfff7c000 0x00080000
9462 11:06:31.940909 FMAP 4. 0xfff7b000 0x00000452
9463 11:06:31.943784 TIME STAMP 5. 0xfff7a000 0x00000910
9464 11:06:31.947090 VBOOT WORK 6. 0xfff66000 0x00014000
9465 11:06:31.950530 RAMOOPS 7. 0xffe66000 0x00100000
9466 11:06:31.953614 COREBOOT 8. 0xffe64000 0x00002000
9467 11:06:31.957286 IMD small region:
9468 11:06:31.959959 IMD ROOT 0. 0xffffec00 0x00000400
9469 11:06:31.963590 VPD 1. 0xffffeb80 0x0000006c
9470 11:06:31.966768 MMC STATUS 2. 0xffffeb60 0x00000004
9471 11:06:31.969922 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9472 11:06:31.977012 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9473 11:06:32.017699 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9474 11:06:32.021193 Checking segment from ROM address 0x40100000
9475 11:06:32.024639 Checking segment from ROM address 0x4010001c
9476 11:06:32.031019 Loading segment from ROM address 0x40100000
9477 11:06:32.031466 code (compression=0)
9478 11:06:32.040490 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9479 11:06:32.047620 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9480 11:06:32.048102 it's not compressed!
9481 11:06:32.054422 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9482 11:06:32.060424 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9483 11:06:32.078056 Loading segment from ROM address 0x4010001c
9484 11:06:32.078514 Entry Point 0x80000000
9485 11:06:32.081765 Loaded segments
9486 11:06:32.084421 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9487 11:06:32.091285 Jumping to boot code at 0x80000000(0xffe64000)
9488 11:06:32.097794 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9489 11:06:32.104412 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9490 11:06:32.112121 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9491 11:06:32.115483 Checking segment from ROM address 0x40100000
9492 11:06:32.119787 Checking segment from ROM address 0x4010001c
9493 11:06:32.125488 Loading segment from ROM address 0x40100000
9494 11:06:32.125947 code (compression=1)
9495 11:06:32.132022 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9496 11:06:32.142498 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9497 11:06:32.142962 using LZMA
9498 11:06:32.150599 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9499 11:06:32.157257 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9500 11:06:32.161088 Loading segment from ROM address 0x4010001c
9501 11:06:32.161509 Entry Point 0x54601000
9502 11:06:32.164305 Loaded segments
9503 11:06:32.167543 NOTICE: MT8192 bl31_setup
9504 11:06:32.174067 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9505 11:06:32.177507 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9506 11:06:32.180991 WARNING: region 0:
9507 11:06:32.184193 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 11:06:32.184575 WARNING: region 1:
9509 11:06:32.190523 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9510 11:06:32.193874 WARNING: region 2:
9511 11:06:32.197088 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9512 11:06:32.200513 WARNING: region 3:
9513 11:06:32.207073 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9514 11:06:32.207461 WARNING: region 4:
9515 11:06:32.213680 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9516 11:06:32.214067 WARNING: region 5:
9517 11:06:32.217096 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 11:06:32.219962 WARNING: region 6:
9519 11:06:32.223362 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9520 11:06:32.227218 WARNING: region 7:
9521 11:06:32.229820 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 11:06:32.236902 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9523 11:06:32.240333 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9524 11:06:32.246587 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9525 11:06:32.249874 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9526 11:06:32.253096 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9527 11:06:32.259847 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9528 11:06:32.263327 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9529 11:06:32.269915 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9530 11:06:32.272852 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9531 11:06:32.276144 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9532 11:06:32.282652 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9533 11:06:32.286034 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9534 11:06:32.292291 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9535 11:06:32.296485 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9536 11:06:32.299402 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9537 11:06:32.305675 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9538 11:06:32.308884 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9539 11:06:32.312206 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9540 11:06:32.318922 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9541 11:06:32.321959 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9542 11:06:32.328836 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9543 11:06:32.332393 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9544 11:06:32.335623 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9545 11:06:32.342301 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9546 11:06:32.345035 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9547 11:06:32.352087 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9548 11:06:32.355491 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9549 11:06:32.359346 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9550 11:06:32.365643 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9551 11:06:32.368417 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9552 11:06:32.375185 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9553 11:06:32.378315 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9554 11:06:32.381907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9555 11:06:32.388569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9556 11:06:32.391433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9557 11:06:32.394821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9558 11:06:32.398471 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9559 11:06:32.405013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9560 11:06:32.408401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9561 11:06:32.411476 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9562 11:06:32.414661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9563 11:06:32.421495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9564 11:06:32.424812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9565 11:06:32.428176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9566 11:06:32.431451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9567 11:06:32.437678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9568 11:06:32.441352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9569 11:06:32.444674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9570 11:06:32.451104 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9571 11:06:32.454700 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9572 11:06:32.460865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9573 11:06:32.464314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9574 11:06:32.467484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9575 11:06:32.474267 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9576 11:06:32.477807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9577 11:06:32.483806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9578 11:06:32.487363 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9579 11:06:32.493928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9580 11:06:32.497469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9581 11:06:32.504126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9582 11:06:32.507224 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9583 11:06:32.513680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9584 11:06:32.516831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9585 11:06:32.520218 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9586 11:06:32.526991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9587 11:06:32.529939 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9588 11:06:32.536335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9589 11:06:32.539942 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9590 11:06:32.547349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9591 11:06:32.549456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9592 11:06:32.556255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9593 11:06:32.559858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9594 11:06:32.562828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9595 11:06:32.569246 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9596 11:06:32.572745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9597 11:06:32.580283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9598 11:06:32.582456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9599 11:06:32.589285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9600 11:06:32.592424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9601 11:06:32.599044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9602 11:06:32.602264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9603 11:06:32.609342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9604 11:06:32.612413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9605 11:06:32.615626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9606 11:06:32.622087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9607 11:06:32.625414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9608 11:06:32.632222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9609 11:06:32.635433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9610 11:06:32.641673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9611 11:06:32.645226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9612 11:06:32.651695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9613 11:06:32.655363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9614 11:06:32.658141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9615 11:06:32.665202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9616 11:06:32.668453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9617 11:06:32.674903 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9618 11:06:32.678078 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9619 11:06:32.682078 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9620 11:06:32.688416 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9621 11:06:32.691786 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9622 11:06:32.694782 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9623 11:06:32.701067 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9624 11:06:32.704457 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9625 11:06:32.707924 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9626 11:06:32.714390 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9627 11:06:32.718068 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9628 11:06:32.723999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9629 11:06:32.727708 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9630 11:06:32.730869 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9631 11:06:32.737623 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9632 11:06:32.740680 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9633 11:06:32.747339 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9634 11:06:32.750575 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9635 11:06:32.757157 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9636 11:06:32.761316 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9637 11:06:32.763701 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9638 11:06:32.767181 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9639 11:06:32.773535 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9640 11:06:32.776843 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9641 11:06:32.783424 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9642 11:06:32.786615 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9643 11:06:32.790525 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9644 11:06:32.793705 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9645 11:06:32.800335 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9646 11:06:32.803212 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9647 11:06:32.806692 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9648 11:06:32.813255 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9649 11:06:32.816757 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9650 11:06:32.823328 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9651 11:06:32.826707 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9652 11:06:32.829767 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9653 11:06:32.836507 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9654 11:06:32.839792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9655 11:06:32.846377 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9656 11:06:32.850049 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9657 11:06:32.853177 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9658 11:06:32.859592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9659 11:06:32.862822 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9660 11:06:32.869726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9661 11:06:32.872619 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9662 11:06:32.875693 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9663 11:06:32.882330 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9664 11:06:32.886040 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9665 11:06:32.892544 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9666 11:06:32.895871 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9667 11:06:32.899092 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9668 11:06:32.906105 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9669 11:06:32.908874 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9670 11:06:32.915629 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9671 11:06:32.918684 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9672 11:06:32.922390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9673 11:06:32.929381 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9674 11:06:32.932293 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9675 11:06:32.938538 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9676 11:06:32.941624 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9677 11:06:32.945564 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9678 11:06:32.952067 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9679 11:06:32.956394 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9680 11:06:32.961832 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9681 11:06:32.965487 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9682 11:06:32.968222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9683 11:06:32.975536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9684 11:06:32.978139 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9685 11:06:32.985076 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9686 11:06:32.987684 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9687 11:06:32.991232 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9688 11:06:32.998398 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9689 11:06:33.000853 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9690 11:06:33.007710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9691 11:06:33.010844 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9692 11:06:33.014152 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9693 11:06:33.021330 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9694 11:06:33.024148 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9695 11:06:33.030749 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9696 11:06:33.034598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9697 11:06:33.037339 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9698 11:06:33.044316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9699 11:06:33.047867 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9700 11:06:33.054416 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9701 11:06:33.056964 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9702 11:06:33.060566 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9703 11:06:33.067271 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9704 11:06:33.070776 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9705 11:06:33.077071 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9706 11:06:33.079913 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9707 11:06:33.083734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9708 11:06:33.090303 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9709 11:06:33.093886 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9710 11:06:33.100019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9711 11:06:33.103407 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9712 11:06:33.106785 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9713 11:06:33.113045 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9714 11:06:33.116483 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9715 11:06:33.123349 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9716 11:06:33.126648 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9717 11:06:33.133552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9718 11:06:33.136744 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9719 11:06:33.140582 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9720 11:06:33.146421 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9721 11:06:33.149776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9722 11:06:33.156412 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9723 11:06:33.159686 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9724 11:06:33.165965 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9725 11:06:33.169235 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9726 11:06:33.172646 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9727 11:06:33.178948 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9728 11:06:33.182983 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9729 11:06:33.188900 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9730 11:06:33.192185 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9731 11:06:33.198944 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9732 11:06:33.202895 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9733 11:06:33.205383 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9734 11:06:33.212144 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9735 11:06:33.215502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9736 11:06:33.221913 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9737 11:06:33.225017 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9738 11:06:33.231951 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9739 11:06:33.235369 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9740 11:06:33.239235 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9741 11:06:33.245097 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9742 11:06:33.248088 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9743 11:06:33.255006 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9744 11:06:33.258023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9745 11:06:33.264995 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9746 11:06:33.267842 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9747 11:06:33.271863 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9748 11:06:33.278145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9749 11:06:33.281333 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9750 11:06:33.287834 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9751 11:06:33.291381 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9752 11:06:33.294601 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9753 11:06:33.297890 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9754 11:06:33.304164 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9755 11:06:33.307850 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9756 11:06:33.311139 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9757 11:06:33.317737 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9758 11:06:33.320725 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9759 11:06:33.324398 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9760 11:06:33.330580 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9761 11:06:33.333992 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9762 11:06:33.340446 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9763 11:06:33.343748 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9764 11:06:33.347763 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9765 11:06:33.353773 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9766 11:06:33.357495 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9767 11:06:33.360955 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9768 11:06:33.366895 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9769 11:06:33.371185 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9770 11:06:33.374311 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9771 11:06:33.380036 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9772 11:06:33.383797 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9773 11:06:33.390337 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9774 11:06:33.393217 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9775 11:06:33.396830 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9776 11:06:33.403562 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9777 11:06:33.406455 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9778 11:06:33.413400 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9779 11:06:33.416657 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9780 11:06:33.419749 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9781 11:06:33.426956 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9782 11:06:33.429746 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9783 11:06:33.433657 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9784 11:06:33.439954 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9785 11:06:33.442994 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9786 11:06:33.446108 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9787 11:06:33.452913 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9788 11:06:33.456358 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9789 11:06:33.462603 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9790 11:06:33.466060 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9791 11:06:33.469954 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9792 11:06:33.472526 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9793 11:06:33.479542 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9794 11:06:33.482931 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9795 11:06:33.486647 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9796 11:06:33.489329 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9797 11:06:33.493186 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9798 11:06:33.499504 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9799 11:06:33.502582 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9800 11:06:33.506317 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9801 11:06:33.509350 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9802 11:06:33.516146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9803 11:06:33.519224 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9804 11:06:33.525817 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9805 11:06:33.529112 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9806 11:06:33.532250 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9807 11:06:33.538766 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9808 11:06:33.542635 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9809 11:06:33.548616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9810 11:06:33.551924 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9811 11:06:33.555419 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9812 11:06:33.561628 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9813 11:06:33.565435 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9814 11:06:33.572035 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9815 11:06:33.575667 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9816 11:06:33.581598 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9817 11:06:33.585203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9818 11:06:33.591807 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9819 11:06:33.595154 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9820 11:06:33.598745 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9821 11:06:33.604588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9822 11:06:33.608448 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9823 11:06:33.615031 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9824 11:06:33.618088 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9825 11:06:33.620976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9826 11:06:33.628175 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9827 11:06:33.631389 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9828 11:06:33.638052 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9829 11:06:33.641376 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9830 11:06:33.644404 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9831 11:06:33.651023 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9832 11:06:33.654290 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9833 11:06:33.660865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9834 11:06:33.664283 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9835 11:06:33.670779 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9836 11:06:33.673804 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9837 11:06:33.677117 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9838 11:06:33.683744 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9839 11:06:33.687388 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9840 11:06:33.693592 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9841 11:06:33.697019 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9842 11:06:33.704022 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9843 11:06:33.707051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9844 11:06:33.710468 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9845 11:06:33.717603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9846 11:06:33.720363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9847 11:06:33.726574 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9848 11:06:33.730170 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9849 11:06:33.733537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9850 11:06:33.739762 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9851 11:06:33.743171 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9852 11:06:33.749981 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9853 11:06:33.753117 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9854 11:06:33.759923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9855 11:06:33.763228 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9856 11:06:33.766644 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9857 11:06:33.772705 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9858 11:06:33.776529 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9859 11:06:33.782533 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9860 11:06:33.786022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9861 11:06:33.789809 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9862 11:06:33.795935 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9863 11:06:33.799180 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9864 11:06:33.805550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9865 11:06:33.809051 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9866 11:06:33.815426 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9867 11:06:33.818624 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9868 11:06:33.823632 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9869 11:06:33.829045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9870 11:06:33.832250 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9871 11:06:33.838634 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9872 11:06:33.841911 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9873 11:06:33.848172 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9874 11:06:33.852323 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9875 11:06:33.855029 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9876 11:06:33.861157 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9877 11:06:33.865112 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9878 11:06:33.871381 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9879 11:06:33.874637 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9880 11:06:33.881105 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9881 11:06:33.884306 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9882 11:06:33.887757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9883 11:06:33.894791 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9884 11:06:33.897733 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9885 11:06:33.905071 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9886 11:06:33.907604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9887 11:06:33.914271 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9888 11:06:33.917331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9889 11:06:33.924055 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9890 11:06:33.927436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9891 11:06:33.930648 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9892 11:06:33.937479 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9893 11:06:33.940625 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9894 11:06:33.947110 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9895 11:06:33.950145 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9896 11:06:33.956939 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9897 11:06:33.960162 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9898 11:06:33.966895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9899 11:06:33.970596 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9900 11:06:33.973465 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9901 11:06:33.979940 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9902 11:06:33.983560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9903 11:06:33.989764 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9904 11:06:33.993169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9905 11:06:33.999483 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9906 11:06:34.003097 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9907 11:06:34.009440 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9908 11:06:34.012881 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9909 11:06:34.016430 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9910 11:06:34.022861 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9911 11:06:34.026142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9912 11:06:34.032932 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9913 11:06:34.036455 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9914 11:06:34.042751 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9915 11:06:34.046292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9916 11:06:34.052799 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9917 11:06:34.056407 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9918 11:06:34.059258 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9919 11:06:34.066209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9920 11:06:34.069053 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9921 11:06:34.076026 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9922 11:06:34.079605 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9923 11:06:34.085974 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9924 11:06:34.089073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9925 11:06:34.092152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9926 11:06:34.099175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9927 11:06:34.102794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9928 11:06:34.108822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9929 11:06:34.113066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9930 11:06:34.118663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9931 11:06:34.122205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9932 11:06:34.128596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9933 11:06:34.132089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9934 11:06:34.138925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9935 11:06:34.141765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9936 11:06:34.148600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9937 11:06:34.151598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9938 11:06:34.158308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9939 11:06:34.161576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9940 11:06:34.168250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9941 11:06:34.171377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9942 11:06:34.178107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9943 11:06:34.181706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9944 11:06:34.188213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9945 11:06:34.191374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9946 11:06:34.197878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9947 11:06:34.201305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9948 11:06:34.207959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9949 11:06:34.210856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9950 11:06:34.217424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9951 11:06:34.220880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9952 11:06:34.227808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9953 11:06:34.230620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9954 11:06:34.237297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9955 11:06:34.240748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9956 11:06:34.247358 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9957 11:06:34.247827 INFO: [APUAPC] vio 0
9958 11:06:34.254540 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9959 11:06:34.257341 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9960 11:06:34.260539 INFO: [APUAPC] D0_APC_0: 0x400510
9961 11:06:34.263945 INFO: [APUAPC] D0_APC_1: 0x0
9962 11:06:34.268068 INFO: [APUAPC] D0_APC_2: 0x1540
9963 11:06:34.271252 INFO: [APUAPC] D0_APC_3: 0x0
9964 11:06:34.274384 INFO: [APUAPC] D1_APC_0: 0xffffffff
9965 11:06:34.277580 INFO: [APUAPC] D1_APC_1: 0xffffffff
9966 11:06:34.281278 INFO: [APUAPC] D1_APC_2: 0x3fffff
9967 11:06:34.283787 INFO: [APUAPC] D1_APC_3: 0x0
9968 11:06:34.287332 INFO: [APUAPC] D2_APC_0: 0xffffffff
9969 11:06:34.290552 INFO: [APUAPC] D2_APC_1: 0xffffffff
9970 11:06:34.293557 INFO: [APUAPC] D2_APC_2: 0x3fffff
9971 11:06:34.296804 INFO: [APUAPC] D2_APC_3: 0x0
9972 11:06:34.300169 INFO: [APUAPC] D3_APC_0: 0xffffffff
9973 11:06:34.303507 INFO: [APUAPC] D3_APC_1: 0xffffffff
9974 11:06:34.307290 INFO: [APUAPC] D3_APC_2: 0x3fffff
9975 11:06:34.310433 INFO: [APUAPC] D3_APC_3: 0x0
9976 11:06:34.313295 INFO: [APUAPC] D4_APC_0: 0xffffffff
9977 11:06:34.316735 INFO: [APUAPC] D4_APC_1: 0xffffffff
9978 11:06:34.320123 INFO: [APUAPC] D4_APC_2: 0x3fffff
9979 11:06:34.323457 INFO: [APUAPC] D4_APC_3: 0x0
9980 11:06:34.326481 INFO: [APUAPC] D5_APC_0: 0xffffffff
9981 11:06:34.330117 INFO: [APUAPC] D5_APC_1: 0xffffffff
9982 11:06:34.333369 INFO: [APUAPC] D5_APC_2: 0x3fffff
9983 11:06:34.336568 INFO: [APUAPC] D5_APC_3: 0x0
9984 11:06:34.339842 INFO: [APUAPC] D6_APC_0: 0xffffffff
9985 11:06:34.343343 INFO: [APUAPC] D6_APC_1: 0xffffffff
9986 11:06:34.347139 INFO: [APUAPC] D6_APC_2: 0x3fffff
9987 11:06:34.347598 INFO: [APUAPC] D6_APC_3: 0x0
9988 11:06:34.353045 INFO: [APUAPC] D7_APC_0: 0xffffffff
9989 11:06:34.356847 INFO: [APUAPC] D7_APC_1: 0xffffffff
9990 11:06:34.360199 INFO: [APUAPC] D7_APC_2: 0x3fffff
9991 11:06:34.360688 INFO: [APUAPC] D7_APC_3: 0x0
9992 11:06:34.363018 INFO: [APUAPC] D8_APC_0: 0xffffffff
9993 11:06:34.369516 INFO: [APUAPC] D8_APC_1: 0xffffffff
9994 11:06:34.373213 INFO: [APUAPC] D8_APC_2: 0x3fffff
9995 11:06:34.373689 INFO: [APUAPC] D8_APC_3: 0x0
9996 11:06:34.376772 INFO: [APUAPC] D9_APC_0: 0xffffffff
9997 11:06:34.380155 INFO: [APUAPC] D9_APC_1: 0xffffffff
9998 11:06:34.382520 INFO: [APUAPC] D9_APC_2: 0x3fffff
9999 11:06:34.385858 INFO: [APUAPC] D9_APC_3: 0x0
10000 11:06:34.389464 INFO: [APUAPC] D10_APC_0: 0xffffffff
10001 11:06:34.392890 INFO: [APUAPC] D10_APC_1: 0xffffffff
10002 11:06:34.399278 INFO: [APUAPC] D10_APC_2: 0x3fffff
10003 11:06:34.399708 INFO: [APUAPC] D10_APC_3: 0x0
10004 11:06:34.402696 INFO: [APUAPC] D11_APC_0: 0xffffffff
10005 11:06:34.409227 INFO: [APUAPC] D11_APC_1: 0xffffffff
10006 11:06:34.413317 INFO: [APUAPC] D11_APC_2: 0x3fffff
10007 11:06:34.413817 INFO: [APUAPC] D11_APC_3: 0x0
10008 11:06:34.418952 INFO: [APUAPC] D12_APC_0: 0xffffffff
10009 11:06:34.422300 INFO: [APUAPC] D12_APC_1: 0xffffffff
10010 11:06:34.425678 INFO: [APUAPC] D12_APC_2: 0x3fffff
10011 11:06:34.426253 INFO: [APUAPC] D12_APC_3: 0x0
10012 11:06:34.432447 INFO: [APUAPC] D13_APC_0: 0xffffffff
10013 11:06:34.435792 INFO: [APUAPC] D13_APC_1: 0xffffffff
10014 11:06:34.438707 INFO: [APUAPC] D13_APC_2: 0x3fffff
10015 11:06:34.442074 INFO: [APUAPC] D13_APC_3: 0x0
10016 11:06:34.445313 INFO: [APUAPC] D14_APC_0: 0xffffffff
10017 11:06:34.448435 INFO: [APUAPC] D14_APC_1: 0xffffffff
10018 11:06:34.452537 INFO: [APUAPC] D14_APC_2: 0x3fffff
10019 11:06:34.455115 INFO: [APUAPC] D14_APC_3: 0x0
10020 11:06:34.459159 INFO: [APUAPC] D15_APC_0: 0xffffffff
10021 11:06:34.461757 INFO: [APUAPC] D15_APC_1: 0xffffffff
10022 11:06:34.465486 INFO: [APUAPC] D15_APC_2: 0x3fffff
10023 11:06:34.468533 INFO: [APUAPC] D15_APC_3: 0x0
10024 11:06:34.471688 INFO: [APUAPC] APC_CON: 0x4
10025 11:06:34.472110 INFO: [NOCDAPC] D0_APC_0: 0x0
10026 11:06:34.475134 INFO: [NOCDAPC] D0_APC_1: 0x0
10027 11:06:34.478320 INFO: [NOCDAPC] D1_APC_0: 0x0
10028 11:06:34.481622 INFO: [NOCDAPC] D1_APC_1: 0xfff
10029 11:06:34.484941 INFO: [NOCDAPC] D2_APC_0: 0x0
10030 11:06:34.488733 INFO: [NOCDAPC] D2_APC_1: 0xfff
10031 11:06:34.491511 INFO: [NOCDAPC] D3_APC_0: 0x0
10032 11:06:34.494781 INFO: [NOCDAPC] D3_APC_1: 0xfff
10033 11:06:34.498317 INFO: [NOCDAPC] D4_APC_0: 0x0
10034 11:06:34.502177 INFO: [NOCDAPC] D4_APC_1: 0xfff
10035 11:06:34.502657 INFO: [NOCDAPC] D5_APC_0: 0x0
10036 11:06:34.504586 INFO: [NOCDAPC] D5_APC_1: 0xfff
10037 11:06:34.508779 INFO: [NOCDAPC] D6_APC_0: 0x0
10038 11:06:34.511786 INFO: [NOCDAPC] D6_APC_1: 0xfff
10039 11:06:34.514944 INFO: [NOCDAPC] D7_APC_0: 0x0
10040 11:06:34.517926 INFO: [NOCDAPC] D7_APC_1: 0xfff
10041 11:06:34.521318 INFO: [NOCDAPC] D8_APC_0: 0x0
10042 11:06:34.524308 INFO: [NOCDAPC] D8_APC_1: 0xfff
10043 11:06:34.528174 INFO: [NOCDAPC] D9_APC_0: 0x0
10044 11:06:34.531133 INFO: [NOCDAPC] D9_APC_1: 0xfff
10045 11:06:34.534550 INFO: [NOCDAPC] D10_APC_0: 0x0
10046 11:06:34.537587 INFO: [NOCDAPC] D10_APC_1: 0xfff
10047 11:06:34.541058 INFO: [NOCDAPC] D11_APC_0: 0x0
10048 11:06:34.541579 INFO: [NOCDAPC] D11_APC_1: 0xfff
10049 11:06:34.544712 INFO: [NOCDAPC] D12_APC_0: 0x0
10050 11:06:34.547604 INFO: [NOCDAPC] D12_APC_1: 0xfff
10051 11:06:34.550646 INFO: [NOCDAPC] D13_APC_0: 0x0
10052 11:06:34.554055 INFO: [NOCDAPC] D13_APC_1: 0xfff
10053 11:06:34.557597 INFO: [NOCDAPC] D14_APC_0: 0x0
10054 11:06:34.560855 INFO: [NOCDAPC] D14_APC_1: 0xfff
10055 11:06:34.564114 INFO: [NOCDAPC] D15_APC_0: 0x0
10056 11:06:34.567882 INFO: [NOCDAPC] D15_APC_1: 0xfff
10057 11:06:34.570910 INFO: [NOCDAPC] APC_CON: 0x4
10058 11:06:34.574109 INFO: [APUAPC] set_apusys_apc done
10059 11:06:34.577126 INFO: [DEVAPC] devapc_init done
10060 11:06:34.580467 INFO: GICv3 without legacy support detected.
10061 11:06:34.583766 INFO: ARM GICv3 driver initialized in EL3
10062 11:06:34.587350 INFO: Maximum SPI INTID supported: 639
10063 11:06:34.593647 INFO: BL31: Initializing runtime services
10064 11:06:34.597022 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10065 11:06:34.600506 INFO: SPM: enable CPC mode
10066 11:06:34.606554 INFO: mcdi ready for mcusys-off-idle and system suspend
10067 11:06:34.610339 INFO: BL31: Preparing for EL3 exit to normal world
10068 11:06:34.613031 INFO: Entry point address = 0x80000000
10069 11:06:34.616326 INFO: SPSR = 0x8
10070 11:06:34.622459
10071 11:06:34.622910
10072 11:06:34.623207
10073 11:06:34.626371 Starting depthcharge on Spherion...
10074 11:06:34.626903
10075 11:06:34.627234 Wipe memory regions:
10076 11:06:34.627516
10077 11:06:34.629896 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10078 11:06:34.630371 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10079 11:06:34.630734 Setting prompt string to ['asurada:']
10080 11:06:34.631055 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10081 11:06:34.631625 [0x00000040000000, 0x00000054600000)
10082 11:06:34.750033
10083 11:06:34.750652 [0x00000054660000, 0x00000080000000)
10084 11:06:35.011125
10085 11:06:35.011618 [0x000000821a7280, 0x000000ffe64000)
10086 11:06:35.755403
10087 11:06:35.755854 [0x00000100000000, 0x00000240000000)
10088 11:06:37.645296
10089 11:06:37.648628 Initializing XHCI USB controller at 0x11200000.
10090 11:06:38.686919
10091 11:06:38.690594 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10092 11:06:38.691012
10093 11:06:38.691318
10094 11:06:38.692000 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10095 11:06:38.692384 Sending line: 'tftpboot 192.168.201.1 14786840/tftp-deploy-vj02v5np/kernel/image.itb 14786840/tftp-deploy-vj02v5np/kernel/cmdline '
10097 11:06:38.793907 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10098 11:06:38.794316 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10099 11:06:38.798829 asurada: tftpboot 192.168.201.1 14786840/tftp-deploy-vj02v5np/kernel/image.ittp-deploy-vj02v5np/kernel/cmdline
10100 11:06:38.799372
10101 11:06:38.799709 Waiting for link
10102 11:06:38.957264
10103 11:06:38.957719 R8152: Initializing
10104 11:06:38.958021
10105 11:06:38.960569 Version 6 (ocp_data = 5c30)
10106 11:06:38.961037
10107 11:06:38.963694 R8152: Done initializing
10108 11:06:38.964164
10109 11:06:38.964474 Adding net device
10110 11:06:40.928255
10111 11:06:40.928869 done.
10112 11:06:40.929466
10113 11:06:40.929806 MAC: 00:24:32:30:7c:7b
10114 11:06:40.930112
10115 11:06:40.931324 Sending DHCP discover... done.
10116 11:06:40.931748
10117 11:06:40.934555 Waiting for reply... done.
10118 11:06:40.935070
10119 11:06:40.937812 Sending DHCP request... done.
10120 11:06:40.938222
10121 11:06:40.938705 Waiting for reply... done.
10122 11:06:40.939009
10123 11:06:40.941029 My ip is 192.168.201.14
10124 11:06:40.941466
10125 11:06:40.944399 The DHCP server ip is 192.168.201.1
10126 11:06:40.944780
10127 11:06:40.947916 TFTP server IP predefined by user: 192.168.201.1
10128 11:06:40.948384
10129 11:06:40.954173 Bootfile predefined by user: 14786840/tftp-deploy-vj02v5np/kernel/image.itb
10130 11:06:40.954623
10131 11:06:40.957591 Sending tftp read request... done.
10132 11:06:40.957971
10133 11:06:40.967960 Waiting for the transfer...
10134 11:06:40.968338
10135 11:06:41.678566 00000000 ################################################################
10136 11:06:41.679053
10137 11:06:42.380011 00080000 ################################################################
10138 11:06:42.380536
10139 11:06:43.081583 00100000 ################################################################
10140 11:06:43.082076
10141 11:06:43.791085 00180000 ################################################################
10142 11:06:43.791552
10143 11:06:44.493124 00200000 ################################################################
10144 11:06:44.493649
10145 11:06:45.191321 00280000 ################################################################
10146 11:06:45.191787
10147 11:06:45.887549 00300000 ################################################################
10148 11:06:45.888022
10149 11:06:46.588884 00380000 ################################################################
10150 11:06:46.589570
10151 11:06:47.287637 00400000 ################################################################
10152 11:06:47.288107
10153 11:06:47.984868 00480000 ################################################################
10154 11:06:47.985448
10155 11:06:48.687034 00500000 ################################################################
10156 11:06:48.687640
10157 11:06:49.387875 00580000 ################################################################
10158 11:06:49.388348
10159 11:06:50.088834 00600000 ################################################################
10160 11:06:50.089384
10161 11:06:50.787331 00680000 ################################################################
10162 11:06:50.787808
10163 11:06:51.483242 00700000 ################################################################
10164 11:06:51.483701
10165 11:06:52.176144 00780000 ################################################################
10166 11:06:52.176628
10167 11:06:52.877295 00800000 ################################################################
10168 11:06:52.877762
10169 11:06:53.582864 00880000 ################################################################
10170 11:06:53.583393
10171 11:06:54.208472 00900000 ################################################################
10172 11:06:54.208721
10173 11:06:54.913238 00980000 ################################################################
10174 11:06:54.913786
10175 11:06:55.642068 00a00000 ################################################################
10176 11:06:55.642525
10177 11:06:56.350861 00a80000 ################################################################
10178 11:06:56.351330
10179 11:06:57.050614 00b00000 ################################################################
10180 11:06:57.051072
10181 11:06:57.747070 00b80000 ################################################################
10182 11:06:57.747546
10183 11:06:58.440723 00c00000 ################################################################
10184 11:06:58.441210
10185 11:06:59.103694 00c80000 ################################################################
10186 11:06:59.104153
10187 11:06:59.789389 00d00000 ################################################################
10188 11:06:59.789856
10189 11:07:00.480374 00d80000 ################################################################
10190 11:07:00.480971
10191 11:07:01.164893 00e00000 ################################################################
10192 11:07:01.165433
10193 11:07:01.862751 00e80000 ################################################################
10194 11:07:01.863207
10195 11:07:02.561186 00f00000 ################################################################
10196 11:07:02.561704
10197 11:07:03.233332 00f80000 ################################################################
10198 11:07:03.233816
10199 11:07:03.925860 01000000 ################################################################
10200 11:07:03.926467
10201 11:07:04.631301 01080000 ################################################################
10202 11:07:04.631796
10203 11:07:05.291361 01100000 ################################################################
10204 11:07:05.291485
10205 11:07:05.928190 01180000 ################################################################
10206 11:07:05.928685
10207 11:07:06.618683 01200000 ################################################################
10208 11:07:06.619157
10209 11:07:07.281012 01280000 ################################################################
10210 11:07:07.281527
10211 11:07:07.966062 01300000 ################################################################
10212 11:07:07.966517
10213 11:07:08.665511 01380000 ################################################################
10214 11:07:08.665971
10215 11:07:09.347661 01400000 ################################################################
10216 11:07:09.348130
10217 11:07:09.965455 01480000 ################################################################
10218 11:07:09.965913
10219 11:07:10.659678 01500000 ################################################################
10220 11:07:10.660180
10221 11:07:11.360001 01580000 ################################################################
10222 11:07:11.360512
10223 11:07:12.048896 01600000 ################################################################
10224 11:07:12.049396
10225 11:07:12.735773 01680000 ################################################################
10226 11:07:12.736242
10227 11:07:13.417165 01700000 ################################################################
10228 11:07:13.417690
10229 11:07:14.085022 01780000 ################################################################
10230 11:07:14.085172
10231 11:07:14.750794 01800000 ################################################################
10232 11:07:14.751253
10233 11:07:15.423598 01880000 ################################################################
10234 11:07:15.424054
10235 11:07:16.044085 01900000 ################################################################
10236 11:07:16.044235
10237 11:07:16.621527 01980000 ################################################################
10238 11:07:16.621649
10239 11:07:17.217213 01a00000 ################################################################
10240 11:07:17.217809
10241 11:07:17.900916 01a80000 ################################################################
10242 11:07:17.901416
10243 11:07:18.500608 01b00000 ################################################################
10244 11:07:18.500723
10245 11:07:19.064047 01b80000 ################################################################
10246 11:07:19.064169
10247 11:07:19.645738 01c00000 ################################################################
10248 11:07:19.645898
10249 11:07:20.223571 01c80000 ################################################################
10250 11:07:20.223697
10251 11:07:20.813795 01d00000 ################################################################
10252 11:07:20.813916
10253 11:07:21.374110 01d80000 ################################################################
10254 11:07:21.374333
10255 11:07:21.809758 01e00000 ################################################### done.
10256 11:07:21.809886
10257 11:07:21.813422 The bootfile was 31874890 bytes long.
10258 11:07:21.813502
10259 11:07:21.816525 Sending tftp read request... done.
10260 11:07:21.816634
10261 11:07:21.816694 Waiting for the transfer...
10262 11:07:21.816748
10263 11:07:21.819485 00000000 # done.
10264 11:07:21.819564
10265 11:07:21.825875 Command line loaded dynamically from TFTP file: 14786840/tftp-deploy-vj02v5np/kernel/cmdline
10266 11:07:21.825954
10267 11:07:21.849568 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786840/extract-nfsrootfs-171i6dsw,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10268 11:07:21.849678
10269 11:07:21.852224 Loading FIT.
10270 11:07:21.852300
10271 11:07:21.852358 Image ramdisk-1 has 18709345 bytes.
10272 11:07:21.856319
10273 11:07:21.856393 Image fdt-1 has 47258 bytes.
10274 11:07:21.856516
10275 11:07:21.859180 Image kernel-1 has 13116259 bytes.
10276 11:07:21.859255
10277 11:07:21.868839 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10278 11:07:21.868952
10279 11:07:21.885265 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10280 11:07:21.885431
10281 11:07:21.891694 Choosing best match conf-1 for compat google,spherion-rev2.
10282 11:07:21.895385
10283 11:07:21.900440 Connected to device vid:did:rid of 1ae0:0028:00
10284 11:07:21.907496
10285 11:07:21.910677 tpm_get_response: command 0x17b, return code 0x0
10286 11:07:21.910755
10287 11:07:21.913613 ec_init: CrosEC protocol v3 supported (256, 248)
10288 11:07:21.917884
10289 11:07:21.921556 tpm_cleanup: add release locality here.
10290 11:07:21.921632
10291 11:07:21.921690 Shutting down all USB controllers.
10292 11:07:21.924832
10293 11:07:21.924906 Removing current net device
10294 11:07:21.924965
10295 11:07:21.931755 Exiting depthcharge with code 4 at timestamp: 76645801
10296 11:07:21.931831
10297 11:07:21.934983 LZMA decompressing kernel-1 to 0x821a6718
10298 11:07:21.935058
10299 11:07:21.937943 LZMA decompressing kernel-1 to 0x40000000
10300 11:07:23.553634
10301 11:07:23.553765 jumping to kernel
10302 11:07:23.554581 end: 2.2.4 bootloader-commands (duration 00:00:49) [common]
10303 11:07:23.554697 start: 2.2.5 auto-login-action (timeout 00:03:31) [common]
10304 11:07:23.554791 Setting prompt string to ['Linux version [0-9]']
10305 11:07:23.554880 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10306 11:07:23.554970 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10307 11:07:23.634623
10308 11:07:23.637611 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10309 11:07:23.641314 start: 2.2.5.1 login-action (timeout 00:03:31) [common]
10310 11:07:23.641433 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10311 11:07:23.641503 Setting prompt string to []
10312 11:07:23.641574 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10313 11:07:23.641639 Using line separator: #'\n'#
10314 11:07:23.641691 No login prompt set.
10315 11:07:23.641747 Parsing kernel messages
10316 11:07:23.641797 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10317 11:07:23.641891 [login-action] Waiting for messages, (timeout 00:03:31)
10318 11:07:23.641953 Waiting using forced prompt support (timeout 00:01:45)
10319 11:07:23.661077 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10320 11:07:23.664090 [ 0.000000] random: crng init done
10321 11:07:23.667462 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10322 11:07:23.670738 [ 0.000000] efi: UEFI not found.
10323 11:07:23.682500 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10324 11:07:23.687397 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10325 11:07:23.697223 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10326 11:07:23.707298 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10327 11:07:23.713968 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10328 11:07:23.717411 [ 0.000000] printk: bootconsole [mtk8250] enabled
10329 11:07:23.725429 [ 0.000000] NUMA: No NUMA configuration found
10330 11:07:23.732509 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10331 11:07:23.738591 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10332 11:07:23.738667 [ 0.000000] Zone ranges:
10333 11:07:23.745106 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10334 11:07:23.748704 [ 0.000000] DMA32 empty
10335 11:07:23.755145 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10336 11:07:23.758572 [ 0.000000] Movable zone start for each node
10337 11:07:23.761763 [ 0.000000] Early memory node ranges
10338 11:07:23.769108 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10339 11:07:23.775219 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10340 11:07:23.781894 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10341 11:07:23.788672 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10342 11:07:23.795730 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10343 11:07:23.801524 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10344 11:07:23.859114 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10345 11:07:23.865707 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10346 11:07:23.871853 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10347 11:07:23.875299 [ 0.000000] psci: probing for conduit method from DT.
10348 11:07:23.882129 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10349 11:07:23.885108 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10350 11:07:23.892442 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10351 11:07:23.895170 [ 0.000000] psci: SMC Calling Convention v1.2
10352 11:07:23.902662 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10353 11:07:23.905419 [ 0.000000] Detected VIPT I-cache on CPU0
10354 11:07:23.911751 [ 0.000000] CPU features: detected: GIC system register CPU interface
10355 11:07:23.918273 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10356 11:07:23.925018 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10357 11:07:23.931488 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10358 11:07:23.938646 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10359 11:07:23.947974 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10360 11:07:23.951460 [ 0.000000] alternatives: applying boot alternatives
10361 11:07:23.958047 [ 0.000000] Fallback order for Node 0: 0
10362 11:07:23.964507 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10363 11:07:23.967875 [ 0.000000] Policy zone: Normal
10364 11:07:23.990733 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786840/extract-nfsrootfs-171i6dsw,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10365 11:07:24.000716 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10366 11:07:24.011571 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10367 11:07:24.022211 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10368 11:07:24.028053 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10369 11:07:24.031361 <6>[ 0.000000] software IO TLB: area num 8.
10370 11:07:24.088469 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10371 11:07:24.237871 <6>[ 0.000000] Memory: 7945788K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406980K reserved, 32768K cma-reserved)
10372 11:07:24.244373 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10373 11:07:24.250947 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10374 11:07:24.254621 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10375 11:07:24.260521 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10376 11:07:24.267190 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10377 11:07:24.270588 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10378 11:07:24.280287 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10379 11:07:24.286961 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10380 11:07:24.293555 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10381 11:07:24.300331 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10382 11:07:24.303445 <6>[ 0.000000] GICv3: 608 SPIs implemented
10383 11:07:24.307230 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10384 11:07:24.313896 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10385 11:07:24.317124 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10386 11:07:24.323642 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10387 11:07:24.336772 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10388 11:07:24.350019 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10389 11:07:24.356791 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10390 11:07:24.364747 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10391 11:07:24.377342 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10392 11:07:24.383937 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10393 11:07:24.390906 <6>[ 0.009229] Console: colour dummy device 80x25
10394 11:07:24.400684 <6>[ 0.013962] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10395 11:07:24.404473 <6>[ 0.024403] pid_max: default: 32768 minimum: 301
10396 11:07:24.411058 <6>[ 0.029276] LSM: Security Framework initializing
10397 11:07:24.417422 <6>[ 0.034243] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10398 11:07:24.427717 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 11:07:24.433764 <6>[ 0.051483] cblist_init_generic: Setting adjustable number of callback queues.
10400 11:07:24.440286 <6>[ 0.058925] cblist_init_generic: Setting shift to 3 and lim to 1.
10401 11:07:24.450547 <6>[ 0.065265] cblist_init_generic: Setting adjustable number of callback queues.
10402 11:07:24.456994 <6>[ 0.072692] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 11:07:24.460058 <6>[ 0.079093] rcu: Hierarchical SRCU implementation.
10404 11:07:24.467026 <6>[ 0.084109] rcu: Max phase no-delay instances is 1000.
10405 11:07:24.473777 <6>[ 0.091139] EFI services will not be available.
10406 11:07:24.477094 <6>[ 0.096101] smp: Bringing up secondary CPUs ...
10407 11:07:24.484943 <6>[ 0.101153] Detected VIPT I-cache on CPU1
10408 11:07:24.491476 <6>[ 0.101225] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10409 11:07:24.498256 <6>[ 0.101255] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10410 11:07:24.501414 <6>[ 0.101601] Detected VIPT I-cache on CPU2
10411 11:07:24.511284 <6>[ 0.101654] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10412 11:07:24.518607 <6>[ 0.101671] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10413 11:07:24.521076 <6>[ 0.101936] Detected VIPT I-cache on CPU3
10414 11:07:24.527894 <6>[ 0.101983] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10415 11:07:24.534547 <6>[ 0.101999] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10416 11:07:24.541259 <6>[ 0.102309] CPU features: detected: Spectre-v4
10417 11:07:24.544502 <6>[ 0.102315] CPU features: detected: Spectre-BHB
10418 11:07:24.547764 <6>[ 0.102321] Detected PIPT I-cache on CPU4
10419 11:07:24.554050 <6>[ 0.102381] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10420 11:07:24.564136 <6>[ 0.102398] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10421 11:07:24.567250 <6>[ 0.102700] Detected PIPT I-cache on CPU5
10422 11:07:24.573861 <6>[ 0.102765] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10423 11:07:24.580827 <6>[ 0.102781] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10424 11:07:24.584000 <6>[ 0.103064] Detected PIPT I-cache on CPU6
10425 11:07:24.594041 <6>[ 0.103130] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10426 11:07:24.600404 <6>[ 0.103145] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10427 11:07:24.603570 <6>[ 0.103443] Detected PIPT I-cache on CPU7
10428 11:07:24.610482 <6>[ 0.103511] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10429 11:07:24.616898 <6>[ 0.103526] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10430 11:07:24.620487 <6>[ 0.103575] smp: Brought up 1 node, 8 CPUs
10431 11:07:24.627077 <6>[ 0.245037] SMP: Total of 8 processors activated.
10432 11:07:24.633503 <6>[ 0.249958] CPU features: detected: 32-bit EL0 Support
10433 11:07:24.640426 <6>[ 0.255355] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10434 11:07:24.646652 <6>[ 0.264155] CPU features: detected: Common not Private translations
10435 11:07:24.653346 <6>[ 0.270671] CPU features: detected: CRC32 instructions
10436 11:07:24.660316 <6>[ 0.276023] CPU features: detected: RCpc load-acquire (LDAPR)
10437 11:07:24.663395 <6>[ 0.281983] CPU features: detected: LSE atomic instructions
10438 11:07:24.669762 <6>[ 0.287796] CPU features: detected: Privileged Access Never
10439 11:07:24.676873 <6>[ 0.293575] CPU features: detected: RAS Extension Support
10440 11:07:24.683400 <6>[ 0.299184] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10441 11:07:24.686704 <6>[ 0.306442] CPU: All CPU(s) started at EL2
10442 11:07:24.693127 <6>[ 0.310758] alternatives: applying system-wide alternatives
10443 11:07:24.703063 <6>[ 0.321637] devtmpfs: initialized
10444 11:07:24.715032 <6>[ 0.330419] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10445 11:07:24.725156 <6>[ 0.340383] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10446 11:07:24.732364 <6>[ 0.348633] pinctrl core: initialized pinctrl subsystem
10447 11:07:24.735083 <6>[ 0.355303] DMI not present or invalid.
10448 11:07:24.741868 <6>[ 0.359724] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10449 11:07:24.751612 <6>[ 0.366620] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10450 11:07:24.758242 <6>[ 0.374208] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10451 11:07:24.768047 <6>[ 0.382440] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10452 11:07:24.771067 <6>[ 0.390687] audit: initializing netlink subsys (disabled)
10453 11:07:24.781110 <5>[ 0.396388] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10454 11:07:24.787885 <6>[ 0.397107] thermal_sys: Registered thermal governor 'step_wise'
10455 11:07:24.794224 <6>[ 0.404354] thermal_sys: Registered thermal governor 'power_allocator'
10456 11:07:24.797856 <6>[ 0.410609] cpuidle: using governor menu
10457 11:07:24.803908 <6>[ 0.421569] NET: Registered PF_QIPCRTR protocol family
10458 11:07:24.811014 <6>[ 0.427090] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10459 11:07:24.817239 <6>[ 0.434194] ASID allocator initialised with 32768 entries
10460 11:07:24.820657 <6>[ 0.440769] Serial: AMBA PL011 UART driver
10461 11:07:24.831281 <4>[ 0.450166] Trying to register duplicate clock ID: 134
10462 11:07:24.889990 <6>[ 0.511347] KASLR enabled
10463 11:07:24.903690 <6>[ 0.518949] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10464 11:07:24.910401 <6>[ 0.525961] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10465 11:07:24.917127 <6>[ 0.532451] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10466 11:07:24.923162 <6>[ 0.539457] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10467 11:07:24.929870 <6>[ 0.545941] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10468 11:07:24.936734 <6>[ 0.552945] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10469 11:07:24.943006 <6>[ 0.559432] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10470 11:07:24.949540 <6>[ 0.566436] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10471 11:07:24.952979 <6>[ 0.573889] ACPI: Interpreter disabled.
10472 11:07:24.962427 <6>[ 0.580324] iommu: Default domain type: Translated
10473 11:07:24.968798 <6>[ 0.585475] iommu: DMA domain TLB invalidation policy: strict mode
10474 11:07:24.971462 <5>[ 0.592125] SCSI subsystem initialized
10475 11:07:24.978227 <6>[ 0.596372] usbcore: registered new interface driver usbfs
10476 11:07:24.984914 <6>[ 0.602102] usbcore: registered new interface driver hub
10477 11:07:24.988275 <6>[ 0.607655] usbcore: registered new device driver usb
10478 11:07:24.995592 <6>[ 0.613777] pps_core: LinuxPPS API ver. 1 registered
10479 11:07:25.005074 <6>[ 0.618971] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10480 11:07:25.008229 <6>[ 0.628311] PTP clock support registered
10481 11:07:25.011717 <6>[ 0.632553] EDAC MC: Ver: 3.0.0
10482 11:07:25.019814 <6>[ 0.637752] FPGA manager framework
10483 11:07:25.026096 <6>[ 0.641429] Advanced Linux Sound Architecture Driver Initialized.
10484 11:07:25.029163 <6>[ 0.648222] vgaarb: loaded
10485 11:07:25.035488 <6>[ 0.651389] clocksource: Switched to clocksource arch_sys_counter
10486 11:07:25.038699 <5>[ 0.657839] VFS: Disk quotas dquot_6.6.0
10487 11:07:25.045841 <6>[ 0.662023] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10488 11:07:25.048918 <6>[ 0.669213] pnp: PnP ACPI: disabled
10489 11:07:25.057039 <6>[ 0.675867] NET: Registered PF_INET protocol family
10490 11:07:25.067115 <6>[ 0.681459] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10491 11:07:25.078738 <6>[ 0.693780] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10492 11:07:25.088215 <6>[ 0.702594] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10493 11:07:25.094774 <6>[ 0.710566] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10494 11:07:25.104878 <6>[ 0.719263] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10495 11:07:25.111422 <6>[ 0.729019] TCP: Hash tables configured (established 65536 bind 65536)
10496 11:07:25.117887 <6>[ 0.735893] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10497 11:07:25.127688 <6>[ 0.743091] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 11:07:25.134301 <6>[ 0.750794] NET: Registered PF_UNIX/PF_LOCAL protocol family
10499 11:07:25.140788 <6>[ 0.756941] RPC: Registered named UNIX socket transport module.
10500 11:07:25.144063 <6>[ 0.763096] RPC: Registered udp transport module.
10501 11:07:25.150628 <6>[ 0.768030] RPC: Registered tcp transport module.
10502 11:07:25.157221 <6>[ 0.772962] RPC: Registered tcp NFSv4.1 backchannel transport module.
10503 11:07:25.160671 <6>[ 0.779627] PCI: CLS 0 bytes, default 64
10504 11:07:25.164113 <6>[ 0.783970] Unpacking initramfs...
10505 11:07:25.187918 <6>[ 0.803495] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10506 11:07:25.198252 <6>[ 0.812158] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10507 11:07:25.201724 <6>[ 0.821017] kvm [1]: IPA Size Limit: 40 bits
10508 11:07:25.207963 <6>[ 0.825549] kvm [1]: GICv3: no GICV resource entry
10509 11:07:25.211387 <6>[ 0.830569] kvm [1]: disabling GICv2 emulation
10510 11:07:25.218017 <6>[ 0.835256] kvm [1]: GIC system register CPU interface enabled
10511 11:07:25.221399 <6>[ 0.841418] kvm [1]: vgic interrupt IRQ18
10512 11:07:25.227780 <6>[ 0.845773] kvm [1]: VHE mode initialized successfully
10513 11:07:25.234686 <5>[ 0.852190] Initialise system trusted keyrings
10514 11:07:25.241098 <6>[ 0.856991] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10515 11:07:25.248520 <6>[ 0.866962] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10516 11:07:25.254973 <5>[ 0.873341] NFS: Registering the id_resolver key type
10517 11:07:25.257951 <5>[ 0.878656] Key type id_resolver registered
10518 11:07:25.264666 <5>[ 0.883070] Key type id_legacy registered
10519 11:07:25.271587 <6>[ 0.887349] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10520 11:07:25.277745 <6>[ 0.894273] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10521 11:07:25.284460 <6>[ 0.902012] 9p: Installing v9fs 9p2000 file system support
10522 11:07:25.320933 <5>[ 0.939327] Key type asymmetric registered
10523 11:07:25.324148 <5>[ 0.943658] Asymmetric key parser 'x509' registered
10524 11:07:25.333703 <6>[ 0.948803] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10525 11:07:25.337055 <6>[ 0.956423] io scheduler mq-deadline registered
10526 11:07:25.340384 <6>[ 0.961199] io scheduler kyber registered
10527 11:07:25.359748 <6>[ 0.978362] EINJ: ACPI disabled.
10528 11:07:25.392863 <4>[ 1.004385] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 11:07:25.402315 <4>[ 1.015022] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 11:07:25.417521 <6>[ 1.036421] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10531 11:07:25.425690 <6>[ 1.044466] printk: console [ttyS0] disabled
10532 11:07:25.454123 <6>[ 1.069132] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10533 11:07:25.460198 <6>[ 1.078607] printk: console [ttyS0] enabled
10534 11:07:25.463831 <6>[ 1.078607] printk: console [ttyS0] enabled
10535 11:07:25.470195 <6>[ 1.087500] printk: bootconsole [mtk8250] disabled
10536 11:07:25.473814 <6>[ 1.087500] printk: bootconsole [mtk8250] disabled
10537 11:07:25.480339 <6>[ 1.098836] SuperH (H)SCI(F) driver initialized
10538 11:07:25.483497 <6>[ 1.104123] msm_serial: driver initialized
10539 11:07:25.497840 <6>[ 1.113129] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10540 11:07:25.507671 <6>[ 1.121677] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10541 11:07:25.514441 <6>[ 1.130219] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10542 11:07:25.524501 <6>[ 1.138846] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10543 11:07:25.534201 <6>[ 1.147552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10544 11:07:25.540523 <6>[ 1.156266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10545 11:07:25.550751 <6>[ 1.164812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10546 11:07:25.557220 <6>[ 1.173615] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10547 11:07:25.566936 <6>[ 1.182157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10548 11:07:25.579168 <6>[ 1.198031] loop: module loaded
10549 11:07:25.585910 <6>[ 1.204068] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10550 11:07:25.609041 <4>[ 1.227919] mtk-pmic-keys: Failed to locate of_node [id: -1]
10551 11:07:25.616425 <6>[ 1.235161] megasas: 07.719.03.00-rc1
10552 11:07:25.626653 <6>[ 1.244997] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10553 11:07:25.632846 <6>[ 1.246848] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10554 11:07:25.648451 <6>[ 1.266904] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10555 11:07:25.705244 <6>[ 1.317204] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10556 11:07:25.967364 <6>[ 1.585898] Freeing initrd memory: 18268K
10557 11:07:25.978423 <6>[ 1.597392] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10558 11:07:25.989771 <6>[ 1.608482] tun: Universal TUN/TAP device driver, 1.6
10559 11:07:25.993314 <6>[ 1.614533] thunder_xcv, ver 1.0
10560 11:07:25.996435 <6>[ 1.618045] thunder_bgx, ver 1.0
10561 11:07:25.999780 <6>[ 1.621543] nicpf, ver 1.0
10562 11:07:26.010030 <6>[ 1.625572] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10563 11:07:26.013531 <6>[ 1.633048] hns3: Copyright (c) 2017 Huawei Corporation.
10564 11:07:26.020476 <6>[ 1.638639] hclge is initializing
10565 11:07:26.023478 <6>[ 1.642222] e1000: Intel(R) PRO/1000 Network Driver
10566 11:07:26.030331 <6>[ 1.647351] e1000: Copyright (c) 1999-2006 Intel Corporation.
10567 11:07:26.033508 <6>[ 1.653365] e1000e: Intel(R) PRO/1000 Network Driver
10568 11:07:26.040245 <6>[ 1.658580] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10569 11:07:26.047542 <6>[ 1.664766] igb: Intel(R) Gigabit Ethernet Network Driver
10570 11:07:26.053170 <6>[ 1.670416] igb: Copyright (c) 2007-2014 Intel Corporation.
10571 11:07:26.059876 <6>[ 1.676252] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10572 11:07:26.066449 <6>[ 1.682770] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10573 11:07:26.069989 <6>[ 1.689240] sky2: driver version 1.30
10574 11:07:26.076281 <6>[ 1.694174] usbcore: registered new device driver r8152-cfgselector
10575 11:07:26.083116 <6>[ 1.700708] usbcore: registered new interface driver r8152
10576 11:07:26.089826 <6>[ 1.706526] VFIO - User Level meta-driver version: 0.3
10577 11:07:26.096248 <6>[ 1.714796] usbcore: registered new interface driver usb-storage
10578 11:07:26.103257 <6>[ 1.721246] usbcore: registered new device driver onboard-usb-hub
10579 11:07:26.111701 <6>[ 1.730412] mt6397-rtc mt6359-rtc: registered as rtc0
10580 11:07:26.121606 <6>[ 1.735880] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:07:25 UTC (1720609645)
10581 11:07:26.125084 <6>[ 1.745445] i2c_dev: i2c /dev entries driver
10582 11:07:26.138689 <4>[ 1.757564] cpu cpu0: supply cpu not found, using dummy regulator
10583 11:07:26.145336 <4>[ 1.764002] cpu cpu1: supply cpu not found, using dummy regulator
10584 11:07:26.152479 <4>[ 1.770407] cpu cpu2: supply cpu not found, using dummy regulator
10585 11:07:26.158620 <4>[ 1.776808] cpu cpu3: supply cpu not found, using dummy regulator
10586 11:07:26.165672 <4>[ 1.783208] cpu cpu4: supply cpu not found, using dummy regulator
10587 11:07:26.172310 <4>[ 1.789602] cpu cpu5: supply cpu not found, using dummy regulator
10588 11:07:26.178809 <4>[ 1.796016] cpu cpu6: supply cpu not found, using dummy regulator
10589 11:07:26.185393 <4>[ 1.802416] cpu cpu7: supply cpu not found, using dummy regulator
10590 11:07:26.204721 <6>[ 1.823049] cpu cpu0: EM: created perf domain
10591 11:07:26.207486 <6>[ 1.827975] cpu cpu4: EM: created perf domain
10592 11:07:26.215060 <6>[ 1.833583] sdhci: Secure Digital Host Controller Interface driver
10593 11:07:26.221345 <6>[ 1.840015] sdhci: Copyright(c) Pierre Ossman
10594 11:07:26.228006 <6>[ 1.844974] Synopsys Designware Multimedia Card Interface Driver
10595 11:07:26.234662 <6>[ 1.851618] sdhci-pltfm: SDHCI platform and OF driver helper
10596 11:07:26.238132 <6>[ 1.851692] mmc0: CQHCI version 5.10
10597 11:07:26.244404 <6>[ 1.861859] ledtrig-cpu: registered to indicate activity on CPUs
10598 11:07:26.251456 <6>[ 1.868885] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10599 11:07:26.257791 <6>[ 1.875947] usbcore: registered new interface driver usbhid
10600 11:07:26.261238 <6>[ 1.881770] usbhid: USB HID core driver
10601 11:07:26.267675 <6>[ 1.885975] spi_master spi0: will run message pump with realtime priority
10602 11:07:26.318840 <6>[ 1.931133] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10603 11:07:26.339856 <6>[ 1.946802] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10604 11:07:26.341871 <3>[ 1.955519] mtk-msdc 11f60000.mmc: phase error: [map:0]
10605 11:07:26.349068 <6>[ 1.961997] cros-ec-spi spi0.0: Chrome EC device registered
10606 11:07:26.352768 <3>[ 1.965670] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10607 11:07:26.358573 <3>[ 1.977410] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10608 11:07:26.365771 <3>[ 1.983770] mmc0: error -5 whilst initialising MMC card
10609 11:07:26.375362 <6>[ 1.985773] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10610 11:07:26.382293 <6>[ 1.999666] NET: Registered PF_PACKET protocol family
10611 11:07:26.385132 <6>[ 2.005080] 9pnet: Installing 9P2000 support
10612 11:07:26.392109 <5>[ 2.009669] Key type dns_resolver registered
10613 11:07:26.395374 <6>[ 2.014865] registered taskstats version 1
10614 11:07:26.401520 <5>[ 2.019263] Loading compiled-in X.509 certificates
10615 11:07:26.430374 <4>[ 2.042489] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 11:07:26.440107 <4>[ 2.053282] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 11:07:26.456707 <6>[ 2.075434] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10618 11:07:26.463463 <6>[ 2.082374] xhci-mtk 11200000.usb: xHCI Host Controller
10619 11:07:26.470393 <6>[ 2.087915] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10620 11:07:26.480244 <6>[ 2.095787] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10621 11:07:26.487676 <6>[ 2.105227] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10622 11:07:26.493792 <6>[ 2.111329] xhci-mtk 11200000.usb: xHCI Host Controller
10623 11:07:26.500385 <6>[ 2.116822] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10624 11:07:26.506970 <6>[ 2.124577] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10625 11:07:26.513811 <6>[ 2.132454] hub 1-0:1.0: USB hub found
10626 11:07:26.517155 <6>[ 2.136411] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15814
10627 11:07:26.523834 <6>[ 2.136480] hub 1-0:1.0: 1 port detected
10628 11:07:26.527155 <6>[ 2.146756] mmc0: Command Queue Engine enabled
10629 11:07:26.537059 <6>[ 2.146789] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10630 11:07:26.543665 <6>[ 2.151468] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10631 11:07:26.546759 <6>[ 2.160185] hub 2-0:1.0: USB hub found
10632 11:07:26.550319 <6>[ 2.166808] mmcblk0: mmc0:0001 DA4128 116 GiB
10633 11:07:26.556703 <6>[ 2.170422] hub 2-0:1.0: 1 port detected
10634 11:07:26.560444 <6>[ 2.179022] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10635 11:07:26.567050 <6>[ 2.182706] mtk-msdc 11f70000.mmc: Got CD GPIO
10636 11:07:26.570007 <6>[ 2.186743] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10637 11:07:26.578477 <6>[ 2.196671] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10638 11:07:26.587980 <6>[ 2.201597] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10639 11:07:26.594214 <6>[ 2.202769] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10640 11:07:26.601331 <6>[ 2.210263] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10641 11:07:26.611024 <6>[ 2.210269] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10642 11:07:26.617765 <6>[ 2.210274] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10643 11:07:26.627633 <6>[ 2.241801] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10644 11:07:26.634635 <6>[ 2.250141] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10645 11:07:26.643928 <6>[ 2.258483] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10646 11:07:26.650480 <6>[ 2.266822] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10647 11:07:26.660888 <6>[ 2.275162] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10648 11:07:26.667531 <6>[ 2.283512] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10649 11:07:26.677096 <6>[ 2.291854] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10650 11:07:26.683466 <6>[ 2.300192] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10651 11:07:26.693411 <6>[ 2.308532] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10652 11:07:26.700041 <6>[ 2.316870] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10653 11:07:26.710185 <6>[ 2.325210] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10654 11:07:26.716779 <6>[ 2.334112] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10655 11:07:26.723574 <6>[ 2.341345] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10656 11:07:26.730231 <6>[ 2.348130] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10657 11:07:26.736568 <6>[ 2.354900] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10658 11:07:26.743247 <6>[ 2.361824] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10659 11:07:26.753091 <6>[ 2.368691] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10660 11:07:26.763183 <6>[ 2.377828] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10661 11:07:26.772821 <6>[ 2.386948] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10662 11:07:26.782857 <6>[ 2.396243] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10663 11:07:26.792692 <6>[ 2.405713] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10664 11:07:26.799472 <6>[ 2.415182] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10665 11:07:26.809132 <6>[ 2.424303] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10666 11:07:26.819253 <6>[ 2.433770] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10667 11:07:26.829148 <6>[ 2.442894] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10668 11:07:26.838709 <6>[ 2.452192] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10669 11:07:26.848926 <6>[ 2.462355] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10670 11:07:26.858402 <6>[ 2.473977] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10671 11:07:26.866109 <6>[ 2.484997] Trying to probe devices needed for running init ...
10672 11:07:26.876516 <3>[ 2.492168] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10673 11:07:26.952056 <6>[ 2.567662] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10674 11:07:27.106998 <6>[ 2.725878] hub 1-1:1.0: USB hub found
10675 11:07:27.110452 <6>[ 2.730408] hub 1-1:1.0: 4 ports detected
10676 11:07:27.122438 <6>[ 2.740757] hub 1-1:1.0: USB hub found
10677 11:07:27.124950 <6>[ 2.745140] hub 1-1:1.0: 4 ports detected
10678 11:07:27.232361 <6>[ 2.848096] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10679 11:07:27.260140 <6>[ 2.878731] hub 2-1:1.0: USB hub found
10680 11:07:27.263257 <6>[ 2.883191] hub 2-1:1.0: 3 ports detected
10681 11:07:27.275872 <6>[ 2.894801] hub 2-1:1.0: USB hub found
10682 11:07:27.279521 <6>[ 2.899275] hub 2-1:1.0: 3 ports detected
10683 11:07:27.447927 <6>[ 3.063706] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 11:07:27.580227 <6>[ 3.199226] hub 1-1.4:1.0: USB hub found
10685 11:07:27.583443 <6>[ 3.203835] hub 1-1.4:1.0: 2 ports detected
10686 11:07:27.598348 <6>[ 3.217260] hub 1-1.4:1.0: USB hub found
10687 11:07:27.601911 <6>[ 3.221872] hub 1-1.4:1.0: 2 ports detected
10688 11:07:27.660477 <6>[ 3.275926] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10689 11:07:27.769306 <6>[ 3.384349] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 11:07:27.805005 <4>[ 3.420491] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10691 11:07:27.814985 <4>[ 3.429584] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10692 11:07:27.854267 <6>[ 3.473183] r8152 2-1.3:1.0 eth0: v1.12.13
10693 11:07:27.900593 <6>[ 3.515710] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10694 11:07:28.099969 <6>[ 3.715503] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10695 11:07:29.459224 <6>[ 5.078581] r8152 2-1.3:1.0 eth0: carrier on
10696 11:07:32.364166 <5>[ 5.107476] Sending DHCP requests .., OK
10697 11:07:32.370696 <6>[ 7.987838] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10698 11:07:32.373935 <6>[ 7.996132] IP-Config: Complete:
10699 11:07:32.387297 <6>[ 7.999626] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10700 11:07:32.393936 <6>[ 8.010345] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10701 11:07:32.400637 <6>[ 8.018964] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10702 11:07:32.407217 <6>[ 8.018973] nameserver0=192.168.201.1
10703 11:07:32.409968 <6>[ 8.031145] clk: Disabling unused clocks
10704 11:07:32.413637 <6>[ 8.036659] ALSA device list:
10705 11:07:32.420489 <6>[ 8.039914] No soundcards found.
10706 11:07:32.427935 <6>[ 8.047593] Freeing unused kernel memory: 8512K
10707 11:07:32.431368 <6>[ 8.052548] Run /init as init process
10708 11:07:32.442469 Loading, please wait...
10709 11:07:32.476966 Starting systemd-udevd version 252.22-1~deb12u1
10710 11:07:32.753417 <6>[ 8.369509] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10711 11:07:32.759838 <6>[ 8.371621] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10712 11:07:32.767262 <6>[ 8.372183] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10713 11:07:32.776292 <6>[ 8.372239] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10714 11:07:32.786468 <6>[ 8.373578] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10715 11:07:32.793021 <6>[ 8.402211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10716 11:07:32.802995 <6>[ 8.418105] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10717 11:07:32.806254 <6>[ 8.418978] remoteproc remoteproc0: scp is available
10718 11:07:32.815984 <4>[ 8.426159] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10719 11:07:32.819329 <6>[ 8.431340] remoteproc remoteproc0: powering up scp
10720 11:07:32.829338 <3>[ 8.441212] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 11:07:32.835779 <4>[ 8.443254] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10722 11:07:32.845795 <6>[ 8.445480] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10723 11:07:32.852220 <6>[ 8.445561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10724 11:07:32.862389 <6>[ 8.445568] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10725 11:07:32.869007 <3>[ 8.453805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 11:07:32.875323 <4>[ 8.455957] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10727 11:07:32.885565 <6>[ 8.456682] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10728 11:07:32.891799 <6>[ 8.456700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10729 11:07:32.902180 <6>[ 8.456703] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10730 11:07:32.908681 <6>[ 8.456708] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10731 11:07:32.915137 <6>[ 8.456828] mc: Linux media interface: v0.10
10732 11:07:32.918273 <6>[ 8.461210] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10733 11:07:32.928135 <3>[ 8.469828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 11:07:32.934837 <6>[ 8.496989] videodev: Linux video capture interface: v2.00
10735 11:07:32.941524 <6>[ 8.499508] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10736 11:07:32.944933 <6>[ 8.499527] pci_bus 0000:00: root bus resource [bus 00-ff]
10737 11:07:32.951496 <6>[ 8.499541] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10738 11:07:32.961940 <6>[ 8.499547] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10739 11:07:32.968247 <6>[ 8.499654] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10740 11:07:32.978281 <6>[ 8.499730] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10741 11:07:32.981380 <6>[ 8.500119] pci 0000:00:00.0: supports D1 D2
10742 11:07:32.989238 <6>[ 8.500140] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 11:07:32.998629 <6>[ 8.506429] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10744 11:07:33.004965 <3>[ 8.507038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 11:07:33.011656 <3>[ 8.507082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:07:33.021613 <3>[ 8.507093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 11:07:33.027696 <3>[ 8.507099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 11:07:33.038075 <3>[ 8.507103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 11:07:33.044850 <3>[ 8.507593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 11:07:33.054666 <3>[ 8.507668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 11:07:33.061032 <3>[ 8.507671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 11:07:33.067747 <3>[ 8.507674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 11:07:33.078260 <3>[ 8.507724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 11:07:33.085148 <3>[ 8.507729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 11:07:33.094782 <3>[ 8.507733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 11:07:33.101527 <3>[ 8.507738] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 11:07:33.111682 <3>[ 8.507742] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 11:07:33.117890 <3>[ 8.509369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 11:07:33.124624 <6>[ 8.521405] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10760 11:07:33.130974 <6>[ 8.529616] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10761 11:07:33.137959 <6>[ 8.534155] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10762 11:07:33.147649 <4>[ 8.556646] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10763 11:07:33.154483 <4>[ 8.556646] Fallback method does not support PEC.
10764 11:07:33.161006 <6>[ 8.558107] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10765 11:07:33.170952 <6>[ 8.571756] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10766 11:07:33.177580 <6>[ 8.577874] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10767 11:07:33.187183 <6>[ 8.580231] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10768 11:07:33.197119 <6>[ 8.580543] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10769 11:07:33.203703 <6>[ 8.606043] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10770 11:07:33.210190 <6>[ 8.606089] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10771 11:07:33.216905 <6>[ 8.606097] remoteproc remoteproc0: remote processor scp is now up
10772 11:07:33.223827 <6>[ 8.613682] pci 0000:01:00.0: supports D1 D2
10773 11:07:33.226658 <6>[ 8.621937] Bluetooth: Core ver 2.22
10774 11:07:33.233932 <6>[ 8.629791] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10775 11:07:33.239937 <6>[ 8.630879] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10776 11:07:33.249762 <6>[ 8.632983] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10777 11:07:33.256422 <6>[ 8.637446] NET: Registered PF_BLUETOOTH protocol family
10778 11:07:33.262963 <3>[ 8.646476] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10779 11:07:33.269671 <6>[ 8.653540] Bluetooth: HCI device and connection manager initialized
10780 11:07:33.276738 <6>[ 8.653560] Bluetooth: HCI socket layer initialized
10781 11:07:33.282873 <6>[ 8.663594] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10782 11:07:33.289745 <6>[ 8.669717] Bluetooth: L2CAP socket layer initialized
10783 11:07:33.296203 <6>[ 8.670785] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10784 11:07:33.306256 <6>[ 8.672154] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10785 11:07:33.312540 <6>[ 8.672448] usbcore: registered new interface driver uvcvideo
10786 11:07:33.322847 <6>[ 8.677820] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10787 11:07:33.325810 <6>[ 8.685879] Bluetooth: SCO socket layer initialized
10788 11:07:33.335832 <6>[ 8.693951] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10789 11:07:33.342204 <3>[ 8.718187] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 11:07:33.352626 <6>[ 8.726270] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10791 11:07:33.358689 <6>[ 8.727296] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10792 11:07:33.362034 <6>[ 8.749119] usbcore: registered new interface driver btusb
10793 11:07:33.375240 <4>[ 8.750003] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10794 11:07:33.381908 <3>[ 8.750012] Bluetooth: hci0: Failed to load firmware file (-2)
10795 11:07:33.385415 <3>[ 8.750016] Bluetooth: hci0: Failed to set up firmware (-2)
10796 11:07:33.394931 <4>[ 8.750019] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10797 11:07:33.404962 <6>[ 8.756348] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10798 11:07:33.411918 <6>[ 9.029197] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10799 11:07:33.417987 <6>[ 9.037278] pci 0000:00:00.0: PCI bridge to [bus 01]
10800 11:07:33.424615 <6>[ 9.042622] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10801 11:07:33.431392 <6>[ 9.050795] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10802 11:07:33.438732 <6>[ 9.057587] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10803 11:07:33.444705 <6>[ 9.064279] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10804 11:07:33.467252 <5>[ 9.083637] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10805 11:07:33.486350 <5>[ 9.102683] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10806 11:07:33.493025 <5>[ 9.110161] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10807 11:07:33.502982 <4>[ 9.118689] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10808 11:07:33.509775 <6>[ 9.127594] cfg80211: failed to load regulatory.db
10809 11:07:33.566519 <6>[ 9.182680] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10810 11:07:33.572930 <6>[ 9.190237] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10811 11:07:33.597954 <6>[ 9.217239] mt7921e 0000:01:00.0: ASIC revision: 79610010
10812 11:07:33.701534 <6>[ 9.317699] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10813 11:07:33.704748 <6>[ 9.317699]
10814 11:07:33.721020 Begin: Loading essential drivers ... done.
10815 11:07:33.724409 Begin: Running /scripts/init-premount ... done.
10816 11:07:33.731049 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10817 11:07:33.741220 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10818 11:07:33.744134 Device /sys/class/net/eth0 found
10819 11:07:33.744223 done.
10820 11:07:33.750360 Begin: Waiting up to 180 secs for any network device to become available ... done.
10821 11:07:33.812366 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10822 11:07:33.819272 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10823 11:07:33.825606 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10824 11:07:33.831757 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10825 11:07:33.838613 host : mt8192-asurada-spherion-r0-cbg-2
10826 11:07:33.845036 domain : lava-rack
10827 11:07:33.848193 rootserver: 192.168.201.1 rootpath:
10828 11:07:33.848296 filename :
10829 11:07:33.851855 done.
10830 11:07:33.855158 Begin: Running /scripts/nfs-bottom ... done.
10831 11:07:33.875886 Begin: Running /scripts/init-bottom ... done.
10832 11:07:33.973887 <6>[ 9.590341] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10833 11:07:35.235415 <6>[ 10.855087] NET: Registered PF_INET6 protocol family
10834 11:07:35.243126 <6>[ 10.862624] Segment Routing with IPv6
10835 11:07:35.246298 <6>[ 10.866583] In-situ OAM (IOAM) with IPv6
10836 11:07:35.411965 <30>[ 11.005190] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10837 11:07:35.418546 <30>[ 11.038323] systemd[1]: Detected architecture arm64.
10838 11:07:35.427779
10839 11:07:35.430353 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10840 11:07:35.430483
10841 11:07:35.453566 <30>[ 11.073150] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10842 11:07:36.538722 <30>[ 12.155574] systemd[1]: Queued start job for default target graphical.target.
10843 11:07:36.575437 <30>[ 12.192178] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10844 11:07:36.582035 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10845 11:07:36.600811 <30>[ 12.217252] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10846 11:07:36.610806 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10847 11:07:36.628992 <30>[ 12.245432] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10848 11:07:36.638513 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10849 11:07:36.657165 <30>[ 12.273896] systemd[1]: Created slice user.slice - User and Session Slice.
10850 11:07:36.663601 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10851 11:07:36.686811 <30>[ 12.300048] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10852 11:07:36.696568 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10853 11:07:36.715494 <30>[ 12.327927] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10854 11:07:36.721625 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10855 11:07:36.749622 <30>[ 12.356325] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10856 11:07:36.759492 <30>[ 12.376264] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10857 11:07:36.766213 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10858 11:07:36.783448 <30>[ 12.399687] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10859 11:07:36.789473 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10860 11:07:36.807031 <30>[ 12.423763] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10861 11:07:36.817050 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10862 11:07:36.831622 <30>[ 12.451764] systemd[1]: Reached target paths.target - Path Units.
10863 11:07:36.841604 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10864 11:07:36.859259 <30>[ 12.476121] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10865 11:07:36.866083 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10866 11:07:36.879941 <30>[ 12.499681] systemd[1]: Reached target slices.target - Slice Units.
10867 11:07:36.889604 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10868 11:07:36.904031 <30>[ 12.524169] systemd[1]: Reached target swap.target - Swaps.
10869 11:07:36.911130 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10870 11:07:36.931259 <30>[ 12.547781] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10871 11:07:36.941676 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10872 11:07:36.959518 <30>[ 12.576241] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10873 11:07:36.969728 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10874 11:07:36.990976 <30>[ 12.607619] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10875 11:07:37.001030 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10876 11:07:37.020733 <30>[ 12.637339] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10877 11:07:37.031187 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10878 11:07:37.047795 <30>[ 12.664380] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10879 11:07:37.054720 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10880 11:07:37.072514 <30>[ 12.689263] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10881 11:07:37.082430 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10882 11:07:37.102407 <30>[ 12.718734] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10883 11:07:37.112004 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10884 11:07:37.127760 <30>[ 12.744183] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10885 11:07:37.137420 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10886 11:07:37.191054 <30>[ 12.807907] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10887 11:07:37.197749 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10888 11:07:37.219681 <30>[ 12.836340] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10889 11:07:37.225976 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10890 11:07:37.251626 <30>[ 12.868494] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10891 11:07:37.258517 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10892 11:07:37.285812 <30>[ 12.896024] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10893 11:07:37.331990 <30>[ 12.948472] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10894 11:07:37.341623 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10895 11:07:37.364817 <30>[ 12.981678] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10896 11:07:37.371188 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10897 11:07:37.444105 <30>[ 13.060610] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10898 11:07:37.450569 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10899 11:07:37.474747 <30>[ 13.091422] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10900 11:07:37.487789 Starting [0;1;39mmodprobe@drm.service<6>[ 13.103578] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10901 11:07:37.491411 [0m - Load Kernel Module drm...
10902 11:07:37.512998 <30>[ 13.129489] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10903 11:07:37.522675 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10904 11:07:37.544928 <30>[ 13.161376] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10905 11:07:37.551158 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10906 11:07:37.576635 <30>[ 13.193174] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10907 11:07:37.584108 Starting [0;1;39mmodpr<6>[ 13.203584] fuse: init (API version 7.37)
10908 11:07:37.586296 obe@loop.ser…e[0m - Load Kernel Module loop...
10909 11:07:37.616619 <30>[ 13.233057] systemd[1]: Starting systemd-journald.service - Journal Service...
10910 11:07:37.622929 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10911 11:07:37.656470 <30>[ 13.273271] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10912 11:07:37.662957 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10913 11:07:37.714604 <30>[ 13.328263] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10914 11:07:37.721848 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10915 11:07:37.745661 <30>[ 13.362558] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10916 11:07:37.755281 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10917 11:07:37.781680 <3>[ 13.398363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 11:07:37.812082 <30>[ 13.428320] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10919 11:07:37.822717 <3>[ 13.430353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 11:07:37.829091 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10921 11:07:37.852750 <30>[ 13.468330] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10922 11:07:37.862288 [[0;32m OK [0m] Mounted [0;<3>[ 13.478830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 11:07:37.869250 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10924 11:07:37.887767 <30>[ 13.504217] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10925 11:07:37.894657 <3>[ 13.509033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 11:07:37.904919 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10927 11:07:37.923784 <30>[ 13.540237] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10928 11:07:37.933282 <3>[ 13.543310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:07:37.939999 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10930 11:07:37.960327 <30>[ 13.576784] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10931 11:07:37.969884 <3>[ 13.578531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 11:07:37.976548 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10933 11:07:37.997153 <30>[ 13.613294] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10934 11:07:38.003919 <3>[ 13.617053] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:07:38.013132 <30>[ 13.621360] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10936 11:07:38.020169 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10937 11:07:38.033153 <3>[ 13.649682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 11:07:38.043232 <30>[ 13.659902] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10939 11:07:38.049790 <30>[ 13.668495] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10940 11:07:38.064002 [[0;32m OK [0m] Finished [0<3>[ 13.679233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 11:07:38.067622 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10942 11:07:38.086109 <30>[ 13.705355] systemd[1]: modprobe@drm.service: Deactivated successfully.
10943 11:07:38.095928 <3>[ 13.711885] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 11:07:38.102272 <30>[ 13.713309] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10945 11:07:38.112746 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10946 11:07:38.126876 <3>[ 13.743471] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 11:07:38.137081 <30>[ 13.754206] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10948 11:07:38.148217 <30>[ 13.762693] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10949 11:07:38.157624 [[0;32m OK [<3>[ 13.772768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 11:07:38.164585 0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10951 11:07:38.182484 <30>[ 13.802092] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10952 11:07:38.192919 <3>[ 13.808602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 11:07:38.199238 <30>[ 13.810126] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10954 11:07:38.209602 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10955 11:07:38.227182 <3>[ 13.843937] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 11:07:38.233506 <30>[ 13.845847] systemd[1]: modprobe@loop.service: Deactivated successfully.
10957 11:07:38.244136 <30>[ 13.861017] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10958 11:07:38.251471 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10959 11:07:38.270571 <3>[ 13.887446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 11:07:38.282342 <30>[ 13.897997] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10961 11:07:38.295759 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…servic<3>[ 13.911781] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:07:38.312334 e[0m - Load Ker<4>[ 13.920670] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10963 11:07:38.312514 nel Modules.
10964 11:07:38.322823 <3>[ 13.935939] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:07:38.328801 <3>[ 13.937657] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10966 11:07:38.344218 <30>[ 13.956756] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10967 11:07:38.350688 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10968 11:07:38.373580 <30>[ 13.989574] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10969 11:07:38.383821 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10970 11:07:38.400739 <30>[ 14.017341] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10971 11:07:38.410418 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10972 11:07:38.428923 <30>[ 14.045261] systemd[1]: Reached target network-pre.target - Preparation for Network.
10973 11:07:38.435067 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10974 11:07:38.495309 <30>[ 14.112220] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10975 11:07:38.501994 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10976 11:07:38.527584 <30>[ 14.144491] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10977 11:07:38.534404 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10978 11:07:38.561962 <30>[ 14.171824] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10979 11:07:38.578009 <30>[ 14.185439] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10980 11:07:38.589667 <30>[ 14.206561] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10981 11:07:38.596547 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10982 11:07:38.621659 <30>[ 14.235000] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10983 11:07:38.664237 <30>[ 14.280547] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10984 11:07:38.670434 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10985 11:07:38.699407 <30>[ 14.316219] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10986 11:07:38.705937 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10987 11:07:38.735355 <30>[ 14.352072] systemd[1]: Started systemd-journald.service - Journal Service.
10988 11:07:38.741980 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10989 11:07:38.768466 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10990 11:07:38.791713 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10991 11:07:38.812407 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10992 11:07:38.832162 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10993 11:07:38.852293 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10994 11:07:38.923710 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10995 11:07:38.948111 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10996 11:07:39.012413 <46>[ 14.629607] systemd-journald[311]: Received client request to flush runtime journal.
10997 11:07:39.060789 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10998 11:07:39.079553 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10999 11:07:39.099039 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11000 11:07:39.799933 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11001 11:07:40.426413 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11002 11:07:40.484332 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11003 11:07:40.548152 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11004 11:07:40.605394 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11005 11:07:40.647955 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11006 11:07:40.966406 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11007 11:07:40.984009 <6>[ 16.604135] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11008 11:07:41.026313 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11009 11:07:41.055146 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11010 11:07:41.138368 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11011 11:07:41.191261 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11012 11:07:41.212445 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11013 11:07:41.240598 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11014 11:07:41.255762 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11015 11:07:41.285176 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11016 11:07:41.382554 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11017 11:07:41.457986 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11018 11:07:41.479251 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11019 11:07:41.524098 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11020 11:07:41.633676 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11021 11:07:41.655626 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11022 11:07:41.679324 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11023 11:07:41.702907 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11024 11:07:41.726787 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11025 11:07:41.746346 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11026 11:07:41.763888 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11027 11:07:41.787110 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11028 11:07:41.819926 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11029 11:07:41.839190 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11030 11:07:41.857333 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11031 11:07:41.875463 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11032 11:07:41.895532 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11033 11:07:41.941901 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11034 11:07:41.974341 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11035 11:07:42.052592 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11036 11:07:42.076625 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11037 11:07:42.276642 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11038 11:07:42.332185 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11039 11:07:42.350849 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11040 11:07:42.367150 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11041 11:07:42.383940 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11042 11:07:42.425646 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11043 11:07:42.449033 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11044 11:07:42.468960 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11045 11:07:42.487666 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11046 11:07:42.540533 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11047 11:07:42.584145 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11048 11:07:42.682595
11049 11:07:42.686509 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11050 11:07:42.686592
11051 11:07:42.688888 debian-bookworm-arm64 login: root (automatic login)
11052 11:07:42.688991
11053 11:07:43.002839 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11054 11:07:43.003006
11055 11:07:43.009643 The programs included with the Debian GNU/Linux system are free software;
11056 11:07:43.015895 the exact distribution terms for each program are described in the
11057 11:07:43.019252 individual files in /usr/share/doc/*/copyright.
11058 11:07:43.019385
11059 11:07:43.025983 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11060 11:07:43.028861 permitted by applicable law.
11061 11:07:44.126390 Matched prompt #10: / #
11063 11:07:44.126763 Setting prompt string to ['/ #']
11064 11:07:44.126894 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11066 11:07:44.127177 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11067 11:07:44.127299 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
11068 11:07:44.127398 Setting prompt string to ['/ #']
11069 11:07:44.127493 Forcing a shell prompt, looking for ['/ #']
11070 11:07:44.127580 Sending line: ''
11072 11:07:44.177992 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11073 11:07:44.178101 Waiting using forced prompt support (timeout 00:02:30)
11074 11:07:44.182588 / #
11075 11:07:44.182898 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11076 11:07:44.183036 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
11077 11:07:44.183148 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786840/extract-nfsrootfs-171i6dsw'"
11079 11:07:44.288444 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786840/extract-nfsrootfs-171i6dsw'
11080 11:07:44.288714 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11082 11:07:44.394098 / # export NFS_SERVER_IP='192.168.201.1'
11083 11:07:44.394531 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11084 11:07:44.394651 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11085 11:07:44.394734 end: 2 depthcharge-action (duration 00:01:50) [common]
11086 11:07:44.394835 start: 3 lava-test-retry (timeout 00:07:31) [common]
11087 11:07:44.394919 start: 3.1 lava-test-shell (timeout 00:07:31) [common]
11088 11:07:44.395003 Using namespace: common
11089 11:07:44.395087 Sending line: '#'
11091 11:07:44.495541 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11092 11:07:44.500452 / # #
11093 11:07:44.500723 Using /lava-14786840
11094 11:07:44.500789 Sending line: 'export SHELL=/bin/bash'
11096 11:07:44.606244 / # export SHELL=/bin/bash
11097 11:07:44.606503 Sending line: '. /lava-14786840/environment'
11099 11:07:44.711596 / # . /lava-14786840/environment
11100 11:07:44.717665 Sending line: '/lava-14786840/bin/lava-test-runner /lava-14786840/0'
11102 11:07:44.818252 Test shell timeout: 10s (minimum of the action and connection timeout)
11103 11:07:44.823324 / # /lava-14786840/bin/lava-test-runner /lava-14786840/0
11104 11:07:45.095239 + export TESTRUN_ID=0_timesync-off
11105 11:07:45.097854 + TESTRUN_ID=0_timesync-off
11106 11:07:45.101905 + cd /lava-14786840/0/tests/0_timesync-off
11107 11:07:45.104500 ++ cat uuid
11108 11:07:45.109633 + UUID=14786840_1.6.2.3.1
11109 11:07:45.109722 + set +x
11110 11:07:45.116194 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14786840_1.6.2.3.1>
11111 11:07:45.116503 Received signal: <STARTRUN> 0_timesync-off 14786840_1.6.2.3.1
11112 11:07:45.116601 Starting test lava.0_timesync-off (14786840_1.6.2.3.1)
11113 11:07:45.116711 Skipping test definition patterns.
11114 11:07:45.119001 + systemctl stop systemd-timesyncd
11115 11:07:45.179635 + set +x
11116 11:07:45.182928 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14786840_1.6.2.3.1>
11117 11:07:45.183182 Received signal: <ENDRUN> 0_timesync-off 14786840_1.6.2.3.1
11118 11:07:45.183262 Ending use of test pattern.
11119 11:07:45.183318 Ending test lava.0_timesync-off (14786840_1.6.2.3.1), duration 0.07
11121 11:07:45.255899 + export TESTRUN_ID=1_kselftest-alsa
11122 11:07:45.259924 + TESTRUN_ID=1_kselftest-alsa
11123 11:07:45.265924 + cd /lava-14786840/0/tests/1_kselftest-alsa
11124 11:07:45.266019 ++ cat uuid
11125 11:07:45.271035 + UUID=14786840_1.6.2.3.5
11126 11:07:45.271143 + set +x
11127 11:07:45.277672 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14786840_1.6.2.3.5>
11128 11:07:45.277927 Received signal: <STARTRUN> 1_kselftest-alsa 14786840_1.6.2.3.5
11129 11:07:45.277993 Starting test lava.1_kselftest-alsa (14786840_1.6.2.3.5)
11130 11:07:45.278066 Skipping test definition patterns.
11131 11:07:45.280923 + cd ./automated/linux/kselftest/
11132 11:07:45.307488 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11133 11:07:45.351407 INFO: install_deps skipped
11134 11:07:45.851604 --2024-07-10 11:07:45-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11135 11:07:45.877127 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11136 11:07:46.011720 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11137 11:07:46.145032 HTTP request sent, awaiting response... 200 OK
11138 11:07:46.148272 Length: 1919896 (1.8M) [application/octet-stream]
11139 11:07:46.151620 Saving to: 'kselftest_armhf.tar.gz'
11140 11:07:46.151724
11141 11:07:46.151809
11142 11:07:46.412551 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11143 11:07:46.678776 kselftest_armhf.tar 2%[ ] 50.15K 188KB/s
11144 11:07:47.077836 kselftest_armhf.tar 11%[=> ] 217.50K 408KB/s
11145 11:07:47.216638 kselftest_armhf.tar 45%[========> ] 860.89K 924KB/s
11146 11:07:47.222717 kselftest_armhf.tar 100%[===================>] 1.83M 1.71MB/s in 1.1s
11147 11:07:47.222845
11148 11:07:47.391914 2024-07-10 11:07:47 (1.71 MB/s) - 'kselftest_armhf.tar.gz' saved [1919896/1919896]
11149 11:07:47.392071
11150 11:07:54.384991 skiplist:
11151 11:07:54.388313 ========================================
11152 11:07:54.391720 ========================================
11153 11:07:54.444314 alsa:mixer-test
11154 11:07:54.465615 ============== Tests to run ===============
11155 11:07:54.468955 alsa:mixer-test
11156 11:07:54.472429 ===========End Tests to run ===============
11157 11:07:54.475935 shardfile-alsa pass
11158 11:07:54.585230 <12>[ 30.206807] kselftest: Running tests in alsa
11159 11:07:54.594688 TAP version 13
11160 11:07:54.609849 1..1
11161 11:07:54.626965 # selftests: alsa: mixer-test
11162 11:07:55.129798 # TAP version 13
11163 11:07:55.129910 # 1..0
11164 11:07:55.136104 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11165 11:07:55.139076 ok 1 selftests: alsa: mixer-test
11166 11:07:56.602931 alsa_mixer-test pass
11167 11:07:56.681839 + ../../utils/send-to-lava.sh ./output/result.txt
11168 11:07:56.759189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11169 11:07:56.759527 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11171 11:07:56.813345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11172 11:07:56.813530 + set +x
11173 11:07:56.813839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11175 11:07:56.819941 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14786840_1.6.2.3.5>
11176 11:07:56.820185 Received signal: <ENDRUN> 1_kselftest-alsa 14786840_1.6.2.3.5
11177 11:07:56.820252 Ending use of test pattern.
11178 11:07:56.820307 Ending test lava.1_kselftest-alsa (14786840_1.6.2.3.5), duration 11.54
11180 11:07:56.823563 <LAVA_TEST_RUNNER EXIT>
11181 11:07:56.823805 ok: lava_test_shell seems to have completed
11182 11:07:56.823894 shardfile-alsa: pass
alsa_mixer-test: pass
11183 11:07:56.823976 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11184 11:07:56.824054 end: 3 lava-test-retry (duration 00:00:12) [common]
11185 11:07:56.824133 start: 4 finalize (timeout 00:07:19) [common]
11186 11:07:56.824211 start: 4.1 power-off (timeout 00:00:30) [common]
11187 11:07:56.824336 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11188 11:07:58.895244 >> Command sent successfully.
11189 11:07:58.898419 Returned 0 in 2 seconds
11190 11:07:58.898586 end: 4.1 power-off (duration 00:00:02) [common]
11192 11:07:58.898870 start: 4.2 read-feedback (timeout 00:07:17) [common]
11193 11:07:58.899036 Listened to connection for namespace 'common' for up to 1s
11194 11:07:59.900079 Finalising connection for namespace 'common'
11195 11:07:59.900233 Disconnecting from shell: Finalise
11196 11:07:59.900299 / #
11197 11:08:00.000536 end: 4.2 read-feedback (duration 00:00:01) [common]
11198 11:08:00.000685 end: 4 finalize (duration 00:00:03) [common]
11199 11:08:00.000786 Cleaning after the job
11200 11:08:00.000880 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/ramdisk
11201 11:08:00.003119 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/kernel
11202 11:08:00.013717 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/dtb
11203 11:08:00.013888 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/nfsrootfs
11204 11:08:00.077105 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786840/tftp-deploy-vj02v5np/modules
11205 11:08:00.082771 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786840
11206 11:08:00.628500 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786840
11207 11:08:00.628682 Job finished correctly